1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend
;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend
;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode
;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p
: 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p
: 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p
: 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p
: 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi
= NO_ABI
;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls
= FALSE
;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared
= TRUE
;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros
;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float
;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float
;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32
= -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32
= -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float
= 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float
= 0;
292 static struct mips_set_options mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
299 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask
;
306 unsigned long mips_cprmask
[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa
= ISA_UNKNOWN
;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16
;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips
;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d
;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx
;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips
;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp
;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2 \
355 || mips_opts.micromips)
357 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
359 /* True if -mdspr2 was passed or implied by arguments passed on the
360 command line (e.g., by -march). */
361 static int file_ase_dspr2
;
363 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
364 || mips_opts.isa == ISA_MIPS64R2 \
365 || mips_opts.micromips)
367 /* True if -mmt was passed or implied by arguments passed on the
368 command line (e.g., by -march). */
369 static int file_ase_mt
;
371 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
372 || mips_opts.isa == ISA_MIPS64R2)
374 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
375 || mips_opts.isa == ISA_MIPS64R2 \
376 || mips_opts.micromips)
378 /* The argument of the -march= flag. The architecture we are assembling. */
379 static int file_mips_arch
= CPU_UNKNOWN
;
380 static const char *mips_arch_string
;
382 /* The argument of the -mtune= flag. The architecture for which we
384 static int mips_tune
= CPU_UNKNOWN
;
385 static const char *mips_tune_string
;
387 /* True when generating 32-bit code for a 64-bit processor. */
388 static int mips_32bitmode
= 0;
390 /* True if the given ABI requires 32-bit registers. */
391 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
393 /* Likewise 64-bit registers. */
394 #define ABI_NEEDS_64BIT_REGS(ABI) \
396 || (ABI) == N64_ABI \
399 /* Return true if ISA supports 64 bit wide gp registers. */
400 #define ISA_HAS_64BIT_REGS(ISA) \
401 ((ISA) == ISA_MIPS3 \
402 || (ISA) == ISA_MIPS4 \
403 || (ISA) == ISA_MIPS5 \
404 || (ISA) == ISA_MIPS64 \
405 || (ISA) == ISA_MIPS64R2)
407 /* Return true if ISA supports 64 bit wide float registers. */
408 #define ISA_HAS_64BIT_FPRS(ISA) \
409 ((ISA) == ISA_MIPS3 \
410 || (ISA) == ISA_MIPS4 \
411 || (ISA) == ISA_MIPS5 \
412 || (ISA) == ISA_MIPS32R2 \
413 || (ISA) == ISA_MIPS64 \
414 || (ISA) == ISA_MIPS64R2)
416 /* Return true if ISA supports 64-bit right rotate (dror et al.)
418 #define ISA_HAS_DROR(ISA) \
419 ((ISA) == ISA_MIPS64R2 \
420 || (mips_opts.micromips \
421 && ISA_HAS_64BIT_REGS (ISA)) \
424 /* Return true if ISA supports 32-bit right rotate (ror et al.)
426 #define ISA_HAS_ROR(ISA) \
427 ((ISA) == ISA_MIPS32R2 \
428 || (ISA) == ISA_MIPS64R2 \
429 || mips_opts.ase_smartmips \
430 || mips_opts.micromips \
433 /* Return true if ISA supports single-precision floats in odd registers. */
434 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
435 ((ISA) == ISA_MIPS32 \
436 || (ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64 \
438 || (ISA) == ISA_MIPS64R2)
440 /* Return true if ISA supports move to/from high part of a 64-bit
441 floating-point register. */
442 #define ISA_HAS_MXHC1(ISA) \
443 ((ISA) == ISA_MIPS32R2 \
444 || (ISA) == ISA_MIPS64R2)
446 #define HAVE_32BIT_GPRS \
447 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
449 #define HAVE_32BIT_FPRS \
450 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
452 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
453 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
455 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
457 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
459 /* True if relocations are stored in-place. */
460 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
462 /* The ABI-derived address size. */
463 #define HAVE_64BIT_ADDRESSES \
464 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
465 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
467 /* The size of symbolic constants (i.e., expressions of the form
468 "SYMBOL" or "SYMBOL + OFFSET"). */
469 #define HAVE_32BIT_SYMBOLS \
470 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
471 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
473 /* Addresses are loaded in different ways, depending on the address size
474 in use. The n32 ABI Documentation also mandates the use of additions
475 with overflow checking, but existing implementations don't follow it. */
476 #define ADDRESS_ADD_INSN \
477 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
479 #define ADDRESS_ADDI_INSN \
480 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
482 #define ADDRESS_LOAD_INSN \
483 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
485 #define ADDRESS_STORE_INSN \
486 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
488 /* Return true if the given CPU supports the MIPS16 ASE. */
489 #define CPU_HAS_MIPS16(cpu) \
490 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
491 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
493 /* Return true if the given CPU supports the microMIPS ASE. */
494 #define CPU_HAS_MICROMIPS(cpu) 0
496 /* True if CPU has a dror instruction. */
497 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
499 /* True if CPU has a ror instruction. */
500 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
502 /* True if CPU is in the Octeon family */
503 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
505 /* True if CPU has seq/sne and seqi/snei instructions. */
506 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
508 /* True if mflo and mfhi can be immediately followed by instructions
509 which write to the HI and LO registers.
511 According to MIPS specifications, MIPS ISAs I, II, and III need
512 (at least) two instructions between the reads of HI/LO and
513 instructions which write them, and later ISAs do not. Contradicting
514 the MIPS specifications, some MIPS IV processor user manuals (e.g.
515 the UM for the NEC Vr5000) document needing the instructions between
516 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
517 MIPS64 and later ISAs to have the interlocks, plus any specific
518 earlier-ISA CPUs for which CPU documentation declares that the
519 instructions are really interlocked. */
520 #define hilo_interlocks \
521 (mips_opts.isa == ISA_MIPS32 \
522 || mips_opts.isa == ISA_MIPS32R2 \
523 || mips_opts.isa == ISA_MIPS64 \
524 || mips_opts.isa == ISA_MIPS64R2 \
525 || mips_opts.arch == CPU_R4010 \
526 || mips_opts.arch == CPU_R10000 \
527 || mips_opts.arch == CPU_R12000 \
528 || mips_opts.arch == CPU_R14000 \
529 || mips_opts.arch == CPU_R16000 \
530 || mips_opts.arch == CPU_RM7000 \
531 || mips_opts.arch == CPU_VR5500 \
532 || mips_opts.micromips \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from the GPRs after they are loaded from memory, and thus does not
537 require nops to be inserted. This applies to instructions marked
538 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
539 level I and microMIPS mode instructions are always interlocked. */
540 #define gpr_interlocks \
541 (mips_opts.isa != ISA_MIPS1 \
542 || mips_opts.arch == CPU_R3900 \
543 || mips_opts.micromips \
546 /* Whether the processor uses hardware interlocks to avoid delays
547 required by coprocessor instructions, and thus does not require
548 nops to be inserted. This applies to instructions marked
549 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
550 between instructions marked INSN_WRITE_COND_CODE and ones marked
551 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
552 levels I, II, and III and microMIPS mode instructions are always
554 /* Itbl support may require additional care here. */
555 #define cop_interlocks \
556 ((mips_opts.isa != ISA_MIPS1 \
557 && mips_opts.isa != ISA_MIPS2 \
558 && mips_opts.isa != ISA_MIPS3) \
559 || mips_opts.arch == CPU_R4300 \
560 || mips_opts.micromips \
563 /* Whether the processor uses hardware interlocks to protect reads
564 from coprocessor registers after they are loaded from memory, and
565 thus does not require nops to be inserted. This applies to
566 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
567 requires at MIPS ISA level I and microMIPS mode instructions are
568 always interlocked. */
569 #define cop_mem_interlocks \
570 (mips_opts.isa != ISA_MIPS1 \
571 || mips_opts.micromips \
574 /* Is this a mfhi or mflo instruction? */
575 #define MF_HILO_INSN(PINFO) \
576 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
578 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
579 has been selected. This implies, in particular, that addresses of text
580 labels have their LSB set. */
581 #define HAVE_CODE_COMPRESSION \
582 ((mips_opts.mips16 | mips_opts.micromips) != 0)
584 /* MIPS PIC level. */
586 enum mips_pic_level mips_pic
;
588 /* 1 if we should generate 32 bit offsets from the $gp register in
589 SVR4_PIC mode. Currently has no meaning in other modes. */
590 static int mips_big_got
= 0;
592 /* 1 if trap instructions should used for overflow rather than break
594 static int mips_trap
= 0;
596 /* 1 if double width floating point constants should not be constructed
597 by assembling two single width halves into two single width floating
598 point registers which just happen to alias the double width destination
599 register. On some architectures this aliasing can be disabled by a bit
600 in the status register, and the setting of this bit cannot be determined
601 automatically at assemble time. */
602 static int mips_disable_float_construction
;
604 /* Non-zero if any .set noreorder directives were used. */
606 static int mips_any_noreorder
;
608 /* Non-zero if nops should be inserted when the register referenced in
609 an mfhi/mflo instruction is read in the next two instructions. */
610 static int mips_7000_hilo_fix
;
612 /* The size of objects in the small data section. */
613 static unsigned int g_switch_value
= 8;
614 /* Whether the -G option was used. */
615 static int g_switch_seen
= 0;
620 /* If we can determine in advance that GP optimization won't be
621 possible, we can skip the relaxation stuff that tries to produce
622 GP-relative references. This makes delay slot optimization work
625 This function can only provide a guess, but it seems to work for
626 gcc output. It needs to guess right for gcc, otherwise gcc
627 will put what it thinks is a GP-relative instruction in a branch
630 I don't know if a fix is needed for the SVR4_PIC mode. I've only
631 fixed it for the non-PIC mode. KR 95/04/07 */
632 static int nopic_need_relax (symbolS
*, int);
634 /* handle of the OPCODE hash table */
635 static struct hash_control
*op_hash
= NULL
;
637 /* The opcode hash table we use for the mips16. */
638 static struct hash_control
*mips16_op_hash
= NULL
;
640 /* The opcode hash table we use for the microMIPS ASE. */
641 static struct hash_control
*micromips_op_hash
= NULL
;
643 /* This array holds the chars that always start a comment. If the
644 pre-processor is disabled, these aren't very useful */
645 const char comment_chars
[] = "#";
647 /* This array holds the chars that only start a comment at the beginning of
648 a line. If the line seems to have the form '# 123 filename'
649 .line and .file directives will appear in the pre-processed output */
650 /* Note that input_file.c hand checks for '#' at the beginning of the
651 first line of the input file. This is because the compiler outputs
652 #NO_APP at the beginning of its output. */
653 /* Also note that C style comments are always supported. */
654 const char line_comment_chars
[] = "#";
656 /* This array holds machine specific line separator characters. */
657 const char line_separator_chars
[] = ";";
659 /* Chars that can be used to separate mant from exp in floating point nums */
660 const char EXP_CHARS
[] = "eE";
662 /* Chars that mean this number is a floating point constant */
665 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
667 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
668 changed in read.c . Ideally it shouldn't have to know about it at all,
669 but nothing is ideal around here.
672 static char *insn_error
;
674 static int auto_align
= 1;
676 /* When outputting SVR4 PIC code, the assembler needs to know the
677 offset in the stack frame from which to restore the $gp register.
678 This is set by the .cprestore pseudo-op, and saved in this
680 static offsetT mips_cprestore_offset
= -1;
682 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
683 more optimizations, it can use a register value instead of a memory-saved
684 offset and even an other register than $gp as global pointer. */
685 static offsetT mips_cpreturn_offset
= -1;
686 static int mips_cpreturn_register
= -1;
687 static int mips_gp_register
= GP
;
688 static int mips_gprel_offset
= 0;
690 /* Whether mips_cprestore_offset has been set in the current function
691 (or whether it has already been warned about, if not). */
692 static int mips_cprestore_valid
= 0;
694 /* This is the register which holds the stack frame, as set by the
695 .frame pseudo-op. This is needed to implement .cprestore. */
696 static int mips_frame_reg
= SP
;
698 /* Whether mips_frame_reg has been set in the current function
699 (or whether it has already been warned about, if not). */
700 static int mips_frame_reg_valid
= 0;
702 /* To output NOP instructions correctly, we need to keep information
703 about the previous two instructions. */
705 /* Whether we are optimizing. The default value of 2 means to remove
706 unneeded NOPs and swap branch instructions when possible. A value
707 of 1 means to not swap branches. A value of 0 means to always
709 static int mips_optimize
= 2;
711 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
712 equivalent to seeing no -g option at all. */
713 static int mips_debug
= 0;
715 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
716 #define MAX_VR4130_NOPS 4
718 /* The maximum number of NOPs needed to fill delay slots. */
719 #define MAX_DELAY_NOPS 2
721 /* The maximum number of NOPs needed for any purpose. */
724 /* A list of previous instructions, with index 0 being the most recent.
725 We need to look back MAX_NOPS instructions when filling delay slots
726 or working around processor errata. We need to look back one
727 instruction further if we're thinking about using history[0] to
728 fill a branch delay slot. */
729 static struct mips_cl_insn history
[1 + MAX_NOPS
];
731 /* Nop instructions used by emit_nop. */
732 static struct mips_cl_insn nop_insn
;
733 static struct mips_cl_insn mips16_nop_insn
;
734 static struct mips_cl_insn micromips_nop16_insn
;
735 static struct mips_cl_insn micromips_nop32_insn
;
737 /* The appropriate nop for the current mode. */
738 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
739 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
741 /* The size of NOP_INSN in bytes. */
742 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
744 /* If this is set, it points to a frag holding nop instructions which
745 were inserted before the start of a noreorder section. If those
746 nops turn out to be unnecessary, the size of the frag can be
748 static fragS
*prev_nop_frag
;
750 /* The number of nop instructions we created in prev_nop_frag. */
751 static int prev_nop_frag_holds
;
753 /* The number of nop instructions that we know we need in
755 static int prev_nop_frag_required
;
757 /* The number of instructions we've seen since prev_nop_frag. */
758 static int prev_nop_frag_since
;
760 /* For ECOFF and ELF, relocations against symbols are done in two
761 parts, with a HI relocation and a LO relocation. Each relocation
762 has only 16 bits of space to store an addend. This means that in
763 order for the linker to handle carries correctly, it must be able
764 to locate both the HI and the LO relocation. This means that the
765 relocations must appear in order in the relocation table.
767 In order to implement this, we keep track of each unmatched HI
768 relocation. We then sort them so that they immediately precede the
769 corresponding LO relocation. */
774 struct mips_hi_fixup
*next
;
777 /* The section this fixup is in. */
781 /* The list of unmatched HI relocs. */
783 static struct mips_hi_fixup
*mips_hi_fixup_list
;
785 /* The frag containing the last explicit relocation operator.
786 Null if explicit relocations have not been used. */
788 static fragS
*prev_reloc_op_frag
;
790 /* Map normal MIPS register numbers to mips16 register numbers. */
792 #define X ILLEGAL_REG
793 static const int mips32_to_16_reg_map
[] =
795 X
, X
, 2, 3, 4, 5, 6, 7,
796 X
, X
, X
, X
, X
, X
, X
, X
,
797 0, 1, X
, X
, X
, X
, X
, X
,
798 X
, X
, X
, X
, X
, X
, X
, X
802 /* Map mips16 register numbers to normal MIPS register numbers. */
804 static const unsigned int mips16_to_32_reg_map
[] =
806 16, 17, 2, 3, 4, 5, 6, 7
809 /* Map normal MIPS register numbers to microMIPS register numbers. */
811 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
813 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
814 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
815 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
819 #define X ILLEGAL_REG
820 /* reg type h: 4, 5, 6. */
821 static const int mips32_to_micromips_reg_h_map
[] =
823 X
, X
, X
, X
, 4, 5, 6, X
,
824 X
, X
, X
, X
, X
, X
, X
, X
,
825 X
, X
, X
, X
, X
, X
, X
, X
,
826 X
, X
, X
, X
, X
, X
, X
, X
829 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
830 static const int mips32_to_micromips_reg_m_map
[] =
832 0, X
, 2, 3, X
, X
, X
, X
,
833 X
, X
, X
, X
, X
, X
, X
, X
,
834 4, 1, 5, 6, 7, X
, X
, X
,
835 X
, X
, X
, X
, X
, X
, X
, X
838 /* reg type q: 0, 2-7. 17. */
839 static const int mips32_to_micromips_reg_q_map
[] =
841 0, X
, 2, 3, 4, 5, 6, 7,
842 X
, X
, X
, X
, X
, X
, X
, X
,
843 X
, 1, X
, X
, X
, X
, X
, X
,
844 X
, X
, X
, X
, X
, X
, X
, X
847 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
850 /* Map microMIPS register numbers to normal MIPS register numbers. */
852 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
853 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
854 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
855 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
856 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
859 /* The microMIPS registers with type h. */
860 static const unsigned int micromips_to_32_reg_h_map
[] =
862 5, 5, 6, 4, 4, 4, 4, 4
865 /* The microMIPS registers with type i. */
866 static const unsigned int micromips_to_32_reg_i_map
[] =
868 6, 7, 7, 21, 22, 5, 6, 7
871 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
873 /* The microMIPS registers with type m. */
874 static const unsigned int micromips_to_32_reg_m_map
[] =
876 0, 17, 2, 3, 16, 18, 19, 20
879 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
881 /* The microMIPS registers with type q. */
882 static const unsigned int micromips_to_32_reg_q_map
[] =
884 0, 17, 2, 3, 4, 5, 6, 7
887 /* microMIPS imm type B. */
888 static const int micromips_imm_b_map
[] =
890 1, 4, 8, 12, 16, 20, 24, -1
893 /* microMIPS imm type C. */
894 static const int micromips_imm_c_map
[] =
896 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
899 /* Classifies the kind of instructions we're interested in when
900 implementing -mfix-vr4120. */
901 enum fix_vr4120_class
909 NUM_FIX_VR4120_CLASSES
912 /* ...likewise -mfix-loongson2f-jump. */
913 static bfd_boolean mips_fix_loongson2f_jump
;
915 /* ...likewise -mfix-loongson2f-nop. */
916 static bfd_boolean mips_fix_loongson2f_nop
;
918 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
919 static bfd_boolean mips_fix_loongson2f
;
921 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
922 there must be at least one other instruction between an instruction
923 of type X and an instruction of type Y. */
924 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
926 /* True if -mfix-vr4120 is in force. */
927 static int mips_fix_vr4120
;
929 /* ...likewise -mfix-vr4130. */
930 static int mips_fix_vr4130
;
932 /* ...likewise -mfix-24k. */
933 static int mips_fix_24k
;
935 /* ...likewise -mfix-cn63xxp1 */
936 static bfd_boolean mips_fix_cn63xxp1
;
938 /* We don't relax branches by default, since this causes us to expand
939 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
940 fail to compute the offset before expanding the macro to the most
941 efficient expansion. */
943 static int mips_relax_branch
;
945 /* The expansion of many macros depends on the type of symbol that
946 they refer to. For example, when generating position-dependent code,
947 a macro that refers to a symbol may have two different expansions,
948 one which uses GP-relative addresses and one which uses absolute
949 addresses. When generating SVR4-style PIC, a macro may have
950 different expansions for local and global symbols.
952 We handle these situations by generating both sequences and putting
953 them in variant frags. In position-dependent code, the first sequence
954 will be the GP-relative one and the second sequence will be the
955 absolute one. In SVR4 PIC, the first sequence will be for global
956 symbols and the second will be for local symbols.
958 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
959 SECOND are the lengths of the two sequences in bytes. These fields
960 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
961 the subtype has the following flags:
964 Set if it has been decided that we should use the second
965 sequence instead of the first.
968 Set in the first variant frag if the macro's second implementation
969 is longer than its first. This refers to the macro as a whole,
970 not an individual relaxation.
973 Set in the first variant frag if the macro appeared in a .set nomacro
974 block and if one alternative requires a warning but the other does not.
977 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
980 RELAX_DELAY_SLOT_16BIT
981 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
984 RELAX_DELAY_SLOT_SIZE_FIRST
985 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
986 the macro is of the wrong size for the branch delay slot.
988 RELAX_DELAY_SLOT_SIZE_SECOND
989 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
990 the macro is of the wrong size for the branch delay slot.
992 The frag's "opcode" points to the first fixup for relaxable code.
994 Relaxable macros are generated using a sequence such as:
996 relax_start (SYMBOL);
997 ... generate first expansion ...
999 ... generate second expansion ...
1002 The code and fixups for the unwanted alternative are discarded
1003 by md_convert_frag. */
1004 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1006 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1007 #define RELAX_SECOND(X) ((X) & 0xff)
1008 #define RELAX_USE_SECOND 0x10000
1009 #define RELAX_SECOND_LONGER 0x20000
1010 #define RELAX_NOMACRO 0x40000
1011 #define RELAX_DELAY_SLOT 0x80000
1012 #define RELAX_DELAY_SLOT_16BIT 0x100000
1013 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1014 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1016 /* Branch without likely bit. If label is out of range, we turn:
1018 beq reg1, reg2, label
1028 with the following opcode replacements:
1035 bltzal <-> bgezal (with jal label instead of j label)
1037 Even though keeping the delay slot instruction in the delay slot of
1038 the branch would be more efficient, it would be very tricky to do
1039 correctly, because we'd have to introduce a variable frag *after*
1040 the delay slot instruction, and expand that instead. Let's do it
1041 the easy way for now, even if the branch-not-taken case now costs
1042 one additional instruction. Out-of-range branches are not supposed
1043 to be common, anyway.
1045 Branch likely. If label is out of range, we turn:
1047 beql reg1, reg2, label
1048 delay slot (annulled if branch not taken)
1057 delay slot (executed only if branch taken)
1060 It would be possible to generate a shorter sequence by losing the
1061 likely bit, generating something like:
1066 delay slot (executed only if branch taken)
1078 bltzall -> bgezal (with jal label instead of j label)
1079 bgezall -> bltzal (ditto)
1082 but it's not clear that it would actually improve performance. */
1083 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1084 ((relax_substateT) \
1087 | ((toofar) ? 0x20 : 0) \
1088 | ((link) ? 0x40 : 0) \
1089 | ((likely) ? 0x80 : 0) \
1090 | ((uncond) ? 0x100 : 0)))
1091 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1092 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1093 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1094 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1095 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1096 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1098 /* For mips16 code, we use an entirely different form of relaxation.
1099 mips16 supports two versions of most instructions which take
1100 immediate values: a small one which takes some small value, and a
1101 larger one which takes a 16 bit value. Since branches also follow
1102 this pattern, relaxing these values is required.
1104 We can assemble both mips16 and normal MIPS code in a single
1105 object. Therefore, we need to support this type of relaxation at
1106 the same time that we support the relaxation described above. We
1107 use the high bit of the subtype field to distinguish these cases.
1109 The information we store for this type of relaxation is the
1110 argument code found in the opcode file for this relocation, whether
1111 the user explicitly requested a small or extended form, and whether
1112 the relocation is in a jump or jal delay slot. That tells us the
1113 size of the value, and how it should be stored. We also store
1114 whether the fragment is considered to be extended or not. We also
1115 store whether this is known to be a branch to a different section,
1116 whether we have tried to relax this frag yet, and whether we have
1117 ever extended a PC relative fragment because of a shift count. */
1118 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1121 | ((small) ? 0x100 : 0) \
1122 | ((ext) ? 0x200 : 0) \
1123 | ((dslot) ? 0x400 : 0) \
1124 | ((jal_dslot) ? 0x800 : 0))
1125 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1126 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1127 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1128 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1129 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1130 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1131 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1132 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1133 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1134 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1135 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1136 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1138 /* For microMIPS code, we use relaxation similar to one we use for
1139 MIPS16 code. Some instructions that take immediate values support
1140 two encodings: a small one which takes some small value, and a
1141 larger one which takes a 16 bit value. As some branches also follow
1142 this pattern, relaxing these values is required.
1144 We can assemble both microMIPS and normal MIPS code in a single
1145 object. Therefore, we need to support this type of relaxation at
1146 the same time that we support the relaxation described above. We
1147 use one of the high bits of the subtype field to distinguish these
1150 The information we store for this type of relaxation is the argument
1151 code found in the opcode file for this relocation, the register
1152 selected as the assembler temporary, whether the branch is
1153 unconditional, whether it is compact, whether it stores the link
1154 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1155 branches to a sequence of instructions is enabled, and whether the
1156 displacement of a branch is too large to fit as an immediate argument
1157 of a 16-bit and a 32-bit branch, respectively. */
1158 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1159 relax32, toofar16, toofar32) \
1162 | (((at) & 0x1f) << 8) \
1163 | ((uncond) ? 0x2000 : 0) \
1164 | ((compact) ? 0x4000 : 0) \
1165 | ((link) ? 0x8000 : 0) \
1166 | ((relax32) ? 0x10000 : 0) \
1167 | ((toofar16) ? 0x20000 : 0) \
1168 | ((toofar32) ? 0x40000 : 0))
1169 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1170 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1171 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1172 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1173 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1174 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1175 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1177 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1178 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1179 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1180 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1181 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1182 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1184 /* Is the given value a sign-extended 32-bit value? */
1185 #define IS_SEXT_32BIT_NUM(x) \
1186 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1187 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1189 /* Is the given value a sign-extended 16-bit value? */
1190 #define IS_SEXT_16BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1194 /* Is the given value a sign-extended 12-bit value? */
1195 #define IS_SEXT_12BIT_NUM(x) \
1196 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1198 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1199 #define IS_ZEXT_32BIT_NUM(x) \
1200 (((x) &~ (offsetT) 0xffffffff) == 0 \
1201 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1203 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1204 VALUE << SHIFT. VALUE is evaluated exactly once. */
1205 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1206 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1207 | (((VALUE) & (MASK)) << (SHIFT)))
1209 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1211 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1212 (((STRUCT) >> (SHIFT)) & (MASK))
1214 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1215 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1217 include/opcode/mips.h specifies operand fields using the macros
1218 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1219 with "MIPS16OP" instead of "OP". */
1220 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1223 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1224 OP_MASK_##FIELD, OP_SH_##FIELD); \
1226 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1227 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1229 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1233 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1234 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1236 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1237 : EXTRACT_BITS ((INSN).insn_opcode, \
1238 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1239 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1240 EXTRACT_BITS ((INSN).insn_opcode, \
1241 MIPS16OP_MASK_##FIELD, \
1242 MIPS16OP_SH_##FIELD)
1244 /* Whether or not we are emitting a branch-likely macro. */
1245 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1247 /* Global variables used when generating relaxable macros. See the
1248 comment above RELAX_ENCODE for more details about how relaxation
1251 /* 0 if we're not emitting a relaxable macro.
1252 1 if we're emitting the first of the two relaxation alternatives.
1253 2 if we're emitting the second alternative. */
1256 /* The first relaxable fixup in the current frag. (In other words,
1257 the first fixup that refers to relaxable code.) */
1260 /* sizes[0] says how many bytes of the first alternative are stored in
1261 the current frag. Likewise sizes[1] for the second alternative. */
1262 unsigned int sizes
[2];
1264 /* The symbol on which the choice of sequence depends. */
1268 /* Global variables used to decide whether a macro needs a warning. */
1270 /* True if the macro is in a branch delay slot. */
1271 bfd_boolean delay_slot_p
;
1273 /* Set to the length in bytes required if the macro is in a delay slot
1274 that requires a specific length of instruction, otherwise zero. */
1275 unsigned int delay_slot_length
;
1277 /* For relaxable macros, sizes[0] is the length of the first alternative
1278 in bytes and sizes[1] is the length of the second alternative.
1279 For non-relaxable macros, both elements give the length of the
1281 unsigned int sizes
[2];
1283 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1284 instruction of the first alternative in bytes and first_insn_sizes[1]
1285 is the length of the first instruction of the second alternative.
1286 For non-relaxable macros, both elements give the length of the first
1287 instruction in bytes.
1289 Set to zero if we haven't yet seen the first instruction. */
1290 unsigned int first_insn_sizes
[2];
1292 /* For relaxable macros, insns[0] is the number of instructions for the
1293 first alternative and insns[1] is the number of instructions for the
1296 For non-relaxable macros, both elements give the number of
1297 instructions for the macro. */
1298 unsigned int insns
[2];
1300 /* The first variant frag for this macro. */
1302 } mips_macro_warning
;
1304 /* Prototypes for static functions. */
1306 #define internalError() \
1307 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1309 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1311 static void append_insn
1312 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1313 bfd_boolean expansionp
);
1314 static void mips_no_prev_insn (void);
1315 static void macro_build (expressionS
*, const char *, const char *, ...);
1316 static void mips16_macro_build
1317 (expressionS
*, const char *, const char *, va_list *);
1318 static void load_register (int, expressionS
*, int);
1319 static void macro_start (void);
1320 static void macro_end (void);
1321 static void macro (struct mips_cl_insn
* ip
);
1322 static void mips16_macro (struct mips_cl_insn
* ip
);
1323 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1324 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1325 static void mips16_immed
1326 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1327 unsigned long *, bfd_boolean
*, unsigned short *);
1328 static size_t my_getSmallExpression
1329 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1330 static void my_getExpression (expressionS
*, char *);
1331 static void s_align (int);
1332 static void s_change_sec (int);
1333 static void s_change_section (int);
1334 static void s_cons (int);
1335 static void s_float_cons (int);
1336 static void s_mips_globl (int);
1337 static void s_option (int);
1338 static void s_mipsset (int);
1339 static void s_abicalls (int);
1340 static void s_cpload (int);
1341 static void s_cpsetup (int);
1342 static void s_cplocal (int);
1343 static void s_cprestore (int);
1344 static void s_cpreturn (int);
1345 static void s_dtprelword (int);
1346 static void s_dtpreldword (int);
1347 static void s_tprelword (int);
1348 static void s_tpreldword (int);
1349 static void s_gpvalue (int);
1350 static void s_gpword (int);
1351 static void s_gpdword (int);
1352 static void s_cpadd (int);
1353 static void s_insn (int);
1354 static void md_obj_begin (void);
1355 static void md_obj_end (void);
1356 static void s_mips_ent (int);
1357 static void s_mips_end (int);
1358 static void s_mips_frame (int);
1359 static void s_mips_mask (int reg_type
);
1360 static void s_mips_stab (int);
1361 static void s_mips_weakext (int);
1362 static void s_mips_file (int);
1363 static void s_mips_loc (int);
1364 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1365 static int relaxed_branch_length (fragS
*, asection
*, int);
1366 static int validate_mips_insn (const struct mips_opcode
*);
1367 static int validate_micromips_insn (const struct mips_opcode
*);
1368 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1369 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1371 /* Table and functions used to map between CPU/ISA names, and
1372 ISA levels, and CPU numbers. */
1374 struct mips_cpu_info
1376 const char *name
; /* CPU or ISA name. */
1377 int flags
; /* ASEs available, or ISA flag. */
1378 int isa
; /* ISA level. */
1379 int cpu
; /* CPU number (default CPU if ISA). */
1382 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1383 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1384 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1385 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1386 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1387 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1388 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1389 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1391 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1392 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1393 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1397 The following pseudo-ops from the Kane and Heinrich MIPS book
1398 should be defined here, but are currently unsupported: .alias,
1399 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1401 The following pseudo-ops from the Kane and Heinrich MIPS book are
1402 specific to the type of debugging information being generated, and
1403 should be defined by the object format: .aent, .begin, .bend,
1404 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1407 The following pseudo-ops from the Kane and Heinrich MIPS book are
1408 not MIPS CPU specific, but are also not specific to the object file
1409 format. This file is probably the best place to define them, but
1410 they are not currently supported: .asm0, .endr, .lab, .struct. */
1412 static const pseudo_typeS mips_pseudo_table
[] =
1414 /* MIPS specific pseudo-ops. */
1415 {"option", s_option
, 0},
1416 {"set", s_mipsset
, 0},
1417 {"rdata", s_change_sec
, 'r'},
1418 {"sdata", s_change_sec
, 's'},
1419 {"livereg", s_ignore
, 0},
1420 {"abicalls", s_abicalls
, 0},
1421 {"cpload", s_cpload
, 0},
1422 {"cpsetup", s_cpsetup
, 0},
1423 {"cplocal", s_cplocal
, 0},
1424 {"cprestore", s_cprestore
, 0},
1425 {"cpreturn", s_cpreturn
, 0},
1426 {"dtprelword", s_dtprelword
, 0},
1427 {"dtpreldword", s_dtpreldword
, 0},
1428 {"tprelword", s_tprelword
, 0},
1429 {"tpreldword", s_tpreldword
, 0},
1430 {"gpvalue", s_gpvalue
, 0},
1431 {"gpword", s_gpword
, 0},
1432 {"gpdword", s_gpdword
, 0},
1433 {"cpadd", s_cpadd
, 0},
1434 {"insn", s_insn
, 0},
1436 /* Relatively generic pseudo-ops that happen to be used on MIPS
1438 {"asciiz", stringer
, 8 + 1},
1439 {"bss", s_change_sec
, 'b'},
1441 {"half", s_cons
, 1},
1442 {"dword", s_cons
, 3},
1443 {"weakext", s_mips_weakext
, 0},
1444 {"origin", s_org
, 0},
1445 {"repeat", s_rept
, 0},
1447 /* For MIPS this is non-standard, but we define it for consistency. */
1448 {"sbss", s_change_sec
, 'B'},
1450 /* These pseudo-ops are defined in read.c, but must be overridden
1451 here for one reason or another. */
1452 {"align", s_align
, 0},
1453 {"byte", s_cons
, 0},
1454 {"data", s_change_sec
, 'd'},
1455 {"double", s_float_cons
, 'd'},
1456 {"float", s_float_cons
, 'f'},
1457 {"globl", s_mips_globl
, 0},
1458 {"global", s_mips_globl
, 0},
1459 {"hword", s_cons
, 1},
1461 {"long", s_cons
, 2},
1462 {"octa", s_cons
, 4},
1463 {"quad", s_cons
, 3},
1464 {"section", s_change_section
, 0},
1465 {"short", s_cons
, 1},
1466 {"single", s_float_cons
, 'f'},
1467 {"stabn", s_mips_stab
, 'n'},
1468 {"text", s_change_sec
, 't'},
1469 {"word", s_cons
, 2},
1471 { "extern", ecoff_directive_extern
, 0},
1476 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1478 /* These pseudo-ops should be defined by the object file format.
1479 However, a.out doesn't support them, so we have versions here. */
1480 {"aent", s_mips_ent
, 1},
1481 {"bgnb", s_ignore
, 0},
1482 {"end", s_mips_end
, 0},
1483 {"endb", s_ignore
, 0},
1484 {"ent", s_mips_ent
, 0},
1485 {"file", s_mips_file
, 0},
1486 {"fmask", s_mips_mask
, 'F'},
1487 {"frame", s_mips_frame
, 0},
1488 {"loc", s_mips_loc
, 0},
1489 {"mask", s_mips_mask
, 'R'},
1490 {"verstamp", s_ignore
, 0},
1494 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1495 purpose of the `.dc.a' internal pseudo-op. */
1498 mips_address_bytes (void)
1500 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1503 extern void pop_insert (const pseudo_typeS
*);
1506 mips_pop_insert (void)
1508 pop_insert (mips_pseudo_table
);
1509 if (! ECOFF_DEBUGGING
)
1510 pop_insert (mips_nonecoff_pseudo_table
);
1513 /* Symbols labelling the current insn. */
1515 struct insn_label_list
1517 struct insn_label_list
*next
;
1521 static struct insn_label_list
*free_insn_labels
;
1522 #define label_list tc_segment_info_data.labels
1524 static void mips_clear_insn_labels (void);
1525 static void mips_mark_labels (void);
1526 static void mips_compressed_mark_labels (void);
1529 mips_clear_insn_labels (void)
1531 register struct insn_label_list
**pl
;
1532 segment_info_type
*si
;
1536 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1539 si
= seg_info (now_seg
);
1540 *pl
= si
->label_list
;
1541 si
->label_list
= NULL
;
1545 /* Mark instruction labels in MIPS16/microMIPS mode. */
1548 mips_mark_labels (void)
1550 if (HAVE_CODE_COMPRESSION
)
1551 mips_compressed_mark_labels ();
1554 static char *expr_end
;
1556 /* Expressions which appear in instructions. These are set by
1559 static expressionS imm_expr
;
1560 static expressionS imm2_expr
;
1561 static expressionS offset_expr
;
1563 /* Relocs associated with imm_expr and offset_expr. */
1565 static bfd_reloc_code_real_type imm_reloc
[3]
1566 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1567 static bfd_reloc_code_real_type offset_reloc
[3]
1568 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1570 /* This is set to the resulting size of the instruction to be produced
1571 by mips16_ip if an explicit extension is used or by mips_ip if an
1572 explicit size is supplied. */
1574 static unsigned int forced_insn_length
;
1577 /* The pdr segment for per procedure frame/regmask info. Not used for
1580 static segT pdr_seg
;
1583 /* The default target format to use. */
1585 #if defined (TE_FreeBSD)
1586 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1587 #elif defined (TE_TMIPS)
1588 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1590 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1594 mips_target_format (void)
1596 switch (OUTPUT_FLAVOR
)
1598 case bfd_target_ecoff_flavour
:
1599 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1600 case bfd_target_coff_flavour
:
1602 case bfd_target_elf_flavour
:
1604 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1605 return (target_big_endian
1606 ? "elf32-bigmips-vxworks"
1607 : "elf32-littlemips-vxworks");
1609 return (target_big_endian
1610 ? (HAVE_64BIT_OBJECTS
1611 ? ELF_TARGET ("elf64-", "big")
1613 ? ELF_TARGET ("elf32-n", "big")
1614 : ELF_TARGET ("elf32-", "big")))
1615 : (HAVE_64BIT_OBJECTS
1616 ? ELF_TARGET ("elf64-", "little")
1618 ? ELF_TARGET ("elf32-n", "little")
1619 : ELF_TARGET ("elf32-", "little"))));
1626 /* Return the length of a microMIPS instruction in bytes. If bits of
1627 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1628 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1629 major opcode) will require further modifications to the opcode
1632 static inline unsigned int
1633 micromips_insn_length (const struct mips_opcode
*mo
)
1635 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1638 /* Return the length of instruction INSN. */
1640 static inline unsigned int
1641 insn_length (const struct mips_cl_insn
*insn
)
1643 if (mips_opts
.micromips
)
1644 return micromips_insn_length (insn
->insn_mo
);
1645 else if (mips_opts
.mips16
)
1646 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1651 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1654 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1659 insn
->use_extend
= FALSE
;
1661 insn
->insn_opcode
= mo
->match
;
1664 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1665 insn
->fixp
[i
] = NULL
;
1666 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1667 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1668 insn
->mips16_absolute_jump_p
= 0;
1669 insn
->complete_p
= 0;
1672 /* Record the current MIPS16/microMIPS mode in now_seg. */
1675 mips_record_compressed_mode (void)
1677 segment_info_type
*si
;
1679 si
= seg_info (now_seg
);
1680 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1681 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1682 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1683 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1686 /* Install INSN at the location specified by its "frag" and "where" fields. */
1689 install_insn (const struct mips_cl_insn
*insn
)
1691 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1692 if (!HAVE_CODE_COMPRESSION
)
1693 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1694 else if (mips_opts
.micromips
)
1696 unsigned int length
= insn_length (insn
);
1698 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1699 else if (length
== 4)
1701 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1703 md_number_to_chars (f
, insn
->insn_opcode
& 0xffff, 2);
1706 as_bad (_("48-bit microMIPS instructions are not supported"));
1708 else if (insn
->mips16_absolute_jump_p
)
1710 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1711 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1715 if (insn
->use_extend
)
1717 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1720 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1722 mips_record_compressed_mode ();
1725 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1726 and install the opcode in the new location. */
1729 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1734 insn
->where
= where
;
1735 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1736 if (insn
->fixp
[i
] != NULL
)
1738 insn
->fixp
[i
]->fx_frag
= frag
;
1739 insn
->fixp
[i
]->fx_where
= where
;
1741 install_insn (insn
);
1744 /* Add INSN to the end of the output. */
1747 add_fixed_insn (struct mips_cl_insn
*insn
)
1749 char *f
= frag_more (insn_length (insn
));
1750 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1753 /* Start a variant frag and move INSN to the start of the variant part,
1754 marking it as fixed. The other arguments are as for frag_var. */
1757 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1758 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1760 frag_grow (max_chars
);
1761 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1763 frag_var (rs_machine_dependent
, max_chars
, var
,
1764 subtype
, symbol
, offset
, NULL
);
1767 /* Insert N copies of INSN into the history buffer, starting at
1768 position FIRST. Neither FIRST nor N need to be clipped. */
1771 insert_into_history (unsigned int first
, unsigned int n
,
1772 const struct mips_cl_insn
*insn
)
1774 if (mips_relax
.sequence
!= 2)
1778 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1780 history
[i
] = history
[i
- n
];
1786 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1787 the idea is to make it obvious at a glance that each errata is
1791 init_vr4120_conflicts (void)
1793 #define CONFLICT(FIRST, SECOND) \
1794 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1796 /* Errata 21 - [D]DIV[U] after [D]MACC */
1797 CONFLICT (MACC
, DIV
);
1798 CONFLICT (DMACC
, DIV
);
1800 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1801 CONFLICT (DMULT
, DMULT
);
1802 CONFLICT (DMULT
, DMACC
);
1803 CONFLICT (DMACC
, DMULT
);
1804 CONFLICT (DMACC
, DMACC
);
1806 /* Errata 24 - MT{LO,HI} after [D]MACC */
1807 CONFLICT (MACC
, MTHILO
);
1808 CONFLICT (DMACC
, MTHILO
);
1810 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1811 instruction is executed immediately after a MACC or DMACC
1812 instruction, the result of [either instruction] is incorrect." */
1813 CONFLICT (MACC
, MULT
);
1814 CONFLICT (MACC
, DMULT
);
1815 CONFLICT (DMACC
, MULT
);
1816 CONFLICT (DMACC
, DMULT
);
1818 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1819 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1820 DDIV or DDIVU instruction, the result of the MACC or
1821 DMACC instruction is incorrect.". */
1822 CONFLICT (DMULT
, MACC
);
1823 CONFLICT (DMULT
, DMACC
);
1824 CONFLICT (DIV
, MACC
);
1825 CONFLICT (DIV
, DMACC
);
1835 #define RTYPE_MASK 0x1ff00
1836 #define RTYPE_NUM 0x00100
1837 #define RTYPE_FPU 0x00200
1838 #define RTYPE_FCC 0x00400
1839 #define RTYPE_VEC 0x00800
1840 #define RTYPE_GP 0x01000
1841 #define RTYPE_CP0 0x02000
1842 #define RTYPE_PC 0x04000
1843 #define RTYPE_ACC 0x08000
1844 #define RTYPE_CCC 0x10000
1845 #define RNUM_MASK 0x000ff
1846 #define RWARN 0x80000
1848 #define GENERIC_REGISTER_NUMBERS \
1849 {"$0", RTYPE_NUM | 0}, \
1850 {"$1", RTYPE_NUM | 1}, \
1851 {"$2", RTYPE_NUM | 2}, \
1852 {"$3", RTYPE_NUM | 3}, \
1853 {"$4", RTYPE_NUM | 4}, \
1854 {"$5", RTYPE_NUM | 5}, \
1855 {"$6", RTYPE_NUM | 6}, \
1856 {"$7", RTYPE_NUM | 7}, \
1857 {"$8", RTYPE_NUM | 8}, \
1858 {"$9", RTYPE_NUM | 9}, \
1859 {"$10", RTYPE_NUM | 10}, \
1860 {"$11", RTYPE_NUM | 11}, \
1861 {"$12", RTYPE_NUM | 12}, \
1862 {"$13", RTYPE_NUM | 13}, \
1863 {"$14", RTYPE_NUM | 14}, \
1864 {"$15", RTYPE_NUM | 15}, \
1865 {"$16", RTYPE_NUM | 16}, \
1866 {"$17", RTYPE_NUM | 17}, \
1867 {"$18", RTYPE_NUM | 18}, \
1868 {"$19", RTYPE_NUM | 19}, \
1869 {"$20", RTYPE_NUM | 20}, \
1870 {"$21", RTYPE_NUM | 21}, \
1871 {"$22", RTYPE_NUM | 22}, \
1872 {"$23", RTYPE_NUM | 23}, \
1873 {"$24", RTYPE_NUM | 24}, \
1874 {"$25", RTYPE_NUM | 25}, \
1875 {"$26", RTYPE_NUM | 26}, \
1876 {"$27", RTYPE_NUM | 27}, \
1877 {"$28", RTYPE_NUM | 28}, \
1878 {"$29", RTYPE_NUM | 29}, \
1879 {"$30", RTYPE_NUM | 30}, \
1880 {"$31", RTYPE_NUM | 31}
1882 #define FPU_REGISTER_NAMES \
1883 {"$f0", RTYPE_FPU | 0}, \
1884 {"$f1", RTYPE_FPU | 1}, \
1885 {"$f2", RTYPE_FPU | 2}, \
1886 {"$f3", RTYPE_FPU | 3}, \
1887 {"$f4", RTYPE_FPU | 4}, \
1888 {"$f5", RTYPE_FPU | 5}, \
1889 {"$f6", RTYPE_FPU | 6}, \
1890 {"$f7", RTYPE_FPU | 7}, \
1891 {"$f8", RTYPE_FPU | 8}, \
1892 {"$f9", RTYPE_FPU | 9}, \
1893 {"$f10", RTYPE_FPU | 10}, \
1894 {"$f11", RTYPE_FPU | 11}, \
1895 {"$f12", RTYPE_FPU | 12}, \
1896 {"$f13", RTYPE_FPU | 13}, \
1897 {"$f14", RTYPE_FPU | 14}, \
1898 {"$f15", RTYPE_FPU | 15}, \
1899 {"$f16", RTYPE_FPU | 16}, \
1900 {"$f17", RTYPE_FPU | 17}, \
1901 {"$f18", RTYPE_FPU | 18}, \
1902 {"$f19", RTYPE_FPU | 19}, \
1903 {"$f20", RTYPE_FPU | 20}, \
1904 {"$f21", RTYPE_FPU | 21}, \
1905 {"$f22", RTYPE_FPU | 22}, \
1906 {"$f23", RTYPE_FPU | 23}, \
1907 {"$f24", RTYPE_FPU | 24}, \
1908 {"$f25", RTYPE_FPU | 25}, \
1909 {"$f26", RTYPE_FPU | 26}, \
1910 {"$f27", RTYPE_FPU | 27}, \
1911 {"$f28", RTYPE_FPU | 28}, \
1912 {"$f29", RTYPE_FPU | 29}, \
1913 {"$f30", RTYPE_FPU | 30}, \
1914 {"$f31", RTYPE_FPU | 31}
1916 #define FPU_CONDITION_CODE_NAMES \
1917 {"$fcc0", RTYPE_FCC | 0}, \
1918 {"$fcc1", RTYPE_FCC | 1}, \
1919 {"$fcc2", RTYPE_FCC | 2}, \
1920 {"$fcc3", RTYPE_FCC | 3}, \
1921 {"$fcc4", RTYPE_FCC | 4}, \
1922 {"$fcc5", RTYPE_FCC | 5}, \
1923 {"$fcc6", RTYPE_FCC | 6}, \
1924 {"$fcc7", RTYPE_FCC | 7}
1926 #define COPROC_CONDITION_CODE_NAMES \
1927 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1928 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1929 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1930 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1931 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1932 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1933 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1934 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1936 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1937 {"$a4", RTYPE_GP | 8}, \
1938 {"$a5", RTYPE_GP | 9}, \
1939 {"$a6", RTYPE_GP | 10}, \
1940 {"$a7", RTYPE_GP | 11}, \
1941 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1942 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1943 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1944 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1945 {"$t0", RTYPE_GP | 12}, \
1946 {"$t1", RTYPE_GP | 13}, \
1947 {"$t2", RTYPE_GP | 14}, \
1948 {"$t3", RTYPE_GP | 15}
1950 #define O32_SYMBOLIC_REGISTER_NAMES \
1951 {"$t0", RTYPE_GP | 8}, \
1952 {"$t1", RTYPE_GP | 9}, \
1953 {"$t2", RTYPE_GP | 10}, \
1954 {"$t3", RTYPE_GP | 11}, \
1955 {"$t4", RTYPE_GP | 12}, \
1956 {"$t5", RTYPE_GP | 13}, \
1957 {"$t6", RTYPE_GP | 14}, \
1958 {"$t7", RTYPE_GP | 15}, \
1959 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1960 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1961 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1962 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1964 /* Remaining symbolic register names */
1965 #define SYMBOLIC_REGISTER_NAMES \
1966 {"$zero", RTYPE_GP | 0}, \
1967 {"$at", RTYPE_GP | 1}, \
1968 {"$AT", RTYPE_GP | 1}, \
1969 {"$v0", RTYPE_GP | 2}, \
1970 {"$v1", RTYPE_GP | 3}, \
1971 {"$a0", RTYPE_GP | 4}, \
1972 {"$a1", RTYPE_GP | 5}, \
1973 {"$a2", RTYPE_GP | 6}, \
1974 {"$a3", RTYPE_GP | 7}, \
1975 {"$s0", RTYPE_GP | 16}, \
1976 {"$s1", RTYPE_GP | 17}, \
1977 {"$s2", RTYPE_GP | 18}, \
1978 {"$s3", RTYPE_GP | 19}, \
1979 {"$s4", RTYPE_GP | 20}, \
1980 {"$s5", RTYPE_GP | 21}, \
1981 {"$s6", RTYPE_GP | 22}, \
1982 {"$s7", RTYPE_GP | 23}, \
1983 {"$t8", RTYPE_GP | 24}, \
1984 {"$t9", RTYPE_GP | 25}, \
1985 {"$k0", RTYPE_GP | 26}, \
1986 {"$kt0", RTYPE_GP | 26}, \
1987 {"$k1", RTYPE_GP | 27}, \
1988 {"$kt1", RTYPE_GP | 27}, \
1989 {"$gp", RTYPE_GP | 28}, \
1990 {"$sp", RTYPE_GP | 29}, \
1991 {"$s8", RTYPE_GP | 30}, \
1992 {"$fp", RTYPE_GP | 30}, \
1993 {"$ra", RTYPE_GP | 31}
1995 #define MIPS16_SPECIAL_REGISTER_NAMES \
1996 {"$pc", RTYPE_PC | 0}
1998 #define MDMX_VECTOR_REGISTER_NAMES \
1999 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2000 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2001 {"$v2", RTYPE_VEC | 2}, \
2002 {"$v3", RTYPE_VEC | 3}, \
2003 {"$v4", RTYPE_VEC | 4}, \
2004 {"$v5", RTYPE_VEC | 5}, \
2005 {"$v6", RTYPE_VEC | 6}, \
2006 {"$v7", RTYPE_VEC | 7}, \
2007 {"$v8", RTYPE_VEC | 8}, \
2008 {"$v9", RTYPE_VEC | 9}, \
2009 {"$v10", RTYPE_VEC | 10}, \
2010 {"$v11", RTYPE_VEC | 11}, \
2011 {"$v12", RTYPE_VEC | 12}, \
2012 {"$v13", RTYPE_VEC | 13}, \
2013 {"$v14", RTYPE_VEC | 14}, \
2014 {"$v15", RTYPE_VEC | 15}, \
2015 {"$v16", RTYPE_VEC | 16}, \
2016 {"$v17", RTYPE_VEC | 17}, \
2017 {"$v18", RTYPE_VEC | 18}, \
2018 {"$v19", RTYPE_VEC | 19}, \
2019 {"$v20", RTYPE_VEC | 20}, \
2020 {"$v21", RTYPE_VEC | 21}, \
2021 {"$v22", RTYPE_VEC | 22}, \
2022 {"$v23", RTYPE_VEC | 23}, \
2023 {"$v24", RTYPE_VEC | 24}, \
2024 {"$v25", RTYPE_VEC | 25}, \
2025 {"$v26", RTYPE_VEC | 26}, \
2026 {"$v27", RTYPE_VEC | 27}, \
2027 {"$v28", RTYPE_VEC | 28}, \
2028 {"$v29", RTYPE_VEC | 29}, \
2029 {"$v30", RTYPE_VEC | 30}, \
2030 {"$v31", RTYPE_VEC | 31}
2032 #define MIPS_DSP_ACCUMULATOR_NAMES \
2033 {"$ac0", RTYPE_ACC | 0}, \
2034 {"$ac1", RTYPE_ACC | 1}, \
2035 {"$ac2", RTYPE_ACC | 2}, \
2036 {"$ac3", RTYPE_ACC | 3}
2038 static const struct regname reg_names
[] = {
2039 GENERIC_REGISTER_NUMBERS
,
2041 FPU_CONDITION_CODE_NAMES
,
2042 COPROC_CONDITION_CODE_NAMES
,
2044 /* The $txx registers depends on the abi,
2045 these will be added later into the symbol table from
2046 one of the tables below once mips_abi is set after
2047 parsing of arguments from the command line. */
2048 SYMBOLIC_REGISTER_NAMES
,
2050 MIPS16_SPECIAL_REGISTER_NAMES
,
2051 MDMX_VECTOR_REGISTER_NAMES
,
2052 MIPS_DSP_ACCUMULATOR_NAMES
,
2056 static const struct regname reg_names_o32
[] = {
2057 O32_SYMBOLIC_REGISTER_NAMES
,
2061 static const struct regname reg_names_n32n64
[] = {
2062 N32N64_SYMBOLIC_REGISTER_NAMES
,
2066 /* Check if S points at a valid register specifier according to TYPES.
2067 If so, then return 1, advance S to consume the specifier and store
2068 the register's number in REGNOP, otherwise return 0. */
2071 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2078 /* Find end of name. */
2080 if (is_name_beginner (*e
))
2082 while (is_part_of_name (*e
))
2085 /* Terminate name. */
2089 /* Look for a register symbol. */
2090 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2092 int r
= S_GET_VALUE (symbolP
);
2094 reg
= r
& RNUM_MASK
;
2095 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2096 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2097 reg
= (r
& RNUM_MASK
) - 2;
2099 /* Else see if this is a register defined in an itbl entry. */
2100 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2107 if (itbl_get_reg_val (n
, &r
))
2108 reg
= r
& RNUM_MASK
;
2111 /* Advance to next token if a register was recognised. */
2114 else if (types
& RWARN
)
2115 as_warn (_("Unrecognized register name `%s'"), *s
);
2123 /* Check if S points at a valid register list according to TYPES.
2124 If so, then return 1, advance S to consume the list and store
2125 the registers present on the list as a bitmask of ones in REGLISTP,
2126 otherwise return 0. A valid list comprises a comma-separated
2127 enumeration of valid single registers and/or dash-separated
2128 contiguous register ranges as determined by their numbers.
2130 As a special exception if one of s0-s7 registers is specified as
2131 the range's lower delimiter and s8 (fp) is its upper one, then no
2132 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2133 are selected; they have to be listed separately if needed. */
2136 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2138 unsigned int reglist
= 0;
2139 unsigned int lastregno
;
2140 bfd_boolean ok
= TRUE
;
2141 unsigned int regmask
;
2142 char *s_endlist
= *s
;
2146 while (reg_lookup (s
, types
, ®no
))
2152 ok
= reg_lookup (s
, types
, &lastregno
);
2153 if (ok
&& lastregno
< regno
)
2159 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2164 regmask
= 1 << lastregno
;
2165 regmask
= (regmask
<< 1) - 1;
2166 regmask
^= (1 << regno
) - 1;
2180 *reglistp
= reglist
;
2181 return ok
&& reglist
!= 0;
2184 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2185 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2188 is_opcode_valid (const struct mips_opcode
*mo
)
2190 int isa
= mips_opts
.isa
;
2193 if (mips_opts
.ase_mdmx
)
2195 if (mips_opts
.ase_dsp
)
2197 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2199 if (mips_opts
.ase_dspr2
)
2201 if (mips_opts
.ase_mt
)
2203 if (mips_opts
.ase_mips3d
)
2205 if (mips_opts
.ase_smartmips
)
2206 isa
|= INSN_SMARTMIPS
;
2207 if (mips_opts
.ase_mcu
)
2210 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2213 /* Check whether the instruction or macro requires single-precision or
2214 double-precision floating-point support. Note that this information is
2215 stored differently in the opcode table for insns and macros. */
2216 if (mo
->pinfo
== INSN_MACRO
)
2218 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2219 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2223 fp_s
= mo
->pinfo
& FP_S
;
2224 fp_d
= mo
->pinfo
& FP_D
;
2227 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2230 if (fp_s
&& mips_opts
.soft_float
)
2236 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2237 selected ISA and architecture. */
2240 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2242 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2245 /* Return TRUE if the size of the microMIPS opcode MO matches one
2246 explicitly requested. Always TRUE in the standard MIPS mode. */
2249 is_size_valid (const struct mips_opcode
*mo
)
2251 if (!mips_opts
.micromips
)
2254 if (!forced_insn_length
)
2256 if (mo
->pinfo
== INSN_MACRO
)
2258 return forced_insn_length
== micromips_insn_length (mo
);
2261 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2262 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2265 is_delay_slot_valid (const struct mips_opcode
*mo
)
2267 if (!mips_opts
.micromips
)
2270 if (mo
->pinfo
== INSN_MACRO
)
2272 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2273 && micromips_insn_length (mo
) != 4)
2275 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2276 && micromips_insn_length (mo
) != 2)
2282 /* This function is called once, at assembler startup time. It should set up
2283 all the tables, etc. that the MD part of the assembler will need. */
2288 const char *retval
= NULL
;
2292 if (mips_pic
!= NO_PIC
)
2294 if (g_switch_seen
&& g_switch_value
!= 0)
2295 as_bad (_("-G may not be used in position-independent code"));
2299 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2300 as_warn (_("Could not set architecture and machine"));
2302 op_hash
= hash_new ();
2304 for (i
= 0; i
< NUMOPCODES
;)
2306 const char *name
= mips_opcodes
[i
].name
;
2308 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2311 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2312 mips_opcodes
[i
].name
, retval
);
2313 /* Probably a memory allocation problem? Give up now. */
2314 as_fatal (_("Broken assembler. No assembly attempted."));
2318 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2320 if (!validate_mips_insn (&mips_opcodes
[i
]))
2322 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2324 create_insn (&nop_insn
, mips_opcodes
+ i
);
2325 if (mips_fix_loongson2f_nop
)
2326 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2327 nop_insn
.fixed_p
= 1;
2332 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2335 mips16_op_hash
= hash_new ();
2338 while (i
< bfd_mips16_num_opcodes
)
2340 const char *name
= mips16_opcodes
[i
].name
;
2342 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2344 as_fatal (_("internal: can't hash `%s': %s"),
2345 mips16_opcodes
[i
].name
, retval
);
2348 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2349 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2350 != mips16_opcodes
[i
].match
))
2352 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2353 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2356 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2358 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2359 mips16_nop_insn
.fixed_p
= 1;
2363 while (i
< bfd_mips16_num_opcodes
2364 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2367 micromips_op_hash
= hash_new ();
2370 while (i
< bfd_micromips_num_opcodes
)
2372 const char *name
= micromips_opcodes
[i
].name
;
2374 retval
= hash_insert (micromips_op_hash
, name
,
2375 (void *) µmips_opcodes
[i
]);
2377 as_fatal (_("internal: can't hash `%s': %s"),
2378 micromips_opcodes
[i
].name
, retval
);
2380 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2382 struct mips_cl_insn
*micromips_nop_insn
;
2384 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2387 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2388 micromips_nop_insn
= µmips_nop16_insn
;
2389 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2390 micromips_nop_insn
= µmips_nop32_insn
;
2394 if (micromips_nop_insn
->insn_mo
== NULL
2395 && strcmp (name
, "nop") == 0)
2397 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2398 micromips_nop_insn
->fixed_p
= 1;
2401 while (++i
< bfd_micromips_num_opcodes
2402 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2406 as_fatal (_("Broken assembler. No assembly attempted."));
2408 /* We add all the general register names to the symbol table. This
2409 helps us detect invalid uses of them. */
2410 for (i
= 0; reg_names
[i
].name
; i
++)
2411 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2412 reg_names
[i
].num
, /* & RNUM_MASK, */
2413 &zero_address_frag
));
2415 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2416 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2417 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2418 &zero_address_frag
));
2420 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2421 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2422 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2423 &zero_address_frag
));
2425 mips_no_prev_insn ();
2428 mips_cprmask
[0] = 0;
2429 mips_cprmask
[1] = 0;
2430 mips_cprmask
[2] = 0;
2431 mips_cprmask
[3] = 0;
2433 /* set the default alignment for the text section (2**2) */
2434 record_alignment (text_section
, 2);
2436 bfd_set_gp_size (stdoutput
, g_switch_value
);
2441 /* On a native system other than VxWorks, sections must be aligned
2442 to 16 byte boundaries. When configured for an embedded ELF
2443 target, we don't bother. */
2444 if (strncmp (TARGET_OS
, "elf", 3) != 0
2445 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2447 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2448 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2449 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2452 /* Create a .reginfo section for register masks and a .mdebug
2453 section for debugging information. */
2461 subseg
= now_subseg
;
2463 /* The ABI says this section should be loaded so that the
2464 running program can access it. However, we don't load it
2465 if we are configured for an embedded target */
2466 flags
= SEC_READONLY
| SEC_DATA
;
2467 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2468 flags
|= SEC_ALLOC
| SEC_LOAD
;
2470 if (mips_abi
!= N64_ABI
)
2472 sec
= subseg_new (".reginfo", (subsegT
) 0);
2474 bfd_set_section_flags (stdoutput
, sec
, flags
);
2475 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2477 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2481 /* The 64-bit ABI uses a .MIPS.options section rather than
2482 .reginfo section. */
2483 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2484 bfd_set_section_flags (stdoutput
, sec
, flags
);
2485 bfd_set_section_alignment (stdoutput
, sec
, 3);
2487 /* Set up the option header. */
2489 Elf_Internal_Options opthdr
;
2492 opthdr
.kind
= ODK_REGINFO
;
2493 opthdr
.size
= (sizeof (Elf_External_Options
)
2494 + sizeof (Elf64_External_RegInfo
));
2497 f
= frag_more (sizeof (Elf_External_Options
));
2498 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2499 (Elf_External_Options
*) f
);
2501 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2505 if (ECOFF_DEBUGGING
)
2507 sec
= subseg_new (".mdebug", (subsegT
) 0);
2508 (void) bfd_set_section_flags (stdoutput
, sec
,
2509 SEC_HAS_CONTENTS
| SEC_READONLY
);
2510 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2512 else if (mips_flag_pdr
)
2514 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2515 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2516 SEC_READONLY
| SEC_RELOC
2518 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2521 subseg_set (seg
, subseg
);
2524 #endif /* OBJ_ELF */
2526 if (! ECOFF_DEBUGGING
)
2529 if (mips_fix_vr4120
)
2530 init_vr4120_conflicts ();
2536 mips_emit_delays ();
2537 if (! ECOFF_DEBUGGING
)
2542 md_assemble (char *str
)
2544 struct mips_cl_insn insn
;
2545 bfd_reloc_code_real_type unused_reloc
[3]
2546 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2548 imm_expr
.X_op
= O_absent
;
2549 imm2_expr
.X_op
= O_absent
;
2550 offset_expr
.X_op
= O_absent
;
2551 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2552 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2553 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2554 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2555 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2556 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2558 if (mips_opts
.mips16
)
2559 mips16_ip (str
, &insn
);
2562 mips_ip (str
, &insn
);
2563 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2564 str
, insn
.insn_opcode
));
2569 as_bad ("%s `%s'", insn_error
, str
);
2573 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2576 if (mips_opts
.mips16
)
2577 mips16_macro (&insn
);
2584 if (imm_expr
.X_op
!= O_absent
)
2585 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2586 else if (offset_expr
.X_op
!= O_absent
)
2587 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2589 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2593 /* Convenience functions for abstracting away the differences between
2594 MIPS16 and non-MIPS16 relocations. */
2596 static inline bfd_boolean
2597 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2601 case BFD_RELOC_MIPS16_JMP
:
2602 case BFD_RELOC_MIPS16_GPREL
:
2603 case BFD_RELOC_MIPS16_GOT16
:
2604 case BFD_RELOC_MIPS16_CALL16
:
2605 case BFD_RELOC_MIPS16_HI16_S
:
2606 case BFD_RELOC_MIPS16_HI16
:
2607 case BFD_RELOC_MIPS16_LO16
:
2615 static inline bfd_boolean
2616 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2620 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2621 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2622 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2623 case BFD_RELOC_MICROMIPS_GPREL16
:
2624 case BFD_RELOC_MICROMIPS_JMP
:
2625 case BFD_RELOC_MICROMIPS_HI16
:
2626 case BFD_RELOC_MICROMIPS_HI16_S
:
2627 case BFD_RELOC_MICROMIPS_LO16
:
2628 case BFD_RELOC_MICROMIPS_LITERAL
:
2629 case BFD_RELOC_MICROMIPS_GOT16
:
2630 case BFD_RELOC_MICROMIPS_CALL16
:
2631 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2632 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2633 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2634 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2635 case BFD_RELOC_MICROMIPS_SUB
:
2636 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2637 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2638 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2639 case BFD_RELOC_MICROMIPS_HIGHEST
:
2640 case BFD_RELOC_MICROMIPS_HIGHER
:
2641 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2642 case BFD_RELOC_MICROMIPS_JALR
:
2650 static inline bfd_boolean
2651 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2653 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2656 static inline bfd_boolean
2657 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2659 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2660 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2663 static inline bfd_boolean
2664 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2666 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2667 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2670 static inline bfd_boolean
2671 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2673 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2674 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2677 static inline bfd_boolean
2678 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2680 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2683 /* Return true if the given relocation might need a matching %lo().
2684 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2685 need a matching %lo() when applied to local symbols. */
2687 static inline bfd_boolean
2688 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2690 return (HAVE_IN_PLACE_ADDENDS
2691 && (hi16_reloc_p (reloc
)
2692 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2693 all GOT16 relocations evaluate to "G". */
2694 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2697 /* Return the type of %lo() reloc needed by RELOC, given that
2698 reloc_needs_lo_p. */
2700 static inline bfd_reloc_code_real_type
2701 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2703 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2704 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2708 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2711 static inline bfd_boolean
2712 fixup_has_matching_lo_p (fixS
*fixp
)
2714 return (fixp
->fx_next
!= NULL
2715 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2716 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2717 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2720 /* This function returns true if modifying a register requires a
2724 reg_needs_delay (unsigned int reg
)
2726 unsigned long prev_pinfo
;
2728 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2729 if (! mips_opts
.noreorder
2730 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2731 && ! gpr_interlocks
)
2732 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2733 && ! cop_interlocks
)))
2735 /* A load from a coprocessor or from memory. All load delays
2736 delay the use of general register rt for one instruction. */
2737 /* Itbl support may require additional care here. */
2738 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2739 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2746 /* Move all labels in LABELS to the current insertion point. TEXT_P
2747 says whether the labels refer to text or data. */
2750 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2752 struct insn_label_list
*l
;
2755 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2757 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2758 symbol_set_frag (l
->label
, frag_now
);
2759 val
= (valueT
) frag_now_fix ();
2760 /* MIPS16/microMIPS text labels are stored as odd. */
2761 if (text_p
&& HAVE_CODE_COMPRESSION
)
2763 S_SET_VALUE (l
->label
, val
);
2767 /* Move all labels in insn_labels to the current insertion point
2768 and treat them as text labels. */
2771 mips_move_text_labels (void)
2773 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2777 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2779 bfd_boolean linkonce
= FALSE
;
2780 segT symseg
= S_GET_SEGMENT (sym
);
2782 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2784 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2787 /* The GNU toolchain uses an extension for ELF: a section
2788 beginning with the magic string .gnu.linkonce is a
2789 linkonce section. */
2790 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2791 sizeof ".gnu.linkonce" - 1) == 0)
2798 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2799 linker to handle them specially, such as generating jalx instructions
2800 when needed. We also make them odd for the duration of the assembly,
2801 in order to generate the right sort of code. We will make them even
2802 in the adjust_symtab routine, while leaving them marked. This is
2803 convenient for the debugger and the disassembler. The linker knows
2804 to make them odd again. */
2807 mips_compressed_mark_labels (void)
2809 segment_info_type
*si
= seg_info (now_seg
);
2810 struct insn_label_list
*l
;
2812 gas_assert (HAVE_CODE_COMPRESSION
);
2814 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2816 symbolS
*label
= l
->label
;
2818 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2821 if (mips_opts
.mips16
)
2822 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2824 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2827 if ((S_GET_VALUE (label
) & 1) == 0
2828 /* Don't adjust the address if the label is global or weak, or
2829 in a link-once section, since we'll be emitting symbol reloc
2830 references to it which will be patched up by the linker, and
2831 the final value of the symbol may or may not be MIPS16/microMIPS. */
2832 && ! S_IS_WEAK (label
)
2833 && ! S_IS_EXTERNAL (label
)
2834 && ! s_is_linkonce (label
, now_seg
))
2835 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2839 /* End the current frag. Make it a variant frag and record the
2843 relax_close_frag (void)
2845 mips_macro_warning
.first_frag
= frag_now
;
2846 frag_var (rs_machine_dependent
, 0, 0,
2847 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2848 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2850 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2851 mips_relax
.first_fixup
= 0;
2854 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2855 See the comment above RELAX_ENCODE for more details. */
2858 relax_start (symbolS
*symbol
)
2860 gas_assert (mips_relax
.sequence
== 0);
2861 mips_relax
.sequence
= 1;
2862 mips_relax
.symbol
= symbol
;
2865 /* Start generating the second version of a relaxable sequence.
2866 See the comment above RELAX_ENCODE for more details. */
2871 gas_assert (mips_relax
.sequence
== 1);
2872 mips_relax
.sequence
= 2;
2875 /* End the current relaxable sequence. */
2880 gas_assert (mips_relax
.sequence
== 2);
2881 relax_close_frag ();
2882 mips_relax
.sequence
= 0;
2885 /* Return true if IP is a delayed branch or jump. */
2887 static inline bfd_boolean
2888 delayed_branch_p (const struct mips_cl_insn
*ip
)
2890 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2891 | INSN_COND_BRANCH_DELAY
2892 | INSN_COND_BRANCH_LIKELY
)) != 0;
2895 /* Return true if IP is a compact branch or jump. */
2897 static inline bfd_boolean
2898 compact_branch_p (const struct mips_cl_insn
*ip
)
2900 if (mips_opts
.mips16
)
2901 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2902 | MIPS16_INSN_COND_BRANCH
)) != 0;
2904 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2905 | INSN2_COND_BRANCH
)) != 0;
2908 /* Return true if IP is an unconditional branch or jump. */
2910 static inline bfd_boolean
2911 uncond_branch_p (const struct mips_cl_insn
*ip
)
2913 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2914 || (mips_opts
.mips16
2915 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2916 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2919 /* Return true if IP is a branch-likely instruction. */
2921 static inline bfd_boolean
2922 branch_likely_p (const struct mips_cl_insn
*ip
)
2924 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2927 /* Return the type of nop that should be used to fill the delay slot
2928 of delayed branch IP. */
2930 static struct mips_cl_insn
*
2931 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2933 if (mips_opts
.micromips
2934 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2935 return µmips_nop32_insn
;
2939 /* Return the mask of core registers that IP reads or writes. */
2942 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2944 unsigned long pinfo2
;
2948 pinfo2
= ip
->insn_mo
->pinfo2
;
2949 if (mips_opts
.micromips
)
2951 if (pinfo2
& INSN2_MOD_GPR_MD
)
2952 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2953 if (pinfo2
& INSN2_MOD_GPR_MF
)
2954 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
2955 if (pinfo2
& INSN2_MOD_SP
)
2961 /* Return the mask of core registers that IP reads. */
2964 gpr_read_mask (const struct mips_cl_insn
*ip
)
2966 unsigned long pinfo
, pinfo2
;
2969 mask
= gpr_mod_mask (ip
);
2970 pinfo
= ip
->insn_mo
->pinfo
;
2971 pinfo2
= ip
->insn_mo
->pinfo2
;
2972 if (mips_opts
.mips16
)
2974 if (pinfo
& MIPS16_INSN_READ_X
)
2975 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
2976 if (pinfo
& MIPS16_INSN_READ_Y
)
2977 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
2978 if (pinfo
& MIPS16_INSN_READ_T
)
2980 if (pinfo
& MIPS16_INSN_READ_SP
)
2982 if (pinfo
& MIPS16_INSN_READ_31
)
2984 if (pinfo
& MIPS16_INSN_READ_Z
)
2985 mask
|= 1 << (mips16_to_32_reg_map
2986 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
2987 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2988 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2992 if (pinfo2
& INSN2_READ_GPR_D
)
2993 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
2994 if (pinfo
& INSN_READ_GPR_T
)
2995 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
2996 if (pinfo
& INSN_READ_GPR_S
)
2997 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
2998 if (pinfo2
& INSN2_READ_GP
)
3000 if (pinfo2
& INSN2_READ_GPR_31
)
3002 if (pinfo2
& INSN2_READ_GPR_Z
)
3003 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3005 if (mips_opts
.micromips
)
3007 if (pinfo2
& INSN2_READ_GPR_MC
)
3008 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3009 if (pinfo2
& INSN2_READ_GPR_ME
)
3010 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3011 if (pinfo2
& INSN2_READ_GPR_MG
)
3012 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3013 if (pinfo2
& INSN2_READ_GPR_MJ
)
3014 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3015 if (pinfo2
& INSN2_READ_GPR_MMN
)
3017 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3018 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3020 if (pinfo2
& INSN2_READ_GPR_MP
)
3021 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3022 if (pinfo2
& INSN2_READ_GPR_MQ
)
3023 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3025 /* Don't include register 0. */
3029 /* Return the mask of core registers that IP writes. */
3032 gpr_write_mask (const struct mips_cl_insn
*ip
)
3034 unsigned long pinfo
, pinfo2
;
3037 mask
= gpr_mod_mask (ip
);
3038 pinfo
= ip
->insn_mo
->pinfo
;
3039 pinfo2
= ip
->insn_mo
->pinfo2
;
3040 if (mips_opts
.mips16
)
3042 if (pinfo
& MIPS16_INSN_WRITE_X
)
3043 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3044 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3045 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3046 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3047 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3048 if (pinfo
& MIPS16_INSN_WRITE_T
)
3050 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3052 if (pinfo
& MIPS16_INSN_WRITE_31
)
3054 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3055 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3059 if (pinfo
& INSN_WRITE_GPR_D
)
3060 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3061 if (pinfo
& INSN_WRITE_GPR_T
)
3062 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3063 if (pinfo
& INSN_WRITE_GPR_S
)
3064 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3065 if (pinfo
& INSN_WRITE_GPR_31
)
3067 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3068 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3070 if (mips_opts
.micromips
)
3072 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3073 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3074 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3076 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3077 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3079 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3080 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3081 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3082 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3084 /* Don't include register 0. */
3088 /* Return the mask of floating-point registers that IP reads. */
3091 fpr_read_mask (const struct mips_cl_insn
*ip
)
3093 unsigned long pinfo
, pinfo2
;
3097 pinfo
= ip
->insn_mo
->pinfo
;
3098 pinfo2
= ip
->insn_mo
->pinfo2
;
3099 if (!mips_opts
.mips16
)
3101 if (pinfo2
& INSN2_READ_FPR_D
)
3102 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3103 if (pinfo
& INSN_READ_FPR_S
)
3104 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3105 if (pinfo
& INSN_READ_FPR_T
)
3106 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3107 if (pinfo
& INSN_READ_FPR_R
)
3108 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3109 if (pinfo2
& INSN2_READ_FPR_Z
)
3110 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3112 /* Conservatively treat all operands to an FP_D instruction are doubles.
3113 (This is overly pessimistic for things like cvt.d.s.) */
3114 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3119 /* Return the mask of floating-point registers that IP writes. */
3122 fpr_write_mask (const struct mips_cl_insn
*ip
)
3124 unsigned long pinfo
, pinfo2
;
3128 pinfo
= ip
->insn_mo
->pinfo
;
3129 pinfo2
= ip
->insn_mo
->pinfo2
;
3130 if (!mips_opts
.mips16
)
3132 if (pinfo
& INSN_WRITE_FPR_D
)
3133 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3134 if (pinfo
& INSN_WRITE_FPR_S
)
3135 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3136 if (pinfo
& INSN_WRITE_FPR_T
)
3137 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3138 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3139 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3141 /* Conservatively treat all operands to an FP_D instruction are doubles.
3142 (This is overly pessimistic for things like cvt.s.d.) */
3143 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3148 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3149 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3150 by VR4120 errata. */
3153 classify_vr4120_insn (const char *name
)
3155 if (strncmp (name
, "macc", 4) == 0)
3156 return FIX_VR4120_MACC
;
3157 if (strncmp (name
, "dmacc", 5) == 0)
3158 return FIX_VR4120_DMACC
;
3159 if (strncmp (name
, "mult", 4) == 0)
3160 return FIX_VR4120_MULT
;
3161 if (strncmp (name
, "dmult", 5) == 0)
3162 return FIX_VR4120_DMULT
;
3163 if (strstr (name
, "div"))
3164 return FIX_VR4120_DIV
;
3165 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3166 return FIX_VR4120_MTHILO
;
3167 return NUM_FIX_VR4120_CLASSES
;
3170 #define INSN_ERET 0x42000018
3171 #define INSN_DERET 0x4200001f
3173 /* Return the number of instructions that must separate INSN1 and INSN2,
3174 where INSN1 is the earlier instruction. Return the worst-case value
3175 for any INSN2 if INSN2 is null. */
3178 insns_between (const struct mips_cl_insn
*insn1
,
3179 const struct mips_cl_insn
*insn2
)
3181 unsigned long pinfo1
, pinfo2
;
3184 /* This function needs to know which pinfo flags are set for INSN2
3185 and which registers INSN2 uses. The former is stored in PINFO2 and
3186 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3187 will have every flag set and INSN2_USES_GPR will always return true. */
3188 pinfo1
= insn1
->insn_mo
->pinfo
;
3189 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3191 #define INSN2_USES_GPR(REG) \
3192 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3194 /* For most targets, write-after-read dependencies on the HI and LO
3195 registers must be separated by at least two instructions. */
3196 if (!hilo_interlocks
)
3198 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3200 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3204 /* If we're working around r7000 errata, there must be two instructions
3205 between an mfhi or mflo and any instruction that uses the result. */
3206 if (mips_7000_hilo_fix
3207 && !mips_opts
.micromips
3208 && MF_HILO_INSN (pinfo1
)
3209 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3212 /* If we're working around 24K errata, one instruction is required
3213 if an ERET or DERET is followed by a branch instruction. */
3214 if (mips_fix_24k
&& !mips_opts
.micromips
)
3216 if (insn1
->insn_opcode
== INSN_ERET
3217 || insn1
->insn_opcode
== INSN_DERET
)
3220 || insn2
->insn_opcode
== INSN_ERET
3221 || insn2
->insn_opcode
== INSN_DERET
3222 || delayed_branch_p (insn2
))
3227 /* If working around VR4120 errata, check for combinations that need
3228 a single intervening instruction. */
3229 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3231 unsigned int class1
, class2
;
3233 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3234 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3238 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3239 if (vr4120_conflicts
[class1
] & (1 << class2
))
3244 if (!HAVE_CODE_COMPRESSION
)
3246 /* Check for GPR or coprocessor load delays. All such delays
3247 are on the RT register. */
3248 /* Itbl support may require additional care here. */
3249 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3250 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3252 know (pinfo1
& INSN_WRITE_GPR_T
);
3253 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3257 /* Check for generic coprocessor hazards.
3259 This case is not handled very well. There is no special
3260 knowledge of CP0 handling, and the coprocessors other than
3261 the floating point unit are not distinguished at all. */
3262 /* Itbl support may require additional care here. FIXME!
3263 Need to modify this to include knowledge about
3264 user specified delays! */
3265 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3266 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3268 /* Handle cases where INSN1 writes to a known general coprocessor
3269 register. There must be a one instruction delay before INSN2
3270 if INSN2 reads that register, otherwise no delay is needed. */
3271 mask
= fpr_write_mask (insn1
);
3274 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3279 /* Read-after-write dependencies on the control registers
3280 require a two-instruction gap. */
3281 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3282 && (pinfo2
& INSN_READ_COND_CODE
))
3285 /* We don't know exactly what INSN1 does. If INSN2 is
3286 also a coprocessor instruction, assume there must be
3287 a one instruction gap. */
3288 if (pinfo2
& INSN_COP
)
3293 /* Check for read-after-write dependencies on the coprocessor
3294 control registers in cases where INSN1 does not need a general
3295 coprocessor delay. This means that INSN1 is a floating point
3296 comparison instruction. */
3297 /* Itbl support may require additional care here. */
3298 else if (!cop_interlocks
3299 && (pinfo1
& INSN_WRITE_COND_CODE
)
3300 && (pinfo2
& INSN_READ_COND_CODE
))
3304 #undef INSN2_USES_GPR
3309 /* Return the number of nops that would be needed to work around the
3310 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3311 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3312 that are contained within the first IGNORE instructions of HIST. */
3315 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3316 const struct mips_cl_insn
*insn
)
3321 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3322 are not affected by the errata. */
3324 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3325 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3326 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3329 /* Search for the first MFLO or MFHI. */
3330 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3331 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3333 /* Extract the destination register. */
3334 mask
= gpr_write_mask (&hist
[i
]);
3336 /* No nops are needed if INSN reads that register. */
3337 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3340 /* ...or if any of the intervening instructions do. */
3341 for (j
= 0; j
< i
; j
++)
3342 if (gpr_read_mask (&hist
[j
]) & mask
)
3346 return MAX_VR4130_NOPS
- i
;
3351 #define BASE_REG_EQ(INSN1, INSN2) \
3352 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3353 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3355 /* Return the minimum alignment for this store instruction. */
3358 fix_24k_align_to (const struct mips_opcode
*mo
)
3360 if (strcmp (mo
->name
, "sh") == 0)
3363 if (strcmp (mo
->name
, "swc1") == 0
3364 || strcmp (mo
->name
, "swc2") == 0
3365 || strcmp (mo
->name
, "sw") == 0
3366 || strcmp (mo
->name
, "sc") == 0
3367 || strcmp (mo
->name
, "s.s") == 0)
3370 if (strcmp (mo
->name
, "sdc1") == 0
3371 || strcmp (mo
->name
, "sdc2") == 0
3372 || strcmp (mo
->name
, "s.d") == 0)
3379 struct fix_24k_store_info
3381 /* Immediate offset, if any, for this store instruction. */
3383 /* Alignment required by this store instruction. */
3385 /* True for register offsets. */
3386 int register_offset
;
3389 /* Comparison function used by qsort. */
3392 fix_24k_sort (const void *a
, const void *b
)
3394 const struct fix_24k_store_info
*pos1
= a
;
3395 const struct fix_24k_store_info
*pos2
= b
;
3397 return (pos1
->off
- pos2
->off
);
3400 /* INSN is a store instruction. Try to record the store information
3401 in STINFO. Return false if the information isn't known. */
3404 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3405 const struct mips_cl_insn
*insn
)
3407 /* The instruction must have a known offset. */
3408 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3411 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3412 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3416 /* Return the number of nops that would be needed to work around the 24k
3417 "lost data on stores during refill" errata if instruction INSN
3418 immediately followed the 2 instructions described by HIST.
3419 Ignore hazards that are contained within the first IGNORE
3420 instructions of HIST.
3422 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3423 for the data cache refills and store data. The following describes
3424 the scenario where the store data could be lost.
3426 * A data cache miss, due to either a load or a store, causing fill
3427 data to be supplied by the memory subsystem
3428 * The first three doublewords of fill data are returned and written
3430 * A sequence of four stores occurs in consecutive cycles around the
3431 final doubleword of the fill:
3435 * Zero, One or more instructions
3438 The four stores A-D must be to different doublewords of the line that
3439 is being filled. The fourth instruction in the sequence above permits
3440 the fill of the final doubleword to be transferred from the FSB into
3441 the cache. In the sequence above, the stores may be either integer
3442 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3443 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3444 different doublewords on the line. If the floating point unit is
3445 running in 1:2 mode, it is not possible to create the sequence above
3446 using only floating point store instructions.
3448 In this case, the cache line being filled is incorrectly marked
3449 invalid, thereby losing the data from any store to the line that
3450 occurs between the original miss and the completion of the five
3451 cycle sequence shown above.
3453 The workarounds are:
3455 * Run the data cache in write-through mode.
3456 * Insert a non-store instruction between
3457 Store A and Store B or Store B and Store C. */
3460 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3461 const struct mips_cl_insn
*insn
)
3463 struct fix_24k_store_info pos
[3];
3464 int align
, i
, base_offset
;
3469 /* If the previous instruction wasn't a store, there's nothing to
3471 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3474 /* If the instructions after the previous one are unknown, we have
3475 to assume the worst. */
3479 /* Check whether we are dealing with three consecutive stores. */
3480 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3481 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3484 /* If we don't know the relationship between the store addresses,
3485 assume the worst. */
3486 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3487 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3490 if (!fix_24k_record_store_info (&pos
[0], insn
)
3491 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3492 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3495 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3497 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3498 X bytes and such that the base register + X is known to be aligned
3501 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3505 align
= pos
[0].align_to
;
3506 base_offset
= pos
[0].off
;
3507 for (i
= 1; i
< 3; i
++)
3508 if (align
< pos
[i
].align_to
)
3510 align
= pos
[i
].align_to
;
3511 base_offset
= pos
[i
].off
;
3513 for (i
= 0; i
< 3; i
++)
3514 pos
[i
].off
-= base_offset
;
3517 pos
[0].off
&= ~align
+ 1;
3518 pos
[1].off
&= ~align
+ 1;
3519 pos
[2].off
&= ~align
+ 1;
3521 /* If any two stores write to the same chunk, they also write to the
3522 same doubleword. The offsets are still sorted at this point. */
3523 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3526 /* A range of at least 9 bytes is needed for the stores to be in
3527 non-overlapping doublewords. */
3528 if (pos
[2].off
- pos
[0].off
<= 8)
3531 if (pos
[2].off
- pos
[1].off
>= 24
3532 || pos
[1].off
- pos
[0].off
>= 24
3533 || pos
[2].off
- pos
[0].off
>= 32)
3539 /* Return the number of nops that would be needed if instruction INSN
3540 immediately followed the MAX_NOPS instructions given by HIST,
3541 where HIST[0] is the most recent instruction. Ignore hazards
3542 between INSN and the first IGNORE instructions in HIST.
3544 If INSN is null, return the worse-case number of nops for any
3548 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3549 const struct mips_cl_insn
*insn
)
3551 int i
, nops
, tmp_nops
;
3554 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3556 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3557 if (tmp_nops
> nops
)
3561 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3563 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3564 if (tmp_nops
> nops
)
3568 if (mips_fix_24k
&& !mips_opts
.micromips
)
3570 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3571 if (tmp_nops
> nops
)
3578 /* The variable arguments provide NUM_INSNS extra instructions that
3579 might be added to HIST. Return the largest number of nops that
3580 would be needed after the extended sequence, ignoring hazards
3581 in the first IGNORE instructions. */
3584 nops_for_sequence (int num_insns
, int ignore
,
3585 const struct mips_cl_insn
*hist
, ...)
3588 struct mips_cl_insn buffer
[MAX_NOPS
];
3589 struct mips_cl_insn
*cursor
;
3592 va_start (args
, hist
);
3593 cursor
= buffer
+ num_insns
;
3594 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3595 while (cursor
> buffer
)
3596 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3598 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3603 /* Like nops_for_insn, but if INSN is a branch, take into account the
3604 worst-case delay for the branch target. */
3607 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3608 const struct mips_cl_insn
*insn
)
3612 nops
= nops_for_insn (ignore
, hist
, insn
);
3613 if (delayed_branch_p (insn
))
3615 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3616 hist
, insn
, get_delay_slot_nop (insn
));
3617 if (tmp_nops
> nops
)
3620 else if (compact_branch_p (insn
))
3622 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3623 if (tmp_nops
> nops
)
3629 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3632 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3634 gas_assert (!HAVE_CODE_COMPRESSION
);
3635 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3636 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3639 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3640 jr target pc &= 'hffff_ffff_cfff_ffff. */
3643 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3645 gas_assert (!HAVE_CODE_COMPRESSION
);
3646 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3647 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3648 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3656 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3657 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3660 ep
.X_op
= O_constant
;
3661 ep
.X_add_number
= 0xcfff0000;
3662 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3663 ep
.X_add_number
= 0xffff;
3664 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3665 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3670 fix_loongson2f (struct mips_cl_insn
* ip
)
3672 if (mips_fix_loongson2f_nop
)
3673 fix_loongson2f_nop (ip
);
3675 if (mips_fix_loongson2f_jump
)
3676 fix_loongson2f_jump (ip
);
3679 /* IP is a branch that has a delay slot, and we need to fill it
3680 automatically. Return true if we can do that by swapping IP
3681 with the previous instruction. */
3684 can_swap_branch_p (struct mips_cl_insn
*ip
)
3686 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3687 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3689 /* -O2 and above is required for this optimization. */
3690 if (mips_optimize
< 2)
3693 /* If we have seen .set volatile or .set nomove, don't optimize. */
3694 if (mips_opts
.nomove
)
3697 /* We can't swap if the previous instruction's position is fixed. */
3698 if (history
[0].fixed_p
)
3701 /* If the previous previous insn was in a .set noreorder, we can't
3702 swap. Actually, the MIPS assembler will swap in this situation.
3703 However, gcc configured -with-gnu-as will generate code like
3711 in which we can not swap the bne and INSN. If gcc is not configured
3712 -with-gnu-as, it does not output the .set pseudo-ops. */
3713 if (history
[1].noreorder_p
)
3716 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3717 This means that the previous instruction was a 4-byte one anyhow. */
3718 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3721 /* If the branch is itself the target of a branch, we can not swap.
3722 We cheat on this; all we check for is whether there is a label on
3723 this instruction. If there are any branches to anything other than
3724 a label, users must use .set noreorder. */
3725 if (seg_info (now_seg
)->label_list
)
3728 /* If the previous instruction is in a variant frag other than this
3729 branch's one, we cannot do the swap. This does not apply to
3730 MIPS16 code, which uses variant frags for different purposes. */
3731 if (!mips_opts
.mips16
3733 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3736 /* We do not swap with instructions that cannot architecturally
3737 be placed in a branch delay slot, such as SYNC or ERET. We
3738 also refrain from swapping with a trap instruction, since it
3739 complicates trap handlers to have the trap instruction be in
3741 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3742 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3745 /* Check for conflicts between the branch and the instructions
3746 before the candidate delay slot. */
3747 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3750 /* Check for conflicts between the swapped sequence and the
3751 target of the branch. */
3752 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3755 /* If the branch reads a register that the previous
3756 instruction sets, we can not swap. */
3757 gpr_read
= gpr_read_mask (ip
);
3758 prev_gpr_write
= gpr_write_mask (&history
[0]);
3759 if (gpr_read
& prev_gpr_write
)
3762 /* If the branch writes a register that the previous
3763 instruction sets, we can not swap. */
3764 gpr_write
= gpr_write_mask (ip
);
3765 if (gpr_write
& prev_gpr_write
)
3768 /* If the branch writes a register that the previous
3769 instruction reads, we can not swap. */
3770 prev_gpr_read
= gpr_read_mask (&history
[0]);
3771 if (gpr_write
& prev_gpr_read
)
3774 /* If one instruction sets a condition code and the
3775 other one uses a condition code, we can not swap. */
3776 pinfo
= ip
->insn_mo
->pinfo
;
3777 if ((pinfo
& INSN_READ_COND_CODE
)
3778 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3780 if ((pinfo
& INSN_WRITE_COND_CODE
)
3781 && (prev_pinfo
& INSN_READ_COND_CODE
))
3784 /* If the previous instruction uses the PC, we can not swap. */
3785 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3786 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3788 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3791 /* If the previous instruction has an incorrect size for a fixed
3792 branch delay slot in microMIPS mode, we cannot swap. */
3793 pinfo2
= ip
->insn_mo
->pinfo2
;
3794 if (mips_opts
.micromips
3795 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3796 && insn_length (history
) != 2)
3798 if (mips_opts
.micromips
3799 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3800 && insn_length (history
) != 4)
3806 /* Decide how we should add IP to the instruction stream. */
3808 static enum append_method
3809 get_append_method (struct mips_cl_insn
*ip
)
3811 unsigned long pinfo
;
3813 /* The relaxed version of a macro sequence must be inherently
3815 if (mips_relax
.sequence
== 2)
3818 /* We must not dabble with instructions in a ".set norerorder" block. */
3819 if (mips_opts
.noreorder
)
3822 /* Otherwise, it's our responsibility to fill branch delay slots. */
3823 if (delayed_branch_p (ip
))
3825 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3828 pinfo
= ip
->insn_mo
->pinfo
;
3829 if (mips_opts
.mips16
3830 && ISA_SUPPORTS_MIPS16E
3831 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3832 return APPEND_ADD_COMPACT
;
3834 return APPEND_ADD_WITH_NOP
;
3840 /* IP is a MIPS16 instruction whose opcode we have just changed.
3841 Point IP->insn_mo to the new opcode's definition. */
3844 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3846 const struct mips_opcode
*mo
, *end
;
3848 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3849 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3850 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3858 /* For microMIPS macros, we need to generate a local number label
3859 as the target of branches. */
3860 #define MICROMIPS_LABEL_CHAR '\037'
3861 static unsigned long micromips_target_label
;
3862 static char micromips_target_name
[32];
3865 micromips_label_name (void)
3867 char *p
= micromips_target_name
;
3868 char symbol_name_temporary
[24];
3876 l
= micromips_target_label
;
3877 #ifdef LOCAL_LABEL_PREFIX
3878 *p
++ = LOCAL_LABEL_PREFIX
;
3881 *p
++ = MICROMIPS_LABEL_CHAR
;
3884 symbol_name_temporary
[i
++] = l
% 10 + '0';
3889 *p
++ = symbol_name_temporary
[--i
];
3892 return micromips_target_name
;
3896 micromips_label_expr (expressionS
*label_expr
)
3898 label_expr
->X_op
= O_symbol
;
3899 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3900 label_expr
->X_add_number
= 0;
3904 micromips_label_inc (void)
3906 micromips_target_label
++;
3907 *micromips_target_name
= '\0';
3911 micromips_add_label (void)
3915 s
= colon (micromips_label_name ());
3916 micromips_label_inc ();
3917 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3919 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3925 /* If assembling microMIPS code, then return the microMIPS reloc
3926 corresponding to the requested one if any. Otherwise return
3927 the reloc unchanged. */
3929 static bfd_reloc_code_real_type
3930 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3932 static const bfd_reloc_code_real_type relocs
[][2] =
3934 /* Keep sorted incrementally by the left-hand key. */
3935 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3936 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3937 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3938 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3939 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3940 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3941 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3942 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3943 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3944 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3945 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3946 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3947 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3948 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3949 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3950 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3951 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3952 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3953 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
3954 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
3955 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
3956 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
3957 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
3958 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
3959 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
3960 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
3961 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
3963 bfd_reloc_code_real_type r
;
3966 if (!mips_opts
.micromips
)
3968 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
3974 return relocs
[i
][1];
3979 /* Output an instruction. IP is the instruction information.
3980 ADDRESS_EXPR is an operand of the instruction to be used with
3981 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3982 a macro expansion. */
3985 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3986 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
3988 unsigned long prev_pinfo2
, pinfo
;
3989 bfd_boolean relaxed_branch
= FALSE
;
3990 enum append_method method
;
3991 bfd_boolean relax32
;
3994 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
3995 fix_loongson2f (ip
);
3997 mips_mark_labels ();
3999 file_ase_mips16
|= mips_opts
.mips16
;
4000 file_ase_micromips
|= mips_opts
.micromips
;
4002 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4003 pinfo
= ip
->insn_mo
->pinfo
;
4005 if (mips_opts
.micromips
4007 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4008 && micromips_insn_length (ip
->insn_mo
) != 2)
4009 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4010 && micromips_insn_length (ip
->insn_mo
) != 4)))
4011 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4012 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4014 if (address_expr
== NULL
)
4016 else if (*reloc_type
<= BFD_RELOC_UNUSED
4017 && address_expr
->X_op
== O_constant
)
4022 switch (*reloc_type
)
4025 ip
->insn_opcode
|= address_expr
->X_add_number
;
4028 case BFD_RELOC_MIPS_HIGHEST
:
4029 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
4030 ip
->insn_opcode
|= tmp
& 0xffff;
4033 case BFD_RELOC_MIPS_HIGHER
:
4034 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
4035 ip
->insn_opcode
|= tmp
& 0xffff;
4038 case BFD_RELOC_HI16_S
:
4039 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
4040 ip
->insn_opcode
|= tmp
& 0xffff;
4043 case BFD_RELOC_HI16
:
4044 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
4047 case BFD_RELOC_UNUSED
:
4048 case BFD_RELOC_LO16
:
4049 case BFD_RELOC_MIPS_GOT_DISP
:
4050 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
4053 case BFD_RELOC_MIPS_JMP
:
4057 shift
= mips_opts
.micromips
? 1 : 2;
4058 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4059 as_bad (_("jump to misaligned address (0x%lx)"),
4060 (unsigned long) address_expr
->X_add_number
);
4061 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4067 case BFD_RELOC_MIPS16_JMP
:
4068 if ((address_expr
->X_add_number
& 3) != 0)
4069 as_bad (_("jump to misaligned address (0x%lx)"),
4070 (unsigned long) address_expr
->X_add_number
);
4072 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4073 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4074 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4078 case BFD_RELOC_16_PCREL_S2
:
4082 shift
= mips_opts
.micromips
? 1 : 2;
4083 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4084 as_bad (_("branch to misaligned address (0x%lx)"),
4085 (unsigned long) address_expr
->X_add_number
);
4086 if (!mips_relax_branch
)
4088 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4089 & ~((1 << (shift
+ 16)) - 1))
4090 as_bad (_("branch address range overflow (0x%lx)"),
4091 (unsigned long) address_expr
->X_add_number
);
4092 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4106 /* There are a lot of optimizations we could do that we don't.
4107 In particular, we do not, in general, reorder instructions.
4108 If you use gcc with optimization, it will reorder
4109 instructions and generally do much more optimization then we
4110 do here; repeating all that work in the assembler would only
4111 benefit hand written assembly code, and does not seem worth
4113 int nops
= (mips_optimize
== 0
4114 ? nops_for_insn (0, history
, NULL
)
4115 : nops_for_insn_or_target (0, history
, ip
));
4119 unsigned long old_frag_offset
;
4122 old_frag
= frag_now
;
4123 old_frag_offset
= frag_now_fix ();
4125 for (i
= 0; i
< nops
; i
++)
4126 add_fixed_insn (NOP_INSN
);
4127 insert_into_history (0, nops
, NOP_INSN
);
4131 listing_prev_line ();
4132 /* We may be at the start of a variant frag. In case we
4133 are, make sure there is enough space for the frag
4134 after the frags created by listing_prev_line. The
4135 argument to frag_grow here must be at least as large
4136 as the argument to all other calls to frag_grow in
4137 this file. We don't have to worry about being in the
4138 middle of a variant frag, because the variants insert
4139 all needed nop instructions themselves. */
4143 mips_move_text_labels ();
4145 #ifndef NO_ECOFF_DEBUGGING
4146 if (ECOFF_DEBUGGING
)
4147 ecoff_fix_loc (old_frag
, old_frag_offset
);
4151 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4155 /* Work out how many nops in prev_nop_frag are needed by IP,
4156 ignoring hazards generated by the first prev_nop_frag_since
4158 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4159 gas_assert (nops
<= prev_nop_frag_holds
);
4161 /* Enforce NOPS as a minimum. */
4162 if (nops
> prev_nop_frag_required
)
4163 prev_nop_frag_required
= nops
;
4165 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4167 /* Settle for the current number of nops. Update the history
4168 accordingly (for the benefit of any future .set reorder code). */
4169 prev_nop_frag
= NULL
;
4170 insert_into_history (prev_nop_frag_since
,
4171 prev_nop_frag_holds
, NOP_INSN
);
4175 /* Allow this instruction to replace one of the nops that was
4176 tentatively added to prev_nop_frag. */
4177 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4178 prev_nop_frag_holds
--;
4179 prev_nop_frag_since
++;
4183 method
= get_append_method (ip
);
4184 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4187 /* The value passed to dwarf2_emit_insn is the distance between
4188 the beginning of the current instruction and the address that
4189 should be recorded in the debug tables. This is normally the
4192 For MIPS16/microMIPS debug info we want to use ISA-encoded
4193 addresses, so we use -1 for an address higher by one than the
4196 If the instruction produced is a branch that we will swap with
4197 the preceding instruction, then we add the displacement by which
4198 the branch will be moved backwards. This is more appropriate
4199 and for MIPS16/microMIPS code also prevents a debugger from
4200 placing a breakpoint in the middle of the branch (and corrupting
4201 code if software breakpoints are used). */
4202 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4205 relax32
= (mips_relax_branch
4206 /* Don't try branch relaxation within .set nomacro, or within
4207 .set noat if we use $at for PIC computations. If it turns
4208 out that the branch was out-of-range, we'll get an error. */
4209 && !mips_opts
.warn_about_macros
4210 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4211 /* Don't relax BPOSGE32/64 as they have no complementing
4213 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4215 if (!HAVE_CODE_COMPRESSION
4218 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4219 && delayed_branch_p (ip
))
4221 relaxed_branch
= TRUE
;
4222 add_relaxed_insn (ip
, (relaxed_branch_length
4224 uncond_branch_p (ip
) ? -1
4225 : branch_likely_p (ip
) ? 1
4229 uncond_branch_p (ip
),
4230 branch_likely_p (ip
),
4231 pinfo
& INSN_WRITE_GPR_31
,
4233 address_expr
->X_add_symbol
,
4234 address_expr
->X_add_number
);
4235 *reloc_type
= BFD_RELOC_UNUSED
;
4237 else if (mips_opts
.micromips
4239 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4240 || *reloc_type
> BFD_RELOC_UNUSED
)
4241 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4242 /* Don't try branch relaxation when users specify
4243 16-bit/32-bit instructions. */
4244 && !forced_insn_length
)
4246 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4247 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4248 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4249 int compact
= compact_branch_p (ip
);
4250 int al
= pinfo
& INSN_WRITE_GPR_31
;
4253 gas_assert (address_expr
!= NULL
);
4254 gas_assert (!mips_relax
.sequence
);
4256 relaxed_branch
= TRUE
;
4257 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4258 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4259 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4261 address_expr
->X_add_symbol
,
4262 address_expr
->X_add_number
);
4263 *reloc_type
= BFD_RELOC_UNUSED
;
4265 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4267 /* We need to set up a variant frag. */
4268 gas_assert (address_expr
!= NULL
);
4269 add_relaxed_insn (ip
, 4, 0,
4271 (*reloc_type
- BFD_RELOC_UNUSED
,
4272 forced_insn_length
== 2, forced_insn_length
== 4,
4273 delayed_branch_p (&history
[0]),
4274 history
[0].mips16_absolute_jump_p
),
4275 make_expr_symbol (address_expr
), 0);
4277 else if (mips_opts
.mips16
4279 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
4281 if (!delayed_branch_p (ip
))
4282 /* Make sure there is enough room to swap this instruction with
4283 a following jump instruction. */
4285 add_fixed_insn (ip
);
4289 if (mips_opts
.mips16
4290 && mips_opts
.noreorder
4291 && delayed_branch_p (&history
[0]))
4292 as_warn (_("extended instruction in delay slot"));
4294 if (mips_relax
.sequence
)
4296 /* If we've reached the end of this frag, turn it into a variant
4297 frag and record the information for the instructions we've
4299 if (frag_room () < 4)
4300 relax_close_frag ();
4301 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4304 if (mips_relax
.sequence
!= 2)
4306 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4307 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4308 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4309 mips_macro_warning
.insns
[0]++;
4311 if (mips_relax
.sequence
!= 1)
4313 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4314 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4315 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4316 mips_macro_warning
.insns
[1]++;
4319 if (mips_opts
.mips16
)
4322 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4324 add_fixed_insn (ip
);
4327 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4329 bfd_reloc_code_real_type final_type
[3];
4330 reloc_howto_type
*howto0
;
4331 reloc_howto_type
*howto
;
4334 /* Perform any necessary conversion to microMIPS relocations
4335 and find out how many relocations there actually are. */
4336 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4337 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4339 /* In a compound relocation, it is the final (outermost)
4340 operator that determines the relocated field. */
4341 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4345 /* To reproduce this failure try assembling gas/testsuites/
4346 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4348 as_bad (_("Unsupported MIPS relocation number %d"),
4350 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4354 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4355 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4356 bfd_get_reloc_size (howto
),
4358 howto0
&& howto0
->pc_relative
,
4361 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4362 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4363 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4365 /* These relocations can have an addend that won't fit in
4366 4 octets for 64bit assembly. */
4368 && ! howto
->partial_inplace
4369 && (reloc_type
[0] == BFD_RELOC_16
4370 || reloc_type
[0] == BFD_RELOC_32
4371 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4372 || reloc_type
[0] == BFD_RELOC_GPREL16
4373 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4374 || reloc_type
[0] == BFD_RELOC_GPREL32
4375 || reloc_type
[0] == BFD_RELOC_64
4376 || reloc_type
[0] == BFD_RELOC_CTOR
4377 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4378 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4379 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4380 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4381 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4382 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4383 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4384 || hi16_reloc_p (reloc_type
[0])
4385 || lo16_reloc_p (reloc_type
[0])))
4386 ip
->fixp
[0]->fx_no_overflow
= 1;
4388 if (mips_relax
.sequence
)
4390 if (mips_relax
.first_fixup
== 0)
4391 mips_relax
.first_fixup
= ip
->fixp
[0];
4393 else if (reloc_needs_lo_p (*reloc_type
))
4395 struct mips_hi_fixup
*hi_fixup
;
4397 /* Reuse the last entry if it already has a matching %lo. */
4398 hi_fixup
= mips_hi_fixup_list
;
4400 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4402 hi_fixup
= ((struct mips_hi_fixup
*)
4403 xmalloc (sizeof (struct mips_hi_fixup
)));
4404 hi_fixup
->next
= mips_hi_fixup_list
;
4405 mips_hi_fixup_list
= hi_fixup
;
4407 hi_fixup
->fixp
= ip
->fixp
[0];
4408 hi_fixup
->seg
= now_seg
;
4411 /* Add fixups for the second and third relocations, if given.
4412 Note that the ABI allows the second relocation to be
4413 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4414 moment we only use RSS_UNDEF, but we could add support
4415 for the others if it ever becomes necessary. */
4416 for (i
= 1; i
< 3; i
++)
4417 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4419 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4420 ip
->fixp
[0]->fx_size
, NULL
, 0,
4421 FALSE
, final_type
[i
]);
4423 /* Use fx_tcbit to mark compound relocs. */
4424 ip
->fixp
[0]->fx_tcbit
= 1;
4425 ip
->fixp
[i
]->fx_tcbit
= 1;
4430 /* Update the register mask information. */
4431 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4432 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4437 insert_into_history (0, 1, ip
);
4440 case APPEND_ADD_WITH_NOP
:
4442 struct mips_cl_insn
*nop
;
4444 insert_into_history (0, 1, ip
);
4445 nop
= get_delay_slot_nop (ip
);
4446 add_fixed_insn (nop
);
4447 insert_into_history (0, 1, nop
);
4448 if (mips_relax
.sequence
)
4449 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4453 case APPEND_ADD_COMPACT
:
4454 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4455 gas_assert (mips_opts
.mips16
);
4456 ip
->insn_opcode
|= 0x0080;
4457 find_altered_mips16_opcode (ip
);
4459 insert_into_history (0, 1, ip
);
4464 struct mips_cl_insn delay
= history
[0];
4465 if (mips_opts
.mips16
)
4467 know (delay
.frag
== ip
->frag
);
4468 move_insn (ip
, delay
.frag
, delay
.where
);
4469 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4471 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4473 /* Add the delay slot instruction to the end of the
4474 current frag and shrink the fixed part of the
4475 original frag. If the branch occupies the tail of
4476 the latter, move it backwards to cover the gap. */
4477 delay
.frag
->fr_fix
-= branch_disp
;
4478 if (delay
.frag
== ip
->frag
)
4479 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4480 add_fixed_insn (&delay
);
4484 move_insn (&delay
, ip
->frag
,
4485 ip
->where
- branch_disp
+ insn_length (ip
));
4486 move_insn (ip
, history
[0].frag
, history
[0].where
);
4490 insert_into_history (0, 1, &delay
);
4495 /* If we have just completed an unconditional branch, clear the history. */
4496 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4497 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4498 mips_no_prev_insn ();
4500 /* We need to emit a label at the end of branch-likely macros. */
4501 if (emit_branch_likely_macro
)
4503 emit_branch_likely_macro
= FALSE
;
4504 micromips_add_label ();
4507 /* We just output an insn, so the next one doesn't have a label. */
4508 mips_clear_insn_labels ();
4511 /* Forget that there was any previous instruction or label. */
4514 mips_no_prev_insn (void)
4516 prev_nop_frag
= NULL
;
4517 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4518 mips_clear_insn_labels ();
4521 /* This function must be called before we emit something other than
4522 instructions. It is like mips_no_prev_insn except that it inserts
4523 any NOPS that might be needed by previous instructions. */
4526 mips_emit_delays (void)
4528 if (! mips_opts
.noreorder
)
4530 int nops
= nops_for_insn (0, history
, NULL
);
4534 add_fixed_insn (NOP_INSN
);
4535 mips_move_text_labels ();
4538 mips_no_prev_insn ();
4541 /* Start a (possibly nested) noreorder block. */
4544 start_noreorder (void)
4546 if (mips_opts
.noreorder
== 0)
4551 /* None of the instructions before the .set noreorder can be moved. */
4552 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4553 history
[i
].fixed_p
= 1;
4555 /* Insert any nops that might be needed between the .set noreorder
4556 block and the previous instructions. We will later remove any
4557 nops that turn out not to be needed. */
4558 nops
= nops_for_insn (0, history
, NULL
);
4561 if (mips_optimize
!= 0)
4563 /* Record the frag which holds the nop instructions, so
4564 that we can remove them if we don't need them. */
4565 frag_grow (nops
* NOP_INSN_SIZE
);
4566 prev_nop_frag
= frag_now
;
4567 prev_nop_frag_holds
= nops
;
4568 prev_nop_frag_required
= 0;
4569 prev_nop_frag_since
= 0;
4572 for (; nops
> 0; --nops
)
4573 add_fixed_insn (NOP_INSN
);
4575 /* Move on to a new frag, so that it is safe to simply
4576 decrease the size of prev_nop_frag. */
4577 frag_wane (frag_now
);
4579 mips_move_text_labels ();
4581 mips_mark_labels ();
4582 mips_clear_insn_labels ();
4584 mips_opts
.noreorder
++;
4585 mips_any_noreorder
= 1;
4588 /* End a nested noreorder block. */
4591 end_noreorder (void)
4593 mips_opts
.noreorder
--;
4594 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4596 /* Commit to inserting prev_nop_frag_required nops and go back to
4597 handling nop insertion the .set reorder way. */
4598 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4600 insert_into_history (prev_nop_frag_since
,
4601 prev_nop_frag_required
, NOP_INSN
);
4602 prev_nop_frag
= NULL
;
4606 /* Set up global variables for the start of a new macro. */
4611 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4612 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4613 sizeof (mips_macro_warning
.first_insn_sizes
));
4614 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4615 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4616 && delayed_branch_p (&history
[0]));
4617 switch (history
[0].insn_mo
->pinfo2
4618 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4620 case INSN2_BRANCH_DELAY_32BIT
:
4621 mips_macro_warning
.delay_slot_length
= 4;
4623 case INSN2_BRANCH_DELAY_16BIT
:
4624 mips_macro_warning
.delay_slot_length
= 2;
4627 mips_macro_warning
.delay_slot_length
= 0;
4630 mips_macro_warning
.first_frag
= NULL
;
4633 /* Given that a macro is longer than one instruction or of the wrong size,
4634 return the appropriate warning for it. Return null if no warning is
4635 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4636 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4637 and RELAX_NOMACRO. */
4640 macro_warning (relax_substateT subtype
)
4642 if (subtype
& RELAX_DELAY_SLOT
)
4643 return _("Macro instruction expanded into multiple instructions"
4644 " in a branch delay slot");
4645 else if (subtype
& RELAX_NOMACRO
)
4646 return _("Macro instruction expanded into multiple instructions");
4647 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4648 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4649 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4650 ? _("Macro instruction expanded into a wrong size instruction"
4651 " in a 16-bit branch delay slot")
4652 : _("Macro instruction expanded into a wrong size instruction"
4653 " in a 32-bit branch delay slot"));
4658 /* Finish up a macro. Emit warnings as appropriate. */
4663 /* Relaxation warning flags. */
4664 relax_substateT subtype
= 0;
4666 /* Check delay slot size requirements. */
4667 if (mips_macro_warning
.delay_slot_length
== 2)
4668 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4669 if (mips_macro_warning
.delay_slot_length
!= 0)
4671 if (mips_macro_warning
.delay_slot_length
4672 != mips_macro_warning
.first_insn_sizes
[0])
4673 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4674 if (mips_macro_warning
.delay_slot_length
4675 != mips_macro_warning
.first_insn_sizes
[1])
4676 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4679 /* Check instruction count requirements. */
4680 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4682 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4683 subtype
|= RELAX_SECOND_LONGER
;
4684 if (mips_opts
.warn_about_macros
)
4685 subtype
|= RELAX_NOMACRO
;
4686 if (mips_macro_warning
.delay_slot_p
)
4687 subtype
|= RELAX_DELAY_SLOT
;
4690 /* If both alternatives fail to fill a delay slot correctly,
4691 emit the warning now. */
4692 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4693 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4698 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4699 | RELAX_DELAY_SLOT_SIZE_FIRST
4700 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4701 msg
= macro_warning (s
);
4703 as_warn ("%s", msg
);
4707 /* If both implementations are longer than 1 instruction, then emit the
4709 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4714 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4715 msg
= macro_warning (s
);
4717 as_warn ("%s", msg
);
4721 /* If any flags still set, then one implementation might need a warning
4722 and the other either will need one of a different kind or none at all.
4723 Pass any remaining flags over to relaxation. */
4724 if (mips_macro_warning
.first_frag
!= NULL
)
4725 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4728 /* Instruction operand formats used in macros that vary between
4729 standard MIPS and microMIPS code. */
4731 static const char * const brk_fmt
[2] = { "c", "mF" };
4732 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4733 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4734 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4735 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4736 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4737 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4738 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4740 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4741 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4742 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4743 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4744 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4745 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4746 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4747 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4749 /* Read a macro's relocation codes from *ARGS and store them in *R.
4750 The first argument in *ARGS will be either the code for a single
4751 relocation or -1 followed by the three codes that make up a
4752 composite relocation. */
4755 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4759 next
= va_arg (*args
, int);
4761 r
[0] = (bfd_reloc_code_real_type
) next
;
4763 for (i
= 0; i
< 3; i
++)
4764 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4767 /* Build an instruction created by a macro expansion. This is passed
4768 a pointer to the count of instructions created so far, an
4769 expression, the name of the instruction to build, an operand format
4770 string, and corresponding arguments. */
4773 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4775 const struct mips_opcode
*mo
= NULL
;
4776 bfd_reloc_code_real_type r
[3];
4777 const struct mips_opcode
*amo
;
4778 struct hash_control
*hash
;
4779 struct mips_cl_insn insn
;
4782 va_start (args
, fmt
);
4784 if (mips_opts
.mips16
)
4786 mips16_macro_build (ep
, name
, fmt
, &args
);
4791 r
[0] = BFD_RELOC_UNUSED
;
4792 r
[1] = BFD_RELOC_UNUSED
;
4793 r
[2] = BFD_RELOC_UNUSED
;
4794 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4795 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4797 gas_assert (strcmp (name
, amo
->name
) == 0);
4801 /* Search until we get a match for NAME. It is assumed here that
4802 macros will never generate MDMX, MIPS-3D, or MT instructions.
4803 We try to match an instruction that fulfils the branch delay
4804 slot instruction length requirement (if any) of the previous
4805 instruction. While doing this we record the first instruction
4806 seen that matches all the other conditions and use it anyway
4807 if the requirement cannot be met; we will issue an appropriate
4808 warning later on. */
4809 if (strcmp (fmt
, amo
->args
) == 0
4810 && amo
->pinfo
!= INSN_MACRO
4811 && is_opcode_valid (amo
)
4812 && is_size_valid (amo
))
4814 if (is_delay_slot_valid (amo
))
4824 gas_assert (amo
->name
);
4826 while (strcmp (name
, amo
->name
) == 0);
4829 create_insn (&insn
, mo
);
4847 INSERT_OPERAND (mips_opts
.micromips
,
4848 EXTLSB
, insn
, va_arg (args
, int));
4853 /* Note that in the macro case, these arguments are already
4854 in MSB form. (When handling the instruction in the
4855 non-macro case, these arguments are sizes from which
4856 MSB values must be calculated.) */
4857 INSERT_OPERAND (mips_opts
.micromips
,
4858 INSMSB
, insn
, va_arg (args
, int));
4864 /* Note that in the macro case, these arguments are already
4865 in MSBD form. (When handling the instruction in the
4866 non-macro case, these arguments are sizes from which
4867 MSBD values must be calculated.) */
4868 INSERT_OPERAND (mips_opts
.micromips
,
4869 EXTMSBD
, insn
, va_arg (args
, int));
4873 gas_assert (!mips_opts
.micromips
);
4874 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4883 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
4887 gas_assert (mips_opts
.micromips
);
4891 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4895 gas_assert (!mips_opts
.micromips
);
4896 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4900 gas_assert (!mips_opts
.micromips
);
4902 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4906 if (mips_opts
.micromips
)
4907 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4909 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4913 gas_assert (!mips_opts
.micromips
);
4915 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4919 gas_assert (!mips_opts
.micromips
);
4921 int tmp
= va_arg (args
, int);
4923 INSERT_OPERAND (0, RT
, insn
, tmp
);
4924 INSERT_OPERAND (0, RD
, insn
, tmp
);
4930 gas_assert (!mips_opts
.micromips
);
4931 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
4938 INSERT_OPERAND (mips_opts
.micromips
,
4939 SHAMT
, insn
, va_arg (args
, int));
4943 gas_assert (!mips_opts
.micromips
);
4944 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
4948 gas_assert (!mips_opts
.micromips
);
4949 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
4953 gas_assert (!mips_opts
.micromips
);
4954 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
4958 gas_assert (!mips_opts
.micromips
);
4959 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
4966 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
4971 macro_read_relocs (&args
, r
);
4972 gas_assert (*r
== BFD_RELOC_GPREL16
4973 || *r
== BFD_RELOC_MIPS_HIGHER
4974 || *r
== BFD_RELOC_HI16_S
4975 || *r
== BFD_RELOC_LO16
4976 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
4980 macro_read_relocs (&args
, r
);
4984 macro_read_relocs (&args
, r
);
4985 gas_assert (ep
!= NULL
4986 && (ep
->X_op
== O_constant
4987 || (ep
->X_op
== O_symbol
4988 && (*r
== BFD_RELOC_MIPS_HIGHEST
4989 || *r
== BFD_RELOC_HI16_S
4990 || *r
== BFD_RELOC_HI16
4991 || *r
== BFD_RELOC_GPREL16
4992 || *r
== BFD_RELOC_MIPS_GOT_HI16
4993 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
4997 gas_assert (ep
!= NULL
);
5000 * This allows macro() to pass an immediate expression for
5001 * creating short branches without creating a symbol.
5003 * We don't allow branch relaxation for these branches, as
5004 * they should only appear in ".set nomacro" anyway.
5006 if (ep
->X_op
== O_constant
)
5008 /* For microMIPS we always use relocations for branches.
5009 So we should not resolve immediate values. */
5010 gas_assert (!mips_opts
.micromips
);
5012 if ((ep
->X_add_number
& 3) != 0)
5013 as_bad (_("branch to misaligned address (0x%lx)"),
5014 (unsigned long) ep
->X_add_number
);
5015 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5016 as_bad (_("branch address range overflow (0x%lx)"),
5017 (unsigned long) ep
->X_add_number
);
5018 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5022 *r
= BFD_RELOC_16_PCREL_S2
;
5026 gas_assert (ep
!= NULL
);
5027 *r
= BFD_RELOC_MIPS_JMP
;
5031 gas_assert (!mips_opts
.micromips
);
5032 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5036 INSERT_OPERAND (mips_opts
.micromips
,
5037 CACHE
, insn
, va_arg (args
, unsigned long));
5041 gas_assert (mips_opts
.micromips
);
5042 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5046 gas_assert (mips_opts
.micromips
);
5047 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5051 INSERT_OPERAND (mips_opts
.micromips
,
5052 3BITPOS
, insn
, va_arg (args
, unsigned int));
5056 INSERT_OPERAND (mips_opts
.micromips
,
5057 OFFSET12
, insn
, va_arg (args
, unsigned long));
5061 gas_assert (mips_opts
.micromips
);
5062 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5065 case 'm': /* Opcode extension character. */
5066 gas_assert (mips_opts
.micromips
);
5070 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5074 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5078 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5092 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5094 append_insn (&insn
, ep
, r
, TRUE
);
5098 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5101 struct mips_opcode
*mo
;
5102 struct mips_cl_insn insn
;
5103 bfd_reloc_code_real_type r
[3]
5104 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5106 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5108 gas_assert (strcmp (name
, mo
->name
) == 0);
5110 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5113 gas_assert (mo
->name
);
5114 gas_assert (strcmp (name
, mo
->name
) == 0);
5117 create_insn (&insn
, mo
);
5135 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5140 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5144 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5148 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5158 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5165 regno
= va_arg (*args
, int);
5166 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5167 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5188 gas_assert (ep
!= NULL
);
5190 if (ep
->X_op
!= O_constant
)
5191 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5194 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
5195 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
5198 *r
= BFD_RELOC_UNUSED
;
5204 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5211 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5213 append_insn (&insn
, ep
, r
, TRUE
);
5217 * Sign-extend 32-bit mode constants that have bit 31 set and all
5218 * higher bits unset.
5221 normalize_constant_expr (expressionS
*ex
)
5223 if (ex
->X_op
== O_constant
5224 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5225 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5230 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5231 * all higher bits unset.
5234 normalize_address_expr (expressionS
*ex
)
5236 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5237 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5238 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5239 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5244 * Generate a "jalr" instruction with a relocation hint to the called
5245 * function. This occurs in NewABI PIC code.
5248 macro_build_jalr (expressionS
*ep
, int cprestore
)
5250 static const bfd_reloc_code_real_type jalr_relocs
[2]
5251 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5252 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5256 if (MIPS_JALR_HINT_P (ep
))
5261 if (mips_opts
.micromips
)
5263 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5264 if (MIPS_JALR_HINT_P (ep
))
5265 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5267 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5270 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5271 if (MIPS_JALR_HINT_P (ep
))
5272 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5276 * Generate a "lui" instruction.
5279 macro_build_lui (expressionS
*ep
, int regnum
)
5281 gas_assert (! mips_opts
.mips16
);
5283 if (ep
->X_op
!= O_constant
)
5285 gas_assert (ep
->X_op
== O_symbol
);
5286 /* _gp_disp is a special case, used from s_cpload.
5287 __gnu_local_gp is used if mips_no_shared. */
5288 gas_assert (mips_pic
== NO_PIC
5290 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5291 || (! mips_in_shared
5292 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5293 "__gnu_local_gp") == 0));
5296 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5299 /* Generate a sequence of instructions to do a load or store from a constant
5300 offset off of a base register (breg) into/from a target register (treg),
5301 using AT if necessary. */
5303 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5304 int treg
, int breg
, int dbl
)
5306 gas_assert (ep
->X_op
== O_constant
);
5308 /* Sign-extending 32-bit constants makes their handling easier. */
5310 normalize_constant_expr (ep
);
5312 /* Right now, this routine can only handle signed 32-bit constants. */
5313 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5314 as_warn (_("operand overflow"));
5316 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5318 /* Signed 16-bit offset will fit in the op. Easy! */
5319 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5323 /* 32-bit offset, need multiple instructions and AT, like:
5324 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5325 addu $tempreg,$tempreg,$breg
5326 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5327 to handle the complete offset. */
5328 macro_build_lui (ep
, AT
);
5329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5330 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5333 as_bad (_("Macro used $at after \".set noat\""));
5338 * Generates code to set the $at register to true (one)
5339 * if reg is less than the immediate expression.
5342 set_at (int reg
, int unsignedp
)
5344 if (imm_expr
.X_op
== O_constant
5345 && imm_expr
.X_add_number
>= -0x8000
5346 && imm_expr
.X_add_number
< 0x8000)
5347 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5348 AT
, reg
, BFD_RELOC_LO16
);
5351 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5352 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5356 /* Warn if an expression is not a constant. */
5359 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5361 if (ex
->X_op
== O_big
)
5362 as_bad (_("unsupported large constant"));
5363 else if (ex
->X_op
!= O_constant
)
5364 as_bad (_("Instruction %s requires absolute expression"),
5367 if (HAVE_32BIT_GPRS
)
5368 normalize_constant_expr (ex
);
5371 /* Count the leading zeroes by performing a binary chop. This is a
5372 bulky bit of source, but performance is a LOT better for the
5373 majority of values than a simple loop to count the bits:
5374 for (lcnt = 0; (lcnt < 32); lcnt++)
5375 if ((v) & (1 << (31 - lcnt)))
5377 However it is not code size friendly, and the gain will drop a bit
5378 on certain cached systems.
5380 #define COUNT_TOP_ZEROES(v) \
5381 (((v) & ~0xffff) == 0 \
5382 ? ((v) & ~0xff) == 0 \
5383 ? ((v) & ~0xf) == 0 \
5384 ? ((v) & ~0x3) == 0 \
5385 ? ((v) & ~0x1) == 0 \
5390 : ((v) & ~0x7) == 0 \
5393 : ((v) & ~0x3f) == 0 \
5394 ? ((v) & ~0x1f) == 0 \
5397 : ((v) & ~0x7f) == 0 \
5400 : ((v) & ~0xfff) == 0 \
5401 ? ((v) & ~0x3ff) == 0 \
5402 ? ((v) & ~0x1ff) == 0 \
5405 : ((v) & ~0x7ff) == 0 \
5408 : ((v) & ~0x3fff) == 0 \
5409 ? ((v) & ~0x1fff) == 0 \
5412 : ((v) & ~0x7fff) == 0 \
5415 : ((v) & ~0xffffff) == 0 \
5416 ? ((v) & ~0xfffff) == 0 \
5417 ? ((v) & ~0x3ffff) == 0 \
5418 ? ((v) & ~0x1ffff) == 0 \
5421 : ((v) & ~0x7ffff) == 0 \
5424 : ((v) & ~0x3fffff) == 0 \
5425 ? ((v) & ~0x1fffff) == 0 \
5428 : ((v) & ~0x7fffff) == 0 \
5431 : ((v) & ~0xfffffff) == 0 \
5432 ? ((v) & ~0x3ffffff) == 0 \
5433 ? ((v) & ~0x1ffffff) == 0 \
5436 : ((v) & ~0x7ffffff) == 0 \
5439 : ((v) & ~0x3fffffff) == 0 \
5440 ? ((v) & ~0x1fffffff) == 0 \
5443 : ((v) & ~0x7fffffff) == 0 \
5448 * This routine generates the least number of instructions necessary to load
5449 * an absolute expression value into a register.
5452 load_register (int reg
, expressionS
*ep
, int dbl
)
5455 expressionS hi32
, lo32
;
5457 if (ep
->X_op
!= O_big
)
5459 gas_assert (ep
->X_op
== O_constant
);
5461 /* Sign-extending 32-bit constants makes their handling easier. */
5463 normalize_constant_expr (ep
);
5465 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5467 /* We can handle 16 bit signed values with an addiu to
5468 $zero. No need to ever use daddiu here, since $zero and
5469 the result are always correct in 32 bit mode. */
5470 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5473 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5475 /* We can handle 16 bit unsigned values with an ori to
5477 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5480 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5482 /* 32 bit values require an lui. */
5483 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5484 if ((ep
->X_add_number
& 0xffff) != 0)
5485 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5490 /* The value is larger than 32 bits. */
5492 if (!dbl
|| HAVE_32BIT_GPRS
)
5496 sprintf_vma (value
, ep
->X_add_number
);
5497 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5498 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5502 if (ep
->X_op
!= O_big
)
5505 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5506 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5507 hi32
.X_add_number
&= 0xffffffff;
5509 lo32
.X_add_number
&= 0xffffffff;
5513 gas_assert (ep
->X_add_number
> 2);
5514 if (ep
->X_add_number
== 3)
5515 generic_bignum
[3] = 0;
5516 else if (ep
->X_add_number
> 4)
5517 as_bad (_("Number larger than 64 bits"));
5518 lo32
.X_op
= O_constant
;
5519 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5520 hi32
.X_op
= O_constant
;
5521 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5524 if (hi32
.X_add_number
== 0)
5529 unsigned long hi
, lo
;
5531 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5533 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5535 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5538 if (lo32
.X_add_number
& 0x80000000)
5540 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5541 if (lo32
.X_add_number
& 0xffff)
5542 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5547 /* Check for 16bit shifted constant. We know that hi32 is
5548 non-zero, so start the mask on the first bit of the hi32
5553 unsigned long himask
, lomask
;
5557 himask
= 0xffff >> (32 - shift
);
5558 lomask
= (0xffff << shift
) & 0xffffffff;
5562 himask
= 0xffff << (shift
- 32);
5565 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5566 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5570 tmp
.X_op
= O_constant
;
5572 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5573 | (lo32
.X_add_number
>> shift
));
5575 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5576 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5577 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5578 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5583 while (shift
<= (64 - 16));
5585 /* Find the bit number of the lowest one bit, and store the
5586 shifted value in hi/lo. */
5587 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5588 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5592 while ((lo
& 1) == 0)
5597 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5603 while ((hi
& 1) == 0)
5612 /* Optimize if the shifted value is a (power of 2) - 1. */
5613 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5614 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5616 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5621 /* This instruction will set the register to be all
5623 tmp
.X_op
= O_constant
;
5624 tmp
.X_add_number
= (offsetT
) -1;
5625 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5629 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5630 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5632 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5633 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5638 /* Sign extend hi32 before calling load_register, because we can
5639 generally get better code when we load a sign extended value. */
5640 if ((hi32
.X_add_number
& 0x80000000) != 0)
5641 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5642 load_register (reg
, &hi32
, 0);
5645 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5649 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5657 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5659 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5660 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5666 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5670 mid16
.X_add_number
>>= 16;
5671 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5672 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5675 if ((lo32
.X_add_number
& 0xffff) != 0)
5676 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5680 load_delay_nop (void)
5682 if (!gpr_interlocks
)
5683 macro_build (NULL
, "nop", "");
5686 /* Load an address into a register. */
5689 load_address (int reg
, expressionS
*ep
, int *used_at
)
5691 if (ep
->X_op
!= O_constant
5692 && ep
->X_op
!= O_symbol
)
5694 as_bad (_("expression too complex"));
5695 ep
->X_op
= O_constant
;
5698 if (ep
->X_op
== O_constant
)
5700 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5704 if (mips_pic
== NO_PIC
)
5706 /* If this is a reference to a GP relative symbol, we want
5707 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5709 lui $reg,<sym> (BFD_RELOC_HI16_S)
5710 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5711 If we have an addend, we always use the latter form.
5713 With 64bit address space and a usable $at we want
5714 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5715 lui $at,<sym> (BFD_RELOC_HI16_S)
5716 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5717 daddiu $at,<sym> (BFD_RELOC_LO16)
5721 If $at is already in use, we use a path which is suboptimal
5722 on superscalar processors.
5723 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5724 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5726 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5728 daddiu $reg,<sym> (BFD_RELOC_LO16)
5730 For GP relative symbols in 64bit address space we can use
5731 the same sequence as in 32bit address space. */
5732 if (HAVE_64BIT_SYMBOLS
)
5734 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5735 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5737 relax_start (ep
->X_add_symbol
);
5738 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5739 mips_gp_register
, BFD_RELOC_GPREL16
);
5743 if (*used_at
== 0 && mips_opts
.at
)
5745 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5746 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5747 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5748 BFD_RELOC_MIPS_HIGHER
);
5749 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5750 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5751 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5756 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5757 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5758 BFD_RELOC_MIPS_HIGHER
);
5759 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5760 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5761 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5762 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5765 if (mips_relax
.sequence
)
5770 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5771 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5773 relax_start (ep
->X_add_symbol
);
5774 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5775 mips_gp_register
, BFD_RELOC_GPREL16
);
5778 macro_build_lui (ep
, reg
);
5779 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5780 reg
, reg
, BFD_RELOC_LO16
);
5781 if (mips_relax
.sequence
)
5785 else if (!mips_big_got
)
5789 /* If this is a reference to an external symbol, we want
5790 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5792 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5794 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5795 If there is a constant, it must be added in after.
5797 If we have NewABI, we want
5798 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5799 unless we're referencing a global symbol with a non-zero
5800 offset, in which case cst must be added separately. */
5803 if (ep
->X_add_number
)
5805 ex
.X_add_number
= ep
->X_add_number
;
5806 ep
->X_add_number
= 0;
5807 relax_start (ep
->X_add_symbol
);
5808 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5809 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5810 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5811 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5812 ex
.X_op
= O_constant
;
5813 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5814 reg
, reg
, BFD_RELOC_LO16
);
5815 ep
->X_add_number
= ex
.X_add_number
;
5818 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5819 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5820 if (mips_relax
.sequence
)
5825 ex
.X_add_number
= ep
->X_add_number
;
5826 ep
->X_add_number
= 0;
5827 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5828 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5830 relax_start (ep
->X_add_symbol
);
5832 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5836 if (ex
.X_add_number
!= 0)
5838 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5839 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5840 ex
.X_op
= O_constant
;
5841 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5842 reg
, reg
, BFD_RELOC_LO16
);
5846 else if (mips_big_got
)
5850 /* This is the large GOT case. If this is a reference to an
5851 external symbol, we want
5852 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5854 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5856 Otherwise, for a reference to a local symbol in old ABI, we want
5857 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5859 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5860 If there is a constant, it must be added in after.
5862 In the NewABI, for local symbols, with or without offsets, we want:
5863 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5864 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5868 ex
.X_add_number
= ep
->X_add_number
;
5869 ep
->X_add_number
= 0;
5870 relax_start (ep
->X_add_symbol
);
5871 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5872 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5873 reg
, reg
, mips_gp_register
);
5874 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5875 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5876 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5877 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5878 else if (ex
.X_add_number
)
5880 ex
.X_op
= O_constant
;
5881 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5885 ep
->X_add_number
= ex
.X_add_number
;
5887 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5888 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5889 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5890 BFD_RELOC_MIPS_GOT_OFST
);
5895 ex
.X_add_number
= ep
->X_add_number
;
5896 ep
->X_add_number
= 0;
5897 relax_start (ep
->X_add_symbol
);
5898 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5899 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5900 reg
, reg
, mips_gp_register
);
5901 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5902 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5904 if (reg_needs_delay (mips_gp_register
))
5906 /* We need a nop before loading from $gp. This special
5907 check is required because the lui which starts the main
5908 instruction stream does not refer to $gp, and so will not
5909 insert the nop which may be required. */
5910 macro_build (NULL
, "nop", "");
5912 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5913 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5915 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5919 if (ex
.X_add_number
!= 0)
5921 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5922 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5923 ex
.X_op
= O_constant
;
5924 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5932 if (!mips_opts
.at
&& *used_at
== 1)
5933 as_bad (_("Macro used $at after \".set noat\""));
5936 /* Move the contents of register SOURCE into register DEST. */
5939 move_register (int dest
, int source
)
5941 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5942 instruction specifically requires a 32-bit one. */
5943 if (mips_opts
.micromips
5944 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5945 macro_build (NULL
, "move", "mp,mj", dest
, source
);
5947 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
5951 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5952 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5953 The two alternatives are:
5955 Global symbol Local sybmol
5956 ------------- ------------
5957 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5959 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5961 load_got_offset emits the first instruction and add_got_offset
5962 emits the second for a 16-bit offset or add_got_offset_hilo emits
5963 a sequence to add a 32-bit offset using a scratch register. */
5966 load_got_offset (int dest
, expressionS
*local
)
5971 global
.X_add_number
= 0;
5973 relax_start (local
->X_add_symbol
);
5974 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5975 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5977 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5978 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5983 add_got_offset (int dest
, expressionS
*local
)
5987 global
.X_op
= O_constant
;
5988 global
.X_op_symbol
= NULL
;
5989 global
.X_add_symbol
= NULL
;
5990 global
.X_add_number
= local
->X_add_number
;
5992 relax_start (local
->X_add_symbol
);
5993 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
5994 dest
, dest
, BFD_RELOC_LO16
);
5996 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6001 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6004 int hold_mips_optimize
;
6006 global
.X_op
= O_constant
;
6007 global
.X_op_symbol
= NULL
;
6008 global
.X_add_symbol
= NULL
;
6009 global
.X_add_number
= local
->X_add_number
;
6011 relax_start (local
->X_add_symbol
);
6012 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6014 /* Set mips_optimize around the lui instruction to avoid
6015 inserting an unnecessary nop after the lw. */
6016 hold_mips_optimize
= mips_optimize
;
6018 macro_build_lui (&global
, tmp
);
6019 mips_optimize
= hold_mips_optimize
;
6020 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6023 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6026 /* Emit a sequence of instructions to emulate a branch likely operation.
6027 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6028 is its complementing branch with the original condition negated.
6029 CALL is set if the original branch specified the link operation.
6030 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6032 Code like this is produced in the noreorder mode:
6037 delay slot (executed only if branch taken)
6045 delay slot (executed only if branch taken)
6048 In the reorder mode the delay slot would be filled with a nop anyway,
6049 so code produced is simply:
6054 This function is used when producing code for the microMIPS ASE that
6055 does not implement branch likely instructions in hardware. */
6058 macro_build_branch_likely (const char *br
, const char *brneg
,
6059 int call
, expressionS
*ep
, const char *fmt
,
6060 unsigned int sreg
, unsigned int treg
)
6062 int noreorder
= mips_opts
.noreorder
;
6065 gas_assert (mips_opts
.micromips
);
6069 micromips_label_expr (&expr1
);
6070 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6071 macro_build (NULL
, "nop", "");
6072 macro_build (ep
, call
? "bal" : "b", "p");
6074 /* Set to true so that append_insn adds a label. */
6075 emit_branch_likely_macro
= TRUE
;
6079 macro_build (ep
, br
, fmt
, sreg
, treg
);
6080 macro_build (NULL
, "nop", "");
6085 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6086 the condition code tested. EP specifies the branch target. */
6089 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6116 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6119 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6120 the register tested. EP specifies the branch target. */
6123 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6125 const char *brneg
= NULL
;
6135 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6139 gas_assert (mips_opts
.micromips
);
6148 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6155 br
= mips_opts
.micromips
? "blez" : "blezl";
6162 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6166 gas_assert (mips_opts
.micromips
);
6174 if (mips_opts
.micromips
&& brneg
)
6175 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6177 macro_build (ep
, br
, "s,p", sreg
);
6180 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6181 TREG as the registers tested. EP specifies the branch target. */
6184 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6185 unsigned int sreg
, unsigned int treg
)
6187 const char *brneg
= NULL
;
6199 br
= mips_opts
.micromips
? "beq" : "beql";
6208 br
= mips_opts
.micromips
? "bne" : "bnel";
6214 if (mips_opts
.micromips
&& brneg
)
6215 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6217 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6222 * This routine implements the seemingly endless macro or synthesized
6223 * instructions and addressing modes in the mips assembly language. Many
6224 * of these macros are simple and are similar to each other. These could
6225 * probably be handled by some kind of table or grammar approach instead of
6226 * this verbose method. Others are not simple macros but are more like
6227 * optimizing code generation.
6228 * One interesting optimization is when several store macros appear
6229 * consecutively that would load AT with the upper half of the same address.
6230 * The ensuing load upper instructions are ommited. This implies some kind
6231 * of global optimization. We currently only optimize within a single macro.
6232 * For many of the load and store macros if the address is specified as a
6233 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6234 * first load register 'at' with zero and use it as the base register. The
6235 * mips assembler simply uses register $zero. Just one tiny optimization
6239 macro (struct mips_cl_insn
*ip
)
6241 unsigned int treg
, sreg
, dreg
, breg
;
6242 unsigned int tempreg
;
6245 expressionS label_expr
;
6264 bfd_reloc_code_real_type r
;
6265 int hold_mips_optimize
;
6267 gas_assert (! mips_opts
.mips16
);
6269 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6270 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6271 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6272 mask
= ip
->insn_mo
->mask
;
6274 label_expr
.X_op
= O_constant
;
6275 label_expr
.X_op_symbol
= NULL
;
6276 label_expr
.X_add_symbol
= NULL
;
6277 label_expr
.X_add_number
= 0;
6279 expr1
.X_op
= O_constant
;
6280 expr1
.X_op_symbol
= NULL
;
6281 expr1
.X_add_symbol
= NULL
;
6282 expr1
.X_add_number
= 1;
6297 if (mips_opts
.micromips
)
6298 micromips_label_expr (&label_expr
);
6300 label_expr
.X_add_number
= 8;
6301 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6303 macro_build (NULL
, "nop", "");
6305 move_register (dreg
, sreg
);
6306 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6307 if (mips_opts
.micromips
)
6308 micromips_add_label ();
6325 if (!mips_opts
.micromips
)
6327 if (imm_expr
.X_op
== O_constant
6328 && imm_expr
.X_add_number
>= -0x200
6329 && imm_expr
.X_add_number
< 0x200)
6331 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6340 if (imm_expr
.X_op
== O_constant
6341 && imm_expr
.X_add_number
>= -0x8000
6342 && imm_expr
.X_add_number
< 0x8000)
6344 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6349 load_register (AT
, &imm_expr
, dbl
);
6350 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6369 if (imm_expr
.X_op
== O_constant
6370 && imm_expr
.X_add_number
>= 0
6371 && imm_expr
.X_add_number
< 0x10000)
6373 if (mask
!= M_NOR_I
)
6374 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6377 macro_build (&imm_expr
, "ori", "t,r,i",
6378 treg
, sreg
, BFD_RELOC_LO16
);
6379 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6385 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6386 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6390 switch (imm_expr
.X_add_number
)
6393 macro_build (NULL
, "nop", "");
6396 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6400 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6401 (int) imm_expr
.X_add_number
);
6404 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6405 (unsigned long) imm_expr
.X_add_number
);
6414 gas_assert (mips_opts
.micromips
);
6415 macro_build_branch_ccl (mask
, &offset_expr
,
6416 EXTRACT_OPERAND (1, BCC
, *ip
));
6423 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6429 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6434 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6441 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6443 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6447 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6448 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6449 &offset_expr
, AT
, ZERO
);
6459 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6465 /* Check for > max integer. */
6466 maxnum
= 0x7fffffff;
6467 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6474 if (imm_expr
.X_op
== O_constant
6475 && imm_expr
.X_add_number
>= maxnum
6476 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6479 /* Result is always false. */
6481 macro_build (NULL
, "nop", "");
6483 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6486 if (imm_expr
.X_op
!= O_constant
)
6487 as_bad (_("Unsupported large constant"));
6488 ++imm_expr
.X_add_number
;
6492 if (mask
== M_BGEL_I
)
6494 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6496 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6497 &offset_expr
, sreg
);
6500 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6502 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6503 &offset_expr
, sreg
);
6506 maxnum
= 0x7fffffff;
6507 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6514 maxnum
= - maxnum
- 1;
6515 if (imm_expr
.X_op
== O_constant
6516 && imm_expr
.X_add_number
<= maxnum
6517 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6520 /* result is always true */
6521 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6522 macro_build (&offset_expr
, "b", "p");
6527 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6528 &offset_expr
, AT
, ZERO
);
6537 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6538 &offset_expr
, ZERO
, treg
);
6542 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6543 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6544 &offset_expr
, AT
, ZERO
);
6553 && imm_expr
.X_op
== O_constant
6554 && imm_expr
.X_add_number
== -1))
6556 if (imm_expr
.X_op
!= O_constant
)
6557 as_bad (_("Unsupported large constant"));
6558 ++imm_expr
.X_add_number
;
6562 if (mask
== M_BGEUL_I
)
6564 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6566 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6567 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6568 &offset_expr
, sreg
, ZERO
);
6573 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6574 &offset_expr
, AT
, ZERO
);
6582 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6584 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6588 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6589 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6590 &offset_expr
, AT
, ZERO
);
6598 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6599 &offset_expr
, sreg
, ZERO
);
6605 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6606 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6607 &offset_expr
, AT
, ZERO
);
6615 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6617 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6621 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6622 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6623 &offset_expr
, AT
, ZERO
);
6630 maxnum
= 0x7fffffff;
6631 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6638 if (imm_expr
.X_op
== O_constant
6639 && imm_expr
.X_add_number
>= maxnum
6640 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6642 if (imm_expr
.X_op
!= O_constant
)
6643 as_bad (_("Unsupported large constant"));
6644 ++imm_expr
.X_add_number
;
6648 if (mask
== M_BLTL_I
)
6650 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6651 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6652 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6653 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6658 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6659 &offset_expr
, AT
, ZERO
);
6667 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6668 &offset_expr
, sreg
, ZERO
);
6674 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6675 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6676 &offset_expr
, AT
, ZERO
);
6685 && imm_expr
.X_op
== O_constant
6686 && imm_expr
.X_add_number
== -1))
6688 if (imm_expr
.X_op
!= O_constant
)
6689 as_bad (_("Unsupported large constant"));
6690 ++imm_expr
.X_add_number
;
6694 if (mask
== M_BLTUL_I
)
6696 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6698 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6699 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6700 &offset_expr
, sreg
, ZERO
);
6705 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6706 &offset_expr
, AT
, ZERO
);
6714 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6716 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6720 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6721 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6722 &offset_expr
, AT
, ZERO
);
6732 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6733 &offset_expr
, ZERO
, treg
);
6737 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6738 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6739 &offset_expr
, AT
, ZERO
);
6745 /* Use unsigned arithmetic. */
6749 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6751 as_bad (_("Unsupported large constant"));
6756 pos
= imm_expr
.X_add_number
;
6757 size
= imm2_expr
.X_add_number
;
6762 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6765 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6767 as_bad (_("Improper extract size (%lu, position %lu)"),
6768 (unsigned long) size
, (unsigned long) pos
);
6772 if (size
<= 32 && pos
< 32)
6777 else if (size
<= 32)
6787 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6794 /* Use unsigned arithmetic. */
6798 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6800 as_bad (_("Unsupported large constant"));
6805 pos
= imm_expr
.X_add_number
;
6806 size
= imm2_expr
.X_add_number
;
6811 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6814 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6816 as_bad (_("Improper insert size (%lu, position %lu)"),
6817 (unsigned long) size
, (unsigned long) pos
);
6821 if (pos
< 32 && (pos
+ size
- 1) < 32)
6836 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6837 (int) (pos
+ size
- 1));
6853 as_warn (_("Divide by zero."));
6855 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6857 macro_build (NULL
, "break", BRK_FMT
, 7);
6864 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6865 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6869 if (mips_opts
.micromips
)
6870 micromips_label_expr (&label_expr
);
6872 label_expr
.X_add_number
= 8;
6873 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6874 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6875 macro_build (NULL
, "break", BRK_FMT
, 7);
6876 if (mips_opts
.micromips
)
6877 micromips_add_label ();
6879 expr1
.X_add_number
= -1;
6881 load_register (AT
, &expr1
, dbl
);
6882 if (mips_opts
.micromips
)
6883 micromips_label_expr (&label_expr
);
6885 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6886 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6889 expr1
.X_add_number
= 1;
6890 load_register (AT
, &expr1
, dbl
);
6891 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6895 expr1
.X_add_number
= 0x80000000;
6896 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6900 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6901 /* We want to close the noreorder block as soon as possible, so
6902 that later insns are available for delay slot filling. */
6907 if (mips_opts
.micromips
)
6908 micromips_label_expr (&label_expr
);
6910 label_expr
.X_add_number
= 8;
6911 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6912 macro_build (NULL
, "nop", "");
6914 /* We want to close the noreorder block as soon as possible, so
6915 that later insns are available for delay slot filling. */
6918 macro_build (NULL
, "break", BRK_FMT
, 6);
6920 if (mips_opts
.micromips
)
6921 micromips_add_label ();
6922 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
6961 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6963 as_warn (_("Divide by zero."));
6965 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6967 macro_build (NULL
, "break", BRK_FMT
, 7);
6970 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6972 if (strcmp (s2
, "mflo") == 0)
6973 move_register (dreg
, sreg
);
6975 move_register (dreg
, ZERO
);
6978 if (imm_expr
.X_op
== O_constant
6979 && imm_expr
.X_add_number
== -1
6980 && s
[strlen (s
) - 1] != 'u')
6982 if (strcmp (s2
, "mflo") == 0)
6984 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
6987 move_register (dreg
, ZERO
);
6992 load_register (AT
, &imm_expr
, dbl
);
6993 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
6994 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7016 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7017 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7018 /* We want to close the noreorder block as soon as possible, so
7019 that later insns are available for delay slot filling. */
7024 if (mips_opts
.micromips
)
7025 micromips_label_expr (&label_expr
);
7027 label_expr
.X_add_number
= 8;
7028 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7029 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7031 /* We want to close the noreorder block as soon as possible, so
7032 that later insns are available for delay slot filling. */
7034 macro_build (NULL
, "break", BRK_FMT
, 7);
7035 if (mips_opts
.micromips
)
7036 micromips_add_label ();
7038 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7050 /* Load the address of a symbol into a register. If breg is not
7051 zero, we then add a base register to it. */
7053 if (dbl
&& HAVE_32BIT_GPRS
)
7054 as_warn (_("dla used to load 32-bit register"));
7056 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7057 as_warn (_("la used to load 64-bit address"));
7059 if (offset_expr
.X_op
== O_constant
7060 && offset_expr
.X_add_number
>= -0x8000
7061 && offset_expr
.X_add_number
< 0x8000)
7063 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7064 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7068 if (mips_opts
.at
&& (treg
== breg
))
7078 if (offset_expr
.X_op
!= O_symbol
7079 && offset_expr
.X_op
!= O_constant
)
7081 as_bad (_("Expression too complex"));
7082 offset_expr
.X_op
= O_constant
;
7085 if (offset_expr
.X_op
== O_constant
)
7086 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7087 else if (mips_pic
== NO_PIC
)
7089 /* If this is a reference to a GP relative symbol, we want
7090 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7092 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7093 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7094 If we have a constant, we need two instructions anyhow,
7095 so we may as well always use the latter form.
7097 With 64bit address space and a usable $at we want
7098 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7099 lui $at,<sym> (BFD_RELOC_HI16_S)
7100 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7101 daddiu $at,<sym> (BFD_RELOC_LO16)
7103 daddu $tempreg,$tempreg,$at
7105 If $at is already in use, we use a path which is suboptimal
7106 on superscalar processors.
7107 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7108 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7110 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7112 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7114 For GP relative symbols in 64bit address space we can use
7115 the same sequence as in 32bit address space. */
7116 if (HAVE_64BIT_SYMBOLS
)
7118 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7119 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7121 relax_start (offset_expr
.X_add_symbol
);
7122 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7123 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7127 if (used_at
== 0 && mips_opts
.at
)
7129 macro_build (&offset_expr
, "lui", LUI_FMT
,
7130 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7131 macro_build (&offset_expr
, "lui", LUI_FMT
,
7132 AT
, BFD_RELOC_HI16_S
);
7133 macro_build (&offset_expr
, "daddiu", "t,r,j",
7134 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7135 macro_build (&offset_expr
, "daddiu", "t,r,j",
7136 AT
, AT
, BFD_RELOC_LO16
);
7137 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7138 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7143 macro_build (&offset_expr
, "lui", LUI_FMT
,
7144 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7145 macro_build (&offset_expr
, "daddiu", "t,r,j",
7146 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7147 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7148 macro_build (&offset_expr
, "daddiu", "t,r,j",
7149 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7150 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7151 macro_build (&offset_expr
, "daddiu", "t,r,j",
7152 tempreg
, tempreg
, BFD_RELOC_LO16
);
7155 if (mips_relax
.sequence
)
7160 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7161 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7163 relax_start (offset_expr
.X_add_symbol
);
7164 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7165 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7168 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7169 as_bad (_("Offset too large"));
7170 macro_build_lui (&offset_expr
, tempreg
);
7171 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7172 tempreg
, tempreg
, BFD_RELOC_LO16
);
7173 if (mips_relax
.sequence
)
7177 else if (!mips_big_got
&& !HAVE_NEWABI
)
7179 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7181 /* If this is a reference to an external symbol, and there
7182 is no constant, we want
7183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7184 or for lca or if tempreg is PIC_CALL_REG
7185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7186 For a local symbol, we want
7187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7189 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7191 If we have a small constant, and this is a reference to
7192 an external symbol, we want
7193 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7195 addiu $tempreg,$tempreg,<constant>
7196 For a local symbol, we want the same instruction
7197 sequence, but we output a BFD_RELOC_LO16 reloc on the
7200 If we have a large constant, and this is a reference to
7201 an external symbol, we want
7202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7203 lui $at,<hiconstant>
7204 addiu $at,$at,<loconstant>
7205 addu $tempreg,$tempreg,$at
7206 For a local symbol, we want the same instruction
7207 sequence, but we output a BFD_RELOC_LO16 reloc on the
7211 if (offset_expr
.X_add_number
== 0)
7213 if (mips_pic
== SVR4_PIC
7215 && (call
|| tempreg
== PIC_CALL_REG
))
7216 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7218 relax_start (offset_expr
.X_add_symbol
);
7219 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7220 lw_reloc_type
, mips_gp_register
);
7223 /* We're going to put in an addu instruction using
7224 tempreg, so we may as well insert the nop right
7229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7230 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7232 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7233 tempreg
, tempreg
, BFD_RELOC_LO16
);
7235 /* FIXME: If breg == 0, and the next instruction uses
7236 $tempreg, then if this variant case is used an extra
7237 nop will be generated. */
7239 else if (offset_expr
.X_add_number
>= -0x8000
7240 && offset_expr
.X_add_number
< 0x8000)
7242 load_got_offset (tempreg
, &offset_expr
);
7244 add_got_offset (tempreg
, &offset_expr
);
7248 expr1
.X_add_number
= offset_expr
.X_add_number
;
7249 offset_expr
.X_add_number
=
7250 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7251 load_got_offset (tempreg
, &offset_expr
);
7252 offset_expr
.X_add_number
= expr1
.X_add_number
;
7253 /* If we are going to add in a base register, and the
7254 target register and the base register are the same,
7255 then we are using AT as a temporary register. Since
7256 we want to load the constant into AT, we add our
7257 current AT (from the global offset table) and the
7258 register into the register now, and pretend we were
7259 not using a base register. */
7263 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7268 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7272 else if (!mips_big_got
&& HAVE_NEWABI
)
7274 int add_breg_early
= 0;
7276 /* If this is a reference to an external, and there is no
7277 constant, or local symbol (*), with or without a
7279 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7280 or for lca or if tempreg is PIC_CALL_REG
7281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7283 If we have a small constant, and this is a reference to
7284 an external symbol, we want
7285 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7286 addiu $tempreg,$tempreg,<constant>
7288 If we have a large constant, and this is a reference to
7289 an external symbol, we want
7290 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7291 lui $at,<hiconstant>
7292 addiu $at,$at,<loconstant>
7293 addu $tempreg,$tempreg,$at
7295 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7296 local symbols, even though it introduces an additional
7299 if (offset_expr
.X_add_number
)
7301 expr1
.X_add_number
= offset_expr
.X_add_number
;
7302 offset_expr
.X_add_number
= 0;
7304 relax_start (offset_expr
.X_add_symbol
);
7305 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7306 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7308 if (expr1
.X_add_number
>= -0x8000
7309 && expr1
.X_add_number
< 0x8000)
7311 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7312 tempreg
, tempreg
, BFD_RELOC_LO16
);
7314 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7316 /* If we are going to add in a base register, and the
7317 target register and the base register are the same,
7318 then we are using AT as a temporary register. Since
7319 we want to load the constant into AT, we add our
7320 current AT (from the global offset table) and the
7321 register into the register now, and pretend we were
7322 not using a base register. */
7327 gas_assert (tempreg
== AT
);
7328 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7334 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7335 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7341 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7344 offset_expr
.X_add_number
= expr1
.X_add_number
;
7346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7347 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7351 treg
, tempreg
, breg
);
7357 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7359 relax_start (offset_expr
.X_add_symbol
);
7360 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7361 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7363 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7364 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7369 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7370 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7373 else if (mips_big_got
&& !HAVE_NEWABI
)
7376 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7377 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7378 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7380 /* This is the large GOT case. If this is a reference to an
7381 external symbol, and there is no constant, we want
7382 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7383 addu $tempreg,$tempreg,$gp
7384 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7385 or for lca or if tempreg is PIC_CALL_REG
7386 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7387 addu $tempreg,$tempreg,$gp
7388 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7389 For a local symbol, we want
7390 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7392 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7394 If we have a small constant, and this is a reference to
7395 an external symbol, we want
7396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7397 addu $tempreg,$tempreg,$gp
7398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7400 addiu $tempreg,$tempreg,<constant>
7401 For a local symbol, we want
7402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7404 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7406 If we have a large constant, and this is a reference to
7407 an external symbol, we want
7408 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7409 addu $tempreg,$tempreg,$gp
7410 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7411 lui $at,<hiconstant>
7412 addiu $at,$at,<loconstant>
7413 addu $tempreg,$tempreg,$at
7414 For a local symbol, we want
7415 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7416 lui $at,<hiconstant>
7417 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7418 addu $tempreg,$tempreg,$at
7421 expr1
.X_add_number
= offset_expr
.X_add_number
;
7422 offset_expr
.X_add_number
= 0;
7423 relax_start (offset_expr
.X_add_symbol
);
7424 gpdelay
= reg_needs_delay (mips_gp_register
);
7425 if (expr1
.X_add_number
== 0 && breg
== 0
7426 && (call
|| tempreg
== PIC_CALL_REG
))
7428 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7429 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7431 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7433 tempreg
, tempreg
, mips_gp_register
);
7434 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7435 tempreg
, lw_reloc_type
, tempreg
);
7436 if (expr1
.X_add_number
== 0)
7440 /* We're going to put in an addu instruction using
7441 tempreg, so we may as well insert the nop right
7446 else if (expr1
.X_add_number
>= -0x8000
7447 && expr1
.X_add_number
< 0x8000)
7450 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7451 tempreg
, tempreg
, BFD_RELOC_LO16
);
7455 /* If we are going to add in a base register, and the
7456 target register and the base register are the same,
7457 then we are using AT as a temporary register. Since
7458 we want to load the constant into AT, we add our
7459 current AT (from the global offset table) and the
7460 register into the register now, and pretend we were
7461 not using a base register. */
7466 gas_assert (tempreg
== AT
);
7468 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7473 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7474 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7478 offset_expr
.X_add_number
=
7479 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7484 /* This is needed because this instruction uses $gp, but
7485 the first instruction on the main stream does not. */
7486 macro_build (NULL
, "nop", "");
7489 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7490 local_reloc_type
, mips_gp_register
);
7491 if (expr1
.X_add_number
>= -0x8000
7492 && expr1
.X_add_number
< 0x8000)
7495 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7496 tempreg
, tempreg
, BFD_RELOC_LO16
);
7497 /* FIXME: If add_number is 0, and there was no base
7498 register, the external symbol case ended with a load,
7499 so if the symbol turns out to not be external, and
7500 the next instruction uses tempreg, an unnecessary nop
7501 will be inserted. */
7507 /* We must add in the base register now, as in the
7508 external symbol case. */
7509 gas_assert (tempreg
== AT
);
7511 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7514 /* We set breg to 0 because we have arranged to add
7515 it in in both cases. */
7519 macro_build_lui (&expr1
, AT
);
7520 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7521 AT
, AT
, BFD_RELOC_LO16
);
7522 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7523 tempreg
, tempreg
, AT
);
7528 else if (mips_big_got
&& HAVE_NEWABI
)
7530 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7531 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7532 int add_breg_early
= 0;
7534 /* This is the large GOT case. If this is a reference to an
7535 external symbol, and there is no constant, we want
7536 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7537 add $tempreg,$tempreg,$gp
7538 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7539 or for lca or if tempreg is PIC_CALL_REG
7540 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7541 add $tempreg,$tempreg,$gp
7542 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7544 If we have a small constant, and this is a reference to
7545 an external symbol, we want
7546 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7547 add $tempreg,$tempreg,$gp
7548 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7549 addi $tempreg,$tempreg,<constant>
7551 If we have a large constant, and this is a reference to
7552 an external symbol, we want
7553 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7554 addu $tempreg,$tempreg,$gp
7555 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7556 lui $at,<hiconstant>
7557 addi $at,$at,<loconstant>
7558 add $tempreg,$tempreg,$at
7560 If we have NewABI, and we know it's a local symbol, we want
7561 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7562 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7563 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7565 relax_start (offset_expr
.X_add_symbol
);
7567 expr1
.X_add_number
= offset_expr
.X_add_number
;
7568 offset_expr
.X_add_number
= 0;
7570 if (expr1
.X_add_number
== 0 && breg
== 0
7571 && (call
|| tempreg
== PIC_CALL_REG
))
7573 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7574 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7576 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7578 tempreg
, tempreg
, mips_gp_register
);
7579 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7580 tempreg
, lw_reloc_type
, tempreg
);
7582 if (expr1
.X_add_number
== 0)
7584 else if (expr1
.X_add_number
>= -0x8000
7585 && expr1
.X_add_number
< 0x8000)
7587 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7588 tempreg
, tempreg
, BFD_RELOC_LO16
);
7590 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7592 /* If we are going to add in a base register, and the
7593 target register and the base register are the same,
7594 then we are using AT as a temporary register. Since
7595 we want to load the constant into AT, we add our
7596 current AT (from the global offset table) and the
7597 register into the register now, and pretend we were
7598 not using a base register. */
7603 gas_assert (tempreg
== AT
);
7604 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7610 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7611 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7616 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7619 offset_expr
.X_add_number
= expr1
.X_add_number
;
7620 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7621 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7622 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7623 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7627 treg
, tempreg
, breg
);
7637 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7641 gas_assert (!mips_opts
.micromips
);
7643 unsigned long temp
= (treg
<< 16) | (0x01);
7644 macro_build (NULL
, "c2", "C", temp
);
7649 gas_assert (!mips_opts
.micromips
);
7651 unsigned long temp
= (0x02);
7652 macro_build (NULL
, "c2", "C", temp
);
7657 gas_assert (!mips_opts
.micromips
);
7659 unsigned long temp
= (treg
<< 16) | (0x02);
7660 macro_build (NULL
, "c2", "C", temp
);
7665 gas_assert (!mips_opts
.micromips
);
7666 macro_build (NULL
, "c2", "C", 3);
7670 gas_assert (!mips_opts
.micromips
);
7672 unsigned long temp
= (treg
<< 16) | 0x03;
7673 macro_build (NULL
, "c2", "C", temp
);
7678 /* The j instruction may not be used in PIC code, since it
7679 requires an absolute address. We convert it to a b
7681 if (mips_pic
== NO_PIC
)
7682 macro_build (&offset_expr
, "j", "a");
7684 macro_build (&offset_expr
, "b", "p");
7687 /* The jal instructions must be handled as macros because when
7688 generating PIC code they expand to multi-instruction
7689 sequences. Normally they are simple instructions. */
7694 gas_assert (mips_opts
.micromips
);
7702 if (mips_pic
== NO_PIC
)
7704 s
= jals
? "jalrs" : "jalr";
7705 if (mips_opts
.micromips
&& dreg
== RA
)
7706 macro_build (NULL
, s
, "mj", sreg
);
7708 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7712 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7713 && mips_cprestore_offset
>= 0);
7715 if (sreg
!= PIC_CALL_REG
)
7716 as_warn (_("MIPS PIC call to register other than $25"));
7718 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7719 ? "jalrs" : "jalr");
7720 if (mips_opts
.micromips
&& dreg
== RA
)
7721 macro_build (NULL
, s
, "mj", sreg
);
7723 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7724 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7726 if (mips_cprestore_offset
< 0)
7727 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7730 if (!mips_frame_reg_valid
)
7732 as_warn (_("No .frame pseudo-op used in PIC code"));
7733 /* Quiet this warning. */
7734 mips_frame_reg_valid
= 1;
7736 if (!mips_cprestore_valid
)
7738 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7739 /* Quiet this warning. */
7740 mips_cprestore_valid
= 1;
7742 if (mips_opts
.noreorder
)
7743 macro_build (NULL
, "nop", "");
7744 expr1
.X_add_number
= mips_cprestore_offset
;
7745 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7748 HAVE_64BIT_ADDRESSES
);
7756 gas_assert (mips_opts
.micromips
);
7760 if (mips_pic
== NO_PIC
)
7761 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7762 else if (mips_pic
== SVR4_PIC
)
7764 /* If this is a reference to an external symbol, and we are
7765 using a small GOT, we want
7766 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7770 lw $gp,cprestore($sp)
7771 The cprestore value is set using the .cprestore
7772 pseudo-op. If we are using a big GOT, we want
7773 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7775 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7779 lw $gp,cprestore($sp)
7780 If the symbol is not external, we want
7781 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7783 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7786 lw $gp,cprestore($sp)
7788 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7789 sequences above, minus nops, unless the symbol is local,
7790 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7796 relax_start (offset_expr
.X_add_symbol
);
7797 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7798 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7801 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7802 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7808 relax_start (offset_expr
.X_add_symbol
);
7809 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7810 BFD_RELOC_MIPS_CALL_HI16
);
7811 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7812 PIC_CALL_REG
, mips_gp_register
);
7813 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7814 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7817 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7818 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7820 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7821 PIC_CALL_REG
, PIC_CALL_REG
,
7822 BFD_RELOC_MIPS_GOT_OFST
);
7826 macro_build_jalr (&offset_expr
, 0);
7830 relax_start (offset_expr
.X_add_symbol
);
7833 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7834 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7843 gpdelay
= reg_needs_delay (mips_gp_register
);
7844 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7845 BFD_RELOC_MIPS_CALL_HI16
);
7846 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7847 PIC_CALL_REG
, mips_gp_register
);
7848 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7849 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7854 macro_build (NULL
, "nop", "");
7856 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7857 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7860 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7861 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7863 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7865 if (mips_cprestore_offset
< 0)
7866 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7869 if (!mips_frame_reg_valid
)
7871 as_warn (_("No .frame pseudo-op used in PIC code"));
7872 /* Quiet this warning. */
7873 mips_frame_reg_valid
= 1;
7875 if (!mips_cprestore_valid
)
7877 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7878 /* Quiet this warning. */
7879 mips_cprestore_valid
= 1;
7881 if (mips_opts
.noreorder
)
7882 macro_build (NULL
, "nop", "");
7883 expr1
.X_add_number
= mips_cprestore_offset
;
7884 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7887 HAVE_64BIT_ADDRESSES
);
7891 else if (mips_pic
== VXWORKS_PIC
)
7892 as_bad (_("Non-PIC jump used in PIC library"));
7902 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7910 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7941 gas_assert (!mips_opts
.micromips
);
7944 /* Itbl support may require additional care here. */
7951 /* Itbl support may require additional care here. */
7959 off12
= mips_opts
.micromips
;
7960 /* Itbl support may require additional care here. */
7965 gas_assert (!mips_opts
.micromips
);
7968 /* Itbl support may require additional care here. */
7976 off12
= mips_opts
.micromips
;
7983 off12
= mips_opts
.micromips
;
7989 /* Itbl support may require additional care here. */
7997 off12
= mips_opts
.micromips
;
7998 /* Itbl support may require additional care here. */
8005 /* Itbl support may require additional care here. */
8013 off12
= mips_opts
.micromips
;
8020 off12
= mips_opts
.micromips
;
8027 off12
= mips_opts
.micromips
;
8034 off12
= mips_opts
.micromips
;
8041 off12
= mips_opts
.micromips
;
8046 gas_assert (mips_opts
.micromips
);
8055 gas_assert (mips_opts
.micromips
);
8064 gas_assert (mips_opts
.micromips
);
8072 gas_assert (mips_opts
.micromips
);
8079 if (breg
== treg
+ lp
)
8082 tempreg
= treg
+ lp
;
8102 gas_assert (!mips_opts
.micromips
);
8105 /* Itbl support may require additional care here. */
8112 /* Itbl support may require additional care here. */
8120 off12
= mips_opts
.micromips
;
8121 /* Itbl support may require additional care here. */
8126 gas_assert (!mips_opts
.micromips
);
8129 /* Itbl support may require additional care here. */
8137 off12
= mips_opts
.micromips
;
8144 off12
= mips_opts
.micromips
;
8151 off12
= mips_opts
.micromips
;
8158 off12
= mips_opts
.micromips
;
8164 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8165 off12
= mips_opts
.micromips
;
8171 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8172 off12
= mips_opts
.micromips
;
8179 /* Itbl support may require additional care here. */
8186 off12
= mips_opts
.micromips
;
8187 /* Itbl support may require additional care here. */
8192 gas_assert (!mips_opts
.micromips
);
8195 /* Itbl support may require additional care here. */
8203 off12
= mips_opts
.micromips
;
8210 off12
= mips_opts
.micromips
;
8215 gas_assert (mips_opts
.micromips
);
8223 gas_assert (mips_opts
.micromips
);
8231 gas_assert (mips_opts
.micromips
);
8239 gas_assert (mips_opts
.micromips
);
8248 if (offset_expr
.X_op
!= O_constant
8249 && offset_expr
.X_op
!= O_symbol
)
8251 as_bad (_("Expression too complex"));
8252 offset_expr
.X_op
= O_constant
;
8255 if (HAVE_32BIT_ADDRESSES
8256 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8260 sprintf_vma (value
, offset_expr
.X_add_number
);
8261 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8264 /* A constant expression in PIC code can be handled just as it
8265 is in non PIC code. */
8266 if (offset_expr
.X_op
== O_constant
)
8270 expr1
.X_add_number
= offset_expr
.X_add_number
;
8271 normalize_address_expr (&expr1
);
8272 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8274 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8275 & ~(bfd_vma
) 0xffff);
8278 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8280 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8281 & ~(bfd_vma
) 0xfff);
8286 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8288 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8289 tempreg
, tempreg
, breg
);
8294 if (offset_expr
.X_add_number
== 0)
8297 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8298 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8299 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8302 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8304 macro_build (NULL
, s
, fmt
,
8305 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8307 else if (off12
|| off0
)
8309 /* A 12-bit or 0-bit offset field is too narrow to be used
8310 for a low-part relocation, so load the whole address into
8311 the auxillary register. In the case of "A(b)" addresses,
8312 we first load absolute address "A" into the register and
8313 then add base register "b". In the case of "o(b)" addresses,
8314 we simply need to add 16-bit offset "o" to base register "b", and
8315 offset_reloc already contains the relocations associated
8319 load_address (tempreg
, &offset_expr
, &used_at
);
8321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8322 tempreg
, tempreg
, breg
);
8325 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8327 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8328 expr1
.X_add_number
= 0;
8330 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8332 macro_build (NULL
, s
, fmt
,
8333 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8335 else if (mips_pic
== NO_PIC
)
8337 /* If this is a reference to a GP relative symbol, and there
8338 is no base register, we want
8339 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8340 Otherwise, if there is no base register, we want
8341 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8342 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8343 If we have a constant, we need two instructions anyhow,
8344 so we always use the latter form.
8346 If we have a base register, and this is a reference to a
8347 GP relative symbol, we want
8348 addu $tempreg,$breg,$gp
8349 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8351 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8352 addu $tempreg,$tempreg,$breg
8353 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8354 With a constant we always use the latter case.
8356 With 64bit address space and no base register and $at usable,
8358 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8359 lui $at,<sym> (BFD_RELOC_HI16_S)
8360 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8363 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8364 If we have a base register, we want
8365 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8366 lui $at,<sym> (BFD_RELOC_HI16_S)
8367 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8371 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8373 Without $at we can't generate the optimal path for superscalar
8374 processors here since this would require two temporary registers.
8375 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8376 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8378 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8380 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8381 If we have a base register, we want
8382 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8383 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8385 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8387 daddu $tempreg,$tempreg,$breg
8388 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8390 For GP relative symbols in 64bit address space we can use
8391 the same sequence as in 32bit address space. */
8392 if (HAVE_64BIT_SYMBOLS
)
8394 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8395 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8397 relax_start (offset_expr
.X_add_symbol
);
8400 macro_build (&offset_expr
, s
, fmt
, treg
,
8401 BFD_RELOC_GPREL16
, mips_gp_register
);
8405 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8406 tempreg
, breg
, mips_gp_register
);
8407 macro_build (&offset_expr
, s
, fmt
, treg
,
8408 BFD_RELOC_GPREL16
, tempreg
);
8413 if (used_at
== 0 && mips_opts
.at
)
8415 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8416 BFD_RELOC_MIPS_HIGHEST
);
8417 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8419 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8420 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8422 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8423 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8424 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8425 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8431 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8432 BFD_RELOC_MIPS_HIGHEST
);
8433 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8434 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8435 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8436 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8437 tempreg
, BFD_RELOC_HI16_S
);
8438 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8440 macro_build (NULL
, "daddu", "d,v,t",
8441 tempreg
, tempreg
, breg
);
8442 macro_build (&offset_expr
, s
, fmt
, treg
,
8443 BFD_RELOC_LO16
, tempreg
);
8446 if (mips_relax
.sequence
)
8453 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8454 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8456 relax_start (offset_expr
.X_add_symbol
);
8457 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8461 macro_build_lui (&offset_expr
, tempreg
);
8462 macro_build (&offset_expr
, s
, fmt
, treg
,
8463 BFD_RELOC_LO16
, tempreg
);
8464 if (mips_relax
.sequence
)
8469 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8470 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8472 relax_start (offset_expr
.X_add_symbol
);
8473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8474 tempreg
, breg
, mips_gp_register
);
8475 macro_build (&offset_expr
, s
, fmt
, treg
,
8476 BFD_RELOC_GPREL16
, tempreg
);
8479 macro_build_lui (&offset_expr
, tempreg
);
8480 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8481 tempreg
, tempreg
, breg
);
8482 macro_build (&offset_expr
, s
, fmt
, treg
,
8483 BFD_RELOC_LO16
, tempreg
);
8484 if (mips_relax
.sequence
)
8488 else if (!mips_big_got
)
8490 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8492 /* If this is a reference to an external symbol, we want
8493 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8495 <op> $treg,0($tempreg)
8497 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8499 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8500 <op> $treg,0($tempreg)
8503 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8504 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8506 If there is a base register, we add it to $tempreg before
8507 the <op>. If there is a constant, we stick it in the
8508 <op> instruction. We don't handle constants larger than
8509 16 bits, because we have no way to load the upper 16 bits
8510 (actually, we could handle them for the subset of cases
8511 in which we are not using $at). */
8512 gas_assert (offset_expr
.X_op
== O_symbol
);
8515 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8516 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8518 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8519 tempreg
, tempreg
, breg
);
8520 macro_build (&offset_expr
, s
, fmt
, treg
,
8521 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8524 expr1
.X_add_number
= offset_expr
.X_add_number
;
8525 offset_expr
.X_add_number
= 0;
8526 if (expr1
.X_add_number
< -0x8000
8527 || expr1
.X_add_number
>= 0x8000)
8528 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8529 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8530 lw_reloc_type
, mips_gp_register
);
8532 relax_start (offset_expr
.X_add_symbol
);
8534 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8535 tempreg
, BFD_RELOC_LO16
);
8538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8539 tempreg
, tempreg
, breg
);
8540 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8542 else if (mips_big_got
&& !HAVE_NEWABI
)
8546 /* If this is a reference to an external symbol, we want
8547 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8548 addu $tempreg,$tempreg,$gp
8549 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8550 <op> $treg,0($tempreg)
8552 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8554 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8555 <op> $treg,0($tempreg)
8556 If there is a base register, we add it to $tempreg before
8557 the <op>. If there is a constant, we stick it in the
8558 <op> instruction. We don't handle constants larger than
8559 16 bits, because we have no way to load the upper 16 bits
8560 (actually, we could handle them for the subset of cases
8561 in which we are not using $at). */
8562 gas_assert (offset_expr
.X_op
== O_symbol
);
8563 expr1
.X_add_number
= offset_expr
.X_add_number
;
8564 offset_expr
.X_add_number
= 0;
8565 if (expr1
.X_add_number
< -0x8000
8566 || expr1
.X_add_number
>= 0x8000)
8567 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8568 gpdelay
= reg_needs_delay (mips_gp_register
);
8569 relax_start (offset_expr
.X_add_symbol
);
8570 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8571 BFD_RELOC_MIPS_GOT_HI16
);
8572 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8575 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8578 macro_build (NULL
, "nop", "");
8579 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8580 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8582 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8583 tempreg
, BFD_RELOC_LO16
);
8587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8588 tempreg
, tempreg
, breg
);
8589 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8591 else if (mips_big_got
&& HAVE_NEWABI
)
8593 /* If this is a reference to an external symbol, we want
8594 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8595 add $tempreg,$tempreg,$gp
8596 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8597 <op> $treg,<ofst>($tempreg)
8598 Otherwise, for local symbols, we want:
8599 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8600 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8601 gas_assert (offset_expr
.X_op
== O_symbol
);
8602 expr1
.X_add_number
= offset_expr
.X_add_number
;
8603 offset_expr
.X_add_number
= 0;
8604 if (expr1
.X_add_number
< -0x8000
8605 || expr1
.X_add_number
>= 0x8000)
8606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8607 relax_start (offset_expr
.X_add_symbol
);
8608 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8609 BFD_RELOC_MIPS_GOT_HI16
);
8610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8612 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8613 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8615 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8616 tempreg
, tempreg
, breg
);
8617 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8620 offset_expr
.X_add_number
= expr1
.X_add_number
;
8621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8622 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8624 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8625 tempreg
, tempreg
, breg
);
8626 macro_build (&offset_expr
, s
, fmt
, treg
,
8627 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8637 load_register (treg
, &imm_expr
, 0);
8641 load_register (treg
, &imm_expr
, 1);
8645 if (imm_expr
.X_op
== O_constant
)
8648 load_register (AT
, &imm_expr
, 0);
8649 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8654 gas_assert (offset_expr
.X_op
== O_symbol
8655 && strcmp (segment_name (S_GET_SEGMENT
8656 (offset_expr
.X_add_symbol
)),
8658 && offset_expr
.X_add_number
== 0);
8659 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8660 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8665 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8666 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8667 order 32 bits of the value and the low order 32 bits are either
8668 zero or in OFFSET_EXPR. */
8669 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8671 if (HAVE_64BIT_GPRS
)
8672 load_register (treg
, &imm_expr
, 1);
8677 if (target_big_endian
)
8689 load_register (hreg
, &imm_expr
, 0);
8692 if (offset_expr
.X_op
== O_absent
)
8693 move_register (lreg
, 0);
8696 gas_assert (offset_expr
.X_op
== O_constant
);
8697 load_register (lreg
, &offset_expr
, 0);
8704 /* We know that sym is in the .rdata section. First we get the
8705 upper 16 bits of the address. */
8706 if (mips_pic
== NO_PIC
)
8708 macro_build_lui (&offset_expr
, AT
);
8713 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8714 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8718 /* Now we load the register(s). */
8719 if (HAVE_64BIT_GPRS
)
8722 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8727 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8730 /* FIXME: How in the world do we deal with the possible
8732 offset_expr
.X_add_number
+= 4;
8733 macro_build (&offset_expr
, "lw", "t,o(b)",
8734 treg
+ 1, BFD_RELOC_LO16
, AT
);
8740 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8741 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8742 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8743 the value and the low order 32 bits are either zero or in
8745 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8748 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8749 if (HAVE_64BIT_FPRS
)
8751 gas_assert (HAVE_64BIT_GPRS
);
8752 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8756 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8757 if (offset_expr
.X_op
== O_absent
)
8758 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8761 gas_assert (offset_expr
.X_op
== O_constant
);
8762 load_register (AT
, &offset_expr
, 0);
8763 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8769 gas_assert (offset_expr
.X_op
== O_symbol
8770 && offset_expr
.X_add_number
== 0);
8771 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8772 if (strcmp (s
, ".lit8") == 0)
8774 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8776 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8777 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8780 breg
= mips_gp_register
;
8781 r
= BFD_RELOC_MIPS_LITERAL
;
8786 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8788 if (mips_pic
!= NO_PIC
)
8789 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8790 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8793 /* FIXME: This won't work for a 64 bit address. */
8794 macro_build_lui (&offset_expr
, AT
);
8797 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8799 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8800 treg
, BFD_RELOC_LO16
, AT
);
8809 /* Even on a big endian machine $fn comes before $fn+1. We have
8810 to adjust when loading from memory. */
8813 gas_assert (!mips_opts
.micromips
);
8814 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8815 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8816 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8817 /* FIXME: A possible overflow which I don't know how to deal
8819 offset_expr
.X_add_number
+= 4;
8820 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8821 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8825 gas_assert (!mips_opts
.micromips
);
8826 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8827 /* Even on a big endian machine $fn comes before $fn+1. We have
8828 to adjust when storing to memory. */
8829 macro_build (&offset_expr
, "swc1", "T,o(b)",
8830 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8831 offset_expr
.X_add_number
+= 4;
8832 macro_build (&offset_expr
, "swc1", "T,o(b)",
8833 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8837 gas_assert (!mips_opts
.micromips
);
8839 * The MIPS assembler seems to check for X_add_number not
8840 * being double aligned and generating:
8843 * addiu at,at,%lo(foo+1)
8846 * But, the resulting address is the same after relocation so why
8847 * generate the extra instruction?
8849 /* Itbl support may require additional care here. */
8852 if (mips_opts
.isa
!= ISA_MIPS1
)
8861 gas_assert (!mips_opts
.micromips
);
8862 /* Itbl support may require additional care here. */
8865 if (mips_opts
.isa
!= ISA_MIPS1
)
8875 if (HAVE_64BIT_GPRS
)
8885 if (HAVE_64BIT_GPRS
)
8893 if (offset_expr
.X_op
!= O_symbol
8894 && offset_expr
.X_op
!= O_constant
)
8896 as_bad (_("Expression too complex"));
8897 offset_expr
.X_op
= O_constant
;
8900 if (HAVE_32BIT_ADDRESSES
8901 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8905 sprintf_vma (value
, offset_expr
.X_add_number
);
8906 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8909 /* Even on a big endian machine $fn comes before $fn+1. We have
8910 to adjust when loading from memory. We set coproc if we must
8911 load $fn+1 first. */
8912 /* Itbl support may require additional care here. */
8913 if (!target_big_endian
)
8916 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8918 /* If this is a reference to a GP relative symbol, we want
8919 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8920 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8921 If we have a base register, we use this
8923 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8924 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8925 If this is not a GP relative symbol, we want
8926 lui $at,<sym> (BFD_RELOC_HI16_S)
8927 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8928 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8929 If there is a base register, we add it to $at after the
8930 lui instruction. If there is a constant, we always use
8932 if (offset_expr
.X_op
== O_symbol
8933 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8934 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8936 relax_start (offset_expr
.X_add_symbol
);
8939 tempreg
= mips_gp_register
;
8943 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8944 AT
, breg
, mips_gp_register
);
8949 /* Itbl support may require additional care here. */
8950 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8951 BFD_RELOC_GPREL16
, tempreg
);
8952 offset_expr
.X_add_number
+= 4;
8954 /* Set mips_optimize to 2 to avoid inserting an
8956 hold_mips_optimize
= mips_optimize
;
8958 /* Itbl support may require additional care here. */
8959 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8960 BFD_RELOC_GPREL16
, tempreg
);
8961 mips_optimize
= hold_mips_optimize
;
8965 offset_expr
.X_add_number
-= 4;
8968 macro_build_lui (&offset_expr
, AT
);
8970 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
8971 /* Itbl support may require additional care here. */
8972 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8973 BFD_RELOC_LO16
, AT
);
8974 /* FIXME: How do we handle overflow here? */
8975 offset_expr
.X_add_number
+= 4;
8976 /* Itbl support may require additional care here. */
8977 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8978 BFD_RELOC_LO16
, AT
);
8979 if (mips_relax
.sequence
)
8982 else if (!mips_big_got
)
8984 /* If this is a reference to an external symbol, we want
8985 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8990 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8992 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8993 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8994 If there is a base register we add it to $at before the
8995 lwc1 instructions. If there is a constant we include it
8996 in the lwc1 instructions. */
8998 expr1
.X_add_number
= offset_expr
.X_add_number
;
8999 if (expr1
.X_add_number
< -0x8000
9000 || expr1
.X_add_number
>= 0x8000 - 4)
9001 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9002 load_got_offset (AT
, &offset_expr
);
9005 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9007 /* Set mips_optimize to 2 to avoid inserting an undesired
9009 hold_mips_optimize
= mips_optimize
;
9012 /* Itbl support may require additional care here. */
9013 relax_start (offset_expr
.X_add_symbol
);
9014 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9015 BFD_RELOC_LO16
, AT
);
9016 expr1
.X_add_number
+= 4;
9017 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9018 BFD_RELOC_LO16
, AT
);
9020 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9021 BFD_RELOC_LO16
, AT
);
9022 offset_expr
.X_add_number
+= 4;
9023 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9024 BFD_RELOC_LO16
, AT
);
9027 mips_optimize
= hold_mips_optimize
;
9029 else if (mips_big_got
)
9033 /* If this is a reference to an external symbol, we want
9034 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9036 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9041 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9043 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9044 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9045 If there is a base register we add it to $at before the
9046 lwc1 instructions. If there is a constant we include it
9047 in the lwc1 instructions. */
9049 expr1
.X_add_number
= offset_expr
.X_add_number
;
9050 offset_expr
.X_add_number
= 0;
9051 if (expr1
.X_add_number
< -0x8000
9052 || expr1
.X_add_number
>= 0x8000 - 4)
9053 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9054 gpdelay
= reg_needs_delay (mips_gp_register
);
9055 relax_start (offset_expr
.X_add_symbol
);
9056 macro_build (&offset_expr
, "lui", LUI_FMT
,
9057 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9059 AT
, AT
, mips_gp_register
);
9060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9061 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9065 /* Itbl support may require additional care here. */
9066 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9067 BFD_RELOC_LO16
, AT
);
9068 expr1
.X_add_number
+= 4;
9070 /* Set mips_optimize to 2 to avoid inserting an undesired
9072 hold_mips_optimize
= mips_optimize
;
9074 /* Itbl support may require additional care here. */
9075 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9076 BFD_RELOC_LO16
, AT
);
9077 mips_optimize
= hold_mips_optimize
;
9078 expr1
.X_add_number
-= 4;
9081 offset_expr
.X_add_number
= expr1
.X_add_number
;
9083 macro_build (NULL
, "nop", "");
9084 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9085 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9088 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9089 /* Itbl support may require additional care here. */
9090 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9091 BFD_RELOC_LO16
, AT
);
9092 offset_expr
.X_add_number
+= 4;
9094 /* Set mips_optimize to 2 to avoid inserting an undesired
9096 hold_mips_optimize
= mips_optimize
;
9098 /* Itbl support may require additional care here. */
9099 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9100 BFD_RELOC_LO16
, AT
);
9101 mips_optimize
= hold_mips_optimize
;
9110 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9113 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9115 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9116 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9118 if (!HAVE_64BIT_GPRS
)
9120 offset_expr
.X_add_number
+= 4;
9121 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9122 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9143 /* New code added to support COPZ instructions.
9144 This code builds table entries out of the macros in mip_opcodes.
9145 R4000 uses interlocks to handle coproc delays.
9146 Other chips (like the R3000) require nops to be inserted for delays.
9148 FIXME: Currently, we require that the user handle delays.
9149 In order to fill delay slots for non-interlocked chips,
9150 we must have a way to specify delays based on the coprocessor.
9151 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9152 What are the side-effects of the cop instruction?
9153 What cache support might we have and what are its effects?
9154 Both coprocessor & memory require delays. how long???
9155 What registers are read/set/modified?
9157 If an itbl is provided to interpret cop instructions,
9158 this knowledge can be encoded in the itbl spec. */
9172 gas_assert (!mips_opts
.micromips
);
9173 /* For now we just do C (same as Cz). The parameter will be
9174 stored in insn_opcode by mips_ip. */
9175 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9179 move_register (dreg
, sreg
);
9185 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9186 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9192 /* The MIPS assembler some times generates shifts and adds. I'm
9193 not trying to be that fancy. GCC should do this for us
9196 load_register (AT
, &imm_expr
, dbl
);
9197 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9198 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9214 load_register (AT
, &imm_expr
, dbl
);
9215 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9216 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9217 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9218 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9220 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9223 if (mips_opts
.micromips
)
9224 micromips_label_expr (&label_expr
);
9226 label_expr
.X_add_number
= 8;
9227 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9228 macro_build (NULL
, "nop", "");
9229 macro_build (NULL
, "break", BRK_FMT
, 6);
9230 if (mips_opts
.micromips
)
9231 micromips_add_label ();
9234 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9250 load_register (AT
, &imm_expr
, dbl
);
9251 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9252 sreg
, imm
? AT
: treg
);
9253 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9254 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9256 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9259 if (mips_opts
.micromips
)
9260 micromips_label_expr (&label_expr
);
9262 label_expr
.X_add_number
= 8;
9263 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9264 macro_build (NULL
, "nop", "");
9265 macro_build (NULL
, "break", BRK_FMT
, 6);
9266 if (mips_opts
.micromips
)
9267 micromips_add_label ();
9273 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9284 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9285 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9289 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9290 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9291 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9292 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9296 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9307 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9308 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9312 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9313 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9314 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9315 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9324 if (imm_expr
.X_op
!= O_constant
)
9325 as_bad (_("Improper rotate count"));
9326 rot
= imm_expr
.X_add_number
& 0x3f;
9327 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9329 rot
= (64 - rot
) & 0x3f;
9331 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9333 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9338 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9341 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9342 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9345 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9346 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9347 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9355 if (imm_expr
.X_op
!= O_constant
)
9356 as_bad (_("Improper rotate count"));
9357 rot
= imm_expr
.X_add_number
& 0x1f;
9358 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9360 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9365 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9369 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9370 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9371 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9376 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9378 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9382 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9383 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9384 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9385 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9389 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9391 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9395 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9396 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9397 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9398 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9407 if (imm_expr
.X_op
!= O_constant
)
9408 as_bad (_("Improper rotate count"));
9409 rot
= imm_expr
.X_add_number
& 0x3f;
9410 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9413 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9415 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9420 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9423 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9424 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9427 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9428 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9429 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9437 if (imm_expr
.X_op
!= O_constant
)
9438 as_bad (_("Improper rotate count"));
9439 rot
= imm_expr
.X_add_number
& 0x1f;
9440 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9442 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9447 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9451 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9452 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9453 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9459 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9461 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9464 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9465 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9470 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9472 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9477 as_warn (_("Instruction %s: result is always false"),
9479 move_register (dreg
, 0);
9482 if (CPU_HAS_SEQ (mips_opts
.arch
)
9483 && -512 <= imm_expr
.X_add_number
9484 && imm_expr
.X_add_number
< 512)
9486 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9487 (int) imm_expr
.X_add_number
);
9490 if (imm_expr
.X_op
== O_constant
9491 && imm_expr
.X_add_number
>= 0
9492 && imm_expr
.X_add_number
< 0x10000)
9494 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9496 else if (imm_expr
.X_op
== O_constant
9497 && imm_expr
.X_add_number
> -0x8000
9498 && imm_expr
.X_add_number
< 0)
9500 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9501 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9502 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9504 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9507 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9508 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9513 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9514 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9517 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9520 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9526 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9527 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9530 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9532 if (imm_expr
.X_op
== O_constant
9533 && imm_expr
.X_add_number
>= -0x8000
9534 && imm_expr
.X_add_number
< 0x8000)
9536 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9537 dreg
, sreg
, BFD_RELOC_LO16
);
9541 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9542 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9546 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9549 case M_SGT
: /* sreg > treg <==> treg < sreg */
9555 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9558 case M_SGT_I
: /* sreg > I <==> I < sreg */
9565 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9566 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9569 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9575 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9576 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9579 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9586 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9587 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9588 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9592 if (imm_expr
.X_op
== O_constant
9593 && imm_expr
.X_add_number
>= -0x8000
9594 && imm_expr
.X_add_number
< 0x8000)
9596 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9600 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9601 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9605 if (imm_expr
.X_op
== O_constant
9606 && imm_expr
.X_add_number
>= -0x8000
9607 && imm_expr
.X_add_number
< 0x8000)
9609 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9614 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9615 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9620 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9622 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9625 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9626 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9631 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9633 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9638 as_warn (_("Instruction %s: result is always true"),
9640 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9641 dreg
, 0, BFD_RELOC_LO16
);
9644 if (CPU_HAS_SEQ (mips_opts
.arch
)
9645 && -512 <= imm_expr
.X_add_number
9646 && imm_expr
.X_add_number
< 512)
9648 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9649 (int) imm_expr
.X_add_number
);
9652 if (imm_expr
.X_op
== O_constant
9653 && imm_expr
.X_add_number
>= 0
9654 && imm_expr
.X_add_number
< 0x10000)
9656 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9658 else if (imm_expr
.X_op
== O_constant
9659 && imm_expr
.X_add_number
> -0x8000
9660 && imm_expr
.X_add_number
< 0)
9662 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9663 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9664 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9666 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9669 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9670 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9675 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9676 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9679 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9694 if (!mips_opts
.micromips
)
9696 if (imm_expr
.X_op
== O_constant
9697 && imm_expr
.X_add_number
> -0x200
9698 && imm_expr
.X_add_number
<= 0x200)
9700 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9709 if (imm_expr
.X_op
== O_constant
9710 && imm_expr
.X_add_number
> -0x8000
9711 && imm_expr
.X_add_number
<= 0x8000)
9713 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9714 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9719 load_register (AT
, &imm_expr
, dbl
);
9720 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9742 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9743 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9748 gas_assert (!mips_opts
.micromips
);
9749 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9751 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9752 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9755 * Is the double cfc1 instruction a bug in the mips assembler;
9756 * or is there a reason for it?
9759 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9760 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9761 macro_build (NULL
, "nop", "");
9762 expr1
.X_add_number
= 3;
9763 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9764 expr1
.X_add_number
= 2;
9765 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9766 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9767 macro_build (NULL
, "nop", "");
9768 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9770 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9771 macro_build (NULL
, "nop", "");
9794 off12
= mips_opts
.micromips
;
9802 off12
= mips_opts
.micromips
;
9818 off12
= mips_opts
.micromips
;
9827 off12
= mips_opts
.micromips
;
9832 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9833 as_bad (_("Operand overflow"));
9836 expr1
.X_add_number
= 0;
9841 load_address (tempreg
, ep
, &used_at
);
9843 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9844 tempreg
, tempreg
, breg
);
9850 && (offset_expr
.X_op
!= O_constant
9851 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9852 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9856 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9857 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9862 else if (!ust
&& treg
== breg
)
9873 if (!target_big_endian
)
9874 ep
->X_add_number
+= off
;
9876 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9878 macro_build (NULL
, s
, "t,~(b)",
9879 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9881 if (!target_big_endian
)
9882 ep
->X_add_number
-= off
;
9884 ep
->X_add_number
+= off
;
9886 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9888 macro_build (NULL
, s2
, "t,~(b)",
9889 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9891 /* If necessary, move the result in tempreg to the final destination. */
9892 if (!ust
&& treg
!= tempreg
)
9894 /* Protect second load's delay slot. */
9896 move_register (treg
, tempreg
);
9902 if (target_big_endian
== ust
)
9903 ep
->X_add_number
+= off
;
9904 tempreg
= ust
|| ab
? treg
: AT
;
9905 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9907 /* For halfword transfers we need a temporary register to shuffle
9908 bytes. Unfortunately for M_USH_A we have none available before
9909 the next store as AT holds the base address. We deal with this
9910 case by clobbering TREG and then restoring it as with ULH. */
9911 tempreg
= ust
== ab
? treg
: AT
;
9913 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9915 if (target_big_endian
== ust
)
9916 ep
->X_add_number
-= off
;
9918 ep
->X_add_number
+= off
;
9919 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9921 /* For M_USH_A re-retrieve the LSB. */
9924 if (target_big_endian
)
9925 ep
->X_add_number
+= off
;
9927 ep
->X_add_number
-= off
;
9928 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9930 /* For ULH and M_USH_A OR the LSB in. */
9933 tempreg
= !ab
? AT
: treg
;
9934 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
9935 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
9940 /* FIXME: Check if this is one of the itbl macros, since they
9941 are added dynamically. */
9942 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
9945 if (!mips_opts
.at
&& used_at
)
9946 as_bad (_("Macro used $at after \".set noat\""));
9949 /* Implement macros in mips16 mode. */
9952 mips16_macro (struct mips_cl_insn
*ip
)
9955 int xreg
, yreg
, zreg
, tmp
;
9958 const char *s
, *s2
, *s3
;
9960 mask
= ip
->insn_mo
->mask
;
9962 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
9963 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
9964 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
9966 expr1
.X_op
= O_constant
;
9967 expr1
.X_op_symbol
= NULL
;
9968 expr1
.X_add_symbol
= NULL
;
9969 expr1
.X_add_number
= 1;
9989 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
9990 expr1
.X_add_number
= 2;
9991 macro_build (&expr1
, "bnez", "x,p", yreg
);
9992 macro_build (NULL
, "break", "6", 7);
9994 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9995 since that causes an overflow. We should do that as well,
9996 but I don't see how to do the comparisons without a temporary
9999 macro_build (NULL
, s
, "x", zreg
);
10018 start_noreorder ();
10019 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10020 expr1
.X_add_number
= 2;
10021 macro_build (&expr1
, "bnez", "x,p", yreg
);
10022 macro_build (NULL
, "break", "6", 7);
10024 macro_build (NULL
, s2
, "x", zreg
);
10030 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10031 macro_build (NULL
, "mflo", "x", zreg
);
10039 if (imm_expr
.X_op
!= O_constant
)
10040 as_bad (_("Unsupported large constant"));
10041 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10042 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10046 if (imm_expr
.X_op
!= O_constant
)
10047 as_bad (_("Unsupported large constant"));
10048 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10049 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10053 if (imm_expr
.X_op
!= O_constant
)
10054 as_bad (_("Unsupported large constant"));
10055 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10056 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10078 goto do_reverse_branch
;
10082 goto do_reverse_branch
;
10094 goto do_reverse_branch
;
10105 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10106 macro_build (&offset_expr
, s2
, "p");
10133 goto do_addone_branch_i
;
10138 goto do_addone_branch_i
;
10153 goto do_addone_branch_i
;
10159 do_addone_branch_i
:
10160 if (imm_expr
.X_op
!= O_constant
)
10161 as_bad (_("Unsupported large constant"));
10162 ++imm_expr
.X_add_number
;
10165 macro_build (&imm_expr
, s
, s3
, xreg
);
10166 macro_build (&offset_expr
, s2
, "p");
10170 expr1
.X_add_number
= 0;
10171 macro_build (&expr1
, "slti", "x,8", yreg
);
10173 move_register (xreg
, yreg
);
10174 expr1
.X_add_number
= 2;
10175 macro_build (&expr1
, "bteqz", "p");
10176 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10180 /* For consistency checking, verify that all bits are specified either
10181 by the match/mask part of the instruction definition, or by the
10184 validate_mips_insn (const struct mips_opcode
*opc
)
10186 const char *p
= opc
->args
;
10188 unsigned long used_bits
= opc
->mask
;
10190 if ((used_bits
& opc
->match
) != opc
->match
)
10192 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10193 opc
->name
, opc
->args
);
10196 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10206 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10207 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10208 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10209 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10210 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10211 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10212 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10213 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10214 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10215 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10216 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10217 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10218 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10220 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10221 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10222 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10223 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10224 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10225 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10226 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10227 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10228 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10229 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10230 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10231 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10232 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10233 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10234 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10237 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10238 c
, opc
->name
, opc
->args
);
10242 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10243 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10245 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10246 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10247 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10248 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10250 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10251 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10253 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10254 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10256 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10257 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10258 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10259 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10260 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10261 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10262 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10263 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10264 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10265 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10266 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10267 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10268 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10269 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10270 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10271 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10272 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10274 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10275 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10276 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10277 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10279 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10280 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10281 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10282 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10283 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10284 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10285 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10286 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10287 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10290 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10291 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10292 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10293 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10294 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10297 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10298 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10299 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10300 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10301 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10302 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10303 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10304 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10305 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10306 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10307 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10308 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10309 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10310 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10311 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10312 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10313 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10314 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10315 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10316 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10318 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10319 c
, opc
->name
, opc
->args
);
10323 if (used_bits
!= 0xffffffff)
10325 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10326 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10332 /* For consistency checking, verify that the length implied matches the
10333 major opcode and that all bits are specified either by the match/mask
10334 part of the instruction definition, or by the operand list. */
10337 validate_micromips_insn (const struct mips_opcode
*opc
)
10339 unsigned long match
= opc
->match
;
10340 unsigned long mask
= opc
->mask
;
10341 const char *p
= opc
->args
;
10342 unsigned long insn_bits
;
10343 unsigned long used_bits
;
10344 unsigned long major
;
10345 unsigned int length
;
10349 if ((mask
& match
) != match
)
10351 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10352 opc
->name
, opc
->args
);
10355 length
= micromips_insn_length (opc
);
10356 if (length
!= 2 && length
!= 4)
10358 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10359 "%s %s"), length
, opc
->name
, opc
->args
);
10362 major
= match
>> (10 + 8 * (length
- 2));
10363 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10364 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10366 as_bad (_("Internal error: bad microMIPS opcode "
10367 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10371 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10372 insn_bits
= 1 << 4 * length
;
10373 insn_bits
<<= 4 * length
;
10376 #define USE_BITS(field) \
10377 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10388 case 'A': USE_BITS (EXTLSB
); break;
10389 case 'B': USE_BITS (INSMSB
); break;
10390 case 'C': USE_BITS (EXTMSBD
); break;
10391 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10392 case 'E': USE_BITS (EXTLSB
); break;
10393 case 'F': USE_BITS (INSMSB
); break;
10394 case 'G': USE_BITS (EXTMSBD
); break;
10395 case 'H': USE_BITS (EXTMSBD
); break;
10397 as_bad (_("Internal error: bad mips opcode "
10398 "(unknown extension operand type `%c%c'): %s %s"),
10399 e
, c
, opc
->name
, opc
->args
);
10407 case 'A': USE_BITS (IMMA
); break;
10408 case 'B': USE_BITS (IMMB
); break;
10409 case 'C': USE_BITS (IMMC
); break;
10410 case 'D': USE_BITS (IMMD
); break;
10411 case 'E': USE_BITS (IMME
); break;
10412 case 'F': USE_BITS (IMMF
); break;
10413 case 'G': USE_BITS (IMMG
); break;
10414 case 'H': USE_BITS (IMMH
); break;
10415 case 'I': USE_BITS (IMMI
); break;
10416 case 'J': USE_BITS (IMMJ
); break;
10417 case 'L': USE_BITS (IMML
); break;
10418 case 'M': USE_BITS (IMMM
); break;
10419 case 'N': USE_BITS (IMMN
); break;
10420 case 'O': USE_BITS (IMMO
); break;
10421 case 'P': USE_BITS (IMMP
); break;
10422 case 'Q': USE_BITS (IMMQ
); break;
10423 case 'U': USE_BITS (IMMU
); break;
10424 case 'W': USE_BITS (IMMW
); break;
10425 case 'X': USE_BITS (IMMX
); break;
10426 case 'Y': USE_BITS (IMMY
); break;
10429 case 'b': USE_BITS (MB
); break;
10430 case 'c': USE_BITS (MC
); break;
10431 case 'd': USE_BITS (MD
); break;
10432 case 'e': USE_BITS (ME
); break;
10433 case 'f': USE_BITS (MF
); break;
10434 case 'g': USE_BITS (MG
); break;
10435 case 'h': USE_BITS (MH
); break;
10436 case 'i': USE_BITS (MI
); break;
10437 case 'j': USE_BITS (MJ
); break;
10438 case 'l': USE_BITS (ML
); break;
10439 case 'm': USE_BITS (MM
); break;
10440 case 'n': USE_BITS (MN
); break;
10441 case 'p': USE_BITS (MP
); break;
10442 case 'q': USE_BITS (MQ
); break;
10450 as_bad (_("Internal error: bad mips opcode "
10451 "(unknown extension operand type `%c%c'): %s %s"),
10452 e
, c
, opc
->name
, opc
->args
);
10456 case '.': USE_BITS (OFFSET10
); break;
10457 case '1': USE_BITS (STYPE
); break;
10458 case '2': USE_BITS (BP
); break;
10459 case '3': USE_BITS (SA3
); break;
10460 case '4': USE_BITS (SA4
); break;
10461 case '5': USE_BITS (IMM8
); break;
10462 case '6': USE_BITS (RS
); break;
10463 case '7': USE_BITS (DSPACC
); break;
10464 case '8': USE_BITS (WRDSP
); break;
10465 case '0': USE_BITS (DSPSFT
); break;
10466 case '<': USE_BITS (SHAMT
); break;
10467 case '>': USE_BITS (SHAMT
); break;
10468 case '@': USE_BITS (IMM10
); break;
10469 case 'B': USE_BITS (CODE10
); break;
10470 case 'C': USE_BITS (COPZ
); break;
10471 case 'D': USE_BITS (FD
); break;
10472 case 'E': USE_BITS (RT
); break;
10473 case 'G': USE_BITS (RS
); break;
10474 case 'H': USE_BITS (SEL
); break;
10475 case 'K': USE_BITS (RS
); break;
10476 case 'M': USE_BITS (CCC
); break;
10477 case 'N': USE_BITS (BCC
); break;
10478 case 'R': USE_BITS (FR
); break;
10479 case 'S': USE_BITS (FS
); break;
10480 case 'T': USE_BITS (FT
); break;
10481 case 'V': USE_BITS (FS
); break;
10482 case '\\': USE_BITS (3BITPOS
); break;
10483 case '^': USE_BITS (RD
); break;
10484 case 'a': USE_BITS (TARGET
); break;
10485 case 'b': USE_BITS (RS
); break;
10486 case 'c': USE_BITS (CODE
); break;
10487 case 'd': USE_BITS (RD
); break;
10488 case 'h': USE_BITS (PREFX
); break;
10489 case 'i': USE_BITS (IMMEDIATE
); break;
10490 case 'j': USE_BITS (DELTA
); break;
10491 case 'k': USE_BITS (CACHE
); break;
10492 case 'n': USE_BITS (RT
); break;
10493 case 'o': USE_BITS (DELTA
); break;
10494 case 'p': USE_BITS (DELTA
); break;
10495 case 'q': USE_BITS (CODE2
); break;
10496 case 'r': USE_BITS (RS
); break;
10497 case 's': USE_BITS (RS
); break;
10498 case 't': USE_BITS (RT
); break;
10499 case 'u': USE_BITS (IMMEDIATE
); break;
10500 case 'v': USE_BITS (RS
); break;
10501 case 'w': USE_BITS (RT
); break;
10502 case 'y': USE_BITS (RS3
); break;
10504 case '|': USE_BITS (TRAP
); break;
10505 case '~': USE_BITS (OFFSET12
); break;
10507 as_bad (_("Internal error: bad microMIPS opcode "
10508 "(unknown operand type `%c'): %s %s"),
10509 c
, opc
->name
, opc
->args
);
10513 if (used_bits
!= insn_bits
)
10515 if (~used_bits
& insn_bits
)
10516 as_bad (_("Internal error: bad microMIPS opcode "
10517 "(bits 0x%lx undefined): %s %s"),
10518 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10519 if (used_bits
& ~insn_bits
)
10520 as_bad (_("Internal error: bad microMIPS opcode "
10521 "(bits 0x%lx defined): %s %s"),
10522 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10528 /* UDI immediates. */
10529 struct mips_immed
{
10531 unsigned int shift
;
10532 unsigned long mask
;
10536 static const struct mips_immed mips_immed
[] = {
10537 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10538 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10539 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10540 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10544 /* Check whether an odd floating-point register is allowed. */
10546 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10548 const char *s
= insn
->name
;
10550 if (insn
->pinfo
== INSN_MACRO
)
10551 /* Let a macro pass, we'll catch it later when it is expanded. */
10554 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10556 /* Allow odd registers for single-precision ops. */
10557 switch (insn
->pinfo
& (FP_S
| FP_D
))
10561 return 1; /* both single precision - ok */
10563 return 0; /* both double precision - fail */
10568 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10569 s
= strchr (insn
->name
, '.');
10571 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10572 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10575 /* Single-precision coprocessor loads and moves are OK too. */
10576 if ((insn
->pinfo
& FP_S
)
10577 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10578 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10584 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10585 taking bits from BIT up. */
10587 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10589 return (ep
->X_op
== O_constant
10590 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10591 && ep
->X_add_number
>= min
<< bit
10592 && ep
->X_add_number
< max
<< bit
);
10595 /* This routine assembles an instruction into its binary format. As a
10596 side effect, it sets one of the global variables imm_reloc or
10597 offset_reloc to the type of relocation to do if one of the operands
10598 is an address expression. */
10601 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10603 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10604 bfd_boolean need_delay_slot_ok
= TRUE
;
10605 struct mips_opcode
*firstinsn
= NULL
;
10606 const struct mips_opcode
*past
;
10607 struct hash_control
*hash
;
10611 struct mips_opcode
*insn
;
10613 unsigned int regno
;
10614 unsigned int lastregno
;
10615 unsigned int destregno
= 0;
10616 unsigned int lastpos
= 0;
10617 unsigned int limlo
, limhi
;
10619 offsetT min_range
, max_range
;
10623 unsigned int rtype
;
10629 if (mips_opts
.micromips
)
10631 hash
= micromips_op_hash
;
10632 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10637 past
= &mips_opcodes
[NUMOPCODES
];
10639 forced_insn_length
= 0;
10642 /* We first try to match an instruction up to a space or to the end. */
10643 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10646 /* Make a copy of the instruction so that we can fiddle with it. */
10647 name
= alloca (end
+ 1);
10648 memcpy (name
, str
, end
);
10653 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10655 if (insn
!= NULL
|| !mips_opts
.micromips
)
10657 if (forced_insn_length
)
10660 /* See if there's an instruction size override suffix,
10661 either `16' or `32', at the end of the mnemonic proper,
10662 that defines the operation, i.e. before the first `.'
10663 character if any. Strip it and retry. */
10664 dot
= strchr (name
, '.');
10665 opend
= dot
!= NULL
? dot
- name
: end
;
10668 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10669 forced_insn_length
= 2;
10670 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10671 forced_insn_length
= 4;
10674 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10678 insn_error
= _("Unrecognized opcode");
10682 /* For microMIPS instructions placed in a fixed-length branch delay slot
10683 we make up to two passes over the relevant fragment of the opcode
10684 table. First we try instructions that meet the delay slot's length
10685 requirement. If none matched, then we retry with the remaining ones
10686 and if one matches, then we use it and then issue an appropriate
10687 warning later on. */
10688 argsStart
= s
= str
+ end
;
10691 bfd_boolean delay_slot_ok
;
10692 bfd_boolean size_ok
;
10695 gas_assert (strcmp (insn
->name
, name
) == 0);
10697 ok
= is_opcode_valid (insn
);
10698 size_ok
= is_size_valid (insn
);
10699 delay_slot_ok
= is_delay_slot_valid (insn
);
10700 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10703 wrong_delay_slot_insns
= TRUE
;
10705 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10707 static char buf
[256];
10709 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10714 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10716 gas_assert (firstinsn
);
10717 need_delay_slot_ok
= FALSE
;
10727 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10728 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10729 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10731 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10732 8 * forced_insn_length
);
10738 create_insn (ip
, insn
);
10741 lastregno
= 0xffffffff;
10742 for (args
= insn
->args
;; ++args
)
10746 s
+= strspn (s
, " \t");
10750 case '\0': /* end of args */
10756 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10757 code) or 14 (for microMIPS code). */
10758 my_getExpression (&imm_expr
, s
);
10759 check_absolute_expr (ip
, &imm_expr
);
10760 if ((unsigned long) imm_expr
.X_add_number
!= 1
10761 && (unsigned long) imm_expr
.X_add_number
!= 3)
10763 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10764 (unsigned long) imm_expr
.X_add_number
);
10766 INSERT_OPERAND (mips_opts
.micromips
,
10767 BP
, *ip
, imm_expr
.X_add_number
);
10768 imm_expr
.X_op
= O_absent
;
10773 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10774 code) or 21 (for microMIPS code). */
10776 unsigned long mask
= (mips_opts
.micromips
10777 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10779 my_getExpression (&imm_expr
, s
);
10780 check_absolute_expr (ip
, &imm_expr
);
10781 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10782 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10783 mask
, (unsigned long) imm_expr
.X_add_number
);
10784 INSERT_OPERAND (mips_opts
.micromips
,
10785 SA3
, *ip
, imm_expr
.X_add_number
);
10786 imm_expr
.X_op
= O_absent
;
10792 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10793 code) or 21 (for microMIPS code). */
10795 unsigned long mask
= (mips_opts
.micromips
10796 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10798 my_getExpression (&imm_expr
, s
);
10799 check_absolute_expr (ip
, &imm_expr
);
10800 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10801 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10802 mask
, (unsigned long) imm_expr
.X_add_number
);
10803 INSERT_OPERAND (mips_opts
.micromips
,
10804 SA4
, *ip
, imm_expr
.X_add_number
);
10805 imm_expr
.X_op
= O_absent
;
10811 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10812 code) or 16 (for microMIPS code). */
10814 unsigned long mask
= (mips_opts
.micromips
10815 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
10817 my_getExpression (&imm_expr
, s
);
10818 check_absolute_expr (ip
, &imm_expr
);
10819 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10820 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10821 mask
, (unsigned long) imm_expr
.X_add_number
);
10822 INSERT_OPERAND (mips_opts
.micromips
,
10823 IMM8
, *ip
, imm_expr
.X_add_number
);
10824 imm_expr
.X_op
= O_absent
;
10830 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10831 code) or 21 (for microMIPS code). */
10833 unsigned long mask
= (mips_opts
.micromips
10834 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
10836 my_getExpression (&imm_expr
, s
);
10837 check_absolute_expr (ip
, &imm_expr
);
10838 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10839 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10840 mask
, (unsigned long) imm_expr
.X_add_number
);
10841 INSERT_OPERAND (mips_opts
.micromips
,
10842 RS
, *ip
, imm_expr
.X_add_number
);
10843 imm_expr
.X_op
= O_absent
;
10848 case '7': /* Four DSP accumulators in bits 11,12. */
10849 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10850 && s
[3] >= '0' && s
[3] <= '3')
10852 regno
= s
[3] - '0';
10854 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
10858 as_bad (_("Invalid dsp acc register"));
10862 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10863 code) or 14 (for microMIPS code). */
10865 unsigned long mask
= (mips_opts
.micromips
10866 ? MICROMIPSOP_MASK_WRDSP
10869 my_getExpression (&imm_expr
, s
);
10870 check_absolute_expr (ip
, &imm_expr
);
10871 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10872 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10873 mask
, (unsigned long) imm_expr
.X_add_number
);
10874 INSERT_OPERAND (mips_opts
.micromips
,
10875 WRDSP
, *ip
, imm_expr
.X_add_number
);
10876 imm_expr
.X_op
= O_absent
;
10881 case '9': /* Four DSP accumulators in bits 21,22. */
10882 gas_assert (!mips_opts
.micromips
);
10883 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10884 && s
[3] >= '0' && s
[3] <= '3')
10886 regno
= s
[3] - '0';
10888 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10892 as_bad (_("Invalid dsp acc register"));
10896 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10897 code) or 20 (for microMIPS code). */
10899 long mask
= (mips_opts
.micromips
10900 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
10902 my_getExpression (&imm_expr
, s
);
10903 check_absolute_expr (ip
, &imm_expr
);
10904 min_range
= -((mask
+ 1) >> 1);
10905 max_range
= ((mask
+ 1) >> 1) - 1;
10906 if (imm_expr
.X_add_number
< min_range
10907 || imm_expr
.X_add_number
> max_range
)
10908 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10909 (long) min_range
, (long) max_range
,
10910 (long) imm_expr
.X_add_number
);
10911 INSERT_OPERAND (mips_opts
.micromips
,
10912 DSPSFT
, *ip
, imm_expr
.X_add_number
);
10913 imm_expr
.X_op
= O_absent
;
10918 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10919 gas_assert (!mips_opts
.micromips
);
10920 my_getExpression (&imm_expr
, s
);
10921 check_absolute_expr (ip
, &imm_expr
);
10922 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10924 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10926 (unsigned long) imm_expr
.X_add_number
);
10928 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10929 imm_expr
.X_op
= O_absent
;
10933 case ':': /* DSP 7-bit signed immediate in bit 19. */
10934 gas_assert (!mips_opts
.micromips
);
10935 my_getExpression (&imm_expr
, s
);
10936 check_absolute_expr (ip
, &imm_expr
);
10937 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
10938 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
10939 if (imm_expr
.X_add_number
< min_range
||
10940 imm_expr
.X_add_number
> max_range
)
10942 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10943 (long) min_range
, (long) max_range
,
10944 (long) imm_expr
.X_add_number
);
10946 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
10947 imm_expr
.X_op
= O_absent
;
10951 case '@': /* DSP 10-bit signed immediate in bit 16. */
10953 long mask
= (mips_opts
.micromips
10954 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
10956 my_getExpression (&imm_expr
, s
);
10957 check_absolute_expr (ip
, &imm_expr
);
10958 min_range
= -((mask
+ 1) >> 1);
10959 max_range
= ((mask
+ 1) >> 1) - 1;
10960 if (imm_expr
.X_add_number
< min_range
10961 || imm_expr
.X_add_number
> max_range
)
10962 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10963 (long) min_range
, (long) max_range
,
10964 (long) imm_expr
.X_add_number
);
10965 INSERT_OPERAND (mips_opts
.micromips
,
10966 IMM10
, *ip
, imm_expr
.X_add_number
);
10967 imm_expr
.X_op
= O_absent
;
10972 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
10973 gas_assert (mips_opts
.micromips
);
10974 my_getExpression (&imm_expr
, s
);
10975 check_absolute_expr (ip
, &imm_expr
);
10976 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
10977 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10978 MICROMIPSOP_MASK_RD
,
10979 (unsigned long) imm_expr
.X_add_number
);
10980 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
10981 imm_expr
.X_op
= O_absent
;
10985 case '!': /* MT usermode flag bit. */
10986 gas_assert (!mips_opts
.micromips
);
10987 my_getExpression (&imm_expr
, s
);
10988 check_absolute_expr (ip
, &imm_expr
);
10989 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
10990 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10991 (unsigned long) imm_expr
.X_add_number
);
10992 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
10993 imm_expr
.X_op
= O_absent
;
10997 case '$': /* MT load high flag bit. */
10998 gas_assert (!mips_opts
.micromips
);
10999 my_getExpression (&imm_expr
, s
);
11000 check_absolute_expr (ip
, &imm_expr
);
11001 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11002 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11003 (unsigned long) imm_expr
.X_add_number
);
11004 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11005 imm_expr
.X_op
= O_absent
;
11009 case '*': /* Four DSP accumulators in bits 18,19. */
11010 gas_assert (!mips_opts
.micromips
);
11011 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11012 s
[3] >= '0' && s
[3] <= '3')
11014 regno
= s
[3] - '0';
11016 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11020 as_bad (_("Invalid dsp/smartmips acc register"));
11023 case '&': /* Four DSP accumulators in bits 13,14. */
11024 gas_assert (!mips_opts
.micromips
);
11025 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11026 s
[3] >= '0' && s
[3] <= '3')
11028 regno
= s
[3] - '0';
11030 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11034 as_bad (_("Invalid dsp/smartmips acc register"));
11037 case '\\': /* 3-bit bit position. */
11039 unsigned long mask
= (mips_opts
.micromips
11040 ? MICROMIPSOP_MASK_3BITPOS
11041 : OP_MASK_3BITPOS
);
11043 my_getExpression (&imm_expr
, s
);
11044 check_absolute_expr (ip
, &imm_expr
);
11045 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11046 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11048 mask
, (unsigned long) imm_expr
.X_add_number
);
11049 INSERT_OPERAND (mips_opts
.micromips
,
11050 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11051 imm_expr
.X_op
= O_absent
;
11065 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11069 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11073 gas_assert (!mips_opts
.micromips
);
11074 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11078 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11084 /* Handle optional base register.
11085 Either the base register is omitted or
11086 we must have a left paren. */
11087 /* This is dependent on the next operand specifier
11088 is a base register specification. */
11089 gas_assert (args
[1] == 'b'
11090 || (mips_opts
.micromips
11092 && (args
[2] == 'l' || args
[2] == 'n'
11093 || args
[2] == 's' || args
[2] == 'a')));
11094 if (*s
== '\0' && args
[1] == 'b')
11096 /* Fall through. */
11098 case ')': /* These must match exactly. */
11103 case '[': /* These must match exactly. */
11105 gas_assert (!mips_opts
.micromips
);
11110 case '+': /* Opcode extension character. */
11113 case '1': /* UDI immediates. */
11117 gas_assert (!mips_opts
.micromips
);
11119 const struct mips_immed
*imm
= mips_immed
;
11121 while (imm
->type
&& imm
->type
!= *args
)
11125 my_getExpression (&imm_expr
, s
);
11126 check_absolute_expr (ip
, &imm_expr
);
11127 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11129 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11130 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11131 (unsigned long) imm_expr
.X_add_number
,
11132 (unsigned long) imm_expr
.X_add_number
);
11133 imm_expr
.X_add_number
&= imm
->mask
;
11135 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11137 imm_expr
.X_op
= O_absent
;
11142 case 'A': /* ins/ext position, becomes LSB. */
11151 my_getExpression (&imm_expr
, s
);
11152 check_absolute_expr (ip
, &imm_expr
);
11153 if ((unsigned long) imm_expr
.X_add_number
< limlo
11154 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11156 as_bad (_("Improper position (%lu)"),
11157 (unsigned long) imm_expr
.X_add_number
);
11158 imm_expr
.X_add_number
= limlo
;
11160 lastpos
= imm_expr
.X_add_number
;
11161 INSERT_OPERAND (mips_opts
.micromips
,
11162 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11163 imm_expr
.X_op
= O_absent
;
11167 case 'B': /* ins size, becomes MSB. */
11176 my_getExpression (&imm_expr
, s
);
11177 check_absolute_expr (ip
, &imm_expr
);
11178 /* Check for negative input so that small negative numbers
11179 will not succeed incorrectly. The checks against
11180 (pos+size) transitively check "size" itself,
11181 assuming that "pos" is reasonable. */
11182 if ((long) imm_expr
.X_add_number
< 0
11183 || ((unsigned long) imm_expr
.X_add_number
11185 || ((unsigned long) imm_expr
.X_add_number
11186 + lastpos
) > limhi
)
11188 as_bad (_("Improper insert size (%lu, position %lu)"),
11189 (unsigned long) imm_expr
.X_add_number
,
11190 (unsigned long) lastpos
);
11191 imm_expr
.X_add_number
= limlo
- lastpos
;
11193 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11194 lastpos
+ imm_expr
.X_add_number
- 1);
11195 imm_expr
.X_op
= O_absent
;
11199 case 'C': /* ext size, becomes MSBD. */
11212 my_getExpression (&imm_expr
, s
);
11213 check_absolute_expr (ip
, &imm_expr
);
11214 /* Check for negative input so that small negative numbers
11215 will not succeed incorrectly. The checks against
11216 (pos+size) transitively check "size" itself,
11217 assuming that "pos" is reasonable. */
11218 if ((long) imm_expr
.X_add_number
< 0
11219 || ((unsigned long) imm_expr
.X_add_number
11221 || ((unsigned long) imm_expr
.X_add_number
11222 + lastpos
) > limhi
)
11224 as_bad (_("Improper extract size (%lu, position %lu)"),
11225 (unsigned long) imm_expr
.X_add_number
,
11226 (unsigned long) lastpos
);
11227 imm_expr
.X_add_number
= limlo
- lastpos
;
11229 INSERT_OPERAND (mips_opts
.micromips
,
11230 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11231 imm_expr
.X_op
= O_absent
;
11236 /* +D is for disassembly only; never match. */
11240 /* "+I" is like "I", except that imm2_expr is used. */
11241 my_getExpression (&imm2_expr
, s
);
11242 if (imm2_expr
.X_op
!= O_big
11243 && imm2_expr
.X_op
!= O_constant
)
11244 insn_error
= _("absolute expression required");
11245 if (HAVE_32BIT_GPRS
)
11246 normalize_constant_expr (&imm2_expr
);
11250 case 'T': /* Coprocessor register. */
11251 gas_assert (!mips_opts
.micromips
);
11252 /* +T is for disassembly only; never match. */
11255 case 't': /* Coprocessor register number. */
11256 gas_assert (!mips_opts
.micromips
);
11257 if (s
[0] == '$' && ISDIGIT (s
[1]))
11267 while (ISDIGIT (*s
));
11269 as_bad (_("Invalid register number (%d)"), regno
);
11272 INSERT_OPERAND (0, RT
, *ip
, regno
);
11277 as_bad (_("Invalid coprocessor 0 register number"));
11281 /* bbit[01] and bbit[01]32 bit index. Give error if index
11282 is not in the valid range. */
11283 gas_assert (!mips_opts
.micromips
);
11284 my_getExpression (&imm_expr
, s
);
11285 check_absolute_expr (ip
, &imm_expr
);
11286 if ((unsigned) imm_expr
.X_add_number
> 31)
11288 as_bad (_("Improper bit index (%lu)"),
11289 (unsigned long) imm_expr
.X_add_number
);
11290 imm_expr
.X_add_number
= 0;
11292 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11293 imm_expr
.X_op
= O_absent
;
11298 /* bbit[01] bit index when bbit is used but we generate
11299 bbit[01]32 because the index is over 32. Move to the
11300 next candidate if index is not in the valid range. */
11301 gas_assert (!mips_opts
.micromips
);
11302 my_getExpression (&imm_expr
, s
);
11303 check_absolute_expr (ip
, &imm_expr
);
11304 if ((unsigned) imm_expr
.X_add_number
< 32
11305 || (unsigned) imm_expr
.X_add_number
> 63)
11307 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11308 imm_expr
.X_op
= O_absent
;
11313 /* cins, cins32, exts and exts32 position field. Give error
11314 if it's not in the valid range. */
11315 gas_assert (!mips_opts
.micromips
);
11316 my_getExpression (&imm_expr
, s
);
11317 check_absolute_expr (ip
, &imm_expr
);
11318 if ((unsigned) imm_expr
.X_add_number
> 31)
11320 as_bad (_("Improper position (%lu)"),
11321 (unsigned long) imm_expr
.X_add_number
);
11322 imm_expr
.X_add_number
= 0;
11324 /* Make the pos explicit to simplify +S. */
11325 lastpos
= imm_expr
.X_add_number
+ 32;
11326 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11327 imm_expr
.X_op
= O_absent
;
11332 /* cins, cins32, exts and exts32 position field. Move to
11333 the next candidate if it's not in the valid range. */
11334 gas_assert (!mips_opts
.micromips
);
11335 my_getExpression (&imm_expr
, s
);
11336 check_absolute_expr (ip
, &imm_expr
);
11337 if ((unsigned) imm_expr
.X_add_number
< 32
11338 || (unsigned) imm_expr
.X_add_number
> 63)
11340 lastpos
= imm_expr
.X_add_number
;
11341 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11342 imm_expr
.X_op
= O_absent
;
11347 /* cins and exts length-minus-one field. */
11348 gas_assert (!mips_opts
.micromips
);
11349 my_getExpression (&imm_expr
, s
);
11350 check_absolute_expr (ip
, &imm_expr
);
11351 if ((unsigned long) imm_expr
.X_add_number
> 31)
11353 as_bad (_("Improper size (%lu)"),
11354 (unsigned long) imm_expr
.X_add_number
);
11355 imm_expr
.X_add_number
= 0;
11357 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11358 imm_expr
.X_op
= O_absent
;
11363 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11364 length-minus-one field. */
11365 gas_assert (!mips_opts
.micromips
);
11366 my_getExpression (&imm_expr
, s
);
11367 check_absolute_expr (ip
, &imm_expr
);
11368 if ((long) imm_expr
.X_add_number
< 0
11369 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11371 as_bad (_("Improper size (%lu)"),
11372 (unsigned long) imm_expr
.X_add_number
);
11373 imm_expr
.X_add_number
= 0;
11375 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11376 imm_expr
.X_op
= O_absent
;
11381 /* seqi/snei immediate field. */
11382 gas_assert (!mips_opts
.micromips
);
11383 my_getExpression (&imm_expr
, s
);
11384 check_absolute_expr (ip
, &imm_expr
);
11385 if ((long) imm_expr
.X_add_number
< -512
11386 || (long) imm_expr
.X_add_number
>= 512)
11388 as_bad (_("Improper immediate (%ld)"),
11389 (long) imm_expr
.X_add_number
);
11390 imm_expr
.X_add_number
= 0;
11392 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11393 imm_expr
.X_op
= O_absent
;
11397 case 'a': /* 8-bit signed offset in bit 6 */
11398 gas_assert (!mips_opts
.micromips
);
11399 my_getExpression (&imm_expr
, s
);
11400 check_absolute_expr (ip
, &imm_expr
);
11401 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11402 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11403 if (imm_expr
.X_add_number
< min_range
11404 || imm_expr
.X_add_number
> max_range
)
11406 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11407 (long) min_range
, (long) max_range
,
11408 (long) imm_expr
.X_add_number
);
11410 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11411 imm_expr
.X_op
= O_absent
;
11415 case 'b': /* 8-bit signed offset in bit 3 */
11416 gas_assert (!mips_opts
.micromips
);
11417 my_getExpression (&imm_expr
, s
);
11418 check_absolute_expr (ip
, &imm_expr
);
11419 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11420 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11421 if (imm_expr
.X_add_number
< min_range
11422 || imm_expr
.X_add_number
> max_range
)
11424 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11425 (long) min_range
, (long) max_range
,
11426 (long) imm_expr
.X_add_number
);
11428 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11429 imm_expr
.X_op
= O_absent
;
11433 case 'c': /* 9-bit signed offset in bit 6 */
11434 gas_assert (!mips_opts
.micromips
);
11435 my_getExpression (&imm_expr
, s
);
11436 check_absolute_expr (ip
, &imm_expr
);
11437 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11438 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11439 /* We check the offset range before adjusted. */
11442 if (imm_expr
.X_add_number
< min_range
11443 || imm_expr
.X_add_number
> max_range
)
11445 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11446 (long) min_range
, (long) max_range
,
11447 (long) imm_expr
.X_add_number
);
11449 if (imm_expr
.X_add_number
& 0xf)
11451 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11452 (long) imm_expr
.X_add_number
);
11454 /* Right shift 4 bits to adjust the offset operand. */
11455 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11456 imm_expr
.X_add_number
>> 4);
11457 imm_expr
.X_op
= O_absent
;
11462 gas_assert (!mips_opts
.micromips
);
11463 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11465 if (regno
== AT
&& mips_opts
.at
)
11467 if (mips_opts
.at
== ATREG
)
11468 as_warn (_("used $at without \".set noat\""));
11470 as_warn (_("used $%u with \".set at=$%u\""),
11471 regno
, mips_opts
.at
);
11473 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11477 gas_assert (!mips_opts
.micromips
);
11478 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11480 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11484 as_bad (_("Internal error: bad %s opcode "
11485 "(unknown extension operand type `+%c'): %s %s"),
11486 mips_opts
.micromips
? "microMIPS" : "MIPS",
11487 *args
, insn
->name
, insn
->args
);
11488 /* Further processing is fruitless. */
11493 case '.': /* 10-bit offset. */
11494 gas_assert (mips_opts
.micromips
);
11495 case '~': /* 12-bit offset. */
11497 int shift
= *args
== '.' ? 9 : 11;
11500 /* Check whether there is only a single bracketed expression
11501 left. If so, it must be the base register and the
11502 constant must be zero. */
11503 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11506 /* If this value won't fit into the offset, then go find
11507 a macro that will generate a 16- or 32-bit offset code
11509 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11510 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11511 || imm_expr
.X_add_number
>= 1 << shift
11512 || imm_expr
.X_add_number
< -1 << shift
))
11515 imm_expr
.X_op
= O_absent
;
11519 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11521 INSERT_OPERAND (mips_opts
.micromips
,
11522 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11523 imm_expr
.X_op
= O_absent
;
11528 case '<': /* must be at least one digit */
11530 * According to the manual, if the shift amount is greater
11531 * than 31 or less than 0, then the shift amount should be
11532 * mod 32. In reality the mips assembler issues an error.
11533 * We issue a warning and mask out all but the low 5 bits.
11535 my_getExpression (&imm_expr
, s
);
11536 check_absolute_expr (ip
, &imm_expr
);
11537 if ((unsigned long) imm_expr
.X_add_number
> 31)
11538 as_warn (_("Improper shift amount (%lu)"),
11539 (unsigned long) imm_expr
.X_add_number
);
11540 INSERT_OPERAND (mips_opts
.micromips
,
11541 SHAMT
, *ip
, imm_expr
.X_add_number
);
11542 imm_expr
.X_op
= O_absent
;
11546 case '>': /* shift amount minus 32 */
11547 my_getExpression (&imm_expr
, s
);
11548 check_absolute_expr (ip
, &imm_expr
);
11549 if ((unsigned long) imm_expr
.X_add_number
< 32
11550 || (unsigned long) imm_expr
.X_add_number
> 63)
11552 INSERT_OPERAND (mips_opts
.micromips
,
11553 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11554 imm_expr
.X_op
= O_absent
;
11558 case 'k': /* CACHE code. */
11559 case 'h': /* PREFX code. */
11560 case '1': /* SYNC type. */
11561 my_getExpression (&imm_expr
, s
);
11562 check_absolute_expr (ip
, &imm_expr
);
11563 if ((unsigned long) imm_expr
.X_add_number
> 31)
11564 as_warn (_("Invalid value for `%s' (%lu)"),
11566 (unsigned long) imm_expr
.X_add_number
);
11570 if (mips_fix_cn63xxp1
11571 && !mips_opts
.micromips
11572 && strcmp ("pref", insn
->name
) == 0)
11573 switch (imm_expr
.X_add_number
)
11582 case 31: /* These are ok. */
11585 default: /* The rest must be changed to 28. */
11586 imm_expr
.X_add_number
= 28;
11589 INSERT_OPERAND (mips_opts
.micromips
,
11590 CACHE
, *ip
, imm_expr
.X_add_number
);
11593 INSERT_OPERAND (mips_opts
.micromips
,
11594 PREFX
, *ip
, imm_expr
.X_add_number
);
11597 INSERT_OPERAND (mips_opts
.micromips
,
11598 STYPE
, *ip
, imm_expr
.X_add_number
);
11601 imm_expr
.X_op
= O_absent
;
11605 case 'c': /* BREAK code. */
11607 unsigned long mask
= (mips_opts
.micromips
11608 ? MICROMIPSOP_MASK_CODE
11611 my_getExpression (&imm_expr
, s
);
11612 check_absolute_expr (ip
, &imm_expr
);
11613 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11614 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11616 mask
, (unsigned long) imm_expr
.X_add_number
);
11617 INSERT_OPERAND (mips_opts
.micromips
,
11618 CODE
, *ip
, imm_expr
.X_add_number
);
11619 imm_expr
.X_op
= O_absent
;
11624 case 'q': /* Lower BREAK code. */
11626 unsigned long mask
= (mips_opts
.micromips
11627 ? MICROMIPSOP_MASK_CODE2
11630 my_getExpression (&imm_expr
, s
);
11631 check_absolute_expr (ip
, &imm_expr
);
11632 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11633 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11635 mask
, (unsigned long) imm_expr
.X_add_number
);
11636 INSERT_OPERAND (mips_opts
.micromips
,
11637 CODE2
, *ip
, imm_expr
.X_add_number
);
11638 imm_expr
.X_op
= O_absent
;
11643 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11645 unsigned long mask
= (mips_opts
.micromips
11646 ? MICROMIPSOP_MASK_CODE10
11649 my_getExpression (&imm_expr
, s
);
11650 check_absolute_expr (ip
, &imm_expr
);
11651 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11652 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11654 mask
, (unsigned long) imm_expr
.X_add_number
);
11655 if (mips_opts
.micromips
)
11656 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11658 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11659 imm_expr
.X_op
= O_absent
;
11664 case 'C': /* 25- or 23-bit coprocessor code. */
11666 unsigned long mask
= (mips_opts
.micromips
11667 ? MICROMIPSOP_MASK_COPZ
11670 my_getExpression (&imm_expr
, s
);
11671 check_absolute_expr (ip
, &imm_expr
);
11672 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11673 as_warn (_("Coproccesor code > %u bits (%lu)"),
11674 mips_opts
.micromips
? 23U : 25U,
11675 (unsigned long) imm_expr
.X_add_number
);
11676 INSERT_OPERAND (mips_opts
.micromips
,
11677 COPZ
, *ip
, imm_expr
.X_add_number
);
11678 imm_expr
.X_op
= O_absent
;
11683 case 'J': /* 19-bit WAIT code. */
11684 gas_assert (!mips_opts
.micromips
);
11685 my_getExpression (&imm_expr
, s
);
11686 check_absolute_expr (ip
, &imm_expr
);
11687 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11689 as_warn (_("Illegal 19-bit code (%lu)"),
11690 (unsigned long) imm_expr
.X_add_number
);
11691 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11693 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11694 imm_expr
.X_op
= O_absent
;
11698 case 'P': /* Performance register. */
11699 gas_assert (!mips_opts
.micromips
);
11700 my_getExpression (&imm_expr
, s
);
11701 check_absolute_expr (ip
, &imm_expr
);
11702 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11703 as_warn (_("Invalid performance register (%lu)"),
11704 (unsigned long) imm_expr
.X_add_number
);
11705 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11706 imm_expr
.X_op
= O_absent
;
11710 case 'G': /* Coprocessor destination register. */
11712 unsigned long opcode
= ip
->insn_opcode
;
11713 unsigned long mask
;
11714 unsigned int types
;
11717 if (mips_opts
.micromips
)
11719 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11720 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11721 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11725 case 0x000000fc: /* mfc0 */
11726 case 0x000002fc: /* mtc0 */
11727 case 0x580000fc: /* dmfc0 */
11728 case 0x580002fc: /* dmtc0 */
11738 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11739 cop0
= opcode
== OP_OP_COP0
;
11741 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11742 ok
= reg_lookup (&s
, types
, ®no
);
11743 if (mips_opts
.micromips
)
11744 INSERT_OPERAND (1, RS
, *ip
, regno
);
11746 INSERT_OPERAND (0, RD
, *ip
, regno
);
11755 case 'y': /* ALNV.PS source register. */
11756 gas_assert (mips_opts
.micromips
);
11758 case 'x': /* Ignore register name. */
11759 case 'U': /* Destination register (CLO/CLZ). */
11760 case 'g': /* Coprocessor destination register. */
11761 gas_assert (!mips_opts
.micromips
);
11762 case 'b': /* Base register. */
11763 case 'd': /* Destination register. */
11764 case 's': /* Source register. */
11765 case 't': /* Target register. */
11766 case 'r': /* Both target and source. */
11767 case 'v': /* Both dest and source. */
11768 case 'w': /* Both dest and target. */
11769 case 'E': /* Coprocessor target register. */
11770 case 'K': /* RDHWR destination register. */
11771 case 'z': /* Must be zero register. */
11774 if (*args
== 'E' || *args
== 'K')
11775 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11778 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11779 if (regno
== AT
&& mips_opts
.at
)
11781 if (mips_opts
.at
== ATREG
)
11782 as_warn (_("Used $at without \".set noat\""));
11784 as_warn (_("Used $%u with \".set at=$%u\""),
11785 regno
, mips_opts
.at
);
11795 if (c
== 'r' || c
== 'v' || c
== 'w')
11802 /* 'z' only matches $0. */
11803 if (c
== 'z' && regno
!= 0)
11806 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11808 if (regno
== lastregno
)
11811 = _("Source and destination must be different");
11814 if (regno
== 31 && lastregno
== 0xffffffff)
11817 = _("A destination register must be supplied");
11821 /* Now that we have assembled one operand, we use the args
11822 string to figure out where it goes in the instruction. */
11829 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11833 if (mips_opts
.micromips
)
11834 INSERT_OPERAND (1, RS
, *ip
, regno
);
11836 INSERT_OPERAND (0, RD
, *ip
, regno
);
11841 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11845 gas_assert (!mips_opts
.micromips
);
11846 INSERT_OPERAND (0, RD
, *ip
, regno
);
11847 INSERT_OPERAND (0, RT
, *ip
, regno
);
11853 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11857 gas_assert (mips_opts
.micromips
);
11858 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11862 /* This case exists because on the r3000 trunc
11863 expands into a macro which requires a gp
11864 register. On the r6000 or r4000 it is
11865 assembled into a single instruction which
11866 ignores the register. Thus the insn version
11867 is MIPS_ISA2 and uses 'x', and the macro
11868 version is MIPS_ISA1 and uses 't'. */
11872 /* This case is for the div instruction, which
11873 acts differently if the destination argument
11874 is $0. This only matches $0, and is checked
11875 outside the switch. */
11885 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11889 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11894 case 'O': /* MDMX alignment immediate constant. */
11895 gas_assert (!mips_opts
.micromips
);
11896 my_getExpression (&imm_expr
, s
);
11897 check_absolute_expr (ip
, &imm_expr
);
11898 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11899 as_warn (_("Improper align amount (%ld), using low bits"),
11900 (long) imm_expr
.X_add_number
);
11901 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11902 imm_expr
.X_op
= O_absent
;
11906 case 'Q': /* MDMX vector, element sel, or const. */
11909 /* MDMX Immediate. */
11910 gas_assert (!mips_opts
.micromips
);
11911 my_getExpression (&imm_expr
, s
);
11912 check_absolute_expr (ip
, &imm_expr
);
11913 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11914 as_warn (_("Invalid MDMX Immediate (%ld)"),
11915 (long) imm_expr
.X_add_number
);
11916 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11917 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11918 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11920 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11921 imm_expr
.X_op
= O_absent
;
11925 /* Not MDMX Immediate. Fall through. */
11926 case 'X': /* MDMX destination register. */
11927 case 'Y': /* MDMX source register. */
11928 case 'Z': /* MDMX target register. */
11931 gas_assert (!mips_opts
.micromips
);
11932 case 'D': /* Floating point destination register. */
11933 case 'S': /* Floating point source register. */
11934 case 'T': /* Floating point target register. */
11935 case 'R': /* Floating point source register. */
11939 || (mips_opts
.ase_mdmx
11940 && (ip
->insn_mo
->pinfo
& FP_D
)
11941 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
11942 | INSN_COPROC_MEMORY_DELAY
11943 | INSN_LOAD_COPROC_DELAY
11944 | INSN_LOAD_MEMORY_DELAY
11945 | INSN_STORE_MEMORY
))))
11946 rtype
|= RTYPE_VEC
;
11948 if (reg_lookup (&s
, rtype
, ®no
))
11950 if ((regno
& 1) != 0
11952 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
11953 as_warn (_("Float register should be even, was %d"),
11961 if (c
== 'V' || c
== 'W')
11972 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
11978 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
11982 /* This is like 'Z', but also needs to fix the MDMX
11983 vector/scalar select bits. Note that the
11984 scalar immediate case is handled above. */
11987 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
11988 int max_el
= (is_qh
? 3 : 7);
11990 my_getExpression(&imm_expr
, s
);
11991 check_absolute_expr (ip
, &imm_expr
);
11993 if (imm_expr
.X_add_number
> max_el
)
11994 as_bad (_("Bad element selector %ld"),
11995 (long) imm_expr
.X_add_number
);
11996 imm_expr
.X_add_number
&= max_el
;
11997 ip
->insn_opcode
|= (imm_expr
.X_add_number
12000 imm_expr
.X_op
= O_absent
;
12002 as_warn (_("Expecting ']' found '%s'"), s
);
12008 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12009 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12012 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12015 /* Fall through. */
12019 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12023 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12033 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12037 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12043 my_getExpression (&imm_expr
, s
);
12044 if (imm_expr
.X_op
!= O_big
12045 && imm_expr
.X_op
!= O_constant
)
12046 insn_error
= _("absolute expression required");
12047 if (HAVE_32BIT_GPRS
)
12048 normalize_constant_expr (&imm_expr
);
12053 my_getExpression (&offset_expr
, s
);
12054 normalize_address_expr (&offset_expr
);
12055 *imm_reloc
= BFD_RELOC_32
;
12068 unsigned char temp
[8];
12070 unsigned int length
;
12075 /* These only appear as the last operand in an
12076 instruction, and every instruction that accepts
12077 them in any variant accepts them in all variants.
12078 This means we don't have to worry about backing out
12079 any changes if the instruction does not match.
12081 The difference between them is the size of the
12082 floating point constant and where it goes. For 'F'
12083 and 'L' the constant is 64 bits; for 'f' and 'l' it
12084 is 32 bits. Where the constant is placed is based
12085 on how the MIPS assembler does things:
12088 f -- immediate value
12091 The .lit4 and .lit8 sections are only used if
12092 permitted by the -G argument.
12094 The code below needs to know whether the target register
12095 is 32 or 64 bits wide. It relies on the fact 'f' and
12096 'F' are used with GPR-based instructions and 'l' and
12097 'L' are used with FPR-based instructions. */
12099 f64
= *args
== 'F' || *args
== 'L';
12100 using_gprs
= *args
== 'F' || *args
== 'f';
12102 save_in
= input_line_pointer
;
12103 input_line_pointer
= s
;
12104 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12106 s
= input_line_pointer
;
12107 input_line_pointer
= save_in
;
12108 if (err
!= NULL
&& *err
!= '\0')
12110 as_bad (_("Bad floating point constant: %s"), err
);
12111 memset (temp
, '\0', sizeof temp
);
12112 length
= f64
? 8 : 4;
12115 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12119 && (g_switch_value
< 4
12120 || (temp
[0] == 0 && temp
[1] == 0)
12121 || (temp
[2] == 0 && temp
[3] == 0))))
12123 imm_expr
.X_op
= O_constant
;
12124 if (!target_big_endian
)
12125 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12127 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12129 else if (length
> 4
12130 && !mips_disable_float_construction
12131 /* Constants can only be constructed in GPRs and
12132 copied to FPRs if the GPRs are at least as wide
12133 as the FPRs. Force the constant into memory if
12134 we are using 64-bit FPRs but the GPRs are only
12137 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12138 && ((temp
[0] == 0 && temp
[1] == 0)
12139 || (temp
[2] == 0 && temp
[3] == 0))
12140 && ((temp
[4] == 0 && temp
[5] == 0)
12141 || (temp
[6] == 0 && temp
[7] == 0)))
12143 /* The value is simple enough to load with a couple of
12144 instructions. If using 32-bit registers, set
12145 imm_expr to the high order 32 bits and offset_expr to
12146 the low order 32 bits. Otherwise, set imm_expr to
12147 the entire 64 bit constant. */
12148 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12150 imm_expr
.X_op
= O_constant
;
12151 offset_expr
.X_op
= O_constant
;
12152 if (!target_big_endian
)
12154 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12155 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12159 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12160 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12162 if (offset_expr
.X_add_number
== 0)
12163 offset_expr
.X_op
= O_absent
;
12165 else if (sizeof (imm_expr
.X_add_number
) > 4)
12167 imm_expr
.X_op
= O_constant
;
12168 if (!target_big_endian
)
12169 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12171 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12175 imm_expr
.X_op
= O_big
;
12176 imm_expr
.X_add_number
= 4;
12177 if (!target_big_endian
)
12179 generic_bignum
[0] = bfd_getl16 (temp
);
12180 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12181 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12182 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12186 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12187 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12188 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12189 generic_bignum
[3] = bfd_getb16 (temp
);
12195 const char *newname
;
12198 /* Switch to the right section. */
12200 subseg
= now_subseg
;
12203 default: /* unused default case avoids warnings. */
12205 newname
= RDATA_SECTION_NAME
;
12206 if (g_switch_value
>= 8)
12210 newname
= RDATA_SECTION_NAME
;
12213 gas_assert (g_switch_value
>= 4);
12217 new_seg
= subseg_new (newname
, (subsegT
) 0);
12219 bfd_set_section_flags (stdoutput
, new_seg
,
12224 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12225 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12226 record_alignment (new_seg
, 4);
12228 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12229 if (seg
== now_seg
)
12230 as_bad (_("Can't use floating point insn in this section"));
12232 /* Set the argument to the current address in the
12234 offset_expr
.X_op
= O_symbol
;
12235 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12236 offset_expr
.X_add_number
= 0;
12238 /* Put the floating point number into the section. */
12239 p
= frag_more ((int) length
);
12240 memcpy (p
, temp
, length
);
12242 /* Switch back to the original section. */
12243 subseg_set (seg
, subseg
);
12248 case 'i': /* 16-bit unsigned immediate. */
12249 case 'j': /* 16-bit signed immediate. */
12250 *imm_reloc
= BFD_RELOC_LO16
;
12251 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12254 offsetT minval
, maxval
;
12256 more
= (insn
+ 1 < past
12257 && strcmp (insn
->name
, insn
[1].name
) == 0);
12259 /* If the expression was written as an unsigned number,
12260 only treat it as signed if there are no more
12264 && sizeof (imm_expr
.X_add_number
) <= 4
12265 && imm_expr
.X_op
== O_constant
12266 && imm_expr
.X_add_number
< 0
12267 && imm_expr
.X_unsigned
12268 && HAVE_64BIT_GPRS
)
12271 /* For compatibility with older assemblers, we accept
12272 0x8000-0xffff as signed 16-bit numbers when only
12273 signed numbers are allowed. */
12275 minval
= 0, maxval
= 0xffff;
12277 minval
= -0x8000, maxval
= 0x7fff;
12279 minval
= -0x8000, maxval
= 0xffff;
12281 if (imm_expr
.X_op
!= O_constant
12282 || imm_expr
.X_add_number
< minval
12283 || imm_expr
.X_add_number
> maxval
)
12287 if (imm_expr
.X_op
== O_constant
12288 || imm_expr
.X_op
== O_big
)
12289 as_bad (_("Expression out of range"));
12295 case 'o': /* 16-bit offset. */
12296 offset_reloc
[0] = BFD_RELOC_LO16
;
12297 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12298 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12300 /* Check whether there is only a single bracketed expression
12301 left. If so, it must be the base register and the
12302 constant must be zero. */
12303 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12305 offset_expr
.X_op
= O_constant
;
12306 offset_expr
.X_add_number
= 0;
12310 /* If this value won't fit into a 16 bit offset, then go
12311 find a macro that will generate the 32 bit offset
12313 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12314 && (offset_expr
.X_op
!= O_constant
12315 || offset_expr
.X_add_number
>= 0x8000
12316 || offset_expr
.X_add_number
< -0x8000))
12322 case 'p': /* PC-relative offset. */
12323 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12324 my_getExpression (&offset_expr
, s
);
12328 case 'u': /* Upper 16 bits. */
12329 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12330 && imm_expr
.X_op
== O_constant
12331 && (imm_expr
.X_add_number
< 0
12332 || imm_expr
.X_add_number
>= 0x10000))
12333 as_bad (_("lui expression (%lu) not in range 0..65535"),
12334 (unsigned long) imm_expr
.X_add_number
);
12338 case 'a': /* 26-bit address. */
12339 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12340 my_getExpression (&offset_expr
, s
);
12344 case 'N': /* 3-bit branch condition code. */
12345 case 'M': /* 3-bit compare condition code. */
12347 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12348 rtype
|= RTYPE_FCC
;
12349 if (!reg_lookup (&s
, rtype
, ®no
))
12351 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12352 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12353 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12354 && (regno
& 1) != 0)
12355 as_warn (_("Condition code register should be even for %s, "
12358 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12359 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12360 && (regno
& 3) != 0)
12361 as_warn (_("Condition code register should be 0 or 4 for %s, "
12365 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12367 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12371 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12382 while (ISDIGIT (*s
));
12385 c
= 8; /* Invalid sel value. */
12388 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12389 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12393 gas_assert (!mips_opts
.micromips
);
12394 /* Must be at least one digit. */
12395 my_getExpression (&imm_expr
, s
);
12396 check_absolute_expr (ip
, &imm_expr
);
12398 if ((unsigned long) imm_expr
.X_add_number
12399 > (unsigned long) OP_MASK_VECBYTE
)
12401 as_bad (_("bad byte vector index (%ld)"),
12402 (long) imm_expr
.X_add_number
);
12403 imm_expr
.X_add_number
= 0;
12406 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12407 imm_expr
.X_op
= O_absent
;
12412 gas_assert (!mips_opts
.micromips
);
12413 my_getExpression (&imm_expr
, s
);
12414 check_absolute_expr (ip
, &imm_expr
);
12416 if ((unsigned long) imm_expr
.X_add_number
12417 > (unsigned long) OP_MASK_VECALIGN
)
12419 as_bad (_("bad byte vector index (%ld)"),
12420 (long) imm_expr
.X_add_number
);
12421 imm_expr
.X_add_number
= 0;
12424 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12425 imm_expr
.X_op
= O_absent
;
12429 case 'm': /* Opcode extension character. */
12430 gas_assert (mips_opts
.micromips
);
12435 if (strncmp (s
, "$pc", 3) == 0)
12463 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12464 if (regno
== AT
&& mips_opts
.at
)
12466 if (mips_opts
.at
== ATREG
)
12467 as_warn (_("Used $at without \".set noat\""));
12469 as_warn (_("Used $%u with \".set at=$%u\""),
12470 regno
, mips_opts
.at
);
12476 gas_assert (args
[1] == ',');
12482 gas_assert (args
[1] == ',');
12484 continue; /* Nothing to do. */
12490 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12492 if (regno
== lastregno
)
12495 = _("Source and destination must be different");
12498 if (regno
== 31 && lastregno
== 0xffffffff)
12501 = _("A destination register must be supplied");
12512 gas_assert (args
[1] == ',');
12519 gas_assert (args
[1] == ',');
12522 continue; /* Nothing to do. */
12526 /* Make sure regno is the same as lastregno. */
12527 if (c
== 't' && regno
!= lastregno
)
12530 /* Make sure regno is the same as destregno. */
12531 if (c
== 'x' && regno
!= destregno
)
12534 /* We need to save regno, before regno maps to the
12535 microMIPS register encoding. */
12545 regno
= ILLEGAL_REG
;
12549 regno
= mips32_to_micromips_reg_b_map
[regno
];
12553 regno
= mips32_to_micromips_reg_c_map
[regno
];
12557 regno
= mips32_to_micromips_reg_d_map
[regno
];
12561 regno
= mips32_to_micromips_reg_e_map
[regno
];
12565 regno
= mips32_to_micromips_reg_f_map
[regno
];
12569 regno
= mips32_to_micromips_reg_g_map
[regno
];
12573 regno
= mips32_to_micromips_reg_h_map
[regno
];
12577 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12582 else if (regno
== 22)
12584 else if (regno
== 5)
12586 else if (regno
== 6)
12588 else if (regno
== 7)
12591 regno
= ILLEGAL_REG
;
12597 else if (regno
== 7)
12600 regno
= ILLEGAL_REG
;
12607 regno
= ILLEGAL_REG
;
12611 regno
= ILLEGAL_REG
;
12617 regno
= mips32_to_micromips_reg_l_map
[regno
];
12621 regno
= mips32_to_micromips_reg_m_map
[regno
];
12625 regno
= mips32_to_micromips_reg_n_map
[regno
];
12629 regno
= mips32_to_micromips_reg_q_map
[regno
];
12634 regno
= ILLEGAL_REG
;
12639 regno
= ILLEGAL_REG
;
12644 regno
= ILLEGAL_REG
;
12647 case 'j': /* Do nothing. */
12657 if (regno
== ILLEGAL_REG
)
12663 INSERT_OPERAND (1, MB
, *ip
, regno
);
12667 INSERT_OPERAND (1, MC
, *ip
, regno
);
12671 INSERT_OPERAND (1, MD
, *ip
, regno
);
12675 INSERT_OPERAND (1, ME
, *ip
, regno
);
12679 INSERT_OPERAND (1, MF
, *ip
, regno
);
12683 INSERT_OPERAND (1, MG
, *ip
, regno
);
12687 INSERT_OPERAND (1, MH
, *ip
, regno
);
12691 INSERT_OPERAND (1, MI
, *ip
, regno
);
12695 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12699 INSERT_OPERAND (1, ML
, *ip
, regno
);
12703 INSERT_OPERAND (1, MM
, *ip
, regno
);
12707 INSERT_OPERAND (1, MN
, *ip
, regno
);
12711 INSERT_OPERAND (1, MP
, *ip
, regno
);
12715 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12718 case 'a': /* Do nothing. */
12719 case 's': /* Do nothing. */
12720 case 't': /* Do nothing. */
12721 case 'x': /* Do nothing. */
12722 case 'y': /* Do nothing. */
12723 case 'z': /* Do nothing. */
12733 bfd_reloc_code_real_type r
[3];
12737 /* Check whether there is only a single bracketed
12738 expression left. If so, it must be the base register
12739 and the constant must be zero. */
12740 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12742 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12746 if (my_getSmallExpression (&ep
, r
, s
) > 0
12747 || !expr_const_in_range (&ep
, -64, 64, 2))
12750 imm
= ep
.X_add_number
>> 2;
12751 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12758 bfd_reloc_code_real_type r
[3];
12762 if (my_getSmallExpression (&ep
, r
, s
) > 0
12763 || ep
.X_op
!= O_constant
)
12766 for (imm
= 0; imm
< 8; imm
++)
12767 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12772 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12779 bfd_reloc_code_real_type r
[3];
12783 if (my_getSmallExpression (&ep
, r
, s
) > 0
12784 || ep
.X_op
!= O_constant
)
12787 for (imm
= 0; imm
< 16; imm
++)
12788 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12793 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12798 case 'D': /* pc relative offset */
12799 case 'E': /* pc relative offset */
12800 my_getExpression (&offset_expr
, s
);
12801 if (offset_expr
.X_op
== O_register
)
12804 if (!forced_insn_length
)
12805 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12807 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12809 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12815 bfd_reloc_code_real_type r
[3];
12819 if (my_getSmallExpression (&ep
, r
, s
) > 0
12820 || !expr_const_in_range (&ep
, 0, 16, 0))
12823 imm
= ep
.X_add_number
;
12824 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12831 bfd_reloc_code_real_type r
[3];
12835 /* Check whether there is only a single bracketed
12836 expression left. If so, it must be the base register
12837 and the constant must be zero. */
12838 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12840 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12844 if (my_getSmallExpression (&ep
, r
, s
) > 0
12845 || !expr_const_in_range (&ep
, -1, 15, 0))
12848 imm
= ep
.X_add_number
& 15;
12849 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12856 bfd_reloc_code_real_type r
[3];
12860 /* Check whether there is only a single bracketed
12861 expression left. If so, it must be the base register
12862 and the constant must be zero. */
12863 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12865 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12869 if (my_getSmallExpression (&ep
, r
, s
) > 0
12870 || !expr_const_in_range (&ep
, 0, 16, 1))
12873 imm
= ep
.X_add_number
>> 1;
12874 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12881 bfd_reloc_code_real_type r
[3];
12885 if (my_getSmallExpression (&ep
, r
, s
) > 0
12886 || !expr_const_in_range (&ep
, -1, 127, 0))
12889 imm
= ep
.X_add_number
& 127;
12890 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12897 bfd_reloc_code_real_type r
[3];
12901 /* Check whether there is only a single bracketed
12902 expression left. If so, it must be the base register
12903 and the constant must be zero. */
12904 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12906 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12910 if (my_getSmallExpression (&ep
, r
, s
) > 0
12911 || !expr_const_in_range (&ep
, 0, 16, 2))
12914 imm
= ep
.X_add_number
>> 2;
12915 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12922 bfd_reloc_code_real_type r
[3];
12926 /* Check whether there is only a single bracketed
12927 expression left. If so, it must be the base register
12928 and the constant must be zero. */
12929 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12931 INSERT_OPERAND (1, IMML
, *ip
, 0);
12935 if (my_getSmallExpression (&ep
, r
, s
) > 0
12936 || !expr_const_in_range (&ep
, 0, 16, 0))
12939 imm
= ep
.X_add_number
;
12940 INSERT_OPERAND (1, IMML
, *ip
, imm
);
12947 bfd_reloc_code_real_type r
[3];
12951 if (my_getSmallExpression (&ep
, r
, s
) > 0
12952 || !expr_const_in_range (&ep
, 1, 9, 0))
12955 imm
= ep
.X_add_number
& 7;
12956 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
12961 case 'N': /* Register list for lwm and swm. */
12963 /* A comma-separated list of registers and/or
12964 dash-separated contiguous ranges including
12965 both ra and a set of one or more registers
12966 starting at s0 up to s3 which have to be
12973 and any permutations of these. */
12974 unsigned int reglist
;
12977 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
12980 if ((reglist
& 0xfff1ffff) != 0x80010000)
12983 reglist
= (reglist
>> 17) & 7;
12985 if ((reglist
& -reglist
) != reglist
)
12988 imm
= ffs (reglist
) - 1;
12989 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
12993 case 'O': /* sdbbp 4-bit code. */
12995 bfd_reloc_code_real_type r
[3];
12999 if (my_getSmallExpression (&ep
, r
, s
) > 0
13000 || !expr_const_in_range (&ep
, 0, 16, 0))
13003 imm
= ep
.X_add_number
;
13004 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13011 bfd_reloc_code_real_type r
[3];
13015 if (my_getSmallExpression (&ep
, r
, s
) > 0
13016 || !expr_const_in_range (&ep
, 0, 32, 2))
13019 imm
= ep
.X_add_number
>> 2;
13020 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13027 bfd_reloc_code_real_type r
[3];
13031 if (my_getSmallExpression (&ep
, r
, s
) > 0
13032 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13035 imm
= ep
.X_add_number
>> 2;
13036 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13043 bfd_reloc_code_real_type r
[3];
13047 /* Check whether there is only a single bracketed
13048 expression left. If so, it must be the base register
13049 and the constant must be zero. */
13050 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13052 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13056 if (my_getSmallExpression (&ep
, r
, s
) > 0
13057 || !expr_const_in_range (&ep
, 0, 32, 2))
13060 imm
= ep
.X_add_number
>> 2;
13061 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13068 bfd_reloc_code_real_type r
[3];
13072 if (my_getSmallExpression (&ep
, r
, s
) > 0
13073 || !expr_const_in_range (&ep
, 0, 64, 2))
13076 imm
= ep
.X_add_number
>> 2;
13077 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13084 bfd_reloc_code_real_type r
[3];
13088 if (my_getSmallExpression (&ep
, r
, s
) > 0
13089 || !expr_const_in_range (&ep
, -8, 8, 0))
13092 imm
= ep
.X_add_number
;
13093 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13100 bfd_reloc_code_real_type r
[3];
13104 if (my_getSmallExpression (&ep
, r
, s
) > 0
13105 || expr_const_in_range (&ep
, -2, 2, 2)
13106 || !expr_const_in_range (&ep
, -258, 258, 2))
13109 imm
= ep
.X_add_number
>> 2;
13110 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13111 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13118 bfd_reloc_code_real_type r
[3];
13121 if (my_getSmallExpression (&ep
, r
, s
) > 0
13122 || !expr_const_in_range (&ep
, 0, 1, 0))
13129 as_bad (_("Internal error: bad microMIPS opcode "
13130 "(unknown extension operand type `m%c'): %s %s"),
13131 *args
, insn
->name
, insn
->args
);
13132 /* Further processing is fruitless. */
13137 case 'n': /* Register list for 32-bit lwm and swm. */
13138 gas_assert (mips_opts
.micromips
);
13140 /* A comma-separated list of registers and/or
13141 dash-separated contiguous ranges including
13142 at least one of ra and a set of one or more
13143 registers starting at s0 up to s7 and then
13144 s8 which have to be consecutive, e.g.:
13152 and any permutations of these. */
13153 unsigned int reglist
;
13157 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13160 if ((reglist
& 0x3f00ffff) != 0)
13163 ra
= (reglist
>> 27) & 0x10;
13164 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13166 if ((reglist
& -reglist
) != reglist
)
13169 imm
= (ffs (reglist
) - 1) | ra
;
13170 INSERT_OPERAND (1, RT
, *ip
, imm
);
13171 imm_expr
.X_op
= O_absent
;
13175 case '|': /* 4-bit trap code. */
13176 gas_assert (mips_opts
.micromips
);
13177 my_getExpression (&imm_expr
, s
);
13178 check_absolute_expr (ip
, &imm_expr
);
13179 if ((unsigned long) imm_expr
.X_add_number
13180 > MICROMIPSOP_MASK_TRAP
)
13181 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13182 (unsigned long) imm_expr
.X_add_number
,
13183 ip
->insn_mo
->name
);
13184 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13185 imm_expr
.X_op
= O_absent
;
13190 as_bad (_("Bad char = '%c'\n"), *args
);
13195 /* Args don't match. */
13197 insn_error
= _("Illegal operands");
13198 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13203 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13205 gas_assert (firstinsn
);
13206 need_delay_slot_ok
= FALSE
;
13215 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13217 /* This routine assembles an instruction into its binary format when
13218 assembling for the mips16. As a side effect, it sets one of the
13219 global variables imm_reloc or offset_reloc to the type of relocation
13220 to do if one of the operands is an address expression. It also sets
13221 forced_insn_length to the resulting instruction size in bytes if the
13222 user explicitly requested a small or extended instruction. */
13225 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13229 struct mips_opcode
*insn
;
13231 unsigned int regno
;
13232 unsigned int lastregno
= 0;
13238 forced_insn_length
= 0;
13240 for (s
= str
; ISLOWER (*s
); ++s
)
13252 if (s
[1] == 't' && s
[2] == ' ')
13255 forced_insn_length
= 2;
13259 else if (s
[1] == 'e' && s
[2] == ' ')
13262 forced_insn_length
= 4;
13266 /* Fall through. */
13268 insn_error
= _("unknown opcode");
13272 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13273 forced_insn_length
= 2;
13275 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13277 insn_error
= _("unrecognized opcode");
13286 gas_assert (strcmp (insn
->name
, str
) == 0);
13288 ok
= is_opcode_valid_16 (insn
);
13291 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13292 && strcmp (insn
->name
, insn
[1].name
) == 0)
13301 static char buf
[100];
13303 _("Opcode not supported on this processor: %s (%s)"),
13304 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13305 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13312 create_insn (ip
, insn
);
13313 imm_expr
.X_op
= O_absent
;
13314 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13315 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13316 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13317 imm2_expr
.X_op
= O_absent
;
13318 offset_expr
.X_op
= O_absent
;
13319 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13320 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13321 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13322 for (args
= insn
->args
; 1; ++args
)
13329 /* In this switch statement we call break if we did not find
13330 a match, continue if we did find a match, or return if we
13339 /* Stuff the immediate value in now, if we can. */
13340 if (imm_expr
.X_op
== O_constant
13341 && *imm_reloc
> BFD_RELOC_UNUSED
13342 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
13343 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
13344 && insn
->pinfo
!= INSN_MACRO
)
13348 switch (*offset_reloc
)
13350 case BFD_RELOC_MIPS16_HI16_S
:
13351 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
13354 case BFD_RELOC_MIPS16_HI16
:
13355 tmp
= imm_expr
.X_add_number
>> 16;
13358 case BFD_RELOC_MIPS16_LO16
:
13359 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
13363 case BFD_RELOC_UNUSED
:
13364 tmp
= imm_expr
.X_add_number
;
13370 *offset_reloc
= BFD_RELOC_UNUSED
;
13372 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13373 tmp
, TRUE
, forced_insn_length
== 2,
13374 forced_insn_length
== 4, &ip
->insn_opcode
,
13375 &ip
->use_extend
, &ip
->extend
);
13376 imm_expr
.X_op
= O_absent
;
13377 *imm_reloc
= BFD_RELOC_UNUSED
;
13391 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13394 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13410 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13412 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13416 /* Fall through. */
13427 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13429 if (c
== 'v' || c
== 'w')
13432 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13434 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13445 if (c
== 'v' || c
== 'w')
13447 regno
= mips16_to_32_reg_map
[lastregno
];
13461 regno
= mips32_to_16_reg_map
[regno
];
13466 regno
= ILLEGAL_REG
;
13471 regno
= ILLEGAL_REG
;
13476 regno
= ILLEGAL_REG
;
13481 if (regno
== AT
&& mips_opts
.at
)
13483 if (mips_opts
.at
== ATREG
)
13484 as_warn (_("used $at without \".set noat\""));
13486 as_warn (_("used $%u with \".set at=$%u\""),
13487 regno
, mips_opts
.at
);
13495 if (regno
== ILLEGAL_REG
)
13502 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13506 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13509 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13512 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13518 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13521 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13522 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13532 if (strncmp (s
, "$pc", 3) == 0)
13549 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13552 if (imm_expr
.X_op
!= O_constant
)
13554 forced_insn_length
= 4;
13555 ip
->use_extend
= TRUE
;
13560 /* We need to relax this instruction. */
13561 *offset_reloc
= *imm_reloc
;
13562 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13567 *imm_reloc
= BFD_RELOC_UNUSED
;
13568 /* Fall through. */
13575 my_getExpression (&imm_expr
, s
);
13576 if (imm_expr
.X_op
== O_register
)
13578 /* What we thought was an expression turned out to
13581 if (s
[0] == '(' && args
[1] == '(')
13583 /* It looks like the expression was omitted
13584 before a register indirection, which means
13585 that the expression is implicitly zero. We
13586 still set up imm_expr, so that we handle
13587 explicit extensions correctly. */
13588 imm_expr
.X_op
= O_constant
;
13589 imm_expr
.X_add_number
= 0;
13590 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13597 /* We need to relax this instruction. */
13598 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13607 /* We use offset_reloc rather than imm_reloc for the PC
13608 relative operands. This lets macros with both
13609 immediate and address operands work correctly. */
13610 my_getExpression (&offset_expr
, s
);
13612 if (offset_expr
.X_op
== O_register
)
13615 /* We need to relax this instruction. */
13616 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13620 case '6': /* break code */
13621 my_getExpression (&imm_expr
, s
);
13622 check_absolute_expr (ip
, &imm_expr
);
13623 if ((unsigned long) imm_expr
.X_add_number
> 63)
13624 as_warn (_("Invalid value for `%s' (%lu)"),
13626 (unsigned long) imm_expr
.X_add_number
);
13627 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13628 imm_expr
.X_op
= O_absent
;
13632 case 'a': /* 26 bit address */
13633 my_getExpression (&offset_expr
, s
);
13635 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13636 ip
->insn_opcode
<<= 16;
13639 case 'l': /* register list for entry macro */
13640 case 'L': /* register list for exit macro */
13650 unsigned int freg
, reg1
, reg2
;
13652 while (*s
== ' ' || *s
== ',')
13654 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13656 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13660 as_bad (_("can't parse register list"));
13670 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13671 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13673 as_bad (_("invalid register list"));
13677 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13679 mask
&= ~ (7 << 3);
13682 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13684 mask
&= ~ (7 << 3);
13687 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13688 mask
|= (reg2
- 3) << 3;
13689 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13690 mask
|= (reg2
- 15) << 1;
13691 else if (reg1
== RA
&& reg2
== RA
)
13695 as_bad (_("invalid register list"));
13699 /* The mask is filled in in the opcode table for the
13700 benefit of the disassembler. We remove it before
13701 applying the actual mask. */
13702 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13703 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13707 case 'm': /* Register list for save insn. */
13708 case 'M': /* Register list for restore insn. */
13711 int framesz
= 0, seen_framesz
= 0;
13712 int nargs
= 0, statics
= 0, sregs
= 0;
13716 unsigned int reg1
, reg2
;
13718 SKIP_SPACE_TABS (s
);
13721 SKIP_SPACE_TABS (s
);
13723 my_getExpression (&imm_expr
, s
);
13724 if (imm_expr
.X_op
== O_constant
)
13726 /* Handle the frame size. */
13729 as_bad (_("more than one frame size in list"));
13733 framesz
= imm_expr
.X_add_number
;
13734 imm_expr
.X_op
= O_absent
;
13739 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13741 as_bad (_("can't parse register list"));
13753 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13756 as_bad (_("can't parse register list"));
13761 while (reg1
<= reg2
)
13763 if (reg1
>= 4 && reg1
<= 7)
13767 nargs
|= 1 << (reg1
- 4);
13769 /* statics $a0-$a3 */
13770 statics
|= 1 << (reg1
- 4);
13772 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13775 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13777 else if (reg1
== 31)
13779 /* Add $ra to insn. */
13784 as_bad (_("unexpected register in list"));
13792 /* Encode args/statics combination. */
13793 if (nargs
& statics
)
13794 as_bad (_("arg/static registers overlap"));
13795 else if (nargs
== 0xf)
13796 /* All $a0-$a3 are args. */
13797 opcode
|= MIPS16_ALL_ARGS
<< 16;
13798 else if (statics
== 0xf)
13799 /* All $a0-$a3 are statics. */
13800 opcode
|= MIPS16_ALL_STATICS
<< 16;
13803 int narg
= 0, nstat
= 0;
13805 /* Count arg registers. */
13806 while (nargs
& 0x1)
13812 as_bad (_("invalid arg register list"));
13814 /* Count static registers. */
13815 while (statics
& 0x8)
13817 statics
= (statics
<< 1) & 0xf;
13821 as_bad (_("invalid static register list"));
13823 /* Encode args/statics. */
13824 opcode
|= ((narg
<< 2) | nstat
) << 16;
13827 /* Encode $s0/$s1. */
13828 if (sregs
& (1 << 0)) /* $s0 */
13830 if (sregs
& (1 << 1)) /* $s1 */
13836 /* Count regs $s2-$s8. */
13844 as_bad (_("invalid static register list"));
13845 /* Encode $s2-$s8. */
13846 opcode
|= nsreg
<< 24;
13849 /* Encode frame size. */
13851 as_bad (_("missing frame size"));
13852 else if ((framesz
& 7) != 0 || framesz
< 0
13853 || framesz
> 0xff * 8)
13854 as_bad (_("invalid frame size"));
13855 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13858 opcode
|= (((framesz
& 0xf0) << 16)
13859 | (framesz
& 0x0f));
13862 /* Finally build the instruction. */
13863 if ((opcode
>> 16) != 0 || framesz
== 0)
13865 ip
->use_extend
= TRUE
;
13866 ip
->extend
= opcode
>> 16;
13868 ip
->insn_opcode
|= opcode
& 0x7f;
13872 case 'e': /* extend code */
13873 my_getExpression (&imm_expr
, s
);
13874 check_absolute_expr (ip
, &imm_expr
);
13875 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13877 as_warn (_("Invalid value for `%s' (%lu)"),
13879 (unsigned long) imm_expr
.X_add_number
);
13880 imm_expr
.X_add_number
&= 0x7ff;
13882 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13883 imm_expr
.X_op
= O_absent
;
13893 /* Args don't match. */
13894 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13895 strcmp (insn
->name
, insn
[1].name
) == 0)
13902 insn_error
= _("illegal operands");
13908 /* This structure holds information we know about a mips16 immediate
13911 struct mips16_immed_operand
13913 /* The type code used in the argument string in the opcode table. */
13915 /* The number of bits in the short form of the opcode. */
13917 /* The number of bits in the extended form of the opcode. */
13919 /* The amount by which the short form is shifted when it is used;
13920 for example, the sw instruction has a shift count of 2. */
13922 /* The amount by which the short form is shifted when it is stored
13923 into the instruction code. */
13925 /* Non-zero if the short form is unsigned. */
13927 /* Non-zero if the extended form is unsigned. */
13929 /* Non-zero if the value is PC relative. */
13933 /* The mips16 immediate operand types. */
13935 static const struct mips16_immed_operand mips16_immed_operands
[] =
13937 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13938 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13939 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13940 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13941 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13942 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13943 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13944 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13945 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13946 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13947 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13948 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13949 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13950 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13951 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13952 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13953 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13954 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13955 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13956 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13957 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13960 #define MIPS16_NUM_IMMED \
13961 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13963 /* Handle a mips16 instruction with an immediate value. This or's the
13964 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13965 whether an extended value is needed; if one is needed, it sets
13966 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13967 If SMALL is true, an unextended opcode was explicitly requested.
13968 If EXT is true, an extended opcode was explicitly requested. If
13969 WARN is true, warn if EXT does not match reality. */
13972 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
13973 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
13974 unsigned long *insn
, bfd_boolean
*use_extend
,
13975 unsigned short *extend
)
13977 const struct mips16_immed_operand
*op
;
13978 int mintiny
, maxtiny
;
13979 bfd_boolean needext
;
13981 op
= mips16_immed_operands
;
13982 while (op
->type
!= type
)
13985 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13990 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13993 maxtiny
= 1 << op
->nbits
;
13998 maxtiny
= (1 << op
->nbits
) - 1;
14003 mintiny
= - (1 << (op
->nbits
- 1));
14004 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14007 /* Branch offsets have an implicit 0 in the lowest bit. */
14008 if (type
== 'p' || type
== 'q')
14011 if ((val
& ((1 << op
->shift
) - 1)) != 0
14012 || val
< (mintiny
<< op
->shift
)
14013 || val
> (maxtiny
<< op
->shift
))
14018 if (warn
&& ext
&& ! needext
)
14019 as_warn_where (file
, line
,
14020 _("extended operand requested but not required"));
14021 if (small
&& needext
)
14022 as_bad_where (file
, line
, _("invalid unextended operand value"));
14024 if (small
|| (! ext
&& ! needext
))
14028 *use_extend
= FALSE
;
14029 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14030 insnval
<<= op
->op_shift
;
14035 long minext
, maxext
;
14041 maxext
= (1 << op
->extbits
) - 1;
14045 minext
= - (1 << (op
->extbits
- 1));
14046 maxext
= (1 << (op
->extbits
- 1)) - 1;
14048 if (val
< minext
|| val
> maxext
)
14049 as_bad_where (file
, line
,
14050 _("operand value out of range for instruction"));
14052 *use_extend
= TRUE
;
14053 if (op
->extbits
== 16)
14055 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14058 else if (op
->extbits
== 15)
14060 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14065 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14069 *extend
= (unsigned short) extval
;
14074 struct percent_op_match
14077 bfd_reloc_code_real_type reloc
;
14080 static const struct percent_op_match mips_percent_op
[] =
14082 {"%lo", BFD_RELOC_LO16
},
14084 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14085 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14086 {"%call16", BFD_RELOC_MIPS_CALL16
},
14087 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14088 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14089 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14090 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14091 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14092 {"%got", BFD_RELOC_MIPS_GOT16
},
14093 {"%gp_rel", BFD_RELOC_GPREL16
},
14094 {"%half", BFD_RELOC_16
},
14095 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14096 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14097 {"%neg", BFD_RELOC_MIPS_SUB
},
14098 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14099 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14100 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14101 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14102 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14103 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14104 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14106 {"%hi", BFD_RELOC_HI16_S
}
14109 static const struct percent_op_match mips16_percent_op
[] =
14111 {"%lo", BFD_RELOC_MIPS16_LO16
},
14112 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14113 {"%got", BFD_RELOC_MIPS16_GOT16
},
14114 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14115 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14116 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14117 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14118 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14119 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14120 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14121 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14122 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14126 /* Return true if *STR points to a relocation operator. When returning true,
14127 move *STR over the operator and store its relocation code in *RELOC.
14128 Leave both *STR and *RELOC alone when returning false. */
14131 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14133 const struct percent_op_match
*percent_op
;
14136 if (mips_opts
.mips16
)
14138 percent_op
= mips16_percent_op
;
14139 limit
= ARRAY_SIZE (mips16_percent_op
);
14143 percent_op
= mips_percent_op
;
14144 limit
= ARRAY_SIZE (mips_percent_op
);
14147 for (i
= 0; i
< limit
; i
++)
14148 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14150 int len
= strlen (percent_op
[i
].str
);
14152 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14155 *str
+= strlen (percent_op
[i
].str
);
14156 *reloc
= percent_op
[i
].reloc
;
14158 /* Check whether the output BFD supports this relocation.
14159 If not, issue an error and fall back on something safe. */
14160 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14162 as_bad (_("relocation %s isn't supported by the current ABI"),
14163 percent_op
[i
].str
);
14164 *reloc
= BFD_RELOC_UNUSED
;
14172 /* Parse string STR as a 16-bit relocatable operand. Store the
14173 expression in *EP and the relocations in the array starting
14174 at RELOC. Return the number of relocation operators used.
14176 On exit, EXPR_END points to the first character after the expression. */
14179 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14182 bfd_reloc_code_real_type reversed_reloc
[3];
14183 size_t reloc_index
, i
;
14184 int crux_depth
, str_depth
;
14187 /* Search for the start of the main expression, recoding relocations
14188 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14189 of the main expression and with CRUX_DEPTH containing the number
14190 of open brackets at that point. */
14197 crux_depth
= str_depth
;
14199 /* Skip over whitespace and brackets, keeping count of the number
14201 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14206 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14207 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14209 my_getExpression (ep
, crux
);
14212 /* Match every open bracket. */
14213 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14217 if (crux_depth
> 0)
14218 as_bad (_("unclosed '('"));
14222 if (reloc_index
!= 0)
14224 prev_reloc_op_frag
= frag_now
;
14225 for (i
= 0; i
< reloc_index
; i
++)
14226 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14229 return reloc_index
;
14233 my_getExpression (expressionS
*ep
, char *str
)
14237 save_in
= input_line_pointer
;
14238 input_line_pointer
= str
;
14240 expr_end
= input_line_pointer
;
14241 input_line_pointer
= save_in
;
14245 md_atof (int type
, char *litP
, int *sizeP
)
14247 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14251 md_number_to_chars (char *buf
, valueT val
, int n
)
14253 if (target_big_endian
)
14254 number_to_chars_bigendian (buf
, val
, n
);
14256 number_to_chars_littleendian (buf
, val
, n
);
14260 static int support_64bit_objects(void)
14262 const char **list
, **l
;
14265 list
= bfd_target_list ();
14266 for (l
= list
; *l
!= NULL
; l
++)
14267 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14268 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14270 yes
= (*l
!= NULL
);
14274 #endif /* OBJ_ELF */
14276 const char *md_shortopts
= "O::g::G:";
14280 OPTION_MARCH
= OPTION_MD_BASE
,
14302 OPTION_NO_SMARTMIPS
,
14306 OPTION_NO_MICROMIPS
,
14309 OPTION_COMPAT_ARCH_BASE
,
14318 OPTION_M7000_HILO_FIX
,
14319 OPTION_MNO_7000_HILO_FIX
,
14322 OPTION_FIX_LOONGSON2F_JUMP
,
14323 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14324 OPTION_FIX_LOONGSON2F_NOP
,
14325 OPTION_NO_FIX_LOONGSON2F_NOP
,
14327 OPTION_NO_FIX_VR4120
,
14329 OPTION_NO_FIX_VR4130
,
14330 OPTION_FIX_CN63XXP1
,
14331 OPTION_NO_FIX_CN63XXP1
,
14338 OPTION_CONSTRUCT_FLOATS
,
14339 OPTION_NO_CONSTRUCT_FLOATS
,
14342 OPTION_RELAX_BRANCH
,
14343 OPTION_NO_RELAX_BRANCH
,
14350 OPTION_SINGLE_FLOAT
,
14351 OPTION_DOUBLE_FLOAT
,
14354 OPTION_CALL_SHARED
,
14355 OPTION_CALL_NONPIC
,
14365 OPTION_MVXWORKS_PIC
,
14366 #endif /* OBJ_ELF */
14370 struct option md_longopts
[] =
14372 /* Options which specify architecture. */
14373 {"march", required_argument
, NULL
, OPTION_MARCH
},
14374 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14375 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14376 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14377 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14378 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14379 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14380 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14381 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14382 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14383 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14384 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14386 /* Options which specify Application Specific Extensions (ASEs). */
14387 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14388 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14389 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14390 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14391 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14392 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14393 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14394 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14395 {"mmt", no_argument
, NULL
, OPTION_MT
},
14396 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14397 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14398 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14399 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14400 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14401 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14402 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14403 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14404 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14406 /* Old-style architecture options. Don't add more of these. */
14407 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14408 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14409 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14410 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14411 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14412 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14413 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14414 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14416 /* Options which enable bug fixes. */
14417 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14418 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14419 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14420 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14421 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14422 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14423 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14424 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14425 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14426 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14427 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14428 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14429 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14430 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14431 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14433 /* Miscellaneous options. */
14434 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14435 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14436 {"break", no_argument
, NULL
, OPTION_BREAK
},
14437 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14438 {"EB", no_argument
, NULL
, OPTION_EB
},
14439 {"EL", no_argument
, NULL
, OPTION_EL
},
14440 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14441 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14442 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14443 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14444 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14445 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14446 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14447 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14448 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14449 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14450 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14451 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14452 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14453 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14454 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14455 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14457 /* Strictly speaking this next option is ELF specific,
14458 but we allow it for other ports as well in order to
14459 make testing easier. */
14460 {"32", no_argument
, NULL
, OPTION_32
},
14462 /* ELF-specific options. */
14464 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14465 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14466 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14467 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14468 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14469 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14470 {"n32", no_argument
, NULL
, OPTION_N32
},
14471 {"64", no_argument
, NULL
, OPTION_64
},
14472 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14473 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14474 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14475 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14476 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14477 #endif /* OBJ_ELF */
14479 {NULL
, no_argument
, NULL
, 0}
14481 size_t md_longopts_size
= sizeof (md_longopts
);
14483 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14484 NEW_VALUE. Warn if another value was already specified. Note:
14485 we have to defer parsing the -march and -mtune arguments in order
14486 to handle 'from-abi' correctly, since the ABI might be specified
14487 in a later argument. */
14490 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14492 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14493 as_warn (_("A different %s was already specified, is now %s"),
14494 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14497 *string_ptr
= new_value
;
14501 md_parse_option (int c
, char *arg
)
14505 case OPTION_CONSTRUCT_FLOATS
:
14506 mips_disable_float_construction
= 0;
14509 case OPTION_NO_CONSTRUCT_FLOATS
:
14510 mips_disable_float_construction
= 1;
14522 target_big_endian
= 1;
14526 target_big_endian
= 0;
14532 else if (arg
[0] == '0')
14534 else if (arg
[0] == '1')
14544 mips_debug
= atoi (arg
);
14548 file_mips_isa
= ISA_MIPS1
;
14552 file_mips_isa
= ISA_MIPS2
;
14556 file_mips_isa
= ISA_MIPS3
;
14560 file_mips_isa
= ISA_MIPS4
;
14564 file_mips_isa
= ISA_MIPS5
;
14567 case OPTION_MIPS32
:
14568 file_mips_isa
= ISA_MIPS32
;
14571 case OPTION_MIPS32R2
:
14572 file_mips_isa
= ISA_MIPS32R2
;
14575 case OPTION_MIPS64R2
:
14576 file_mips_isa
= ISA_MIPS64R2
;
14579 case OPTION_MIPS64
:
14580 file_mips_isa
= ISA_MIPS64
;
14584 mips_set_option_string (&mips_tune_string
, arg
);
14588 mips_set_option_string (&mips_arch_string
, arg
);
14592 mips_set_option_string (&mips_arch_string
, "4650");
14593 mips_set_option_string (&mips_tune_string
, "4650");
14596 case OPTION_NO_M4650
:
14600 mips_set_option_string (&mips_arch_string
, "4010");
14601 mips_set_option_string (&mips_tune_string
, "4010");
14604 case OPTION_NO_M4010
:
14608 mips_set_option_string (&mips_arch_string
, "4100");
14609 mips_set_option_string (&mips_tune_string
, "4100");
14612 case OPTION_NO_M4100
:
14616 mips_set_option_string (&mips_arch_string
, "3900");
14617 mips_set_option_string (&mips_tune_string
, "3900");
14620 case OPTION_NO_M3900
:
14624 mips_opts
.ase_mdmx
= 1;
14627 case OPTION_NO_MDMX
:
14628 mips_opts
.ase_mdmx
= 0;
14632 mips_opts
.ase_dsp
= 1;
14633 mips_opts
.ase_dspr2
= 0;
14636 case OPTION_NO_DSP
:
14637 mips_opts
.ase_dsp
= 0;
14638 mips_opts
.ase_dspr2
= 0;
14642 mips_opts
.ase_dspr2
= 1;
14643 mips_opts
.ase_dsp
= 1;
14646 case OPTION_NO_DSPR2
:
14647 mips_opts
.ase_dspr2
= 0;
14648 mips_opts
.ase_dsp
= 0;
14652 mips_opts
.ase_mt
= 1;
14656 mips_opts
.ase_mt
= 0;
14660 mips_opts
.ase_mcu
= 1;
14663 case OPTION_NO_MCU
:
14664 mips_opts
.ase_mcu
= 0;
14667 case OPTION_MICROMIPS
:
14668 if (mips_opts
.mips16
== 1)
14670 as_bad (_("-mmicromips cannot be used with -mips16"));
14673 mips_opts
.micromips
= 1;
14674 mips_no_prev_insn ();
14677 case OPTION_NO_MICROMIPS
:
14678 mips_opts
.micromips
= 0;
14679 mips_no_prev_insn ();
14682 case OPTION_MIPS16
:
14683 if (mips_opts
.micromips
== 1)
14685 as_bad (_("-mips16 cannot be used with -micromips"));
14688 mips_opts
.mips16
= 1;
14689 mips_no_prev_insn ();
14692 case OPTION_NO_MIPS16
:
14693 mips_opts
.mips16
= 0;
14694 mips_no_prev_insn ();
14697 case OPTION_MIPS3D
:
14698 mips_opts
.ase_mips3d
= 1;
14701 case OPTION_NO_MIPS3D
:
14702 mips_opts
.ase_mips3d
= 0;
14705 case OPTION_SMARTMIPS
:
14706 mips_opts
.ase_smartmips
= 1;
14709 case OPTION_NO_SMARTMIPS
:
14710 mips_opts
.ase_smartmips
= 0;
14713 case OPTION_FIX_24K
:
14717 case OPTION_NO_FIX_24K
:
14721 case OPTION_FIX_LOONGSON2F_JUMP
:
14722 mips_fix_loongson2f_jump
= TRUE
;
14725 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14726 mips_fix_loongson2f_jump
= FALSE
;
14729 case OPTION_FIX_LOONGSON2F_NOP
:
14730 mips_fix_loongson2f_nop
= TRUE
;
14733 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14734 mips_fix_loongson2f_nop
= FALSE
;
14737 case OPTION_FIX_VR4120
:
14738 mips_fix_vr4120
= 1;
14741 case OPTION_NO_FIX_VR4120
:
14742 mips_fix_vr4120
= 0;
14745 case OPTION_FIX_VR4130
:
14746 mips_fix_vr4130
= 1;
14749 case OPTION_NO_FIX_VR4130
:
14750 mips_fix_vr4130
= 0;
14753 case OPTION_FIX_CN63XXP1
:
14754 mips_fix_cn63xxp1
= TRUE
;
14757 case OPTION_NO_FIX_CN63XXP1
:
14758 mips_fix_cn63xxp1
= FALSE
;
14761 case OPTION_RELAX_BRANCH
:
14762 mips_relax_branch
= 1;
14765 case OPTION_NO_RELAX_BRANCH
:
14766 mips_relax_branch
= 0;
14769 case OPTION_MSHARED
:
14770 mips_in_shared
= TRUE
;
14773 case OPTION_MNO_SHARED
:
14774 mips_in_shared
= FALSE
;
14777 case OPTION_MSYM32
:
14778 mips_opts
.sym32
= TRUE
;
14781 case OPTION_MNO_SYM32
:
14782 mips_opts
.sym32
= FALSE
;
14786 /* When generating ELF code, we permit -KPIC and -call_shared to
14787 select SVR4_PIC, and -non_shared to select no PIC. This is
14788 intended to be compatible with Irix 5. */
14789 case OPTION_CALL_SHARED
:
14792 as_bad (_("-call_shared is supported only for ELF format"));
14795 mips_pic
= SVR4_PIC
;
14796 mips_abicalls
= TRUE
;
14799 case OPTION_CALL_NONPIC
:
14802 as_bad (_("-call_nonpic is supported only for ELF format"));
14806 mips_abicalls
= TRUE
;
14809 case OPTION_NON_SHARED
:
14812 as_bad (_("-non_shared is supported only for ELF format"));
14816 mips_abicalls
= FALSE
;
14819 /* The -xgot option tells the assembler to use 32 bit offsets
14820 when accessing the got in SVR4_PIC mode. It is for Irix
14825 #endif /* OBJ_ELF */
14828 g_switch_value
= atoi (arg
);
14832 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14836 mips_abi
= O32_ABI
;
14837 /* We silently ignore -32 for non-ELF targets. This greatly
14838 simplifies the construction of the MIPS GAS test cases. */
14845 as_bad (_("-n32 is supported for ELF format only"));
14848 mips_abi
= N32_ABI
;
14854 as_bad (_("-64 is supported for ELF format only"));
14857 mips_abi
= N64_ABI
;
14858 if (!support_64bit_objects())
14859 as_fatal (_("No compiled in support for 64 bit object file format"));
14861 #endif /* OBJ_ELF */
14864 file_mips_gp32
= 1;
14868 file_mips_gp32
= 0;
14872 file_mips_fp32
= 1;
14876 file_mips_fp32
= 0;
14879 case OPTION_SINGLE_FLOAT
:
14880 file_mips_single_float
= 1;
14883 case OPTION_DOUBLE_FLOAT
:
14884 file_mips_single_float
= 0;
14887 case OPTION_SOFT_FLOAT
:
14888 file_mips_soft_float
= 1;
14891 case OPTION_HARD_FLOAT
:
14892 file_mips_soft_float
= 0;
14899 as_bad (_("-mabi is supported for ELF format only"));
14902 if (strcmp (arg
, "32") == 0)
14903 mips_abi
= O32_ABI
;
14904 else if (strcmp (arg
, "o64") == 0)
14905 mips_abi
= O64_ABI
;
14906 else if (strcmp (arg
, "n32") == 0)
14907 mips_abi
= N32_ABI
;
14908 else if (strcmp (arg
, "64") == 0)
14910 mips_abi
= N64_ABI
;
14911 if (! support_64bit_objects())
14912 as_fatal (_("No compiled in support for 64 bit object file "
14915 else if (strcmp (arg
, "eabi") == 0)
14916 mips_abi
= EABI_ABI
;
14919 as_fatal (_("invalid abi -mabi=%s"), arg
);
14923 #endif /* OBJ_ELF */
14925 case OPTION_M7000_HILO_FIX
:
14926 mips_7000_hilo_fix
= TRUE
;
14929 case OPTION_MNO_7000_HILO_FIX
:
14930 mips_7000_hilo_fix
= FALSE
;
14934 case OPTION_MDEBUG
:
14935 mips_flag_mdebug
= TRUE
;
14938 case OPTION_NO_MDEBUG
:
14939 mips_flag_mdebug
= FALSE
;
14943 mips_flag_pdr
= TRUE
;
14946 case OPTION_NO_PDR
:
14947 mips_flag_pdr
= FALSE
;
14950 case OPTION_MVXWORKS_PIC
:
14951 mips_pic
= VXWORKS_PIC
;
14953 #endif /* OBJ_ELF */
14959 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14964 /* Set up globals to generate code for the ISA or processor
14965 described by INFO. */
14968 mips_set_architecture (const struct mips_cpu_info
*info
)
14972 file_mips_arch
= info
->cpu
;
14973 mips_opts
.arch
= info
->cpu
;
14974 mips_opts
.isa
= info
->isa
;
14979 /* Likewise for tuning. */
14982 mips_set_tune (const struct mips_cpu_info
*info
)
14985 mips_tune
= info
->cpu
;
14990 mips_after_parse_args (void)
14992 const struct mips_cpu_info
*arch_info
= 0;
14993 const struct mips_cpu_info
*tune_info
= 0;
14995 /* GP relative stuff not working for PE */
14996 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14998 if (g_switch_seen
&& g_switch_value
!= 0)
14999 as_bad (_("-G not supported in this configuration."));
15000 g_switch_value
= 0;
15003 if (mips_abi
== NO_ABI
)
15004 mips_abi
= MIPS_DEFAULT_ABI
;
15006 /* The following code determines the architecture and register size.
15007 Similar code was added to GCC 3.3 (see override_options() in
15008 config/mips/mips.c). The GAS and GCC code should be kept in sync
15009 as much as possible. */
15011 if (mips_arch_string
!= 0)
15012 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15014 if (file_mips_isa
!= ISA_UNKNOWN
)
15016 /* Handle -mipsN. At this point, file_mips_isa contains the
15017 ISA level specified by -mipsN, while arch_info->isa contains
15018 the -march selection (if any). */
15019 if (arch_info
!= 0)
15021 /* -march takes precedence over -mipsN, since it is more descriptive.
15022 There's no harm in specifying both as long as the ISA levels
15024 if (file_mips_isa
!= arch_info
->isa
)
15025 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15026 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15027 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15030 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15033 if (arch_info
== 0)
15035 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15036 gas_assert (arch_info
);
15039 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15040 as_bad (_("-march=%s is not compatible with the selected ABI"),
15043 mips_set_architecture (arch_info
);
15045 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15046 if (mips_tune_string
!= 0)
15047 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15049 if (tune_info
== 0)
15050 mips_set_tune (arch_info
);
15052 mips_set_tune (tune_info
);
15054 if (file_mips_gp32
>= 0)
15056 /* The user specified the size of the integer registers. Make sure
15057 it agrees with the ABI and ISA. */
15058 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15059 as_bad (_("-mgp64 used with a 32-bit processor"));
15060 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15061 as_bad (_("-mgp32 used with a 64-bit ABI"));
15062 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15063 as_bad (_("-mgp64 used with a 32-bit ABI"));
15067 /* Infer the integer register size from the ABI and processor.
15068 Restrict ourselves to 32-bit registers if that's all the
15069 processor has, or if the ABI cannot handle 64-bit registers. */
15070 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15071 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15074 switch (file_mips_fp32
)
15078 /* No user specified float register size.
15079 ??? GAS treats single-float processors as though they had 64-bit
15080 float registers (although it complains when double-precision
15081 instructions are used). As things stand, saying they have 32-bit
15082 registers would lead to spurious "register must be even" messages.
15083 So here we assume float registers are never smaller than the
15085 if (file_mips_gp32
== 0)
15086 /* 64-bit integer registers implies 64-bit float registers. */
15087 file_mips_fp32
= 0;
15088 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15089 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15090 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15091 file_mips_fp32
= 0;
15093 /* 32-bit float registers. */
15094 file_mips_fp32
= 1;
15097 /* The user specified the size of the float registers. Check if it
15098 agrees with the ABI and ISA. */
15100 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15101 as_bad (_("-mfp64 used with a 32-bit fpu"));
15102 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15103 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15104 as_warn (_("-mfp64 used with a 32-bit ABI"));
15107 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15108 as_warn (_("-mfp32 used with a 64-bit ABI"));
15112 /* End of GCC-shared inference code. */
15114 /* This flag is set when we have a 64-bit capable CPU but use only
15115 32-bit wide registers. Note that EABI does not use it. */
15116 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15117 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15118 || mips_abi
== O32_ABI
))
15119 mips_32bitmode
= 1;
15121 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15122 as_bad (_("trap exception not supported at ISA 1"));
15124 /* If the selected architecture includes support for ASEs, enable
15125 generation of code for them. */
15126 if (mips_opts
.mips16
== -1)
15127 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15128 if (mips_opts
.micromips
== -1)
15129 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15130 if (mips_opts
.ase_mips3d
== -1)
15131 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15132 && file_mips_fp32
== 0) ? 1 : 0;
15133 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15134 as_bad (_("-mfp32 used with -mips3d"));
15136 if (mips_opts
.ase_mdmx
== -1)
15137 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15138 && file_mips_fp32
== 0) ? 1 : 0;
15139 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15140 as_bad (_("-mfp32 used with -mdmx"));
15142 if (mips_opts
.ase_smartmips
== -1)
15143 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15144 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15145 as_warn (_("%s ISA does not support SmartMIPS"),
15146 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15148 if (mips_opts
.ase_dsp
== -1)
15149 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15150 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15151 as_warn (_("%s ISA does not support DSP ASE"),
15152 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15154 if (mips_opts
.ase_dspr2
== -1)
15156 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15157 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15159 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15160 as_warn (_("%s ISA does not support DSP R2 ASE"),
15161 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15163 if (mips_opts
.ase_mt
== -1)
15164 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15165 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15166 as_warn (_("%s ISA does not support MT ASE"),
15167 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15169 if (mips_opts
.ase_mcu
== -1)
15170 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15171 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15172 as_warn (_("%s ISA does not support MCU ASE"),
15173 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15175 file_mips_isa
= mips_opts
.isa
;
15176 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15177 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15178 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15179 file_ase_dsp
= mips_opts
.ase_dsp
;
15180 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15181 file_ase_mt
= mips_opts
.ase_mt
;
15182 mips_opts
.gp32
= file_mips_gp32
;
15183 mips_opts
.fp32
= file_mips_fp32
;
15184 mips_opts
.soft_float
= file_mips_soft_float
;
15185 mips_opts
.single_float
= file_mips_single_float
;
15187 if (mips_flag_mdebug
< 0)
15189 #ifdef OBJ_MAYBE_ECOFF
15190 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15191 mips_flag_mdebug
= 1;
15193 #endif /* OBJ_MAYBE_ECOFF */
15194 mips_flag_mdebug
= 0;
15199 mips_init_after_args (void)
15201 /* initialize opcodes */
15202 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15203 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15207 md_pcrel_from (fixS
*fixP
)
15209 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15210 switch (fixP
->fx_r_type
)
15212 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15213 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15214 /* Return the address of the delay slot. */
15217 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15218 case BFD_RELOC_MICROMIPS_JMP
:
15219 case BFD_RELOC_16_PCREL_S2
:
15220 case BFD_RELOC_MIPS_JMP
:
15221 /* Return the address of the delay slot. */
15225 /* We have no relocation type for PC relative MIPS16 instructions. */
15226 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15228 _("PC relative MIPS16 instruction references a different section"));
15233 /* This is called before the symbol table is processed. In order to
15234 work with gcc when using mips-tfile, we must keep all local labels.
15235 However, in other cases, we want to discard them. If we were
15236 called with -g, but we didn't see any debugging information, it may
15237 mean that gcc is smuggling debugging information through to
15238 mips-tfile, in which case we must generate all local labels. */
15241 mips_frob_file_before_adjust (void)
15243 #ifndef NO_ECOFF_DEBUGGING
15244 if (ECOFF_DEBUGGING
15246 && ! ecoff_debugging_seen
)
15247 flag_keep_locals
= 1;
15251 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15252 the corresponding LO16 reloc. This is called before md_apply_fix and
15253 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15254 relocation operators.
15256 For our purposes, a %lo() expression matches a %got() or %hi()
15259 (a) it refers to the same symbol; and
15260 (b) the offset applied in the %lo() expression is no lower than
15261 the offset applied in the %got() or %hi().
15263 (b) allows us to cope with code like:
15266 lh $4,%lo(foo+2)($4)
15268 ...which is legal on RELA targets, and has a well-defined behaviour
15269 if the user knows that adding 2 to "foo" will not induce a carry to
15272 When several %lo()s match a particular %got() or %hi(), we use the
15273 following rules to distinguish them:
15275 (1) %lo()s with smaller offsets are a better match than %lo()s with
15278 (2) %lo()s with no matching %got() or %hi() are better than those
15279 that already have a matching %got() or %hi().
15281 (3) later %lo()s are better than earlier %lo()s.
15283 These rules are applied in order.
15285 (1) means, among other things, that %lo()s with identical offsets are
15286 chosen if they exist.
15288 (2) means that we won't associate several high-part relocations with
15289 the same low-part relocation unless there's no alternative. Having
15290 several high parts for the same low part is a GNU extension; this rule
15291 allows careful users to avoid it.
15293 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15294 with the last high-part relocation being at the front of the list.
15295 It therefore makes sense to choose the last matching low-part
15296 relocation, all other things being equal. It's also easier
15297 to code that way. */
15300 mips_frob_file (void)
15302 struct mips_hi_fixup
*l
;
15303 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15305 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15307 segment_info_type
*seginfo
;
15308 bfd_boolean matched_lo_p
;
15309 fixS
**hi_pos
, **lo_pos
, **pos
;
15311 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15313 /* If a GOT16 relocation turns out to be against a global symbol,
15314 there isn't supposed to be a matching LO. */
15315 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15316 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
15319 /* Check quickly whether the next fixup happens to be a matching %lo. */
15320 if (fixup_has_matching_lo_p (l
->fixp
))
15323 seginfo
= seg_info (l
->seg
);
15325 /* Set HI_POS to the position of this relocation in the chain.
15326 Set LO_POS to the position of the chosen low-part relocation.
15327 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15328 relocation that matches an immediately-preceding high-part
15332 matched_lo_p
= FALSE
;
15333 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15335 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15337 if (*pos
== l
->fixp
)
15340 if ((*pos
)->fx_r_type
== looking_for_rtype
15341 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15342 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15344 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15346 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15349 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15350 && fixup_has_matching_lo_p (*pos
));
15353 /* If we found a match, remove the high-part relocation from its
15354 current position and insert it before the low-part relocation.
15355 Make the offsets match so that fixup_has_matching_lo_p()
15358 We don't warn about unmatched high-part relocations since some
15359 versions of gcc have been known to emit dead "lui ...%hi(...)"
15361 if (lo_pos
!= NULL
)
15363 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15364 if (l
->fixp
->fx_next
!= *lo_pos
)
15366 *hi_pos
= l
->fixp
->fx_next
;
15367 l
->fixp
->fx_next
= *lo_pos
;
15374 /* We may have combined relocations without symbols in the N32/N64 ABI.
15375 We have to prevent gas from dropping them. */
15378 mips_force_relocation (fixS
*fixp
)
15380 if (generic_force_reloc (fixp
))
15383 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15384 so that the linker relaxation can update targets. */
15385 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15386 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15387 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15391 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
15392 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
15393 || hi16_reloc_p (fixp
->fx_r_type
)
15394 || lo16_reloc_p (fixp
->fx_r_type
)))
15400 /* Apply a fixup to the object file. */
15403 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15407 reloc_howto_type
*howto
;
15409 /* We ignore generic BFD relocations we don't know about. */
15410 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15414 gas_assert (fixP
->fx_size
== 2
15415 || fixP
->fx_size
== 4
15416 || fixP
->fx_r_type
== BFD_RELOC_16
15417 || fixP
->fx_r_type
== BFD_RELOC_64
15418 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15419 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15420 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15421 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15422 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15423 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15425 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
15427 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15428 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15429 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15430 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15432 /* Don't treat parts of a composite relocation as done. There are two
15435 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15436 should nevertheless be emitted if the first part is.
15438 (2) In normal usage, composite relocations are never assembly-time
15439 constants. The easiest way of dealing with the pathological
15440 exceptions is to generate a relocation against STN_UNDEF and
15441 leave everything up to the linker. */
15442 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15445 switch (fixP
->fx_r_type
)
15447 case BFD_RELOC_MIPS_TLS_GD
:
15448 case BFD_RELOC_MIPS_TLS_LDM
:
15449 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15450 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15451 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15452 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15453 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15454 case BFD_RELOC_MIPS_TLS_TPREL32
:
15455 case BFD_RELOC_MIPS_TLS_TPREL64
:
15456 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15457 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15458 case BFD_RELOC_MICROMIPS_TLS_GD
:
15459 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15460 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15461 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15462 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15463 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15464 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15465 case BFD_RELOC_MIPS16_TLS_GD
:
15466 case BFD_RELOC_MIPS16_TLS_LDM
:
15467 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15468 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15469 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15470 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15471 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15472 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15475 case BFD_RELOC_MIPS_JMP
:
15476 case BFD_RELOC_MIPS_SHIFT5
:
15477 case BFD_RELOC_MIPS_SHIFT6
:
15478 case BFD_RELOC_MIPS_GOT_DISP
:
15479 case BFD_RELOC_MIPS_GOT_PAGE
:
15480 case BFD_RELOC_MIPS_GOT_OFST
:
15481 case BFD_RELOC_MIPS_SUB
:
15482 case BFD_RELOC_MIPS_INSERT_A
:
15483 case BFD_RELOC_MIPS_INSERT_B
:
15484 case BFD_RELOC_MIPS_DELETE
:
15485 case BFD_RELOC_MIPS_HIGHEST
:
15486 case BFD_RELOC_MIPS_HIGHER
:
15487 case BFD_RELOC_MIPS_SCN_DISP
:
15488 case BFD_RELOC_MIPS_REL16
:
15489 case BFD_RELOC_MIPS_RELGOT
:
15490 case BFD_RELOC_MIPS_JALR
:
15491 case BFD_RELOC_HI16
:
15492 case BFD_RELOC_HI16_S
:
15493 case BFD_RELOC_GPREL16
:
15494 case BFD_RELOC_MIPS_LITERAL
:
15495 case BFD_RELOC_MIPS_CALL16
:
15496 case BFD_RELOC_MIPS_GOT16
:
15497 case BFD_RELOC_GPREL32
:
15498 case BFD_RELOC_MIPS_GOT_HI16
:
15499 case BFD_RELOC_MIPS_GOT_LO16
:
15500 case BFD_RELOC_MIPS_CALL_HI16
:
15501 case BFD_RELOC_MIPS_CALL_LO16
:
15502 case BFD_RELOC_MIPS16_GPREL
:
15503 case BFD_RELOC_MIPS16_GOT16
:
15504 case BFD_RELOC_MIPS16_CALL16
:
15505 case BFD_RELOC_MIPS16_HI16
:
15506 case BFD_RELOC_MIPS16_HI16_S
:
15507 case BFD_RELOC_MIPS16_JMP
:
15508 case BFD_RELOC_MICROMIPS_JMP
:
15509 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15510 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15511 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15512 case BFD_RELOC_MICROMIPS_SUB
:
15513 case BFD_RELOC_MICROMIPS_HIGHEST
:
15514 case BFD_RELOC_MICROMIPS_HIGHER
:
15515 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15516 case BFD_RELOC_MICROMIPS_JALR
:
15517 case BFD_RELOC_MICROMIPS_HI16
:
15518 case BFD_RELOC_MICROMIPS_HI16_S
:
15519 case BFD_RELOC_MICROMIPS_GPREL16
:
15520 case BFD_RELOC_MICROMIPS_LITERAL
:
15521 case BFD_RELOC_MICROMIPS_CALL16
:
15522 case BFD_RELOC_MICROMIPS_GOT16
:
15523 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15524 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15525 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15526 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15527 /* Nothing needed to do. The value comes from the reloc entry. */
15531 /* This is handled like BFD_RELOC_32, but we output a sign
15532 extended value if we are only 32 bits. */
15535 if (8 <= sizeof (valueT
))
15536 md_number_to_chars ((char *) buf
, *valP
, 8);
15541 if ((*valP
& 0x80000000) != 0)
15545 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
15547 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
15553 case BFD_RELOC_RVA
:
15556 /* If we are deleting this reloc entry, we must fill in the
15557 value now. This can happen if we have a .word which is not
15558 resolved when it appears but is later defined. */
15560 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
15563 case BFD_RELOC_LO16
:
15564 case BFD_RELOC_MIPS16_LO16
:
15565 case BFD_RELOC_MICROMIPS_LO16
:
15566 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15567 may be safe to remove, but if so it's not obvious. */
15568 /* When handling an embedded PIC switch statement, we can wind
15569 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15572 if (*valP
+ 0x8000 > 0xffff)
15573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15574 _("relocation overflow"));
15575 /* 32-bit microMIPS instructions are divided into two halfwords.
15576 Relocations always refer to the second halfword, regardless
15578 if (target_big_endian
|| fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_LO16
)
15580 md_number_to_chars ((char *) buf
, *valP
, 2);
15584 case BFD_RELOC_16_PCREL_S2
:
15585 if ((*valP
& 0x3) != 0)
15586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15587 _("Branch to misaligned address (%lx)"), (long) *valP
);
15589 /* We need to save the bits in the instruction since fixup_segment()
15590 might be deleting the relocation entry (i.e., a branch within
15591 the current segment). */
15592 if (! fixP
->fx_done
)
15595 /* Update old instruction data. */
15596 if (target_big_endian
)
15597 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
15599 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
15601 if (*valP
+ 0x20000 <= 0x3ffff)
15603 insn
|= (*valP
>> 2) & 0xffff;
15604 md_number_to_chars ((char *) buf
, insn
, 4);
15606 else if (mips_pic
== NO_PIC
15608 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15609 && (fixP
->fx_frag
->fr_address
15610 < text_section
->vma
+ bfd_get_section_size (text_section
))
15611 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15612 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15613 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15615 /* The branch offset is too large. If this is an
15616 unconditional branch, and we are not generating PIC code,
15617 we can convert it to an absolute jump instruction. */
15618 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15619 insn
= 0x0c000000; /* jal */
15621 insn
= 0x08000000; /* j */
15622 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15624 fixP
->fx_addsy
= section_symbol (text_section
);
15625 *valP
+= md_pcrel_from (fixP
);
15626 md_number_to_chars ((char *) buf
, insn
, 4);
15630 /* If we got here, we have branch-relaxation disabled,
15631 and there's nothing we can do to fix this instruction
15632 without turning it into a longer sequence. */
15633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15634 _("Branch out of range"));
15638 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15639 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15640 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15641 /* We adjust the offset back to even. */
15642 if ((*valP
& 0x1) != 0)
15645 if (! fixP
->fx_done
)
15648 /* Should never visit here, because we keep the relocation. */
15652 case BFD_RELOC_VTABLE_INHERIT
:
15655 && !S_IS_DEFINED (fixP
->fx_addsy
)
15656 && !S_IS_WEAK (fixP
->fx_addsy
))
15657 S_SET_WEAK (fixP
->fx_addsy
);
15660 case BFD_RELOC_VTABLE_ENTRY
:
15668 /* Remember value for tc_gen_reloc. */
15669 fixP
->fx_addnumber
= *valP
;
15679 name
= input_line_pointer
;
15680 c
= get_symbol_end ();
15681 p
= (symbolS
*) symbol_find_or_make (name
);
15682 *input_line_pointer
= c
;
15686 /* Align the current frag to a given power of two. If a particular
15687 fill byte should be used, FILL points to an integer that contains
15688 that byte, otherwise FILL is null.
15690 This function used to have the comment:
15692 The MIPS assembler also automatically adjusts any preceding label.
15694 The implementation therefore applied the adjustment to a maximum of
15695 one label. However, other label adjustments are applied to batches
15696 of labels, and adjusting just one caused problems when new labels
15697 were added for the sake of debugging or unwind information.
15698 We therefore adjust all preceding labels (given as LABELS) instead. */
15701 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15703 mips_emit_delays ();
15704 mips_record_compressed_mode ();
15705 if (fill
== NULL
&& subseg_text_p (now_seg
))
15706 frag_align_code (to
, 0);
15708 frag_align (to
, fill
? *fill
: 0, 0);
15709 record_alignment (now_seg
, to
);
15710 mips_move_labels (labels
, FALSE
);
15713 /* Align to a given power of two. .align 0 turns off the automatic
15714 alignment used by the data creating pseudo-ops. */
15717 s_align (int x ATTRIBUTE_UNUSED
)
15719 int temp
, fill_value
, *fill_ptr
;
15720 long max_alignment
= 28;
15722 /* o Note that the assembler pulls down any immediately preceding label
15723 to the aligned address.
15724 o It's not documented but auto alignment is reinstated by
15725 a .align pseudo instruction.
15726 o Note also that after auto alignment is turned off the mips assembler
15727 issues an error on attempt to assemble an improperly aligned data item.
15730 temp
= get_absolute_expression ();
15731 if (temp
> max_alignment
)
15732 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15735 as_warn (_("Alignment negative: 0 assumed."));
15738 if (*input_line_pointer
== ',')
15740 ++input_line_pointer
;
15741 fill_value
= get_absolute_expression ();
15742 fill_ptr
= &fill_value
;
15748 segment_info_type
*si
= seg_info (now_seg
);
15749 struct insn_label_list
*l
= si
->label_list
;
15750 /* Auto alignment should be switched on by next section change. */
15752 mips_align (temp
, fill_ptr
, l
);
15759 demand_empty_rest_of_line ();
15763 s_change_sec (int sec
)
15768 /* The ELF backend needs to know that we are changing sections, so
15769 that .previous works correctly. We could do something like check
15770 for an obj_section_change_hook macro, but that might be confusing
15771 as it would not be appropriate to use it in the section changing
15772 functions in read.c, since obj-elf.c intercepts those. FIXME:
15773 This should be cleaner, somehow. */
15775 obj_elf_section_change_hook ();
15778 mips_emit_delays ();
15789 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15790 demand_empty_rest_of_line ();
15794 seg
= subseg_new (RDATA_SECTION_NAME
,
15795 (subsegT
) get_absolute_expression ());
15798 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15799 | SEC_READONLY
| SEC_RELOC
15801 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15802 record_alignment (seg
, 4);
15804 demand_empty_rest_of_line ();
15808 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15811 bfd_set_section_flags (stdoutput
, seg
,
15812 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15813 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15814 record_alignment (seg
, 4);
15816 demand_empty_rest_of_line ();
15820 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15823 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15824 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15825 record_alignment (seg
, 4);
15827 demand_empty_rest_of_line ();
15835 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15838 char *section_name
;
15843 int section_entry_size
;
15844 int section_alignment
;
15849 section_name
= input_line_pointer
;
15850 c
= get_symbol_end ();
15852 next_c
= *(input_line_pointer
+ 1);
15854 /* Do we have .section Name<,"flags">? */
15855 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15857 /* just after name is now '\0'. */
15858 *input_line_pointer
= c
;
15859 input_line_pointer
= section_name
;
15860 obj_elf_section (ignore
);
15863 input_line_pointer
++;
15865 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15867 section_type
= get_absolute_expression ();
15870 if (*input_line_pointer
++ == ',')
15871 section_flag
= get_absolute_expression ();
15874 if (*input_line_pointer
++ == ',')
15875 section_entry_size
= get_absolute_expression ();
15877 section_entry_size
= 0;
15878 if (*input_line_pointer
++ == ',')
15879 section_alignment
= get_absolute_expression ();
15881 section_alignment
= 0;
15882 /* FIXME: really ignore? */
15883 (void) section_alignment
;
15885 section_name
= xstrdup (section_name
);
15887 /* When using the generic form of .section (as implemented by obj-elf.c),
15888 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15889 traditionally had to fall back on the more common @progbits instead.
15891 There's nothing really harmful in this, since bfd will correct
15892 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15893 means that, for backwards compatibility, the special_section entries
15894 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15896 Even so, we shouldn't force users of the MIPS .section syntax to
15897 incorrectly label the sections as SHT_PROGBITS. The best compromise
15898 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15899 generic type-checking code. */
15900 if (section_type
== SHT_MIPS_DWARF
)
15901 section_type
= SHT_PROGBITS
;
15903 obj_elf_change_section (section_name
, section_type
, section_flag
,
15904 section_entry_size
, 0, 0, 0);
15906 if (now_seg
->name
!= section_name
)
15907 free (section_name
);
15908 #endif /* OBJ_ELF */
15912 mips_enable_auto_align (void)
15918 s_cons (int log_size
)
15920 segment_info_type
*si
= seg_info (now_seg
);
15921 struct insn_label_list
*l
= si
->label_list
;
15923 mips_emit_delays ();
15924 if (log_size
> 0 && auto_align
)
15925 mips_align (log_size
, 0, l
);
15926 cons (1 << log_size
);
15927 mips_clear_insn_labels ();
15931 s_float_cons (int type
)
15933 segment_info_type
*si
= seg_info (now_seg
);
15934 struct insn_label_list
*l
= si
->label_list
;
15936 mips_emit_delays ();
15941 mips_align (3, 0, l
);
15943 mips_align (2, 0, l
);
15947 mips_clear_insn_labels ();
15950 /* Handle .globl. We need to override it because on Irix 5 you are
15953 where foo is an undefined symbol, to mean that foo should be
15954 considered to be the address of a function. */
15957 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15966 name
= input_line_pointer
;
15967 c
= get_symbol_end ();
15968 symbolP
= symbol_find_or_make (name
);
15969 S_SET_EXTERNAL (symbolP
);
15971 *input_line_pointer
= c
;
15972 SKIP_WHITESPACE ();
15974 /* On Irix 5, every global symbol that is not explicitly labelled as
15975 being a function is apparently labelled as being an object. */
15978 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15979 && (*input_line_pointer
!= ','))
15984 secname
= input_line_pointer
;
15985 c
= get_symbol_end ();
15986 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15988 as_bad (_("%s: no such section"), secname
);
15989 *input_line_pointer
= c
;
15991 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15992 flag
= BSF_FUNCTION
;
15995 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15997 c
= *input_line_pointer
;
16000 input_line_pointer
++;
16001 SKIP_WHITESPACE ();
16002 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16008 demand_empty_rest_of_line ();
16012 s_option (int x ATTRIBUTE_UNUSED
)
16017 opt
= input_line_pointer
;
16018 c
= get_symbol_end ();
16022 /* FIXME: What does this mean? */
16024 else if (strncmp (opt
, "pic", 3) == 0)
16028 i
= atoi (opt
+ 3);
16033 mips_pic
= SVR4_PIC
;
16034 mips_abicalls
= TRUE
;
16037 as_bad (_(".option pic%d not supported"), i
);
16039 if (mips_pic
== SVR4_PIC
)
16041 if (g_switch_seen
&& g_switch_value
!= 0)
16042 as_warn (_("-G may not be used with SVR4 PIC code"));
16043 g_switch_value
= 0;
16044 bfd_set_gp_size (stdoutput
, 0);
16048 as_warn (_("Unrecognized option \"%s\""), opt
);
16050 *input_line_pointer
= c
;
16051 demand_empty_rest_of_line ();
16054 /* This structure is used to hold a stack of .set values. */
16056 struct mips_option_stack
16058 struct mips_option_stack
*next
;
16059 struct mips_set_options options
;
16062 static struct mips_option_stack
*mips_opts_stack
;
16064 /* Handle the .set pseudo-op. */
16067 s_mipsset (int x ATTRIBUTE_UNUSED
)
16069 char *name
= input_line_pointer
, ch
;
16071 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16072 ++input_line_pointer
;
16073 ch
= *input_line_pointer
;
16074 *input_line_pointer
= '\0';
16076 if (strcmp (name
, "reorder") == 0)
16078 if (mips_opts
.noreorder
)
16081 else if (strcmp (name
, "noreorder") == 0)
16083 if (!mips_opts
.noreorder
)
16084 start_noreorder ();
16086 else if (strncmp (name
, "at=", 3) == 0)
16088 char *s
= name
+ 3;
16090 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16091 as_bad (_("Unrecognized register name `%s'"), s
);
16093 else if (strcmp (name
, "at") == 0)
16095 mips_opts
.at
= ATREG
;
16097 else if (strcmp (name
, "noat") == 0)
16099 mips_opts
.at
= ZERO
;
16101 else if (strcmp (name
, "macro") == 0)
16103 mips_opts
.warn_about_macros
= 0;
16105 else if (strcmp (name
, "nomacro") == 0)
16107 if (mips_opts
.noreorder
== 0)
16108 as_bad (_("`noreorder' must be set before `nomacro'"));
16109 mips_opts
.warn_about_macros
= 1;
16111 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16113 mips_opts
.nomove
= 0;
16115 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16117 mips_opts
.nomove
= 1;
16119 else if (strcmp (name
, "bopt") == 0)
16121 mips_opts
.nobopt
= 0;
16123 else if (strcmp (name
, "nobopt") == 0)
16125 mips_opts
.nobopt
= 1;
16127 else if (strcmp (name
, "gp=default") == 0)
16128 mips_opts
.gp32
= file_mips_gp32
;
16129 else if (strcmp (name
, "gp=32") == 0)
16130 mips_opts
.gp32
= 1;
16131 else if (strcmp (name
, "gp=64") == 0)
16133 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16134 as_warn (_("%s isa does not support 64-bit registers"),
16135 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16136 mips_opts
.gp32
= 0;
16138 else if (strcmp (name
, "fp=default") == 0)
16139 mips_opts
.fp32
= file_mips_fp32
;
16140 else if (strcmp (name
, "fp=32") == 0)
16141 mips_opts
.fp32
= 1;
16142 else if (strcmp (name
, "fp=64") == 0)
16144 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16145 as_warn (_("%s isa does not support 64-bit floating point registers"),
16146 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16147 mips_opts
.fp32
= 0;
16149 else if (strcmp (name
, "softfloat") == 0)
16150 mips_opts
.soft_float
= 1;
16151 else if (strcmp (name
, "hardfloat") == 0)
16152 mips_opts
.soft_float
= 0;
16153 else if (strcmp (name
, "singlefloat") == 0)
16154 mips_opts
.single_float
= 1;
16155 else if (strcmp (name
, "doublefloat") == 0)
16156 mips_opts
.single_float
= 0;
16157 else if (strcmp (name
, "mips16") == 0
16158 || strcmp (name
, "MIPS-16") == 0)
16160 if (mips_opts
.micromips
== 1)
16161 as_fatal (_("`mips16' cannot be used with `micromips'"));
16162 mips_opts
.mips16
= 1;
16164 else if (strcmp (name
, "nomips16") == 0
16165 || strcmp (name
, "noMIPS-16") == 0)
16166 mips_opts
.mips16
= 0;
16167 else if (strcmp (name
, "micromips") == 0)
16169 if (mips_opts
.mips16
== 1)
16170 as_fatal (_("`micromips' cannot be used with `mips16'"));
16171 mips_opts
.micromips
= 1;
16173 else if (strcmp (name
, "nomicromips") == 0)
16174 mips_opts
.micromips
= 0;
16175 else if (strcmp (name
, "smartmips") == 0)
16177 if (!ISA_SUPPORTS_SMARTMIPS
)
16178 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16179 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16180 mips_opts
.ase_smartmips
= 1;
16182 else if (strcmp (name
, "nosmartmips") == 0)
16183 mips_opts
.ase_smartmips
= 0;
16184 else if (strcmp (name
, "mips3d") == 0)
16185 mips_opts
.ase_mips3d
= 1;
16186 else if (strcmp (name
, "nomips3d") == 0)
16187 mips_opts
.ase_mips3d
= 0;
16188 else if (strcmp (name
, "mdmx") == 0)
16189 mips_opts
.ase_mdmx
= 1;
16190 else if (strcmp (name
, "nomdmx") == 0)
16191 mips_opts
.ase_mdmx
= 0;
16192 else if (strcmp (name
, "dsp") == 0)
16194 if (!ISA_SUPPORTS_DSP_ASE
)
16195 as_warn (_("%s ISA does not support DSP ASE"),
16196 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16197 mips_opts
.ase_dsp
= 1;
16198 mips_opts
.ase_dspr2
= 0;
16200 else if (strcmp (name
, "nodsp") == 0)
16202 mips_opts
.ase_dsp
= 0;
16203 mips_opts
.ase_dspr2
= 0;
16205 else if (strcmp (name
, "dspr2") == 0)
16207 if (!ISA_SUPPORTS_DSPR2_ASE
)
16208 as_warn (_("%s ISA does not support DSP R2 ASE"),
16209 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16210 mips_opts
.ase_dspr2
= 1;
16211 mips_opts
.ase_dsp
= 1;
16213 else if (strcmp (name
, "nodspr2") == 0)
16215 mips_opts
.ase_dspr2
= 0;
16216 mips_opts
.ase_dsp
= 0;
16218 else if (strcmp (name
, "mt") == 0)
16220 if (!ISA_SUPPORTS_MT_ASE
)
16221 as_warn (_("%s ISA does not support MT ASE"),
16222 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16223 mips_opts
.ase_mt
= 1;
16225 else if (strcmp (name
, "nomt") == 0)
16226 mips_opts
.ase_mt
= 0;
16227 else if (strcmp (name
, "mcu") == 0)
16228 mips_opts
.ase_mcu
= 1;
16229 else if (strcmp (name
, "nomcu") == 0)
16230 mips_opts
.ase_mcu
= 0;
16231 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16235 /* Permit the user to change the ISA and architecture on the fly.
16236 Needless to say, misuse can cause serious problems. */
16237 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16240 mips_opts
.isa
= file_mips_isa
;
16241 mips_opts
.arch
= file_mips_arch
;
16243 else if (strncmp (name
, "arch=", 5) == 0)
16245 const struct mips_cpu_info
*p
;
16247 p
= mips_parse_cpu("internal use", name
+ 5);
16249 as_bad (_("unknown architecture %s"), name
+ 5);
16252 mips_opts
.arch
= p
->cpu
;
16253 mips_opts
.isa
= p
->isa
;
16256 else if (strncmp (name
, "mips", 4) == 0)
16258 const struct mips_cpu_info
*p
;
16260 p
= mips_parse_cpu("internal use", name
);
16262 as_bad (_("unknown ISA level %s"), name
+ 4);
16265 mips_opts
.arch
= p
->cpu
;
16266 mips_opts
.isa
= p
->isa
;
16270 as_bad (_("unknown ISA or architecture %s"), name
);
16272 switch (mips_opts
.isa
)
16280 mips_opts
.gp32
= 1;
16281 mips_opts
.fp32
= 1;
16288 mips_opts
.gp32
= 0;
16289 mips_opts
.fp32
= 0;
16292 as_bad (_("unknown ISA level %s"), name
+ 4);
16297 mips_opts
.gp32
= file_mips_gp32
;
16298 mips_opts
.fp32
= file_mips_fp32
;
16301 else if (strcmp (name
, "autoextend") == 0)
16302 mips_opts
.noautoextend
= 0;
16303 else if (strcmp (name
, "noautoextend") == 0)
16304 mips_opts
.noautoextend
= 1;
16305 else if (strcmp (name
, "push") == 0)
16307 struct mips_option_stack
*s
;
16309 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16310 s
->next
= mips_opts_stack
;
16311 s
->options
= mips_opts
;
16312 mips_opts_stack
= s
;
16314 else if (strcmp (name
, "pop") == 0)
16316 struct mips_option_stack
*s
;
16318 s
= mips_opts_stack
;
16320 as_bad (_(".set pop with no .set push"));
16323 /* If we're changing the reorder mode we need to handle
16324 delay slots correctly. */
16325 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16326 start_noreorder ();
16327 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16330 mips_opts
= s
->options
;
16331 mips_opts_stack
= s
->next
;
16335 else if (strcmp (name
, "sym32") == 0)
16336 mips_opts
.sym32
= TRUE
;
16337 else if (strcmp (name
, "nosym32") == 0)
16338 mips_opts
.sym32
= FALSE
;
16339 else if (strchr (name
, ','))
16341 /* Generic ".set" directive; use the generic handler. */
16342 *input_line_pointer
= ch
;
16343 input_line_pointer
= name
;
16349 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16351 *input_line_pointer
= ch
;
16352 demand_empty_rest_of_line ();
16355 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16356 .option pic2. It means to generate SVR4 PIC calls. */
16359 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16361 mips_pic
= SVR4_PIC
;
16362 mips_abicalls
= TRUE
;
16364 if (g_switch_seen
&& g_switch_value
!= 0)
16365 as_warn (_("-G may not be used with SVR4 PIC code"));
16366 g_switch_value
= 0;
16368 bfd_set_gp_size (stdoutput
, 0);
16369 demand_empty_rest_of_line ();
16372 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16373 PIC code. It sets the $gp register for the function based on the
16374 function address, which is in the register named in the argument.
16375 This uses a relocation against _gp_disp, which is handled specially
16376 by the linker. The result is:
16377 lui $gp,%hi(_gp_disp)
16378 addiu $gp,$gp,%lo(_gp_disp)
16379 addu $gp,$gp,.cpload argument
16380 The .cpload argument is normally $25 == $t9.
16382 The -mno-shared option changes this to:
16383 lui $gp,%hi(__gnu_local_gp)
16384 addiu $gp,$gp,%lo(__gnu_local_gp)
16385 and the argument is ignored. This saves an instruction, but the
16386 resulting code is not position independent; it uses an absolute
16387 address for __gnu_local_gp. Thus code assembled with -mno-shared
16388 can go into an ordinary executable, but not into a shared library. */
16391 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16397 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16398 .cpload is ignored. */
16399 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16405 if (mips_opts
.mips16
)
16407 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16408 ignore_rest_of_line ();
16412 /* .cpload should be in a .set noreorder section. */
16413 if (mips_opts
.noreorder
== 0)
16414 as_warn (_(".cpload not in noreorder section"));
16416 reg
= tc_get_register (0);
16418 /* If we need to produce a 64-bit address, we are better off using
16419 the default instruction sequence. */
16420 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16422 ex
.X_op
= O_symbol
;
16423 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16425 ex
.X_op_symbol
= NULL
;
16426 ex
.X_add_number
= 0;
16428 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16429 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16432 macro_build_lui (&ex
, mips_gp_register
);
16433 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16434 mips_gp_register
, BFD_RELOC_LO16
);
16436 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16437 mips_gp_register
, reg
);
16440 demand_empty_rest_of_line ();
16443 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16444 .cpsetup $reg1, offset|$reg2, label
16446 If offset is given, this results in:
16447 sd $gp, offset($sp)
16448 lui $gp, %hi(%neg(%gp_rel(label)))
16449 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16450 daddu $gp, $gp, $reg1
16452 If $reg2 is given, this results in:
16453 daddu $reg2, $gp, $0
16454 lui $gp, %hi(%neg(%gp_rel(label)))
16455 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16456 daddu $gp, $gp, $reg1
16457 $reg1 is normally $25 == $t9.
16459 The -mno-shared option replaces the last three instructions with
16461 addiu $gp,$gp,%lo(_gp) */
16464 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16466 expressionS ex_off
;
16467 expressionS ex_sym
;
16470 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16471 We also need NewABI support. */
16472 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16478 if (mips_opts
.mips16
)
16480 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16481 ignore_rest_of_line ();
16485 reg1
= tc_get_register (0);
16486 SKIP_WHITESPACE ();
16487 if (*input_line_pointer
!= ',')
16489 as_bad (_("missing argument separator ',' for .cpsetup"));
16493 ++input_line_pointer
;
16494 SKIP_WHITESPACE ();
16495 if (*input_line_pointer
== '$')
16497 mips_cpreturn_register
= tc_get_register (0);
16498 mips_cpreturn_offset
= -1;
16502 mips_cpreturn_offset
= get_absolute_expression ();
16503 mips_cpreturn_register
= -1;
16505 SKIP_WHITESPACE ();
16506 if (*input_line_pointer
!= ',')
16508 as_bad (_("missing argument separator ',' for .cpsetup"));
16512 ++input_line_pointer
;
16513 SKIP_WHITESPACE ();
16514 expression (&ex_sym
);
16517 if (mips_cpreturn_register
== -1)
16519 ex_off
.X_op
= O_constant
;
16520 ex_off
.X_add_symbol
= NULL
;
16521 ex_off
.X_op_symbol
= NULL
;
16522 ex_off
.X_add_number
= mips_cpreturn_offset
;
16524 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16525 BFD_RELOC_LO16
, SP
);
16528 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16529 mips_gp_register
, 0);
16531 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16533 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16534 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16537 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16538 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16539 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16542 mips_gp_register
, reg1
);
16548 ex
.X_op
= O_symbol
;
16549 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16550 ex
.X_op_symbol
= NULL
;
16551 ex
.X_add_number
= 0;
16553 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16554 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16556 macro_build_lui (&ex
, mips_gp_register
);
16557 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16558 mips_gp_register
, BFD_RELOC_LO16
);
16563 demand_empty_rest_of_line ();
16567 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16569 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16570 .cplocal is ignored. */
16571 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16577 if (mips_opts
.mips16
)
16579 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16580 ignore_rest_of_line ();
16584 mips_gp_register
= tc_get_register (0);
16585 demand_empty_rest_of_line ();
16588 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16589 offset from $sp. The offset is remembered, and after making a PIC
16590 call $gp is restored from that location. */
16593 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16597 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16598 .cprestore is ignored. */
16599 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16605 if (mips_opts
.mips16
)
16607 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16608 ignore_rest_of_line ();
16612 mips_cprestore_offset
= get_absolute_expression ();
16613 mips_cprestore_valid
= 1;
16615 ex
.X_op
= O_constant
;
16616 ex
.X_add_symbol
= NULL
;
16617 ex
.X_op_symbol
= NULL
;
16618 ex
.X_add_number
= mips_cprestore_offset
;
16621 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16622 SP
, HAVE_64BIT_ADDRESSES
);
16625 demand_empty_rest_of_line ();
16628 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16629 was given in the preceding .cpsetup, it results in:
16630 ld $gp, offset($sp)
16632 If a register $reg2 was given there, it results in:
16633 daddu $gp, $reg2, $0 */
16636 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16640 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16641 We also need NewABI support. */
16642 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16648 if (mips_opts
.mips16
)
16650 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16651 ignore_rest_of_line ();
16656 if (mips_cpreturn_register
== -1)
16658 ex
.X_op
= O_constant
;
16659 ex
.X_add_symbol
= NULL
;
16660 ex
.X_op_symbol
= NULL
;
16661 ex
.X_add_number
= mips_cpreturn_offset
;
16663 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16666 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16667 mips_cpreturn_register
, 0);
16670 demand_empty_rest_of_line ();
16673 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16674 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16675 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16676 debug information or MIPS16 TLS. */
16679 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16680 bfd_reloc_code_real_type rtype
)
16687 if (ex
.X_op
!= O_symbol
)
16689 as_bad (_("Unsupported use of %s"), dirstr
);
16690 ignore_rest_of_line ();
16693 p
= frag_more (bytes
);
16694 md_number_to_chars (p
, 0, bytes
);
16695 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16696 demand_empty_rest_of_line ();
16697 mips_clear_insn_labels ();
16700 /* Handle .dtprelword. */
16703 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16705 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16708 /* Handle .dtpreldword. */
16711 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16713 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16716 /* Handle .tprelword. */
16719 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16721 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16724 /* Handle .tpreldword. */
16727 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16729 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16732 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16733 code. It sets the offset to use in gp_rel relocations. */
16736 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16738 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16739 We also need NewABI support. */
16740 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16746 mips_gprel_offset
= get_absolute_expression ();
16748 demand_empty_rest_of_line ();
16751 /* Handle the .gpword pseudo-op. This is used when generating PIC
16752 code. It generates a 32 bit GP relative reloc. */
16755 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16757 segment_info_type
*si
;
16758 struct insn_label_list
*l
;
16762 /* When not generating PIC code, this is treated as .word. */
16763 if (mips_pic
!= SVR4_PIC
)
16769 si
= seg_info (now_seg
);
16770 l
= si
->label_list
;
16771 mips_emit_delays ();
16773 mips_align (2, 0, l
);
16776 mips_clear_insn_labels ();
16778 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16780 as_bad (_("Unsupported use of .gpword"));
16781 ignore_rest_of_line ();
16785 md_number_to_chars (p
, 0, 4);
16786 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16787 BFD_RELOC_GPREL32
);
16789 demand_empty_rest_of_line ();
16793 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16795 segment_info_type
*si
;
16796 struct insn_label_list
*l
;
16800 /* When not generating PIC code, this is treated as .dword. */
16801 if (mips_pic
!= SVR4_PIC
)
16807 si
= seg_info (now_seg
);
16808 l
= si
->label_list
;
16809 mips_emit_delays ();
16811 mips_align (3, 0, l
);
16814 mips_clear_insn_labels ();
16816 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16818 as_bad (_("Unsupported use of .gpdword"));
16819 ignore_rest_of_line ();
16823 md_number_to_chars (p
, 0, 8);
16824 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16825 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16827 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16828 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16829 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16831 demand_empty_rest_of_line ();
16834 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16835 tables in SVR4 PIC code. */
16838 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16842 /* This is ignored when not generating SVR4 PIC code. */
16843 if (mips_pic
!= SVR4_PIC
)
16849 /* Add $gp to the register named as an argument. */
16851 reg
= tc_get_register (0);
16852 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16855 demand_empty_rest_of_line ();
16858 /* Handle the .insn pseudo-op. This marks instruction labels in
16859 mips16/micromips mode. This permits the linker to handle them specially,
16860 such as generating jalx instructions when needed. We also make
16861 them odd for the duration of the assembly, in order to generate the
16862 right sort of code. We will make them even in the adjust_symtab
16863 routine, while leaving them marked. This is convenient for the
16864 debugger and the disassembler. The linker knows to make them odd
16868 s_insn (int ignore ATTRIBUTE_UNUSED
)
16870 mips_mark_labels ();
16872 demand_empty_rest_of_line ();
16875 /* Handle a .stabn directive. We need these in order to mark a label
16876 as being a mips16 text label correctly. Sometimes the compiler
16877 will emit a label, followed by a .stabn, and then switch sections.
16878 If the label and .stabn are in mips16 mode, then the label is
16879 really a mips16 text label. */
16882 s_mips_stab (int type
)
16885 mips_mark_labels ();
16890 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16893 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16900 name
= input_line_pointer
;
16901 c
= get_symbol_end ();
16902 symbolP
= symbol_find_or_make (name
);
16903 S_SET_WEAK (symbolP
);
16904 *input_line_pointer
= c
;
16906 SKIP_WHITESPACE ();
16908 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16910 if (S_IS_DEFINED (symbolP
))
16912 as_bad (_("ignoring attempt to redefine symbol %s"),
16913 S_GET_NAME (symbolP
));
16914 ignore_rest_of_line ();
16918 if (*input_line_pointer
== ',')
16920 ++input_line_pointer
;
16921 SKIP_WHITESPACE ();
16925 if (exp
.X_op
!= O_symbol
)
16927 as_bad (_("bad .weakext directive"));
16928 ignore_rest_of_line ();
16931 symbol_set_value_expression (symbolP
, &exp
);
16934 demand_empty_rest_of_line ();
16937 /* Parse a register string into a number. Called from the ECOFF code
16938 to parse .frame. The argument is non-zero if this is the frame
16939 register, so that we can record it in mips_frame_reg. */
16942 tc_get_register (int frame
)
16946 SKIP_WHITESPACE ();
16947 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16951 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16952 mips_frame_reg_valid
= 1;
16953 mips_cprestore_valid
= 0;
16959 md_section_align (asection
*seg
, valueT addr
)
16961 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16965 /* We don't need to align ELF sections to the full alignment.
16966 However, Irix 5 may prefer that we align them at least to a 16
16967 byte boundary. We don't bother to align the sections if we
16968 are targeted for an embedded system. */
16969 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16975 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16978 /* Utility routine, called from above as well. If called while the
16979 input file is still being read, it's only an approximation. (For
16980 example, a symbol may later become defined which appeared to be
16981 undefined earlier.) */
16984 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16989 if (g_switch_value
> 0)
16991 const char *symname
;
16994 /* Find out whether this symbol can be referenced off the $gp
16995 register. It can be if it is smaller than the -G size or if
16996 it is in the .sdata or .sbss section. Certain symbols can
16997 not be referenced off the $gp, although it appears as though
16999 symname
= S_GET_NAME (sym
);
17000 if (symname
!= (const char *) NULL
17001 && (strcmp (symname
, "eprol") == 0
17002 || strcmp (symname
, "etext") == 0
17003 || strcmp (symname
, "_gp") == 0
17004 || strcmp (symname
, "edata") == 0
17005 || strcmp (symname
, "_fbss") == 0
17006 || strcmp (symname
, "_fdata") == 0
17007 || strcmp (symname
, "_ftext") == 0
17008 || strcmp (symname
, "end") == 0
17009 || strcmp (symname
, "_gp_disp") == 0))
17011 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17013 #ifndef NO_ECOFF_DEBUGGING
17014 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17015 && (symbol_get_obj (sym
)->ecoff_extern_size
17016 <= g_switch_value
))
17018 /* We must defer this decision until after the whole
17019 file has been read, since there might be a .extern
17020 after the first use of this symbol. */
17021 || (before_relaxing
17022 #ifndef NO_ECOFF_DEBUGGING
17023 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17025 && S_GET_VALUE (sym
) == 0)
17026 || (S_GET_VALUE (sym
) != 0
17027 && S_GET_VALUE (sym
) <= g_switch_value
)))
17031 const char *segname
;
17033 segname
= segment_name (S_GET_SEGMENT (sym
));
17034 gas_assert (strcmp (segname
, ".lit8") != 0
17035 && strcmp (segname
, ".lit4") != 0);
17036 change
= (strcmp (segname
, ".sdata") != 0
17037 && strcmp (segname
, ".sbss") != 0
17038 && strncmp (segname
, ".sdata.", 7) != 0
17039 && strncmp (segname
, ".sbss.", 6) != 0
17040 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17041 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17046 /* We are not optimizing for the $gp register. */
17051 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17054 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17058 /* Handle the case of a symbol equated to another symbol. */
17059 while (symbol_equated_reloc_p (sym
))
17063 /* It's possible to get a loop here in a badly written program. */
17064 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17070 if (symbol_section_p (sym
))
17073 symsec
= S_GET_SEGMENT (sym
);
17075 /* This must duplicate the test in adjust_reloc_syms. */
17076 return (!bfd_is_und_section (symsec
)
17077 && !bfd_is_abs_section (symsec
)
17078 && !bfd_is_com_section (symsec
)
17079 && !s_is_linkonce (sym
, segtype
)
17081 /* A global or weak symbol is treated as external. */
17082 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17088 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17089 extended opcode. SEC is the section the frag is in. */
17092 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17095 const struct mips16_immed_operand
*op
;
17097 int mintiny
, maxtiny
;
17101 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17103 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17106 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17107 op
= mips16_immed_operands
;
17108 while (op
->type
!= type
)
17111 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17116 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17119 maxtiny
= 1 << op
->nbits
;
17124 maxtiny
= (1 << op
->nbits
) - 1;
17129 mintiny
= - (1 << (op
->nbits
- 1));
17130 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17133 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17134 val
= S_GET_VALUE (fragp
->fr_symbol
);
17135 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17141 /* We won't have the section when we are called from
17142 mips_relax_frag. However, we will always have been called
17143 from md_estimate_size_before_relax first. If this is a
17144 branch to a different section, we mark it as such. If SEC is
17145 NULL, and the frag is not marked, then it must be a branch to
17146 the same section. */
17149 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17154 /* Must have been called from md_estimate_size_before_relax. */
17157 fragp
->fr_subtype
=
17158 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17160 /* FIXME: We should support this, and let the linker
17161 catch branches and loads that are out of range. */
17162 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17163 _("unsupported PC relative reference to different section"));
17167 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17168 /* Assume non-extended on the first relaxation pass.
17169 The address we have calculated will be bogus if this is
17170 a forward branch to another frag, as the forward frag
17171 will have fr_address == 0. */
17175 /* In this case, we know for sure that the symbol fragment is in
17176 the same section. If the relax_marker of the symbol fragment
17177 differs from the relax_marker of this fragment, we have not
17178 yet adjusted the symbol fragment fr_address. We want to add
17179 in STRETCH in order to get a better estimate of the address.
17180 This particularly matters because of the shift bits. */
17182 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17186 /* Adjust stretch for any alignment frag. Note that if have
17187 been expanding the earlier code, the symbol may be
17188 defined in what appears to be an earlier frag. FIXME:
17189 This doesn't handle the fr_subtype field, which specifies
17190 a maximum number of bytes to skip when doing an
17192 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17194 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17197 stretch
= - ((- stretch
)
17198 & ~ ((1 << (int) f
->fr_offset
) - 1));
17200 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17209 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17211 /* The base address rules are complicated. The base address of
17212 a branch is the following instruction. The base address of a
17213 PC relative load or add is the instruction itself, but if it
17214 is in a delay slot (in which case it can not be extended) use
17215 the address of the instruction whose delay slot it is in. */
17216 if (type
== 'p' || type
== 'q')
17220 /* If we are currently assuming that this frag should be
17221 extended, then, the current address is two bytes
17223 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17226 /* Ignore the low bit in the target, since it will be set
17227 for a text label. */
17228 if ((val
& 1) != 0)
17231 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17233 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17236 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17238 /* Branch offsets have an implicit 0 in the lowest bit. */
17239 if (type
== 'p' || type
== 'q')
17242 /* If any of the shifted bits are set, we must use an extended
17243 opcode. If the address depends on the size of this
17244 instruction, this can lead to a loop, so we arrange to always
17245 use an extended opcode. We only check this when we are in
17246 the main relaxation loop, when SEC is NULL. */
17247 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17249 fragp
->fr_subtype
=
17250 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17254 /* If we are about to mark a frag as extended because the value
17255 is precisely maxtiny + 1, then there is a chance of an
17256 infinite loop as in the following code:
17261 In this case when the la is extended, foo is 0x3fc bytes
17262 away, so the la can be shrunk, but then foo is 0x400 away, so
17263 the la must be extended. To avoid this loop, we mark the
17264 frag as extended if it was small, and is about to become
17265 extended with a value of maxtiny + 1. */
17266 if (val
== ((maxtiny
+ 1) << op
->shift
)
17267 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17270 fragp
->fr_subtype
=
17271 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17275 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17276 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17278 if ((val
& ((1 << op
->shift
) - 1)) != 0
17279 || val
< (mintiny
<< op
->shift
)
17280 || val
> (maxtiny
<< op
->shift
))
17286 /* Compute the length of a branch sequence, and adjust the
17287 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17288 worst-case length is computed, with UPDATE being used to indicate
17289 whether an unconditional (-1), branch-likely (+1) or regular (0)
17290 branch is to be computed. */
17292 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17294 bfd_boolean toofar
;
17298 && S_IS_DEFINED (fragp
->fr_symbol
)
17299 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17304 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17306 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17310 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17313 /* If the symbol is not defined or it's in a different segment,
17314 assume the user knows what's going on and emit a short
17320 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17322 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17323 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17324 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17325 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17331 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17334 if (mips_pic
!= NO_PIC
)
17336 /* Additional space for PIC loading of target address. */
17338 if (mips_opts
.isa
== ISA_MIPS1
)
17339 /* Additional space for $at-stabilizing nop. */
17343 /* If branch is conditional. */
17344 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17351 /* Compute the length of a branch sequence, and adjust the
17352 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17353 worst-case length is computed, with UPDATE being used to indicate
17354 whether an unconditional (-1), or regular (0) branch is to be
17358 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17360 bfd_boolean toofar
;
17364 && S_IS_DEFINED (fragp
->fr_symbol
)
17365 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17370 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17371 /* Ignore the low bit in the target, since it will be set
17372 for a text label. */
17373 if ((val
& 1) != 0)
17376 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17380 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17383 /* If the symbol is not defined or it's in a different segment,
17384 assume the user knows what's going on and emit a short
17390 if (fragp
&& update
17391 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17392 fragp
->fr_subtype
= (toofar
17393 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17394 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17399 bfd_boolean compact_known
= fragp
!= NULL
;
17400 bfd_boolean compact
= FALSE
;
17401 bfd_boolean uncond
;
17404 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17406 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17408 uncond
= update
< 0;
17410 /* If label is out of range, we turn branch <br>:
17412 <br> label # 4 bytes
17418 nop # 2 bytes if compact && !PIC
17421 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17424 /* If assembling PIC code, we further turn:
17430 lw/ld at, %got(label)(gp) # 4 bytes
17431 d/addiu at, %lo(label) # 4 bytes
17434 if (mips_pic
!= NO_PIC
)
17437 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17439 <brneg> 0f # 4 bytes
17440 nop # 2 bytes if !compact
17443 length
+= (compact_known
&& compact
) ? 4 : 6;
17449 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17450 bit accordingly. */
17453 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17455 bfd_boolean toofar
;
17458 && S_IS_DEFINED (fragp
->fr_symbol
)
17459 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17465 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17466 /* Ignore the low bit in the target, since it will be set
17467 for a text label. */
17468 if ((val
& 1) != 0)
17471 /* Assume this is a 2-byte branch. */
17472 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17474 /* We try to avoid the infinite loop by not adding 2 more bytes for
17479 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17481 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17482 else if (type
== 'E')
17483 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17488 /* If the symbol is not defined or it's in a different segment,
17489 we emit a normal 32-bit branch. */
17492 if (fragp
&& update
17493 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17495 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17496 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17504 /* Estimate the size of a frag before relaxing. Unless this is the
17505 mips16, we are not really relaxing here, and the final size is
17506 encoded in the subtype information. For the mips16, we have to
17507 decide whether we are using an extended opcode or not. */
17510 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17514 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17517 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17519 return fragp
->fr_var
;
17522 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17523 /* We don't want to modify the EXTENDED bit here; it might get us
17524 into infinite loops. We change it only in mips_relax_frag(). */
17525 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17527 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17531 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17532 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17533 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17534 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17535 fragp
->fr_var
= length
;
17540 if (mips_pic
== NO_PIC
)
17541 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17542 else if (mips_pic
== SVR4_PIC
)
17543 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17544 else if (mips_pic
== VXWORKS_PIC
)
17545 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17552 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17553 return -RELAX_FIRST (fragp
->fr_subtype
);
17556 return -RELAX_SECOND (fragp
->fr_subtype
);
17559 /* This is called to see whether a reloc against a defined symbol
17560 should be converted into a reloc against a section. */
17563 mips_fix_adjustable (fixS
*fixp
)
17565 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17566 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17569 if (fixp
->fx_addsy
== NULL
)
17572 /* If symbol SYM is in a mergeable section, relocations of the form
17573 SYM + 0 can usually be made section-relative. The mergeable data
17574 is then identified by the section offset rather than by the symbol.
17576 However, if we're generating REL LO16 relocations, the offset is split
17577 between the LO16 and parterning high part relocation. The linker will
17578 need to recalculate the complete offset in order to correctly identify
17581 The linker has traditionally not looked for the parterning high part
17582 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17583 placed anywhere. Rather than break backwards compatibility by changing
17584 this, it seems better not to force the issue, and instead keep the
17585 original symbol. This will work with either linker behavior. */
17586 if ((lo16_reloc_p (fixp
->fx_r_type
)
17587 || reloc_needs_lo_p (fixp
->fx_r_type
))
17588 && HAVE_IN_PLACE_ADDENDS
17589 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17592 /* There is no place to store an in-place offset for JALR relocations.
17593 Likewise an in-range offset of PC-relative relocations may overflow
17594 the in-place relocatable field if recalculated against the start
17595 address of the symbol's containing section. */
17596 if (HAVE_IN_PLACE_ADDENDS
17597 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17601 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17602 to a floating-point stub. The same is true for non-R_MIPS16_26
17603 relocations against MIPS16 functions; in this case, the stub becomes
17604 the function's canonical address.
17606 Floating-point stubs are stored in unique .mips16.call.* or
17607 .mips16.fn.* sections. If a stub T for function F is in section S,
17608 the first relocation in section S must be against F; this is how the
17609 linker determines the target function. All relocations that might
17610 resolve to T must also be against F. We therefore have the following
17611 restrictions, which are given in an intentionally-redundant way:
17613 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17616 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17617 if that stub might be used.
17619 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17622 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17623 that stub might be used.
17625 There is a further restriction:
17627 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17628 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17629 targets with in-place addends; the relocation field cannot
17630 encode the low bit.
17632 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17633 against a MIPS16 symbol. We deal with (5) by by not reducing any
17634 such relocations on REL targets.
17636 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17637 relocation against some symbol R, no relocation against R may be
17638 reduced. (Note that this deals with (2) as well as (1) because
17639 relocations against global symbols will never be reduced on ELF
17640 targets.) This approach is a little simpler than trying to detect
17641 stub sections, and gives the "all or nothing" per-symbol consistency
17642 that we have for MIPS16 symbols. */
17644 && fixp
->fx_subsy
== NULL
17645 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17646 || *symbol_get_tc (fixp
->fx_addsy
)
17647 || (HAVE_IN_PLACE_ADDENDS
17648 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17649 && jmp_reloc_p (fixp
->fx_r_type
))))
17656 /* Translate internal representation of relocation info to BFD target
17660 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17662 static arelent
*retval
[4];
17664 bfd_reloc_code_real_type code
;
17666 memset (retval
, 0, sizeof(retval
));
17667 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17668 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17669 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17670 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17672 if (fixp
->fx_pcrel
)
17674 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17675 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17676 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17677 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17679 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17680 Relocations want only the symbol offset. */
17681 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17684 /* A gruesome hack which is a result of the gruesome gas
17685 reloc handling. What's worse, for COFF (as opposed to
17686 ECOFF), we might need yet another copy of reloc->address.
17687 See bfd_install_relocation. */
17688 reloc
->addend
+= reloc
->address
;
17692 reloc
->addend
= fixp
->fx_addnumber
;
17694 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17695 entry to be used in the relocation's section offset. */
17696 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17698 reloc
->address
= reloc
->addend
;
17702 code
= fixp
->fx_r_type
;
17704 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17705 if (reloc
->howto
== NULL
)
17707 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17708 _("Can not represent %s relocation in this object file format"),
17709 bfd_get_reloc_code_name (code
));
17716 /* Relax a machine dependent frag. This returns the amount by which
17717 the current size of the frag should change. */
17720 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17722 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17724 offsetT old_var
= fragp
->fr_var
;
17726 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17728 return fragp
->fr_var
- old_var
;
17731 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17733 offsetT old_var
= fragp
->fr_var
;
17734 offsetT new_var
= 4;
17736 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17737 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17738 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17739 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17740 fragp
->fr_var
= new_var
;
17742 return new_var
- old_var
;
17745 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17748 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17750 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17752 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17757 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17759 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17766 /* Convert a machine dependent frag. */
17769 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17771 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17774 unsigned long insn
;
17778 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
17780 if (target_big_endian
)
17781 insn
= bfd_getb32 (buf
);
17783 insn
= bfd_getl32 (buf
);
17785 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17787 /* We generate a fixup instead of applying it right now
17788 because, if there are linker relaxations, we're going to
17789 need the relocations. */
17790 exp
.X_op
= O_symbol
;
17791 exp
.X_add_symbol
= fragp
->fr_symbol
;
17792 exp
.X_add_number
= fragp
->fr_offset
;
17794 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17795 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
17796 fixp
->fx_file
= fragp
->fr_file
;
17797 fixp
->fx_line
= fragp
->fr_line
;
17799 md_number_to_chars ((char *) buf
, insn
, 4);
17806 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17807 _("Relaxed out-of-range branch into a jump"));
17809 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17812 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17814 /* Reverse the branch. */
17815 switch ((insn
>> 28) & 0xf)
17818 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17819 have the condition reversed by tweaking a single
17820 bit, and their opcodes all have 0x4???????. */
17821 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17822 insn
^= 0x00010000;
17826 /* bltz 0x04000000 bgez 0x04010000
17827 bltzal 0x04100000 bgezal 0x04110000 */
17828 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17829 insn
^= 0x00010000;
17833 /* beq 0x10000000 bne 0x14000000
17834 blez 0x18000000 bgtz 0x1c000000 */
17835 insn
^= 0x04000000;
17843 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17845 /* Clear the and-link bit. */
17846 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17848 /* bltzal 0x04100000 bgezal 0x04110000
17849 bltzall 0x04120000 bgezall 0x04130000 */
17850 insn
&= ~0x00100000;
17853 /* Branch over the branch (if the branch was likely) or the
17854 full jump (not likely case). Compute the offset from the
17855 current instruction to branch to. */
17856 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17860 /* How many bytes in instructions we've already emitted? */
17861 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17862 /* How many bytes in instructions from here to the end? */
17863 i
= fragp
->fr_var
- i
;
17865 /* Convert to instruction count. */
17867 /* Branch counts from the next instruction. */
17870 /* Branch over the jump. */
17871 md_number_to_chars ((char *) buf
, insn
, 4);
17875 md_number_to_chars ((char *) buf
, 0, 4);
17878 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17880 /* beql $0, $0, 2f */
17882 /* Compute the PC offset from the current instruction to
17883 the end of the variable frag. */
17884 /* How many bytes in instructions we've already emitted? */
17885 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17886 /* How many bytes in instructions from here to the end? */
17887 i
= fragp
->fr_var
- i
;
17888 /* Convert to instruction count. */
17890 /* Don't decrement i, because we want to branch over the
17894 md_number_to_chars ((char *) buf
, insn
, 4);
17897 md_number_to_chars ((char *) buf
, 0, 4);
17902 if (mips_pic
== NO_PIC
)
17905 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17906 ? 0x0c000000 : 0x08000000);
17907 exp
.X_op
= O_symbol
;
17908 exp
.X_add_symbol
= fragp
->fr_symbol
;
17909 exp
.X_add_number
= fragp
->fr_offset
;
17911 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17912 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
17913 fixp
->fx_file
= fragp
->fr_file
;
17914 fixp
->fx_line
= fragp
->fr_line
;
17916 md_number_to_chars ((char *) buf
, insn
, 4);
17921 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17923 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17924 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17925 insn
|= at
<< OP_SH_RT
;
17926 exp
.X_op
= O_symbol
;
17927 exp
.X_add_symbol
= fragp
->fr_symbol
;
17928 exp
.X_add_number
= fragp
->fr_offset
;
17930 if (fragp
->fr_offset
)
17932 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17933 exp
.X_add_number
= 0;
17936 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17937 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
17938 fixp
->fx_file
= fragp
->fr_file
;
17939 fixp
->fx_line
= fragp
->fr_line
;
17941 md_number_to_chars ((char *) buf
, insn
, 4);
17944 if (mips_opts
.isa
== ISA_MIPS1
)
17947 md_number_to_chars ((char *) buf
, 0, 4);
17951 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17952 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17953 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17955 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17956 4, &exp
, FALSE
, BFD_RELOC_LO16
);
17957 fixp
->fx_file
= fragp
->fr_file
;
17958 fixp
->fx_line
= fragp
->fr_line
;
17960 md_number_to_chars ((char *) buf
, insn
, 4);
17964 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17968 insn
|= at
<< OP_SH_RS
;
17970 md_number_to_chars ((char *) buf
, insn
, 4);
17975 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
17976 + fragp
->fr_fix
+ fragp
->fr_var
);
17978 fragp
->fr_fix
+= fragp
->fr_var
;
17983 /* Relax microMIPS branches. */
17984 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17986 bfd_byte
*buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
17987 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17988 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17989 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17990 bfd_boolean short_ds
;
17991 unsigned long insn
;
17995 exp
.X_op
= O_symbol
;
17996 exp
.X_add_symbol
= fragp
->fr_symbol
;
17997 exp
.X_add_number
= fragp
->fr_offset
;
17999 fragp
->fr_fix
+= fragp
->fr_var
;
18001 /* Handle 16-bit branches that fit or are forced to fit. */
18002 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18004 /* We generate a fixup instead of applying it right now,
18005 because if there is linker relaxation, we're going to
18006 need the relocations. */
18008 fixp
= fix_new_exp (fragp
,
18009 buf
- (bfd_byte
*) fragp
->fr_literal
,
18011 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18012 else if (type
== 'E')
18013 fixp
= fix_new_exp (fragp
,
18014 buf
- (bfd_byte
*) fragp
->fr_literal
,
18016 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18020 fixp
->fx_file
= fragp
->fr_file
;
18021 fixp
->fx_line
= fragp
->fr_line
;
18023 /* These relocations can have an addend that won't fit in
18025 fixp
->fx_no_overflow
= 1;
18030 /* Handle 32-bit branches that fit or are forced to fit. */
18031 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18032 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18034 /* We generate a fixup instead of applying it right now,
18035 because if there is linker relaxation, we're going to
18036 need the relocations. */
18037 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18038 4, &exp
, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18039 fixp
->fx_file
= fragp
->fr_file
;
18040 fixp
->fx_line
= fragp
->fr_line
;
18046 /* Relax 16-bit branches to 32-bit branches. */
18049 if (target_big_endian
)
18050 insn
= bfd_getb16 (buf
);
18052 insn
= bfd_getl16 (buf
);
18054 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18055 insn
= 0x94000000; /* beq */
18056 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18058 unsigned long regno
;
18060 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18061 regno
= micromips_to_32_reg_d_map
[regno
];
18062 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18063 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18068 /* Nothing else to do, just write it out. */
18069 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18070 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18072 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18074 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18077 gas_assert (buf
== ((bfd_byte
*) fragp
->fr_literal
18084 unsigned long next
;
18086 if (target_big_endian
)
18088 insn
= bfd_getb16 (buf
);
18089 next
= bfd_getb16 (buf
+ 2);
18093 insn
= bfd_getl16 (buf
);
18094 next
= bfd_getl16 (buf
+ 2);
18096 insn
= (insn
<< 16) | next
;
18099 /* Relax 32-bit branches to a sequence of instructions. */
18100 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18101 _("Relaxed out-of-range branch into a jump"));
18103 /* Set the short-delay-slot bit. */
18104 short_ds
= al
&& (insn
& 0x02000000) != 0;
18106 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18110 /* Reverse the branch. */
18111 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18112 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18113 insn
^= 0x20000000;
18114 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18115 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18116 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18117 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18118 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18119 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18120 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18121 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18122 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18123 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18124 insn
^= 0x00400000;
18125 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18126 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18127 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18128 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18129 insn
^= 0x00200000;
18135 /* Clear the and-link and short-delay-slot bits. */
18136 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18138 /* bltzal 0x40200000 bgezal 0x40600000 */
18139 /* bltzals 0x42200000 bgezals 0x42600000 */
18140 insn
&= ~0x02200000;
18143 /* Make a label at the end for use with the branch. */
18144 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18145 micromips_label_inc ();
18146 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18148 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18152 fixp
= fix_new (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18153 4, l
, 0, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18154 fixp
->fx_file
= fragp
->fr_file
;
18155 fixp
->fx_line
= fragp
->fr_line
;
18157 /* Branch over the jump. */
18158 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18160 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18167 md_number_to_chars ((char *) buf
, insn
, 2);
18172 if (mips_pic
== NO_PIC
)
18174 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18176 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18177 insn
= al
? jal
: 0xd4000000;
18179 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18180 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18181 fixp
->fx_file
= fragp
->fr_file
;
18182 fixp
->fx_line
= fragp
->fr_line
;
18184 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18186 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18193 md_number_to_chars ((char *) buf
, insn
, 2);
18199 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18200 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18201 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18203 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18204 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18205 insn
|= at
<< MICROMIPSOP_SH_RT
;
18207 if (exp
.X_add_number
)
18209 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18210 exp
.X_add_number
= 0;
18213 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18214 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18215 fixp
->fx_file
= fragp
->fr_file
;
18216 fixp
->fx_line
= fragp
->fr_line
;
18218 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18220 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18223 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18224 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18225 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18227 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18228 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18229 fixp
->fx_file
= fragp
->fr_file
;
18230 fixp
->fx_line
= fragp
->fr_line
;
18232 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18234 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18237 /* jr/jrc/jalr/jalrs $at */
18238 insn
= al
? jalr
: jr
;
18239 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18241 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18245 gas_assert (buf
== (bfd_byte
*) fragp
->fr_literal
+ fragp
->fr_fix
);
18249 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18252 const struct mips16_immed_operand
*op
;
18253 bfd_boolean small
, ext
;
18256 unsigned long insn
;
18257 bfd_boolean use_extend
;
18258 unsigned short extend
;
18260 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18261 op
= mips16_immed_operands
;
18262 while (op
->type
!= type
)
18265 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18276 val
= resolve_symbol_value (fragp
->fr_symbol
);
18281 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18283 /* The rules for the base address of a PC relative reloc are
18284 complicated; see mips16_extended_frag. */
18285 if (type
== 'p' || type
== 'q')
18290 /* Ignore the low bit in the target, since it will be
18291 set for a text label. */
18292 if ((val
& 1) != 0)
18295 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18297 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18300 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18303 /* Make sure the section winds up with the alignment we have
18306 record_alignment (asec
, op
->shift
);
18310 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18311 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18312 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18313 _("extended instruction in delay slot"));
18315 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
18317 if (target_big_endian
)
18318 insn
= bfd_getb16 (buf
);
18320 insn
= bfd_getl16 (buf
);
18322 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
18323 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
18324 small
, ext
, &insn
, &use_extend
, &extend
);
18328 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
18329 fragp
->fr_fix
+= 2;
18333 md_number_to_chars ((char *) buf
, insn
, 2);
18334 fragp
->fr_fix
+= 2;
18339 relax_substateT subtype
= fragp
->fr_subtype
;
18340 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18341 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18345 first
= RELAX_FIRST (subtype
);
18346 second
= RELAX_SECOND (subtype
);
18347 fixp
= (fixS
*) fragp
->fr_opcode
;
18349 /* If the delay slot chosen does not match the size of the instruction,
18350 then emit a warning. */
18351 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18352 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18357 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18358 | RELAX_DELAY_SLOT_SIZE_FIRST
18359 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18360 msg
= macro_warning (s
);
18362 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18366 /* Possibly emit a warning if we've chosen the longer option. */
18367 if (use_second
== second_longer
)
18373 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18374 msg
= macro_warning (s
);
18376 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18380 /* Go through all the fixups for the first sequence. Disable them
18381 (by marking them as done) if we're going to use the second
18382 sequence instead. */
18384 && fixp
->fx_frag
== fragp
18385 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18387 if (subtype
& RELAX_USE_SECOND
)
18389 fixp
= fixp
->fx_next
;
18392 /* Go through the fixups for the second sequence. Disable them if
18393 we're going to use the first sequence, otherwise adjust their
18394 addresses to account for the relaxation. */
18395 while (fixp
&& fixp
->fx_frag
== fragp
)
18397 if (subtype
& RELAX_USE_SECOND
)
18398 fixp
->fx_where
-= first
;
18401 fixp
= fixp
->fx_next
;
18404 /* Now modify the frag contents. */
18405 if (subtype
& RELAX_USE_SECOND
)
18409 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18410 memmove (start
, start
+ first
, second
);
18411 fragp
->fr_fix
-= first
;
18414 fragp
->fr_fix
-= second
;
18420 /* This function is called after the relocs have been generated.
18421 We've been storing mips16 text labels as odd. Here we convert them
18422 back to even for the convenience of the debugger. */
18425 mips_frob_file_after_relocs (void)
18428 unsigned int count
, i
;
18433 syms
= bfd_get_outsymbols (stdoutput
);
18434 count
= bfd_get_symcount (stdoutput
);
18435 for (i
= 0; i
< count
; i
++, syms
++)
18436 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18437 && ((*syms
)->value
& 1) != 0)
18439 (*syms
)->value
&= ~1;
18440 /* If the symbol has an odd size, it was probably computed
18441 incorrectly, so adjust that as well. */
18442 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18443 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18449 /* This function is called whenever a label is defined, including fake
18450 labels instantiated off the dot special symbol. It is used when
18451 handling branch delays; if a branch has a label, we assume we cannot
18452 move it. This also bumps the value of the symbol by 1 in compressed
18456 mips_record_label (symbolS
*sym
)
18458 segment_info_type
*si
= seg_info (now_seg
);
18459 struct insn_label_list
*l
;
18461 if (free_insn_labels
== NULL
)
18462 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18465 l
= free_insn_labels
;
18466 free_insn_labels
= l
->next
;
18470 l
->next
= si
->label_list
;
18471 si
->label_list
= l
;
18474 /* This function is called as tc_frob_label() whenever a label is defined
18475 and adds a DWARF-2 record we only want for true labels. */
18478 mips_define_label (symbolS
*sym
)
18480 mips_record_label (sym
);
18482 dwarf2_emit_label (sym
);
18486 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18488 /* Some special processing for a MIPS ELF file. */
18491 mips_elf_final_processing (void)
18493 /* Write out the register information. */
18494 if (mips_abi
!= N64_ABI
)
18498 s
.ri_gprmask
= mips_gprmask
;
18499 s
.ri_cprmask
[0] = mips_cprmask
[0];
18500 s
.ri_cprmask
[1] = mips_cprmask
[1];
18501 s
.ri_cprmask
[2] = mips_cprmask
[2];
18502 s
.ri_cprmask
[3] = mips_cprmask
[3];
18503 /* The gp_value field is set by the MIPS ELF backend. */
18505 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18506 ((Elf32_External_RegInfo
*)
18507 mips_regmask_frag
));
18511 Elf64_Internal_RegInfo s
;
18513 s
.ri_gprmask
= mips_gprmask
;
18515 s
.ri_cprmask
[0] = mips_cprmask
[0];
18516 s
.ri_cprmask
[1] = mips_cprmask
[1];
18517 s
.ri_cprmask
[2] = mips_cprmask
[2];
18518 s
.ri_cprmask
[3] = mips_cprmask
[3];
18519 /* The gp_value field is set by the MIPS ELF backend. */
18521 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18522 ((Elf64_External_RegInfo
*)
18523 mips_regmask_frag
));
18526 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18527 sort of BFD interface for this. */
18528 if (mips_any_noreorder
)
18529 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18530 if (mips_pic
!= NO_PIC
)
18532 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18533 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18536 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18538 /* Set MIPS ELF flags for ASEs. */
18539 /* We may need to define a new flag for DSP ASE, and set this flag when
18540 file_ase_dsp is true. */
18541 /* Same for DSP R2. */
18542 /* We may need to define a new flag for MT ASE, and set this flag when
18543 file_ase_mt is true. */
18544 if (file_ase_mips16
)
18545 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18546 if (file_ase_micromips
)
18547 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18548 #if 0 /* XXX FIXME */
18549 if (file_ase_mips3d
)
18550 elf_elfheader (stdoutput
)->e_flags
|= ???;
18553 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18555 /* Set the MIPS ELF ABI flags. */
18556 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18557 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18558 else if (mips_abi
== O64_ABI
)
18559 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18560 else if (mips_abi
== EABI_ABI
)
18562 if (!file_mips_gp32
)
18563 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18565 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18567 else if (mips_abi
== N32_ABI
)
18568 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18570 /* Nothing to do for N64_ABI. */
18572 if (mips_32bitmode
)
18573 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18575 #if 0 /* XXX FIXME */
18576 /* 32 bit code with 64 bit FP registers. */
18577 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18578 elf_elfheader (stdoutput
)->e_flags
|= ???;
18582 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18584 typedef struct proc
{
18586 symbolS
*func_end_sym
;
18587 unsigned long reg_mask
;
18588 unsigned long reg_offset
;
18589 unsigned long fpreg_mask
;
18590 unsigned long fpreg_offset
;
18591 unsigned long frame_offset
;
18592 unsigned long frame_reg
;
18593 unsigned long pc_reg
;
18596 static procS cur_proc
;
18597 static procS
*cur_proc_ptr
;
18598 static int numprocs
;
18600 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18601 as "2", and a normal nop as "0". */
18603 #define NOP_OPCODE_MIPS 0
18604 #define NOP_OPCODE_MIPS16 1
18605 #define NOP_OPCODE_MICROMIPS 2
18608 mips_nop_opcode (void)
18610 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18611 return NOP_OPCODE_MICROMIPS
;
18612 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18613 return NOP_OPCODE_MIPS16
;
18615 return NOP_OPCODE_MIPS
;
18618 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18619 32-bit microMIPS NOPs here (if applicable). */
18622 mips_handle_align (fragS
*fragp
)
18626 int bytes
, size
, excess
;
18629 if (fragp
->fr_type
!= rs_align_code
)
18632 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18634 switch (nop_opcode
)
18636 case NOP_OPCODE_MICROMIPS
:
18637 opcode
= micromips_nop32_insn
.insn_opcode
;
18640 case NOP_OPCODE_MIPS16
:
18641 opcode
= mips16_nop_insn
.insn_opcode
;
18644 case NOP_OPCODE_MIPS
:
18646 opcode
= nop_insn
.insn_opcode
;
18651 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18652 excess
= bytes
% size
;
18654 /* Handle the leading part if we're not inserting a whole number of
18655 instructions, and make it the end of the fixed part of the frag.
18656 Try to fit in a short microMIPS NOP if applicable and possible,
18657 and use zeroes otherwise. */
18658 gas_assert (excess
< 4);
18659 fragp
->fr_fix
+= excess
;
18664 /* Fall through. */
18666 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18668 md_number_to_chars (p
, micromips_nop16_insn
.insn_opcode
, 2);
18673 /* Fall through. */
18676 /* Fall through. */
18681 md_number_to_chars (p
, opcode
, size
);
18682 fragp
->fr_var
= size
;
18686 md_obj_begin (void)
18693 /* Check for premature end, nesting errors, etc. */
18695 as_warn (_("missing .end at end of assembly"));
18704 if (*input_line_pointer
== '-')
18706 ++input_line_pointer
;
18709 if (!ISDIGIT (*input_line_pointer
))
18710 as_bad (_("expected simple number"));
18711 if (input_line_pointer
[0] == '0')
18713 if (input_line_pointer
[1] == 'x')
18715 input_line_pointer
+= 2;
18716 while (ISXDIGIT (*input_line_pointer
))
18719 val
|= hex_value (*input_line_pointer
++);
18721 return negative
? -val
: val
;
18725 ++input_line_pointer
;
18726 while (ISDIGIT (*input_line_pointer
))
18729 val
|= *input_line_pointer
++ - '0';
18731 return negative
? -val
: val
;
18734 if (!ISDIGIT (*input_line_pointer
))
18736 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18737 *input_line_pointer
, *input_line_pointer
);
18738 as_warn (_("invalid number"));
18741 while (ISDIGIT (*input_line_pointer
))
18744 val
+= *input_line_pointer
++ - '0';
18746 return negative
? -val
: val
;
18749 /* The .file directive; just like the usual .file directive, but there
18750 is an initial number which is the ECOFF file index. In the non-ECOFF
18751 case .file implies DWARF-2. */
18754 s_mips_file (int x ATTRIBUTE_UNUSED
)
18756 static int first_file_directive
= 0;
18758 if (ECOFF_DEBUGGING
)
18767 filename
= dwarf2_directive_file (0);
18769 /* Versions of GCC up to 3.1 start files with a ".file"
18770 directive even for stabs output. Make sure that this
18771 ".file" is handled. Note that you need a version of GCC
18772 after 3.1 in order to support DWARF-2 on MIPS. */
18773 if (filename
!= NULL
&& ! first_file_directive
)
18775 (void) new_logical_line (filename
, -1);
18776 s_app_file_string (filename
, 0);
18778 first_file_directive
= 1;
18782 /* The .loc directive, implying DWARF-2. */
18785 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18787 if (!ECOFF_DEBUGGING
)
18788 dwarf2_directive_loc (0);
18791 /* The .end directive. */
18794 s_mips_end (int x ATTRIBUTE_UNUSED
)
18798 /* Following functions need their own .frame and .cprestore directives. */
18799 mips_frame_reg_valid
= 0;
18800 mips_cprestore_valid
= 0;
18802 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18805 demand_empty_rest_of_line ();
18810 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18811 as_warn (_(".end not in text section"));
18815 as_warn (_(".end directive without a preceding .ent directive."));
18816 demand_empty_rest_of_line ();
18822 gas_assert (S_GET_NAME (p
));
18823 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18824 as_warn (_(".end symbol does not match .ent symbol."));
18826 if (debug_type
== DEBUG_STABS
)
18827 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18831 as_warn (_(".end directive missing or unknown symbol"));
18834 /* Create an expression to calculate the size of the function. */
18835 if (p
&& cur_proc_ptr
)
18837 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18838 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18841 exp
->X_op
= O_subtract
;
18842 exp
->X_add_symbol
= symbol_temp_new_now ();
18843 exp
->X_op_symbol
= p
;
18844 exp
->X_add_number
= 0;
18846 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18849 /* Generate a .pdr section. */
18850 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18852 segT saved_seg
= now_seg
;
18853 subsegT saved_subseg
= now_subseg
;
18857 #ifdef md_flush_pending_output
18858 md_flush_pending_output ();
18861 gas_assert (pdr_seg
);
18862 subseg_set (pdr_seg
, 0);
18864 /* Write the symbol. */
18865 exp
.X_op
= O_symbol
;
18866 exp
.X_add_symbol
= p
;
18867 exp
.X_add_number
= 0;
18868 emit_expr (&exp
, 4);
18870 fragp
= frag_more (7 * 4);
18872 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18873 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18874 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18875 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18876 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18877 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18878 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18880 subseg_set (saved_seg
, saved_subseg
);
18882 #endif /* OBJ_ELF */
18884 cur_proc_ptr
= NULL
;
18887 /* The .aent and .ent directives. */
18890 s_mips_ent (int aent
)
18894 symbolP
= get_symbol ();
18895 if (*input_line_pointer
== ',')
18896 ++input_line_pointer
;
18897 SKIP_WHITESPACE ();
18898 if (ISDIGIT (*input_line_pointer
)
18899 || *input_line_pointer
== '-')
18902 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18903 as_warn (_(".ent or .aent not in text section."));
18905 if (!aent
&& cur_proc_ptr
)
18906 as_warn (_("missing .end"));
18910 /* This function needs its own .frame and .cprestore directives. */
18911 mips_frame_reg_valid
= 0;
18912 mips_cprestore_valid
= 0;
18914 cur_proc_ptr
= &cur_proc
;
18915 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18917 cur_proc_ptr
->func_sym
= symbolP
;
18921 if (debug_type
== DEBUG_STABS
)
18922 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18923 S_GET_NAME (symbolP
));
18926 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18928 demand_empty_rest_of_line ();
18931 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18932 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18933 s_mips_frame is used so that we can set the PDR information correctly.
18934 We can't use the ecoff routines because they make reference to the ecoff
18935 symbol table (in the mdebug section). */
18938 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18941 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18945 if (cur_proc_ptr
== (procS
*) NULL
)
18947 as_warn (_(".frame outside of .ent"));
18948 demand_empty_rest_of_line ();
18952 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18954 SKIP_WHITESPACE ();
18955 if (*input_line_pointer
++ != ','
18956 || get_absolute_expression_and_terminator (&val
) != ',')
18958 as_warn (_("Bad .frame directive"));
18959 --input_line_pointer
;
18960 demand_empty_rest_of_line ();
18964 cur_proc_ptr
->frame_offset
= val
;
18965 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18967 demand_empty_rest_of_line ();
18970 #endif /* OBJ_ELF */
18974 /* The .fmask and .mask directives. If the mdebug section is present
18975 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18976 embedded targets, s_mips_mask is used so that we can set the PDR
18977 information correctly. We can't use the ecoff routines because they
18978 make reference to the ecoff symbol table (in the mdebug section). */
18981 s_mips_mask (int reg_type
)
18984 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18988 if (cur_proc_ptr
== (procS
*) NULL
)
18990 as_warn (_(".mask/.fmask outside of .ent"));
18991 demand_empty_rest_of_line ();
18995 if (get_absolute_expression_and_terminator (&mask
) != ',')
18997 as_warn (_("Bad .mask/.fmask directive"));
18998 --input_line_pointer
;
18999 demand_empty_rest_of_line ();
19003 off
= get_absolute_expression ();
19005 if (reg_type
== 'F')
19007 cur_proc_ptr
->fpreg_mask
= mask
;
19008 cur_proc_ptr
->fpreg_offset
= off
;
19012 cur_proc_ptr
->reg_mask
= mask
;
19013 cur_proc_ptr
->reg_offset
= off
;
19016 demand_empty_rest_of_line ();
19019 #endif /* OBJ_ELF */
19020 s_ignore (reg_type
);
19023 /* A table describing all the processors gas knows about. Names are
19024 matched in the order listed.
19026 To ease comparison, please keep this table in the same order as
19027 gcc's mips_cpu_info_table[]. */
19028 static const struct mips_cpu_info mips_cpu_info_table
[] =
19030 /* Entries for generic ISAs */
19031 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19032 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19033 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19034 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19035 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19036 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19037 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19038 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19039 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19042 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19043 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19044 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19047 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19050 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19051 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19052 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19053 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19054 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19055 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19056 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19057 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19058 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19059 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19060 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19061 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19062 /* ST Microelectronics Loongson 2E and 2F cores */
19063 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19064 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19067 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19068 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19069 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19070 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19071 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19072 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19073 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19074 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19075 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19076 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19077 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19078 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19079 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19080 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19081 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19084 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19085 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19086 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19087 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19089 /* MIPS 32 Release 2 */
19090 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19091 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19092 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19093 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19094 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19095 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19096 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19097 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19098 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19099 ISA_MIPS32R2
, CPU_MIPS32R2
},
19100 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19101 ISA_MIPS32R2
, CPU_MIPS32R2
},
19102 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19103 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19104 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19105 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19106 /* Deprecated forms of the above. */
19107 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19108 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19109 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19110 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19111 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19112 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19113 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19114 /* Deprecated forms of the above. */
19115 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19116 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19117 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19118 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19119 ISA_MIPS32R2
, CPU_MIPS32R2
},
19120 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19121 ISA_MIPS32R2
, CPU_MIPS32R2
},
19122 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19123 ISA_MIPS32R2
, CPU_MIPS32R2
},
19124 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19125 ISA_MIPS32R2
, CPU_MIPS32R2
},
19126 /* Deprecated forms of the above. */
19127 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19128 ISA_MIPS32R2
, CPU_MIPS32R2
},
19129 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19130 ISA_MIPS32R2
, CPU_MIPS32R2
},
19131 /* 34Kn is a 34kc without DSP. */
19132 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19133 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19134 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19135 ISA_MIPS32R2
, CPU_MIPS32R2
},
19136 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19137 ISA_MIPS32R2
, CPU_MIPS32R2
},
19138 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19139 ISA_MIPS32R2
, CPU_MIPS32R2
},
19140 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19141 ISA_MIPS32R2
, CPU_MIPS32R2
},
19142 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19143 ISA_MIPS32R2
, CPU_MIPS32R2
},
19144 /* Deprecated forms of the above. */
19145 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19146 ISA_MIPS32R2
, CPU_MIPS32R2
},
19147 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19148 ISA_MIPS32R2
, CPU_MIPS32R2
},
19149 /* 1004K cores are multiprocessor versions of the 34K. */
19150 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19151 ISA_MIPS32R2
, CPU_MIPS32R2
},
19152 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19153 ISA_MIPS32R2
, CPU_MIPS32R2
},
19154 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19155 ISA_MIPS32R2
, CPU_MIPS32R2
},
19156 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19157 ISA_MIPS32R2
, CPU_MIPS32R2
},
19160 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19161 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19162 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19163 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19165 /* Broadcom SB-1 CPU core */
19166 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19167 ISA_MIPS64
, CPU_SB1
},
19168 /* Broadcom SB-1A CPU core */
19169 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19170 ISA_MIPS64
, CPU_SB1
},
19172 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19174 /* MIPS 64 Release 2 */
19176 /* Cavium Networks Octeon CPU core */
19177 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19178 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19179 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19182 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19185 XLP is mostly like XLR, with the prominent exception that it is
19186 MIPS64R2 rather than MIPS64. */
19187 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19194 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19195 with a final "000" replaced by "k". Ignore case.
19197 Note: this function is shared between GCC and GAS. */
19200 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19202 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19203 given
++, canonical
++;
19205 return ((*given
== 0 && *canonical
== 0)
19206 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19210 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19211 CPU name. We've traditionally allowed a lot of variation here.
19213 Note: this function is shared between GCC and GAS. */
19216 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19218 /* First see if the name matches exactly, or with a final "000"
19219 turned into "k". */
19220 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19223 /* If not, try comparing based on numerical designation alone.
19224 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19225 if (TOLOWER (*given
) == 'r')
19227 if (!ISDIGIT (*given
))
19230 /* Skip over some well-known prefixes in the canonical name,
19231 hoping to find a number there too. */
19232 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19234 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19236 else if (TOLOWER (canonical
[0]) == 'r')
19239 return mips_strict_matching_cpu_name_p (canonical
, given
);
19243 /* Parse an option that takes the name of a processor as its argument.
19244 OPTION is the name of the option and CPU_STRING is the argument.
19245 Return the corresponding processor enumeration if the CPU_STRING is
19246 recognized, otherwise report an error and return null.
19248 A similar function exists in GCC. */
19250 static const struct mips_cpu_info
*
19251 mips_parse_cpu (const char *option
, const char *cpu_string
)
19253 const struct mips_cpu_info
*p
;
19255 /* 'from-abi' selects the most compatible architecture for the given
19256 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19257 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19258 version. Look first at the -mgp options, if given, otherwise base
19259 the choice on MIPS_DEFAULT_64BIT.
19261 Treat NO_ABI like the EABIs. One reason to do this is that the
19262 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19263 architecture. This code picks MIPS I for 'mips' and MIPS III for
19264 'mips64', just as we did in the days before 'from-abi'. */
19265 if (strcasecmp (cpu_string
, "from-abi") == 0)
19267 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19268 return mips_cpu_info_from_isa (ISA_MIPS1
);
19270 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19271 return mips_cpu_info_from_isa (ISA_MIPS3
);
19273 if (file_mips_gp32
>= 0)
19274 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19276 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19281 /* 'default' has traditionally been a no-op. Probably not very useful. */
19282 if (strcasecmp (cpu_string
, "default") == 0)
19285 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19286 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19289 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19293 /* Return the canonical processor information for ISA (a member of the
19294 ISA_MIPS* enumeration). */
19296 static const struct mips_cpu_info
*
19297 mips_cpu_info_from_isa (int isa
)
19301 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19302 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19303 && isa
== mips_cpu_info_table
[i
].isa
)
19304 return (&mips_cpu_info_table
[i
]);
19309 static const struct mips_cpu_info
*
19310 mips_cpu_info_from_arch (int arch
)
19314 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19315 if (arch
== mips_cpu_info_table
[i
].cpu
)
19316 return (&mips_cpu_info_table
[i
]);
19322 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19326 fprintf (stream
, "%24s", "");
19331 fprintf (stream
, ", ");
19335 if (*col_p
+ strlen (string
) > 72)
19337 fprintf (stream
, "\n%24s", "");
19341 fprintf (stream
, "%s", string
);
19342 *col_p
+= strlen (string
);
19348 md_show_usage (FILE *stream
)
19353 fprintf (stream
, _("\
19355 -EB generate big endian output\n\
19356 -EL generate little endian output\n\
19357 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19358 -G NUM allow referencing objects up to NUM bytes\n\
19359 implicitly with the gp register [default 8]\n"));
19360 fprintf (stream
, _("\
19361 -mips1 generate MIPS ISA I instructions\n\
19362 -mips2 generate MIPS ISA II instructions\n\
19363 -mips3 generate MIPS ISA III instructions\n\
19364 -mips4 generate MIPS ISA IV instructions\n\
19365 -mips5 generate MIPS ISA V instructions\n\
19366 -mips32 generate MIPS32 ISA instructions\n\
19367 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19368 -mips64 generate MIPS64 ISA instructions\n\
19369 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19370 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19374 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19375 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19376 show (stream
, "from-abi", &column
, &first
);
19377 fputc ('\n', stream
);
19379 fprintf (stream
, _("\
19380 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19381 -no-mCPU don't generate code specific to CPU.\n\
19382 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19386 show (stream
, "3900", &column
, &first
);
19387 show (stream
, "4010", &column
, &first
);
19388 show (stream
, "4100", &column
, &first
);
19389 show (stream
, "4650", &column
, &first
);
19390 fputc ('\n', stream
);
19392 fprintf (stream
, _("\
19393 -mips16 generate mips16 instructions\n\
19394 -no-mips16 do not generate mips16 instructions\n"));
19395 fprintf (stream
, _("\
19396 -mmicromips generate microMIPS instructions\n\
19397 -mno-micromips do not generate microMIPS instructions\n"));
19398 fprintf (stream
, _("\
19399 -msmartmips generate smartmips instructions\n\
19400 -mno-smartmips do not generate smartmips instructions\n"));
19401 fprintf (stream
, _("\
19402 -mdsp generate DSP instructions\n\
19403 -mno-dsp do not generate DSP instructions\n"));
19404 fprintf (stream
, _("\
19405 -mdspr2 generate DSP R2 instructions\n\
19406 -mno-dspr2 do not generate DSP R2 instructions\n"));
19407 fprintf (stream
, _("\
19408 -mmt generate MT instructions\n\
19409 -mno-mt do not generate MT instructions\n"));
19410 fprintf (stream
, _("\
19411 -mmcu generate MCU instructions\n\
19412 -mno-mcu do not generate MCU instructions\n"));
19413 fprintf (stream
, _("\
19414 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19415 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19416 -mfix-vr4120 work around certain VR4120 errata\n\
19417 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19418 -mfix-24k insert a nop after ERET and DERET instructions\n\
19419 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19420 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19421 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19422 -msym32 assume all symbols have 32-bit values\n\
19423 -O0 remove unneeded NOPs, do not swap branches\n\
19424 -O remove unneeded NOPs and swap branches\n\
19425 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19426 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19427 fprintf (stream
, _("\
19428 -mhard-float allow floating-point instructions\n\
19429 -msoft-float do not allow floating-point instructions\n\
19430 -msingle-float only allow 32-bit floating-point operations\n\
19431 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19432 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19435 fprintf (stream
, _("\
19436 -KPIC, -call_shared generate SVR4 position independent code\n\
19437 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19438 -mvxworks-pic generate VxWorks position independent code\n\
19439 -non_shared do not generate code that can operate with DSOs\n\
19440 -xgot assume a 32 bit GOT\n\
19441 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19442 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19443 position dependent (non shared) code\n\
19444 -mabi=ABI create ABI conformant object file for:\n"));
19448 show (stream
, "32", &column
, &first
);
19449 show (stream
, "o64", &column
, &first
);
19450 show (stream
, "n32", &column
, &first
);
19451 show (stream
, "64", &column
, &first
);
19452 show (stream
, "eabi", &column
, &first
);
19454 fputc ('\n', stream
);
19456 fprintf (stream
, _("\
19457 -32 create o32 ABI object file (default)\n\
19458 -n32 create n32 ABI object file\n\
19459 -64 create 64 ABI object file\n"));
19465 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19467 if (HAVE_64BIT_SYMBOLS
)
19468 return dwarf2_format_64bit_irix
;
19470 return dwarf2_format_32bit
;
19475 mips_dwarf2_addr_size (void)
19477 if (HAVE_64BIT_OBJECTS
)
19483 /* Standard calling conventions leave the CFA at SP on entry. */
19485 mips_cfi_frame_initial_instructions (void)
19487 cfi_add_CFA_def_cfa_register (SP
);
19491 tc_mips_regname_to_dw2regnum (char *regname
)
19493 unsigned int regnum
= -1;
19496 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))