1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \
1138 | ((pic) ? 0x100 : 0) \
1139 | ((sym32) ? 0x200 : 0) \
1140 | ((nomacro) ? 0x400 : 0) \
1141 | ((small) ? 0x800 : 0) \
1142 | ((ext) ? 0x1000 : 0) \
1143 | ((dslot) ? 0x2000 : 0) \
1144 | ((jal_dslot) ? 0x4000 : 0))
1146 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1147 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1148 #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0)
1149 #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0)
1150 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0)
1151 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0)
1152 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0)
1153 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0)
1157 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000)
1158 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000)
1159 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0)
1160 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000)
1161 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000)
1162 #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0)
1163 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000)
1164 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000)
1166 /* For microMIPS code, we use relaxation similar to one we use for
1167 MIPS16 code. Some instructions that take immediate values support
1168 two encodings: a small one which takes some small value, and a
1169 larger one which takes a 16 bit value. As some branches also follow
1170 this pattern, relaxing these values is required.
1172 We can assemble both microMIPS and normal MIPS code in a single
1173 object. Therefore, we need to support this type of relaxation at
1174 the same time that we support the relaxation described above. We
1175 use one of the high bits of the subtype field to distinguish these
1178 The information we store for this type of relaxation is the argument
1179 code found in the opcode file for this relocation, the register
1180 selected as the assembler temporary, whether in the 32-bit
1181 instruction mode, whether the branch is unconditional, whether it is
1182 compact, whether there is no delay-slot instruction available to fill
1183 in, whether it stores the link address implicitly in $ra, whether
1184 relaxation of out-of-range 32-bit branches to a sequence of
1185 instructions is enabled, and whether the displacement of a branch is
1186 too large to fit as an immediate argument of a 16-bit and a 32-bit
1187 branch, respectively. */
1188 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1189 uncond, compact, link, nods, \
1190 relax32, toofar16, toofar32) \
1193 | (((at) & 0x1f) << 8) \
1194 | ((insn32) ? 0x2000 : 0) \
1195 | ((pic) ? 0x4000 : 0) \
1196 | ((uncond) ? 0x8000 : 0) \
1197 | ((compact) ? 0x10000 : 0) \
1198 | ((link) ? 0x20000 : 0) \
1199 | ((nods) ? 0x40000 : 0) \
1200 | ((relax32) ? 0x80000 : 0) \
1201 | ((toofar16) ? 0x100000 : 0) \
1202 | ((toofar32) ? 0x200000 : 0))
1203 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1204 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1205 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1206 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1207 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1208 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1209 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1210 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1211 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1212 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1214 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1215 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1216 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1217 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1218 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1219 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1221 /* Sign-extend 16-bit value X. */
1222 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1224 /* Is the given value a sign-extended 32-bit value? */
1225 #define IS_SEXT_32BIT_NUM(x) \
1226 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1227 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1229 /* Is the given value a sign-extended 16-bit value? */
1230 #define IS_SEXT_16BIT_NUM(x) \
1231 (((x) &~ (offsetT) 0x7fff) == 0 \
1232 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1234 /* Is the given value a sign-extended 12-bit value? */
1235 #define IS_SEXT_12BIT_NUM(x) \
1236 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1238 /* Is the given value a sign-extended 9-bit value? */
1239 #define IS_SEXT_9BIT_NUM(x) \
1240 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1242 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1243 #define IS_ZEXT_32BIT_NUM(x) \
1244 (((x) &~ (offsetT) 0xffffffff) == 0 \
1245 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1247 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1249 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1250 (((STRUCT) >> (SHIFT)) & (MASK))
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes
[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p
;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length
;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes
[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes
[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns
[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning
;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1330 static void append_insn
1331 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1332 bfd_boolean expansionp
);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS
*, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS
*, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS
*, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn
*ip
, char *str
);
1341 static void mips16_macro (struct mips_cl_insn
* ip
);
1342 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1343 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1344 static void mips16_immed
1345 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1349 static void my_getExpression (expressionS
*, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_ehword (int);
1372 static void s_cpadd (int);
1373 static void s_insn (int);
1374 static void s_nan (int);
1375 static void s_module (int);
1376 static void s_mips_ent (int);
1377 static void s_mips_end (int);
1378 static void s_mips_frame (int);
1379 static void s_mips_mask (int reg_type
);
1380 static void s_mips_stab (int);
1381 static void s_mips_weakext (int);
1382 static void s_mips_file (int);
1383 static void s_mips_loc (int);
1384 static bfd_boolean
pic_need_relax (symbolS
*);
1385 static int relaxed_branch_length (fragS
*, asection
*, int);
1386 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1387 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1388 static void file_mips_check_options (void);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name
; /* CPU or ISA name. */
1396 int flags
; /* MIPS_CPU_* flags. */
1397 int ase
; /* Set of ASEs implemented by the CPU. */
1398 int isa
; /* ISA level. */
1399 int cpu
; /* CPU number (default CPU if ISA). */
1402 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1404 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1405 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1406 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1408 /* Command-line options. */
1409 const char *md_shortopts
= "O::g::G:";
1413 OPTION_MARCH
= OPTION_MD_BASE
,
1445 OPTION_NO_SMARTMIPS
,
1455 OPTION_NO_MICROMIPS
,
1458 OPTION_COMPAT_ARCH_BASE
,
1467 OPTION_M7000_HILO_FIX
,
1468 OPTION_MNO_7000_HILO_FIX
,
1472 OPTION_NO_FIX_RM7000
,
1473 OPTION_FIX_LOONGSON2F_JUMP
,
1474 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1475 OPTION_FIX_LOONGSON2F_NOP
,
1476 OPTION_NO_FIX_LOONGSON2F_NOP
,
1478 OPTION_NO_FIX_VR4120
,
1480 OPTION_NO_FIX_VR4130
,
1481 OPTION_FIX_CN63XXP1
,
1482 OPTION_NO_FIX_CN63XXP1
,
1489 OPTION_CONSTRUCT_FLOATS
,
1490 OPTION_NO_CONSTRUCT_FLOATS
,
1494 OPTION_RELAX_BRANCH
,
1495 OPTION_NO_RELAX_BRANCH
,
1496 OPTION_IGNORE_BRANCH_ISA
,
1497 OPTION_NO_IGNORE_BRANCH_ISA
,
1506 OPTION_SINGLE_FLOAT
,
1507 OPTION_DOUBLE_FLOAT
,
1520 OPTION_MVXWORKS_PIC
,
1523 OPTION_NO_ODD_SPREG
,
1527 struct option md_longopts
[] =
1529 /* Options which specify architecture. */
1530 {"march", required_argument
, NULL
, OPTION_MARCH
},
1531 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1532 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1533 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1534 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1535 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1536 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1537 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1538 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1539 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1540 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1541 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1542 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1543 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1544 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1545 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1546 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1547 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1549 /* Options which specify Application Specific Extensions (ASEs). */
1550 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1551 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1552 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1553 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1554 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1555 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1556 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1557 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1558 {"mmt", no_argument
, NULL
, OPTION_MT
},
1559 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1560 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1561 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1562 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1563 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1564 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1565 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1566 {"meva", no_argument
, NULL
, OPTION_EVA
},
1567 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1568 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1569 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1570 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1571 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1572 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1573 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1574 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1575 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1576 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1577 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1579 /* Old-style architecture options. Don't add more of these. */
1580 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1581 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1582 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1583 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1584 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1585 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1586 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1587 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1589 /* Options which enable bug fixes. */
1590 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1591 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1592 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1593 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1594 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1595 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1596 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1597 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1598 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1599 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1600 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1601 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1602 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1603 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1604 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1605 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1606 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1608 /* Miscellaneous options. */
1609 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1610 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1611 {"break", no_argument
, NULL
, OPTION_BREAK
},
1612 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1613 {"EB", no_argument
, NULL
, OPTION_EB
},
1614 {"EL", no_argument
, NULL
, OPTION_EL
},
1615 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1616 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1617 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1618 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1619 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1620 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1621 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1622 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1623 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1624 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1625 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1626 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1627 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1628 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1629 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1630 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1631 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1632 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1633 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1634 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1635 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1636 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1637 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1639 /* Strictly speaking this next option is ELF specific,
1640 but we allow it for other ports as well in order to
1641 make testing easier. */
1642 {"32", no_argument
, NULL
, OPTION_32
},
1644 /* ELF-specific options. */
1645 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1646 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1647 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1648 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1649 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1650 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1651 {"n32", no_argument
, NULL
, OPTION_N32
},
1652 {"64", no_argument
, NULL
, OPTION_64
},
1653 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1654 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1655 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1656 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1657 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1658 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1660 {NULL
, no_argument
, NULL
, 0}
1662 size_t md_longopts_size
= sizeof (md_longopts
);
1664 /* Information about either an Application Specific Extension or an
1665 optional architecture feature that, for simplicity, we treat in the
1666 same way as an ASE. */
1669 /* The name of the ASE, used in both the command-line and .set options. */
1672 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1673 and 64-bit architectures, the flags here refer to the subset that
1674 is available on both. */
1677 /* The ASE_* flag used for instructions that are available on 64-bit
1678 architectures but that are not included in FLAGS. */
1679 unsigned int flags64
;
1681 /* The command-line options that turn the ASE on and off. */
1685 /* The minimum required architecture revisions for MIPS32, MIPS64,
1686 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1689 int micromips32_rev
;
1690 int micromips64_rev
;
1692 /* The architecture where the ASE was removed or -1 if the extension has not
1697 /* A table of all supported ASEs. */
1698 static const struct mips_ase mips_ases
[] = {
1699 { "dsp", ASE_DSP
, ASE_DSP64
,
1700 OPTION_DSP
, OPTION_NO_DSP
,
1704 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1705 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1709 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1710 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1714 { "eva", ASE_EVA
, 0,
1715 OPTION_EVA
, OPTION_NO_EVA
,
1719 { "mcu", ASE_MCU
, 0,
1720 OPTION_MCU
, OPTION_NO_MCU
,
1724 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1725 { "mdmx", ASE_MDMX
, 0,
1726 OPTION_MDMX
, OPTION_NO_MDMX
,
1730 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1731 { "mips3d", ASE_MIPS3D
, 0,
1732 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1737 OPTION_MT
, OPTION_NO_MT
,
1741 { "smartmips", ASE_SMARTMIPS
, 0,
1742 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1746 { "virt", ASE_VIRT
, ASE_VIRT64
,
1747 OPTION_VIRT
, OPTION_NO_VIRT
,
1751 { "msa", ASE_MSA
, ASE_MSA64
,
1752 OPTION_MSA
, OPTION_NO_MSA
,
1756 { "xpa", ASE_XPA
, 0,
1757 OPTION_XPA
, OPTION_NO_XPA
,
1762 /* The set of ASEs that require -mfp64. */
1763 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1765 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1766 static const unsigned int mips_ase_groups
[] = {
1767 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1772 The following pseudo-ops from the Kane and Heinrich MIPS book
1773 should be defined here, but are currently unsupported: .alias,
1774 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1776 The following pseudo-ops from the Kane and Heinrich MIPS book are
1777 specific to the type of debugging information being generated, and
1778 should be defined by the object format: .aent, .begin, .bend,
1779 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1782 The following pseudo-ops from the Kane and Heinrich MIPS book are
1783 not MIPS CPU specific, but are also not specific to the object file
1784 format. This file is probably the best place to define them, but
1785 they are not currently supported: .asm0, .endr, .lab, .struct. */
1787 static const pseudo_typeS mips_pseudo_table
[] =
1789 /* MIPS specific pseudo-ops. */
1790 {"option", s_option
, 0},
1791 {"set", s_mipsset
, 0},
1792 {"rdata", s_change_sec
, 'r'},
1793 {"sdata", s_change_sec
, 's'},
1794 {"livereg", s_ignore
, 0},
1795 {"abicalls", s_abicalls
, 0},
1796 {"cpload", s_cpload
, 0},
1797 {"cpsetup", s_cpsetup
, 0},
1798 {"cplocal", s_cplocal
, 0},
1799 {"cprestore", s_cprestore
, 0},
1800 {"cpreturn", s_cpreturn
, 0},
1801 {"dtprelword", s_dtprelword
, 0},
1802 {"dtpreldword", s_dtpreldword
, 0},
1803 {"tprelword", s_tprelword
, 0},
1804 {"tpreldword", s_tpreldword
, 0},
1805 {"gpvalue", s_gpvalue
, 0},
1806 {"gpword", s_gpword
, 0},
1807 {"gpdword", s_gpdword
, 0},
1808 {"ehword", s_ehword
, 0},
1809 {"cpadd", s_cpadd
, 0},
1810 {"insn", s_insn
, 0},
1812 {"module", s_module
, 0},
1814 /* Relatively generic pseudo-ops that happen to be used on MIPS
1816 {"asciiz", stringer
, 8 + 1},
1817 {"bss", s_change_sec
, 'b'},
1819 {"half", s_cons
, 1},
1820 {"dword", s_cons
, 3},
1821 {"weakext", s_mips_weakext
, 0},
1822 {"origin", s_org
, 0},
1823 {"repeat", s_rept
, 0},
1825 /* For MIPS this is non-standard, but we define it for consistency. */
1826 {"sbss", s_change_sec
, 'B'},
1828 /* These pseudo-ops are defined in read.c, but must be overridden
1829 here for one reason or another. */
1830 {"align", s_align
, 0},
1831 {"byte", s_cons
, 0},
1832 {"data", s_change_sec
, 'd'},
1833 {"double", s_float_cons
, 'd'},
1834 {"float", s_float_cons
, 'f'},
1835 {"globl", s_mips_globl
, 0},
1836 {"global", s_mips_globl
, 0},
1837 {"hword", s_cons
, 1},
1839 {"long", s_cons
, 2},
1840 {"octa", s_cons
, 4},
1841 {"quad", s_cons
, 3},
1842 {"section", s_change_section
, 0},
1843 {"short", s_cons
, 1},
1844 {"single", s_float_cons
, 'f'},
1845 {"stabd", s_mips_stab
, 'd'},
1846 {"stabn", s_mips_stab
, 'n'},
1847 {"stabs", s_mips_stab
, 's'},
1848 {"text", s_change_sec
, 't'},
1849 {"word", s_cons
, 2},
1851 { "extern", ecoff_directive_extern
, 0},
1856 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1858 /* These pseudo-ops should be defined by the object file format.
1859 However, a.out doesn't support them, so we have versions here. */
1860 {"aent", s_mips_ent
, 1},
1861 {"bgnb", s_ignore
, 0},
1862 {"end", s_mips_end
, 0},
1863 {"endb", s_ignore
, 0},
1864 {"ent", s_mips_ent
, 0},
1865 {"file", s_mips_file
, 0},
1866 {"fmask", s_mips_mask
, 'F'},
1867 {"frame", s_mips_frame
, 0},
1868 {"loc", s_mips_loc
, 0},
1869 {"mask", s_mips_mask
, 'R'},
1870 {"verstamp", s_ignore
, 0},
1874 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1875 purpose of the `.dc.a' internal pseudo-op. */
1878 mips_address_bytes (void)
1880 file_mips_check_options ();
1881 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1884 extern void pop_insert (const pseudo_typeS
*);
1887 mips_pop_insert (void)
1889 pop_insert (mips_pseudo_table
);
1890 if (! ECOFF_DEBUGGING
)
1891 pop_insert (mips_nonecoff_pseudo_table
);
1894 /* Symbols labelling the current insn. */
1896 struct insn_label_list
1898 struct insn_label_list
*next
;
1902 static struct insn_label_list
*free_insn_labels
;
1903 #define label_list tc_segment_info_data.labels
1905 static void mips_clear_insn_labels (void);
1906 static void mips_mark_labels (void);
1907 static void mips_compressed_mark_labels (void);
1910 mips_clear_insn_labels (void)
1912 struct insn_label_list
**pl
;
1913 segment_info_type
*si
;
1917 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1920 si
= seg_info (now_seg
);
1921 *pl
= si
->label_list
;
1922 si
->label_list
= NULL
;
1926 /* Mark instruction labels in MIPS16/microMIPS mode. */
1929 mips_mark_labels (void)
1931 if (HAVE_CODE_COMPRESSION
)
1932 mips_compressed_mark_labels ();
1935 static char *expr_end
;
1937 /* An expression in a macro instruction. This is set by mips_ip and
1938 mips16_ip and when populated is always an O_constant. */
1940 static expressionS imm_expr
;
1942 /* The relocatable field in an instruction and the relocs associated
1943 with it. These variables are used for instructions like LUI and
1944 JAL as well as true offsets. They are also used for address
1945 operands in macros. */
1947 static expressionS offset_expr
;
1948 static bfd_reloc_code_real_type offset_reloc
[3]
1949 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1951 /* This is set to the resulting size of the instruction to be produced
1952 by mips16_ip if an explicit extension is used or by mips_ip if an
1953 explicit size is supplied. */
1955 static unsigned int forced_insn_length
;
1957 /* True if we are assembling an instruction. All dot symbols defined during
1958 this time should be treated as code labels. */
1960 static bfd_boolean mips_assembling_insn
;
1962 /* The pdr segment for per procedure frame/regmask info. Not used for
1965 static segT pdr_seg
;
1967 /* The default target format to use. */
1969 #if defined (TE_FreeBSD)
1970 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1971 #elif defined (TE_TMIPS)
1972 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1974 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1978 mips_target_format (void)
1980 switch (OUTPUT_FLAVOR
)
1982 case bfd_target_elf_flavour
:
1984 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1985 return (target_big_endian
1986 ? "elf32-bigmips-vxworks"
1987 : "elf32-littlemips-vxworks");
1989 return (target_big_endian
1990 ? (HAVE_64BIT_OBJECTS
1991 ? ELF_TARGET ("elf64-", "big")
1993 ? ELF_TARGET ("elf32-n", "big")
1994 : ELF_TARGET ("elf32-", "big")))
1995 : (HAVE_64BIT_OBJECTS
1996 ? ELF_TARGET ("elf64-", "little")
1998 ? ELF_TARGET ("elf32-n", "little")
1999 : ELF_TARGET ("elf32-", "little"))));
2006 /* Return the ISA revision that is currently in use, or 0 if we are
2007 generating code for MIPS V or below. */
2012 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2015 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2018 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2021 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2024 /* microMIPS implies revision 2 or above. */
2025 if (mips_opts
.micromips
)
2028 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2034 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2037 mips_ase_mask (unsigned int flags
)
2041 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2042 if (flags
& mips_ase_groups
[i
])
2043 flags
|= mips_ase_groups
[i
];
2047 /* Check whether the current ISA supports ASE. Issue a warning if
2051 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2055 static unsigned int warned_isa
;
2056 static unsigned int warned_fp32
;
2058 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2059 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2061 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2062 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2063 && (warned_isa
& ase
->flags
) != ase
->flags
)
2065 warned_isa
|= ase
->flags
;
2066 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2067 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2069 as_warn (_("the %d-bit %s architecture does not support the"
2070 " `%s' extension"), size
, base
, ase
->name
);
2072 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2073 ase
->name
, base
, size
, min_rev
);
2075 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2076 && (warned_isa
& ase
->flags
) != ase
->flags
)
2078 warned_isa
|= ase
->flags
;
2079 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2080 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2081 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2082 ase
->name
, base
, size
, ase
->rem_rev
);
2085 if ((ase
->flags
& FP64_ASES
)
2086 && mips_opts
.fp
!= 64
2087 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2089 warned_fp32
|= ase
->flags
;
2090 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2094 /* Check all enabled ASEs to see whether they are supported by the
2095 chosen architecture. */
2098 mips_check_isa_supports_ases (void)
2100 unsigned int i
, mask
;
2102 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2104 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2105 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2106 mips_check_isa_supports_ase (&mips_ases
[i
]);
2110 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2111 that were affected. */
2114 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2115 bfd_boolean enabled_p
)
2119 mask
= mips_ase_mask (ase
->flags
);
2122 opts
->ase
|= ase
->flags
;
2126 /* Return the ASE called NAME, or null if none. */
2128 static const struct mips_ase
*
2129 mips_lookup_ase (const char *name
)
2133 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2134 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2135 return &mips_ases
[i
];
2139 /* Return the length of a microMIPS instruction in bytes. If bits of
2140 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2141 otherwise it is a 32-bit instruction. */
2143 static inline unsigned int
2144 micromips_insn_length (const struct mips_opcode
*mo
)
2146 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2149 /* Return the length of MIPS16 instruction OPCODE. */
2151 static inline unsigned int
2152 mips16_opcode_length (unsigned long opcode
)
2154 return (opcode
>> 16) == 0 ? 2 : 4;
2157 /* Return the length of instruction INSN. */
2159 static inline unsigned int
2160 insn_length (const struct mips_cl_insn
*insn
)
2162 if (mips_opts
.micromips
)
2163 return micromips_insn_length (insn
->insn_mo
);
2164 else if (mips_opts
.mips16
)
2165 return mips16_opcode_length (insn
->insn_opcode
);
2170 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2173 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2178 insn
->insn_opcode
= mo
->match
;
2181 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2182 insn
->fixp
[i
] = NULL
;
2183 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2184 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2185 insn
->mips16_absolute_jump_p
= 0;
2186 insn
->complete_p
= 0;
2187 insn
->cleared_p
= 0;
2190 /* Get a list of all the operands in INSN. */
2192 static const struct mips_operand_array
*
2193 insn_operands (const struct mips_cl_insn
*insn
)
2195 if (insn
->insn_mo
>= &mips_opcodes
[0]
2196 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2197 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2199 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2200 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2201 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2203 if (insn
->insn_mo
>= µmips_opcodes
[0]
2204 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2205 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2210 /* Get a description of operand OPNO of INSN. */
2212 static const struct mips_operand
*
2213 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2215 const struct mips_operand_array
*operands
;
2217 operands
= insn_operands (insn
);
2218 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2220 return operands
->operand
[opno
];
2223 /* Install UVAL as the value of OPERAND in INSN. */
2226 insn_insert_operand (struct mips_cl_insn
*insn
,
2227 const struct mips_operand
*operand
, unsigned int uval
)
2229 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2232 /* Extract the value of OPERAND from INSN. */
2234 static inline unsigned
2235 insn_extract_operand (const struct mips_cl_insn
*insn
,
2236 const struct mips_operand
*operand
)
2238 return mips_extract_operand (operand
, insn
->insn_opcode
);
2241 /* Record the current MIPS16/microMIPS mode in now_seg. */
2244 mips_record_compressed_mode (void)
2246 segment_info_type
*si
;
2248 si
= seg_info (now_seg
);
2249 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2250 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2251 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2252 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2255 /* Read a standard MIPS instruction from BUF. */
2257 static unsigned long
2258 read_insn (char *buf
)
2260 if (target_big_endian
)
2261 return bfd_getb32 ((bfd_byte
*) buf
);
2263 return bfd_getl32 ((bfd_byte
*) buf
);
2266 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2270 write_insn (char *buf
, unsigned int insn
)
2272 md_number_to_chars (buf
, insn
, 4);
2276 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2277 has length LENGTH. */
2279 static unsigned long
2280 read_compressed_insn (char *buf
, unsigned int length
)
2286 for (i
= 0; i
< length
; i
+= 2)
2289 if (target_big_endian
)
2290 insn
|= bfd_getb16 ((char *) buf
);
2292 insn
|= bfd_getl16 ((char *) buf
);
2298 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2299 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2302 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2306 for (i
= 0; i
< length
; i
+= 2)
2307 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2308 return buf
+ length
;
2311 /* Install INSN at the location specified by its "frag" and "where" fields. */
2314 install_insn (const struct mips_cl_insn
*insn
)
2316 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2317 if (HAVE_CODE_COMPRESSION
)
2318 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2320 write_insn (f
, insn
->insn_opcode
);
2321 mips_record_compressed_mode ();
2324 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2325 and install the opcode in the new location. */
2328 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2333 insn
->where
= where
;
2334 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2335 if (insn
->fixp
[i
] != NULL
)
2337 insn
->fixp
[i
]->fx_frag
= frag
;
2338 insn
->fixp
[i
]->fx_where
= where
;
2340 install_insn (insn
);
2343 /* Add INSN to the end of the output. */
2346 add_fixed_insn (struct mips_cl_insn
*insn
)
2348 char *f
= frag_more (insn_length (insn
));
2349 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2352 /* Start a variant frag and move INSN to the start of the variant part,
2353 marking it as fixed. The other arguments are as for frag_var. */
2356 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2357 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2359 frag_grow (max_chars
);
2360 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2362 frag_var (rs_machine_dependent
, max_chars
, var
,
2363 subtype
, symbol
, offset
, NULL
);
2366 /* Insert N copies of INSN into the history buffer, starting at
2367 position FIRST. Neither FIRST nor N need to be clipped. */
2370 insert_into_history (unsigned int first
, unsigned int n
,
2371 const struct mips_cl_insn
*insn
)
2373 if (mips_relax
.sequence
!= 2)
2377 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2379 history
[i
] = history
[i
- n
];
2385 /* Clear the error in insn_error. */
2388 clear_insn_error (void)
2390 memset (&insn_error
, 0, sizeof (insn_error
));
2393 /* Possibly record error message MSG for the current instruction.
2394 If the error is about a particular argument, ARGNUM is the 1-based
2395 number of that argument, otherwise it is 0. FORMAT is the format
2396 of MSG. Return true if MSG was used, false if the current message
2400 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2405 /* Give priority to errors against specific arguments, and to
2406 the first whole-instruction message. */
2412 /* Keep insn_error if it is against a later argument. */
2413 if (argnum
< insn_error
.min_argnum
)
2416 /* If both errors are against the same argument but are different,
2417 give up on reporting a specific error for this argument.
2418 See the comment about mips_insn_error for details. */
2419 if (argnum
== insn_error
.min_argnum
2421 && strcmp (insn_error
.msg
, msg
) != 0)
2424 insn_error
.min_argnum
+= 1;
2428 insn_error
.min_argnum
= argnum
;
2429 insn_error
.format
= format
;
2430 insn_error
.msg
= msg
;
2434 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2435 as for set_insn_error_format. */
2438 set_insn_error (int argnum
, const char *msg
)
2440 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2443 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2444 as for set_insn_error_format. */
2447 set_insn_error_i (int argnum
, const char *msg
, int i
)
2449 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2453 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2454 are as for set_insn_error_format. */
2457 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2459 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2461 insn_error
.u
.ss
[0] = s1
;
2462 insn_error
.u
.ss
[1] = s2
;
2466 /* Report the error in insn_error, which is against assembly code STR. */
2469 report_insn_error (const char *str
)
2471 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2473 switch (insn_error
.format
)
2480 as_bad (msg
, insn_error
.u
.i
, str
);
2484 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2488 free ((char *) msg
);
2491 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2492 the idea is to make it obvious at a glance that each errata is
2496 init_vr4120_conflicts (void)
2498 #define CONFLICT(FIRST, SECOND) \
2499 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2501 /* Errata 21 - [D]DIV[U] after [D]MACC */
2502 CONFLICT (MACC
, DIV
);
2503 CONFLICT (DMACC
, DIV
);
2505 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2506 CONFLICT (DMULT
, DMULT
);
2507 CONFLICT (DMULT
, DMACC
);
2508 CONFLICT (DMACC
, DMULT
);
2509 CONFLICT (DMACC
, DMACC
);
2511 /* Errata 24 - MT{LO,HI} after [D]MACC */
2512 CONFLICT (MACC
, MTHILO
);
2513 CONFLICT (DMACC
, MTHILO
);
2515 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2516 instruction is executed immediately after a MACC or DMACC
2517 instruction, the result of [either instruction] is incorrect." */
2518 CONFLICT (MACC
, MULT
);
2519 CONFLICT (MACC
, DMULT
);
2520 CONFLICT (DMACC
, MULT
);
2521 CONFLICT (DMACC
, DMULT
);
2523 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2524 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2525 DDIV or DDIVU instruction, the result of the MACC or
2526 DMACC instruction is incorrect.". */
2527 CONFLICT (DMULT
, MACC
);
2528 CONFLICT (DMULT
, DMACC
);
2529 CONFLICT (DIV
, MACC
);
2530 CONFLICT (DIV
, DMACC
);
2540 #define RNUM_MASK 0x00000ff
2541 #define RTYPE_MASK 0x0ffff00
2542 #define RTYPE_NUM 0x0000100
2543 #define RTYPE_FPU 0x0000200
2544 #define RTYPE_FCC 0x0000400
2545 #define RTYPE_VEC 0x0000800
2546 #define RTYPE_GP 0x0001000
2547 #define RTYPE_CP0 0x0002000
2548 #define RTYPE_PC 0x0004000
2549 #define RTYPE_ACC 0x0008000
2550 #define RTYPE_CCC 0x0010000
2551 #define RTYPE_VI 0x0020000
2552 #define RTYPE_VF 0x0040000
2553 #define RTYPE_R5900_I 0x0080000
2554 #define RTYPE_R5900_Q 0x0100000
2555 #define RTYPE_R5900_R 0x0200000
2556 #define RTYPE_R5900_ACC 0x0400000
2557 #define RTYPE_MSA 0x0800000
2558 #define RWARN 0x8000000
2560 #define GENERIC_REGISTER_NUMBERS \
2561 {"$0", RTYPE_NUM | 0}, \
2562 {"$1", RTYPE_NUM | 1}, \
2563 {"$2", RTYPE_NUM | 2}, \
2564 {"$3", RTYPE_NUM | 3}, \
2565 {"$4", RTYPE_NUM | 4}, \
2566 {"$5", RTYPE_NUM | 5}, \
2567 {"$6", RTYPE_NUM | 6}, \
2568 {"$7", RTYPE_NUM | 7}, \
2569 {"$8", RTYPE_NUM | 8}, \
2570 {"$9", RTYPE_NUM | 9}, \
2571 {"$10", RTYPE_NUM | 10}, \
2572 {"$11", RTYPE_NUM | 11}, \
2573 {"$12", RTYPE_NUM | 12}, \
2574 {"$13", RTYPE_NUM | 13}, \
2575 {"$14", RTYPE_NUM | 14}, \
2576 {"$15", RTYPE_NUM | 15}, \
2577 {"$16", RTYPE_NUM | 16}, \
2578 {"$17", RTYPE_NUM | 17}, \
2579 {"$18", RTYPE_NUM | 18}, \
2580 {"$19", RTYPE_NUM | 19}, \
2581 {"$20", RTYPE_NUM | 20}, \
2582 {"$21", RTYPE_NUM | 21}, \
2583 {"$22", RTYPE_NUM | 22}, \
2584 {"$23", RTYPE_NUM | 23}, \
2585 {"$24", RTYPE_NUM | 24}, \
2586 {"$25", RTYPE_NUM | 25}, \
2587 {"$26", RTYPE_NUM | 26}, \
2588 {"$27", RTYPE_NUM | 27}, \
2589 {"$28", RTYPE_NUM | 28}, \
2590 {"$29", RTYPE_NUM | 29}, \
2591 {"$30", RTYPE_NUM | 30}, \
2592 {"$31", RTYPE_NUM | 31}
2594 #define FPU_REGISTER_NAMES \
2595 {"$f0", RTYPE_FPU | 0}, \
2596 {"$f1", RTYPE_FPU | 1}, \
2597 {"$f2", RTYPE_FPU | 2}, \
2598 {"$f3", RTYPE_FPU | 3}, \
2599 {"$f4", RTYPE_FPU | 4}, \
2600 {"$f5", RTYPE_FPU | 5}, \
2601 {"$f6", RTYPE_FPU | 6}, \
2602 {"$f7", RTYPE_FPU | 7}, \
2603 {"$f8", RTYPE_FPU | 8}, \
2604 {"$f9", RTYPE_FPU | 9}, \
2605 {"$f10", RTYPE_FPU | 10}, \
2606 {"$f11", RTYPE_FPU | 11}, \
2607 {"$f12", RTYPE_FPU | 12}, \
2608 {"$f13", RTYPE_FPU | 13}, \
2609 {"$f14", RTYPE_FPU | 14}, \
2610 {"$f15", RTYPE_FPU | 15}, \
2611 {"$f16", RTYPE_FPU | 16}, \
2612 {"$f17", RTYPE_FPU | 17}, \
2613 {"$f18", RTYPE_FPU | 18}, \
2614 {"$f19", RTYPE_FPU | 19}, \
2615 {"$f20", RTYPE_FPU | 20}, \
2616 {"$f21", RTYPE_FPU | 21}, \
2617 {"$f22", RTYPE_FPU | 22}, \
2618 {"$f23", RTYPE_FPU | 23}, \
2619 {"$f24", RTYPE_FPU | 24}, \
2620 {"$f25", RTYPE_FPU | 25}, \
2621 {"$f26", RTYPE_FPU | 26}, \
2622 {"$f27", RTYPE_FPU | 27}, \
2623 {"$f28", RTYPE_FPU | 28}, \
2624 {"$f29", RTYPE_FPU | 29}, \
2625 {"$f30", RTYPE_FPU | 30}, \
2626 {"$f31", RTYPE_FPU | 31}
2628 #define FPU_CONDITION_CODE_NAMES \
2629 {"$fcc0", RTYPE_FCC | 0}, \
2630 {"$fcc1", RTYPE_FCC | 1}, \
2631 {"$fcc2", RTYPE_FCC | 2}, \
2632 {"$fcc3", RTYPE_FCC | 3}, \
2633 {"$fcc4", RTYPE_FCC | 4}, \
2634 {"$fcc5", RTYPE_FCC | 5}, \
2635 {"$fcc6", RTYPE_FCC | 6}, \
2636 {"$fcc7", RTYPE_FCC | 7}
2638 #define COPROC_CONDITION_CODE_NAMES \
2639 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2640 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2641 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2642 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2643 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2644 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2645 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2646 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2648 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2649 {"$a4", RTYPE_GP | 8}, \
2650 {"$a5", RTYPE_GP | 9}, \
2651 {"$a6", RTYPE_GP | 10}, \
2652 {"$a7", RTYPE_GP | 11}, \
2653 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2654 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2655 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2656 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2657 {"$t0", RTYPE_GP | 12}, \
2658 {"$t1", RTYPE_GP | 13}, \
2659 {"$t2", RTYPE_GP | 14}, \
2660 {"$t3", RTYPE_GP | 15}
2662 #define O32_SYMBOLIC_REGISTER_NAMES \
2663 {"$t0", RTYPE_GP | 8}, \
2664 {"$t1", RTYPE_GP | 9}, \
2665 {"$t2", RTYPE_GP | 10}, \
2666 {"$t3", RTYPE_GP | 11}, \
2667 {"$t4", RTYPE_GP | 12}, \
2668 {"$t5", RTYPE_GP | 13}, \
2669 {"$t6", RTYPE_GP | 14}, \
2670 {"$t7", RTYPE_GP | 15}, \
2671 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2672 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2673 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2674 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2676 /* Remaining symbolic register names */
2677 #define SYMBOLIC_REGISTER_NAMES \
2678 {"$zero", RTYPE_GP | 0}, \
2679 {"$at", RTYPE_GP | 1}, \
2680 {"$AT", RTYPE_GP | 1}, \
2681 {"$v0", RTYPE_GP | 2}, \
2682 {"$v1", RTYPE_GP | 3}, \
2683 {"$a0", RTYPE_GP | 4}, \
2684 {"$a1", RTYPE_GP | 5}, \
2685 {"$a2", RTYPE_GP | 6}, \
2686 {"$a3", RTYPE_GP | 7}, \
2687 {"$s0", RTYPE_GP | 16}, \
2688 {"$s1", RTYPE_GP | 17}, \
2689 {"$s2", RTYPE_GP | 18}, \
2690 {"$s3", RTYPE_GP | 19}, \
2691 {"$s4", RTYPE_GP | 20}, \
2692 {"$s5", RTYPE_GP | 21}, \
2693 {"$s6", RTYPE_GP | 22}, \
2694 {"$s7", RTYPE_GP | 23}, \
2695 {"$t8", RTYPE_GP | 24}, \
2696 {"$t9", RTYPE_GP | 25}, \
2697 {"$k0", RTYPE_GP | 26}, \
2698 {"$kt0", RTYPE_GP | 26}, \
2699 {"$k1", RTYPE_GP | 27}, \
2700 {"$kt1", RTYPE_GP | 27}, \
2701 {"$gp", RTYPE_GP | 28}, \
2702 {"$sp", RTYPE_GP | 29}, \
2703 {"$s8", RTYPE_GP | 30}, \
2704 {"$fp", RTYPE_GP | 30}, \
2705 {"$ra", RTYPE_GP | 31}
2707 #define MIPS16_SPECIAL_REGISTER_NAMES \
2708 {"$pc", RTYPE_PC | 0}
2710 #define MDMX_VECTOR_REGISTER_NAMES \
2711 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2712 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2713 {"$v2", RTYPE_VEC | 2}, \
2714 {"$v3", RTYPE_VEC | 3}, \
2715 {"$v4", RTYPE_VEC | 4}, \
2716 {"$v5", RTYPE_VEC | 5}, \
2717 {"$v6", RTYPE_VEC | 6}, \
2718 {"$v7", RTYPE_VEC | 7}, \
2719 {"$v8", RTYPE_VEC | 8}, \
2720 {"$v9", RTYPE_VEC | 9}, \
2721 {"$v10", RTYPE_VEC | 10}, \
2722 {"$v11", RTYPE_VEC | 11}, \
2723 {"$v12", RTYPE_VEC | 12}, \
2724 {"$v13", RTYPE_VEC | 13}, \
2725 {"$v14", RTYPE_VEC | 14}, \
2726 {"$v15", RTYPE_VEC | 15}, \
2727 {"$v16", RTYPE_VEC | 16}, \
2728 {"$v17", RTYPE_VEC | 17}, \
2729 {"$v18", RTYPE_VEC | 18}, \
2730 {"$v19", RTYPE_VEC | 19}, \
2731 {"$v20", RTYPE_VEC | 20}, \
2732 {"$v21", RTYPE_VEC | 21}, \
2733 {"$v22", RTYPE_VEC | 22}, \
2734 {"$v23", RTYPE_VEC | 23}, \
2735 {"$v24", RTYPE_VEC | 24}, \
2736 {"$v25", RTYPE_VEC | 25}, \
2737 {"$v26", RTYPE_VEC | 26}, \
2738 {"$v27", RTYPE_VEC | 27}, \
2739 {"$v28", RTYPE_VEC | 28}, \
2740 {"$v29", RTYPE_VEC | 29}, \
2741 {"$v30", RTYPE_VEC | 30}, \
2742 {"$v31", RTYPE_VEC | 31}
2744 #define R5900_I_NAMES \
2745 {"$I", RTYPE_R5900_I | 0}
2747 #define R5900_Q_NAMES \
2748 {"$Q", RTYPE_R5900_Q | 0}
2750 #define R5900_R_NAMES \
2751 {"$R", RTYPE_R5900_R | 0}
2753 #define R5900_ACC_NAMES \
2754 {"$ACC", RTYPE_R5900_ACC | 0 }
2756 #define MIPS_DSP_ACCUMULATOR_NAMES \
2757 {"$ac0", RTYPE_ACC | 0}, \
2758 {"$ac1", RTYPE_ACC | 1}, \
2759 {"$ac2", RTYPE_ACC | 2}, \
2760 {"$ac3", RTYPE_ACC | 3}
2762 static const struct regname reg_names
[] = {
2763 GENERIC_REGISTER_NUMBERS
,
2765 FPU_CONDITION_CODE_NAMES
,
2766 COPROC_CONDITION_CODE_NAMES
,
2768 /* The $txx registers depends on the abi,
2769 these will be added later into the symbol table from
2770 one of the tables below once mips_abi is set after
2771 parsing of arguments from the command line. */
2772 SYMBOLIC_REGISTER_NAMES
,
2774 MIPS16_SPECIAL_REGISTER_NAMES
,
2775 MDMX_VECTOR_REGISTER_NAMES
,
2780 MIPS_DSP_ACCUMULATOR_NAMES
,
2784 static const struct regname reg_names_o32
[] = {
2785 O32_SYMBOLIC_REGISTER_NAMES
,
2789 static const struct regname reg_names_n32n64
[] = {
2790 N32N64_SYMBOLIC_REGISTER_NAMES
,
2794 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2795 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2796 of these register symbols, return the associated vector register,
2797 otherwise return SYMVAL itself. */
2800 mips_prefer_vec_regno (unsigned int symval
)
2802 if ((symval
& -2) == (RTYPE_GP
| 2))
2803 return RTYPE_VEC
| (symval
& 1);
2807 /* Return true if string [S, E) is a valid register name, storing its
2808 symbol value in *SYMVAL_PTR if so. */
2811 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2816 /* Terminate name. */
2820 /* Look up the name. */
2821 symbol
= symbol_find (s
);
2824 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2827 *symval_ptr
= S_GET_VALUE (symbol
);
2831 /* Return true if the string at *SPTR is a valid register name. Allow it
2832 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2835 When returning true, move *SPTR past the register, store the
2836 register's symbol value in *SYMVAL_PTR and the channel mask in
2837 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2838 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2839 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2842 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2843 unsigned int *channels_ptr
)
2847 unsigned int channels
, symval
, bit
;
2849 /* Find end of name. */
2851 if (is_name_beginner (*e
))
2853 while (is_part_of_name (*e
))
2857 if (!mips_parse_register_1 (s
, e
, &symval
))
2862 /* Eat characters from the end of the string that are valid
2863 channel suffixes. The preceding register must be $ACC or
2864 end with a digit, so there is no ambiguity. */
2867 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2868 if (m
> s
&& m
[-1] == *q
)
2875 || !mips_parse_register_1 (s
, m
, &symval
)
2876 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2881 *symval_ptr
= symval
;
2883 *channels_ptr
= channels
;
2887 /* Check if SPTR points at a valid register specifier according to TYPES.
2888 If so, then return 1, advance S to consume the specifier and store
2889 the register's number in REGNOP, otherwise return 0. */
2892 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2896 if (mips_parse_register (s
, ®no
, NULL
))
2898 if (types
& RTYPE_VEC
)
2899 regno
= mips_prefer_vec_regno (regno
);
2908 as_warn (_("unrecognized register name `%s'"), *s
);
2913 return regno
<= RNUM_MASK
;
2916 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2917 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2920 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2925 for (i
= 0; i
< 4; i
++)
2926 if (*s
== "xyzw"[i
])
2928 *channels
|= 1 << (3 - i
);
2934 /* Token types for parsed operand lists. */
2935 enum mips_operand_token_type
{
2936 /* A plain register, e.g. $f2. */
2939 /* A 4-bit XYZW channel mask. */
2942 /* A constant vector index, e.g. [1]. */
2945 /* A register vector index, e.g. [$2]. */
2948 /* A continuous range of registers, e.g. $s0-$s4. */
2951 /* A (possibly relocated) expression. */
2954 /* A floating-point value. */
2957 /* A single character. This can be '(', ')' or ',', but '(' only appears
2961 /* A doubled character, either "--" or "++". */
2964 /* The end of the operand list. */
2968 /* A parsed operand token. */
2969 struct mips_operand_token
2971 /* The type of token. */
2972 enum mips_operand_token_type type
;
2975 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2978 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2979 unsigned int channels
;
2981 /* The integer value of an OT_INTEGER_INDEX. */
2984 /* The two register symbol values involved in an OT_REG_RANGE. */
2986 unsigned int regno1
;
2987 unsigned int regno2
;
2990 /* The value of an OT_INTEGER. The value is represented as an
2991 expression and the relocation operators that were applied to
2992 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2993 relocation operators were used. */
2996 bfd_reloc_code_real_type relocs
[3];
2999 /* The binary data for an OT_FLOAT constant, and the number of bytes
3002 unsigned char data
[8];
3006 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3011 /* An obstack used to construct lists of mips_operand_tokens. */
3012 static struct obstack mips_operand_tokens
;
3014 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3017 mips_add_token (struct mips_operand_token
*token
,
3018 enum mips_operand_token_type type
)
3021 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3024 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3025 and OT_REG tokens for them if so, and return a pointer to the first
3026 unconsumed character. Return null otherwise. */
3029 mips_parse_base_start (char *s
)
3031 struct mips_operand_token token
;
3032 unsigned int regno
, channels
;
3033 bfd_boolean decrement_p
;
3039 SKIP_SPACE_TABS (s
);
3041 /* Only match "--" as part of a base expression. In other contexts "--X"
3042 is a double negative. */
3043 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3047 SKIP_SPACE_TABS (s
);
3050 /* Allow a channel specifier because that leads to better error messages
3051 than treating something like "$vf0x++" as an expression. */
3052 if (!mips_parse_register (&s
, ®no
, &channels
))
3056 mips_add_token (&token
, OT_CHAR
);
3061 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3064 token
.u
.regno
= regno
;
3065 mips_add_token (&token
, OT_REG
);
3069 token
.u
.channels
= channels
;
3070 mips_add_token (&token
, OT_CHANNELS
);
3073 /* For consistency, only match "++" as part of base expressions too. */
3074 SKIP_SPACE_TABS (s
);
3075 if (s
[0] == '+' && s
[1] == '+')
3079 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3085 /* Parse one or more tokens from S. Return a pointer to the first
3086 unconsumed character on success. Return null if an error was found
3087 and store the error text in insn_error. FLOAT_FORMAT is as for
3088 mips_parse_arguments. */
3091 mips_parse_argument_token (char *s
, char float_format
)
3093 char *end
, *save_in
;
3095 unsigned int regno1
, regno2
, channels
;
3096 struct mips_operand_token token
;
3098 /* First look for "($reg", since we want to treat that as an
3099 OT_CHAR and OT_REG rather than an expression. */
3100 end
= mips_parse_base_start (s
);
3104 /* Handle other characters that end up as OT_CHARs. */
3105 if (*s
== ')' || *s
== ',')
3108 mips_add_token (&token
, OT_CHAR
);
3113 /* Handle tokens that start with a register. */
3114 if (mips_parse_register (&s
, ®no1
, &channels
))
3118 /* A register and a VU0 channel suffix. */
3119 token
.u
.regno
= regno1
;
3120 mips_add_token (&token
, OT_REG
);
3122 token
.u
.channels
= channels
;
3123 mips_add_token (&token
, OT_CHANNELS
);
3127 SKIP_SPACE_TABS (s
);
3130 /* A register range. */
3132 SKIP_SPACE_TABS (s
);
3133 if (!mips_parse_register (&s
, ®no2
, NULL
))
3135 set_insn_error (0, _("invalid register range"));
3139 token
.u
.reg_range
.regno1
= regno1
;
3140 token
.u
.reg_range
.regno2
= regno2
;
3141 mips_add_token (&token
, OT_REG_RANGE
);
3145 /* Add the register itself. */
3146 token
.u
.regno
= regno1
;
3147 mips_add_token (&token
, OT_REG
);
3149 /* Check for a vector index. */
3153 SKIP_SPACE_TABS (s
);
3154 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3155 mips_add_token (&token
, OT_REG_INDEX
);
3158 expressionS element
;
3160 my_getExpression (&element
, s
);
3161 if (element
.X_op
!= O_constant
)
3163 set_insn_error (0, _("vector element must be constant"));
3167 token
.u
.index
= element
.X_add_number
;
3168 mips_add_token (&token
, OT_INTEGER_INDEX
);
3170 SKIP_SPACE_TABS (s
);
3173 set_insn_error (0, _("missing `]'"));
3183 /* First try to treat expressions as floats. */
3184 save_in
= input_line_pointer
;
3185 input_line_pointer
= s
;
3186 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3187 &token
.u
.flt
.length
);
3188 end
= input_line_pointer
;
3189 input_line_pointer
= save_in
;
3192 set_insn_error (0, err
);
3197 mips_add_token (&token
, OT_FLOAT
);
3202 /* Treat everything else as an integer expression. */
3203 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3204 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3205 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3206 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3208 mips_add_token (&token
, OT_INTEGER
);
3212 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3213 if expressions should be treated as 32-bit floating-point constants,
3214 'd' if they should be treated as 64-bit floating-point constants,
3215 or 0 if they should be treated as integer expressions (the usual case).
3217 Return a list of tokens on success, otherwise return 0. The caller
3218 must obstack_free the list after use. */
3220 static struct mips_operand_token
*
3221 mips_parse_arguments (char *s
, char float_format
)
3223 struct mips_operand_token token
;
3225 SKIP_SPACE_TABS (s
);
3228 s
= mips_parse_argument_token (s
, float_format
);
3231 obstack_free (&mips_operand_tokens
,
3232 obstack_finish (&mips_operand_tokens
));
3235 SKIP_SPACE_TABS (s
);
3237 mips_add_token (&token
, OT_END
);
3238 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3241 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3242 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3245 is_opcode_valid (const struct mips_opcode
*mo
)
3247 int isa
= mips_opts
.isa
;
3248 int ase
= mips_opts
.ase
;
3252 if (ISA_HAS_64BIT_REGS (isa
))
3253 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3254 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3255 ase
|= mips_ases
[i
].flags64
;
3257 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3260 /* Check whether the instruction or macro requires single-precision or
3261 double-precision floating-point support. Note that this information is
3262 stored differently in the opcode table for insns and macros. */
3263 if (mo
->pinfo
== INSN_MACRO
)
3265 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3266 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3270 fp_s
= mo
->pinfo
& FP_S
;
3271 fp_d
= mo
->pinfo
& FP_D
;
3274 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3277 if (fp_s
&& mips_opts
.soft_float
)
3283 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3284 selected ISA and architecture. */
3287 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3289 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3292 /* Return TRUE if the size of the microMIPS opcode MO matches one
3293 explicitly requested. Always TRUE in the standard MIPS mode.
3294 Use is_size_valid_16 for MIPS16 opcodes. */
3297 is_size_valid (const struct mips_opcode
*mo
)
3299 if (!mips_opts
.micromips
)
3302 if (mips_opts
.insn32
)
3304 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3306 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3309 if (!forced_insn_length
)
3311 if (mo
->pinfo
== INSN_MACRO
)
3313 return forced_insn_length
== micromips_insn_length (mo
);
3316 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3317 explicitly requested. */
3320 is_size_valid_16 (const struct mips_opcode
*mo
)
3322 if (!forced_insn_length
)
3324 if (mo
->pinfo
== INSN_MACRO
)
3326 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3328 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3333 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3334 of the preceding instruction. Always TRUE in the standard MIPS mode.
3336 We don't accept macros in 16-bit delay slots to avoid a case where
3337 a macro expansion fails because it relies on a preceding 32-bit real
3338 instruction to have matched and does not handle the operands correctly.
3339 The only macros that may expand to 16-bit instructions are JAL that
3340 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3341 and BGT (that likewise cannot be placed in a delay slot) that decay to
3342 a NOP. In all these cases the macros precede any corresponding real
3343 instruction definitions in the opcode table, so they will match in the
3344 second pass where the size of the delay slot is ignored and therefore
3345 produce correct code. */
3348 is_delay_slot_valid (const struct mips_opcode
*mo
)
3350 if (!mips_opts
.micromips
)
3353 if (mo
->pinfo
== INSN_MACRO
)
3354 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3355 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3356 && micromips_insn_length (mo
) != 4)
3358 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3359 && micromips_insn_length (mo
) != 2)
3365 /* For consistency checking, verify that all bits of OPCODE are specified
3366 either by the match/mask part of the instruction definition, or by the
3367 operand list. Also build up a list of operands in OPERANDS.
3369 INSN_BITS says which bits of the instruction are significant.
3370 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3371 provides the mips_operand description of each operand. DECODE_OPERAND
3372 is null for MIPS16 instructions. */
3375 validate_mips_insn (const struct mips_opcode
*opcode
,
3376 unsigned long insn_bits
,
3377 const struct mips_operand
*(*decode_operand
) (const char *),
3378 struct mips_operand_array
*operands
)
3381 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3382 const struct mips_operand
*operand
;
3384 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3385 if ((mask
& opcode
->match
) != opcode
->match
)
3387 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3388 opcode
->name
, opcode
->args
);
3393 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3394 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3395 for (s
= opcode
->args
; *s
; ++s
)
3408 if (!decode_operand
)
3409 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3411 operand
= decode_operand (s
);
3412 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3414 as_bad (_("internal: unknown operand type: %s %s"),
3415 opcode
->name
, opcode
->args
);
3418 gas_assert (opno
< MAX_OPERANDS
);
3419 operands
->operand
[opno
] = operand
;
3420 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3422 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3423 if (operand
->type
== OP_MDMX_IMM_REG
)
3424 /* Bit 5 is the format selector (OB vs QH). The opcode table
3425 has separate entries for each format. */
3426 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3427 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3428 used_bits
&= ~(mask
& 0x700);
3430 /* Skip prefix characters. */
3431 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3436 doubled
= used_bits
& mask
& insn_bits
;
3439 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3440 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3444 undefined
= ~used_bits
& insn_bits
;
3445 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3447 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3448 undefined
, opcode
->name
, opcode
->args
);
3451 used_bits
&= ~insn_bits
;
3454 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3455 used_bits
, opcode
->name
, opcode
->args
);
3461 /* The MIPS16 version of validate_mips_insn. */
3464 validate_mips16_insn (const struct mips_opcode
*opcode
,
3465 struct mips_operand_array
*operands
)
3467 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3469 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3472 /* The microMIPS version of validate_mips_insn. */
3475 validate_micromips_insn (const struct mips_opcode
*opc
,
3476 struct mips_operand_array
*operands
)
3478 unsigned long insn_bits
;
3479 unsigned long major
;
3480 unsigned int length
;
3482 if (opc
->pinfo
== INSN_MACRO
)
3483 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3486 length
= micromips_insn_length (opc
);
3487 if (length
!= 2 && length
!= 4)
3489 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3490 "%s %s"), length
, opc
->name
, opc
->args
);
3493 major
= opc
->match
>> (10 + 8 * (length
- 2));
3494 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3495 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3497 as_bad (_("internal error: bad microMIPS opcode "
3498 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3502 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3503 insn_bits
= 1 << 4 * length
;
3504 insn_bits
<<= 4 * length
;
3506 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3510 /* This function is called once, at assembler startup time. It should set up
3511 all the tables, etc. that the MD part of the assembler will need. */
3516 const char *retval
= NULL
;
3520 if (mips_pic
!= NO_PIC
)
3522 if (g_switch_seen
&& g_switch_value
!= 0)
3523 as_bad (_("-G may not be used in position-independent code"));
3526 else if (mips_abicalls
)
3528 if (g_switch_seen
&& g_switch_value
!= 0)
3529 as_bad (_("-G may not be used with abicalls"));
3533 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3534 as_warn (_("could not set architecture and machine"));
3536 op_hash
= hash_new ();
3538 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3539 for (i
= 0; i
< NUMOPCODES
;)
3541 const char *name
= mips_opcodes
[i
].name
;
3543 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3546 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3547 mips_opcodes
[i
].name
, retval
);
3548 /* Probably a memory allocation problem? Give up now. */
3549 as_fatal (_("broken assembler, no assembly attempted"));
3553 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3554 decode_mips_operand
, &mips_operands
[i
]))
3556 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3558 create_insn (&nop_insn
, mips_opcodes
+ i
);
3559 if (mips_fix_loongson2f_nop
)
3560 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3561 nop_insn
.fixed_p
= 1;
3565 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3568 mips16_op_hash
= hash_new ();
3569 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3570 bfd_mips16_num_opcodes
);
3573 while (i
< bfd_mips16_num_opcodes
)
3575 const char *name
= mips16_opcodes
[i
].name
;
3577 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3579 as_fatal (_("internal: can't hash `%s': %s"),
3580 mips16_opcodes
[i
].name
, retval
);
3583 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3585 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3587 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3588 mips16_nop_insn
.fixed_p
= 1;
3592 while (i
< bfd_mips16_num_opcodes
3593 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3596 micromips_op_hash
= hash_new ();
3597 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3598 bfd_micromips_num_opcodes
);
3601 while (i
< bfd_micromips_num_opcodes
)
3603 const char *name
= micromips_opcodes
[i
].name
;
3605 retval
= hash_insert (micromips_op_hash
, name
,
3606 (void *) µmips_opcodes
[i
]);
3608 as_fatal (_("internal: can't hash `%s': %s"),
3609 micromips_opcodes
[i
].name
, retval
);
3612 struct mips_cl_insn
*micromips_nop_insn
;
3614 if (!validate_micromips_insn (µmips_opcodes
[i
],
3615 µmips_operands
[i
]))
3618 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3620 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3621 micromips_nop_insn
= µmips_nop16_insn
;
3622 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3623 micromips_nop_insn
= µmips_nop32_insn
;
3627 if (micromips_nop_insn
->insn_mo
== NULL
3628 && strcmp (name
, "nop") == 0)
3630 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3631 micromips_nop_insn
->fixed_p
= 1;
3635 while (++i
< bfd_micromips_num_opcodes
3636 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3640 as_fatal (_("broken assembler, no assembly attempted"));
3642 /* We add all the general register names to the symbol table. This
3643 helps us detect invalid uses of them. */
3644 for (i
= 0; reg_names
[i
].name
; i
++)
3645 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3646 reg_names
[i
].num
, /* & RNUM_MASK, */
3647 &zero_address_frag
));
3649 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3650 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3651 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3652 &zero_address_frag
));
3654 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3655 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3656 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3657 &zero_address_frag
));
3659 for (i
= 0; i
< 32; i
++)
3663 /* R5900 VU0 floating-point register. */
3664 sprintf (regname
, "$vf%d", i
);
3665 symbol_table_insert (symbol_new (regname
, reg_section
,
3666 RTYPE_VF
| i
, &zero_address_frag
));
3668 /* R5900 VU0 integer register. */
3669 sprintf (regname
, "$vi%d", i
);
3670 symbol_table_insert (symbol_new (regname
, reg_section
,
3671 RTYPE_VI
| i
, &zero_address_frag
));
3674 sprintf (regname
, "$w%d", i
);
3675 symbol_table_insert (symbol_new (regname
, reg_section
,
3676 RTYPE_MSA
| i
, &zero_address_frag
));
3679 obstack_init (&mips_operand_tokens
);
3681 mips_no_prev_insn ();
3684 mips_cprmask
[0] = 0;
3685 mips_cprmask
[1] = 0;
3686 mips_cprmask
[2] = 0;
3687 mips_cprmask
[3] = 0;
3689 /* set the default alignment for the text section (2**2) */
3690 record_alignment (text_section
, 2);
3692 bfd_set_gp_size (stdoutput
, g_switch_value
);
3694 /* On a native system other than VxWorks, sections must be aligned
3695 to 16 byte boundaries. When configured for an embedded ELF
3696 target, we don't bother. */
3697 if (strncmp (TARGET_OS
, "elf", 3) != 0
3698 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3700 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3701 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3702 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3705 /* Create a .reginfo section for register masks and a .mdebug
3706 section for debugging information. */
3714 subseg
= now_subseg
;
3716 /* The ABI says this section should be loaded so that the
3717 running program can access it. However, we don't load it
3718 if we are configured for an embedded target */
3719 flags
= SEC_READONLY
| SEC_DATA
;
3720 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3721 flags
|= SEC_ALLOC
| SEC_LOAD
;
3723 if (mips_abi
!= N64_ABI
)
3725 sec
= subseg_new (".reginfo", (subsegT
) 0);
3727 bfd_set_section_flags (stdoutput
, sec
, flags
);
3728 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3730 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3734 /* The 64-bit ABI uses a .MIPS.options section rather than
3735 .reginfo section. */
3736 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3737 bfd_set_section_flags (stdoutput
, sec
, flags
);
3738 bfd_set_section_alignment (stdoutput
, sec
, 3);
3740 /* Set up the option header. */
3742 Elf_Internal_Options opthdr
;
3745 opthdr
.kind
= ODK_REGINFO
;
3746 opthdr
.size
= (sizeof (Elf_External_Options
)
3747 + sizeof (Elf64_External_RegInfo
));
3750 f
= frag_more (sizeof (Elf_External_Options
));
3751 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3752 (Elf_External_Options
*) f
);
3754 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3758 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3759 bfd_set_section_flags (stdoutput
, sec
,
3760 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3761 bfd_set_section_alignment (stdoutput
, sec
, 3);
3762 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3764 if (ECOFF_DEBUGGING
)
3766 sec
= subseg_new (".mdebug", (subsegT
) 0);
3767 (void) bfd_set_section_flags (stdoutput
, sec
,
3768 SEC_HAS_CONTENTS
| SEC_READONLY
);
3769 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3771 else if (mips_flag_pdr
)
3773 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3774 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3775 SEC_READONLY
| SEC_RELOC
3777 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3780 subseg_set (seg
, subseg
);
3783 if (mips_fix_vr4120
)
3784 init_vr4120_conflicts ();
3788 fpabi_incompatible_with (int fpabi
, const char *what
)
3790 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3791 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3795 fpabi_requires (int fpabi
, const char *what
)
3797 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3798 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3801 /* Check -mabi and register sizes against the specified FP ABI. */
3803 check_fpabi (int fpabi
)
3807 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3808 if (file_mips_opts
.soft_float
)
3809 fpabi_incompatible_with (fpabi
, "softfloat");
3810 else if (file_mips_opts
.single_float
)
3811 fpabi_incompatible_with (fpabi
, "singlefloat");
3812 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3813 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3814 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3815 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3818 case Val_GNU_MIPS_ABI_FP_XX
:
3819 if (mips_abi
!= O32_ABI
)
3820 fpabi_requires (fpabi
, "-mabi=32");
3821 else if (file_mips_opts
.soft_float
)
3822 fpabi_incompatible_with (fpabi
, "softfloat");
3823 else if (file_mips_opts
.single_float
)
3824 fpabi_incompatible_with (fpabi
, "singlefloat");
3825 else if (file_mips_opts
.fp
!= 0)
3826 fpabi_requires (fpabi
, "fp=xx");
3829 case Val_GNU_MIPS_ABI_FP_64A
:
3830 case Val_GNU_MIPS_ABI_FP_64
:
3831 if (mips_abi
!= O32_ABI
)
3832 fpabi_requires (fpabi
, "-mabi=32");
3833 else if (file_mips_opts
.soft_float
)
3834 fpabi_incompatible_with (fpabi
, "softfloat");
3835 else if (file_mips_opts
.single_float
)
3836 fpabi_incompatible_with (fpabi
, "singlefloat");
3837 else if (file_mips_opts
.fp
!= 64)
3838 fpabi_requires (fpabi
, "fp=64");
3839 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3840 fpabi_incompatible_with (fpabi
, "nooddspreg");
3841 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3842 fpabi_requires (fpabi
, "nooddspreg");
3845 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3846 if (file_mips_opts
.soft_float
)
3847 fpabi_incompatible_with (fpabi
, "softfloat");
3848 else if (!file_mips_opts
.single_float
)
3849 fpabi_requires (fpabi
, "singlefloat");
3852 case Val_GNU_MIPS_ABI_FP_SOFT
:
3853 if (!file_mips_opts
.soft_float
)
3854 fpabi_requires (fpabi
, "softfloat");
3857 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3858 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3859 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3862 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3863 /* Silently ignore compatibility value. */
3867 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3868 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3873 /* Perform consistency checks on the current options. */
3876 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3878 /* Check the size of integer registers agrees with the ABI and ISA. */
3879 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3880 as_bad (_("`gp=64' used with a 32-bit processor"));
3882 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3883 as_bad (_("`gp=32' used with a 64-bit ABI"));
3885 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3886 as_bad (_("`gp=64' used with a 32-bit ABI"));
3888 /* Check the size of the float registers agrees with the ABI and ISA. */
3892 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3893 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3894 else if (opts
->single_float
== 1)
3895 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3898 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3899 as_bad (_("`fp=64' used with a 32-bit fpu"));
3901 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3902 && !ISA_HAS_MXHC1 (opts
->isa
))
3903 as_warn (_("`fp=64' used with a 32-bit ABI"));
3907 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3908 as_warn (_("`fp=32' used with a 64-bit ABI"));
3909 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3910 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3913 as_bad (_("Unknown size of floating point registers"));
3917 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3918 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3920 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3921 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3922 else if (ISA_IS_R6 (opts
->isa
)
3923 && (opts
->micromips
== 1
3924 || opts
->mips16
== 1))
3925 as_fatal (_("`%s' cannot be used with `%s'"),
3926 opts
->micromips
? "micromips" : "mips16",
3927 mips_cpu_info_from_isa (opts
->isa
)->name
);
3929 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3930 as_fatal (_("branch relaxation is not supported in `%s'"),
3931 mips_cpu_info_from_isa (opts
->isa
)->name
);
3934 /* Perform consistency checks on the module level options exactly once.
3935 This is a deferred check that happens:
3936 at the first .set directive
3937 or, at the first pseudo op that generates code (inc .dc.a)
3938 or, at the first instruction
3942 file_mips_check_options (void)
3944 const struct mips_cpu_info
*arch_info
= 0;
3946 if (file_mips_opts_checked
)
3949 /* The following code determines the register size.
3950 Similar code was added to GCC 3.3 (see override_options() in
3951 config/mips/mips.c). The GAS and GCC code should be kept in sync
3952 as much as possible. */
3954 if (file_mips_opts
.gp
< 0)
3956 /* Infer the integer register size from the ABI and processor.
3957 Restrict ourselves to 32-bit registers if that's all the
3958 processor has, or if the ABI cannot handle 64-bit registers. */
3959 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3960 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3964 if (file_mips_opts
.fp
< 0)
3966 /* No user specified float register size.
3967 ??? GAS treats single-float processors as though they had 64-bit
3968 float registers (although it complains when double-precision
3969 instructions are used). As things stand, saying they have 32-bit
3970 registers would lead to spurious "register must be even" messages.
3971 So here we assume float registers are never smaller than the
3973 if (file_mips_opts
.gp
== 64)
3974 /* 64-bit integer registers implies 64-bit float registers. */
3975 file_mips_opts
.fp
= 64;
3976 else if ((file_mips_opts
.ase
& FP64_ASES
)
3977 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3978 /* Handle ASEs that require 64-bit float registers, if possible. */
3979 file_mips_opts
.fp
= 64;
3980 else if (ISA_IS_R6 (mips_opts
.isa
))
3981 /* R6 implies 64-bit float registers. */
3982 file_mips_opts
.fp
= 64;
3984 /* 32-bit float registers. */
3985 file_mips_opts
.fp
= 32;
3988 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3990 /* Disable operations on odd-numbered floating-point registers by default
3991 when using the FPXX ABI. */
3992 if (file_mips_opts
.oddspreg
< 0)
3994 if (file_mips_opts
.fp
== 0)
3995 file_mips_opts
.oddspreg
= 0;
3997 file_mips_opts
.oddspreg
= 1;
4000 /* End of GCC-shared inference code. */
4002 /* This flag is set when we have a 64-bit capable CPU but use only
4003 32-bit wide registers. Note that EABI does not use it. */
4004 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4005 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4006 || mips_abi
== O32_ABI
))
4009 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4010 as_bad (_("trap exception not supported at ISA 1"));
4012 /* If the selected architecture includes support for ASEs, enable
4013 generation of code for them. */
4014 if (file_mips_opts
.mips16
== -1)
4015 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4016 if (file_mips_opts
.micromips
== -1)
4017 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4020 if (mips_nan2008
== -1)
4021 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4022 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4023 as_fatal (_("`%s' does not support legacy NaN"),
4024 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4026 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4027 being selected implicitly. */
4028 if (file_mips_opts
.fp
!= 64)
4029 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4031 /* If the user didn't explicitly select or deselect a particular ASE,
4032 use the default setting for the CPU. */
4033 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4035 /* Set up the current options. These may change throughout assembly. */
4036 mips_opts
= file_mips_opts
;
4038 mips_check_isa_supports_ases ();
4039 mips_check_options (&file_mips_opts
, TRUE
);
4040 file_mips_opts_checked
= TRUE
;
4042 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4043 as_warn (_("could not set architecture and machine"));
4047 md_assemble (char *str
)
4049 struct mips_cl_insn insn
;
4050 bfd_reloc_code_real_type unused_reloc
[3]
4051 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4053 file_mips_check_options ();
4055 imm_expr
.X_op
= O_absent
;
4056 offset_expr
.X_op
= O_absent
;
4057 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4058 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4059 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4061 mips_mark_labels ();
4062 mips_assembling_insn
= TRUE
;
4063 clear_insn_error ();
4065 if (mips_opts
.mips16
)
4066 mips16_ip (str
, &insn
);
4069 mips_ip (str
, &insn
);
4070 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4071 str
, insn
.insn_opcode
));
4075 report_insn_error (str
);
4076 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4079 if (mips_opts
.mips16
)
4080 mips16_macro (&insn
);
4087 if (offset_expr
.X_op
!= O_absent
)
4088 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4090 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4093 mips_assembling_insn
= FALSE
;
4096 /* Convenience functions for abstracting away the differences between
4097 MIPS16 and non-MIPS16 relocations. */
4099 static inline bfd_boolean
4100 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4104 case BFD_RELOC_MIPS16_JMP
:
4105 case BFD_RELOC_MIPS16_GPREL
:
4106 case BFD_RELOC_MIPS16_GOT16
:
4107 case BFD_RELOC_MIPS16_CALL16
:
4108 case BFD_RELOC_MIPS16_HI16_S
:
4109 case BFD_RELOC_MIPS16_HI16
:
4110 case BFD_RELOC_MIPS16_LO16
:
4111 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4119 static inline bfd_boolean
4120 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4124 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4125 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4126 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4127 case BFD_RELOC_MICROMIPS_GPREL16
:
4128 case BFD_RELOC_MICROMIPS_JMP
:
4129 case BFD_RELOC_MICROMIPS_HI16
:
4130 case BFD_RELOC_MICROMIPS_HI16_S
:
4131 case BFD_RELOC_MICROMIPS_LO16
:
4132 case BFD_RELOC_MICROMIPS_LITERAL
:
4133 case BFD_RELOC_MICROMIPS_GOT16
:
4134 case BFD_RELOC_MICROMIPS_CALL16
:
4135 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4136 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4137 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4138 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4139 case BFD_RELOC_MICROMIPS_SUB
:
4140 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4141 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4142 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4143 case BFD_RELOC_MICROMIPS_HIGHEST
:
4144 case BFD_RELOC_MICROMIPS_HIGHER
:
4145 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4146 case BFD_RELOC_MICROMIPS_JALR
:
4154 static inline bfd_boolean
4155 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4157 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4160 static inline bfd_boolean
4161 b_reloc_p (bfd_reloc_code_real_type reloc
)
4163 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4164 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4165 || reloc
== BFD_RELOC_16_PCREL_S2
4166 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4167 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4168 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4169 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4172 static inline bfd_boolean
4173 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4175 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4176 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4179 static inline bfd_boolean
4180 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4182 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4183 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4186 static inline bfd_boolean
4187 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4189 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4190 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4193 static inline bfd_boolean
4194 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4196 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4199 static inline bfd_boolean
4200 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4202 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4203 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4206 /* Return true if RELOC is a PC-relative relocation that does not have
4207 full address range. */
4209 static inline bfd_boolean
4210 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4214 case BFD_RELOC_16_PCREL_S2
:
4215 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4216 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4217 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4218 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4219 case BFD_RELOC_MIPS_21_PCREL_S2
:
4220 case BFD_RELOC_MIPS_26_PCREL_S2
:
4221 case BFD_RELOC_MIPS_18_PCREL_S3
:
4222 case BFD_RELOC_MIPS_19_PCREL_S2
:
4225 case BFD_RELOC_32_PCREL
:
4226 case BFD_RELOC_HI16_S_PCREL
:
4227 case BFD_RELOC_LO16_PCREL
:
4228 return HAVE_64BIT_ADDRESSES
;
4235 /* Return true if the given relocation might need a matching %lo().
4236 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4237 need a matching %lo() when applied to local symbols. */
4239 static inline bfd_boolean
4240 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4242 return (HAVE_IN_PLACE_ADDENDS
4243 && (hi16_reloc_p (reloc
)
4244 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4245 all GOT16 relocations evaluate to "G". */
4246 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4249 /* Return the type of %lo() reloc needed by RELOC, given that
4250 reloc_needs_lo_p. */
4252 static inline bfd_reloc_code_real_type
4253 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4255 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4256 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4260 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4263 static inline bfd_boolean
4264 fixup_has_matching_lo_p (fixS
*fixp
)
4266 return (fixp
->fx_next
!= NULL
4267 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4268 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4269 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4272 /* Move all labels in LABELS to the current insertion point. TEXT_P
4273 says whether the labels refer to text or data. */
4276 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4278 struct insn_label_list
*l
;
4281 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4283 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4284 symbol_set_frag (l
->label
, frag_now
);
4285 val
= (valueT
) frag_now_fix ();
4286 /* MIPS16/microMIPS text labels are stored as odd. */
4287 if (text_p
&& HAVE_CODE_COMPRESSION
)
4289 S_SET_VALUE (l
->label
, val
);
4293 /* Move all labels in insn_labels to the current insertion point
4294 and treat them as text labels. */
4297 mips_move_text_labels (void)
4299 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4302 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4305 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4307 bfd_boolean linkonce
= FALSE
;
4308 segT symseg
= S_GET_SEGMENT (sym
);
4310 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4312 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4314 /* The GNU toolchain uses an extension for ELF: a section
4315 beginning with the magic string .gnu.linkonce is a
4316 linkonce section. */
4317 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4318 sizeof ".gnu.linkonce" - 1) == 0)
4324 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4325 linker to handle them specially, such as generating jalx instructions
4326 when needed. We also make them odd for the duration of the assembly,
4327 in order to generate the right sort of code. We will make them even
4328 in the adjust_symtab routine, while leaving them marked. This is
4329 convenient for the debugger and the disassembler. The linker knows
4330 to make them odd again. */
4333 mips_compressed_mark_label (symbolS
*label
)
4335 gas_assert (HAVE_CODE_COMPRESSION
);
4337 if (mips_opts
.mips16
)
4338 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4340 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4341 if ((S_GET_VALUE (label
) & 1) == 0
4342 /* Don't adjust the address if the label is global or weak, or
4343 in a link-once section, since we'll be emitting symbol reloc
4344 references to it which will be patched up by the linker, and
4345 the final value of the symbol may or may not be MIPS16/microMIPS. */
4346 && !S_IS_WEAK (label
)
4347 && !S_IS_EXTERNAL (label
)
4348 && !s_is_linkonce (label
, now_seg
))
4349 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4352 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4355 mips_compressed_mark_labels (void)
4357 struct insn_label_list
*l
;
4359 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4360 mips_compressed_mark_label (l
->label
);
4363 /* End the current frag. Make it a variant frag and record the
4367 relax_close_frag (void)
4369 mips_macro_warning
.first_frag
= frag_now
;
4370 frag_var (rs_machine_dependent
, 0, 0,
4371 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4372 mips_pic
!= NO_PIC
),
4373 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4375 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4376 mips_relax
.first_fixup
= 0;
4379 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4380 See the comment above RELAX_ENCODE for more details. */
4383 relax_start (symbolS
*symbol
)
4385 gas_assert (mips_relax
.sequence
== 0);
4386 mips_relax
.sequence
= 1;
4387 mips_relax
.symbol
= symbol
;
4390 /* Start generating the second version of a relaxable sequence.
4391 See the comment above RELAX_ENCODE for more details. */
4396 gas_assert (mips_relax
.sequence
== 1);
4397 mips_relax
.sequence
= 2;
4400 /* End the current relaxable sequence. */
4405 gas_assert (mips_relax
.sequence
== 2);
4406 relax_close_frag ();
4407 mips_relax
.sequence
= 0;
4410 /* Return true if IP is a delayed branch or jump. */
4412 static inline bfd_boolean
4413 delayed_branch_p (const struct mips_cl_insn
*ip
)
4415 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4416 | INSN_COND_BRANCH_DELAY
4417 | INSN_COND_BRANCH_LIKELY
)) != 0;
4420 /* Return true if IP is a compact branch or jump. */
4422 static inline bfd_boolean
4423 compact_branch_p (const struct mips_cl_insn
*ip
)
4425 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4426 | INSN2_COND_BRANCH
)) != 0;
4429 /* Return true if IP is an unconditional branch or jump. */
4431 static inline bfd_boolean
4432 uncond_branch_p (const struct mips_cl_insn
*ip
)
4434 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4435 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4438 /* Return true if IP is a branch-likely instruction. */
4440 static inline bfd_boolean
4441 branch_likely_p (const struct mips_cl_insn
*ip
)
4443 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4446 /* Return the type of nop that should be used to fill the delay slot
4447 of delayed branch IP. */
4449 static struct mips_cl_insn
*
4450 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4452 if (mips_opts
.micromips
4453 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4454 return µmips_nop32_insn
;
4458 /* Return a mask that has bit N set if OPCODE reads the register(s)
4462 insn_read_mask (const struct mips_opcode
*opcode
)
4464 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4467 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4471 insn_write_mask (const struct mips_opcode
*opcode
)
4473 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4476 /* Return a mask of the registers specified by operand OPERAND of INSN.
4477 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4481 operand_reg_mask (const struct mips_cl_insn
*insn
,
4482 const struct mips_operand
*operand
,
4483 unsigned int type_mask
)
4485 unsigned int uval
, vsel
;
4487 switch (operand
->type
)
4494 case OP_ADDIUSP_INT
:
4495 case OP_ENTRY_EXIT_LIST
:
4496 case OP_REPEAT_DEST_REG
:
4497 case OP_REPEAT_PREV_REG
:
4500 case OP_VU0_MATCH_SUFFIX
:
4505 case OP_OPTIONAL_REG
:
4507 const struct mips_reg_operand
*reg_op
;
4509 reg_op
= (const struct mips_reg_operand
*) operand
;
4510 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4512 uval
= insn_extract_operand (insn
, operand
);
4513 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4518 const struct mips_reg_pair_operand
*pair_op
;
4520 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4521 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4523 uval
= insn_extract_operand (insn
, operand
);
4524 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4527 case OP_CLO_CLZ_DEST
:
4528 if (!(type_mask
& (1 << OP_REG_GP
)))
4530 uval
= insn_extract_operand (insn
, operand
);
4531 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4534 if (!(type_mask
& (1 << OP_REG_GP
)))
4536 uval
= insn_extract_operand (insn
, operand
);
4537 gas_assert ((uval
& 31) == (uval
>> 5));
4538 return 1 << (uval
& 31);
4541 case OP_NON_ZERO_REG
:
4542 if (!(type_mask
& (1 << OP_REG_GP
)))
4544 uval
= insn_extract_operand (insn
, operand
);
4545 return 1 << (uval
& 31);
4547 case OP_LWM_SWM_LIST
:
4550 case OP_SAVE_RESTORE_LIST
:
4553 case OP_MDMX_IMM_REG
:
4554 if (!(type_mask
& (1 << OP_REG_VEC
)))
4556 uval
= insn_extract_operand (insn
, operand
);
4558 if ((vsel
& 0x18) == 0x18)
4560 return 1 << (uval
& 31);
4563 if (!(type_mask
& (1 << OP_REG_GP
)))
4565 return 1 << insn_extract_operand (insn
, operand
);
4570 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4571 where bit N of OPNO_MASK is set if operand N should be included.
4572 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4576 insn_reg_mask (const struct mips_cl_insn
*insn
,
4577 unsigned int type_mask
, unsigned int opno_mask
)
4579 unsigned int opno
, reg_mask
;
4583 while (opno_mask
!= 0)
4586 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4593 /* Return the mask of core registers that IP reads. */
4596 gpr_read_mask (const struct mips_cl_insn
*ip
)
4598 unsigned long pinfo
, pinfo2
;
4601 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4602 pinfo
= ip
->insn_mo
->pinfo
;
4603 pinfo2
= ip
->insn_mo
->pinfo2
;
4604 if (pinfo
& INSN_UDI
)
4606 /* UDI instructions have traditionally been assumed to read RS
4608 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4609 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4611 if (pinfo
& INSN_READ_GPR_24
)
4613 if (pinfo2
& INSN2_READ_GPR_16
)
4615 if (pinfo2
& INSN2_READ_SP
)
4617 if (pinfo2
& INSN2_READ_GPR_31
)
4619 /* Don't include register 0. */
4623 /* Return the mask of core registers that IP writes. */
4626 gpr_write_mask (const struct mips_cl_insn
*ip
)
4628 unsigned long pinfo
, pinfo2
;
4631 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4632 pinfo
= ip
->insn_mo
->pinfo
;
4633 pinfo2
= ip
->insn_mo
->pinfo2
;
4634 if (pinfo
& INSN_WRITE_GPR_24
)
4636 if (pinfo
& INSN_WRITE_GPR_31
)
4638 if (pinfo
& INSN_UDI
)
4639 /* UDI instructions have traditionally been assumed to write to RD. */
4640 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4641 if (pinfo2
& INSN2_WRITE_SP
)
4643 /* Don't include register 0. */
4647 /* Return the mask of floating-point registers that IP reads. */
4650 fpr_read_mask (const struct mips_cl_insn
*ip
)
4652 unsigned long pinfo
;
4655 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4656 | (1 << OP_REG_MSA
)),
4657 insn_read_mask (ip
->insn_mo
));
4658 pinfo
= ip
->insn_mo
->pinfo
;
4659 /* Conservatively treat all operands to an FP_D instruction are doubles.
4660 (This is overly pessimistic for things like cvt.d.s.) */
4661 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4666 /* Return the mask of floating-point registers that IP writes. */
4669 fpr_write_mask (const struct mips_cl_insn
*ip
)
4671 unsigned long pinfo
;
4674 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4675 | (1 << OP_REG_MSA
)),
4676 insn_write_mask (ip
->insn_mo
));
4677 pinfo
= ip
->insn_mo
->pinfo
;
4678 /* Conservatively treat all operands to an FP_D instruction are doubles.
4679 (This is overly pessimistic for things like cvt.s.d.) */
4680 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4685 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4686 Check whether that is allowed. */
4689 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4691 const char *s
= insn
->name
;
4692 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4694 && mips_opts
.oddspreg
;
4696 if (insn
->pinfo
== INSN_MACRO
)
4697 /* Let a macro pass, we'll catch it later when it is expanded. */
4700 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4701 otherwise it depends on oddspreg. */
4702 if ((insn
->pinfo
& FP_S
)
4703 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4704 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4705 return FPR_SIZE
== 32 || oddspreg
;
4707 /* Allow odd registers for single-precision ops and double-precision if the
4708 floating-point registers are 64-bit wide. */
4709 switch (insn
->pinfo
& (FP_S
| FP_D
))
4715 return FPR_SIZE
== 64;
4720 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4721 s
= strchr (insn
->name
, '.');
4722 if (s
!= NULL
&& opnum
== 2)
4723 s
= strchr (s
+ 1, '.');
4724 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4727 return FPR_SIZE
== 64;
4730 /* Information about an instruction argument that we're trying to match. */
4731 struct mips_arg_info
4733 /* The instruction so far. */
4734 struct mips_cl_insn
*insn
;
4736 /* The first unconsumed operand token. */
4737 struct mips_operand_token
*token
;
4739 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4742 /* The 1-based argument number, for error reporting. This does not
4743 count elided optional registers, etc.. */
4746 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4747 unsigned int last_regno
;
4749 /* If the first operand was an OP_REG, this is the register that it
4750 specified, otherwise it is ILLEGAL_REG. */
4751 unsigned int dest_regno
;
4753 /* The value of the last OP_INT operand. Only used for OP_MSB,
4754 where it gives the lsb position. */
4755 unsigned int last_op_int
;
4757 /* If true, match routines should assume that no later instruction
4758 alternative matches and should therefore be as accommodating as
4759 possible. Match routines should not report errors if something
4760 is only invalid for !LAX_MATCH. */
4761 bfd_boolean lax_match
;
4763 /* True if a reference to the current AT register was seen. */
4764 bfd_boolean seen_at
;
4767 /* Record that the argument is out of range. */
4770 match_out_of_range (struct mips_arg_info
*arg
)
4772 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4775 /* Record that the argument isn't constant but needs to be. */
4778 match_not_constant (struct mips_arg_info
*arg
)
4780 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4784 /* Try to match an OT_CHAR token for character CH. Consume the token
4785 and return true on success, otherwise return false. */
4788 match_char (struct mips_arg_info
*arg
, char ch
)
4790 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4800 /* Try to get an expression from the next tokens in ARG. Consume the
4801 tokens and return true on success, storing the expression value in
4802 VALUE and relocation types in R. */
4805 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4806 bfd_reloc_code_real_type
*r
)
4808 /* If the next token is a '(' that was parsed as being part of a base
4809 expression, assume we have an elided offset. The later match will fail
4810 if this turns out to be wrong. */
4811 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4813 value
->X_op
= O_constant
;
4814 value
->X_add_number
= 0;
4815 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4819 /* Reject register-based expressions such as "0+$2" and "(($2))".
4820 For plain registers the default error seems more appropriate. */
4821 if (arg
->token
->type
== OT_INTEGER
4822 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4824 set_insn_error (arg
->argnum
, _("register value used as expression"));
4828 if (arg
->token
->type
== OT_INTEGER
)
4830 *value
= arg
->token
->u
.integer
.value
;
4831 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4837 (arg
->argnum
, _("operand %d must be an immediate expression"),
4842 /* Try to get a constant expression from the next tokens in ARG. Consume
4843 the tokens and return return true on success, storing the constant value
4847 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4850 bfd_reloc_code_real_type r
[3];
4852 if (!match_expression (arg
, &ex
, r
))
4855 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4856 *value
= ex
.X_add_number
;
4859 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4860 match_out_of_range (arg
);
4862 match_not_constant (arg
);
4868 /* Return the RTYPE_* flags for a register operand of type TYPE that
4869 appears in instruction OPCODE. */
4872 convert_reg_type (const struct mips_opcode
*opcode
,
4873 enum mips_reg_operand_type type
)
4878 return RTYPE_NUM
| RTYPE_GP
;
4881 /* Allow vector register names for MDMX if the instruction is a 64-bit
4882 FPR load, store or move (including moves to and from GPRs). */
4883 if ((mips_opts
.ase
& ASE_MDMX
)
4884 && (opcode
->pinfo
& FP_D
)
4885 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4886 | INSN_COPROC_MEMORY_DELAY
4889 | INSN_STORE_MEMORY
)))
4890 return RTYPE_FPU
| RTYPE_VEC
;
4894 if (opcode
->pinfo
& (FP_D
| FP_S
))
4895 return RTYPE_CCC
| RTYPE_FCC
;
4899 if (opcode
->membership
& INSN_5400
)
4901 return RTYPE_FPU
| RTYPE_VEC
;
4907 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4908 return RTYPE_NUM
| RTYPE_CP0
;
4915 return RTYPE_NUM
| RTYPE_VI
;
4918 return RTYPE_NUM
| RTYPE_VF
;
4920 case OP_REG_R5900_I
:
4921 return RTYPE_R5900_I
;
4923 case OP_REG_R5900_Q
:
4924 return RTYPE_R5900_Q
;
4926 case OP_REG_R5900_R
:
4927 return RTYPE_R5900_R
;
4929 case OP_REG_R5900_ACC
:
4930 return RTYPE_R5900_ACC
;
4935 case OP_REG_MSA_CTRL
:
4941 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4944 check_regno (struct mips_arg_info
*arg
,
4945 enum mips_reg_operand_type type
, unsigned int regno
)
4947 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4948 arg
->seen_at
= TRUE
;
4950 if (type
== OP_REG_FP
4952 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4954 /* This was a warning prior to introducing O32 FPXX and FP64 support
4955 so maintain a warning for FP32 but raise an error for the new
4958 as_warn (_("float register should be even, was %d"), regno
);
4960 as_bad (_("float register should be even, was %d"), regno
);
4963 if (type
== OP_REG_CCC
)
4968 name
= arg
->insn
->insn_mo
->name
;
4969 length
= strlen (name
);
4970 if ((regno
& 1) != 0
4971 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4972 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4973 as_warn (_("condition code register should be even for %s, was %d"),
4976 if ((regno
& 3) != 0
4977 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4978 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4983 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4984 a register of type TYPE. Return true on success, storing the register
4985 number in *REGNO and warning about any dubious uses. */
4988 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4989 unsigned int symval
, unsigned int *regno
)
4991 if (type
== OP_REG_VEC
)
4992 symval
= mips_prefer_vec_regno (symval
);
4993 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4996 *regno
= symval
& RNUM_MASK
;
4997 check_regno (arg
, type
, *regno
);
5001 /* Try to interpret the next token in ARG as a register of type TYPE.
5002 Consume the token and return true on success, storing the register
5003 number in *REGNO. Return false on failure. */
5006 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5007 unsigned int *regno
)
5009 if (arg
->token
->type
== OT_REG
5010 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5018 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5019 Consume the token and return true on success, storing the register numbers
5020 in *REGNO1 and *REGNO2. Return false on failure. */
5023 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5024 unsigned int *regno1
, unsigned int *regno2
)
5026 if (match_reg (arg
, type
, regno1
))
5031 if (arg
->token
->type
== OT_REG_RANGE
5032 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5033 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5034 && *regno1
<= *regno2
)
5042 /* OP_INT matcher. */
5045 match_int_operand (struct mips_arg_info
*arg
,
5046 const struct mips_operand
*operand_base
)
5048 const struct mips_int_operand
*operand
;
5050 int min_val
, max_val
, factor
;
5053 operand
= (const struct mips_int_operand
*) operand_base
;
5054 factor
= 1 << operand
->shift
;
5055 min_val
= mips_int_operand_min (operand
);
5056 max_val
= mips_int_operand_max (operand
);
5058 if (operand_base
->lsb
== 0
5059 && operand_base
->size
== 16
5060 && operand
->shift
== 0
5061 && operand
->bias
== 0
5062 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5064 /* The operand can be relocated. */
5065 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5068 if (offset_expr
.X_op
== O_big
)
5070 match_out_of_range (arg
);
5074 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5075 /* Relocation operators were used. Accept the argument and
5076 leave the relocation value in offset_expr and offset_relocs
5077 for the caller to process. */
5080 if (offset_expr
.X_op
!= O_constant
)
5082 /* Accept non-constant operands if no later alternative matches,
5083 leaving it for the caller to process. */
5084 if (!arg
->lax_match
)
5086 offset_reloc
[0] = BFD_RELOC_LO16
;
5090 /* Clear the global state; we're going to install the operand
5092 sval
= offset_expr
.X_add_number
;
5093 offset_expr
.X_op
= O_absent
;
5095 /* For compatibility with older assemblers, we accept
5096 0x8000-0xffff as signed 16-bit numbers when only
5097 signed numbers are allowed. */
5100 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5101 if (!arg
->lax_match
&& sval
<= max_val
)
5107 if (!match_const_int (arg
, &sval
))
5111 arg
->last_op_int
= sval
;
5113 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5115 match_out_of_range (arg
);
5119 uval
= (unsigned int) sval
>> operand
->shift
;
5120 uval
-= operand
->bias
;
5122 /* Handle -mfix-cn63xxp1. */
5124 && mips_fix_cn63xxp1
5125 && !mips_opts
.micromips
5126 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5141 /* The rest must be changed to 28. */
5146 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5150 /* OP_MAPPED_INT matcher. */
5153 match_mapped_int_operand (struct mips_arg_info
*arg
,
5154 const struct mips_operand
*operand_base
)
5156 const struct mips_mapped_int_operand
*operand
;
5157 unsigned int uval
, num_vals
;
5160 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5161 if (!match_const_int (arg
, &sval
))
5164 num_vals
= 1 << operand_base
->size
;
5165 for (uval
= 0; uval
< num_vals
; uval
++)
5166 if (operand
->int_map
[uval
] == sval
)
5168 if (uval
== num_vals
)
5170 match_out_of_range (arg
);
5174 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5178 /* OP_MSB matcher. */
5181 match_msb_operand (struct mips_arg_info
*arg
,
5182 const struct mips_operand
*operand_base
)
5184 const struct mips_msb_operand
*operand
;
5185 int min_val
, max_val
, max_high
;
5186 offsetT size
, sval
, high
;
5188 operand
= (const struct mips_msb_operand
*) operand_base
;
5189 min_val
= operand
->bias
;
5190 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5191 max_high
= operand
->opsize
;
5193 if (!match_const_int (arg
, &size
))
5196 high
= size
+ arg
->last_op_int
;
5197 sval
= operand
->add_lsb
? high
: size
;
5199 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5201 match_out_of_range (arg
);
5204 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5208 /* OP_REG matcher. */
5211 match_reg_operand (struct mips_arg_info
*arg
,
5212 const struct mips_operand
*operand_base
)
5214 const struct mips_reg_operand
*operand
;
5215 unsigned int regno
, uval
, num_vals
;
5217 operand
= (const struct mips_reg_operand
*) operand_base
;
5218 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5221 if (operand
->reg_map
)
5223 num_vals
= 1 << operand
->root
.size
;
5224 for (uval
= 0; uval
< num_vals
; uval
++)
5225 if (operand
->reg_map
[uval
] == regno
)
5227 if (num_vals
== uval
)
5233 arg
->last_regno
= regno
;
5234 if (arg
->opnum
== 1)
5235 arg
->dest_regno
= regno
;
5236 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5240 /* OP_REG_PAIR matcher. */
5243 match_reg_pair_operand (struct mips_arg_info
*arg
,
5244 const struct mips_operand
*operand_base
)
5246 const struct mips_reg_pair_operand
*operand
;
5247 unsigned int regno1
, regno2
, uval
, num_vals
;
5249 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5250 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5251 || !match_char (arg
, ',')
5252 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5255 num_vals
= 1 << operand_base
->size
;
5256 for (uval
= 0; uval
< num_vals
; uval
++)
5257 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5259 if (uval
== num_vals
)
5262 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5266 /* OP_PCREL matcher. The caller chooses the relocation type. */
5269 match_pcrel_operand (struct mips_arg_info
*arg
)
5271 bfd_reloc_code_real_type r
[3];
5273 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5276 /* OP_PERF_REG matcher. */
5279 match_perf_reg_operand (struct mips_arg_info
*arg
,
5280 const struct mips_operand
*operand
)
5284 if (!match_const_int (arg
, &sval
))
5289 || (mips_opts
.arch
== CPU_R5900
5290 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5291 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5293 set_insn_error (arg
->argnum
, _("invalid performance register"));
5297 insn_insert_operand (arg
->insn
, operand
, sval
);
5301 /* OP_ADDIUSP matcher. */
5304 match_addiusp_operand (struct mips_arg_info
*arg
,
5305 const struct mips_operand
*operand
)
5310 if (!match_const_int (arg
, &sval
))
5315 match_out_of_range (arg
);
5320 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5322 match_out_of_range (arg
);
5326 uval
= (unsigned int) sval
;
5327 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5328 insn_insert_operand (arg
->insn
, operand
, uval
);
5332 /* OP_CLO_CLZ_DEST matcher. */
5335 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5336 const struct mips_operand
*operand
)
5340 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5343 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5347 /* OP_CHECK_PREV matcher. */
5350 match_check_prev_operand (struct mips_arg_info
*arg
,
5351 const struct mips_operand
*operand_base
)
5353 const struct mips_check_prev_operand
*operand
;
5356 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5358 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5361 if (!operand
->zero_ok
&& regno
== 0)
5364 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5365 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5366 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5368 arg
->last_regno
= regno
;
5369 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5376 /* OP_SAME_RS_RT matcher. */
5379 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5380 const struct mips_operand
*operand
)
5384 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5389 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5393 arg
->last_regno
= regno
;
5395 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5399 /* OP_LWM_SWM_LIST matcher. */
5402 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5403 const struct mips_operand
*operand
)
5405 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5406 struct mips_arg_info reset
;
5409 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5413 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5418 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5421 while (match_char (arg
, ',')
5422 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5425 if (operand
->size
== 2)
5427 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5433 and any permutations of these. */
5434 if ((reglist
& 0xfff1ffff) != 0x80010000)
5437 sregs
= (reglist
>> 17) & 7;
5442 /* The list must include at least one of ra and s0-sN,
5443 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5444 which are $23 and $30 respectively.) E.g.:
5452 and any permutations of these. */
5453 if ((reglist
& 0x3f00ffff) != 0)
5456 ra
= (reglist
>> 27) & 0x10;
5457 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5460 if ((sregs
& -sregs
) != sregs
)
5463 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5467 /* OP_ENTRY_EXIT_LIST matcher. */
5470 match_entry_exit_operand (struct mips_arg_info
*arg
,
5471 const struct mips_operand
*operand
)
5474 bfd_boolean is_exit
;
5476 /* The format is the same for both ENTRY and EXIT, but the constraints
5478 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5479 mask
= (is_exit
? 7 << 3 : 0);
5482 unsigned int regno1
, regno2
;
5483 bfd_boolean is_freg
;
5485 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5487 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5492 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5495 mask
|= (5 + regno2
) << 3;
5497 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5498 mask
|= (regno2
- 3) << 3;
5499 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5500 mask
|= (regno2
- 15) << 1;
5501 else if (regno1
== RA
&& regno2
== RA
)
5506 while (match_char (arg
, ','));
5508 insn_insert_operand (arg
->insn
, operand
, mask
);
5512 /* OP_SAVE_RESTORE_LIST matcher. */
5515 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5517 unsigned int opcode
, args
, statics
, sregs
;
5518 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5521 opcode
= arg
->insn
->insn_opcode
;
5523 num_frame_sizes
= 0;
5529 unsigned int regno1
, regno2
;
5531 if (arg
->token
->type
== OT_INTEGER
)
5533 /* Handle the frame size. */
5534 if (!match_const_int (arg
, &frame_size
))
5536 num_frame_sizes
+= 1;
5540 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5543 while (regno1
<= regno2
)
5545 if (regno1
>= 4 && regno1
<= 7)
5547 if (num_frame_sizes
== 0)
5549 args
|= 1 << (regno1
- 4);
5551 /* statics $a0-$a3 */
5552 statics
|= 1 << (regno1
- 4);
5554 else if (regno1
>= 16 && regno1
<= 23)
5556 sregs
|= 1 << (regno1
- 16);
5557 else if (regno1
== 30)
5560 else if (regno1
== 31)
5561 /* Add $ra to insn. */
5571 while (match_char (arg
, ','));
5573 /* Encode args/statics combination. */
5576 else if (args
== 0xf)
5577 /* All $a0-$a3 are args. */
5578 opcode
|= MIPS16_ALL_ARGS
<< 16;
5579 else if (statics
== 0xf)
5580 /* All $a0-$a3 are statics. */
5581 opcode
|= MIPS16_ALL_STATICS
<< 16;
5584 /* Count arg registers. */
5594 /* Count static registers. */
5596 while (statics
& 0x8)
5598 statics
= (statics
<< 1) & 0xf;
5604 /* Encode args/statics. */
5605 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5608 /* Encode $s0/$s1. */
5609 if (sregs
& (1 << 0)) /* $s0 */
5611 if (sregs
& (1 << 1)) /* $s1 */
5615 /* Encode $s2-$s8. */
5624 opcode
|= num_sregs
<< 24;
5626 /* Encode frame size. */
5627 if (num_frame_sizes
== 0)
5629 set_insn_error (arg
->argnum
, _("missing frame size"));
5632 if (num_frame_sizes
> 1)
5634 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5637 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5639 set_insn_error (arg
->argnum
, _("invalid frame size"));
5642 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5645 opcode
|= (((frame_size
& 0xf0) << 16)
5646 | (frame_size
& 0x0f));
5649 /* Finally build the instruction. */
5650 if ((opcode
>> 16) != 0 || frame_size
== 0)
5651 opcode
|= MIPS16_EXTEND
;
5652 arg
->insn
->insn_opcode
= opcode
;
5656 /* OP_MDMX_IMM_REG matcher. */
5659 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5660 const struct mips_operand
*operand
)
5662 unsigned int regno
, uval
;
5664 const struct mips_opcode
*opcode
;
5666 /* The mips_opcode records whether this is an octobyte or quadhalf
5667 instruction. Start out with that bit in place. */
5668 opcode
= arg
->insn
->insn_mo
;
5669 uval
= mips_extract_operand (operand
, opcode
->match
);
5670 is_qh
= (uval
!= 0);
5672 if (arg
->token
->type
== OT_REG
)
5674 if ((opcode
->membership
& INSN_5400
)
5675 && strcmp (opcode
->name
, "rzu.ob") == 0)
5677 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5682 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5686 /* Check whether this is a vector register or a broadcast of
5687 a single element. */
5688 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5690 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5692 set_insn_error (arg
->argnum
, _("invalid element selector"));
5695 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5700 /* A full vector. */
5701 if ((opcode
->membership
& INSN_5400
)
5702 && (strcmp (opcode
->name
, "sll.ob") == 0
5703 || strcmp (opcode
->name
, "srl.ob") == 0))
5705 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5711 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5713 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5721 if (!match_const_int (arg
, &sval
))
5723 if (sval
< 0 || sval
> 31)
5725 match_out_of_range (arg
);
5728 uval
|= (sval
& 31);
5730 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5732 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5734 insn_insert_operand (arg
->insn
, operand
, uval
);
5738 /* OP_IMM_INDEX matcher. */
5741 match_imm_index_operand (struct mips_arg_info
*arg
,
5742 const struct mips_operand
*operand
)
5744 unsigned int max_val
;
5746 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5749 max_val
= (1 << operand
->size
) - 1;
5750 if (arg
->token
->u
.index
> max_val
)
5752 match_out_of_range (arg
);
5755 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5760 /* OP_REG_INDEX matcher. */
5763 match_reg_index_operand (struct mips_arg_info
*arg
,
5764 const struct mips_operand
*operand
)
5768 if (arg
->token
->type
!= OT_REG_INDEX
)
5771 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5774 insn_insert_operand (arg
->insn
, operand
, regno
);
5779 /* OP_PC matcher. */
5782 match_pc_operand (struct mips_arg_info
*arg
)
5784 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5792 /* OP_NON_ZERO_REG matcher. */
5795 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5796 const struct mips_operand
*operand
)
5800 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5806 arg
->last_regno
= regno
;
5807 insn_insert_operand (arg
->insn
, operand
, regno
);
5811 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5812 register that we need to match. */
5815 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5819 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5822 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5823 the length of the value in bytes (4 for float, 8 for double) and
5824 USING_GPRS says whether the destination is a GPR rather than an FPR.
5826 Return the constant in IMM and OFFSET as follows:
5828 - If the constant should be loaded via memory, set IMM to O_absent and
5829 OFFSET to the memory address.
5831 - Otherwise, if the constant should be loaded into two 32-bit registers,
5832 set IMM to the O_constant to load into the high register and OFFSET
5833 to the corresponding value for the low register.
5835 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5837 These constants only appear as the last operand in an instruction,
5838 and every instruction that accepts them in any variant accepts them
5839 in all variants. This means we don't have to worry about backing out
5840 any changes if the instruction does not match. We just match
5841 unconditionally and report an error if the constant is invalid. */
5844 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5845 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5850 const char *newname
;
5851 unsigned char *data
;
5853 /* Where the constant is placed is based on how the MIPS assembler
5856 length == 4 && using_gprs -- immediate value only
5857 length == 8 && using_gprs -- .rdata or immediate value
5858 length == 4 && !using_gprs -- .lit4 or immediate value
5859 length == 8 && !using_gprs -- .lit8 or immediate value
5861 The .lit4 and .lit8 sections are only used if permitted by the
5863 if (arg
->token
->type
!= OT_FLOAT
)
5865 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5869 gas_assert (arg
->token
->u
.flt
.length
== length
);
5870 data
= arg
->token
->u
.flt
.data
;
5873 /* Handle 32-bit constants for which an immediate value is best. */
5876 || g_switch_value
< 4
5877 || (data
[0] == 0 && data
[1] == 0)
5878 || (data
[2] == 0 && data
[3] == 0)))
5880 imm
->X_op
= O_constant
;
5881 if (!target_big_endian
)
5882 imm
->X_add_number
= bfd_getl32 (data
);
5884 imm
->X_add_number
= bfd_getb32 (data
);
5885 offset
->X_op
= O_absent
;
5889 /* Handle 64-bit constants for which an immediate value is best. */
5891 && !mips_disable_float_construction
5892 /* Constants can only be constructed in GPRs and copied to FPRs if the
5893 GPRs are at least as wide as the FPRs or MTHC1 is available.
5894 Unlike most tests for 32-bit floating-point registers this check
5895 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5896 permit 64-bit moves without MXHC1.
5897 Force the constant into memory otherwise. */
5900 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5902 && ((data
[0] == 0 && data
[1] == 0)
5903 || (data
[2] == 0 && data
[3] == 0))
5904 && ((data
[4] == 0 && data
[5] == 0)
5905 || (data
[6] == 0 && data
[7] == 0)))
5907 /* The value is simple enough to load with a couple of instructions.
5908 If using 32-bit registers, set IMM to the high order 32 bits and
5909 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5911 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5913 imm
->X_op
= O_constant
;
5914 offset
->X_op
= O_constant
;
5915 if (!target_big_endian
)
5917 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5918 offset
->X_add_number
= bfd_getl32 (data
);
5922 imm
->X_add_number
= bfd_getb32 (data
);
5923 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5925 if (offset
->X_add_number
== 0)
5926 offset
->X_op
= O_absent
;
5930 imm
->X_op
= O_constant
;
5931 if (!target_big_endian
)
5932 imm
->X_add_number
= bfd_getl64 (data
);
5934 imm
->X_add_number
= bfd_getb64 (data
);
5935 offset
->X_op
= O_absent
;
5940 /* Switch to the right section. */
5942 subseg
= now_subseg
;
5945 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5950 if (using_gprs
|| g_switch_value
< 8)
5951 newname
= RDATA_SECTION_NAME
;
5956 new_seg
= subseg_new (newname
, (subsegT
) 0);
5957 bfd_set_section_flags (stdoutput
, new_seg
,
5958 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5959 frag_align (length
== 4 ? 2 : 3, 0, 0);
5960 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5961 record_alignment (new_seg
, 4);
5963 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5965 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5967 /* Set the argument to the current address in the section. */
5968 imm
->X_op
= O_absent
;
5969 offset
->X_op
= O_symbol
;
5970 offset
->X_add_symbol
= symbol_temp_new_now ();
5971 offset
->X_add_number
= 0;
5973 /* Put the floating point number into the section. */
5974 p
= frag_more (length
);
5975 memcpy (p
, data
, length
);
5977 /* Switch back to the original section. */
5978 subseg_set (seg
, subseg
);
5982 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5986 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5987 const struct mips_operand
*operand
,
5988 bfd_boolean match_p
)
5992 /* The operand can be an XYZW mask or a single 2-bit channel index
5993 (with X being 0). */
5994 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5996 /* The suffix can be omitted when it is already part of the opcode. */
5997 if (arg
->token
->type
!= OT_CHANNELS
)
6000 uval
= arg
->token
->u
.channels
;
6001 if (operand
->size
== 2)
6003 /* Check that a single bit is set and convert it into a 2-bit index. */
6004 if ((uval
& -uval
) != uval
)
6006 uval
= 4 - ffs (uval
);
6009 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6014 insn_insert_operand (arg
->insn
, operand
, uval
);
6018 /* S is the text seen for ARG. Match it against OPERAND. Return the end
6019 of the argument text if the match is successful, otherwise return null. */
6022 match_operand (struct mips_arg_info
*arg
,
6023 const struct mips_operand
*operand
)
6025 switch (operand
->type
)
6028 return match_int_operand (arg
, operand
);
6031 return match_mapped_int_operand (arg
, operand
);
6034 return match_msb_operand (arg
, operand
);
6037 case OP_OPTIONAL_REG
:
6038 return match_reg_operand (arg
, operand
);
6041 return match_reg_pair_operand (arg
, operand
);
6044 return match_pcrel_operand (arg
);
6047 return match_perf_reg_operand (arg
, operand
);
6049 case OP_ADDIUSP_INT
:
6050 return match_addiusp_operand (arg
, operand
);
6052 case OP_CLO_CLZ_DEST
:
6053 return match_clo_clz_dest_operand (arg
, operand
);
6055 case OP_LWM_SWM_LIST
:
6056 return match_lwm_swm_list_operand (arg
, operand
);
6058 case OP_ENTRY_EXIT_LIST
:
6059 return match_entry_exit_operand (arg
, operand
);
6061 case OP_SAVE_RESTORE_LIST
:
6062 return match_save_restore_list_operand (arg
);
6064 case OP_MDMX_IMM_REG
:
6065 return match_mdmx_imm_reg_operand (arg
, operand
);
6067 case OP_REPEAT_DEST_REG
:
6068 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6070 case OP_REPEAT_PREV_REG
:
6071 return match_tied_reg_operand (arg
, arg
->last_regno
);
6074 return match_pc_operand (arg
);
6077 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6079 case OP_VU0_MATCH_SUFFIX
:
6080 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6083 return match_imm_index_operand (arg
, operand
);
6086 return match_reg_index_operand (arg
, operand
);
6089 return match_same_rs_rt_operand (arg
, operand
);
6092 return match_check_prev_operand (arg
, operand
);
6094 case OP_NON_ZERO_REG
:
6095 return match_non_zero_reg_operand (arg
, operand
);
6100 /* ARG is the state after successfully matching an instruction.
6101 Issue any queued-up warnings. */
6104 check_completed_insn (struct mips_arg_info
*arg
)
6109 as_warn (_("used $at without \".set noat\""));
6111 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6115 /* Return true if modifying general-purpose register REG needs a delay. */
6118 reg_needs_delay (unsigned int reg
)
6120 unsigned long prev_pinfo
;
6122 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6123 if (!mips_opts
.noreorder
6124 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6125 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6126 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6132 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6133 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6134 by VR4120 errata. */
6137 classify_vr4120_insn (const char *name
)
6139 if (strncmp (name
, "macc", 4) == 0)
6140 return FIX_VR4120_MACC
;
6141 if (strncmp (name
, "dmacc", 5) == 0)
6142 return FIX_VR4120_DMACC
;
6143 if (strncmp (name
, "mult", 4) == 0)
6144 return FIX_VR4120_MULT
;
6145 if (strncmp (name
, "dmult", 5) == 0)
6146 return FIX_VR4120_DMULT
;
6147 if (strstr (name
, "div"))
6148 return FIX_VR4120_DIV
;
6149 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6150 return FIX_VR4120_MTHILO
;
6151 return NUM_FIX_VR4120_CLASSES
;
6154 #define INSN_ERET 0x42000018
6155 #define INSN_DERET 0x4200001f
6156 #define INSN_DMULT 0x1c
6157 #define INSN_DMULTU 0x1d
6159 /* Return the number of instructions that must separate INSN1 and INSN2,
6160 where INSN1 is the earlier instruction. Return the worst-case value
6161 for any INSN2 if INSN2 is null. */
6164 insns_between (const struct mips_cl_insn
*insn1
,
6165 const struct mips_cl_insn
*insn2
)
6167 unsigned long pinfo1
, pinfo2
;
6170 /* If INFO2 is null, pessimistically assume that all flags are set for
6171 the second instruction. */
6172 pinfo1
= insn1
->insn_mo
->pinfo
;
6173 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6175 /* For most targets, write-after-read dependencies on the HI and LO
6176 registers must be separated by at least two instructions. */
6177 if (!hilo_interlocks
)
6179 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6181 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6185 /* If we're working around r7000 errata, there must be two instructions
6186 between an mfhi or mflo and any instruction that uses the result. */
6187 if (mips_7000_hilo_fix
6188 && !mips_opts
.micromips
6189 && MF_HILO_INSN (pinfo1
)
6190 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6193 /* If we're working around 24K errata, one instruction is required
6194 if an ERET or DERET is followed by a branch instruction. */
6195 if (mips_fix_24k
&& !mips_opts
.micromips
)
6197 if (insn1
->insn_opcode
== INSN_ERET
6198 || insn1
->insn_opcode
== INSN_DERET
)
6201 || insn2
->insn_opcode
== INSN_ERET
6202 || insn2
->insn_opcode
== INSN_DERET
6203 || delayed_branch_p (insn2
))
6208 /* If we're working around PMC RM7000 errata, there must be three
6209 nops between a dmult and a load instruction. */
6210 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6212 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6213 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6215 if (pinfo2
& INSN_LOAD_MEMORY
)
6220 /* If working around VR4120 errata, check for combinations that need
6221 a single intervening instruction. */
6222 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6224 unsigned int class1
, class2
;
6226 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6227 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6231 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6232 if (vr4120_conflicts
[class1
] & (1 << class2
))
6237 if (!HAVE_CODE_COMPRESSION
)
6239 /* Check for GPR or coprocessor load delays. All such delays
6240 are on the RT register. */
6241 /* Itbl support may require additional care here. */
6242 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6243 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6245 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6249 /* Check for generic coprocessor hazards.
6251 This case is not handled very well. There is no special
6252 knowledge of CP0 handling, and the coprocessors other than
6253 the floating point unit are not distinguished at all. */
6254 /* Itbl support may require additional care here. FIXME!
6255 Need to modify this to include knowledge about
6256 user specified delays! */
6257 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6258 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6260 /* Handle cases where INSN1 writes to a known general coprocessor
6261 register. There must be a one instruction delay before INSN2
6262 if INSN2 reads that register, otherwise no delay is needed. */
6263 mask
= fpr_write_mask (insn1
);
6266 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6271 /* Read-after-write dependencies on the control registers
6272 require a two-instruction gap. */
6273 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6274 && (pinfo2
& INSN_READ_COND_CODE
))
6277 /* We don't know exactly what INSN1 does. If INSN2 is
6278 also a coprocessor instruction, assume there must be
6279 a one instruction gap. */
6280 if (pinfo2
& INSN_COP
)
6285 /* Check for read-after-write dependencies on the coprocessor
6286 control registers in cases where INSN1 does not need a general
6287 coprocessor delay. This means that INSN1 is a floating point
6288 comparison instruction. */
6289 /* Itbl support may require additional care here. */
6290 else if (!cop_interlocks
6291 && (pinfo1
& INSN_WRITE_COND_CODE
)
6292 && (pinfo2
& INSN_READ_COND_CODE
))
6296 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6297 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6299 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6300 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6301 || (insn2
&& delayed_branch_p (insn2
))))
6307 /* Return the number of nops that would be needed to work around the
6308 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6309 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6310 that are contained within the first IGNORE instructions of HIST. */
6313 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6314 const struct mips_cl_insn
*insn
)
6319 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6320 are not affected by the errata. */
6322 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6323 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6324 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6327 /* Search for the first MFLO or MFHI. */
6328 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6329 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6331 /* Extract the destination register. */
6332 mask
= gpr_write_mask (&hist
[i
]);
6334 /* No nops are needed if INSN reads that register. */
6335 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6338 /* ...or if any of the intervening instructions do. */
6339 for (j
= 0; j
< i
; j
++)
6340 if (gpr_read_mask (&hist
[j
]) & mask
)
6344 return MAX_VR4130_NOPS
- i
;
6349 #define BASE_REG_EQ(INSN1, INSN2) \
6350 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6351 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6353 /* Return the minimum alignment for this store instruction. */
6356 fix_24k_align_to (const struct mips_opcode
*mo
)
6358 if (strcmp (mo
->name
, "sh") == 0)
6361 if (strcmp (mo
->name
, "swc1") == 0
6362 || strcmp (mo
->name
, "swc2") == 0
6363 || strcmp (mo
->name
, "sw") == 0
6364 || strcmp (mo
->name
, "sc") == 0
6365 || strcmp (mo
->name
, "s.s") == 0)
6368 if (strcmp (mo
->name
, "sdc1") == 0
6369 || strcmp (mo
->name
, "sdc2") == 0
6370 || strcmp (mo
->name
, "s.d") == 0)
6377 struct fix_24k_store_info
6379 /* Immediate offset, if any, for this store instruction. */
6381 /* Alignment required by this store instruction. */
6383 /* True for register offsets. */
6384 int register_offset
;
6387 /* Comparison function used by qsort. */
6390 fix_24k_sort (const void *a
, const void *b
)
6392 const struct fix_24k_store_info
*pos1
= a
;
6393 const struct fix_24k_store_info
*pos2
= b
;
6395 return (pos1
->off
- pos2
->off
);
6398 /* INSN is a store instruction. Try to record the store information
6399 in STINFO. Return false if the information isn't known. */
6402 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6403 const struct mips_cl_insn
*insn
)
6405 /* The instruction must have a known offset. */
6406 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6409 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6410 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6414 /* Return the number of nops that would be needed to work around the 24k
6415 "lost data on stores during refill" errata if instruction INSN
6416 immediately followed the 2 instructions described by HIST.
6417 Ignore hazards that are contained within the first IGNORE
6418 instructions of HIST.
6420 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6421 for the data cache refills and store data. The following describes
6422 the scenario where the store data could be lost.
6424 * A data cache miss, due to either a load or a store, causing fill
6425 data to be supplied by the memory subsystem
6426 * The first three doublewords of fill data are returned and written
6428 * A sequence of four stores occurs in consecutive cycles around the
6429 final doubleword of the fill:
6433 * Zero, One or more instructions
6436 The four stores A-D must be to different doublewords of the line that
6437 is being filled. The fourth instruction in the sequence above permits
6438 the fill of the final doubleword to be transferred from the FSB into
6439 the cache. In the sequence above, the stores may be either integer
6440 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6441 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6442 different doublewords on the line. If the floating point unit is
6443 running in 1:2 mode, it is not possible to create the sequence above
6444 using only floating point store instructions.
6446 In this case, the cache line being filled is incorrectly marked
6447 invalid, thereby losing the data from any store to the line that
6448 occurs between the original miss and the completion of the five
6449 cycle sequence shown above.
6451 The workarounds are:
6453 * Run the data cache in write-through mode.
6454 * Insert a non-store instruction between
6455 Store A and Store B or Store B and Store C. */
6458 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6459 const struct mips_cl_insn
*insn
)
6461 struct fix_24k_store_info pos
[3];
6462 int align
, i
, base_offset
;
6467 /* If the previous instruction wasn't a store, there's nothing to
6469 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6472 /* If the instructions after the previous one are unknown, we have
6473 to assume the worst. */
6477 /* Check whether we are dealing with three consecutive stores. */
6478 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6479 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6482 /* If we don't know the relationship between the store addresses,
6483 assume the worst. */
6484 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6485 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6488 if (!fix_24k_record_store_info (&pos
[0], insn
)
6489 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6490 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6493 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6495 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6496 X bytes and such that the base register + X is known to be aligned
6499 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6503 align
= pos
[0].align_to
;
6504 base_offset
= pos
[0].off
;
6505 for (i
= 1; i
< 3; i
++)
6506 if (align
< pos
[i
].align_to
)
6508 align
= pos
[i
].align_to
;
6509 base_offset
= pos
[i
].off
;
6511 for (i
= 0; i
< 3; i
++)
6512 pos
[i
].off
-= base_offset
;
6515 pos
[0].off
&= ~align
+ 1;
6516 pos
[1].off
&= ~align
+ 1;
6517 pos
[2].off
&= ~align
+ 1;
6519 /* If any two stores write to the same chunk, they also write to the
6520 same doubleword. The offsets are still sorted at this point. */
6521 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6524 /* A range of at least 9 bytes is needed for the stores to be in
6525 non-overlapping doublewords. */
6526 if (pos
[2].off
- pos
[0].off
<= 8)
6529 if (pos
[2].off
- pos
[1].off
>= 24
6530 || pos
[1].off
- pos
[0].off
>= 24
6531 || pos
[2].off
- pos
[0].off
>= 32)
6537 /* Return the number of nops that would be needed if instruction INSN
6538 immediately followed the MAX_NOPS instructions given by HIST,
6539 where HIST[0] is the most recent instruction. Ignore hazards
6540 between INSN and the first IGNORE instructions in HIST.
6542 If INSN is null, return the worse-case number of nops for any
6546 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6547 const struct mips_cl_insn
*insn
)
6549 int i
, nops
, tmp_nops
;
6552 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6554 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6555 if (tmp_nops
> nops
)
6559 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6561 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6562 if (tmp_nops
> nops
)
6566 if (mips_fix_24k
&& !mips_opts
.micromips
)
6568 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6569 if (tmp_nops
> nops
)
6576 /* The variable arguments provide NUM_INSNS extra instructions that
6577 might be added to HIST. Return the largest number of nops that
6578 would be needed after the extended sequence, ignoring hazards
6579 in the first IGNORE instructions. */
6582 nops_for_sequence (int num_insns
, int ignore
,
6583 const struct mips_cl_insn
*hist
, ...)
6586 struct mips_cl_insn buffer
[MAX_NOPS
];
6587 struct mips_cl_insn
*cursor
;
6590 va_start (args
, hist
);
6591 cursor
= buffer
+ num_insns
;
6592 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6593 while (cursor
> buffer
)
6594 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6596 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6601 /* Like nops_for_insn, but if INSN is a branch, take into account the
6602 worst-case delay for the branch target. */
6605 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6606 const struct mips_cl_insn
*insn
)
6610 nops
= nops_for_insn (ignore
, hist
, insn
);
6611 if (delayed_branch_p (insn
))
6613 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6614 hist
, insn
, get_delay_slot_nop (insn
));
6615 if (tmp_nops
> nops
)
6618 else if (compact_branch_p (insn
))
6620 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6621 if (tmp_nops
> nops
)
6627 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6630 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6632 gas_assert (!HAVE_CODE_COMPRESSION
);
6633 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6634 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6637 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6638 jr target pc &= 'hffff_ffff_cfff_ffff. */
6641 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6643 gas_assert (!HAVE_CODE_COMPRESSION
);
6644 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6645 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6646 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6654 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6655 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6658 ep
.X_op
= O_constant
;
6659 ep
.X_add_number
= 0xcfff0000;
6660 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6661 ep
.X_add_number
= 0xffff;
6662 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6663 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6668 fix_loongson2f (struct mips_cl_insn
* ip
)
6670 if (mips_fix_loongson2f_nop
)
6671 fix_loongson2f_nop (ip
);
6673 if (mips_fix_loongson2f_jump
)
6674 fix_loongson2f_jump (ip
);
6677 /* IP is a branch that has a delay slot, and we need to fill it
6678 automatically. Return true if we can do that by swapping IP
6679 with the previous instruction.
6680 ADDRESS_EXPR is an operand of the instruction to be used with
6684 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6685 bfd_reloc_code_real_type
*reloc_type
)
6687 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6688 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6689 unsigned int fpr_read
, prev_fpr_write
;
6691 /* -O2 and above is required for this optimization. */
6692 if (mips_optimize
< 2)
6695 /* If we have seen .set volatile or .set nomove, don't optimize. */
6696 if (mips_opts
.nomove
)
6699 /* We can't swap if the previous instruction's position is fixed. */
6700 if (history
[0].fixed_p
)
6703 /* If the previous previous insn was in a .set noreorder, we can't
6704 swap. Actually, the MIPS assembler will swap in this situation.
6705 However, gcc configured -with-gnu-as will generate code like
6713 in which we can not swap the bne and INSN. If gcc is not configured
6714 -with-gnu-as, it does not output the .set pseudo-ops. */
6715 if (history
[1].noreorder_p
)
6718 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6719 This means that the previous instruction was a 4-byte one anyhow. */
6720 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6723 /* If the branch is itself the target of a branch, we can not swap.
6724 We cheat on this; all we check for is whether there is a label on
6725 this instruction. If there are any branches to anything other than
6726 a label, users must use .set noreorder. */
6727 if (seg_info (now_seg
)->label_list
)
6730 /* If the previous instruction is in a variant frag other than this
6731 branch's one, we cannot do the swap. This does not apply to
6732 MIPS16 code, which uses variant frags for different purposes. */
6733 if (!mips_opts
.mips16
6735 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6738 /* We do not swap with instructions that cannot architecturally
6739 be placed in a branch delay slot, such as SYNC or ERET. We
6740 also refrain from swapping with a trap instruction, since it
6741 complicates trap handlers to have the trap instruction be in
6743 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6744 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6747 /* Check for conflicts between the branch and the instructions
6748 before the candidate delay slot. */
6749 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6752 /* Check for conflicts between the swapped sequence and the
6753 target of the branch. */
6754 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6757 /* If the branch reads a register that the previous
6758 instruction sets, we can not swap. */
6759 gpr_read
= gpr_read_mask (ip
);
6760 prev_gpr_write
= gpr_write_mask (&history
[0]);
6761 if (gpr_read
& prev_gpr_write
)
6764 fpr_read
= fpr_read_mask (ip
);
6765 prev_fpr_write
= fpr_write_mask (&history
[0]);
6766 if (fpr_read
& prev_fpr_write
)
6769 /* If the branch writes a register that the previous
6770 instruction sets, we can not swap. */
6771 gpr_write
= gpr_write_mask (ip
);
6772 if (gpr_write
& prev_gpr_write
)
6775 /* If the branch writes a register that the previous
6776 instruction reads, we can not swap. */
6777 prev_gpr_read
= gpr_read_mask (&history
[0]);
6778 if (gpr_write
& prev_gpr_read
)
6781 /* If one instruction sets a condition code and the
6782 other one uses a condition code, we can not swap. */
6783 pinfo
= ip
->insn_mo
->pinfo
;
6784 if ((pinfo
& INSN_READ_COND_CODE
)
6785 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6787 if ((pinfo
& INSN_WRITE_COND_CODE
)
6788 && (prev_pinfo
& INSN_READ_COND_CODE
))
6791 /* If the previous instruction uses the PC, we can not swap. */
6792 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6793 if (prev_pinfo2
& INSN2_READ_PC
)
6796 /* If the previous instruction has an incorrect size for a fixed
6797 branch delay slot in microMIPS mode, we cannot swap. */
6798 pinfo2
= ip
->insn_mo
->pinfo2
;
6799 if (mips_opts
.micromips
6800 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6801 && insn_length (history
) != 2)
6803 if (mips_opts
.micromips
6804 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6805 && insn_length (history
) != 4)
6808 /* On R5900 short loops need to be fixed by inserting a nop in
6809 the branch delay slots.
6810 A short loop can be terminated too early. */
6811 if (mips_opts
.arch
== CPU_R5900
6812 /* Check if instruction has a parameter, ignore "j $31". */
6813 && (address_expr
!= NULL
)
6814 /* Parameter must be 16 bit. */
6815 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6816 /* Branch to same segment. */
6817 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6818 /* Branch to same code fragment. */
6819 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6820 /* Can only calculate branch offset if value is known. */
6821 && symbol_constant_p (address_expr
->X_add_symbol
)
6822 /* Check if branch is really conditional. */
6823 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6824 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6825 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6828 /* Check if loop is shorter than 6 instructions including
6829 branch and delay slot. */
6830 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6837 /* When the loop includes branches or jumps,
6838 it is not a short loop. */
6839 for (i
= 0; i
< (distance
/ 4); i
++)
6841 if ((history
[i
].cleared_p
)
6842 || delayed_branch_p (&history
[i
]))
6850 /* Insert nop after branch to fix short loop. */
6859 /* Decide how we should add IP to the instruction stream.
6860 ADDRESS_EXPR is an operand of the instruction to be used with
6863 static enum append_method
6864 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6865 bfd_reloc_code_real_type
*reloc_type
)
6867 /* The relaxed version of a macro sequence must be inherently
6869 if (mips_relax
.sequence
== 2)
6872 /* We must not dabble with instructions in a ".set noreorder" block. */
6873 if (mips_opts
.noreorder
)
6876 /* Otherwise, it's our responsibility to fill branch delay slots. */
6877 if (delayed_branch_p (ip
))
6879 if (!branch_likely_p (ip
)
6880 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6883 if (mips_opts
.mips16
6884 && ISA_SUPPORTS_MIPS16E
6885 && gpr_read_mask (ip
) != 0)
6886 return APPEND_ADD_COMPACT
;
6888 if (mips_opts
.micromips
6889 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6890 || (!forced_insn_length
6891 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6892 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6893 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6894 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6895 return APPEND_ADD_COMPACT
;
6897 return APPEND_ADD_WITH_NOP
;
6903 /* IP is an instruction whose opcode we have just changed, END points
6904 to the end of the opcode table processed. Point IP->insn_mo to the
6905 new opcode's definition. */
6908 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6910 const struct mips_opcode
*mo
;
6912 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6913 if (mo
->pinfo
!= INSN_MACRO
6914 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6922 /* IP is a MIPS16 instruction whose opcode we have just changed.
6923 Point IP->insn_mo to the new opcode's definition. */
6926 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6928 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6931 /* IP is a microMIPS instruction whose opcode we have just changed.
6932 Point IP->insn_mo to the new opcode's definition. */
6935 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6937 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6940 /* For microMIPS macros, we need to generate a local number label
6941 as the target of branches. */
6942 #define MICROMIPS_LABEL_CHAR '\037'
6943 static unsigned long micromips_target_label
;
6944 static char micromips_target_name
[32];
6947 micromips_label_name (void)
6949 char *p
= micromips_target_name
;
6950 char symbol_name_temporary
[24];
6958 l
= micromips_target_label
;
6959 #ifdef LOCAL_LABEL_PREFIX
6960 *p
++ = LOCAL_LABEL_PREFIX
;
6963 *p
++ = MICROMIPS_LABEL_CHAR
;
6966 symbol_name_temporary
[i
++] = l
% 10 + '0';
6971 *p
++ = symbol_name_temporary
[--i
];
6974 return micromips_target_name
;
6978 micromips_label_expr (expressionS
*label_expr
)
6980 label_expr
->X_op
= O_symbol
;
6981 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6982 label_expr
->X_add_number
= 0;
6986 micromips_label_inc (void)
6988 micromips_target_label
++;
6989 *micromips_target_name
= '\0';
6993 micromips_add_label (void)
6997 s
= colon (micromips_label_name ());
6998 micromips_label_inc ();
6999 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7002 /* If assembling microMIPS code, then return the microMIPS reloc
7003 corresponding to the requested one if any. Otherwise return
7004 the reloc unchanged. */
7006 static bfd_reloc_code_real_type
7007 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7009 static const bfd_reloc_code_real_type relocs
[][2] =
7011 /* Keep sorted incrementally by the left-hand key. */
7012 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7013 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7014 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7015 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7016 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7017 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7018 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7019 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7020 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7021 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7022 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7023 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7024 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7025 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7026 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7027 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7028 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7029 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7030 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7031 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7032 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7033 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7034 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7035 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7036 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7037 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7038 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7040 bfd_reloc_code_real_type r
;
7043 if (!mips_opts
.micromips
)
7045 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7051 return relocs
[i
][1];
7056 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7057 Return true on success, storing the resolved value in RESULT. */
7060 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7065 case BFD_RELOC_MIPS_HIGHEST
:
7066 case BFD_RELOC_MICROMIPS_HIGHEST
:
7067 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7070 case BFD_RELOC_MIPS_HIGHER
:
7071 case BFD_RELOC_MICROMIPS_HIGHER
:
7072 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7075 case BFD_RELOC_HI16_S
:
7076 case BFD_RELOC_HI16_S_PCREL
:
7077 case BFD_RELOC_MICROMIPS_HI16_S
:
7078 case BFD_RELOC_MIPS16_HI16_S
:
7079 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7082 case BFD_RELOC_HI16
:
7083 case BFD_RELOC_MICROMIPS_HI16
:
7084 case BFD_RELOC_MIPS16_HI16
:
7085 *result
= (operand
>> 16) & 0xffff;
7088 case BFD_RELOC_LO16
:
7089 case BFD_RELOC_LO16_PCREL
:
7090 case BFD_RELOC_MICROMIPS_LO16
:
7091 case BFD_RELOC_MIPS16_LO16
:
7092 *result
= operand
& 0xffff;
7095 case BFD_RELOC_UNUSED
:
7104 /* Output an instruction. IP is the instruction information.
7105 ADDRESS_EXPR is an operand of the instruction to be used with
7106 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7107 a macro expansion. */
7110 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7111 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7113 unsigned long prev_pinfo2
, pinfo
;
7114 bfd_boolean relaxed_branch
= FALSE
;
7115 enum append_method method
;
7116 bfd_boolean relax32
;
7119 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7120 fix_loongson2f (ip
);
7122 file_ase_mips16
|= mips_opts
.mips16
;
7123 file_ase_micromips
|= mips_opts
.micromips
;
7125 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7126 pinfo
= ip
->insn_mo
->pinfo
;
7128 /* Don't raise alarm about `nods' frags as they'll fill in the right
7129 kind of nop in relaxation if required. */
7130 if (mips_opts
.micromips
7132 && !(history
[0].frag
7133 && history
[0].frag
->fr_type
== rs_machine_dependent
7134 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7135 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7136 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7137 && micromips_insn_length (ip
->insn_mo
) != 2)
7138 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7139 && micromips_insn_length (ip
->insn_mo
) != 4)))
7140 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7141 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7143 if (address_expr
== NULL
)
7145 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7146 && reloc_type
[1] == BFD_RELOC_UNUSED
7147 && reloc_type
[2] == BFD_RELOC_UNUSED
7148 && address_expr
->X_op
== O_constant
)
7150 switch (*reloc_type
)
7152 case BFD_RELOC_MIPS_JMP
:
7156 /* Shift is 2, unusually, for microMIPS JALX. */
7157 shift
= (mips_opts
.micromips
7158 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7159 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7160 as_bad (_("jump to misaligned address (0x%lx)"),
7161 (unsigned long) address_expr
->X_add_number
);
7162 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7168 case BFD_RELOC_MIPS16_JMP
:
7169 if ((address_expr
->X_add_number
& 3) != 0)
7170 as_bad (_("jump to misaligned address (0x%lx)"),
7171 (unsigned long) address_expr
->X_add_number
);
7173 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7174 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7175 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7179 case BFD_RELOC_16_PCREL_S2
:
7183 shift
= mips_opts
.micromips
? 1 : 2;
7184 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7185 as_bad (_("branch to misaligned address (0x%lx)"),
7186 (unsigned long) address_expr
->X_add_number
);
7187 if (!mips_relax_branch
)
7189 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7190 & ~((1 << (shift
+ 16)) - 1))
7191 as_bad (_("branch address range overflow (0x%lx)"),
7192 (unsigned long) address_expr
->X_add_number
);
7193 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7199 case BFD_RELOC_MIPS_21_PCREL_S2
:
7204 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7205 as_bad (_("branch to misaligned address (0x%lx)"),
7206 (unsigned long) address_expr
->X_add_number
);
7207 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7208 & ~((1 << (shift
+ 21)) - 1))
7209 as_bad (_("branch address range overflow (0x%lx)"),
7210 (unsigned long) address_expr
->X_add_number
);
7211 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7216 case BFD_RELOC_MIPS_26_PCREL_S2
:
7221 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7222 as_bad (_("branch to misaligned address (0x%lx)"),
7223 (unsigned long) address_expr
->X_add_number
);
7224 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7225 & ~((1 << (shift
+ 26)) - 1))
7226 as_bad (_("branch address range overflow (0x%lx)"),
7227 (unsigned long) address_expr
->X_add_number
);
7228 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7237 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7240 ip
->insn_opcode
|= value
& 0xffff;
7248 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7250 /* There are a lot of optimizations we could do that we don't.
7251 In particular, we do not, in general, reorder instructions.
7252 If you use gcc with optimization, it will reorder
7253 instructions and generally do much more optimization then we
7254 do here; repeating all that work in the assembler would only
7255 benefit hand written assembly code, and does not seem worth
7257 int nops
= (mips_optimize
== 0
7258 ? nops_for_insn (0, history
, NULL
)
7259 : nops_for_insn_or_target (0, history
, ip
));
7263 unsigned long old_frag_offset
;
7266 old_frag
= frag_now
;
7267 old_frag_offset
= frag_now_fix ();
7269 for (i
= 0; i
< nops
; i
++)
7270 add_fixed_insn (NOP_INSN
);
7271 insert_into_history (0, nops
, NOP_INSN
);
7275 listing_prev_line ();
7276 /* We may be at the start of a variant frag. In case we
7277 are, make sure there is enough space for the frag
7278 after the frags created by listing_prev_line. The
7279 argument to frag_grow here must be at least as large
7280 as the argument to all other calls to frag_grow in
7281 this file. We don't have to worry about being in the
7282 middle of a variant frag, because the variants insert
7283 all needed nop instructions themselves. */
7287 mips_move_text_labels ();
7289 #ifndef NO_ECOFF_DEBUGGING
7290 if (ECOFF_DEBUGGING
)
7291 ecoff_fix_loc (old_frag
, old_frag_offset
);
7295 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7299 /* Work out how many nops in prev_nop_frag are needed by IP,
7300 ignoring hazards generated by the first prev_nop_frag_since
7302 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7303 gas_assert (nops
<= prev_nop_frag_holds
);
7305 /* Enforce NOPS as a minimum. */
7306 if (nops
> prev_nop_frag_required
)
7307 prev_nop_frag_required
= nops
;
7309 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7311 /* Settle for the current number of nops. Update the history
7312 accordingly (for the benefit of any future .set reorder code). */
7313 prev_nop_frag
= NULL
;
7314 insert_into_history (prev_nop_frag_since
,
7315 prev_nop_frag_holds
, NOP_INSN
);
7319 /* Allow this instruction to replace one of the nops that was
7320 tentatively added to prev_nop_frag. */
7321 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7322 prev_nop_frag_holds
--;
7323 prev_nop_frag_since
++;
7327 method
= get_append_method (ip
, address_expr
, reloc_type
);
7328 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7330 dwarf2_emit_insn (0);
7331 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7332 so "move" the instruction address accordingly.
7334 Also, it doesn't seem appropriate for the assembler to reorder .loc
7335 entries. If this instruction is a branch that we are going to swap
7336 with the previous instruction, the two instructions should be
7337 treated as a unit, and the debug information for both instructions
7338 should refer to the start of the branch sequence. Using the
7339 current position is certainly wrong when swapping a 32-bit branch
7340 and a 16-bit delay slot, since the current position would then be
7341 in the middle of a branch. */
7342 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7344 relax32
= (mips_relax_branch
7345 /* Don't try branch relaxation within .set nomacro, or within
7346 .set noat if we use $at for PIC computations. If it turns
7347 out that the branch was out-of-range, we'll get an error. */
7348 && !mips_opts
.warn_about_macros
7349 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7350 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7351 as they have no complementing branches. */
7352 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7354 if (!HAVE_CODE_COMPRESSION
7357 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7358 && delayed_branch_p (ip
))
7360 relaxed_branch
= TRUE
;
7361 add_relaxed_insn (ip
, (relaxed_branch_length
7363 uncond_branch_p (ip
) ? -1
7364 : branch_likely_p (ip
) ? 1
7367 (AT
, mips_pic
!= NO_PIC
,
7368 uncond_branch_p (ip
),
7369 branch_likely_p (ip
),
7370 pinfo
& INSN_WRITE_GPR_31
,
7372 address_expr
->X_add_symbol
,
7373 address_expr
->X_add_number
);
7374 *reloc_type
= BFD_RELOC_UNUSED
;
7376 else if (mips_opts
.micromips
7378 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7379 || *reloc_type
> BFD_RELOC_UNUSED
)
7380 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7381 /* Don't try branch relaxation when users specify
7382 16-bit/32-bit instructions. */
7383 && !forced_insn_length
)
7385 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7386 && *reloc_type
> BFD_RELOC_UNUSED
);
7387 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7388 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7389 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7390 int nods
= method
== APPEND_ADD_WITH_NOP
;
7391 int al
= pinfo
& INSN_WRITE_GPR_31
;
7392 int length32
= nods
? 8 : 4;
7394 gas_assert (address_expr
!= NULL
);
7395 gas_assert (!mips_relax
.sequence
);
7397 relaxed_branch
= TRUE
;
7399 method
= APPEND_ADD
;
7401 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7402 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7403 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7405 uncond
, compact
, al
, nods
,
7407 address_expr
->X_add_symbol
,
7408 address_expr
->X_add_number
);
7409 *reloc_type
= BFD_RELOC_UNUSED
;
7411 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7413 bfd_boolean require_unextended
;
7414 bfd_boolean require_extended
;
7418 if (forced_insn_length
!= 0)
7420 require_unextended
= forced_insn_length
== 2;
7421 require_extended
= forced_insn_length
== 4;
7425 require_unextended
= (mips_opts
.noautoextend
7426 && !mips_opcode_32bit_p (ip
->insn_mo
));
7427 require_extended
= 0;
7430 /* We need to set up a variant frag. */
7431 gas_assert (address_expr
!= NULL
);
7432 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7433 symbol created by `make_expr_symbol' may not get a necessary
7434 external relocation produced. */
7435 if (address_expr
->X_op
== O_symbol
)
7437 symbol
= address_expr
->X_add_symbol
;
7438 offset
= address_expr
->X_add_number
;
7442 symbol
= make_expr_symbol (address_expr
);
7443 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7446 add_relaxed_insn (ip
, 12, 0,
7448 (*reloc_type
- BFD_RELOC_UNUSED
,
7451 mips_opts
.warn_about_macros
,
7452 require_unextended
, require_extended
,
7453 delayed_branch_p (&history
[0]),
7454 history
[0].mips16_absolute_jump_p
),
7457 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7459 if (!delayed_branch_p (ip
))
7460 /* Make sure there is enough room to swap this instruction with
7461 a following jump instruction. */
7463 add_fixed_insn (ip
);
7467 if (mips_opts
.mips16
7468 && mips_opts
.noreorder
7469 && delayed_branch_p (&history
[0]))
7470 as_warn (_("extended instruction in delay slot"));
7472 if (mips_relax
.sequence
)
7474 /* If we've reached the end of this frag, turn it into a variant
7475 frag and record the information for the instructions we've
7477 if (frag_room () < 4)
7478 relax_close_frag ();
7479 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7482 if (mips_relax
.sequence
!= 2)
7484 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7485 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7486 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7487 mips_macro_warning
.insns
[0]++;
7489 if (mips_relax
.sequence
!= 1)
7491 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7492 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7493 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7494 mips_macro_warning
.insns
[1]++;
7497 if (mips_opts
.mips16
)
7500 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7502 add_fixed_insn (ip
);
7505 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7507 bfd_reloc_code_real_type final_type
[3];
7508 reloc_howto_type
*howto0
;
7509 reloc_howto_type
*howto
;
7512 /* Perform any necessary conversion to microMIPS relocations
7513 and find out how many relocations there actually are. */
7514 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7515 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7517 /* In a compound relocation, it is the final (outermost)
7518 operator that determines the relocated field. */
7519 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7524 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7525 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7526 bfd_get_reloc_size (howto
),
7528 howto0
&& howto0
->pc_relative
,
7530 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7531 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7533 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7534 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7535 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7537 /* These relocations can have an addend that won't fit in
7538 4 octets for 64bit assembly. */
7540 && ! howto
->partial_inplace
7541 && (reloc_type
[0] == BFD_RELOC_16
7542 || reloc_type
[0] == BFD_RELOC_32
7543 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7544 || reloc_type
[0] == BFD_RELOC_GPREL16
7545 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7546 || reloc_type
[0] == BFD_RELOC_GPREL32
7547 || reloc_type
[0] == BFD_RELOC_64
7548 || reloc_type
[0] == BFD_RELOC_CTOR
7549 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7550 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7551 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7552 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7553 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7554 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7555 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7556 || hi16_reloc_p (reloc_type
[0])
7557 || lo16_reloc_p (reloc_type
[0])))
7558 ip
->fixp
[0]->fx_no_overflow
= 1;
7560 /* These relocations can have an addend that won't fit in 2 octets. */
7561 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7562 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7563 ip
->fixp
[0]->fx_no_overflow
= 1;
7565 if (mips_relax
.sequence
)
7567 if (mips_relax
.first_fixup
== 0)
7568 mips_relax
.first_fixup
= ip
->fixp
[0];
7570 else if (reloc_needs_lo_p (*reloc_type
))
7572 struct mips_hi_fixup
*hi_fixup
;
7574 /* Reuse the last entry if it already has a matching %lo. */
7575 hi_fixup
= mips_hi_fixup_list
;
7577 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7579 hi_fixup
= XNEW (struct mips_hi_fixup
);
7580 hi_fixup
->next
= mips_hi_fixup_list
;
7581 mips_hi_fixup_list
= hi_fixup
;
7583 hi_fixup
->fixp
= ip
->fixp
[0];
7584 hi_fixup
->seg
= now_seg
;
7587 /* Add fixups for the second and third relocations, if given.
7588 Note that the ABI allows the second relocation to be
7589 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7590 moment we only use RSS_UNDEF, but we could add support
7591 for the others if it ever becomes necessary. */
7592 for (i
= 1; i
< 3; i
++)
7593 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7595 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7596 ip
->fixp
[0]->fx_size
, NULL
, 0,
7597 FALSE
, final_type
[i
]);
7599 /* Use fx_tcbit to mark compound relocs. */
7600 ip
->fixp
[0]->fx_tcbit
= 1;
7601 ip
->fixp
[i
]->fx_tcbit
= 1;
7605 /* Update the register mask information. */
7606 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7607 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7612 insert_into_history (0, 1, ip
);
7615 case APPEND_ADD_WITH_NOP
:
7617 struct mips_cl_insn
*nop
;
7619 insert_into_history (0, 1, ip
);
7620 nop
= get_delay_slot_nop (ip
);
7621 add_fixed_insn (nop
);
7622 insert_into_history (0, 1, nop
);
7623 if (mips_relax
.sequence
)
7624 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7628 case APPEND_ADD_COMPACT
:
7629 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7630 if (mips_opts
.mips16
)
7632 ip
->insn_opcode
|= 0x0080;
7633 find_altered_mips16_opcode (ip
);
7635 /* Convert microMIPS instructions. */
7636 else if (mips_opts
.micromips
)
7639 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7640 ip
->insn_opcode
|= 0x0020;
7642 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7643 ip
->insn_opcode
= 0x40e00000;
7644 /* beqz16->beqzc, bnez16->bnezc */
7645 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7647 unsigned long regno
;
7649 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7650 regno
&= MICROMIPSOP_MASK_MD
;
7651 regno
= micromips_to_32_reg_d_map
[regno
];
7652 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7653 | (regno
<< MICROMIPSOP_SH_RS
)
7654 | 0x40a00000) ^ 0x00400000;
7656 /* beqz->beqzc, bnez->bnezc */
7657 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7658 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7659 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7660 | 0x40a00000) ^ 0x00400000;
7661 /* beq $0->beqzc, bne $0->bnezc */
7662 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7663 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7664 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7665 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7666 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7667 | 0x40a00000) ^ 0x00400000;
7670 find_altered_micromips_opcode (ip
);
7675 insert_into_history (0, 1, ip
);
7680 struct mips_cl_insn delay
= history
[0];
7682 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7684 /* Add the delay slot instruction to the end of the
7685 current frag and shrink the fixed part of the
7686 original frag. If the branch occupies the tail of
7687 the latter, move it backwards to cover the gap. */
7688 delay
.frag
->fr_fix
-= branch_disp
;
7689 if (delay
.frag
== ip
->frag
)
7690 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7691 add_fixed_insn (&delay
);
7695 /* If this is not a relaxed branch and we are in the
7696 same frag, then just swap the instructions. */
7697 move_insn (ip
, delay
.frag
, delay
.where
);
7698 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7702 insert_into_history (0, 1, &delay
);
7707 /* If we have just completed an unconditional branch, clear the history. */
7708 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7709 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7713 mips_no_prev_insn ();
7715 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7716 history
[i
].cleared_p
= 1;
7719 /* We need to emit a label at the end of branch-likely macros. */
7720 if (emit_branch_likely_macro
)
7722 emit_branch_likely_macro
= FALSE
;
7723 micromips_add_label ();
7726 /* We just output an insn, so the next one doesn't have a label. */
7727 mips_clear_insn_labels ();
7730 /* Forget that there was any previous instruction or label.
7731 When BRANCH is true, the branch history is also flushed. */
7734 mips_no_prev_insn (void)
7736 prev_nop_frag
= NULL
;
7737 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7738 mips_clear_insn_labels ();
7741 /* This function must be called before we emit something other than
7742 instructions. It is like mips_no_prev_insn except that it inserts
7743 any NOPS that might be needed by previous instructions. */
7746 mips_emit_delays (void)
7748 if (! mips_opts
.noreorder
)
7750 int nops
= nops_for_insn (0, history
, NULL
);
7754 add_fixed_insn (NOP_INSN
);
7755 mips_move_text_labels ();
7758 mips_no_prev_insn ();
7761 /* Start a (possibly nested) noreorder block. */
7764 start_noreorder (void)
7766 if (mips_opts
.noreorder
== 0)
7771 /* None of the instructions before the .set noreorder can be moved. */
7772 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7773 history
[i
].fixed_p
= 1;
7775 /* Insert any nops that might be needed between the .set noreorder
7776 block and the previous instructions. We will later remove any
7777 nops that turn out not to be needed. */
7778 nops
= nops_for_insn (0, history
, NULL
);
7781 if (mips_optimize
!= 0)
7783 /* Record the frag which holds the nop instructions, so
7784 that we can remove them if we don't need them. */
7785 frag_grow (nops
* NOP_INSN_SIZE
);
7786 prev_nop_frag
= frag_now
;
7787 prev_nop_frag_holds
= nops
;
7788 prev_nop_frag_required
= 0;
7789 prev_nop_frag_since
= 0;
7792 for (; nops
> 0; --nops
)
7793 add_fixed_insn (NOP_INSN
);
7795 /* Move on to a new frag, so that it is safe to simply
7796 decrease the size of prev_nop_frag. */
7797 frag_wane (frag_now
);
7799 mips_move_text_labels ();
7801 mips_mark_labels ();
7802 mips_clear_insn_labels ();
7804 mips_opts
.noreorder
++;
7805 mips_any_noreorder
= 1;
7808 /* End a nested noreorder block. */
7811 end_noreorder (void)
7813 mips_opts
.noreorder
--;
7814 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7816 /* Commit to inserting prev_nop_frag_required nops and go back to
7817 handling nop insertion the .set reorder way. */
7818 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7820 insert_into_history (prev_nop_frag_since
,
7821 prev_nop_frag_required
, NOP_INSN
);
7822 prev_nop_frag
= NULL
;
7826 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7827 higher bits unset. */
7830 normalize_constant_expr (expressionS
*ex
)
7832 if (ex
->X_op
== O_constant
7833 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7834 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7838 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7839 all higher bits unset. */
7842 normalize_address_expr (expressionS
*ex
)
7844 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7845 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7846 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7847 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7851 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7852 Return true if the match was successful.
7854 OPCODE_EXTRA is a value that should be ORed into the opcode
7855 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7856 there are more alternatives after OPCODE and SOFT_MATCH is
7857 as for mips_arg_info. */
7860 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7861 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7862 bfd_boolean lax_match
, bfd_boolean complete_p
)
7865 struct mips_arg_info arg
;
7866 const struct mips_operand
*operand
;
7869 imm_expr
.X_op
= O_absent
;
7870 offset_expr
.X_op
= O_absent
;
7871 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7872 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7873 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7875 create_insn (insn
, opcode
);
7876 /* When no opcode suffix is specified, assume ".xyzw". */
7877 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7878 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7880 insn
->insn_opcode
|= opcode_extra
;
7881 memset (&arg
, 0, sizeof (arg
));
7885 arg
.last_regno
= ILLEGAL_REG
;
7886 arg
.dest_regno
= ILLEGAL_REG
;
7887 arg
.lax_match
= lax_match
;
7888 for (args
= opcode
->args
;; ++args
)
7890 if (arg
.token
->type
== OT_END
)
7892 /* Handle unary instructions in which only one operand is given.
7893 The source is then the same as the destination. */
7894 if (arg
.opnum
== 1 && *args
== ',')
7896 operand
= (mips_opts
.micromips
7897 ? decode_micromips_operand (args
+ 1)
7898 : decode_mips_operand (args
+ 1));
7899 if (operand
&& mips_optional_operand_p (operand
))
7907 /* Treat elided base registers as $0. */
7908 if (strcmp (args
, "(b)") == 0)
7916 /* The register suffix is optional. */
7921 /* Fail the match if there were too few operands. */
7925 /* Successful match. */
7928 clear_insn_error ();
7929 if (arg
.dest_regno
== arg
.last_regno
7930 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7934 (0, _("source and destination must be different"));
7935 else if (arg
.last_regno
== 31)
7937 (0, _("a destination register must be supplied"));
7939 else if (arg
.last_regno
== 31
7940 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7941 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7942 set_insn_error (0, _("the source register must not be $31"));
7943 check_completed_insn (&arg
);
7947 /* Fail the match if the line has too many operands. */
7951 /* Handle characters that need to match exactly. */
7952 if (*args
== '(' || *args
== ')' || *args
== ',')
7954 if (match_char (&arg
, *args
))
7961 if (arg
.token
->type
== OT_DOUBLE_CHAR
7962 && arg
.token
->u
.ch
== *args
)
7970 /* Handle special macro operands. Work out the properties of
7979 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7983 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7992 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7996 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8000 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8006 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8008 imm_expr
.X_op
= O_constant
;
8010 normalize_constant_expr (&imm_expr
);
8014 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8016 /* Assume that the offset has been elided and that what
8017 we saw was a base register. The match will fail later
8018 if that assumption turns out to be wrong. */
8019 offset_expr
.X_op
= O_constant
;
8020 offset_expr
.X_add_number
= 0;
8024 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8026 normalize_address_expr (&offset_expr
);
8031 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8037 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8043 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8049 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8055 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8059 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8063 gas_assert (mips_opts
.micromips
);
8069 if (!forced_insn_length
)
8070 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8072 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8074 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8080 operand
= (mips_opts
.micromips
8081 ? decode_micromips_operand (args
)
8082 : decode_mips_operand (args
));
8086 /* Skip prefixes. */
8087 if (*args
== '+' || *args
== 'm' || *args
== '-')
8090 if (mips_optional_operand_p (operand
)
8092 && (arg
.token
[0].type
!= OT_REG
8093 || arg
.token
[1].type
== OT_END
))
8095 /* Assume that the register has been elided and is the
8096 same as the first operand. */
8101 if (!match_operand (&arg
, operand
))
8106 /* Like match_insn, but for MIPS16. */
8109 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8110 struct mips_operand_token
*tokens
)
8113 const struct mips_operand
*operand
;
8114 const struct mips_operand
*ext_operand
;
8115 bfd_boolean pcrel
= FALSE
;
8116 int required_insn_length
;
8117 struct mips_arg_info arg
;
8120 if (forced_insn_length
)
8121 required_insn_length
= forced_insn_length
;
8122 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8123 required_insn_length
= 2;
8125 required_insn_length
= 0;
8127 create_insn (insn
, opcode
);
8128 imm_expr
.X_op
= O_absent
;
8129 offset_expr
.X_op
= O_absent
;
8130 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8131 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8132 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8135 memset (&arg
, 0, sizeof (arg
));
8139 arg
.last_regno
= ILLEGAL_REG
;
8140 arg
.dest_regno
= ILLEGAL_REG
;
8142 for (args
= opcode
->args
;; ++args
)
8146 if (arg
.token
->type
== OT_END
)
8150 /* Handle unary instructions in which only one operand is given.
8151 The source is then the same as the destination. */
8152 if (arg
.opnum
== 1 && *args
== ',')
8154 operand
= decode_mips16_operand (args
[1], FALSE
);
8155 if (operand
&& mips_optional_operand_p (operand
))
8163 /* Fail the match if there were too few operands. */
8167 /* Successful match. Stuff the immediate value in now, if
8169 clear_insn_error ();
8170 if (opcode
->pinfo
== INSN_MACRO
)
8172 gas_assert (relax_char
== 0 || relax_char
== 'p');
8173 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8176 && offset_expr
.X_op
== O_constant
8178 && calculate_reloc (*offset_reloc
,
8179 offset_expr
.X_add_number
,
8182 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8183 required_insn_length
, &insn
->insn_opcode
);
8184 offset_expr
.X_op
= O_absent
;
8185 *offset_reloc
= BFD_RELOC_UNUSED
;
8187 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8189 if (required_insn_length
== 2)
8190 set_insn_error (0, _("invalid unextended operand value"));
8193 forced_insn_length
= 4;
8194 insn
->insn_opcode
|= MIPS16_EXTEND
;
8197 else if (relax_char
)
8198 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8200 check_completed_insn (&arg
);
8204 /* Fail the match if the line has too many operands. */
8208 /* Handle characters that need to match exactly. */
8209 if (*args
== '(' || *args
== ')' || *args
== ',')
8211 if (match_char (&arg
, *args
))
8229 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8231 imm_expr
.X_op
= O_constant
;
8233 normalize_constant_expr (&imm_expr
);
8238 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8242 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8246 if (operand
->type
== OP_PCREL
)
8250 ext_operand
= decode_mips16_operand (c
, TRUE
);
8251 if (operand
!= ext_operand
)
8253 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8255 offset_expr
.X_op
= O_constant
;
8256 offset_expr
.X_add_number
= 0;
8261 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8264 /* '8' is used for SLTI(U) and has traditionally not
8265 been allowed to take relocation operators. */
8266 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8267 && (ext_operand
->size
!= 16 || c
== '8'))
8269 match_not_constant (&arg
);
8273 if (offset_expr
.X_op
== O_big
)
8275 match_out_of_range (&arg
);
8284 if (mips_optional_operand_p (operand
)
8286 && (arg
.token
[0].type
!= OT_REG
8287 || arg
.token
[1].type
== OT_END
))
8289 /* Assume that the register has been elided and is the
8290 same as the first operand. */
8295 if (!match_operand (&arg
, operand
))
8300 /* Record that the current instruction is invalid for the current ISA. */
8303 match_invalid_for_isa (void)
8306 (0, _("opcode not supported on this processor: %s (%s)"),
8307 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8308 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8311 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8312 Return true if a definite match or failure was found, storing any match
8313 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8314 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8315 tried and failed to match under normal conditions and now want to try a
8316 more relaxed match. */
8319 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8320 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8321 int opcode_extra
, bfd_boolean lax_match
)
8323 const struct mips_opcode
*opcode
;
8324 const struct mips_opcode
*invalid_delay_slot
;
8325 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8327 /* Search for a match, ignoring alternatives that don't satisfy the
8328 current ISA or forced_length. */
8329 invalid_delay_slot
= 0;
8330 seen_valid_for_isa
= FALSE
;
8331 seen_valid_for_size
= FALSE
;
8335 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8336 if (is_opcode_valid (opcode
))
8338 seen_valid_for_isa
= TRUE
;
8339 if (is_size_valid (opcode
))
8341 bfd_boolean delay_slot_ok
;
8343 seen_valid_for_size
= TRUE
;
8344 delay_slot_ok
= is_delay_slot_valid (opcode
);
8345 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8346 lax_match
, delay_slot_ok
))
8350 if (!invalid_delay_slot
)
8351 invalid_delay_slot
= opcode
;
8360 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8362 /* If the only matches we found had the wrong length for the delay slot,
8363 pick the first such match. We'll issue an appropriate warning later. */
8364 if (invalid_delay_slot
)
8366 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8372 /* Handle the case where we didn't try to match an instruction because
8373 all the alternatives were incompatible with the current ISA. */
8374 if (!seen_valid_for_isa
)
8376 match_invalid_for_isa ();
8380 /* Handle the case where we didn't try to match an instruction because
8381 all the alternatives were of the wrong size. */
8382 if (!seen_valid_for_size
)
8384 if (mips_opts
.insn32
)
8385 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8388 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8389 8 * forced_insn_length
);
8396 /* Like match_insns, but for MIPS16. */
8399 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8400 struct mips_operand_token
*tokens
)
8402 const struct mips_opcode
*opcode
;
8403 bfd_boolean seen_valid_for_isa
;
8404 bfd_boolean seen_valid_for_size
;
8406 /* Search for a match, ignoring alternatives that don't satisfy the
8407 current ISA. There are no separate entries for extended forms so
8408 we deal with forced_length later. */
8409 seen_valid_for_isa
= FALSE
;
8410 seen_valid_for_size
= FALSE
;
8414 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8415 if (is_opcode_valid_16 (opcode
))
8417 seen_valid_for_isa
= TRUE
;
8418 if (is_size_valid_16 (opcode
))
8420 seen_valid_for_size
= TRUE
;
8421 if (match_mips16_insn (insn
, opcode
, tokens
))
8427 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8428 && strcmp (opcode
->name
, first
->name
) == 0);
8430 /* Handle the case where we didn't try to match an instruction because
8431 all the alternatives were incompatible with the current ISA. */
8432 if (!seen_valid_for_isa
)
8434 match_invalid_for_isa ();
8438 /* Handle the case where we didn't try to match an instruction because
8439 all the alternatives were of the wrong size. */
8440 if (!seen_valid_for_size
)
8442 if (forced_insn_length
== 2)
8444 (0, _("unrecognized unextended version of MIPS16 opcode"));
8447 (0, _("unrecognized extended version of MIPS16 opcode"));
8454 /* Set up global variables for the start of a new macro. */
8459 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8460 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8461 sizeof (mips_macro_warning
.first_insn_sizes
));
8462 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8463 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8464 && delayed_branch_p (&history
[0]));
8466 && history
[0].frag
->fr_type
== rs_machine_dependent
8467 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8468 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8469 mips_macro_warning
.delay_slot_length
= 0;
8471 switch (history
[0].insn_mo
->pinfo2
8472 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8474 case INSN2_BRANCH_DELAY_32BIT
:
8475 mips_macro_warning
.delay_slot_length
= 4;
8477 case INSN2_BRANCH_DELAY_16BIT
:
8478 mips_macro_warning
.delay_slot_length
= 2;
8481 mips_macro_warning
.delay_slot_length
= 0;
8484 mips_macro_warning
.first_frag
= NULL
;
8487 /* Given that a macro is longer than one instruction or of the wrong size,
8488 return the appropriate warning for it. Return null if no warning is
8489 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8490 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8491 and RELAX_NOMACRO. */
8494 macro_warning (relax_substateT subtype
)
8496 if (subtype
& RELAX_DELAY_SLOT
)
8497 return _("macro instruction expanded into multiple instructions"
8498 " in a branch delay slot");
8499 else if (subtype
& RELAX_NOMACRO
)
8500 return _("macro instruction expanded into multiple instructions");
8501 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8502 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8503 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8504 ? _("macro instruction expanded into a wrong size instruction"
8505 " in a 16-bit branch delay slot")
8506 : _("macro instruction expanded into a wrong size instruction"
8507 " in a 32-bit branch delay slot"));
8512 /* Finish up a macro. Emit warnings as appropriate. */
8517 /* Relaxation warning flags. */
8518 relax_substateT subtype
= 0;
8520 /* Check delay slot size requirements. */
8521 if (mips_macro_warning
.delay_slot_length
== 2)
8522 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8523 if (mips_macro_warning
.delay_slot_length
!= 0)
8525 if (mips_macro_warning
.delay_slot_length
8526 != mips_macro_warning
.first_insn_sizes
[0])
8527 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8528 if (mips_macro_warning
.delay_slot_length
8529 != mips_macro_warning
.first_insn_sizes
[1])
8530 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8533 /* Check instruction count requirements. */
8534 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8536 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8537 subtype
|= RELAX_SECOND_LONGER
;
8538 if (mips_opts
.warn_about_macros
)
8539 subtype
|= RELAX_NOMACRO
;
8540 if (mips_macro_warning
.delay_slot_p
)
8541 subtype
|= RELAX_DELAY_SLOT
;
8544 /* If both alternatives fail to fill a delay slot correctly,
8545 emit the warning now. */
8546 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8547 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8552 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8553 | RELAX_DELAY_SLOT_SIZE_FIRST
8554 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8555 msg
= macro_warning (s
);
8557 as_warn ("%s", msg
);
8561 /* If both implementations are longer than 1 instruction, then emit the
8563 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8568 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8569 msg
= macro_warning (s
);
8571 as_warn ("%s", msg
);
8575 /* If any flags still set, then one implementation might need a warning
8576 and the other either will need one of a different kind or none at all.
8577 Pass any remaining flags over to relaxation. */
8578 if (mips_macro_warning
.first_frag
!= NULL
)
8579 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8582 /* Instruction operand formats used in macros that vary between
8583 standard MIPS and microMIPS code. */
8585 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8586 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8587 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8588 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8589 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8590 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8591 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8592 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8594 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8595 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8596 : cop12_fmt[mips_opts.micromips])
8597 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8598 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8599 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8600 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8601 : mem12_fmt[mips_opts.micromips])
8602 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8603 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8604 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8606 /* Read a macro's relocation codes from *ARGS and store them in *R.
8607 The first argument in *ARGS will be either the code for a single
8608 relocation or -1 followed by the three codes that make up a
8609 composite relocation. */
8612 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8616 next
= va_arg (*args
, int);
8618 r
[0] = (bfd_reloc_code_real_type
) next
;
8621 for (i
= 0; i
< 3; i
++)
8622 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8623 /* This function is only used for 16-bit relocation fields.
8624 To make the macro code simpler, treat an unrelocated value
8625 in the same way as BFD_RELOC_LO16. */
8626 if (r
[0] == BFD_RELOC_UNUSED
)
8627 r
[0] = BFD_RELOC_LO16
;
8631 /* Build an instruction created by a macro expansion. This is passed
8632 a pointer to the count of instructions created so far, an
8633 expression, the name of the instruction to build, an operand format
8634 string, and corresponding arguments. */
8637 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8639 const struct mips_opcode
*mo
= NULL
;
8640 bfd_reloc_code_real_type r
[3];
8641 const struct mips_opcode
*amo
;
8642 const struct mips_operand
*operand
;
8643 struct hash_control
*hash
;
8644 struct mips_cl_insn insn
;
8648 va_start (args
, fmt
);
8650 if (mips_opts
.mips16
)
8652 mips16_macro_build (ep
, name
, fmt
, &args
);
8657 r
[0] = BFD_RELOC_UNUSED
;
8658 r
[1] = BFD_RELOC_UNUSED
;
8659 r
[2] = BFD_RELOC_UNUSED
;
8660 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8661 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8663 gas_assert (strcmp (name
, amo
->name
) == 0);
8667 /* Search until we get a match for NAME. It is assumed here that
8668 macros will never generate MDMX, MIPS-3D, or MT instructions.
8669 We try to match an instruction that fulfills the branch delay
8670 slot instruction length requirement (if any) of the previous
8671 instruction. While doing this we record the first instruction
8672 seen that matches all the other conditions and use it anyway
8673 if the requirement cannot be met; we will issue an appropriate
8674 warning later on. */
8675 if (strcmp (fmt
, amo
->args
) == 0
8676 && amo
->pinfo
!= INSN_MACRO
8677 && is_opcode_valid (amo
)
8678 && is_size_valid (amo
))
8680 if (is_delay_slot_valid (amo
))
8690 gas_assert (amo
->name
);
8692 while (strcmp (name
, amo
->name
) == 0);
8695 create_insn (&insn
, mo
);
8708 macro_read_relocs (&args
, r
);
8709 gas_assert (*r
== BFD_RELOC_GPREL16
8710 || *r
== BFD_RELOC_MIPS_HIGHER
8711 || *r
== BFD_RELOC_HI16_S
8712 || *r
== BFD_RELOC_LO16
8713 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8717 macro_read_relocs (&args
, r
);
8721 macro_read_relocs (&args
, r
);
8722 gas_assert (ep
!= NULL
8723 && (ep
->X_op
== O_constant
8724 || (ep
->X_op
== O_symbol
8725 && (*r
== BFD_RELOC_MIPS_HIGHEST
8726 || *r
== BFD_RELOC_HI16_S
8727 || *r
== BFD_RELOC_HI16
8728 || *r
== BFD_RELOC_GPREL16
8729 || *r
== BFD_RELOC_MIPS_GOT_HI16
8730 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8734 gas_assert (ep
!= NULL
);
8737 * This allows macro() to pass an immediate expression for
8738 * creating short branches without creating a symbol.
8740 * We don't allow branch relaxation for these branches, as
8741 * they should only appear in ".set nomacro" anyway.
8743 if (ep
->X_op
== O_constant
)
8745 /* For microMIPS we always use relocations for branches.
8746 So we should not resolve immediate values. */
8747 gas_assert (!mips_opts
.micromips
);
8749 if ((ep
->X_add_number
& 3) != 0)
8750 as_bad (_("branch to misaligned address (0x%lx)"),
8751 (unsigned long) ep
->X_add_number
);
8752 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8753 as_bad (_("branch address range overflow (0x%lx)"),
8754 (unsigned long) ep
->X_add_number
);
8755 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8759 *r
= BFD_RELOC_16_PCREL_S2
;
8763 gas_assert (ep
!= NULL
);
8764 *r
= BFD_RELOC_MIPS_JMP
;
8768 operand
= (mips_opts
.micromips
8769 ? decode_micromips_operand (fmt
)
8770 : decode_mips_operand (fmt
));
8774 uval
= va_arg (args
, int);
8775 if (operand
->type
== OP_CLO_CLZ_DEST
)
8776 uval
|= (uval
<< 5);
8777 insn_insert_operand (&insn
, operand
, uval
);
8779 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8785 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8787 append_insn (&insn
, ep
, r
, TRUE
);
8791 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8794 struct mips_opcode
*mo
;
8795 struct mips_cl_insn insn
;
8796 const struct mips_operand
*operand
;
8797 bfd_reloc_code_real_type r
[3]
8798 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8800 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8802 gas_assert (strcmp (name
, mo
->name
) == 0);
8804 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8807 gas_assert (mo
->name
);
8808 gas_assert (strcmp (name
, mo
->name
) == 0);
8811 create_insn (&insn
, mo
);
8848 gas_assert (ep
!= NULL
);
8850 if (ep
->X_op
!= O_constant
)
8851 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8852 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8854 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8856 *r
= BFD_RELOC_UNUSED
;
8862 operand
= decode_mips16_operand (c
, FALSE
);
8866 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8871 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8873 append_insn (&insn
, ep
, r
, TRUE
);
8877 * Generate a "jalr" instruction with a relocation hint to the called
8878 * function. This occurs in NewABI PIC code.
8881 macro_build_jalr (expressionS
*ep
, int cprestore
)
8883 static const bfd_reloc_code_real_type jalr_relocs
[2]
8884 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8885 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8889 if (MIPS_JALR_HINT_P (ep
))
8894 if (mips_opts
.micromips
)
8896 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8897 ? "jalr" : "jalrs");
8898 if (MIPS_JALR_HINT_P (ep
)
8900 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8901 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8903 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8906 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8907 if (MIPS_JALR_HINT_P (ep
))
8908 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8912 * Generate a "lui" instruction.
8915 macro_build_lui (expressionS
*ep
, int regnum
)
8917 gas_assert (! mips_opts
.mips16
);
8919 if (ep
->X_op
!= O_constant
)
8921 gas_assert (ep
->X_op
== O_symbol
);
8922 /* _gp_disp is a special case, used from s_cpload.
8923 __gnu_local_gp is used if mips_no_shared. */
8924 gas_assert (mips_pic
== NO_PIC
8926 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8927 || (! mips_in_shared
8928 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8929 "__gnu_local_gp") == 0));
8932 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8935 /* Generate a sequence of instructions to do a load or store from a constant
8936 offset off of a base register (breg) into/from a target register (treg),
8937 using AT if necessary. */
8939 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8940 int treg
, int breg
, int dbl
)
8942 gas_assert (ep
->X_op
== O_constant
);
8944 /* Sign-extending 32-bit constants makes their handling easier. */
8946 normalize_constant_expr (ep
);
8948 /* Right now, this routine can only handle signed 32-bit constants. */
8949 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8950 as_warn (_("operand overflow"));
8952 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8954 /* Signed 16-bit offset will fit in the op. Easy! */
8955 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8959 /* 32-bit offset, need multiple instructions and AT, like:
8960 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8961 addu $tempreg,$tempreg,$breg
8962 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8963 to handle the complete offset. */
8964 macro_build_lui (ep
, AT
);
8965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8966 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8969 as_bad (_("macro used $at after \".set noat\""));
8974 * Generates code to set the $at register to true (one)
8975 * if reg is less than the immediate expression.
8978 set_at (int reg
, int unsignedp
)
8980 if (imm_expr
.X_add_number
>= -0x8000
8981 && imm_expr
.X_add_number
< 0x8000)
8982 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8983 AT
, reg
, BFD_RELOC_LO16
);
8986 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8987 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8991 /* Count the leading zeroes by performing a binary chop. This is a
8992 bulky bit of source, but performance is a LOT better for the
8993 majority of values than a simple loop to count the bits:
8994 for (lcnt = 0; (lcnt < 32); lcnt++)
8995 if ((v) & (1 << (31 - lcnt)))
8997 However it is not code size friendly, and the gain will drop a bit
8998 on certain cached systems.
9000 #define COUNT_TOP_ZEROES(v) \
9001 (((v) & ~0xffff) == 0 \
9002 ? ((v) & ~0xff) == 0 \
9003 ? ((v) & ~0xf) == 0 \
9004 ? ((v) & ~0x3) == 0 \
9005 ? ((v) & ~0x1) == 0 \
9010 : ((v) & ~0x7) == 0 \
9013 : ((v) & ~0x3f) == 0 \
9014 ? ((v) & ~0x1f) == 0 \
9017 : ((v) & ~0x7f) == 0 \
9020 : ((v) & ~0xfff) == 0 \
9021 ? ((v) & ~0x3ff) == 0 \
9022 ? ((v) & ~0x1ff) == 0 \
9025 : ((v) & ~0x7ff) == 0 \
9028 : ((v) & ~0x3fff) == 0 \
9029 ? ((v) & ~0x1fff) == 0 \
9032 : ((v) & ~0x7fff) == 0 \
9035 : ((v) & ~0xffffff) == 0 \
9036 ? ((v) & ~0xfffff) == 0 \
9037 ? ((v) & ~0x3ffff) == 0 \
9038 ? ((v) & ~0x1ffff) == 0 \
9041 : ((v) & ~0x7ffff) == 0 \
9044 : ((v) & ~0x3fffff) == 0 \
9045 ? ((v) & ~0x1fffff) == 0 \
9048 : ((v) & ~0x7fffff) == 0 \
9051 : ((v) & ~0xfffffff) == 0 \
9052 ? ((v) & ~0x3ffffff) == 0 \
9053 ? ((v) & ~0x1ffffff) == 0 \
9056 : ((v) & ~0x7ffffff) == 0 \
9059 : ((v) & ~0x3fffffff) == 0 \
9060 ? ((v) & ~0x1fffffff) == 0 \
9063 : ((v) & ~0x7fffffff) == 0 \
9068 * This routine generates the least number of instructions necessary to load
9069 * an absolute expression value into a register.
9072 load_register (int reg
, expressionS
*ep
, int dbl
)
9075 expressionS hi32
, lo32
;
9077 if (ep
->X_op
!= O_big
)
9079 gas_assert (ep
->X_op
== O_constant
);
9081 /* Sign-extending 32-bit constants makes their handling easier. */
9083 normalize_constant_expr (ep
);
9085 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9087 /* We can handle 16 bit signed values with an addiu to
9088 $zero. No need to ever use daddiu here, since $zero and
9089 the result are always correct in 32 bit mode. */
9090 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9093 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9095 /* We can handle 16 bit unsigned values with an ori to
9097 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9100 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9102 /* 32 bit values require an lui. */
9103 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9104 if ((ep
->X_add_number
& 0xffff) != 0)
9105 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9110 /* The value is larger than 32 bits. */
9112 if (!dbl
|| GPR_SIZE
== 32)
9116 sprintf_vma (value
, ep
->X_add_number
);
9117 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9118 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9122 if (ep
->X_op
!= O_big
)
9125 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9126 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9127 hi32
.X_add_number
&= 0xffffffff;
9129 lo32
.X_add_number
&= 0xffffffff;
9133 gas_assert (ep
->X_add_number
> 2);
9134 if (ep
->X_add_number
== 3)
9135 generic_bignum
[3] = 0;
9136 else if (ep
->X_add_number
> 4)
9137 as_bad (_("number larger than 64 bits"));
9138 lo32
.X_op
= O_constant
;
9139 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9140 hi32
.X_op
= O_constant
;
9141 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9144 if (hi32
.X_add_number
== 0)
9149 unsigned long hi
, lo
;
9151 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9153 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9155 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9158 if (lo32
.X_add_number
& 0x80000000)
9160 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9161 if (lo32
.X_add_number
& 0xffff)
9162 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9167 /* Check for 16bit shifted constant. We know that hi32 is
9168 non-zero, so start the mask on the first bit of the hi32
9173 unsigned long himask
, lomask
;
9177 himask
= 0xffff >> (32 - shift
);
9178 lomask
= (0xffff << shift
) & 0xffffffff;
9182 himask
= 0xffff << (shift
- 32);
9185 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9186 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9190 tmp
.X_op
= O_constant
;
9192 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9193 | (lo32
.X_add_number
>> shift
));
9195 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9196 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9197 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9198 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9203 while (shift
<= (64 - 16));
9205 /* Find the bit number of the lowest one bit, and store the
9206 shifted value in hi/lo. */
9207 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9208 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9212 while ((lo
& 1) == 0)
9217 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9223 while ((hi
& 1) == 0)
9232 /* Optimize if the shifted value is a (power of 2) - 1. */
9233 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9234 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9236 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9241 /* This instruction will set the register to be all
9243 tmp
.X_op
= O_constant
;
9244 tmp
.X_add_number
= (offsetT
) -1;
9245 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9249 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9250 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9252 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9253 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9258 /* Sign extend hi32 before calling load_register, because we can
9259 generally get better code when we load a sign extended value. */
9260 if ((hi32
.X_add_number
& 0x80000000) != 0)
9261 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9262 load_register (reg
, &hi32
, 0);
9265 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9269 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9277 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9279 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9280 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9286 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9290 mid16
.X_add_number
>>= 16;
9291 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9292 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9295 if ((lo32
.X_add_number
& 0xffff) != 0)
9296 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9300 load_delay_nop (void)
9302 if (!gpr_interlocks
)
9303 macro_build (NULL
, "nop", "");
9306 /* Load an address into a register. */
9309 load_address (int reg
, expressionS
*ep
, int *used_at
)
9311 if (ep
->X_op
!= O_constant
9312 && ep
->X_op
!= O_symbol
)
9314 as_bad (_("expression too complex"));
9315 ep
->X_op
= O_constant
;
9318 if (ep
->X_op
== O_constant
)
9320 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9324 if (mips_pic
== NO_PIC
)
9326 /* If this is a reference to a GP relative symbol, we want
9327 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9329 lui $reg,<sym> (BFD_RELOC_HI16_S)
9330 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9331 If we have an addend, we always use the latter form.
9333 With 64bit address space and a usable $at we want
9334 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9335 lui $at,<sym> (BFD_RELOC_HI16_S)
9336 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9337 daddiu $at,<sym> (BFD_RELOC_LO16)
9341 If $at is already in use, we use a path which is suboptimal
9342 on superscalar processors.
9343 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9344 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9346 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9348 daddiu $reg,<sym> (BFD_RELOC_LO16)
9350 For GP relative symbols in 64bit address space we can use
9351 the same sequence as in 32bit address space. */
9352 if (HAVE_64BIT_SYMBOLS
)
9354 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9355 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9357 relax_start (ep
->X_add_symbol
);
9358 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9359 mips_gp_register
, BFD_RELOC_GPREL16
);
9363 if (*used_at
== 0 && mips_opts
.at
)
9365 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9366 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9367 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9368 BFD_RELOC_MIPS_HIGHER
);
9369 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9370 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9371 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9376 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9377 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9378 BFD_RELOC_MIPS_HIGHER
);
9379 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9380 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9381 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9382 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9385 if (mips_relax
.sequence
)
9390 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9391 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9393 relax_start (ep
->X_add_symbol
);
9394 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9395 mips_gp_register
, BFD_RELOC_GPREL16
);
9398 macro_build_lui (ep
, reg
);
9399 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9400 reg
, reg
, BFD_RELOC_LO16
);
9401 if (mips_relax
.sequence
)
9405 else if (!mips_big_got
)
9409 /* If this is a reference to an external symbol, we want
9410 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9412 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9414 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9415 If there is a constant, it must be added in after.
9417 If we have NewABI, we want
9418 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9419 unless we're referencing a global symbol with a non-zero
9420 offset, in which case cst must be added separately. */
9423 if (ep
->X_add_number
)
9425 ex
.X_add_number
= ep
->X_add_number
;
9426 ep
->X_add_number
= 0;
9427 relax_start (ep
->X_add_symbol
);
9428 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9429 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9430 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9431 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9432 ex
.X_op
= O_constant
;
9433 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9434 reg
, reg
, BFD_RELOC_LO16
);
9435 ep
->X_add_number
= ex
.X_add_number
;
9438 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9439 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9440 if (mips_relax
.sequence
)
9445 ex
.X_add_number
= ep
->X_add_number
;
9446 ep
->X_add_number
= 0;
9447 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9448 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9450 relax_start (ep
->X_add_symbol
);
9452 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9456 if (ex
.X_add_number
!= 0)
9458 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9459 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9460 ex
.X_op
= O_constant
;
9461 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9462 reg
, reg
, BFD_RELOC_LO16
);
9466 else if (mips_big_got
)
9470 /* This is the large GOT case. If this is a reference to an
9471 external symbol, we want
9472 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9474 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9476 Otherwise, for a reference to a local symbol in old ABI, we want
9477 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9479 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9480 If there is a constant, it must be added in after.
9482 In the NewABI, for local symbols, with or without offsets, we want:
9483 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9484 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9488 ex
.X_add_number
= ep
->X_add_number
;
9489 ep
->X_add_number
= 0;
9490 relax_start (ep
->X_add_symbol
);
9491 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9492 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9493 reg
, reg
, mips_gp_register
);
9494 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9495 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9496 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9497 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9498 else if (ex
.X_add_number
)
9500 ex
.X_op
= O_constant
;
9501 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9505 ep
->X_add_number
= ex
.X_add_number
;
9507 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9508 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9509 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9510 BFD_RELOC_MIPS_GOT_OFST
);
9515 ex
.X_add_number
= ep
->X_add_number
;
9516 ep
->X_add_number
= 0;
9517 relax_start (ep
->X_add_symbol
);
9518 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9519 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9520 reg
, reg
, mips_gp_register
);
9521 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9522 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9524 if (reg_needs_delay (mips_gp_register
))
9526 /* We need a nop before loading from $gp. This special
9527 check is required because the lui which starts the main
9528 instruction stream does not refer to $gp, and so will not
9529 insert the nop which may be required. */
9530 macro_build (NULL
, "nop", "");
9532 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9533 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9535 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9539 if (ex
.X_add_number
!= 0)
9541 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9542 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9543 ex
.X_op
= O_constant
;
9544 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9552 if (!mips_opts
.at
&& *used_at
== 1)
9553 as_bad (_("macro used $at after \".set noat\""));
9556 /* Move the contents of register SOURCE into register DEST. */
9559 move_register (int dest
, int source
)
9561 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9562 instruction specifically requires a 32-bit one. */
9563 if (mips_opts
.micromips
9564 && !mips_opts
.insn32
9565 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9566 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9568 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9571 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9572 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9573 The two alternatives are:
9575 Global symbol Local symbol
9576 ------------- ------------
9577 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9579 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9581 load_got_offset emits the first instruction and add_got_offset
9582 emits the second for a 16-bit offset or add_got_offset_hilo emits
9583 a sequence to add a 32-bit offset using a scratch register. */
9586 load_got_offset (int dest
, expressionS
*local
)
9591 global
.X_add_number
= 0;
9593 relax_start (local
->X_add_symbol
);
9594 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9595 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9597 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9598 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9603 add_got_offset (int dest
, expressionS
*local
)
9607 global
.X_op
= O_constant
;
9608 global
.X_op_symbol
= NULL
;
9609 global
.X_add_symbol
= NULL
;
9610 global
.X_add_number
= local
->X_add_number
;
9612 relax_start (local
->X_add_symbol
);
9613 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9614 dest
, dest
, BFD_RELOC_LO16
);
9616 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9621 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9624 int hold_mips_optimize
;
9626 global
.X_op
= O_constant
;
9627 global
.X_op_symbol
= NULL
;
9628 global
.X_add_symbol
= NULL
;
9629 global
.X_add_number
= local
->X_add_number
;
9631 relax_start (local
->X_add_symbol
);
9632 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9634 /* Set mips_optimize around the lui instruction to avoid
9635 inserting an unnecessary nop after the lw. */
9636 hold_mips_optimize
= mips_optimize
;
9638 macro_build_lui (&global
, tmp
);
9639 mips_optimize
= hold_mips_optimize
;
9640 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9643 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9646 /* Emit a sequence of instructions to emulate a branch likely operation.
9647 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9648 is its complementing branch with the original condition negated.
9649 CALL is set if the original branch specified the link operation.
9650 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9652 Code like this is produced in the noreorder mode:
9657 delay slot (executed only if branch taken)
9665 delay slot (executed only if branch taken)
9668 In the reorder mode the delay slot would be filled with a nop anyway,
9669 so code produced is simply:
9674 This function is used when producing code for the microMIPS ASE that
9675 does not implement branch likely instructions in hardware. */
9678 macro_build_branch_likely (const char *br
, const char *brneg
,
9679 int call
, expressionS
*ep
, const char *fmt
,
9680 unsigned int sreg
, unsigned int treg
)
9682 int noreorder
= mips_opts
.noreorder
;
9685 gas_assert (mips_opts
.micromips
);
9689 micromips_label_expr (&expr1
);
9690 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9691 macro_build (NULL
, "nop", "");
9692 macro_build (ep
, call
? "bal" : "b", "p");
9694 /* Set to true so that append_insn adds a label. */
9695 emit_branch_likely_macro
= TRUE
;
9699 macro_build (ep
, br
, fmt
, sreg
, treg
);
9700 macro_build (NULL
, "nop", "");
9705 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9706 the condition code tested. EP specifies the branch target. */
9709 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9736 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9739 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9740 the register tested. EP specifies the branch target. */
9743 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9745 const char *brneg
= NULL
;
9755 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9759 gas_assert (mips_opts
.micromips
);
9760 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9768 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9775 br
= mips_opts
.micromips
? "blez" : "blezl";
9782 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9786 gas_assert (mips_opts
.micromips
);
9787 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9794 if (mips_opts
.micromips
&& brneg
)
9795 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9797 macro_build (ep
, br
, "s,p", sreg
);
9800 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9801 TREG as the registers tested. EP specifies the branch target. */
9804 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9805 unsigned int sreg
, unsigned int treg
)
9807 const char *brneg
= NULL
;
9819 br
= mips_opts
.micromips
? "beq" : "beql";
9828 br
= mips_opts
.micromips
? "bne" : "bnel";
9834 if (mips_opts
.micromips
&& brneg
)
9835 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9837 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9840 /* Return the high part that should be loaded in order to make the low
9841 part of VALUE accessible using an offset of OFFBITS bits. */
9844 offset_high_part (offsetT value
, unsigned int offbits
)
9851 bias
= 1 << (offbits
- 1);
9852 low_mask
= bias
* 2 - 1;
9853 return (value
+ bias
) & ~low_mask
;
9856 /* Return true if the value stored in offset_expr and offset_reloc
9857 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9858 amount that the caller wants to add without inducing overflow
9859 and ALIGN is the known alignment of the value in bytes. */
9862 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9866 /* Accept any relocation operator if overflow isn't a concern. */
9867 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9870 /* These relocations are guaranteed not to overflow in correct links. */
9871 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9872 || gprel16_reloc_p (*offset_reloc
))
9875 if (offset_expr
.X_op
== O_constant
9876 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9877 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9884 * This routine implements the seemingly endless macro or synthesized
9885 * instructions and addressing modes in the mips assembly language. Many
9886 * of these macros are simple and are similar to each other. These could
9887 * probably be handled by some kind of table or grammar approach instead of
9888 * this verbose method. Others are not simple macros but are more like
9889 * optimizing code generation.
9890 * One interesting optimization is when several store macros appear
9891 * consecutively that would load AT with the upper half of the same address.
9892 * The ensuing load upper instructions are omitted. This implies some kind
9893 * of global optimization. We currently only optimize within a single macro.
9894 * For many of the load and store macros if the address is specified as a
9895 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9896 * first load register 'at' with zero and use it as the base register. The
9897 * mips assembler simply uses register $zero. Just one tiny optimization
9901 macro (struct mips_cl_insn
*ip
, char *str
)
9903 const struct mips_operand_array
*operands
;
9904 unsigned int breg
, i
;
9905 unsigned int tempreg
;
9908 expressionS label_expr
;
9923 bfd_boolean large_offset
;
9925 int hold_mips_optimize
;
9927 unsigned int op
[MAX_OPERANDS
];
9929 gas_assert (! mips_opts
.mips16
);
9931 operands
= insn_operands (ip
);
9932 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9933 if (operands
->operand
[i
])
9934 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9938 mask
= ip
->insn_mo
->mask
;
9940 label_expr
.X_op
= O_constant
;
9941 label_expr
.X_op_symbol
= NULL
;
9942 label_expr
.X_add_symbol
= NULL
;
9943 label_expr
.X_add_number
= 0;
9945 expr1
.X_op
= O_constant
;
9946 expr1
.X_op_symbol
= NULL
;
9947 expr1
.X_add_symbol
= NULL
;
9948 expr1
.X_add_number
= 1;
9965 if (mips_opts
.micromips
)
9966 micromips_label_expr (&label_expr
);
9968 label_expr
.X_add_number
= 8;
9969 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9971 macro_build (NULL
, "nop", "");
9973 move_register (op
[0], op
[1]);
9974 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9975 if (mips_opts
.micromips
)
9976 micromips_add_label ();
9993 if (!mips_opts
.micromips
)
9995 if (imm_expr
.X_add_number
>= -0x200
9996 && imm_expr
.X_add_number
< 0x200)
9998 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9999 (int) imm_expr
.X_add_number
);
10008 if (imm_expr
.X_add_number
>= -0x8000
10009 && imm_expr
.X_add_number
< 0x8000)
10011 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10016 load_register (AT
, &imm_expr
, dbl
);
10017 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10036 if (imm_expr
.X_add_number
>= 0
10037 && imm_expr
.X_add_number
< 0x10000)
10039 if (mask
!= M_NOR_I
)
10040 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10043 macro_build (&imm_expr
, "ori", "t,r,i",
10044 op
[0], op
[1], BFD_RELOC_LO16
);
10045 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10051 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10052 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10056 switch (imm_expr
.X_add_number
)
10059 macro_build (NULL
, "nop", "");
10062 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10066 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10067 (int) imm_expr
.X_add_number
);
10070 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10071 (unsigned long) imm_expr
.X_add_number
);
10080 gas_assert (mips_opts
.micromips
);
10081 macro_build_branch_ccl (mask
, &offset_expr
,
10082 EXTRACT_OPERAND (1, BCC
, *ip
));
10089 if (imm_expr
.X_add_number
== 0)
10095 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10097 /* Fall through. */
10100 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10105 /* Fall through. */
10108 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10109 else if (op
[0] == 0)
10110 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10114 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10115 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10116 &offset_expr
, AT
, ZERO
);
10126 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10131 /* Fall through. */
10133 /* Check for > max integer. */
10134 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10137 /* Result is always false. */
10139 macro_build (NULL
, "nop", "");
10141 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10144 ++imm_expr
.X_add_number
;
10148 if (mask
== M_BGEL_I
)
10150 if (imm_expr
.X_add_number
== 0)
10152 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10153 &offset_expr
, op
[0]);
10156 if (imm_expr
.X_add_number
== 1)
10158 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10159 &offset_expr
, op
[0]);
10162 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10165 /* result is always true */
10166 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10167 macro_build (&offset_expr
, "b", "p");
10172 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10173 &offset_expr
, AT
, ZERO
);
10178 /* Fall through. */
10182 else if (op
[0] == 0)
10183 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10184 &offset_expr
, ZERO
, op
[1]);
10188 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10189 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10190 &offset_expr
, AT
, ZERO
);
10196 /* Fall through. */
10200 && imm_expr
.X_add_number
== -1))
10202 ++imm_expr
.X_add_number
;
10206 if (mask
== M_BGEUL_I
)
10208 if (imm_expr
.X_add_number
== 0)
10210 else if (imm_expr
.X_add_number
== 1)
10211 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10212 &offset_expr
, op
[0], ZERO
);
10217 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10218 &offset_expr
, AT
, ZERO
);
10224 /* Fall through. */
10227 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10228 else if (op
[0] == 0)
10229 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10233 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10234 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10235 &offset_expr
, AT
, ZERO
);
10241 /* Fall through. */
10244 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10245 &offset_expr
, op
[0], ZERO
);
10246 else if (op
[0] == 0)
10251 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10252 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10253 &offset_expr
, AT
, ZERO
);
10259 /* Fall through. */
10262 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10263 else if (op
[0] == 0)
10264 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10268 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10269 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10270 &offset_expr
, AT
, ZERO
);
10276 /* Fall through. */
10278 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10280 ++imm_expr
.X_add_number
;
10284 if (mask
== M_BLTL_I
)
10286 if (imm_expr
.X_add_number
== 0)
10287 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10288 else if (imm_expr
.X_add_number
== 1)
10289 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10294 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10295 &offset_expr
, AT
, ZERO
);
10301 /* Fall through. */
10304 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10305 &offset_expr
, op
[0], ZERO
);
10306 else if (op
[0] == 0)
10311 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10312 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10313 &offset_expr
, AT
, ZERO
);
10319 /* Fall through. */
10323 && imm_expr
.X_add_number
== -1))
10325 ++imm_expr
.X_add_number
;
10329 if (mask
== M_BLTUL_I
)
10331 if (imm_expr
.X_add_number
== 0)
10333 else if (imm_expr
.X_add_number
== 1)
10334 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10335 &offset_expr
, op
[0], ZERO
);
10340 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10341 &offset_expr
, AT
, ZERO
);
10347 /* Fall through. */
10350 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10351 else if (op
[0] == 0)
10352 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10356 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10357 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10358 &offset_expr
, AT
, ZERO
);
10364 /* Fall through. */
10368 else if (op
[0] == 0)
10369 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10370 &offset_expr
, ZERO
, op
[1]);
10374 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10375 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10376 &offset_expr
, AT
, ZERO
);
10382 /* Fall through. */
10388 /* Fall through. */
10394 as_warn (_("divide by zero"));
10396 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10398 macro_build (NULL
, "break", BRK_FMT
, 7);
10402 start_noreorder ();
10405 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10406 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10410 if (mips_opts
.micromips
)
10411 micromips_label_expr (&label_expr
);
10413 label_expr
.X_add_number
= 8;
10414 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10415 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10416 macro_build (NULL
, "break", BRK_FMT
, 7);
10417 if (mips_opts
.micromips
)
10418 micromips_add_label ();
10420 expr1
.X_add_number
= -1;
10422 load_register (AT
, &expr1
, dbl
);
10423 if (mips_opts
.micromips
)
10424 micromips_label_expr (&label_expr
);
10426 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10427 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10430 expr1
.X_add_number
= 1;
10431 load_register (AT
, &expr1
, dbl
);
10432 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10436 expr1
.X_add_number
= 0x80000000;
10437 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10441 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10442 /* We want to close the noreorder block as soon as possible, so
10443 that later insns are available for delay slot filling. */
10448 if (mips_opts
.micromips
)
10449 micromips_label_expr (&label_expr
);
10451 label_expr
.X_add_number
= 8;
10452 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10453 macro_build (NULL
, "nop", "");
10455 /* We want to close the noreorder block as soon as possible, so
10456 that later insns are available for delay slot filling. */
10459 macro_build (NULL
, "break", BRK_FMT
, 6);
10461 if (mips_opts
.micromips
)
10462 micromips_add_label ();
10463 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10502 if (imm_expr
.X_add_number
== 0)
10504 as_warn (_("divide by zero"));
10506 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10508 macro_build (NULL
, "break", BRK_FMT
, 7);
10511 if (imm_expr
.X_add_number
== 1)
10513 if (strcmp (s2
, "mflo") == 0)
10514 move_register (op
[0], op
[1]);
10516 move_register (op
[0], ZERO
);
10519 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10521 if (strcmp (s2
, "mflo") == 0)
10522 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10524 move_register (op
[0], ZERO
);
10529 load_register (AT
, &imm_expr
, dbl
);
10530 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10531 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10550 start_noreorder ();
10553 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10554 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10555 /* We want to close the noreorder block as soon as possible, so
10556 that later insns are available for delay slot filling. */
10561 if (mips_opts
.micromips
)
10562 micromips_label_expr (&label_expr
);
10564 label_expr
.X_add_number
= 8;
10565 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10566 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10568 /* We want to close the noreorder block as soon as possible, so
10569 that later insns are available for delay slot filling. */
10571 macro_build (NULL
, "break", BRK_FMT
, 7);
10572 if (mips_opts
.micromips
)
10573 micromips_add_label ();
10575 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10580 /* Fall through. */
10586 /* Fall through. */
10589 /* Load the address of a symbol into a register. If breg is not
10590 zero, we then add a base register to it. */
10593 if (dbl
&& GPR_SIZE
== 32)
10594 as_warn (_("dla used to load 32-bit register; recommend using la "
10597 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10598 as_warn (_("la used to load 64-bit address; recommend using dla "
10601 if (small_offset_p (0, align
, 16))
10603 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10604 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10608 if (mips_opts
.at
&& (op
[0] == breg
))
10616 if (offset_expr
.X_op
!= O_symbol
10617 && offset_expr
.X_op
!= O_constant
)
10619 as_bad (_("expression too complex"));
10620 offset_expr
.X_op
= O_constant
;
10623 if (offset_expr
.X_op
== O_constant
)
10624 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10625 else if (mips_pic
== NO_PIC
)
10627 /* If this is a reference to a GP relative symbol, we want
10628 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10630 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10631 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10632 If we have a constant, we need two instructions anyhow,
10633 so we may as well always use the latter form.
10635 With 64bit address space and a usable $at we want
10636 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10637 lui $at,<sym> (BFD_RELOC_HI16_S)
10638 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10639 daddiu $at,<sym> (BFD_RELOC_LO16)
10641 daddu $tempreg,$tempreg,$at
10643 If $at is already in use, we use a path which is suboptimal
10644 on superscalar processors.
10645 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10646 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10648 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10650 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10652 For GP relative symbols in 64bit address space we can use
10653 the same sequence as in 32bit address space. */
10654 if (HAVE_64BIT_SYMBOLS
)
10656 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10657 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10659 relax_start (offset_expr
.X_add_symbol
);
10660 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10661 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10665 if (used_at
== 0 && mips_opts
.at
)
10667 macro_build (&offset_expr
, "lui", LUI_FMT
,
10668 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10669 macro_build (&offset_expr
, "lui", LUI_FMT
,
10670 AT
, BFD_RELOC_HI16_S
);
10671 macro_build (&offset_expr
, "daddiu", "t,r,j",
10672 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10673 macro_build (&offset_expr
, "daddiu", "t,r,j",
10674 AT
, AT
, BFD_RELOC_LO16
);
10675 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10676 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10681 macro_build (&offset_expr
, "lui", LUI_FMT
,
10682 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10683 macro_build (&offset_expr
, "daddiu", "t,r,j",
10684 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10685 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10686 macro_build (&offset_expr
, "daddiu", "t,r,j",
10687 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10688 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10689 macro_build (&offset_expr
, "daddiu", "t,r,j",
10690 tempreg
, tempreg
, BFD_RELOC_LO16
);
10693 if (mips_relax
.sequence
)
10698 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10699 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10701 relax_start (offset_expr
.X_add_symbol
);
10702 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10703 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10706 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10707 as_bad (_("offset too large"));
10708 macro_build_lui (&offset_expr
, tempreg
);
10709 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10710 tempreg
, tempreg
, BFD_RELOC_LO16
);
10711 if (mips_relax
.sequence
)
10715 else if (!mips_big_got
&& !HAVE_NEWABI
)
10717 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10719 /* If this is a reference to an external symbol, and there
10720 is no constant, we want
10721 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10722 or for lca or if tempreg is PIC_CALL_REG
10723 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10724 For a local symbol, we want
10725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10727 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10729 If we have a small constant, and this is a reference to
10730 an external symbol, we want
10731 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10733 addiu $tempreg,$tempreg,<constant>
10734 For a local symbol, we want the same instruction
10735 sequence, but we output a BFD_RELOC_LO16 reloc on the
10738 If we have a large constant, and this is a reference to
10739 an external symbol, we want
10740 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10741 lui $at,<hiconstant>
10742 addiu $at,$at,<loconstant>
10743 addu $tempreg,$tempreg,$at
10744 For a local symbol, we want the same instruction
10745 sequence, but we output a BFD_RELOC_LO16 reloc on the
10749 if (offset_expr
.X_add_number
== 0)
10751 if (mips_pic
== SVR4_PIC
10753 && (call
|| tempreg
== PIC_CALL_REG
))
10754 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10756 relax_start (offset_expr
.X_add_symbol
);
10757 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10758 lw_reloc_type
, mips_gp_register
);
10761 /* We're going to put in an addu instruction using
10762 tempreg, so we may as well insert the nop right
10767 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10768 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10770 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10771 tempreg
, tempreg
, BFD_RELOC_LO16
);
10773 /* FIXME: If breg == 0, and the next instruction uses
10774 $tempreg, then if this variant case is used an extra
10775 nop will be generated. */
10777 else if (offset_expr
.X_add_number
>= -0x8000
10778 && offset_expr
.X_add_number
< 0x8000)
10780 load_got_offset (tempreg
, &offset_expr
);
10782 add_got_offset (tempreg
, &offset_expr
);
10786 expr1
.X_add_number
= offset_expr
.X_add_number
;
10787 offset_expr
.X_add_number
=
10788 SEXT_16BIT (offset_expr
.X_add_number
);
10789 load_got_offset (tempreg
, &offset_expr
);
10790 offset_expr
.X_add_number
= expr1
.X_add_number
;
10791 /* If we are going to add in a base register, and the
10792 target register and the base register are the same,
10793 then we are using AT as a temporary register. Since
10794 we want to load the constant into AT, we add our
10795 current AT (from the global offset table) and the
10796 register into the register now, and pretend we were
10797 not using a base register. */
10801 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10806 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10810 else if (!mips_big_got
&& HAVE_NEWABI
)
10812 int add_breg_early
= 0;
10814 /* If this is a reference to an external, and there is no
10815 constant, or local symbol (*), with or without a
10817 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10818 or for lca or if tempreg is PIC_CALL_REG
10819 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10821 If we have a small constant, and this is a reference to
10822 an external symbol, we want
10823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10824 addiu $tempreg,$tempreg,<constant>
10826 If we have a large constant, and this is a reference to
10827 an external symbol, we want
10828 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10829 lui $at,<hiconstant>
10830 addiu $at,$at,<loconstant>
10831 addu $tempreg,$tempreg,$at
10833 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10834 local symbols, even though it introduces an additional
10837 if (offset_expr
.X_add_number
)
10839 expr1
.X_add_number
= offset_expr
.X_add_number
;
10840 offset_expr
.X_add_number
= 0;
10842 relax_start (offset_expr
.X_add_symbol
);
10843 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10844 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10846 if (expr1
.X_add_number
>= -0x8000
10847 && expr1
.X_add_number
< 0x8000)
10849 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10850 tempreg
, tempreg
, BFD_RELOC_LO16
);
10852 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10856 /* If we are going to add in a base register, and the
10857 target register and the base register are the same,
10858 then we are using AT as a temporary register. Since
10859 we want to load the constant into AT, we add our
10860 current AT (from the global offset table) and the
10861 register into the register now, and pretend we were
10862 not using a base register. */
10867 gas_assert (tempreg
== AT
);
10868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10871 add_breg_early
= 1;
10874 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10881 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10884 offset_expr
.X_add_number
= expr1
.X_add_number
;
10886 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10887 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10888 if (add_breg_early
)
10890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10891 op
[0], tempreg
, breg
);
10897 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10899 relax_start (offset_expr
.X_add_symbol
);
10900 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10901 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10903 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10904 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10909 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10910 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10913 else if (mips_big_got
&& !HAVE_NEWABI
)
10916 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10917 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10918 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10920 /* This is the large GOT case. If this is a reference to an
10921 external symbol, and there is no constant, we want
10922 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10923 addu $tempreg,$tempreg,$gp
10924 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10925 or for lca or if tempreg is PIC_CALL_REG
10926 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10927 addu $tempreg,$tempreg,$gp
10928 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10929 For a local symbol, we want
10930 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10932 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10934 If we have a small constant, and this is a reference to
10935 an external symbol, we want
10936 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10937 addu $tempreg,$tempreg,$gp
10938 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10940 addiu $tempreg,$tempreg,<constant>
10941 For a local symbol, we want
10942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10944 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10946 If we have a large constant, and this is a reference to
10947 an external symbol, we want
10948 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10949 addu $tempreg,$tempreg,$gp
10950 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10951 lui $at,<hiconstant>
10952 addiu $at,$at,<loconstant>
10953 addu $tempreg,$tempreg,$at
10954 For a local symbol, we want
10955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10956 lui $at,<hiconstant>
10957 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10958 addu $tempreg,$tempreg,$at
10961 expr1
.X_add_number
= offset_expr
.X_add_number
;
10962 offset_expr
.X_add_number
= 0;
10963 relax_start (offset_expr
.X_add_symbol
);
10964 gpdelay
= reg_needs_delay (mips_gp_register
);
10965 if (expr1
.X_add_number
== 0 && breg
== 0
10966 && (call
|| tempreg
== PIC_CALL_REG
))
10968 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10969 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10971 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10972 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10973 tempreg
, tempreg
, mips_gp_register
);
10974 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10975 tempreg
, lw_reloc_type
, tempreg
);
10976 if (expr1
.X_add_number
== 0)
10980 /* We're going to put in an addu instruction using
10981 tempreg, so we may as well insert the nop right
10986 else if (expr1
.X_add_number
>= -0x8000
10987 && expr1
.X_add_number
< 0x8000)
10990 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10991 tempreg
, tempreg
, BFD_RELOC_LO16
);
10997 /* If we are going to add in a base register, and the
10998 target register and the base register are the same,
10999 then we are using AT as a temporary register. Since
11000 we want to load the constant into AT, we add our
11001 current AT (from the global offset table) and the
11002 register into the register now, and pretend we were
11003 not using a base register. */
11008 gas_assert (tempreg
== AT
);
11010 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11015 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11020 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11025 /* This is needed because this instruction uses $gp, but
11026 the first instruction on the main stream does not. */
11027 macro_build (NULL
, "nop", "");
11030 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11031 local_reloc_type
, mips_gp_register
);
11032 if (expr1
.X_add_number
>= -0x8000
11033 && expr1
.X_add_number
< 0x8000)
11036 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11037 tempreg
, tempreg
, BFD_RELOC_LO16
);
11038 /* FIXME: If add_number is 0, and there was no base
11039 register, the external symbol case ended with a load,
11040 so if the symbol turns out to not be external, and
11041 the next instruction uses tempreg, an unnecessary nop
11042 will be inserted. */
11048 /* We must add in the base register now, as in the
11049 external symbol case. */
11050 gas_assert (tempreg
== AT
);
11052 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11055 /* We set breg to 0 because we have arranged to add
11056 it in in both cases. */
11060 macro_build_lui (&expr1
, AT
);
11061 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11062 AT
, AT
, BFD_RELOC_LO16
);
11063 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11064 tempreg
, tempreg
, AT
);
11069 else if (mips_big_got
&& HAVE_NEWABI
)
11071 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11072 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11073 int add_breg_early
= 0;
11075 /* This is the large GOT case. If this is a reference to an
11076 external symbol, and there is no constant, we want
11077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11078 add $tempreg,$tempreg,$gp
11079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11080 or for lca or if tempreg is PIC_CALL_REG
11081 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11082 add $tempreg,$tempreg,$gp
11083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11085 If we have a small constant, and this is a reference to
11086 an external symbol, we want
11087 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11088 add $tempreg,$tempreg,$gp
11089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11090 addi $tempreg,$tempreg,<constant>
11092 If we have a large constant, and this is a reference to
11093 an external symbol, we want
11094 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11095 addu $tempreg,$tempreg,$gp
11096 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11097 lui $at,<hiconstant>
11098 addi $at,$at,<loconstant>
11099 add $tempreg,$tempreg,$at
11101 If we have NewABI, and we know it's a local symbol, we want
11102 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11103 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11104 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11106 relax_start (offset_expr
.X_add_symbol
);
11108 expr1
.X_add_number
= offset_expr
.X_add_number
;
11109 offset_expr
.X_add_number
= 0;
11111 if (expr1
.X_add_number
== 0 && breg
== 0
11112 && (call
|| tempreg
== PIC_CALL_REG
))
11114 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11115 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11117 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11119 tempreg
, tempreg
, mips_gp_register
);
11120 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11121 tempreg
, lw_reloc_type
, tempreg
);
11123 if (expr1
.X_add_number
== 0)
11125 else if (expr1
.X_add_number
>= -0x8000
11126 && expr1
.X_add_number
< 0x8000)
11128 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11129 tempreg
, tempreg
, BFD_RELOC_LO16
);
11131 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11135 /* If we are going to add in a base register, and the
11136 target register and the base register are the same,
11137 then we are using AT as a temporary register. Since
11138 we want to load the constant into AT, we add our
11139 current AT (from the global offset table) and the
11140 register into the register now, and pretend we were
11141 not using a base register. */
11146 gas_assert (tempreg
== AT
);
11147 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11150 add_breg_early
= 1;
11153 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11159 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11162 offset_expr
.X_add_number
= expr1
.X_add_number
;
11163 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11164 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11165 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11166 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11167 if (add_breg_early
)
11169 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11170 op
[0], tempreg
, breg
);
11180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11184 gas_assert (!mips_opts
.micromips
);
11185 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11189 gas_assert (!mips_opts
.micromips
);
11190 macro_build (NULL
, "c2", "C", 0x02);
11194 gas_assert (!mips_opts
.micromips
);
11195 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11199 gas_assert (!mips_opts
.micromips
);
11200 macro_build (NULL
, "c2", "C", 3);
11204 gas_assert (!mips_opts
.micromips
);
11205 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11209 /* The j instruction may not be used in PIC code, since it
11210 requires an absolute address. We convert it to a b
11212 if (mips_pic
== NO_PIC
)
11213 macro_build (&offset_expr
, "j", "a");
11215 macro_build (&offset_expr
, "b", "p");
11218 /* The jal instructions must be handled as macros because when
11219 generating PIC code they expand to multi-instruction
11220 sequences. Normally they are simple instructions. */
11224 /* Fall through. */
11226 gas_assert (mips_opts
.micromips
);
11227 if (mips_opts
.insn32
)
11229 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11237 /* Fall through. */
11240 if (mips_pic
== NO_PIC
)
11242 s
= jals
? "jalrs" : "jalr";
11243 if (mips_opts
.micromips
11244 && !mips_opts
.insn32
11246 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11247 macro_build (NULL
, s
, "mj", op
[1]);
11249 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11253 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11254 && mips_cprestore_offset
>= 0);
11256 if (op
[1] != PIC_CALL_REG
)
11257 as_warn (_("MIPS PIC call to register other than $25"));
11259 s
= ((mips_opts
.micromips
11260 && !mips_opts
.insn32
11261 && (!mips_opts
.noreorder
|| cprestore
))
11262 ? "jalrs" : "jalr");
11263 if (mips_opts
.micromips
11264 && !mips_opts
.insn32
11266 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11267 macro_build (NULL
, s
, "mj", op
[1]);
11269 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11270 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11272 if (mips_cprestore_offset
< 0)
11273 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11276 if (!mips_frame_reg_valid
)
11278 as_warn (_("no .frame pseudo-op used in PIC code"));
11279 /* Quiet this warning. */
11280 mips_frame_reg_valid
= 1;
11282 if (!mips_cprestore_valid
)
11284 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11285 /* Quiet this warning. */
11286 mips_cprestore_valid
= 1;
11288 if (mips_opts
.noreorder
)
11289 macro_build (NULL
, "nop", "");
11290 expr1
.X_add_number
= mips_cprestore_offset
;
11291 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11294 HAVE_64BIT_ADDRESSES
);
11302 gas_assert (mips_opts
.micromips
);
11303 if (mips_opts
.insn32
)
11305 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11309 /* Fall through. */
11311 if (mips_pic
== NO_PIC
)
11312 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11313 else if (mips_pic
== SVR4_PIC
)
11315 /* If this is a reference to an external symbol, and we are
11316 using a small GOT, we want
11317 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11321 lw $gp,cprestore($sp)
11322 The cprestore value is set using the .cprestore
11323 pseudo-op. If we are using a big GOT, we want
11324 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11326 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11330 lw $gp,cprestore($sp)
11331 If the symbol is not external, we want
11332 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11334 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11337 lw $gp,cprestore($sp)
11339 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11340 sequences above, minus nops, unless the symbol is local,
11341 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11347 relax_start (offset_expr
.X_add_symbol
);
11348 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11349 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11352 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11353 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11359 relax_start (offset_expr
.X_add_symbol
);
11360 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11361 BFD_RELOC_MIPS_CALL_HI16
);
11362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11363 PIC_CALL_REG
, mips_gp_register
);
11364 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11365 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11368 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11369 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11371 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11372 PIC_CALL_REG
, PIC_CALL_REG
,
11373 BFD_RELOC_MIPS_GOT_OFST
);
11377 macro_build_jalr (&offset_expr
, 0);
11381 relax_start (offset_expr
.X_add_symbol
);
11384 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11385 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11394 gpdelay
= reg_needs_delay (mips_gp_register
);
11395 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11396 BFD_RELOC_MIPS_CALL_HI16
);
11397 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11398 PIC_CALL_REG
, mips_gp_register
);
11399 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11400 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11405 macro_build (NULL
, "nop", "");
11407 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11408 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11411 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11412 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11414 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11416 if (mips_cprestore_offset
< 0)
11417 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11420 if (!mips_frame_reg_valid
)
11422 as_warn (_("no .frame pseudo-op used in PIC code"));
11423 /* Quiet this warning. */
11424 mips_frame_reg_valid
= 1;
11426 if (!mips_cprestore_valid
)
11428 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11429 /* Quiet this warning. */
11430 mips_cprestore_valid
= 1;
11432 if (mips_opts
.noreorder
)
11433 macro_build (NULL
, "nop", "");
11434 expr1
.X_add_number
= mips_cprestore_offset
;
11435 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11438 HAVE_64BIT_ADDRESSES
);
11442 else if (mips_pic
== VXWORKS_PIC
)
11443 as_bad (_("non-PIC jump used in PIC library"));
11550 gas_assert (!mips_opts
.micromips
);
11553 /* Itbl support may require additional care here. */
11559 /* Itbl support may require additional care here. */
11565 offbits
= (mips_opts
.micromips
? 12
11566 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11568 /* Itbl support may require additional care here. */
11572 gas_assert (!mips_opts
.micromips
);
11575 /* Itbl support may require additional care here. */
11581 offbits
= (mips_opts
.micromips
? 12 : 16);
11586 offbits
= (mips_opts
.micromips
? 12 : 16);
11591 /* Itbl support may require additional care here. */
11597 offbits
= (mips_opts
.micromips
? 12
11598 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11600 /* Itbl support may require additional care here. */
11606 /* Itbl support may require additional care here. */
11612 /* Itbl support may require additional care here. */
11618 offbits
= (mips_opts
.micromips
? 12 : 16);
11623 offbits
= (mips_opts
.micromips
? 12 : 16);
11628 offbits
= (mips_opts
.micromips
? 12
11629 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11635 offbits
= (mips_opts
.micromips
? 12
11636 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11642 offbits
= (mips_opts
.micromips
? 12 : 16);
11645 gas_assert (mips_opts
.micromips
);
11652 gas_assert (mips_opts
.micromips
);
11659 gas_assert (mips_opts
.micromips
);
11665 gas_assert (mips_opts
.micromips
);
11672 /* We don't want to use $0 as tempreg. */
11673 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11676 tempreg
= op
[0] + lp
;
11692 gas_assert (!mips_opts
.micromips
);
11695 /* Itbl support may require additional care here. */
11701 /* Itbl support may require additional care here. */
11707 offbits
= (mips_opts
.micromips
? 12
11708 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11710 /* Itbl support may require additional care here. */
11714 gas_assert (!mips_opts
.micromips
);
11717 /* Itbl support may require additional care here. */
11723 offbits
= (mips_opts
.micromips
? 12 : 16);
11728 offbits
= (mips_opts
.micromips
? 12 : 16);
11733 offbits
= (mips_opts
.micromips
? 12
11734 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11740 offbits
= (mips_opts
.micromips
? 12
11741 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11746 fmt
= (mips_opts
.micromips
? "k,~(b)"
11747 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11749 offbits
= (mips_opts
.micromips
? 12
11750 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11760 fmt
= (mips_opts
.micromips
? "k,~(b)"
11761 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11763 offbits
= (mips_opts
.micromips
? 12
11764 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11776 /* Itbl support may require additional care here. */
11781 offbits
= (mips_opts
.micromips
? 12
11782 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11784 /* Itbl support may require additional care here. */
11790 /* Itbl support may require additional care here. */
11794 gas_assert (!mips_opts
.micromips
);
11797 /* Itbl support may require additional care here. */
11803 offbits
= (mips_opts
.micromips
? 12 : 16);
11808 offbits
= (mips_opts
.micromips
? 12 : 16);
11811 gas_assert (mips_opts
.micromips
);
11817 gas_assert (mips_opts
.micromips
);
11823 gas_assert (mips_opts
.micromips
);
11829 gas_assert (mips_opts
.micromips
);
11838 if (small_offset_p (0, align
, 16))
11840 /* The first case exists for M_LD_AB and M_SD_AB, which are
11841 macros for o32 but which should act like normal instructions
11844 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11845 offset_reloc
[1], offset_reloc
[2], breg
);
11846 else if (small_offset_p (0, align
, offbits
))
11849 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11851 macro_build (NULL
, s
, fmt
, op
[0],
11852 (int) offset_expr
.X_add_number
, breg
);
11858 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11859 tempreg
, breg
, -1, offset_reloc
[0],
11860 offset_reloc
[1], offset_reloc
[2]);
11862 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11864 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11872 if (offset_expr
.X_op
!= O_constant
11873 && offset_expr
.X_op
!= O_symbol
)
11875 as_bad (_("expression too complex"));
11876 offset_expr
.X_op
= O_constant
;
11879 if (HAVE_32BIT_ADDRESSES
11880 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11884 sprintf_vma (value
, offset_expr
.X_add_number
);
11885 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11888 /* A constant expression in PIC code can be handled just as it
11889 is in non PIC code. */
11890 if (offset_expr
.X_op
== O_constant
)
11892 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11893 offbits
== 0 ? 16 : offbits
);
11894 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11896 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11898 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11899 tempreg
, tempreg
, breg
);
11902 if (offset_expr
.X_add_number
!= 0)
11903 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11904 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11905 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11907 else if (offbits
== 16)
11908 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11910 macro_build (NULL
, s
, fmt
, op
[0],
11911 (int) offset_expr
.X_add_number
, tempreg
);
11913 else if (offbits
!= 16)
11915 /* The offset field is too narrow to be used for a low-part
11916 relocation, so load the whole address into the auxiliary
11918 load_address (tempreg
, &offset_expr
, &used_at
);
11920 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11921 tempreg
, tempreg
, breg
);
11923 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11925 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11927 else if (mips_pic
== NO_PIC
)
11929 /* If this is a reference to a GP relative symbol, and there
11930 is no base register, we want
11931 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11932 Otherwise, if there is no base register, we want
11933 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11934 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11935 If we have a constant, we need two instructions anyhow,
11936 so we always use the latter form.
11938 If we have a base register, and this is a reference to a
11939 GP relative symbol, we want
11940 addu $tempreg,$breg,$gp
11941 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11943 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11944 addu $tempreg,$tempreg,$breg
11945 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11946 With a constant we always use the latter case.
11948 With 64bit address space and no base register and $at usable,
11950 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11951 lui $at,<sym> (BFD_RELOC_HI16_S)
11952 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11955 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11956 If we have a base register, we want
11957 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11958 lui $at,<sym> (BFD_RELOC_HI16_S)
11959 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11963 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11965 Without $at we can't generate the optimal path for superscalar
11966 processors here since this would require two temporary registers.
11967 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11968 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11970 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11972 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11973 If we have a base register, we want
11974 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11975 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11977 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11979 daddu $tempreg,$tempreg,$breg
11980 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11982 For GP relative symbols in 64bit address space we can use
11983 the same sequence as in 32bit address space. */
11984 if (HAVE_64BIT_SYMBOLS
)
11986 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11987 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11989 relax_start (offset_expr
.X_add_symbol
);
11992 macro_build (&offset_expr
, s
, fmt
, op
[0],
11993 BFD_RELOC_GPREL16
, mips_gp_register
);
11997 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11998 tempreg
, breg
, mips_gp_register
);
11999 macro_build (&offset_expr
, s
, fmt
, op
[0],
12000 BFD_RELOC_GPREL16
, tempreg
);
12005 if (used_at
== 0 && mips_opts
.at
)
12007 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12008 BFD_RELOC_MIPS_HIGHEST
);
12009 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12011 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12012 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12014 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12015 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12016 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12017 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12023 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12024 BFD_RELOC_MIPS_HIGHEST
);
12025 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12026 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12027 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12028 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12029 tempreg
, BFD_RELOC_HI16_S
);
12030 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12032 macro_build (NULL
, "daddu", "d,v,t",
12033 tempreg
, tempreg
, breg
);
12034 macro_build (&offset_expr
, s
, fmt
, op
[0],
12035 BFD_RELOC_LO16
, tempreg
);
12038 if (mips_relax
.sequence
)
12045 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12046 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12048 relax_start (offset_expr
.X_add_symbol
);
12049 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12053 macro_build_lui (&offset_expr
, tempreg
);
12054 macro_build (&offset_expr
, s
, fmt
, op
[0],
12055 BFD_RELOC_LO16
, tempreg
);
12056 if (mips_relax
.sequence
)
12061 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12062 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12064 relax_start (offset_expr
.X_add_symbol
);
12065 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12066 tempreg
, breg
, mips_gp_register
);
12067 macro_build (&offset_expr
, s
, fmt
, op
[0],
12068 BFD_RELOC_GPREL16
, tempreg
);
12071 macro_build_lui (&offset_expr
, tempreg
);
12072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12073 tempreg
, tempreg
, breg
);
12074 macro_build (&offset_expr
, s
, fmt
, op
[0],
12075 BFD_RELOC_LO16
, tempreg
);
12076 if (mips_relax
.sequence
)
12080 else if (!mips_big_got
)
12082 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12084 /* If this is a reference to an external symbol, we want
12085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12087 <op> op[0],0($tempreg)
12089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12091 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12092 <op> op[0],0($tempreg)
12094 For NewABI, we want
12095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12096 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12098 If there is a base register, we add it to $tempreg before
12099 the <op>. If there is a constant, we stick it in the
12100 <op> instruction. We don't handle constants larger than
12101 16 bits, because we have no way to load the upper 16 bits
12102 (actually, we could handle them for the subset of cases
12103 in which we are not using $at). */
12104 gas_assert (offset_expr
.X_op
== O_symbol
);
12107 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12108 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12111 tempreg
, tempreg
, breg
);
12112 macro_build (&offset_expr
, s
, fmt
, op
[0],
12113 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12116 expr1
.X_add_number
= offset_expr
.X_add_number
;
12117 offset_expr
.X_add_number
= 0;
12118 if (expr1
.X_add_number
< -0x8000
12119 || expr1
.X_add_number
>= 0x8000)
12120 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12122 lw_reloc_type
, mips_gp_register
);
12124 relax_start (offset_expr
.X_add_symbol
);
12126 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12127 tempreg
, BFD_RELOC_LO16
);
12130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12131 tempreg
, tempreg
, breg
);
12132 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12134 else if (mips_big_got
&& !HAVE_NEWABI
)
12138 /* If this is a reference to an external symbol, we want
12139 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12140 addu $tempreg,$tempreg,$gp
12141 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12142 <op> op[0],0($tempreg)
12144 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12146 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12147 <op> op[0],0($tempreg)
12148 If there is a base register, we add it to $tempreg before
12149 the <op>. If there is a constant, we stick it in the
12150 <op> instruction. We don't handle constants larger than
12151 16 bits, because we have no way to load the upper 16 bits
12152 (actually, we could handle them for the subset of cases
12153 in which we are not using $at). */
12154 gas_assert (offset_expr
.X_op
== O_symbol
);
12155 expr1
.X_add_number
= offset_expr
.X_add_number
;
12156 offset_expr
.X_add_number
= 0;
12157 if (expr1
.X_add_number
< -0x8000
12158 || expr1
.X_add_number
>= 0x8000)
12159 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12160 gpdelay
= reg_needs_delay (mips_gp_register
);
12161 relax_start (offset_expr
.X_add_symbol
);
12162 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12163 BFD_RELOC_MIPS_GOT_HI16
);
12164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12167 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12170 macro_build (NULL
, "nop", "");
12171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12172 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12174 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12175 tempreg
, BFD_RELOC_LO16
);
12179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12180 tempreg
, tempreg
, breg
);
12181 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12183 else if (mips_big_got
&& HAVE_NEWABI
)
12185 /* If this is a reference to an external symbol, we want
12186 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12187 add $tempreg,$tempreg,$gp
12188 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12189 <op> op[0],<ofst>($tempreg)
12190 Otherwise, for local symbols, we want:
12191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12192 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12193 gas_assert (offset_expr
.X_op
== O_symbol
);
12194 expr1
.X_add_number
= offset_expr
.X_add_number
;
12195 offset_expr
.X_add_number
= 0;
12196 if (expr1
.X_add_number
< -0x8000
12197 || expr1
.X_add_number
>= 0x8000)
12198 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12199 relax_start (offset_expr
.X_add_symbol
);
12200 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12201 BFD_RELOC_MIPS_GOT_HI16
);
12202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12205 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12207 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12208 tempreg
, tempreg
, breg
);
12209 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12212 offset_expr
.X_add_number
= expr1
.X_add_number
;
12213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12214 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12217 tempreg
, tempreg
, breg
);
12218 macro_build (&offset_expr
, s
, fmt
, op
[0],
12219 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12228 gas_assert (mips_opts
.micromips
);
12229 gas_assert (mips_opts
.insn32
);
12230 start_noreorder ();
12231 macro_build (NULL
, "jr", "s", RA
);
12232 expr1
.X_add_number
= op
[0] << 2;
12233 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12238 gas_assert (mips_opts
.micromips
);
12239 gas_assert (mips_opts
.insn32
);
12240 macro_build (NULL
, "jr", "s", op
[0]);
12241 if (mips_opts
.noreorder
)
12242 macro_build (NULL
, "nop", "");
12247 load_register (op
[0], &imm_expr
, 0);
12251 load_register (op
[0], &imm_expr
, 1);
12255 if (imm_expr
.X_op
== O_constant
)
12258 load_register (AT
, &imm_expr
, 0);
12259 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12264 gas_assert (imm_expr
.X_op
== O_absent
12265 && offset_expr
.X_op
== O_symbol
12266 && strcmp (segment_name (S_GET_SEGMENT
12267 (offset_expr
.X_add_symbol
)),
12269 && offset_expr
.X_add_number
== 0);
12270 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12271 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12276 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12277 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12278 order 32 bits of the value and the low order 32 bits are either
12279 zero or in OFFSET_EXPR. */
12280 if (imm_expr
.X_op
== O_constant
)
12282 if (GPR_SIZE
== 64)
12283 load_register (op
[0], &imm_expr
, 1);
12288 if (target_big_endian
)
12300 load_register (hreg
, &imm_expr
, 0);
12303 if (offset_expr
.X_op
== O_absent
)
12304 move_register (lreg
, 0);
12307 gas_assert (offset_expr
.X_op
== O_constant
);
12308 load_register (lreg
, &offset_expr
, 0);
12314 gas_assert (imm_expr
.X_op
== O_absent
);
12316 /* We know that sym is in the .rdata section. First we get the
12317 upper 16 bits of the address. */
12318 if (mips_pic
== NO_PIC
)
12320 macro_build_lui (&offset_expr
, AT
);
12325 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12326 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12330 /* Now we load the register(s). */
12331 if (GPR_SIZE
== 64)
12334 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12335 BFD_RELOC_LO16
, AT
);
12340 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12341 BFD_RELOC_LO16
, AT
);
12344 /* FIXME: How in the world do we deal with the possible
12346 offset_expr
.X_add_number
+= 4;
12347 macro_build (&offset_expr
, "lw", "t,o(b)",
12348 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12354 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12355 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12356 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12357 the value and the low order 32 bits are either zero or in
12359 if (imm_expr
.X_op
== O_constant
)
12362 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12363 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12364 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12367 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12368 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12369 else if (FPR_SIZE
!= 32)
12370 as_bad (_("Unable to generate `%s' compliant code "
12372 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12374 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12375 if (offset_expr
.X_op
== O_absent
)
12376 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12379 gas_assert (offset_expr
.X_op
== O_constant
);
12380 load_register (AT
, &offset_expr
, 0);
12381 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12387 gas_assert (imm_expr
.X_op
== O_absent
12388 && offset_expr
.X_op
== O_symbol
12389 && offset_expr
.X_add_number
== 0);
12390 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12391 if (strcmp (s
, ".lit8") == 0)
12393 op
[2] = mips_gp_register
;
12394 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12395 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12396 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12400 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12402 if (mips_pic
!= NO_PIC
)
12403 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12404 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12407 /* FIXME: This won't work for a 64 bit address. */
12408 macro_build_lui (&offset_expr
, AT
);
12412 offset_reloc
[0] = BFD_RELOC_LO16
;
12413 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12414 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12421 * The MIPS assembler seems to check for X_add_number not
12422 * being double aligned and generating:
12423 * lui at,%hi(foo+1)
12425 * addiu at,at,%lo(foo+1)
12428 * But, the resulting address is the same after relocation so why
12429 * generate the extra instruction?
12431 /* Itbl support may require additional care here. */
12434 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12443 gas_assert (!mips_opts
.micromips
);
12444 /* Itbl support may require additional care here. */
12447 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12467 if (GPR_SIZE
== 64)
12477 if (GPR_SIZE
== 64)
12485 /* Even on a big endian machine $fn comes before $fn+1. We have
12486 to adjust when loading from memory. We set coproc if we must
12487 load $fn+1 first. */
12488 /* Itbl support may require additional care here. */
12489 if (!target_big_endian
)
12493 if (small_offset_p (0, align
, 16))
12496 if (!small_offset_p (4, align
, 16))
12498 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12499 -1, offset_reloc
[0], offset_reloc
[1],
12501 expr1
.X_add_number
= 0;
12505 offset_reloc
[0] = BFD_RELOC_LO16
;
12506 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12507 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12509 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12511 ep
->X_add_number
+= 4;
12512 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12513 offset_reloc
[1], offset_reloc
[2], breg
);
12514 ep
->X_add_number
-= 4;
12515 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12516 offset_reloc
[1], offset_reloc
[2], breg
);
12520 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12521 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12523 ep
->X_add_number
+= 4;
12524 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12525 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12531 if (offset_expr
.X_op
!= O_symbol
12532 && offset_expr
.X_op
!= O_constant
)
12534 as_bad (_("expression too complex"));
12535 offset_expr
.X_op
= O_constant
;
12538 if (HAVE_32BIT_ADDRESSES
12539 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12543 sprintf_vma (value
, offset_expr
.X_add_number
);
12544 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12547 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12549 /* If this is a reference to a GP relative symbol, we want
12550 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12551 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12552 If we have a base register, we use this
12554 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12555 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12556 If this is not a GP relative symbol, we want
12557 lui $at,<sym> (BFD_RELOC_HI16_S)
12558 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12559 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12560 If there is a base register, we add it to $at after the
12561 lui instruction. If there is a constant, we always use
12563 if (offset_expr
.X_op
== O_symbol
12564 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12565 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12567 relax_start (offset_expr
.X_add_symbol
);
12570 tempreg
= mips_gp_register
;
12574 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12575 AT
, breg
, mips_gp_register
);
12580 /* Itbl support may require additional care here. */
12581 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12582 BFD_RELOC_GPREL16
, tempreg
);
12583 offset_expr
.X_add_number
+= 4;
12585 /* Set mips_optimize to 2 to avoid inserting an
12587 hold_mips_optimize
= mips_optimize
;
12589 /* Itbl support may require additional care here. */
12590 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12591 BFD_RELOC_GPREL16
, tempreg
);
12592 mips_optimize
= hold_mips_optimize
;
12596 offset_expr
.X_add_number
-= 4;
12599 if (offset_high_part (offset_expr
.X_add_number
, 16)
12600 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12602 load_address (AT
, &offset_expr
, &used_at
);
12603 offset_expr
.X_op
= O_constant
;
12604 offset_expr
.X_add_number
= 0;
12607 macro_build_lui (&offset_expr
, AT
);
12609 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12610 /* Itbl support may require additional care here. */
12611 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12612 BFD_RELOC_LO16
, AT
);
12613 /* FIXME: How do we handle overflow here? */
12614 offset_expr
.X_add_number
+= 4;
12615 /* Itbl support may require additional care here. */
12616 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12617 BFD_RELOC_LO16
, AT
);
12618 if (mips_relax
.sequence
)
12621 else if (!mips_big_got
)
12623 /* If this is a reference to an external symbol, we want
12624 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12627 <op> op[0]+1,4($at)
12629 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12631 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12632 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12633 If there is a base register we add it to $at before the
12634 lwc1 instructions. If there is a constant we include it
12635 in the lwc1 instructions. */
12637 expr1
.X_add_number
= offset_expr
.X_add_number
;
12638 if (expr1
.X_add_number
< -0x8000
12639 || expr1
.X_add_number
>= 0x8000 - 4)
12640 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12641 load_got_offset (AT
, &offset_expr
);
12644 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12646 /* Set mips_optimize to 2 to avoid inserting an undesired
12648 hold_mips_optimize
= mips_optimize
;
12651 /* Itbl support may require additional care here. */
12652 relax_start (offset_expr
.X_add_symbol
);
12653 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12654 BFD_RELOC_LO16
, AT
);
12655 expr1
.X_add_number
+= 4;
12656 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12657 BFD_RELOC_LO16
, AT
);
12659 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12660 BFD_RELOC_LO16
, AT
);
12661 offset_expr
.X_add_number
+= 4;
12662 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12663 BFD_RELOC_LO16
, AT
);
12666 mips_optimize
= hold_mips_optimize
;
12668 else if (mips_big_got
)
12672 /* If this is a reference to an external symbol, we want
12673 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12675 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12678 <op> op[0]+1,4($at)
12680 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12682 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12683 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12684 If there is a base register we add it to $at before the
12685 lwc1 instructions. If there is a constant we include it
12686 in the lwc1 instructions. */
12688 expr1
.X_add_number
= offset_expr
.X_add_number
;
12689 offset_expr
.X_add_number
= 0;
12690 if (expr1
.X_add_number
< -0x8000
12691 || expr1
.X_add_number
>= 0x8000 - 4)
12692 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12693 gpdelay
= reg_needs_delay (mips_gp_register
);
12694 relax_start (offset_expr
.X_add_symbol
);
12695 macro_build (&offset_expr
, "lui", LUI_FMT
,
12696 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12698 AT
, AT
, mips_gp_register
);
12699 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12700 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12703 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12704 /* Itbl support may require additional care here. */
12705 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12706 BFD_RELOC_LO16
, AT
);
12707 expr1
.X_add_number
+= 4;
12709 /* Set mips_optimize to 2 to avoid inserting an undesired
12711 hold_mips_optimize
= mips_optimize
;
12713 /* Itbl support may require additional care here. */
12714 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12715 BFD_RELOC_LO16
, AT
);
12716 mips_optimize
= hold_mips_optimize
;
12717 expr1
.X_add_number
-= 4;
12720 offset_expr
.X_add_number
= expr1
.X_add_number
;
12722 macro_build (NULL
, "nop", "");
12723 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12724 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12727 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12728 /* Itbl support may require additional care here. */
12729 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12730 BFD_RELOC_LO16
, AT
);
12731 offset_expr
.X_add_number
+= 4;
12733 /* Set mips_optimize to 2 to avoid inserting an undesired
12735 hold_mips_optimize
= mips_optimize
;
12737 /* Itbl support may require additional care here. */
12738 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12739 BFD_RELOC_LO16
, AT
);
12740 mips_optimize
= hold_mips_optimize
;
12754 gas_assert (!mips_opts
.micromips
);
12759 /* New code added to support COPZ instructions.
12760 This code builds table entries out of the macros in mip_opcodes.
12761 R4000 uses interlocks to handle coproc delays.
12762 Other chips (like the R3000) require nops to be inserted for delays.
12764 FIXME: Currently, we require that the user handle delays.
12765 In order to fill delay slots for non-interlocked chips,
12766 we must have a way to specify delays based on the coprocessor.
12767 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12768 What are the side-effects of the cop instruction?
12769 What cache support might we have and what are its effects?
12770 Both coprocessor & memory require delays. how long???
12771 What registers are read/set/modified?
12773 If an itbl is provided to interpret cop instructions,
12774 this knowledge can be encoded in the itbl spec. */
12788 gas_assert (!mips_opts
.micromips
);
12789 /* For now we just do C (same as Cz). The parameter will be
12790 stored in insn_opcode by mips_ip. */
12791 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12795 move_register (op
[0], op
[1]);
12799 gas_assert (mips_opts
.micromips
);
12800 gas_assert (mips_opts
.insn32
);
12801 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12802 micromips_to_32_reg_m_map
[op
[1]]);
12803 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12804 micromips_to_32_reg_n_map
[op
[2]]);
12809 /* Fall through. */
12811 if (mips_opts
.arch
== CPU_R5900
)
12812 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12816 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12817 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12823 /* Fall through. */
12825 /* The MIPS assembler some times generates shifts and adds. I'm
12826 not trying to be that fancy. GCC should do this for us
12829 load_register (AT
, &imm_expr
, dbl
);
12830 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12831 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12836 /* Fall through. */
12843 /* Fall through. */
12846 start_noreorder ();
12849 load_register (AT
, &imm_expr
, dbl
);
12850 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12851 op
[1], imm
? AT
: op
[2]);
12852 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12853 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12854 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12856 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12859 if (mips_opts
.micromips
)
12860 micromips_label_expr (&label_expr
);
12862 label_expr
.X_add_number
= 8;
12863 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12864 macro_build (NULL
, "nop", "");
12865 macro_build (NULL
, "break", BRK_FMT
, 6);
12866 if (mips_opts
.micromips
)
12867 micromips_add_label ();
12870 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12875 /* Fall through. */
12882 /* Fall through. */
12885 start_noreorder ();
12888 load_register (AT
, &imm_expr
, dbl
);
12889 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12890 op
[1], imm
? AT
: op
[2]);
12891 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12892 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12894 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12897 if (mips_opts
.micromips
)
12898 micromips_label_expr (&label_expr
);
12900 label_expr
.X_add_number
= 8;
12901 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12902 macro_build (NULL
, "nop", "");
12903 macro_build (NULL
, "break", BRK_FMT
, 6);
12904 if (mips_opts
.micromips
)
12905 micromips_add_label ();
12911 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12913 if (op
[0] == op
[1])
12920 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12921 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12925 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12926 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12927 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12928 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12932 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12934 if (op
[0] == op
[1])
12941 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12942 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12946 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12947 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12948 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12949 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12958 rot
= imm_expr
.X_add_number
& 0x3f;
12959 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12961 rot
= (64 - rot
) & 0x3f;
12963 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12965 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12970 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12973 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12974 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12977 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12978 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12979 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12987 rot
= imm_expr
.X_add_number
& 0x1f;
12988 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12990 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12991 (32 - rot
) & 0x1f);
12996 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13000 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13001 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13002 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13007 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13009 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13013 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13014 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13015 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13016 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13020 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13022 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13026 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13027 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13028 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13029 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13038 rot
= imm_expr
.X_add_number
& 0x3f;
13039 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13042 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13044 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13049 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13052 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13053 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13056 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13057 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13058 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13066 rot
= imm_expr
.X_add_number
& 0x1f;
13067 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13069 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13074 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13078 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13079 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13080 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13086 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13087 else if (op
[2] == 0)
13088 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13091 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13092 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13097 if (imm_expr
.X_add_number
== 0)
13099 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13104 as_warn (_("instruction %s: result is always false"),
13105 ip
->insn_mo
->name
);
13106 move_register (op
[0], 0);
13109 if (CPU_HAS_SEQ (mips_opts
.arch
)
13110 && -512 <= imm_expr
.X_add_number
13111 && imm_expr
.X_add_number
< 512)
13113 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13114 (int) imm_expr
.X_add_number
);
13117 if (imm_expr
.X_add_number
>= 0
13118 && imm_expr
.X_add_number
< 0x10000)
13119 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13120 else if (imm_expr
.X_add_number
> -0x8000
13121 && imm_expr
.X_add_number
< 0)
13123 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13124 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13125 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13127 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13130 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13131 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13136 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13137 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13140 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13143 case M_SGE
: /* X >= Y <==> not (X < Y) */
13149 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13150 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13153 case M_SGE_I
: /* X >= I <==> not (X < I) */
13155 if (imm_expr
.X_add_number
>= -0x8000
13156 && imm_expr
.X_add_number
< 0x8000)
13157 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13158 op
[0], op
[1], BFD_RELOC_LO16
);
13161 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13162 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13166 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13169 case M_SGT
: /* X > Y <==> Y < X */
13175 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13178 case M_SGT_I
: /* X > I <==> I < X */
13185 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13186 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13189 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13195 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13196 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13199 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13206 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13207 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13208 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13212 if (imm_expr
.X_add_number
>= -0x8000
13213 && imm_expr
.X_add_number
< 0x8000)
13215 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13220 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13221 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13225 if (imm_expr
.X_add_number
>= -0x8000
13226 && imm_expr
.X_add_number
< 0x8000)
13228 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13233 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13234 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13239 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13240 else if (op
[2] == 0)
13241 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13244 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13245 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13250 if (imm_expr
.X_add_number
== 0)
13252 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13257 as_warn (_("instruction %s: result is always true"),
13258 ip
->insn_mo
->name
);
13259 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13260 op
[0], 0, BFD_RELOC_LO16
);
13263 if (CPU_HAS_SEQ (mips_opts
.arch
)
13264 && -512 <= imm_expr
.X_add_number
13265 && imm_expr
.X_add_number
< 512)
13267 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13268 (int) imm_expr
.X_add_number
);
13271 if (imm_expr
.X_add_number
>= 0
13272 && imm_expr
.X_add_number
< 0x10000)
13274 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13277 else if (imm_expr
.X_add_number
> -0x8000
13278 && imm_expr
.X_add_number
< 0)
13280 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13281 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13282 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13284 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13287 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13288 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13293 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13294 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13297 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13312 if (!mips_opts
.micromips
)
13314 if (imm_expr
.X_add_number
> -0x200
13315 && imm_expr
.X_add_number
<= 0x200)
13317 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13318 (int) -imm_expr
.X_add_number
);
13327 if (imm_expr
.X_add_number
> -0x8000
13328 && imm_expr
.X_add_number
<= 0x8000)
13330 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13331 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13336 load_register (AT
, &imm_expr
, dbl
);
13337 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13359 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13360 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13365 gas_assert (!mips_opts
.micromips
);
13366 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13370 * Is the double cfc1 instruction a bug in the mips assembler;
13371 * or is there a reason for it?
13373 start_noreorder ();
13374 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13375 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13376 macro_build (NULL
, "nop", "");
13377 expr1
.X_add_number
= 3;
13378 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13379 expr1
.X_add_number
= 2;
13380 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13381 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13382 macro_build (NULL
, "nop", "");
13383 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13385 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13386 macro_build (NULL
, "nop", "");
13403 offbits
= (mips_opts
.micromips
? 12 : 16);
13409 offbits
= (mips_opts
.micromips
? 12 : 16);
13421 offbits
= (mips_opts
.micromips
? 12 : 16);
13428 offbits
= (mips_opts
.micromips
? 12 : 16);
13434 large_offset
= !small_offset_p (off
, align
, offbits
);
13436 expr1
.X_add_number
= 0;
13441 if (small_offset_p (0, align
, 16))
13442 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13443 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13446 load_address (tempreg
, ep
, &used_at
);
13448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13449 tempreg
, tempreg
, breg
);
13451 offset_reloc
[0] = BFD_RELOC_LO16
;
13452 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13453 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13458 else if (!ust
&& op
[0] == breg
)
13469 if (!target_big_endian
)
13470 ep
->X_add_number
+= off
;
13472 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13474 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13475 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13477 if (!target_big_endian
)
13478 ep
->X_add_number
-= off
;
13480 ep
->X_add_number
+= off
;
13482 macro_build (NULL
, s2
, "t,~(b)",
13483 tempreg
, (int) ep
->X_add_number
, breg
);
13485 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13486 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13488 /* If necessary, move the result in tempreg to the final destination. */
13489 if (!ust
&& op
[0] != tempreg
)
13491 /* Protect second load's delay slot. */
13493 move_register (op
[0], tempreg
);
13499 if (target_big_endian
== ust
)
13500 ep
->X_add_number
+= off
;
13501 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13502 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13503 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13505 /* For halfword transfers we need a temporary register to shuffle
13506 bytes. Unfortunately for M_USH_A we have none available before
13507 the next store as AT holds the base address. We deal with this
13508 case by clobbering TREG and then restoring it as with ULH. */
13509 tempreg
= ust
== large_offset
? op
[0] : AT
;
13511 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13513 if (target_big_endian
== ust
)
13514 ep
->X_add_number
-= off
;
13516 ep
->X_add_number
+= off
;
13517 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13518 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13520 /* For M_USH_A re-retrieve the LSB. */
13521 if (ust
&& large_offset
)
13523 if (target_big_endian
)
13524 ep
->X_add_number
+= off
;
13526 ep
->X_add_number
-= off
;
13527 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13528 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13530 /* For ULH and M_USH_A OR the LSB in. */
13531 if (!ust
|| large_offset
)
13533 tempreg
= !large_offset
? AT
: op
[0];
13534 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13535 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13540 /* FIXME: Check if this is one of the itbl macros, since they
13541 are added dynamically. */
13542 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13545 if (!mips_opts
.at
&& used_at
)
13546 as_bad (_("macro used $at after \".set noat\""));
13549 /* Implement macros in mips16 mode. */
13552 mips16_macro (struct mips_cl_insn
*ip
)
13554 const struct mips_operand_array
*operands
;
13559 const char *s
, *s2
, *s3
;
13560 unsigned int op
[MAX_OPERANDS
];
13563 mask
= ip
->insn_mo
->mask
;
13565 operands
= insn_operands (ip
);
13566 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13567 if (operands
->operand
[i
])
13568 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13572 expr1
.X_op
= O_constant
;
13573 expr1
.X_op_symbol
= NULL
;
13574 expr1
.X_add_symbol
= NULL
;
13575 expr1
.X_add_number
= 1;
13586 /* Fall through. */
13592 /* Fall through. */
13596 start_noreorder ();
13597 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13598 expr1
.X_add_number
= 2;
13599 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13600 macro_build (NULL
, "break", "6", 7);
13602 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13603 since that causes an overflow. We should do that as well,
13604 but I don't see how to do the comparisons without a temporary
13607 macro_build (NULL
, s
, "x", op
[0]);
13626 start_noreorder ();
13627 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13628 expr1
.X_add_number
= 2;
13629 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13630 macro_build (NULL
, "break", "6", 7);
13632 macro_build (NULL
, s2
, "x", op
[0]);
13637 /* Fall through. */
13639 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13640 macro_build (NULL
, "mflo", "x", op
[0]);
13648 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13649 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13653 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13654 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13658 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13659 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13681 goto do_reverse_branch
;
13685 goto do_reverse_branch
;
13697 goto do_reverse_branch
;
13708 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13709 macro_build (&offset_expr
, s2
, "p");
13736 goto do_addone_branch_i
;
13741 goto do_addone_branch_i
;
13756 goto do_addone_branch_i
;
13762 do_addone_branch_i
:
13763 ++imm_expr
.X_add_number
;
13766 macro_build (&imm_expr
, s
, s3
, op
[0]);
13767 macro_build (&offset_expr
, s2
, "p");
13771 expr1
.X_add_number
= 0;
13772 macro_build (&expr1
, "slti", "x,8", op
[1]);
13773 if (op
[0] != op
[1])
13774 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13775 expr1
.X_add_number
= 2;
13776 macro_build (&expr1
, "bteqz", "p");
13777 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13782 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13783 opcode bits in *OPCODE_EXTRA. */
13785 static struct mips_opcode
*
13786 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13787 ssize_t length
, unsigned int *opcode_extra
)
13789 char *name
, *dot
, *p
;
13790 unsigned int mask
, suffix
;
13792 struct mips_opcode
*insn
;
13794 /* Make a copy of the instruction so that we can fiddle with it. */
13795 name
= xstrndup (start
, length
);
13797 /* Look up the instruction as-is. */
13798 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13802 dot
= strchr (name
, '.');
13805 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13806 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13807 if (*p
== 0 && mask
!= 0)
13810 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13812 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13814 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13820 if (mips_opts
.micromips
)
13822 /* See if there's an instruction size override suffix,
13823 either `16' or `32', at the end of the mnemonic proper,
13824 that defines the operation, i.e. before the first `.'
13825 character if any. Strip it and retry. */
13826 opend
= dot
!= NULL
? dot
- name
: length
;
13827 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13829 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13835 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13836 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13839 forced_insn_length
= suffix
;
13851 /* Assemble an instruction into its binary format. If the instruction
13852 is a macro, set imm_expr and offset_expr to the values associated
13853 with "I" and "A" operands respectively. Otherwise store the value
13854 of the relocatable field (if any) in offset_expr. In both cases
13855 set offset_reloc to the relocation operators applied to offset_expr. */
13858 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13860 const struct mips_opcode
*first
, *past
;
13861 struct hash_control
*hash
;
13864 struct mips_operand_token
*tokens
;
13865 unsigned int opcode_extra
;
13867 if (mips_opts
.micromips
)
13869 hash
= micromips_op_hash
;
13870 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13875 past
= &mips_opcodes
[NUMOPCODES
];
13877 forced_insn_length
= 0;
13880 /* We first try to match an instruction up to a space or to the end. */
13881 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13884 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13887 set_insn_error (0, _("unrecognized opcode"));
13891 if (strcmp (first
->name
, "li.s") == 0)
13893 else if (strcmp (first
->name
, "li.d") == 0)
13897 tokens
= mips_parse_arguments (str
+ end
, format
);
13901 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13902 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13903 set_insn_error (0, _("invalid operands"));
13905 obstack_free (&mips_operand_tokens
, tokens
);
13908 /* As for mips_ip, but used when assembling MIPS16 code.
13909 Also set forced_insn_length to the resulting instruction size in
13910 bytes if the user explicitly requested a small or extended instruction. */
13913 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13916 struct mips_opcode
*first
;
13917 struct mips_operand_token
*tokens
;
13920 for (s
= str
; ISLOWER (*s
); ++s
)
13942 else if (*s
== 'e')
13949 else if (*s
++ == ' ')
13951 /* Fall through. */
13953 set_insn_error (0, _("unrecognized opcode"));
13956 forced_insn_length
= l
;
13959 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13964 set_insn_error (0, _("unrecognized opcode"));
13968 tokens
= mips_parse_arguments (s
, 0);
13972 if (!match_mips16_insns (insn
, first
, tokens
))
13973 set_insn_error (0, _("invalid operands"));
13975 obstack_free (&mips_operand_tokens
, tokens
);
13978 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13979 NBITS is the number of significant bits in VAL. */
13981 static unsigned long
13982 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13987 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13990 else if (nbits
== 15)
13992 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13997 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14000 return (extval
<< 16) | val
;
14003 /* Like decode_mips16_operand, but require the operand to be defined and
14004 require it to be an integer. */
14006 static const struct mips_int_operand
*
14007 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14009 const struct mips_operand
*operand
;
14011 operand
= decode_mips16_operand (type
, extended_p
);
14012 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14014 return (const struct mips_int_operand
*) operand
;
14017 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14020 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14021 bfd_reloc_code_real_type reloc
, offsetT sval
)
14023 int min_val
, max_val
;
14025 min_val
= mips_int_operand_min (operand
);
14026 max_val
= mips_int_operand_max (operand
);
14027 if (reloc
!= BFD_RELOC_UNUSED
)
14030 sval
= SEXT_16BIT (sval
);
14035 return (sval
>= min_val
14037 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14040 /* Install immediate value VAL into MIPS16 instruction *INSN,
14041 extending it if necessary. The instruction in *INSN may
14042 already be extended.
14044 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14045 if none. In the former case, VAL is a 16-bit number with no
14046 defined signedness.
14048 TYPE is the type of the immediate field. USER_INSN_LENGTH
14049 is the length that the user requested, or 0 if none. */
14052 mips16_immed (const char *file
, unsigned int line
, int type
,
14053 bfd_reloc_code_real_type reloc
, offsetT val
,
14054 unsigned int user_insn_length
, unsigned long *insn
)
14056 const struct mips_int_operand
*operand
;
14057 unsigned int uval
, length
;
14059 operand
= mips16_immed_operand (type
, FALSE
);
14060 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14062 /* We need an extended instruction. */
14063 if (user_insn_length
== 2)
14064 as_bad_where (file
, line
, _("invalid unextended operand value"));
14066 *insn
|= MIPS16_EXTEND
;
14068 else if (user_insn_length
== 4)
14070 /* The operand doesn't force an unextended instruction to be extended.
14071 Warn if the user wanted an extended instruction anyway. */
14072 *insn
|= MIPS16_EXTEND
;
14073 as_warn_where (file
, line
,
14074 _("extended operand requested but not required"));
14077 length
= mips16_opcode_length (*insn
);
14080 operand
= mips16_immed_operand (type
, TRUE
);
14081 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14082 as_bad_where (file
, line
,
14083 _("operand value out of range for instruction"));
14085 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14086 if (length
== 2 || operand
->root
.lsb
!= 0)
14087 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14089 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14092 struct percent_op_match
14095 bfd_reloc_code_real_type reloc
;
14098 static const struct percent_op_match mips_percent_op
[] =
14100 {"%lo", BFD_RELOC_LO16
},
14101 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14102 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14103 {"%call16", BFD_RELOC_MIPS_CALL16
},
14104 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14105 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14106 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14107 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14108 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14109 {"%got", BFD_RELOC_MIPS_GOT16
},
14110 {"%gp_rel", BFD_RELOC_GPREL16
},
14111 {"%gprel", BFD_RELOC_GPREL16
},
14112 {"%half", BFD_RELOC_16
},
14113 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14114 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14115 {"%neg", BFD_RELOC_MIPS_SUB
},
14116 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14117 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14118 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14119 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14120 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14121 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14122 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14123 {"%hi", BFD_RELOC_HI16_S
},
14124 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14125 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14128 static const struct percent_op_match mips16_percent_op
[] =
14130 {"%lo", BFD_RELOC_MIPS16_LO16
},
14131 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14132 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14133 {"%got", BFD_RELOC_MIPS16_GOT16
},
14134 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14135 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14136 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14137 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14138 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14139 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14140 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14141 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14142 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14146 /* Return true if *STR points to a relocation operator. When returning true,
14147 move *STR over the operator and store its relocation code in *RELOC.
14148 Leave both *STR and *RELOC alone when returning false. */
14151 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14153 const struct percent_op_match
*percent_op
;
14156 if (mips_opts
.mips16
)
14158 percent_op
= mips16_percent_op
;
14159 limit
= ARRAY_SIZE (mips16_percent_op
);
14163 percent_op
= mips_percent_op
;
14164 limit
= ARRAY_SIZE (mips_percent_op
);
14167 for (i
= 0; i
< limit
; i
++)
14168 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14170 int len
= strlen (percent_op
[i
].str
);
14172 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14175 *str
+= strlen (percent_op
[i
].str
);
14176 *reloc
= percent_op
[i
].reloc
;
14178 /* Check whether the output BFD supports this relocation.
14179 If not, issue an error and fall back on something safe. */
14180 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14182 as_bad (_("relocation %s isn't supported by the current ABI"),
14183 percent_op
[i
].str
);
14184 *reloc
= BFD_RELOC_UNUSED
;
14192 /* Parse string STR as a 16-bit relocatable operand. Store the
14193 expression in *EP and the relocations in the array starting
14194 at RELOC. Return the number of relocation operators used.
14196 On exit, EXPR_END points to the first character after the expression. */
14199 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14202 bfd_reloc_code_real_type reversed_reloc
[3];
14203 size_t reloc_index
, i
;
14204 int crux_depth
, str_depth
;
14207 /* Search for the start of the main expression, recoding relocations
14208 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14209 of the main expression and with CRUX_DEPTH containing the number
14210 of open brackets at that point. */
14217 crux_depth
= str_depth
;
14219 /* Skip over whitespace and brackets, keeping count of the number
14221 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14226 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14227 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14229 my_getExpression (ep
, crux
);
14232 /* Match every open bracket. */
14233 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14237 if (crux_depth
> 0)
14238 as_bad (_("unclosed '('"));
14242 if (reloc_index
!= 0)
14244 prev_reloc_op_frag
= frag_now
;
14245 for (i
= 0; i
< reloc_index
; i
++)
14246 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14249 return reloc_index
;
14253 my_getExpression (expressionS
*ep
, char *str
)
14257 save_in
= input_line_pointer
;
14258 input_line_pointer
= str
;
14260 expr_end
= input_line_pointer
;
14261 input_line_pointer
= save_in
;
14265 md_atof (int type
, char *litP
, int *sizeP
)
14267 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14271 md_number_to_chars (char *buf
, valueT val
, int n
)
14273 if (target_big_endian
)
14274 number_to_chars_bigendian (buf
, val
, n
);
14276 number_to_chars_littleendian (buf
, val
, n
);
14279 static int support_64bit_objects(void)
14281 const char **list
, **l
;
14284 list
= bfd_target_list ();
14285 for (l
= list
; *l
!= NULL
; l
++)
14286 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14287 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14289 yes
= (*l
!= NULL
);
14294 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14295 NEW_VALUE. Warn if another value was already specified. Note:
14296 we have to defer parsing the -march and -mtune arguments in order
14297 to handle 'from-abi' correctly, since the ABI might be specified
14298 in a later argument. */
14301 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14303 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14304 as_warn (_("a different %s was already specified, is now %s"),
14305 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14308 *string_ptr
= new_value
;
14312 md_parse_option (int c
, const char *arg
)
14316 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14317 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14319 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14320 c
== mips_ases
[i
].option_on
);
14326 case OPTION_CONSTRUCT_FLOATS
:
14327 mips_disable_float_construction
= 0;
14330 case OPTION_NO_CONSTRUCT_FLOATS
:
14331 mips_disable_float_construction
= 1;
14343 target_big_endian
= 1;
14347 target_big_endian
= 0;
14353 else if (arg
[0] == '0')
14355 else if (arg
[0] == '1')
14365 mips_debug
= atoi (arg
);
14369 file_mips_opts
.isa
= ISA_MIPS1
;
14373 file_mips_opts
.isa
= ISA_MIPS2
;
14377 file_mips_opts
.isa
= ISA_MIPS3
;
14381 file_mips_opts
.isa
= ISA_MIPS4
;
14385 file_mips_opts
.isa
= ISA_MIPS5
;
14388 case OPTION_MIPS32
:
14389 file_mips_opts
.isa
= ISA_MIPS32
;
14392 case OPTION_MIPS32R2
:
14393 file_mips_opts
.isa
= ISA_MIPS32R2
;
14396 case OPTION_MIPS32R3
:
14397 file_mips_opts
.isa
= ISA_MIPS32R3
;
14400 case OPTION_MIPS32R5
:
14401 file_mips_opts
.isa
= ISA_MIPS32R5
;
14404 case OPTION_MIPS32R6
:
14405 file_mips_opts
.isa
= ISA_MIPS32R6
;
14408 case OPTION_MIPS64R2
:
14409 file_mips_opts
.isa
= ISA_MIPS64R2
;
14412 case OPTION_MIPS64R3
:
14413 file_mips_opts
.isa
= ISA_MIPS64R3
;
14416 case OPTION_MIPS64R5
:
14417 file_mips_opts
.isa
= ISA_MIPS64R5
;
14420 case OPTION_MIPS64R6
:
14421 file_mips_opts
.isa
= ISA_MIPS64R6
;
14424 case OPTION_MIPS64
:
14425 file_mips_opts
.isa
= ISA_MIPS64
;
14429 mips_set_option_string (&mips_tune_string
, arg
);
14433 mips_set_option_string (&mips_arch_string
, arg
);
14437 mips_set_option_string (&mips_arch_string
, "4650");
14438 mips_set_option_string (&mips_tune_string
, "4650");
14441 case OPTION_NO_M4650
:
14445 mips_set_option_string (&mips_arch_string
, "4010");
14446 mips_set_option_string (&mips_tune_string
, "4010");
14449 case OPTION_NO_M4010
:
14453 mips_set_option_string (&mips_arch_string
, "4100");
14454 mips_set_option_string (&mips_tune_string
, "4100");
14457 case OPTION_NO_M4100
:
14461 mips_set_option_string (&mips_arch_string
, "3900");
14462 mips_set_option_string (&mips_tune_string
, "3900");
14465 case OPTION_NO_M3900
:
14468 case OPTION_MICROMIPS
:
14469 if (file_mips_opts
.mips16
== 1)
14471 as_bad (_("-mmicromips cannot be used with -mips16"));
14474 file_mips_opts
.micromips
= 1;
14475 mips_no_prev_insn ();
14478 case OPTION_NO_MICROMIPS
:
14479 file_mips_opts
.micromips
= 0;
14480 mips_no_prev_insn ();
14483 case OPTION_MIPS16
:
14484 if (file_mips_opts
.micromips
== 1)
14486 as_bad (_("-mips16 cannot be used with -micromips"));
14489 file_mips_opts
.mips16
= 1;
14490 mips_no_prev_insn ();
14493 case OPTION_NO_MIPS16
:
14494 file_mips_opts
.mips16
= 0;
14495 mips_no_prev_insn ();
14498 case OPTION_FIX_24K
:
14502 case OPTION_NO_FIX_24K
:
14506 case OPTION_FIX_RM7000
:
14507 mips_fix_rm7000
= 1;
14510 case OPTION_NO_FIX_RM7000
:
14511 mips_fix_rm7000
= 0;
14514 case OPTION_FIX_LOONGSON2F_JUMP
:
14515 mips_fix_loongson2f_jump
= TRUE
;
14518 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14519 mips_fix_loongson2f_jump
= FALSE
;
14522 case OPTION_FIX_LOONGSON2F_NOP
:
14523 mips_fix_loongson2f_nop
= TRUE
;
14526 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14527 mips_fix_loongson2f_nop
= FALSE
;
14530 case OPTION_FIX_VR4120
:
14531 mips_fix_vr4120
= 1;
14534 case OPTION_NO_FIX_VR4120
:
14535 mips_fix_vr4120
= 0;
14538 case OPTION_FIX_VR4130
:
14539 mips_fix_vr4130
= 1;
14542 case OPTION_NO_FIX_VR4130
:
14543 mips_fix_vr4130
= 0;
14546 case OPTION_FIX_CN63XXP1
:
14547 mips_fix_cn63xxp1
= TRUE
;
14550 case OPTION_NO_FIX_CN63XXP1
:
14551 mips_fix_cn63xxp1
= FALSE
;
14554 case OPTION_RELAX_BRANCH
:
14555 mips_relax_branch
= 1;
14558 case OPTION_NO_RELAX_BRANCH
:
14559 mips_relax_branch
= 0;
14562 case OPTION_IGNORE_BRANCH_ISA
:
14563 mips_ignore_branch_isa
= TRUE
;
14566 case OPTION_NO_IGNORE_BRANCH_ISA
:
14567 mips_ignore_branch_isa
= FALSE
;
14570 case OPTION_INSN32
:
14571 file_mips_opts
.insn32
= TRUE
;
14574 case OPTION_NO_INSN32
:
14575 file_mips_opts
.insn32
= FALSE
;
14578 case OPTION_MSHARED
:
14579 mips_in_shared
= TRUE
;
14582 case OPTION_MNO_SHARED
:
14583 mips_in_shared
= FALSE
;
14586 case OPTION_MSYM32
:
14587 file_mips_opts
.sym32
= TRUE
;
14590 case OPTION_MNO_SYM32
:
14591 file_mips_opts
.sym32
= FALSE
;
14594 /* When generating ELF code, we permit -KPIC and -call_shared to
14595 select SVR4_PIC, and -non_shared to select no PIC. This is
14596 intended to be compatible with Irix 5. */
14597 case OPTION_CALL_SHARED
:
14598 mips_pic
= SVR4_PIC
;
14599 mips_abicalls
= TRUE
;
14602 case OPTION_CALL_NONPIC
:
14604 mips_abicalls
= TRUE
;
14607 case OPTION_NON_SHARED
:
14609 mips_abicalls
= FALSE
;
14612 /* The -xgot option tells the assembler to use 32 bit offsets
14613 when accessing the got in SVR4_PIC mode. It is for Irix
14620 g_switch_value
= atoi (arg
);
14624 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14627 mips_abi
= O32_ABI
;
14631 mips_abi
= N32_ABI
;
14635 mips_abi
= N64_ABI
;
14636 if (!support_64bit_objects())
14637 as_fatal (_("no compiled in support for 64 bit object file format"));
14641 file_mips_opts
.gp
= 32;
14645 file_mips_opts
.gp
= 64;
14649 file_mips_opts
.fp
= 32;
14653 file_mips_opts
.fp
= 0;
14657 file_mips_opts
.fp
= 64;
14660 case OPTION_ODD_SPREG
:
14661 file_mips_opts
.oddspreg
= 1;
14664 case OPTION_NO_ODD_SPREG
:
14665 file_mips_opts
.oddspreg
= 0;
14668 case OPTION_SINGLE_FLOAT
:
14669 file_mips_opts
.single_float
= 1;
14672 case OPTION_DOUBLE_FLOAT
:
14673 file_mips_opts
.single_float
= 0;
14676 case OPTION_SOFT_FLOAT
:
14677 file_mips_opts
.soft_float
= 1;
14680 case OPTION_HARD_FLOAT
:
14681 file_mips_opts
.soft_float
= 0;
14685 if (strcmp (arg
, "32") == 0)
14686 mips_abi
= O32_ABI
;
14687 else if (strcmp (arg
, "o64") == 0)
14688 mips_abi
= O64_ABI
;
14689 else if (strcmp (arg
, "n32") == 0)
14690 mips_abi
= N32_ABI
;
14691 else if (strcmp (arg
, "64") == 0)
14693 mips_abi
= N64_ABI
;
14694 if (! support_64bit_objects())
14695 as_fatal (_("no compiled in support for 64 bit object file "
14698 else if (strcmp (arg
, "eabi") == 0)
14699 mips_abi
= EABI_ABI
;
14702 as_fatal (_("invalid abi -mabi=%s"), arg
);
14707 case OPTION_M7000_HILO_FIX
:
14708 mips_7000_hilo_fix
= TRUE
;
14711 case OPTION_MNO_7000_HILO_FIX
:
14712 mips_7000_hilo_fix
= FALSE
;
14715 case OPTION_MDEBUG
:
14716 mips_flag_mdebug
= TRUE
;
14719 case OPTION_NO_MDEBUG
:
14720 mips_flag_mdebug
= FALSE
;
14724 mips_flag_pdr
= TRUE
;
14727 case OPTION_NO_PDR
:
14728 mips_flag_pdr
= FALSE
;
14731 case OPTION_MVXWORKS_PIC
:
14732 mips_pic
= VXWORKS_PIC
;
14736 if (strcmp (arg
, "2008") == 0)
14738 else if (strcmp (arg
, "legacy") == 0)
14742 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14751 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14756 /* Set up globals to tune for the ISA or processor described by INFO. */
14759 mips_set_tune (const struct mips_cpu_info
*info
)
14762 mips_tune
= info
->cpu
;
14767 mips_after_parse_args (void)
14769 const struct mips_cpu_info
*arch_info
= 0;
14770 const struct mips_cpu_info
*tune_info
= 0;
14772 /* GP relative stuff not working for PE */
14773 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14775 if (g_switch_seen
&& g_switch_value
!= 0)
14776 as_bad (_("-G not supported in this configuration"));
14777 g_switch_value
= 0;
14780 if (mips_abi
== NO_ABI
)
14781 mips_abi
= MIPS_DEFAULT_ABI
;
14783 /* The following code determines the architecture.
14784 Similar code was added to GCC 3.3 (see override_options() in
14785 config/mips/mips.c). The GAS and GCC code should be kept in sync
14786 as much as possible. */
14788 if (mips_arch_string
!= 0)
14789 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14791 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14793 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14794 ISA level specified by -mipsN, while arch_info->isa contains
14795 the -march selection (if any). */
14796 if (arch_info
!= 0)
14798 /* -march takes precedence over -mipsN, since it is more descriptive.
14799 There's no harm in specifying both as long as the ISA levels
14801 if (file_mips_opts
.isa
!= arch_info
->isa
)
14802 as_bad (_("-%s conflicts with the other architecture options,"
14803 " which imply -%s"),
14804 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14805 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14808 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14811 if (arch_info
== 0)
14813 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14814 gas_assert (arch_info
);
14817 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14818 as_bad (_("-march=%s is not compatible with the selected ABI"),
14821 file_mips_opts
.arch
= arch_info
->cpu
;
14822 file_mips_opts
.isa
= arch_info
->isa
;
14824 /* Set up initial mips_opts state. */
14825 mips_opts
= file_mips_opts
;
14827 /* The register size inference code is now placed in
14828 file_mips_check_options. */
14830 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14832 if (mips_tune_string
!= 0)
14833 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14835 if (tune_info
== 0)
14836 mips_set_tune (arch_info
);
14838 mips_set_tune (tune_info
);
14840 if (mips_flag_mdebug
< 0)
14841 mips_flag_mdebug
= 0;
14845 mips_init_after_args (void)
14847 /* initialize opcodes */
14848 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14849 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14853 md_pcrel_from (fixS
*fixP
)
14855 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14856 switch (fixP
->fx_r_type
)
14858 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14859 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14860 /* Return the address of the delay slot. */
14863 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14864 case BFD_RELOC_MICROMIPS_JMP
:
14865 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14866 case BFD_RELOC_16_PCREL_S2
:
14867 case BFD_RELOC_MIPS_21_PCREL_S2
:
14868 case BFD_RELOC_MIPS_26_PCREL_S2
:
14869 case BFD_RELOC_MIPS_JMP
:
14870 /* Return the address of the delay slot. */
14873 case BFD_RELOC_MIPS_18_PCREL_S3
:
14874 /* Return the aligned address of the doubleword containing
14875 the instruction. */
14883 /* This is called before the symbol table is processed. In order to
14884 work with gcc when using mips-tfile, we must keep all local labels.
14885 However, in other cases, we want to discard them. If we were
14886 called with -g, but we didn't see any debugging information, it may
14887 mean that gcc is smuggling debugging information through to
14888 mips-tfile, in which case we must generate all local labels. */
14891 mips_frob_file_before_adjust (void)
14893 #ifndef NO_ECOFF_DEBUGGING
14894 if (ECOFF_DEBUGGING
14896 && ! ecoff_debugging_seen
)
14897 flag_keep_locals
= 1;
14901 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14902 the corresponding LO16 reloc. This is called before md_apply_fix and
14903 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14904 relocation operators.
14906 For our purposes, a %lo() expression matches a %got() or %hi()
14909 (a) it refers to the same symbol; and
14910 (b) the offset applied in the %lo() expression is no lower than
14911 the offset applied in the %got() or %hi().
14913 (b) allows us to cope with code like:
14916 lh $4,%lo(foo+2)($4)
14918 ...which is legal on RELA targets, and has a well-defined behaviour
14919 if the user knows that adding 2 to "foo" will not induce a carry to
14922 When several %lo()s match a particular %got() or %hi(), we use the
14923 following rules to distinguish them:
14925 (1) %lo()s with smaller offsets are a better match than %lo()s with
14928 (2) %lo()s with no matching %got() or %hi() are better than those
14929 that already have a matching %got() or %hi().
14931 (3) later %lo()s are better than earlier %lo()s.
14933 These rules are applied in order.
14935 (1) means, among other things, that %lo()s with identical offsets are
14936 chosen if they exist.
14938 (2) means that we won't associate several high-part relocations with
14939 the same low-part relocation unless there's no alternative. Having
14940 several high parts for the same low part is a GNU extension; this rule
14941 allows careful users to avoid it.
14943 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14944 with the last high-part relocation being at the front of the list.
14945 It therefore makes sense to choose the last matching low-part
14946 relocation, all other things being equal. It's also easier
14947 to code that way. */
14950 mips_frob_file (void)
14952 struct mips_hi_fixup
*l
;
14953 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14955 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14957 segment_info_type
*seginfo
;
14958 bfd_boolean matched_lo_p
;
14959 fixS
**hi_pos
, **lo_pos
, **pos
;
14961 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14963 /* If a GOT16 relocation turns out to be against a global symbol,
14964 there isn't supposed to be a matching LO. Ignore %gots against
14965 constants; we'll report an error for those later. */
14966 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14967 && !(l
->fixp
->fx_addsy
14968 && pic_need_relax (l
->fixp
->fx_addsy
)))
14971 /* Check quickly whether the next fixup happens to be a matching %lo. */
14972 if (fixup_has_matching_lo_p (l
->fixp
))
14975 seginfo
= seg_info (l
->seg
);
14977 /* Set HI_POS to the position of this relocation in the chain.
14978 Set LO_POS to the position of the chosen low-part relocation.
14979 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14980 relocation that matches an immediately-preceding high-part
14984 matched_lo_p
= FALSE
;
14985 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14987 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14989 if (*pos
== l
->fixp
)
14992 if ((*pos
)->fx_r_type
== looking_for_rtype
14993 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14994 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14996 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14998 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15001 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15002 && fixup_has_matching_lo_p (*pos
));
15005 /* If we found a match, remove the high-part relocation from its
15006 current position and insert it before the low-part relocation.
15007 Make the offsets match so that fixup_has_matching_lo_p()
15010 We don't warn about unmatched high-part relocations since some
15011 versions of gcc have been known to emit dead "lui ...%hi(...)"
15013 if (lo_pos
!= NULL
)
15015 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15016 if (l
->fixp
->fx_next
!= *lo_pos
)
15018 *hi_pos
= l
->fixp
->fx_next
;
15019 l
->fixp
->fx_next
= *lo_pos
;
15027 mips_force_relocation (fixS
*fixp
)
15029 if (generic_force_reloc (fixp
))
15032 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15033 so that the linker relaxation can update targets. */
15034 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15035 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15036 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15039 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15040 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15041 microMIPS symbols so that we can do cross-mode branch diagnostics
15042 and BAL to JALX conversion by the linker. */
15043 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15044 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15045 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15047 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15050 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15051 if (ISA_IS_R6 (file_mips_opts
.isa
)
15052 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15053 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15054 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15055 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15056 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15057 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15058 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15064 /* Implement TC_FORCE_RELOCATION_ABS. */
15067 mips_force_relocation_abs (fixS
*fixp
)
15069 if (generic_force_reloc (fixp
))
15072 /* These relocations do not have enough bits in the in-place addend
15073 to hold an arbitrary absolute section's offset. */
15074 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15080 /* Read the instruction associated with RELOC from BUF. */
15082 static unsigned int
15083 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15085 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15086 return read_compressed_insn (buf
, 4);
15088 return read_insn (buf
);
15091 /* Write instruction INSN to BUF, given that it has been relocated
15095 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15096 unsigned long insn
)
15098 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15099 write_compressed_insn (buf
, insn
, 4);
15101 write_insn (buf
, insn
);
15104 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15105 to a symbol in another ISA mode, which cannot be converted to JALX. */
15108 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15110 unsigned long opcode
;
15114 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15117 other
= S_GET_OTHER (fixP
->fx_addsy
);
15118 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15119 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15120 switch (fixP
->fx_r_type
)
15122 case BFD_RELOC_MIPS_JMP
:
15123 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15124 case BFD_RELOC_MICROMIPS_JMP
:
15125 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15131 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15132 jump to a symbol in the same ISA mode. */
15135 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15137 unsigned long opcode
;
15141 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15144 other
= S_GET_OTHER (fixP
->fx_addsy
);
15145 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15146 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15147 switch (fixP
->fx_r_type
)
15149 case BFD_RELOC_MIPS_JMP
:
15150 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15151 case BFD_RELOC_MIPS16_JMP
:
15152 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15153 case BFD_RELOC_MICROMIPS_JMP
:
15154 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15160 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15161 to a symbol whose value plus addend is not aligned according to the
15162 ultimate (after linker relaxation) jump instruction's immediate field
15163 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15164 regular MIPS code, to (1 << 2). */
15167 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15169 bfd_boolean micro_to_mips_p
;
15173 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15176 other
= S_GET_OTHER (fixP
->fx_addsy
);
15177 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15178 val
+= fixP
->fx_offset
;
15179 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15180 && !ELF_ST_IS_MICROMIPS (other
));
15181 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15182 != ELF_ST_IS_COMPRESSED (other
));
15185 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15186 to a symbol whose annotation indicates another ISA mode. For absolute
15187 symbols check the ISA bit instead.
15189 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15190 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15191 MIPS symbols and associated with BAL instructions as these instructions
15192 may be be converted to JALX by the linker. */
15195 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15197 bfd_boolean absolute_p
;
15198 unsigned long opcode
;
15204 if (mips_ignore_branch_isa
)
15207 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15210 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15211 absolute_p
= bfd_is_abs_section (symsec
);
15213 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15214 other
= S_GET_OTHER (fixP
->fx_addsy
);
15216 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15217 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15218 switch (fixP
->fx_r_type
)
15220 case BFD_RELOC_16_PCREL_S2
:
15221 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15222 && opcode
!= 0x0411);
15223 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15224 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15225 && opcode
!= 0x4060);
15226 case BFD_RELOC_MIPS_21_PCREL_S2
:
15227 case BFD_RELOC_MIPS_26_PCREL_S2
:
15228 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15229 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15230 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15231 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15232 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15233 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15239 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15240 branch instruction pointed to by FIXP is not aligned according to the
15241 branch instruction's immediate field requirement. We need the addend
15242 to preserve the ISA bit and also the sum must not have bit 2 set. We
15243 must explicitly OR in the ISA bit from symbol annotation as the bit
15244 won't be set in the symbol's value then. */
15247 fix_bad_misaligned_branch_p (fixS
*fixP
)
15249 bfd_boolean absolute_p
;
15256 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15259 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15260 absolute_p
= bfd_is_abs_section (symsec
);
15262 val
= S_GET_VALUE (fixP
->fx_addsy
);
15263 other
= S_GET_OTHER (fixP
->fx_addsy
);
15264 off
= fixP
->fx_offset
;
15266 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15267 val
|= ELF_ST_IS_COMPRESSED (other
);
15269 return (val
& 0x3) != isa_bit
;
15272 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15273 and its calculated value VAL. */
15276 fix_validate_branch (fixS
*fixP
, valueT val
)
15278 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15280 _("branch to misaligned address (0x%lx)"),
15281 (long) (val
+ md_pcrel_from (fixP
)));
15282 else if (fix_bad_cross_mode_branch_p (fixP
))
15283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15284 _("branch to a symbol in another ISA mode"));
15285 else if (fix_bad_misaligned_branch_p (fixP
))
15286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15287 _("branch to misaligned address (0x%lx)"),
15288 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15289 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15290 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15291 _("cannot encode misaligned addend "
15292 "in the relocatable field (0x%lx)"),
15293 (long) fixP
->fx_offset
);
15296 /* Apply a fixup to the object file. */
15299 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15302 unsigned long insn
;
15303 reloc_howto_type
*howto
;
15305 if (fixP
->fx_pcrel
)
15306 switch (fixP
->fx_r_type
)
15308 case BFD_RELOC_16_PCREL_S2
:
15309 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15310 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15311 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15312 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15313 case BFD_RELOC_32_PCREL
:
15314 case BFD_RELOC_MIPS_21_PCREL_S2
:
15315 case BFD_RELOC_MIPS_26_PCREL_S2
:
15316 case BFD_RELOC_MIPS_18_PCREL_S3
:
15317 case BFD_RELOC_MIPS_19_PCREL_S2
:
15318 case BFD_RELOC_HI16_S_PCREL
:
15319 case BFD_RELOC_LO16_PCREL
:
15323 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15328 _("PC-relative reference to a different section"));
15332 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15333 that have no MIPS ELF equivalent. */
15334 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15336 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15341 gas_assert (fixP
->fx_size
== 2
15342 || fixP
->fx_size
== 4
15343 || fixP
->fx_r_type
== BFD_RELOC_8
15344 || fixP
->fx_r_type
== BFD_RELOC_16
15345 || fixP
->fx_r_type
== BFD_RELOC_64
15346 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15347 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15348 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15349 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15350 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15351 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15352 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15354 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15356 /* Don't treat parts of a composite relocation as done. There are two
15359 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15360 should nevertheless be emitted if the first part is.
15362 (2) In normal usage, composite relocations are never assembly-time
15363 constants. The easiest way of dealing with the pathological
15364 exceptions is to generate a relocation against STN_UNDEF and
15365 leave everything up to the linker. */
15366 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15369 switch (fixP
->fx_r_type
)
15371 case BFD_RELOC_MIPS_TLS_GD
:
15372 case BFD_RELOC_MIPS_TLS_LDM
:
15373 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15374 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15375 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15376 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15377 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15378 case BFD_RELOC_MIPS_TLS_TPREL32
:
15379 case BFD_RELOC_MIPS_TLS_TPREL64
:
15380 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15381 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15382 case BFD_RELOC_MICROMIPS_TLS_GD
:
15383 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15384 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15385 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15386 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15387 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15388 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15389 case BFD_RELOC_MIPS16_TLS_GD
:
15390 case BFD_RELOC_MIPS16_TLS_LDM
:
15391 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15392 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15393 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15394 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15395 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15396 if (fixP
->fx_addsy
)
15397 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15400 _("TLS relocation against a constant"));
15403 case BFD_RELOC_MIPS_JMP
:
15404 case BFD_RELOC_MIPS16_JMP
:
15405 case BFD_RELOC_MICROMIPS_JMP
:
15409 gas_assert (!fixP
->fx_done
);
15411 /* Shift is 2, unusually, for microMIPS JALX. */
15412 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15413 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15418 if (fix_bad_cross_mode_jump_p (fixP
))
15419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15420 _("jump to a symbol in another ISA mode"));
15421 else if (fix_bad_same_mode_jalx_p (fixP
))
15422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15423 _("JALX to a symbol in the same ISA mode"));
15424 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15426 _("jump to misaligned address (0x%lx)"),
15427 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15428 + fixP
->fx_offset
));
15429 else if (HAVE_IN_PLACE_ADDENDS
15430 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15432 _("cannot encode misaligned addend "
15433 "in the relocatable field (0x%lx)"),
15434 (long) fixP
->fx_offset
);
15436 /* Fall through. */
15438 case BFD_RELOC_MIPS_SHIFT5
:
15439 case BFD_RELOC_MIPS_SHIFT6
:
15440 case BFD_RELOC_MIPS_GOT_DISP
:
15441 case BFD_RELOC_MIPS_GOT_PAGE
:
15442 case BFD_RELOC_MIPS_GOT_OFST
:
15443 case BFD_RELOC_MIPS_SUB
:
15444 case BFD_RELOC_MIPS_INSERT_A
:
15445 case BFD_RELOC_MIPS_INSERT_B
:
15446 case BFD_RELOC_MIPS_DELETE
:
15447 case BFD_RELOC_MIPS_HIGHEST
:
15448 case BFD_RELOC_MIPS_HIGHER
:
15449 case BFD_RELOC_MIPS_SCN_DISP
:
15450 case BFD_RELOC_MIPS_REL16
:
15451 case BFD_RELOC_MIPS_RELGOT
:
15452 case BFD_RELOC_MIPS_JALR
:
15453 case BFD_RELOC_HI16
:
15454 case BFD_RELOC_HI16_S
:
15455 case BFD_RELOC_LO16
:
15456 case BFD_RELOC_GPREL16
:
15457 case BFD_RELOC_MIPS_LITERAL
:
15458 case BFD_RELOC_MIPS_CALL16
:
15459 case BFD_RELOC_MIPS_GOT16
:
15460 case BFD_RELOC_GPREL32
:
15461 case BFD_RELOC_MIPS_GOT_HI16
:
15462 case BFD_RELOC_MIPS_GOT_LO16
:
15463 case BFD_RELOC_MIPS_CALL_HI16
:
15464 case BFD_RELOC_MIPS_CALL_LO16
:
15465 case BFD_RELOC_HI16_S_PCREL
:
15466 case BFD_RELOC_LO16_PCREL
:
15467 case BFD_RELOC_MIPS16_GPREL
:
15468 case BFD_RELOC_MIPS16_GOT16
:
15469 case BFD_RELOC_MIPS16_CALL16
:
15470 case BFD_RELOC_MIPS16_HI16
:
15471 case BFD_RELOC_MIPS16_HI16_S
:
15472 case BFD_RELOC_MIPS16_LO16
:
15473 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15474 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15475 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15476 case BFD_RELOC_MICROMIPS_SUB
:
15477 case BFD_RELOC_MICROMIPS_HIGHEST
:
15478 case BFD_RELOC_MICROMIPS_HIGHER
:
15479 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15480 case BFD_RELOC_MICROMIPS_JALR
:
15481 case BFD_RELOC_MICROMIPS_HI16
:
15482 case BFD_RELOC_MICROMIPS_HI16_S
:
15483 case BFD_RELOC_MICROMIPS_LO16
:
15484 case BFD_RELOC_MICROMIPS_GPREL16
:
15485 case BFD_RELOC_MICROMIPS_LITERAL
:
15486 case BFD_RELOC_MICROMIPS_CALL16
:
15487 case BFD_RELOC_MICROMIPS_GOT16
:
15488 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15489 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15490 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15491 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15492 case BFD_RELOC_MIPS_EH
:
15497 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15499 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15500 if (mips16_reloc_p (fixP
->fx_r_type
))
15501 insn
|= mips16_immed_extend (value
, 16);
15503 insn
|= (value
& 0xffff);
15504 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15508 _("unsupported constant in relocation"));
15513 /* This is handled like BFD_RELOC_32, but we output a sign
15514 extended value if we are only 32 bits. */
15517 if (8 <= sizeof (valueT
))
15518 md_number_to_chars (buf
, *valP
, 8);
15523 if ((*valP
& 0x80000000) != 0)
15527 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15528 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15533 case BFD_RELOC_RVA
:
15535 case BFD_RELOC_32_PCREL
:
15538 /* If we are deleting this reloc entry, we must fill in the
15539 value now. This can happen if we have a .word which is not
15540 resolved when it appears but is later defined. */
15542 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15545 case BFD_RELOC_MIPS_21_PCREL_S2
:
15546 fix_validate_branch (fixP
, *valP
);
15547 if (!fixP
->fx_done
)
15550 if (*valP
+ 0x400000 <= 0x7fffff)
15552 insn
= read_insn (buf
);
15553 insn
|= (*valP
>> 2) & 0x1fffff;
15554 write_insn (buf
, insn
);
15557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15558 _("branch out of range"));
15561 case BFD_RELOC_MIPS_26_PCREL_S2
:
15562 fix_validate_branch (fixP
, *valP
);
15563 if (!fixP
->fx_done
)
15566 if (*valP
+ 0x8000000 <= 0xfffffff)
15568 insn
= read_insn (buf
);
15569 insn
|= (*valP
>> 2) & 0x3ffffff;
15570 write_insn (buf
, insn
);
15573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15574 _("branch out of range"));
15577 case BFD_RELOC_MIPS_18_PCREL_S3
:
15578 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15580 _("PC-relative access using misaligned symbol (%lx)"),
15581 (long) S_GET_VALUE (fixP
->fx_addsy
));
15582 if ((fixP
->fx_offset
& 0x7) != 0)
15583 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15584 _("PC-relative access using misaligned offset (%lx)"),
15585 (long) fixP
->fx_offset
);
15586 if (!fixP
->fx_done
)
15589 if (*valP
+ 0x100000 <= 0x1fffff)
15591 insn
= read_insn (buf
);
15592 insn
|= (*valP
>> 3) & 0x3ffff;
15593 write_insn (buf
, insn
);
15596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15597 _("PC-relative access out of range"));
15600 case BFD_RELOC_MIPS_19_PCREL_S2
:
15601 if ((*valP
& 0x3) != 0)
15602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15603 _("PC-relative access to misaligned address (%lx)"),
15605 if (!fixP
->fx_done
)
15608 if (*valP
+ 0x100000 <= 0x1fffff)
15610 insn
= read_insn (buf
);
15611 insn
|= (*valP
>> 2) & 0x7ffff;
15612 write_insn (buf
, insn
);
15615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15616 _("PC-relative access out of range"));
15619 case BFD_RELOC_16_PCREL_S2
:
15620 fix_validate_branch (fixP
, *valP
);
15622 /* We need to save the bits in the instruction since fixup_segment()
15623 might be deleting the relocation entry (i.e., a branch within
15624 the current segment). */
15625 if (! fixP
->fx_done
)
15628 /* Update old instruction data. */
15629 insn
= read_insn (buf
);
15631 if (*valP
+ 0x20000 <= 0x3ffff)
15633 insn
|= (*valP
>> 2) & 0xffff;
15634 write_insn (buf
, insn
);
15636 else if (fixP
->fx_tcbit2
15638 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15639 && (fixP
->fx_frag
->fr_address
15640 < text_section
->vma
+ bfd_get_section_size (text_section
))
15641 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15642 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15643 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15645 /* The branch offset is too large. If this is an
15646 unconditional branch, and we are not generating PIC code,
15647 we can convert it to an absolute jump instruction. */
15648 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15649 insn
= 0x0c000000; /* jal */
15651 insn
= 0x08000000; /* j */
15652 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15654 fixP
->fx_addsy
= section_symbol (text_section
);
15655 *valP
+= md_pcrel_from (fixP
);
15656 write_insn (buf
, insn
);
15660 /* If we got here, we have branch-relaxation disabled,
15661 and there's nothing we can do to fix this instruction
15662 without turning it into a longer sequence. */
15663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15664 _("branch out of range"));
15668 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15669 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15670 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15671 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15672 gas_assert (!fixP
->fx_done
);
15673 if (fix_bad_cross_mode_branch_p (fixP
))
15674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15675 _("branch to a symbol in another ISA mode"));
15676 else if (fixP
->fx_addsy
15677 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15678 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15679 && (fixP
->fx_offset
& 0x1) != 0)
15680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15681 _("branch to misaligned address (0x%lx)"),
15682 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15683 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15685 _("cannot encode misaligned addend "
15686 "in the relocatable field (0x%lx)"),
15687 (long) fixP
->fx_offset
);
15690 case BFD_RELOC_VTABLE_INHERIT
:
15693 && !S_IS_DEFINED (fixP
->fx_addsy
)
15694 && !S_IS_WEAK (fixP
->fx_addsy
))
15695 S_SET_WEAK (fixP
->fx_addsy
);
15698 case BFD_RELOC_NONE
:
15699 case BFD_RELOC_VTABLE_ENTRY
:
15707 /* Remember value for tc_gen_reloc. */
15708 fixP
->fx_addnumber
= *valP
;
15718 c
= get_symbol_name (&name
);
15719 p
= (symbolS
*) symbol_find_or_make (name
);
15720 (void) restore_line_pointer (c
);
15724 /* Align the current frag to a given power of two. If a particular
15725 fill byte should be used, FILL points to an integer that contains
15726 that byte, otherwise FILL is null.
15728 This function used to have the comment:
15730 The MIPS assembler also automatically adjusts any preceding label.
15732 The implementation therefore applied the adjustment to a maximum of
15733 one label. However, other label adjustments are applied to batches
15734 of labels, and adjusting just one caused problems when new labels
15735 were added for the sake of debugging or unwind information.
15736 We therefore adjust all preceding labels (given as LABELS) instead. */
15739 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15741 mips_emit_delays ();
15742 mips_record_compressed_mode ();
15743 if (fill
== NULL
&& subseg_text_p (now_seg
))
15744 frag_align_code (to
, 0);
15746 frag_align (to
, fill
? *fill
: 0, 0);
15747 record_alignment (now_seg
, to
);
15748 mips_move_labels (labels
, FALSE
);
15751 /* Align to a given power of two. .align 0 turns off the automatic
15752 alignment used by the data creating pseudo-ops. */
15755 s_align (int x ATTRIBUTE_UNUSED
)
15757 int temp
, fill_value
, *fill_ptr
;
15758 long max_alignment
= 28;
15760 /* o Note that the assembler pulls down any immediately preceding label
15761 to the aligned address.
15762 o It's not documented but auto alignment is reinstated by
15763 a .align pseudo instruction.
15764 o Note also that after auto alignment is turned off the mips assembler
15765 issues an error on attempt to assemble an improperly aligned data item.
15768 temp
= get_absolute_expression ();
15769 if (temp
> max_alignment
)
15770 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15773 as_warn (_("alignment negative, 0 assumed"));
15776 if (*input_line_pointer
== ',')
15778 ++input_line_pointer
;
15779 fill_value
= get_absolute_expression ();
15780 fill_ptr
= &fill_value
;
15786 segment_info_type
*si
= seg_info (now_seg
);
15787 struct insn_label_list
*l
= si
->label_list
;
15788 /* Auto alignment should be switched on by next section change. */
15790 mips_align (temp
, fill_ptr
, l
);
15797 demand_empty_rest_of_line ();
15801 s_change_sec (int sec
)
15805 /* The ELF backend needs to know that we are changing sections, so
15806 that .previous works correctly. We could do something like check
15807 for an obj_section_change_hook macro, but that might be confusing
15808 as it would not be appropriate to use it in the section changing
15809 functions in read.c, since obj-elf.c intercepts those. FIXME:
15810 This should be cleaner, somehow. */
15811 obj_elf_section_change_hook ();
15813 mips_emit_delays ();
15824 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15825 demand_empty_rest_of_line ();
15829 seg
= subseg_new (RDATA_SECTION_NAME
,
15830 (subsegT
) get_absolute_expression ());
15831 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15832 | SEC_READONLY
| SEC_RELOC
15834 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15835 record_alignment (seg
, 4);
15836 demand_empty_rest_of_line ();
15840 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15841 bfd_set_section_flags (stdoutput
, seg
,
15842 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15843 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15844 record_alignment (seg
, 4);
15845 demand_empty_rest_of_line ();
15849 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15850 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15851 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15852 record_alignment (seg
, 4);
15853 demand_empty_rest_of_line ();
15861 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15864 char *section_name
;
15869 int section_entry_size
;
15870 int section_alignment
;
15872 saved_ilp
= input_line_pointer
;
15873 endc
= get_symbol_name (§ion_name
);
15874 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15876 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15878 /* Do we have .section Name<,"flags">? */
15879 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15881 /* Just after name is now '\0'. */
15882 (void) restore_line_pointer (endc
);
15883 input_line_pointer
= saved_ilp
;
15884 obj_elf_section (ignore
);
15888 section_name
= xstrdup (section_name
);
15889 c
= restore_line_pointer (endc
);
15891 input_line_pointer
++;
15893 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15895 section_type
= get_absolute_expression ();
15899 if (*input_line_pointer
++ == ',')
15900 section_flag
= get_absolute_expression ();
15904 if (*input_line_pointer
++ == ',')
15905 section_entry_size
= get_absolute_expression ();
15907 section_entry_size
= 0;
15909 if (*input_line_pointer
++ == ',')
15910 section_alignment
= get_absolute_expression ();
15912 section_alignment
= 0;
15914 /* FIXME: really ignore? */
15915 (void) section_alignment
;
15917 /* When using the generic form of .section (as implemented by obj-elf.c),
15918 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15919 traditionally had to fall back on the more common @progbits instead.
15921 There's nothing really harmful in this, since bfd will correct
15922 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15923 means that, for backwards compatibility, the special_section entries
15924 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15926 Even so, we shouldn't force users of the MIPS .section syntax to
15927 incorrectly label the sections as SHT_PROGBITS. The best compromise
15928 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15929 generic type-checking code. */
15930 if (section_type
== SHT_MIPS_DWARF
)
15931 section_type
= SHT_PROGBITS
;
15933 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
15934 section_entry_size
, 0, 0, 0);
15936 if (now_seg
->name
!= section_name
)
15937 free (section_name
);
15941 mips_enable_auto_align (void)
15947 s_cons (int log_size
)
15949 segment_info_type
*si
= seg_info (now_seg
);
15950 struct insn_label_list
*l
= si
->label_list
;
15952 mips_emit_delays ();
15953 if (log_size
> 0 && auto_align
)
15954 mips_align (log_size
, 0, l
);
15955 cons (1 << log_size
);
15956 mips_clear_insn_labels ();
15960 s_float_cons (int type
)
15962 segment_info_type
*si
= seg_info (now_seg
);
15963 struct insn_label_list
*l
= si
->label_list
;
15965 mips_emit_delays ();
15970 mips_align (3, 0, l
);
15972 mips_align (2, 0, l
);
15976 mips_clear_insn_labels ();
15979 /* Handle .globl. We need to override it because on Irix 5 you are
15982 where foo is an undefined symbol, to mean that foo should be
15983 considered to be the address of a function. */
15986 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15995 c
= get_symbol_name (&name
);
15996 symbolP
= symbol_find_or_make (name
);
15997 S_SET_EXTERNAL (symbolP
);
15999 *input_line_pointer
= c
;
16000 SKIP_WHITESPACE_AFTER_NAME ();
16002 /* On Irix 5, every global symbol that is not explicitly labelled as
16003 being a function is apparently labelled as being an object. */
16006 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16007 && (*input_line_pointer
!= ','))
16012 c
= get_symbol_name (&secname
);
16013 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16015 as_bad (_("%s: no such section"), secname
);
16016 (void) restore_line_pointer (c
);
16018 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16019 flag
= BSF_FUNCTION
;
16022 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16024 c
= *input_line_pointer
;
16027 input_line_pointer
++;
16028 SKIP_WHITESPACE ();
16029 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16035 demand_empty_rest_of_line ();
16039 s_option (int x ATTRIBUTE_UNUSED
)
16044 c
= get_symbol_name (&opt
);
16048 /* FIXME: What does this mean? */
16050 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16054 i
= atoi (opt
+ 3);
16055 if (i
!= 0 && i
!= 2)
16056 as_bad (_(".option pic%d not supported"), i
);
16057 else if (mips_pic
== VXWORKS_PIC
)
16058 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16063 mips_pic
= SVR4_PIC
;
16064 mips_abicalls
= TRUE
;
16067 if (mips_pic
== SVR4_PIC
)
16069 if (g_switch_seen
&& g_switch_value
!= 0)
16070 as_warn (_("-G may not be used with SVR4 PIC code"));
16071 g_switch_value
= 0;
16072 bfd_set_gp_size (stdoutput
, 0);
16076 as_warn (_("unrecognized option \"%s\""), opt
);
16078 (void) restore_line_pointer (c
);
16079 demand_empty_rest_of_line ();
16082 /* This structure is used to hold a stack of .set values. */
16084 struct mips_option_stack
16086 struct mips_option_stack
*next
;
16087 struct mips_set_options options
;
16090 static struct mips_option_stack
*mips_opts_stack
;
16092 /* Return status for .set/.module option handling. */
16094 enum code_option_type
16096 /* Unrecognized option. */
16097 OPTION_TYPE_BAD
= -1,
16099 /* Ordinary option. */
16100 OPTION_TYPE_NORMAL
,
16102 /* ISA changing option. */
16106 /* Handle common .set/.module options. Return status indicating option
16109 static enum code_option_type
16110 parse_code_option (char * name
)
16112 bfd_boolean isa_set
= FALSE
;
16113 const struct mips_ase
*ase
;
16115 if (strncmp (name
, "at=", 3) == 0)
16117 char *s
= name
+ 3;
16119 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16120 as_bad (_("unrecognized register name `%s'"), s
);
16122 else if (strcmp (name
, "at") == 0)
16123 mips_opts
.at
= ATREG
;
16124 else if (strcmp (name
, "noat") == 0)
16125 mips_opts
.at
= ZERO
;
16126 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16127 mips_opts
.nomove
= 0;
16128 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16129 mips_opts
.nomove
= 1;
16130 else if (strcmp (name
, "bopt") == 0)
16131 mips_opts
.nobopt
= 0;
16132 else if (strcmp (name
, "nobopt") == 0)
16133 mips_opts
.nobopt
= 1;
16134 else if (strcmp (name
, "gp=32") == 0)
16136 else if (strcmp (name
, "gp=64") == 0)
16138 else if (strcmp (name
, "fp=32") == 0)
16140 else if (strcmp (name
, "fp=xx") == 0)
16142 else if (strcmp (name
, "fp=64") == 0)
16144 else if (strcmp (name
, "softfloat") == 0)
16145 mips_opts
.soft_float
= 1;
16146 else if (strcmp (name
, "hardfloat") == 0)
16147 mips_opts
.soft_float
= 0;
16148 else if (strcmp (name
, "singlefloat") == 0)
16149 mips_opts
.single_float
= 1;
16150 else if (strcmp (name
, "doublefloat") == 0)
16151 mips_opts
.single_float
= 0;
16152 else if (strcmp (name
, "nooddspreg") == 0)
16153 mips_opts
.oddspreg
= 0;
16154 else if (strcmp (name
, "oddspreg") == 0)
16155 mips_opts
.oddspreg
= 1;
16156 else if (strcmp (name
, "mips16") == 0
16157 || strcmp (name
, "MIPS-16") == 0)
16158 mips_opts
.mips16
= 1;
16159 else if (strcmp (name
, "nomips16") == 0
16160 || strcmp (name
, "noMIPS-16") == 0)
16161 mips_opts
.mips16
= 0;
16162 else if (strcmp (name
, "micromips") == 0)
16163 mips_opts
.micromips
= 1;
16164 else if (strcmp (name
, "nomicromips") == 0)
16165 mips_opts
.micromips
= 0;
16166 else if (name
[0] == 'n'
16168 && (ase
= mips_lookup_ase (name
+ 2)))
16169 mips_set_ase (ase
, &mips_opts
, FALSE
);
16170 else if ((ase
= mips_lookup_ase (name
)))
16171 mips_set_ase (ase
, &mips_opts
, TRUE
);
16172 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16174 /* Permit the user to change the ISA and architecture on the fly.
16175 Needless to say, misuse can cause serious problems. */
16176 if (strncmp (name
, "arch=", 5) == 0)
16178 const struct mips_cpu_info
*p
;
16180 p
= mips_parse_cpu ("internal use", name
+ 5);
16182 as_bad (_("unknown architecture %s"), name
+ 5);
16185 mips_opts
.arch
= p
->cpu
;
16186 mips_opts
.isa
= p
->isa
;
16190 else if (strncmp (name
, "mips", 4) == 0)
16192 const struct mips_cpu_info
*p
;
16194 p
= mips_parse_cpu ("internal use", name
);
16196 as_bad (_("unknown ISA level %s"), name
+ 4);
16199 mips_opts
.arch
= p
->cpu
;
16200 mips_opts
.isa
= p
->isa
;
16205 as_bad (_("unknown ISA or architecture %s"), name
);
16207 else if (strcmp (name
, "autoextend") == 0)
16208 mips_opts
.noautoextend
= 0;
16209 else if (strcmp (name
, "noautoextend") == 0)
16210 mips_opts
.noautoextend
= 1;
16211 else if (strcmp (name
, "insn32") == 0)
16212 mips_opts
.insn32
= TRUE
;
16213 else if (strcmp (name
, "noinsn32") == 0)
16214 mips_opts
.insn32
= FALSE
;
16215 else if (strcmp (name
, "sym32") == 0)
16216 mips_opts
.sym32
= TRUE
;
16217 else if (strcmp (name
, "nosym32") == 0)
16218 mips_opts
.sym32
= FALSE
;
16220 return OPTION_TYPE_BAD
;
16222 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16225 /* Handle the .set pseudo-op. */
16228 s_mipsset (int x ATTRIBUTE_UNUSED
)
16230 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16231 char *name
= input_line_pointer
, ch
;
16233 file_mips_check_options ();
16235 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16236 ++input_line_pointer
;
16237 ch
= *input_line_pointer
;
16238 *input_line_pointer
= '\0';
16240 if (strchr (name
, ','))
16242 /* Generic ".set" directive; use the generic handler. */
16243 *input_line_pointer
= ch
;
16244 input_line_pointer
= name
;
16249 if (strcmp (name
, "reorder") == 0)
16251 if (mips_opts
.noreorder
)
16254 else if (strcmp (name
, "noreorder") == 0)
16256 if (!mips_opts
.noreorder
)
16257 start_noreorder ();
16259 else if (strcmp (name
, "macro") == 0)
16260 mips_opts
.warn_about_macros
= 0;
16261 else if (strcmp (name
, "nomacro") == 0)
16263 if (mips_opts
.noreorder
== 0)
16264 as_bad (_("`noreorder' must be set before `nomacro'"));
16265 mips_opts
.warn_about_macros
= 1;
16267 else if (strcmp (name
, "gp=default") == 0)
16268 mips_opts
.gp
= file_mips_opts
.gp
;
16269 else if (strcmp (name
, "fp=default") == 0)
16270 mips_opts
.fp
= file_mips_opts
.fp
;
16271 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16273 mips_opts
.isa
= file_mips_opts
.isa
;
16274 mips_opts
.arch
= file_mips_opts
.arch
;
16275 mips_opts
.gp
= file_mips_opts
.gp
;
16276 mips_opts
.fp
= file_mips_opts
.fp
;
16278 else if (strcmp (name
, "push") == 0)
16280 struct mips_option_stack
*s
;
16282 s
= XNEW (struct mips_option_stack
);
16283 s
->next
= mips_opts_stack
;
16284 s
->options
= mips_opts
;
16285 mips_opts_stack
= s
;
16287 else if (strcmp (name
, "pop") == 0)
16289 struct mips_option_stack
*s
;
16291 s
= mips_opts_stack
;
16293 as_bad (_(".set pop with no .set push"));
16296 /* If we're changing the reorder mode we need to handle
16297 delay slots correctly. */
16298 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16299 start_noreorder ();
16300 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16303 mips_opts
= s
->options
;
16304 mips_opts_stack
= s
->next
;
16310 type
= parse_code_option (name
);
16311 if (type
== OPTION_TYPE_BAD
)
16312 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16315 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16316 registers based on what is supported by the arch/cpu. */
16317 if (type
== OPTION_TYPE_ISA
)
16319 switch (mips_opts
.isa
)
16324 /* MIPS I cannot support FPXX. */
16326 /* fall-through. */
16333 if (mips_opts
.fp
!= 0)
16349 if (mips_opts
.fp
!= 0)
16351 if (mips_opts
.arch
== CPU_R5900
)
16358 as_bad (_("unknown ISA level %s"), name
+ 4);
16363 mips_check_options (&mips_opts
, FALSE
);
16365 mips_check_isa_supports_ases ();
16366 *input_line_pointer
= ch
;
16367 demand_empty_rest_of_line ();
16370 /* Handle the .module pseudo-op. */
16373 s_module (int ignore ATTRIBUTE_UNUSED
)
16375 char *name
= input_line_pointer
, ch
;
16377 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16378 ++input_line_pointer
;
16379 ch
= *input_line_pointer
;
16380 *input_line_pointer
= '\0';
16382 if (!file_mips_opts_checked
)
16384 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16385 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16387 /* Update module level settings from mips_opts. */
16388 file_mips_opts
= mips_opts
;
16391 as_bad (_(".module is not permitted after generating code"));
16393 *input_line_pointer
= ch
;
16394 demand_empty_rest_of_line ();
16397 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16398 .option pic2. It means to generate SVR4 PIC calls. */
16401 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16403 mips_pic
= SVR4_PIC
;
16404 mips_abicalls
= TRUE
;
16406 if (g_switch_seen
&& g_switch_value
!= 0)
16407 as_warn (_("-G may not be used with SVR4 PIC code"));
16408 g_switch_value
= 0;
16410 bfd_set_gp_size (stdoutput
, 0);
16411 demand_empty_rest_of_line ();
16414 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16415 PIC code. It sets the $gp register for the function based on the
16416 function address, which is in the register named in the argument.
16417 This uses a relocation against _gp_disp, which is handled specially
16418 by the linker. The result is:
16419 lui $gp,%hi(_gp_disp)
16420 addiu $gp,$gp,%lo(_gp_disp)
16421 addu $gp,$gp,.cpload argument
16422 The .cpload argument is normally $25 == $t9.
16424 The -mno-shared option changes this to:
16425 lui $gp,%hi(__gnu_local_gp)
16426 addiu $gp,$gp,%lo(__gnu_local_gp)
16427 and the argument is ignored. This saves an instruction, but the
16428 resulting code is not position independent; it uses an absolute
16429 address for __gnu_local_gp. Thus code assembled with -mno-shared
16430 can go into an ordinary executable, but not into a shared library. */
16433 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16439 file_mips_check_options ();
16441 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16442 .cpload is ignored. */
16443 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16449 if (mips_opts
.mips16
)
16451 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16452 ignore_rest_of_line ();
16456 /* .cpload should be in a .set noreorder section. */
16457 if (mips_opts
.noreorder
== 0)
16458 as_warn (_(".cpload not in noreorder section"));
16460 reg
= tc_get_register (0);
16462 /* If we need to produce a 64-bit address, we are better off using
16463 the default instruction sequence. */
16464 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16466 ex
.X_op
= O_symbol
;
16467 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16469 ex
.X_op_symbol
= NULL
;
16470 ex
.X_add_number
= 0;
16472 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16473 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16475 mips_mark_labels ();
16476 mips_assembling_insn
= TRUE
;
16479 macro_build_lui (&ex
, mips_gp_register
);
16480 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16481 mips_gp_register
, BFD_RELOC_LO16
);
16483 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16484 mips_gp_register
, reg
);
16487 mips_assembling_insn
= FALSE
;
16488 demand_empty_rest_of_line ();
16491 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16492 .cpsetup $reg1, offset|$reg2, label
16494 If offset is given, this results in:
16495 sd $gp, offset($sp)
16496 lui $gp, %hi(%neg(%gp_rel(label)))
16497 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16498 daddu $gp, $gp, $reg1
16500 If $reg2 is given, this results in:
16502 lui $gp, %hi(%neg(%gp_rel(label)))
16503 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16504 daddu $gp, $gp, $reg1
16505 $reg1 is normally $25 == $t9.
16507 The -mno-shared option replaces the last three instructions with
16509 addiu $gp,$gp,%lo(_gp) */
16512 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16514 expressionS ex_off
;
16515 expressionS ex_sym
;
16518 file_mips_check_options ();
16520 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16521 We also need NewABI support. */
16522 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16528 if (mips_opts
.mips16
)
16530 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16531 ignore_rest_of_line ();
16535 reg1
= tc_get_register (0);
16536 SKIP_WHITESPACE ();
16537 if (*input_line_pointer
!= ',')
16539 as_bad (_("missing argument separator ',' for .cpsetup"));
16543 ++input_line_pointer
;
16544 SKIP_WHITESPACE ();
16545 if (*input_line_pointer
== '$')
16547 mips_cpreturn_register
= tc_get_register (0);
16548 mips_cpreturn_offset
= -1;
16552 mips_cpreturn_offset
= get_absolute_expression ();
16553 mips_cpreturn_register
= -1;
16555 SKIP_WHITESPACE ();
16556 if (*input_line_pointer
!= ',')
16558 as_bad (_("missing argument separator ',' for .cpsetup"));
16562 ++input_line_pointer
;
16563 SKIP_WHITESPACE ();
16564 expression (&ex_sym
);
16566 mips_mark_labels ();
16567 mips_assembling_insn
= TRUE
;
16570 if (mips_cpreturn_register
== -1)
16572 ex_off
.X_op
= O_constant
;
16573 ex_off
.X_add_symbol
= NULL
;
16574 ex_off
.X_op_symbol
= NULL
;
16575 ex_off
.X_add_number
= mips_cpreturn_offset
;
16577 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16578 BFD_RELOC_LO16
, SP
);
16581 move_register (mips_cpreturn_register
, mips_gp_register
);
16583 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16585 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16586 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16589 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16590 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16591 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16593 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16594 mips_gp_register
, reg1
);
16600 ex
.X_op
= O_symbol
;
16601 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16602 ex
.X_op_symbol
= NULL
;
16603 ex
.X_add_number
= 0;
16605 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16606 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16608 macro_build_lui (&ex
, mips_gp_register
);
16609 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16610 mips_gp_register
, BFD_RELOC_LO16
);
16615 mips_assembling_insn
= FALSE
;
16616 demand_empty_rest_of_line ();
16620 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16622 file_mips_check_options ();
16624 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16625 .cplocal is ignored. */
16626 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16632 if (mips_opts
.mips16
)
16634 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16635 ignore_rest_of_line ();
16639 mips_gp_register
= tc_get_register (0);
16640 demand_empty_rest_of_line ();
16643 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16644 offset from $sp. The offset is remembered, and after making a PIC
16645 call $gp is restored from that location. */
16648 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16652 file_mips_check_options ();
16654 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16655 .cprestore is ignored. */
16656 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16662 if (mips_opts
.mips16
)
16664 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16665 ignore_rest_of_line ();
16669 mips_cprestore_offset
= get_absolute_expression ();
16670 mips_cprestore_valid
= 1;
16672 ex
.X_op
= O_constant
;
16673 ex
.X_add_symbol
= NULL
;
16674 ex
.X_op_symbol
= NULL
;
16675 ex
.X_add_number
= mips_cprestore_offset
;
16677 mips_mark_labels ();
16678 mips_assembling_insn
= TRUE
;
16681 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16682 SP
, HAVE_64BIT_ADDRESSES
);
16685 mips_assembling_insn
= FALSE
;
16686 demand_empty_rest_of_line ();
16689 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16690 was given in the preceding .cpsetup, it results in:
16691 ld $gp, offset($sp)
16693 If a register $reg2 was given there, it results in:
16694 or $gp, $reg2, $0 */
16697 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16701 file_mips_check_options ();
16703 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16704 We also need NewABI support. */
16705 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16711 if (mips_opts
.mips16
)
16713 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16714 ignore_rest_of_line ();
16718 mips_mark_labels ();
16719 mips_assembling_insn
= TRUE
;
16722 if (mips_cpreturn_register
== -1)
16724 ex
.X_op
= O_constant
;
16725 ex
.X_add_symbol
= NULL
;
16726 ex
.X_op_symbol
= NULL
;
16727 ex
.X_add_number
= mips_cpreturn_offset
;
16729 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16732 move_register (mips_gp_register
, mips_cpreturn_register
);
16736 mips_assembling_insn
= FALSE
;
16737 demand_empty_rest_of_line ();
16740 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16741 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16742 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16743 debug information or MIPS16 TLS. */
16746 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16747 bfd_reloc_code_real_type rtype
)
16754 if (ex
.X_op
!= O_symbol
)
16756 as_bad (_("unsupported use of %s"), dirstr
);
16757 ignore_rest_of_line ();
16760 p
= frag_more (bytes
);
16761 md_number_to_chars (p
, 0, bytes
);
16762 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16763 demand_empty_rest_of_line ();
16764 mips_clear_insn_labels ();
16767 /* Handle .dtprelword. */
16770 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16772 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16775 /* Handle .dtpreldword. */
16778 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16780 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16783 /* Handle .tprelword. */
16786 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16788 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16791 /* Handle .tpreldword. */
16794 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16796 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16799 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16800 code. It sets the offset to use in gp_rel relocations. */
16803 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16805 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16806 We also need NewABI support. */
16807 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16813 mips_gprel_offset
= get_absolute_expression ();
16815 demand_empty_rest_of_line ();
16818 /* Handle the .gpword pseudo-op. This is used when generating PIC
16819 code. It generates a 32 bit GP relative reloc. */
16822 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16824 segment_info_type
*si
;
16825 struct insn_label_list
*l
;
16829 /* When not generating PIC code, this is treated as .word. */
16830 if (mips_pic
!= SVR4_PIC
)
16836 si
= seg_info (now_seg
);
16837 l
= si
->label_list
;
16838 mips_emit_delays ();
16840 mips_align (2, 0, l
);
16843 mips_clear_insn_labels ();
16845 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16847 as_bad (_("unsupported use of .gpword"));
16848 ignore_rest_of_line ();
16852 md_number_to_chars (p
, 0, 4);
16853 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16854 BFD_RELOC_GPREL32
);
16856 demand_empty_rest_of_line ();
16860 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16862 segment_info_type
*si
;
16863 struct insn_label_list
*l
;
16867 /* When not generating PIC code, this is treated as .dword. */
16868 if (mips_pic
!= SVR4_PIC
)
16874 si
= seg_info (now_seg
);
16875 l
= si
->label_list
;
16876 mips_emit_delays ();
16878 mips_align (3, 0, l
);
16881 mips_clear_insn_labels ();
16883 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16885 as_bad (_("unsupported use of .gpdword"));
16886 ignore_rest_of_line ();
16890 md_number_to_chars (p
, 0, 8);
16891 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16892 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16894 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16895 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16896 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16898 demand_empty_rest_of_line ();
16901 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16902 tables. It generates a R_MIPS_EH reloc. */
16905 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16910 mips_emit_delays ();
16913 mips_clear_insn_labels ();
16915 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16917 as_bad (_("unsupported use of .ehword"));
16918 ignore_rest_of_line ();
16922 md_number_to_chars (p
, 0, 4);
16923 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16924 BFD_RELOC_32_PCREL
);
16926 demand_empty_rest_of_line ();
16929 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16930 tables in SVR4 PIC code. */
16933 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16937 file_mips_check_options ();
16939 /* This is ignored when not generating SVR4 PIC code. */
16940 if (mips_pic
!= SVR4_PIC
)
16946 mips_mark_labels ();
16947 mips_assembling_insn
= TRUE
;
16949 /* Add $gp to the register named as an argument. */
16951 reg
= tc_get_register (0);
16952 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16955 mips_assembling_insn
= FALSE
;
16956 demand_empty_rest_of_line ();
16959 /* Handle the .insn pseudo-op. This marks instruction labels in
16960 mips16/micromips mode. This permits the linker to handle them specially,
16961 such as generating jalx instructions when needed. We also make
16962 them odd for the duration of the assembly, in order to generate the
16963 right sort of code. We will make them even in the adjust_symtab
16964 routine, while leaving them marked. This is convenient for the
16965 debugger and the disassembler. The linker knows to make them odd
16969 s_insn (int ignore ATTRIBUTE_UNUSED
)
16971 file_mips_check_options ();
16972 file_ase_mips16
|= mips_opts
.mips16
;
16973 file_ase_micromips
|= mips_opts
.micromips
;
16975 mips_mark_labels ();
16977 demand_empty_rest_of_line ();
16980 /* Handle the .nan pseudo-op. */
16983 s_nan (int ignore ATTRIBUTE_UNUSED
)
16985 static const char str_legacy
[] = "legacy";
16986 static const char str_2008
[] = "2008";
16989 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16991 if (i
== sizeof (str_2008
) - 1
16992 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16994 else if (i
== sizeof (str_legacy
) - 1
16995 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16997 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17000 as_bad (_("`%s' does not support legacy NaN"),
17001 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17004 as_bad (_("bad .nan directive"));
17006 input_line_pointer
+= i
;
17007 demand_empty_rest_of_line ();
17010 /* Handle a .stab[snd] directive. Ideally these directives would be
17011 implemented in a transparent way, so that removing them would not
17012 have any effect on the generated instructions. However, s_stab
17013 internally changes the section, so in practice we need to decide
17014 now whether the preceding label marks compressed code. We do not
17015 support changing the compression mode of a label after a .stab*
17016 directive, such as in:
17022 so the current mode wins. */
17025 s_mips_stab (int type
)
17027 mips_mark_labels ();
17031 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17034 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17041 c
= get_symbol_name (&name
);
17042 symbolP
= symbol_find_or_make (name
);
17043 S_SET_WEAK (symbolP
);
17044 *input_line_pointer
= c
;
17046 SKIP_WHITESPACE_AFTER_NAME ();
17048 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17050 if (S_IS_DEFINED (symbolP
))
17052 as_bad (_("ignoring attempt to redefine symbol %s"),
17053 S_GET_NAME (symbolP
));
17054 ignore_rest_of_line ();
17058 if (*input_line_pointer
== ',')
17060 ++input_line_pointer
;
17061 SKIP_WHITESPACE ();
17065 if (exp
.X_op
!= O_symbol
)
17067 as_bad (_("bad .weakext directive"));
17068 ignore_rest_of_line ();
17071 symbol_set_value_expression (symbolP
, &exp
);
17074 demand_empty_rest_of_line ();
17077 /* Parse a register string into a number. Called from the ECOFF code
17078 to parse .frame. The argument is non-zero if this is the frame
17079 register, so that we can record it in mips_frame_reg. */
17082 tc_get_register (int frame
)
17086 SKIP_WHITESPACE ();
17087 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17091 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17092 mips_frame_reg_valid
= 1;
17093 mips_cprestore_valid
= 0;
17099 md_section_align (asection
*seg
, valueT addr
)
17101 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17103 /* We don't need to align ELF sections to the full alignment.
17104 However, Irix 5 may prefer that we align them at least to a 16
17105 byte boundary. We don't bother to align the sections if we
17106 are targeted for an embedded system. */
17107 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17112 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17115 /* Utility routine, called from above as well. If called while the
17116 input file is still being read, it's only an approximation. (For
17117 example, a symbol may later become defined which appeared to be
17118 undefined earlier.) */
17121 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17126 if (g_switch_value
> 0)
17128 const char *symname
;
17131 /* Find out whether this symbol can be referenced off the $gp
17132 register. It can be if it is smaller than the -G size or if
17133 it is in the .sdata or .sbss section. Certain symbols can
17134 not be referenced off the $gp, although it appears as though
17136 symname
= S_GET_NAME (sym
);
17137 if (symname
!= (const char *) NULL
17138 && (strcmp (symname
, "eprol") == 0
17139 || strcmp (symname
, "etext") == 0
17140 || strcmp (symname
, "_gp") == 0
17141 || strcmp (symname
, "edata") == 0
17142 || strcmp (symname
, "_fbss") == 0
17143 || strcmp (symname
, "_fdata") == 0
17144 || strcmp (symname
, "_ftext") == 0
17145 || strcmp (symname
, "end") == 0
17146 || strcmp (symname
, "_gp_disp") == 0))
17148 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17150 #ifndef NO_ECOFF_DEBUGGING
17151 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17152 && (symbol_get_obj (sym
)->ecoff_extern_size
17153 <= g_switch_value
))
17155 /* We must defer this decision until after the whole
17156 file has been read, since there might be a .extern
17157 after the first use of this symbol. */
17158 || (before_relaxing
17159 #ifndef NO_ECOFF_DEBUGGING
17160 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17162 && S_GET_VALUE (sym
) == 0)
17163 || (S_GET_VALUE (sym
) != 0
17164 && S_GET_VALUE (sym
) <= g_switch_value
)))
17168 const char *segname
;
17170 segname
= segment_name (S_GET_SEGMENT (sym
));
17171 gas_assert (strcmp (segname
, ".lit8") != 0
17172 && strcmp (segname
, ".lit4") != 0);
17173 change
= (strcmp (segname
, ".sdata") != 0
17174 && strcmp (segname
, ".sbss") != 0
17175 && strncmp (segname
, ".sdata.", 7) != 0
17176 && strncmp (segname
, ".sbss.", 6) != 0
17177 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17178 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17183 /* We are not optimizing for the $gp register. */
17188 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17191 pic_need_relax (symbolS
*sym
)
17195 /* Handle the case of a symbol equated to another symbol. */
17196 while (symbol_equated_reloc_p (sym
))
17200 /* It's possible to get a loop here in a badly written program. */
17201 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17207 if (symbol_section_p (sym
))
17210 symsec
= S_GET_SEGMENT (sym
);
17212 /* This must duplicate the test in adjust_reloc_syms. */
17213 return (!bfd_is_und_section (symsec
)
17214 && !bfd_is_abs_section (symsec
)
17215 && !bfd_is_com_section (symsec
)
17216 /* A global or weak symbol is treated as external. */
17217 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17220 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17221 convert a section-relative value VAL to the equivalent PC-relative
17225 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17226 offsetT val
, long stretch
)
17231 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17233 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17235 /* If the relax_marker of the symbol fragment differs from the
17236 relax_marker of this fragment, we have not yet adjusted the
17237 symbol fragment fr_address. We want to add in STRETCH in
17238 order to get a better estimate of the address. This
17239 particularly matters because of the shift bits. */
17240 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17244 /* Adjust stretch for any alignment frag. Note that if have
17245 been expanding the earlier code, the symbol may be
17246 defined in what appears to be an earlier frag. FIXME:
17247 This doesn't handle the fr_subtype field, which specifies
17248 a maximum number of bytes to skip when doing an
17250 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17252 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17255 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17257 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17266 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17268 /* The base address rules are complicated. The base address of
17269 a branch is the following instruction. The base address of a
17270 PC relative load or add is the instruction itself, but if it
17271 is in a delay slot (in which case it can not be extended) use
17272 the address of the instruction whose delay slot it is in. */
17273 if (pcrel_op
->include_isa_bit
)
17277 /* If we are currently assuming that this frag should be
17278 extended, then the current address is two bytes higher. */
17279 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17282 /* Ignore the low bit in the target, since it will be set
17283 for a text label. */
17286 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17288 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17291 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17296 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17297 extended opcode. SEC is the section the frag is in. */
17300 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17302 const struct mips_int_operand
*operand
;
17307 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17309 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17312 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17313 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17314 operand
= mips16_immed_operand (type
, FALSE
);
17315 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17316 || (operand
->root
.type
== OP_PCREL
17318 : !bfd_is_abs_section (symsec
)))
17321 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17323 if (operand
->root
.type
== OP_PCREL
)
17325 const struct mips_pcrel_operand
*pcrel_op
;
17328 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17331 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17332 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17334 /* If any of the shifted bits are set, we must use an extended
17335 opcode. If the address depends on the size of this
17336 instruction, this can lead to a loop, so we arrange to always
17337 use an extended opcode. */
17338 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17340 fragp
->fr_subtype
=
17341 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17345 /* If we are about to mark a frag as extended because the value
17346 is precisely the next value above maxtiny, then there is a
17347 chance of an infinite loop as in the following code:
17352 In this case when the la is extended, foo is 0x3fc bytes
17353 away, so the la can be shrunk, but then foo is 0x400 away, so
17354 the la must be extended. To avoid this loop, we mark the
17355 frag as extended if it was small, and is about to become
17356 extended with the next value above maxtiny. */
17357 maxtiny
= mips_int_operand_max (operand
);
17358 if (val
== maxtiny
+ (1 << operand
->shift
)
17359 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17361 fragp
->fr_subtype
=
17362 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17367 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17370 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17371 macro expansion. SEC is the section the frag is in. We only
17372 support PC-relative instructions (LA, DLA, LW, LD) here, in
17373 non-PIC code using 32-bit addressing. */
17376 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17378 const struct mips_pcrel_operand
*pcrel_op
;
17379 const struct mips_int_operand
*operand
;
17384 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17386 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17388 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17391 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17397 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17398 if (bfd_is_abs_section (symsec
))
17400 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17402 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17405 operand
= mips16_immed_operand (type
, TRUE
);
17406 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17407 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17408 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17410 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17417 /* Compute the length of a branch sequence, and adjust the
17418 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17419 worst-case length is computed, with UPDATE being used to indicate
17420 whether an unconditional (-1), branch-likely (+1) or regular (0)
17421 branch is to be computed. */
17423 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17425 bfd_boolean toofar
;
17429 && S_IS_DEFINED (fragp
->fr_symbol
)
17430 && !S_IS_WEAK (fragp
->fr_symbol
)
17431 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17436 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17438 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17442 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17445 /* If the symbol is not defined or it's in a different segment,
17446 we emit the long sequence. */
17449 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17451 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17452 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17453 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17454 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17455 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17461 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17464 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17466 /* Additional space for PIC loading of target address. */
17468 if (mips_opts
.isa
== ISA_MIPS1
)
17469 /* Additional space for $at-stabilizing nop. */
17473 /* If branch is conditional. */
17474 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17481 /* Get a FRAG's branch instruction delay slot size, either from the
17482 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17483 or SHORT_INSN_SIZE otherwise. */
17486 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17488 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17491 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17493 return short_insn_size
;
17496 /* Compute the length of a branch sequence, and adjust the
17497 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17498 worst-case length is computed, with UPDATE being used to indicate
17499 whether an unconditional (-1), or regular (0) branch is to be
17503 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17505 bfd_boolean insn32
= TRUE
;
17506 bfd_boolean nods
= TRUE
;
17507 bfd_boolean pic
= TRUE
;
17508 bfd_boolean al
= TRUE
;
17509 int short_insn_size
;
17510 bfd_boolean toofar
;
17515 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17516 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17517 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17518 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17520 short_insn_size
= insn32
? 4 : 2;
17523 && S_IS_DEFINED (fragp
->fr_symbol
)
17524 && !S_IS_WEAK (fragp
->fr_symbol
)
17525 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17530 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17531 /* Ignore the low bit in the target, since it will be set
17532 for a text label. */
17533 if ((val
& 1) != 0)
17536 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17540 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17543 /* If the symbol is not defined or it's in a different segment,
17544 we emit the long sequence. */
17547 if (fragp
&& update
17548 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17549 fragp
->fr_subtype
= (toofar
17550 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17551 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17556 bfd_boolean compact_known
= fragp
!= NULL
;
17557 bfd_boolean compact
= FALSE
;
17558 bfd_boolean uncond
;
17562 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17563 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17566 uncond
= update
< 0;
17568 /* If label is out of range, we turn branch <br>:
17570 <br> label # 4 bytes
17577 # compact && (!PIC || insn32)
17580 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17581 length
+= short_insn_size
;
17583 /* If assembling PIC code, we further turn:
17589 lw/ld at, %got(label)(gp) # 4 bytes
17590 d/addiu at, %lo(label) # 4 bytes
17591 jr/c at # 2/4 bytes
17594 length
+= 4 + short_insn_size
;
17596 /* Add an extra nop if the jump has no compact form and we need
17597 to fill the delay slot. */
17598 if ((!pic
|| al
) && nods
)
17600 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17601 : short_insn_size
);
17603 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17605 <brneg> 0f # 4 bytes
17606 nop # 2/4 bytes if !compact
17609 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17613 /* Add an extra nop to fill the delay slot. */
17614 gas_assert (fragp
);
17615 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17621 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17622 bit accordingly. */
17625 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17627 bfd_boolean toofar
;
17630 && S_IS_DEFINED (fragp
->fr_symbol
)
17631 && !S_IS_WEAK (fragp
->fr_symbol
)
17632 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17638 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17639 /* Ignore the low bit in the target, since it will be set
17640 for a text label. */
17641 if ((val
& 1) != 0)
17644 /* Assume this is a 2-byte branch. */
17645 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17647 /* We try to avoid the infinite loop by not adding 2 more bytes for
17652 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17654 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17655 else if (type
== 'E')
17656 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17661 /* If the symbol is not defined or it's in a different segment,
17662 we emit a normal 32-bit branch. */
17665 if (fragp
&& update
17666 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17668 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17669 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17677 /* Estimate the size of a frag before relaxing. Unless this is the
17678 mips16, we are not really relaxing here, and the final size is
17679 encoded in the subtype information. For the mips16, we have to
17680 decide whether we are using an extended opcode or not. */
17683 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17687 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17690 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17692 return fragp
->fr_var
;
17695 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17697 /* We don't want to modify the EXTENDED bit here; it might get us
17698 into infinite loops. We change it only in mips_relax_frag(). */
17699 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17702 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17705 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17709 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17710 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17711 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17712 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17713 fragp
->fr_var
= length
;
17718 if (mips_pic
== VXWORKS_PIC
)
17719 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17721 else if (RELAX_PIC (fragp
->fr_subtype
))
17722 change
= pic_need_relax (fragp
->fr_symbol
);
17724 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17728 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17729 return -RELAX_FIRST (fragp
->fr_subtype
);
17732 return -RELAX_SECOND (fragp
->fr_subtype
);
17735 /* This is called to see whether a reloc against a defined symbol
17736 should be converted into a reloc against a section. */
17739 mips_fix_adjustable (fixS
*fixp
)
17741 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17742 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17745 if (fixp
->fx_addsy
== NULL
)
17748 /* Allow relocs used for EH tables. */
17749 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17752 /* If symbol SYM is in a mergeable section, relocations of the form
17753 SYM + 0 can usually be made section-relative. The mergeable data
17754 is then identified by the section offset rather than by the symbol.
17756 However, if we're generating REL LO16 relocations, the offset is split
17757 between the LO16 and partnering high part relocation. The linker will
17758 need to recalculate the complete offset in order to correctly identify
17761 The linker has traditionally not looked for the partnering high part
17762 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17763 placed anywhere. Rather than break backwards compatibility by changing
17764 this, it seems better not to force the issue, and instead keep the
17765 original symbol. This will work with either linker behavior. */
17766 if ((lo16_reloc_p (fixp
->fx_r_type
)
17767 || reloc_needs_lo_p (fixp
->fx_r_type
))
17768 && HAVE_IN_PLACE_ADDENDS
17769 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17772 /* There is no place to store an in-place offset for JALR relocations. */
17773 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17776 /* Likewise an in-range offset of limited PC-relative relocations may
17777 overflow the in-place relocatable field if recalculated against the
17778 start address of the symbol's containing section.
17780 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17781 section relative to allow linker relaxations to be performed later on. */
17782 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17783 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17786 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17787 to a floating-point stub. The same is true for non-R_MIPS16_26
17788 relocations against MIPS16 functions; in this case, the stub becomes
17789 the function's canonical address.
17791 Floating-point stubs are stored in unique .mips16.call.* or
17792 .mips16.fn.* sections. If a stub T for function F is in section S,
17793 the first relocation in section S must be against F; this is how the
17794 linker determines the target function. All relocations that might
17795 resolve to T must also be against F. We therefore have the following
17796 restrictions, which are given in an intentionally-redundant way:
17798 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17801 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17802 if that stub might be used.
17804 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17807 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17808 that stub might be used.
17810 There is a further restriction:
17812 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17813 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17814 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17815 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17816 against MIPS16 or microMIPS symbols because we need to keep the
17817 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17818 detection and JAL or BAL to JALX instruction conversion in the
17821 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17822 against a MIPS16 symbol. We deal with (5) by additionally leaving
17823 alone any jump and branch relocations against a microMIPS symbol.
17825 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17826 relocation against some symbol R, no relocation against R may be
17827 reduced. (Note that this deals with (2) as well as (1) because
17828 relocations against global symbols will never be reduced on ELF
17829 targets.) This approach is a little simpler than trying to detect
17830 stub sections, and gives the "all or nothing" per-symbol consistency
17831 that we have for MIPS16 symbols. */
17832 if (fixp
->fx_subsy
== NULL
17833 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17834 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17835 && (jmp_reloc_p (fixp
->fx_r_type
)
17836 || b_reloc_p (fixp
->fx_r_type
)))
17837 || *symbol_get_tc (fixp
->fx_addsy
)))
17843 /* Translate internal representation of relocation info to BFD target
17847 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17849 static arelent
*retval
[4];
17851 bfd_reloc_code_real_type code
;
17853 memset (retval
, 0, sizeof(retval
));
17854 reloc
= retval
[0] = XCNEW (arelent
);
17855 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17856 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17857 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17859 if (fixp
->fx_pcrel
)
17861 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17862 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17863 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17864 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17865 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17866 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17867 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17868 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17869 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17870 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17871 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17872 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17874 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17875 Relocations want only the symbol offset. */
17876 switch (fixp
->fx_r_type
)
17878 case BFD_RELOC_MIPS_18_PCREL_S3
:
17879 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17882 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17886 else if (HAVE_IN_PLACE_ADDENDS
17887 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17888 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17889 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17891 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17892 addend accordingly. */
17893 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17896 reloc
->addend
= fixp
->fx_addnumber
;
17898 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17899 entry to be used in the relocation's section offset. */
17900 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17902 reloc
->address
= reloc
->addend
;
17906 code
= fixp
->fx_r_type
;
17908 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17909 if (reloc
->howto
== NULL
)
17911 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17912 _("cannot represent %s relocation in this object file"
17914 bfd_get_reloc_code_name (code
));
17921 /* Relax a machine dependent frag. This returns the amount by which
17922 the current size of the frag should change. */
17925 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17927 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17929 offsetT old_var
= fragp
->fr_var
;
17931 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17933 return fragp
->fr_var
- old_var
;
17936 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17938 offsetT old_var
= fragp
->fr_var
;
17939 offsetT new_var
= 4;
17941 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17942 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17943 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17944 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17945 fragp
->fr_var
= new_var
;
17947 return new_var
- old_var
;
17950 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17953 if (!mips16_extended_frag (fragp
, sec
, stretch
))
17955 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17957 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17960 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17962 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17968 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
17970 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17972 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17973 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17976 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17978 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17986 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17988 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17990 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17991 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
17996 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18004 /* Convert a machine dependent frag. */
18007 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18009 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18012 unsigned long insn
;
18016 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18017 insn
= read_insn (buf
);
18019 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18021 /* We generate a fixup instead of applying it right now
18022 because, if there are linker relaxations, we're going to
18023 need the relocations. */
18024 exp
.X_op
= O_symbol
;
18025 exp
.X_add_symbol
= fragp
->fr_symbol
;
18026 exp
.X_add_number
= fragp
->fr_offset
;
18028 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18029 BFD_RELOC_16_PCREL_S2
);
18030 fixp
->fx_file
= fragp
->fr_file
;
18031 fixp
->fx_line
= fragp
->fr_line
;
18033 buf
= write_insn (buf
, insn
);
18039 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18040 _("relaxed out-of-range branch into a jump"));
18042 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18045 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18047 /* Reverse the branch. */
18048 switch ((insn
>> 28) & 0xf)
18051 if ((insn
& 0xff000000) == 0x47000000
18052 || (insn
& 0xff600000) == 0x45600000)
18054 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18055 reversed by tweaking bit 23. */
18056 insn
^= 0x00800000;
18060 /* bc[0-3][tf]l? instructions can have the condition
18061 reversed by tweaking a single TF bit, and their
18062 opcodes all have 0x4???????. */
18063 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18064 insn
^= 0x00010000;
18069 /* bltz 0x04000000 bgez 0x04010000
18070 bltzal 0x04100000 bgezal 0x04110000 */
18071 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18072 insn
^= 0x00010000;
18076 /* beq 0x10000000 bne 0x14000000
18077 blez 0x18000000 bgtz 0x1c000000 */
18078 insn
^= 0x04000000;
18086 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18088 /* Clear the and-link bit. */
18089 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18091 /* bltzal 0x04100000 bgezal 0x04110000
18092 bltzall 0x04120000 bgezall 0x04130000 */
18093 insn
&= ~0x00100000;
18096 /* Branch over the branch (if the branch was likely) or the
18097 full jump (not likely case). Compute the offset from the
18098 current instruction to branch to. */
18099 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18103 /* How many bytes in instructions we've already emitted? */
18104 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18105 /* How many bytes in instructions from here to the end? */
18106 i
= fragp
->fr_var
- i
;
18108 /* Convert to instruction count. */
18110 /* Branch counts from the next instruction. */
18113 /* Branch over the jump. */
18114 buf
= write_insn (buf
, insn
);
18117 buf
= write_insn (buf
, 0);
18119 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18121 /* beql $0, $0, 2f */
18123 /* Compute the PC offset from the current instruction to
18124 the end of the variable frag. */
18125 /* How many bytes in instructions we've already emitted? */
18126 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18127 /* How many bytes in instructions from here to the end? */
18128 i
= fragp
->fr_var
- i
;
18129 /* Convert to instruction count. */
18131 /* Don't decrement i, because we want to branch over the
18135 buf
= write_insn (buf
, insn
);
18136 buf
= write_insn (buf
, 0);
18140 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18143 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18144 ? 0x0c000000 : 0x08000000);
18145 exp
.X_op
= O_symbol
;
18146 exp
.X_add_symbol
= fragp
->fr_symbol
;
18147 exp
.X_add_number
= fragp
->fr_offset
;
18149 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18150 FALSE
, BFD_RELOC_MIPS_JMP
);
18151 fixp
->fx_file
= fragp
->fr_file
;
18152 fixp
->fx_line
= fragp
->fr_line
;
18154 buf
= write_insn (buf
, insn
);
18158 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18160 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18161 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18162 insn
|= at
<< OP_SH_RT
;
18163 exp
.X_op
= O_symbol
;
18164 exp
.X_add_symbol
= fragp
->fr_symbol
;
18165 exp
.X_add_number
= fragp
->fr_offset
;
18167 if (fragp
->fr_offset
)
18169 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18170 exp
.X_add_number
= 0;
18173 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18174 FALSE
, BFD_RELOC_MIPS_GOT16
);
18175 fixp
->fx_file
= fragp
->fr_file
;
18176 fixp
->fx_line
= fragp
->fr_line
;
18178 buf
= write_insn (buf
, insn
);
18180 if (mips_opts
.isa
== ISA_MIPS1
)
18182 buf
= write_insn (buf
, 0);
18184 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18185 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18186 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18188 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18189 FALSE
, BFD_RELOC_LO16
);
18190 fixp
->fx_file
= fragp
->fr_file
;
18191 fixp
->fx_line
= fragp
->fr_line
;
18193 buf
= write_insn (buf
, insn
);
18196 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18200 insn
|= at
<< OP_SH_RS
;
18202 buf
= write_insn (buf
, insn
);
18206 fragp
->fr_fix
+= fragp
->fr_var
;
18207 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18211 /* Relax microMIPS branches. */
18212 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18214 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18215 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18216 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18217 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18218 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18219 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18220 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18221 bfd_boolean short_ds
;
18222 unsigned long insn
;
18226 exp
.X_op
= O_symbol
;
18227 exp
.X_add_symbol
= fragp
->fr_symbol
;
18228 exp
.X_add_number
= fragp
->fr_offset
;
18230 fragp
->fr_fix
+= fragp
->fr_var
;
18232 /* Handle 16-bit branches that fit or are forced to fit. */
18233 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18235 /* We generate a fixup instead of applying it right now,
18236 because if there is linker relaxation, we're going to
18237 need the relocations. */
18239 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18240 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18241 else if (type
== 'E')
18242 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18243 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18247 fixp
->fx_file
= fragp
->fr_file
;
18248 fixp
->fx_line
= fragp
->fr_line
;
18250 /* These relocations can have an addend that won't fit in
18252 fixp
->fx_no_overflow
= 1;
18257 /* Handle 32-bit branches that fit or are forced to fit. */
18258 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18259 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18261 /* We generate a fixup instead of applying it right now,
18262 because if there is linker relaxation, we're going to
18263 need the relocations. */
18264 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18265 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18266 fixp
->fx_file
= fragp
->fr_file
;
18267 fixp
->fx_line
= fragp
->fr_line
;
18271 insn
= read_compressed_insn (buf
, 4);
18276 /* Check the short-delay-slot bit. */
18277 if (!al
|| (insn
& 0x02000000) != 0)
18278 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18280 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18283 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18288 /* Relax 16-bit branches to 32-bit branches. */
18291 insn
= read_compressed_insn (buf
, 2);
18293 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18294 insn
= 0x94000000; /* beq */
18295 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18297 unsigned long regno
;
18299 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18300 regno
= micromips_to_32_reg_d_map
[regno
];
18301 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18302 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18307 /* Nothing else to do, just write it out. */
18308 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18309 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18311 buf
= write_compressed_insn (buf
, insn
, 4);
18313 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18314 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18319 insn
= read_compressed_insn (buf
, 4);
18321 /* Relax 32-bit branches to a sequence of instructions. */
18322 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18323 _("relaxed out-of-range branch into a jump"));
18325 /* Set the short-delay-slot bit. */
18326 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18328 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18332 /* Reverse the branch. */
18333 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18334 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18335 insn
^= 0x20000000;
18336 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18337 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18338 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18339 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18340 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18341 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18342 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18343 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18344 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18345 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18346 insn
^= 0x00400000;
18347 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18348 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18349 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18350 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18351 insn
^= 0x00200000;
18352 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18354 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18356 insn
^= 0x00800000;
18362 /* Clear the and-link and short-delay-slot bits. */
18363 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18365 /* bltzal 0x40200000 bgezal 0x40600000 */
18366 /* bltzals 0x42200000 bgezals 0x42600000 */
18367 insn
&= ~0x02200000;
18370 /* Make a label at the end for use with the branch. */
18371 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18372 micromips_label_inc ();
18373 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18376 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18377 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18378 fixp
->fx_file
= fragp
->fr_file
;
18379 fixp
->fx_line
= fragp
->fr_line
;
18381 /* Branch over the jump. */
18382 buf
= write_compressed_insn (buf
, insn
, 4);
18388 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18390 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18396 unsigned long jal
= (short_ds
|| nods
18397 ? 0x74000000 : 0xf4000000); /* jal/s */
18399 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18400 insn
= al
? jal
: 0xd4000000;
18402 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18403 BFD_RELOC_MICROMIPS_JMP
);
18404 fixp
->fx_file
= fragp
->fr_file
;
18405 fixp
->fx_line
= fragp
->fr_line
;
18407 buf
= write_compressed_insn (buf
, insn
, 4);
18409 if (compact
|| nods
)
18413 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18415 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18420 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18422 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18423 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18424 insn
|= at
<< MICROMIPSOP_SH_RT
;
18426 if (exp
.X_add_number
)
18428 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18429 exp
.X_add_number
= 0;
18432 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18433 BFD_RELOC_MICROMIPS_GOT16
);
18434 fixp
->fx_file
= fragp
->fr_file
;
18435 fixp
->fx_line
= fragp
->fr_line
;
18437 buf
= write_compressed_insn (buf
, insn
, 4);
18439 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18440 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18441 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18443 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18444 BFD_RELOC_MICROMIPS_LO16
);
18445 fixp
->fx_file
= fragp
->fr_file
;
18446 fixp
->fx_line
= fragp
->fr_line
;
18448 buf
= write_compressed_insn (buf
, insn
, 4);
18453 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18454 insn
|= at
<< MICROMIPSOP_SH_RS
;
18456 buf
= write_compressed_insn (buf
, insn
, 4);
18458 if (compact
|| nods
)
18460 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18464 /* jr/jrc/jalr/jalrs $at */
18465 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18466 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18468 insn
= al
? jalr
: jr
;
18469 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18471 buf
= write_compressed_insn (buf
, insn
, 2);
18476 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18478 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18483 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18487 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18490 const struct mips_int_operand
*operand
;
18493 unsigned int user_length
;
18494 bfd_boolean need_reloc
;
18495 unsigned long insn
;
18500 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18501 operand
= mips16_immed_operand (type
, FALSE
);
18503 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18504 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18505 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18507 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18508 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18509 || (operand
->root
.type
== OP_PCREL
&& !mac
18511 : !bfd_is_abs_section (symsec
)));
18513 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18515 const struct mips_pcrel_operand
*pcrel_op
;
18517 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18519 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18521 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18522 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18523 _("branch to a symbol in another ISA mode"));
18524 else if ((fragp
->fr_offset
& 0x1) != 0)
18525 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18526 _("branch to misaligned address (0x%lx)"),
18530 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18532 /* Make sure the section winds up with the alignment we have
18534 if (operand
->shift
> 0)
18535 record_alignment (asec
, operand
->shift
);
18538 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18539 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18542 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18543 _("macro instruction expanded into multiple "
18544 "instructions in a branch delay slot"));
18546 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18547 _("extended instruction in a branch delay slot"));
18549 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18550 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18551 _("macro instruction expanded into multiple "
18554 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18556 insn
= read_compressed_insn (buf
, 2);
18558 insn
|= MIPS16_EXTEND
;
18560 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18562 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18573 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18574 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18580 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18582 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18583 fragp
->fr_symbol
, fragp
->fr_offset
,
18584 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18585 fixp
->fx_file
= fragp
->fr_file
;
18586 fixp
->fx_line
= fragp
->fr_line
;
18588 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ 8, 4,
18589 fragp
->fr_symbol
, fragp
->fr_offset
,
18590 FALSE
, BFD_RELOC_MIPS16_LO16
);
18591 fixp
->fx_file
= fragp
->fr_file
;
18592 fixp
->fx_line
= fragp
->fr_line
;
18597 switch (insn
& 0xf800)
18599 case 0x0800: /* ADDIU */
18600 reg
= (insn
>> 8) & 0x7;
18601 op
= 0xf0004800 | (reg
<< 8);
18603 case 0xb000: /* LW */
18604 reg
= (insn
>> 8) & 0x7;
18605 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18607 case 0xf800: /* I64 */
18608 reg
= (insn
>> 5) & 0x7;
18609 switch (insn
& 0x0700)
18611 case 0x0400: /* LD */
18612 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18614 case 0x0600: /* DADDIU */
18615 op
= 0xf000fd00 | (reg
<< 5);
18625 new = 0xf0006800 | (reg
<< 8); /* LI */
18626 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18627 buf
= write_compressed_insn (buf
, new, 4);
18628 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18629 buf
= write_compressed_insn (buf
, new, 4);
18630 op
|= mips16_immed_extend (val
, 16);
18631 buf
= write_compressed_insn (buf
, op
, 4);
18633 fragp
->fr_fix
+= 12;
18637 unsigned int length
= ext
? 4 : 2;
18641 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18649 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18654 if (mac
|| reloc
== BFD_RELOC_NONE
)
18655 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18656 _("unsupported relocation"));
18659 exp
.X_op
= O_symbol
;
18660 exp
.X_add_symbol
= fragp
->fr_symbol
;
18661 exp
.X_add_number
= fragp
->fr_offset
;
18663 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18666 fixp
->fx_file
= fragp
->fr_file
;
18667 fixp
->fx_line
= fragp
->fr_line
;
18670 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18671 _("invalid unextended operand value"));
18674 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18675 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18677 gas_assert (mips16_opcode_length (insn
) == length
);
18678 write_compressed_insn (buf
, insn
, length
);
18679 fragp
->fr_fix
+= length
;
18684 relax_substateT subtype
= fragp
->fr_subtype
;
18685 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18686 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18690 first
= RELAX_FIRST (subtype
);
18691 second
= RELAX_SECOND (subtype
);
18692 fixp
= (fixS
*) fragp
->fr_opcode
;
18694 /* If the delay slot chosen does not match the size of the instruction,
18695 then emit a warning. */
18696 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18697 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18702 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18703 | RELAX_DELAY_SLOT_SIZE_FIRST
18704 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18705 msg
= macro_warning (s
);
18707 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18711 /* Possibly emit a warning if we've chosen the longer option. */
18712 if (use_second
== second_longer
)
18718 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18719 msg
= macro_warning (s
);
18721 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18725 /* Go through all the fixups for the first sequence. Disable them
18726 (by marking them as done) if we're going to use the second
18727 sequence instead. */
18729 && fixp
->fx_frag
== fragp
18730 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18732 if (subtype
& RELAX_USE_SECOND
)
18734 fixp
= fixp
->fx_next
;
18737 /* Go through the fixups for the second sequence. Disable them if
18738 we're going to use the first sequence, otherwise adjust their
18739 addresses to account for the relaxation. */
18740 while (fixp
&& fixp
->fx_frag
== fragp
)
18742 if (subtype
& RELAX_USE_SECOND
)
18743 fixp
->fx_where
-= first
;
18746 fixp
= fixp
->fx_next
;
18749 /* Now modify the frag contents. */
18750 if (subtype
& RELAX_USE_SECOND
)
18754 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18755 memmove (start
, start
+ first
, second
);
18756 fragp
->fr_fix
-= first
;
18759 fragp
->fr_fix
-= second
;
18763 /* This function is called after the relocs have been generated.
18764 We've been storing mips16 text labels as odd. Here we convert them
18765 back to even for the convenience of the debugger. */
18768 mips_frob_file_after_relocs (void)
18771 unsigned int count
, i
;
18773 syms
= bfd_get_outsymbols (stdoutput
);
18774 count
= bfd_get_symcount (stdoutput
);
18775 for (i
= 0; i
< count
; i
++, syms
++)
18776 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18777 && ((*syms
)->value
& 1) != 0)
18779 (*syms
)->value
&= ~1;
18780 /* If the symbol has an odd size, it was probably computed
18781 incorrectly, so adjust that as well. */
18782 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18783 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18787 /* This function is called whenever a label is defined, including fake
18788 labels instantiated off the dot special symbol. It is used when
18789 handling branch delays; if a branch has a label, we assume we cannot
18790 move it. This also bumps the value of the symbol by 1 in compressed
18794 mips_record_label (symbolS
*sym
)
18796 segment_info_type
*si
= seg_info (now_seg
);
18797 struct insn_label_list
*l
;
18799 if (free_insn_labels
== NULL
)
18800 l
= XNEW (struct insn_label_list
);
18803 l
= free_insn_labels
;
18804 free_insn_labels
= l
->next
;
18808 l
->next
= si
->label_list
;
18809 si
->label_list
= l
;
18812 /* This function is called as tc_frob_label() whenever a label is defined
18813 and adds a DWARF-2 record we only want for true labels. */
18816 mips_define_label (symbolS
*sym
)
18818 mips_record_label (sym
);
18819 dwarf2_emit_label (sym
);
18822 /* This function is called by tc_new_dot_label whenever a new dot symbol
18826 mips_add_dot_label (symbolS
*sym
)
18828 mips_record_label (sym
);
18829 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18830 mips_compressed_mark_label (sym
);
18833 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18834 static unsigned int
18835 mips_convert_ase_flags (int ase
)
18837 unsigned int ext_ases
= 0;
18840 ext_ases
|= AFL_ASE_DSP
;
18841 if (ase
& ASE_DSPR2
)
18842 ext_ases
|= AFL_ASE_DSPR2
;
18843 if (ase
& ASE_DSPR3
)
18844 ext_ases
|= AFL_ASE_DSPR3
;
18846 ext_ases
|= AFL_ASE_EVA
;
18848 ext_ases
|= AFL_ASE_MCU
;
18849 if (ase
& ASE_MDMX
)
18850 ext_ases
|= AFL_ASE_MDMX
;
18851 if (ase
& ASE_MIPS3D
)
18852 ext_ases
|= AFL_ASE_MIPS3D
;
18854 ext_ases
|= AFL_ASE_MT
;
18855 if (ase
& ASE_SMARTMIPS
)
18856 ext_ases
|= AFL_ASE_SMARTMIPS
;
18857 if (ase
& ASE_VIRT
)
18858 ext_ases
|= AFL_ASE_VIRT
;
18860 ext_ases
|= AFL_ASE_MSA
;
18862 ext_ases
|= AFL_ASE_XPA
;
18866 /* Some special processing for a MIPS ELF file. */
18869 mips_elf_final_processing (void)
18872 Elf_Internal_ABIFlags_v0 flags
;
18876 switch (file_mips_opts
.isa
)
18879 flags
.isa_level
= 1;
18882 flags
.isa_level
= 2;
18885 flags
.isa_level
= 3;
18888 flags
.isa_level
= 4;
18891 flags
.isa_level
= 5;
18894 flags
.isa_level
= 32;
18898 flags
.isa_level
= 32;
18902 flags
.isa_level
= 32;
18906 flags
.isa_level
= 32;
18910 flags
.isa_level
= 32;
18914 flags
.isa_level
= 64;
18918 flags
.isa_level
= 64;
18922 flags
.isa_level
= 64;
18926 flags
.isa_level
= 64;
18930 flags
.isa_level
= 64;
18935 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18936 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18937 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18938 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18940 flags
.cpr2_size
= AFL_REG_NONE
;
18941 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18942 Tag_GNU_MIPS_ABI_FP
);
18943 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18944 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18945 if (file_ase_mips16
)
18946 flags
.ases
|= AFL_ASE_MIPS16
;
18947 if (file_ase_micromips
)
18948 flags
.ases
|= AFL_ASE_MICROMIPS
;
18950 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18951 || file_mips_opts
.fp
== 64)
18952 && file_mips_opts
.oddspreg
)
18953 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18956 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18957 ((Elf_External_ABIFlags_v0
*)
18960 /* Write out the register information. */
18961 if (mips_abi
!= N64_ABI
)
18965 s
.ri_gprmask
= mips_gprmask
;
18966 s
.ri_cprmask
[0] = mips_cprmask
[0];
18967 s
.ri_cprmask
[1] = mips_cprmask
[1];
18968 s
.ri_cprmask
[2] = mips_cprmask
[2];
18969 s
.ri_cprmask
[3] = mips_cprmask
[3];
18970 /* The gp_value field is set by the MIPS ELF backend. */
18972 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18973 ((Elf32_External_RegInfo
*)
18974 mips_regmask_frag
));
18978 Elf64_Internal_RegInfo s
;
18980 s
.ri_gprmask
= mips_gprmask
;
18982 s
.ri_cprmask
[0] = mips_cprmask
[0];
18983 s
.ri_cprmask
[1] = mips_cprmask
[1];
18984 s
.ri_cprmask
[2] = mips_cprmask
[2];
18985 s
.ri_cprmask
[3] = mips_cprmask
[3];
18986 /* The gp_value field is set by the MIPS ELF backend. */
18988 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18989 ((Elf64_External_RegInfo
*)
18990 mips_regmask_frag
));
18993 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18994 sort of BFD interface for this. */
18995 if (mips_any_noreorder
)
18996 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18997 if (mips_pic
!= NO_PIC
)
18999 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19000 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19003 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19005 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19006 defined at present; this might need to change in future. */
19007 if (file_ase_mips16
)
19008 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19009 if (file_ase_micromips
)
19010 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19011 if (file_mips_opts
.ase
& ASE_MDMX
)
19012 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19014 /* Set the MIPS ELF ABI flags. */
19015 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19016 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19017 else if (mips_abi
== O64_ABI
)
19018 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19019 else if (mips_abi
== EABI_ABI
)
19021 if (file_mips_opts
.gp
== 64)
19022 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19024 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19026 else if (mips_abi
== N32_ABI
)
19027 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19029 /* Nothing to do for N64_ABI. */
19031 if (mips_32bitmode
)
19032 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19034 if (mips_nan2008
== 1)
19035 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19037 /* 32 bit code with 64 bit FP registers. */
19038 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19039 Tag_GNU_MIPS_ABI_FP
);
19040 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19041 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19044 typedef struct proc
{
19046 symbolS
*func_end_sym
;
19047 unsigned long reg_mask
;
19048 unsigned long reg_offset
;
19049 unsigned long fpreg_mask
;
19050 unsigned long fpreg_offset
;
19051 unsigned long frame_offset
;
19052 unsigned long frame_reg
;
19053 unsigned long pc_reg
;
19056 static procS cur_proc
;
19057 static procS
*cur_proc_ptr
;
19058 static int numprocs
;
19060 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19061 as "2", and a normal nop as "0". */
19063 #define NOP_OPCODE_MIPS 0
19064 #define NOP_OPCODE_MIPS16 1
19065 #define NOP_OPCODE_MICROMIPS 2
19068 mips_nop_opcode (void)
19070 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19071 return NOP_OPCODE_MICROMIPS
;
19072 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19073 return NOP_OPCODE_MIPS16
;
19075 return NOP_OPCODE_MIPS
;
19078 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19079 32-bit microMIPS NOPs here (if applicable). */
19082 mips_handle_align (fragS
*fragp
)
19086 int bytes
, size
, excess
;
19089 if (fragp
->fr_type
!= rs_align_code
)
19092 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19094 switch (nop_opcode
)
19096 case NOP_OPCODE_MICROMIPS
:
19097 opcode
= micromips_nop32_insn
.insn_opcode
;
19100 case NOP_OPCODE_MIPS16
:
19101 opcode
= mips16_nop_insn
.insn_opcode
;
19104 case NOP_OPCODE_MIPS
:
19106 opcode
= nop_insn
.insn_opcode
;
19111 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19112 excess
= bytes
% size
;
19114 /* Handle the leading part if we're not inserting a whole number of
19115 instructions, and make it the end of the fixed part of the frag.
19116 Try to fit in a short microMIPS NOP if applicable and possible,
19117 and use zeroes otherwise. */
19118 gas_assert (excess
< 4);
19119 fragp
->fr_fix
+= excess
;
19124 /* Fall through. */
19126 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19128 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19132 /* Fall through. */
19135 /* Fall through. */
19140 md_number_to_chars (p
, opcode
, size
);
19141 fragp
->fr_var
= size
;
19150 if (*input_line_pointer
== '-')
19152 ++input_line_pointer
;
19155 if (!ISDIGIT (*input_line_pointer
))
19156 as_bad (_("expected simple number"));
19157 if (input_line_pointer
[0] == '0')
19159 if (input_line_pointer
[1] == 'x')
19161 input_line_pointer
+= 2;
19162 while (ISXDIGIT (*input_line_pointer
))
19165 val
|= hex_value (*input_line_pointer
++);
19167 return negative
? -val
: val
;
19171 ++input_line_pointer
;
19172 while (ISDIGIT (*input_line_pointer
))
19175 val
|= *input_line_pointer
++ - '0';
19177 return negative
? -val
: val
;
19180 if (!ISDIGIT (*input_line_pointer
))
19182 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19183 *input_line_pointer
, *input_line_pointer
);
19184 as_warn (_("invalid number"));
19187 while (ISDIGIT (*input_line_pointer
))
19190 val
+= *input_line_pointer
++ - '0';
19192 return negative
? -val
: val
;
19195 /* The .file directive; just like the usual .file directive, but there
19196 is an initial number which is the ECOFF file index. In the non-ECOFF
19197 case .file implies DWARF-2. */
19200 s_mips_file (int x ATTRIBUTE_UNUSED
)
19202 static int first_file_directive
= 0;
19204 if (ECOFF_DEBUGGING
)
19213 filename
= dwarf2_directive_file (0);
19215 /* Versions of GCC up to 3.1 start files with a ".file"
19216 directive even for stabs output. Make sure that this
19217 ".file" is handled. Note that you need a version of GCC
19218 after 3.1 in order to support DWARF-2 on MIPS. */
19219 if (filename
!= NULL
&& ! first_file_directive
)
19221 (void) new_logical_line (filename
, -1);
19222 s_app_file_string (filename
, 0);
19224 first_file_directive
= 1;
19228 /* The .loc directive, implying DWARF-2. */
19231 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19233 if (!ECOFF_DEBUGGING
)
19234 dwarf2_directive_loc (0);
19237 /* The .end directive. */
19240 s_mips_end (int x ATTRIBUTE_UNUSED
)
19244 /* Following functions need their own .frame and .cprestore directives. */
19245 mips_frame_reg_valid
= 0;
19246 mips_cprestore_valid
= 0;
19248 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19251 demand_empty_rest_of_line ();
19256 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19257 as_warn (_(".end not in text section"));
19261 as_warn (_(".end directive without a preceding .ent directive"));
19262 demand_empty_rest_of_line ();
19268 gas_assert (S_GET_NAME (p
));
19269 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19270 as_warn (_(".end symbol does not match .ent symbol"));
19272 if (debug_type
== DEBUG_STABS
)
19273 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19277 as_warn (_(".end directive missing or unknown symbol"));
19279 /* Create an expression to calculate the size of the function. */
19280 if (p
&& cur_proc_ptr
)
19282 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19283 expressionS
*exp
= XNEW (expressionS
);
19286 exp
->X_op
= O_subtract
;
19287 exp
->X_add_symbol
= symbol_temp_new_now ();
19288 exp
->X_op_symbol
= p
;
19289 exp
->X_add_number
= 0;
19291 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19294 #ifdef md_flush_pending_output
19295 md_flush_pending_output ();
19298 /* Generate a .pdr section. */
19299 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19301 segT saved_seg
= now_seg
;
19302 subsegT saved_subseg
= now_subseg
;
19306 gas_assert (pdr_seg
);
19307 subseg_set (pdr_seg
, 0);
19309 /* Write the symbol. */
19310 exp
.X_op
= O_symbol
;
19311 exp
.X_add_symbol
= p
;
19312 exp
.X_add_number
= 0;
19313 emit_expr (&exp
, 4);
19315 fragp
= frag_more (7 * 4);
19317 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19318 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19319 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19320 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19321 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19322 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19323 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19325 subseg_set (saved_seg
, saved_subseg
);
19328 cur_proc_ptr
= NULL
;
19331 /* The .aent and .ent directives. */
19334 s_mips_ent (int aent
)
19338 symbolP
= get_symbol ();
19339 if (*input_line_pointer
== ',')
19340 ++input_line_pointer
;
19341 SKIP_WHITESPACE ();
19342 if (ISDIGIT (*input_line_pointer
)
19343 || *input_line_pointer
== '-')
19346 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19347 as_warn (_(".ent or .aent not in text section"));
19349 if (!aent
&& cur_proc_ptr
)
19350 as_warn (_("missing .end"));
19354 /* This function needs its own .frame and .cprestore directives. */
19355 mips_frame_reg_valid
= 0;
19356 mips_cprestore_valid
= 0;
19358 cur_proc_ptr
= &cur_proc
;
19359 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19361 cur_proc_ptr
->func_sym
= symbolP
;
19365 if (debug_type
== DEBUG_STABS
)
19366 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19367 S_GET_NAME (symbolP
));
19370 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19372 demand_empty_rest_of_line ();
19375 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19376 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19377 s_mips_frame is used so that we can set the PDR information correctly.
19378 We can't use the ecoff routines because they make reference to the ecoff
19379 symbol table (in the mdebug section). */
19382 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19384 if (ECOFF_DEBUGGING
)
19390 if (cur_proc_ptr
== (procS
*) NULL
)
19392 as_warn (_(".frame outside of .ent"));
19393 demand_empty_rest_of_line ();
19397 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19399 SKIP_WHITESPACE ();
19400 if (*input_line_pointer
++ != ','
19401 || get_absolute_expression_and_terminator (&val
) != ',')
19403 as_warn (_("bad .frame directive"));
19404 --input_line_pointer
;
19405 demand_empty_rest_of_line ();
19409 cur_proc_ptr
->frame_offset
= val
;
19410 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19412 demand_empty_rest_of_line ();
19416 /* The .fmask and .mask directives. If the mdebug section is present
19417 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19418 embedded targets, s_mips_mask is used so that we can set the PDR
19419 information correctly. We can't use the ecoff routines because they
19420 make reference to the ecoff symbol table (in the mdebug section). */
19423 s_mips_mask (int reg_type
)
19425 if (ECOFF_DEBUGGING
)
19426 s_ignore (reg_type
);
19431 if (cur_proc_ptr
== (procS
*) NULL
)
19433 as_warn (_(".mask/.fmask outside of .ent"));
19434 demand_empty_rest_of_line ();
19438 if (get_absolute_expression_and_terminator (&mask
) != ',')
19440 as_warn (_("bad .mask/.fmask directive"));
19441 --input_line_pointer
;
19442 demand_empty_rest_of_line ();
19446 off
= get_absolute_expression ();
19448 if (reg_type
== 'F')
19450 cur_proc_ptr
->fpreg_mask
= mask
;
19451 cur_proc_ptr
->fpreg_offset
= off
;
19455 cur_proc_ptr
->reg_mask
= mask
;
19456 cur_proc_ptr
->reg_offset
= off
;
19459 demand_empty_rest_of_line ();
19463 /* A table describing all the processors gas knows about. Names are
19464 matched in the order listed.
19466 To ease comparison, please keep this table in the same order as
19467 gcc's mips_cpu_info_table[]. */
19468 static const struct mips_cpu_info mips_cpu_info_table
[] =
19470 /* Entries for generic ISAs */
19471 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19472 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19473 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19474 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19475 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19476 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19477 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19478 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19479 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19480 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19481 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19482 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19483 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19484 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19485 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19488 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19489 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19490 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19493 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19496 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19497 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19498 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19499 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19500 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19501 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19502 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19503 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19504 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19505 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19506 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19507 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19508 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19509 /* ST Microelectronics Loongson 2E and 2F cores */
19510 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19511 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19514 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19515 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19516 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19517 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19518 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19519 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19520 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19521 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19522 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19523 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19524 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19525 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19526 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19527 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19528 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19531 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19532 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19533 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19534 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19536 /* MIPS 32 Release 2 */
19537 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19538 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19539 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19540 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19541 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19542 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19543 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19544 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19545 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19546 ISA_MIPS32R2
, CPU_MIPS32R2
},
19547 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19548 ISA_MIPS32R2
, CPU_MIPS32R2
},
19549 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19550 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19551 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19552 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19553 /* Deprecated forms of the above. */
19554 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19555 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19556 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19557 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19558 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19559 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19560 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19561 /* Deprecated forms of the above. */
19562 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19563 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19564 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19565 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19566 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19567 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19568 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19569 /* Deprecated forms of the above. */
19570 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19571 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19572 /* 34Kn is a 34kc without DSP. */
19573 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19574 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19575 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19576 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19577 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19578 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19579 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19580 /* Deprecated forms of the above. */
19581 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19582 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19583 /* 1004K cores are multiprocessor versions of the 34K. */
19584 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19585 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19586 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19587 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19588 /* interaptiv is the new name for 1004kf */
19589 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19591 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19592 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19593 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19594 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19597 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19598 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19599 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19600 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19602 /* Broadcom SB-1 CPU core */
19603 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19604 /* Broadcom SB-1A CPU core */
19605 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19607 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19609 /* MIPS 64 Release 2 */
19611 /* Cavium Networks Octeon CPU core */
19612 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19613 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19614 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19615 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19618 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19621 XLP is mostly like XLR, with the prominent exception that it is
19622 MIPS64R2 rather than MIPS64. */
19623 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19625 /* MIPS 64 Release 6 */
19626 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19627 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19630 { NULL
, 0, 0, 0, 0 }
19634 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19635 with a final "000" replaced by "k". Ignore case.
19637 Note: this function is shared between GCC and GAS. */
19640 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19642 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19643 given
++, canonical
++;
19645 return ((*given
== 0 && *canonical
== 0)
19646 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19650 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19651 CPU name. We've traditionally allowed a lot of variation here.
19653 Note: this function is shared between GCC and GAS. */
19656 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19658 /* First see if the name matches exactly, or with a final "000"
19659 turned into "k". */
19660 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19663 /* If not, try comparing based on numerical designation alone.
19664 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19665 if (TOLOWER (*given
) == 'r')
19667 if (!ISDIGIT (*given
))
19670 /* Skip over some well-known prefixes in the canonical name,
19671 hoping to find a number there too. */
19672 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19674 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19676 else if (TOLOWER (canonical
[0]) == 'r')
19679 return mips_strict_matching_cpu_name_p (canonical
, given
);
19683 /* Parse an option that takes the name of a processor as its argument.
19684 OPTION is the name of the option and CPU_STRING is the argument.
19685 Return the corresponding processor enumeration if the CPU_STRING is
19686 recognized, otherwise report an error and return null.
19688 A similar function exists in GCC. */
19690 static const struct mips_cpu_info
*
19691 mips_parse_cpu (const char *option
, const char *cpu_string
)
19693 const struct mips_cpu_info
*p
;
19695 /* 'from-abi' selects the most compatible architecture for the given
19696 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19697 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19698 version. Look first at the -mgp options, if given, otherwise base
19699 the choice on MIPS_DEFAULT_64BIT.
19701 Treat NO_ABI like the EABIs. One reason to do this is that the
19702 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19703 architecture. This code picks MIPS I for 'mips' and MIPS III for
19704 'mips64', just as we did in the days before 'from-abi'. */
19705 if (strcasecmp (cpu_string
, "from-abi") == 0)
19707 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19708 return mips_cpu_info_from_isa (ISA_MIPS1
);
19710 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19711 return mips_cpu_info_from_isa (ISA_MIPS3
);
19713 if (file_mips_opts
.gp
>= 0)
19714 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19715 ? ISA_MIPS1
: ISA_MIPS3
);
19717 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19722 /* 'default' has traditionally been a no-op. Probably not very useful. */
19723 if (strcasecmp (cpu_string
, "default") == 0)
19726 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19727 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19730 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19734 /* Return the canonical processor information for ISA (a member of the
19735 ISA_MIPS* enumeration). */
19737 static const struct mips_cpu_info
*
19738 mips_cpu_info_from_isa (int isa
)
19742 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19743 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19744 && isa
== mips_cpu_info_table
[i
].isa
)
19745 return (&mips_cpu_info_table
[i
]);
19750 static const struct mips_cpu_info
*
19751 mips_cpu_info_from_arch (int arch
)
19755 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19756 if (arch
== mips_cpu_info_table
[i
].cpu
)
19757 return (&mips_cpu_info_table
[i
]);
19763 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19767 fprintf (stream
, "%24s", "");
19772 fprintf (stream
, ", ");
19776 if (*col_p
+ strlen (string
) > 72)
19778 fprintf (stream
, "\n%24s", "");
19782 fprintf (stream
, "%s", string
);
19783 *col_p
+= strlen (string
);
19789 md_show_usage (FILE *stream
)
19794 fprintf (stream
, _("\
19796 -EB generate big endian output\n\
19797 -EL generate little endian output\n\
19798 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19799 -G NUM allow referencing objects up to NUM bytes\n\
19800 implicitly with the gp register [default 8]\n"));
19801 fprintf (stream
, _("\
19802 -mips1 generate MIPS ISA I instructions\n\
19803 -mips2 generate MIPS ISA II instructions\n\
19804 -mips3 generate MIPS ISA III instructions\n\
19805 -mips4 generate MIPS ISA IV instructions\n\
19806 -mips5 generate MIPS ISA V instructions\n\
19807 -mips32 generate MIPS32 ISA instructions\n\
19808 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19809 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19810 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19811 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19812 -mips64 generate MIPS64 ISA instructions\n\
19813 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19814 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19815 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19816 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19817 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19821 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19822 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19823 show (stream
, "from-abi", &column
, &first
);
19824 fputc ('\n', stream
);
19826 fprintf (stream
, _("\
19827 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19828 -no-mCPU don't generate code specific to CPU.\n\
19829 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19833 show (stream
, "3900", &column
, &first
);
19834 show (stream
, "4010", &column
, &first
);
19835 show (stream
, "4100", &column
, &first
);
19836 show (stream
, "4650", &column
, &first
);
19837 fputc ('\n', stream
);
19839 fprintf (stream
, _("\
19840 -mips16 generate mips16 instructions\n\
19841 -no-mips16 do not generate mips16 instructions\n"));
19842 fprintf (stream
, _("\
19843 -mmicromips generate microMIPS instructions\n\
19844 -mno-micromips do not generate microMIPS instructions\n"));
19845 fprintf (stream
, _("\
19846 -msmartmips generate smartmips instructions\n\
19847 -mno-smartmips do not generate smartmips instructions\n"));
19848 fprintf (stream
, _("\
19849 -mdsp generate DSP instructions\n\
19850 -mno-dsp do not generate DSP instructions\n"));
19851 fprintf (stream
, _("\
19852 -mdspr2 generate DSP R2 instructions\n\
19853 -mno-dspr2 do not generate DSP R2 instructions\n"));
19854 fprintf (stream
, _("\
19855 -mdspr3 generate DSP R3 instructions\n\
19856 -mno-dspr3 do not generate DSP R3 instructions\n"));
19857 fprintf (stream
, _("\
19858 -mmt generate MT instructions\n\
19859 -mno-mt do not generate MT instructions\n"));
19860 fprintf (stream
, _("\
19861 -mmcu generate MCU instructions\n\
19862 -mno-mcu do not generate MCU instructions\n"));
19863 fprintf (stream
, _("\
19864 -mmsa generate MSA instructions\n\
19865 -mno-msa do not generate MSA instructions\n"));
19866 fprintf (stream
, _("\
19867 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19868 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19869 fprintf (stream
, _("\
19870 -mvirt generate Virtualization instructions\n\
19871 -mno-virt do not generate Virtualization instructions\n"));
19872 fprintf (stream
, _("\
19873 -minsn32 only generate 32-bit microMIPS instructions\n\
19874 -mno-insn32 generate all microMIPS instructions\n"));
19875 fprintf (stream
, _("\
19876 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19877 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19878 -mfix-vr4120 work around certain VR4120 errata\n\
19879 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19880 -mfix-24k insert a nop after ERET and DERET instructions\n\
19881 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19882 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19883 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19884 -msym32 assume all symbols have 32-bit values\n\
19885 -O0 remove unneeded NOPs, do not swap branches\n\
19886 -O remove unneeded NOPs and swap branches\n\
19887 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19888 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19889 fprintf (stream
, _("\
19890 -mhard-float allow floating-point instructions\n\
19891 -msoft-float do not allow floating-point instructions\n\
19892 -msingle-float only allow 32-bit floating-point operations\n\
19893 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19894 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19895 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19896 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
19897 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
19898 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19902 show (stream
, "legacy", &column
, &first
);
19903 show (stream
, "2008", &column
, &first
);
19905 fputc ('\n', stream
);
19907 fprintf (stream
, _("\
19908 -KPIC, -call_shared generate SVR4 position independent code\n\
19909 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19910 -mvxworks-pic generate VxWorks position independent code\n\
19911 -non_shared do not generate code that can operate with DSOs\n\
19912 -xgot assume a 32 bit GOT\n\
19913 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19914 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19915 position dependent (non shared) code\n\
19916 -mabi=ABI create ABI conformant object file for:\n"));
19920 show (stream
, "32", &column
, &first
);
19921 show (stream
, "o64", &column
, &first
);
19922 show (stream
, "n32", &column
, &first
);
19923 show (stream
, "64", &column
, &first
);
19924 show (stream
, "eabi", &column
, &first
);
19926 fputc ('\n', stream
);
19928 fprintf (stream
, _("\
19929 -32 create o32 ABI object file (default)\n\
19930 -n32 create n32 ABI object file\n\
19931 -64 create 64 ABI object file\n"));
19936 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19938 if (HAVE_64BIT_SYMBOLS
)
19939 return dwarf2_format_64bit_irix
;
19941 return dwarf2_format_32bit
;
19946 mips_dwarf2_addr_size (void)
19948 if (HAVE_64BIT_OBJECTS
)
19954 /* Standard calling conventions leave the CFA at SP on entry. */
19956 mips_cfi_frame_initial_instructions (void)
19958 cfi_add_CFA_def_cfa_register (SP
);
19962 tc_mips_regname_to_dw2regnum (char *regname
)
19964 unsigned int regnum
= -1;
19967 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19973 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19974 Given a symbolic attribute NAME, return the proper integer value.
19975 Returns -1 if the attribute is not known. */
19978 mips_convert_symbolic_attribute (const char *name
)
19980 static const struct
19985 attribute_table
[] =
19987 #define T(tag) {#tag, tag}
19988 T (Tag_GNU_MIPS_ABI_FP
),
19989 T (Tag_GNU_MIPS_ABI_MSA
),
19997 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19998 if (streq (name
, attribute_table
[i
].name
))
19999 return attribute_table
[i
].tag
;
20007 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20009 mips_emit_delays ();
20011 as_warn (_("missing .end at end of assembly"));
20013 /* Just in case no code was emitted, do the consistency check. */
20014 file_mips_check_options ();
20016 /* Set a floating-point ABI if the user did not. */
20017 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20019 /* Perform consistency checks on the floating-point ABI. */
20020 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20021 Tag_GNU_MIPS_ABI_FP
);
20022 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20023 check_fpabi (fpabi
);
20027 /* Soft-float gets precedence over single-float, the two options should
20028 not be used together so this should not matter. */
20029 if (file_mips_opts
.soft_float
== 1)
20030 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20031 /* Single-float gets precedence over all double_float cases. */
20032 else if (file_mips_opts
.single_float
== 1)
20033 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20036 switch (file_mips_opts
.fp
)
20039 if (file_mips_opts
.gp
== 32)
20040 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20043 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20046 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20047 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20048 else if (file_mips_opts
.gp
== 32)
20049 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20051 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20056 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20057 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20061 /* Returns the relocation type required for a particular CFI encoding. */
20063 bfd_reloc_code_real_type
20064 mips_cfi_reloc_for_encoding (int encoding
)
20066 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20067 return BFD_RELOC_32_PCREL
;
20068 else return BFD_RELOC_NONE
;