1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2020 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static struct hash_control
*op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static struct hash_control
*mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static struct hash_control
*micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* The maximum number of LABELS detect for the same address. */
816 #define MAX_LABELS_SAME 10
818 /* Arrays of operands for each instruction. */
819 #define MAX_OPERANDS 6
820 struct mips_operand_array
822 const struct mips_operand
*operand
[MAX_OPERANDS
];
824 static struct mips_operand_array
*mips_operands
;
825 static struct mips_operand_array
*mips16_operands
;
826 static struct mips_operand_array
*micromips_operands
;
828 /* Nop instructions used by emit_nop. */
829 static struct mips_cl_insn nop_insn
;
830 static struct mips_cl_insn mips16_nop_insn
;
831 static struct mips_cl_insn micromips_nop16_insn
;
832 static struct mips_cl_insn micromips_nop32_insn
;
834 /* Sync instructions used by insert sync. */
835 static struct mips_cl_insn sync_insn
;
837 /* The appropriate nop for the current mode. */
838 #define NOP_INSN (mips_opts.mips16 \
840 : (mips_opts.micromips \
841 ? (mips_opts.insn32 \
842 ? µmips_nop32_insn \
843 : µmips_nop16_insn) \
846 /* The size of NOP_INSN in bytes. */
847 #define NOP_INSN_SIZE ((mips_opts.mips16 \
848 || (mips_opts.micromips && !mips_opts.insn32)) \
851 /* If this is set, it points to a frag holding nop instructions which
852 were inserted before the start of a noreorder section. If those
853 nops turn out to be unnecessary, the size of the frag can be
855 static fragS
*prev_nop_frag
;
857 /* The number of nop instructions we created in prev_nop_frag. */
858 static int prev_nop_frag_holds
;
860 /* The number of nop instructions that we know we need in
862 static int prev_nop_frag_required
;
864 /* The number of instructions we've seen since prev_nop_frag. */
865 static int prev_nop_frag_since
;
867 /* Relocations against symbols are sometimes done in two parts, with a HI
868 relocation and a LO relocation. Each relocation has only 16 bits of
869 space to store an addend. This means that in order for the linker to
870 handle carries correctly, it must be able to locate both the HI and
871 the LO relocation. This means that the relocations must appear in
872 order in the relocation table.
874 In order to implement this, we keep track of each unmatched HI
875 relocation. We then sort them so that they immediately precede the
876 corresponding LO relocation. */
881 struct mips_hi_fixup
*next
;
884 /* The section this fixup is in. */
888 /* The list of unmatched HI relocs. */
890 static struct mips_hi_fixup
*mips_hi_fixup_list
;
892 /* The frag containing the last explicit relocation operator.
893 Null if explicit relocations have not been used. */
895 static fragS
*prev_reloc_op_frag
;
897 /* Map mips16 register numbers to normal MIPS register numbers. */
899 static const unsigned int mips16_to_32_reg_map
[] =
901 16, 17, 2, 3, 4, 5, 6, 7
904 /* Map microMIPS register numbers to normal MIPS register numbers. */
906 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
908 /* The microMIPS registers with type h. */
909 static const unsigned int micromips_to_32_reg_h_map1
[] =
911 5, 5, 6, 4, 4, 4, 4, 4
913 static const unsigned int micromips_to_32_reg_h_map2
[] =
915 6, 7, 7, 21, 22, 5, 6, 7
918 /* The microMIPS registers with type m. */
919 static const unsigned int micromips_to_32_reg_m_map
[] =
921 0, 17, 2, 3, 16, 18, 19, 20
924 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
926 /* Classifies the kind of instructions we're interested in when
927 implementing -mfix-vr4120. */
928 enum fix_vr4120_class
936 NUM_FIX_VR4120_CLASSES
939 /* ...likewise -mfix-loongson2f-jump. */
940 static bfd_boolean mips_fix_loongson2f_jump
;
942 /* ...likewise -mfix-loongson2f-nop. */
943 static bfd_boolean mips_fix_loongson2f_nop
;
945 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
946 static bfd_boolean mips_fix_loongson2f
;
948 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
949 there must be at least one other instruction between an instruction
950 of type X and an instruction of type Y. */
951 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
953 /* True if -mfix-vr4120 is in force. */
954 static int mips_fix_vr4120
;
956 /* ...likewise -mfix-vr4130. */
957 static int mips_fix_vr4130
;
959 /* ...likewise -mfix-24k. */
960 static int mips_fix_24k
;
962 /* ...likewise -mfix-rm7000 */
963 static int mips_fix_rm7000
;
965 /* ...likewise -mfix-cn63xxp1 */
966 static bfd_boolean mips_fix_cn63xxp1
;
968 /* ...likewise -mfix-r5900 */
969 static bfd_boolean mips_fix_r5900
;
970 static bfd_boolean mips_fix_r5900_explicit
;
972 /* ...likewise -mfix-loongson3-llsc. */
973 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
975 /* We don't relax branches by default, since this causes us to expand
976 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
977 fail to compute the offset before expanding the macro to the most
978 efficient expansion. */
980 static int mips_relax_branch
;
982 /* TRUE if checks are suppressed for invalid branches between ISA modes.
983 Needed for broken assembly produced by some GCC versions and some
984 sloppy code out there, where branches to data labels are present. */
985 static bfd_boolean mips_ignore_branch_isa
;
987 /* The expansion of many macros depends on the type of symbol that
988 they refer to. For example, when generating position-dependent code,
989 a macro that refers to a symbol may have two different expansions,
990 one which uses GP-relative addresses and one which uses absolute
991 addresses. When generating SVR4-style PIC, a macro may have
992 different expansions for local and global symbols.
994 We handle these situations by generating both sequences and putting
995 them in variant frags. In position-dependent code, the first sequence
996 will be the GP-relative one and the second sequence will be the
997 absolute one. In SVR4 PIC, the first sequence will be for global
998 symbols and the second will be for local symbols.
1000 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
1001 SECOND are the lengths of the two sequences in bytes. These fields
1002 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1003 the subtype has the following flags:
1006 Set if generating PIC code.
1009 Set if it has been decided that we should use the second
1010 sequence instead of the first.
1013 Set in the first variant frag if the macro's second implementation
1014 is longer than its first. This refers to the macro as a whole,
1015 not an individual relaxation.
1018 Set in the first variant frag if the macro appeared in a .set nomacro
1019 block and if one alternative requires a warning but the other does not.
1022 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1025 RELAX_DELAY_SLOT_16BIT
1026 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1029 RELAX_DELAY_SLOT_SIZE_FIRST
1030 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1031 the macro is of the wrong size for the branch delay slot.
1033 RELAX_DELAY_SLOT_SIZE_SECOND
1034 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1035 the macro is of the wrong size for the branch delay slot.
1037 The frag's "opcode" points to the first fixup for relaxable code.
1039 Relaxable macros are generated using a sequence such as:
1041 relax_start (SYMBOL);
1042 ... generate first expansion ...
1044 ... generate second expansion ...
1047 The code and fixups for the unwanted alternative are discarded
1048 by md_convert_frag. */
1049 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1050 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1052 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1053 #define RELAX_SECOND(X) ((X) & 0xff)
1054 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1055 #define RELAX_USE_SECOND 0x20000
1056 #define RELAX_SECOND_LONGER 0x40000
1057 #define RELAX_NOMACRO 0x80000
1058 #define RELAX_DELAY_SLOT 0x100000
1059 #define RELAX_DELAY_SLOT_16BIT 0x200000
1060 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1061 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1063 /* Branch without likely bit. If label is out of range, we turn:
1065 beq reg1, reg2, label
1075 with the following opcode replacements:
1082 bltzal <-> bgezal (with jal label instead of j label)
1084 Even though keeping the delay slot instruction in the delay slot of
1085 the branch would be more efficient, it would be very tricky to do
1086 correctly, because we'd have to introduce a variable frag *after*
1087 the delay slot instruction, and expand that instead. Let's do it
1088 the easy way for now, even if the branch-not-taken case now costs
1089 one additional instruction. Out-of-range branches are not supposed
1090 to be common, anyway.
1092 Branch likely. If label is out of range, we turn:
1094 beql reg1, reg2, label
1095 delay slot (annulled if branch not taken)
1104 delay slot (executed only if branch taken)
1107 It would be possible to generate a shorter sequence by losing the
1108 likely bit, generating something like:
1113 delay slot (executed only if branch taken)
1125 bltzall -> bgezal (with jal label instead of j label)
1126 bgezall -> bltzal (ditto)
1129 but it's not clear that it would actually improve performance. */
1130 #define RELAX_BRANCH_ENCODE(at, pic, \
1131 uncond, likely, link, toofar) \
1132 ((relax_substateT) \
1135 | ((pic) ? 0x20 : 0) \
1136 | ((toofar) ? 0x40 : 0) \
1137 | ((link) ? 0x80 : 0) \
1138 | ((likely) ? 0x100 : 0) \
1139 | ((uncond) ? 0x200 : 0)))
1140 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1141 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1142 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1143 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1144 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1145 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1146 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1148 /* For mips16 code, we use an entirely different form of relaxation.
1149 mips16 supports two versions of most instructions which take
1150 immediate values: a small one which takes some small value, and a
1151 larger one which takes a 16 bit value. Since branches also follow
1152 this pattern, relaxing these values is required.
1154 We can assemble both mips16 and normal MIPS code in a single
1155 object. Therefore, we need to support this type of relaxation at
1156 the same time that we support the relaxation described above. We
1157 use the high bit of the subtype field to distinguish these cases.
1159 The information we store for this type of relaxation is the
1160 argument code found in the opcode file for this relocation, whether
1161 the user explicitly requested a small or extended form, and whether
1162 the relocation is in a jump or jal delay slot. That tells us the
1163 size of the value, and how it should be stored. We also store
1164 whether the fragment is considered to be extended or not. We also
1165 store whether this is known to be a branch to a different section,
1166 whether we have tried to relax this frag yet, and whether we have
1167 ever extended a PC relative fragment because of a shift count. */
1168 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1173 | ((e2) ? 0x100 : 0) \
1174 | ((pic) ? 0x200 : 0) \
1175 | ((sym32) ? 0x400 : 0) \
1176 | ((nomacro) ? 0x800 : 0) \
1177 | ((small) ? 0x1000 : 0) \
1178 | ((ext) ? 0x2000 : 0) \
1179 | ((dslot) ? 0x4000 : 0) \
1180 | ((jal_dslot) ? 0x8000 : 0))
1182 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1183 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1184 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1185 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1186 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1187 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1188 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1189 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1190 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1191 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1193 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1194 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1195 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1196 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1197 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1198 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1199 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1200 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1201 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1203 /* For microMIPS code, we use relaxation similar to one we use for
1204 MIPS16 code. Some instructions that take immediate values support
1205 two encodings: a small one which takes some small value, and a
1206 larger one which takes a 16 bit value. As some branches also follow
1207 this pattern, relaxing these values is required.
1209 We can assemble both microMIPS and normal MIPS code in a single
1210 object. Therefore, we need to support this type of relaxation at
1211 the same time that we support the relaxation described above. We
1212 use one of the high bits of the subtype field to distinguish these
1215 The information we store for this type of relaxation is the argument
1216 code found in the opcode file for this relocation, the register
1217 selected as the assembler temporary, whether in the 32-bit
1218 instruction mode, whether the branch is unconditional, whether it is
1219 compact, whether there is no delay-slot instruction available to fill
1220 in, whether it stores the link address implicitly in $ra, whether
1221 relaxation of out-of-range 32-bit branches to a sequence of
1222 instructions is enabled, and whether the displacement of a branch is
1223 too large to fit as an immediate argument of a 16-bit and a 32-bit
1224 branch, respectively. */
1225 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1226 uncond, compact, link, nods, \
1227 relax32, toofar16, toofar32) \
1230 | (((at) & 0x1f) << 8) \
1231 | ((insn32) ? 0x2000 : 0) \
1232 | ((pic) ? 0x4000 : 0) \
1233 | ((uncond) ? 0x8000 : 0) \
1234 | ((compact) ? 0x10000 : 0) \
1235 | ((link) ? 0x20000 : 0) \
1236 | ((nods) ? 0x40000 : 0) \
1237 | ((relax32) ? 0x80000 : 0) \
1238 | ((toofar16) ? 0x100000 : 0) \
1239 | ((toofar32) ? 0x200000 : 0))
1240 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1241 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1242 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1243 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1244 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1245 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1246 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1247 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1248 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1249 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1251 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1254 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1255 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1256 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1258 /* Sign-extend 16-bit value X. */
1259 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1261 /* Is the given value a sign-extended 32-bit value? */
1262 #define IS_SEXT_32BIT_NUM(x) \
1263 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1264 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1266 /* Is the given value a sign-extended 16-bit value? */
1267 #define IS_SEXT_16BIT_NUM(x) \
1268 (((x) &~ (offsetT) 0x7fff) == 0 \
1269 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1271 /* Is the given value a sign-extended 12-bit value? */
1272 #define IS_SEXT_12BIT_NUM(x) \
1273 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1275 /* Is the given value a sign-extended 9-bit value? */
1276 #define IS_SEXT_9BIT_NUM(x) \
1277 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1279 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1280 #define IS_ZEXT_32BIT_NUM(x) \
1281 (((x) &~ (offsetT) 0xffffffff) == 0 \
1282 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1284 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1286 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1287 (((STRUCT) >> (SHIFT)) & (MASK))
1289 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1290 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1292 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1293 : EXTRACT_BITS ((INSN).insn_opcode, \
1294 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1295 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1296 EXTRACT_BITS ((INSN).insn_opcode, \
1297 MIPS16OP_MASK_##FIELD, \
1298 MIPS16OP_SH_##FIELD)
1300 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1301 #define MIPS16_EXTEND (0xf000U << 16)
1303 /* Whether or not we are emitting a branch-likely macro. */
1304 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1306 /* Global variables used when generating relaxable macros. See the
1307 comment above RELAX_ENCODE for more details about how relaxation
1310 /* 0 if we're not emitting a relaxable macro.
1311 1 if we're emitting the first of the two relaxation alternatives.
1312 2 if we're emitting the second alternative. */
1315 /* The first relaxable fixup in the current frag. (In other words,
1316 the first fixup that refers to relaxable code.) */
1319 /* sizes[0] says how many bytes of the first alternative are stored in
1320 the current frag. Likewise sizes[1] for the second alternative. */
1321 unsigned int sizes
[2];
1323 /* The symbol on which the choice of sequence depends. */
1327 /* Global variables used to decide whether a macro needs a warning. */
1329 /* True if the macro is in a branch delay slot. */
1330 bfd_boolean delay_slot_p
;
1332 /* Set to the length in bytes required if the macro is in a delay slot
1333 that requires a specific length of instruction, otherwise zero. */
1334 unsigned int delay_slot_length
;
1336 /* For relaxable macros, sizes[0] is the length of the first alternative
1337 in bytes and sizes[1] is the length of the second alternative.
1338 For non-relaxable macros, both elements give the length of the
1340 unsigned int sizes
[2];
1342 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1343 instruction of the first alternative in bytes and first_insn_sizes[1]
1344 is the length of the first instruction of the second alternative.
1345 For non-relaxable macros, both elements give the length of the first
1346 instruction in bytes.
1348 Set to zero if we haven't yet seen the first instruction. */
1349 unsigned int first_insn_sizes
[2];
1351 /* For relaxable macros, insns[0] is the number of instructions for the
1352 first alternative and insns[1] is the number of instructions for the
1355 For non-relaxable macros, both elements give the number of
1356 instructions for the macro. */
1357 unsigned int insns
[2];
1359 /* The first variant frag for this macro. */
1361 } mips_macro_warning
;
1363 /* Prototypes for static functions. */
1365 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1367 static void append_insn
1368 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1369 bfd_boolean expansionp
);
1370 static void mips_no_prev_insn (void);
1371 static void macro_build (expressionS
*, const char *, const char *, ...);
1372 static void mips16_macro_build
1373 (expressionS
*, const char *, const char *, va_list *);
1374 static void load_register (int, expressionS
*, int);
1375 static void macro_start (void);
1376 static void macro_end (void);
1377 static void macro (struct mips_cl_insn
*ip
, char *str
);
1378 static void mips16_macro (struct mips_cl_insn
* ip
);
1379 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1380 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1381 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1382 static void mips16_immed
1383 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1384 unsigned int, unsigned long *);
1385 static size_t my_getSmallExpression
1386 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1387 static void my_getExpression (expressionS
*, char *);
1388 static void s_align (int);
1389 static void s_change_sec (int);
1390 static void s_change_section (int);
1391 static void s_cons (int);
1392 static void s_float_cons (int);
1393 static void s_mips_globl (int);
1394 static void s_option (int);
1395 static void s_mipsset (int);
1396 static void s_abicalls (int);
1397 static void s_cpload (int);
1398 static void s_cpsetup (int);
1399 static void s_cplocal (int);
1400 static void s_cprestore (int);
1401 static void s_cpreturn (int);
1402 static void s_dtprelword (int);
1403 static void s_dtpreldword (int);
1404 static void s_tprelword (int);
1405 static void s_tpreldword (int);
1406 static void s_gpvalue (int);
1407 static void s_gpword (int);
1408 static void s_gpdword (int);
1409 static void s_ehword (int);
1410 static void s_cpadd (int);
1411 static void s_insn (int);
1412 static void s_nan (int);
1413 static void s_module (int);
1414 static void s_mips_ent (int);
1415 static void s_mips_end (int);
1416 static void s_mips_frame (int);
1417 static void s_mips_mask (int reg_type
);
1418 static void s_mips_stab (int);
1419 static void s_mips_weakext (int);
1420 static void s_mips_file (int);
1421 static void s_mips_loc (int);
1422 static bfd_boolean
pic_need_relax (symbolS
*);
1423 static int relaxed_branch_length (fragS
*, asection
*, int);
1424 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1425 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1426 static void file_mips_check_options (void);
1428 /* Table and functions used to map between CPU/ISA names, and
1429 ISA levels, and CPU numbers. */
1431 struct mips_cpu_info
1433 const char *name
; /* CPU or ISA name. */
1434 int flags
; /* MIPS_CPU_* flags. */
1435 int ase
; /* Set of ASEs implemented by the CPU. */
1436 int isa
; /* ISA level. */
1437 int cpu
; /* CPU number (default CPU if ISA). */
1440 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1442 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1443 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1444 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1446 /* Command-line options. */
1447 const char *md_shortopts
= "O::g::G:";
1451 OPTION_MARCH
= OPTION_MD_BASE
,
1483 OPTION_NO_SMARTMIPS
,
1493 OPTION_NO_MICROMIPS
,
1508 OPTION_M7000_HILO_FIX
,
1509 OPTION_MNO_7000_HILO_FIX
,
1513 OPTION_NO_FIX_RM7000
,
1514 OPTION_FIX_LOONGSON3_LLSC
,
1515 OPTION_NO_FIX_LOONGSON3_LLSC
,
1516 OPTION_FIX_LOONGSON2F_JUMP
,
1517 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1518 OPTION_FIX_LOONGSON2F_NOP
,
1519 OPTION_NO_FIX_LOONGSON2F_NOP
,
1521 OPTION_NO_FIX_VR4120
,
1523 OPTION_NO_FIX_VR4130
,
1524 OPTION_FIX_CN63XXP1
,
1525 OPTION_NO_FIX_CN63XXP1
,
1527 OPTION_NO_FIX_R5900
,
1534 OPTION_CONSTRUCT_FLOATS
,
1535 OPTION_NO_CONSTRUCT_FLOATS
,
1539 OPTION_RELAX_BRANCH
,
1540 OPTION_NO_RELAX_BRANCH
,
1541 OPTION_IGNORE_BRANCH_ISA
,
1542 OPTION_NO_IGNORE_BRANCH_ISA
,
1551 OPTION_SINGLE_FLOAT
,
1552 OPTION_DOUBLE_FLOAT
,
1565 OPTION_MVXWORKS_PIC
,
1568 OPTION_NO_ODD_SPREG
,
1571 OPTION_LOONGSON_MMI
,
1572 OPTION_NO_LOONGSON_MMI
,
1573 OPTION_LOONGSON_CAM
,
1574 OPTION_NO_LOONGSON_CAM
,
1575 OPTION_LOONGSON_EXT
,
1576 OPTION_NO_LOONGSON_EXT
,
1577 OPTION_LOONGSON_EXT2
,
1578 OPTION_NO_LOONGSON_EXT2
,
1582 struct option md_longopts
[] =
1584 /* Options which specify architecture. */
1585 {"march", required_argument
, NULL
, OPTION_MARCH
},
1586 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1587 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1588 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1589 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1590 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1591 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1592 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1593 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1594 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1595 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1596 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1597 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1598 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1599 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1600 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1601 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1602 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1604 /* Options which specify Application Specific Extensions (ASEs). */
1605 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1606 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1607 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1608 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1609 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1610 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1611 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1612 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1613 {"mmt", no_argument
, NULL
, OPTION_MT
},
1614 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1615 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1616 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1617 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1618 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1619 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1620 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1621 {"meva", no_argument
, NULL
, OPTION_EVA
},
1622 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1623 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1624 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1625 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1626 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1627 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1628 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1629 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1630 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1631 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1632 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1633 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1634 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1635 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1636 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1637 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1638 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1639 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1640 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1641 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1642 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1643 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1644 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1645 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1646 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1648 /* Old-style architecture options. Don't add more of these. */
1649 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1650 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1651 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1652 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1653 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1654 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1655 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1656 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1658 /* Options which enable bug fixes. */
1659 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1660 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1661 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1662 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1663 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1664 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1665 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1666 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1667 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1668 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1669 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1670 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1671 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1672 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1673 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1674 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1675 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1676 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1677 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1678 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1679 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1681 /* Miscellaneous options. */
1682 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1683 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1684 {"break", no_argument
, NULL
, OPTION_BREAK
},
1685 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1686 {"EB", no_argument
, NULL
, OPTION_EB
},
1687 {"EL", no_argument
, NULL
, OPTION_EL
},
1688 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1689 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1690 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1691 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1692 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1693 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1694 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1695 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1696 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1697 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1698 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1699 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1700 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1701 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1702 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1703 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1704 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1705 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1706 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1707 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1708 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1709 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1710 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1712 /* Strictly speaking this next option is ELF specific,
1713 but we allow it for other ports as well in order to
1714 make testing easier. */
1715 {"32", no_argument
, NULL
, OPTION_32
},
1717 /* ELF-specific options. */
1718 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1719 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1720 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1721 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1722 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1723 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1724 {"n32", no_argument
, NULL
, OPTION_N32
},
1725 {"64", no_argument
, NULL
, OPTION_64
},
1726 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1727 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1728 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1729 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1730 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1731 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1733 {NULL
, no_argument
, NULL
, 0}
1735 size_t md_longopts_size
= sizeof (md_longopts
);
1737 /* Information about either an Application Specific Extension or an
1738 optional architecture feature that, for simplicity, we treat in the
1739 same way as an ASE. */
1742 /* The name of the ASE, used in both the command-line and .set options. */
1745 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1746 and 64-bit architectures, the flags here refer to the subset that
1747 is available on both. */
1750 /* The ASE_* flag used for instructions that are available on 64-bit
1751 architectures but that are not included in FLAGS. */
1752 unsigned int flags64
;
1754 /* The command-line options that turn the ASE on and off. */
1758 /* The minimum required architecture revisions for MIPS32, MIPS64,
1759 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1762 int micromips32_rev
;
1763 int micromips64_rev
;
1765 /* The architecture where the ASE was removed or -1 if the extension has not
1770 /* A table of all supported ASEs. */
1771 static const struct mips_ase mips_ases
[] = {
1772 { "dsp", ASE_DSP
, ASE_DSP64
,
1773 OPTION_DSP
, OPTION_NO_DSP
,
1777 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1778 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1782 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1783 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1787 { "eva", ASE_EVA
, 0,
1788 OPTION_EVA
, OPTION_NO_EVA
,
1792 { "mcu", ASE_MCU
, 0,
1793 OPTION_MCU
, OPTION_NO_MCU
,
1797 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1798 { "mdmx", ASE_MDMX
, 0,
1799 OPTION_MDMX
, OPTION_NO_MDMX
,
1803 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1804 { "mips3d", ASE_MIPS3D
, 0,
1805 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1810 OPTION_MT
, OPTION_NO_MT
,
1814 { "smartmips", ASE_SMARTMIPS
, 0,
1815 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1819 { "virt", ASE_VIRT
, ASE_VIRT64
,
1820 OPTION_VIRT
, OPTION_NO_VIRT
,
1824 { "msa", ASE_MSA
, ASE_MSA64
,
1825 OPTION_MSA
, OPTION_NO_MSA
,
1829 { "xpa", ASE_XPA
, 0,
1830 OPTION_XPA
, OPTION_NO_XPA
,
1834 { "mips16e2", ASE_MIPS16E2
, 0,
1835 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1839 { "crc", ASE_CRC
, ASE_CRC64
,
1840 OPTION_CRC
, OPTION_NO_CRC
,
1844 { "ginv", ASE_GINV
, 0,
1845 OPTION_GINV
, OPTION_NO_GINV
,
1849 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1850 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1854 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1855 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1859 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1860 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1864 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1865 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1870 /* The set of ASEs that require -mfp64. */
1871 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1873 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1874 static const unsigned int mips_ase_groups
[] = {
1875 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1876 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1881 The following pseudo-ops from the Kane and Heinrich MIPS book
1882 should be defined here, but are currently unsupported: .alias,
1883 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1885 The following pseudo-ops from the Kane and Heinrich MIPS book are
1886 specific to the type of debugging information being generated, and
1887 should be defined by the object format: .aent, .begin, .bend,
1888 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1891 The following pseudo-ops from the Kane and Heinrich MIPS book are
1892 not MIPS CPU specific, but are also not specific to the object file
1893 format. This file is probably the best place to define them, but
1894 they are not currently supported: .asm0, .endr, .lab, .struct. */
1896 static const pseudo_typeS mips_pseudo_table
[] =
1898 /* MIPS specific pseudo-ops. */
1899 {"option", s_option
, 0},
1900 {"set", s_mipsset
, 0},
1901 {"rdata", s_change_sec
, 'r'},
1902 {"sdata", s_change_sec
, 's'},
1903 {"livereg", s_ignore
, 0},
1904 {"abicalls", s_abicalls
, 0},
1905 {"cpload", s_cpload
, 0},
1906 {"cpsetup", s_cpsetup
, 0},
1907 {"cplocal", s_cplocal
, 0},
1908 {"cprestore", s_cprestore
, 0},
1909 {"cpreturn", s_cpreturn
, 0},
1910 {"dtprelword", s_dtprelword
, 0},
1911 {"dtpreldword", s_dtpreldword
, 0},
1912 {"tprelword", s_tprelword
, 0},
1913 {"tpreldword", s_tpreldword
, 0},
1914 {"gpvalue", s_gpvalue
, 0},
1915 {"gpword", s_gpword
, 0},
1916 {"gpdword", s_gpdword
, 0},
1917 {"ehword", s_ehword
, 0},
1918 {"cpadd", s_cpadd
, 0},
1919 {"insn", s_insn
, 0},
1921 {"module", s_module
, 0},
1923 /* Relatively generic pseudo-ops that happen to be used on MIPS
1925 {"asciiz", stringer
, 8 + 1},
1926 {"bss", s_change_sec
, 'b'},
1928 {"half", s_cons
, 1},
1929 {"dword", s_cons
, 3},
1930 {"weakext", s_mips_weakext
, 0},
1931 {"origin", s_org
, 0},
1932 {"repeat", s_rept
, 0},
1934 /* For MIPS this is non-standard, but we define it for consistency. */
1935 {"sbss", s_change_sec
, 'B'},
1937 /* These pseudo-ops are defined in read.c, but must be overridden
1938 here for one reason or another. */
1939 {"align", s_align
, 0},
1940 {"byte", s_cons
, 0},
1941 {"data", s_change_sec
, 'd'},
1942 {"double", s_float_cons
, 'd'},
1943 {"float", s_float_cons
, 'f'},
1944 {"globl", s_mips_globl
, 0},
1945 {"global", s_mips_globl
, 0},
1946 {"hword", s_cons
, 1},
1948 {"long", s_cons
, 2},
1949 {"octa", s_cons
, 4},
1950 {"quad", s_cons
, 3},
1951 {"section", s_change_section
, 0},
1952 {"short", s_cons
, 1},
1953 {"single", s_float_cons
, 'f'},
1954 {"stabd", s_mips_stab
, 'd'},
1955 {"stabn", s_mips_stab
, 'n'},
1956 {"stabs", s_mips_stab
, 's'},
1957 {"text", s_change_sec
, 't'},
1958 {"word", s_cons
, 2},
1960 { "extern", ecoff_directive_extern
, 0},
1965 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1967 /* These pseudo-ops should be defined by the object file format.
1968 However, a.out doesn't support them, so we have versions here. */
1969 {"aent", s_mips_ent
, 1},
1970 {"bgnb", s_ignore
, 0},
1971 {"end", s_mips_end
, 0},
1972 {"endb", s_ignore
, 0},
1973 {"ent", s_mips_ent
, 0},
1974 {"file", s_mips_file
, 0},
1975 {"fmask", s_mips_mask
, 'F'},
1976 {"frame", s_mips_frame
, 0},
1977 {"loc", s_mips_loc
, 0},
1978 {"mask", s_mips_mask
, 'R'},
1979 {"verstamp", s_ignore
, 0},
1983 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1984 purpose of the `.dc.a' internal pseudo-op. */
1987 mips_address_bytes (void)
1989 file_mips_check_options ();
1990 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1993 extern void pop_insert (const pseudo_typeS
*);
1996 mips_pop_insert (void)
1998 pop_insert (mips_pseudo_table
);
1999 if (! ECOFF_DEBUGGING
)
2000 pop_insert (mips_nonecoff_pseudo_table
);
2003 /* Symbols labelling the current insn. */
2005 struct insn_label_list
2007 struct insn_label_list
*next
;
2011 static struct insn_label_list
*free_insn_labels
;
2012 #define label_list tc_segment_info_data.labels
2014 static void mips_clear_insn_labels (void);
2015 static void mips_mark_labels (void);
2016 static void mips_compressed_mark_labels (void);
2019 mips_clear_insn_labels (void)
2021 struct insn_label_list
**pl
;
2022 segment_info_type
*si
;
2026 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2029 si
= seg_info (now_seg
);
2030 *pl
= si
->label_list
;
2031 si
->label_list
= NULL
;
2035 /* Mark instruction labels in MIPS16/microMIPS mode. */
2038 mips_mark_labels (void)
2040 if (HAVE_CODE_COMPRESSION
)
2041 mips_compressed_mark_labels ();
2044 static char *expr_end
;
2046 /* An expression in a macro instruction. This is set by mips_ip and
2047 mips16_ip and when populated is always an O_constant. */
2049 static expressionS imm_expr
;
2051 /* The relocatable field in an instruction and the relocs associated
2052 with it. These variables are used for instructions like LUI and
2053 JAL as well as true offsets. They are also used for address
2054 operands in macros. */
2056 static expressionS offset_expr
;
2057 static bfd_reloc_code_real_type offset_reloc
[3]
2058 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2060 /* This is set to the resulting size of the instruction to be produced
2061 by mips16_ip if an explicit extension is used or by mips_ip if an
2062 explicit size is supplied. */
2064 static unsigned int forced_insn_length
;
2066 /* True if we are assembling an instruction. All dot symbols defined during
2067 this time should be treated as code labels. */
2069 static bfd_boolean mips_assembling_insn
;
2071 /* The pdr segment for per procedure frame/regmask info. Not used for
2074 static segT pdr_seg
;
2076 /* The default target format to use. */
2078 #if defined (TE_FreeBSD)
2079 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2080 #elif defined (TE_TMIPS)
2081 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2083 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2087 mips_target_format (void)
2089 switch (OUTPUT_FLAVOR
)
2091 case bfd_target_elf_flavour
:
2093 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2094 return (target_big_endian
2095 ? "elf32-bigmips-vxworks"
2096 : "elf32-littlemips-vxworks");
2098 return (target_big_endian
2099 ? (HAVE_64BIT_OBJECTS
2100 ? ELF_TARGET ("elf64-", "big")
2102 ? ELF_TARGET ("elf32-n", "big")
2103 : ELF_TARGET ("elf32-", "big")))
2104 : (HAVE_64BIT_OBJECTS
2105 ? ELF_TARGET ("elf64-", "little")
2107 ? ELF_TARGET ("elf32-n", "little")
2108 : ELF_TARGET ("elf32-", "little"))));
2115 /* Return the ISA revision that is currently in use, or 0 if we are
2116 generating code for MIPS V or below. */
2121 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2124 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2127 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2130 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2133 /* microMIPS implies revision 2 or above. */
2134 if (mips_opts
.micromips
)
2137 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2143 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2146 mips_ase_mask (unsigned int flags
)
2150 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2151 if (flags
& mips_ase_groups
[i
])
2152 flags
|= mips_ase_groups
[i
];
2156 /* Check whether the current ISA supports ASE. Issue a warning if
2160 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2164 static unsigned int warned_isa
;
2165 static unsigned int warned_fp32
;
2167 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2168 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2170 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2171 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2172 && (warned_isa
& ase
->flags
) != ase
->flags
)
2174 warned_isa
|= ase
->flags
;
2175 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2176 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2178 as_warn (_("the %d-bit %s architecture does not support the"
2179 " `%s' extension"), size
, base
, ase
->name
);
2181 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2182 ase
->name
, base
, size
, min_rev
);
2184 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2185 && (warned_isa
& ase
->flags
) != ase
->flags
)
2187 warned_isa
|= ase
->flags
;
2188 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2189 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2190 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2191 ase
->name
, base
, size
, ase
->rem_rev
);
2194 if ((ase
->flags
& FP64_ASES
)
2195 && mips_opts
.fp
!= 64
2196 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2198 warned_fp32
|= ase
->flags
;
2199 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2203 /* Check all enabled ASEs to see whether they are supported by the
2204 chosen architecture. */
2207 mips_check_isa_supports_ases (void)
2209 unsigned int i
, mask
;
2211 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2213 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2214 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2215 mips_check_isa_supports_ase (&mips_ases
[i
]);
2219 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2220 that were affected. */
2223 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2224 bfd_boolean enabled_p
)
2228 mask
= mips_ase_mask (ase
->flags
);
2231 /* Clear combination ASE flags, which need to be recalculated based on
2232 updated regular ASE settings. */
2233 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2236 opts
->ase
|= ase
->flags
;
2238 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2239 instructions which are only valid when both ASEs are enabled.
2240 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2241 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2243 opts
->ase
|= ASE_XPA_VIRT
;
2244 mask
|= ASE_XPA_VIRT
;
2246 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2248 opts
->ase
|= ASE_MIPS16E2_MT
;
2249 mask
|= ASE_MIPS16E2_MT
;
2252 /* The EVA Extension has instructions which are only valid when the R6 ISA
2253 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2255 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2257 opts
->ase
|= ASE_EVA_R6
;
2264 /* Return the ASE called NAME, or null if none. */
2266 static const struct mips_ase
*
2267 mips_lookup_ase (const char *name
)
2271 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2272 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2273 return &mips_ases
[i
];
2277 /* Return the length of a microMIPS instruction in bytes. If bits of
2278 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2279 otherwise it is a 32-bit instruction. */
2281 static inline unsigned int
2282 micromips_insn_length (const struct mips_opcode
*mo
)
2284 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2287 /* Return the length of MIPS16 instruction OPCODE. */
2289 static inline unsigned int
2290 mips16_opcode_length (unsigned long opcode
)
2292 return (opcode
>> 16) == 0 ? 2 : 4;
2295 /* Return the length of instruction INSN. */
2297 static inline unsigned int
2298 insn_length (const struct mips_cl_insn
*insn
)
2300 if (mips_opts
.micromips
)
2301 return micromips_insn_length (insn
->insn_mo
);
2302 else if (mips_opts
.mips16
)
2303 return mips16_opcode_length (insn
->insn_opcode
);
2308 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2311 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2316 insn
->insn_opcode
= mo
->match
;
2319 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2320 insn
->fixp
[i
] = NULL
;
2321 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2322 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2323 insn
->mips16_absolute_jump_p
= 0;
2324 insn
->complete_p
= 0;
2325 insn
->cleared_p
= 0;
2328 /* Get a list of all the operands in INSN. */
2330 static const struct mips_operand_array
*
2331 insn_operands (const struct mips_cl_insn
*insn
)
2333 if (insn
->insn_mo
>= &mips_opcodes
[0]
2334 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2335 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2337 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2338 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2339 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2341 if (insn
->insn_mo
>= µmips_opcodes
[0]
2342 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2343 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2348 /* Get a description of operand OPNO of INSN. */
2350 static const struct mips_operand
*
2351 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2353 const struct mips_operand_array
*operands
;
2355 operands
= insn_operands (insn
);
2356 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2358 return operands
->operand
[opno
];
2361 /* Install UVAL as the value of OPERAND in INSN. */
2364 insn_insert_operand (struct mips_cl_insn
*insn
,
2365 const struct mips_operand
*operand
, unsigned int uval
)
2367 if (mips_opts
.mips16
2368 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2369 && mips_opcode_32bit_p (insn
->insn_mo
))
2370 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2372 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2375 /* Extract the value of OPERAND from INSN. */
2377 static inline unsigned
2378 insn_extract_operand (const struct mips_cl_insn
*insn
,
2379 const struct mips_operand
*operand
)
2381 return mips_extract_operand (operand
, insn
->insn_opcode
);
2384 /* Record the current MIPS16/microMIPS mode in now_seg. */
2387 mips_record_compressed_mode (void)
2389 segment_info_type
*si
;
2391 si
= seg_info (now_seg
);
2392 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2393 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2394 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2395 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2398 /* Read a standard MIPS instruction from BUF. */
2400 static unsigned long
2401 read_insn (char *buf
)
2403 if (target_big_endian
)
2404 return bfd_getb32 ((bfd_byte
*) buf
);
2406 return bfd_getl32 ((bfd_byte
*) buf
);
2409 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2413 write_insn (char *buf
, unsigned int insn
)
2415 md_number_to_chars (buf
, insn
, 4);
2419 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2420 has length LENGTH. */
2422 static unsigned long
2423 read_compressed_insn (char *buf
, unsigned int length
)
2429 for (i
= 0; i
< length
; i
+= 2)
2432 if (target_big_endian
)
2433 insn
|= bfd_getb16 ((char *) buf
);
2435 insn
|= bfd_getl16 ((char *) buf
);
2441 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2442 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2445 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2449 for (i
= 0; i
< length
; i
+= 2)
2450 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2451 return buf
+ length
;
2454 /* Install INSN at the location specified by its "frag" and "where" fields. */
2457 install_insn (const struct mips_cl_insn
*insn
)
2459 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2460 if (HAVE_CODE_COMPRESSION
)
2461 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2463 write_insn (f
, insn
->insn_opcode
);
2464 mips_record_compressed_mode ();
2467 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2468 and install the opcode in the new location. */
2471 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2476 insn
->where
= where
;
2477 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2478 if (insn
->fixp
[i
] != NULL
)
2480 insn
->fixp
[i
]->fx_frag
= frag
;
2481 insn
->fixp
[i
]->fx_where
= where
;
2483 install_insn (insn
);
2486 /* Add INSN to the end of the output. */
2489 add_fixed_insn (struct mips_cl_insn
*insn
)
2491 char *f
= frag_more (insn_length (insn
));
2492 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2495 /* Start a variant frag and move INSN to the start of the variant part,
2496 marking it as fixed. The other arguments are as for frag_var. */
2499 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2500 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2502 frag_grow (max_chars
);
2503 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2505 frag_var (rs_machine_dependent
, max_chars
, var
,
2506 subtype
, symbol
, offset
, NULL
);
2509 /* Insert N copies of INSN into the history buffer, starting at
2510 position FIRST. Neither FIRST nor N need to be clipped. */
2513 insert_into_history (unsigned int first
, unsigned int n
,
2514 const struct mips_cl_insn
*insn
)
2516 if (mips_relax
.sequence
!= 2)
2520 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2522 history
[i
] = history
[i
- n
];
2528 /* Clear the error in insn_error. */
2531 clear_insn_error (void)
2533 memset (&insn_error
, 0, sizeof (insn_error
));
2536 /* Possibly record error message MSG for the current instruction.
2537 If the error is about a particular argument, ARGNUM is the 1-based
2538 number of that argument, otherwise it is 0. FORMAT is the format
2539 of MSG. Return true if MSG was used, false if the current message
2543 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2548 /* Give priority to errors against specific arguments, and to
2549 the first whole-instruction message. */
2555 /* Keep insn_error if it is against a later argument. */
2556 if (argnum
< insn_error
.min_argnum
)
2559 /* If both errors are against the same argument but are different,
2560 give up on reporting a specific error for this argument.
2561 See the comment about mips_insn_error for details. */
2562 if (argnum
== insn_error
.min_argnum
2564 && strcmp (insn_error
.msg
, msg
) != 0)
2567 insn_error
.min_argnum
+= 1;
2571 insn_error
.min_argnum
= argnum
;
2572 insn_error
.format
= format
;
2573 insn_error
.msg
= msg
;
2577 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2578 as for set_insn_error_format. */
2581 set_insn_error (int argnum
, const char *msg
)
2583 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2586 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2587 as for set_insn_error_format. */
2590 set_insn_error_i (int argnum
, const char *msg
, int i
)
2592 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2596 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2597 are as for set_insn_error_format. */
2600 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2602 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2604 insn_error
.u
.ss
[0] = s1
;
2605 insn_error
.u
.ss
[1] = s2
;
2609 /* Report the error in insn_error, which is against assembly code STR. */
2612 report_insn_error (const char *str
)
2614 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2616 switch (insn_error
.format
)
2623 as_bad (msg
, insn_error
.u
.i
, str
);
2627 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2631 free ((char *) msg
);
2634 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2635 the idea is to make it obvious at a glance that each errata is
2639 init_vr4120_conflicts (void)
2641 #define CONFLICT(FIRST, SECOND) \
2642 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2644 /* Errata 21 - [D]DIV[U] after [D]MACC */
2645 CONFLICT (MACC
, DIV
);
2646 CONFLICT (DMACC
, DIV
);
2648 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2649 CONFLICT (DMULT
, DMULT
);
2650 CONFLICT (DMULT
, DMACC
);
2651 CONFLICT (DMACC
, DMULT
);
2652 CONFLICT (DMACC
, DMACC
);
2654 /* Errata 24 - MT{LO,HI} after [D]MACC */
2655 CONFLICT (MACC
, MTHILO
);
2656 CONFLICT (DMACC
, MTHILO
);
2658 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2659 instruction is executed immediately after a MACC or DMACC
2660 instruction, the result of [either instruction] is incorrect." */
2661 CONFLICT (MACC
, MULT
);
2662 CONFLICT (MACC
, DMULT
);
2663 CONFLICT (DMACC
, MULT
);
2664 CONFLICT (DMACC
, DMULT
);
2666 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2667 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2668 DDIV or DDIVU instruction, the result of the MACC or
2669 DMACC instruction is incorrect.". */
2670 CONFLICT (DMULT
, MACC
);
2671 CONFLICT (DMULT
, DMACC
);
2672 CONFLICT (DIV
, MACC
);
2673 CONFLICT (DIV
, DMACC
);
2683 #define RNUM_MASK 0x00000ff
2684 #define RTYPE_MASK 0x0ffff00
2685 #define RTYPE_NUM 0x0000100
2686 #define RTYPE_FPU 0x0000200
2687 #define RTYPE_FCC 0x0000400
2688 #define RTYPE_VEC 0x0000800
2689 #define RTYPE_GP 0x0001000
2690 #define RTYPE_CP0 0x0002000
2691 #define RTYPE_PC 0x0004000
2692 #define RTYPE_ACC 0x0008000
2693 #define RTYPE_CCC 0x0010000
2694 #define RTYPE_VI 0x0020000
2695 #define RTYPE_VF 0x0040000
2696 #define RTYPE_R5900_I 0x0080000
2697 #define RTYPE_R5900_Q 0x0100000
2698 #define RTYPE_R5900_R 0x0200000
2699 #define RTYPE_R5900_ACC 0x0400000
2700 #define RTYPE_MSA 0x0800000
2701 #define RWARN 0x8000000
2703 #define GENERIC_REGISTER_NUMBERS \
2704 {"$0", RTYPE_NUM | 0}, \
2705 {"$1", RTYPE_NUM | 1}, \
2706 {"$2", RTYPE_NUM | 2}, \
2707 {"$3", RTYPE_NUM | 3}, \
2708 {"$4", RTYPE_NUM | 4}, \
2709 {"$5", RTYPE_NUM | 5}, \
2710 {"$6", RTYPE_NUM | 6}, \
2711 {"$7", RTYPE_NUM | 7}, \
2712 {"$8", RTYPE_NUM | 8}, \
2713 {"$9", RTYPE_NUM | 9}, \
2714 {"$10", RTYPE_NUM | 10}, \
2715 {"$11", RTYPE_NUM | 11}, \
2716 {"$12", RTYPE_NUM | 12}, \
2717 {"$13", RTYPE_NUM | 13}, \
2718 {"$14", RTYPE_NUM | 14}, \
2719 {"$15", RTYPE_NUM | 15}, \
2720 {"$16", RTYPE_NUM | 16}, \
2721 {"$17", RTYPE_NUM | 17}, \
2722 {"$18", RTYPE_NUM | 18}, \
2723 {"$19", RTYPE_NUM | 19}, \
2724 {"$20", RTYPE_NUM | 20}, \
2725 {"$21", RTYPE_NUM | 21}, \
2726 {"$22", RTYPE_NUM | 22}, \
2727 {"$23", RTYPE_NUM | 23}, \
2728 {"$24", RTYPE_NUM | 24}, \
2729 {"$25", RTYPE_NUM | 25}, \
2730 {"$26", RTYPE_NUM | 26}, \
2731 {"$27", RTYPE_NUM | 27}, \
2732 {"$28", RTYPE_NUM | 28}, \
2733 {"$29", RTYPE_NUM | 29}, \
2734 {"$30", RTYPE_NUM | 30}, \
2735 {"$31", RTYPE_NUM | 31}
2737 #define FPU_REGISTER_NAMES \
2738 {"$f0", RTYPE_FPU | 0}, \
2739 {"$f1", RTYPE_FPU | 1}, \
2740 {"$f2", RTYPE_FPU | 2}, \
2741 {"$f3", RTYPE_FPU | 3}, \
2742 {"$f4", RTYPE_FPU | 4}, \
2743 {"$f5", RTYPE_FPU | 5}, \
2744 {"$f6", RTYPE_FPU | 6}, \
2745 {"$f7", RTYPE_FPU | 7}, \
2746 {"$f8", RTYPE_FPU | 8}, \
2747 {"$f9", RTYPE_FPU | 9}, \
2748 {"$f10", RTYPE_FPU | 10}, \
2749 {"$f11", RTYPE_FPU | 11}, \
2750 {"$f12", RTYPE_FPU | 12}, \
2751 {"$f13", RTYPE_FPU | 13}, \
2752 {"$f14", RTYPE_FPU | 14}, \
2753 {"$f15", RTYPE_FPU | 15}, \
2754 {"$f16", RTYPE_FPU | 16}, \
2755 {"$f17", RTYPE_FPU | 17}, \
2756 {"$f18", RTYPE_FPU | 18}, \
2757 {"$f19", RTYPE_FPU | 19}, \
2758 {"$f20", RTYPE_FPU | 20}, \
2759 {"$f21", RTYPE_FPU | 21}, \
2760 {"$f22", RTYPE_FPU | 22}, \
2761 {"$f23", RTYPE_FPU | 23}, \
2762 {"$f24", RTYPE_FPU | 24}, \
2763 {"$f25", RTYPE_FPU | 25}, \
2764 {"$f26", RTYPE_FPU | 26}, \
2765 {"$f27", RTYPE_FPU | 27}, \
2766 {"$f28", RTYPE_FPU | 28}, \
2767 {"$f29", RTYPE_FPU | 29}, \
2768 {"$f30", RTYPE_FPU | 30}, \
2769 {"$f31", RTYPE_FPU | 31}
2771 #define FPU_CONDITION_CODE_NAMES \
2772 {"$fcc0", RTYPE_FCC | 0}, \
2773 {"$fcc1", RTYPE_FCC | 1}, \
2774 {"$fcc2", RTYPE_FCC | 2}, \
2775 {"$fcc3", RTYPE_FCC | 3}, \
2776 {"$fcc4", RTYPE_FCC | 4}, \
2777 {"$fcc5", RTYPE_FCC | 5}, \
2778 {"$fcc6", RTYPE_FCC | 6}, \
2779 {"$fcc7", RTYPE_FCC | 7}
2781 #define COPROC_CONDITION_CODE_NAMES \
2782 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2783 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2784 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2785 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2786 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2787 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2788 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2789 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2791 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2792 {"$a4", RTYPE_GP | 8}, \
2793 {"$a5", RTYPE_GP | 9}, \
2794 {"$a6", RTYPE_GP | 10}, \
2795 {"$a7", RTYPE_GP | 11}, \
2796 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2797 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2798 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2799 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2800 {"$t0", RTYPE_GP | 12}, \
2801 {"$t1", RTYPE_GP | 13}, \
2802 {"$t2", RTYPE_GP | 14}, \
2803 {"$t3", RTYPE_GP | 15}
2805 #define O32_SYMBOLIC_REGISTER_NAMES \
2806 {"$t0", RTYPE_GP | 8}, \
2807 {"$t1", RTYPE_GP | 9}, \
2808 {"$t2", RTYPE_GP | 10}, \
2809 {"$t3", RTYPE_GP | 11}, \
2810 {"$t4", RTYPE_GP | 12}, \
2811 {"$t5", RTYPE_GP | 13}, \
2812 {"$t6", RTYPE_GP | 14}, \
2813 {"$t7", RTYPE_GP | 15}, \
2814 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2815 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2816 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2817 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2819 /* Remaining symbolic register names. */
2820 #define SYMBOLIC_REGISTER_NAMES \
2821 {"$zero", RTYPE_GP | 0}, \
2822 {"$at", RTYPE_GP | 1}, \
2823 {"$AT", RTYPE_GP | 1}, \
2824 {"$v0", RTYPE_GP | 2}, \
2825 {"$v1", RTYPE_GP | 3}, \
2826 {"$a0", RTYPE_GP | 4}, \
2827 {"$a1", RTYPE_GP | 5}, \
2828 {"$a2", RTYPE_GP | 6}, \
2829 {"$a3", RTYPE_GP | 7}, \
2830 {"$s0", RTYPE_GP | 16}, \
2831 {"$s1", RTYPE_GP | 17}, \
2832 {"$s2", RTYPE_GP | 18}, \
2833 {"$s3", RTYPE_GP | 19}, \
2834 {"$s4", RTYPE_GP | 20}, \
2835 {"$s5", RTYPE_GP | 21}, \
2836 {"$s6", RTYPE_GP | 22}, \
2837 {"$s7", RTYPE_GP | 23}, \
2838 {"$t8", RTYPE_GP | 24}, \
2839 {"$t9", RTYPE_GP | 25}, \
2840 {"$k0", RTYPE_GP | 26}, \
2841 {"$kt0", RTYPE_GP | 26}, \
2842 {"$k1", RTYPE_GP | 27}, \
2843 {"$kt1", RTYPE_GP | 27}, \
2844 {"$gp", RTYPE_GP | 28}, \
2845 {"$sp", RTYPE_GP | 29}, \
2846 {"$s8", RTYPE_GP | 30}, \
2847 {"$fp", RTYPE_GP | 30}, \
2848 {"$ra", RTYPE_GP | 31}
2850 #define MIPS16_SPECIAL_REGISTER_NAMES \
2851 {"$pc", RTYPE_PC | 0}
2853 #define MDMX_VECTOR_REGISTER_NAMES \
2854 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2855 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2856 {"$v2", RTYPE_VEC | 2}, \
2857 {"$v3", RTYPE_VEC | 3}, \
2858 {"$v4", RTYPE_VEC | 4}, \
2859 {"$v5", RTYPE_VEC | 5}, \
2860 {"$v6", RTYPE_VEC | 6}, \
2861 {"$v7", RTYPE_VEC | 7}, \
2862 {"$v8", RTYPE_VEC | 8}, \
2863 {"$v9", RTYPE_VEC | 9}, \
2864 {"$v10", RTYPE_VEC | 10}, \
2865 {"$v11", RTYPE_VEC | 11}, \
2866 {"$v12", RTYPE_VEC | 12}, \
2867 {"$v13", RTYPE_VEC | 13}, \
2868 {"$v14", RTYPE_VEC | 14}, \
2869 {"$v15", RTYPE_VEC | 15}, \
2870 {"$v16", RTYPE_VEC | 16}, \
2871 {"$v17", RTYPE_VEC | 17}, \
2872 {"$v18", RTYPE_VEC | 18}, \
2873 {"$v19", RTYPE_VEC | 19}, \
2874 {"$v20", RTYPE_VEC | 20}, \
2875 {"$v21", RTYPE_VEC | 21}, \
2876 {"$v22", RTYPE_VEC | 22}, \
2877 {"$v23", RTYPE_VEC | 23}, \
2878 {"$v24", RTYPE_VEC | 24}, \
2879 {"$v25", RTYPE_VEC | 25}, \
2880 {"$v26", RTYPE_VEC | 26}, \
2881 {"$v27", RTYPE_VEC | 27}, \
2882 {"$v28", RTYPE_VEC | 28}, \
2883 {"$v29", RTYPE_VEC | 29}, \
2884 {"$v30", RTYPE_VEC | 30}, \
2885 {"$v31", RTYPE_VEC | 31}
2887 #define R5900_I_NAMES \
2888 {"$I", RTYPE_R5900_I | 0}
2890 #define R5900_Q_NAMES \
2891 {"$Q", RTYPE_R5900_Q | 0}
2893 #define R5900_R_NAMES \
2894 {"$R", RTYPE_R5900_R | 0}
2896 #define R5900_ACC_NAMES \
2897 {"$ACC", RTYPE_R5900_ACC | 0 }
2899 #define MIPS_DSP_ACCUMULATOR_NAMES \
2900 {"$ac0", RTYPE_ACC | 0}, \
2901 {"$ac1", RTYPE_ACC | 1}, \
2902 {"$ac2", RTYPE_ACC | 2}, \
2903 {"$ac3", RTYPE_ACC | 3}
2905 static const struct regname reg_names
[] = {
2906 GENERIC_REGISTER_NUMBERS
,
2908 FPU_CONDITION_CODE_NAMES
,
2909 COPROC_CONDITION_CODE_NAMES
,
2911 /* The $txx registers depends on the abi,
2912 these will be added later into the symbol table from
2913 one of the tables below once mips_abi is set after
2914 parsing of arguments from the command line. */
2915 SYMBOLIC_REGISTER_NAMES
,
2917 MIPS16_SPECIAL_REGISTER_NAMES
,
2918 MDMX_VECTOR_REGISTER_NAMES
,
2923 MIPS_DSP_ACCUMULATOR_NAMES
,
2927 static const struct regname reg_names_o32
[] = {
2928 O32_SYMBOLIC_REGISTER_NAMES
,
2932 static const struct regname reg_names_n32n64
[] = {
2933 N32N64_SYMBOLIC_REGISTER_NAMES
,
2937 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2938 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2939 of these register symbols, return the associated vector register,
2940 otherwise return SYMVAL itself. */
2943 mips_prefer_vec_regno (unsigned int symval
)
2945 if ((symval
& -2) == (RTYPE_GP
| 2))
2946 return RTYPE_VEC
| (symval
& 1);
2950 /* Return true if string [S, E) is a valid register name, storing its
2951 symbol value in *SYMVAL_PTR if so. */
2954 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2959 /* Terminate name. */
2963 /* Look up the name. */
2964 symbol
= symbol_find (s
);
2967 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2970 *symval_ptr
= S_GET_VALUE (symbol
);
2974 /* Return true if the string at *SPTR is a valid register name. Allow it
2975 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2978 When returning true, move *SPTR past the register, store the
2979 register's symbol value in *SYMVAL_PTR and the channel mask in
2980 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2981 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2982 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2985 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2986 unsigned int *channels_ptr
)
2990 unsigned int channels
, symval
, bit
;
2992 /* Find end of name. */
2994 if (is_name_beginner (*e
))
2996 while (is_part_of_name (*e
))
3000 if (!mips_parse_register_1 (s
, e
, &symval
))
3005 /* Eat characters from the end of the string that are valid
3006 channel suffixes. The preceding register must be $ACC or
3007 end with a digit, so there is no ambiguity. */
3010 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3011 if (m
> s
&& m
[-1] == *q
)
3018 || !mips_parse_register_1 (s
, m
, &symval
)
3019 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3024 *symval_ptr
= symval
;
3026 *channels_ptr
= channels
;
3030 /* Check if SPTR points at a valid register specifier according to TYPES.
3031 If so, then return 1, advance S to consume the specifier and store
3032 the register's number in REGNOP, otherwise return 0. */
3035 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3039 if (mips_parse_register (s
, ®no
, NULL
))
3041 if (types
& RTYPE_VEC
)
3042 regno
= mips_prefer_vec_regno (regno
);
3051 as_warn (_("unrecognized register name `%s'"), *s
);
3056 return regno
<= RNUM_MASK
;
3059 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3060 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3063 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3068 for (i
= 0; i
< 4; i
++)
3069 if (*s
== "xyzw"[i
])
3071 *channels
|= 1 << (3 - i
);
3077 /* Token types for parsed operand lists. */
3078 enum mips_operand_token_type
{
3079 /* A plain register, e.g. $f2. */
3082 /* A 4-bit XYZW channel mask. */
3085 /* A constant vector index, e.g. [1]. */
3088 /* A register vector index, e.g. [$2]. */
3091 /* A continuous range of registers, e.g. $s0-$s4. */
3094 /* A (possibly relocated) expression. */
3097 /* A floating-point value. */
3100 /* A single character. This can be '(', ')' or ',', but '(' only appears
3104 /* A doubled character, either "--" or "++". */
3107 /* The end of the operand list. */
3111 /* A parsed operand token. */
3112 struct mips_operand_token
3114 /* The type of token. */
3115 enum mips_operand_token_type type
;
3118 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3121 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3122 unsigned int channels
;
3124 /* The integer value of an OT_INTEGER_INDEX. */
3127 /* The two register symbol values involved in an OT_REG_RANGE. */
3129 unsigned int regno1
;
3130 unsigned int regno2
;
3133 /* The value of an OT_INTEGER. The value is represented as an
3134 expression and the relocation operators that were applied to
3135 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3136 relocation operators were used. */
3139 bfd_reloc_code_real_type relocs
[3];
3142 /* The binary data for an OT_FLOAT constant, and the number of bytes
3145 unsigned char data
[8];
3149 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3154 /* An obstack used to construct lists of mips_operand_tokens. */
3155 static struct obstack mips_operand_tokens
;
3157 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3160 mips_add_token (struct mips_operand_token
*token
,
3161 enum mips_operand_token_type type
)
3164 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3167 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3168 and OT_REG tokens for them if so, and return a pointer to the first
3169 unconsumed character. Return null otherwise. */
3172 mips_parse_base_start (char *s
)
3174 struct mips_operand_token token
;
3175 unsigned int regno
, channels
;
3176 bfd_boolean decrement_p
;
3182 SKIP_SPACE_TABS (s
);
3184 /* Only match "--" as part of a base expression. In other contexts "--X"
3185 is a double negative. */
3186 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3190 SKIP_SPACE_TABS (s
);
3193 /* Allow a channel specifier because that leads to better error messages
3194 than treating something like "$vf0x++" as an expression. */
3195 if (!mips_parse_register (&s
, ®no
, &channels
))
3199 mips_add_token (&token
, OT_CHAR
);
3204 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3207 token
.u
.regno
= regno
;
3208 mips_add_token (&token
, OT_REG
);
3212 token
.u
.channels
= channels
;
3213 mips_add_token (&token
, OT_CHANNELS
);
3216 /* For consistency, only match "++" as part of base expressions too. */
3217 SKIP_SPACE_TABS (s
);
3218 if (s
[0] == '+' && s
[1] == '+')
3222 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3228 /* Parse one or more tokens from S. Return a pointer to the first
3229 unconsumed character on success. Return null if an error was found
3230 and store the error text in insn_error. FLOAT_FORMAT is as for
3231 mips_parse_arguments. */
3234 mips_parse_argument_token (char *s
, char float_format
)
3236 char *end
, *save_in
;
3238 unsigned int regno1
, regno2
, channels
;
3239 struct mips_operand_token token
;
3241 /* First look for "($reg", since we want to treat that as an
3242 OT_CHAR and OT_REG rather than an expression. */
3243 end
= mips_parse_base_start (s
);
3247 /* Handle other characters that end up as OT_CHARs. */
3248 if (*s
== ')' || *s
== ',')
3251 mips_add_token (&token
, OT_CHAR
);
3256 /* Handle tokens that start with a register. */
3257 if (mips_parse_register (&s
, ®no1
, &channels
))
3261 /* A register and a VU0 channel suffix. */
3262 token
.u
.regno
= regno1
;
3263 mips_add_token (&token
, OT_REG
);
3265 token
.u
.channels
= channels
;
3266 mips_add_token (&token
, OT_CHANNELS
);
3270 SKIP_SPACE_TABS (s
);
3273 /* A register range. */
3275 SKIP_SPACE_TABS (s
);
3276 if (!mips_parse_register (&s
, ®no2
, NULL
))
3278 set_insn_error (0, _("invalid register range"));
3282 token
.u
.reg_range
.regno1
= regno1
;
3283 token
.u
.reg_range
.regno2
= regno2
;
3284 mips_add_token (&token
, OT_REG_RANGE
);
3288 /* Add the register itself. */
3289 token
.u
.regno
= regno1
;
3290 mips_add_token (&token
, OT_REG
);
3292 /* Check for a vector index. */
3296 SKIP_SPACE_TABS (s
);
3297 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3298 mips_add_token (&token
, OT_REG_INDEX
);
3301 expressionS element
;
3303 my_getExpression (&element
, s
);
3304 if (element
.X_op
!= O_constant
)
3306 set_insn_error (0, _("vector element must be constant"));
3310 token
.u
.index
= element
.X_add_number
;
3311 mips_add_token (&token
, OT_INTEGER_INDEX
);
3313 SKIP_SPACE_TABS (s
);
3316 set_insn_error (0, _("missing `]'"));
3326 /* First try to treat expressions as floats. */
3327 save_in
= input_line_pointer
;
3328 input_line_pointer
= s
;
3329 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3330 &token
.u
.flt
.length
);
3331 end
= input_line_pointer
;
3332 input_line_pointer
= save_in
;
3335 set_insn_error (0, err
);
3340 mips_add_token (&token
, OT_FLOAT
);
3345 /* Treat everything else as an integer expression. */
3346 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3347 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3348 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3349 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3351 mips_add_token (&token
, OT_INTEGER
);
3355 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3356 if expressions should be treated as 32-bit floating-point constants,
3357 'd' if they should be treated as 64-bit floating-point constants,
3358 or 0 if they should be treated as integer expressions (the usual case).
3360 Return a list of tokens on success, otherwise return 0. The caller
3361 must obstack_free the list after use. */
3363 static struct mips_operand_token
*
3364 mips_parse_arguments (char *s
, char float_format
)
3366 struct mips_operand_token token
;
3368 SKIP_SPACE_TABS (s
);
3371 s
= mips_parse_argument_token (s
, float_format
);
3374 obstack_free (&mips_operand_tokens
,
3375 obstack_finish (&mips_operand_tokens
));
3378 SKIP_SPACE_TABS (s
);
3380 mips_add_token (&token
, OT_END
);
3381 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3384 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3385 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3388 is_opcode_valid (const struct mips_opcode
*mo
)
3390 int isa
= mips_opts
.isa
;
3391 int ase
= mips_opts
.ase
;
3395 if (ISA_HAS_64BIT_REGS (isa
))
3396 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3397 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3398 ase
|= mips_ases
[i
].flags64
;
3400 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3403 /* Check whether the instruction or macro requires single-precision or
3404 double-precision floating-point support. Note that this information is
3405 stored differently in the opcode table for insns and macros. */
3406 if (mo
->pinfo
== INSN_MACRO
)
3408 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3409 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3413 fp_s
= mo
->pinfo
& FP_S
;
3414 fp_d
= mo
->pinfo
& FP_D
;
3417 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3420 if (fp_s
&& mips_opts
.soft_float
)
3426 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3427 selected ISA and architecture. */
3430 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3432 int isa
= mips_opts
.isa
;
3433 int ase
= mips_opts
.ase
;
3436 if (ISA_HAS_64BIT_REGS (isa
))
3437 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3438 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3439 ase
|= mips_ases
[i
].flags64
;
3441 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3444 /* Return TRUE if the size of the microMIPS opcode MO matches one
3445 explicitly requested. Always TRUE in the standard MIPS mode.
3446 Use is_size_valid_16 for MIPS16 opcodes. */
3449 is_size_valid (const struct mips_opcode
*mo
)
3451 if (!mips_opts
.micromips
)
3454 if (mips_opts
.insn32
)
3456 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3458 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3461 if (!forced_insn_length
)
3463 if (mo
->pinfo
== INSN_MACRO
)
3465 return forced_insn_length
== micromips_insn_length (mo
);
3468 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3469 explicitly requested. */
3472 is_size_valid_16 (const struct mips_opcode
*mo
)
3474 if (!forced_insn_length
)
3476 if (mo
->pinfo
== INSN_MACRO
)
3478 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3480 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3485 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3486 of the preceding instruction. Always TRUE in the standard MIPS mode.
3488 We don't accept macros in 16-bit delay slots to avoid a case where
3489 a macro expansion fails because it relies on a preceding 32-bit real
3490 instruction to have matched and does not handle the operands correctly.
3491 The only macros that may expand to 16-bit instructions are JAL that
3492 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3493 and BGT (that likewise cannot be placed in a delay slot) that decay to
3494 a NOP. In all these cases the macros precede any corresponding real
3495 instruction definitions in the opcode table, so they will match in the
3496 second pass where the size of the delay slot is ignored and therefore
3497 produce correct code. */
3500 is_delay_slot_valid (const struct mips_opcode
*mo
)
3502 if (!mips_opts
.micromips
)
3505 if (mo
->pinfo
== INSN_MACRO
)
3506 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3507 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3508 && micromips_insn_length (mo
) != 4)
3510 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3511 && micromips_insn_length (mo
) != 2)
3517 /* For consistency checking, verify that all bits of OPCODE are specified
3518 either by the match/mask part of the instruction definition, or by the
3519 operand list. Also build up a list of operands in OPERANDS.
3521 INSN_BITS says which bits of the instruction are significant.
3522 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3523 provides the mips_operand description of each operand. DECODE_OPERAND
3524 is null for MIPS16 instructions. */
3527 validate_mips_insn (const struct mips_opcode
*opcode
,
3528 unsigned long insn_bits
,
3529 const struct mips_operand
*(*decode_operand
) (const char *),
3530 struct mips_operand_array
*operands
)
3533 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3534 const struct mips_operand
*operand
;
3536 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3537 if ((mask
& opcode
->match
) != opcode
->match
)
3539 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3540 opcode
->name
, opcode
->args
);
3545 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3546 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3547 for (s
= opcode
->args
; *s
; ++s
)
3560 if (!decode_operand
)
3561 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3563 operand
= decode_operand (s
);
3564 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3566 as_bad (_("internal: unknown operand type: %s %s"),
3567 opcode
->name
, opcode
->args
);
3570 gas_assert (opno
< MAX_OPERANDS
);
3571 operands
->operand
[opno
] = operand
;
3572 if (!decode_operand
&& operand
3573 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3574 && mips_opcode_32bit_p (opcode
))
3575 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3576 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3578 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3579 if (operand
->type
== OP_MDMX_IMM_REG
)
3580 /* Bit 5 is the format selector (OB vs QH). The opcode table
3581 has separate entries for each format. */
3582 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3583 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3584 used_bits
&= ~(mask
& 0x700);
3585 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3586 operand field that cannot be fully described with LSB/SIZE. */
3587 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3588 used_bits
&= ~0x6000;
3590 /* Skip prefix characters. */
3591 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3596 doubled
= used_bits
& mask
& insn_bits
;
3599 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3600 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3604 undefined
= ~used_bits
& insn_bits
;
3605 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3607 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3608 undefined
, opcode
->name
, opcode
->args
);
3611 used_bits
&= ~insn_bits
;
3614 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3615 used_bits
, opcode
->name
, opcode
->args
);
3621 /* The MIPS16 version of validate_mips_insn. */
3624 validate_mips16_insn (const struct mips_opcode
*opcode
,
3625 struct mips_operand_array
*operands
)
3627 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3629 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3632 /* The microMIPS version of validate_mips_insn. */
3635 validate_micromips_insn (const struct mips_opcode
*opc
,
3636 struct mips_operand_array
*operands
)
3638 unsigned long insn_bits
;
3639 unsigned long major
;
3640 unsigned int length
;
3642 if (opc
->pinfo
== INSN_MACRO
)
3643 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3646 length
= micromips_insn_length (opc
);
3647 if (length
!= 2 && length
!= 4)
3649 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3650 "%s %s"), length
, opc
->name
, opc
->args
);
3653 major
= opc
->match
>> (10 + 8 * (length
- 2));
3654 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3655 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3657 as_bad (_("internal error: bad microMIPS opcode "
3658 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3662 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3663 insn_bits
= 1 << 4 * length
;
3664 insn_bits
<<= 4 * length
;
3666 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3670 /* This function is called once, at assembler startup time. It should set up
3671 all the tables, etc. that the MD part of the assembler will need. */
3676 const char *retval
= NULL
;
3680 if (mips_pic
!= NO_PIC
)
3682 if (g_switch_seen
&& g_switch_value
!= 0)
3683 as_bad (_("-G may not be used in position-independent code"));
3686 else if (mips_abicalls
)
3688 if (g_switch_seen
&& g_switch_value
!= 0)
3689 as_bad (_("-G may not be used with abicalls"));
3693 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3694 as_warn (_("could not set architecture and machine"));
3696 op_hash
= hash_new ();
3698 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3699 for (i
= 0; i
< NUMOPCODES
;)
3701 const char *name
= mips_opcodes
[i
].name
;
3703 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3706 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3707 mips_opcodes
[i
].name
, retval
);
3708 /* Probably a memory allocation problem? Give up now. */
3709 as_fatal (_("broken assembler, no assembly attempted"));
3713 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3714 decode_mips_operand
, &mips_operands
[i
]))
3717 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3719 create_insn (&nop_insn
, mips_opcodes
+ i
);
3720 if (mips_fix_loongson2f_nop
)
3721 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3722 nop_insn
.fixed_p
= 1;
3725 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3726 create_insn (&sync_insn
, mips_opcodes
+ i
);
3730 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3733 mips16_op_hash
= hash_new ();
3734 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3735 bfd_mips16_num_opcodes
);
3738 while (i
< bfd_mips16_num_opcodes
)
3740 const char *name
= mips16_opcodes
[i
].name
;
3742 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3744 as_fatal (_("internal: can't hash `%s': %s"),
3745 mips16_opcodes
[i
].name
, retval
);
3748 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3750 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3752 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3753 mips16_nop_insn
.fixed_p
= 1;
3757 while (i
< bfd_mips16_num_opcodes
3758 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3761 micromips_op_hash
= hash_new ();
3762 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3763 bfd_micromips_num_opcodes
);
3766 while (i
< bfd_micromips_num_opcodes
)
3768 const char *name
= micromips_opcodes
[i
].name
;
3770 retval
= hash_insert (micromips_op_hash
, name
,
3771 (void *) µmips_opcodes
[i
]);
3773 as_fatal (_("internal: can't hash `%s': %s"),
3774 micromips_opcodes
[i
].name
, retval
);
3777 struct mips_cl_insn
*micromips_nop_insn
;
3779 if (!validate_micromips_insn (µmips_opcodes
[i
],
3780 µmips_operands
[i
]))
3783 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3785 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3786 micromips_nop_insn
= µmips_nop16_insn
;
3787 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3788 micromips_nop_insn
= µmips_nop32_insn
;
3792 if (micromips_nop_insn
->insn_mo
== NULL
3793 && strcmp (name
, "nop") == 0)
3795 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3796 micromips_nop_insn
->fixed_p
= 1;
3800 while (++i
< bfd_micromips_num_opcodes
3801 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3805 as_fatal (_("broken assembler, no assembly attempted"));
3807 /* We add all the general register names to the symbol table. This
3808 helps us detect invalid uses of them. */
3809 for (i
= 0; reg_names
[i
].name
; i
++)
3810 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3811 reg_names
[i
].num
, /* & RNUM_MASK, */
3812 &zero_address_frag
));
3814 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3815 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3816 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3817 &zero_address_frag
));
3819 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3820 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3821 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3822 &zero_address_frag
));
3824 for (i
= 0; i
< 32; i
++)
3828 /* R5900 VU0 floating-point register. */
3829 sprintf (regname
, "$vf%d", i
);
3830 symbol_table_insert (symbol_new (regname
, reg_section
,
3831 RTYPE_VF
| i
, &zero_address_frag
));
3833 /* R5900 VU0 integer register. */
3834 sprintf (regname
, "$vi%d", i
);
3835 symbol_table_insert (symbol_new (regname
, reg_section
,
3836 RTYPE_VI
| i
, &zero_address_frag
));
3839 sprintf (regname
, "$w%d", i
);
3840 symbol_table_insert (symbol_new (regname
, reg_section
,
3841 RTYPE_MSA
| i
, &zero_address_frag
));
3844 obstack_init (&mips_operand_tokens
);
3846 mips_no_prev_insn ();
3849 mips_cprmask
[0] = 0;
3850 mips_cprmask
[1] = 0;
3851 mips_cprmask
[2] = 0;
3852 mips_cprmask
[3] = 0;
3854 /* set the default alignment for the text section (2**2) */
3855 record_alignment (text_section
, 2);
3857 bfd_set_gp_size (stdoutput
, g_switch_value
);
3859 /* On a native system other than VxWorks, sections must be aligned
3860 to 16 byte boundaries. When configured for an embedded ELF
3861 target, we don't bother. */
3862 if (strncmp (TARGET_OS
, "elf", 3) != 0
3863 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3865 bfd_set_section_alignment (text_section
, 4);
3866 bfd_set_section_alignment (data_section
, 4);
3867 bfd_set_section_alignment (bss_section
, 4);
3870 /* Create a .reginfo section for register masks and a .mdebug
3871 section for debugging information. */
3879 subseg
= now_subseg
;
3881 /* The ABI says this section should be loaded so that the
3882 running program can access it. However, we don't load it
3883 if we are configured for an embedded target. */
3884 flags
= SEC_READONLY
| SEC_DATA
;
3885 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3886 flags
|= SEC_ALLOC
| SEC_LOAD
;
3888 if (mips_abi
!= N64_ABI
)
3890 sec
= subseg_new (".reginfo", (subsegT
) 0);
3892 bfd_set_section_flags (sec
, flags
);
3893 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3895 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3899 /* The 64-bit ABI uses a .MIPS.options section rather than
3900 .reginfo section. */
3901 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3902 bfd_set_section_flags (sec
, flags
);
3903 bfd_set_section_alignment (sec
, 3);
3905 /* Set up the option header. */
3907 Elf_Internal_Options opthdr
;
3910 opthdr
.kind
= ODK_REGINFO
;
3911 opthdr
.size
= (sizeof (Elf_External_Options
)
3912 + sizeof (Elf64_External_RegInfo
));
3915 f
= frag_more (sizeof (Elf_External_Options
));
3916 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3917 (Elf_External_Options
*) f
);
3919 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3923 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3924 bfd_set_section_flags (sec
,
3925 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3926 bfd_set_section_alignment (sec
, 3);
3927 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3929 if (ECOFF_DEBUGGING
)
3931 sec
= subseg_new (".mdebug", (subsegT
) 0);
3932 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3933 bfd_set_section_alignment (sec
, 2);
3935 else if (mips_flag_pdr
)
3937 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3938 bfd_set_section_flags (pdr_seg
,
3939 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3940 bfd_set_section_alignment (pdr_seg
, 2);
3943 subseg_set (seg
, subseg
);
3946 if (mips_fix_vr4120
)
3947 init_vr4120_conflicts ();
3951 fpabi_incompatible_with (int fpabi
, const char *what
)
3953 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3954 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3958 fpabi_requires (int fpabi
, const char *what
)
3960 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3961 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3964 /* Check -mabi and register sizes against the specified FP ABI. */
3966 check_fpabi (int fpabi
)
3970 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3971 if (file_mips_opts
.soft_float
)
3972 fpabi_incompatible_with (fpabi
, "softfloat");
3973 else if (file_mips_opts
.single_float
)
3974 fpabi_incompatible_with (fpabi
, "singlefloat");
3975 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3976 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3977 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3978 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3981 case Val_GNU_MIPS_ABI_FP_XX
:
3982 if (mips_abi
!= O32_ABI
)
3983 fpabi_requires (fpabi
, "-mabi=32");
3984 else if (file_mips_opts
.soft_float
)
3985 fpabi_incompatible_with (fpabi
, "softfloat");
3986 else if (file_mips_opts
.single_float
)
3987 fpabi_incompatible_with (fpabi
, "singlefloat");
3988 else if (file_mips_opts
.fp
!= 0)
3989 fpabi_requires (fpabi
, "fp=xx");
3992 case Val_GNU_MIPS_ABI_FP_64A
:
3993 case Val_GNU_MIPS_ABI_FP_64
:
3994 if (mips_abi
!= O32_ABI
)
3995 fpabi_requires (fpabi
, "-mabi=32");
3996 else if (file_mips_opts
.soft_float
)
3997 fpabi_incompatible_with (fpabi
, "softfloat");
3998 else if (file_mips_opts
.single_float
)
3999 fpabi_incompatible_with (fpabi
, "singlefloat");
4000 else if (file_mips_opts
.fp
!= 64)
4001 fpabi_requires (fpabi
, "fp=64");
4002 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
4003 fpabi_incompatible_with (fpabi
, "nooddspreg");
4004 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
4005 fpabi_requires (fpabi
, "nooddspreg");
4008 case Val_GNU_MIPS_ABI_FP_SINGLE
:
4009 if (file_mips_opts
.soft_float
)
4010 fpabi_incompatible_with (fpabi
, "softfloat");
4011 else if (!file_mips_opts
.single_float
)
4012 fpabi_requires (fpabi
, "singlefloat");
4015 case Val_GNU_MIPS_ABI_FP_SOFT
:
4016 if (!file_mips_opts
.soft_float
)
4017 fpabi_requires (fpabi
, "softfloat");
4020 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4021 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4022 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4025 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4026 /* Silently ignore compatibility value. */
4030 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4031 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4036 /* Perform consistency checks on the current options. */
4039 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4041 /* Check the size of integer registers agrees with the ABI and ISA. */
4042 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4043 as_bad (_("`gp=64' used with a 32-bit processor"));
4045 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4046 as_bad (_("`gp=32' used with a 64-bit ABI"));
4048 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4049 as_bad (_("`gp=64' used with a 32-bit ABI"));
4051 /* Check the size of the float registers agrees with the ABI and ISA. */
4055 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4056 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4057 else if (opts
->single_float
== 1)
4058 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4061 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4062 as_bad (_("`fp=64' used with a 32-bit fpu"));
4064 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4065 && !ISA_HAS_MXHC1 (opts
->isa
))
4066 as_warn (_("`fp=64' used with a 32-bit ABI"));
4070 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4071 as_warn (_("`fp=32' used with a 64-bit ABI"));
4072 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4073 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4076 as_bad (_("Unknown size of floating point registers"));
4080 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4081 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4083 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4084 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4085 else if (ISA_IS_R6 (opts
->isa
)
4086 && (opts
->micromips
== 1
4087 || opts
->mips16
== 1))
4088 as_fatal (_("`%s' cannot be used with `%s'"),
4089 opts
->micromips
? "micromips" : "mips16",
4090 mips_cpu_info_from_isa (opts
->isa
)->name
);
4092 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4093 as_fatal (_("branch relaxation is not supported in `%s'"),
4094 mips_cpu_info_from_isa (opts
->isa
)->name
);
4097 /* Perform consistency checks on the module level options exactly once.
4098 This is a deferred check that happens:
4099 at the first .set directive
4100 or, at the first pseudo op that generates code (inc .dc.a)
4101 or, at the first instruction
4105 file_mips_check_options (void)
4107 if (file_mips_opts_checked
)
4110 /* The following code determines the register size.
4111 Similar code was added to GCC 3.3 (see override_options() in
4112 config/mips/mips.c). The GAS and GCC code should be kept in sync
4113 as much as possible. */
4115 if (file_mips_opts
.gp
< 0)
4117 /* Infer the integer register size from the ABI and processor.
4118 Restrict ourselves to 32-bit registers if that's all the
4119 processor has, or if the ABI cannot handle 64-bit registers. */
4120 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4121 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4125 if (file_mips_opts
.fp
< 0)
4127 /* No user specified float register size.
4128 ??? GAS treats single-float processors as though they had 64-bit
4129 float registers (although it complains when double-precision
4130 instructions are used). As things stand, saying they have 32-bit
4131 registers would lead to spurious "register must be even" messages.
4132 So here we assume float registers are never smaller than the
4134 if (file_mips_opts
.gp
== 64)
4135 /* 64-bit integer registers implies 64-bit float registers. */
4136 file_mips_opts
.fp
= 64;
4137 else if ((file_mips_opts
.ase
& FP64_ASES
)
4138 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4139 /* Handle ASEs that require 64-bit float registers, if possible. */
4140 file_mips_opts
.fp
= 64;
4141 else if (ISA_IS_R6 (mips_opts
.isa
))
4142 /* R6 implies 64-bit float registers. */
4143 file_mips_opts
.fp
= 64;
4145 /* 32-bit float registers. */
4146 file_mips_opts
.fp
= 32;
4149 /* Disable operations on odd-numbered floating-point registers by default
4150 when using the FPXX ABI. */
4151 if (file_mips_opts
.oddspreg
< 0)
4153 if (file_mips_opts
.fp
== 0)
4154 file_mips_opts
.oddspreg
= 0;
4156 file_mips_opts
.oddspreg
= 1;
4159 /* End of GCC-shared inference code. */
4161 /* This flag is set when we have a 64-bit capable CPU but use only
4162 32-bit wide registers. Note that EABI does not use it. */
4163 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4164 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4165 || mips_abi
== O32_ABI
))
4168 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4169 as_bad (_("trap exception not supported at ISA 1"));
4171 /* If the selected architecture includes support for ASEs, enable
4172 generation of code for them. */
4173 if (file_mips_opts
.mips16
== -1)
4174 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4175 if (file_mips_opts
.micromips
== -1)
4176 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4179 if (mips_nan2008
== -1)
4180 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4181 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4182 as_fatal (_("`%s' does not support legacy NaN"),
4183 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4185 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4186 being selected implicitly. */
4187 if (file_mips_opts
.fp
!= 64)
4188 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4190 /* If the user didn't explicitly select or deselect a particular ASE,
4191 use the default setting for the CPU. */
4192 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4194 /* Set up the current options. These may change throughout assembly. */
4195 mips_opts
= file_mips_opts
;
4197 mips_check_isa_supports_ases ();
4198 mips_check_options (&file_mips_opts
, TRUE
);
4199 file_mips_opts_checked
= TRUE
;
4201 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4202 as_warn (_("could not set architecture and machine"));
4206 md_assemble (char *str
)
4208 struct mips_cl_insn insn
;
4209 bfd_reloc_code_real_type unused_reloc
[3]
4210 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4212 file_mips_check_options ();
4214 imm_expr
.X_op
= O_absent
;
4215 offset_expr
.X_op
= O_absent
;
4216 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4217 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4218 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4220 mips_mark_labels ();
4221 mips_assembling_insn
= TRUE
;
4222 clear_insn_error ();
4224 if (mips_opts
.mips16
)
4225 mips16_ip (str
, &insn
);
4228 mips_ip (str
, &insn
);
4229 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4230 str
, insn
.insn_opcode
));
4234 report_insn_error (str
);
4235 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4238 if (mips_opts
.mips16
)
4239 mips16_macro (&insn
);
4246 if (offset_expr
.X_op
!= O_absent
)
4247 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4249 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4252 mips_assembling_insn
= FALSE
;
4255 /* Convenience functions for abstracting away the differences between
4256 MIPS16 and non-MIPS16 relocations. */
4258 static inline bfd_boolean
4259 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4263 case BFD_RELOC_MIPS16_JMP
:
4264 case BFD_RELOC_MIPS16_GPREL
:
4265 case BFD_RELOC_MIPS16_GOT16
:
4266 case BFD_RELOC_MIPS16_CALL16
:
4267 case BFD_RELOC_MIPS16_HI16_S
:
4268 case BFD_RELOC_MIPS16_HI16
:
4269 case BFD_RELOC_MIPS16_LO16
:
4270 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4278 static inline bfd_boolean
4279 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4283 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4284 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4285 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4286 case BFD_RELOC_MICROMIPS_GPREL16
:
4287 case BFD_RELOC_MICROMIPS_JMP
:
4288 case BFD_RELOC_MICROMIPS_HI16
:
4289 case BFD_RELOC_MICROMIPS_HI16_S
:
4290 case BFD_RELOC_MICROMIPS_LO16
:
4291 case BFD_RELOC_MICROMIPS_LITERAL
:
4292 case BFD_RELOC_MICROMIPS_GOT16
:
4293 case BFD_RELOC_MICROMIPS_CALL16
:
4294 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4295 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4296 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4297 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4298 case BFD_RELOC_MICROMIPS_SUB
:
4299 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4300 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4301 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4302 case BFD_RELOC_MICROMIPS_HIGHEST
:
4303 case BFD_RELOC_MICROMIPS_HIGHER
:
4304 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4305 case BFD_RELOC_MICROMIPS_JALR
:
4313 static inline bfd_boolean
4314 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4316 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4319 static inline bfd_boolean
4320 b_reloc_p (bfd_reloc_code_real_type reloc
)
4322 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4323 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4324 || reloc
== BFD_RELOC_16_PCREL_S2
4325 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4326 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4327 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4328 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4331 static inline bfd_boolean
4332 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4334 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4335 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4338 static inline bfd_boolean
4339 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4341 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4342 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4345 static inline bfd_boolean
4346 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4348 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4349 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4352 static inline bfd_boolean
4353 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4355 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4358 static inline bfd_boolean
4359 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4361 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4362 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4365 /* Return true if RELOC is a PC-relative relocation that does not have
4366 full address range. */
4368 static inline bfd_boolean
4369 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4373 case BFD_RELOC_16_PCREL_S2
:
4374 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4375 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4376 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4377 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4378 case BFD_RELOC_MIPS_21_PCREL_S2
:
4379 case BFD_RELOC_MIPS_26_PCREL_S2
:
4380 case BFD_RELOC_MIPS_18_PCREL_S3
:
4381 case BFD_RELOC_MIPS_19_PCREL_S2
:
4384 case BFD_RELOC_32_PCREL
:
4385 case BFD_RELOC_HI16_S_PCREL
:
4386 case BFD_RELOC_LO16_PCREL
:
4387 return HAVE_64BIT_ADDRESSES
;
4394 /* Return true if the given relocation might need a matching %lo().
4395 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4396 need a matching %lo() when applied to local symbols. */
4398 static inline bfd_boolean
4399 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4401 return (HAVE_IN_PLACE_ADDENDS
4402 && (hi16_reloc_p (reloc
)
4403 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4404 all GOT16 relocations evaluate to "G". */
4405 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4408 /* Return the type of %lo() reloc needed by RELOC, given that
4409 reloc_needs_lo_p. */
4411 static inline bfd_reloc_code_real_type
4412 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4414 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4415 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4419 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4422 static inline bfd_boolean
4423 fixup_has_matching_lo_p (fixS
*fixp
)
4425 return (fixp
->fx_next
!= NULL
4426 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4427 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4428 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4431 /* Move all labels in LABELS to the current insertion point. TEXT_P
4432 says whether the labels refer to text or data. */
4435 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4437 struct insn_label_list
*l
;
4440 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4442 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4443 symbol_set_frag (l
->label
, frag_now
);
4444 val
= (valueT
) frag_now_fix ();
4445 /* MIPS16/microMIPS text labels are stored as odd.
4446 We just carry the ISA mode bit forward. */
4447 if (text_p
&& HAVE_CODE_COMPRESSION
)
4448 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4449 S_SET_VALUE (l
->label
, val
);
4453 /* Move all labels in insn_labels to the current insertion point
4454 and treat them as text labels. */
4457 mips_move_text_labels (void)
4459 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4462 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4465 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4467 bfd_boolean linkonce
= FALSE
;
4468 segT symseg
= S_GET_SEGMENT (sym
);
4470 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4472 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4474 /* The GNU toolchain uses an extension for ELF: a section
4475 beginning with the magic string .gnu.linkonce is a
4476 linkonce section. */
4477 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4478 sizeof ".gnu.linkonce" - 1) == 0)
4484 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4485 linker to handle them specially, such as generating jalx instructions
4486 when needed. We also make them odd for the duration of the assembly,
4487 in order to generate the right sort of code. We will make them even
4488 in the adjust_symtab routine, while leaving them marked. This is
4489 convenient for the debugger and the disassembler. The linker knows
4490 to make them odd again. */
4493 mips_compressed_mark_label (symbolS
*label
)
4495 gas_assert (HAVE_CODE_COMPRESSION
);
4497 if (mips_opts
.mips16
)
4498 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4500 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4501 if ((S_GET_VALUE (label
) & 1) == 0
4502 /* Don't adjust the address if the label is global or weak, or
4503 in a link-once section, since we'll be emitting symbol reloc
4504 references to it which will be patched up by the linker, and
4505 the final value of the symbol may or may not be MIPS16/microMIPS. */
4506 && !S_IS_WEAK (label
)
4507 && !S_IS_EXTERNAL (label
)
4508 && !s_is_linkonce (label
, now_seg
))
4509 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4512 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4515 mips_compressed_mark_labels (void)
4517 struct insn_label_list
*l
;
4519 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4520 mips_compressed_mark_label (l
->label
);
4523 /* End the current frag. Make it a variant frag and record the
4527 relax_close_frag (void)
4529 mips_macro_warning
.first_frag
= frag_now
;
4530 frag_var (rs_machine_dependent
, 0, 0,
4531 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4532 mips_pic
!= NO_PIC
),
4533 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4535 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4536 mips_relax
.first_fixup
= 0;
4539 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4540 See the comment above RELAX_ENCODE for more details. */
4543 relax_start (symbolS
*symbol
)
4545 gas_assert (mips_relax
.sequence
== 0);
4546 mips_relax
.sequence
= 1;
4547 mips_relax
.symbol
= symbol
;
4550 /* Start generating the second version of a relaxable sequence.
4551 See the comment above RELAX_ENCODE for more details. */
4556 gas_assert (mips_relax
.sequence
== 1);
4557 mips_relax
.sequence
= 2;
4560 /* End the current relaxable sequence. */
4565 gas_assert (mips_relax
.sequence
== 2);
4566 relax_close_frag ();
4567 mips_relax
.sequence
= 0;
4570 /* Return true if IP is a delayed branch or jump. */
4572 static inline bfd_boolean
4573 delayed_branch_p (const struct mips_cl_insn
*ip
)
4575 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4576 | INSN_COND_BRANCH_DELAY
4577 | INSN_COND_BRANCH_LIKELY
)) != 0;
4580 /* Return true if IP is a compact branch or jump. */
4582 static inline bfd_boolean
4583 compact_branch_p (const struct mips_cl_insn
*ip
)
4585 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4586 | INSN2_COND_BRANCH
)) != 0;
4589 /* Return true if IP is an unconditional branch or jump. */
4591 static inline bfd_boolean
4592 uncond_branch_p (const struct mips_cl_insn
*ip
)
4594 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4595 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4598 /* Return true if IP is a branch-likely instruction. */
4600 static inline bfd_boolean
4601 branch_likely_p (const struct mips_cl_insn
*ip
)
4603 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4606 /* Return the type of nop that should be used to fill the delay slot
4607 of delayed branch IP. */
4609 static struct mips_cl_insn
*
4610 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4612 if (mips_opts
.micromips
4613 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4614 return µmips_nop32_insn
;
4618 /* Return a mask that has bit N set if OPCODE reads the register(s)
4622 insn_read_mask (const struct mips_opcode
*opcode
)
4624 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4627 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4631 insn_write_mask (const struct mips_opcode
*opcode
)
4633 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4636 /* Return a mask of the registers specified by operand OPERAND of INSN.
4637 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4641 operand_reg_mask (const struct mips_cl_insn
*insn
,
4642 const struct mips_operand
*operand
,
4643 unsigned int type_mask
)
4645 unsigned int uval
, vsel
;
4647 switch (operand
->type
)
4654 case OP_ADDIUSP_INT
:
4655 case OP_ENTRY_EXIT_LIST
:
4656 case OP_REPEAT_DEST_REG
:
4657 case OP_REPEAT_PREV_REG
:
4660 case OP_VU0_MATCH_SUFFIX
:
4668 case OP_OPTIONAL_REG
:
4670 const struct mips_reg_operand
*reg_op
;
4672 reg_op
= (const struct mips_reg_operand
*) operand
;
4673 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4675 uval
= insn_extract_operand (insn
, operand
);
4676 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4681 const struct mips_reg_pair_operand
*pair_op
;
4683 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4684 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4686 uval
= insn_extract_operand (insn
, operand
);
4687 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4690 case OP_CLO_CLZ_DEST
:
4691 if (!(type_mask
& (1 << OP_REG_GP
)))
4693 uval
= insn_extract_operand (insn
, operand
);
4694 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4697 if (!(type_mask
& (1 << OP_REG_GP
)))
4699 uval
= insn_extract_operand (insn
, operand
);
4700 gas_assert ((uval
& 31) == (uval
>> 5));
4701 return 1 << (uval
& 31);
4704 case OP_NON_ZERO_REG
:
4705 if (!(type_mask
& (1 << OP_REG_GP
)))
4707 uval
= insn_extract_operand (insn
, operand
);
4708 return 1 << (uval
& 31);
4710 case OP_LWM_SWM_LIST
:
4713 case OP_SAVE_RESTORE_LIST
:
4716 case OP_MDMX_IMM_REG
:
4717 if (!(type_mask
& (1 << OP_REG_VEC
)))
4719 uval
= insn_extract_operand (insn
, operand
);
4721 if ((vsel
& 0x18) == 0x18)
4723 return 1 << (uval
& 31);
4726 if (!(type_mask
& (1 << OP_REG_GP
)))
4728 return 1 << insn_extract_operand (insn
, operand
);
4733 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4734 where bit N of OPNO_MASK is set if operand N should be included.
4735 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4739 insn_reg_mask (const struct mips_cl_insn
*insn
,
4740 unsigned int type_mask
, unsigned int opno_mask
)
4742 unsigned int opno
, reg_mask
;
4746 while (opno_mask
!= 0)
4749 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4756 /* Return the mask of core registers that IP reads. */
4759 gpr_read_mask (const struct mips_cl_insn
*ip
)
4761 unsigned long pinfo
, pinfo2
;
4764 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4765 pinfo
= ip
->insn_mo
->pinfo
;
4766 pinfo2
= ip
->insn_mo
->pinfo2
;
4767 if (pinfo
& INSN_UDI
)
4769 /* UDI instructions have traditionally been assumed to read RS
4771 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4772 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4774 if (pinfo
& INSN_READ_GPR_24
)
4776 if (pinfo2
& INSN2_READ_GPR_16
)
4778 if (pinfo2
& INSN2_READ_SP
)
4780 if (pinfo2
& INSN2_READ_GPR_31
)
4782 /* Don't include register 0. */
4786 /* Return the mask of core registers that IP writes. */
4789 gpr_write_mask (const struct mips_cl_insn
*ip
)
4791 unsigned long pinfo
, pinfo2
;
4794 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4795 pinfo
= ip
->insn_mo
->pinfo
;
4796 pinfo2
= ip
->insn_mo
->pinfo2
;
4797 if (pinfo
& INSN_WRITE_GPR_24
)
4799 if (pinfo
& INSN_WRITE_GPR_31
)
4801 if (pinfo
& INSN_UDI
)
4802 /* UDI instructions have traditionally been assumed to write to RD. */
4803 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4804 if (pinfo2
& INSN2_WRITE_SP
)
4806 /* Don't include register 0. */
4810 /* Return the mask of floating-point registers that IP reads. */
4813 fpr_read_mask (const struct mips_cl_insn
*ip
)
4815 unsigned long pinfo
;
4818 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4819 | (1 << OP_REG_MSA
)),
4820 insn_read_mask (ip
->insn_mo
));
4821 pinfo
= ip
->insn_mo
->pinfo
;
4822 /* Conservatively treat all operands to an FP_D instruction are doubles.
4823 (This is overly pessimistic for things like cvt.d.s.) */
4824 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4829 /* Return the mask of floating-point registers that IP writes. */
4832 fpr_write_mask (const struct mips_cl_insn
*ip
)
4834 unsigned long pinfo
;
4837 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4838 | (1 << OP_REG_MSA
)),
4839 insn_write_mask (ip
->insn_mo
));
4840 pinfo
= ip
->insn_mo
->pinfo
;
4841 /* Conservatively treat all operands to an FP_D instruction are doubles.
4842 (This is overly pessimistic for things like cvt.s.d.) */
4843 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4848 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4849 Check whether that is allowed. */
4852 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4854 const char *s
= insn
->name
;
4855 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4857 && mips_opts
.oddspreg
;
4859 if (insn
->pinfo
== INSN_MACRO
)
4860 /* Let a macro pass, we'll catch it later when it is expanded. */
4863 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4864 otherwise it depends on oddspreg. */
4865 if ((insn
->pinfo
& FP_S
)
4866 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4867 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4868 return FPR_SIZE
== 32 || oddspreg
;
4870 /* Allow odd registers for single-precision ops and double-precision if the
4871 floating-point registers are 64-bit wide. */
4872 switch (insn
->pinfo
& (FP_S
| FP_D
))
4878 return FPR_SIZE
== 64;
4883 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4884 s
= strchr (insn
->name
, '.');
4885 if (s
!= NULL
&& opnum
== 2)
4886 s
= strchr (s
+ 1, '.');
4887 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4890 return FPR_SIZE
== 64;
4893 /* Information about an instruction argument that we're trying to match. */
4894 struct mips_arg_info
4896 /* The instruction so far. */
4897 struct mips_cl_insn
*insn
;
4899 /* The first unconsumed operand token. */
4900 struct mips_operand_token
*token
;
4902 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4905 /* The 1-based argument number, for error reporting. This does not
4906 count elided optional registers, etc.. */
4909 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4910 unsigned int last_regno
;
4912 /* If the first operand was an OP_REG, this is the register that it
4913 specified, otherwise it is ILLEGAL_REG. */
4914 unsigned int dest_regno
;
4916 /* The value of the last OP_INT operand. Only used for OP_MSB,
4917 where it gives the lsb position. */
4918 unsigned int last_op_int
;
4920 /* If true, match routines should assume that no later instruction
4921 alternative matches and should therefore be as accommodating as
4922 possible. Match routines should not report errors if something
4923 is only invalid for !LAX_MATCH. */
4924 bfd_boolean lax_match
;
4926 /* True if a reference to the current AT register was seen. */
4927 bfd_boolean seen_at
;
4930 /* Record that the argument is out of range. */
4933 match_out_of_range (struct mips_arg_info
*arg
)
4935 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4938 /* Record that the argument isn't constant but needs to be. */
4941 match_not_constant (struct mips_arg_info
*arg
)
4943 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4947 /* Try to match an OT_CHAR token for character CH. Consume the token
4948 and return true on success, otherwise return false. */
4951 match_char (struct mips_arg_info
*arg
, char ch
)
4953 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4963 /* Try to get an expression from the next tokens in ARG. Consume the
4964 tokens and return true on success, storing the expression value in
4965 VALUE and relocation types in R. */
4968 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4969 bfd_reloc_code_real_type
*r
)
4971 /* If the next token is a '(' that was parsed as being part of a base
4972 expression, assume we have an elided offset. The later match will fail
4973 if this turns out to be wrong. */
4974 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4976 value
->X_op
= O_constant
;
4977 value
->X_add_number
= 0;
4978 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4982 /* Reject register-based expressions such as "0+$2" and "(($2))".
4983 For plain registers the default error seems more appropriate. */
4984 if (arg
->token
->type
== OT_INTEGER
4985 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4987 set_insn_error (arg
->argnum
, _("register value used as expression"));
4991 if (arg
->token
->type
== OT_INTEGER
)
4993 *value
= arg
->token
->u
.integer
.value
;
4994 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
5000 (arg
->argnum
, _("operand %d must be an immediate expression"),
5005 /* Try to get a constant expression from the next tokens in ARG. Consume
5006 the tokens and return true on success, storing the constant value
5010 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
5013 bfd_reloc_code_real_type r
[3];
5015 if (!match_expression (arg
, &ex
, r
))
5018 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5019 *value
= ex
.X_add_number
;
5022 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5023 match_out_of_range (arg
);
5025 match_not_constant (arg
);
5031 /* Return the RTYPE_* flags for a register operand of type TYPE that
5032 appears in instruction OPCODE. */
5035 convert_reg_type (const struct mips_opcode
*opcode
,
5036 enum mips_reg_operand_type type
)
5041 return RTYPE_NUM
| RTYPE_GP
;
5044 /* Allow vector register names for MDMX if the instruction is a 64-bit
5045 FPR load, store or move (including moves to and from GPRs). */
5046 if ((mips_opts
.ase
& ASE_MDMX
)
5047 && (opcode
->pinfo
& FP_D
)
5048 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5049 | INSN_COPROC_MEMORY_DELAY
5052 | INSN_STORE_MEMORY
)))
5053 return RTYPE_FPU
| RTYPE_VEC
;
5057 if (opcode
->pinfo
& (FP_D
| FP_S
))
5058 return RTYPE_CCC
| RTYPE_FCC
;
5062 if (opcode
->membership
& INSN_5400
)
5064 return RTYPE_FPU
| RTYPE_VEC
;
5070 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5071 return RTYPE_NUM
| RTYPE_CP0
;
5078 return RTYPE_NUM
| RTYPE_VI
;
5081 return RTYPE_NUM
| RTYPE_VF
;
5083 case OP_REG_R5900_I
:
5084 return RTYPE_R5900_I
;
5086 case OP_REG_R5900_Q
:
5087 return RTYPE_R5900_Q
;
5089 case OP_REG_R5900_R
:
5090 return RTYPE_R5900_R
;
5092 case OP_REG_R5900_ACC
:
5093 return RTYPE_R5900_ACC
;
5098 case OP_REG_MSA_CTRL
:
5104 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5107 check_regno (struct mips_arg_info
*arg
,
5108 enum mips_reg_operand_type type
, unsigned int regno
)
5110 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5111 arg
->seen_at
= TRUE
;
5113 if (type
== OP_REG_FP
5115 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5117 /* This was a warning prior to introducing O32 FPXX and FP64 support
5118 so maintain a warning for FP32 but raise an error for the new
5121 as_warn (_("float register should be even, was %d"), regno
);
5123 as_bad (_("float register should be even, was %d"), regno
);
5126 if (type
== OP_REG_CCC
)
5131 name
= arg
->insn
->insn_mo
->name
;
5132 length
= strlen (name
);
5133 if ((regno
& 1) != 0
5134 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5135 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5136 as_warn (_("condition code register should be even for %s, was %d"),
5139 if ((regno
& 3) != 0
5140 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5141 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5146 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5147 a register of type TYPE. Return true on success, storing the register
5148 number in *REGNO and warning about any dubious uses. */
5151 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5152 unsigned int symval
, unsigned int *regno
)
5154 if (type
== OP_REG_VEC
)
5155 symval
= mips_prefer_vec_regno (symval
);
5156 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5159 *regno
= symval
& RNUM_MASK
;
5160 check_regno (arg
, type
, *regno
);
5164 /* Try to interpret the next token in ARG as a register of type TYPE.
5165 Consume the token and return true on success, storing the register
5166 number in *REGNO. Return false on failure. */
5169 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5170 unsigned int *regno
)
5172 if (arg
->token
->type
== OT_REG
5173 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5181 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5182 Consume the token and return true on success, storing the register numbers
5183 in *REGNO1 and *REGNO2. Return false on failure. */
5186 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5187 unsigned int *regno1
, unsigned int *regno2
)
5189 if (match_reg (arg
, type
, regno1
))
5194 if (arg
->token
->type
== OT_REG_RANGE
5195 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5196 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5197 && *regno1
<= *regno2
)
5205 /* OP_INT matcher. */
5208 match_int_operand (struct mips_arg_info
*arg
,
5209 const struct mips_operand
*operand_base
)
5211 const struct mips_int_operand
*operand
;
5213 int min_val
, max_val
, factor
;
5216 operand
= (const struct mips_int_operand
*) operand_base
;
5217 factor
= 1 << operand
->shift
;
5218 min_val
= mips_int_operand_min (operand
);
5219 max_val
= mips_int_operand_max (operand
);
5221 if (operand_base
->lsb
== 0
5222 && operand_base
->size
== 16
5223 && operand
->shift
== 0
5224 && operand
->bias
== 0
5225 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5227 /* The operand can be relocated. */
5228 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5231 if (offset_expr
.X_op
== O_big
)
5233 match_out_of_range (arg
);
5237 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5238 /* Relocation operators were used. Accept the argument and
5239 leave the relocation value in offset_expr and offset_relocs
5240 for the caller to process. */
5243 if (offset_expr
.X_op
!= O_constant
)
5245 /* Accept non-constant operands if no later alternative matches,
5246 leaving it for the caller to process. */
5247 if (!arg
->lax_match
)
5249 match_not_constant (arg
);
5252 offset_reloc
[0] = BFD_RELOC_LO16
;
5256 /* Clear the global state; we're going to install the operand
5258 sval
= offset_expr
.X_add_number
;
5259 offset_expr
.X_op
= O_absent
;
5261 /* For compatibility with older assemblers, we accept
5262 0x8000-0xffff as signed 16-bit numbers when only
5263 signed numbers are allowed. */
5266 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5267 if (!arg
->lax_match
&& sval
<= max_val
)
5269 match_out_of_range (arg
);
5276 if (!match_const_int (arg
, &sval
))
5280 arg
->last_op_int
= sval
;
5282 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5284 match_out_of_range (arg
);
5288 uval
= (unsigned int) sval
>> operand
->shift
;
5289 uval
-= operand
->bias
;
5291 /* Handle -mfix-cn63xxp1. */
5293 && mips_fix_cn63xxp1
5294 && !mips_opts
.micromips
5295 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5310 /* The rest must be changed to 28. */
5315 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5319 /* OP_MAPPED_INT matcher. */
5322 match_mapped_int_operand (struct mips_arg_info
*arg
,
5323 const struct mips_operand
*operand_base
)
5325 const struct mips_mapped_int_operand
*operand
;
5326 unsigned int uval
, num_vals
;
5329 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5330 if (!match_const_int (arg
, &sval
))
5333 num_vals
= 1 << operand_base
->size
;
5334 for (uval
= 0; uval
< num_vals
; uval
++)
5335 if (operand
->int_map
[uval
] == sval
)
5337 if (uval
== num_vals
)
5339 match_out_of_range (arg
);
5343 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5347 /* OP_MSB matcher. */
5350 match_msb_operand (struct mips_arg_info
*arg
,
5351 const struct mips_operand
*operand_base
)
5353 const struct mips_msb_operand
*operand
;
5354 int min_val
, max_val
, max_high
;
5355 offsetT size
, sval
, high
;
5357 operand
= (const struct mips_msb_operand
*) operand_base
;
5358 min_val
= operand
->bias
;
5359 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5360 max_high
= operand
->opsize
;
5362 if (!match_const_int (arg
, &size
))
5365 high
= size
+ arg
->last_op_int
;
5366 sval
= operand
->add_lsb
? high
: size
;
5368 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5370 match_out_of_range (arg
);
5373 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5377 /* OP_REG matcher. */
5380 match_reg_operand (struct mips_arg_info
*arg
,
5381 const struct mips_operand
*operand_base
)
5383 const struct mips_reg_operand
*operand
;
5384 unsigned int regno
, uval
, num_vals
;
5386 operand
= (const struct mips_reg_operand
*) operand_base
;
5387 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5390 if (operand
->reg_map
)
5392 num_vals
= 1 << operand
->root
.size
;
5393 for (uval
= 0; uval
< num_vals
; uval
++)
5394 if (operand
->reg_map
[uval
] == regno
)
5396 if (num_vals
== uval
)
5402 arg
->last_regno
= regno
;
5403 if (arg
->opnum
== 1)
5404 arg
->dest_regno
= regno
;
5405 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5409 /* OP_REG_PAIR matcher. */
5412 match_reg_pair_operand (struct mips_arg_info
*arg
,
5413 const struct mips_operand
*operand_base
)
5415 const struct mips_reg_pair_operand
*operand
;
5416 unsigned int regno1
, regno2
, uval
, num_vals
;
5418 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5419 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5420 || !match_char (arg
, ',')
5421 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5424 num_vals
= 1 << operand_base
->size
;
5425 for (uval
= 0; uval
< num_vals
; uval
++)
5426 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5428 if (uval
== num_vals
)
5431 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5435 /* OP_PCREL matcher. The caller chooses the relocation type. */
5438 match_pcrel_operand (struct mips_arg_info
*arg
)
5440 bfd_reloc_code_real_type r
[3];
5442 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5445 /* OP_PERF_REG matcher. */
5448 match_perf_reg_operand (struct mips_arg_info
*arg
,
5449 const struct mips_operand
*operand
)
5453 if (!match_const_int (arg
, &sval
))
5458 || (mips_opts
.arch
== CPU_R5900
5459 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5460 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5462 set_insn_error (arg
->argnum
, _("invalid performance register"));
5466 insn_insert_operand (arg
->insn
, operand
, sval
);
5470 /* OP_ADDIUSP matcher. */
5473 match_addiusp_operand (struct mips_arg_info
*arg
,
5474 const struct mips_operand
*operand
)
5479 if (!match_const_int (arg
, &sval
))
5484 match_out_of_range (arg
);
5489 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5491 match_out_of_range (arg
);
5495 uval
= (unsigned int) sval
;
5496 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5497 insn_insert_operand (arg
->insn
, operand
, uval
);
5501 /* OP_CLO_CLZ_DEST matcher. */
5504 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5505 const struct mips_operand
*operand
)
5509 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5512 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5516 /* OP_CHECK_PREV matcher. */
5519 match_check_prev_operand (struct mips_arg_info
*arg
,
5520 const struct mips_operand
*operand_base
)
5522 const struct mips_check_prev_operand
*operand
;
5525 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5527 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5530 if (!operand
->zero_ok
&& regno
== 0)
5533 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5534 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5535 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5537 arg
->last_regno
= regno
;
5538 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5545 /* OP_SAME_RS_RT matcher. */
5548 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5549 const struct mips_operand
*operand
)
5553 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5558 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5562 arg
->last_regno
= regno
;
5564 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5568 /* OP_LWM_SWM_LIST matcher. */
5571 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5572 const struct mips_operand
*operand
)
5574 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5575 struct mips_arg_info reset
;
5578 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5582 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5587 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5590 while (match_char (arg
, ',')
5591 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5594 if (operand
->size
== 2)
5596 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5602 and any permutations of these. */
5603 if ((reglist
& 0xfff1ffff) != 0x80010000)
5606 sregs
= (reglist
>> 17) & 7;
5611 /* The list must include at least one of ra and s0-sN,
5612 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5613 which are $23 and $30 respectively.) E.g.:
5621 and any permutations of these. */
5622 if ((reglist
& 0x3f00ffff) != 0)
5625 ra
= (reglist
>> 27) & 0x10;
5626 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5629 if ((sregs
& -sregs
) != sregs
)
5632 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5636 /* OP_ENTRY_EXIT_LIST matcher. */
5639 match_entry_exit_operand (struct mips_arg_info
*arg
,
5640 const struct mips_operand
*operand
)
5643 bfd_boolean is_exit
;
5645 /* The format is the same for both ENTRY and EXIT, but the constraints
5647 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5648 mask
= (is_exit
? 7 << 3 : 0);
5651 unsigned int regno1
, regno2
;
5652 bfd_boolean is_freg
;
5654 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5656 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5661 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5664 mask
|= (5 + regno2
) << 3;
5666 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5667 mask
|= (regno2
- 3) << 3;
5668 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5669 mask
|= (regno2
- 15) << 1;
5670 else if (regno1
== RA
&& regno2
== RA
)
5675 while (match_char (arg
, ','));
5677 insn_insert_operand (arg
->insn
, operand
, mask
);
5681 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5682 the argument register mask AMASK, the number of static registers
5683 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5684 respectively, and the frame size FRAME_SIZE. */
5687 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5688 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5689 unsigned int frame_size
)
5691 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5692 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5695 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5696 argument register mask AMASK, the number of static registers saved
5697 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5698 respectively, and the frame size FRAME_SIZE. */
5701 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5702 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5703 unsigned int frame_size
)
5707 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5708 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5709 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5710 | ((frame_size
& 0xf0) << 16));
5714 /* OP_SAVE_RESTORE_LIST matcher. */
5717 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5719 unsigned int opcode
, args
, statics
, sregs
;
5720 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5721 unsigned int arg_mask
, ra
, s0
, s1
;
5724 opcode
= arg
->insn
->insn_opcode
;
5726 num_frame_sizes
= 0;
5735 unsigned int regno1
, regno2
;
5737 if (arg
->token
->type
== OT_INTEGER
)
5739 /* Handle the frame size. */
5740 if (!match_const_int (arg
, &frame_size
))
5742 num_frame_sizes
+= 1;
5746 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5749 while (regno1
<= regno2
)
5751 if (regno1
>= 4 && regno1
<= 7)
5753 if (num_frame_sizes
== 0)
5755 args
|= 1 << (regno1
- 4);
5757 /* statics $a0-$a3 */
5758 statics
|= 1 << (regno1
- 4);
5760 else if (regno1
>= 16 && regno1
<= 23)
5762 sregs
|= 1 << (regno1
- 16);
5763 else if (regno1
== 30)
5766 else if (regno1
== 31)
5767 /* Add $ra to insn. */
5777 while (match_char (arg
, ','));
5779 /* Encode args/statics combination. */
5782 else if (args
== 0xf)
5783 /* All $a0-$a3 are args. */
5784 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5785 else if (statics
== 0xf)
5786 /* All $a0-$a3 are statics. */
5787 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5790 /* Count arg registers. */
5800 /* Count static registers. */
5802 while (statics
& 0x8)
5804 statics
= (statics
<< 1) & 0xf;
5810 /* Encode args/statics. */
5811 arg_mask
= (num_args
<< 2) | num_statics
;
5814 /* Encode $s0/$s1. */
5815 if (sregs
& (1 << 0)) /* $s0 */
5817 if (sregs
& (1 << 1)) /* $s1 */
5821 /* Encode $s2-$s8. */
5831 /* Encode frame size. */
5832 if (num_frame_sizes
== 0)
5834 set_insn_error (arg
->argnum
, _("missing frame size"));
5837 if (num_frame_sizes
> 1)
5839 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5842 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5844 set_insn_error (arg
->argnum
, _("invalid frame size"));
5849 /* Finally build the instruction. */
5850 if (mips_opts
.mips16
)
5851 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5853 else if (!mips_opts
.micromips
)
5854 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5859 arg
->insn
->insn_opcode
= opcode
;
5863 /* OP_MDMX_IMM_REG matcher. */
5866 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5867 const struct mips_operand
*operand
)
5869 unsigned int regno
, uval
;
5871 const struct mips_opcode
*opcode
;
5873 /* The mips_opcode records whether this is an octobyte or quadhalf
5874 instruction. Start out with that bit in place. */
5875 opcode
= arg
->insn
->insn_mo
;
5876 uval
= mips_extract_operand (operand
, opcode
->match
);
5877 is_qh
= (uval
!= 0);
5879 if (arg
->token
->type
== OT_REG
)
5881 if ((opcode
->membership
& INSN_5400
)
5882 && strcmp (opcode
->name
, "rzu.ob") == 0)
5884 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5889 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5893 /* Check whether this is a vector register or a broadcast of
5894 a single element. */
5895 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5897 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5899 set_insn_error (arg
->argnum
, _("invalid element selector"));
5902 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5907 /* A full vector. */
5908 if ((opcode
->membership
& INSN_5400
)
5909 && (strcmp (opcode
->name
, "sll.ob") == 0
5910 || strcmp (opcode
->name
, "srl.ob") == 0))
5912 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5918 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5920 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5928 if (!match_const_int (arg
, &sval
))
5930 if (sval
< 0 || sval
> 31)
5932 match_out_of_range (arg
);
5935 uval
|= (sval
& 31);
5937 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5939 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5941 insn_insert_operand (arg
->insn
, operand
, uval
);
5945 /* OP_IMM_INDEX matcher. */
5948 match_imm_index_operand (struct mips_arg_info
*arg
,
5949 const struct mips_operand
*operand
)
5951 unsigned int max_val
;
5953 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5956 max_val
= (1 << operand
->size
) - 1;
5957 if (arg
->token
->u
.index
> max_val
)
5959 match_out_of_range (arg
);
5962 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5967 /* OP_REG_INDEX matcher. */
5970 match_reg_index_operand (struct mips_arg_info
*arg
,
5971 const struct mips_operand
*operand
)
5975 if (arg
->token
->type
!= OT_REG_INDEX
)
5978 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5981 insn_insert_operand (arg
->insn
, operand
, regno
);
5986 /* OP_PC matcher. */
5989 match_pc_operand (struct mips_arg_info
*arg
)
5991 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5999 /* OP_REG28 matcher. */
6002 match_reg28_operand (struct mips_arg_info
*arg
)
6006 if (arg
->token
->type
== OT_REG
6007 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6016 /* OP_NON_ZERO_REG matcher. */
6019 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6020 const struct mips_operand
*operand
)
6024 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6029 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6033 arg
->last_regno
= regno
;
6034 insn_insert_operand (arg
->insn
, operand
, regno
);
6038 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6039 register that we need to match. */
6042 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6046 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6049 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6050 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6051 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6053 Return the constant in IMM and OFFSET as follows:
6055 - If the constant should be loaded via memory, set IMM to O_absent and
6056 OFFSET to the memory address.
6058 - Otherwise, if the constant should be loaded into two 32-bit registers,
6059 set IMM to the O_constant to load into the high register and OFFSET
6060 to the corresponding value for the low register.
6062 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6064 These constants only appear as the last operand in an instruction,
6065 and every instruction that accepts them in any variant accepts them
6066 in all variants. This means we don't have to worry about backing out
6067 any changes if the instruction does not match. We just match
6068 unconditionally and report an error if the constant is invalid. */
6071 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6072 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6077 const char *newname
;
6078 unsigned char *data
;
6080 /* Where the constant is placed is based on how the MIPS assembler
6083 length == 4 && using_gprs -- immediate value only
6084 length == 8 && using_gprs -- .rdata or immediate value
6085 length == 4 && !using_gprs -- .lit4 or immediate value
6086 length == 8 && !using_gprs -- .lit8 or immediate value
6088 The .lit4 and .lit8 sections are only used if permitted by the
6090 if (arg
->token
->type
!= OT_FLOAT
)
6092 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6096 gas_assert (arg
->token
->u
.flt
.length
== length
);
6097 data
= arg
->token
->u
.flt
.data
;
6100 /* Handle 32-bit constants for which an immediate value is best. */
6103 || g_switch_value
< 4
6104 || (data
[0] == 0 && data
[1] == 0)
6105 || (data
[2] == 0 && data
[3] == 0)))
6107 imm
->X_op
= O_constant
;
6108 if (!target_big_endian
)
6109 imm
->X_add_number
= bfd_getl32 (data
);
6111 imm
->X_add_number
= bfd_getb32 (data
);
6112 offset
->X_op
= O_absent
;
6116 /* Handle 64-bit constants for which an immediate value is best. */
6118 && !mips_disable_float_construction
6119 /* Constants can only be constructed in GPRs and copied to FPRs if the
6120 GPRs are at least as wide as the FPRs or MTHC1 is available.
6121 Unlike most tests for 32-bit floating-point registers this check
6122 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6123 permit 64-bit moves without MXHC1.
6124 Force the constant into memory otherwise. */
6127 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6129 && ((data
[0] == 0 && data
[1] == 0)
6130 || (data
[2] == 0 && data
[3] == 0))
6131 && ((data
[4] == 0 && data
[5] == 0)
6132 || (data
[6] == 0 && data
[7] == 0)))
6134 /* The value is simple enough to load with a couple of instructions.
6135 If using 32-bit registers, set IMM to the high order 32 bits and
6136 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6138 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6140 imm
->X_op
= O_constant
;
6141 offset
->X_op
= O_constant
;
6142 if (!target_big_endian
)
6144 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6145 offset
->X_add_number
= bfd_getl32 (data
);
6149 imm
->X_add_number
= bfd_getb32 (data
);
6150 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6152 if (offset
->X_add_number
== 0)
6153 offset
->X_op
= O_absent
;
6157 imm
->X_op
= O_constant
;
6158 if (!target_big_endian
)
6159 imm
->X_add_number
= bfd_getl64 (data
);
6161 imm
->X_add_number
= bfd_getb64 (data
);
6162 offset
->X_op
= O_absent
;
6167 /* Switch to the right section. */
6169 subseg
= now_subseg
;
6172 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6177 if (using_gprs
|| g_switch_value
< 8)
6178 newname
= RDATA_SECTION_NAME
;
6183 new_seg
= subseg_new (newname
, (subsegT
) 0);
6184 bfd_set_section_flags (new_seg
,
6185 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6186 frag_align (length
== 4 ? 2 : 3, 0, 0);
6187 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6188 record_alignment (new_seg
, 4);
6190 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6192 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6194 /* Set the argument to the current address in the section. */
6195 imm
->X_op
= O_absent
;
6196 offset
->X_op
= O_symbol
;
6197 offset
->X_add_symbol
= symbol_temp_new_now ();
6198 offset
->X_add_number
= 0;
6200 /* Put the floating point number into the section. */
6201 p
= frag_more (length
);
6202 memcpy (p
, data
, length
);
6204 /* Switch back to the original section. */
6205 subseg_set (seg
, subseg
);
6209 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6213 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6214 const struct mips_operand
*operand
,
6215 bfd_boolean match_p
)
6219 /* The operand can be an XYZW mask or a single 2-bit channel index
6220 (with X being 0). */
6221 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6223 /* The suffix can be omitted when it is already part of the opcode. */
6224 if (arg
->token
->type
!= OT_CHANNELS
)
6227 uval
= arg
->token
->u
.channels
;
6228 if (operand
->size
== 2)
6230 /* Check that a single bit is set and convert it into a 2-bit index. */
6231 if ((uval
& -uval
) != uval
)
6233 uval
= 4 - ffs (uval
);
6236 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6241 insn_insert_operand (arg
->insn
, operand
, uval
);
6245 /* Try to match a token from ARG against OPERAND. Consume the token
6246 and return true on success, otherwise return false. */
6249 match_operand (struct mips_arg_info
*arg
,
6250 const struct mips_operand
*operand
)
6252 switch (operand
->type
)
6255 return match_int_operand (arg
, operand
);
6258 return match_mapped_int_operand (arg
, operand
);
6261 return match_msb_operand (arg
, operand
);
6264 case OP_OPTIONAL_REG
:
6265 return match_reg_operand (arg
, operand
);
6268 return match_reg_pair_operand (arg
, operand
);
6271 return match_pcrel_operand (arg
);
6274 return match_perf_reg_operand (arg
, operand
);
6276 case OP_ADDIUSP_INT
:
6277 return match_addiusp_operand (arg
, operand
);
6279 case OP_CLO_CLZ_DEST
:
6280 return match_clo_clz_dest_operand (arg
, operand
);
6282 case OP_LWM_SWM_LIST
:
6283 return match_lwm_swm_list_operand (arg
, operand
);
6285 case OP_ENTRY_EXIT_LIST
:
6286 return match_entry_exit_operand (arg
, operand
);
6288 case OP_SAVE_RESTORE_LIST
:
6289 return match_save_restore_list_operand (arg
);
6291 case OP_MDMX_IMM_REG
:
6292 return match_mdmx_imm_reg_operand (arg
, operand
);
6294 case OP_REPEAT_DEST_REG
:
6295 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6297 case OP_REPEAT_PREV_REG
:
6298 return match_tied_reg_operand (arg
, arg
->last_regno
);
6301 return match_pc_operand (arg
);
6304 return match_reg28_operand (arg
);
6307 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6309 case OP_VU0_MATCH_SUFFIX
:
6310 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6313 return match_imm_index_operand (arg
, operand
);
6316 return match_reg_index_operand (arg
, operand
);
6319 return match_same_rs_rt_operand (arg
, operand
);
6322 return match_check_prev_operand (arg
, operand
);
6324 case OP_NON_ZERO_REG
:
6325 return match_non_zero_reg_operand (arg
, operand
);
6330 /* ARG is the state after successfully matching an instruction.
6331 Issue any queued-up warnings. */
6334 check_completed_insn (struct mips_arg_info
*arg
)
6339 as_warn (_("used $at without \".set noat\""));
6341 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6345 /* Return true if modifying general-purpose register REG needs a delay. */
6348 reg_needs_delay (unsigned int reg
)
6350 unsigned long prev_pinfo
;
6352 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6353 if (!mips_opts
.noreorder
6354 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6355 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6356 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6362 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6363 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6364 by VR4120 errata. */
6367 classify_vr4120_insn (const char *name
)
6369 if (strncmp (name
, "macc", 4) == 0)
6370 return FIX_VR4120_MACC
;
6371 if (strncmp (name
, "dmacc", 5) == 0)
6372 return FIX_VR4120_DMACC
;
6373 if (strncmp (name
, "mult", 4) == 0)
6374 return FIX_VR4120_MULT
;
6375 if (strncmp (name
, "dmult", 5) == 0)
6376 return FIX_VR4120_DMULT
;
6377 if (strstr (name
, "div"))
6378 return FIX_VR4120_DIV
;
6379 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6380 return FIX_VR4120_MTHILO
;
6381 return NUM_FIX_VR4120_CLASSES
;
6384 #define INSN_ERET 0x42000018
6385 #define INSN_DERET 0x4200001f
6386 #define INSN_DMULT 0x1c
6387 #define INSN_DMULTU 0x1d
6389 /* Return the number of instructions that must separate INSN1 and INSN2,
6390 where INSN1 is the earlier instruction. Return the worst-case value
6391 for any INSN2 if INSN2 is null. */
6394 insns_between (const struct mips_cl_insn
*insn1
,
6395 const struct mips_cl_insn
*insn2
)
6397 unsigned long pinfo1
, pinfo2
;
6400 /* If INFO2 is null, pessimistically assume that all flags are set for
6401 the second instruction. */
6402 pinfo1
= insn1
->insn_mo
->pinfo
;
6403 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6405 /* For most targets, write-after-read dependencies on the HI and LO
6406 registers must be separated by at least two instructions. */
6407 if (!hilo_interlocks
)
6409 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6411 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6415 /* If we're working around r7000 errata, there must be two instructions
6416 between an mfhi or mflo and any instruction that uses the result. */
6417 if (mips_7000_hilo_fix
6418 && !mips_opts
.micromips
6419 && MF_HILO_INSN (pinfo1
)
6420 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6423 /* If we're working around 24K errata, one instruction is required
6424 if an ERET or DERET is followed by a branch instruction. */
6425 if (mips_fix_24k
&& !mips_opts
.micromips
)
6427 if (insn1
->insn_opcode
== INSN_ERET
6428 || insn1
->insn_opcode
== INSN_DERET
)
6431 || insn2
->insn_opcode
== INSN_ERET
6432 || insn2
->insn_opcode
== INSN_DERET
6433 || delayed_branch_p (insn2
))
6438 /* If we're working around PMC RM7000 errata, there must be three
6439 nops between a dmult and a load instruction. */
6440 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6442 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6443 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6445 if (pinfo2
& INSN_LOAD_MEMORY
)
6450 /* If working around VR4120 errata, check for combinations that need
6451 a single intervening instruction. */
6452 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6454 unsigned int class1
, class2
;
6456 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6457 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6461 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6462 if (vr4120_conflicts
[class1
] & (1 << class2
))
6467 if (!HAVE_CODE_COMPRESSION
)
6469 /* Check for GPR or coprocessor load delays. All such delays
6470 are on the RT register. */
6471 /* Itbl support may require additional care here. */
6472 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6473 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6475 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6479 /* Check for generic coprocessor hazards.
6481 This case is not handled very well. There is no special
6482 knowledge of CP0 handling, and the coprocessors other than
6483 the floating point unit are not distinguished at all. */
6484 /* Itbl support may require additional care here. FIXME!
6485 Need to modify this to include knowledge about
6486 user specified delays! */
6487 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6488 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6490 /* Handle cases where INSN1 writes to a known general coprocessor
6491 register. There must be a one instruction delay before INSN2
6492 if INSN2 reads that register, otherwise no delay is needed. */
6493 mask
= fpr_write_mask (insn1
);
6496 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6501 /* Read-after-write dependencies on the control registers
6502 require a two-instruction gap. */
6503 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6504 && (pinfo2
& INSN_READ_COND_CODE
))
6507 /* We don't know exactly what INSN1 does. If INSN2 is
6508 also a coprocessor instruction, assume there must be
6509 a one instruction gap. */
6510 if (pinfo2
& INSN_COP
)
6515 /* Check for read-after-write dependencies on the coprocessor
6516 control registers in cases where INSN1 does not need a general
6517 coprocessor delay. This means that INSN1 is a floating point
6518 comparison instruction. */
6519 /* Itbl support may require additional care here. */
6520 else if (!cop_interlocks
6521 && (pinfo1
& INSN_WRITE_COND_CODE
)
6522 && (pinfo2
& INSN_READ_COND_CODE
))
6526 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6527 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6529 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6530 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6531 || (insn2
&& delayed_branch_p (insn2
))))
6537 /* Return the number of nops that would be needed to work around the
6538 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6539 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6540 that are contained within the first IGNORE instructions of HIST. */
6543 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6544 const struct mips_cl_insn
*insn
)
6549 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6550 are not affected by the errata. */
6552 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6553 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6554 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6557 /* Search for the first MFLO or MFHI. */
6558 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6559 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6561 /* Extract the destination register. */
6562 mask
= gpr_write_mask (&hist
[i
]);
6564 /* No nops are needed if INSN reads that register. */
6565 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6568 /* ...or if any of the intervening instructions do. */
6569 for (j
= 0; j
< i
; j
++)
6570 if (gpr_read_mask (&hist
[j
]) & mask
)
6574 return MAX_VR4130_NOPS
- i
;
6579 #define BASE_REG_EQ(INSN1, INSN2) \
6580 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6581 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6583 /* Return the minimum alignment for this store instruction. */
6586 fix_24k_align_to (const struct mips_opcode
*mo
)
6588 if (strcmp (mo
->name
, "sh") == 0)
6591 if (strcmp (mo
->name
, "swc1") == 0
6592 || strcmp (mo
->name
, "swc2") == 0
6593 || strcmp (mo
->name
, "sw") == 0
6594 || strcmp (mo
->name
, "sc") == 0
6595 || strcmp (mo
->name
, "s.s") == 0)
6598 if (strcmp (mo
->name
, "sdc1") == 0
6599 || strcmp (mo
->name
, "sdc2") == 0
6600 || strcmp (mo
->name
, "s.d") == 0)
6607 struct fix_24k_store_info
6609 /* Immediate offset, if any, for this store instruction. */
6611 /* Alignment required by this store instruction. */
6613 /* True for register offsets. */
6614 int register_offset
;
6617 /* Comparison function used by qsort. */
6620 fix_24k_sort (const void *a
, const void *b
)
6622 const struct fix_24k_store_info
*pos1
= a
;
6623 const struct fix_24k_store_info
*pos2
= b
;
6625 return (pos1
->off
- pos2
->off
);
6628 /* INSN is a store instruction. Try to record the store information
6629 in STINFO. Return false if the information isn't known. */
6632 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6633 const struct mips_cl_insn
*insn
)
6635 /* The instruction must have a known offset. */
6636 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6639 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6640 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6644 /* Return the number of nops that would be needed to work around the 24k
6645 "lost data on stores during refill" errata if instruction INSN
6646 immediately followed the 2 instructions described by HIST.
6647 Ignore hazards that are contained within the first IGNORE
6648 instructions of HIST.
6650 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6651 for the data cache refills and store data. The following describes
6652 the scenario where the store data could be lost.
6654 * A data cache miss, due to either a load or a store, causing fill
6655 data to be supplied by the memory subsystem
6656 * The first three doublewords of fill data are returned and written
6658 * A sequence of four stores occurs in consecutive cycles around the
6659 final doubleword of the fill:
6663 * Zero, One or more instructions
6666 The four stores A-D must be to different doublewords of the line that
6667 is being filled. The fourth instruction in the sequence above permits
6668 the fill of the final doubleword to be transferred from the FSB into
6669 the cache. In the sequence above, the stores may be either integer
6670 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6671 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6672 different doublewords on the line. If the floating point unit is
6673 running in 1:2 mode, it is not possible to create the sequence above
6674 using only floating point store instructions.
6676 In this case, the cache line being filled is incorrectly marked
6677 invalid, thereby losing the data from any store to the line that
6678 occurs between the original miss and the completion of the five
6679 cycle sequence shown above.
6681 The workarounds are:
6683 * Run the data cache in write-through mode.
6684 * Insert a non-store instruction between
6685 Store A and Store B or Store B and Store C. */
6688 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6689 const struct mips_cl_insn
*insn
)
6691 struct fix_24k_store_info pos
[3];
6692 int align
, i
, base_offset
;
6697 /* If the previous instruction wasn't a store, there's nothing to
6699 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6702 /* If the instructions after the previous one are unknown, we have
6703 to assume the worst. */
6707 /* Check whether we are dealing with three consecutive stores. */
6708 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6709 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6712 /* If we don't know the relationship between the store addresses,
6713 assume the worst. */
6714 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6715 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6718 if (!fix_24k_record_store_info (&pos
[0], insn
)
6719 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6720 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6723 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6725 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6726 X bytes and such that the base register + X is known to be aligned
6729 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6733 align
= pos
[0].align_to
;
6734 base_offset
= pos
[0].off
;
6735 for (i
= 1; i
< 3; i
++)
6736 if (align
< pos
[i
].align_to
)
6738 align
= pos
[i
].align_to
;
6739 base_offset
= pos
[i
].off
;
6741 for (i
= 0; i
< 3; i
++)
6742 pos
[i
].off
-= base_offset
;
6745 pos
[0].off
&= ~align
+ 1;
6746 pos
[1].off
&= ~align
+ 1;
6747 pos
[2].off
&= ~align
+ 1;
6749 /* If any two stores write to the same chunk, they also write to the
6750 same doubleword. The offsets are still sorted at this point. */
6751 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6754 /* A range of at least 9 bytes is needed for the stores to be in
6755 non-overlapping doublewords. */
6756 if (pos
[2].off
- pos
[0].off
<= 8)
6759 if (pos
[2].off
- pos
[1].off
>= 24
6760 || pos
[1].off
- pos
[0].off
>= 24
6761 || pos
[2].off
- pos
[0].off
>= 32)
6767 /* Return the number of nops that would be needed if instruction INSN
6768 immediately followed the MAX_NOPS instructions given by HIST,
6769 where HIST[0] is the most recent instruction. Ignore hazards
6770 between INSN and the first IGNORE instructions in HIST.
6772 If INSN is null, return the worse-case number of nops for any
6776 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6777 const struct mips_cl_insn
*insn
)
6779 int i
, nops
, tmp_nops
;
6782 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6784 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6785 if (tmp_nops
> nops
)
6789 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6791 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6792 if (tmp_nops
> nops
)
6796 if (mips_fix_24k
&& !mips_opts
.micromips
)
6798 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6799 if (tmp_nops
> nops
)
6806 /* The variable arguments provide NUM_INSNS extra instructions that
6807 might be added to HIST. Return the largest number of nops that
6808 would be needed after the extended sequence, ignoring hazards
6809 in the first IGNORE instructions. */
6812 nops_for_sequence (int num_insns
, int ignore
,
6813 const struct mips_cl_insn
*hist
, ...)
6816 struct mips_cl_insn buffer
[MAX_NOPS
];
6817 struct mips_cl_insn
*cursor
;
6820 va_start (args
, hist
);
6821 cursor
= buffer
+ num_insns
;
6822 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6823 while (cursor
> buffer
)
6824 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6826 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6831 /* Like nops_for_insn, but if INSN is a branch, take into account the
6832 worst-case delay for the branch target. */
6835 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6836 const struct mips_cl_insn
*insn
)
6840 nops
= nops_for_insn (ignore
, hist
, insn
);
6841 if (delayed_branch_p (insn
))
6843 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6844 hist
, insn
, get_delay_slot_nop (insn
));
6845 if (tmp_nops
> nops
)
6848 else if (compact_branch_p (insn
))
6850 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6851 if (tmp_nops
> nops
)
6857 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6860 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6862 gas_assert (!HAVE_CODE_COMPRESSION
);
6863 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6864 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6867 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6868 jr target pc &= 'hffff_ffff_cfff_ffff. */
6871 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6873 gas_assert (!HAVE_CODE_COMPRESSION
);
6874 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6875 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6876 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6884 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6885 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6888 ep
.X_op
= O_constant
;
6889 ep
.X_add_number
= 0xcfff0000;
6890 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6891 ep
.X_add_number
= 0xffff;
6892 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6893 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6898 fix_loongson2f (struct mips_cl_insn
* ip
)
6900 if (mips_fix_loongson2f_nop
)
6901 fix_loongson2f_nop (ip
);
6903 if (mips_fix_loongson2f_jump
)
6904 fix_loongson2f_jump (ip
);
6908 has_label_name (const char *arr
[], size_t len
,const char *s
)
6911 for (i
= 0; i
< len
; i
++)
6915 if (streq (arr
[i
], s
))
6921 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6924 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6926 gas_assert (!HAVE_CODE_COMPRESSION
);
6928 /* If is an local label and the insn is not sync,
6929 look forward that whether an branch between ll/sc jump to here
6930 if so, insert a sync. */
6931 if (seg_info (now_seg
)->label_list
6932 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6933 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6937 const char *label_names
[MAX_LABELS_SAME
];
6938 const char *label_name
;
6940 label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6941 label_names
[0] = label_name
;
6942 struct insn_label_list
*llist
= seg_info (now_seg
)->label_list
;
6943 label_value
= S_GET_VALUE (llist
->label
);
6945 for (i
= 1; i
< MAX_LABELS_SAME
; i
++)
6947 llist
= llist
->next
;
6950 if (S_GET_VALUE (llist
->label
) == label_value
)
6951 label_names
[i
] = S_GET_NAME (llist
->label
);
6955 for (; i
< MAX_LABELS_SAME
; i
++)
6956 label_names
[i
] = NULL
;
6958 unsigned long lookback
= ARRAY_SIZE (history
);
6959 for (i
= 0; i
< lookback
; i
++)
6961 if (streq (history
[i
].insn_mo
->name
, "ll")
6962 || streq (history
[i
].insn_mo
->name
, "lld"))
6965 if (streq (history
[i
].insn_mo
->name
, "sc")
6966 || streq (history
[i
].insn_mo
->name
, "scd"))
6970 for (j
= i
+ 1; j
< lookback
; j
++)
6972 if (streq (history
[i
].insn_mo
->name
, "ll")
6973 || streq (history
[i
].insn_mo
->name
, "lld"))
6976 if (delayed_branch_p (&history
[j
]))
6978 if (has_label_name (label_names
,
6982 add_fixed_insn (&sync_insn
);
6983 insert_into_history (0, 1, &sync_insn
);
6992 /* If we find a sc, we look forward to look for an branch insn,
6993 and see whether it jump back and out of ll/sc. */
6994 else if (streq (ip
->insn_mo
->name
, "sc") || streq (ip
->insn_mo
->name
, "scd"))
6996 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6999 for (i
= 0; i
< lookback
; i
++)
7001 if (streq (history
[i
].insn_mo
->name
, "ll")
7002 || streq (history
[i
].insn_mo
->name
, "lld"))
7005 if (delayed_branch_p (&history
[i
]))
7009 for (j
= i
+ 1; j
< lookback
; j
++)
7011 if (streq (history
[j
].insn_mo
->name
, "ll")
7012 || streq (history
[i
].insn_mo
->name
, "lld"))
7016 for (; j
< lookback
; j
++)
7018 if (history
[j
].label
[0] != '\0'
7019 && streq (history
[j
].label
, history
[i
].target
)
7020 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
7022 add_fixed_insn (&sync_insn
);
7023 insert_into_history (++j
, 1, &sync_insn
);
7030 /* Skip if there is a sync before ll/lld. */
7031 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
7032 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
7033 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
7035 add_fixed_insn (&sync_insn
);
7036 insert_into_history (0, 1, &sync_insn
);
7040 /* IP is a branch that has a delay slot, and we need to fill it
7041 automatically. Return true if we can do that by swapping IP
7042 with the previous instruction.
7043 ADDRESS_EXPR is an operand of the instruction to be used with
7047 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7048 bfd_reloc_code_real_type
*reloc_type
)
7050 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7051 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7052 unsigned int fpr_read
, prev_fpr_write
;
7054 /* -O2 and above is required for this optimization. */
7055 if (mips_optimize
< 2)
7058 /* If we have seen .set volatile or .set nomove, don't optimize. */
7059 if (mips_opts
.nomove
)
7062 /* We can't swap if the previous instruction's position is fixed. */
7063 if (history
[0].fixed_p
)
7066 /* If the previous previous insn was in a .set noreorder, we can't
7067 swap. Actually, the MIPS assembler will swap in this situation.
7068 However, gcc configured -with-gnu-as will generate code like
7076 in which we can not swap the bne and INSN. If gcc is not configured
7077 -with-gnu-as, it does not output the .set pseudo-ops. */
7078 if (history
[1].noreorder_p
)
7081 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7082 This means that the previous instruction was a 4-byte one anyhow. */
7083 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7086 /* If the branch is itself the target of a branch, we can not swap.
7087 We cheat on this; all we check for is whether there is a label on
7088 this instruction. If there are any branches to anything other than
7089 a label, users must use .set noreorder. */
7090 if (seg_info (now_seg
)->label_list
)
7093 /* If the previous instruction is in a variant frag other than this
7094 branch's one, we cannot do the swap. This does not apply to
7095 MIPS16 code, which uses variant frags for different purposes. */
7096 if (!mips_opts
.mips16
7098 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7101 /* We do not swap with instructions that cannot architecturally
7102 be placed in a branch delay slot, such as SYNC or ERET. We
7103 also refrain from swapping with a trap instruction, since it
7104 complicates trap handlers to have the trap instruction be in
7106 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7107 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7110 /* Check for conflicts between the branch and the instructions
7111 before the candidate delay slot. */
7112 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7115 /* Check for conflicts between the swapped sequence and the
7116 target of the branch. */
7117 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7120 /* If the branch reads a register that the previous
7121 instruction sets, we can not swap. */
7122 gpr_read
= gpr_read_mask (ip
);
7123 prev_gpr_write
= gpr_write_mask (&history
[0]);
7124 if (gpr_read
& prev_gpr_write
)
7127 fpr_read
= fpr_read_mask (ip
);
7128 prev_fpr_write
= fpr_write_mask (&history
[0]);
7129 if (fpr_read
& prev_fpr_write
)
7132 /* If the branch writes a register that the previous
7133 instruction sets, we can not swap. */
7134 gpr_write
= gpr_write_mask (ip
);
7135 if (gpr_write
& prev_gpr_write
)
7138 /* If the branch writes a register that the previous
7139 instruction reads, we can not swap. */
7140 prev_gpr_read
= gpr_read_mask (&history
[0]);
7141 if (gpr_write
& prev_gpr_read
)
7144 /* If one instruction sets a condition code and the
7145 other one uses a condition code, we can not swap. */
7146 pinfo
= ip
->insn_mo
->pinfo
;
7147 if ((pinfo
& INSN_READ_COND_CODE
)
7148 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7150 if ((pinfo
& INSN_WRITE_COND_CODE
)
7151 && (prev_pinfo
& INSN_READ_COND_CODE
))
7154 /* If the previous instruction uses the PC, we can not swap. */
7155 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7156 if (prev_pinfo2
& INSN2_READ_PC
)
7159 /* If the previous instruction has an incorrect size for a fixed
7160 branch delay slot in microMIPS mode, we cannot swap. */
7161 pinfo2
= ip
->insn_mo
->pinfo2
;
7162 if (mips_opts
.micromips
7163 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7164 && insn_length (history
) != 2)
7166 if (mips_opts
.micromips
7167 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7168 && insn_length (history
) != 4)
7171 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7174 The short loop bug under certain conditions causes loops to execute
7175 only once or twice. We must ensure that the assembler never
7176 generates loops that satisfy all of the following conditions:
7178 - a loop consists of less than or equal to six instructions
7179 (including the branch delay slot);
7180 - a loop contains only one conditional branch instruction at the end
7182 - a loop does not contain any other branch or jump instructions;
7183 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7185 We need to do this because of a hardware bug in the R5900 chip. */
7187 /* Check if instruction has a parameter, ignore "j $31". */
7188 && (address_expr
!= NULL
)
7189 /* Parameter must be 16 bit. */
7190 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7191 /* Branch to same segment. */
7192 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7193 /* Branch to same code fragment. */
7194 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7195 /* Can only calculate branch offset if value is known. */
7196 && symbol_constant_p (address_expr
->X_add_symbol
)
7197 /* Check if branch is really conditional. */
7198 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7199 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7200 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7203 /* Check if loop is shorter than or equal to 6 instructions
7204 including branch and delay slot. */
7205 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7212 /* When the loop includes branches or jumps,
7213 it is not a short loop. */
7214 for (i
= 0; i
< (distance
/ 4); i
++)
7216 if ((history
[i
].cleared_p
)
7217 || delayed_branch_p (&history
[i
]))
7225 /* Insert nop after branch to fix short loop. */
7234 /* Decide how we should add IP to the instruction stream.
7235 ADDRESS_EXPR is an operand of the instruction to be used with
7238 static enum append_method
7239 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7240 bfd_reloc_code_real_type
*reloc_type
)
7242 /* The relaxed version of a macro sequence must be inherently
7244 if (mips_relax
.sequence
== 2)
7247 /* We must not dabble with instructions in a ".set noreorder" block. */
7248 if (mips_opts
.noreorder
)
7251 /* Otherwise, it's our responsibility to fill branch delay slots. */
7252 if (delayed_branch_p (ip
))
7254 if (!branch_likely_p (ip
)
7255 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7258 if (mips_opts
.mips16
7259 && ISA_SUPPORTS_MIPS16E
7260 && gpr_read_mask (ip
) != 0)
7261 return APPEND_ADD_COMPACT
;
7263 if (mips_opts
.micromips
7264 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7265 || (!forced_insn_length
7266 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7267 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7268 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7269 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7270 return APPEND_ADD_COMPACT
;
7272 return APPEND_ADD_WITH_NOP
;
7278 /* IP is an instruction whose opcode we have just changed, END points
7279 to the end of the opcode table processed. Point IP->insn_mo to the
7280 new opcode's definition. */
7283 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7285 const struct mips_opcode
*mo
;
7287 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7288 if (mo
->pinfo
!= INSN_MACRO
7289 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7297 /* IP is a MIPS16 instruction whose opcode we have just changed.
7298 Point IP->insn_mo to the new opcode's definition. */
7301 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7303 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7306 /* IP is a microMIPS instruction whose opcode we have just changed.
7307 Point IP->insn_mo to the new opcode's definition. */
7310 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7312 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7315 /* For microMIPS macros, we need to generate a local number label
7316 as the target of branches. */
7317 #define MICROMIPS_LABEL_CHAR '\037'
7318 static unsigned long micromips_target_label
;
7319 static char micromips_target_name
[32];
7322 micromips_label_name (void)
7324 char *p
= micromips_target_name
;
7325 char symbol_name_temporary
[24];
7333 l
= micromips_target_label
;
7334 #ifdef LOCAL_LABEL_PREFIX
7335 *p
++ = LOCAL_LABEL_PREFIX
;
7338 *p
++ = MICROMIPS_LABEL_CHAR
;
7341 symbol_name_temporary
[i
++] = l
% 10 + '0';
7346 *p
++ = symbol_name_temporary
[--i
];
7349 return micromips_target_name
;
7353 micromips_label_expr (expressionS
*label_expr
)
7355 label_expr
->X_op
= O_symbol
;
7356 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7357 label_expr
->X_add_number
= 0;
7361 micromips_label_inc (void)
7363 micromips_target_label
++;
7364 *micromips_target_name
= '\0';
7368 micromips_add_label (void)
7372 s
= colon (micromips_label_name ());
7373 micromips_label_inc ();
7374 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7377 /* If assembling microMIPS code, then return the microMIPS reloc
7378 corresponding to the requested one if any. Otherwise return
7379 the reloc unchanged. */
7381 static bfd_reloc_code_real_type
7382 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7384 static const bfd_reloc_code_real_type relocs
[][2] =
7386 /* Keep sorted incrementally by the left-hand key. */
7387 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7388 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7389 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7390 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7391 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7392 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7393 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7394 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7395 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7396 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7397 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7398 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7399 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7400 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7401 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7402 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7403 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7404 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7405 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7406 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7407 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7408 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7409 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7410 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7411 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7412 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7413 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7415 bfd_reloc_code_real_type r
;
7418 if (!mips_opts
.micromips
)
7420 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7426 return relocs
[i
][1];
7431 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7432 Return true on success, storing the resolved value in RESULT. */
7435 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7440 case BFD_RELOC_MIPS_HIGHEST
:
7441 case BFD_RELOC_MICROMIPS_HIGHEST
:
7442 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7445 case BFD_RELOC_MIPS_HIGHER
:
7446 case BFD_RELOC_MICROMIPS_HIGHER
:
7447 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7450 case BFD_RELOC_HI16_S
:
7451 case BFD_RELOC_HI16_S_PCREL
:
7452 case BFD_RELOC_MICROMIPS_HI16_S
:
7453 case BFD_RELOC_MIPS16_HI16_S
:
7454 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7457 case BFD_RELOC_HI16
:
7458 case BFD_RELOC_MICROMIPS_HI16
:
7459 case BFD_RELOC_MIPS16_HI16
:
7460 *result
= (operand
>> 16) & 0xffff;
7463 case BFD_RELOC_LO16
:
7464 case BFD_RELOC_LO16_PCREL
:
7465 case BFD_RELOC_MICROMIPS_LO16
:
7466 case BFD_RELOC_MIPS16_LO16
:
7467 *result
= operand
& 0xffff;
7470 case BFD_RELOC_UNUSED
:
7479 /* Output an instruction. IP is the instruction information.
7480 ADDRESS_EXPR is an operand of the instruction to be used with
7481 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7482 a macro expansion. */
7485 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7486 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7488 unsigned long prev_pinfo2
, pinfo
;
7489 bfd_boolean relaxed_branch
= FALSE
;
7490 enum append_method method
;
7491 bfd_boolean relax32
;
7494 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7495 fix_loongson2f (ip
);
7497 ip
->target
[0] = '\0';
7498 if (offset_expr
.X_op
== O_symbol
)
7499 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7500 ip
->label
[0] = '\0';
7501 if (seg_info (now_seg
)->label_list
)
7502 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7503 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7504 fix_loongson3_llsc (ip
);
7506 file_ase_mips16
|= mips_opts
.mips16
;
7507 file_ase_micromips
|= mips_opts
.micromips
;
7509 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7510 pinfo
= ip
->insn_mo
->pinfo
;
7512 /* Don't raise alarm about `nods' frags as they'll fill in the right
7513 kind of nop in relaxation if required. */
7514 if (mips_opts
.micromips
7516 && !(history
[0].frag
7517 && history
[0].frag
->fr_type
== rs_machine_dependent
7518 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7519 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7520 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7521 && micromips_insn_length (ip
->insn_mo
) != 2)
7522 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7523 && micromips_insn_length (ip
->insn_mo
) != 4)))
7524 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7525 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7527 if (address_expr
== NULL
)
7529 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7530 && reloc_type
[1] == BFD_RELOC_UNUSED
7531 && reloc_type
[2] == BFD_RELOC_UNUSED
7532 && address_expr
->X_op
== O_constant
)
7534 switch (*reloc_type
)
7536 case BFD_RELOC_MIPS_JMP
:
7540 /* Shift is 2, unusually, for microMIPS JALX. */
7541 shift
= (mips_opts
.micromips
7542 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7543 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7544 as_bad (_("jump to misaligned address (0x%lx)"),
7545 (unsigned long) address_expr
->X_add_number
);
7546 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7552 case BFD_RELOC_MIPS16_JMP
:
7553 if ((address_expr
->X_add_number
& 3) != 0)
7554 as_bad (_("jump to misaligned address (0x%lx)"),
7555 (unsigned long) address_expr
->X_add_number
);
7557 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7558 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7559 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7563 case BFD_RELOC_16_PCREL_S2
:
7567 shift
= mips_opts
.micromips
? 1 : 2;
7568 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7569 as_bad (_("branch to misaligned address (0x%lx)"),
7570 (unsigned long) address_expr
->X_add_number
);
7571 if (!mips_relax_branch
)
7573 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7574 & ~((1 << (shift
+ 16)) - 1))
7575 as_bad (_("branch address range overflow (0x%lx)"),
7576 (unsigned long) address_expr
->X_add_number
);
7577 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7583 case BFD_RELOC_MIPS_21_PCREL_S2
:
7588 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7589 as_bad (_("branch to misaligned address (0x%lx)"),
7590 (unsigned long) address_expr
->X_add_number
);
7591 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7592 & ~((1 << (shift
+ 21)) - 1))
7593 as_bad (_("branch address range overflow (0x%lx)"),
7594 (unsigned long) address_expr
->X_add_number
);
7595 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7600 case BFD_RELOC_MIPS_26_PCREL_S2
:
7605 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7606 as_bad (_("branch to misaligned address (0x%lx)"),
7607 (unsigned long) address_expr
->X_add_number
);
7608 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7609 & ~((1 << (shift
+ 26)) - 1))
7610 as_bad (_("branch address range overflow (0x%lx)"),
7611 (unsigned long) address_expr
->X_add_number
);
7612 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7621 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7624 ip
->insn_opcode
|= value
& 0xffff;
7632 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7634 /* There are a lot of optimizations we could do that we don't.
7635 In particular, we do not, in general, reorder instructions.
7636 If you use gcc with optimization, it will reorder
7637 instructions and generally do much more optimization then we
7638 do here; repeating all that work in the assembler would only
7639 benefit hand written assembly code, and does not seem worth
7641 int nops
= (mips_optimize
== 0
7642 ? nops_for_insn (0, history
, NULL
)
7643 : nops_for_insn_or_target (0, history
, ip
));
7647 unsigned long old_frag_offset
;
7650 old_frag
= frag_now
;
7651 old_frag_offset
= frag_now_fix ();
7653 for (i
= 0; i
< nops
; i
++)
7654 add_fixed_insn (NOP_INSN
);
7655 insert_into_history (0, nops
, NOP_INSN
);
7659 listing_prev_line ();
7660 /* We may be at the start of a variant frag. In case we
7661 are, make sure there is enough space for the frag
7662 after the frags created by listing_prev_line. The
7663 argument to frag_grow here must be at least as large
7664 as the argument to all other calls to frag_grow in
7665 this file. We don't have to worry about being in the
7666 middle of a variant frag, because the variants insert
7667 all needed nop instructions themselves. */
7671 mips_move_text_labels ();
7673 #ifndef NO_ECOFF_DEBUGGING
7674 if (ECOFF_DEBUGGING
)
7675 ecoff_fix_loc (old_frag
, old_frag_offset
);
7679 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7683 /* Work out how many nops in prev_nop_frag are needed by IP,
7684 ignoring hazards generated by the first prev_nop_frag_since
7686 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7687 gas_assert (nops
<= prev_nop_frag_holds
);
7689 /* Enforce NOPS as a minimum. */
7690 if (nops
> prev_nop_frag_required
)
7691 prev_nop_frag_required
= nops
;
7693 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7695 /* Settle for the current number of nops. Update the history
7696 accordingly (for the benefit of any future .set reorder code). */
7697 prev_nop_frag
= NULL
;
7698 insert_into_history (prev_nop_frag_since
,
7699 prev_nop_frag_holds
, NOP_INSN
);
7703 /* Allow this instruction to replace one of the nops that was
7704 tentatively added to prev_nop_frag. */
7705 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7706 prev_nop_frag_holds
--;
7707 prev_nop_frag_since
++;
7711 method
= get_append_method (ip
, address_expr
, reloc_type
);
7712 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7714 dwarf2_emit_insn (0);
7715 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7716 so "move" the instruction address accordingly.
7718 Also, it doesn't seem appropriate for the assembler to reorder .loc
7719 entries. If this instruction is a branch that we are going to swap
7720 with the previous instruction, the two instructions should be
7721 treated as a unit, and the debug information for both instructions
7722 should refer to the start of the branch sequence. Using the
7723 current position is certainly wrong when swapping a 32-bit branch
7724 and a 16-bit delay slot, since the current position would then be
7725 in the middle of a branch. */
7726 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7728 relax32
= (mips_relax_branch
7729 /* Don't try branch relaxation within .set nomacro, or within
7730 .set noat if we use $at for PIC computations. If it turns
7731 out that the branch was out-of-range, we'll get an error. */
7732 && !mips_opts
.warn_about_macros
7733 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7734 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7735 as they have no complementing branches. */
7736 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7738 if (!HAVE_CODE_COMPRESSION
7741 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7742 && delayed_branch_p (ip
))
7744 relaxed_branch
= TRUE
;
7745 add_relaxed_insn (ip
, (relaxed_branch_length
7747 uncond_branch_p (ip
) ? -1
7748 : branch_likely_p (ip
) ? 1
7751 (AT
, mips_pic
!= NO_PIC
,
7752 uncond_branch_p (ip
),
7753 branch_likely_p (ip
),
7754 pinfo
& INSN_WRITE_GPR_31
,
7756 address_expr
->X_add_symbol
,
7757 address_expr
->X_add_number
);
7758 *reloc_type
= BFD_RELOC_UNUSED
;
7760 else if (mips_opts
.micromips
7762 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7763 || *reloc_type
> BFD_RELOC_UNUSED
)
7764 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7765 /* Don't try branch relaxation when users specify
7766 16-bit/32-bit instructions. */
7767 && !forced_insn_length
)
7769 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7770 && *reloc_type
> BFD_RELOC_UNUSED
);
7771 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7772 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7773 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7774 int nods
= method
== APPEND_ADD_WITH_NOP
;
7775 int al
= pinfo
& INSN_WRITE_GPR_31
;
7776 int length32
= nods
? 8 : 4;
7778 gas_assert (address_expr
!= NULL
);
7779 gas_assert (!mips_relax
.sequence
);
7781 relaxed_branch
= TRUE
;
7783 method
= APPEND_ADD
;
7785 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7786 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7787 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7789 uncond
, compact
, al
, nods
,
7791 address_expr
->X_add_symbol
,
7792 address_expr
->X_add_number
);
7793 *reloc_type
= BFD_RELOC_UNUSED
;
7795 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7797 bfd_boolean require_unextended
;
7798 bfd_boolean require_extended
;
7802 if (forced_insn_length
!= 0)
7804 require_unextended
= forced_insn_length
== 2;
7805 require_extended
= forced_insn_length
== 4;
7809 require_unextended
= (mips_opts
.noautoextend
7810 && !mips_opcode_32bit_p (ip
->insn_mo
));
7811 require_extended
= 0;
7814 /* We need to set up a variant frag. */
7815 gas_assert (address_expr
!= NULL
);
7816 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7817 symbol created by `make_expr_symbol' may not get a necessary
7818 external relocation produced. */
7819 if (address_expr
->X_op
== O_symbol
)
7821 symbol
= address_expr
->X_add_symbol
;
7822 offset
= address_expr
->X_add_number
;
7826 symbol
= make_expr_symbol (address_expr
);
7827 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7830 add_relaxed_insn (ip
, 12, 0,
7832 (*reloc_type
- BFD_RELOC_UNUSED
,
7833 mips_opts
.ase
& ASE_MIPS16E2
,
7836 mips_opts
.warn_about_macros
,
7837 require_unextended
, require_extended
,
7838 delayed_branch_p (&history
[0]),
7839 history
[0].mips16_absolute_jump_p
),
7842 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7844 if (!delayed_branch_p (ip
))
7845 /* Make sure there is enough room to swap this instruction with
7846 a following jump instruction. */
7848 add_fixed_insn (ip
);
7852 if (mips_opts
.mips16
7853 && mips_opts
.noreorder
7854 && delayed_branch_p (&history
[0]))
7855 as_warn (_("extended instruction in delay slot"));
7857 if (mips_relax
.sequence
)
7859 /* If we've reached the end of this frag, turn it into a variant
7860 frag and record the information for the instructions we've
7862 if (frag_room () < 4)
7863 relax_close_frag ();
7864 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7867 if (mips_relax
.sequence
!= 2)
7869 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7870 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7871 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7872 mips_macro_warning
.insns
[0]++;
7874 if (mips_relax
.sequence
!= 1)
7876 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7877 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7878 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7879 mips_macro_warning
.insns
[1]++;
7882 if (mips_opts
.mips16
)
7885 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7887 add_fixed_insn (ip
);
7890 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7892 bfd_reloc_code_real_type final_type
[3];
7893 reloc_howto_type
*howto0
;
7894 reloc_howto_type
*howto
;
7897 /* Perform any necessary conversion to microMIPS relocations
7898 and find out how many relocations there actually are. */
7899 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7900 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7902 /* In a compound relocation, it is the final (outermost)
7903 operator that determines the relocated field. */
7904 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7909 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7910 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7911 bfd_get_reloc_size (howto
),
7913 howto0
&& howto0
->pc_relative
,
7915 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7916 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7918 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7919 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7920 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7922 /* These relocations can have an addend that won't fit in
7923 4 octets for 64bit assembly. */
7925 && ! howto
->partial_inplace
7926 && (reloc_type
[0] == BFD_RELOC_16
7927 || reloc_type
[0] == BFD_RELOC_32
7928 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7929 || reloc_type
[0] == BFD_RELOC_GPREL16
7930 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7931 || reloc_type
[0] == BFD_RELOC_GPREL32
7932 || reloc_type
[0] == BFD_RELOC_64
7933 || reloc_type
[0] == BFD_RELOC_CTOR
7934 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7935 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7936 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7937 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7938 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7939 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7940 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7941 || hi16_reloc_p (reloc_type
[0])
7942 || lo16_reloc_p (reloc_type
[0])))
7943 ip
->fixp
[0]->fx_no_overflow
= 1;
7945 /* These relocations can have an addend that won't fit in 2 octets. */
7946 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7947 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7948 ip
->fixp
[0]->fx_no_overflow
= 1;
7950 if (mips_relax
.sequence
)
7952 if (mips_relax
.first_fixup
== 0)
7953 mips_relax
.first_fixup
= ip
->fixp
[0];
7955 else if (reloc_needs_lo_p (*reloc_type
))
7957 struct mips_hi_fixup
*hi_fixup
;
7959 /* Reuse the last entry if it already has a matching %lo. */
7960 hi_fixup
= mips_hi_fixup_list
;
7962 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7964 hi_fixup
= XNEW (struct mips_hi_fixup
);
7965 hi_fixup
->next
= mips_hi_fixup_list
;
7966 mips_hi_fixup_list
= hi_fixup
;
7968 hi_fixup
->fixp
= ip
->fixp
[0];
7969 hi_fixup
->seg
= now_seg
;
7972 /* Add fixups for the second and third relocations, if given.
7973 Note that the ABI allows the second relocation to be
7974 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7975 moment we only use RSS_UNDEF, but we could add support
7976 for the others if it ever becomes necessary. */
7977 for (i
= 1; i
< 3; i
++)
7978 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7980 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7981 ip
->fixp
[0]->fx_size
, NULL
, 0,
7982 FALSE
, final_type
[i
]);
7984 /* Use fx_tcbit to mark compound relocs. */
7985 ip
->fixp
[0]->fx_tcbit
= 1;
7986 ip
->fixp
[i
]->fx_tcbit
= 1;
7990 /* Update the register mask information. */
7991 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7992 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7997 insert_into_history (0, 1, ip
);
8000 case APPEND_ADD_WITH_NOP
:
8002 struct mips_cl_insn
*nop
;
8004 insert_into_history (0, 1, ip
);
8005 nop
= get_delay_slot_nop (ip
);
8006 add_fixed_insn (nop
);
8007 insert_into_history (0, 1, nop
);
8008 if (mips_relax
.sequence
)
8009 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
8013 case APPEND_ADD_COMPACT
:
8014 /* Convert MIPS16 jr/jalr into a "compact" jump. */
8015 if (mips_opts
.mips16
)
8017 ip
->insn_opcode
|= 0x0080;
8018 find_altered_mips16_opcode (ip
);
8020 /* Convert microMIPS instructions. */
8021 else if (mips_opts
.micromips
)
8024 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
8025 ip
->insn_opcode
|= 0x0020;
8027 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
8028 ip
->insn_opcode
= 0x40e00000;
8029 /* beqz16->beqzc, bnez16->bnezc */
8030 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
8032 unsigned long regno
;
8034 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
8035 regno
&= MICROMIPSOP_MASK_MD
;
8036 regno
= micromips_to_32_reg_d_map
[regno
];
8037 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8038 | (regno
<< MICROMIPSOP_SH_RS
)
8039 | 0x40a00000) ^ 0x00400000;
8041 /* beqz->beqzc, bnez->bnezc */
8042 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8043 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8044 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8045 | 0x40a00000) ^ 0x00400000;
8046 /* beq $0->beqzc, bne $0->bnezc */
8047 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8048 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8049 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8050 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8051 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8052 | 0x40a00000) ^ 0x00400000;
8055 find_altered_micromips_opcode (ip
);
8060 insert_into_history (0, 1, ip
);
8065 struct mips_cl_insn delay
= history
[0];
8067 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8069 /* Add the delay slot instruction to the end of the
8070 current frag and shrink the fixed part of the
8071 original frag. If the branch occupies the tail of
8072 the latter, move it backwards to cover the gap. */
8073 delay
.frag
->fr_fix
-= branch_disp
;
8074 if (delay
.frag
== ip
->frag
)
8075 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8076 add_fixed_insn (&delay
);
8080 /* If this is not a relaxed branch and we are in the
8081 same frag, then just swap the instructions. */
8082 move_insn (ip
, delay
.frag
, delay
.where
);
8083 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8087 insert_into_history (0, 1, &delay
);
8092 /* If we have just completed an unconditional branch, clear the history. */
8093 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8094 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8098 mips_no_prev_insn ();
8100 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8101 history
[i
].cleared_p
= 1;
8104 /* We need to emit a label at the end of branch-likely macros. */
8105 if (emit_branch_likely_macro
)
8107 emit_branch_likely_macro
= FALSE
;
8108 micromips_add_label ();
8111 /* We just output an insn, so the next one doesn't have a label. */
8112 mips_clear_insn_labels ();
8115 /* Forget that there was any previous instruction or label.
8116 When BRANCH is true, the branch history is also flushed. */
8119 mips_no_prev_insn (void)
8121 prev_nop_frag
= NULL
;
8122 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8123 mips_clear_insn_labels ();
8126 /* This function must be called before we emit something other than
8127 instructions. It is like mips_no_prev_insn except that it inserts
8128 any NOPS that might be needed by previous instructions. */
8131 mips_emit_delays (void)
8133 if (! mips_opts
.noreorder
)
8135 int nops
= nops_for_insn (0, history
, NULL
);
8139 add_fixed_insn (NOP_INSN
);
8140 mips_move_text_labels ();
8143 mips_no_prev_insn ();
8146 /* Start a (possibly nested) noreorder block. */
8149 start_noreorder (void)
8151 if (mips_opts
.noreorder
== 0)
8156 /* None of the instructions before the .set noreorder can be moved. */
8157 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8158 history
[i
].fixed_p
= 1;
8160 /* Insert any nops that might be needed between the .set noreorder
8161 block and the previous instructions. We will later remove any
8162 nops that turn out not to be needed. */
8163 nops
= nops_for_insn (0, history
, NULL
);
8166 if (mips_optimize
!= 0)
8168 /* Record the frag which holds the nop instructions, so
8169 that we can remove them if we don't need them. */
8170 frag_grow (nops
* NOP_INSN_SIZE
);
8171 prev_nop_frag
= frag_now
;
8172 prev_nop_frag_holds
= nops
;
8173 prev_nop_frag_required
= 0;
8174 prev_nop_frag_since
= 0;
8177 for (; nops
> 0; --nops
)
8178 add_fixed_insn (NOP_INSN
);
8180 /* Move on to a new frag, so that it is safe to simply
8181 decrease the size of prev_nop_frag. */
8182 frag_wane (frag_now
);
8184 mips_move_text_labels ();
8186 mips_mark_labels ();
8187 mips_clear_insn_labels ();
8189 mips_opts
.noreorder
++;
8190 mips_any_noreorder
= 1;
8193 /* End a nested noreorder block. */
8196 end_noreorder (void)
8198 mips_opts
.noreorder
--;
8199 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8201 /* Commit to inserting prev_nop_frag_required nops and go back to
8202 handling nop insertion the .set reorder way. */
8203 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8205 insert_into_history (prev_nop_frag_since
,
8206 prev_nop_frag_required
, NOP_INSN
);
8207 prev_nop_frag
= NULL
;
8211 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8212 higher bits unset. */
8215 normalize_constant_expr (expressionS
*ex
)
8217 if (ex
->X_op
== O_constant
8218 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8219 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8223 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8224 all higher bits unset. */
8227 normalize_address_expr (expressionS
*ex
)
8229 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8230 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8231 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8232 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8236 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8237 Return true if the match was successful.
8239 OPCODE_EXTRA is a value that should be ORed into the opcode
8240 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8241 there are more alternatives after OPCODE and SOFT_MATCH is
8242 as for mips_arg_info. */
8245 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8246 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8247 bfd_boolean lax_match
, bfd_boolean complete_p
)
8250 struct mips_arg_info arg
;
8251 const struct mips_operand
*operand
;
8254 imm_expr
.X_op
= O_absent
;
8255 offset_expr
.X_op
= O_absent
;
8256 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8257 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8258 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8260 create_insn (insn
, opcode
);
8261 /* When no opcode suffix is specified, assume ".xyzw". */
8262 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8263 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8265 insn
->insn_opcode
|= opcode_extra
;
8266 memset (&arg
, 0, sizeof (arg
));
8270 arg
.last_regno
= ILLEGAL_REG
;
8271 arg
.dest_regno
= ILLEGAL_REG
;
8272 arg
.lax_match
= lax_match
;
8273 for (args
= opcode
->args
;; ++args
)
8275 if (arg
.token
->type
== OT_END
)
8277 /* Handle unary instructions in which only one operand is given.
8278 The source is then the same as the destination. */
8279 if (arg
.opnum
== 1 && *args
== ',')
8281 operand
= (mips_opts
.micromips
8282 ? decode_micromips_operand (args
+ 1)
8283 : decode_mips_operand (args
+ 1));
8284 if (operand
&& mips_optional_operand_p (operand
))
8292 /* Treat elided base registers as $0. */
8293 if (strcmp (args
, "(b)") == 0)
8301 /* The register suffix is optional. */
8306 /* Fail the match if there were too few operands. */
8310 /* Successful match. */
8313 clear_insn_error ();
8314 if (arg
.dest_regno
== arg
.last_regno
8315 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8319 (0, _("source and destination must be different"));
8320 else if (arg
.last_regno
== 31)
8322 (0, _("a destination register must be supplied"));
8324 else if (arg
.last_regno
== 31
8325 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8326 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8327 set_insn_error (0, _("the source register must not be $31"));
8328 check_completed_insn (&arg
);
8332 /* Fail the match if the line has too many operands. */
8336 /* Handle characters that need to match exactly. */
8337 if (*args
== '(' || *args
== ')' || *args
== ',')
8339 if (match_char (&arg
, *args
))
8346 if (arg
.token
->type
== OT_DOUBLE_CHAR
8347 && arg
.token
->u
.ch
== *args
)
8355 /* Handle special macro operands. Work out the properties of
8364 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8368 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8377 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8381 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8385 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8391 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8393 imm_expr
.X_op
= O_constant
;
8395 normalize_constant_expr (&imm_expr
);
8399 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8401 /* Assume that the offset has been elided and that what
8402 we saw was a base register. The match will fail later
8403 if that assumption turns out to be wrong. */
8404 offset_expr
.X_op
= O_constant
;
8405 offset_expr
.X_add_number
= 0;
8409 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8411 normalize_address_expr (&offset_expr
);
8416 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8422 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8428 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8434 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8440 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8444 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8448 gas_assert (mips_opts
.micromips
);
8454 if (!forced_insn_length
)
8455 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8457 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8459 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8465 operand
= (mips_opts
.micromips
8466 ? decode_micromips_operand (args
)
8467 : decode_mips_operand (args
));
8471 /* Skip prefixes. */
8472 if (*args
== '+' || *args
== 'm' || *args
== '-')
8475 if (mips_optional_operand_p (operand
)
8477 && (arg
.token
[0].type
!= OT_REG
8478 || arg
.token
[1].type
== OT_END
))
8480 /* Assume that the register has been elided and is the
8481 same as the first operand. */
8486 if (!match_operand (&arg
, operand
))
8491 /* Like match_insn, but for MIPS16. */
8494 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8495 struct mips_operand_token
*tokens
)
8498 const struct mips_operand
*operand
;
8499 const struct mips_operand
*ext_operand
;
8500 bfd_boolean pcrel
= FALSE
;
8501 int required_insn_length
;
8502 struct mips_arg_info arg
;
8505 if (forced_insn_length
)
8506 required_insn_length
= forced_insn_length
;
8507 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8508 required_insn_length
= 2;
8510 required_insn_length
= 0;
8512 create_insn (insn
, opcode
);
8513 imm_expr
.X_op
= O_absent
;
8514 offset_expr
.X_op
= O_absent
;
8515 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8516 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8517 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8520 memset (&arg
, 0, sizeof (arg
));
8524 arg
.last_regno
= ILLEGAL_REG
;
8525 arg
.dest_regno
= ILLEGAL_REG
;
8527 for (args
= opcode
->args
;; ++args
)
8531 if (arg
.token
->type
== OT_END
)
8535 /* Handle unary instructions in which only one operand is given.
8536 The source is then the same as the destination. */
8537 if (arg
.opnum
== 1 && *args
== ',')
8539 operand
= decode_mips16_operand (args
[1], FALSE
);
8540 if (operand
&& mips_optional_operand_p (operand
))
8548 /* Fail the match if there were too few operands. */
8552 /* Successful match. Stuff the immediate value in now, if
8554 clear_insn_error ();
8555 if (opcode
->pinfo
== INSN_MACRO
)
8557 gas_assert (relax_char
== 0 || relax_char
== 'p');
8558 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8561 && offset_expr
.X_op
== O_constant
8563 && calculate_reloc (*offset_reloc
,
8564 offset_expr
.X_add_number
,
8567 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8568 required_insn_length
, &insn
->insn_opcode
);
8569 offset_expr
.X_op
= O_absent
;
8570 *offset_reloc
= BFD_RELOC_UNUSED
;
8572 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8574 if (required_insn_length
== 2)
8575 set_insn_error (0, _("invalid unextended operand value"));
8576 else if (!mips_opcode_32bit_p (opcode
))
8578 forced_insn_length
= 4;
8579 insn
->insn_opcode
|= MIPS16_EXTEND
;
8582 else if (relax_char
)
8583 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8585 check_completed_insn (&arg
);
8589 /* Fail the match if the line has too many operands. */
8593 /* Handle characters that need to match exactly. */
8594 if (*args
== '(' || *args
== ')' || *args
== ',')
8596 if (match_char (&arg
, *args
))
8616 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8618 imm_expr
.X_op
= O_constant
;
8620 normalize_constant_expr (&imm_expr
);
8625 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8629 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8633 if (operand
->type
== OP_PCREL
)
8637 ext_operand
= decode_mips16_operand (c
, TRUE
);
8638 if (operand
!= ext_operand
)
8640 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8642 offset_expr
.X_op
= O_constant
;
8643 offset_expr
.X_add_number
= 0;
8648 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8651 /* '8' is used for SLTI(U) and has traditionally not
8652 been allowed to take relocation operators. */
8653 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8654 && (ext_operand
->size
!= 16 || c
== '8'))
8656 match_not_constant (&arg
);
8660 if (offset_expr
.X_op
== O_big
)
8662 match_out_of_range (&arg
);
8671 if (mips_optional_operand_p (operand
)
8673 && (arg
.token
[0].type
!= OT_REG
8674 || arg
.token
[1].type
== OT_END
))
8676 /* Assume that the register has been elided and is the
8677 same as the first operand. */
8682 if (!match_operand (&arg
, operand
))
8687 /* Record that the current instruction is invalid for the current ISA. */
8690 match_invalid_for_isa (void)
8693 (0, _("opcode not supported on this processor: %s (%s)"),
8694 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8695 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8698 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8699 Return true if a definite match or failure was found, storing any match
8700 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8701 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8702 tried and failed to match under normal conditions and now want to try a
8703 more relaxed match. */
8706 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8707 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8708 int opcode_extra
, bfd_boolean lax_match
)
8710 const struct mips_opcode
*opcode
;
8711 const struct mips_opcode
*invalid_delay_slot
;
8712 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8714 /* Search for a match, ignoring alternatives that don't satisfy the
8715 current ISA or forced_length. */
8716 invalid_delay_slot
= 0;
8717 seen_valid_for_isa
= FALSE
;
8718 seen_valid_for_size
= FALSE
;
8722 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8723 if (is_opcode_valid (opcode
))
8725 seen_valid_for_isa
= TRUE
;
8726 if (is_size_valid (opcode
))
8728 bfd_boolean delay_slot_ok
;
8730 seen_valid_for_size
= TRUE
;
8731 delay_slot_ok
= is_delay_slot_valid (opcode
);
8732 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8733 lax_match
, delay_slot_ok
))
8737 if (!invalid_delay_slot
)
8738 invalid_delay_slot
= opcode
;
8747 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8749 /* If the only matches we found had the wrong length for the delay slot,
8750 pick the first such match. We'll issue an appropriate warning later. */
8751 if (invalid_delay_slot
)
8753 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8759 /* Handle the case where we didn't try to match an instruction because
8760 all the alternatives were incompatible with the current ISA. */
8761 if (!seen_valid_for_isa
)
8763 match_invalid_for_isa ();
8767 /* Handle the case where we didn't try to match an instruction because
8768 all the alternatives were of the wrong size. */
8769 if (!seen_valid_for_size
)
8771 if (mips_opts
.insn32
)
8772 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8775 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8776 8 * forced_insn_length
);
8783 /* Like match_insns, but for MIPS16. */
8786 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8787 struct mips_operand_token
*tokens
)
8789 const struct mips_opcode
*opcode
;
8790 bfd_boolean seen_valid_for_isa
;
8791 bfd_boolean seen_valid_for_size
;
8793 /* Search for a match, ignoring alternatives that don't satisfy the
8794 current ISA. There are no separate entries for extended forms so
8795 we deal with forced_length later. */
8796 seen_valid_for_isa
= FALSE
;
8797 seen_valid_for_size
= FALSE
;
8801 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8802 if (is_opcode_valid_16 (opcode
))
8804 seen_valid_for_isa
= TRUE
;
8805 if (is_size_valid_16 (opcode
))
8807 seen_valid_for_size
= TRUE
;
8808 if (match_mips16_insn (insn
, opcode
, tokens
))
8814 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8815 && strcmp (opcode
->name
, first
->name
) == 0);
8817 /* Handle the case where we didn't try to match an instruction because
8818 all the alternatives were incompatible with the current ISA. */
8819 if (!seen_valid_for_isa
)
8821 match_invalid_for_isa ();
8825 /* Handle the case where we didn't try to match an instruction because
8826 all the alternatives were of the wrong size. */
8827 if (!seen_valid_for_size
)
8829 if (forced_insn_length
== 2)
8831 (0, _("unrecognized unextended version of MIPS16 opcode"));
8834 (0, _("unrecognized extended version of MIPS16 opcode"));
8841 /* Set up global variables for the start of a new macro. */
8846 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8847 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8848 sizeof (mips_macro_warning
.first_insn_sizes
));
8849 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8850 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8851 && delayed_branch_p (&history
[0]));
8853 && history
[0].frag
->fr_type
== rs_machine_dependent
8854 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8855 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8856 mips_macro_warning
.delay_slot_length
= 0;
8858 switch (history
[0].insn_mo
->pinfo2
8859 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8861 case INSN2_BRANCH_DELAY_32BIT
:
8862 mips_macro_warning
.delay_slot_length
= 4;
8864 case INSN2_BRANCH_DELAY_16BIT
:
8865 mips_macro_warning
.delay_slot_length
= 2;
8868 mips_macro_warning
.delay_slot_length
= 0;
8871 mips_macro_warning
.first_frag
= NULL
;
8874 /* Given that a macro is longer than one instruction or of the wrong size,
8875 return the appropriate warning for it. Return null if no warning is
8876 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8877 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8878 and RELAX_NOMACRO. */
8881 macro_warning (relax_substateT subtype
)
8883 if (subtype
& RELAX_DELAY_SLOT
)
8884 return _("macro instruction expanded into multiple instructions"
8885 " in a branch delay slot");
8886 else if (subtype
& RELAX_NOMACRO
)
8887 return _("macro instruction expanded into multiple instructions");
8888 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8889 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8890 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8891 ? _("macro instruction expanded into a wrong size instruction"
8892 " in a 16-bit branch delay slot")
8893 : _("macro instruction expanded into a wrong size instruction"
8894 " in a 32-bit branch delay slot"));
8899 /* Finish up a macro. Emit warnings as appropriate. */
8904 /* Relaxation warning flags. */
8905 relax_substateT subtype
= 0;
8907 /* Check delay slot size requirements. */
8908 if (mips_macro_warning
.delay_slot_length
== 2)
8909 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8910 if (mips_macro_warning
.delay_slot_length
!= 0)
8912 if (mips_macro_warning
.delay_slot_length
8913 != mips_macro_warning
.first_insn_sizes
[0])
8914 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8915 if (mips_macro_warning
.delay_slot_length
8916 != mips_macro_warning
.first_insn_sizes
[1])
8917 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8920 /* Check instruction count requirements. */
8921 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8923 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8924 subtype
|= RELAX_SECOND_LONGER
;
8925 if (mips_opts
.warn_about_macros
)
8926 subtype
|= RELAX_NOMACRO
;
8927 if (mips_macro_warning
.delay_slot_p
)
8928 subtype
|= RELAX_DELAY_SLOT
;
8931 /* If both alternatives fail to fill a delay slot correctly,
8932 emit the warning now. */
8933 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8934 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8939 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8940 | RELAX_DELAY_SLOT_SIZE_FIRST
8941 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8942 msg
= macro_warning (s
);
8944 as_warn ("%s", msg
);
8948 /* If both implementations are longer than 1 instruction, then emit the
8950 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8955 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8956 msg
= macro_warning (s
);
8958 as_warn ("%s", msg
);
8962 /* If any flags still set, then one implementation might need a warning
8963 and the other either will need one of a different kind or none at all.
8964 Pass any remaining flags over to relaxation. */
8965 if (mips_macro_warning
.first_frag
!= NULL
)
8966 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8969 /* Instruction operand formats used in macros that vary between
8970 standard MIPS and microMIPS code. */
8972 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8973 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8974 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8975 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8976 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8977 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8978 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8979 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8981 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8982 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8983 : cop12_fmt[mips_opts.micromips])
8984 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8985 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8986 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8987 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8988 : mem12_fmt[mips_opts.micromips])
8989 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8990 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8991 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8993 /* Read a macro's relocation codes from *ARGS and store them in *R.
8994 The first argument in *ARGS will be either the code for a single
8995 relocation or -1 followed by the three codes that make up a
8996 composite relocation. */
8999 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
9003 next
= va_arg (*args
, int);
9005 r
[0] = (bfd_reloc_code_real_type
) next
;
9008 for (i
= 0; i
< 3; i
++)
9009 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
9010 /* This function is only used for 16-bit relocation fields.
9011 To make the macro code simpler, treat an unrelocated value
9012 in the same way as BFD_RELOC_LO16. */
9013 if (r
[0] == BFD_RELOC_UNUSED
)
9014 r
[0] = BFD_RELOC_LO16
;
9018 /* Build an instruction created by a macro expansion. This is passed
9019 a pointer to the count of instructions created so far, an
9020 expression, the name of the instruction to build, an operand format
9021 string, and corresponding arguments. */
9024 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
9026 const struct mips_opcode
*mo
= NULL
;
9027 bfd_reloc_code_real_type r
[3];
9028 const struct mips_opcode
*amo
;
9029 const struct mips_operand
*operand
;
9030 struct hash_control
*hash
;
9031 struct mips_cl_insn insn
;
9035 va_start (args
, fmt
);
9037 if (mips_opts
.mips16
)
9039 mips16_macro_build (ep
, name
, fmt
, &args
);
9044 r
[0] = BFD_RELOC_UNUSED
;
9045 r
[1] = BFD_RELOC_UNUSED
;
9046 r
[2] = BFD_RELOC_UNUSED
;
9047 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9048 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
9050 gas_assert (strcmp (name
, amo
->name
) == 0);
9054 /* Search until we get a match for NAME. It is assumed here that
9055 macros will never generate MDMX, MIPS-3D, or MT instructions.
9056 We try to match an instruction that fulfills the branch delay
9057 slot instruction length requirement (if any) of the previous
9058 instruction. While doing this we record the first instruction
9059 seen that matches all the other conditions and use it anyway
9060 if the requirement cannot be met; we will issue an appropriate
9061 warning later on. */
9062 if (strcmp (fmt
, amo
->args
) == 0
9063 && amo
->pinfo
!= INSN_MACRO
9064 && is_opcode_valid (amo
)
9065 && is_size_valid (amo
))
9067 if (is_delay_slot_valid (amo
))
9077 gas_assert (amo
->name
);
9079 while (strcmp (name
, amo
->name
) == 0);
9082 create_insn (&insn
, mo
);
9095 macro_read_relocs (&args
, r
);
9096 gas_assert (*r
== BFD_RELOC_GPREL16
9097 || *r
== BFD_RELOC_MIPS_HIGHER
9098 || *r
== BFD_RELOC_HI16_S
9099 || *r
== BFD_RELOC_LO16
9100 || *r
== BFD_RELOC_MIPS_GOT_OFST
9101 || (mips_opts
.micromips
9102 && (*r
== BFD_RELOC_16
9103 || *r
== BFD_RELOC_MIPS_GOT16
9104 || *r
== BFD_RELOC_MIPS_CALL16
9105 || *r
== BFD_RELOC_MIPS_GOT_HI16
9106 || *r
== BFD_RELOC_MIPS_GOT_LO16
9107 || *r
== BFD_RELOC_MIPS_CALL_HI16
9108 || *r
== BFD_RELOC_MIPS_CALL_LO16
9109 || *r
== BFD_RELOC_MIPS_SUB
9110 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9111 || *r
== BFD_RELOC_MIPS_HIGHEST
9112 || *r
== BFD_RELOC_MIPS_GOT_DISP
9113 || *r
== BFD_RELOC_MIPS_TLS_GD
9114 || *r
== BFD_RELOC_MIPS_TLS_LDM
9115 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9116 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9117 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9118 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9119 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9123 macro_read_relocs (&args
, r
);
9127 macro_read_relocs (&args
, r
);
9128 gas_assert (ep
!= NULL
9129 && (ep
->X_op
== O_constant
9130 || (ep
->X_op
== O_symbol
9131 && (*r
== BFD_RELOC_MIPS_HIGHEST
9132 || *r
== BFD_RELOC_HI16_S
9133 || *r
== BFD_RELOC_HI16
9134 || *r
== BFD_RELOC_GPREL16
9135 || *r
== BFD_RELOC_MIPS_GOT_HI16
9136 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9140 gas_assert (ep
!= NULL
);
9143 * This allows macro() to pass an immediate expression for
9144 * creating short branches without creating a symbol.
9146 * We don't allow branch relaxation for these branches, as
9147 * they should only appear in ".set nomacro" anyway.
9149 if (ep
->X_op
== O_constant
)
9151 /* For microMIPS we always use relocations for branches.
9152 So we should not resolve immediate values. */
9153 gas_assert (!mips_opts
.micromips
);
9155 if ((ep
->X_add_number
& 3) != 0)
9156 as_bad (_("branch to misaligned address (0x%lx)"),
9157 (unsigned long) ep
->X_add_number
);
9158 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9159 as_bad (_("branch address range overflow (0x%lx)"),
9160 (unsigned long) ep
->X_add_number
);
9161 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9165 *r
= BFD_RELOC_16_PCREL_S2
;
9169 gas_assert (ep
!= NULL
);
9170 *r
= BFD_RELOC_MIPS_JMP
;
9174 operand
= (mips_opts
.micromips
9175 ? decode_micromips_operand (fmt
)
9176 : decode_mips_operand (fmt
));
9180 uval
= va_arg (args
, int);
9181 if (operand
->type
== OP_CLO_CLZ_DEST
)
9182 uval
|= (uval
<< 5);
9183 insn_insert_operand (&insn
, operand
, uval
);
9185 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9191 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9193 append_insn (&insn
, ep
, r
, TRUE
);
9197 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9200 struct mips_opcode
*mo
;
9201 struct mips_cl_insn insn
;
9202 const struct mips_operand
*operand
;
9203 bfd_reloc_code_real_type r
[3]
9204 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9206 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9208 gas_assert (strcmp (name
, mo
->name
) == 0);
9210 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9213 gas_assert (mo
->name
);
9214 gas_assert (strcmp (name
, mo
->name
) == 0);
9217 create_insn (&insn
, mo
);
9254 gas_assert (ep
!= NULL
);
9256 if (ep
->X_op
!= O_constant
)
9257 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9258 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9260 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9262 *r
= BFD_RELOC_UNUSED
;
9268 operand
= decode_mips16_operand (c
, FALSE
);
9272 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9277 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9279 append_insn (&insn
, ep
, r
, TRUE
);
9283 * Generate a "jalr" instruction with a relocation hint to the called
9284 * function. This occurs in NewABI PIC code.
9287 macro_build_jalr (expressionS
*ep
, int cprestore
)
9289 static const bfd_reloc_code_real_type jalr_relocs
[2]
9290 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9291 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9295 if (MIPS_JALR_HINT_P (ep
))
9300 if (mips_opts
.micromips
)
9302 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9303 ? "jalr" : "jalrs");
9304 if (MIPS_JALR_HINT_P (ep
)
9306 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9307 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9309 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9312 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9313 if (MIPS_JALR_HINT_P (ep
))
9314 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9318 * Generate a "lui" instruction.
9321 macro_build_lui (expressionS
*ep
, int regnum
)
9323 gas_assert (! mips_opts
.mips16
);
9325 if (ep
->X_op
!= O_constant
)
9327 gas_assert (ep
->X_op
== O_symbol
);
9328 /* _gp_disp is a special case, used from s_cpload.
9329 __gnu_local_gp is used if mips_no_shared. */
9330 gas_assert (mips_pic
== NO_PIC
9332 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9333 || (! mips_in_shared
9334 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9335 "__gnu_local_gp") == 0));
9338 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9341 /* Generate a sequence of instructions to do a load or store from a constant
9342 offset off of a base register (breg) into/from a target register (treg),
9343 using AT if necessary. */
9345 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9346 int treg
, int breg
, int dbl
)
9348 gas_assert (ep
->X_op
== O_constant
);
9350 /* Sign-extending 32-bit constants makes their handling easier. */
9352 normalize_constant_expr (ep
);
9354 /* Right now, this routine can only handle signed 32-bit constants. */
9355 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9356 as_warn (_("operand overflow"));
9358 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9360 /* Signed 16-bit offset will fit in the op. Easy! */
9361 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9365 /* 32-bit offset, need multiple instructions and AT, like:
9366 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9367 addu $tempreg,$tempreg,$breg
9368 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9369 to handle the complete offset. */
9370 macro_build_lui (ep
, AT
);
9371 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9372 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9375 as_bad (_("macro used $at after \".set noat\""));
9380 * Generates code to set the $at register to true (one)
9381 * if reg is less than the immediate expression.
9384 set_at (int reg
, int unsignedp
)
9386 if (imm_expr
.X_add_number
>= -0x8000
9387 && imm_expr
.X_add_number
< 0x8000)
9388 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9389 AT
, reg
, BFD_RELOC_LO16
);
9392 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9393 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9397 /* Count the leading zeroes by performing a binary chop. This is a
9398 bulky bit of source, but performance is a LOT better for the
9399 majority of values than a simple loop to count the bits:
9400 for (lcnt = 0; (lcnt < 32); lcnt++)
9401 if ((v) & (1 << (31 - lcnt)))
9403 However it is not code size friendly, and the gain will drop a bit
9404 on certain cached systems.
9406 #define COUNT_TOP_ZEROES(v) \
9407 (((v) & ~0xffff) == 0 \
9408 ? ((v) & ~0xff) == 0 \
9409 ? ((v) & ~0xf) == 0 \
9410 ? ((v) & ~0x3) == 0 \
9411 ? ((v) & ~0x1) == 0 \
9416 : ((v) & ~0x7) == 0 \
9419 : ((v) & ~0x3f) == 0 \
9420 ? ((v) & ~0x1f) == 0 \
9423 : ((v) & ~0x7f) == 0 \
9426 : ((v) & ~0xfff) == 0 \
9427 ? ((v) & ~0x3ff) == 0 \
9428 ? ((v) & ~0x1ff) == 0 \
9431 : ((v) & ~0x7ff) == 0 \
9434 : ((v) & ~0x3fff) == 0 \
9435 ? ((v) & ~0x1fff) == 0 \
9438 : ((v) & ~0x7fff) == 0 \
9441 : ((v) & ~0xffffff) == 0 \
9442 ? ((v) & ~0xfffff) == 0 \
9443 ? ((v) & ~0x3ffff) == 0 \
9444 ? ((v) & ~0x1ffff) == 0 \
9447 : ((v) & ~0x7ffff) == 0 \
9450 : ((v) & ~0x3fffff) == 0 \
9451 ? ((v) & ~0x1fffff) == 0 \
9454 : ((v) & ~0x7fffff) == 0 \
9457 : ((v) & ~0xfffffff) == 0 \
9458 ? ((v) & ~0x3ffffff) == 0 \
9459 ? ((v) & ~0x1ffffff) == 0 \
9462 : ((v) & ~0x7ffffff) == 0 \
9465 : ((v) & ~0x3fffffff) == 0 \
9466 ? ((v) & ~0x1fffffff) == 0 \
9469 : ((v) & ~0x7fffffff) == 0 \
9474 * This routine generates the least number of instructions necessary to load
9475 * an absolute expression value into a register.
9478 load_register (int reg
, expressionS
*ep
, int dbl
)
9481 expressionS hi32
, lo32
;
9483 if (ep
->X_op
!= O_big
)
9485 gas_assert (ep
->X_op
== O_constant
);
9487 /* Sign-extending 32-bit constants makes their handling easier. */
9489 normalize_constant_expr (ep
);
9491 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9493 /* We can handle 16 bit signed values with an addiu to
9494 $zero. No need to ever use daddiu here, since $zero and
9495 the result are always correct in 32 bit mode. */
9496 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9499 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9501 /* We can handle 16 bit unsigned values with an ori to
9503 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9506 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9508 /* 32 bit values require an lui. */
9509 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9510 if ((ep
->X_add_number
& 0xffff) != 0)
9511 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9516 /* The value is larger than 32 bits. */
9518 if (!dbl
|| GPR_SIZE
== 32)
9522 sprintf_vma (value
, ep
->X_add_number
);
9523 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9524 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9528 if (ep
->X_op
!= O_big
)
9531 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9532 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9533 hi32
.X_add_number
&= 0xffffffff;
9535 lo32
.X_add_number
&= 0xffffffff;
9539 gas_assert (ep
->X_add_number
> 2);
9540 if (ep
->X_add_number
== 3)
9541 generic_bignum
[3] = 0;
9542 else if (ep
->X_add_number
> 4)
9543 as_bad (_("number larger than 64 bits"));
9544 lo32
.X_op
= O_constant
;
9545 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9546 hi32
.X_op
= O_constant
;
9547 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9550 if (hi32
.X_add_number
== 0)
9555 unsigned long hi
, lo
;
9557 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9559 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9561 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9564 if (lo32
.X_add_number
& 0x80000000)
9566 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9567 if (lo32
.X_add_number
& 0xffff)
9568 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9573 /* Check for 16bit shifted constant. We know that hi32 is
9574 non-zero, so start the mask on the first bit of the hi32
9579 unsigned long himask
, lomask
;
9583 himask
= 0xffff >> (32 - shift
);
9584 lomask
= (0xffff << shift
) & 0xffffffff;
9588 himask
= 0xffff << (shift
- 32);
9591 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9592 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9596 tmp
.X_op
= O_constant
;
9598 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9599 | (lo32
.X_add_number
>> shift
));
9601 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9602 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9603 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9604 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9609 while (shift
<= (64 - 16));
9611 /* Find the bit number of the lowest one bit, and store the
9612 shifted value in hi/lo. */
9613 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9614 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9618 while ((lo
& 1) == 0)
9623 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9629 while ((hi
& 1) == 0)
9638 /* Optimize if the shifted value is a (power of 2) - 1. */
9639 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9640 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9642 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9647 /* This instruction will set the register to be all
9649 tmp
.X_op
= O_constant
;
9650 tmp
.X_add_number
= (offsetT
) -1;
9651 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9655 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9656 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9658 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9659 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9664 /* Sign extend hi32 before calling load_register, because we can
9665 generally get better code when we load a sign extended value. */
9666 if ((hi32
.X_add_number
& 0x80000000) != 0)
9667 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9668 load_register (reg
, &hi32
, 0);
9671 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9675 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9683 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9685 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9686 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9692 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9696 mid16
.X_add_number
>>= 16;
9697 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9698 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9701 if ((lo32
.X_add_number
& 0xffff) != 0)
9702 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9706 load_delay_nop (void)
9708 if (!gpr_interlocks
)
9709 macro_build (NULL
, "nop", "");
9712 /* Load an address into a register. */
9715 load_address (int reg
, expressionS
*ep
, int *used_at
)
9717 if (ep
->X_op
!= O_constant
9718 && ep
->X_op
!= O_symbol
)
9720 as_bad (_("expression too complex"));
9721 ep
->X_op
= O_constant
;
9724 if (ep
->X_op
== O_constant
)
9726 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9730 if (mips_pic
== NO_PIC
)
9732 /* If this is a reference to a GP relative symbol, we want
9733 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9735 lui $reg,<sym> (BFD_RELOC_HI16_S)
9736 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9737 If we have an addend, we always use the latter form.
9739 With 64bit address space and a usable $at we want
9740 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9741 lui $at,<sym> (BFD_RELOC_HI16_S)
9742 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9743 daddiu $at,<sym> (BFD_RELOC_LO16)
9747 If $at is already in use, we use a path which is suboptimal
9748 on superscalar processors.
9749 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9750 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9752 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9754 daddiu $reg,<sym> (BFD_RELOC_LO16)
9756 For GP relative symbols in 64bit address space we can use
9757 the same sequence as in 32bit address space. */
9758 if (HAVE_64BIT_SYMBOLS
)
9760 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9761 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9763 relax_start (ep
->X_add_symbol
);
9764 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9765 mips_gp_register
, BFD_RELOC_GPREL16
);
9769 if (*used_at
== 0 && mips_opts
.at
)
9771 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9772 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9773 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9774 BFD_RELOC_MIPS_HIGHER
);
9775 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9776 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9777 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9782 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9783 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9784 BFD_RELOC_MIPS_HIGHER
);
9785 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9786 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9787 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9788 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9791 if (mips_relax
.sequence
)
9796 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9797 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9799 relax_start (ep
->X_add_symbol
);
9800 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9801 mips_gp_register
, BFD_RELOC_GPREL16
);
9804 macro_build_lui (ep
, reg
);
9805 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9806 reg
, reg
, BFD_RELOC_LO16
);
9807 if (mips_relax
.sequence
)
9811 else if (!mips_big_got
)
9815 /* If this is a reference to an external symbol, we want
9816 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9818 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9820 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9821 If there is a constant, it must be added in after.
9823 If we have NewABI, we want
9824 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9825 unless we're referencing a global symbol with a non-zero
9826 offset, in which case cst must be added separately. */
9829 if (ep
->X_add_number
)
9831 ex
.X_add_number
= ep
->X_add_number
;
9832 ep
->X_add_number
= 0;
9833 relax_start (ep
->X_add_symbol
);
9834 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9835 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9836 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9837 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9838 ex
.X_op
= O_constant
;
9839 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9840 reg
, reg
, BFD_RELOC_LO16
);
9841 ep
->X_add_number
= ex
.X_add_number
;
9844 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9845 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9846 if (mips_relax
.sequence
)
9851 ex
.X_add_number
= ep
->X_add_number
;
9852 ep
->X_add_number
= 0;
9853 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9854 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9856 relax_start (ep
->X_add_symbol
);
9858 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9862 if (ex
.X_add_number
!= 0)
9864 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9865 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9866 ex
.X_op
= O_constant
;
9867 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9868 reg
, reg
, BFD_RELOC_LO16
);
9872 else if (mips_big_got
)
9876 /* This is the large GOT case. If this is a reference to an
9877 external symbol, we want
9878 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9880 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9882 Otherwise, for a reference to a local symbol in old ABI, we want
9883 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9885 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9886 If there is a constant, it must be added in after.
9888 In the NewABI, for local symbols, with or without offsets, we want:
9889 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9890 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9894 ex
.X_add_number
= ep
->X_add_number
;
9895 ep
->X_add_number
= 0;
9896 relax_start (ep
->X_add_symbol
);
9897 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9898 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9899 reg
, reg
, mips_gp_register
);
9900 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9901 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9902 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9903 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9904 else if (ex
.X_add_number
)
9906 ex
.X_op
= O_constant
;
9907 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9911 ep
->X_add_number
= ex
.X_add_number
;
9913 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9914 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9915 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9916 BFD_RELOC_MIPS_GOT_OFST
);
9921 ex
.X_add_number
= ep
->X_add_number
;
9922 ep
->X_add_number
= 0;
9923 relax_start (ep
->X_add_symbol
);
9924 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9926 reg
, reg
, mips_gp_register
);
9927 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9928 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9930 if (reg_needs_delay (mips_gp_register
))
9932 /* We need a nop before loading from $gp. This special
9933 check is required because the lui which starts the main
9934 instruction stream does not refer to $gp, and so will not
9935 insert the nop which may be required. */
9936 macro_build (NULL
, "nop", "");
9938 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9939 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9941 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9945 if (ex
.X_add_number
!= 0)
9947 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9948 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9949 ex
.X_op
= O_constant
;
9950 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9958 if (!mips_opts
.at
&& *used_at
== 1)
9959 as_bad (_("macro used $at after \".set noat\""));
9962 /* Move the contents of register SOURCE into register DEST. */
9965 move_register (int dest
, int source
)
9967 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9968 instruction specifically requires a 32-bit one. */
9969 if (mips_opts
.micromips
9970 && !mips_opts
.insn32
9971 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9972 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9974 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9977 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9978 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9979 The two alternatives are:
9981 Global symbol Local symbol
9982 ------------- ------------
9983 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9985 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9987 load_got_offset emits the first instruction and add_got_offset
9988 emits the second for a 16-bit offset or add_got_offset_hilo emits
9989 a sequence to add a 32-bit offset using a scratch register. */
9992 load_got_offset (int dest
, expressionS
*local
)
9997 global
.X_add_number
= 0;
9999 relax_start (local
->X_add_symbol
);
10000 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
10001 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10003 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
10004 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10009 add_got_offset (int dest
, expressionS
*local
)
10011 expressionS global
;
10013 global
.X_op
= O_constant
;
10014 global
.X_op_symbol
= NULL
;
10015 global
.X_add_symbol
= NULL
;
10016 global
.X_add_number
= local
->X_add_number
;
10018 relax_start (local
->X_add_symbol
);
10019 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
10020 dest
, dest
, BFD_RELOC_LO16
);
10022 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
10027 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
10029 expressionS global
;
10030 int hold_mips_optimize
;
10032 global
.X_op
= O_constant
;
10033 global
.X_op_symbol
= NULL
;
10034 global
.X_add_symbol
= NULL
;
10035 global
.X_add_number
= local
->X_add_number
;
10037 relax_start (local
->X_add_symbol
);
10038 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10040 /* Set mips_optimize around the lui instruction to avoid
10041 inserting an unnecessary nop after the lw. */
10042 hold_mips_optimize
= mips_optimize
;
10044 macro_build_lui (&global
, tmp
);
10045 mips_optimize
= hold_mips_optimize
;
10046 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10049 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10052 /* Emit a sequence of instructions to emulate a branch likely operation.
10053 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10054 is its complementing branch with the original condition negated.
10055 CALL is set if the original branch specified the link operation.
10056 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10058 Code like this is produced in the noreorder mode:
10063 delay slot (executed only if branch taken)
10066 or, if CALL is set:
10071 delay slot (executed only if branch taken)
10074 In the reorder mode the delay slot would be filled with a nop anyway,
10075 so code produced is simply:
10080 This function is used when producing code for the microMIPS ASE that
10081 does not implement branch likely instructions in hardware. */
10084 macro_build_branch_likely (const char *br
, const char *brneg
,
10085 int call
, expressionS
*ep
, const char *fmt
,
10086 unsigned int sreg
, unsigned int treg
)
10088 int noreorder
= mips_opts
.noreorder
;
10091 gas_assert (mips_opts
.micromips
);
10092 start_noreorder ();
10095 micromips_label_expr (&expr1
);
10096 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10097 macro_build (NULL
, "nop", "");
10098 macro_build (ep
, call
? "bal" : "b", "p");
10100 /* Set to true so that append_insn adds a label. */
10101 emit_branch_likely_macro
= TRUE
;
10105 macro_build (ep
, br
, fmt
, sreg
, treg
);
10106 macro_build (NULL
, "nop", "");
10111 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10112 the condition code tested. EP specifies the branch target. */
10115 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10117 const int call
= 0;
10142 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10145 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10146 the register tested. EP specifies the branch target. */
10149 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10151 const char *brneg
= NULL
;
10161 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10165 gas_assert (mips_opts
.micromips
);
10166 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10174 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10181 br
= mips_opts
.micromips
? "blez" : "blezl";
10188 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10192 gas_assert (mips_opts
.micromips
);
10193 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10200 if (mips_opts
.micromips
&& brneg
)
10201 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10203 macro_build (ep
, br
, "s,p", sreg
);
10206 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10207 TREG as the registers tested. EP specifies the branch target. */
10210 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10211 unsigned int sreg
, unsigned int treg
)
10213 const char *brneg
= NULL
;
10214 const int call
= 0;
10225 br
= mips_opts
.micromips
? "beq" : "beql";
10234 br
= mips_opts
.micromips
? "bne" : "bnel";
10240 if (mips_opts
.micromips
&& brneg
)
10241 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10243 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10246 /* Return the high part that should be loaded in order to make the low
10247 part of VALUE accessible using an offset of OFFBITS bits. */
10250 offset_high_part (offsetT value
, unsigned int offbits
)
10257 bias
= 1 << (offbits
- 1);
10258 low_mask
= bias
* 2 - 1;
10259 return (value
+ bias
) & ~low_mask
;
10262 /* Return true if the value stored in offset_expr and offset_reloc
10263 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10264 amount that the caller wants to add without inducing overflow
10265 and ALIGN is the known alignment of the value in bytes. */
10268 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10272 /* Accept any relocation operator if overflow isn't a concern. */
10273 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10276 /* These relocations are guaranteed not to overflow in correct links. */
10277 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10278 || gprel16_reloc_p (*offset_reloc
))
10281 if (offset_expr
.X_op
== O_constant
10282 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10283 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10290 * This routine implements the seemingly endless macro or synthesized
10291 * instructions and addressing modes in the mips assembly language. Many
10292 * of these macros are simple and are similar to each other. These could
10293 * probably be handled by some kind of table or grammar approach instead of
10294 * this verbose method. Others are not simple macros but are more like
10295 * optimizing code generation.
10296 * One interesting optimization is when several store macros appear
10297 * consecutively that would load AT with the upper half of the same address.
10298 * The ensuing load upper instructions are omitted. This implies some kind
10299 * of global optimization. We currently only optimize within a single macro.
10300 * For many of the load and store macros if the address is specified as a
10301 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10302 * first load register 'at' with zero and use it as the base register. The
10303 * mips assembler simply uses register $zero. Just one tiny optimization
10307 macro (struct mips_cl_insn
*ip
, char *str
)
10309 const struct mips_operand_array
*operands
;
10310 unsigned int breg
, i
;
10311 unsigned int tempreg
;
10314 expressionS label_expr
;
10329 int ll_sc_paired
= 0;
10330 bfd_boolean large_offset
;
10332 int hold_mips_optimize
;
10333 unsigned int align
;
10334 unsigned int op
[MAX_OPERANDS
];
10336 gas_assert (! mips_opts
.mips16
);
10338 operands
= insn_operands (ip
);
10339 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10340 if (operands
->operand
[i
])
10341 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10345 mask
= ip
->insn_mo
->mask
;
10347 label_expr
.X_op
= O_constant
;
10348 label_expr
.X_op_symbol
= NULL
;
10349 label_expr
.X_add_symbol
= NULL
;
10350 label_expr
.X_add_number
= 0;
10352 expr1
.X_op
= O_constant
;
10353 expr1
.X_op_symbol
= NULL
;
10354 expr1
.X_add_symbol
= NULL
;
10355 expr1
.X_add_number
= 1;
10362 /* Fall through. */
10370 start_noreorder ();
10372 if (mips_opts
.micromips
)
10373 micromips_label_expr (&label_expr
);
10375 label_expr
.X_add_number
= 8;
10376 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10377 if (op
[0] == op
[1])
10378 macro_build (NULL
, "nop", "");
10380 move_register (op
[0], op
[1]);
10381 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10382 if (mips_opts
.micromips
)
10383 micromips_add_label ();
10391 if (ISA_IS_R6 (mips_opts
.isa
))
10403 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10405 if (imm_expr
.X_add_number
>= -0x200
10406 && imm_expr
.X_add_number
< 0x200
10407 && !ISA_IS_R6 (mips_opts
.isa
))
10409 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10410 (int) imm_expr
.X_add_number
);
10419 if (imm_expr
.X_add_number
>= -0x8000
10420 && imm_expr
.X_add_number
< 0x8000)
10422 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10427 load_register (AT
, &imm_expr
, dbl
);
10428 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10447 if (imm_expr
.X_add_number
>= 0
10448 && imm_expr
.X_add_number
< 0x10000)
10450 if (mask
!= M_NOR_I
)
10451 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10454 macro_build (&imm_expr
, "ori", "t,r,i",
10455 op
[0], op
[1], BFD_RELOC_LO16
);
10456 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10462 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10463 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10467 switch (imm_expr
.X_add_number
)
10470 macro_build (NULL
, "nop", "");
10473 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10477 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10478 (int) imm_expr
.X_add_number
);
10481 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10482 (unsigned long) imm_expr
.X_add_number
);
10491 gas_assert (mips_opts
.micromips
);
10492 macro_build_branch_ccl (mask
, &offset_expr
,
10493 EXTRACT_OPERAND (1, BCC
, *ip
));
10500 if (imm_expr
.X_add_number
== 0)
10506 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10508 /* Fall through. */
10511 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10516 /* Fall through. */
10519 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10520 else if (op
[0] == 0)
10521 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10525 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10526 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10527 &offset_expr
, AT
, ZERO
);
10537 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10542 /* Fall through. */
10544 /* Check for > max integer. */
10545 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10548 /* Result is always false. */
10550 macro_build (NULL
, "nop", "");
10552 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10555 ++imm_expr
.X_add_number
;
10556 /* Fall through. */
10559 if (mask
== M_BGEL_I
)
10561 if (imm_expr
.X_add_number
== 0)
10563 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10564 &offset_expr
, op
[0]);
10567 if (imm_expr
.X_add_number
== 1)
10569 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10570 &offset_expr
, op
[0]);
10573 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10576 /* Result is always true. */
10577 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10578 macro_build (&offset_expr
, "b", "p");
10583 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10584 &offset_expr
, AT
, ZERO
);
10589 /* Fall through. */
10593 else if (op
[0] == 0)
10594 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10595 &offset_expr
, ZERO
, op
[1]);
10599 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10600 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10601 &offset_expr
, AT
, ZERO
);
10607 /* Fall through. */
10611 && imm_expr
.X_add_number
== -1))
10613 ++imm_expr
.X_add_number
;
10614 /* Fall through. */
10617 if (mask
== M_BGEUL_I
)
10619 if (imm_expr
.X_add_number
== 0)
10621 else if (imm_expr
.X_add_number
== 1)
10622 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10623 &offset_expr
, op
[0], ZERO
);
10628 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10629 &offset_expr
, AT
, ZERO
);
10635 /* Fall through. */
10638 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10639 else if (op
[0] == 0)
10640 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10644 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10645 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10646 &offset_expr
, AT
, ZERO
);
10652 /* Fall through. */
10655 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10656 &offset_expr
, op
[0], ZERO
);
10657 else if (op
[0] == 0)
10662 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10663 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10664 &offset_expr
, AT
, ZERO
);
10670 /* Fall through. */
10673 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10674 else if (op
[0] == 0)
10675 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10679 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10680 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10681 &offset_expr
, AT
, ZERO
);
10687 /* Fall through. */
10689 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10691 ++imm_expr
.X_add_number
;
10692 /* Fall through. */
10695 if (mask
== M_BLTL_I
)
10697 if (imm_expr
.X_add_number
== 0)
10698 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10699 else if (imm_expr
.X_add_number
== 1)
10700 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10705 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10706 &offset_expr
, AT
, ZERO
);
10712 /* Fall through. */
10715 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10716 &offset_expr
, op
[0], ZERO
);
10717 else if (op
[0] == 0)
10722 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10723 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10724 &offset_expr
, AT
, ZERO
);
10730 /* Fall through. */
10734 && imm_expr
.X_add_number
== -1))
10736 ++imm_expr
.X_add_number
;
10737 /* Fall through. */
10740 if (mask
== M_BLTUL_I
)
10742 if (imm_expr
.X_add_number
== 0)
10744 else if (imm_expr
.X_add_number
== 1)
10745 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10746 &offset_expr
, op
[0], ZERO
);
10751 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10752 &offset_expr
, AT
, ZERO
);
10758 /* Fall through. */
10761 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10762 else if (op
[0] == 0)
10763 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10767 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10768 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10769 &offset_expr
, AT
, ZERO
);
10775 /* Fall through. */
10779 else if (op
[0] == 0)
10780 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10781 &offset_expr
, ZERO
, op
[1]);
10785 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10786 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10787 &offset_expr
, AT
, ZERO
);
10793 /* Fall through. */
10799 /* Fall through. */
10805 as_warn (_("divide by zero"));
10807 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10809 macro_build (NULL
, "break", BRK_FMT
, 7);
10813 start_noreorder ();
10816 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10817 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10821 if (mips_opts
.micromips
)
10822 micromips_label_expr (&label_expr
);
10824 label_expr
.X_add_number
= 8;
10825 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10826 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10827 macro_build (NULL
, "break", BRK_FMT
, 7);
10828 if (mips_opts
.micromips
)
10829 micromips_add_label ();
10831 expr1
.X_add_number
= -1;
10833 load_register (AT
, &expr1
, dbl
);
10834 if (mips_opts
.micromips
)
10835 micromips_label_expr (&label_expr
);
10837 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10838 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10841 expr1
.X_add_number
= 1;
10842 load_register (AT
, &expr1
, dbl
);
10843 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10847 expr1
.X_add_number
= 0x80000000;
10848 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10852 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10853 /* We want to close the noreorder block as soon as possible, so
10854 that later insns are available for delay slot filling. */
10859 if (mips_opts
.micromips
)
10860 micromips_label_expr (&label_expr
);
10862 label_expr
.X_add_number
= 8;
10863 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10864 macro_build (NULL
, "nop", "");
10866 /* We want to close the noreorder block as soon as possible, so
10867 that later insns are available for delay slot filling. */
10870 macro_build (NULL
, "break", BRK_FMT
, 6);
10872 if (mips_opts
.micromips
)
10873 micromips_add_label ();
10874 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10913 if (imm_expr
.X_add_number
== 0)
10915 as_warn (_("divide by zero"));
10917 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10919 macro_build (NULL
, "break", BRK_FMT
, 7);
10922 if (imm_expr
.X_add_number
== 1)
10924 if (strcmp (s2
, "mflo") == 0)
10925 move_register (op
[0], op
[1]);
10927 move_register (op
[0], ZERO
);
10930 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10932 if (strcmp (s2
, "mflo") == 0)
10933 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10935 move_register (op
[0], ZERO
);
10940 load_register (AT
, &imm_expr
, dbl
);
10941 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10942 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10961 start_noreorder ();
10964 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10965 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10966 /* We want to close the noreorder block as soon as possible, so
10967 that later insns are available for delay slot filling. */
10972 if (mips_opts
.micromips
)
10973 micromips_label_expr (&label_expr
);
10975 label_expr
.X_add_number
= 8;
10976 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10977 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10979 /* We want to close the noreorder block as soon as possible, so
10980 that later insns are available for delay slot filling. */
10982 macro_build (NULL
, "break", BRK_FMT
, 7);
10983 if (mips_opts
.micromips
)
10984 micromips_add_label ();
10986 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10991 /* Fall through. */
10997 /* Fall through. */
11000 /* Load the address of a symbol into a register. If breg is not
11001 zero, we then add a base register to it. */
11004 if (dbl
&& GPR_SIZE
== 32)
11005 as_warn (_("dla used to load 32-bit register; recommend using la "
11008 if (!dbl
&& HAVE_64BIT_OBJECTS
)
11009 as_warn (_("la used to load 64-bit address; recommend using dla "
11012 if (small_offset_p (0, align
, 16))
11014 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
11015 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11019 if (mips_opts
.at
&& (op
[0] == breg
))
11027 if (offset_expr
.X_op
!= O_symbol
11028 && offset_expr
.X_op
!= O_constant
)
11030 as_bad (_("expression too complex"));
11031 offset_expr
.X_op
= O_constant
;
11034 if (offset_expr
.X_op
== O_constant
)
11035 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
11036 else if (mips_pic
== NO_PIC
)
11038 /* If this is a reference to a GP relative symbol, we want
11039 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11041 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11042 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11043 If we have a constant, we need two instructions anyhow,
11044 so we may as well always use the latter form.
11046 With 64bit address space and a usable $at we want
11047 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11048 lui $at,<sym> (BFD_RELOC_HI16_S)
11049 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11050 daddiu $at,<sym> (BFD_RELOC_LO16)
11052 daddu $tempreg,$tempreg,$at
11054 If $at is already in use, we use a path which is suboptimal
11055 on superscalar processors.
11056 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11057 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11059 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11061 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11063 For GP relative symbols in 64bit address space we can use
11064 the same sequence as in 32bit address space. */
11065 if (HAVE_64BIT_SYMBOLS
)
11067 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11068 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11070 relax_start (offset_expr
.X_add_symbol
);
11071 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11072 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11076 if (used_at
== 0 && mips_opts
.at
)
11078 macro_build (&offset_expr
, "lui", LUI_FMT
,
11079 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11080 macro_build (&offset_expr
, "lui", LUI_FMT
,
11081 AT
, BFD_RELOC_HI16_S
);
11082 macro_build (&offset_expr
, "daddiu", "t,r,j",
11083 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11084 macro_build (&offset_expr
, "daddiu", "t,r,j",
11085 AT
, AT
, BFD_RELOC_LO16
);
11086 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11087 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11092 macro_build (&offset_expr
, "lui", LUI_FMT
,
11093 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11094 macro_build (&offset_expr
, "daddiu", "t,r,j",
11095 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11096 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11097 macro_build (&offset_expr
, "daddiu", "t,r,j",
11098 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11099 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11100 macro_build (&offset_expr
, "daddiu", "t,r,j",
11101 tempreg
, tempreg
, BFD_RELOC_LO16
);
11104 if (mips_relax
.sequence
)
11109 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11110 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11112 relax_start (offset_expr
.X_add_symbol
);
11113 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11114 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11117 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11118 as_bad (_("offset too large"));
11119 macro_build_lui (&offset_expr
, tempreg
);
11120 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11121 tempreg
, tempreg
, BFD_RELOC_LO16
);
11122 if (mips_relax
.sequence
)
11126 else if (!mips_big_got
&& !HAVE_NEWABI
)
11128 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11130 /* If this is a reference to an external symbol, and there
11131 is no constant, we want
11132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11133 or for lca or if tempreg is PIC_CALL_REG
11134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11135 For a local symbol, we want
11136 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11138 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11140 If we have a small constant, and this is a reference to
11141 an external symbol, we want
11142 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11144 addiu $tempreg,$tempreg,<constant>
11145 For a local symbol, we want the same instruction
11146 sequence, but we output a BFD_RELOC_LO16 reloc on the
11149 If we have a large constant, and this is a reference to
11150 an external symbol, we want
11151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11152 lui $at,<hiconstant>
11153 addiu $at,$at,<loconstant>
11154 addu $tempreg,$tempreg,$at
11155 For a local symbol, we want the same instruction
11156 sequence, but we output a BFD_RELOC_LO16 reloc on the
11160 if (offset_expr
.X_add_number
== 0)
11162 if (mips_pic
== SVR4_PIC
11164 && (call
|| tempreg
== PIC_CALL_REG
))
11165 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11167 relax_start (offset_expr
.X_add_symbol
);
11168 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11169 lw_reloc_type
, mips_gp_register
);
11172 /* We're going to put in an addu instruction using
11173 tempreg, so we may as well insert the nop right
11178 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11179 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11181 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11182 tempreg
, tempreg
, BFD_RELOC_LO16
);
11184 /* FIXME: If breg == 0, and the next instruction uses
11185 $tempreg, then if this variant case is used an extra
11186 nop will be generated. */
11188 else if (offset_expr
.X_add_number
>= -0x8000
11189 && offset_expr
.X_add_number
< 0x8000)
11191 load_got_offset (tempreg
, &offset_expr
);
11193 add_got_offset (tempreg
, &offset_expr
);
11197 expr1
.X_add_number
= offset_expr
.X_add_number
;
11198 offset_expr
.X_add_number
=
11199 SEXT_16BIT (offset_expr
.X_add_number
);
11200 load_got_offset (tempreg
, &offset_expr
);
11201 offset_expr
.X_add_number
= expr1
.X_add_number
;
11202 /* If we are going to add in a base register, and the
11203 target register and the base register are the same,
11204 then we are using AT as a temporary register. Since
11205 we want to load the constant into AT, we add our
11206 current AT (from the global offset table) and the
11207 register into the register now, and pretend we were
11208 not using a base register. */
11212 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11217 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11221 else if (!mips_big_got
&& HAVE_NEWABI
)
11223 int add_breg_early
= 0;
11225 /* If this is a reference to an external, and there is no
11226 constant, or local symbol (*), with or without a
11228 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11229 or for lca or if tempreg is PIC_CALL_REG
11230 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11232 If we have a small constant, and this is a reference to
11233 an external symbol, we want
11234 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11235 addiu $tempreg,$tempreg,<constant>
11237 If we have a large constant, and this is a reference to
11238 an external symbol, we want
11239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11240 lui $at,<hiconstant>
11241 addiu $at,$at,<loconstant>
11242 addu $tempreg,$tempreg,$at
11244 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11245 local symbols, even though it introduces an additional
11248 if (offset_expr
.X_add_number
)
11250 expr1
.X_add_number
= offset_expr
.X_add_number
;
11251 offset_expr
.X_add_number
= 0;
11253 relax_start (offset_expr
.X_add_symbol
);
11254 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11255 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11257 if (expr1
.X_add_number
>= -0x8000
11258 && expr1
.X_add_number
< 0x8000)
11260 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11261 tempreg
, tempreg
, BFD_RELOC_LO16
);
11263 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11267 /* If we are going to add in a base register, and the
11268 target register and the base register are the same,
11269 then we are using AT as a temporary register. Since
11270 we want to load the constant into AT, we add our
11271 current AT (from the global offset table) and the
11272 register into the register now, and pretend we were
11273 not using a base register. */
11278 gas_assert (tempreg
== AT
);
11279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11282 add_breg_early
= 1;
11285 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11292 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11295 offset_expr
.X_add_number
= expr1
.X_add_number
;
11297 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11298 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11299 if (add_breg_early
)
11301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11302 op
[0], tempreg
, breg
);
11308 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11310 relax_start (offset_expr
.X_add_symbol
);
11311 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11312 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11314 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11315 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11320 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11321 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11324 else if (mips_big_got
&& !HAVE_NEWABI
)
11327 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11328 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11329 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11331 /* This is the large GOT case. If this is a reference to an
11332 external symbol, and there is no constant, we want
11333 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11334 addu $tempreg,$tempreg,$gp
11335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11336 or for lca or if tempreg is PIC_CALL_REG
11337 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11338 addu $tempreg,$tempreg,$gp
11339 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11340 For a local symbol, we want
11341 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11343 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11345 If we have a small constant, and this is a reference to
11346 an external symbol, we want
11347 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11348 addu $tempreg,$tempreg,$gp
11349 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11351 addiu $tempreg,$tempreg,<constant>
11352 For a local symbol, we want
11353 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11355 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11357 If we have a large constant, and this is a reference to
11358 an external symbol, we want
11359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11360 addu $tempreg,$tempreg,$gp
11361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11362 lui $at,<hiconstant>
11363 addiu $at,$at,<loconstant>
11364 addu $tempreg,$tempreg,$at
11365 For a local symbol, we want
11366 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11367 lui $at,<hiconstant>
11368 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11369 addu $tempreg,$tempreg,$at
11372 expr1
.X_add_number
= offset_expr
.X_add_number
;
11373 offset_expr
.X_add_number
= 0;
11374 relax_start (offset_expr
.X_add_symbol
);
11375 gpdelay
= reg_needs_delay (mips_gp_register
);
11376 if (expr1
.X_add_number
== 0 && breg
== 0
11377 && (call
|| tempreg
== PIC_CALL_REG
))
11379 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11380 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11382 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11383 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11384 tempreg
, tempreg
, mips_gp_register
);
11385 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11386 tempreg
, lw_reloc_type
, tempreg
);
11387 if (expr1
.X_add_number
== 0)
11391 /* We're going to put in an addu instruction using
11392 tempreg, so we may as well insert the nop right
11397 else if (expr1
.X_add_number
>= -0x8000
11398 && expr1
.X_add_number
< 0x8000)
11401 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11402 tempreg
, tempreg
, BFD_RELOC_LO16
);
11408 /* If we are going to add in a base register, and the
11409 target register and the base register are the same,
11410 then we are using AT as a temporary register. Since
11411 we want to load the constant into AT, we add our
11412 current AT (from the global offset table) and the
11413 register into the register now, and pretend we were
11414 not using a base register. */
11419 gas_assert (tempreg
== AT
);
11421 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11426 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11431 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11436 /* This is needed because this instruction uses $gp, but
11437 the first instruction on the main stream does not. */
11438 macro_build (NULL
, "nop", "");
11441 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11442 local_reloc_type
, mips_gp_register
);
11443 if (expr1
.X_add_number
>= -0x8000
11444 && expr1
.X_add_number
< 0x8000)
11447 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11448 tempreg
, tempreg
, BFD_RELOC_LO16
);
11449 /* FIXME: If add_number is 0, and there was no base
11450 register, the external symbol case ended with a load,
11451 so if the symbol turns out to not be external, and
11452 the next instruction uses tempreg, an unnecessary nop
11453 will be inserted. */
11459 /* We must add in the base register now, as in the
11460 external symbol case. */
11461 gas_assert (tempreg
== AT
);
11463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11466 /* We set breg to 0 because we have arranged to add
11467 it in in both cases. */
11471 macro_build_lui (&expr1
, AT
);
11472 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11473 AT
, AT
, BFD_RELOC_LO16
);
11474 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11475 tempreg
, tempreg
, AT
);
11480 else if (mips_big_got
&& HAVE_NEWABI
)
11482 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11483 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11484 int add_breg_early
= 0;
11486 /* This is the large GOT case. If this is a reference to an
11487 external symbol, and there is no constant, we want
11488 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11489 add $tempreg,$tempreg,$gp
11490 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11491 or for lca or if tempreg is PIC_CALL_REG
11492 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11493 add $tempreg,$tempreg,$gp
11494 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11496 If we have a small constant, and this is a reference to
11497 an external symbol, we want
11498 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11499 add $tempreg,$tempreg,$gp
11500 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11501 addi $tempreg,$tempreg,<constant>
11503 If we have a large constant, and this is a reference to
11504 an external symbol, we want
11505 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11506 addu $tempreg,$tempreg,$gp
11507 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11508 lui $at,<hiconstant>
11509 addi $at,$at,<loconstant>
11510 add $tempreg,$tempreg,$at
11512 If we have NewABI, and we know it's a local symbol, we want
11513 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11514 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11515 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11517 relax_start (offset_expr
.X_add_symbol
);
11519 expr1
.X_add_number
= offset_expr
.X_add_number
;
11520 offset_expr
.X_add_number
= 0;
11522 if (expr1
.X_add_number
== 0 && breg
== 0
11523 && (call
|| tempreg
== PIC_CALL_REG
))
11525 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11526 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11528 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11529 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11530 tempreg
, tempreg
, mips_gp_register
);
11531 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11532 tempreg
, lw_reloc_type
, tempreg
);
11534 if (expr1
.X_add_number
== 0)
11536 else if (expr1
.X_add_number
>= -0x8000
11537 && expr1
.X_add_number
< 0x8000)
11539 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11540 tempreg
, tempreg
, BFD_RELOC_LO16
);
11542 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11546 /* If we are going to add in a base register, and the
11547 target register and the base register are the same,
11548 then we are using AT as a temporary register. Since
11549 we want to load the constant into AT, we add our
11550 current AT (from the global offset table) and the
11551 register into the register now, and pretend we were
11552 not using a base register. */
11557 gas_assert (tempreg
== AT
);
11558 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11561 add_breg_early
= 1;
11564 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11565 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11570 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11573 offset_expr
.X_add_number
= expr1
.X_add_number
;
11574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11575 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11576 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11577 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11578 if (add_breg_early
)
11580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11581 op
[0], tempreg
, breg
);
11591 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11595 gas_assert (!mips_opts
.micromips
);
11596 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11600 gas_assert (!mips_opts
.micromips
);
11601 macro_build (NULL
, "c2", "C", 0x02);
11605 gas_assert (!mips_opts
.micromips
);
11606 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11610 gas_assert (!mips_opts
.micromips
);
11611 macro_build (NULL
, "c2", "C", 3);
11615 gas_assert (!mips_opts
.micromips
);
11616 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11620 /* The j instruction may not be used in PIC code, since it
11621 requires an absolute address. We convert it to a b
11623 if (mips_pic
== NO_PIC
)
11624 macro_build (&offset_expr
, "j", "a");
11626 macro_build (&offset_expr
, "b", "p");
11629 /* The jal instructions must be handled as macros because when
11630 generating PIC code they expand to multi-instruction
11631 sequences. Normally they are simple instructions. */
11635 /* Fall through. */
11637 gas_assert (mips_opts
.micromips
);
11638 if (mips_opts
.insn32
)
11640 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11648 /* Fall through. */
11651 if (mips_pic
== NO_PIC
)
11653 s
= jals
? "jalrs" : "jalr";
11654 if (mips_opts
.micromips
11655 && !mips_opts
.insn32
11657 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11658 macro_build (NULL
, s
, "mj", op
[1]);
11660 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11664 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11665 && mips_cprestore_offset
>= 0);
11667 if (op
[1] != PIC_CALL_REG
)
11668 as_warn (_("MIPS PIC call to register other than $25"));
11670 s
= ((mips_opts
.micromips
11671 && !mips_opts
.insn32
11672 && (!mips_opts
.noreorder
|| cprestore
))
11673 ? "jalrs" : "jalr");
11674 if (mips_opts
.micromips
11675 && !mips_opts
.insn32
11677 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11678 macro_build (NULL
, s
, "mj", op
[1]);
11680 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11681 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11683 if (mips_cprestore_offset
< 0)
11684 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11687 if (!mips_frame_reg_valid
)
11689 as_warn (_("no .frame pseudo-op used in PIC code"));
11690 /* Quiet this warning. */
11691 mips_frame_reg_valid
= 1;
11693 if (!mips_cprestore_valid
)
11695 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11696 /* Quiet this warning. */
11697 mips_cprestore_valid
= 1;
11699 if (mips_opts
.noreorder
)
11700 macro_build (NULL
, "nop", "");
11701 expr1
.X_add_number
= mips_cprestore_offset
;
11702 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11705 HAVE_64BIT_ADDRESSES
);
11713 gas_assert (mips_opts
.micromips
);
11714 if (mips_opts
.insn32
)
11716 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11720 /* Fall through. */
11722 if (mips_pic
== NO_PIC
)
11723 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11724 else if (mips_pic
== SVR4_PIC
)
11726 /* If this is a reference to an external symbol, and we are
11727 using a small GOT, we want
11728 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11732 lw $gp,cprestore($sp)
11733 The cprestore value is set using the .cprestore
11734 pseudo-op. If we are using a big GOT, we want
11735 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11737 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11741 lw $gp,cprestore($sp)
11742 If the symbol is not external, we want
11743 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11745 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11748 lw $gp,cprestore($sp)
11750 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11751 sequences above, minus nops, unless the symbol is local,
11752 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11758 relax_start (offset_expr
.X_add_symbol
);
11759 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11760 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11763 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11764 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11770 relax_start (offset_expr
.X_add_symbol
);
11771 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11772 BFD_RELOC_MIPS_CALL_HI16
);
11773 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11774 PIC_CALL_REG
, mips_gp_register
);
11775 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11776 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11779 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11780 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11782 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11783 PIC_CALL_REG
, PIC_CALL_REG
,
11784 BFD_RELOC_MIPS_GOT_OFST
);
11788 macro_build_jalr (&offset_expr
, 0);
11792 relax_start (offset_expr
.X_add_symbol
);
11795 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11796 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11805 gpdelay
= reg_needs_delay (mips_gp_register
);
11806 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11807 BFD_RELOC_MIPS_CALL_HI16
);
11808 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11809 PIC_CALL_REG
, mips_gp_register
);
11810 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11811 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11816 macro_build (NULL
, "nop", "");
11818 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11819 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11822 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11823 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11825 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11827 if (mips_cprestore_offset
< 0)
11828 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11831 if (!mips_frame_reg_valid
)
11833 as_warn (_("no .frame pseudo-op used in PIC code"));
11834 /* Quiet this warning. */
11835 mips_frame_reg_valid
= 1;
11837 if (!mips_cprestore_valid
)
11839 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11840 /* Quiet this warning. */
11841 mips_cprestore_valid
= 1;
11843 if (mips_opts
.noreorder
)
11844 macro_build (NULL
, "nop", "");
11845 expr1
.X_add_number
= mips_cprestore_offset
;
11846 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11849 HAVE_64BIT_ADDRESSES
);
11853 else if (mips_pic
== VXWORKS_PIC
)
11854 as_bad (_("non-PIC jump used in PIC library"));
11961 gas_assert (!mips_opts
.micromips
);
11964 /* Itbl support may require additional care here. */
11970 /* Itbl support may require additional care here. */
11976 offbits
= (mips_opts
.micromips
? 12
11977 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11979 /* Itbl support may require additional care here. */
11983 gas_assert (!mips_opts
.micromips
);
11986 /* Itbl support may require additional care here. */
11992 offbits
= (mips_opts
.micromips
? 12 : 16);
11997 offbits
= (mips_opts
.micromips
? 12 : 16);
12002 /* Itbl support may require additional care here. */
12008 offbits
= (mips_opts
.micromips
? 12
12009 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12011 /* Itbl support may require additional care here. */
12017 /* Itbl support may require additional care here. */
12023 /* Itbl support may require additional care here. */
12029 offbits
= (mips_opts
.micromips
? 12 : 16);
12034 offbits
= (mips_opts
.micromips
? 12 : 16);
12039 offbits
= (mips_opts
.micromips
? 12
12040 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12046 offbits
= (mips_opts
.micromips
? 12
12047 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12053 offbits
= (mips_opts
.micromips
? 12 : 16);
12056 gas_assert (mips_opts
.micromips
);
12063 gas_assert (mips_opts
.micromips
);
12072 s
= ip
->insn_mo
->name
;
12078 gas_assert (mips_opts
.micromips
);
12084 gas_assert (mips_opts
.micromips
);
12091 /* Try to use one the the load registers to compute the base address.
12092 We don't want to use $0 as tempreg. */
12095 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12096 || (op
[1] == ZERO
&& op
[3] == op
[0])
12097 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12099 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12106 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12109 tempreg
= op
[0] + lp
;
12126 gas_assert (!mips_opts
.micromips
);
12129 /* Itbl support may require additional care here. */
12135 /* Itbl support may require additional care here. */
12141 offbits
= (mips_opts
.micromips
? 12
12142 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12144 /* Itbl support may require additional care here. */
12148 gas_assert (!mips_opts
.micromips
);
12151 /* Itbl support may require additional care here. */
12157 offbits
= (mips_opts
.micromips
? 12 : 16);
12162 offbits
= (mips_opts
.micromips
? 12 : 16);
12167 offbits
= (mips_opts
.micromips
? 12
12168 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12174 offbits
= (mips_opts
.micromips
? 12
12175 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12181 s
= ip
->insn_mo
->name
;
12188 fmt
= (mips_opts
.micromips
? "k,~(b)"
12189 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12191 offbits
= (mips_opts
.micromips
? 12
12192 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12202 fmt
= (mips_opts
.micromips
? "k,~(b)"
12203 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12205 offbits
= (mips_opts
.micromips
? 12
12206 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12218 /* Itbl support may require additional care here. */
12223 offbits
= (mips_opts
.micromips
? 12
12224 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12226 /* Itbl support may require additional care here. */
12232 /* Itbl support may require additional care here. */
12236 gas_assert (!mips_opts
.micromips
);
12239 /* Itbl support may require additional care here. */
12245 offbits
= (mips_opts
.micromips
? 12 : 16);
12250 offbits
= (mips_opts
.micromips
? 12 : 16);
12253 gas_assert (mips_opts
.micromips
);
12259 gas_assert (mips_opts
.micromips
);
12265 gas_assert (mips_opts
.micromips
);
12271 gas_assert (mips_opts
.micromips
);
12279 breg
= ll_sc_paired
? op
[3] : op
[2];
12280 if (small_offset_p (0, align
, 16))
12282 /* The first case exists for M_LD_AB and M_SD_AB, which are
12283 macros for o32 but which should act like normal instructions
12286 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12287 offset_reloc
[1], offset_reloc
[2], breg
);
12288 else if (small_offset_p (0, align
, offbits
))
12293 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12295 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12298 macro_build (NULL
, s
, fmt
, op
[0],
12299 (int) offset_expr
.X_add_number
, breg
);
12305 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12306 tempreg
, breg
, -1, offset_reloc
[0],
12307 offset_reloc
[1], offset_reloc
[2]);
12311 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12313 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12316 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12324 if (offset_expr
.X_op
!= O_constant
12325 && offset_expr
.X_op
!= O_symbol
)
12327 as_bad (_("expression too complex"));
12328 offset_expr
.X_op
= O_constant
;
12331 if (HAVE_32BIT_ADDRESSES
12332 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12336 sprintf_vma (value
, offset_expr
.X_add_number
);
12337 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12340 /* A constant expression in PIC code can be handled just as it
12341 is in non PIC code. */
12342 if (offset_expr
.X_op
== O_constant
)
12344 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12345 offbits
== 0 ? 16 : offbits
);
12346 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12348 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12351 tempreg
, tempreg
, breg
);
12354 if (offset_expr
.X_add_number
!= 0)
12355 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12356 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12358 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12360 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12362 else if (offbits
== 16)
12363 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12365 macro_build (NULL
, s
, fmt
, op
[0],
12366 (int) offset_expr
.X_add_number
, tempreg
);
12368 else if (offbits
!= 16)
12370 /* The offset field is too narrow to be used for a low-part
12371 relocation, so load the whole address into the auxiliary
12373 load_address (tempreg
, &offset_expr
, &used_at
);
12375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12376 tempreg
, tempreg
, breg
);
12380 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12382 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12385 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12387 else if (mips_pic
== NO_PIC
)
12389 /* If this is a reference to a GP relative symbol, and there
12390 is no base register, we want
12391 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12392 Otherwise, if there is no base register, we want
12393 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12394 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12395 If we have a constant, we need two instructions anyhow,
12396 so we always use the latter form.
12398 If we have a base register, and this is a reference to a
12399 GP relative symbol, we want
12400 addu $tempreg,$breg,$gp
12401 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12403 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12404 addu $tempreg,$tempreg,$breg
12405 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12406 With a constant we always use the latter case.
12408 With 64bit address space and no base register and $at usable,
12410 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12411 lui $at,<sym> (BFD_RELOC_HI16_S)
12412 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12415 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12416 If we have a base register, we want
12417 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12418 lui $at,<sym> (BFD_RELOC_HI16_S)
12419 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12423 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12425 Without $at we can't generate the optimal path for superscalar
12426 processors here since this would require two temporary registers.
12427 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12428 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12430 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12432 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12433 If we have a base register, we want
12434 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12435 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12437 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12439 daddu $tempreg,$tempreg,$breg
12440 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12442 For GP relative symbols in 64bit address space we can use
12443 the same sequence as in 32bit address space. */
12444 if (HAVE_64BIT_SYMBOLS
)
12446 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12447 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12449 relax_start (offset_expr
.X_add_symbol
);
12452 macro_build (&offset_expr
, s
, fmt
, op
[0],
12453 BFD_RELOC_GPREL16
, mips_gp_register
);
12457 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12458 tempreg
, breg
, mips_gp_register
);
12459 macro_build (&offset_expr
, s
, fmt
, op
[0],
12460 BFD_RELOC_GPREL16
, tempreg
);
12465 if (used_at
== 0 && mips_opts
.at
)
12467 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12468 BFD_RELOC_MIPS_HIGHEST
);
12469 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12471 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12472 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12474 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12475 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12476 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12477 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12483 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12484 BFD_RELOC_MIPS_HIGHEST
);
12485 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12486 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12487 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12488 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12489 tempreg
, BFD_RELOC_HI16_S
);
12490 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12492 macro_build (NULL
, "daddu", "d,v,t",
12493 tempreg
, tempreg
, breg
);
12494 macro_build (&offset_expr
, s
, fmt
, op
[0],
12495 BFD_RELOC_LO16
, tempreg
);
12498 if (mips_relax
.sequence
)
12505 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12506 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12508 relax_start (offset_expr
.X_add_symbol
);
12509 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12513 macro_build_lui (&offset_expr
, tempreg
);
12514 macro_build (&offset_expr
, s
, fmt
, op
[0],
12515 BFD_RELOC_LO16
, tempreg
);
12516 if (mips_relax
.sequence
)
12521 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12522 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12524 relax_start (offset_expr
.X_add_symbol
);
12525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12526 tempreg
, breg
, mips_gp_register
);
12527 macro_build (&offset_expr
, s
, fmt
, op
[0],
12528 BFD_RELOC_GPREL16
, tempreg
);
12531 macro_build_lui (&offset_expr
, tempreg
);
12532 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12533 tempreg
, tempreg
, breg
);
12534 macro_build (&offset_expr
, s
, fmt
, op
[0],
12535 BFD_RELOC_LO16
, tempreg
);
12536 if (mips_relax
.sequence
)
12540 else if (!mips_big_got
)
12542 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12544 /* If this is a reference to an external symbol, we want
12545 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12547 <op> op[0],0($tempreg)
12549 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12551 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12552 <op> op[0],0($tempreg)
12554 For NewABI, we want
12555 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12556 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12558 If there is a base register, we add it to $tempreg before
12559 the <op>. If there is a constant, we stick it in the
12560 <op> instruction. We don't handle constants larger than
12561 16 bits, because we have no way to load the upper 16 bits
12562 (actually, we could handle them for the subset of cases
12563 in which we are not using $at). */
12564 gas_assert (offset_expr
.X_op
== O_symbol
);
12567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12568 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12570 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12571 tempreg
, tempreg
, breg
);
12572 macro_build (&offset_expr
, s
, fmt
, op
[0],
12573 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12576 expr1
.X_add_number
= offset_expr
.X_add_number
;
12577 offset_expr
.X_add_number
= 0;
12578 if (expr1
.X_add_number
< -0x8000
12579 || expr1
.X_add_number
>= 0x8000)
12580 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12582 lw_reloc_type
, mips_gp_register
);
12584 relax_start (offset_expr
.X_add_symbol
);
12586 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12587 tempreg
, BFD_RELOC_LO16
);
12590 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12591 tempreg
, tempreg
, breg
);
12592 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12594 else if (mips_big_got
&& !HAVE_NEWABI
)
12598 /* If this is a reference to an external symbol, we want
12599 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12600 addu $tempreg,$tempreg,$gp
12601 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12602 <op> op[0],0($tempreg)
12604 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12606 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12607 <op> op[0],0($tempreg)
12608 If there is a base register, we add it to $tempreg before
12609 the <op>. If there is a constant, we stick it in the
12610 <op> instruction. We don't handle constants larger than
12611 16 bits, because we have no way to load the upper 16 bits
12612 (actually, we could handle them for the subset of cases
12613 in which we are not using $at). */
12614 gas_assert (offset_expr
.X_op
== O_symbol
);
12615 expr1
.X_add_number
= offset_expr
.X_add_number
;
12616 offset_expr
.X_add_number
= 0;
12617 if (expr1
.X_add_number
< -0x8000
12618 || expr1
.X_add_number
>= 0x8000)
12619 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12620 gpdelay
= reg_needs_delay (mips_gp_register
);
12621 relax_start (offset_expr
.X_add_symbol
);
12622 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12623 BFD_RELOC_MIPS_GOT_HI16
);
12624 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12626 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12627 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12630 macro_build (NULL
, "nop", "");
12631 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12632 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12634 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12635 tempreg
, BFD_RELOC_LO16
);
12639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12640 tempreg
, tempreg
, breg
);
12641 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12643 else if (mips_big_got
&& HAVE_NEWABI
)
12645 /* If this is a reference to an external symbol, we want
12646 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12647 add $tempreg,$tempreg,$gp
12648 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12649 <op> op[0],<ofst>($tempreg)
12650 Otherwise, for local symbols, we want:
12651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12652 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12653 gas_assert (offset_expr
.X_op
== O_symbol
);
12654 expr1
.X_add_number
= offset_expr
.X_add_number
;
12655 offset_expr
.X_add_number
= 0;
12656 if (expr1
.X_add_number
< -0x8000
12657 || expr1
.X_add_number
>= 0x8000)
12658 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12659 relax_start (offset_expr
.X_add_symbol
);
12660 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12661 BFD_RELOC_MIPS_GOT_HI16
);
12662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12665 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12668 tempreg
, tempreg
, breg
);
12669 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12672 offset_expr
.X_add_number
= expr1
.X_add_number
;
12673 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12674 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12677 tempreg
, tempreg
, breg
);
12678 macro_build (&offset_expr
, s
, fmt
, op
[0],
12679 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12688 gas_assert (mips_opts
.micromips
);
12689 gas_assert (mips_opts
.insn32
);
12690 start_noreorder ();
12691 macro_build (NULL
, "jr", "s", RA
);
12692 expr1
.X_add_number
= op
[0] << 2;
12693 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12698 gas_assert (mips_opts
.micromips
);
12699 gas_assert (mips_opts
.insn32
);
12700 macro_build (NULL
, "jr", "s", op
[0]);
12701 if (mips_opts
.noreorder
)
12702 macro_build (NULL
, "nop", "");
12707 load_register (op
[0], &imm_expr
, 0);
12711 load_register (op
[0], &imm_expr
, 1);
12715 if (imm_expr
.X_op
== O_constant
)
12718 load_register (AT
, &imm_expr
, 0);
12719 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12724 gas_assert (imm_expr
.X_op
== O_absent
12725 && offset_expr
.X_op
== O_symbol
12726 && strcmp (segment_name (S_GET_SEGMENT
12727 (offset_expr
.X_add_symbol
)),
12729 && offset_expr
.X_add_number
== 0);
12730 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12731 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12736 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12737 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12738 order 32 bits of the value and the low order 32 bits are either
12739 zero or in OFFSET_EXPR. */
12740 if (imm_expr
.X_op
== O_constant
)
12742 if (GPR_SIZE
== 64)
12743 load_register (op
[0], &imm_expr
, 1);
12748 if (target_big_endian
)
12760 load_register (hreg
, &imm_expr
, 0);
12763 if (offset_expr
.X_op
== O_absent
)
12764 move_register (lreg
, 0);
12767 gas_assert (offset_expr
.X_op
== O_constant
);
12768 load_register (lreg
, &offset_expr
, 0);
12774 gas_assert (imm_expr
.X_op
== O_absent
);
12776 /* We know that sym is in the .rdata section. First we get the
12777 upper 16 bits of the address. */
12778 if (mips_pic
== NO_PIC
)
12780 macro_build_lui (&offset_expr
, AT
);
12785 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12786 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12790 /* Now we load the register(s). */
12791 if (GPR_SIZE
== 64)
12794 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12795 BFD_RELOC_LO16
, AT
);
12800 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12801 BFD_RELOC_LO16
, AT
);
12804 /* FIXME: How in the world do we deal with the possible
12806 offset_expr
.X_add_number
+= 4;
12807 macro_build (&offset_expr
, "lw", "t,o(b)",
12808 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12814 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12815 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12816 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12817 the value and the low order 32 bits are either zero or in
12819 if (imm_expr
.X_op
== O_constant
)
12822 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12823 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12824 && imm_expr
.X_add_number
!= 0)
12828 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12830 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12831 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12834 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12836 if (FPR_SIZE
!= 32)
12837 as_bad (_("Unable to generate `%s' compliant code "
12839 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12841 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12843 if (offset_expr
.X_op
== O_absent
)
12844 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12847 gas_assert (offset_expr
.X_op
== O_constant
);
12848 load_register (AT
, &offset_expr
, 0);
12849 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12851 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12853 if (imm_expr
.X_add_number
!= 0)
12857 load_register (AT
, &imm_expr
, 0);
12859 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12865 gas_assert (imm_expr
.X_op
== O_absent
12866 && offset_expr
.X_op
== O_symbol
12867 && offset_expr
.X_add_number
== 0);
12868 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12869 if (strcmp (s
, ".lit8") == 0)
12871 op
[2] = mips_gp_register
;
12872 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12873 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12874 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12878 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12880 if (mips_pic
!= NO_PIC
)
12881 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12882 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12885 /* FIXME: This won't work for a 64 bit address. */
12886 macro_build_lui (&offset_expr
, AT
);
12890 offset_reloc
[0] = BFD_RELOC_LO16
;
12891 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12892 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12895 /* Fall through. */
12898 /* The MIPS assembler seems to check for X_add_number not
12899 being double aligned and generating:
12902 addiu at,at,%lo(foo+1)
12905 But, the resulting address is the same after relocation so why
12906 generate the extra instruction? */
12907 /* Itbl support may require additional care here. */
12910 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12919 gas_assert (!mips_opts
.micromips
);
12920 /* Itbl support may require additional care here. */
12923 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12943 if (GPR_SIZE
== 64)
12953 if (GPR_SIZE
== 64)
12961 /* Even on a big endian machine $fn comes before $fn+1. We have
12962 to adjust when loading from memory. We set coproc if we must
12963 load $fn+1 first. */
12964 /* Itbl support may require additional care here. */
12965 if (!target_big_endian
)
12969 if (small_offset_p (0, align
, 16))
12972 if (!small_offset_p (4, align
, 16))
12974 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12975 -1, offset_reloc
[0], offset_reloc
[1],
12977 expr1
.X_add_number
= 0;
12981 offset_reloc
[0] = BFD_RELOC_LO16
;
12982 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12983 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12985 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12987 ep
->X_add_number
+= 4;
12988 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12989 offset_reloc
[1], offset_reloc
[2], breg
);
12990 ep
->X_add_number
-= 4;
12991 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12992 offset_reloc
[1], offset_reloc
[2], breg
);
12996 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12997 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12999 ep
->X_add_number
+= 4;
13000 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
13001 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
13007 if (offset_expr
.X_op
!= O_symbol
13008 && offset_expr
.X_op
!= O_constant
)
13010 as_bad (_("expression too complex"));
13011 offset_expr
.X_op
= O_constant
;
13014 if (HAVE_32BIT_ADDRESSES
13015 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
13019 sprintf_vma (value
, offset_expr
.X_add_number
);
13020 as_bad (_("number (0x%s) larger than 32 bits"), value
);
13023 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
13025 /* If this is a reference to a GP relative symbol, we want
13026 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13027 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13028 If we have a base register, we use this
13030 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13031 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13032 If this is not a GP relative symbol, we want
13033 lui $at,<sym> (BFD_RELOC_HI16_S)
13034 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13035 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13036 If there is a base register, we add it to $at after the
13037 lui instruction. If there is a constant, we always use
13039 if (offset_expr
.X_op
== O_symbol
13040 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13041 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13043 relax_start (offset_expr
.X_add_symbol
);
13046 tempreg
= mips_gp_register
;
13050 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13051 AT
, breg
, mips_gp_register
);
13056 /* Itbl support may require additional care here. */
13057 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13058 BFD_RELOC_GPREL16
, tempreg
);
13059 offset_expr
.X_add_number
+= 4;
13061 /* Set mips_optimize to 2 to avoid inserting an
13063 hold_mips_optimize
= mips_optimize
;
13065 /* Itbl support may require additional care here. */
13066 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13067 BFD_RELOC_GPREL16
, tempreg
);
13068 mips_optimize
= hold_mips_optimize
;
13072 offset_expr
.X_add_number
-= 4;
13075 if (offset_high_part (offset_expr
.X_add_number
, 16)
13076 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13078 load_address (AT
, &offset_expr
, &used_at
);
13079 offset_expr
.X_op
= O_constant
;
13080 offset_expr
.X_add_number
= 0;
13083 macro_build_lui (&offset_expr
, AT
);
13085 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13086 /* Itbl support may require additional care here. */
13087 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13088 BFD_RELOC_LO16
, AT
);
13089 /* FIXME: How do we handle overflow here? */
13090 offset_expr
.X_add_number
+= 4;
13091 /* Itbl support may require additional care here. */
13092 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13093 BFD_RELOC_LO16
, AT
);
13094 if (mips_relax
.sequence
)
13097 else if (!mips_big_got
)
13099 /* If this is a reference to an external symbol, we want
13100 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13103 <op> op[0]+1,4($at)
13105 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13107 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13108 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13109 If there is a base register we add it to $at before the
13110 lwc1 instructions. If there is a constant we include it
13111 in the lwc1 instructions. */
13113 expr1
.X_add_number
= offset_expr
.X_add_number
;
13114 if (expr1
.X_add_number
< -0x8000
13115 || expr1
.X_add_number
>= 0x8000 - 4)
13116 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13117 load_got_offset (AT
, &offset_expr
);
13120 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13122 /* Set mips_optimize to 2 to avoid inserting an undesired
13124 hold_mips_optimize
= mips_optimize
;
13127 /* Itbl support may require additional care here. */
13128 relax_start (offset_expr
.X_add_symbol
);
13129 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13130 BFD_RELOC_LO16
, AT
);
13131 expr1
.X_add_number
+= 4;
13132 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13133 BFD_RELOC_LO16
, AT
);
13135 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13136 BFD_RELOC_LO16
, AT
);
13137 offset_expr
.X_add_number
+= 4;
13138 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13139 BFD_RELOC_LO16
, AT
);
13142 mips_optimize
= hold_mips_optimize
;
13144 else if (mips_big_got
)
13148 /* If this is a reference to an external symbol, we want
13149 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13151 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13154 <op> op[0]+1,4($at)
13156 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13158 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13159 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13160 If there is a base register we add it to $at before the
13161 lwc1 instructions. If there is a constant we include it
13162 in the lwc1 instructions. */
13164 expr1
.X_add_number
= offset_expr
.X_add_number
;
13165 offset_expr
.X_add_number
= 0;
13166 if (expr1
.X_add_number
< -0x8000
13167 || expr1
.X_add_number
>= 0x8000 - 4)
13168 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13169 gpdelay
= reg_needs_delay (mips_gp_register
);
13170 relax_start (offset_expr
.X_add_symbol
);
13171 macro_build (&offset_expr
, "lui", LUI_FMT
,
13172 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13174 AT
, AT
, mips_gp_register
);
13175 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13176 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13180 /* Itbl support may require additional care here. */
13181 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13182 BFD_RELOC_LO16
, AT
);
13183 expr1
.X_add_number
+= 4;
13185 /* Set mips_optimize to 2 to avoid inserting an undesired
13187 hold_mips_optimize
= mips_optimize
;
13189 /* Itbl support may require additional care here. */
13190 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13191 BFD_RELOC_LO16
, AT
);
13192 mips_optimize
= hold_mips_optimize
;
13193 expr1
.X_add_number
-= 4;
13196 offset_expr
.X_add_number
= expr1
.X_add_number
;
13198 macro_build (NULL
, "nop", "");
13199 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13200 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13203 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13204 /* Itbl support may require additional care here. */
13205 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13206 BFD_RELOC_LO16
, AT
);
13207 offset_expr
.X_add_number
+= 4;
13209 /* Set mips_optimize to 2 to avoid inserting an undesired
13211 hold_mips_optimize
= mips_optimize
;
13213 /* Itbl support may require additional care here. */
13214 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13215 BFD_RELOC_LO16
, AT
);
13216 mips_optimize
= hold_mips_optimize
;
13230 gas_assert (!mips_opts
.micromips
);
13235 /* New code added to support COPZ instructions.
13236 This code builds table entries out of the macros in mip_opcodes.
13237 R4000 uses interlocks to handle coproc delays.
13238 Other chips (like the R3000) require nops to be inserted for delays.
13240 FIXME: Currently, we require that the user handle delays.
13241 In order to fill delay slots for non-interlocked chips,
13242 we must have a way to specify delays based on the coprocessor.
13243 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13244 What are the side-effects of the cop instruction?
13245 What cache support might we have and what are its effects?
13246 Both coprocessor & memory require delays. how long???
13247 What registers are read/set/modified?
13249 If an itbl is provided to interpret cop instructions,
13250 this knowledge can be encoded in the itbl spec. */
13264 gas_assert (!mips_opts
.micromips
);
13265 /* For now we just do C (same as Cz). The parameter will be
13266 stored in insn_opcode by mips_ip. */
13267 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13271 move_register (op
[0], op
[1]);
13275 gas_assert (mips_opts
.micromips
);
13276 gas_assert (mips_opts
.insn32
);
13277 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13278 micromips_to_32_reg_m_map
[op
[1]]);
13279 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13280 micromips_to_32_reg_n_map
[op
[2]]);
13285 /* Fall through. */
13287 if (mips_opts
.arch
== CPU_R5900
)
13288 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13292 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13293 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13299 /* Fall through. */
13301 /* The MIPS assembler some times generates shifts and adds. I'm
13302 not trying to be that fancy. GCC should do this for us
13305 load_register (AT
, &imm_expr
, dbl
);
13306 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13307 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13312 /* Fall through. */
13319 /* Fall through. */
13322 start_noreorder ();
13325 load_register (AT
, &imm_expr
, dbl
);
13326 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13327 op
[1], imm
? AT
: op
[2]);
13328 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13329 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13330 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13332 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13335 if (mips_opts
.micromips
)
13336 micromips_label_expr (&label_expr
);
13338 label_expr
.X_add_number
= 8;
13339 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13340 macro_build (NULL
, "nop", "");
13341 macro_build (NULL
, "break", BRK_FMT
, 6);
13342 if (mips_opts
.micromips
)
13343 micromips_add_label ();
13346 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13351 /* Fall through. */
13358 /* Fall through. */
13361 start_noreorder ();
13364 load_register (AT
, &imm_expr
, dbl
);
13365 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13366 op
[1], imm
? AT
: op
[2]);
13367 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13368 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13370 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13373 if (mips_opts
.micromips
)
13374 micromips_label_expr (&label_expr
);
13376 label_expr
.X_add_number
= 8;
13377 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13378 macro_build (NULL
, "nop", "");
13379 macro_build (NULL
, "break", BRK_FMT
, 6);
13380 if (mips_opts
.micromips
)
13381 micromips_add_label ();
13387 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13389 if (op
[0] == op
[1])
13396 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13397 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13401 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13402 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13403 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13404 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13408 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13410 if (op
[0] == op
[1])
13417 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13418 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13422 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13423 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13424 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13425 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13434 rot
= imm_expr
.X_add_number
& 0x3f;
13435 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13437 rot
= (64 - rot
) & 0x3f;
13439 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13441 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13446 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13449 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13450 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13453 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13454 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13455 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13463 rot
= imm_expr
.X_add_number
& 0x1f;
13464 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13466 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13467 (32 - rot
) & 0x1f);
13472 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13476 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13477 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13478 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13483 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13485 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13489 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13490 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13491 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13492 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13496 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13498 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13502 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13503 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13504 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13505 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13514 rot
= imm_expr
.X_add_number
& 0x3f;
13515 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13518 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13520 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13525 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13528 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13529 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13532 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13533 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13534 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13542 rot
= imm_expr
.X_add_number
& 0x1f;
13543 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13545 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13550 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13554 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13555 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13556 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13562 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13563 else if (op
[2] == 0)
13564 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13567 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13568 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13573 if (imm_expr
.X_add_number
== 0)
13575 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13580 as_warn (_("instruction %s: result is always false"),
13581 ip
->insn_mo
->name
);
13582 move_register (op
[0], 0);
13585 if (CPU_HAS_SEQ (mips_opts
.arch
)
13586 && -512 <= imm_expr
.X_add_number
13587 && imm_expr
.X_add_number
< 512)
13589 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13590 (int) imm_expr
.X_add_number
);
13593 if (imm_expr
.X_add_number
>= 0
13594 && imm_expr
.X_add_number
< 0x10000)
13595 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13596 else if (imm_expr
.X_add_number
> -0x8000
13597 && imm_expr
.X_add_number
< 0)
13599 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13600 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13601 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13603 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13606 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13607 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13612 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13613 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13616 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13619 case M_SGE
: /* X >= Y <==> not (X < Y) */
13625 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13626 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13629 case M_SGE_I
: /* X >= I <==> not (X < I). */
13631 if (imm_expr
.X_add_number
>= -0x8000
13632 && imm_expr
.X_add_number
< 0x8000)
13633 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13634 op
[0], op
[1], BFD_RELOC_LO16
);
13637 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13638 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13642 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13645 case M_SGT
: /* X > Y <==> Y < X. */
13651 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13654 case M_SGT_I
: /* X > I <==> I < X. */
13661 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13662 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13665 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13671 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13672 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13675 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13682 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13683 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13684 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13688 if (imm_expr
.X_add_number
>= -0x8000
13689 && imm_expr
.X_add_number
< 0x8000)
13691 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13696 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13697 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13701 if (imm_expr
.X_add_number
>= -0x8000
13702 && imm_expr
.X_add_number
< 0x8000)
13704 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13709 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13710 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13715 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13716 else if (op
[2] == 0)
13717 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13720 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13721 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13726 if (imm_expr
.X_add_number
== 0)
13728 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13733 as_warn (_("instruction %s: result is always true"),
13734 ip
->insn_mo
->name
);
13735 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13736 op
[0], 0, BFD_RELOC_LO16
);
13739 if (CPU_HAS_SEQ (mips_opts
.arch
)
13740 && -512 <= imm_expr
.X_add_number
13741 && imm_expr
.X_add_number
< 512)
13743 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13744 (int) imm_expr
.X_add_number
);
13747 if (imm_expr
.X_add_number
>= 0
13748 && imm_expr
.X_add_number
< 0x10000)
13750 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13753 else if (imm_expr
.X_add_number
> -0x8000
13754 && imm_expr
.X_add_number
< 0)
13756 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13757 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13758 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13760 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13763 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13764 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13769 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13770 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13773 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13779 if (ISA_IS_R6 (mips_opts
.isa
))
13791 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13793 if (imm_expr
.X_add_number
> -0x200
13794 && imm_expr
.X_add_number
<= 0x200
13795 && !ISA_IS_R6 (mips_opts
.isa
))
13797 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13798 (int) -imm_expr
.X_add_number
);
13807 if (imm_expr
.X_add_number
> -0x8000
13808 && imm_expr
.X_add_number
<= 0x8000)
13810 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13811 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13816 load_register (AT
, &imm_expr
, dbl
);
13817 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13839 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13840 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13845 gas_assert (!mips_opts
.micromips
);
13846 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13850 * Is the double cfc1 instruction a bug in the mips assembler;
13851 * or is there a reason for it?
13853 start_noreorder ();
13854 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13855 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13856 macro_build (NULL
, "nop", "");
13857 expr1
.X_add_number
= 3;
13858 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13859 expr1
.X_add_number
= 2;
13860 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13861 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13862 macro_build (NULL
, "nop", "");
13863 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13865 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13866 macro_build (NULL
, "nop", "");
13883 offbits
= (mips_opts
.micromips
? 12 : 16);
13889 offbits
= (mips_opts
.micromips
? 12 : 16);
13901 offbits
= (mips_opts
.micromips
? 12 : 16);
13908 offbits
= (mips_opts
.micromips
? 12 : 16);
13914 large_offset
= !small_offset_p (off
, align
, offbits
);
13916 expr1
.X_add_number
= 0;
13921 if (small_offset_p (0, align
, 16))
13922 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13923 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13926 load_address (tempreg
, ep
, &used_at
);
13928 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13929 tempreg
, tempreg
, breg
);
13931 offset_reloc
[0] = BFD_RELOC_LO16
;
13932 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13933 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13938 else if (!ust
&& op
[0] == breg
)
13949 if (!target_big_endian
)
13950 ep
->X_add_number
+= off
;
13952 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13954 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13955 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13957 if (!target_big_endian
)
13958 ep
->X_add_number
-= off
;
13960 ep
->X_add_number
+= off
;
13962 macro_build (NULL
, s2
, "t,~(b)",
13963 tempreg
, (int) ep
->X_add_number
, breg
);
13965 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13966 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13968 /* If necessary, move the result in tempreg to the final destination. */
13969 if (!ust
&& op
[0] != tempreg
)
13971 /* Protect second load's delay slot. */
13973 move_register (op
[0], tempreg
);
13979 if (target_big_endian
== ust
)
13980 ep
->X_add_number
+= off
;
13981 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13982 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13983 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13985 /* For halfword transfers we need a temporary register to shuffle
13986 bytes. Unfortunately for M_USH_A we have none available before
13987 the next store as AT holds the base address. We deal with this
13988 case by clobbering TREG and then restoring it as with ULH. */
13989 tempreg
= ust
== large_offset
? op
[0] : AT
;
13991 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13993 if (target_big_endian
== ust
)
13994 ep
->X_add_number
-= off
;
13996 ep
->X_add_number
+= off
;
13997 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13998 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
14000 /* For M_USH_A re-retrieve the LSB. */
14001 if (ust
&& large_offset
)
14003 if (target_big_endian
)
14004 ep
->X_add_number
+= off
;
14006 ep
->X_add_number
-= off
;
14007 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
14008 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
14010 /* For ULH and M_USH_A OR the LSB in. */
14011 if (!ust
|| large_offset
)
14013 tempreg
= !large_offset
? AT
: op
[0];
14014 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
14015 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
14020 /* FIXME: Check if this is one of the itbl macros, since they
14021 are added dynamically. */
14022 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
14025 if (!mips_opts
.at
&& used_at
)
14026 as_bad (_("macro used $at after \".set noat\""));
14029 /* Implement macros in mips16 mode. */
14032 mips16_macro (struct mips_cl_insn
*ip
)
14034 const struct mips_operand_array
*operands
;
14039 const char *s
, *s2
, *s3
;
14040 unsigned int op
[MAX_OPERANDS
];
14043 mask
= ip
->insn_mo
->mask
;
14045 operands
= insn_operands (ip
);
14046 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14047 if (operands
->operand
[i
])
14048 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14052 expr1
.X_op
= O_constant
;
14053 expr1
.X_op_symbol
= NULL
;
14054 expr1
.X_add_symbol
= NULL
;
14055 expr1
.X_add_number
= 1;
14066 /* Fall through. */
14072 /* Fall through. */
14076 start_noreorder ();
14077 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14078 expr1
.X_add_number
= 2;
14079 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14080 macro_build (NULL
, "break", "6", 7);
14082 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14083 since that causes an overflow. We should do that as well,
14084 but I don't see how to do the comparisons without a temporary
14087 macro_build (NULL
, s
, "x", op
[0]);
14106 start_noreorder ();
14107 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14108 expr1
.X_add_number
= 2;
14109 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14110 macro_build (NULL
, "break", "6", 7);
14112 macro_build (NULL
, s2
, "x", op
[0]);
14117 /* Fall through. */
14119 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14120 macro_build (NULL
, "mflo", "x", op
[0]);
14128 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14129 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14133 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14134 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14138 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14139 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14161 goto do_reverse_branch
;
14165 goto do_reverse_branch
;
14177 goto do_reverse_branch
;
14188 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14189 macro_build (&offset_expr
, s2
, "p");
14216 goto do_addone_branch_i
;
14221 goto do_addone_branch_i
;
14236 goto do_addone_branch_i
;
14242 do_addone_branch_i
:
14243 ++imm_expr
.X_add_number
;
14246 macro_build (&imm_expr
, s
, s3
, op
[0]);
14247 macro_build (&offset_expr
, s2
, "p");
14251 expr1
.X_add_number
= 0;
14252 macro_build (&expr1
, "slti", "x,8", op
[1]);
14253 if (op
[0] != op
[1])
14254 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14255 expr1
.X_add_number
= 2;
14256 macro_build (&expr1
, "bteqz", "p");
14257 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14262 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14263 opcode bits in *OPCODE_EXTRA. */
14265 static struct mips_opcode
*
14266 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14267 ssize_t length
, unsigned int *opcode_extra
)
14269 char *name
, *dot
, *p
;
14270 unsigned int mask
, suffix
;
14272 struct mips_opcode
*insn
;
14274 /* Make a copy of the instruction so that we can fiddle with it. */
14275 name
= xstrndup (start
, length
);
14277 /* Look up the instruction as-is. */
14278 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14282 dot
= strchr (name
, '.');
14285 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14286 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14287 if (*p
== 0 && mask
!= 0)
14290 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14292 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14294 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14300 if (mips_opts
.micromips
)
14302 /* See if there's an instruction size override suffix,
14303 either `16' or `32', at the end of the mnemonic proper,
14304 that defines the operation, i.e. before the first `.'
14305 character if any. Strip it and retry. */
14306 opend
= dot
!= NULL
? dot
- name
: length
;
14307 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14309 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14315 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14316 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14319 forced_insn_length
= suffix
;
14331 /* Assemble an instruction into its binary format. If the instruction
14332 is a macro, set imm_expr and offset_expr to the values associated
14333 with "I" and "A" operands respectively. Otherwise store the value
14334 of the relocatable field (if any) in offset_expr. In both cases
14335 set offset_reloc to the relocation operators applied to offset_expr. */
14338 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14340 const struct mips_opcode
*first
, *past
;
14341 struct hash_control
*hash
;
14344 struct mips_operand_token
*tokens
;
14345 unsigned int opcode_extra
;
14347 if (mips_opts
.micromips
)
14349 hash
= micromips_op_hash
;
14350 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14355 past
= &mips_opcodes
[NUMOPCODES
];
14357 forced_insn_length
= 0;
14360 /* We first try to match an instruction up to a space or to the end. */
14361 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14364 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14367 set_insn_error (0, _("unrecognized opcode"));
14371 if (strcmp (first
->name
, "li.s") == 0)
14373 else if (strcmp (first
->name
, "li.d") == 0)
14377 tokens
= mips_parse_arguments (str
+ end
, format
);
14381 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14382 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14383 set_insn_error (0, _("invalid operands"));
14385 obstack_free (&mips_operand_tokens
, tokens
);
14388 /* As for mips_ip, but used when assembling MIPS16 code.
14389 Also set forced_insn_length to the resulting instruction size in
14390 bytes if the user explicitly requested a small or extended instruction. */
14393 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14396 struct mips_opcode
*first
;
14397 struct mips_operand_token
*tokens
;
14400 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14422 else if (*s
== 'e')
14429 else if (*s
++ == ' ')
14431 set_insn_error (0, _("unrecognized opcode"));
14434 forced_insn_length
= l
;
14437 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14442 set_insn_error (0, _("unrecognized opcode"));
14446 tokens
= mips_parse_arguments (s
, 0);
14450 if (!match_mips16_insns (insn
, first
, tokens
))
14451 set_insn_error (0, _("invalid operands"));
14453 obstack_free (&mips_operand_tokens
, tokens
);
14456 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14457 NBITS is the number of significant bits in VAL. */
14459 static unsigned long
14460 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14465 val
&= (1U << nbits
) - 1;
14466 if (nbits
== 16 || nbits
== 9)
14468 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14471 else if (nbits
== 15)
14473 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14476 else if (nbits
== 6)
14478 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14481 return (extval
<< 16) | val
;
14484 /* Like decode_mips16_operand, but require the operand to be defined and
14485 require it to be an integer. */
14487 static const struct mips_int_operand
*
14488 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14490 const struct mips_operand
*operand
;
14492 operand
= decode_mips16_operand (type
, extended_p
);
14493 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14495 return (const struct mips_int_operand
*) operand
;
14498 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14501 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14502 bfd_reloc_code_real_type reloc
, offsetT sval
)
14504 int min_val
, max_val
;
14506 min_val
= mips_int_operand_min (operand
);
14507 max_val
= mips_int_operand_max (operand
);
14508 if (reloc
!= BFD_RELOC_UNUSED
)
14511 sval
= SEXT_16BIT (sval
);
14516 return (sval
>= min_val
14518 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14521 /* Install immediate value VAL into MIPS16 instruction *INSN,
14522 extending it if necessary. The instruction in *INSN may
14523 already be extended.
14525 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14526 if none. In the former case, VAL is a 16-bit number with no
14527 defined signedness.
14529 TYPE is the type of the immediate field. USER_INSN_LENGTH
14530 is the length that the user requested, or 0 if none. */
14533 mips16_immed (const char *file
, unsigned int line
, int type
,
14534 bfd_reloc_code_real_type reloc
, offsetT val
,
14535 unsigned int user_insn_length
, unsigned long *insn
)
14537 const struct mips_int_operand
*operand
;
14538 unsigned int uval
, length
;
14540 operand
= mips16_immed_operand (type
, FALSE
);
14541 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14543 /* We need an extended instruction. */
14544 if (user_insn_length
== 2)
14545 as_bad_where (file
, line
, _("invalid unextended operand value"));
14547 *insn
|= MIPS16_EXTEND
;
14549 else if (user_insn_length
== 4)
14551 /* The operand doesn't force an unextended instruction to be extended.
14552 Warn if the user wanted an extended instruction anyway. */
14553 *insn
|= MIPS16_EXTEND
;
14554 as_warn_where (file
, line
,
14555 _("extended operand requested but not required"));
14558 length
= mips16_opcode_length (*insn
);
14561 operand
= mips16_immed_operand (type
, TRUE
);
14562 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14563 as_bad_where (file
, line
,
14564 _("operand value out of range for instruction"));
14566 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14567 if (length
== 2 || operand
->root
.lsb
!= 0)
14568 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14570 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14573 struct percent_op_match
14576 bfd_reloc_code_real_type reloc
;
14579 static const struct percent_op_match mips_percent_op
[] =
14581 {"%lo", BFD_RELOC_LO16
},
14582 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14583 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14584 {"%call16", BFD_RELOC_MIPS_CALL16
},
14585 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14586 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14587 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14588 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14589 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14590 {"%got", BFD_RELOC_MIPS_GOT16
},
14591 {"%gp_rel", BFD_RELOC_GPREL16
},
14592 {"%gprel", BFD_RELOC_GPREL16
},
14593 {"%half", BFD_RELOC_16
},
14594 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14595 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14596 {"%neg", BFD_RELOC_MIPS_SUB
},
14597 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14598 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14599 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14600 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14601 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14602 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14603 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14604 {"%hi", BFD_RELOC_HI16_S
},
14605 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14606 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14609 static const struct percent_op_match mips16_percent_op
[] =
14611 {"%lo", BFD_RELOC_MIPS16_LO16
},
14612 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14613 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14614 {"%got", BFD_RELOC_MIPS16_GOT16
},
14615 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14616 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14617 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14618 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14619 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14620 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14621 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14622 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14623 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14627 /* Return true if *STR points to a relocation operator. When returning true,
14628 move *STR over the operator and store its relocation code in *RELOC.
14629 Leave both *STR and *RELOC alone when returning false. */
14632 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14634 const struct percent_op_match
*percent_op
;
14637 if (mips_opts
.mips16
)
14639 percent_op
= mips16_percent_op
;
14640 limit
= ARRAY_SIZE (mips16_percent_op
);
14644 percent_op
= mips_percent_op
;
14645 limit
= ARRAY_SIZE (mips_percent_op
);
14648 for (i
= 0; i
< limit
; i
++)
14649 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14651 int len
= strlen (percent_op
[i
].str
);
14653 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14656 *str
+= strlen (percent_op
[i
].str
);
14657 *reloc
= percent_op
[i
].reloc
;
14659 /* Check whether the output BFD supports this relocation.
14660 If not, issue an error and fall back on something safe. */
14661 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14663 as_bad (_("relocation %s isn't supported by the current ABI"),
14664 percent_op
[i
].str
);
14665 *reloc
= BFD_RELOC_UNUSED
;
14673 /* Parse string STR as a 16-bit relocatable operand. Store the
14674 expression in *EP and the relocations in the array starting
14675 at RELOC. Return the number of relocation operators used.
14677 On exit, EXPR_END points to the first character after the expression. */
14680 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14683 bfd_reloc_code_real_type reversed_reloc
[3];
14684 size_t reloc_index
, i
;
14685 int crux_depth
, str_depth
;
14688 /* Search for the start of the main expression, recoding relocations
14689 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14690 of the main expression and with CRUX_DEPTH containing the number
14691 of open brackets at that point. */
14698 crux_depth
= str_depth
;
14700 /* Skip over whitespace and brackets, keeping count of the number
14702 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14707 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14708 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14710 my_getExpression (ep
, crux
);
14713 /* Match every open bracket. */
14714 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14718 if (crux_depth
> 0)
14719 as_bad (_("unclosed '('"));
14723 if (reloc_index
!= 0)
14725 prev_reloc_op_frag
= frag_now
;
14726 for (i
= 0; i
< reloc_index
; i
++)
14727 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14730 return reloc_index
;
14734 my_getExpression (expressionS
*ep
, char *str
)
14738 save_in
= input_line_pointer
;
14739 input_line_pointer
= str
;
14741 expr_end
= input_line_pointer
;
14742 input_line_pointer
= save_in
;
14746 md_atof (int type
, char *litP
, int *sizeP
)
14748 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14752 md_number_to_chars (char *buf
, valueT val
, int n
)
14754 if (target_big_endian
)
14755 number_to_chars_bigendian (buf
, val
, n
);
14757 number_to_chars_littleendian (buf
, val
, n
);
14760 static int support_64bit_objects(void)
14762 const char **list
, **l
;
14765 list
= bfd_target_list ();
14766 for (l
= list
; *l
!= NULL
; l
++)
14767 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14768 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14770 yes
= (*l
!= NULL
);
14775 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14776 NEW_VALUE. Warn if another value was already specified. Note:
14777 we have to defer parsing the -march and -mtune arguments in order
14778 to handle 'from-abi' correctly, since the ABI might be specified
14779 in a later argument. */
14782 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14784 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14785 as_warn (_("a different %s was already specified, is now %s"),
14786 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14789 *string_ptr
= new_value
;
14793 md_parse_option (int c
, const char *arg
)
14797 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14798 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14800 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14801 c
== mips_ases
[i
].option_on
);
14807 case OPTION_CONSTRUCT_FLOATS
:
14808 mips_disable_float_construction
= 0;
14811 case OPTION_NO_CONSTRUCT_FLOATS
:
14812 mips_disable_float_construction
= 1;
14824 target_big_endian
= 1;
14828 target_big_endian
= 0;
14834 else if (arg
[0] == '0')
14836 else if (arg
[0] == '1')
14846 mips_debug
= atoi (arg
);
14850 file_mips_opts
.isa
= ISA_MIPS1
;
14854 file_mips_opts
.isa
= ISA_MIPS2
;
14858 file_mips_opts
.isa
= ISA_MIPS3
;
14862 file_mips_opts
.isa
= ISA_MIPS4
;
14866 file_mips_opts
.isa
= ISA_MIPS5
;
14869 case OPTION_MIPS32
:
14870 file_mips_opts
.isa
= ISA_MIPS32
;
14873 case OPTION_MIPS32R2
:
14874 file_mips_opts
.isa
= ISA_MIPS32R2
;
14877 case OPTION_MIPS32R3
:
14878 file_mips_opts
.isa
= ISA_MIPS32R3
;
14881 case OPTION_MIPS32R5
:
14882 file_mips_opts
.isa
= ISA_MIPS32R5
;
14885 case OPTION_MIPS32R6
:
14886 file_mips_opts
.isa
= ISA_MIPS32R6
;
14889 case OPTION_MIPS64R2
:
14890 file_mips_opts
.isa
= ISA_MIPS64R2
;
14893 case OPTION_MIPS64R3
:
14894 file_mips_opts
.isa
= ISA_MIPS64R3
;
14897 case OPTION_MIPS64R5
:
14898 file_mips_opts
.isa
= ISA_MIPS64R5
;
14901 case OPTION_MIPS64R6
:
14902 file_mips_opts
.isa
= ISA_MIPS64R6
;
14905 case OPTION_MIPS64
:
14906 file_mips_opts
.isa
= ISA_MIPS64
;
14910 mips_set_option_string (&mips_tune_string
, arg
);
14914 mips_set_option_string (&mips_arch_string
, arg
);
14918 mips_set_option_string (&mips_arch_string
, "4650");
14919 mips_set_option_string (&mips_tune_string
, "4650");
14922 case OPTION_NO_M4650
:
14926 mips_set_option_string (&mips_arch_string
, "4010");
14927 mips_set_option_string (&mips_tune_string
, "4010");
14930 case OPTION_NO_M4010
:
14934 mips_set_option_string (&mips_arch_string
, "4100");
14935 mips_set_option_string (&mips_tune_string
, "4100");
14938 case OPTION_NO_M4100
:
14942 mips_set_option_string (&mips_arch_string
, "3900");
14943 mips_set_option_string (&mips_tune_string
, "3900");
14946 case OPTION_NO_M3900
:
14949 case OPTION_MICROMIPS
:
14950 if (file_mips_opts
.mips16
== 1)
14952 as_bad (_("-mmicromips cannot be used with -mips16"));
14955 file_mips_opts
.micromips
= 1;
14956 mips_no_prev_insn ();
14959 case OPTION_NO_MICROMIPS
:
14960 file_mips_opts
.micromips
= 0;
14961 mips_no_prev_insn ();
14964 case OPTION_MIPS16
:
14965 if (file_mips_opts
.micromips
== 1)
14967 as_bad (_("-mips16 cannot be used with -micromips"));
14970 file_mips_opts
.mips16
= 1;
14971 mips_no_prev_insn ();
14974 case OPTION_NO_MIPS16
:
14975 file_mips_opts
.mips16
= 0;
14976 mips_no_prev_insn ();
14979 case OPTION_FIX_24K
:
14983 case OPTION_NO_FIX_24K
:
14987 case OPTION_FIX_RM7000
:
14988 mips_fix_rm7000
= 1;
14991 case OPTION_NO_FIX_RM7000
:
14992 mips_fix_rm7000
= 0;
14995 case OPTION_FIX_LOONGSON3_LLSC
:
14996 mips_fix_loongson3_llsc
= TRUE
;
14999 case OPTION_NO_FIX_LOONGSON3_LLSC
:
15000 mips_fix_loongson3_llsc
= FALSE
;
15003 case OPTION_FIX_LOONGSON2F_JUMP
:
15004 mips_fix_loongson2f_jump
= TRUE
;
15007 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15008 mips_fix_loongson2f_jump
= FALSE
;
15011 case OPTION_FIX_LOONGSON2F_NOP
:
15012 mips_fix_loongson2f_nop
= TRUE
;
15015 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15016 mips_fix_loongson2f_nop
= FALSE
;
15019 case OPTION_FIX_VR4120
:
15020 mips_fix_vr4120
= 1;
15023 case OPTION_NO_FIX_VR4120
:
15024 mips_fix_vr4120
= 0;
15027 case OPTION_FIX_VR4130
:
15028 mips_fix_vr4130
= 1;
15031 case OPTION_NO_FIX_VR4130
:
15032 mips_fix_vr4130
= 0;
15035 case OPTION_FIX_CN63XXP1
:
15036 mips_fix_cn63xxp1
= TRUE
;
15039 case OPTION_NO_FIX_CN63XXP1
:
15040 mips_fix_cn63xxp1
= FALSE
;
15043 case OPTION_FIX_R5900
:
15044 mips_fix_r5900
= TRUE
;
15045 mips_fix_r5900_explicit
= TRUE
;
15048 case OPTION_NO_FIX_R5900
:
15049 mips_fix_r5900
= FALSE
;
15050 mips_fix_r5900_explicit
= TRUE
;
15053 case OPTION_RELAX_BRANCH
:
15054 mips_relax_branch
= 1;
15057 case OPTION_NO_RELAX_BRANCH
:
15058 mips_relax_branch
= 0;
15061 case OPTION_IGNORE_BRANCH_ISA
:
15062 mips_ignore_branch_isa
= TRUE
;
15065 case OPTION_NO_IGNORE_BRANCH_ISA
:
15066 mips_ignore_branch_isa
= FALSE
;
15069 case OPTION_INSN32
:
15070 file_mips_opts
.insn32
= TRUE
;
15073 case OPTION_NO_INSN32
:
15074 file_mips_opts
.insn32
= FALSE
;
15077 case OPTION_MSHARED
:
15078 mips_in_shared
= TRUE
;
15081 case OPTION_MNO_SHARED
:
15082 mips_in_shared
= FALSE
;
15085 case OPTION_MSYM32
:
15086 file_mips_opts
.sym32
= TRUE
;
15089 case OPTION_MNO_SYM32
:
15090 file_mips_opts
.sym32
= FALSE
;
15093 /* When generating ELF code, we permit -KPIC and -call_shared to
15094 select SVR4_PIC, and -non_shared to select no PIC. This is
15095 intended to be compatible with Irix 5. */
15096 case OPTION_CALL_SHARED
:
15097 mips_pic
= SVR4_PIC
;
15098 mips_abicalls
= TRUE
;
15101 case OPTION_CALL_NONPIC
:
15103 mips_abicalls
= TRUE
;
15106 case OPTION_NON_SHARED
:
15108 mips_abicalls
= FALSE
;
15111 /* The -xgot option tells the assembler to use 32 bit offsets
15112 when accessing the got in SVR4_PIC mode. It is for Irix
15119 g_switch_value
= atoi (arg
);
15123 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15126 mips_abi
= O32_ABI
;
15130 mips_abi
= N32_ABI
;
15134 mips_abi
= N64_ABI
;
15135 if (!support_64bit_objects())
15136 as_fatal (_("no compiled in support for 64 bit object file format"));
15140 file_mips_opts
.gp
= 32;
15144 file_mips_opts
.gp
= 64;
15148 file_mips_opts
.fp
= 32;
15152 file_mips_opts
.fp
= 0;
15156 file_mips_opts
.fp
= 64;
15159 case OPTION_ODD_SPREG
:
15160 file_mips_opts
.oddspreg
= 1;
15163 case OPTION_NO_ODD_SPREG
:
15164 file_mips_opts
.oddspreg
= 0;
15167 case OPTION_SINGLE_FLOAT
:
15168 file_mips_opts
.single_float
= 1;
15171 case OPTION_DOUBLE_FLOAT
:
15172 file_mips_opts
.single_float
= 0;
15175 case OPTION_SOFT_FLOAT
:
15176 file_mips_opts
.soft_float
= 1;
15179 case OPTION_HARD_FLOAT
:
15180 file_mips_opts
.soft_float
= 0;
15184 if (strcmp (arg
, "32") == 0)
15185 mips_abi
= O32_ABI
;
15186 else if (strcmp (arg
, "o64") == 0)
15187 mips_abi
= O64_ABI
;
15188 else if (strcmp (arg
, "n32") == 0)
15189 mips_abi
= N32_ABI
;
15190 else if (strcmp (arg
, "64") == 0)
15192 mips_abi
= N64_ABI
;
15193 if (! support_64bit_objects())
15194 as_fatal (_("no compiled in support for 64 bit object file "
15197 else if (strcmp (arg
, "eabi") == 0)
15198 mips_abi
= EABI_ABI
;
15201 as_fatal (_("invalid abi -mabi=%s"), arg
);
15206 case OPTION_M7000_HILO_FIX
:
15207 mips_7000_hilo_fix
= TRUE
;
15210 case OPTION_MNO_7000_HILO_FIX
:
15211 mips_7000_hilo_fix
= FALSE
;
15214 case OPTION_MDEBUG
:
15215 mips_flag_mdebug
= TRUE
;
15218 case OPTION_NO_MDEBUG
:
15219 mips_flag_mdebug
= FALSE
;
15223 mips_flag_pdr
= TRUE
;
15226 case OPTION_NO_PDR
:
15227 mips_flag_pdr
= FALSE
;
15230 case OPTION_MVXWORKS_PIC
:
15231 mips_pic
= VXWORKS_PIC
;
15235 if (strcmp (arg
, "2008") == 0)
15237 else if (strcmp (arg
, "legacy") == 0)
15241 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15250 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15255 /* Set up globals to tune for the ISA or processor described by INFO. */
15258 mips_set_tune (const struct mips_cpu_info
*info
)
15261 mips_tune
= info
->cpu
;
15266 mips_after_parse_args (void)
15268 const struct mips_cpu_info
*arch_info
= 0;
15269 const struct mips_cpu_info
*tune_info
= 0;
15271 /* GP relative stuff not working for PE. */
15272 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15274 if (g_switch_seen
&& g_switch_value
!= 0)
15275 as_bad (_("-G not supported in this configuration"));
15276 g_switch_value
= 0;
15279 if (mips_abi
== NO_ABI
)
15280 mips_abi
= MIPS_DEFAULT_ABI
;
15282 /* The following code determines the architecture.
15283 Similar code was added to GCC 3.3 (see override_options() in
15284 config/mips/mips.c). The GAS and GCC code should be kept in sync
15285 as much as possible. */
15287 if (mips_arch_string
!= 0)
15288 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15290 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15292 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15293 ISA level specified by -mipsN, while arch_info->isa contains
15294 the -march selection (if any). */
15295 if (arch_info
!= 0)
15297 /* -march takes precedence over -mipsN, since it is more descriptive.
15298 There's no harm in specifying both as long as the ISA levels
15300 if (file_mips_opts
.isa
!= arch_info
->isa
)
15301 as_bad (_("-%s conflicts with the other architecture options,"
15302 " which imply -%s"),
15303 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15304 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15307 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15310 if (arch_info
== 0)
15312 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15313 gas_assert (arch_info
);
15316 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15317 as_bad (_("-march=%s is not compatible with the selected ABI"),
15320 file_mips_opts
.arch
= arch_info
->cpu
;
15321 file_mips_opts
.isa
= arch_info
->isa
;
15322 file_mips_opts
.init_ase
= arch_info
->ase
;
15324 /* The EVA Extension has instructions which are only valid when the R6 ISA
15325 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15327 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15328 file_mips_opts
.ase
|= ASE_EVA_R6
;
15330 /* Set up initial mips_opts state. */
15331 mips_opts
= file_mips_opts
;
15333 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15334 if (!mips_fix_r5900_explicit
)
15335 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15337 /* The register size inference code is now placed in
15338 file_mips_check_options. */
15340 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15342 if (mips_tune_string
!= 0)
15343 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15345 if (tune_info
== 0)
15346 mips_set_tune (arch_info
);
15348 mips_set_tune (tune_info
);
15350 if (mips_flag_mdebug
< 0)
15351 mips_flag_mdebug
= 0;
15355 mips_init_after_args (void)
15357 /* Initialize opcodes. */
15358 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15359 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15363 md_pcrel_from (fixS
*fixP
)
15365 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15367 switch (fixP
->fx_r_type
)
15369 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15370 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15371 /* Return the address of the delay slot. */
15374 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15375 case BFD_RELOC_MICROMIPS_JMP
:
15376 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15377 case BFD_RELOC_16_PCREL_S2
:
15378 case BFD_RELOC_MIPS_21_PCREL_S2
:
15379 case BFD_RELOC_MIPS_26_PCREL_S2
:
15380 case BFD_RELOC_MIPS_JMP
:
15381 /* Return the address of the delay slot. */
15384 case BFD_RELOC_MIPS_18_PCREL_S3
:
15385 /* Return the aligned address of the doubleword containing
15386 the instruction. */
15394 /* This is called before the symbol table is processed. In order to
15395 work with gcc when using mips-tfile, we must keep all local labels.
15396 However, in other cases, we want to discard them. If we were
15397 called with -g, but we didn't see any debugging information, it may
15398 mean that gcc is smuggling debugging information through to
15399 mips-tfile, in which case we must generate all local labels. */
15402 mips_frob_file_before_adjust (void)
15404 #ifndef NO_ECOFF_DEBUGGING
15405 if (ECOFF_DEBUGGING
15407 && ! ecoff_debugging_seen
)
15408 flag_keep_locals
= 1;
15412 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15413 the corresponding LO16 reloc. This is called before md_apply_fix and
15414 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15415 relocation operators.
15417 For our purposes, a %lo() expression matches a %got() or %hi()
15420 (a) it refers to the same symbol; and
15421 (b) the offset applied in the %lo() expression is no lower than
15422 the offset applied in the %got() or %hi().
15424 (b) allows us to cope with code like:
15427 lh $4,%lo(foo+2)($4)
15429 ...which is legal on RELA targets, and has a well-defined behaviour
15430 if the user knows that adding 2 to "foo" will not induce a carry to
15433 When several %lo()s match a particular %got() or %hi(), we use the
15434 following rules to distinguish them:
15436 (1) %lo()s with smaller offsets are a better match than %lo()s with
15439 (2) %lo()s with no matching %got() or %hi() are better than those
15440 that already have a matching %got() or %hi().
15442 (3) later %lo()s are better than earlier %lo()s.
15444 These rules are applied in order.
15446 (1) means, among other things, that %lo()s with identical offsets are
15447 chosen if they exist.
15449 (2) means that we won't associate several high-part relocations with
15450 the same low-part relocation unless there's no alternative. Having
15451 several high parts for the same low part is a GNU extension; this rule
15452 allows careful users to avoid it.
15454 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15455 with the last high-part relocation being at the front of the list.
15456 It therefore makes sense to choose the last matching low-part
15457 relocation, all other things being equal. It's also easier
15458 to code that way. */
15461 mips_frob_file (void)
15463 struct mips_hi_fixup
*l
;
15464 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15466 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15468 segment_info_type
*seginfo
;
15469 bfd_boolean matched_lo_p
;
15470 fixS
**hi_pos
, **lo_pos
, **pos
;
15472 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15474 /* If a GOT16 relocation turns out to be against a global symbol,
15475 there isn't supposed to be a matching LO. Ignore %gots against
15476 constants; we'll report an error for those later. */
15477 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15478 && !(l
->fixp
->fx_addsy
15479 && pic_need_relax (l
->fixp
->fx_addsy
)))
15482 /* Check quickly whether the next fixup happens to be a matching %lo. */
15483 if (fixup_has_matching_lo_p (l
->fixp
))
15486 seginfo
= seg_info (l
->seg
);
15488 /* Set HI_POS to the position of this relocation in the chain.
15489 Set LO_POS to the position of the chosen low-part relocation.
15490 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15491 relocation that matches an immediately-preceding high-part
15495 matched_lo_p
= FALSE
;
15496 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15498 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15500 if (*pos
== l
->fixp
)
15503 if ((*pos
)->fx_r_type
== looking_for_rtype
15504 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15505 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15507 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15509 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15512 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15513 && fixup_has_matching_lo_p (*pos
));
15516 /* If we found a match, remove the high-part relocation from its
15517 current position and insert it before the low-part relocation.
15518 Make the offsets match so that fixup_has_matching_lo_p()
15521 We don't warn about unmatched high-part relocations since some
15522 versions of gcc have been known to emit dead "lui ...%hi(...)"
15524 if (lo_pos
!= NULL
)
15526 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15527 if (l
->fixp
->fx_next
!= *lo_pos
)
15529 *hi_pos
= l
->fixp
->fx_next
;
15530 l
->fixp
->fx_next
= *lo_pos
;
15538 mips_force_relocation (fixS
*fixp
)
15540 if (generic_force_reloc (fixp
))
15543 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15544 so that the linker relaxation can update targets. */
15545 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15546 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15547 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15550 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15551 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15552 microMIPS symbols so that we can do cross-mode branch diagnostics
15553 and BAL to JALX conversion by the linker. */
15554 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15555 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15556 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15558 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15561 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15562 if (ISA_IS_R6 (file_mips_opts
.isa
)
15563 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15564 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15565 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15566 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15567 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15568 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15569 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15575 /* Implement TC_FORCE_RELOCATION_ABS. */
15578 mips_force_relocation_abs (fixS
*fixp
)
15580 if (generic_force_reloc (fixp
))
15583 /* These relocations do not have enough bits in the in-place addend
15584 to hold an arbitrary absolute section's offset. */
15585 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15591 /* Read the instruction associated with RELOC from BUF. */
15593 static unsigned int
15594 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15596 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15597 return read_compressed_insn (buf
, 4);
15599 return read_insn (buf
);
15602 /* Write instruction INSN to BUF, given that it has been relocated
15606 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15607 unsigned long insn
)
15609 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15610 write_compressed_insn (buf
, insn
, 4);
15612 write_insn (buf
, insn
);
15615 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15616 to a symbol in another ISA mode, which cannot be converted to JALX. */
15619 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15621 unsigned long opcode
;
15625 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15628 other
= S_GET_OTHER (fixP
->fx_addsy
);
15629 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15630 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15631 switch (fixP
->fx_r_type
)
15633 case BFD_RELOC_MIPS_JMP
:
15634 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15635 case BFD_RELOC_MICROMIPS_JMP
:
15636 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15642 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15643 jump to a symbol in the same ISA mode. */
15646 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15648 unsigned long opcode
;
15652 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15655 other
= S_GET_OTHER (fixP
->fx_addsy
);
15656 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15657 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15658 switch (fixP
->fx_r_type
)
15660 case BFD_RELOC_MIPS_JMP
:
15661 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15662 case BFD_RELOC_MIPS16_JMP
:
15663 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15664 case BFD_RELOC_MICROMIPS_JMP
:
15665 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15671 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15672 to a symbol whose value plus addend is not aligned according to the
15673 ultimate (after linker relaxation) jump instruction's immediate field
15674 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15675 regular MIPS code, to (1 << 2). */
15678 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15680 bfd_boolean micro_to_mips_p
;
15684 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15687 other
= S_GET_OTHER (fixP
->fx_addsy
);
15688 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15689 val
+= fixP
->fx_offset
;
15690 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15691 && !ELF_ST_IS_MICROMIPS (other
));
15692 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15693 != ELF_ST_IS_COMPRESSED (other
));
15696 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15697 to a symbol whose annotation indicates another ISA mode. For absolute
15698 symbols check the ISA bit instead.
15700 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15701 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15702 MIPS symbols and associated with BAL instructions as these instructions
15703 may be converted to JALX by the linker. */
15706 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15708 bfd_boolean absolute_p
;
15709 unsigned long opcode
;
15715 if (mips_ignore_branch_isa
)
15718 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15721 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15722 absolute_p
= bfd_is_abs_section (symsec
);
15724 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15725 other
= S_GET_OTHER (fixP
->fx_addsy
);
15727 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15728 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15729 switch (fixP
->fx_r_type
)
15731 case BFD_RELOC_16_PCREL_S2
:
15732 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15733 && opcode
!= 0x0411);
15734 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15735 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15736 && opcode
!= 0x4060);
15737 case BFD_RELOC_MIPS_21_PCREL_S2
:
15738 case BFD_RELOC_MIPS_26_PCREL_S2
:
15739 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15740 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15741 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15742 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15743 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15744 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15750 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15751 branch instruction pointed to by FIXP is not aligned according to the
15752 branch instruction's immediate field requirement. We need the addend
15753 to preserve the ISA bit and also the sum must not have bit 2 set. We
15754 must explicitly OR in the ISA bit from symbol annotation as the bit
15755 won't be set in the symbol's value then. */
15758 fix_bad_misaligned_branch_p (fixS
*fixP
)
15760 bfd_boolean absolute_p
;
15767 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15770 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15771 absolute_p
= bfd_is_abs_section (symsec
);
15773 val
= S_GET_VALUE (fixP
->fx_addsy
);
15774 other
= S_GET_OTHER (fixP
->fx_addsy
);
15775 off
= fixP
->fx_offset
;
15777 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15778 val
|= ELF_ST_IS_COMPRESSED (other
);
15780 return (val
& 0x3) != isa_bit
;
15783 /* Calculate the relocation target by masking off ISA mode bit before
15784 combining symbol and addend. */
15787 fix_bad_misaligned_address (fixS
*fixP
)
15792 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15793 val
= S_GET_VALUE (fixP
->fx_addsy
);
15794 off
= fixP
->fx_offset
;
15795 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15798 return ((val
& ~isa_mode
) + off
);
15801 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15802 and its calculated value VAL. */
15805 fix_validate_branch (fixS
*fixP
, valueT val
)
15807 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15809 _("branch to misaligned address (0x%lx)"),
15810 (long) (val
+ md_pcrel_from (fixP
)));
15811 else if (fix_bad_cross_mode_branch_p (fixP
))
15812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15813 _("branch to a symbol in another ISA mode"));
15814 else if (fix_bad_misaligned_branch_p (fixP
))
15815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15816 _("branch to misaligned address (0x%lx)"),
15817 (long) fix_bad_misaligned_address (fixP
));
15818 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15820 _("cannot encode misaligned addend "
15821 "in the relocatable field (0x%lx)"),
15822 (long) fixP
->fx_offset
);
15825 /* Apply a fixup to the object file. */
15828 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15831 unsigned long insn
;
15832 reloc_howto_type
*howto
;
15834 if (fixP
->fx_pcrel
)
15835 switch (fixP
->fx_r_type
)
15837 case BFD_RELOC_16_PCREL_S2
:
15838 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15839 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15840 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15841 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15842 case BFD_RELOC_32_PCREL
:
15843 case BFD_RELOC_MIPS_21_PCREL_S2
:
15844 case BFD_RELOC_MIPS_26_PCREL_S2
:
15845 case BFD_RELOC_MIPS_18_PCREL_S3
:
15846 case BFD_RELOC_MIPS_19_PCREL_S2
:
15847 case BFD_RELOC_HI16_S_PCREL
:
15848 case BFD_RELOC_LO16_PCREL
:
15852 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15857 _("PC-relative reference to a different section"));
15861 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15862 that have no MIPS ELF equivalent. */
15863 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15865 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15870 gas_assert (fixP
->fx_size
== 2
15871 || fixP
->fx_size
== 4
15872 || fixP
->fx_r_type
== BFD_RELOC_8
15873 || fixP
->fx_r_type
== BFD_RELOC_16
15874 || fixP
->fx_r_type
== BFD_RELOC_64
15875 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15876 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15877 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15878 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15879 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15880 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15881 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15883 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15885 /* Don't treat parts of a composite relocation as done. There are two
15888 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15889 should nevertheless be emitted if the first part is.
15891 (2) In normal usage, composite relocations are never assembly-time
15892 constants. The easiest way of dealing with the pathological
15893 exceptions is to generate a relocation against STN_UNDEF and
15894 leave everything up to the linker. */
15895 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15898 switch (fixP
->fx_r_type
)
15900 case BFD_RELOC_MIPS_TLS_GD
:
15901 case BFD_RELOC_MIPS_TLS_LDM
:
15902 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15903 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15904 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15905 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15906 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15907 case BFD_RELOC_MIPS_TLS_TPREL32
:
15908 case BFD_RELOC_MIPS_TLS_TPREL64
:
15909 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15910 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15911 case BFD_RELOC_MICROMIPS_TLS_GD
:
15912 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15913 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15914 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15915 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15916 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15917 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15918 case BFD_RELOC_MIPS16_TLS_GD
:
15919 case BFD_RELOC_MIPS16_TLS_LDM
:
15920 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15921 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15922 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15923 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15924 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15925 if (fixP
->fx_addsy
)
15926 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15929 _("TLS relocation against a constant"));
15932 case BFD_RELOC_MIPS_JMP
:
15933 case BFD_RELOC_MIPS16_JMP
:
15934 case BFD_RELOC_MICROMIPS_JMP
:
15938 gas_assert (!fixP
->fx_done
);
15940 /* Shift is 2, unusually, for microMIPS JALX. */
15941 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15942 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15947 if (fix_bad_cross_mode_jump_p (fixP
))
15948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15949 _("jump to a symbol in another ISA mode"));
15950 else if (fix_bad_same_mode_jalx_p (fixP
))
15951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15952 _("JALX to a symbol in the same ISA mode"));
15953 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15955 _("jump to misaligned address (0x%lx)"),
15956 (long) fix_bad_misaligned_address (fixP
));
15957 else if (HAVE_IN_PLACE_ADDENDS
15958 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15960 _("cannot encode misaligned addend "
15961 "in the relocatable field (0x%lx)"),
15962 (long) fixP
->fx_offset
);
15964 /* Fall through. */
15966 case BFD_RELOC_MIPS_SHIFT5
:
15967 case BFD_RELOC_MIPS_SHIFT6
:
15968 case BFD_RELOC_MIPS_GOT_DISP
:
15969 case BFD_RELOC_MIPS_GOT_PAGE
:
15970 case BFD_RELOC_MIPS_GOT_OFST
:
15971 case BFD_RELOC_MIPS_SUB
:
15972 case BFD_RELOC_MIPS_INSERT_A
:
15973 case BFD_RELOC_MIPS_INSERT_B
:
15974 case BFD_RELOC_MIPS_DELETE
:
15975 case BFD_RELOC_MIPS_HIGHEST
:
15976 case BFD_RELOC_MIPS_HIGHER
:
15977 case BFD_RELOC_MIPS_SCN_DISP
:
15978 case BFD_RELOC_MIPS_REL16
:
15979 case BFD_RELOC_MIPS_RELGOT
:
15980 case BFD_RELOC_MIPS_JALR
:
15981 case BFD_RELOC_HI16
:
15982 case BFD_RELOC_HI16_S
:
15983 case BFD_RELOC_LO16
:
15984 case BFD_RELOC_GPREL16
:
15985 case BFD_RELOC_MIPS_LITERAL
:
15986 case BFD_RELOC_MIPS_CALL16
:
15987 case BFD_RELOC_MIPS_GOT16
:
15988 case BFD_RELOC_GPREL32
:
15989 case BFD_RELOC_MIPS_GOT_HI16
:
15990 case BFD_RELOC_MIPS_GOT_LO16
:
15991 case BFD_RELOC_MIPS_CALL_HI16
:
15992 case BFD_RELOC_MIPS_CALL_LO16
:
15993 case BFD_RELOC_HI16_S_PCREL
:
15994 case BFD_RELOC_LO16_PCREL
:
15995 case BFD_RELOC_MIPS16_GPREL
:
15996 case BFD_RELOC_MIPS16_GOT16
:
15997 case BFD_RELOC_MIPS16_CALL16
:
15998 case BFD_RELOC_MIPS16_HI16
:
15999 case BFD_RELOC_MIPS16_HI16_S
:
16000 case BFD_RELOC_MIPS16_LO16
:
16001 case BFD_RELOC_MICROMIPS_GOT_DISP
:
16002 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
16003 case BFD_RELOC_MICROMIPS_GOT_OFST
:
16004 case BFD_RELOC_MICROMIPS_SUB
:
16005 case BFD_RELOC_MICROMIPS_HIGHEST
:
16006 case BFD_RELOC_MICROMIPS_HIGHER
:
16007 case BFD_RELOC_MICROMIPS_SCN_DISP
:
16008 case BFD_RELOC_MICROMIPS_JALR
:
16009 case BFD_RELOC_MICROMIPS_HI16
:
16010 case BFD_RELOC_MICROMIPS_HI16_S
:
16011 case BFD_RELOC_MICROMIPS_LO16
:
16012 case BFD_RELOC_MICROMIPS_GPREL16
:
16013 case BFD_RELOC_MICROMIPS_LITERAL
:
16014 case BFD_RELOC_MICROMIPS_CALL16
:
16015 case BFD_RELOC_MICROMIPS_GOT16
:
16016 case BFD_RELOC_MICROMIPS_GOT_HI16
:
16017 case BFD_RELOC_MICROMIPS_GOT_LO16
:
16018 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16019 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16020 case BFD_RELOC_MIPS_EH
:
16025 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16027 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16028 if (mips16_reloc_p (fixP
->fx_r_type
))
16029 insn
|= mips16_immed_extend (value
, 16);
16031 insn
|= (value
& 0xffff);
16032 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16036 _("unsupported constant in relocation"));
16041 /* This is handled like BFD_RELOC_32, but we output a sign
16042 extended value if we are only 32 bits. */
16045 if (8 <= sizeof (valueT
))
16046 md_number_to_chars (buf
, *valP
, 8);
16051 if ((*valP
& 0x80000000) != 0)
16055 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16056 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16061 case BFD_RELOC_RVA
:
16063 case BFD_RELOC_32_PCREL
:
16066 /* If we are deleting this reloc entry, we must fill in the
16067 value now. This can happen if we have a .word which is not
16068 resolved when it appears but is later defined. */
16070 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16073 case BFD_RELOC_MIPS_21_PCREL_S2
:
16074 fix_validate_branch (fixP
, *valP
);
16075 if (!fixP
->fx_done
)
16078 if (*valP
+ 0x400000 <= 0x7fffff)
16080 insn
= read_insn (buf
);
16081 insn
|= (*valP
>> 2) & 0x1fffff;
16082 write_insn (buf
, insn
);
16085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16086 _("branch out of range"));
16089 case BFD_RELOC_MIPS_26_PCREL_S2
:
16090 fix_validate_branch (fixP
, *valP
);
16091 if (!fixP
->fx_done
)
16094 if (*valP
+ 0x8000000 <= 0xfffffff)
16096 insn
= read_insn (buf
);
16097 insn
|= (*valP
>> 2) & 0x3ffffff;
16098 write_insn (buf
, insn
);
16101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16102 _("branch out of range"));
16105 case BFD_RELOC_MIPS_18_PCREL_S3
:
16106 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16108 _("PC-relative access using misaligned symbol (%lx)"),
16109 (long) S_GET_VALUE (fixP
->fx_addsy
));
16110 if ((fixP
->fx_offset
& 0x7) != 0)
16111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16112 _("PC-relative access using misaligned offset (%lx)"),
16113 (long) fixP
->fx_offset
);
16114 if (!fixP
->fx_done
)
16117 if (*valP
+ 0x100000 <= 0x1fffff)
16119 insn
= read_insn (buf
);
16120 insn
|= (*valP
>> 3) & 0x3ffff;
16121 write_insn (buf
, insn
);
16124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16125 _("PC-relative access out of range"));
16128 case BFD_RELOC_MIPS_19_PCREL_S2
:
16129 if ((*valP
& 0x3) != 0)
16130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16131 _("PC-relative access to misaligned address (%lx)"),
16133 if (!fixP
->fx_done
)
16136 if (*valP
+ 0x100000 <= 0x1fffff)
16138 insn
= read_insn (buf
);
16139 insn
|= (*valP
>> 2) & 0x7ffff;
16140 write_insn (buf
, insn
);
16143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16144 _("PC-relative access out of range"));
16147 case BFD_RELOC_16_PCREL_S2
:
16148 fix_validate_branch (fixP
, *valP
);
16150 /* We need to save the bits in the instruction since fixup_segment()
16151 might be deleting the relocation entry (i.e., a branch within
16152 the current segment). */
16153 if (! fixP
->fx_done
)
16156 /* Update old instruction data. */
16157 insn
= read_insn (buf
);
16159 if (*valP
+ 0x20000 <= 0x3ffff)
16161 insn
|= (*valP
>> 2) & 0xffff;
16162 write_insn (buf
, insn
);
16164 else if (fixP
->fx_tcbit2
16166 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16167 && (fixP
->fx_frag
->fr_address
16168 < text_section
->vma
+ bfd_section_size (text_section
))
16169 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16170 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16171 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16173 /* The branch offset is too large. If this is an
16174 unconditional branch, and we are not generating PIC code,
16175 we can convert it to an absolute jump instruction. */
16176 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16177 insn
= 0x0c000000; /* jal */
16179 insn
= 0x08000000; /* j */
16180 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16182 fixP
->fx_addsy
= section_symbol (text_section
);
16183 *valP
+= md_pcrel_from (fixP
);
16184 write_insn (buf
, insn
);
16188 /* If we got here, we have branch-relaxation disabled,
16189 and there's nothing we can do to fix this instruction
16190 without turning it into a longer sequence. */
16191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16192 _("branch out of range"));
16196 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16197 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16198 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16199 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16200 gas_assert (!fixP
->fx_done
);
16201 if (fix_bad_cross_mode_branch_p (fixP
))
16202 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16203 _("branch to a symbol in another ISA mode"));
16204 else if (fixP
->fx_addsy
16205 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16206 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16207 && (fixP
->fx_offset
& 0x1) != 0)
16208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16209 _("branch to misaligned address (0x%lx)"),
16210 (long) fix_bad_misaligned_address (fixP
));
16211 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16213 _("cannot encode misaligned addend "
16214 "in the relocatable field (0x%lx)"),
16215 (long) fixP
->fx_offset
);
16218 case BFD_RELOC_VTABLE_INHERIT
:
16221 && !S_IS_DEFINED (fixP
->fx_addsy
)
16222 && !S_IS_WEAK (fixP
->fx_addsy
))
16223 S_SET_WEAK (fixP
->fx_addsy
);
16226 case BFD_RELOC_NONE
:
16227 case BFD_RELOC_VTABLE_ENTRY
:
16235 /* Remember value for tc_gen_reloc. */
16236 fixP
->fx_addnumber
= *valP
;
16246 c
= get_symbol_name (&name
);
16247 p
= (symbolS
*) symbol_find_or_make (name
);
16248 (void) restore_line_pointer (c
);
16252 /* Align the current frag to a given power of two. If a particular
16253 fill byte should be used, FILL points to an integer that contains
16254 that byte, otherwise FILL is null.
16256 This function used to have the comment:
16258 The MIPS assembler also automatically adjusts any preceding label.
16260 The implementation therefore applied the adjustment to a maximum of
16261 one label. However, other label adjustments are applied to batches
16262 of labels, and adjusting just one caused problems when new labels
16263 were added for the sake of debugging or unwind information.
16264 We therefore adjust all preceding labels (given as LABELS) instead. */
16267 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16269 mips_emit_delays ();
16270 mips_record_compressed_mode ();
16271 if (fill
== NULL
&& subseg_text_p (now_seg
))
16272 frag_align_code (to
, 0);
16274 frag_align (to
, fill
? *fill
: 0, 0);
16275 record_alignment (now_seg
, to
);
16276 mips_move_labels (labels
, subseg_text_p (now_seg
));
16279 /* Align to a given power of two. .align 0 turns off the automatic
16280 alignment used by the data creating pseudo-ops. */
16283 s_align (int x ATTRIBUTE_UNUSED
)
16285 int temp
, fill_value
, *fill_ptr
;
16286 long max_alignment
= 28;
16288 /* o Note that the assembler pulls down any immediately preceding label
16289 to the aligned address.
16290 o It's not documented but auto alignment is reinstated by
16291 a .align pseudo instruction.
16292 o Note also that after auto alignment is turned off the mips assembler
16293 issues an error on attempt to assemble an improperly aligned data item.
16296 temp
= get_absolute_expression ();
16297 if (temp
> max_alignment
)
16298 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16301 as_warn (_("alignment negative, 0 assumed"));
16304 if (*input_line_pointer
== ',')
16306 ++input_line_pointer
;
16307 fill_value
= get_absolute_expression ();
16308 fill_ptr
= &fill_value
;
16314 segment_info_type
*si
= seg_info (now_seg
);
16315 struct insn_label_list
*l
= si
->label_list
;
16316 /* Auto alignment should be switched on by next section change. */
16318 mips_align (temp
, fill_ptr
, l
);
16325 demand_empty_rest_of_line ();
16329 s_change_sec (int sec
)
16333 /* The ELF backend needs to know that we are changing sections, so
16334 that .previous works correctly. We could do something like check
16335 for an obj_section_change_hook macro, but that might be confusing
16336 as it would not be appropriate to use it in the section changing
16337 functions in read.c, since obj-elf.c intercepts those. FIXME:
16338 This should be cleaner, somehow. */
16339 obj_elf_section_change_hook ();
16341 mips_emit_delays ();
16352 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16353 demand_empty_rest_of_line ();
16357 seg
= subseg_new (RDATA_SECTION_NAME
,
16358 (subsegT
) get_absolute_expression ());
16359 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16360 | SEC_RELOC
| SEC_DATA
));
16361 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16362 record_alignment (seg
, 4);
16363 demand_empty_rest_of_line ();
16367 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16368 bfd_set_section_flags (seg
,
16369 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16370 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16371 record_alignment (seg
, 4);
16372 demand_empty_rest_of_line ();
16376 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16377 bfd_set_section_flags (seg
, SEC_ALLOC
);
16378 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16379 record_alignment (seg
, 4);
16380 demand_empty_rest_of_line ();
16388 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16391 char *section_name
;
16396 int section_entry_size
;
16397 int section_alignment
;
16399 saved_ilp
= input_line_pointer
;
16400 endc
= get_symbol_name (§ion_name
);
16401 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16403 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16405 /* Do we have .section Name<,"flags">? */
16406 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16408 /* Just after name is now '\0'. */
16409 (void) restore_line_pointer (endc
);
16410 input_line_pointer
= saved_ilp
;
16411 obj_elf_section (ignore
);
16415 section_name
= xstrdup (section_name
);
16416 c
= restore_line_pointer (endc
);
16418 input_line_pointer
++;
16420 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16422 section_type
= get_absolute_expression ();
16426 if (*input_line_pointer
++ == ',')
16427 section_flag
= get_absolute_expression ();
16431 if (*input_line_pointer
++ == ',')
16432 section_entry_size
= get_absolute_expression ();
16434 section_entry_size
= 0;
16436 if (*input_line_pointer
++ == ',')
16437 section_alignment
= get_absolute_expression ();
16439 section_alignment
= 0;
16441 /* FIXME: really ignore? */
16442 (void) section_alignment
;
16444 /* When using the generic form of .section (as implemented by obj-elf.c),
16445 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16446 traditionally had to fall back on the more common @progbits instead.
16448 There's nothing really harmful in this, since bfd will correct
16449 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16450 means that, for backwards compatibility, the special_section entries
16451 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16453 Even so, we shouldn't force users of the MIPS .section syntax to
16454 incorrectly label the sections as SHT_PROGBITS. The best compromise
16455 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16456 generic type-checking code. */
16457 if (section_type
== SHT_MIPS_DWARF
)
16458 section_type
= SHT_PROGBITS
;
16460 obj_elf_change_section (section_name
, section_type
, section_flag
,
16461 section_entry_size
, 0, 0, 0);
16463 if (now_seg
->name
!= section_name
)
16464 free (section_name
);
16468 mips_enable_auto_align (void)
16474 s_cons (int log_size
)
16476 segment_info_type
*si
= seg_info (now_seg
);
16477 struct insn_label_list
*l
= si
->label_list
;
16479 mips_emit_delays ();
16480 if (log_size
> 0 && auto_align
)
16481 mips_align (log_size
, 0, l
);
16482 cons (1 << log_size
);
16483 mips_clear_insn_labels ();
16487 s_float_cons (int type
)
16489 segment_info_type
*si
= seg_info (now_seg
);
16490 struct insn_label_list
*l
= si
->label_list
;
16492 mips_emit_delays ();
16497 mips_align (3, 0, l
);
16499 mips_align (2, 0, l
);
16503 mips_clear_insn_labels ();
16506 /* Handle .globl. We need to override it because on Irix 5 you are
16509 where foo is an undefined symbol, to mean that foo should be
16510 considered to be the address of a function. */
16513 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16521 c
= get_symbol_name (&name
);
16522 symbolP
= symbol_find_or_make (name
);
16523 S_SET_EXTERNAL (symbolP
);
16525 *input_line_pointer
= c
;
16526 SKIP_WHITESPACE_AFTER_NAME ();
16528 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16529 && (*input_line_pointer
!= ','))
16534 c
= get_symbol_name (&secname
);
16535 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16537 as_bad (_("%s: no such section"), secname
);
16538 (void) restore_line_pointer (c
);
16540 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16541 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16544 c
= *input_line_pointer
;
16547 input_line_pointer
++;
16548 SKIP_WHITESPACE ();
16549 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16555 demand_empty_rest_of_line ();
16559 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16560 any undefined non-function symbol to STT_OBJECT. We try to be
16561 compatible, since newer Irix 5 and 6 linkers care. */
16564 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16566 /* This late in assembly we can set BSF_OBJECT indiscriminately
16567 and let elf.c:swap_out_syms sort out the symbol type. */
16568 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16569 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16570 || !S_IS_DEFINED (symp
))
16571 *flags
|= BSF_OBJECT
;
16576 s_option (int x ATTRIBUTE_UNUSED
)
16581 c
= get_symbol_name (&opt
);
16585 /* FIXME: What does this mean? */
16587 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16591 i
= atoi (opt
+ 3);
16592 if (i
!= 0 && i
!= 2)
16593 as_bad (_(".option pic%d not supported"), i
);
16594 else if (mips_pic
== VXWORKS_PIC
)
16595 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16600 mips_pic
= SVR4_PIC
;
16601 mips_abicalls
= TRUE
;
16604 if (mips_pic
== SVR4_PIC
)
16606 if (g_switch_seen
&& g_switch_value
!= 0)
16607 as_warn (_("-G may not be used with SVR4 PIC code"));
16608 g_switch_value
= 0;
16609 bfd_set_gp_size (stdoutput
, 0);
16613 as_warn (_("unrecognized option \"%s\""), opt
);
16615 (void) restore_line_pointer (c
);
16616 demand_empty_rest_of_line ();
16619 /* This structure is used to hold a stack of .set values. */
16621 struct mips_option_stack
16623 struct mips_option_stack
*next
;
16624 struct mips_set_options options
;
16627 static struct mips_option_stack
*mips_opts_stack
;
16629 /* Return status for .set/.module option handling. */
16631 enum code_option_type
16633 /* Unrecognized option. */
16634 OPTION_TYPE_BAD
= -1,
16636 /* Ordinary option. */
16637 OPTION_TYPE_NORMAL
,
16639 /* ISA changing option. */
16643 /* Handle common .set/.module options. Return status indicating option
16646 static enum code_option_type
16647 parse_code_option (char * name
)
16649 bfd_boolean isa_set
= FALSE
;
16650 const struct mips_ase
*ase
;
16652 if (strncmp (name
, "at=", 3) == 0)
16654 char *s
= name
+ 3;
16656 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16657 as_bad (_("unrecognized register name `%s'"), s
);
16659 else if (strcmp (name
, "at") == 0)
16660 mips_opts
.at
= ATREG
;
16661 else if (strcmp (name
, "noat") == 0)
16662 mips_opts
.at
= ZERO
;
16663 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16664 mips_opts
.nomove
= 0;
16665 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16666 mips_opts
.nomove
= 1;
16667 else if (strcmp (name
, "bopt") == 0)
16668 mips_opts
.nobopt
= 0;
16669 else if (strcmp (name
, "nobopt") == 0)
16670 mips_opts
.nobopt
= 1;
16671 else if (strcmp (name
, "gp=32") == 0)
16673 else if (strcmp (name
, "gp=64") == 0)
16675 else if (strcmp (name
, "fp=32") == 0)
16677 else if (strcmp (name
, "fp=xx") == 0)
16679 else if (strcmp (name
, "fp=64") == 0)
16681 else if (strcmp (name
, "softfloat") == 0)
16682 mips_opts
.soft_float
= 1;
16683 else if (strcmp (name
, "hardfloat") == 0)
16684 mips_opts
.soft_float
= 0;
16685 else if (strcmp (name
, "singlefloat") == 0)
16686 mips_opts
.single_float
= 1;
16687 else if (strcmp (name
, "doublefloat") == 0)
16688 mips_opts
.single_float
= 0;
16689 else if (strcmp (name
, "nooddspreg") == 0)
16690 mips_opts
.oddspreg
= 0;
16691 else if (strcmp (name
, "oddspreg") == 0)
16692 mips_opts
.oddspreg
= 1;
16693 else if (strcmp (name
, "mips16") == 0
16694 || strcmp (name
, "MIPS-16") == 0)
16695 mips_opts
.mips16
= 1;
16696 else if (strcmp (name
, "nomips16") == 0
16697 || strcmp (name
, "noMIPS-16") == 0)
16698 mips_opts
.mips16
= 0;
16699 else if (strcmp (name
, "micromips") == 0)
16700 mips_opts
.micromips
= 1;
16701 else if (strcmp (name
, "nomicromips") == 0)
16702 mips_opts
.micromips
= 0;
16703 else if (name
[0] == 'n'
16705 && (ase
= mips_lookup_ase (name
+ 2)))
16706 mips_set_ase (ase
, &mips_opts
, FALSE
);
16707 else if ((ase
= mips_lookup_ase (name
)))
16708 mips_set_ase (ase
, &mips_opts
, TRUE
);
16709 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16711 /* Permit the user to change the ISA and architecture on the fly.
16712 Needless to say, misuse can cause serious problems. */
16713 if (strncmp (name
, "arch=", 5) == 0)
16715 const struct mips_cpu_info
*p
;
16717 p
= mips_parse_cpu ("internal use", name
+ 5);
16719 as_bad (_("unknown architecture %s"), name
+ 5);
16722 mips_opts
.arch
= p
->cpu
;
16723 mips_opts
.isa
= p
->isa
;
16725 mips_opts
.init_ase
= p
->ase
;
16728 else if (strncmp (name
, "mips", 4) == 0)
16730 const struct mips_cpu_info
*p
;
16732 p
= mips_parse_cpu ("internal use", name
);
16734 as_bad (_("unknown ISA level %s"), name
+ 4);
16737 mips_opts
.arch
= p
->cpu
;
16738 mips_opts
.isa
= p
->isa
;
16740 mips_opts
.init_ase
= p
->ase
;
16744 as_bad (_("unknown ISA or architecture %s"), name
);
16746 else if (strcmp (name
, "autoextend") == 0)
16747 mips_opts
.noautoextend
= 0;
16748 else if (strcmp (name
, "noautoextend") == 0)
16749 mips_opts
.noautoextend
= 1;
16750 else if (strcmp (name
, "insn32") == 0)
16751 mips_opts
.insn32
= TRUE
;
16752 else if (strcmp (name
, "noinsn32") == 0)
16753 mips_opts
.insn32
= FALSE
;
16754 else if (strcmp (name
, "sym32") == 0)
16755 mips_opts
.sym32
= TRUE
;
16756 else if (strcmp (name
, "nosym32") == 0)
16757 mips_opts
.sym32
= FALSE
;
16759 return OPTION_TYPE_BAD
;
16761 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16764 /* Handle the .set pseudo-op. */
16767 s_mipsset (int x ATTRIBUTE_UNUSED
)
16769 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16770 char *name
= input_line_pointer
, ch
;
16772 file_mips_check_options ();
16774 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16775 ++input_line_pointer
;
16776 ch
= *input_line_pointer
;
16777 *input_line_pointer
= '\0';
16779 if (strchr (name
, ','))
16781 /* Generic ".set" directive; use the generic handler. */
16782 *input_line_pointer
= ch
;
16783 input_line_pointer
= name
;
16788 if (strcmp (name
, "reorder") == 0)
16790 if (mips_opts
.noreorder
)
16793 else if (strcmp (name
, "noreorder") == 0)
16795 if (!mips_opts
.noreorder
)
16796 start_noreorder ();
16798 else if (strcmp (name
, "macro") == 0)
16799 mips_opts
.warn_about_macros
= 0;
16800 else if (strcmp (name
, "nomacro") == 0)
16802 if (mips_opts
.noreorder
== 0)
16803 as_bad (_("`noreorder' must be set before `nomacro'"));
16804 mips_opts
.warn_about_macros
= 1;
16806 else if (strcmp (name
, "gp=default") == 0)
16807 mips_opts
.gp
= file_mips_opts
.gp
;
16808 else if (strcmp (name
, "fp=default") == 0)
16809 mips_opts
.fp
= file_mips_opts
.fp
;
16810 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16812 mips_opts
.isa
= file_mips_opts
.isa
;
16813 mips_opts
.arch
= file_mips_opts
.arch
;
16814 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16815 mips_opts
.gp
= file_mips_opts
.gp
;
16816 mips_opts
.fp
= file_mips_opts
.fp
;
16818 else if (strcmp (name
, "push") == 0)
16820 struct mips_option_stack
*s
;
16822 s
= XNEW (struct mips_option_stack
);
16823 s
->next
= mips_opts_stack
;
16824 s
->options
= mips_opts
;
16825 mips_opts_stack
= s
;
16827 else if (strcmp (name
, "pop") == 0)
16829 struct mips_option_stack
*s
;
16831 s
= mips_opts_stack
;
16833 as_bad (_(".set pop with no .set push"));
16836 /* If we're changing the reorder mode we need to handle
16837 delay slots correctly. */
16838 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16839 start_noreorder ();
16840 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16843 mips_opts
= s
->options
;
16844 mips_opts_stack
= s
->next
;
16850 type
= parse_code_option (name
);
16851 if (type
== OPTION_TYPE_BAD
)
16852 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16855 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16856 registers based on what is supported by the arch/cpu. */
16857 if (type
== OPTION_TYPE_ISA
)
16859 switch (mips_opts
.isa
)
16864 /* MIPS I cannot support FPXX. */
16866 /* fall-through. */
16873 if (mips_opts
.fp
!= 0)
16889 if (mips_opts
.fp
!= 0)
16891 if (mips_opts
.arch
== CPU_R5900
)
16898 as_bad (_("unknown ISA level %s"), name
+ 4);
16903 mips_check_options (&mips_opts
, FALSE
);
16905 mips_check_isa_supports_ases ();
16906 *input_line_pointer
= ch
;
16907 demand_empty_rest_of_line ();
16910 /* Handle the .module pseudo-op. */
16913 s_module (int ignore ATTRIBUTE_UNUSED
)
16915 char *name
= input_line_pointer
, ch
;
16917 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16918 ++input_line_pointer
;
16919 ch
= *input_line_pointer
;
16920 *input_line_pointer
= '\0';
16922 if (!file_mips_opts_checked
)
16924 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16925 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16927 /* Update module level settings from mips_opts. */
16928 file_mips_opts
= mips_opts
;
16931 as_bad (_(".module is not permitted after generating code"));
16933 *input_line_pointer
= ch
;
16934 demand_empty_rest_of_line ();
16937 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16938 .option pic2. It means to generate SVR4 PIC calls. */
16941 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16943 mips_pic
= SVR4_PIC
;
16944 mips_abicalls
= TRUE
;
16946 if (g_switch_seen
&& g_switch_value
!= 0)
16947 as_warn (_("-G may not be used with SVR4 PIC code"));
16948 g_switch_value
= 0;
16950 bfd_set_gp_size (stdoutput
, 0);
16951 demand_empty_rest_of_line ();
16954 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16955 PIC code. It sets the $gp register for the function based on the
16956 function address, which is in the register named in the argument.
16957 This uses a relocation against _gp_disp, which is handled specially
16958 by the linker. The result is:
16959 lui $gp,%hi(_gp_disp)
16960 addiu $gp,$gp,%lo(_gp_disp)
16961 addu $gp,$gp,.cpload argument
16962 The .cpload argument is normally $25 == $t9.
16964 The -mno-shared option changes this to:
16965 lui $gp,%hi(__gnu_local_gp)
16966 addiu $gp,$gp,%lo(__gnu_local_gp)
16967 and the argument is ignored. This saves an instruction, but the
16968 resulting code is not position independent; it uses an absolute
16969 address for __gnu_local_gp. Thus code assembled with -mno-shared
16970 can go into an ordinary executable, but not into a shared library. */
16973 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16979 file_mips_check_options ();
16981 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16982 .cpload is ignored. */
16983 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16989 if (mips_opts
.mips16
)
16991 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16992 ignore_rest_of_line ();
16996 /* .cpload should be in a .set noreorder section. */
16997 if (mips_opts
.noreorder
== 0)
16998 as_warn (_(".cpload not in noreorder section"));
17000 reg
= tc_get_register (0);
17002 /* If we need to produce a 64-bit address, we are better off using
17003 the default instruction sequence. */
17004 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
17006 ex
.X_op
= O_symbol
;
17007 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
17009 ex
.X_op_symbol
= NULL
;
17010 ex
.X_add_number
= 0;
17012 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17013 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17015 mips_mark_labels ();
17016 mips_assembling_insn
= TRUE
;
17019 macro_build_lui (&ex
, mips_gp_register
);
17020 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17021 mips_gp_register
, BFD_RELOC_LO16
);
17023 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17024 mips_gp_register
, reg
);
17027 mips_assembling_insn
= FALSE
;
17028 demand_empty_rest_of_line ();
17031 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17032 .cpsetup $reg1, offset|$reg2, label
17034 If offset is given, this results in:
17035 sd $gp, offset($sp)
17036 lui $gp, %hi(%neg(%gp_rel(label)))
17037 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17038 daddu $gp, $gp, $reg1
17040 If $reg2 is given, this results in:
17042 lui $gp, %hi(%neg(%gp_rel(label)))
17043 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17044 daddu $gp, $gp, $reg1
17045 $reg1 is normally $25 == $t9.
17047 The -mno-shared option replaces the last three instructions with
17049 addiu $gp,$gp,%lo(_gp) */
17052 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17054 expressionS ex_off
;
17055 expressionS ex_sym
;
17058 file_mips_check_options ();
17060 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17061 We also need NewABI support. */
17062 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17068 if (mips_opts
.mips16
)
17070 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17071 ignore_rest_of_line ();
17075 reg1
= tc_get_register (0);
17076 SKIP_WHITESPACE ();
17077 if (*input_line_pointer
!= ',')
17079 as_bad (_("missing argument separator ',' for .cpsetup"));
17083 ++input_line_pointer
;
17084 SKIP_WHITESPACE ();
17085 if (*input_line_pointer
== '$')
17087 mips_cpreturn_register
= tc_get_register (0);
17088 mips_cpreturn_offset
= -1;
17092 mips_cpreturn_offset
= get_absolute_expression ();
17093 mips_cpreturn_register
= -1;
17095 SKIP_WHITESPACE ();
17096 if (*input_line_pointer
!= ',')
17098 as_bad (_("missing argument separator ',' for .cpsetup"));
17102 ++input_line_pointer
;
17103 SKIP_WHITESPACE ();
17104 expression (&ex_sym
);
17106 mips_mark_labels ();
17107 mips_assembling_insn
= TRUE
;
17110 if (mips_cpreturn_register
== -1)
17112 ex_off
.X_op
= O_constant
;
17113 ex_off
.X_add_symbol
= NULL
;
17114 ex_off
.X_op_symbol
= NULL
;
17115 ex_off
.X_add_number
= mips_cpreturn_offset
;
17117 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17118 BFD_RELOC_LO16
, SP
);
17121 move_register (mips_cpreturn_register
, mips_gp_register
);
17123 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17125 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17126 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17129 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17130 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17131 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17133 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17134 mips_gp_register
, reg1
);
17140 ex
.X_op
= O_symbol
;
17141 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17142 ex
.X_op_symbol
= NULL
;
17143 ex
.X_add_number
= 0;
17145 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17146 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17148 macro_build_lui (&ex
, mips_gp_register
);
17149 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17150 mips_gp_register
, BFD_RELOC_LO16
);
17155 mips_assembling_insn
= FALSE
;
17156 demand_empty_rest_of_line ();
17160 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17162 file_mips_check_options ();
17164 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17165 .cplocal is ignored. */
17166 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17172 if (mips_opts
.mips16
)
17174 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17175 ignore_rest_of_line ();
17179 mips_gp_register
= tc_get_register (0);
17180 demand_empty_rest_of_line ();
17183 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17184 offset from $sp. The offset is remembered, and after making a PIC
17185 call $gp is restored from that location. */
17188 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17192 file_mips_check_options ();
17194 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17195 .cprestore is ignored. */
17196 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17202 if (mips_opts
.mips16
)
17204 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17205 ignore_rest_of_line ();
17209 mips_cprestore_offset
= get_absolute_expression ();
17210 mips_cprestore_valid
= 1;
17212 ex
.X_op
= O_constant
;
17213 ex
.X_add_symbol
= NULL
;
17214 ex
.X_op_symbol
= NULL
;
17215 ex
.X_add_number
= mips_cprestore_offset
;
17217 mips_mark_labels ();
17218 mips_assembling_insn
= TRUE
;
17221 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17222 SP
, HAVE_64BIT_ADDRESSES
);
17225 mips_assembling_insn
= FALSE
;
17226 demand_empty_rest_of_line ();
17229 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17230 was given in the preceding .cpsetup, it results in:
17231 ld $gp, offset($sp)
17233 If a register $reg2 was given there, it results in:
17234 or $gp, $reg2, $0 */
17237 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17241 file_mips_check_options ();
17243 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17244 We also need NewABI support. */
17245 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17251 if (mips_opts
.mips16
)
17253 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17254 ignore_rest_of_line ();
17258 mips_mark_labels ();
17259 mips_assembling_insn
= TRUE
;
17262 if (mips_cpreturn_register
== -1)
17264 ex
.X_op
= O_constant
;
17265 ex
.X_add_symbol
= NULL
;
17266 ex
.X_op_symbol
= NULL
;
17267 ex
.X_add_number
= mips_cpreturn_offset
;
17269 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17272 move_register (mips_gp_register
, mips_cpreturn_register
);
17276 mips_assembling_insn
= FALSE
;
17277 demand_empty_rest_of_line ();
17280 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17281 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17282 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17283 debug information or MIPS16 TLS. */
17286 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17287 bfd_reloc_code_real_type rtype
)
17294 if (ex
.X_op
!= O_symbol
)
17296 as_bad (_("unsupported use of %s"), dirstr
);
17297 ignore_rest_of_line ();
17300 p
= frag_more (bytes
);
17301 md_number_to_chars (p
, 0, bytes
);
17302 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17303 demand_empty_rest_of_line ();
17304 mips_clear_insn_labels ();
17307 /* Handle .dtprelword. */
17310 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17312 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17315 /* Handle .dtpreldword. */
17318 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17320 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17323 /* Handle .tprelword. */
17326 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17328 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17331 /* Handle .tpreldword. */
17334 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17336 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17339 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17340 code. It sets the offset to use in gp_rel relocations. */
17343 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17345 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17346 We also need NewABI support. */
17347 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17353 mips_gprel_offset
= get_absolute_expression ();
17355 demand_empty_rest_of_line ();
17358 /* Handle the .gpword pseudo-op. This is used when generating PIC
17359 code. It generates a 32 bit GP relative reloc. */
17362 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17364 segment_info_type
*si
;
17365 struct insn_label_list
*l
;
17369 /* When not generating PIC code, this is treated as .word. */
17370 if (mips_pic
!= SVR4_PIC
)
17376 si
= seg_info (now_seg
);
17377 l
= si
->label_list
;
17378 mips_emit_delays ();
17380 mips_align (2, 0, l
);
17383 mips_clear_insn_labels ();
17385 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17387 as_bad (_("unsupported use of .gpword"));
17388 ignore_rest_of_line ();
17392 md_number_to_chars (p
, 0, 4);
17393 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17394 BFD_RELOC_GPREL32
);
17396 demand_empty_rest_of_line ();
17400 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17402 segment_info_type
*si
;
17403 struct insn_label_list
*l
;
17407 /* When not generating PIC code, this is treated as .dword. */
17408 if (mips_pic
!= SVR4_PIC
)
17414 si
= seg_info (now_seg
);
17415 l
= si
->label_list
;
17416 mips_emit_delays ();
17418 mips_align (3, 0, l
);
17421 mips_clear_insn_labels ();
17423 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17425 as_bad (_("unsupported use of .gpdword"));
17426 ignore_rest_of_line ();
17430 md_number_to_chars (p
, 0, 8);
17431 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17432 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17434 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17435 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17436 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17438 demand_empty_rest_of_line ();
17441 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17442 tables. It generates a R_MIPS_EH reloc. */
17445 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17450 mips_emit_delays ();
17453 mips_clear_insn_labels ();
17455 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17457 as_bad (_("unsupported use of .ehword"));
17458 ignore_rest_of_line ();
17462 md_number_to_chars (p
, 0, 4);
17463 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17464 BFD_RELOC_32_PCREL
);
17466 demand_empty_rest_of_line ();
17469 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17470 tables in SVR4 PIC code. */
17473 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17477 file_mips_check_options ();
17479 /* This is ignored when not generating SVR4 PIC code. */
17480 if (mips_pic
!= SVR4_PIC
)
17486 mips_mark_labels ();
17487 mips_assembling_insn
= TRUE
;
17489 /* Add $gp to the register named as an argument. */
17491 reg
= tc_get_register (0);
17492 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17495 mips_assembling_insn
= FALSE
;
17496 demand_empty_rest_of_line ();
17499 /* Handle the .insn pseudo-op. This marks instruction labels in
17500 mips16/micromips mode. This permits the linker to handle them specially,
17501 such as generating jalx instructions when needed. We also make
17502 them odd for the duration of the assembly, in order to generate the
17503 right sort of code. We will make them even in the adjust_symtab
17504 routine, while leaving them marked. This is convenient for the
17505 debugger and the disassembler. The linker knows to make them odd
17509 s_insn (int ignore ATTRIBUTE_UNUSED
)
17511 file_mips_check_options ();
17512 file_ase_mips16
|= mips_opts
.mips16
;
17513 file_ase_micromips
|= mips_opts
.micromips
;
17515 mips_mark_labels ();
17517 demand_empty_rest_of_line ();
17520 /* Handle the .nan pseudo-op. */
17523 s_nan (int ignore ATTRIBUTE_UNUSED
)
17525 static const char str_legacy
[] = "legacy";
17526 static const char str_2008
[] = "2008";
17529 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17531 if (i
== sizeof (str_2008
) - 1
17532 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17534 else if (i
== sizeof (str_legacy
) - 1
17535 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17537 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17540 as_bad (_("`%s' does not support legacy NaN"),
17541 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17544 as_bad (_("bad .nan directive"));
17546 input_line_pointer
+= i
;
17547 demand_empty_rest_of_line ();
17550 /* Handle a .stab[snd] directive. Ideally these directives would be
17551 implemented in a transparent way, so that removing them would not
17552 have any effect on the generated instructions. However, s_stab
17553 internally changes the section, so in practice we need to decide
17554 now whether the preceding label marks compressed code. We do not
17555 support changing the compression mode of a label after a .stab*
17556 directive, such as in:
17562 so the current mode wins. */
17565 s_mips_stab (int type
)
17567 file_mips_check_options ();
17568 mips_mark_labels ();
17572 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17575 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17582 c
= get_symbol_name (&name
);
17583 symbolP
= symbol_find_or_make (name
);
17584 S_SET_WEAK (symbolP
);
17585 *input_line_pointer
= c
;
17587 SKIP_WHITESPACE_AFTER_NAME ();
17589 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17591 if (S_IS_DEFINED (symbolP
))
17593 as_bad (_("ignoring attempt to redefine symbol %s"),
17594 S_GET_NAME (symbolP
));
17595 ignore_rest_of_line ();
17599 if (*input_line_pointer
== ',')
17601 ++input_line_pointer
;
17602 SKIP_WHITESPACE ();
17606 if (exp
.X_op
!= O_symbol
)
17608 as_bad (_("bad .weakext directive"));
17609 ignore_rest_of_line ();
17612 symbol_set_value_expression (symbolP
, &exp
);
17615 demand_empty_rest_of_line ();
17618 /* Parse a register string into a number. Called from the ECOFF code
17619 to parse .frame. The argument is non-zero if this is the frame
17620 register, so that we can record it in mips_frame_reg. */
17623 tc_get_register (int frame
)
17627 SKIP_WHITESPACE ();
17628 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17632 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17633 mips_frame_reg_valid
= 1;
17634 mips_cprestore_valid
= 0;
17640 md_section_align (asection
*seg
, valueT addr
)
17642 int align
= bfd_section_alignment (seg
);
17644 /* We don't need to align ELF sections to the full alignment.
17645 However, Irix 5 may prefer that we align them at least to a 16
17646 byte boundary. We don't bother to align the sections if we
17647 are targeted for an embedded system. */
17648 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17653 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17656 /* Utility routine, called from above as well. If called while the
17657 input file is still being read, it's only an approximation. (For
17658 example, a symbol may later become defined which appeared to be
17659 undefined earlier.) */
17662 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17667 if (g_switch_value
> 0)
17669 const char *symname
;
17672 /* Find out whether this symbol can be referenced off the $gp
17673 register. It can be if it is smaller than the -G size or if
17674 it is in the .sdata or .sbss section. Certain symbols can
17675 not be referenced off the $gp, although it appears as though
17677 symname
= S_GET_NAME (sym
);
17678 if (symname
!= (const char *) NULL
17679 && (strcmp (symname
, "eprol") == 0
17680 || strcmp (symname
, "etext") == 0
17681 || strcmp (symname
, "_gp") == 0
17682 || strcmp (symname
, "edata") == 0
17683 || strcmp (symname
, "_fbss") == 0
17684 || strcmp (symname
, "_fdata") == 0
17685 || strcmp (symname
, "_ftext") == 0
17686 || strcmp (symname
, "end") == 0
17687 || strcmp (symname
, "_gp_disp") == 0))
17689 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17691 #ifndef NO_ECOFF_DEBUGGING
17692 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17693 && (symbol_get_obj (sym
)->ecoff_extern_size
17694 <= g_switch_value
))
17696 /* We must defer this decision until after the whole
17697 file has been read, since there might be a .extern
17698 after the first use of this symbol. */
17699 || (before_relaxing
17700 #ifndef NO_ECOFF_DEBUGGING
17701 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17703 && S_GET_VALUE (sym
) == 0)
17704 || (S_GET_VALUE (sym
) != 0
17705 && S_GET_VALUE (sym
) <= g_switch_value
)))
17709 const char *segname
;
17711 segname
= segment_name (S_GET_SEGMENT (sym
));
17712 gas_assert (strcmp (segname
, ".lit8") != 0
17713 && strcmp (segname
, ".lit4") != 0);
17714 change
= (strcmp (segname
, ".sdata") != 0
17715 && strcmp (segname
, ".sbss") != 0
17716 && strncmp (segname
, ".sdata.", 7) != 0
17717 && strncmp (segname
, ".sbss.", 6) != 0
17718 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17719 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17724 /* We are not optimizing for the $gp register. */
17729 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17732 pic_need_relax (symbolS
*sym
)
17736 /* Handle the case of a symbol equated to another symbol. */
17737 while (symbol_equated_reloc_p (sym
))
17741 /* It's possible to get a loop here in a badly written program. */
17742 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17748 if (symbol_section_p (sym
))
17751 symsec
= S_GET_SEGMENT (sym
);
17753 /* This must duplicate the test in adjust_reloc_syms. */
17754 return (!bfd_is_und_section (symsec
)
17755 && !bfd_is_abs_section (symsec
)
17756 && !bfd_is_com_section (symsec
)
17757 /* A global or weak symbol is treated as external. */
17758 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17761 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17762 convert a section-relative value VAL to the equivalent PC-relative
17766 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17767 offsetT val
, long stretch
)
17772 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17774 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17776 /* If the relax_marker of the symbol fragment differs from the
17777 relax_marker of this fragment, we have not yet adjusted the
17778 symbol fragment fr_address. We want to add in STRETCH in
17779 order to get a better estimate of the address. This
17780 particularly matters because of the shift bits. */
17781 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17785 /* Adjust stretch for any alignment frag. Note that if have
17786 been expanding the earlier code, the symbol may be
17787 defined in what appears to be an earlier frag. FIXME:
17788 This doesn't handle the fr_subtype field, which specifies
17789 a maximum number of bytes to skip when doing an
17791 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17793 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17796 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17798 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17807 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17809 /* The base address rules are complicated. The base address of
17810 a branch is the following instruction. The base address of a
17811 PC relative load or add is the instruction itself, but if it
17812 is in a delay slot (in which case it can not be extended) use
17813 the address of the instruction whose delay slot it is in. */
17814 if (pcrel_op
->include_isa_bit
)
17818 /* If we are currently assuming that this frag should be
17819 extended, then the current address is two bytes higher. */
17820 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17823 /* Ignore the low bit in the target, since it will be set
17824 for a text label. */
17827 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17829 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17832 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17837 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17838 extended opcode. SEC is the section the frag is in. */
17841 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17843 const struct mips_int_operand
*operand
;
17848 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17850 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17853 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17854 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17855 operand
= mips16_immed_operand (type
, FALSE
);
17856 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17857 || (operand
->root
.type
== OP_PCREL
17859 : !bfd_is_abs_section (symsec
)))
17862 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17864 if (operand
->root
.type
== OP_PCREL
)
17866 const struct mips_pcrel_operand
*pcrel_op
;
17869 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17872 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17873 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17875 /* If any of the shifted bits are set, we must use an extended
17876 opcode. If the address depends on the size of this
17877 instruction, this can lead to a loop, so we arrange to always
17878 use an extended opcode. */
17879 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17881 fragp
->fr_subtype
=
17882 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17886 /* If we are about to mark a frag as extended because the value
17887 is precisely the next value above maxtiny, then there is a
17888 chance of an infinite loop as in the following code:
17893 In this case when the la is extended, foo is 0x3fc bytes
17894 away, so the la can be shrunk, but then foo is 0x400 away, so
17895 the la must be extended. To avoid this loop, we mark the
17896 frag as extended if it was small, and is about to become
17897 extended with the next value above maxtiny. */
17898 maxtiny
= mips_int_operand_max (operand
);
17899 if (val
== maxtiny
+ (1 << operand
->shift
)
17900 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17902 fragp
->fr_subtype
=
17903 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17908 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17911 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17912 macro expansion. SEC is the section the frag is in. We only
17913 support PC-relative instructions (LA, DLA, LW, LD) here, in
17914 non-PIC code using 32-bit addressing. */
17917 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17919 const struct mips_pcrel_operand
*pcrel_op
;
17920 const struct mips_int_operand
*operand
;
17925 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17927 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17929 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17932 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17938 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17939 if (bfd_is_abs_section (symsec
))
17941 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17943 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17946 operand
= mips16_immed_operand (type
, TRUE
);
17947 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17948 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17949 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17951 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17958 /* Compute the length of a branch sequence, and adjust the
17959 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17960 worst-case length is computed, with UPDATE being used to indicate
17961 whether an unconditional (-1), branch-likely (+1) or regular (0)
17962 branch is to be computed. */
17964 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17966 bfd_boolean toofar
;
17970 && S_IS_DEFINED (fragp
->fr_symbol
)
17971 && !S_IS_WEAK (fragp
->fr_symbol
)
17972 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17977 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17979 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17983 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17986 /* If the symbol is not defined or it's in a different segment,
17987 we emit the long sequence. */
17990 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17992 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17993 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17994 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17995 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17996 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
18002 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
18005 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18007 /* Additional space for PIC loading of target address. */
18009 if (mips_opts
.isa
== ISA_MIPS1
)
18010 /* Additional space for $at-stabilizing nop. */
18014 /* If branch is conditional. */
18015 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
18022 /* Get a FRAG's branch instruction delay slot size, either from the
18023 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18024 or SHORT_INSN_SIZE otherwise. */
18027 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
18029 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18032 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
18034 return short_insn_size
;
18037 /* Compute the length of a branch sequence, and adjust the
18038 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18039 worst-case length is computed, with UPDATE being used to indicate
18040 whether an unconditional (-1), or regular (0) branch is to be
18044 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18046 bfd_boolean insn32
= TRUE
;
18047 bfd_boolean nods
= TRUE
;
18048 bfd_boolean pic
= TRUE
;
18049 bfd_boolean al
= TRUE
;
18050 int short_insn_size
;
18051 bfd_boolean toofar
;
18056 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18057 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18058 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18059 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18061 short_insn_size
= insn32
? 4 : 2;
18064 && S_IS_DEFINED (fragp
->fr_symbol
)
18065 && !S_IS_WEAK (fragp
->fr_symbol
)
18066 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18071 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18072 /* Ignore the low bit in the target, since it will be set
18073 for a text label. */
18074 if ((val
& 1) != 0)
18077 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18081 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18084 /* If the symbol is not defined or it's in a different segment,
18085 we emit the long sequence. */
18088 if (fragp
&& update
18089 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18090 fragp
->fr_subtype
= (toofar
18091 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18092 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18097 bfd_boolean compact_known
= fragp
!= NULL
;
18098 bfd_boolean compact
= FALSE
;
18099 bfd_boolean uncond
;
18103 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18104 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18107 uncond
= update
< 0;
18109 /* If label is out of range, we turn branch <br>:
18111 <br> label # 4 bytes
18118 # compact && (!PIC || insn32)
18121 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18122 length
+= short_insn_size
;
18124 /* If assembling PIC code, we further turn:
18130 lw/ld at, %got(label)(gp) # 4 bytes
18131 d/addiu at, %lo(label) # 4 bytes
18132 jr/c at # 2/4 bytes
18135 length
+= 4 + short_insn_size
;
18137 /* Add an extra nop if the jump has no compact form and we need
18138 to fill the delay slot. */
18139 if ((!pic
|| al
) && nods
)
18141 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18142 : short_insn_size
);
18144 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18146 <brneg> 0f # 4 bytes
18147 nop # 2/4 bytes if !compact
18150 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18154 /* Add an extra nop to fill the delay slot. */
18155 gas_assert (fragp
);
18156 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18162 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18163 bit accordingly. */
18166 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18168 bfd_boolean toofar
;
18171 && S_IS_DEFINED (fragp
->fr_symbol
)
18172 && !S_IS_WEAK (fragp
->fr_symbol
)
18173 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18179 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18180 /* Ignore the low bit in the target, since it will be set
18181 for a text label. */
18182 if ((val
& 1) != 0)
18185 /* Assume this is a 2-byte branch. */
18186 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18188 /* We try to avoid the infinite loop by not adding 2 more bytes for
18193 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18195 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18196 else if (type
== 'E')
18197 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18202 /* If the symbol is not defined or it's in a different segment,
18203 we emit a normal 32-bit branch. */
18206 if (fragp
&& update
18207 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18209 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18210 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18218 /* Estimate the size of a frag before relaxing. Unless this is the
18219 mips16, we are not really relaxing here, and the final size is
18220 encoded in the subtype information. For the mips16, we have to
18221 decide whether we are using an extended opcode or not. */
18224 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18228 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18231 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18233 return fragp
->fr_var
;
18236 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18238 /* We don't want to modify the EXTENDED bit here; it might get us
18239 into infinite loops. We change it only in mips_relax_frag(). */
18240 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18241 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18243 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18246 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18250 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18251 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18252 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18253 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18254 fragp
->fr_var
= length
;
18259 if (mips_pic
== VXWORKS_PIC
)
18260 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18262 else if (RELAX_PIC (fragp
->fr_subtype
))
18263 change
= pic_need_relax (fragp
->fr_symbol
);
18265 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18269 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18270 return -RELAX_FIRST (fragp
->fr_subtype
);
18273 return -RELAX_SECOND (fragp
->fr_subtype
);
18276 /* This is called to see whether a reloc against a defined symbol
18277 should be converted into a reloc against a section. */
18280 mips_fix_adjustable (fixS
*fixp
)
18282 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18283 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18286 if (fixp
->fx_addsy
== NULL
)
18289 /* Allow relocs used for EH tables. */
18290 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18293 /* If symbol SYM is in a mergeable section, relocations of the form
18294 SYM + 0 can usually be made section-relative. The mergeable data
18295 is then identified by the section offset rather than by the symbol.
18297 However, if we're generating REL LO16 relocations, the offset is split
18298 between the LO16 and partnering high part relocation. The linker will
18299 need to recalculate the complete offset in order to correctly identify
18302 The linker has traditionally not looked for the partnering high part
18303 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18304 placed anywhere. Rather than break backwards compatibility by changing
18305 this, it seems better not to force the issue, and instead keep the
18306 original symbol. This will work with either linker behavior. */
18307 if ((lo16_reloc_p (fixp
->fx_r_type
)
18308 || reloc_needs_lo_p (fixp
->fx_r_type
))
18309 && HAVE_IN_PLACE_ADDENDS
18310 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18313 /* There is no place to store an in-place offset for JALR relocations. */
18314 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18317 /* Likewise an in-range offset of limited PC-relative relocations may
18318 overflow the in-place relocatable field if recalculated against the
18319 start address of the symbol's containing section.
18321 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18322 section relative to allow linker relaxations to be performed later on. */
18323 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18324 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18327 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18328 to a floating-point stub. The same is true for non-R_MIPS16_26
18329 relocations against MIPS16 functions; in this case, the stub becomes
18330 the function's canonical address.
18332 Floating-point stubs are stored in unique .mips16.call.* or
18333 .mips16.fn.* sections. If a stub T for function F is in section S,
18334 the first relocation in section S must be against F; this is how the
18335 linker determines the target function. All relocations that might
18336 resolve to T must also be against F. We therefore have the following
18337 restrictions, which are given in an intentionally-redundant way:
18339 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18342 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18343 if that stub might be used.
18345 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18348 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18349 that stub might be used.
18351 There is a further restriction:
18353 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18354 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18355 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18356 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18357 against MIPS16 or microMIPS symbols because we need to keep the
18358 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18359 detection and JAL or BAL to JALX instruction conversion in the
18362 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18363 against a MIPS16 symbol. We deal with (5) by additionally leaving
18364 alone any jump and branch relocations against a microMIPS symbol.
18366 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18367 relocation against some symbol R, no relocation against R may be
18368 reduced. (Note that this deals with (2) as well as (1) because
18369 relocations against global symbols will never be reduced on ELF
18370 targets.) This approach is a little simpler than trying to detect
18371 stub sections, and gives the "all or nothing" per-symbol consistency
18372 that we have for MIPS16 symbols. */
18373 if (fixp
->fx_subsy
== NULL
18374 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18375 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18376 && (jmp_reloc_p (fixp
->fx_r_type
)
18377 || b_reloc_p (fixp
->fx_r_type
)))
18378 || *symbol_get_tc (fixp
->fx_addsy
)))
18384 /* Translate internal representation of relocation info to BFD target
18388 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18390 static arelent
*retval
[4];
18392 bfd_reloc_code_real_type code
;
18394 memset (retval
, 0, sizeof(retval
));
18395 reloc
= retval
[0] = XCNEW (arelent
);
18396 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18397 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18398 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18400 if (fixp
->fx_pcrel
)
18402 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18403 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18404 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18405 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18406 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18407 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18408 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18409 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18410 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18411 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18412 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18413 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18415 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18416 Relocations want only the symbol offset. */
18417 switch (fixp
->fx_r_type
)
18419 case BFD_RELOC_MIPS_18_PCREL_S3
:
18420 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18423 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18427 else if (HAVE_IN_PLACE_ADDENDS
18428 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18429 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18430 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18432 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18433 addend accordingly. */
18434 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18437 reloc
->addend
= fixp
->fx_addnumber
;
18439 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18440 entry to be used in the relocation's section offset. */
18441 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18443 reloc
->address
= reloc
->addend
;
18447 code
= fixp
->fx_r_type
;
18449 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18450 if (reloc
->howto
== NULL
)
18452 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18453 _("cannot represent %s relocation in this object file"
18455 bfd_get_reloc_code_name (code
));
18462 /* Relax a machine dependent frag. This returns the amount by which
18463 the current size of the frag should change. */
18466 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18468 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18470 offsetT old_var
= fragp
->fr_var
;
18472 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18474 return fragp
->fr_var
- old_var
;
18477 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18479 offsetT old_var
= fragp
->fr_var
;
18480 offsetT new_var
= 4;
18482 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18483 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18484 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18485 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18486 fragp
->fr_var
= new_var
;
18488 return new_var
- old_var
;
18491 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18494 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18496 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18498 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18499 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18501 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18503 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18509 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18511 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18513 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18514 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18515 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18517 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18519 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18527 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18529 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18531 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18532 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18533 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18537 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18538 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18545 /* Convert a machine dependent frag. */
18548 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18550 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18553 unsigned long insn
;
18556 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18557 insn
= read_insn (buf
);
18559 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18561 /* We generate a fixup instead of applying it right now
18562 because, if there are linker relaxations, we're going to
18563 need the relocations. */
18564 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18565 fragp
->fr_symbol
, fragp
->fr_offset
,
18566 TRUE
, BFD_RELOC_16_PCREL_S2
);
18567 fixp
->fx_file
= fragp
->fr_file
;
18568 fixp
->fx_line
= fragp
->fr_line
;
18570 buf
= write_insn (buf
, insn
);
18576 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18577 _("relaxed out-of-range branch into a jump"));
18579 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18582 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18584 /* Reverse the branch. */
18585 switch ((insn
>> 28) & 0xf)
18588 if ((insn
& 0xff000000) == 0x47000000
18589 || (insn
& 0xff600000) == 0x45600000)
18591 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18592 reversed by tweaking bit 23. */
18593 insn
^= 0x00800000;
18597 /* bc[0-3][tf]l? instructions can have the condition
18598 reversed by tweaking a single TF bit, and their
18599 opcodes all have 0x4???????. */
18600 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18601 insn
^= 0x00010000;
18606 /* bltz 0x04000000 bgez 0x04010000
18607 bltzal 0x04100000 bgezal 0x04110000 */
18608 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18609 insn
^= 0x00010000;
18613 /* beq 0x10000000 bne 0x14000000
18614 blez 0x18000000 bgtz 0x1c000000 */
18615 insn
^= 0x04000000;
18623 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18625 /* Clear the and-link bit. */
18626 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18628 /* bltzal 0x04100000 bgezal 0x04110000
18629 bltzall 0x04120000 bgezall 0x04130000 */
18630 insn
&= ~0x00100000;
18633 /* Branch over the branch (if the branch was likely) or the
18634 full jump (not likely case). Compute the offset from the
18635 current instruction to branch to. */
18636 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18640 /* How many bytes in instructions we've already emitted? */
18641 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18642 /* How many bytes in instructions from here to the end? */
18643 i
= fragp
->fr_var
- i
;
18645 /* Convert to instruction count. */
18647 /* Branch counts from the next instruction. */
18650 /* Branch over the jump. */
18651 buf
= write_insn (buf
, insn
);
18654 buf
= write_insn (buf
, 0);
18656 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18658 /* beql $0, $0, 2f */
18660 /* Compute the PC offset from the current instruction to
18661 the end of the variable frag. */
18662 /* How many bytes in instructions we've already emitted? */
18663 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18664 /* How many bytes in instructions from here to the end? */
18665 i
= fragp
->fr_var
- i
;
18666 /* Convert to instruction count. */
18668 /* Don't decrement i, because we want to branch over the
18672 buf
= write_insn (buf
, insn
);
18673 buf
= write_insn (buf
, 0);
18677 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18680 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18681 ? 0x0c000000 : 0x08000000);
18683 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18684 fragp
->fr_symbol
, fragp
->fr_offset
,
18685 FALSE
, BFD_RELOC_MIPS_JMP
);
18686 fixp
->fx_file
= fragp
->fr_file
;
18687 fixp
->fx_line
= fragp
->fr_line
;
18689 buf
= write_insn (buf
, insn
);
18693 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18695 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18696 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18697 insn
|= at
<< OP_SH_RT
;
18699 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18700 fragp
->fr_symbol
, fragp
->fr_offset
,
18701 FALSE
, BFD_RELOC_MIPS_GOT16
);
18702 fixp
->fx_file
= fragp
->fr_file
;
18703 fixp
->fx_line
= fragp
->fr_line
;
18705 buf
= write_insn (buf
, insn
);
18707 if (mips_opts
.isa
== ISA_MIPS1
)
18709 buf
= write_insn (buf
, 0);
18711 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18712 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18713 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18715 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18716 fragp
->fr_symbol
, fragp
->fr_offset
,
18717 FALSE
, BFD_RELOC_LO16
);
18718 fixp
->fx_file
= fragp
->fr_file
;
18719 fixp
->fx_line
= fragp
->fr_line
;
18721 buf
= write_insn (buf
, insn
);
18724 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18728 insn
|= at
<< OP_SH_RS
;
18730 buf
= write_insn (buf
, insn
);
18734 fragp
->fr_fix
+= fragp
->fr_var
;
18735 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18739 /* Relax microMIPS branches. */
18740 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18742 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18743 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18744 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18745 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18746 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18747 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18748 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18749 bfd_boolean short_ds
;
18750 unsigned long insn
;
18753 fragp
->fr_fix
+= fragp
->fr_var
;
18755 /* Handle 16-bit branches that fit or are forced to fit. */
18756 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18758 /* We generate a fixup instead of applying it right now,
18759 because if there is linker relaxation, we're going to
18760 need the relocations. */
18764 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18765 fragp
->fr_symbol
, fragp
->fr_offset
,
18766 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18769 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18770 fragp
->fr_symbol
, fragp
->fr_offset
,
18771 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18777 fixp
->fx_file
= fragp
->fr_file
;
18778 fixp
->fx_line
= fragp
->fr_line
;
18780 /* These relocations can have an addend that won't fit in
18782 fixp
->fx_no_overflow
= 1;
18787 /* Handle 32-bit branches that fit or are forced to fit. */
18788 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18789 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18791 /* We generate a fixup instead of applying it right now,
18792 because if there is linker relaxation, we're going to
18793 need the relocations. */
18794 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18795 fragp
->fr_symbol
, fragp
->fr_offset
,
18796 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18797 fixp
->fx_file
= fragp
->fr_file
;
18798 fixp
->fx_line
= fragp
->fr_line
;
18802 insn
= read_compressed_insn (buf
, 4);
18807 /* Check the short-delay-slot bit. */
18808 if (!al
|| (insn
& 0x02000000) != 0)
18809 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18811 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18814 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18819 /* Relax 16-bit branches to 32-bit branches. */
18822 insn
= read_compressed_insn (buf
, 2);
18824 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18825 insn
= 0x94000000; /* beq */
18826 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18828 unsigned long regno
;
18830 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18831 regno
= micromips_to_32_reg_d_map
[regno
];
18832 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18833 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18838 /* Nothing else to do, just write it out. */
18839 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18840 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18842 buf
= write_compressed_insn (buf
, insn
, 4);
18844 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18845 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18850 insn
= read_compressed_insn (buf
, 4);
18852 /* Relax 32-bit branches to a sequence of instructions. */
18853 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18854 _("relaxed out-of-range branch into a jump"));
18856 /* Set the short-delay-slot bit. */
18857 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18859 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18863 /* Reverse the branch. */
18864 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18865 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18866 insn
^= 0x20000000;
18867 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18868 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18869 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18870 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18871 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18872 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18873 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18874 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18875 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18876 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18877 insn
^= 0x00400000;
18878 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18879 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18880 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18881 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18882 insn
^= 0x00200000;
18883 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18885 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18887 insn
^= 0x00800000;
18893 /* Clear the and-link and short-delay-slot bits. */
18894 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18896 /* bltzal 0x40200000 bgezal 0x40600000 */
18897 /* bltzals 0x42200000 bgezals 0x42600000 */
18898 insn
&= ~0x02200000;
18901 /* Make a label at the end for use with the branch. */
18902 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18903 micromips_label_inc ();
18904 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18907 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18908 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18909 fixp
->fx_file
= fragp
->fr_file
;
18910 fixp
->fx_line
= fragp
->fr_line
;
18912 /* Branch over the jump. */
18913 buf
= write_compressed_insn (buf
, insn
, 4);
18919 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18921 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18927 unsigned long jal
= (short_ds
|| nods
18928 ? 0x74000000 : 0xf4000000); /* jal/s */
18930 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18931 insn
= al
? jal
: 0xd4000000;
18933 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18934 fragp
->fr_symbol
, fragp
->fr_offset
,
18935 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18936 fixp
->fx_file
= fragp
->fr_file
;
18937 fixp
->fx_line
= fragp
->fr_line
;
18939 buf
= write_compressed_insn (buf
, insn
, 4);
18941 if (compact
|| nods
)
18945 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18947 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18952 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18954 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18955 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18956 insn
|= at
<< MICROMIPSOP_SH_RT
;
18958 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18959 fragp
->fr_symbol
, fragp
->fr_offset
,
18960 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18961 fixp
->fx_file
= fragp
->fr_file
;
18962 fixp
->fx_line
= fragp
->fr_line
;
18964 buf
= write_compressed_insn (buf
, insn
, 4);
18966 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18967 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18968 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18970 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18971 fragp
->fr_symbol
, fragp
->fr_offset
,
18972 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18973 fixp
->fx_file
= fragp
->fr_file
;
18974 fixp
->fx_line
= fragp
->fr_line
;
18976 buf
= write_compressed_insn (buf
, insn
, 4);
18981 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18982 insn
|= at
<< MICROMIPSOP_SH_RS
;
18984 buf
= write_compressed_insn (buf
, insn
, 4);
18986 if (compact
|| nods
)
18988 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18992 /* jr/jrc/jalr/jalrs $at */
18993 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18994 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18996 insn
= al
? jalr
: jr
;
18997 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18999 buf
= write_compressed_insn (buf
, insn
, 2);
19004 buf
= write_compressed_insn (buf
, 0x0c00, 2);
19006 buf
= write_compressed_insn (buf
, 0x00000000, 4);
19011 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
19015 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
19018 const struct mips_int_operand
*operand
;
19021 unsigned int user_length
;
19022 bfd_boolean need_reloc
;
19023 unsigned long insn
;
19028 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
19029 operand
= mips16_immed_operand (type
, FALSE
);
19031 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
19032 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
19033 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
19035 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
19036 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
19037 || (operand
->root
.type
== OP_PCREL
&& !mac
19039 : !bfd_is_abs_section (symsec
)));
19041 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19043 const struct mips_pcrel_operand
*pcrel_op
;
19045 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19047 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19049 if (!mips_ignore_branch_isa
19050 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19051 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19052 _("branch to a symbol in another ISA mode"));
19053 else if ((fragp
->fr_offset
& 0x1) != 0)
19054 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19055 _("branch to misaligned address (0x%lx)"),
19056 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19057 + (fragp
->fr_offset
& ~1)));
19060 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19062 /* Make sure the section winds up with the alignment we have
19064 if (operand
->shift
> 0)
19065 record_alignment (asec
, operand
->shift
);
19068 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19069 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19072 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19073 _("macro instruction expanded into multiple "
19074 "instructions in a branch delay slot"));
19076 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19077 _("extended instruction in a branch delay slot"));
19079 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19080 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19081 _("macro instruction expanded into multiple "
19084 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19086 insn
= read_compressed_insn (buf
, 2);
19088 insn
|= MIPS16_EXTEND
;
19090 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19092 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19104 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19105 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19107 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19113 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19115 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19116 fragp
->fr_symbol
, fragp
->fr_offset
,
19117 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
19118 fixp
->fx_file
= fragp
->fr_file
;
19119 fixp
->fx_line
= fragp
->fr_line
;
19121 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19122 fragp
->fr_symbol
, fragp
->fr_offset
,
19123 FALSE
, BFD_RELOC_MIPS16_LO16
);
19124 fixp
->fx_file
= fragp
->fr_file
;
19125 fixp
->fx_line
= fragp
->fr_line
;
19130 switch (insn
& 0xf800)
19132 case 0x0800: /* ADDIU */
19133 reg
= (insn
>> 8) & 0x7;
19134 op
= 0xf0004800 | (reg
<< 8);
19136 case 0xb000: /* LW */
19137 reg
= (insn
>> 8) & 0x7;
19138 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19140 case 0xf800: /* I64 */
19141 reg
= (insn
>> 5) & 0x7;
19142 switch (insn
& 0x0700)
19144 case 0x0400: /* LD */
19145 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19147 case 0x0600: /* DADDIU */
19148 op
= 0xf000fd00 | (reg
<< 5);
19158 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19159 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19160 buf
= write_compressed_insn (buf
, new, 4);
19163 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19164 buf
= write_compressed_insn (buf
, new, 4);
19166 op
|= mips16_immed_extend (val
, 16);
19167 buf
= write_compressed_insn (buf
, op
, 4);
19169 fragp
->fr_fix
+= e2
? 8 : 12;
19173 unsigned int length
= ext
? 4 : 2;
19177 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19184 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19189 if (mac
|| reloc
== BFD_RELOC_NONE
)
19190 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19191 _("unsupported relocation"));
19194 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19195 fragp
->fr_symbol
, fragp
->fr_offset
,
19197 fixp
->fx_file
= fragp
->fr_file
;
19198 fixp
->fx_line
= fragp
->fr_line
;
19201 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19202 _("invalid unextended operand value"));
19205 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19206 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19208 gas_assert (mips16_opcode_length (insn
) == length
);
19209 write_compressed_insn (buf
, insn
, length
);
19210 fragp
->fr_fix
+= length
;
19215 relax_substateT subtype
= fragp
->fr_subtype
;
19216 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19217 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19218 unsigned int first
, second
;
19221 first
= RELAX_FIRST (subtype
);
19222 second
= RELAX_SECOND (subtype
);
19223 fixp
= (fixS
*) fragp
->fr_opcode
;
19225 /* If the delay slot chosen does not match the size of the instruction,
19226 then emit a warning. */
19227 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19228 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19233 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19234 | RELAX_DELAY_SLOT_SIZE_FIRST
19235 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19236 msg
= macro_warning (s
);
19238 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19242 /* Possibly emit a warning if we've chosen the longer option. */
19243 if (use_second
== second_longer
)
19249 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19250 msg
= macro_warning (s
);
19252 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19256 /* Go through all the fixups for the first sequence. Disable them
19257 (by marking them as done) if we're going to use the second
19258 sequence instead. */
19260 && fixp
->fx_frag
== fragp
19261 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19263 if (subtype
& RELAX_USE_SECOND
)
19265 fixp
= fixp
->fx_next
;
19268 /* Go through the fixups for the second sequence. Disable them if
19269 we're going to use the first sequence, otherwise adjust their
19270 addresses to account for the relaxation. */
19271 while (fixp
&& fixp
->fx_frag
== fragp
)
19273 if (subtype
& RELAX_USE_SECOND
)
19274 fixp
->fx_where
-= first
;
19277 fixp
= fixp
->fx_next
;
19280 /* Now modify the frag contents. */
19281 if (subtype
& RELAX_USE_SECOND
)
19285 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19286 memmove (start
, start
+ first
, second
);
19287 fragp
->fr_fix
-= first
;
19290 fragp
->fr_fix
-= second
;
19294 /* This function is called after the relocs have been generated.
19295 We've been storing mips16 text labels as odd. Here we convert them
19296 back to even for the convenience of the debugger. */
19299 mips_frob_file_after_relocs (void)
19302 unsigned int count
, i
;
19304 syms
= bfd_get_outsymbols (stdoutput
);
19305 count
= bfd_get_symcount (stdoutput
);
19306 for (i
= 0; i
< count
; i
++, syms
++)
19307 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19308 && ((*syms
)->value
& 1) != 0)
19310 (*syms
)->value
&= ~1;
19311 /* If the symbol has an odd size, it was probably computed
19312 incorrectly, so adjust that as well. */
19313 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19314 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19318 /* This function is called whenever a label is defined, including fake
19319 labels instantiated off the dot special symbol. It is used when
19320 handling branch delays; if a branch has a label, we assume we cannot
19321 move it. This also bumps the value of the symbol by 1 in compressed
19325 mips_record_label (symbolS
*sym
)
19327 segment_info_type
*si
= seg_info (now_seg
);
19328 struct insn_label_list
*l
;
19330 if (free_insn_labels
== NULL
)
19331 l
= XNEW (struct insn_label_list
);
19334 l
= free_insn_labels
;
19335 free_insn_labels
= l
->next
;
19339 l
->next
= si
->label_list
;
19340 si
->label_list
= l
;
19343 /* This function is called as tc_frob_label() whenever a label is defined
19344 and adds a DWARF-2 record we only want for true labels. */
19347 mips_define_label (symbolS
*sym
)
19349 mips_record_label (sym
);
19350 dwarf2_emit_label (sym
);
19353 /* This function is called by tc_new_dot_label whenever a new dot symbol
19357 mips_add_dot_label (symbolS
*sym
)
19359 mips_record_label (sym
);
19360 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19361 mips_compressed_mark_label (sym
);
19364 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19365 static unsigned int
19366 mips_convert_ase_flags (int ase
)
19368 unsigned int ext_ases
= 0;
19371 ext_ases
|= AFL_ASE_DSP
;
19372 if (ase
& ASE_DSPR2
)
19373 ext_ases
|= AFL_ASE_DSPR2
;
19374 if (ase
& ASE_DSPR3
)
19375 ext_ases
|= AFL_ASE_DSPR3
;
19377 ext_ases
|= AFL_ASE_EVA
;
19379 ext_ases
|= AFL_ASE_MCU
;
19380 if (ase
& ASE_MDMX
)
19381 ext_ases
|= AFL_ASE_MDMX
;
19382 if (ase
& ASE_MIPS3D
)
19383 ext_ases
|= AFL_ASE_MIPS3D
;
19385 ext_ases
|= AFL_ASE_MT
;
19386 if (ase
& ASE_SMARTMIPS
)
19387 ext_ases
|= AFL_ASE_SMARTMIPS
;
19388 if (ase
& ASE_VIRT
)
19389 ext_ases
|= AFL_ASE_VIRT
;
19391 ext_ases
|= AFL_ASE_MSA
;
19393 ext_ases
|= AFL_ASE_XPA
;
19394 if (ase
& ASE_MIPS16E2
)
19395 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19397 ext_ases
|= AFL_ASE_CRC
;
19398 if (ase
& ASE_GINV
)
19399 ext_ases
|= AFL_ASE_GINV
;
19400 if (ase
& ASE_LOONGSON_MMI
)
19401 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19402 if (ase
& ASE_LOONGSON_CAM
)
19403 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19404 if (ase
& ASE_LOONGSON_EXT
)
19405 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19406 if (ase
& ASE_LOONGSON_EXT2
)
19407 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19411 /* Some special processing for a MIPS ELF file. */
19414 mips_elf_final_processing (void)
19417 Elf_Internal_ABIFlags_v0 flags
;
19421 switch (file_mips_opts
.isa
)
19424 flags
.isa_level
= 1;
19427 flags
.isa_level
= 2;
19430 flags
.isa_level
= 3;
19433 flags
.isa_level
= 4;
19436 flags
.isa_level
= 5;
19439 flags
.isa_level
= 32;
19443 flags
.isa_level
= 32;
19447 flags
.isa_level
= 32;
19451 flags
.isa_level
= 32;
19455 flags
.isa_level
= 32;
19459 flags
.isa_level
= 64;
19463 flags
.isa_level
= 64;
19467 flags
.isa_level
= 64;
19471 flags
.isa_level
= 64;
19475 flags
.isa_level
= 64;
19480 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19481 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19482 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19483 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19485 flags
.cpr2_size
= AFL_REG_NONE
;
19486 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19487 Tag_GNU_MIPS_ABI_FP
);
19488 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19489 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19490 if (file_ase_mips16
)
19491 flags
.ases
|= AFL_ASE_MIPS16
;
19492 if (file_ase_micromips
)
19493 flags
.ases
|= AFL_ASE_MICROMIPS
;
19495 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19496 || file_mips_opts
.fp
== 64)
19497 && file_mips_opts
.oddspreg
)
19498 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19501 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19502 ((Elf_External_ABIFlags_v0
*)
19505 /* Write out the register information. */
19506 if (mips_abi
!= N64_ABI
)
19510 s
.ri_gprmask
= mips_gprmask
;
19511 s
.ri_cprmask
[0] = mips_cprmask
[0];
19512 s
.ri_cprmask
[1] = mips_cprmask
[1];
19513 s
.ri_cprmask
[2] = mips_cprmask
[2];
19514 s
.ri_cprmask
[3] = mips_cprmask
[3];
19515 /* The gp_value field is set by the MIPS ELF backend. */
19517 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19518 ((Elf32_External_RegInfo
*)
19519 mips_regmask_frag
));
19523 Elf64_Internal_RegInfo s
;
19525 s
.ri_gprmask
= mips_gprmask
;
19527 s
.ri_cprmask
[0] = mips_cprmask
[0];
19528 s
.ri_cprmask
[1] = mips_cprmask
[1];
19529 s
.ri_cprmask
[2] = mips_cprmask
[2];
19530 s
.ri_cprmask
[3] = mips_cprmask
[3];
19531 /* The gp_value field is set by the MIPS ELF backend. */
19533 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19534 ((Elf64_External_RegInfo
*)
19535 mips_regmask_frag
));
19538 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19539 sort of BFD interface for this. */
19540 if (mips_any_noreorder
)
19541 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19542 if (mips_pic
!= NO_PIC
)
19544 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19545 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19548 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19550 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19551 defined at present; this might need to change in future. */
19552 if (file_ase_mips16
)
19553 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19554 if (file_ase_micromips
)
19555 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19556 if (file_mips_opts
.ase
& ASE_MDMX
)
19557 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19559 /* Set the MIPS ELF ABI flags. */
19560 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19561 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19562 else if (mips_abi
== O64_ABI
)
19563 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19564 else if (mips_abi
== EABI_ABI
)
19566 if (file_mips_opts
.gp
== 64)
19567 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19569 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19572 /* Nothing to do for N32_ABI or N64_ABI. */
19574 if (mips_32bitmode
)
19575 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19577 if (mips_nan2008
== 1)
19578 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19580 /* 32 bit code with 64 bit FP registers. */
19581 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19582 Tag_GNU_MIPS_ABI_FP
);
19583 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19584 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19587 typedef struct proc
{
19589 symbolS
*func_end_sym
;
19590 unsigned long reg_mask
;
19591 unsigned long reg_offset
;
19592 unsigned long fpreg_mask
;
19593 unsigned long fpreg_offset
;
19594 unsigned long frame_offset
;
19595 unsigned long frame_reg
;
19596 unsigned long pc_reg
;
19599 static procS cur_proc
;
19600 static procS
*cur_proc_ptr
;
19601 static int numprocs
;
19603 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19604 as "2", and a normal nop as "0". */
19606 #define NOP_OPCODE_MIPS 0
19607 #define NOP_OPCODE_MIPS16 1
19608 #define NOP_OPCODE_MICROMIPS 2
19611 mips_nop_opcode (void)
19613 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19614 return NOP_OPCODE_MICROMIPS
;
19615 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19616 return NOP_OPCODE_MIPS16
;
19618 return NOP_OPCODE_MIPS
;
19621 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19622 32-bit microMIPS NOPs here (if applicable). */
19625 mips_handle_align (fragS
*fragp
)
19629 int bytes
, size
, excess
;
19632 if (fragp
->fr_type
!= rs_align_code
)
19635 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19637 switch (nop_opcode
)
19639 case NOP_OPCODE_MICROMIPS
:
19640 opcode
= micromips_nop32_insn
.insn_opcode
;
19643 case NOP_OPCODE_MIPS16
:
19644 opcode
= mips16_nop_insn
.insn_opcode
;
19647 case NOP_OPCODE_MIPS
:
19649 opcode
= nop_insn
.insn_opcode
;
19654 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19655 excess
= bytes
% size
;
19657 /* Handle the leading part if we're not inserting a whole number of
19658 instructions, and make it the end of the fixed part of the frag.
19659 Try to fit in a short microMIPS NOP if applicable and possible,
19660 and use zeroes otherwise. */
19661 gas_assert (excess
< 4);
19662 fragp
->fr_fix
+= excess
;
19667 /* Fall through. */
19669 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19671 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19675 /* Fall through. */
19678 /* Fall through. */
19683 md_number_to_chars (p
, opcode
, size
);
19684 fragp
->fr_var
= size
;
19693 if (*input_line_pointer
== '-')
19695 ++input_line_pointer
;
19698 if (!ISDIGIT (*input_line_pointer
))
19699 as_bad (_("expected simple number"));
19700 if (input_line_pointer
[0] == '0')
19702 if (input_line_pointer
[1] == 'x')
19704 input_line_pointer
+= 2;
19705 while (ISXDIGIT (*input_line_pointer
))
19708 val
|= hex_value (*input_line_pointer
++);
19710 return negative
? -val
: val
;
19714 ++input_line_pointer
;
19715 while (ISDIGIT (*input_line_pointer
))
19718 val
|= *input_line_pointer
++ - '0';
19720 return negative
? -val
: val
;
19723 if (!ISDIGIT (*input_line_pointer
))
19725 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19726 *input_line_pointer
, *input_line_pointer
);
19727 as_warn (_("invalid number"));
19730 while (ISDIGIT (*input_line_pointer
))
19733 val
+= *input_line_pointer
++ - '0';
19735 return negative
? -val
: val
;
19738 /* The .file directive; just like the usual .file directive, but there
19739 is an initial number which is the ECOFF file index. In the non-ECOFF
19740 case .file implies DWARF-2. */
19743 s_mips_file (int x ATTRIBUTE_UNUSED
)
19745 static int first_file_directive
= 0;
19747 if (ECOFF_DEBUGGING
)
19756 filename
= dwarf2_directive_filename ();
19758 /* Versions of GCC up to 3.1 start files with a ".file"
19759 directive even for stabs output. Make sure that this
19760 ".file" is handled. Note that you need a version of GCC
19761 after 3.1 in order to support DWARF-2 on MIPS. */
19762 if (filename
!= NULL
&& ! first_file_directive
)
19764 (void) new_logical_line (filename
, -1);
19765 s_app_file_string (filename
, 0);
19767 first_file_directive
= 1;
19771 /* The .loc directive, implying DWARF-2. */
19774 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19776 if (!ECOFF_DEBUGGING
)
19777 dwarf2_directive_loc (0);
19780 /* The .end directive. */
19783 s_mips_end (int x ATTRIBUTE_UNUSED
)
19787 /* Following functions need their own .frame and .cprestore directives. */
19788 mips_frame_reg_valid
= 0;
19789 mips_cprestore_valid
= 0;
19791 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19794 demand_empty_rest_of_line ();
19799 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19800 as_warn (_(".end not in text section"));
19804 as_warn (_(".end directive without a preceding .ent directive"));
19805 demand_empty_rest_of_line ();
19811 gas_assert (S_GET_NAME (p
));
19812 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19813 as_warn (_(".end symbol does not match .ent symbol"));
19815 if (debug_type
== DEBUG_STABS
)
19816 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19820 as_warn (_(".end directive missing or unknown symbol"));
19822 /* Create an expression to calculate the size of the function. */
19823 if (p
&& cur_proc_ptr
)
19825 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19826 expressionS
*exp
= XNEW (expressionS
);
19829 exp
->X_op
= O_subtract
;
19830 exp
->X_add_symbol
= symbol_temp_new_now ();
19831 exp
->X_op_symbol
= p
;
19832 exp
->X_add_number
= 0;
19834 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19837 #ifdef md_flush_pending_output
19838 md_flush_pending_output ();
19841 /* Generate a .pdr section. */
19842 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19844 segT saved_seg
= now_seg
;
19845 subsegT saved_subseg
= now_subseg
;
19849 gas_assert (pdr_seg
);
19850 subseg_set (pdr_seg
, 0);
19852 /* Write the symbol. */
19853 exp
.X_op
= O_symbol
;
19854 exp
.X_add_symbol
= p
;
19855 exp
.X_add_number
= 0;
19856 emit_expr (&exp
, 4);
19858 fragp
= frag_more (7 * 4);
19860 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19861 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19862 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19863 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19864 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19865 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19866 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19868 subseg_set (saved_seg
, saved_subseg
);
19871 cur_proc_ptr
= NULL
;
19874 /* The .aent and .ent directives. */
19877 s_mips_ent (int aent
)
19881 symbolP
= get_symbol ();
19882 if (*input_line_pointer
== ',')
19883 ++input_line_pointer
;
19884 SKIP_WHITESPACE ();
19885 if (ISDIGIT (*input_line_pointer
)
19886 || *input_line_pointer
== '-')
19889 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19890 as_warn (_(".ent or .aent not in text section"));
19892 if (!aent
&& cur_proc_ptr
)
19893 as_warn (_("missing .end"));
19897 /* This function needs its own .frame and .cprestore directives. */
19898 mips_frame_reg_valid
= 0;
19899 mips_cprestore_valid
= 0;
19901 cur_proc_ptr
= &cur_proc
;
19902 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19904 cur_proc_ptr
->func_sym
= symbolP
;
19908 if (debug_type
== DEBUG_STABS
)
19909 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19910 S_GET_NAME (symbolP
));
19913 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19915 demand_empty_rest_of_line ();
19918 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19919 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19920 s_mips_frame is used so that we can set the PDR information correctly.
19921 We can't use the ecoff routines because they make reference to the ecoff
19922 symbol table (in the mdebug section). */
19925 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19927 if (ECOFF_DEBUGGING
)
19933 if (cur_proc_ptr
== (procS
*) NULL
)
19935 as_warn (_(".frame outside of .ent"));
19936 demand_empty_rest_of_line ();
19940 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19942 SKIP_WHITESPACE ();
19943 if (*input_line_pointer
++ != ','
19944 || get_absolute_expression_and_terminator (&val
) != ',')
19946 as_warn (_("bad .frame directive"));
19947 --input_line_pointer
;
19948 demand_empty_rest_of_line ();
19952 cur_proc_ptr
->frame_offset
= val
;
19953 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19955 demand_empty_rest_of_line ();
19959 /* The .fmask and .mask directives. If the mdebug section is present
19960 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19961 embedded targets, s_mips_mask is used so that we can set the PDR
19962 information correctly. We can't use the ecoff routines because they
19963 make reference to the ecoff symbol table (in the mdebug section). */
19966 s_mips_mask (int reg_type
)
19968 if (ECOFF_DEBUGGING
)
19969 s_ignore (reg_type
);
19974 if (cur_proc_ptr
== (procS
*) NULL
)
19976 as_warn (_(".mask/.fmask outside of .ent"));
19977 demand_empty_rest_of_line ();
19981 if (get_absolute_expression_and_terminator (&mask
) != ',')
19983 as_warn (_("bad .mask/.fmask directive"));
19984 --input_line_pointer
;
19985 demand_empty_rest_of_line ();
19989 off
= get_absolute_expression ();
19991 if (reg_type
== 'F')
19993 cur_proc_ptr
->fpreg_mask
= mask
;
19994 cur_proc_ptr
->fpreg_offset
= off
;
19998 cur_proc_ptr
->reg_mask
= mask
;
19999 cur_proc_ptr
->reg_offset
= off
;
20002 demand_empty_rest_of_line ();
20006 /* A table describing all the processors gas knows about. Names are
20007 matched in the order listed.
20009 To ease comparison, please keep this table in the same order as
20010 gcc's mips_cpu_info_table[]. */
20011 static const struct mips_cpu_info mips_cpu_info_table
[] =
20013 /* Entries for generic ISAs. */
20014 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
20015 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
20016 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
20017 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
20018 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
20019 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
20020 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20021 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
20022 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
20023 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
20024 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
20025 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
20026 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
20027 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
20028 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
20031 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20032 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20033 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
20036 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20039 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20040 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20041 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20042 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20043 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20044 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20045 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20046 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20047 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20048 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20049 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20050 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20051 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20052 /* ST Microelectronics Loongson 2E and 2F cores. */
20053 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20054 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20057 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20058 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20059 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20060 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20061 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20062 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20063 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20064 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20065 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20066 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20067 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20068 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20069 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20070 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20071 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20074 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20075 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20076 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20077 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20079 /* MIPS 32 Release 2 */
20080 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20081 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20082 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20084 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20085 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20086 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20087 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20088 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20089 ISA_MIPS32R2
, CPU_MIPS32R2
},
20090 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20091 ISA_MIPS32R2
, CPU_MIPS32R2
},
20092 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20093 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20094 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20095 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20096 /* Deprecated forms of the above. */
20097 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20098 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20099 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20100 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20101 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20102 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20103 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20104 /* Deprecated forms of the above. */
20105 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20106 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20107 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20108 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20109 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20110 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20111 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20112 /* Deprecated forms of the above. */
20113 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20114 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20115 /* 34Kn is a 34kc without DSP. */
20116 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20117 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20118 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20119 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20120 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20121 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20122 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20123 /* Deprecated forms of the above. */
20124 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20125 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20126 /* 1004K cores are multiprocessor versions of the 34K. */
20127 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20128 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20129 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20130 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20131 /* interaptiv is the new name for 1004kf. */
20132 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20133 { "interaptiv-mr2", 0,
20134 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20135 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20136 /* M5100 family. */
20137 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20138 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20139 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20140 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20143 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20144 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20145 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20146 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20148 /* Broadcom SB-1 CPU core. */
20149 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20150 /* Broadcom SB-1A CPU core. */
20151 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20153 /* MIPS 64 Release 2. */
20154 /* Loongson CPU core. */
20155 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20156 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20157 ISA_MIPS64R2
, CPU_GS464
},
20158 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20159 ISA_MIPS64R2
, CPU_GS464
},
20160 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20161 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20162 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20163 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20165 /* Cavium Networks Octeon CPU core. */
20166 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20167 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20168 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20169 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20172 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20175 XLP is mostly like XLR, with the prominent exception that it is
20176 MIPS64R2 rather than MIPS64. */
20177 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20179 /* MIPS 64 Release 6. */
20180 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20181 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20182 ISA_MIPS64R6
, CPU_MIPS64R6
},
20183 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20186 { NULL
, 0, 0, 0, 0 }
20190 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20191 with a final "000" replaced by "k". Ignore case.
20193 Note: this function is shared between GCC and GAS. */
20196 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20198 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20199 given
++, canonical
++;
20201 return ((*given
== 0 && *canonical
== 0)
20202 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20206 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20207 CPU name. We've traditionally allowed a lot of variation here.
20209 Note: this function is shared between GCC and GAS. */
20212 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20214 /* First see if the name matches exactly, or with a final "000"
20215 turned into "k". */
20216 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20219 /* If not, try comparing based on numerical designation alone.
20220 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20221 if (TOLOWER (*given
) == 'r')
20223 if (!ISDIGIT (*given
))
20226 /* Skip over some well-known prefixes in the canonical name,
20227 hoping to find a number there too. */
20228 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20230 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20232 else if (TOLOWER (canonical
[0]) == 'r')
20235 return mips_strict_matching_cpu_name_p (canonical
, given
);
20239 /* Parse an option that takes the name of a processor as its argument.
20240 OPTION is the name of the option and CPU_STRING is the argument.
20241 Return the corresponding processor enumeration if the CPU_STRING is
20242 recognized, otherwise report an error and return null.
20244 A similar function exists in GCC. */
20246 static const struct mips_cpu_info
*
20247 mips_parse_cpu (const char *option
, const char *cpu_string
)
20249 const struct mips_cpu_info
*p
;
20251 /* 'from-abi' selects the most compatible architecture for the given
20252 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20253 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20254 version. Look first at the -mgp options, if given, otherwise base
20255 the choice on MIPS_DEFAULT_64BIT.
20257 Treat NO_ABI like the EABIs. One reason to do this is that the
20258 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20259 architecture. This code picks MIPS I for 'mips' and MIPS III for
20260 'mips64', just as we did in the days before 'from-abi'. */
20261 if (strcasecmp (cpu_string
, "from-abi") == 0)
20263 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20264 return mips_cpu_info_from_isa (ISA_MIPS1
);
20266 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20267 return mips_cpu_info_from_isa (ISA_MIPS3
);
20269 if (file_mips_opts
.gp
>= 0)
20270 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20271 ? ISA_MIPS1
: ISA_MIPS3
);
20273 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20278 /* 'default' has traditionally been a no-op. Probably not very useful. */
20279 if (strcasecmp (cpu_string
, "default") == 0)
20282 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20283 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20286 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20290 /* Return the canonical processor information for ISA (a member of the
20291 ISA_MIPS* enumeration). */
20293 static const struct mips_cpu_info
*
20294 mips_cpu_info_from_isa (int isa
)
20298 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20299 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20300 && isa
== mips_cpu_info_table
[i
].isa
)
20301 return (&mips_cpu_info_table
[i
]);
20306 static const struct mips_cpu_info
*
20307 mips_cpu_info_from_arch (int arch
)
20311 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20312 if (arch
== mips_cpu_info_table
[i
].cpu
)
20313 return (&mips_cpu_info_table
[i
]);
20319 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20323 fprintf (stream
, "%24s", "");
20328 fprintf (stream
, ", ");
20332 if (*col_p
+ strlen (string
) > 72)
20334 fprintf (stream
, "\n%24s", "");
20338 fprintf (stream
, "%s", string
);
20339 *col_p
+= strlen (string
);
20345 md_show_usage (FILE *stream
)
20350 fprintf (stream
, _("\
20352 -EB generate big endian output\n\
20353 -EL generate little endian output\n\
20354 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20355 -G NUM allow referencing objects up to NUM bytes\n\
20356 implicitly with the gp register [default 8]\n"));
20357 fprintf (stream
, _("\
20358 -mips1 generate MIPS ISA I instructions\n\
20359 -mips2 generate MIPS ISA II instructions\n\
20360 -mips3 generate MIPS ISA III instructions\n\
20361 -mips4 generate MIPS ISA IV instructions\n\
20362 -mips5 generate MIPS ISA V instructions\n\
20363 -mips32 generate MIPS32 ISA instructions\n\
20364 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20365 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20366 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20367 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20368 -mips64 generate MIPS64 ISA instructions\n\
20369 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20370 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20371 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20372 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20373 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20377 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20378 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20379 show (stream
, "from-abi", &column
, &first
);
20380 fputc ('\n', stream
);
20382 fprintf (stream
, _("\
20383 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20384 -no-mCPU don't generate code specific to CPU.\n\
20385 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20389 show (stream
, "3900", &column
, &first
);
20390 show (stream
, "4010", &column
, &first
);
20391 show (stream
, "4100", &column
, &first
);
20392 show (stream
, "4650", &column
, &first
);
20393 fputc ('\n', stream
);
20395 fprintf (stream
, _("\
20396 -mips16 generate mips16 instructions\n\
20397 -no-mips16 do not generate mips16 instructions\n"));
20398 fprintf (stream
, _("\
20399 -mmips16e2 generate MIPS16e2 instructions\n\
20400 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20401 fprintf (stream
, _("\
20402 -mmicromips generate microMIPS instructions\n\
20403 -mno-micromips do not generate microMIPS instructions\n"));
20404 fprintf (stream
, _("\
20405 -msmartmips generate smartmips instructions\n\
20406 -mno-smartmips do not generate smartmips instructions\n"));
20407 fprintf (stream
, _("\
20408 -mdsp generate DSP instructions\n\
20409 -mno-dsp do not generate DSP instructions\n"));
20410 fprintf (stream
, _("\
20411 -mdspr2 generate DSP R2 instructions\n\
20412 -mno-dspr2 do not generate DSP R2 instructions\n"));
20413 fprintf (stream
, _("\
20414 -mdspr3 generate DSP R3 instructions\n\
20415 -mno-dspr3 do not generate DSP R3 instructions\n"));
20416 fprintf (stream
, _("\
20417 -mmt generate MT instructions\n\
20418 -mno-mt do not generate MT instructions\n"));
20419 fprintf (stream
, _("\
20420 -mmcu generate MCU instructions\n\
20421 -mno-mcu do not generate MCU instructions\n"));
20422 fprintf (stream
, _("\
20423 -mmsa generate MSA instructions\n\
20424 -mno-msa do not generate MSA instructions\n"));
20425 fprintf (stream
, _("\
20426 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20427 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20428 fprintf (stream
, _("\
20429 -mvirt generate Virtualization instructions\n\
20430 -mno-virt do not generate Virtualization instructions\n"));
20431 fprintf (stream
, _("\
20432 -mcrc generate CRC instructions\n\
20433 -mno-crc do not generate CRC instructions\n"));
20434 fprintf (stream
, _("\
20435 -mginv generate Global INValidate (GINV) instructions\n\
20436 -mno-ginv do not generate Global INValidate instructions\n"));
20437 fprintf (stream
, _("\
20438 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20439 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20440 fprintf (stream
, _("\
20441 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20442 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20443 fprintf (stream
, _("\
20444 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20445 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20446 fprintf (stream
, _("\
20447 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20448 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20449 fprintf (stream
, _("\
20450 -minsn32 only generate 32-bit microMIPS instructions\n\
20451 -mno-insn32 generate all microMIPS instructions\n"));
20452 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20453 fprintf (stream
, _("\
20454 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20455 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20457 fprintf (stream
, _("\
20458 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20459 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20461 fprintf (stream
, _("\
20462 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20463 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20464 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20465 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20466 -mfix-vr4120 work around certain VR4120 errata\n\
20467 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20468 -mfix-24k insert a nop after ERET and DERET instructions\n\
20469 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20470 -mfix-r5900 work around R5900 short loop errata\n\
20471 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20472 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20473 -msym32 assume all symbols have 32-bit values\n\
20474 -O0 do not remove unneeded NOPs, do not swap branches\n\
20475 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20476 -O2 remove unneeded NOPs and swap branches\n\
20477 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20478 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20479 fprintf (stream
, _("\
20480 -mhard-float allow floating-point instructions\n\
20481 -msoft-float do not allow floating-point instructions\n\
20482 -msingle-float only allow 32-bit floating-point operations\n\
20483 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20484 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20485 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20486 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20487 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20488 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20492 show (stream
, "legacy", &column
, &first
);
20493 show (stream
, "2008", &column
, &first
);
20495 fputc ('\n', stream
);
20497 fprintf (stream
, _("\
20498 -KPIC, -call_shared generate SVR4 position independent code\n\
20499 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20500 -mvxworks-pic generate VxWorks position independent code\n\
20501 -non_shared do not generate code that can operate with DSOs\n\
20502 -xgot assume a 32 bit GOT\n\
20503 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20504 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20505 position dependent (non shared) code\n\
20506 -mabi=ABI create ABI conformant object file for:\n"));
20510 show (stream
, "32", &column
, &first
);
20511 show (stream
, "o64", &column
, &first
);
20512 show (stream
, "n32", &column
, &first
);
20513 show (stream
, "64", &column
, &first
);
20514 show (stream
, "eabi", &column
, &first
);
20516 fputc ('\n', stream
);
20518 fprintf (stream
, _("\
20519 -32 create o32 ABI object file%s\n"),
20520 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20521 fprintf (stream
, _("\
20522 -n32 create n32 ABI object file%s\n"),
20523 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20524 fprintf (stream
, _("\
20525 -64 create 64 ABI object file%s\n"),
20526 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20531 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20533 if (HAVE_64BIT_SYMBOLS
)
20534 return dwarf2_format_64bit_irix
;
20536 return dwarf2_format_32bit
;
20541 mips_dwarf2_addr_size (void)
20543 if (HAVE_64BIT_OBJECTS
)
20549 /* Standard calling conventions leave the CFA at SP on entry. */
20551 mips_cfi_frame_initial_instructions (void)
20553 cfi_add_CFA_def_cfa_register (SP
);
20557 tc_mips_regname_to_dw2regnum (char *regname
)
20559 unsigned int regnum
= -1;
20562 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20568 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20569 Given a symbolic attribute NAME, return the proper integer value.
20570 Returns -1 if the attribute is not known. */
20573 mips_convert_symbolic_attribute (const char *name
)
20575 static const struct
20580 attribute_table
[] =
20582 #define T(tag) {#tag, tag}
20583 T (Tag_GNU_MIPS_ABI_FP
),
20584 T (Tag_GNU_MIPS_ABI_MSA
),
20592 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20593 if (streq (name
, attribute_table
[i
].name
))
20594 return attribute_table
[i
].tag
;
20602 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20604 mips_emit_delays ();
20606 as_warn (_("missing .end at end of assembly"));
20608 /* Just in case no code was emitted, do the consistency check. */
20609 file_mips_check_options ();
20611 /* Set a floating-point ABI if the user did not. */
20612 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20614 /* Perform consistency checks on the floating-point ABI. */
20615 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20616 Tag_GNU_MIPS_ABI_FP
);
20617 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20618 check_fpabi (fpabi
);
20622 /* Soft-float gets precedence over single-float, the two options should
20623 not be used together so this should not matter. */
20624 if (file_mips_opts
.soft_float
== 1)
20625 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20626 /* Single-float gets precedence over all double_float cases. */
20627 else if (file_mips_opts
.single_float
== 1)
20628 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20631 switch (file_mips_opts
.fp
)
20634 if (file_mips_opts
.gp
== 32)
20635 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20638 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20641 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20642 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20643 else if (file_mips_opts
.gp
== 32)
20644 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20646 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20651 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20652 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20656 /* Returns the relocation type required for a particular CFI encoding. */
20658 bfd_reloc_code_real_type
20659 mips_cfi_reloc_for_encoding (int encoding
)
20661 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20662 return BFD_RELOC_32_PCREL
;
20663 else return BFD_RELOC_NONE
;