1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occured in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
196 /* Whether we are assembling for the mips16 processor. 0 if we are
197 not, 1 if we are, and -1 if the value has not been initialized.
198 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
199 -nomips16 command line options, and the default CPU. */
201 /* Non-zero if we should not reorder instructions. Changed by `.set
202 reorder' and `.set noreorder'. */
204 /* Non-zero if we should not permit the $at ($1) register to be used
205 in instructions. Changed by `.set at' and `.set noat'. */
207 /* Non-zero if we should warn when a macro instruction expands into
208 more than one machine instruction. Changed by `.set nomacro' and
210 int warn_about_macros
;
211 /* Non-zero if we should not move instructions. Changed by `.set
212 move', `.set volatile', `.set nomove', and `.set novolatile'. */
214 /* Non-zero if we should not optimize branches by moving the target
215 of the branch into the delay slot. Actually, we don't perform
216 this optimization anyhow. Changed by `.set bopt' and `.set
219 /* Non-zero if we should not autoextend mips16 instructions.
220 Changed by `.set autoextend' and `.set noautoextend'. */
222 /* Restrict general purpose registers and floating point registers
223 to 32 bit. This is initially determined when -mgp32 or -mfp32
224 is passed but can changed if the assembler code uses .set mipsN. */
227 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
228 command line option, and the default CPU. */
230 /* True if ".set sym32" is in effect. */
234 /* True if -mgp32 was passed. */
235 static int file_mips_gp32
= -1;
237 /* True if -mfp32 was passed. */
238 static int file_mips_fp32
= -1;
240 /* This is the struct we use to hold the current set of options. Note
241 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
242 -1 to indicate that they have not been initialized. */
244 static struct mips_set_options mips_opts
=
246 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
249 /* These variables are filled in with the masks of registers used.
250 The object format code reads them and puts them in the appropriate
252 unsigned long mips_gprmask
;
253 unsigned long mips_cprmask
[4];
255 /* MIPS ISA we are using for this output file. */
256 static int file_mips_isa
= ISA_UNKNOWN
;
258 /* True if -mips16 was passed or implied by arguments passed on the
259 command line (e.g., by -march). */
260 static int file_ase_mips16
;
262 /* True if -mips3d was passed or implied by arguments passed on the
263 command line (e.g., by -march). */
264 static int file_ase_mips3d
;
266 /* True if -mdmx was passed or implied by arguments passed on the
267 command line (e.g., by -march). */
268 static int file_ase_mdmx
;
270 /* The argument of the -march= flag. The architecture we are assembling. */
271 static int file_mips_arch
= CPU_UNKNOWN
;
272 static const char *mips_arch_string
;
274 /* The argument of the -mtune= flag. The architecture for which we
276 static int mips_tune
= CPU_UNKNOWN
;
277 static const char *mips_tune_string
;
279 /* True when generating 32-bit code for a 64-bit processor. */
280 static int mips_32bitmode
= 0;
282 /* True if the given ABI requires 32-bit registers. */
283 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
285 /* Likewise 64-bit registers. */
286 #define ABI_NEEDS_64BIT_REGS(ABI) \
288 || (ABI) == N64_ABI \
291 /* Return true if ISA supports 64 bit gp register instructions. */
292 #define ISA_HAS_64BIT_REGS(ISA) ( \
294 || (ISA) == ISA_MIPS4 \
295 || (ISA) == ISA_MIPS5 \
296 || (ISA) == ISA_MIPS64 \
297 || (ISA) == ISA_MIPS64R2 \
300 /* Return true if ISA supports 64-bit right rotate (dror et al.)
302 #define ISA_HAS_DROR(ISA) ( \
303 (ISA) == ISA_MIPS64R2 \
306 /* Return true if ISA supports 32-bit right rotate (ror et al.)
308 #define ISA_HAS_ROR(ISA) ( \
309 (ISA) == ISA_MIPS32R2 \
310 || (ISA) == ISA_MIPS64R2 \
313 #define HAVE_32BIT_GPRS \
314 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
316 #define HAVE_32BIT_FPRS \
317 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
319 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
320 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
322 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
324 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
326 /* True if relocations are stored in-place. */
327 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
329 /* The ABI-derived address size. */
330 #define HAVE_64BIT_ADDRESSES \
331 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
332 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
334 /* The size of symbolic constants (i.e., expressions of the form
335 "SYMBOL" or "SYMBOL + OFFSET"). */
336 #define HAVE_32BIT_SYMBOLS \
337 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
338 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
340 /* Addresses are loaded in different ways, depending on the address size
341 in use. The n32 ABI Documentation also mandates the use of additions
342 with overflow checking, but existing implementations don't follow it. */
343 #define ADDRESS_ADD_INSN \
344 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
346 #define ADDRESS_ADDI_INSN \
347 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
349 #define ADDRESS_LOAD_INSN \
350 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
352 #define ADDRESS_STORE_INSN \
353 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
355 /* Return true if the given CPU supports the MIPS16 ASE. */
356 #define CPU_HAS_MIPS16(cpu) \
357 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
358 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
360 /* Return true if the given CPU supports the MIPS3D ASE. */
361 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
364 /* Return true if the given CPU supports the MDMX ASE. */
365 #define CPU_HAS_MDMX(cpu) (FALSE \
368 /* True if CPU has a dror instruction. */
369 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
371 /* True if CPU has a ror instruction. */
372 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
374 /* True if mflo and mfhi can be immediately followed by instructions
375 which write to the HI and LO registers.
377 According to MIPS specifications, MIPS ISAs I, II, and III need
378 (at least) two instructions between the reads of HI/LO and
379 instructions which write them, and later ISAs do not. Contradicting
380 the MIPS specifications, some MIPS IV processor user manuals (e.g.
381 the UM for the NEC Vr5000) document needing the instructions between
382 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
383 MIPS64 and later ISAs to have the interlocks, plus any specific
384 earlier-ISA CPUs for which CPU documentation declares that the
385 instructions are really interlocked. */
386 #define hilo_interlocks \
387 (mips_opts.isa == ISA_MIPS32 \
388 || mips_opts.isa == ISA_MIPS32R2 \
389 || mips_opts.isa == ISA_MIPS64 \
390 || mips_opts.isa == ISA_MIPS64R2 \
391 || mips_opts.arch == CPU_R4010 \
392 || mips_opts.arch == CPU_R10000 \
393 || mips_opts.arch == CPU_R12000 \
394 || mips_opts.arch == CPU_RM7000 \
395 || mips_opts.arch == CPU_VR5500 \
398 /* Whether the processor uses hardware interlocks to protect reads
399 from the GPRs after they are loaded from memory, and thus does not
400 require nops to be inserted. This applies to instructions marked
401 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
403 #define gpr_interlocks \
404 (mips_opts.isa != ISA_MIPS1 \
405 || mips_opts.arch == CPU_R3900)
407 /* Whether the processor uses hardware interlocks to avoid delays
408 required by coprocessor instructions, and thus does not require
409 nops to be inserted. This applies to instructions marked
410 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
411 between instructions marked INSN_WRITE_COND_CODE and ones marked
412 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
413 levels I, II, and III. */
414 /* Itbl support may require additional care here. */
415 #define cop_interlocks \
416 ((mips_opts.isa != ISA_MIPS1 \
417 && mips_opts.isa != ISA_MIPS2 \
418 && mips_opts.isa != ISA_MIPS3) \
419 || mips_opts.arch == CPU_R4300 \
422 /* Whether the processor uses hardware interlocks to protect reads
423 from coprocessor registers after they are loaded from memory, and
424 thus does not require nops to be inserted. This applies to
425 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
426 requires at MIPS ISA level I. */
427 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
429 /* Is this a mfhi or mflo instruction? */
430 #define MF_HILO_INSN(PINFO) \
431 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
433 /* MIPS PIC level. */
435 enum mips_pic_level mips_pic
;
437 /* 1 if we should generate 32 bit offsets from the $gp register in
438 SVR4_PIC mode. Currently has no meaning in other modes. */
439 static int mips_big_got
= 0;
441 /* 1 if trap instructions should used for overflow rather than break
443 static int mips_trap
= 0;
445 /* 1 if double width floating point constants should not be constructed
446 by assembling two single width halves into two single width floating
447 point registers which just happen to alias the double width destination
448 register. On some architectures this aliasing can be disabled by a bit
449 in the status register, and the setting of this bit cannot be determined
450 automatically at assemble time. */
451 static int mips_disable_float_construction
;
453 /* Non-zero if any .set noreorder directives were used. */
455 static int mips_any_noreorder
;
457 /* Non-zero if nops should be inserted when the register referenced in
458 an mfhi/mflo instruction is read in the next two instructions. */
459 static int mips_7000_hilo_fix
;
461 /* The size of the small data section. */
462 static unsigned int g_switch_value
= 8;
463 /* Whether the -G option was used. */
464 static int g_switch_seen
= 0;
469 /* If we can determine in advance that GP optimization won't be
470 possible, we can skip the relaxation stuff that tries to produce
471 GP-relative references. This makes delay slot optimization work
474 This function can only provide a guess, but it seems to work for
475 gcc output. It needs to guess right for gcc, otherwise gcc
476 will put what it thinks is a GP-relative instruction in a branch
479 I don't know if a fix is needed for the SVR4_PIC mode. I've only
480 fixed it for the non-PIC mode. KR 95/04/07 */
481 static int nopic_need_relax (symbolS
*, int);
483 /* handle of the OPCODE hash table */
484 static struct hash_control
*op_hash
= NULL
;
486 /* The opcode hash table we use for the mips16. */
487 static struct hash_control
*mips16_op_hash
= NULL
;
489 /* This array holds the chars that always start a comment. If the
490 pre-processor is disabled, these aren't very useful */
491 const char comment_chars
[] = "#";
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output */
496 /* Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output. */
499 /* Also note that C style comments are always supported. */
500 const char line_comment_chars
[] = "#";
502 /* This array holds machine specific line separator characters. */
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point nums */
506 const char EXP_CHARS
[] = "eE";
508 /* Chars that mean this number is a floating point constant */
511 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
513 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
514 changed in read.c . Ideally it shouldn't have to know about it at all,
515 but nothing is ideal around here.
518 static char *insn_error
;
520 static int auto_align
= 1;
522 /* When outputting SVR4 PIC code, the assembler needs to know the
523 offset in the stack frame from which to restore the $gp register.
524 This is set by the .cprestore pseudo-op, and saved in this
526 static offsetT mips_cprestore_offset
= -1;
528 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
529 more optimizations, it can use a register value instead of a memory-saved
530 offset and even an other register than $gp as global pointer. */
531 static offsetT mips_cpreturn_offset
= -1;
532 static int mips_cpreturn_register
= -1;
533 static int mips_gp_register
= GP
;
534 static int mips_gprel_offset
= 0;
536 /* Whether mips_cprestore_offset has been set in the current function
537 (or whether it has already been warned about, if not). */
538 static int mips_cprestore_valid
= 0;
540 /* This is the register which holds the stack frame, as set by the
541 .frame pseudo-op. This is needed to implement .cprestore. */
542 static int mips_frame_reg
= SP
;
544 /* Whether mips_frame_reg has been set in the current function
545 (or whether it has already been warned about, if not). */
546 static int mips_frame_reg_valid
= 0;
548 /* To output NOP instructions correctly, we need to keep information
549 about the previous two instructions. */
551 /* Whether we are optimizing. The default value of 2 means to remove
552 unneeded NOPs and swap branch instructions when possible. A value
553 of 1 means to not swap branches. A value of 0 means to always
555 static int mips_optimize
= 2;
557 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
558 equivalent to seeing no -g option at all. */
559 static int mips_debug
= 0;
561 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
562 #define MAX_VR4130_NOPS 4
564 /* The maximum number of NOPs needed to fill delay slots. */
565 #define MAX_DELAY_NOPS 2
567 /* The maximum number of NOPs needed for any purpose. */
570 /* A list of previous instructions, with index 0 being the most recent.
571 We need to look back MAX_NOPS instructions when filling delay slots
572 or working around processor errata. We need to look back one
573 instruction further if we're thinking about using history[0] to
574 fill a branch delay slot. */
575 static struct mips_cl_insn history
[1 + MAX_NOPS
];
577 /* Nop instructions used by emit_nop. */
578 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
580 /* The appropriate nop for the current mode. */
581 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
583 /* If this is set, it points to a frag holding nop instructions which
584 were inserted before the start of a noreorder section. If those
585 nops turn out to be unnecessary, the size of the frag can be
587 static fragS
*prev_nop_frag
;
589 /* The number of nop instructions we created in prev_nop_frag. */
590 static int prev_nop_frag_holds
;
592 /* The number of nop instructions that we know we need in
594 static int prev_nop_frag_required
;
596 /* The number of instructions we've seen since prev_nop_frag. */
597 static int prev_nop_frag_since
;
599 /* For ECOFF and ELF, relocations against symbols are done in two
600 parts, with a HI relocation and a LO relocation. Each relocation
601 has only 16 bits of space to store an addend. This means that in
602 order for the linker to handle carries correctly, it must be able
603 to locate both the HI and the LO relocation. This means that the
604 relocations must appear in order in the relocation table.
606 In order to implement this, we keep track of each unmatched HI
607 relocation. We then sort them so that they immediately precede the
608 corresponding LO relocation. */
613 struct mips_hi_fixup
*next
;
616 /* The section this fixup is in. */
620 /* The list of unmatched HI relocs. */
622 static struct mips_hi_fixup
*mips_hi_fixup_list
;
624 /* The frag containing the last explicit relocation operator.
625 Null if explicit relocations have not been used. */
627 static fragS
*prev_reloc_op_frag
;
629 /* Map normal MIPS register numbers to mips16 register numbers. */
631 #define X ILLEGAL_REG
632 static const int mips32_to_16_reg_map
[] =
634 X
, X
, 2, 3, 4, 5, 6, 7,
635 X
, X
, X
, X
, X
, X
, X
, X
,
636 0, 1, X
, X
, X
, X
, X
, X
,
637 X
, X
, X
, X
, X
, X
, X
, X
641 /* Map mips16 register numbers to normal MIPS register numbers. */
643 static const unsigned int mips16_to_32_reg_map
[] =
645 16, 17, 2, 3, 4, 5, 6, 7
648 /* Classifies the kind of instructions we're interested in when
649 implementing -mfix-vr4120. */
650 enum fix_vr4120_class
{
657 NUM_FIX_VR4120_CLASSES
660 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
661 there must be at least one other instruction between an instruction
662 of type X and an instruction of type Y. */
663 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
665 /* True if -mfix-vr4120 is in force. */
666 static int mips_fix_vr4120
;
668 /* ...likewise -mfix-vr4130. */
669 static int mips_fix_vr4130
;
671 /* We don't relax branches by default, since this causes us to expand
672 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
673 fail to compute the offset before expanding the macro to the most
674 efficient expansion. */
676 static int mips_relax_branch
;
678 /* The expansion of many macros depends on the type of symbol that
679 they refer to. For example, when generating position-dependent code,
680 a macro that refers to a symbol may have two different expansions,
681 one which uses GP-relative addresses and one which uses absolute
682 addresses. When generating SVR4-style PIC, a macro may have
683 different expansions for local and global symbols.
685 We handle these situations by generating both sequences and putting
686 them in variant frags. In position-dependent code, the first sequence
687 will be the GP-relative one and the second sequence will be the
688 absolute one. In SVR4 PIC, the first sequence will be for global
689 symbols and the second will be for local symbols.
691 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
692 SECOND are the lengths of the two sequences in bytes. These fields
693 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
694 the subtype has the following flags:
697 Set if it has been decided that we should use the second
698 sequence instead of the first.
701 Set in the first variant frag if the macro's second implementation
702 is longer than its first. This refers to the macro as a whole,
703 not an individual relaxation.
706 Set in the first variant frag if the macro appeared in a .set nomacro
707 block and if one alternative requires a warning but the other does not.
710 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
713 The frag's "opcode" points to the first fixup for relaxable code.
715 Relaxable macros are generated using a sequence such as:
717 relax_start (SYMBOL);
718 ... generate first expansion ...
720 ... generate second expansion ...
723 The code and fixups for the unwanted alternative are discarded
724 by md_convert_frag. */
725 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
727 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
728 #define RELAX_SECOND(X) ((X) & 0xff)
729 #define RELAX_USE_SECOND 0x10000
730 #define RELAX_SECOND_LONGER 0x20000
731 #define RELAX_NOMACRO 0x40000
732 #define RELAX_DELAY_SLOT 0x80000
734 /* Branch without likely bit. If label is out of range, we turn:
736 beq reg1, reg2, label
746 with the following opcode replacements:
753 bltzal <-> bgezal (with jal label instead of j label)
755 Even though keeping the delay slot instruction in the delay slot of
756 the branch would be more efficient, it would be very tricky to do
757 correctly, because we'd have to introduce a variable frag *after*
758 the delay slot instruction, and expand that instead. Let's do it
759 the easy way for now, even if the branch-not-taken case now costs
760 one additional instruction. Out-of-range branches are not supposed
761 to be common, anyway.
763 Branch likely. If label is out of range, we turn:
765 beql reg1, reg2, label
766 delay slot (annulled if branch not taken)
775 delay slot (executed only if branch taken)
778 It would be possible to generate a shorter sequence by losing the
779 likely bit, generating something like:
784 delay slot (executed only if branch taken)
796 bltzall -> bgezal (with jal label instead of j label)
797 bgezall -> bltzal (ditto)
800 but it's not clear that it would actually improve performance. */
801 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
804 | ((toofar) ? 1 : 0) \
806 | ((likely) ? 4 : 0) \
807 | ((uncond) ? 8 : 0)))
808 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
809 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
810 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
811 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
812 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
814 /* For mips16 code, we use an entirely different form of relaxation.
815 mips16 supports two versions of most instructions which take
816 immediate values: a small one which takes some small value, and a
817 larger one which takes a 16 bit value. Since branches also follow
818 this pattern, relaxing these values is required.
820 We can assemble both mips16 and normal MIPS code in a single
821 object. Therefore, we need to support this type of relaxation at
822 the same time that we support the relaxation described above. We
823 use the high bit of the subtype field to distinguish these cases.
825 The information we store for this type of relaxation is the
826 argument code found in the opcode file for this relocation, whether
827 the user explicitly requested a small or extended form, and whether
828 the relocation is in a jump or jal delay slot. That tells us the
829 size of the value, and how it should be stored. We also store
830 whether the fragment is considered to be extended or not. We also
831 store whether this is known to be a branch to a different section,
832 whether we have tried to relax this frag yet, and whether we have
833 ever extended a PC relative fragment because of a shift count. */
834 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
837 | ((small) ? 0x100 : 0) \
838 | ((ext) ? 0x200 : 0) \
839 | ((dslot) ? 0x400 : 0) \
840 | ((jal_dslot) ? 0x800 : 0))
841 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
842 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
843 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
844 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
845 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
846 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
847 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
848 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
849 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
850 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
851 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
852 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
854 /* Is the given value a sign-extended 32-bit value? */
855 #define IS_SEXT_32BIT_NUM(x) \
856 (((x) &~ (offsetT) 0x7fffffff) == 0 \
857 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
859 /* Is the given value a sign-extended 16-bit value? */
860 #define IS_SEXT_16BIT_NUM(x) \
861 (((x) &~ (offsetT) 0x7fff) == 0 \
862 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
864 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
865 #define IS_ZEXT_32BIT_NUM(x) \
866 (((x) &~ (offsetT) 0xffffffff) == 0 \
867 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
869 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
870 VALUE << SHIFT. VALUE is evaluated exactly once. */
871 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
872 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
873 | (((VALUE) & (MASK)) << (SHIFT)))
875 /* Extract bits MASK << SHIFT from STRUCT and shift them right
877 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
878 (((STRUCT) >> (SHIFT)) & (MASK))
880 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
881 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
883 include/opcode/mips.h specifies operand fields using the macros
884 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
885 with "MIPS16OP" instead of "OP". */
886 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
887 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
888 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
889 INSERT_BITS ((INSN).insn_opcode, VALUE, \
890 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
892 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
893 #define EXTRACT_OPERAND(FIELD, INSN) \
894 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
895 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
896 EXTRACT_BITS ((INSN).insn_opcode, \
897 MIPS16OP_MASK_##FIELD, \
900 /* Global variables used when generating relaxable macros. See the
901 comment above RELAX_ENCODE for more details about how relaxation
904 /* 0 if we're not emitting a relaxable macro.
905 1 if we're emitting the first of the two relaxation alternatives.
906 2 if we're emitting the second alternative. */
909 /* The first relaxable fixup in the current frag. (In other words,
910 the first fixup that refers to relaxable code.) */
913 /* sizes[0] says how many bytes of the first alternative are stored in
914 the current frag. Likewise sizes[1] for the second alternative. */
915 unsigned int sizes
[2];
917 /* The symbol on which the choice of sequence depends. */
921 /* Global variables used to decide whether a macro needs a warning. */
923 /* True if the macro is in a branch delay slot. */
924 bfd_boolean delay_slot_p
;
926 /* For relaxable macros, sizes[0] is the length of the first alternative
927 in bytes and sizes[1] is the length of the second alternative.
928 For non-relaxable macros, both elements give the length of the
930 unsigned int sizes
[2];
932 /* The first variant frag for this macro. */
934 } mips_macro_warning
;
936 /* Prototypes for static functions. */
938 #define internalError() \
939 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
941 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
943 static void append_insn
944 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
945 static void mips_no_prev_insn (void);
946 static void mips16_macro_build
947 (expressionS
*, const char *, const char *, va_list);
948 static void load_register (int, expressionS
*, int);
949 static void macro_start (void);
950 static void macro_end (void);
951 static void macro (struct mips_cl_insn
* ip
);
952 static void mips16_macro (struct mips_cl_insn
* ip
);
953 #ifdef LOSING_COMPILER
954 static void macro2 (struct mips_cl_insn
* ip
);
956 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
957 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
958 static void mips16_immed
959 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
960 unsigned long *, bfd_boolean
*, unsigned short *);
961 static size_t my_getSmallExpression
962 (expressionS
*, bfd_reloc_code_real_type
*, char *);
963 static void my_getExpression (expressionS
*, char *);
964 static void s_align (int);
965 static void s_change_sec (int);
966 static void s_change_section (int);
967 static void s_cons (int);
968 static void s_float_cons (int);
969 static void s_mips_globl (int);
970 static void s_option (int);
971 static void s_mipsset (int);
972 static void s_abicalls (int);
973 static void s_cpload (int);
974 static void s_cpsetup (int);
975 static void s_cplocal (int);
976 static void s_cprestore (int);
977 static void s_cpreturn (int);
978 static void s_gpvalue (int);
979 static void s_gpword (int);
980 static void s_gpdword (int);
981 static void s_cpadd (int);
982 static void s_insn (int);
983 static void md_obj_begin (void);
984 static void md_obj_end (void);
985 static void s_mips_ent (int);
986 static void s_mips_end (int);
987 static void s_mips_frame (int);
988 static void s_mips_mask (int reg_type
);
989 static void s_mips_stab (int);
990 static void s_mips_weakext (int);
991 static void s_mips_file (int);
992 static void s_mips_loc (int);
993 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
994 static int relaxed_branch_length (fragS
*, asection
*, int);
995 static int validate_mips_insn (const struct mips_opcode
*);
997 /* Table and functions used to map between CPU/ISA names, and
998 ISA levels, and CPU numbers. */
1000 struct mips_cpu_info
1002 const char *name
; /* CPU or ISA name. */
1003 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1004 int isa
; /* ISA level. */
1005 int cpu
; /* CPU number (default CPU if ISA). */
1008 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1009 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1010 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1014 The following pseudo-ops from the Kane and Heinrich MIPS book
1015 should be defined here, but are currently unsupported: .alias,
1016 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1018 The following pseudo-ops from the Kane and Heinrich MIPS book are
1019 specific to the type of debugging information being generated, and
1020 should be defined by the object format: .aent, .begin, .bend,
1021 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1024 The following pseudo-ops from the Kane and Heinrich MIPS book are
1025 not MIPS CPU specific, but are also not specific to the object file
1026 format. This file is probably the best place to define them, but
1027 they are not currently supported: .asm0, .endr, .lab, .repeat,
1030 static const pseudo_typeS mips_pseudo_table
[] =
1032 /* MIPS specific pseudo-ops. */
1033 {"option", s_option
, 0},
1034 {"set", s_mipsset
, 0},
1035 {"rdata", s_change_sec
, 'r'},
1036 {"sdata", s_change_sec
, 's'},
1037 {"livereg", s_ignore
, 0},
1038 {"abicalls", s_abicalls
, 0},
1039 {"cpload", s_cpload
, 0},
1040 {"cpsetup", s_cpsetup
, 0},
1041 {"cplocal", s_cplocal
, 0},
1042 {"cprestore", s_cprestore
, 0},
1043 {"cpreturn", s_cpreturn
, 0},
1044 {"gpvalue", s_gpvalue
, 0},
1045 {"gpword", s_gpword
, 0},
1046 {"gpdword", s_gpdword
, 0},
1047 {"cpadd", s_cpadd
, 0},
1048 {"insn", s_insn
, 0},
1050 /* Relatively generic pseudo-ops that happen to be used on MIPS
1052 {"asciiz", stringer
, 1},
1053 {"bss", s_change_sec
, 'b'},
1055 {"half", s_cons
, 1},
1056 {"dword", s_cons
, 3},
1057 {"weakext", s_mips_weakext
, 0},
1059 /* These pseudo-ops are defined in read.c, but must be overridden
1060 here for one reason or another. */
1061 {"align", s_align
, 0},
1062 {"byte", s_cons
, 0},
1063 {"data", s_change_sec
, 'd'},
1064 {"double", s_float_cons
, 'd'},
1065 {"float", s_float_cons
, 'f'},
1066 {"globl", s_mips_globl
, 0},
1067 {"global", s_mips_globl
, 0},
1068 {"hword", s_cons
, 1},
1070 {"long", s_cons
, 2},
1071 {"octa", s_cons
, 4},
1072 {"quad", s_cons
, 3},
1073 {"section", s_change_section
, 0},
1074 {"short", s_cons
, 1},
1075 {"single", s_float_cons
, 'f'},
1076 {"stabn", s_mips_stab
, 'n'},
1077 {"text", s_change_sec
, 't'},
1078 {"word", s_cons
, 2},
1080 { "extern", ecoff_directive_extern
, 0},
1085 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1087 /* These pseudo-ops should be defined by the object file format.
1088 However, a.out doesn't support them, so we have versions here. */
1089 {"aent", s_mips_ent
, 1},
1090 {"bgnb", s_ignore
, 0},
1091 {"end", s_mips_end
, 0},
1092 {"endb", s_ignore
, 0},
1093 {"ent", s_mips_ent
, 0},
1094 {"file", s_mips_file
, 0},
1095 {"fmask", s_mips_mask
, 'F'},
1096 {"frame", s_mips_frame
, 0},
1097 {"loc", s_mips_loc
, 0},
1098 {"mask", s_mips_mask
, 'R'},
1099 {"verstamp", s_ignore
, 0},
1103 extern void pop_insert (const pseudo_typeS
*);
1106 mips_pop_insert (void)
1108 pop_insert (mips_pseudo_table
);
1109 if (! ECOFF_DEBUGGING
)
1110 pop_insert (mips_nonecoff_pseudo_table
);
1113 /* Symbols labelling the current insn. */
1115 struct insn_label_list
1117 struct insn_label_list
*next
;
1121 static struct insn_label_list
*insn_labels
;
1122 static struct insn_label_list
*free_insn_labels
;
1124 static void mips_clear_insn_labels (void);
1127 mips_clear_insn_labels (void)
1129 register struct insn_label_list
**pl
;
1131 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1137 static char *expr_end
;
1139 /* Expressions which appear in instructions. These are set by
1142 static expressionS imm_expr
;
1143 static expressionS imm2_expr
;
1144 static expressionS offset_expr
;
1146 /* Relocs associated with imm_expr and offset_expr. */
1148 static bfd_reloc_code_real_type imm_reloc
[3]
1149 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1150 static bfd_reloc_code_real_type offset_reloc
[3]
1151 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1153 /* These are set by mips16_ip if an explicit extension is used. */
1155 static bfd_boolean mips16_small
, mips16_ext
;
1158 /* The pdr segment for per procedure frame/regmask info. Not used for
1161 static segT pdr_seg
;
1164 /* The default target format to use. */
1167 mips_target_format (void)
1169 switch (OUTPUT_FLAVOR
)
1171 case bfd_target_ecoff_flavour
:
1172 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1173 case bfd_target_coff_flavour
:
1175 case bfd_target_elf_flavour
:
1177 /* This is traditional mips. */
1178 return (target_big_endian
1179 ? (HAVE_64BIT_OBJECTS
1180 ? "elf64-tradbigmips"
1182 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1183 : (HAVE_64BIT_OBJECTS
1184 ? "elf64-tradlittlemips"
1186 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1188 return (target_big_endian
1189 ? (HAVE_64BIT_OBJECTS
1192 ? "elf32-nbigmips" : "elf32-bigmips"))
1193 : (HAVE_64BIT_OBJECTS
1194 ? "elf64-littlemips"
1196 ? "elf32-nlittlemips" : "elf32-littlemips")));
1204 /* Return the length of instruction INSN. */
1206 static inline unsigned int
1207 insn_length (const struct mips_cl_insn
*insn
)
1209 if (!mips_opts
.mips16
)
1211 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1214 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1217 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1222 insn
->use_extend
= FALSE
;
1224 insn
->insn_opcode
= mo
->match
;
1227 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1228 insn
->fixp
[i
] = NULL
;
1229 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1230 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1231 insn
->mips16_absolute_jump_p
= 0;
1234 /* Install INSN at the location specified by its "frag" and "where" fields. */
1237 install_insn (const struct mips_cl_insn
*insn
)
1239 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1240 if (!mips_opts
.mips16
)
1241 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1242 else if (insn
->mips16_absolute_jump_p
)
1244 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1245 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1249 if (insn
->use_extend
)
1251 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1254 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1258 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1259 and install the opcode in the new location. */
1262 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1267 insn
->where
= where
;
1268 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1269 if (insn
->fixp
[i
] != NULL
)
1271 insn
->fixp
[i
]->fx_frag
= frag
;
1272 insn
->fixp
[i
]->fx_where
= where
;
1274 install_insn (insn
);
1277 /* Add INSN to the end of the output. */
1280 add_fixed_insn (struct mips_cl_insn
*insn
)
1282 char *f
= frag_more (insn_length (insn
));
1283 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1286 /* Start a variant frag and move INSN to the start of the variant part,
1287 marking it as fixed. The other arguments are as for frag_var. */
1290 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1291 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1293 frag_grow (max_chars
);
1294 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1296 frag_var (rs_machine_dependent
, max_chars
, var
,
1297 subtype
, symbol
, offset
, NULL
);
1300 /* Insert N copies of INSN into the history buffer, starting at
1301 position FIRST. Neither FIRST nor N need to be clipped. */
1304 insert_into_history (unsigned int first
, unsigned int n
,
1305 const struct mips_cl_insn
*insn
)
1307 if (mips_relax
.sequence
!= 2)
1311 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1313 history
[i
] = history
[i
- n
];
1319 /* Emit a nop instruction, recording it in the history buffer. */
1324 add_fixed_insn (NOP_INSN
);
1325 insert_into_history (0, 1, NOP_INSN
);
1328 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1329 the idea is to make it obvious at a glance that each errata is
1333 init_vr4120_conflicts (void)
1335 #define CONFLICT(FIRST, SECOND) \
1336 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1338 /* Errata 21 - [D]DIV[U] after [D]MACC */
1339 CONFLICT (MACC
, DIV
);
1340 CONFLICT (DMACC
, DIV
);
1342 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1343 CONFLICT (DMULT
, DMULT
);
1344 CONFLICT (DMULT
, DMACC
);
1345 CONFLICT (DMACC
, DMULT
);
1346 CONFLICT (DMACC
, DMACC
);
1348 /* Errata 24 - MT{LO,HI} after [D]MACC */
1349 CONFLICT (MACC
, MTHILO
);
1350 CONFLICT (DMACC
, MTHILO
);
1352 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1353 instruction is executed immediately after a MACC or DMACC
1354 instruction, the result of [either instruction] is incorrect." */
1355 CONFLICT (MACC
, MULT
);
1356 CONFLICT (MACC
, DMULT
);
1357 CONFLICT (DMACC
, MULT
);
1358 CONFLICT (DMACC
, DMULT
);
1360 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1361 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1362 DDIV or DDIVU instruction, the result of the MACC or
1363 DMACC instruction is incorrect.". */
1364 CONFLICT (DMULT
, MACC
);
1365 CONFLICT (DMULT
, DMACC
);
1366 CONFLICT (DIV
, MACC
);
1367 CONFLICT (DIV
, DMACC
);
1372 /* This function is called once, at assembler startup time. It should
1373 set up all the tables, etc. that the MD part of the assembler will need. */
1378 register const char *retval
= NULL
;
1382 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1383 as_warn (_("Could not set architecture and machine"));
1385 op_hash
= hash_new ();
1387 for (i
= 0; i
< NUMOPCODES
;)
1389 const char *name
= mips_opcodes
[i
].name
;
1391 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1394 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1395 mips_opcodes
[i
].name
, retval
);
1396 /* Probably a memory allocation problem? Give up now. */
1397 as_fatal (_("Broken assembler. No assembly attempted."));
1401 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1403 if (!validate_mips_insn (&mips_opcodes
[i
]))
1405 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1407 create_insn (&nop_insn
, mips_opcodes
+ i
);
1408 nop_insn
.fixed_p
= 1;
1413 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1416 mips16_op_hash
= hash_new ();
1419 while (i
< bfd_mips16_num_opcodes
)
1421 const char *name
= mips16_opcodes
[i
].name
;
1423 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1425 as_fatal (_("internal: can't hash `%s': %s"),
1426 mips16_opcodes
[i
].name
, retval
);
1429 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1430 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1431 != mips16_opcodes
[i
].match
))
1433 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1434 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1437 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1439 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1440 mips16_nop_insn
.fixed_p
= 1;
1444 while (i
< bfd_mips16_num_opcodes
1445 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1449 as_fatal (_("Broken assembler. No assembly attempted."));
1451 /* We add all the general register names to the symbol table. This
1452 helps us detect invalid uses of them. */
1453 for (i
= 0; i
< 32; i
++)
1457 sprintf (buf
, "$%d", i
);
1458 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1459 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1464 &zero_address_frag
));
1465 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1466 &zero_address_frag
));
1467 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1468 &zero_address_frag
));
1469 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1470 &zero_address_frag
));
1471 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1472 &zero_address_frag
));
1473 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1474 &zero_address_frag
));
1475 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1476 &zero_address_frag
));
1477 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1478 &zero_address_frag
));
1480 /* If we don't add these register names to the symbol table, they
1481 may end up being added as regular symbols by operand(), and then
1482 make it to the object file as undefined in case they're not
1483 regarded as local symbols. They're local in o32, since `$' is a
1484 local symbol prefix, but not in n32 or n64. */
1485 for (i
= 0; i
< 8; i
++)
1489 sprintf (buf
, "$fcc%i", i
);
1490 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1491 &zero_address_frag
));
1494 mips_no_prev_insn ();
1497 mips_cprmask
[0] = 0;
1498 mips_cprmask
[1] = 0;
1499 mips_cprmask
[2] = 0;
1500 mips_cprmask
[3] = 0;
1502 /* set the default alignment for the text section (2**2) */
1503 record_alignment (text_section
, 2);
1505 bfd_set_gp_size (stdoutput
, g_switch_value
);
1507 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1509 /* On a native system, sections must be aligned to 16 byte
1510 boundaries. When configured for an embedded ELF target, we
1512 if (strcmp (TARGET_OS
, "elf") != 0)
1514 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1515 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1516 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1519 /* Create a .reginfo section for register masks and a .mdebug
1520 section for debugging information. */
1528 subseg
= now_subseg
;
1530 /* The ABI says this section should be loaded so that the
1531 running program can access it. However, we don't load it
1532 if we are configured for an embedded target */
1533 flags
= SEC_READONLY
| SEC_DATA
;
1534 if (strcmp (TARGET_OS
, "elf") != 0)
1535 flags
|= SEC_ALLOC
| SEC_LOAD
;
1537 if (mips_abi
!= N64_ABI
)
1539 sec
= subseg_new (".reginfo", (subsegT
) 0);
1541 bfd_set_section_flags (stdoutput
, sec
, flags
);
1542 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1545 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1550 /* The 64-bit ABI uses a .MIPS.options section rather than
1551 .reginfo section. */
1552 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1553 bfd_set_section_flags (stdoutput
, sec
, flags
);
1554 bfd_set_section_alignment (stdoutput
, sec
, 3);
1557 /* Set up the option header. */
1559 Elf_Internal_Options opthdr
;
1562 opthdr
.kind
= ODK_REGINFO
;
1563 opthdr
.size
= (sizeof (Elf_External_Options
)
1564 + sizeof (Elf64_External_RegInfo
));
1567 f
= frag_more (sizeof (Elf_External_Options
));
1568 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1569 (Elf_External_Options
*) f
);
1571 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1576 if (ECOFF_DEBUGGING
)
1578 sec
= subseg_new (".mdebug", (subsegT
) 0);
1579 (void) bfd_set_section_flags (stdoutput
, sec
,
1580 SEC_HAS_CONTENTS
| SEC_READONLY
);
1581 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1584 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1586 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1587 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1588 SEC_READONLY
| SEC_RELOC
1590 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1594 subseg_set (seg
, subseg
);
1598 if (! ECOFF_DEBUGGING
)
1601 if (mips_fix_vr4120
)
1602 init_vr4120_conflicts ();
1608 if (! ECOFF_DEBUGGING
)
1613 md_assemble (char *str
)
1615 struct mips_cl_insn insn
;
1616 bfd_reloc_code_real_type unused_reloc
[3]
1617 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1619 imm_expr
.X_op
= O_absent
;
1620 imm2_expr
.X_op
= O_absent
;
1621 offset_expr
.X_op
= O_absent
;
1622 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1623 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1624 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1625 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1626 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1627 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1629 if (mips_opts
.mips16
)
1630 mips16_ip (str
, &insn
);
1633 mips_ip (str
, &insn
);
1634 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1635 str
, insn
.insn_opcode
));
1640 as_bad ("%s `%s'", insn_error
, str
);
1644 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1647 if (mips_opts
.mips16
)
1648 mips16_macro (&insn
);
1655 if (imm_expr
.X_op
!= O_absent
)
1656 append_insn (&insn
, &imm_expr
, imm_reloc
);
1657 else if (offset_expr
.X_op
!= O_absent
)
1658 append_insn (&insn
, &offset_expr
, offset_reloc
);
1660 append_insn (&insn
, NULL
, unused_reloc
);
1664 /* Return true if the given relocation might need a matching %lo().
1665 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1666 applied to local symbols. */
1668 static inline bfd_boolean
1669 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1671 return (HAVE_IN_PLACE_ADDENDS
1672 && (reloc
== BFD_RELOC_HI16_S
1673 || reloc
== BFD_RELOC_MIPS_GOT16
1674 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1677 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1680 static inline bfd_boolean
1681 fixup_has_matching_lo_p (fixS
*fixp
)
1683 return (fixp
->fx_next
!= NULL
1684 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1685 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1686 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1687 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1690 /* See whether instruction IP reads register REG. CLASS is the type
1694 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1695 enum mips_regclass
class)
1697 if (class == MIPS16_REG
)
1699 assert (mips_opts
.mips16
);
1700 reg
= mips16_to_32_reg_map
[reg
];
1701 class = MIPS_GR_REG
;
1704 /* Don't report on general register ZERO, since it never changes. */
1705 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1708 if (class == MIPS_FP_REG
)
1710 assert (! mips_opts
.mips16
);
1711 /* If we are called with either $f0 or $f1, we must check $f0.
1712 This is not optimal, because it will introduce an unnecessary
1713 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1714 need to distinguish reading both $f0 and $f1 or just one of
1715 them. Note that we don't have to check the other way,
1716 because there is no instruction that sets both $f0 and $f1
1717 and requires a delay. */
1718 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1719 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1720 == (reg
&~ (unsigned) 1)))
1722 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1723 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1724 == (reg
&~ (unsigned) 1)))
1727 else if (! mips_opts
.mips16
)
1729 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1730 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1732 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1733 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1739 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1741 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1742 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1744 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1745 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1748 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1750 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1752 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1754 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1755 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1762 /* This function returns true if modifying a register requires a
1766 reg_needs_delay (unsigned int reg
)
1768 unsigned long prev_pinfo
;
1770 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1771 if (! mips_opts
.noreorder
1772 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1773 && ! gpr_interlocks
)
1774 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1775 && ! cop_interlocks
)))
1777 /* A load from a coprocessor or from memory. All load delays
1778 delay the use of general register rt for one instruction. */
1779 /* Itbl support may require additional care here. */
1780 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1781 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1788 /* Move all labels in insn_labels to the current insertion point. */
1791 mips_move_labels (void)
1793 struct insn_label_list
*l
;
1796 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1798 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1799 symbol_set_frag (l
->label
, frag_now
);
1800 val
= (valueT
) frag_now_fix ();
1801 /* mips16 text labels are stored as odd. */
1802 if (mips_opts
.mips16
)
1804 S_SET_VALUE (l
->label
, val
);
1808 /* Mark instruction labels in mips16 mode. This permits the linker to
1809 handle them specially, such as generating jalx instructions when
1810 needed. We also make them odd for the duration of the assembly, in
1811 order to generate the right sort of code. We will make them even
1812 in the adjust_symtab routine, while leaving them marked. This is
1813 convenient for the debugger and the disassembler. The linker knows
1814 to make them odd again. */
1817 mips16_mark_labels (void)
1819 if (mips_opts
.mips16
)
1821 struct insn_label_list
*l
;
1824 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1827 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1828 S_SET_OTHER (l
->label
, STO_MIPS16
);
1830 val
= S_GET_VALUE (l
->label
);
1832 S_SET_VALUE (l
->label
, val
+ 1);
1837 /* End the current frag. Make it a variant frag and record the
1841 relax_close_frag (void)
1843 mips_macro_warning
.first_frag
= frag_now
;
1844 frag_var (rs_machine_dependent
, 0, 0,
1845 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1846 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1848 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1849 mips_relax
.first_fixup
= 0;
1852 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1853 See the comment above RELAX_ENCODE for more details. */
1856 relax_start (symbolS
*symbol
)
1858 assert (mips_relax
.sequence
== 0);
1859 mips_relax
.sequence
= 1;
1860 mips_relax
.symbol
= symbol
;
1863 /* Start generating the second version of a relaxable sequence.
1864 See the comment above RELAX_ENCODE for more details. */
1869 assert (mips_relax
.sequence
== 1);
1870 mips_relax
.sequence
= 2;
1873 /* End the current relaxable sequence. */
1878 assert (mips_relax
.sequence
== 2);
1879 relax_close_frag ();
1880 mips_relax
.sequence
= 0;
1883 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1884 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1885 by VR4120 errata. */
1888 classify_vr4120_insn (const char *name
)
1890 if (strncmp (name
, "macc", 4) == 0)
1891 return FIX_VR4120_MACC
;
1892 if (strncmp (name
, "dmacc", 5) == 0)
1893 return FIX_VR4120_DMACC
;
1894 if (strncmp (name
, "mult", 4) == 0)
1895 return FIX_VR4120_MULT
;
1896 if (strncmp (name
, "dmult", 5) == 0)
1897 return FIX_VR4120_DMULT
;
1898 if (strstr (name
, "div"))
1899 return FIX_VR4120_DIV
;
1900 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1901 return FIX_VR4120_MTHILO
;
1902 return NUM_FIX_VR4120_CLASSES
;
1905 /* Return the number of instructions that must separate INSN1 and INSN2,
1906 where INSN1 is the earlier instruction. Return the worst-case value
1907 for any INSN2 if INSN2 is null. */
1910 insns_between (const struct mips_cl_insn
*insn1
,
1911 const struct mips_cl_insn
*insn2
)
1913 unsigned long pinfo1
, pinfo2
;
1915 /* This function needs to know which pinfo flags are set for INSN2
1916 and which registers INSN2 uses. The former is stored in PINFO2 and
1917 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1918 will have every flag set and INSN2_USES_REG will always return true. */
1919 pinfo1
= insn1
->insn_mo
->pinfo
;
1920 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1922 #define INSN2_USES_REG(REG, CLASS) \
1923 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1925 /* For most targets, write-after-read dependencies on the HI and LO
1926 registers must be separated by at least two instructions. */
1927 if (!hilo_interlocks
)
1929 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1931 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1935 /* If we're working around r7000 errata, there must be two instructions
1936 between an mfhi or mflo and any instruction that uses the result. */
1937 if (mips_7000_hilo_fix
1938 && MF_HILO_INSN (pinfo1
)
1939 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1942 /* If working around VR4120 errata, check for combinations that need
1943 a single intervening instruction. */
1944 if (mips_fix_vr4120
)
1946 unsigned int class1
, class2
;
1948 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1949 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1953 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1954 if (vr4120_conflicts
[class1
] & (1 << class2
))
1959 if (!mips_opts
.mips16
)
1961 /* Check for GPR or coprocessor load delays. All such delays
1962 are on the RT register. */
1963 /* Itbl support may require additional care here. */
1964 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1965 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1967 know (pinfo1
& INSN_WRITE_GPR_T
);
1968 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1972 /* Check for generic coprocessor hazards.
1974 This case is not handled very well. There is no special
1975 knowledge of CP0 handling, and the coprocessors other than
1976 the floating point unit are not distinguished at all. */
1977 /* Itbl support may require additional care here. FIXME!
1978 Need to modify this to include knowledge about
1979 user specified delays! */
1980 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1981 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1983 /* Handle cases where INSN1 writes to a known general coprocessor
1984 register. There must be a one instruction delay before INSN2
1985 if INSN2 reads that register, otherwise no delay is needed. */
1986 if (pinfo1
& INSN_WRITE_FPR_T
)
1988 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1991 else if (pinfo1
& INSN_WRITE_FPR_S
)
1993 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1998 /* Read-after-write dependencies on the control registers
1999 require a two-instruction gap. */
2000 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2001 && (pinfo2
& INSN_READ_COND_CODE
))
2004 /* We don't know exactly what INSN1 does. If INSN2 is
2005 also a coprocessor instruction, assume there must be
2006 a one instruction gap. */
2007 if (pinfo2
& INSN_COP
)
2012 /* Check for read-after-write dependencies on the coprocessor
2013 control registers in cases where INSN1 does not need a general
2014 coprocessor delay. This means that INSN1 is a floating point
2015 comparison instruction. */
2016 /* Itbl support may require additional care here. */
2017 else if (!cop_interlocks
2018 && (pinfo1
& INSN_WRITE_COND_CODE
)
2019 && (pinfo2
& INSN_READ_COND_CODE
))
2023 #undef INSN2_USES_REG
2028 /* Return the number of nops that would be needed to work around the
2029 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2030 the MAX_VR4130_NOPS instructions described by HISTORY. */
2033 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2034 const struct mips_cl_insn
*insn
)
2038 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2039 are not affected by the errata. */
2041 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2042 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2043 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2046 /* Search for the first MFLO or MFHI. */
2047 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2048 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2050 /* Extract the destination register. */
2051 if (mips_opts
.mips16
)
2052 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2054 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2056 /* No nops are needed if INSN reads that register. */
2057 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2060 /* ...or if any of the intervening instructions do. */
2061 for (j
= 0; j
< i
; j
++)
2062 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2065 return MAX_VR4130_NOPS
- i
;
2070 /* Return the number of nops that would be needed if instruction INSN
2071 immediately followed the MAX_NOPS instructions given by HISTORY,
2072 where HISTORY[0] is the most recent instruction. If INSN is null,
2073 return the worse-case number of nops for any instruction. */
2076 nops_for_insn (const struct mips_cl_insn
*history
,
2077 const struct mips_cl_insn
*insn
)
2079 int i
, nops
, tmp_nops
;
2082 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2083 if (!history
[i
].noreorder_p
)
2085 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2086 if (tmp_nops
> nops
)
2090 if (mips_fix_vr4130
)
2092 tmp_nops
= nops_for_vr4130 (history
, insn
);
2093 if (tmp_nops
> nops
)
2100 /* The variable arguments provide NUM_INSNS extra instructions that
2101 might be added to HISTORY. Return the largest number of nops that
2102 would be needed after the extended sequence. */
2105 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2108 struct mips_cl_insn buffer
[MAX_NOPS
];
2109 struct mips_cl_insn
*cursor
;
2112 va_start (args
, history
);
2113 cursor
= buffer
+ num_insns
;
2114 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2115 while (cursor
> buffer
)
2116 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2118 nops
= nops_for_insn (buffer
, NULL
);
2123 /* Like nops_for_insn, but if INSN is a branch, take into account the
2124 worst-case delay for the branch target. */
2127 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2128 const struct mips_cl_insn
*insn
)
2132 nops
= nops_for_insn (history
, insn
);
2133 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2134 | INSN_COND_BRANCH_DELAY
2135 | INSN_COND_BRANCH_LIKELY
))
2137 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2138 if (tmp_nops
> nops
)
2141 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2143 tmp_nops
= nops_for_sequence (1, history
, insn
);
2144 if (tmp_nops
> nops
)
2150 /* Output an instruction. IP is the instruction information.
2151 ADDRESS_EXPR is an operand of the instruction to be used with
2155 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2156 bfd_reloc_code_real_type
*reloc_type
)
2158 register unsigned long prev_pinfo
, pinfo
;
2159 relax_stateT prev_insn_frag_type
= 0;
2160 bfd_boolean relaxed_branch
= FALSE
;
2162 /* Mark instruction labels in mips16 mode. */
2163 mips16_mark_labels ();
2165 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2166 pinfo
= ip
->insn_mo
->pinfo
;
2168 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2170 /* There are a lot of optimizations we could do that we don't.
2171 In particular, we do not, in general, reorder instructions.
2172 If you use gcc with optimization, it will reorder
2173 instructions and generally do much more optimization then we
2174 do here; repeating all that work in the assembler would only
2175 benefit hand written assembly code, and does not seem worth
2177 int nops
= (mips_optimize
== 0
2178 ? nops_for_insn (history
, NULL
)
2179 : nops_for_insn_or_target (history
, ip
));
2183 unsigned long old_frag_offset
;
2186 old_frag
= frag_now
;
2187 old_frag_offset
= frag_now_fix ();
2189 for (i
= 0; i
< nops
; i
++)
2194 listing_prev_line ();
2195 /* We may be at the start of a variant frag. In case we
2196 are, make sure there is enough space for the frag
2197 after the frags created by listing_prev_line. The
2198 argument to frag_grow here must be at least as large
2199 as the argument to all other calls to frag_grow in
2200 this file. We don't have to worry about being in the
2201 middle of a variant frag, because the variants insert
2202 all needed nop instructions themselves. */
2206 mips_move_labels ();
2208 #ifndef NO_ECOFF_DEBUGGING
2209 if (ECOFF_DEBUGGING
)
2210 ecoff_fix_loc (old_frag
, old_frag_offset
);
2214 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2216 /* Work out how many nops in prev_nop_frag are needed by IP. */
2217 int nops
= nops_for_insn_or_target (history
, ip
);
2218 assert (nops
<= prev_nop_frag_holds
);
2220 /* Enforce NOPS as a minimum. */
2221 if (nops
> prev_nop_frag_required
)
2222 prev_nop_frag_required
= nops
;
2224 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2226 /* Settle for the current number of nops. Update the history
2227 accordingly (for the benefit of any future .set reorder code). */
2228 prev_nop_frag
= NULL
;
2229 insert_into_history (prev_nop_frag_since
,
2230 prev_nop_frag_holds
, NOP_INSN
);
2234 /* Allow this instruction to replace one of the nops that was
2235 tentatively added to prev_nop_frag. */
2236 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2237 prev_nop_frag_holds
--;
2238 prev_nop_frag_since
++;
2243 /* The value passed to dwarf2_emit_insn is the distance between
2244 the beginning of the current instruction and the address that
2245 should be recorded in the debug tables. For MIPS16 debug info
2246 we want to use ISA-encoded addresses, so we pass -1 for an
2247 address higher by one than the current. */
2248 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2251 /* Record the frag type before frag_var. */
2252 if (history
[0].frag
)
2253 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2256 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2257 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2258 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2259 && mips_relax_branch
2260 /* Don't try branch relaxation within .set nomacro, or within
2261 .set noat if we use $at for PIC computations. If it turns
2262 out that the branch was out-of-range, we'll get an error. */
2263 && !mips_opts
.warn_about_macros
2264 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2265 && !mips_opts
.mips16
)
2267 relaxed_branch
= TRUE
;
2268 add_relaxed_insn (ip
, (relaxed_branch_length
2270 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2271 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2274 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2275 pinfo
& INSN_COND_BRANCH_LIKELY
,
2276 pinfo
& INSN_WRITE_GPR_31
,
2278 address_expr
->X_add_symbol
,
2279 address_expr
->X_add_number
);
2280 *reloc_type
= BFD_RELOC_UNUSED
;
2282 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2284 /* We need to set up a variant frag. */
2285 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2286 add_relaxed_insn (ip
, 4, 0,
2288 (*reloc_type
- BFD_RELOC_UNUSED
,
2289 mips16_small
, mips16_ext
,
2290 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2291 history
[0].mips16_absolute_jump_p
),
2292 make_expr_symbol (address_expr
), 0);
2294 else if (mips_opts
.mips16
2296 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2298 /* Make sure there is enough room to swap this instruction with
2299 a following jump instruction. */
2301 add_fixed_insn (ip
);
2305 if (mips_opts
.mips16
2306 && mips_opts
.noreorder
2307 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2308 as_warn (_("extended instruction in delay slot"));
2310 if (mips_relax
.sequence
)
2312 /* If we've reached the end of this frag, turn it into a variant
2313 frag and record the information for the instructions we've
2315 if (frag_room () < 4)
2316 relax_close_frag ();
2317 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2320 if (mips_relax
.sequence
!= 2)
2321 mips_macro_warning
.sizes
[0] += 4;
2322 if (mips_relax
.sequence
!= 1)
2323 mips_macro_warning
.sizes
[1] += 4;
2325 if (mips_opts
.mips16
)
2328 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2330 add_fixed_insn (ip
);
2333 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2335 if (address_expr
->X_op
== O_constant
)
2339 switch (*reloc_type
)
2342 ip
->insn_opcode
|= address_expr
->X_add_number
;
2345 case BFD_RELOC_MIPS_HIGHEST
:
2346 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2347 ip
->insn_opcode
|= tmp
& 0xffff;
2350 case BFD_RELOC_MIPS_HIGHER
:
2351 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2352 ip
->insn_opcode
|= tmp
& 0xffff;
2355 case BFD_RELOC_HI16_S
:
2356 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2357 ip
->insn_opcode
|= tmp
& 0xffff;
2360 case BFD_RELOC_HI16
:
2361 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2364 case BFD_RELOC_UNUSED
:
2365 case BFD_RELOC_LO16
:
2366 case BFD_RELOC_MIPS_GOT_DISP
:
2367 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2370 case BFD_RELOC_MIPS_JMP
:
2371 if ((address_expr
->X_add_number
& 3) != 0)
2372 as_bad (_("jump to misaligned address (0x%lx)"),
2373 (unsigned long) address_expr
->X_add_number
);
2374 if (address_expr
->X_add_number
& ~0xfffffff)
2375 as_bad (_("jump address range overflow (0x%lx)"),
2376 (unsigned long) address_expr
->X_add_number
);
2377 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2380 case BFD_RELOC_MIPS16_JMP
:
2381 if ((address_expr
->X_add_number
& 3) != 0)
2382 as_bad (_("jump to misaligned address (0x%lx)"),
2383 (unsigned long) address_expr
->X_add_number
);
2384 if (address_expr
->X_add_number
& ~0xfffffff)
2385 as_bad (_("jump address range overflow (0x%lx)"),
2386 (unsigned long) address_expr
->X_add_number
);
2388 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2389 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2390 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2393 case BFD_RELOC_16_PCREL_S2
:
2400 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2403 reloc_howto_type
*howto
;
2406 /* In a compound relocation, it is the final (outermost)
2407 operator that determines the relocated field. */
2408 for (i
= 1; i
< 3; i
++)
2409 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2412 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2413 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2414 bfd_get_reloc_size (howto
),
2416 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2419 /* These relocations can have an addend that won't fit in
2420 4 octets for 64bit assembly. */
2422 && ! howto
->partial_inplace
2423 && (reloc_type
[0] == BFD_RELOC_16
2424 || reloc_type
[0] == BFD_RELOC_32
2425 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2426 || reloc_type
[0] == BFD_RELOC_HI16_S
2427 || reloc_type
[0] == BFD_RELOC_LO16
2428 || reloc_type
[0] == BFD_RELOC_GPREL16
2429 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2430 || reloc_type
[0] == BFD_RELOC_GPREL32
2431 || reloc_type
[0] == BFD_RELOC_64
2432 || reloc_type
[0] == BFD_RELOC_CTOR
2433 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2434 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2435 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2436 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2437 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2438 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2439 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2440 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2441 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2442 ip
->fixp
[0]->fx_no_overflow
= 1;
2444 if (mips_relax
.sequence
)
2446 if (mips_relax
.first_fixup
== 0)
2447 mips_relax
.first_fixup
= ip
->fixp
[0];
2449 else if (reloc_needs_lo_p (*reloc_type
))
2451 struct mips_hi_fixup
*hi_fixup
;
2453 /* Reuse the last entry if it already has a matching %lo. */
2454 hi_fixup
= mips_hi_fixup_list
;
2456 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2458 hi_fixup
= ((struct mips_hi_fixup
*)
2459 xmalloc (sizeof (struct mips_hi_fixup
)));
2460 hi_fixup
->next
= mips_hi_fixup_list
;
2461 mips_hi_fixup_list
= hi_fixup
;
2463 hi_fixup
->fixp
= ip
->fixp
[0];
2464 hi_fixup
->seg
= now_seg
;
2467 /* Add fixups for the second and third relocations, if given.
2468 Note that the ABI allows the second relocation to be
2469 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2470 moment we only use RSS_UNDEF, but we could add support
2471 for the others if it ever becomes necessary. */
2472 for (i
= 1; i
< 3; i
++)
2473 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2475 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2476 ip
->fixp
[0]->fx_size
, NULL
, 0,
2477 FALSE
, reloc_type
[i
]);
2479 /* Use fx_tcbit to mark compound relocs. */
2480 ip
->fixp
[0]->fx_tcbit
= 1;
2481 ip
->fixp
[i
]->fx_tcbit
= 1;
2487 /* Update the register mask information. */
2488 if (! mips_opts
.mips16
)
2490 if (pinfo
& INSN_WRITE_GPR_D
)
2491 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2492 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2493 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2494 if (pinfo
& INSN_READ_GPR_S
)
2495 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2496 if (pinfo
& INSN_WRITE_GPR_31
)
2497 mips_gprmask
|= 1 << RA
;
2498 if (pinfo
& INSN_WRITE_FPR_D
)
2499 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2500 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2501 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2502 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2503 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2504 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2505 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2506 if (pinfo
& INSN_COP
)
2508 /* We don't keep enough information to sort these cases out.
2509 The itbl support does keep this information however, although
2510 we currently don't support itbl fprmats as part of the cop
2511 instruction. May want to add this support in the future. */
2513 /* Never set the bit for $0, which is always zero. */
2514 mips_gprmask
&= ~1 << 0;
2518 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2519 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2520 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2521 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2522 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2523 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2524 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2525 mips_gprmask
|= 1 << TREG
;
2526 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2527 mips_gprmask
|= 1 << SP
;
2528 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2529 mips_gprmask
|= 1 << RA
;
2530 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2531 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2532 if (pinfo
& MIPS16_INSN_READ_Z
)
2533 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2534 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2535 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2538 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2540 /* Filling the branch delay slot is more complex. We try to
2541 switch the branch with the previous instruction, which we can
2542 do if the previous instruction does not set up a condition
2543 that the branch tests and if the branch is not itself the
2544 target of any branch. */
2545 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2546 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2548 if (mips_optimize
< 2
2549 /* If we have seen .set volatile or .set nomove, don't
2551 || mips_opts
.nomove
!= 0
2552 /* We can't swap if the previous instruction's position
2554 || history
[0].fixed_p
2555 /* If the previous previous insn was in a .set
2556 noreorder, we can't swap. Actually, the MIPS
2557 assembler will swap in this situation. However, gcc
2558 configured -with-gnu-as will generate code like
2564 in which we can not swap the bne and INSN. If gcc is
2565 not configured -with-gnu-as, it does not output the
2567 || history
[1].noreorder_p
2568 /* If the branch is itself the target of a branch, we
2569 can not swap. We cheat on this; all we check for is
2570 whether there is a label on this instruction. If
2571 there are any branches to anything other than a
2572 label, users must use .set noreorder. */
2573 || insn_labels
!= NULL
2574 /* If the previous instruction is in a variant frag
2575 other than this branch's one, we cannot do the swap.
2576 This does not apply to the mips16, which uses variant
2577 frags for different purposes. */
2578 || (! mips_opts
.mips16
2579 && prev_insn_frag_type
== rs_machine_dependent
)
2580 /* Check for conflicts between the branch and the instructions
2581 before the candidate delay slot. */
2582 || nops_for_insn (history
+ 1, ip
) > 0
2583 /* Check for conflicts between the swapped sequence and the
2584 target of the branch. */
2585 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2586 /* We do not swap with a trap instruction, since it
2587 complicates trap handlers to have the trap
2588 instruction be in a delay slot. */
2589 || (prev_pinfo
& INSN_TRAP
)
2590 /* If the branch reads a register that the previous
2591 instruction sets, we can not swap. */
2592 || (! mips_opts
.mips16
2593 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2594 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2596 || (! mips_opts
.mips16
2597 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2598 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2600 || (mips_opts
.mips16
2601 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2603 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2605 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2607 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2609 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2611 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2613 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2614 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2615 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2616 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2617 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2618 && insn_uses_reg (ip
,
2619 MIPS16OP_EXTRACT_REG32R
2620 (history
[0].insn_opcode
),
2622 /* If the branch writes a register that the previous
2623 instruction sets, we can not swap (we know that
2624 branches write only to RD or to $31). */
2625 || (! mips_opts
.mips16
2626 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2627 && (((pinfo
& INSN_WRITE_GPR_D
)
2628 && (EXTRACT_OPERAND (RT
, history
[0])
2629 == EXTRACT_OPERAND (RD
, *ip
)))
2630 || ((pinfo
& INSN_WRITE_GPR_31
)
2631 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2632 || (! mips_opts
.mips16
2633 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2634 && (((pinfo
& INSN_WRITE_GPR_D
)
2635 && (EXTRACT_OPERAND (RD
, history
[0])
2636 == EXTRACT_OPERAND (RD
, *ip
)))
2637 || ((pinfo
& INSN_WRITE_GPR_31
)
2638 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2639 || (mips_opts
.mips16
2640 && (pinfo
& MIPS16_INSN_WRITE_31
)
2641 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2642 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2643 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2645 /* If the branch writes a register that the previous
2646 instruction reads, we can not swap (we know that
2647 branches only write to RD or to $31). */
2648 || (! mips_opts
.mips16
2649 && (pinfo
& INSN_WRITE_GPR_D
)
2650 && insn_uses_reg (&history
[0],
2651 EXTRACT_OPERAND (RD
, *ip
),
2653 || (! mips_opts
.mips16
2654 && (pinfo
& INSN_WRITE_GPR_31
)
2655 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2656 || (mips_opts
.mips16
2657 && (pinfo
& MIPS16_INSN_WRITE_31
)
2658 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2659 /* If one instruction sets a condition code and the
2660 other one uses a condition code, we can not swap. */
2661 || ((pinfo
& INSN_READ_COND_CODE
)
2662 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2663 || ((pinfo
& INSN_WRITE_COND_CODE
)
2664 && (prev_pinfo
& INSN_READ_COND_CODE
))
2665 /* If the previous instruction uses the PC, we can not
2667 || (mips_opts
.mips16
2668 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2669 /* If the previous instruction had a fixup in mips16
2670 mode, we can not swap. This normally means that the
2671 previous instruction was a 4 byte branch anyhow. */
2672 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2673 /* If the previous instruction is a sync, sync.l, or
2674 sync.p, we can not swap. */
2675 || (prev_pinfo
& INSN_SYNC
))
2677 /* We could do even better for unconditional branches to
2678 portions of this object file; we could pick up the
2679 instruction at the destination, put it in the delay
2680 slot, and bump the destination address. */
2681 insert_into_history (0, 1, ip
);
2683 if (mips_relax
.sequence
)
2684 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2688 /* It looks like we can actually do the swap. */
2689 struct mips_cl_insn delay
= history
[0];
2690 if (mips_opts
.mips16
)
2692 know (delay
.frag
== ip
->frag
);
2693 move_insn (ip
, delay
.frag
, delay
.where
);
2694 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2696 else if (relaxed_branch
)
2698 /* Add the delay slot instruction to the end of the
2699 current frag and shrink the fixed part of the
2700 original frag. If the branch occupies the tail of
2701 the latter, move it backwards to cover the gap. */
2702 delay
.frag
->fr_fix
-= 4;
2703 if (delay
.frag
== ip
->frag
)
2704 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2705 add_fixed_insn (&delay
);
2709 move_insn (&delay
, ip
->frag
, ip
->where
);
2710 move_insn (ip
, history
[0].frag
, history
[0].where
);
2714 insert_into_history (0, 1, &delay
);
2717 /* If that was an unconditional branch, forget the previous
2718 insn information. */
2719 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2720 mips_no_prev_insn ();
2722 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2724 /* We don't yet optimize a branch likely. What we should do
2725 is look at the target, copy the instruction found there
2726 into the delay slot, and increment the branch to jump to
2727 the next instruction. */
2728 insert_into_history (0, 1, ip
);
2732 insert_into_history (0, 1, ip
);
2735 insert_into_history (0, 1, ip
);
2737 /* We just output an insn, so the next one doesn't have a label. */
2738 mips_clear_insn_labels ();
2741 /* Forget that there was any previous instruction or label. */
2744 mips_no_prev_insn (void)
2746 prev_nop_frag
= NULL
;
2747 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2748 mips_clear_insn_labels ();
2751 /* This function must be called before we emit something other than
2752 instructions. It is like mips_no_prev_insn except that it inserts
2753 any NOPS that might be needed by previous instructions. */
2756 mips_emit_delays (void)
2758 if (! mips_opts
.noreorder
)
2760 int nops
= nops_for_insn (history
, NULL
);
2764 add_fixed_insn (NOP_INSN
);
2765 mips_move_labels ();
2768 mips_no_prev_insn ();
2771 /* Start a (possibly nested) noreorder block. */
2774 start_noreorder (void)
2776 if (mips_opts
.noreorder
== 0)
2781 /* None of the instructions before the .set noreorder can be moved. */
2782 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2783 history
[i
].fixed_p
= 1;
2785 /* Insert any nops that might be needed between the .set noreorder
2786 block and the previous instructions. We will later remove any
2787 nops that turn out not to be needed. */
2788 nops
= nops_for_insn (history
, NULL
);
2791 if (mips_optimize
!= 0)
2793 /* Record the frag which holds the nop instructions, so
2794 that we can remove them if we don't need them. */
2795 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2796 prev_nop_frag
= frag_now
;
2797 prev_nop_frag_holds
= nops
;
2798 prev_nop_frag_required
= 0;
2799 prev_nop_frag_since
= 0;
2802 for (; nops
> 0; --nops
)
2803 add_fixed_insn (NOP_INSN
);
2805 /* Move on to a new frag, so that it is safe to simply
2806 decrease the size of prev_nop_frag. */
2807 frag_wane (frag_now
);
2809 mips_move_labels ();
2811 mips16_mark_labels ();
2812 mips_clear_insn_labels ();
2814 mips_opts
.noreorder
++;
2815 mips_any_noreorder
= 1;
2818 /* End a nested noreorder block. */
2821 end_noreorder (void)
2823 mips_opts
.noreorder
--;
2824 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2826 /* Commit to inserting prev_nop_frag_required nops and go back to
2827 handling nop insertion the .set reorder way. */
2828 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2829 * (mips_opts
.mips16
? 2 : 4));
2830 insert_into_history (prev_nop_frag_since
,
2831 prev_nop_frag_required
, NOP_INSN
);
2832 prev_nop_frag
= NULL
;
2836 /* Set up global variables for the start of a new macro. */
2841 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2842 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2843 && (history
[0].insn_mo
->pinfo
2844 & (INSN_UNCOND_BRANCH_DELAY
2845 | INSN_COND_BRANCH_DELAY
2846 | INSN_COND_BRANCH_LIKELY
)) != 0);
2849 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2850 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2851 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2854 macro_warning (relax_substateT subtype
)
2856 if (subtype
& RELAX_DELAY_SLOT
)
2857 return _("Macro instruction expanded into multiple instructions"
2858 " in a branch delay slot");
2859 else if (subtype
& RELAX_NOMACRO
)
2860 return _("Macro instruction expanded into multiple instructions");
2865 /* Finish up a macro. Emit warnings as appropriate. */
2870 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2872 relax_substateT subtype
;
2874 /* Set up the relaxation warning flags. */
2876 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2877 subtype
|= RELAX_SECOND_LONGER
;
2878 if (mips_opts
.warn_about_macros
)
2879 subtype
|= RELAX_NOMACRO
;
2880 if (mips_macro_warning
.delay_slot_p
)
2881 subtype
|= RELAX_DELAY_SLOT
;
2883 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2885 /* Either the macro has a single implementation or both
2886 implementations are longer than 4 bytes. Emit the
2888 const char *msg
= macro_warning (subtype
);
2894 /* One implementation might need a warning but the other
2895 definitely doesn't. */
2896 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2901 /* Read a macro's relocation codes from *ARGS and store them in *R.
2902 The first argument in *ARGS will be either the code for a single
2903 relocation or -1 followed by the three codes that make up a
2904 composite relocation. */
2907 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2911 next
= va_arg (*args
, int);
2913 r
[0] = (bfd_reloc_code_real_type
) next
;
2915 for (i
= 0; i
< 3; i
++)
2916 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2919 /* Build an instruction created by a macro expansion. This is passed
2920 a pointer to the count of instructions created so far, an
2921 expression, the name of the instruction to build, an operand format
2922 string, and corresponding arguments. */
2925 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2927 const struct mips_opcode
*mo
;
2928 struct mips_cl_insn insn
;
2929 bfd_reloc_code_real_type r
[3];
2932 va_start (args
, fmt
);
2934 if (mips_opts
.mips16
)
2936 mips16_macro_build (ep
, name
, fmt
, args
);
2941 r
[0] = BFD_RELOC_UNUSED
;
2942 r
[1] = BFD_RELOC_UNUSED
;
2943 r
[2] = BFD_RELOC_UNUSED
;
2944 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2946 assert (strcmp (name
, mo
->name
) == 0);
2948 /* Search until we get a match for NAME. It is assumed here that
2949 macros will never generate MDMX or MIPS-3D instructions. */
2950 while (strcmp (fmt
, mo
->args
) != 0
2951 || mo
->pinfo
== INSN_MACRO
2952 || !OPCODE_IS_MEMBER (mo
,
2954 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2956 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2960 assert (strcmp (name
, mo
->name
) == 0);
2963 create_insn (&insn
, mo
);
2981 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2986 /* Note that in the macro case, these arguments are already
2987 in MSB form. (When handling the instruction in the
2988 non-macro case, these arguments are sizes from which
2989 MSB values must be calculated.) */
2990 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2996 /* Note that in the macro case, these arguments are already
2997 in MSBD form. (When handling the instruction in the
2998 non-macro case, these arguments are sizes from which
2999 MSBD values must be calculated.) */
3000 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3011 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3015 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3020 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3026 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3031 int tmp
= va_arg (args
, int);
3033 INSERT_OPERAND (RT
, insn
, tmp
);
3034 INSERT_OPERAND (RD
, insn
, tmp
);
3040 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3047 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3051 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3055 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3059 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3063 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3070 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3076 macro_read_relocs (&args
, r
);
3077 assert (*r
== BFD_RELOC_GPREL16
3078 || *r
== BFD_RELOC_MIPS_LITERAL
3079 || *r
== BFD_RELOC_MIPS_HIGHER
3080 || *r
== BFD_RELOC_HI16_S
3081 || *r
== BFD_RELOC_LO16
3082 || *r
== BFD_RELOC_MIPS_GOT16
3083 || *r
== BFD_RELOC_MIPS_CALL16
3084 || *r
== BFD_RELOC_MIPS_GOT_DISP
3085 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3086 || *r
== BFD_RELOC_MIPS_GOT_OFST
3087 || *r
== BFD_RELOC_MIPS_GOT_LO16
3088 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3092 macro_read_relocs (&args
, r
);
3094 && (ep
->X_op
== O_constant
3095 || (ep
->X_op
== O_symbol
3096 && (*r
== BFD_RELOC_MIPS_HIGHEST
3097 || *r
== BFD_RELOC_HI16_S
3098 || *r
== BFD_RELOC_HI16
3099 || *r
== BFD_RELOC_GPREL16
3100 || *r
== BFD_RELOC_MIPS_GOT_HI16
3101 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3105 assert (ep
!= NULL
);
3107 * This allows macro() to pass an immediate expression for
3108 * creating short branches without creating a symbol.
3109 * Note that the expression still might come from the assembly
3110 * input, in which case the value is not checked for range nor
3111 * is a relocation entry generated (yuck).
3113 if (ep
->X_op
== O_constant
)
3115 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3119 *r
= BFD_RELOC_16_PCREL_S2
;
3123 assert (ep
!= NULL
);
3124 *r
= BFD_RELOC_MIPS_JMP
;
3128 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3137 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3139 append_insn (&insn
, ep
, r
);
3143 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3146 struct mips_opcode
*mo
;
3147 struct mips_cl_insn insn
;
3148 bfd_reloc_code_real_type r
[3]
3149 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3151 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3153 assert (strcmp (name
, mo
->name
) == 0);
3155 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3159 assert (strcmp (name
, mo
->name
) == 0);
3162 create_insn (&insn
, mo
);
3180 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3185 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3189 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3193 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3203 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3210 regno
= va_arg (args
, int);
3211 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3212 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3233 assert (ep
!= NULL
);
3235 if (ep
->X_op
!= O_constant
)
3236 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3239 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3240 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3243 *r
= BFD_RELOC_UNUSED
;
3249 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3256 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3258 append_insn (&insn
, ep
, r
);
3263 * Sign-extend 32-bit mode constants that have bit 31 set and all
3264 * higher bits unset.
3266 normalize_constant_expr (expressionS
*ex
)
3268 if ((ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3269 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3270 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3275 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3276 * all higher bits unset.
3279 normalize_address_expr (expressionS
*ex
)
3281 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3282 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3283 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3284 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3289 * Generate a "jalr" instruction with a relocation hint to the called
3290 * function. This occurs in NewABI PIC code.
3293 macro_build_jalr (expressionS
*ep
)
3302 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3304 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3305 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3309 * Generate a "lui" instruction.
3312 macro_build_lui (expressionS
*ep
, int regnum
)
3314 expressionS high_expr
;
3315 const struct mips_opcode
*mo
;
3316 struct mips_cl_insn insn
;
3317 bfd_reloc_code_real_type r
[3]
3318 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3319 const char *name
= "lui";
3320 const char *fmt
= "t,u";
3322 assert (! mips_opts
.mips16
);
3326 if (high_expr
.X_op
== O_constant
)
3328 /* we can compute the instruction now without a relocation entry */
3329 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3331 *r
= BFD_RELOC_UNUSED
;
3335 assert (ep
->X_op
== O_symbol
);
3336 /* _gp_disp is a special case, used from s_cpload.
3337 __gnu_local_gp is used if mips_no_shared. */
3338 assert (mips_pic
== NO_PIC
3340 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3341 || (! mips_in_shared
3342 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3343 "__gnu_local_gp") == 0));
3344 *r
= BFD_RELOC_HI16_S
;
3347 mo
= hash_find (op_hash
, name
);
3348 assert (strcmp (name
, mo
->name
) == 0);
3349 assert (strcmp (fmt
, mo
->args
) == 0);
3350 create_insn (&insn
, mo
);
3352 insn
.insn_opcode
= insn
.insn_mo
->match
;
3353 INSERT_OPERAND (RT
, insn
, regnum
);
3354 if (*r
== BFD_RELOC_UNUSED
)
3356 insn
.insn_opcode
|= high_expr
.X_add_number
;
3357 append_insn (&insn
, NULL
, r
);
3360 append_insn (&insn
, &high_expr
, r
);
3363 /* Generate a sequence of instructions to do a load or store from a constant
3364 offset off of a base register (breg) into/from a target register (treg),
3365 using AT if necessary. */
3367 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3368 int treg
, int breg
, int dbl
)
3370 assert (ep
->X_op
== O_constant
);
3372 /* Sign-extending 32-bit constants makes their handling easier. */
3374 normalize_constant_expr (ep
);
3376 /* Right now, this routine can only handle signed 32-bit constants. */
3377 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3378 as_warn (_("operand overflow"));
3380 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3382 /* Signed 16-bit offset will fit in the op. Easy! */
3383 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3387 /* 32-bit offset, need multiple instructions and AT, like:
3388 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3389 addu $tempreg,$tempreg,$breg
3390 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3391 to handle the complete offset. */
3392 macro_build_lui (ep
, AT
);
3393 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3394 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3397 as_bad (_("Macro used $at after \".set noat\""));
3402 * Generates code to set the $at register to true (one)
3403 * if reg is less than the immediate expression.
3406 set_at (int reg
, int unsignedp
)
3408 if (imm_expr
.X_op
== O_constant
3409 && imm_expr
.X_add_number
>= -0x8000
3410 && imm_expr
.X_add_number
< 0x8000)
3411 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3412 AT
, reg
, BFD_RELOC_LO16
);
3415 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3416 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3420 /* Warn if an expression is not a constant. */
3423 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3425 if (ex
->X_op
== O_big
)
3426 as_bad (_("unsupported large constant"));
3427 else if (ex
->X_op
!= O_constant
)
3428 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3430 normalize_constant_expr (ex
);
3433 /* Count the leading zeroes by performing a binary chop. This is a
3434 bulky bit of source, but performance is a LOT better for the
3435 majority of values than a simple loop to count the bits:
3436 for (lcnt = 0; (lcnt < 32); lcnt++)
3437 if ((v) & (1 << (31 - lcnt)))
3439 However it is not code size friendly, and the gain will drop a bit
3440 on certain cached systems.
3442 #define COUNT_TOP_ZEROES(v) \
3443 (((v) & ~0xffff) == 0 \
3444 ? ((v) & ~0xff) == 0 \
3445 ? ((v) & ~0xf) == 0 \
3446 ? ((v) & ~0x3) == 0 \
3447 ? ((v) & ~0x1) == 0 \
3452 : ((v) & ~0x7) == 0 \
3455 : ((v) & ~0x3f) == 0 \
3456 ? ((v) & ~0x1f) == 0 \
3459 : ((v) & ~0x7f) == 0 \
3462 : ((v) & ~0xfff) == 0 \
3463 ? ((v) & ~0x3ff) == 0 \
3464 ? ((v) & ~0x1ff) == 0 \
3467 : ((v) & ~0x7ff) == 0 \
3470 : ((v) & ~0x3fff) == 0 \
3471 ? ((v) & ~0x1fff) == 0 \
3474 : ((v) & ~0x7fff) == 0 \
3477 : ((v) & ~0xffffff) == 0 \
3478 ? ((v) & ~0xfffff) == 0 \
3479 ? ((v) & ~0x3ffff) == 0 \
3480 ? ((v) & ~0x1ffff) == 0 \
3483 : ((v) & ~0x7ffff) == 0 \
3486 : ((v) & ~0x3fffff) == 0 \
3487 ? ((v) & ~0x1fffff) == 0 \
3490 : ((v) & ~0x7fffff) == 0 \
3493 : ((v) & ~0xfffffff) == 0 \
3494 ? ((v) & ~0x3ffffff) == 0 \
3495 ? ((v) & ~0x1ffffff) == 0 \
3498 : ((v) & ~0x7ffffff) == 0 \
3501 : ((v) & ~0x3fffffff) == 0 \
3502 ? ((v) & ~0x1fffffff) == 0 \
3505 : ((v) & ~0x7fffffff) == 0 \
3510 * This routine generates the least number of instructions necessary to load
3511 * an absolute expression value into a register.
3514 load_register (int reg
, expressionS
*ep
, int dbl
)
3517 expressionS hi32
, lo32
;
3519 if (ep
->X_op
!= O_big
)
3521 assert (ep
->X_op
== O_constant
);
3523 /* Sign-extending 32-bit constants makes their handling easier. */
3525 normalize_constant_expr (ep
);
3527 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3529 /* We can handle 16 bit signed values with an addiu to
3530 $zero. No need to ever use daddiu here, since $zero and
3531 the result are always correct in 32 bit mode. */
3532 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3535 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3537 /* We can handle 16 bit unsigned values with an ori to
3539 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3542 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3544 /* 32 bit values require an lui. */
3545 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3546 if ((ep
->X_add_number
& 0xffff) != 0)
3547 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3552 /* The value is larger than 32 bits. */
3554 if (!dbl
|| HAVE_32BIT_GPRS
)
3556 as_bad (_("Number (0x%lx%08lx) larger than 32 bits"),
3557 (unsigned long) (ep
->X_add_number
>> 32),
3558 (unsigned long) (ep
->X_add_number
& 0xffffffff));
3559 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3563 if (ep
->X_op
!= O_big
)
3566 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3567 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3568 hi32
.X_add_number
&= 0xffffffff;
3570 lo32
.X_add_number
&= 0xffffffff;
3574 assert (ep
->X_add_number
> 2);
3575 if (ep
->X_add_number
== 3)
3576 generic_bignum
[3] = 0;
3577 else if (ep
->X_add_number
> 4)
3578 as_bad (_("Number larger than 64 bits"));
3579 lo32
.X_op
= O_constant
;
3580 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3581 hi32
.X_op
= O_constant
;
3582 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3585 if (hi32
.X_add_number
== 0)
3590 unsigned long hi
, lo
;
3592 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3594 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3596 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3599 if (lo32
.X_add_number
& 0x80000000)
3601 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3602 if (lo32
.X_add_number
& 0xffff)
3603 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3608 /* Check for 16bit shifted constant. We know that hi32 is
3609 non-zero, so start the mask on the first bit of the hi32
3614 unsigned long himask
, lomask
;
3618 himask
= 0xffff >> (32 - shift
);
3619 lomask
= (0xffff << shift
) & 0xffffffff;
3623 himask
= 0xffff << (shift
- 32);
3626 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3627 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3631 tmp
.X_op
= O_constant
;
3633 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3634 | (lo32
.X_add_number
>> shift
));
3636 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3637 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3638 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3639 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3644 while (shift
<= (64 - 16));
3646 /* Find the bit number of the lowest one bit, and store the
3647 shifted value in hi/lo. */
3648 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3649 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3653 while ((lo
& 1) == 0)
3658 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3664 while ((hi
& 1) == 0)
3673 /* Optimize if the shifted value is a (power of 2) - 1. */
3674 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3675 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3677 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3682 /* This instruction will set the register to be all
3684 tmp
.X_op
= O_constant
;
3685 tmp
.X_add_number
= (offsetT
) -1;
3686 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3690 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3691 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3693 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3694 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3699 /* Sign extend hi32 before calling load_register, because we can
3700 generally get better code when we load a sign extended value. */
3701 if ((hi32
.X_add_number
& 0x80000000) != 0)
3702 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3703 load_register (reg
, &hi32
, 0);
3706 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3710 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3718 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3720 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3721 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3727 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3731 mid16
.X_add_number
>>= 16;
3732 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3733 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3736 if ((lo32
.X_add_number
& 0xffff) != 0)
3737 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3741 load_delay_nop (void)
3743 if (!gpr_interlocks
)
3744 macro_build (NULL
, "nop", "");
3747 /* Load an address into a register. */
3750 load_address (int reg
, expressionS
*ep
, int *used_at
)
3752 if (ep
->X_op
!= O_constant
3753 && ep
->X_op
!= O_symbol
)
3755 as_bad (_("expression too complex"));
3756 ep
->X_op
= O_constant
;
3759 if (ep
->X_op
== O_constant
)
3761 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3765 if (mips_pic
== NO_PIC
)
3767 /* If this is a reference to a GP relative symbol, we want
3768 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3770 lui $reg,<sym> (BFD_RELOC_HI16_S)
3771 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3772 If we have an addend, we always use the latter form.
3774 With 64bit address space and a usable $at we want
3775 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3776 lui $at,<sym> (BFD_RELOC_HI16_S)
3777 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3778 daddiu $at,<sym> (BFD_RELOC_LO16)
3782 If $at is already in use, we use a path which is suboptimal
3783 on superscalar processors.
3784 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3785 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3787 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3789 daddiu $reg,<sym> (BFD_RELOC_LO16)
3791 For GP relative symbols in 64bit address space we can use
3792 the same sequence as in 32bit address space. */
3793 if (HAVE_64BIT_SYMBOLS
)
3795 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3796 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3798 relax_start (ep
->X_add_symbol
);
3799 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3800 mips_gp_register
, BFD_RELOC_GPREL16
);
3804 if (*used_at
== 0 && !mips_opts
.noat
)
3806 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3807 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3808 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3809 BFD_RELOC_MIPS_HIGHER
);
3810 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3811 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3812 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3817 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3818 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3819 BFD_RELOC_MIPS_HIGHER
);
3820 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3821 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3822 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3823 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3826 if (mips_relax
.sequence
)
3831 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3832 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3834 relax_start (ep
->X_add_symbol
);
3835 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3836 mips_gp_register
, BFD_RELOC_GPREL16
);
3839 macro_build_lui (ep
, reg
);
3840 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3841 reg
, reg
, BFD_RELOC_LO16
);
3842 if (mips_relax
.sequence
)
3846 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3850 /* If this is a reference to an external symbol, we want
3851 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3853 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3855 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3856 If there is a constant, it must be added in after.
3858 If we have NewABI, we want
3859 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3860 unless we're referencing a global symbol with a non-zero
3861 offset, in which case cst must be added separately. */
3864 if (ep
->X_add_number
)
3866 ex
.X_add_number
= ep
->X_add_number
;
3867 ep
->X_add_number
= 0;
3868 relax_start (ep
->X_add_symbol
);
3869 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3870 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3871 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3872 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3873 ex
.X_op
= O_constant
;
3874 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3875 reg
, reg
, BFD_RELOC_LO16
);
3876 ep
->X_add_number
= ex
.X_add_number
;
3879 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3880 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3881 if (mips_relax
.sequence
)
3886 ex
.X_add_number
= ep
->X_add_number
;
3887 ep
->X_add_number
= 0;
3888 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3889 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3891 relax_start (ep
->X_add_symbol
);
3893 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3897 if (ex
.X_add_number
!= 0)
3899 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3900 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3901 ex
.X_op
= O_constant
;
3902 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3903 reg
, reg
, BFD_RELOC_LO16
);
3907 else if (mips_pic
== SVR4_PIC
)
3911 /* This is the large GOT case. If this is a reference to an
3912 external symbol, we want
3913 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3915 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3917 Otherwise, for a reference to a local symbol in old ABI, we want
3918 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3920 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3921 If there is a constant, it must be added in after.
3923 In the NewABI, for local symbols, with or without offsets, we want:
3924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3925 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3929 ex
.X_add_number
= ep
->X_add_number
;
3930 ep
->X_add_number
= 0;
3931 relax_start (ep
->X_add_symbol
);
3932 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3933 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3934 reg
, reg
, mips_gp_register
);
3935 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3936 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3937 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3939 else if (ex
.X_add_number
)
3941 ex
.X_op
= O_constant
;
3942 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3946 ep
->X_add_number
= ex
.X_add_number
;
3948 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3949 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3950 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3951 BFD_RELOC_MIPS_GOT_OFST
);
3956 ex
.X_add_number
= ep
->X_add_number
;
3957 ep
->X_add_number
= 0;
3958 relax_start (ep
->X_add_symbol
);
3959 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3960 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3961 reg
, reg
, mips_gp_register
);
3962 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3963 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3965 if (reg_needs_delay (mips_gp_register
))
3967 /* We need a nop before loading from $gp. This special
3968 check is required because the lui which starts the main
3969 instruction stream does not refer to $gp, and so will not
3970 insert the nop which may be required. */
3971 macro_build (NULL
, "nop", "");
3973 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3974 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3976 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3980 if (ex
.X_add_number
!= 0)
3982 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3983 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3984 ex
.X_op
= O_constant
;
3985 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3993 if (mips_opts
.noat
&& *used_at
== 1)
3994 as_bad (_("Macro used $at after \".set noat\""));
3997 /* Move the contents of register SOURCE into register DEST. */
4000 move_register (int dest
, int source
)
4002 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4006 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4007 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4008 The two alternatives are:
4010 Global symbol Local sybmol
4011 ------------- ------------
4012 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4014 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4016 load_got_offset emits the first instruction and add_got_offset
4017 emits the second for a 16-bit offset or add_got_offset_hilo emits
4018 a sequence to add a 32-bit offset using a scratch register. */
4021 load_got_offset (int dest
, expressionS
*local
)
4026 global
.X_add_number
= 0;
4028 relax_start (local
->X_add_symbol
);
4029 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4030 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4032 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4033 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4038 add_got_offset (int dest
, expressionS
*local
)
4042 global
.X_op
= O_constant
;
4043 global
.X_op_symbol
= NULL
;
4044 global
.X_add_symbol
= NULL
;
4045 global
.X_add_number
= local
->X_add_number
;
4047 relax_start (local
->X_add_symbol
);
4048 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4049 dest
, dest
, BFD_RELOC_LO16
);
4051 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4056 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4059 int hold_mips_optimize
;
4061 global
.X_op
= O_constant
;
4062 global
.X_op_symbol
= NULL
;
4063 global
.X_add_symbol
= NULL
;
4064 global
.X_add_number
= local
->X_add_number
;
4066 relax_start (local
->X_add_symbol
);
4067 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4069 /* Set mips_optimize around the lui instruction to avoid
4070 inserting an unnecessary nop after the lw. */
4071 hold_mips_optimize
= mips_optimize
;
4073 macro_build_lui (&global
, tmp
);
4074 mips_optimize
= hold_mips_optimize
;
4075 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4078 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4083 * This routine implements the seemingly endless macro or synthesized
4084 * instructions and addressing modes in the mips assembly language. Many
4085 * of these macros are simple and are similar to each other. These could
4086 * probably be handled by some kind of table or grammar approach instead of
4087 * this verbose method. Others are not simple macros but are more like
4088 * optimizing code generation.
4089 * One interesting optimization is when several store macros appear
4090 * consecutively that would load AT with the upper half of the same address.
4091 * The ensuing load upper instructions are ommited. This implies some kind
4092 * of global optimization. We currently only optimize within a single macro.
4093 * For many of the load and store macros if the address is specified as a
4094 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4095 * first load register 'at' with zero and use it as the base register. The
4096 * mips assembler simply uses register $zero. Just one tiny optimization
4100 macro (struct mips_cl_insn
*ip
)
4102 register int treg
, sreg
, dreg
, breg
;
4118 bfd_reloc_code_real_type r
;
4119 int hold_mips_optimize
;
4121 assert (! mips_opts
.mips16
);
4123 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4124 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4125 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4126 mask
= ip
->insn_mo
->mask
;
4128 expr1
.X_op
= O_constant
;
4129 expr1
.X_op_symbol
= NULL
;
4130 expr1
.X_add_symbol
= NULL
;
4131 expr1
.X_add_number
= 1;
4145 expr1
.X_add_number
= 8;
4146 macro_build (&expr1
, "bgez", "s,p", sreg
);
4148 macro_build (NULL
, "nop", "", 0);
4150 move_register (dreg
, sreg
);
4151 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4174 if (imm_expr
.X_op
== O_constant
4175 && imm_expr
.X_add_number
>= -0x8000
4176 && imm_expr
.X_add_number
< 0x8000)
4178 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4182 load_register (AT
, &imm_expr
, dbl
);
4183 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4202 if (imm_expr
.X_op
== O_constant
4203 && imm_expr
.X_add_number
>= 0
4204 && imm_expr
.X_add_number
< 0x10000)
4206 if (mask
!= M_NOR_I
)
4207 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4210 macro_build (&imm_expr
, "ori", "t,r,i",
4211 treg
, sreg
, BFD_RELOC_LO16
);
4212 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4218 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4219 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4236 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4238 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4242 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4243 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4251 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4256 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4260 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4261 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4267 /* check for > max integer */
4268 maxnum
= 0x7fffffff;
4269 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4276 if (imm_expr
.X_op
== O_constant
4277 && imm_expr
.X_add_number
>= maxnum
4278 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4281 /* result is always false */
4283 macro_build (NULL
, "nop", "", 0);
4285 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4288 if (imm_expr
.X_op
!= O_constant
)
4289 as_bad (_("Unsupported large constant"));
4290 ++imm_expr
.X_add_number
;
4294 if (mask
== M_BGEL_I
)
4296 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4298 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4301 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4303 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4306 maxnum
= 0x7fffffff;
4307 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4314 maxnum
= - maxnum
- 1;
4315 if (imm_expr
.X_op
== O_constant
4316 && imm_expr
.X_add_number
<= maxnum
4317 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4320 /* result is always true */
4321 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4322 macro_build (&offset_expr
, "b", "p");
4327 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4337 macro_build (&offset_expr
, likely
? "beql" : "beq",
4342 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4343 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4351 && imm_expr
.X_op
== O_constant
4352 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4354 if (imm_expr
.X_op
!= O_constant
)
4355 as_bad (_("Unsupported large constant"));
4356 ++imm_expr
.X_add_number
;
4360 if (mask
== M_BGEUL_I
)
4362 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4364 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4366 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4372 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4380 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4385 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4389 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4390 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4398 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4405 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4406 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4414 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4419 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4423 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4424 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4430 maxnum
= 0x7fffffff;
4431 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4438 if (imm_expr
.X_op
== O_constant
4439 && imm_expr
.X_add_number
>= maxnum
4440 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4442 if (imm_expr
.X_op
!= O_constant
)
4443 as_bad (_("Unsupported large constant"));
4444 ++imm_expr
.X_add_number
;
4448 if (mask
== M_BLTL_I
)
4450 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4452 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4455 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4457 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4462 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4470 macro_build (&offset_expr
, likely
? "beql" : "beq",
4477 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4478 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4486 && imm_expr
.X_op
== O_constant
4487 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4489 if (imm_expr
.X_op
!= O_constant
)
4490 as_bad (_("Unsupported large constant"));
4491 ++imm_expr
.X_add_number
;
4495 if (mask
== M_BLTUL_I
)
4497 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4499 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4501 macro_build (&offset_expr
, likely
? "beql" : "beq",
4507 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4515 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4520 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4524 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4525 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4535 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4540 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4541 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4549 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4551 as_bad (_("Unsupported large constant"));
4556 pos
= (unsigned long) imm_expr
.X_add_number
;
4557 size
= (unsigned long) imm2_expr
.X_add_number
;
4562 as_bad (_("Improper position (%lu)"), pos
);
4565 if (size
== 0 || size
> 64
4566 || (pos
+ size
- 1) > 63)
4568 as_bad (_("Improper extract size (%lu, position %lu)"),
4573 if (size
<= 32 && pos
< 32)
4578 else if (size
<= 32)
4588 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4597 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4599 as_bad (_("Unsupported large constant"));
4604 pos
= (unsigned long) imm_expr
.X_add_number
;
4605 size
= (unsigned long) imm2_expr
.X_add_number
;
4610 as_bad (_("Improper position (%lu)"), pos
);
4613 if (size
== 0 || size
> 64
4614 || (pos
+ size
- 1) > 63)
4616 as_bad (_("Improper insert size (%lu, position %lu)"),
4621 if (pos
< 32 && (pos
+ size
- 1) < 32)
4636 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4653 as_warn (_("Divide by zero."));
4655 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4657 macro_build (NULL
, "break", "c", 7);
4664 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4665 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4669 expr1
.X_add_number
= 8;
4670 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4671 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4672 macro_build (NULL
, "break", "c", 7);
4674 expr1
.X_add_number
= -1;
4676 load_register (AT
, &expr1
, dbl
);
4677 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4678 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4681 expr1
.X_add_number
= 1;
4682 load_register (AT
, &expr1
, dbl
);
4683 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4687 expr1
.X_add_number
= 0x80000000;
4688 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4692 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4693 /* We want to close the noreorder block as soon as possible, so
4694 that later insns are available for delay slot filling. */
4699 expr1
.X_add_number
= 8;
4700 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4701 macro_build (NULL
, "nop", "", 0);
4703 /* We want to close the noreorder block as soon as possible, so
4704 that later insns are available for delay slot filling. */
4707 macro_build (NULL
, "break", "c", 6);
4709 macro_build (NULL
, s
, "d", dreg
);
4748 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4750 as_warn (_("Divide by zero."));
4752 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4754 macro_build (NULL
, "break", "c", 7);
4757 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4759 if (strcmp (s2
, "mflo") == 0)
4760 move_register (dreg
, sreg
);
4762 move_register (dreg
, 0);
4765 if (imm_expr
.X_op
== O_constant
4766 && imm_expr
.X_add_number
== -1
4767 && s
[strlen (s
) - 1] != 'u')
4769 if (strcmp (s2
, "mflo") == 0)
4771 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4774 move_register (dreg
, 0);
4779 load_register (AT
, &imm_expr
, dbl
);
4780 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4781 macro_build (NULL
, s2
, "d", dreg
);
4803 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4804 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4805 /* We want to close the noreorder block as soon as possible, so
4806 that later insns are available for delay slot filling. */
4811 expr1
.X_add_number
= 8;
4812 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4813 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4815 /* We want to close the noreorder block as soon as possible, so
4816 that later insns are available for delay slot filling. */
4818 macro_build (NULL
, "break", "c", 7);
4820 macro_build (NULL
, s2
, "d", dreg
);
4832 /* Load the address of a symbol into a register. If breg is not
4833 zero, we then add a base register to it. */
4835 if (dbl
&& HAVE_32BIT_GPRS
)
4836 as_warn (_("dla used to load 32-bit register"));
4838 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4839 as_warn (_("la used to load 64-bit address"));
4841 if (offset_expr
.X_op
== O_constant
4842 && offset_expr
.X_add_number
>= -0x8000
4843 && offset_expr
.X_add_number
< 0x8000)
4845 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4846 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4850 if (!mips_opts
.noat
&& (treg
== breg
))
4860 if (offset_expr
.X_op
!= O_symbol
4861 && offset_expr
.X_op
!= O_constant
)
4863 as_bad (_("expression too complex"));
4864 offset_expr
.X_op
= O_constant
;
4867 if (offset_expr
.X_op
== O_constant
)
4868 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4869 else if (mips_pic
== NO_PIC
)
4871 /* If this is a reference to a GP relative symbol, we want
4872 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4874 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4875 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4876 If we have a constant, we need two instructions anyhow,
4877 so we may as well always use the latter form.
4879 With 64bit address space and a usable $at we want
4880 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4881 lui $at,<sym> (BFD_RELOC_HI16_S)
4882 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4883 daddiu $at,<sym> (BFD_RELOC_LO16)
4885 daddu $tempreg,$tempreg,$at
4887 If $at is already in use, we use a path which is suboptimal
4888 on superscalar processors.
4889 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4890 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4892 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4894 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4896 For GP relative symbols in 64bit address space we can use
4897 the same sequence as in 32bit address space. */
4898 if (HAVE_64BIT_SYMBOLS
)
4900 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4901 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4903 relax_start (offset_expr
.X_add_symbol
);
4904 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4905 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4909 if (used_at
== 0 && !mips_opts
.noat
)
4911 macro_build (&offset_expr
, "lui", "t,u",
4912 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4913 macro_build (&offset_expr
, "lui", "t,u",
4914 AT
, BFD_RELOC_HI16_S
);
4915 macro_build (&offset_expr
, "daddiu", "t,r,j",
4916 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4917 macro_build (&offset_expr
, "daddiu", "t,r,j",
4918 AT
, AT
, BFD_RELOC_LO16
);
4919 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4920 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4925 macro_build (&offset_expr
, "lui", "t,u",
4926 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4927 macro_build (&offset_expr
, "daddiu", "t,r,j",
4928 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4929 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4930 macro_build (&offset_expr
, "daddiu", "t,r,j",
4931 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4932 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4933 macro_build (&offset_expr
, "daddiu", "t,r,j",
4934 tempreg
, tempreg
, BFD_RELOC_LO16
);
4937 if (mips_relax
.sequence
)
4942 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4943 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4945 relax_start (offset_expr
.X_add_symbol
);
4946 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4947 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4950 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4951 as_bad (_("offset too large"));
4952 macro_build_lui (&offset_expr
, tempreg
);
4953 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4954 tempreg
, tempreg
, BFD_RELOC_LO16
);
4955 if (mips_relax
.sequence
)
4959 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4961 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4963 /* If this is a reference to an external symbol, and there
4964 is no constant, we want
4965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4966 or for lca or if tempreg is PIC_CALL_REG
4967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4968 For a local symbol, we want
4969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4971 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4973 If we have a small constant, and this is a reference to
4974 an external symbol, we want
4975 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4977 addiu $tempreg,$tempreg,<constant>
4978 For a local symbol, we want the same instruction
4979 sequence, but we output a BFD_RELOC_LO16 reloc on the
4982 If we have a large constant, and this is a reference to
4983 an external symbol, we want
4984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4985 lui $at,<hiconstant>
4986 addiu $at,$at,<loconstant>
4987 addu $tempreg,$tempreg,$at
4988 For a local symbol, we want the same instruction
4989 sequence, but we output a BFD_RELOC_LO16 reloc on the
4993 if (offset_expr
.X_add_number
== 0)
4995 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4996 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4998 relax_start (offset_expr
.X_add_symbol
);
4999 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5000 lw_reloc_type
, mips_gp_register
);
5003 /* We're going to put in an addu instruction using
5004 tempreg, so we may as well insert the nop right
5009 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5010 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5012 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5013 tempreg
, tempreg
, BFD_RELOC_LO16
);
5015 /* FIXME: If breg == 0, and the next instruction uses
5016 $tempreg, then if this variant case is used an extra
5017 nop will be generated. */
5019 else if (offset_expr
.X_add_number
>= -0x8000
5020 && offset_expr
.X_add_number
< 0x8000)
5022 load_got_offset (tempreg
, &offset_expr
);
5024 add_got_offset (tempreg
, &offset_expr
);
5028 expr1
.X_add_number
= offset_expr
.X_add_number
;
5029 offset_expr
.X_add_number
=
5030 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5031 load_got_offset (tempreg
, &offset_expr
);
5032 offset_expr
.X_add_number
= expr1
.X_add_number
;
5033 /* If we are going to add in a base register, and the
5034 target register and the base register are the same,
5035 then we are using AT as a temporary register. Since
5036 we want to load the constant into AT, we add our
5037 current AT (from the global offset table) and the
5038 register into the register now, and pretend we were
5039 not using a base register. */
5043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5048 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5052 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5054 int add_breg_early
= 0;
5056 /* If this is a reference to an external, and there is no
5057 constant, or local symbol (*), with or without a
5059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5060 or for lca or if tempreg is PIC_CALL_REG
5061 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5063 If we have a small constant, and this is a reference to
5064 an external symbol, we want
5065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5066 addiu $tempreg,$tempreg,<constant>
5068 If we have a large constant, and this is a reference to
5069 an external symbol, we want
5070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5071 lui $at,<hiconstant>
5072 addiu $at,$at,<loconstant>
5073 addu $tempreg,$tempreg,$at
5075 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5076 local symbols, even though it introduces an additional
5079 if (offset_expr
.X_add_number
)
5081 expr1
.X_add_number
= offset_expr
.X_add_number
;
5082 offset_expr
.X_add_number
= 0;
5084 relax_start (offset_expr
.X_add_symbol
);
5085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5086 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5088 if (expr1
.X_add_number
>= -0x8000
5089 && expr1
.X_add_number
< 0x8000)
5091 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5092 tempreg
, tempreg
, BFD_RELOC_LO16
);
5094 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5098 /* If we are going to add in a base register, and the
5099 target register and the base register are the same,
5100 then we are using AT as a temporary register. Since
5101 we want to load the constant into AT, we add our
5102 current AT (from the global offset table) and the
5103 register into the register now, and pretend we were
5104 not using a base register. */
5109 assert (tempreg
== AT
);
5110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5116 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5123 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5126 offset_expr
.X_add_number
= expr1
.X_add_number
;
5128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5129 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5132 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5133 treg
, tempreg
, breg
);
5139 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5141 relax_start (offset_expr
.X_add_symbol
);
5142 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5143 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5145 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5146 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5151 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5152 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5155 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5158 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5159 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5160 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5162 /* This is the large GOT case. If this is a reference to an
5163 external symbol, and there is no constant, we want
5164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5165 addu $tempreg,$tempreg,$gp
5166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5167 or for lca or if tempreg is PIC_CALL_REG
5168 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5169 addu $tempreg,$tempreg,$gp
5170 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5171 For a local symbol, we want
5172 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5174 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5176 If we have a small constant, and this is a reference to
5177 an external symbol, we want
5178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5179 addu $tempreg,$tempreg,$gp
5180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5182 addiu $tempreg,$tempreg,<constant>
5183 For a local symbol, we want
5184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5186 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5188 If we have a large constant, and this is a reference to
5189 an external symbol, we want
5190 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5191 addu $tempreg,$tempreg,$gp
5192 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5193 lui $at,<hiconstant>
5194 addiu $at,$at,<loconstant>
5195 addu $tempreg,$tempreg,$at
5196 For a local symbol, we want
5197 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5198 lui $at,<hiconstant>
5199 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5200 addu $tempreg,$tempreg,$at
5203 expr1
.X_add_number
= offset_expr
.X_add_number
;
5204 offset_expr
.X_add_number
= 0;
5205 relax_start (offset_expr
.X_add_symbol
);
5206 gpdelay
= reg_needs_delay (mips_gp_register
);
5207 if (expr1
.X_add_number
== 0 && breg
== 0
5208 && (call
|| tempreg
== PIC_CALL_REG
))
5210 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5211 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5213 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5214 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5215 tempreg
, tempreg
, mips_gp_register
);
5216 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5217 tempreg
, lw_reloc_type
, tempreg
);
5218 if (expr1
.X_add_number
== 0)
5222 /* We're going to put in an addu instruction using
5223 tempreg, so we may as well insert the nop right
5228 else if (expr1
.X_add_number
>= -0x8000
5229 && expr1
.X_add_number
< 0x8000)
5232 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5233 tempreg
, tempreg
, BFD_RELOC_LO16
);
5239 /* If we are going to add in a base register, and the
5240 target register and the base register are the same,
5241 then we are using AT as a temporary register. Since
5242 we want to load the constant into AT, we add our
5243 current AT (from the global offset table) and the
5244 register into the register now, and pretend we were
5245 not using a base register. */
5250 assert (tempreg
== AT
);
5252 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5257 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5258 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5262 offset_expr
.X_add_number
=
5263 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5268 /* This is needed because this instruction uses $gp, but
5269 the first instruction on the main stream does not. */
5270 macro_build (NULL
, "nop", "");
5273 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5274 local_reloc_type
, mips_gp_register
);
5275 if (expr1
.X_add_number
>= -0x8000
5276 && expr1
.X_add_number
< 0x8000)
5279 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5280 tempreg
, tempreg
, BFD_RELOC_LO16
);
5281 /* FIXME: If add_number is 0, and there was no base
5282 register, the external symbol case ended with a load,
5283 so if the symbol turns out to not be external, and
5284 the next instruction uses tempreg, an unnecessary nop
5285 will be inserted. */
5291 /* We must add in the base register now, as in the
5292 external symbol case. */
5293 assert (tempreg
== AT
);
5295 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5298 /* We set breg to 0 because we have arranged to add
5299 it in in both cases. */
5303 macro_build_lui (&expr1
, AT
);
5304 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5305 AT
, AT
, BFD_RELOC_LO16
);
5306 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5307 tempreg
, tempreg
, AT
);
5312 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5314 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5315 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5316 int add_breg_early
= 0;
5318 /* This is the large GOT case. If this is a reference to an
5319 external symbol, and there is no constant, we want
5320 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5321 add $tempreg,$tempreg,$gp
5322 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5323 or for lca or if tempreg is PIC_CALL_REG
5324 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5325 add $tempreg,$tempreg,$gp
5326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5328 If we have a small constant, and this is a reference to
5329 an external symbol, we want
5330 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5331 add $tempreg,$tempreg,$gp
5332 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5333 addi $tempreg,$tempreg,<constant>
5335 If we have a large constant, and this is a reference to
5336 an external symbol, we want
5337 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5338 addu $tempreg,$tempreg,$gp
5339 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5340 lui $at,<hiconstant>
5341 addi $at,$at,<loconstant>
5342 add $tempreg,$tempreg,$at
5344 If we have NewABI, and we know it's a local symbol, we want
5345 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5346 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5347 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5349 relax_start (offset_expr
.X_add_symbol
);
5351 expr1
.X_add_number
= offset_expr
.X_add_number
;
5352 offset_expr
.X_add_number
= 0;
5354 if (expr1
.X_add_number
== 0 && breg
== 0
5355 && (call
|| tempreg
== PIC_CALL_REG
))
5357 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5358 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5360 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5361 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5362 tempreg
, tempreg
, mips_gp_register
);
5363 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5364 tempreg
, lw_reloc_type
, tempreg
);
5366 if (expr1
.X_add_number
== 0)
5368 else if (expr1
.X_add_number
>= -0x8000
5369 && expr1
.X_add_number
< 0x8000)
5371 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5372 tempreg
, tempreg
, BFD_RELOC_LO16
);
5374 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5378 /* If we are going to add in a base register, and the
5379 target register and the base register are the same,
5380 then we are using AT as a temporary register. Since
5381 we want to load the constant into AT, we add our
5382 current AT (from the global offset table) and the
5383 register into the register now, and pretend we were
5384 not using a base register. */
5389 assert (tempreg
== AT
);
5390 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5396 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5397 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5402 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5405 offset_expr
.X_add_number
= expr1
.X_add_number
;
5406 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5407 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5408 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5409 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5412 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5413 treg
, tempreg
, breg
);
5423 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5427 /* The j instruction may not be used in PIC code, since it
5428 requires an absolute address. We convert it to a b
5430 if (mips_pic
== NO_PIC
)
5431 macro_build (&offset_expr
, "j", "a");
5433 macro_build (&offset_expr
, "b", "p");
5436 /* The jal instructions must be handled as macros because when
5437 generating PIC code they expand to multi-instruction
5438 sequences. Normally they are simple instructions. */
5443 if (mips_pic
== NO_PIC
)
5444 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5445 else if (mips_pic
== SVR4_PIC
)
5447 if (sreg
!= PIC_CALL_REG
)
5448 as_warn (_("MIPS PIC call to register other than $25"));
5450 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5453 if (mips_cprestore_offset
< 0)
5454 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5457 if (! mips_frame_reg_valid
)
5459 as_warn (_("No .frame pseudo-op used in PIC code"));
5460 /* Quiet this warning. */
5461 mips_frame_reg_valid
= 1;
5463 if (! mips_cprestore_valid
)
5465 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5466 /* Quiet this warning. */
5467 mips_cprestore_valid
= 1;
5469 expr1
.X_add_number
= mips_cprestore_offset
;
5470 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5473 HAVE_64BIT_ADDRESSES
);
5483 if (mips_pic
== NO_PIC
)
5484 macro_build (&offset_expr
, "jal", "a");
5485 else if (mips_pic
== SVR4_PIC
)
5487 /* If this is a reference to an external symbol, and we are
5488 using a small GOT, we want
5489 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5493 lw $gp,cprestore($sp)
5494 The cprestore value is set using the .cprestore
5495 pseudo-op. If we are using a big GOT, we want
5496 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5498 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5502 lw $gp,cprestore($sp)
5503 If the symbol is not external, we want
5504 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5506 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5509 lw $gp,cprestore($sp)
5511 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5512 sequences above, minus nops, unless the symbol is local,
5513 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5519 relax_start (offset_expr
.X_add_symbol
);
5520 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5521 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5524 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5525 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5531 relax_start (offset_expr
.X_add_symbol
);
5532 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5533 BFD_RELOC_MIPS_CALL_HI16
);
5534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5535 PIC_CALL_REG
, mips_gp_register
);
5536 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5537 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5540 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5541 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5543 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5544 PIC_CALL_REG
, PIC_CALL_REG
,
5545 BFD_RELOC_MIPS_GOT_OFST
);
5549 macro_build_jalr (&offset_expr
);
5553 relax_start (offset_expr
.X_add_symbol
);
5556 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5557 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5566 gpdelay
= reg_needs_delay (mips_gp_register
);
5567 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5568 BFD_RELOC_MIPS_CALL_HI16
);
5569 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5570 PIC_CALL_REG
, mips_gp_register
);
5571 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5572 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5577 macro_build (NULL
, "nop", "");
5579 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5580 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5583 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5584 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5586 macro_build_jalr (&offset_expr
);
5588 if (mips_cprestore_offset
< 0)
5589 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5592 if (! mips_frame_reg_valid
)
5594 as_warn (_("No .frame pseudo-op used in PIC code"));
5595 /* Quiet this warning. */
5596 mips_frame_reg_valid
= 1;
5598 if (! mips_cprestore_valid
)
5600 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5601 /* Quiet this warning. */
5602 mips_cprestore_valid
= 1;
5604 if (mips_opts
.noreorder
)
5605 macro_build (NULL
, "nop", "");
5606 expr1
.X_add_number
= mips_cprestore_offset
;
5607 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5610 HAVE_64BIT_ADDRESSES
);
5636 /* Itbl support may require additional care here. */
5641 /* Itbl support may require additional care here. */
5646 /* Itbl support may require additional care here. */
5651 /* Itbl support may require additional care here. */
5663 if (mips_opts
.arch
== CPU_R4650
)
5665 as_bad (_("opcode not supported on this processor"));
5669 /* Itbl support may require additional care here. */
5674 /* Itbl support may require additional care here. */
5679 /* Itbl support may require additional care here. */
5699 if (breg
== treg
|| coproc
|| lr
)
5720 /* Itbl support may require additional care here. */
5725 /* Itbl support may require additional care here. */
5730 /* Itbl support may require additional care here. */
5735 /* Itbl support may require additional care here. */
5751 if (mips_opts
.arch
== CPU_R4650
)
5753 as_bad (_("opcode not supported on this processor"));
5758 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5779 /* Itbl support may require additional care here. */
5780 if (mask
== M_LWC1_AB
5781 || mask
== M_SWC1_AB
5782 || mask
== M_LDC1_AB
5783 || mask
== M_SDC1_AB
5792 if (offset_expr
.X_op
!= O_constant
5793 && offset_expr
.X_op
!= O_symbol
)
5795 as_bad (_("expression too complex"));
5796 offset_expr
.X_op
= O_constant
;
5799 if (HAVE_32BIT_ADDRESSES
5800 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5801 as_bad (_("Number (0x%lx%08lx) larger than 32 bits"),
5802 (unsigned long) (offset_expr
.X_add_number
>> 32),
5803 (unsigned long) (offset_expr
.X_add_number
& 0xffffffff));
5805 /* A constant expression in PIC code can be handled just as it
5806 is in non PIC code. */
5807 if (offset_expr
.X_op
== O_constant
)
5809 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5810 & ~(bfd_vma
) 0xffff);
5811 normalize_address_expr (&expr1
);
5812 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5814 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5815 tempreg
, tempreg
, breg
);
5816 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5818 else if (mips_pic
== NO_PIC
)
5820 /* If this is a reference to a GP relative symbol, and there
5821 is no base register, we want
5822 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5823 Otherwise, if there is no base register, we want
5824 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5825 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5826 If we have a constant, we need two instructions anyhow,
5827 so we always use the latter form.
5829 If we have a base register, and this is a reference to a
5830 GP relative symbol, we want
5831 addu $tempreg,$breg,$gp
5832 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5834 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5835 addu $tempreg,$tempreg,$breg
5836 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5837 With a constant we always use the latter case.
5839 With 64bit address space and no base register and $at usable,
5841 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5842 lui $at,<sym> (BFD_RELOC_HI16_S)
5843 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5846 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5847 If we have a base register, we want
5848 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5849 lui $at,<sym> (BFD_RELOC_HI16_S)
5850 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5854 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5856 Without $at we can't generate the optimal path for superscalar
5857 processors here since this would require two temporary registers.
5858 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5859 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5861 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5864 If we have a base register, we want
5865 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5866 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5868 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5870 daddu $tempreg,$tempreg,$breg
5871 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5873 For GP relative symbols in 64bit address space we can use
5874 the same sequence as in 32bit address space. */
5875 if (HAVE_64BIT_SYMBOLS
)
5877 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5878 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5880 relax_start (offset_expr
.X_add_symbol
);
5883 macro_build (&offset_expr
, s
, fmt
, treg
,
5884 BFD_RELOC_GPREL16
, mips_gp_register
);
5888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5889 tempreg
, breg
, mips_gp_register
);
5890 macro_build (&offset_expr
, s
, fmt
, treg
,
5891 BFD_RELOC_GPREL16
, tempreg
);
5896 if (used_at
== 0 && !mips_opts
.noat
)
5898 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5899 BFD_RELOC_MIPS_HIGHEST
);
5900 macro_build (&offset_expr
, "lui", "t,u", AT
,
5902 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5903 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5905 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5906 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5907 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5908 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5914 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5915 BFD_RELOC_MIPS_HIGHEST
);
5916 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5917 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5918 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5919 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5920 tempreg
, BFD_RELOC_HI16_S
);
5921 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5923 macro_build (NULL
, "daddu", "d,v,t",
5924 tempreg
, tempreg
, breg
);
5925 macro_build (&offset_expr
, s
, fmt
, treg
,
5926 BFD_RELOC_LO16
, tempreg
);
5929 if (mips_relax
.sequence
)
5936 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5937 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5939 relax_start (offset_expr
.X_add_symbol
);
5940 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5944 macro_build_lui (&offset_expr
, tempreg
);
5945 macro_build (&offset_expr
, s
, fmt
, treg
,
5946 BFD_RELOC_LO16
, tempreg
);
5947 if (mips_relax
.sequence
)
5952 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5953 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5955 relax_start (offset_expr
.X_add_symbol
);
5956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5957 tempreg
, breg
, mips_gp_register
);
5958 macro_build (&offset_expr
, s
, fmt
, treg
,
5959 BFD_RELOC_GPREL16
, tempreg
);
5962 macro_build_lui (&offset_expr
, tempreg
);
5963 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5964 tempreg
, tempreg
, breg
);
5965 macro_build (&offset_expr
, s
, fmt
, treg
,
5966 BFD_RELOC_LO16
, tempreg
);
5967 if (mips_relax
.sequence
)
5971 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5973 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5975 /* If this is a reference to an external symbol, we want
5976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5978 <op> $treg,0($tempreg)
5980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5982 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5983 <op> $treg,0($tempreg)
5986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5987 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5989 If there is a base register, we add it to $tempreg before
5990 the <op>. If there is a constant, we stick it in the
5991 <op> instruction. We don't handle constants larger than
5992 16 bits, because we have no way to load the upper 16 bits
5993 (actually, we could handle them for the subset of cases
5994 in which we are not using $at). */
5995 assert (offset_expr
.X_op
== O_symbol
);
5998 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5999 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6002 tempreg
, tempreg
, breg
);
6003 macro_build (&offset_expr
, s
, fmt
, treg
,
6004 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6007 expr1
.X_add_number
= offset_expr
.X_add_number
;
6008 offset_expr
.X_add_number
= 0;
6009 if (expr1
.X_add_number
< -0x8000
6010 || expr1
.X_add_number
>= 0x8000)
6011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6012 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6013 lw_reloc_type
, mips_gp_register
);
6015 relax_start (offset_expr
.X_add_symbol
);
6017 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6018 tempreg
, BFD_RELOC_LO16
);
6021 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6022 tempreg
, tempreg
, breg
);
6023 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6025 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6029 /* If this is a reference to an external symbol, we want
6030 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6031 addu $tempreg,$tempreg,$gp
6032 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6033 <op> $treg,0($tempreg)
6035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6037 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6038 <op> $treg,0($tempreg)
6039 If there is a base register, we add it to $tempreg before
6040 the <op>. If there is a constant, we stick it in the
6041 <op> instruction. We don't handle constants larger than
6042 16 bits, because we have no way to load the upper 16 bits
6043 (actually, we could handle them for the subset of cases
6044 in which we are not using $at). */
6045 assert (offset_expr
.X_op
== O_symbol
);
6046 expr1
.X_add_number
= offset_expr
.X_add_number
;
6047 offset_expr
.X_add_number
= 0;
6048 if (expr1
.X_add_number
< -0x8000
6049 || expr1
.X_add_number
>= 0x8000)
6050 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6051 gpdelay
= reg_needs_delay (mips_gp_register
);
6052 relax_start (offset_expr
.X_add_symbol
);
6053 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6054 BFD_RELOC_MIPS_GOT_HI16
);
6055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6057 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6058 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6061 macro_build (NULL
, "nop", "");
6062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6063 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6065 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6066 tempreg
, BFD_RELOC_LO16
);
6070 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6071 tempreg
, tempreg
, breg
);
6072 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6074 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6076 /* If this is a reference to an external symbol, we want
6077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6078 add $tempreg,$tempreg,$gp
6079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6080 <op> $treg,<ofst>($tempreg)
6081 Otherwise, for local symbols, we want:
6082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6083 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6084 assert (offset_expr
.X_op
== O_symbol
);
6085 expr1
.X_add_number
= offset_expr
.X_add_number
;
6086 offset_expr
.X_add_number
= 0;
6087 if (expr1
.X_add_number
< -0x8000
6088 || expr1
.X_add_number
>= 0x8000)
6089 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6090 relax_start (offset_expr
.X_add_symbol
);
6091 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6092 BFD_RELOC_MIPS_GOT_HI16
);
6093 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6095 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6096 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6099 tempreg
, tempreg
, breg
);
6100 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6103 offset_expr
.X_add_number
= expr1
.X_add_number
;
6104 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6105 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6108 tempreg
, tempreg
, breg
);
6109 macro_build (&offset_expr
, s
, fmt
, treg
,
6110 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6120 load_register (treg
, &imm_expr
, 0);
6124 load_register (treg
, &imm_expr
, 1);
6128 if (imm_expr
.X_op
== O_constant
)
6131 load_register (AT
, &imm_expr
, 0);
6132 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6137 assert (offset_expr
.X_op
== O_symbol
6138 && strcmp (segment_name (S_GET_SEGMENT
6139 (offset_expr
.X_add_symbol
)),
6141 && offset_expr
.X_add_number
== 0);
6142 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6143 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6148 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6149 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6150 order 32 bits of the value and the low order 32 bits are either
6151 zero or in OFFSET_EXPR. */
6152 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6154 if (HAVE_64BIT_GPRS
)
6155 load_register (treg
, &imm_expr
, 1);
6160 if (target_big_endian
)
6172 load_register (hreg
, &imm_expr
, 0);
6175 if (offset_expr
.X_op
== O_absent
)
6176 move_register (lreg
, 0);
6179 assert (offset_expr
.X_op
== O_constant
);
6180 load_register (lreg
, &offset_expr
, 0);
6187 /* We know that sym is in the .rdata section. First we get the
6188 upper 16 bits of the address. */
6189 if (mips_pic
== NO_PIC
)
6191 macro_build_lui (&offset_expr
, AT
);
6194 else if (mips_pic
== SVR4_PIC
)
6196 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6197 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6203 /* Now we load the register(s). */
6204 if (HAVE_64BIT_GPRS
)
6207 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6212 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6215 /* FIXME: How in the world do we deal with the possible
6217 offset_expr
.X_add_number
+= 4;
6218 macro_build (&offset_expr
, "lw", "t,o(b)",
6219 treg
+ 1, BFD_RELOC_LO16
, AT
);
6225 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6226 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6227 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6228 the value and the low order 32 bits are either zero or in
6230 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6233 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6234 if (HAVE_64BIT_FPRS
)
6236 assert (HAVE_64BIT_GPRS
);
6237 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6241 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6242 if (offset_expr
.X_op
== O_absent
)
6243 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6246 assert (offset_expr
.X_op
== O_constant
);
6247 load_register (AT
, &offset_expr
, 0);
6248 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6254 assert (offset_expr
.X_op
== O_symbol
6255 && offset_expr
.X_add_number
== 0);
6256 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6257 if (strcmp (s
, ".lit8") == 0)
6259 if (mips_opts
.isa
!= ISA_MIPS1
)
6261 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6262 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6265 breg
= mips_gp_register
;
6266 r
= BFD_RELOC_MIPS_LITERAL
;
6271 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6273 if (mips_pic
== SVR4_PIC
)
6274 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6275 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6278 /* FIXME: This won't work for a 64 bit address. */
6279 macro_build_lui (&offset_expr
, AT
);
6282 if (mips_opts
.isa
!= ISA_MIPS1
)
6284 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6285 treg
, BFD_RELOC_LO16
, AT
);
6294 if (mips_opts
.arch
== CPU_R4650
)
6296 as_bad (_("opcode not supported on this processor"));
6299 /* Even on a big endian machine $fn comes before $fn+1. We have
6300 to adjust when loading from memory. */
6303 assert (mips_opts
.isa
== ISA_MIPS1
);
6304 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6305 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6306 /* FIXME: A possible overflow which I don't know how to deal
6308 offset_expr
.X_add_number
+= 4;
6309 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6310 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6315 * The MIPS assembler seems to check for X_add_number not
6316 * being double aligned and generating:
6319 * addiu at,at,%lo(foo+1)
6322 * But, the resulting address is the same after relocation so why
6323 * generate the extra instruction?
6325 if (mips_opts
.arch
== CPU_R4650
)
6327 as_bad (_("opcode not supported on this processor"));
6330 /* Itbl support may require additional care here. */
6332 if (mips_opts
.isa
!= ISA_MIPS1
)
6343 if (mips_opts
.arch
== CPU_R4650
)
6345 as_bad (_("opcode not supported on this processor"));
6349 if (mips_opts
.isa
!= ISA_MIPS1
)
6357 /* Itbl support may require additional care here. */
6362 if (HAVE_64BIT_GPRS
)
6373 if (HAVE_64BIT_GPRS
)
6383 if (offset_expr
.X_op
!= O_symbol
6384 && offset_expr
.X_op
!= O_constant
)
6386 as_bad (_("expression too complex"));
6387 offset_expr
.X_op
= O_constant
;
6390 if (HAVE_32BIT_ADDRESSES
6391 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6392 as_bad (_("Number (0x%lx%08lx) larger than 32 bits"),
6393 (unsigned long) (offset_expr
.X_add_number
>> 32),
6394 (unsigned long) (offset_expr
.X_add_number
& 0xffffffff));
6396 /* Even on a big endian machine $fn comes before $fn+1. We have
6397 to adjust when loading from memory. We set coproc if we must
6398 load $fn+1 first. */
6399 /* Itbl support may require additional care here. */
6400 if (! target_big_endian
)
6403 if (mips_pic
== NO_PIC
6404 || offset_expr
.X_op
== O_constant
)
6406 /* If this is a reference to a GP relative symbol, we want
6407 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6408 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6409 If we have a base register, we use this
6411 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6412 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6413 If this is not a GP relative symbol, we want
6414 lui $at,<sym> (BFD_RELOC_HI16_S)
6415 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6416 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6417 If there is a base register, we add it to $at after the
6418 lui instruction. If there is a constant, we always use
6420 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6421 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6423 relax_start (offset_expr
.X_add_symbol
);
6426 tempreg
= mips_gp_register
;
6430 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6431 AT
, breg
, mips_gp_register
);
6436 /* Itbl support may require additional care here. */
6437 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6438 BFD_RELOC_GPREL16
, tempreg
);
6439 offset_expr
.X_add_number
+= 4;
6441 /* Set mips_optimize to 2 to avoid inserting an
6443 hold_mips_optimize
= mips_optimize
;
6445 /* Itbl support may require additional care here. */
6446 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6447 BFD_RELOC_GPREL16
, tempreg
);
6448 mips_optimize
= hold_mips_optimize
;
6452 /* We just generated two relocs. When tc_gen_reloc
6453 handles this case, it will skip the first reloc and
6454 handle the second. The second reloc already has an
6455 extra addend of 4, which we added above. We must
6456 subtract it out, and then subtract another 4 to make
6457 the first reloc come out right. The second reloc
6458 will come out right because we are going to add 4 to
6459 offset_expr when we build its instruction below.
6461 If we have a symbol, then we don't want to include
6462 the offset, because it will wind up being included
6463 when we generate the reloc. */
6465 if (offset_expr
.X_op
== O_constant
)
6466 offset_expr
.X_add_number
-= 8;
6469 offset_expr
.X_add_number
= -4;
6470 offset_expr
.X_op
= O_constant
;
6474 macro_build_lui (&offset_expr
, AT
);
6476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6477 /* Itbl support may require additional care here. */
6478 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6479 BFD_RELOC_LO16
, AT
);
6480 /* FIXME: How do we handle overflow here? */
6481 offset_expr
.X_add_number
+= 4;
6482 /* Itbl support may require additional care here. */
6483 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6484 BFD_RELOC_LO16
, AT
);
6485 if (mips_relax
.sequence
)
6488 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6490 /* If this is a reference to an external symbol, we want
6491 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6496 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6498 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6499 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6500 If there is a base register we add it to $at before the
6501 lwc1 instructions. If there is a constant we include it
6502 in the lwc1 instructions. */
6504 expr1
.X_add_number
= offset_expr
.X_add_number
;
6505 if (expr1
.X_add_number
< -0x8000
6506 || expr1
.X_add_number
>= 0x8000 - 4)
6507 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6508 load_got_offset (AT
, &offset_expr
);
6511 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6513 /* Set mips_optimize to 2 to avoid inserting an undesired
6515 hold_mips_optimize
= mips_optimize
;
6518 /* Itbl support may require additional care here. */
6519 relax_start (offset_expr
.X_add_symbol
);
6520 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6521 BFD_RELOC_LO16
, AT
);
6522 expr1
.X_add_number
+= 4;
6523 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6524 BFD_RELOC_LO16
, AT
);
6526 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6527 BFD_RELOC_LO16
, AT
);
6528 offset_expr
.X_add_number
+= 4;
6529 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6530 BFD_RELOC_LO16
, AT
);
6533 mips_optimize
= hold_mips_optimize
;
6535 else if (mips_pic
== SVR4_PIC
)
6539 /* If this is a reference to an external symbol, we want
6540 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6542 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6547 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6549 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6550 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6551 If there is a base register we add it to $at before the
6552 lwc1 instructions. If there is a constant we include it
6553 in the lwc1 instructions. */
6555 expr1
.X_add_number
= offset_expr
.X_add_number
;
6556 offset_expr
.X_add_number
= 0;
6557 if (expr1
.X_add_number
< -0x8000
6558 || expr1
.X_add_number
>= 0x8000 - 4)
6559 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6560 gpdelay
= reg_needs_delay (mips_gp_register
);
6561 relax_start (offset_expr
.X_add_symbol
);
6562 macro_build (&offset_expr
, "lui", "t,u",
6563 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6564 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6565 AT
, AT
, mips_gp_register
);
6566 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6567 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6570 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6571 /* Itbl support may require additional care here. */
6572 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6573 BFD_RELOC_LO16
, AT
);
6574 expr1
.X_add_number
+= 4;
6576 /* Set mips_optimize to 2 to avoid inserting an undesired
6578 hold_mips_optimize
= mips_optimize
;
6580 /* Itbl support may require additional care here. */
6581 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6582 BFD_RELOC_LO16
, AT
);
6583 mips_optimize
= hold_mips_optimize
;
6584 expr1
.X_add_number
-= 4;
6587 offset_expr
.X_add_number
= expr1
.X_add_number
;
6589 macro_build (NULL
, "nop", "");
6590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6591 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6594 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6595 /* Itbl support may require additional care here. */
6596 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6597 BFD_RELOC_LO16
, AT
);
6598 offset_expr
.X_add_number
+= 4;
6600 /* Set mips_optimize to 2 to avoid inserting an undesired
6602 hold_mips_optimize
= mips_optimize
;
6604 /* Itbl support may require additional care here. */
6605 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6606 BFD_RELOC_LO16
, AT
);
6607 mips_optimize
= hold_mips_optimize
;
6621 assert (HAVE_32BIT_ADDRESSES
);
6622 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6623 offset_expr
.X_add_number
+= 4;
6624 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6627 /* New code added to support COPZ instructions.
6628 This code builds table entries out of the macros in mip_opcodes.
6629 R4000 uses interlocks to handle coproc delays.
6630 Other chips (like the R3000) require nops to be inserted for delays.
6632 FIXME: Currently, we require that the user handle delays.
6633 In order to fill delay slots for non-interlocked chips,
6634 we must have a way to specify delays based on the coprocessor.
6635 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6636 What are the side-effects of the cop instruction?
6637 What cache support might we have and what are its effects?
6638 Both coprocessor & memory require delays. how long???
6639 What registers are read/set/modified?
6641 If an itbl is provided to interpret cop instructions,
6642 this knowledge can be encoded in the itbl spec. */
6656 /* For now we just do C (same as Cz). The parameter will be
6657 stored in insn_opcode by mips_ip. */
6658 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6662 move_register (dreg
, sreg
);
6665 #ifdef LOSING_COMPILER
6667 /* Try and see if this is a new itbl instruction.
6668 This code builds table entries out of the macros in mip_opcodes.
6669 FIXME: For now we just assemble the expression and pass it's
6670 value along as a 32-bit immediate.
6671 We may want to have the assembler assemble this value,
6672 so that we gain the assembler's knowledge of delay slots,
6674 Would it be more efficient to use mask (id) here? */
6675 if (itbl_have_entries
6676 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6678 s
= ip
->insn_mo
->name
;
6680 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6681 macro_build (&immed_expr
, s
, "C");
6687 if (mips_opts
.noat
&& used_at
)
6688 as_bad (_("Macro used $at after \".set noat\""));
6692 macro2 (struct mips_cl_insn
*ip
)
6694 register int treg
, sreg
, dreg
, breg
;
6709 bfd_reloc_code_real_type r
;
6711 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6712 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6713 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6714 mask
= ip
->insn_mo
->mask
;
6716 expr1
.X_op
= O_constant
;
6717 expr1
.X_op_symbol
= NULL
;
6718 expr1
.X_add_symbol
= NULL
;
6719 expr1
.X_add_number
= 1;
6723 #endif /* LOSING_COMPILER */
6728 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6729 macro_build (NULL
, "mflo", "d", dreg
);
6735 /* The MIPS assembler some times generates shifts and adds. I'm
6736 not trying to be that fancy. GCC should do this for us
6739 load_register (AT
, &imm_expr
, dbl
);
6740 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6741 macro_build (NULL
, "mflo", "d", dreg
);
6757 load_register (AT
, &imm_expr
, dbl
);
6758 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6759 macro_build (NULL
, "mflo", "d", dreg
);
6760 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6761 macro_build (NULL
, "mfhi", "d", AT
);
6763 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6766 expr1
.X_add_number
= 8;
6767 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6768 macro_build (NULL
, "nop", "", 0);
6769 macro_build (NULL
, "break", "c", 6);
6772 macro_build (NULL
, "mflo", "d", dreg
);
6788 load_register (AT
, &imm_expr
, dbl
);
6789 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6790 sreg
, imm
? AT
: treg
);
6791 macro_build (NULL
, "mfhi", "d", AT
);
6792 macro_build (NULL
, "mflo", "d", dreg
);
6794 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6797 expr1
.X_add_number
= 8;
6798 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6799 macro_build (NULL
, "nop", "", 0);
6800 macro_build (NULL
, "break", "c", 6);
6806 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6817 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6818 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6822 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6823 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6824 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6825 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6829 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6840 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6841 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6845 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6846 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6847 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6848 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6856 if (imm_expr
.X_op
!= O_constant
)
6857 as_bad (_("Improper rotate count"));
6858 rot
= imm_expr
.X_add_number
& 0x3f;
6859 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6861 rot
= (64 - rot
) & 0x3f;
6863 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6865 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6870 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6873 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6874 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6877 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6878 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6879 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6887 if (imm_expr
.X_op
!= O_constant
)
6888 as_bad (_("Improper rotate count"));
6889 rot
= imm_expr
.X_add_number
& 0x1f;
6890 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6892 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6897 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6901 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6902 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6903 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6908 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6910 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6914 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6915 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6916 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6917 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6921 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6923 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6927 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6928 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6929 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6930 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6938 if (imm_expr
.X_op
!= O_constant
)
6939 as_bad (_("Improper rotate count"));
6940 rot
= imm_expr
.X_add_number
& 0x3f;
6941 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6944 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6946 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6951 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6954 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6955 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6958 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6959 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6960 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6968 if (imm_expr
.X_op
!= O_constant
)
6969 as_bad (_("Improper rotate count"));
6970 rot
= imm_expr
.X_add_number
& 0x1f;
6971 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6973 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6978 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6982 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6983 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6984 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6989 if (mips_opts
.arch
== CPU_R4650
)
6991 as_bad (_("opcode not supported on this processor"));
6994 assert (mips_opts
.isa
== ISA_MIPS1
);
6995 /* Even on a big endian machine $fn comes before $fn+1. We have
6996 to adjust when storing to memory. */
6997 macro_build (&offset_expr
, "swc1", "T,o(b)",
6998 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6999 offset_expr
.X_add_number
+= 4;
7000 macro_build (&offset_expr
, "swc1", "T,o(b)",
7001 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7006 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7008 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7011 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7012 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7017 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7019 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7024 as_warn (_("Instruction %s: result is always false"),
7026 move_register (dreg
, 0);
7029 if (imm_expr
.X_op
== O_constant
7030 && imm_expr
.X_add_number
>= 0
7031 && imm_expr
.X_add_number
< 0x10000)
7033 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7035 else if (imm_expr
.X_op
== O_constant
7036 && imm_expr
.X_add_number
> -0x8000
7037 && imm_expr
.X_add_number
< 0)
7039 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7040 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7041 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7045 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7046 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7049 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7052 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7058 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7059 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7062 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7064 if (imm_expr
.X_op
== O_constant
7065 && imm_expr
.X_add_number
>= -0x8000
7066 && imm_expr
.X_add_number
< 0x8000)
7068 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7069 dreg
, sreg
, BFD_RELOC_LO16
);
7073 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7074 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7078 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7081 case M_SGT
: /* sreg > treg <==> treg < sreg */
7087 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7090 case M_SGT_I
: /* sreg > I <==> I < sreg */
7097 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7098 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7101 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7107 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7108 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7111 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7118 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7119 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7120 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7124 if (imm_expr
.X_op
== O_constant
7125 && imm_expr
.X_add_number
>= -0x8000
7126 && imm_expr
.X_add_number
< 0x8000)
7128 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7132 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7133 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7137 if (imm_expr
.X_op
== O_constant
7138 && imm_expr
.X_add_number
>= -0x8000
7139 && imm_expr
.X_add_number
< 0x8000)
7141 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7146 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7147 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7152 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7154 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7157 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7158 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7163 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7165 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7170 as_warn (_("Instruction %s: result is always true"),
7172 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7173 dreg
, 0, BFD_RELOC_LO16
);
7176 if (imm_expr
.X_op
== O_constant
7177 && imm_expr
.X_add_number
>= 0
7178 && imm_expr
.X_add_number
< 0x10000)
7180 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7182 else if (imm_expr
.X_op
== O_constant
7183 && imm_expr
.X_add_number
> -0x8000
7184 && imm_expr
.X_add_number
< 0)
7186 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7187 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7188 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7192 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7193 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7196 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7202 if (imm_expr
.X_op
== O_constant
7203 && imm_expr
.X_add_number
> -0x8000
7204 && imm_expr
.X_add_number
<= 0x8000)
7206 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7207 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7208 dreg
, sreg
, BFD_RELOC_LO16
);
7212 load_register (AT
, &imm_expr
, dbl
);
7213 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7219 if (imm_expr
.X_op
== O_constant
7220 && imm_expr
.X_add_number
> -0x8000
7221 && imm_expr
.X_add_number
<= 0x8000)
7223 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7224 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7225 dreg
, sreg
, BFD_RELOC_LO16
);
7229 load_register (AT
, &imm_expr
, dbl
);
7230 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7252 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7253 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7258 assert (mips_opts
.isa
== ISA_MIPS1
);
7260 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7261 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7264 * Is the double cfc1 instruction a bug in the mips assembler;
7265 * or is there a reason for it?
7268 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7269 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7270 macro_build (NULL
, "nop", "");
7271 expr1
.X_add_number
= 3;
7272 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7273 expr1
.X_add_number
= 2;
7274 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7275 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7276 macro_build (NULL
, "nop", "");
7277 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7279 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7280 macro_build (NULL
, "nop", "");
7291 if (offset_expr
.X_add_number
>= 0x7fff)
7292 as_bad (_("operand overflow"));
7293 if (! target_big_endian
)
7294 ++offset_expr
.X_add_number
;
7295 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7296 if (! target_big_endian
)
7297 --offset_expr
.X_add_number
;
7299 ++offset_expr
.X_add_number
;
7300 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7301 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7302 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7315 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7316 as_bad (_("operand overflow"));
7324 if (! target_big_endian
)
7325 offset_expr
.X_add_number
+= off
;
7326 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7327 if (! target_big_endian
)
7328 offset_expr
.X_add_number
-= off
;
7330 offset_expr
.X_add_number
+= off
;
7331 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7333 /* If necessary, move the result in tempreg the final destination. */
7334 if (treg
== tempreg
)
7336 /* Protect second load's delay slot. */
7338 move_register (treg
, tempreg
);
7352 load_address (AT
, &offset_expr
, &used_at
);
7354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7355 if (! target_big_endian
)
7356 expr1
.X_add_number
= off
;
7358 expr1
.X_add_number
= 0;
7359 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7360 if (! target_big_endian
)
7361 expr1
.X_add_number
= 0;
7363 expr1
.X_add_number
= off
;
7364 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7370 load_address (AT
, &offset_expr
, &used_at
);
7372 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7373 if (target_big_endian
)
7374 expr1
.X_add_number
= 0;
7375 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7376 treg
, BFD_RELOC_LO16
, AT
);
7377 if (target_big_endian
)
7378 expr1
.X_add_number
= 1;
7380 expr1
.X_add_number
= 0;
7381 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7382 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7383 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7388 if (offset_expr
.X_add_number
>= 0x7fff)
7389 as_bad (_("operand overflow"));
7390 if (target_big_endian
)
7391 ++offset_expr
.X_add_number
;
7392 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7393 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7394 if (target_big_endian
)
7395 --offset_expr
.X_add_number
;
7397 ++offset_expr
.X_add_number
;
7398 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7411 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7412 as_bad (_("operand overflow"));
7413 if (! target_big_endian
)
7414 offset_expr
.X_add_number
+= off
;
7415 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7416 if (! target_big_endian
)
7417 offset_expr
.X_add_number
-= off
;
7419 offset_expr
.X_add_number
+= off
;
7420 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7434 load_address (AT
, &offset_expr
, &used_at
);
7436 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7437 if (! target_big_endian
)
7438 expr1
.X_add_number
= off
;
7440 expr1
.X_add_number
= 0;
7441 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7442 if (! target_big_endian
)
7443 expr1
.X_add_number
= 0;
7445 expr1
.X_add_number
= off
;
7446 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7451 load_address (AT
, &offset_expr
, &used_at
);
7453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7454 if (! target_big_endian
)
7455 expr1
.X_add_number
= 0;
7456 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7457 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7458 if (! target_big_endian
)
7459 expr1
.X_add_number
= 1;
7461 expr1
.X_add_number
= 0;
7462 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7463 if (! target_big_endian
)
7464 expr1
.X_add_number
= 0;
7466 expr1
.X_add_number
= 1;
7467 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7468 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7469 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7473 /* FIXME: Check if this is one of the itbl macros, since they
7474 are added dynamically. */
7475 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7478 if (mips_opts
.noat
&& used_at
)
7479 as_bad (_("Macro used $at after \".set noat\""));
7482 /* Implement macros in mips16 mode. */
7485 mips16_macro (struct mips_cl_insn
*ip
)
7488 int xreg
, yreg
, zreg
, tmp
;
7491 const char *s
, *s2
, *s3
;
7493 mask
= ip
->insn_mo
->mask
;
7495 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7496 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7497 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7499 expr1
.X_op
= O_constant
;
7500 expr1
.X_op_symbol
= NULL
;
7501 expr1
.X_add_symbol
= NULL
;
7502 expr1
.X_add_number
= 1;
7522 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7523 expr1
.X_add_number
= 2;
7524 macro_build (&expr1
, "bnez", "x,p", yreg
);
7525 macro_build (NULL
, "break", "6", 7);
7527 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7528 since that causes an overflow. We should do that as well,
7529 but I don't see how to do the comparisons without a temporary
7532 macro_build (NULL
, s
, "x", zreg
);
7552 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7553 expr1
.X_add_number
= 2;
7554 macro_build (&expr1
, "bnez", "x,p", yreg
);
7555 macro_build (NULL
, "break", "6", 7);
7557 macro_build (NULL
, s2
, "x", zreg
);
7563 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7564 macro_build (NULL
, "mflo", "x", zreg
);
7572 if (imm_expr
.X_op
!= O_constant
)
7573 as_bad (_("Unsupported large constant"));
7574 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7575 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7579 if (imm_expr
.X_op
!= O_constant
)
7580 as_bad (_("Unsupported large constant"));
7581 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7582 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7586 if (imm_expr
.X_op
!= O_constant
)
7587 as_bad (_("Unsupported large constant"));
7588 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7589 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7611 goto do_reverse_branch
;
7615 goto do_reverse_branch
;
7627 goto do_reverse_branch
;
7638 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7639 macro_build (&offset_expr
, s2
, "p");
7666 goto do_addone_branch_i
;
7671 goto do_addone_branch_i
;
7686 goto do_addone_branch_i
;
7693 if (imm_expr
.X_op
!= O_constant
)
7694 as_bad (_("Unsupported large constant"));
7695 ++imm_expr
.X_add_number
;
7698 macro_build (&imm_expr
, s
, s3
, xreg
);
7699 macro_build (&offset_expr
, s2
, "p");
7703 expr1
.X_add_number
= 0;
7704 macro_build (&expr1
, "slti", "x,8", yreg
);
7706 move_register (xreg
, yreg
);
7707 expr1
.X_add_number
= 2;
7708 macro_build (&expr1
, "bteqz", "p");
7709 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7713 /* For consistency checking, verify that all bits are specified either
7714 by the match/mask part of the instruction definition, or by the
7717 validate_mips_insn (const struct mips_opcode
*opc
)
7719 const char *p
= opc
->args
;
7721 unsigned long used_bits
= opc
->mask
;
7723 if ((used_bits
& opc
->match
) != opc
->match
)
7725 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7726 opc
->name
, opc
->args
);
7729 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7739 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7740 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7741 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7742 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7743 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7744 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7745 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7746 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7747 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7750 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7751 c
, opc
->name
, opc
->args
);
7755 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7756 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7758 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7759 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7760 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7761 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7763 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7764 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7766 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7767 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7769 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7770 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7771 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7772 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7773 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7774 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7775 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7776 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7777 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7778 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7779 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7780 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7781 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7782 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7783 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7784 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7785 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7787 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7788 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7789 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7790 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7792 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7793 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7794 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7795 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7796 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7797 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7798 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7799 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7800 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7803 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7804 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7805 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7806 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7807 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7811 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7812 c
, opc
->name
, opc
->args
);
7816 if (used_bits
!= 0xffffffff)
7818 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7819 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7825 /* This routine assembles an instruction into its binary format. As a
7826 side effect, it sets one of the global variables imm_reloc or
7827 offset_reloc to the type of relocation to do if one of the operands
7828 is an address expression. */
7831 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7836 struct mips_opcode
*insn
;
7839 unsigned int lastregno
= 0;
7840 unsigned int lastpos
= 0;
7841 unsigned int limlo
, limhi
;
7847 /* If the instruction contains a '.', we first try to match an instruction
7848 including the '.'. Then we try again without the '.'. */
7850 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7853 /* If we stopped on whitespace, then replace the whitespace with null for
7854 the call to hash_find. Save the character we replaced just in case we
7855 have to re-parse the instruction. */
7862 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7864 /* If we didn't find the instruction in the opcode table, try again, but
7865 this time with just the instruction up to, but not including the
7869 /* Restore the character we overwrite above (if any). */
7873 /* Scan up to the first '.' or whitespace. */
7875 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7879 /* If we did not find a '.', then we can quit now. */
7882 insn_error
= "unrecognized opcode";
7886 /* Lookup the instruction in the hash table. */
7888 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7890 insn_error
= "unrecognized opcode";
7900 assert (strcmp (insn
->name
, str
) == 0);
7902 if (OPCODE_IS_MEMBER (insn
,
7904 | (file_ase_mips16
? INSN_MIPS16
: 0)
7905 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7906 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7912 if (insn
->pinfo
!= INSN_MACRO
)
7914 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7920 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7921 && strcmp (insn
->name
, insn
[1].name
) == 0)
7930 static char buf
[100];
7932 _("opcode not supported on this processor: %s (%s)"),
7933 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7934 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7943 create_insn (ip
, insn
);
7945 for (args
= insn
->args
;; ++args
)
7949 s
+= strspn (s
, " \t");
7953 case '\0': /* end of args */
7966 INSERT_OPERAND (RS
, *ip
, lastregno
);
7970 INSERT_OPERAND (RT
, *ip
, lastregno
);
7974 INSERT_OPERAND (FT
, *ip
, lastregno
);
7978 INSERT_OPERAND (FS
, *ip
, lastregno
);
7984 /* Handle optional base register.
7985 Either the base register is omitted or
7986 we must have a left paren. */
7987 /* This is dependent on the next operand specifier
7988 is a base register specification. */
7989 assert (args
[1] == 'b' || args
[1] == '5'
7990 || args
[1] == '-' || args
[1] == '4');
7994 case ')': /* these must match exactly */
8001 case '+': /* Opcode extension character. */
8004 case 'A': /* ins/ext position, becomes LSB. */
8013 my_getExpression (&imm_expr
, s
);
8014 check_absolute_expr (ip
, &imm_expr
);
8015 if ((unsigned long) imm_expr
.X_add_number
< limlo
8016 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8018 as_bad (_("Improper position (%lu)"),
8019 (unsigned long) imm_expr
.X_add_number
);
8020 imm_expr
.X_add_number
= limlo
;
8022 lastpos
= imm_expr
.X_add_number
;
8023 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8024 imm_expr
.X_op
= O_absent
;
8028 case 'B': /* ins size, becomes MSB. */
8037 my_getExpression (&imm_expr
, s
);
8038 check_absolute_expr (ip
, &imm_expr
);
8039 /* Check for negative input so that small negative numbers
8040 will not succeed incorrectly. The checks against
8041 (pos+size) transitively check "size" itself,
8042 assuming that "pos" is reasonable. */
8043 if ((long) imm_expr
.X_add_number
< 0
8044 || ((unsigned long) imm_expr
.X_add_number
8046 || ((unsigned long) imm_expr
.X_add_number
8049 as_bad (_("Improper insert size (%lu, position %lu)"),
8050 (unsigned long) imm_expr
.X_add_number
,
8051 (unsigned long) lastpos
);
8052 imm_expr
.X_add_number
= limlo
- lastpos
;
8054 INSERT_OPERAND (INSMSB
, *ip
,
8055 lastpos
+ imm_expr
.X_add_number
- 1);
8056 imm_expr
.X_op
= O_absent
;
8060 case 'C': /* ext size, becomes MSBD. */
8073 my_getExpression (&imm_expr
, s
);
8074 check_absolute_expr (ip
, &imm_expr
);
8075 /* Check for negative input so that small negative numbers
8076 will not succeed incorrectly. The checks against
8077 (pos+size) transitively check "size" itself,
8078 assuming that "pos" is reasonable. */
8079 if ((long) imm_expr
.X_add_number
< 0
8080 || ((unsigned long) imm_expr
.X_add_number
8082 || ((unsigned long) imm_expr
.X_add_number
8085 as_bad (_("Improper extract size (%lu, position %lu)"),
8086 (unsigned long) imm_expr
.X_add_number
,
8087 (unsigned long) lastpos
);
8088 imm_expr
.X_add_number
= limlo
- lastpos
;
8090 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8091 imm_expr
.X_op
= O_absent
;
8096 /* +D is for disassembly only; never match. */
8100 /* "+I" is like "I", except that imm2_expr is used. */
8101 my_getExpression (&imm2_expr
, s
);
8102 if (imm2_expr
.X_op
!= O_big
8103 && imm2_expr
.X_op
!= O_constant
)
8104 insn_error
= _("absolute expression required");
8105 normalize_constant_expr (&imm2_expr
);
8110 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8111 *args
, insn
->name
, insn
->args
);
8112 /* Further processing is fruitless. */
8117 case '<': /* must be at least one digit */
8119 * According to the manual, if the shift amount is greater
8120 * than 31 or less than 0, then the shift amount should be
8121 * mod 32. In reality the mips assembler issues an error.
8122 * We issue a warning and mask out all but the low 5 bits.
8124 my_getExpression (&imm_expr
, s
);
8125 check_absolute_expr (ip
, &imm_expr
);
8126 if ((unsigned long) imm_expr
.X_add_number
> 31)
8127 as_warn (_("Improper shift amount (%lu)"),
8128 (unsigned long) imm_expr
.X_add_number
);
8129 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8130 imm_expr
.X_op
= O_absent
;
8134 case '>': /* shift amount minus 32 */
8135 my_getExpression (&imm_expr
, s
);
8136 check_absolute_expr (ip
, &imm_expr
);
8137 if ((unsigned long) imm_expr
.X_add_number
< 32
8138 || (unsigned long) imm_expr
.X_add_number
> 63)
8140 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8141 imm_expr
.X_op
= O_absent
;
8145 case 'k': /* cache code */
8146 case 'h': /* prefx code */
8147 my_getExpression (&imm_expr
, s
);
8148 check_absolute_expr (ip
, &imm_expr
);
8149 if ((unsigned long) imm_expr
.X_add_number
> 31)
8150 as_warn (_("Invalid value for `%s' (%lu)"),
8152 (unsigned long) imm_expr
.X_add_number
);
8154 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8156 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8157 imm_expr
.X_op
= O_absent
;
8161 case 'c': /* break code */
8162 my_getExpression (&imm_expr
, s
);
8163 check_absolute_expr (ip
, &imm_expr
);
8164 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8165 as_warn (_("Illegal break code (%lu)"),
8166 (unsigned long) imm_expr
.X_add_number
);
8167 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8168 imm_expr
.X_op
= O_absent
;
8172 case 'q': /* lower break code */
8173 my_getExpression (&imm_expr
, s
);
8174 check_absolute_expr (ip
, &imm_expr
);
8175 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8176 as_warn (_("Illegal lower break code (%lu)"),
8177 (unsigned long) imm_expr
.X_add_number
);
8178 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8179 imm_expr
.X_op
= O_absent
;
8183 case 'B': /* 20-bit syscall/break code. */
8184 my_getExpression (&imm_expr
, s
);
8185 check_absolute_expr (ip
, &imm_expr
);
8186 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8187 as_warn (_("Illegal 20-bit code (%lu)"),
8188 (unsigned long) imm_expr
.X_add_number
);
8189 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8190 imm_expr
.X_op
= O_absent
;
8194 case 'C': /* Coprocessor code */
8195 my_getExpression (&imm_expr
, s
);
8196 check_absolute_expr (ip
, &imm_expr
);
8197 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8199 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8200 (unsigned long) imm_expr
.X_add_number
);
8201 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8203 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8204 imm_expr
.X_op
= O_absent
;
8208 case 'J': /* 19-bit wait code. */
8209 my_getExpression (&imm_expr
, s
);
8210 check_absolute_expr (ip
, &imm_expr
);
8211 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8212 as_warn (_("Illegal 19-bit code (%lu)"),
8213 (unsigned long) imm_expr
.X_add_number
);
8214 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8215 imm_expr
.X_op
= O_absent
;
8219 case 'P': /* Performance register */
8220 my_getExpression (&imm_expr
, s
);
8221 check_absolute_expr (ip
, &imm_expr
);
8222 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8223 as_warn (_("Invalid performance register (%lu)"),
8224 (unsigned long) imm_expr
.X_add_number
);
8225 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8226 imm_expr
.X_op
= O_absent
;
8230 case 'b': /* base register */
8231 case 'd': /* destination register */
8232 case 's': /* source register */
8233 case 't': /* target register */
8234 case 'r': /* both target and source */
8235 case 'v': /* both dest and source */
8236 case 'w': /* both dest and target */
8237 case 'E': /* coprocessor target register */
8238 case 'G': /* coprocessor destination register */
8239 case 'K': /* 'rdhwr' destination register */
8240 case 'x': /* ignore register name */
8241 case 'z': /* must be zero register */
8242 case 'U': /* destination register (clo/clz). */
8257 while (ISDIGIT (*s
));
8259 as_bad (_("Invalid register number (%d)"), regno
);
8261 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8265 if (s
[1] == 'r' && s
[2] == 'a')
8270 else if (s
[1] == 'f' && s
[2] == 'p')
8275 else if (s
[1] == 's' && s
[2] == 'p')
8280 else if (s
[1] == 'g' && s
[2] == 'p')
8285 else if (s
[1] == 'a' && s
[2] == 't')
8290 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8295 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8300 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8305 else if (itbl_have_entries
)
8310 p
= s
+ 1; /* advance past '$' */
8311 n
= itbl_get_field (&p
); /* n is name */
8313 /* See if this is a register defined in an
8315 if (itbl_get_reg_val (n
, &r
))
8317 /* Get_field advances to the start of
8318 the next field, so we need to back
8319 rack to the end of the last field. */
8323 s
= strchr (s
, '\0');
8337 as_warn (_("Used $at without \".set noat\""));
8343 if (c
== 'r' || c
== 'v' || c
== 'w')
8350 /* 'z' only matches $0. */
8351 if (c
== 'z' && regno
!= 0)
8354 /* Now that we have assembled one operand, we use the args string
8355 * to figure out where it goes in the instruction. */
8362 INSERT_OPERAND (RS
, *ip
, regno
);
8367 INSERT_OPERAND (RD
, *ip
, regno
);
8370 INSERT_OPERAND (RD
, *ip
, regno
);
8371 INSERT_OPERAND (RT
, *ip
, regno
);
8376 INSERT_OPERAND (RT
, *ip
, regno
);
8379 /* This case exists because on the r3000 trunc
8380 expands into a macro which requires a gp
8381 register. On the r6000 or r4000 it is
8382 assembled into a single instruction which
8383 ignores the register. Thus the insn version
8384 is MIPS_ISA2 and uses 'x', and the macro
8385 version is MIPS_ISA1 and uses 't'. */
8388 /* This case is for the div instruction, which
8389 acts differently if the destination argument
8390 is $0. This only matches $0, and is checked
8391 outside the switch. */
8394 /* Itbl operand; not yet implemented. FIXME ?? */
8396 /* What about all other operands like 'i', which
8397 can be specified in the opcode table? */
8407 INSERT_OPERAND (RS
, *ip
, lastregno
);
8410 INSERT_OPERAND (RT
, *ip
, lastregno
);
8415 case 'O': /* MDMX alignment immediate constant. */
8416 my_getExpression (&imm_expr
, s
);
8417 check_absolute_expr (ip
, &imm_expr
);
8418 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8419 as_warn ("Improper align amount (%ld), using low bits",
8420 (long) imm_expr
.X_add_number
);
8421 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8422 imm_expr
.X_op
= O_absent
;
8426 case 'Q': /* MDMX vector, element sel, or const. */
8429 /* MDMX Immediate. */
8430 my_getExpression (&imm_expr
, s
);
8431 check_absolute_expr (ip
, &imm_expr
);
8432 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8433 as_warn (_("Invalid MDMX Immediate (%ld)"),
8434 (long) imm_expr
.X_add_number
);
8435 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8436 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8437 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8439 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8440 imm_expr
.X_op
= O_absent
;
8444 /* Not MDMX Immediate. Fall through. */
8445 case 'X': /* MDMX destination register. */
8446 case 'Y': /* MDMX source register. */
8447 case 'Z': /* MDMX target register. */
8449 case 'D': /* floating point destination register */
8450 case 'S': /* floating point source register */
8451 case 'T': /* floating point target register */
8452 case 'R': /* floating point source register */
8456 /* Accept $fN for FP and MDMX register numbers, and in
8457 addition accept $vN for MDMX register numbers. */
8458 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8459 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8470 while (ISDIGIT (*s
));
8473 as_bad (_("Invalid float register number (%d)"), regno
);
8475 if ((regno
& 1) != 0
8477 && ! (strcmp (str
, "mtc1") == 0
8478 || strcmp (str
, "mfc1") == 0
8479 || strcmp (str
, "lwc1") == 0
8480 || strcmp (str
, "swc1") == 0
8481 || strcmp (str
, "l.s") == 0
8482 || strcmp (str
, "s.s") == 0))
8483 as_warn (_("Float register should be even, was %d"),
8491 if (c
== 'V' || c
== 'W')
8502 INSERT_OPERAND (FD
, *ip
, regno
);
8507 INSERT_OPERAND (FS
, *ip
, regno
);
8510 /* This is like 'Z', but also needs to fix the MDMX
8511 vector/scalar select bits. Note that the
8512 scalar immediate case is handled above. */
8515 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8516 int max_el
= (is_qh
? 3 : 7);
8518 my_getExpression(&imm_expr
, s
);
8519 check_absolute_expr (ip
, &imm_expr
);
8521 if (imm_expr
.X_add_number
> max_el
)
8522 as_bad(_("Bad element selector %ld"),
8523 (long) imm_expr
.X_add_number
);
8524 imm_expr
.X_add_number
&= max_el
;
8525 ip
->insn_opcode
|= (imm_expr
.X_add_number
8528 imm_expr
.X_op
= O_absent
;
8530 as_warn(_("Expecting ']' found '%s'"), s
);
8536 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8537 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8540 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8547 INSERT_OPERAND (FT
, *ip
, regno
);
8550 INSERT_OPERAND (FR
, *ip
, regno
);
8560 INSERT_OPERAND (FS
, *ip
, lastregno
);
8563 INSERT_OPERAND (FT
, *ip
, lastregno
);
8569 my_getExpression (&imm_expr
, s
);
8570 if (imm_expr
.X_op
!= O_big
8571 && imm_expr
.X_op
!= O_constant
)
8572 insn_error
= _("absolute expression required");
8573 normalize_constant_expr (&imm_expr
);
8578 my_getExpression (&offset_expr
, s
);
8579 normalize_address_expr (&offset_expr
);
8580 *imm_reloc
= BFD_RELOC_32
;
8593 unsigned char temp
[8];
8595 unsigned int length
;
8600 /* These only appear as the last operand in an
8601 instruction, and every instruction that accepts
8602 them in any variant accepts them in all variants.
8603 This means we don't have to worry about backing out
8604 any changes if the instruction does not match.
8606 The difference between them is the size of the
8607 floating point constant and where it goes. For 'F'
8608 and 'L' the constant is 64 bits; for 'f' and 'l' it
8609 is 32 bits. Where the constant is placed is based
8610 on how the MIPS assembler does things:
8613 f -- immediate value
8616 The .lit4 and .lit8 sections are only used if
8617 permitted by the -G argument.
8619 The code below needs to know whether the target register
8620 is 32 or 64 bits wide. It relies on the fact 'f' and
8621 'F' are used with GPR-based instructions and 'l' and
8622 'L' are used with FPR-based instructions. */
8624 f64
= *args
== 'F' || *args
== 'L';
8625 using_gprs
= *args
== 'F' || *args
== 'f';
8627 save_in
= input_line_pointer
;
8628 input_line_pointer
= s
;
8629 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8631 s
= input_line_pointer
;
8632 input_line_pointer
= save_in
;
8633 if (err
!= NULL
&& *err
!= '\0')
8635 as_bad (_("Bad floating point constant: %s"), err
);
8636 memset (temp
, '\0', sizeof temp
);
8637 length
= f64
? 8 : 4;
8640 assert (length
== (unsigned) (f64
? 8 : 4));
8644 && (g_switch_value
< 4
8645 || (temp
[0] == 0 && temp
[1] == 0)
8646 || (temp
[2] == 0 && temp
[3] == 0))))
8648 imm_expr
.X_op
= O_constant
;
8649 if (! target_big_endian
)
8650 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8652 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8655 && ! mips_disable_float_construction
8656 /* Constants can only be constructed in GPRs and
8657 copied to FPRs if the GPRs are at least as wide
8658 as the FPRs. Force the constant into memory if
8659 we are using 64-bit FPRs but the GPRs are only
8662 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8663 && ((temp
[0] == 0 && temp
[1] == 0)
8664 || (temp
[2] == 0 && temp
[3] == 0))
8665 && ((temp
[4] == 0 && temp
[5] == 0)
8666 || (temp
[6] == 0 && temp
[7] == 0)))
8668 /* The value is simple enough to load with a couple of
8669 instructions. If using 32-bit registers, set
8670 imm_expr to the high order 32 bits and offset_expr to
8671 the low order 32 bits. Otherwise, set imm_expr to
8672 the entire 64 bit constant. */
8673 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8675 imm_expr
.X_op
= O_constant
;
8676 offset_expr
.X_op
= O_constant
;
8677 if (! target_big_endian
)
8679 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8680 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8684 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8685 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8687 if (offset_expr
.X_add_number
== 0)
8688 offset_expr
.X_op
= O_absent
;
8690 else if (sizeof (imm_expr
.X_add_number
) > 4)
8692 imm_expr
.X_op
= O_constant
;
8693 if (! target_big_endian
)
8694 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8696 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8700 imm_expr
.X_op
= O_big
;
8701 imm_expr
.X_add_number
= 4;
8702 if (! target_big_endian
)
8704 generic_bignum
[0] = bfd_getl16 (temp
);
8705 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8706 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8707 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8711 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8712 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8713 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8714 generic_bignum
[3] = bfd_getb16 (temp
);
8720 const char *newname
;
8723 /* Switch to the right section. */
8725 subseg
= now_subseg
;
8728 default: /* unused default case avoids warnings. */
8730 newname
= RDATA_SECTION_NAME
;
8731 if (g_switch_value
>= 8)
8735 newname
= RDATA_SECTION_NAME
;
8738 assert (g_switch_value
>= 4);
8742 new_seg
= subseg_new (newname
, (subsegT
) 0);
8743 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8744 bfd_set_section_flags (stdoutput
, new_seg
,
8749 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8750 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8751 && strcmp (TARGET_OS
, "elf") != 0)
8752 record_alignment (new_seg
, 4);
8754 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8756 as_bad (_("Can't use floating point insn in this section"));
8758 /* Set the argument to the current address in the
8760 offset_expr
.X_op
= O_symbol
;
8761 offset_expr
.X_add_symbol
=
8762 symbol_new ("L0\001", now_seg
,
8763 (valueT
) frag_now_fix (), frag_now
);
8764 offset_expr
.X_add_number
= 0;
8766 /* Put the floating point number into the section. */
8767 p
= frag_more ((int) length
);
8768 memcpy (p
, temp
, length
);
8770 /* Switch back to the original section. */
8771 subseg_set (seg
, subseg
);
8776 case 'i': /* 16 bit unsigned immediate */
8777 case 'j': /* 16 bit signed immediate */
8778 *imm_reloc
= BFD_RELOC_LO16
;
8779 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8782 offsetT minval
, maxval
;
8784 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8785 && strcmp (insn
->name
, insn
[1].name
) == 0);
8787 /* If the expression was written as an unsigned number,
8788 only treat it as signed if there are no more
8792 && sizeof (imm_expr
.X_add_number
) <= 4
8793 && imm_expr
.X_op
== O_constant
8794 && imm_expr
.X_add_number
< 0
8795 && imm_expr
.X_unsigned
8799 /* For compatibility with older assemblers, we accept
8800 0x8000-0xffff as signed 16-bit numbers when only
8801 signed numbers are allowed. */
8803 minval
= 0, maxval
= 0xffff;
8805 minval
= -0x8000, maxval
= 0x7fff;
8807 minval
= -0x8000, maxval
= 0xffff;
8809 if (imm_expr
.X_op
!= O_constant
8810 || imm_expr
.X_add_number
< minval
8811 || imm_expr
.X_add_number
> maxval
)
8815 if (imm_expr
.X_op
== O_constant
8816 || imm_expr
.X_op
== O_big
)
8817 as_bad (_("expression out of range"));
8823 case 'o': /* 16 bit offset */
8824 /* Check whether there is only a single bracketed expression
8825 left. If so, it must be the base register and the
8826 constant must be zero. */
8827 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8829 offset_expr
.X_op
= O_constant
;
8830 offset_expr
.X_add_number
= 0;
8834 /* If this value won't fit into a 16 bit offset, then go
8835 find a macro that will generate the 32 bit offset
8837 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8838 && (offset_expr
.X_op
!= O_constant
8839 || offset_expr
.X_add_number
>= 0x8000
8840 || offset_expr
.X_add_number
< -0x8000))
8846 case 'p': /* pc relative offset */
8847 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8848 my_getExpression (&offset_expr
, s
);
8852 case 'u': /* upper 16 bits */
8853 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8854 && imm_expr
.X_op
== O_constant
8855 && (imm_expr
.X_add_number
< 0
8856 || imm_expr
.X_add_number
>= 0x10000))
8857 as_bad (_("lui expression not in range 0..65535"));
8861 case 'a': /* 26 bit address */
8862 my_getExpression (&offset_expr
, s
);
8864 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8867 case 'N': /* 3 bit branch condition code */
8868 case 'M': /* 3 bit compare condition code */
8869 if (strncmp (s
, "$fcc", 4) != 0)
8879 while (ISDIGIT (*s
));
8881 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8882 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8883 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8884 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8885 && (regno
& 1) != 0)
8886 as_warn(_("Condition code register should be even for %s, was %d"),
8888 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8889 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8890 && (regno
& 3) != 0)
8891 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8894 INSERT_OPERAND (BCC
, *ip
, regno
);
8896 INSERT_OPERAND (CCC
, *ip
, regno
);
8900 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8911 while (ISDIGIT (*s
));
8914 c
= 8; /* Invalid sel value. */
8917 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8918 ip
->insn_opcode
|= c
;
8922 /* Must be at least one digit. */
8923 my_getExpression (&imm_expr
, s
);
8924 check_absolute_expr (ip
, &imm_expr
);
8926 if ((unsigned long) imm_expr
.X_add_number
8927 > (unsigned long) OP_MASK_VECBYTE
)
8929 as_bad (_("bad byte vector index (%ld)"),
8930 (long) imm_expr
.X_add_number
);
8931 imm_expr
.X_add_number
= 0;
8934 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8935 imm_expr
.X_op
= O_absent
;
8940 my_getExpression (&imm_expr
, s
);
8941 check_absolute_expr (ip
, &imm_expr
);
8943 if ((unsigned long) imm_expr
.X_add_number
8944 > (unsigned long) OP_MASK_VECALIGN
)
8946 as_bad (_("bad byte vector index (%ld)"),
8947 (long) imm_expr
.X_add_number
);
8948 imm_expr
.X_add_number
= 0;
8951 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8952 imm_expr
.X_op
= O_absent
;
8957 as_bad (_("bad char = '%c'\n"), *args
);
8962 /* Args don't match. */
8963 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8964 !strcmp (insn
->name
, insn
[1].name
))
8968 insn_error
= _("illegal operands");
8973 insn_error
= _("illegal operands");
8978 /* This routine assembles an instruction into its binary format when
8979 assembling for the mips16. As a side effect, it sets one of the
8980 global variables imm_reloc or offset_reloc to the type of
8981 relocation to do if one of the operands is an address expression.
8982 It also sets mips16_small and mips16_ext if the user explicitly
8983 requested a small or extended instruction. */
8986 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8990 struct mips_opcode
*insn
;
8993 unsigned int lastregno
= 0;
8999 mips16_small
= FALSE
;
9002 for (s
= str
; ISLOWER (*s
); ++s
)
9014 if (s
[1] == 't' && s
[2] == ' ')
9017 mips16_small
= TRUE
;
9021 else if (s
[1] == 'e' && s
[2] == ' ')
9030 insn_error
= _("unknown opcode");
9034 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9035 mips16_small
= TRUE
;
9037 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9039 insn_error
= _("unrecognized opcode");
9046 assert (strcmp (insn
->name
, str
) == 0);
9048 create_insn (ip
, insn
);
9049 imm_expr
.X_op
= O_absent
;
9050 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9051 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9052 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9053 imm2_expr
.X_op
= O_absent
;
9054 offset_expr
.X_op
= O_absent
;
9055 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9056 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9057 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9058 for (args
= insn
->args
; 1; ++args
)
9065 /* In this switch statement we call break if we did not find
9066 a match, continue if we did find a match, or return if we
9075 /* Stuff the immediate value in now, if we can. */
9076 if (imm_expr
.X_op
== O_constant
9077 && *imm_reloc
> BFD_RELOC_UNUSED
9078 && insn
->pinfo
!= INSN_MACRO
)
9082 switch (*offset_reloc
)
9084 case BFD_RELOC_MIPS16_HI16_S
:
9085 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9088 case BFD_RELOC_MIPS16_HI16
:
9089 tmp
= imm_expr
.X_add_number
>> 16;
9092 case BFD_RELOC_MIPS16_LO16
:
9093 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9097 case BFD_RELOC_UNUSED
:
9098 tmp
= imm_expr
.X_add_number
;
9104 *offset_reloc
= BFD_RELOC_UNUSED
;
9106 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9107 tmp
, TRUE
, mips16_small
,
9108 mips16_ext
, &ip
->insn_opcode
,
9109 &ip
->use_extend
, &ip
->extend
);
9110 imm_expr
.X_op
= O_absent
;
9111 *imm_reloc
= BFD_RELOC_UNUSED
;
9125 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9128 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9144 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9146 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9173 while (ISDIGIT (*s
));
9176 as_bad (_("invalid register number (%d)"), regno
);
9182 if (s
[1] == 'r' && s
[2] == 'a')
9187 else if (s
[1] == 'f' && s
[2] == 'p')
9192 else if (s
[1] == 's' && s
[2] == 'p')
9197 else if (s
[1] == 'g' && s
[2] == 'p')
9202 else if (s
[1] == 'a' && s
[2] == 't')
9207 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9212 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9217 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9230 if (c
== 'v' || c
== 'w')
9232 regno
= mips16_to_32_reg_map
[lastregno
];
9246 regno
= mips32_to_16_reg_map
[regno
];
9251 regno
= ILLEGAL_REG
;
9256 regno
= ILLEGAL_REG
;
9261 regno
= ILLEGAL_REG
;
9266 if (regno
== AT
&& ! mips_opts
.noat
)
9267 as_warn (_("used $at without \".set noat\""));
9274 if (regno
== ILLEGAL_REG
)
9281 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9285 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9288 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9291 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9297 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9300 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9301 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9311 if (strncmp (s
, "$pc", 3) == 0)
9328 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9331 if (imm_expr
.X_op
!= O_constant
)
9334 ip
->use_extend
= TRUE
;
9339 /* We need to relax this instruction. */
9340 *offset_reloc
= *imm_reloc
;
9341 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9346 *imm_reloc
= BFD_RELOC_UNUSED
;
9354 my_getExpression (&imm_expr
, s
);
9355 if (imm_expr
.X_op
== O_register
)
9357 /* What we thought was an expression turned out to
9360 if (s
[0] == '(' && args
[1] == '(')
9362 /* It looks like the expression was omitted
9363 before a register indirection, which means
9364 that the expression is implicitly zero. We
9365 still set up imm_expr, so that we handle
9366 explicit extensions correctly. */
9367 imm_expr
.X_op
= O_constant
;
9368 imm_expr
.X_add_number
= 0;
9369 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9376 /* We need to relax this instruction. */
9377 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9386 /* We use offset_reloc rather than imm_reloc for the PC
9387 relative operands. This lets macros with both
9388 immediate and address operands work correctly. */
9389 my_getExpression (&offset_expr
, s
);
9391 if (offset_expr
.X_op
== O_register
)
9394 /* We need to relax this instruction. */
9395 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9399 case '6': /* break code */
9400 my_getExpression (&imm_expr
, s
);
9401 check_absolute_expr (ip
, &imm_expr
);
9402 if ((unsigned long) imm_expr
.X_add_number
> 63)
9403 as_warn (_("Invalid value for `%s' (%lu)"),
9405 (unsigned long) imm_expr
.X_add_number
);
9406 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9407 imm_expr
.X_op
= O_absent
;
9411 case 'a': /* 26 bit address */
9412 my_getExpression (&offset_expr
, s
);
9414 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9415 ip
->insn_opcode
<<= 16;
9418 case 'l': /* register list for entry macro */
9419 case 'L': /* register list for exit macro */
9429 int freg
, reg1
, reg2
;
9431 while (*s
== ' ' || *s
== ',')
9435 as_bad (_("can't parse register list"));
9447 while (ISDIGIT (*s
))
9469 as_bad (_("invalid register list"));
9474 while (ISDIGIT (*s
))
9481 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9486 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9491 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9492 mask
|= (reg2
- 3) << 3;
9493 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9494 mask
|= (reg2
- 15) << 1;
9495 else if (reg1
== RA
&& reg2
== RA
)
9499 as_bad (_("invalid register list"));
9503 /* The mask is filled in in the opcode table for the
9504 benefit of the disassembler. We remove it before
9505 applying the actual mask. */
9506 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9507 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9511 case 'e': /* extend code */
9512 my_getExpression (&imm_expr
, s
);
9513 check_absolute_expr (ip
, &imm_expr
);
9514 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9516 as_warn (_("Invalid value for `%s' (%lu)"),
9518 (unsigned long) imm_expr
.X_add_number
);
9519 imm_expr
.X_add_number
&= 0x7ff;
9521 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9522 imm_expr
.X_op
= O_absent
;
9532 /* Args don't match. */
9533 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9534 strcmp (insn
->name
, insn
[1].name
) == 0)
9541 insn_error
= _("illegal operands");
9547 /* This structure holds information we know about a mips16 immediate
9550 struct mips16_immed_operand
9552 /* The type code used in the argument string in the opcode table. */
9554 /* The number of bits in the short form of the opcode. */
9556 /* The number of bits in the extended form of the opcode. */
9558 /* The amount by which the short form is shifted when it is used;
9559 for example, the sw instruction has a shift count of 2. */
9561 /* The amount by which the short form is shifted when it is stored
9562 into the instruction code. */
9564 /* Non-zero if the short form is unsigned. */
9566 /* Non-zero if the extended form is unsigned. */
9568 /* Non-zero if the value is PC relative. */
9572 /* The mips16 immediate operand types. */
9574 static const struct mips16_immed_operand mips16_immed_operands
[] =
9576 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9577 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9578 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9579 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9580 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9581 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9582 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9583 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9584 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9585 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9586 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9587 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9588 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9589 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9590 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9591 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9592 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9593 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9594 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9595 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9596 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9599 #define MIPS16_NUM_IMMED \
9600 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9602 /* Handle a mips16 instruction with an immediate value. This or's the
9603 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9604 whether an extended value is needed; if one is needed, it sets
9605 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9606 If SMALL is true, an unextended opcode was explicitly requested.
9607 If EXT is true, an extended opcode was explicitly requested. If
9608 WARN is true, warn if EXT does not match reality. */
9611 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9612 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9613 unsigned long *insn
, bfd_boolean
*use_extend
,
9614 unsigned short *extend
)
9616 register const struct mips16_immed_operand
*op
;
9617 int mintiny
, maxtiny
;
9618 bfd_boolean needext
;
9620 op
= mips16_immed_operands
;
9621 while (op
->type
!= type
)
9624 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9629 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9632 maxtiny
= 1 << op
->nbits
;
9637 maxtiny
= (1 << op
->nbits
) - 1;
9642 mintiny
= - (1 << (op
->nbits
- 1));
9643 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9646 /* Branch offsets have an implicit 0 in the lowest bit. */
9647 if (type
== 'p' || type
== 'q')
9650 if ((val
& ((1 << op
->shift
) - 1)) != 0
9651 || val
< (mintiny
<< op
->shift
)
9652 || val
> (maxtiny
<< op
->shift
))
9657 if (warn
&& ext
&& ! needext
)
9658 as_warn_where (file
, line
,
9659 _("extended operand requested but not required"));
9660 if (small
&& needext
)
9661 as_bad_where (file
, line
, _("invalid unextended operand value"));
9663 if (small
|| (! ext
&& ! needext
))
9667 *use_extend
= FALSE
;
9668 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9669 insnval
<<= op
->op_shift
;
9674 long minext
, maxext
;
9680 maxext
= (1 << op
->extbits
) - 1;
9684 minext
= - (1 << (op
->extbits
- 1));
9685 maxext
= (1 << (op
->extbits
- 1)) - 1;
9687 if (val
< minext
|| val
> maxext
)
9688 as_bad_where (file
, line
,
9689 _("operand value out of range for instruction"));
9692 if (op
->extbits
== 16)
9694 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9697 else if (op
->extbits
== 15)
9699 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9704 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9708 *extend
= (unsigned short) extval
;
9713 struct percent_op_match
9716 bfd_reloc_code_real_type reloc
;
9719 static const struct percent_op_match mips_percent_op
[] =
9721 {"%lo", BFD_RELOC_LO16
},
9723 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9724 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9725 {"%call16", BFD_RELOC_MIPS_CALL16
},
9726 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9727 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9728 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9729 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9730 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9731 {"%got", BFD_RELOC_MIPS_GOT16
},
9732 {"%gp_rel", BFD_RELOC_GPREL16
},
9733 {"%half", BFD_RELOC_16
},
9734 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9735 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9736 {"%neg", BFD_RELOC_MIPS_SUB
},
9737 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9738 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9739 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9740 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9741 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9742 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9743 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9745 {"%hi", BFD_RELOC_HI16_S
}
9748 static const struct percent_op_match mips16_percent_op
[] =
9750 {"%lo", BFD_RELOC_MIPS16_LO16
},
9751 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9752 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9756 /* Return true if *STR points to a relocation operator. When returning true,
9757 move *STR over the operator and store its relocation code in *RELOC.
9758 Leave both *STR and *RELOC alone when returning false. */
9761 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9763 const struct percent_op_match
*percent_op
;
9766 if (mips_opts
.mips16
)
9768 percent_op
= mips16_percent_op
;
9769 limit
= ARRAY_SIZE (mips16_percent_op
);
9773 percent_op
= mips_percent_op
;
9774 limit
= ARRAY_SIZE (mips_percent_op
);
9777 for (i
= 0; i
< limit
; i
++)
9778 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9780 int len
= strlen (percent_op
[i
].str
);
9782 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9785 *str
+= strlen (percent_op
[i
].str
);
9786 *reloc
= percent_op
[i
].reloc
;
9788 /* Check whether the output BFD supports this relocation.
9789 If not, issue an error and fall back on something safe. */
9790 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9792 as_bad ("relocation %s isn't supported by the current ABI",
9794 *reloc
= BFD_RELOC_UNUSED
;
9802 /* Parse string STR as a 16-bit relocatable operand. Store the
9803 expression in *EP and the relocations in the array starting
9804 at RELOC. Return the number of relocation operators used.
9806 On exit, EXPR_END points to the first character after the expression. */
9809 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9812 bfd_reloc_code_real_type reversed_reloc
[3];
9813 size_t reloc_index
, i
;
9814 int crux_depth
, str_depth
;
9817 /* Search for the start of the main expression, recoding relocations
9818 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9819 of the main expression and with CRUX_DEPTH containing the number
9820 of open brackets at that point. */
9827 crux_depth
= str_depth
;
9829 /* Skip over whitespace and brackets, keeping count of the number
9831 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9836 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9837 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9839 my_getExpression (ep
, crux
);
9842 /* Match every open bracket. */
9843 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9848 as_bad ("unclosed '('");
9852 if (reloc_index
!= 0)
9854 prev_reloc_op_frag
= frag_now
;
9855 for (i
= 0; i
< reloc_index
; i
++)
9856 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9863 my_getExpression (expressionS
*ep
, char *str
)
9868 save_in
= input_line_pointer
;
9869 input_line_pointer
= str
;
9871 expr_end
= input_line_pointer
;
9872 input_line_pointer
= save_in
;
9874 /* If we are in mips16 mode, and this is an expression based on `.',
9875 then we bump the value of the symbol by 1 since that is how other
9876 text symbols are handled. We don't bother to handle complex
9877 expressions, just `.' plus or minus a constant. */
9878 if (mips_opts
.mips16
9879 && ep
->X_op
== O_symbol
9880 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9881 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9882 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9883 && symbol_constant_p (ep
->X_add_symbol
)
9884 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9885 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9888 /* Turn a string in input_line_pointer into a floating point constant
9889 of type TYPE, and store the appropriate bytes in *LITP. The number
9890 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9891 returned, or NULL on OK. */
9894 md_atof (int type
, char *litP
, int *sizeP
)
9897 LITTLENUM_TYPE words
[4];
9913 return _("bad call to md_atof");
9916 t
= atof_ieee (input_line_pointer
, type
, words
);
9918 input_line_pointer
= t
;
9922 if (! target_big_endian
)
9924 for (i
= prec
- 1; i
>= 0; i
--)
9926 md_number_to_chars (litP
, words
[i
], 2);
9932 for (i
= 0; i
< prec
; i
++)
9934 md_number_to_chars (litP
, words
[i
], 2);
9943 md_number_to_chars (char *buf
, valueT val
, int n
)
9945 if (target_big_endian
)
9946 number_to_chars_bigendian (buf
, val
, n
);
9948 number_to_chars_littleendian (buf
, val
, n
);
9952 static int support_64bit_objects(void)
9954 const char **list
, **l
;
9957 list
= bfd_target_list ();
9958 for (l
= list
; *l
!= NULL
; l
++)
9960 /* This is traditional mips */
9961 if (strcmp (*l
, "elf64-tradbigmips") == 0
9962 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9964 if (strcmp (*l
, "elf64-bigmips") == 0
9965 || strcmp (*l
, "elf64-littlemips") == 0)
9972 #endif /* OBJ_ELF */
9974 const char *md_shortopts
= "O::g::G:";
9976 struct option md_longopts
[] =
9978 /* Options which specify architecture. */
9979 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9980 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9981 {"march", required_argument
, NULL
, OPTION_MARCH
},
9982 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9983 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9984 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9985 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9986 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9987 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9988 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9989 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9990 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9991 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9992 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9993 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9994 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9995 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9996 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9997 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9998 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9999 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10000 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10001 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10002 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10004 /* Options which specify Application Specific Extensions (ASEs). */
10005 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10006 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10007 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10008 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10009 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10010 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10011 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10012 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10013 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10014 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10015 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10016 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10017 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10019 /* Old-style architecture options. Don't add more of these. */
10020 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10021 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10022 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10023 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10024 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10025 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10026 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10027 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10028 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10029 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10030 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10031 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10032 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10033 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10034 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10035 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10036 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10038 /* Options which enable bug fixes. */
10039 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10040 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10041 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10042 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10043 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10044 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10045 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10046 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10047 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10048 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10049 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10050 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10051 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10052 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10054 /* Miscellaneous options. */
10055 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10056 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10057 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10058 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10059 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10060 {"break", no_argument
, NULL
, OPTION_BREAK
},
10061 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10062 #define OPTION_EB (OPTION_MISC_BASE + 2)
10063 {"EB", no_argument
, NULL
, OPTION_EB
},
10064 #define OPTION_EL (OPTION_MISC_BASE + 3)
10065 {"EL", no_argument
, NULL
, OPTION_EL
},
10066 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10067 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10068 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10069 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10070 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10071 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10072 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10073 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10074 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10075 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10076 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10077 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10078 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10079 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10080 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10081 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10082 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10083 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10084 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10085 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10086 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10087 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10088 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10089 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10091 /* ELF-specific options. */
10093 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10094 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10095 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10096 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10097 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10098 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10099 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10100 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10101 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10102 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10103 #define OPTION_32 (OPTION_ELF_BASE + 4)
10104 {"32", no_argument
, NULL
, OPTION_32
},
10105 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10106 {"n32", no_argument
, NULL
, OPTION_N32
},
10107 #define OPTION_64 (OPTION_ELF_BASE + 6)
10108 {"64", no_argument
, NULL
, OPTION_64
},
10109 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10110 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10111 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10112 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10113 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10114 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10115 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10116 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10117 #endif /* OBJ_ELF */
10119 {NULL
, no_argument
, NULL
, 0}
10121 size_t md_longopts_size
= sizeof (md_longopts
);
10123 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10124 NEW_VALUE. Warn if another value was already specified. Note:
10125 we have to defer parsing the -march and -mtune arguments in order
10126 to handle 'from-abi' correctly, since the ABI might be specified
10127 in a later argument. */
10130 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10132 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10133 as_warn (_("A different %s was already specified, is now %s"),
10134 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10137 *string_ptr
= new_value
;
10141 md_parse_option (int c
, char *arg
)
10145 case OPTION_CONSTRUCT_FLOATS
:
10146 mips_disable_float_construction
= 0;
10149 case OPTION_NO_CONSTRUCT_FLOATS
:
10150 mips_disable_float_construction
= 1;
10162 target_big_endian
= 1;
10166 target_big_endian
= 0;
10170 if (arg
&& arg
[1] == '0')
10180 mips_debug
= atoi (arg
);
10181 /* When the MIPS assembler sees -g or -g2, it does not do
10182 optimizations which limit full symbolic debugging. We take
10183 that to be equivalent to -O0. */
10184 if (mips_debug
== 2)
10189 file_mips_isa
= ISA_MIPS1
;
10193 file_mips_isa
= ISA_MIPS2
;
10197 file_mips_isa
= ISA_MIPS3
;
10201 file_mips_isa
= ISA_MIPS4
;
10205 file_mips_isa
= ISA_MIPS5
;
10208 case OPTION_MIPS32
:
10209 file_mips_isa
= ISA_MIPS32
;
10212 case OPTION_MIPS32R2
:
10213 file_mips_isa
= ISA_MIPS32R2
;
10216 case OPTION_MIPS64R2
:
10217 file_mips_isa
= ISA_MIPS64R2
;
10220 case OPTION_MIPS64
:
10221 file_mips_isa
= ISA_MIPS64
;
10225 mips_set_option_string (&mips_tune_string
, arg
);
10229 mips_set_option_string (&mips_arch_string
, arg
);
10233 mips_set_option_string (&mips_arch_string
, "4650");
10234 mips_set_option_string (&mips_tune_string
, "4650");
10237 case OPTION_NO_M4650
:
10241 mips_set_option_string (&mips_arch_string
, "4010");
10242 mips_set_option_string (&mips_tune_string
, "4010");
10245 case OPTION_NO_M4010
:
10249 mips_set_option_string (&mips_arch_string
, "4100");
10250 mips_set_option_string (&mips_tune_string
, "4100");
10253 case OPTION_NO_M4100
:
10257 mips_set_option_string (&mips_arch_string
, "3900");
10258 mips_set_option_string (&mips_tune_string
, "3900");
10261 case OPTION_NO_M3900
:
10265 mips_opts
.ase_mdmx
= 1;
10268 case OPTION_NO_MDMX
:
10269 mips_opts
.ase_mdmx
= 0;
10272 case OPTION_MIPS16
:
10273 mips_opts
.mips16
= 1;
10274 mips_no_prev_insn ();
10277 case OPTION_NO_MIPS16
:
10278 mips_opts
.mips16
= 0;
10279 mips_no_prev_insn ();
10282 case OPTION_MIPS3D
:
10283 mips_opts
.ase_mips3d
= 1;
10286 case OPTION_NO_MIPS3D
:
10287 mips_opts
.ase_mips3d
= 0;
10290 case OPTION_FIX_VR4120
:
10291 mips_fix_vr4120
= 1;
10294 case OPTION_NO_FIX_VR4120
:
10295 mips_fix_vr4120
= 0;
10298 case OPTION_FIX_VR4130
:
10299 mips_fix_vr4130
= 1;
10302 case OPTION_NO_FIX_VR4130
:
10303 mips_fix_vr4130
= 0;
10306 case OPTION_RELAX_BRANCH
:
10307 mips_relax_branch
= 1;
10310 case OPTION_NO_RELAX_BRANCH
:
10311 mips_relax_branch
= 0;
10314 case OPTION_MSHARED
:
10315 mips_in_shared
= TRUE
;
10318 case OPTION_MNO_SHARED
:
10319 mips_in_shared
= FALSE
;
10322 case OPTION_MSYM32
:
10323 mips_opts
.sym32
= TRUE
;
10326 case OPTION_MNO_SYM32
:
10327 mips_opts
.sym32
= FALSE
;
10331 /* When generating ELF code, we permit -KPIC and -call_shared to
10332 select SVR4_PIC, and -non_shared to select no PIC. This is
10333 intended to be compatible with Irix 5. */
10334 case OPTION_CALL_SHARED
:
10335 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10337 as_bad (_("-call_shared is supported only for ELF format"));
10340 mips_pic
= SVR4_PIC
;
10341 mips_abicalls
= TRUE
;
10342 if (g_switch_seen
&& g_switch_value
!= 0)
10344 as_bad (_("-G may not be used with SVR4 PIC code"));
10347 g_switch_value
= 0;
10350 case OPTION_NON_SHARED
:
10351 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10353 as_bad (_("-non_shared is supported only for ELF format"));
10357 mips_abicalls
= FALSE
;
10360 /* The -xgot option tells the assembler to use 32 offsets when
10361 accessing the got in SVR4_PIC mode. It is for Irix
10366 #endif /* OBJ_ELF */
10369 g_switch_value
= atoi (arg
);
10371 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10373 as_bad (_("-G may not be used with SVR4 PIC code"));
10379 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10382 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10384 as_bad (_("-32 is supported for ELF format only"));
10387 mips_abi
= O32_ABI
;
10391 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10393 as_bad (_("-n32 is supported for ELF format only"));
10396 mips_abi
= N32_ABI
;
10400 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10402 as_bad (_("-64 is supported for ELF format only"));
10405 mips_abi
= N64_ABI
;
10406 if (! support_64bit_objects())
10407 as_fatal (_("No compiled in support for 64 bit object file format"));
10409 #endif /* OBJ_ELF */
10412 file_mips_gp32
= 1;
10416 file_mips_gp32
= 0;
10420 file_mips_fp32
= 1;
10424 file_mips_fp32
= 0;
10429 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10431 as_bad (_("-mabi is supported for ELF format only"));
10434 if (strcmp (arg
, "32") == 0)
10435 mips_abi
= O32_ABI
;
10436 else if (strcmp (arg
, "o64") == 0)
10437 mips_abi
= O64_ABI
;
10438 else if (strcmp (arg
, "n32") == 0)
10439 mips_abi
= N32_ABI
;
10440 else if (strcmp (arg
, "64") == 0)
10442 mips_abi
= N64_ABI
;
10443 if (! support_64bit_objects())
10444 as_fatal (_("No compiled in support for 64 bit object file "
10447 else if (strcmp (arg
, "eabi") == 0)
10448 mips_abi
= EABI_ABI
;
10451 as_fatal (_("invalid abi -mabi=%s"), arg
);
10455 #endif /* OBJ_ELF */
10457 case OPTION_M7000_HILO_FIX
:
10458 mips_7000_hilo_fix
= TRUE
;
10461 case OPTION_MNO_7000_HILO_FIX
:
10462 mips_7000_hilo_fix
= FALSE
;
10466 case OPTION_MDEBUG
:
10467 mips_flag_mdebug
= TRUE
;
10470 case OPTION_NO_MDEBUG
:
10471 mips_flag_mdebug
= FALSE
;
10475 mips_flag_pdr
= TRUE
;
10478 case OPTION_NO_PDR
:
10479 mips_flag_pdr
= FALSE
;
10481 #endif /* OBJ_ELF */
10490 /* Set up globals to generate code for the ISA or processor
10491 described by INFO. */
10494 mips_set_architecture (const struct mips_cpu_info
*info
)
10498 file_mips_arch
= info
->cpu
;
10499 mips_opts
.arch
= info
->cpu
;
10500 mips_opts
.isa
= info
->isa
;
10505 /* Likewise for tuning. */
10508 mips_set_tune (const struct mips_cpu_info
*info
)
10511 mips_tune
= info
->cpu
;
10516 mips_after_parse_args (void)
10518 const struct mips_cpu_info
*arch_info
= 0;
10519 const struct mips_cpu_info
*tune_info
= 0;
10521 /* GP relative stuff not working for PE */
10522 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10524 if (g_switch_seen
&& g_switch_value
!= 0)
10525 as_bad (_("-G not supported in this configuration."));
10526 g_switch_value
= 0;
10529 if (mips_abi
== NO_ABI
)
10530 mips_abi
= MIPS_DEFAULT_ABI
;
10532 /* The following code determines the architecture and register size.
10533 Similar code was added to GCC 3.3 (see override_options() in
10534 config/mips/mips.c). The GAS and GCC code should be kept in sync
10535 as much as possible. */
10537 if (mips_arch_string
!= 0)
10538 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10540 if (file_mips_isa
!= ISA_UNKNOWN
)
10542 /* Handle -mipsN. At this point, file_mips_isa contains the
10543 ISA level specified by -mipsN, while arch_info->isa contains
10544 the -march selection (if any). */
10545 if (arch_info
!= 0)
10547 /* -march takes precedence over -mipsN, since it is more descriptive.
10548 There's no harm in specifying both as long as the ISA levels
10550 if (file_mips_isa
!= arch_info
->isa
)
10551 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10552 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10553 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10556 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10559 if (arch_info
== 0)
10560 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10562 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10563 as_bad ("-march=%s is not compatible with the selected ABI",
10566 mips_set_architecture (arch_info
);
10568 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10569 if (mips_tune_string
!= 0)
10570 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10572 if (tune_info
== 0)
10573 mips_set_tune (arch_info
);
10575 mips_set_tune (tune_info
);
10577 if (file_mips_gp32
>= 0)
10579 /* The user specified the size of the integer registers. Make sure
10580 it agrees with the ABI and ISA. */
10581 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10582 as_bad (_("-mgp64 used with a 32-bit processor"));
10583 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10584 as_bad (_("-mgp32 used with a 64-bit ABI"));
10585 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10586 as_bad (_("-mgp64 used with a 32-bit ABI"));
10590 /* Infer the integer register size from the ABI and processor.
10591 Restrict ourselves to 32-bit registers if that's all the
10592 processor has, or if the ABI cannot handle 64-bit registers. */
10593 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10594 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10597 /* ??? GAS treats single-float processors as though they had 64-bit
10598 float registers (although it complains when double-precision
10599 instructions are used). As things stand, saying they have 32-bit
10600 registers would lead to spurious "register must be even" messages.
10601 So here we assume float registers are always the same size as
10602 integer ones, unless the user says otherwise. */
10603 if (file_mips_fp32
< 0)
10604 file_mips_fp32
= file_mips_gp32
;
10606 /* End of GCC-shared inference code. */
10608 /* This flag is set when we have a 64-bit capable CPU but use only
10609 32-bit wide registers. Note that EABI does not use it. */
10610 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10611 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10612 || mips_abi
== O32_ABI
))
10613 mips_32bitmode
= 1;
10615 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10616 as_bad (_("trap exception not supported at ISA 1"));
10618 /* If the selected architecture includes support for ASEs, enable
10619 generation of code for them. */
10620 if (mips_opts
.mips16
== -1)
10621 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10622 if (mips_opts
.ase_mips3d
== -1)
10623 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10624 if (mips_opts
.ase_mdmx
== -1)
10625 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10627 file_mips_isa
= mips_opts
.isa
;
10628 file_ase_mips16
= mips_opts
.mips16
;
10629 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10630 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10631 mips_opts
.gp32
= file_mips_gp32
;
10632 mips_opts
.fp32
= file_mips_fp32
;
10634 if (mips_flag_mdebug
< 0)
10636 #ifdef OBJ_MAYBE_ECOFF
10637 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10638 mips_flag_mdebug
= 1;
10640 #endif /* OBJ_MAYBE_ECOFF */
10641 mips_flag_mdebug
= 0;
10646 mips_init_after_args (void)
10648 /* initialize opcodes */
10649 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10650 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10654 md_pcrel_from (fixS
*fixP
)
10656 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10657 switch (fixP
->fx_r_type
)
10659 case BFD_RELOC_16_PCREL_S2
:
10660 case BFD_RELOC_MIPS_JMP
:
10661 /* Return the address of the delay slot. */
10668 /* This is called before the symbol table is processed. In order to
10669 work with gcc when using mips-tfile, we must keep all local labels.
10670 However, in other cases, we want to discard them. If we were
10671 called with -g, but we didn't see any debugging information, it may
10672 mean that gcc is smuggling debugging information through to
10673 mips-tfile, in which case we must generate all local labels. */
10676 mips_frob_file_before_adjust (void)
10678 #ifndef NO_ECOFF_DEBUGGING
10679 if (ECOFF_DEBUGGING
10681 && ! ecoff_debugging_seen
)
10682 flag_keep_locals
= 1;
10686 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10687 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10688 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10689 relocation operators.
10691 For our purposes, a %lo() expression matches a %got() or %hi()
10694 (a) it refers to the same symbol; and
10695 (b) the offset applied in the %lo() expression is no lower than
10696 the offset applied in the %got() or %hi().
10698 (b) allows us to cope with code like:
10701 lh $4,%lo(foo+2)($4)
10703 ...which is legal on RELA targets, and has a well-defined behaviour
10704 if the user knows that adding 2 to "foo" will not induce a carry to
10707 When several %lo()s match a particular %got() or %hi(), we use the
10708 following rules to distinguish them:
10710 (1) %lo()s with smaller offsets are a better match than %lo()s with
10713 (2) %lo()s with no matching %got() or %hi() are better than those
10714 that already have a matching %got() or %hi().
10716 (3) later %lo()s are better than earlier %lo()s.
10718 These rules are applied in order.
10720 (1) means, among other things, that %lo()s with identical offsets are
10721 chosen if they exist.
10723 (2) means that we won't associate several high-part relocations with
10724 the same low-part relocation unless there's no alternative. Having
10725 several high parts for the same low part is a GNU extension; this rule
10726 allows careful users to avoid it.
10728 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10729 with the last high-part relocation being at the front of the list.
10730 It therefore makes sense to choose the last matching low-part
10731 relocation, all other things being equal. It's also easier
10732 to code that way. */
10735 mips_frob_file (void)
10737 struct mips_hi_fixup
*l
;
10739 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10741 segment_info_type
*seginfo
;
10742 bfd_boolean matched_lo_p
;
10743 fixS
**hi_pos
, **lo_pos
, **pos
;
10745 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10747 /* If a GOT16 relocation turns out to be against a global symbol,
10748 there isn't supposed to be a matching LO. */
10749 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10750 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10753 /* Check quickly whether the next fixup happens to be a matching %lo. */
10754 if (fixup_has_matching_lo_p (l
->fixp
))
10757 seginfo
= seg_info (l
->seg
);
10759 /* Set HI_POS to the position of this relocation in the chain.
10760 Set LO_POS to the position of the chosen low-part relocation.
10761 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10762 relocation that matches an immediately-preceding high-part
10766 matched_lo_p
= FALSE
;
10767 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10769 if (*pos
== l
->fixp
)
10772 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
10773 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
10774 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10775 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10777 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10779 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10782 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10783 && fixup_has_matching_lo_p (*pos
));
10786 /* If we found a match, remove the high-part relocation from its
10787 current position and insert it before the low-part relocation.
10788 Make the offsets match so that fixup_has_matching_lo_p()
10791 We don't warn about unmatched high-part relocations since some
10792 versions of gcc have been known to emit dead "lui ...%hi(...)"
10794 if (lo_pos
!= NULL
)
10796 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10797 if (l
->fixp
->fx_next
!= *lo_pos
)
10799 *hi_pos
= l
->fixp
->fx_next
;
10800 l
->fixp
->fx_next
= *lo_pos
;
10807 /* We may have combined relocations without symbols in the N32/N64 ABI.
10808 We have to prevent gas from dropping them. */
10811 mips_force_relocation (fixS
*fixp
)
10813 if (generic_force_reloc (fixp
))
10817 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10818 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10819 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10820 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10826 /* This hook is called before a fix is simplified. We don't really
10827 decide whether to skip a fix here. Rather, we turn global symbols
10828 used as branch targets into local symbols, such that they undergo
10829 simplification. We can only do this if the symbol is defined and
10830 it is in the same section as the branch. If this doesn't hold, we
10831 emit a better error message than just saying the relocation is not
10832 valid for the selected object format.
10834 FIXP is the fix-up we're going to try to simplify, SEG is the
10835 segment in which the fix up occurs. The return value should be
10836 non-zero to indicate the fix-up is valid for further
10837 simplifications. */
10840 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10842 /* There's a lot of discussion on whether it should be possible to
10843 use R_MIPS_PC16 to represent branch relocations. The outcome
10844 seems to be that it can, but gas/bfd are very broken in creating
10845 RELA relocations for this, so for now we only accept branches to
10846 symbols in the same section. Anything else is of dubious value,
10847 since there's no guarantee that at link time the symbol would be
10848 in range. Even for branches to local symbols this is arguably
10849 wrong, since it we assume the symbol is not going to be
10850 overridden, which should be possible per ELF library semantics,
10851 but then, there isn't a dynamic relocation that could be used to
10852 this effect, and the target would likely be out of range as well.
10854 Unfortunately, it seems that there is too much code out there
10855 that relies on branches to symbols that are global to be resolved
10856 as if they were local, like the IRIX tools do, so we do it as
10857 well, but with a warning so that people are reminded to fix their
10858 code. If we ever get back to using R_MIPS_PC16 for branch
10859 targets, this entire block should go away (and probably the
10860 whole function). */
10862 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10863 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10864 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10865 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10868 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10871 _("Cannot branch to undefined symbol."));
10872 /* Avoid any further errors about this fixup. */
10875 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10878 _("Cannot branch to symbol in another section."));
10881 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10883 symbolS
*sym
= fixP
->fx_addsy
;
10885 if (mips_pic
== SVR4_PIC
)
10886 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10887 _("Pretending global symbol used as branch target is local."));
10889 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10890 S_GET_SEGMENT (sym
),
10892 symbol_get_frag (sym
));
10893 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10894 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10895 assert (symbol_resolved_p (sym
));
10896 symbol_mark_resolved (fixP
->fx_addsy
);
10903 /* Apply a fixup to the object file. */
10906 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10910 reloc_howto_type
*howto
;
10912 /* We ignore generic BFD relocations we don't know about. */
10913 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10917 assert (fixP
->fx_size
== 4
10918 || fixP
->fx_r_type
== BFD_RELOC_16
10919 || fixP
->fx_r_type
== BFD_RELOC_64
10920 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10921 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10922 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10923 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10925 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10927 assert (! fixP
->fx_pcrel
);
10929 /* Don't treat parts of a composite relocation as done. There are two
10932 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10933 should nevertheless be emitted if the first part is.
10935 (2) In normal usage, composite relocations are never assembly-time
10936 constants. The easiest way of dealing with the pathological
10937 exceptions is to generate a relocation against STN_UNDEF and
10938 leave everything up to the linker. */
10939 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10942 switch (fixP
->fx_r_type
)
10944 case BFD_RELOC_MIPS_TLS_GD
:
10945 case BFD_RELOC_MIPS_TLS_LDM
:
10946 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10947 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10948 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10949 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10950 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10951 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10954 case BFD_RELOC_MIPS_JMP
:
10955 case BFD_RELOC_MIPS_SHIFT5
:
10956 case BFD_RELOC_MIPS_SHIFT6
:
10957 case BFD_RELOC_MIPS_GOT_DISP
:
10958 case BFD_RELOC_MIPS_GOT_PAGE
:
10959 case BFD_RELOC_MIPS_GOT_OFST
:
10960 case BFD_RELOC_MIPS_SUB
:
10961 case BFD_RELOC_MIPS_INSERT_A
:
10962 case BFD_RELOC_MIPS_INSERT_B
:
10963 case BFD_RELOC_MIPS_DELETE
:
10964 case BFD_RELOC_MIPS_HIGHEST
:
10965 case BFD_RELOC_MIPS_HIGHER
:
10966 case BFD_RELOC_MIPS_SCN_DISP
:
10967 case BFD_RELOC_MIPS_REL16
:
10968 case BFD_RELOC_MIPS_RELGOT
:
10969 case BFD_RELOC_MIPS_JALR
:
10970 case BFD_RELOC_HI16
:
10971 case BFD_RELOC_HI16_S
:
10972 case BFD_RELOC_GPREL16
:
10973 case BFD_RELOC_MIPS_LITERAL
:
10974 case BFD_RELOC_MIPS_CALL16
:
10975 case BFD_RELOC_MIPS_GOT16
:
10976 case BFD_RELOC_GPREL32
:
10977 case BFD_RELOC_MIPS_GOT_HI16
:
10978 case BFD_RELOC_MIPS_GOT_LO16
:
10979 case BFD_RELOC_MIPS_CALL_HI16
:
10980 case BFD_RELOC_MIPS_CALL_LO16
:
10981 case BFD_RELOC_MIPS16_GPREL
:
10982 case BFD_RELOC_MIPS16_HI16
:
10983 case BFD_RELOC_MIPS16_HI16_S
:
10984 assert (! fixP
->fx_pcrel
);
10985 /* Nothing needed to do. The value comes from the reloc entry */
10988 case BFD_RELOC_MIPS16_JMP
:
10989 /* We currently always generate a reloc against a symbol, which
10990 means that we don't want an addend even if the symbol is
10996 /* This is handled like BFD_RELOC_32, but we output a sign
10997 extended value if we are only 32 bits. */
11000 if (8 <= sizeof (valueT
))
11001 md_number_to_chars ((char *) buf
, *valP
, 8);
11006 if ((*valP
& 0x80000000) != 0)
11010 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11012 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11018 case BFD_RELOC_RVA
:
11020 /* If we are deleting this reloc entry, we must fill in the
11021 value now. This can happen if we have a .word which is not
11022 resolved when it appears but is later defined. */
11024 md_number_to_chars ((char *) buf
, *valP
, 4);
11028 /* If we are deleting this reloc entry, we must fill in the
11031 md_number_to_chars ((char *) buf
, *valP
, 2);
11034 case BFD_RELOC_LO16
:
11035 case BFD_RELOC_MIPS16_LO16
:
11036 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11037 may be safe to remove, but if so it's not obvious. */
11038 /* When handling an embedded PIC switch statement, we can wind
11039 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11042 if (*valP
+ 0x8000 > 0xffff)
11043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11044 _("relocation overflow"));
11045 if (target_big_endian
)
11047 md_number_to_chars ((char *) buf
, *valP
, 2);
11051 case BFD_RELOC_16_PCREL_S2
:
11052 if ((*valP
& 0x3) != 0)
11053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11054 _("Branch to odd address (%lx)"), (long) *valP
);
11057 * We need to save the bits in the instruction since fixup_segment()
11058 * might be deleting the relocation entry (i.e., a branch within
11059 * the current segment).
11061 if (! fixP
->fx_done
)
11064 /* update old instruction data */
11065 if (target_big_endian
)
11066 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11068 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11070 if (*valP
+ 0x20000 <= 0x3ffff)
11072 insn
|= (*valP
>> 2) & 0xffff;
11073 md_number_to_chars ((char *) buf
, insn
, 4);
11075 else if (mips_pic
== NO_PIC
11077 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11078 && (fixP
->fx_frag
->fr_address
11079 < text_section
->vma
+ bfd_get_section_size (text_section
))
11080 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11081 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11082 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11084 /* The branch offset is too large. If this is an
11085 unconditional branch, and we are not generating PIC code,
11086 we can convert it to an absolute jump instruction. */
11087 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11088 insn
= 0x0c000000; /* jal */
11090 insn
= 0x08000000; /* j */
11091 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11093 fixP
->fx_addsy
= section_symbol (text_section
);
11094 *valP
+= md_pcrel_from (fixP
);
11095 md_number_to_chars ((char *) buf
, insn
, 4);
11099 /* If we got here, we have branch-relaxation disabled,
11100 and there's nothing we can do to fix this instruction
11101 without turning it into a longer sequence. */
11102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11103 _("Branch out of range"));
11107 case BFD_RELOC_VTABLE_INHERIT
:
11110 && !S_IS_DEFINED (fixP
->fx_addsy
)
11111 && !S_IS_WEAK (fixP
->fx_addsy
))
11112 S_SET_WEAK (fixP
->fx_addsy
);
11115 case BFD_RELOC_VTABLE_ENTRY
:
11123 /* Remember value for tc_gen_reloc. */
11124 fixP
->fx_addnumber
= *valP
;
11134 name
= input_line_pointer
;
11135 c
= get_symbol_end ();
11136 p
= (symbolS
*) symbol_find_or_make (name
);
11137 *input_line_pointer
= c
;
11141 /* Align the current frag to a given power of two. The MIPS assembler
11142 also automatically adjusts any preceding label. */
11145 mips_align (int to
, int fill
, symbolS
*label
)
11147 mips_emit_delays ();
11148 frag_align (to
, fill
, 0);
11149 record_alignment (now_seg
, to
);
11152 assert (S_GET_SEGMENT (label
) == now_seg
);
11153 symbol_set_frag (label
, frag_now
);
11154 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11158 /* Align to a given power of two. .align 0 turns off the automatic
11159 alignment used by the data creating pseudo-ops. */
11162 s_align (int x ATTRIBUTE_UNUSED
)
11165 register long temp_fill
;
11166 long max_alignment
= 15;
11170 o Note that the assembler pulls down any immediately preceding label
11171 to the aligned address.
11172 o It's not documented but auto alignment is reinstated by
11173 a .align pseudo instruction.
11174 o Note also that after auto alignment is turned off the mips assembler
11175 issues an error on attempt to assemble an improperly aligned data item.
11180 temp
= get_absolute_expression ();
11181 if (temp
> max_alignment
)
11182 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11185 as_warn (_("Alignment negative: 0 assumed."));
11188 if (*input_line_pointer
== ',')
11190 ++input_line_pointer
;
11191 temp_fill
= get_absolute_expression ();
11198 mips_align (temp
, (int) temp_fill
,
11199 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11206 demand_empty_rest_of_line ();
11210 s_change_sec (int sec
)
11215 /* The ELF backend needs to know that we are changing sections, so
11216 that .previous works correctly. We could do something like check
11217 for an obj_section_change_hook macro, but that might be confusing
11218 as it would not be appropriate to use it in the section changing
11219 functions in read.c, since obj-elf.c intercepts those. FIXME:
11220 This should be cleaner, somehow. */
11221 obj_elf_section_change_hook ();
11224 mips_emit_delays ();
11234 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11235 demand_empty_rest_of_line ();
11239 seg
= subseg_new (RDATA_SECTION_NAME
,
11240 (subsegT
) get_absolute_expression ());
11241 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11243 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11244 | SEC_READONLY
| SEC_RELOC
11246 if (strcmp (TARGET_OS
, "elf") != 0)
11247 record_alignment (seg
, 4);
11249 demand_empty_rest_of_line ();
11253 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11254 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11256 bfd_set_section_flags (stdoutput
, seg
,
11257 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11258 if (strcmp (TARGET_OS
, "elf") != 0)
11259 record_alignment (seg
, 4);
11261 demand_empty_rest_of_line ();
11269 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11272 char *section_name
;
11277 int section_entry_size
;
11278 int section_alignment
;
11280 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11283 section_name
= input_line_pointer
;
11284 c
= get_symbol_end ();
11286 next_c
= *(input_line_pointer
+ 1);
11288 /* Do we have .section Name<,"flags">? */
11289 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11291 /* just after name is now '\0'. */
11292 *input_line_pointer
= c
;
11293 input_line_pointer
= section_name
;
11294 obj_elf_section (ignore
);
11297 input_line_pointer
++;
11299 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11301 section_type
= get_absolute_expression ();
11304 if (*input_line_pointer
++ == ',')
11305 section_flag
= get_absolute_expression ();
11308 if (*input_line_pointer
++ == ',')
11309 section_entry_size
= get_absolute_expression ();
11311 section_entry_size
= 0;
11312 if (*input_line_pointer
++ == ',')
11313 section_alignment
= get_absolute_expression ();
11315 section_alignment
= 0;
11317 section_name
= xstrdup (section_name
);
11319 /* When using the generic form of .section (as implemented by obj-elf.c),
11320 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11321 traditionally had to fall back on the more common @progbits instead.
11323 There's nothing really harmful in this, since bfd will correct
11324 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11325 means that, for backwards compatibiltiy, the special_section entries
11326 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11328 Even so, we shouldn't force users of the MIPS .section syntax to
11329 incorrectly label the sections as SHT_PROGBITS. The best compromise
11330 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11331 generic type-checking code. */
11332 if (section_type
== SHT_MIPS_DWARF
)
11333 section_type
= SHT_PROGBITS
;
11335 obj_elf_change_section (section_name
, section_type
, section_flag
,
11336 section_entry_size
, 0, 0, 0);
11338 if (now_seg
->name
!= section_name
)
11339 free (section_name
);
11340 #endif /* OBJ_ELF */
11344 mips_enable_auto_align (void)
11350 s_cons (int log_size
)
11354 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11355 mips_emit_delays ();
11356 if (log_size
> 0 && auto_align
)
11357 mips_align (log_size
, 0, label
);
11358 mips_clear_insn_labels ();
11359 cons (1 << log_size
);
11363 s_float_cons (int type
)
11367 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11369 mips_emit_delays ();
11374 mips_align (3, 0, label
);
11376 mips_align (2, 0, label
);
11379 mips_clear_insn_labels ();
11384 /* Handle .globl. We need to override it because on Irix 5 you are
11387 where foo is an undefined symbol, to mean that foo should be
11388 considered to be the address of a function. */
11391 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11398 name
= input_line_pointer
;
11399 c
= get_symbol_end ();
11400 symbolP
= symbol_find_or_make (name
);
11401 *input_line_pointer
= c
;
11402 SKIP_WHITESPACE ();
11404 /* On Irix 5, every global symbol that is not explicitly labelled as
11405 being a function is apparently labelled as being an object. */
11408 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11413 secname
= input_line_pointer
;
11414 c
= get_symbol_end ();
11415 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11417 as_bad (_("%s: no such section"), secname
);
11418 *input_line_pointer
= c
;
11420 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11421 flag
= BSF_FUNCTION
;
11424 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11426 S_SET_EXTERNAL (symbolP
);
11427 demand_empty_rest_of_line ();
11431 s_option (int x ATTRIBUTE_UNUSED
)
11436 opt
= input_line_pointer
;
11437 c
= get_symbol_end ();
11441 /* FIXME: What does this mean? */
11443 else if (strncmp (opt
, "pic", 3) == 0)
11447 i
= atoi (opt
+ 3);
11452 mips_pic
= SVR4_PIC
;
11453 mips_abicalls
= TRUE
;
11456 as_bad (_(".option pic%d not supported"), i
);
11458 if (mips_pic
== SVR4_PIC
)
11460 if (g_switch_seen
&& g_switch_value
!= 0)
11461 as_warn (_("-G may not be used with SVR4 PIC code"));
11462 g_switch_value
= 0;
11463 bfd_set_gp_size (stdoutput
, 0);
11467 as_warn (_("Unrecognized option \"%s\""), opt
);
11469 *input_line_pointer
= c
;
11470 demand_empty_rest_of_line ();
11473 /* This structure is used to hold a stack of .set values. */
11475 struct mips_option_stack
11477 struct mips_option_stack
*next
;
11478 struct mips_set_options options
;
11481 static struct mips_option_stack
*mips_opts_stack
;
11483 /* Handle the .set pseudo-op. */
11486 s_mipsset (int x ATTRIBUTE_UNUSED
)
11488 char *name
= input_line_pointer
, ch
;
11490 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11491 ++input_line_pointer
;
11492 ch
= *input_line_pointer
;
11493 *input_line_pointer
= '\0';
11495 if (strcmp (name
, "reorder") == 0)
11497 if (mips_opts
.noreorder
)
11500 else if (strcmp (name
, "noreorder") == 0)
11502 if (!mips_opts
.noreorder
)
11503 start_noreorder ();
11505 else if (strcmp (name
, "at") == 0)
11507 mips_opts
.noat
= 0;
11509 else if (strcmp (name
, "noat") == 0)
11511 mips_opts
.noat
= 1;
11513 else if (strcmp (name
, "macro") == 0)
11515 mips_opts
.warn_about_macros
= 0;
11517 else if (strcmp (name
, "nomacro") == 0)
11519 if (mips_opts
.noreorder
== 0)
11520 as_bad (_("`noreorder' must be set before `nomacro'"));
11521 mips_opts
.warn_about_macros
= 1;
11523 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11525 mips_opts
.nomove
= 0;
11527 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11529 mips_opts
.nomove
= 1;
11531 else if (strcmp (name
, "bopt") == 0)
11533 mips_opts
.nobopt
= 0;
11535 else if (strcmp (name
, "nobopt") == 0)
11537 mips_opts
.nobopt
= 1;
11539 else if (strcmp (name
, "mips16") == 0
11540 || strcmp (name
, "MIPS-16") == 0)
11541 mips_opts
.mips16
= 1;
11542 else if (strcmp (name
, "nomips16") == 0
11543 || strcmp (name
, "noMIPS-16") == 0)
11544 mips_opts
.mips16
= 0;
11545 else if (strcmp (name
, "mips3d") == 0)
11546 mips_opts
.ase_mips3d
= 1;
11547 else if (strcmp (name
, "nomips3d") == 0)
11548 mips_opts
.ase_mips3d
= 0;
11549 else if (strcmp (name
, "mdmx") == 0)
11550 mips_opts
.ase_mdmx
= 1;
11551 else if (strcmp (name
, "nomdmx") == 0)
11552 mips_opts
.ase_mdmx
= 0;
11553 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11557 /* Permit the user to change the ISA and architecture on the fly.
11558 Needless to say, misuse can cause serious problems. */
11559 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11562 mips_opts
.isa
= file_mips_isa
;
11563 mips_opts
.arch
= file_mips_arch
;
11565 else if (strncmp (name
, "arch=", 5) == 0)
11567 const struct mips_cpu_info
*p
;
11569 p
= mips_parse_cpu("internal use", name
+ 5);
11571 as_bad (_("unknown architecture %s"), name
+ 5);
11574 mips_opts
.arch
= p
->cpu
;
11575 mips_opts
.isa
= p
->isa
;
11578 else if (strncmp (name
, "mips", 4) == 0)
11580 const struct mips_cpu_info
*p
;
11582 p
= mips_parse_cpu("internal use", name
);
11584 as_bad (_("unknown ISA level %s"), name
+ 4);
11587 mips_opts
.arch
= p
->cpu
;
11588 mips_opts
.isa
= p
->isa
;
11592 as_bad (_("unknown ISA or architecture %s"), name
);
11594 switch (mips_opts
.isa
)
11602 mips_opts
.gp32
= 1;
11603 mips_opts
.fp32
= 1;
11610 mips_opts
.gp32
= 0;
11611 mips_opts
.fp32
= 0;
11614 as_bad (_("unknown ISA level %s"), name
+ 4);
11619 mips_opts
.gp32
= file_mips_gp32
;
11620 mips_opts
.fp32
= file_mips_fp32
;
11623 else if (strcmp (name
, "autoextend") == 0)
11624 mips_opts
.noautoextend
= 0;
11625 else if (strcmp (name
, "noautoextend") == 0)
11626 mips_opts
.noautoextend
= 1;
11627 else if (strcmp (name
, "push") == 0)
11629 struct mips_option_stack
*s
;
11631 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11632 s
->next
= mips_opts_stack
;
11633 s
->options
= mips_opts
;
11634 mips_opts_stack
= s
;
11636 else if (strcmp (name
, "pop") == 0)
11638 struct mips_option_stack
*s
;
11640 s
= mips_opts_stack
;
11642 as_bad (_(".set pop with no .set push"));
11645 /* If we're changing the reorder mode we need to handle
11646 delay slots correctly. */
11647 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11648 start_noreorder ();
11649 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11652 mips_opts
= s
->options
;
11653 mips_opts_stack
= s
->next
;
11657 else if (strcmp (name
, "sym32") == 0)
11658 mips_opts
.sym32
= TRUE
;
11659 else if (strcmp (name
, "nosym32") == 0)
11660 mips_opts
.sym32
= FALSE
;
11663 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11665 *input_line_pointer
= ch
;
11666 demand_empty_rest_of_line ();
11669 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11670 .option pic2. It means to generate SVR4 PIC calls. */
11673 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11675 mips_pic
= SVR4_PIC
;
11676 mips_abicalls
= TRUE
;
11678 if (g_switch_seen
&& g_switch_value
!= 0)
11679 as_warn (_("-G may not be used with SVR4 PIC code"));
11680 g_switch_value
= 0;
11682 bfd_set_gp_size (stdoutput
, 0);
11683 demand_empty_rest_of_line ();
11686 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11687 PIC code. It sets the $gp register for the function based on the
11688 function address, which is in the register named in the argument.
11689 This uses a relocation against _gp_disp, which is handled specially
11690 by the linker. The result is:
11691 lui $gp,%hi(_gp_disp)
11692 addiu $gp,$gp,%lo(_gp_disp)
11693 addu $gp,$gp,.cpload argument
11694 The .cpload argument is normally $25 == $t9.
11696 The -mno-shared option changes this to:
11697 lui $gp,%hi(__gnu_local_gp)
11698 addiu $gp,$gp,%lo(__gnu_local_gp)
11699 and the argument is ignored. This saves an instruction, but the
11700 resulting code is not position independent; it uses an absolute
11701 address for __gnu_local_gp. Thus code assembled with -mno-shared
11702 can go into an ordinary executable, but not into a shared library. */
11705 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11711 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11712 .cpload is ignored. */
11713 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11719 /* .cpload should be in a .set noreorder section. */
11720 if (mips_opts
.noreorder
== 0)
11721 as_warn (_(".cpload not in noreorder section"));
11723 reg
= tc_get_register (0);
11725 /* If we need to produce a 64-bit address, we are better off using
11726 the default instruction sequence. */
11727 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11729 ex
.X_op
= O_symbol
;
11730 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11732 ex
.X_op_symbol
= NULL
;
11733 ex
.X_add_number
= 0;
11735 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11736 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11739 macro_build_lui (&ex
, mips_gp_register
);
11740 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11741 mips_gp_register
, BFD_RELOC_LO16
);
11743 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11744 mips_gp_register
, reg
);
11747 demand_empty_rest_of_line ();
11750 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11751 .cpsetup $reg1, offset|$reg2, label
11753 If offset is given, this results in:
11754 sd $gp, offset($sp)
11755 lui $gp, %hi(%neg(%gp_rel(label)))
11756 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11757 daddu $gp, $gp, $reg1
11759 If $reg2 is given, this results in:
11760 daddu $reg2, $gp, $0
11761 lui $gp, %hi(%neg(%gp_rel(label)))
11762 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11763 daddu $gp, $gp, $reg1
11764 $reg1 is normally $25 == $t9.
11766 The -mno-shared option replaces the last three instructions with
11768 addiu $gp,$gp,%lo(_gp)
11772 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11774 expressionS ex_off
;
11775 expressionS ex_sym
;
11778 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11779 We also need NewABI support. */
11780 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11786 reg1
= tc_get_register (0);
11787 SKIP_WHITESPACE ();
11788 if (*input_line_pointer
!= ',')
11790 as_bad (_("missing argument separator ',' for .cpsetup"));
11794 ++input_line_pointer
;
11795 SKIP_WHITESPACE ();
11796 if (*input_line_pointer
== '$')
11798 mips_cpreturn_register
= tc_get_register (0);
11799 mips_cpreturn_offset
= -1;
11803 mips_cpreturn_offset
= get_absolute_expression ();
11804 mips_cpreturn_register
= -1;
11806 SKIP_WHITESPACE ();
11807 if (*input_line_pointer
!= ',')
11809 as_bad (_("missing argument separator ',' for .cpsetup"));
11813 ++input_line_pointer
;
11814 SKIP_WHITESPACE ();
11815 expression (&ex_sym
);
11818 if (mips_cpreturn_register
== -1)
11820 ex_off
.X_op
= O_constant
;
11821 ex_off
.X_add_symbol
= NULL
;
11822 ex_off
.X_op_symbol
= NULL
;
11823 ex_off
.X_add_number
= mips_cpreturn_offset
;
11825 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11826 BFD_RELOC_LO16
, SP
);
11829 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11830 mips_gp_register
, 0);
11832 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11834 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11835 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11838 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11839 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11840 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11842 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11843 mips_gp_register
, reg1
);
11849 ex
.X_op
= O_symbol
;
11850 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
11851 ex
.X_op_symbol
= NULL
;
11852 ex
.X_add_number
= 0;
11854 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11855 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11857 macro_build_lui (&ex
, mips_gp_register
);
11858 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11859 mips_gp_register
, BFD_RELOC_LO16
);
11864 demand_empty_rest_of_line ();
11868 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11870 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11871 .cplocal is ignored. */
11872 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11878 mips_gp_register
= tc_get_register (0);
11879 demand_empty_rest_of_line ();
11882 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11883 offset from $sp. The offset is remembered, and after making a PIC
11884 call $gp is restored from that location. */
11887 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11891 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11892 .cprestore is ignored. */
11893 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11899 mips_cprestore_offset
= get_absolute_expression ();
11900 mips_cprestore_valid
= 1;
11902 ex
.X_op
= O_constant
;
11903 ex
.X_add_symbol
= NULL
;
11904 ex
.X_op_symbol
= NULL
;
11905 ex
.X_add_number
= mips_cprestore_offset
;
11908 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11909 SP
, HAVE_64BIT_ADDRESSES
);
11912 demand_empty_rest_of_line ();
11915 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11916 was given in the preceding .cpsetup, it results in:
11917 ld $gp, offset($sp)
11919 If a register $reg2 was given there, it results in:
11920 daddu $gp, $reg2, $0
11923 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11927 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11928 We also need NewABI support. */
11929 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11936 if (mips_cpreturn_register
== -1)
11938 ex
.X_op
= O_constant
;
11939 ex
.X_add_symbol
= NULL
;
11940 ex
.X_op_symbol
= NULL
;
11941 ex
.X_add_number
= mips_cpreturn_offset
;
11943 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11946 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11947 mips_cpreturn_register
, 0);
11950 demand_empty_rest_of_line ();
11953 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11954 code. It sets the offset to use in gp_rel relocations. */
11957 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11959 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11960 We also need NewABI support. */
11961 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11967 mips_gprel_offset
= get_absolute_expression ();
11969 demand_empty_rest_of_line ();
11972 /* Handle the .gpword pseudo-op. This is used when generating PIC
11973 code. It generates a 32 bit GP relative reloc. */
11976 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11982 /* When not generating PIC code, this is treated as .word. */
11983 if (mips_pic
!= SVR4_PIC
)
11989 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11990 mips_emit_delays ();
11992 mips_align (2, 0, label
);
11993 mips_clear_insn_labels ();
11997 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11999 as_bad (_("Unsupported use of .gpword"));
12000 ignore_rest_of_line ();
12004 md_number_to_chars (p
, 0, 4);
12005 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12006 BFD_RELOC_GPREL32
);
12008 demand_empty_rest_of_line ();
12012 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12018 /* When not generating PIC code, this is treated as .dword. */
12019 if (mips_pic
!= SVR4_PIC
)
12025 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12026 mips_emit_delays ();
12028 mips_align (3, 0, label
);
12029 mips_clear_insn_labels ();
12033 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12035 as_bad (_("Unsupported use of .gpdword"));
12036 ignore_rest_of_line ();
12040 md_number_to_chars (p
, 0, 8);
12041 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12042 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12044 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12045 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12046 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12048 demand_empty_rest_of_line ();
12051 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12052 tables in SVR4 PIC code. */
12055 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12059 /* This is ignored when not generating SVR4 PIC code. */
12060 if (mips_pic
!= SVR4_PIC
)
12066 /* Add $gp to the register named as an argument. */
12068 reg
= tc_get_register (0);
12069 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12072 demand_empty_rest_of_line ();
12075 /* Handle the .insn pseudo-op. This marks instruction labels in
12076 mips16 mode. This permits the linker to handle them specially,
12077 such as generating jalx instructions when needed. We also make
12078 them odd for the duration of the assembly, in order to generate the
12079 right sort of code. We will make them even in the adjust_symtab
12080 routine, while leaving them marked. This is convenient for the
12081 debugger and the disassembler. The linker knows to make them odd
12085 s_insn (int ignore ATTRIBUTE_UNUSED
)
12087 mips16_mark_labels ();
12089 demand_empty_rest_of_line ();
12092 /* Handle a .stabn directive. We need these in order to mark a label
12093 as being a mips16 text label correctly. Sometimes the compiler
12094 will emit a label, followed by a .stabn, and then switch sections.
12095 If the label and .stabn are in mips16 mode, then the label is
12096 really a mips16 text label. */
12099 s_mips_stab (int type
)
12102 mips16_mark_labels ();
12107 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12111 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12118 name
= input_line_pointer
;
12119 c
= get_symbol_end ();
12120 symbolP
= symbol_find_or_make (name
);
12121 S_SET_WEAK (symbolP
);
12122 *input_line_pointer
= c
;
12124 SKIP_WHITESPACE ();
12126 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12128 if (S_IS_DEFINED (symbolP
))
12130 as_bad ("ignoring attempt to redefine symbol %s",
12131 S_GET_NAME (symbolP
));
12132 ignore_rest_of_line ();
12136 if (*input_line_pointer
== ',')
12138 ++input_line_pointer
;
12139 SKIP_WHITESPACE ();
12143 if (exp
.X_op
!= O_symbol
)
12145 as_bad ("bad .weakext directive");
12146 ignore_rest_of_line ();
12149 symbol_set_value_expression (symbolP
, &exp
);
12152 demand_empty_rest_of_line ();
12155 /* Parse a register string into a number. Called from the ECOFF code
12156 to parse .frame. The argument is non-zero if this is the frame
12157 register, so that we can record it in mips_frame_reg. */
12160 tc_get_register (int frame
)
12164 SKIP_WHITESPACE ();
12165 if (*input_line_pointer
++ != '$')
12167 as_warn (_("expected `$'"));
12170 else if (ISDIGIT (*input_line_pointer
))
12172 reg
= get_absolute_expression ();
12173 if (reg
< 0 || reg
>= 32)
12175 as_warn (_("Bad register number"));
12181 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12184 input_line_pointer
+= 2;
12186 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12189 input_line_pointer
+= 2;
12191 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12194 input_line_pointer
+= 2;
12196 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12199 input_line_pointer
+= 2;
12201 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12204 input_line_pointer
+= 2;
12206 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12209 input_line_pointer
+= 3;
12211 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12214 input_line_pointer
+= 3;
12216 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12219 input_line_pointer
+= 4;
12223 as_warn (_("Unrecognized register name"));
12225 while (ISALNUM(*input_line_pointer
))
12226 input_line_pointer
++;
12231 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12232 mips_frame_reg_valid
= 1;
12233 mips_cprestore_valid
= 0;
12239 md_section_align (asection
*seg
, valueT addr
)
12241 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12244 /* We don't need to align ELF sections to the full alignment.
12245 However, Irix 5 may prefer that we align them at least to a 16
12246 byte boundary. We don't bother to align the sections if we are
12247 targeted for an embedded system. */
12248 if (strcmp (TARGET_OS
, "elf") == 0)
12254 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12257 /* Utility routine, called from above as well. If called while the
12258 input file is still being read, it's only an approximation. (For
12259 example, a symbol may later become defined which appeared to be
12260 undefined earlier.) */
12263 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12268 if (g_switch_value
> 0)
12270 const char *symname
;
12273 /* Find out whether this symbol can be referenced off the $gp
12274 register. It can be if it is smaller than the -G size or if
12275 it is in the .sdata or .sbss section. Certain symbols can
12276 not be referenced off the $gp, although it appears as though
12278 symname
= S_GET_NAME (sym
);
12279 if (symname
!= (const char *) NULL
12280 && (strcmp (symname
, "eprol") == 0
12281 || strcmp (symname
, "etext") == 0
12282 || strcmp (symname
, "_gp") == 0
12283 || strcmp (symname
, "edata") == 0
12284 || strcmp (symname
, "_fbss") == 0
12285 || strcmp (symname
, "_fdata") == 0
12286 || strcmp (symname
, "_ftext") == 0
12287 || strcmp (symname
, "end") == 0
12288 || strcmp (symname
, "_gp_disp") == 0))
12290 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12292 #ifndef NO_ECOFF_DEBUGGING
12293 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12294 && (symbol_get_obj (sym
)->ecoff_extern_size
12295 <= g_switch_value
))
12297 /* We must defer this decision until after the whole
12298 file has been read, since there might be a .extern
12299 after the first use of this symbol. */
12300 || (before_relaxing
12301 #ifndef NO_ECOFF_DEBUGGING
12302 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12304 && S_GET_VALUE (sym
) == 0)
12305 || (S_GET_VALUE (sym
) != 0
12306 && S_GET_VALUE (sym
) <= g_switch_value
)))
12310 const char *segname
;
12312 segname
= segment_name (S_GET_SEGMENT (sym
));
12313 assert (strcmp (segname
, ".lit8") != 0
12314 && strcmp (segname
, ".lit4") != 0);
12315 change
= (strcmp (segname
, ".sdata") != 0
12316 && strcmp (segname
, ".sbss") != 0
12317 && strncmp (segname
, ".sdata.", 7) != 0
12318 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12323 /* We are not optimizing for the $gp register. */
12328 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12331 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12334 bfd_boolean linkonce
;
12336 /* Handle the case of a symbol equated to another symbol. */
12337 while (symbol_equated_reloc_p (sym
))
12341 /* It's possible to get a loop here in a badly written
12343 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12349 symsec
= S_GET_SEGMENT (sym
);
12351 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12353 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12355 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12359 /* The GNU toolchain uses an extension for ELF: a section
12360 beginning with the magic string .gnu.linkonce is a linkonce
12362 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12363 sizeof ".gnu.linkonce" - 1) == 0)
12367 /* This must duplicate the test in adjust_reloc_syms. */
12368 return (symsec
!= &bfd_und_section
12369 && symsec
!= &bfd_abs_section
12370 && ! bfd_is_com_section (symsec
)
12373 /* A global or weak symbol is treated as external. */
12374 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12375 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12381 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12382 extended opcode. SEC is the section the frag is in. */
12385 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12388 register const struct mips16_immed_operand
*op
;
12390 int mintiny
, maxtiny
;
12394 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12396 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12399 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12400 op
= mips16_immed_operands
;
12401 while (op
->type
!= type
)
12404 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12409 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12412 maxtiny
= 1 << op
->nbits
;
12417 maxtiny
= (1 << op
->nbits
) - 1;
12422 mintiny
= - (1 << (op
->nbits
- 1));
12423 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12426 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12427 val
= S_GET_VALUE (fragp
->fr_symbol
);
12428 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12434 /* We won't have the section when we are called from
12435 mips_relax_frag. However, we will always have been called
12436 from md_estimate_size_before_relax first. If this is a
12437 branch to a different section, we mark it as such. If SEC is
12438 NULL, and the frag is not marked, then it must be a branch to
12439 the same section. */
12442 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12447 /* Must have been called from md_estimate_size_before_relax. */
12450 fragp
->fr_subtype
=
12451 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12453 /* FIXME: We should support this, and let the linker
12454 catch branches and loads that are out of range. */
12455 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12456 _("unsupported PC relative reference to different section"));
12460 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12461 /* Assume non-extended on the first relaxation pass.
12462 The address we have calculated will be bogus if this is
12463 a forward branch to another frag, as the forward frag
12464 will have fr_address == 0. */
12468 /* In this case, we know for sure that the symbol fragment is in
12469 the same section. If the relax_marker of the symbol fragment
12470 differs from the relax_marker of this fragment, we have not
12471 yet adjusted the symbol fragment fr_address. We want to add
12472 in STRETCH in order to get a better estimate of the address.
12473 This particularly matters because of the shift bits. */
12475 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12479 /* Adjust stretch for any alignment frag. Note that if have
12480 been expanding the earlier code, the symbol may be
12481 defined in what appears to be an earlier frag. FIXME:
12482 This doesn't handle the fr_subtype field, which specifies
12483 a maximum number of bytes to skip when doing an
12485 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12487 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12490 stretch
= - ((- stretch
)
12491 & ~ ((1 << (int) f
->fr_offset
) - 1));
12493 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12502 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12504 /* The base address rules are complicated. The base address of
12505 a branch is the following instruction. The base address of a
12506 PC relative load or add is the instruction itself, but if it
12507 is in a delay slot (in which case it can not be extended) use
12508 the address of the instruction whose delay slot it is in. */
12509 if (type
== 'p' || type
== 'q')
12513 /* If we are currently assuming that this frag should be
12514 extended, then, the current address is two bytes
12516 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12519 /* Ignore the low bit in the target, since it will be set
12520 for a text label. */
12521 if ((val
& 1) != 0)
12524 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12526 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12529 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12531 /* Branch offsets have an implicit 0 in the lowest bit. */
12532 if (type
== 'p' || type
== 'q')
12535 /* If any of the shifted bits are set, we must use an extended
12536 opcode. If the address depends on the size of this
12537 instruction, this can lead to a loop, so we arrange to always
12538 use an extended opcode. We only check this when we are in
12539 the main relaxation loop, when SEC is NULL. */
12540 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12542 fragp
->fr_subtype
=
12543 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12547 /* If we are about to mark a frag as extended because the value
12548 is precisely maxtiny + 1, then there is a chance of an
12549 infinite loop as in the following code:
12554 In this case when the la is extended, foo is 0x3fc bytes
12555 away, so the la can be shrunk, but then foo is 0x400 away, so
12556 the la must be extended. To avoid this loop, we mark the
12557 frag as extended if it was small, and is about to become
12558 extended with a value of maxtiny + 1. */
12559 if (val
== ((maxtiny
+ 1) << op
->shift
)
12560 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12563 fragp
->fr_subtype
=
12564 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12568 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12569 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12571 if ((val
& ((1 << op
->shift
) - 1)) != 0
12572 || val
< (mintiny
<< op
->shift
)
12573 || val
> (maxtiny
<< op
->shift
))
12579 /* Compute the length of a branch sequence, and adjust the
12580 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12581 worst-case length is computed, with UPDATE being used to indicate
12582 whether an unconditional (-1), branch-likely (+1) or regular (0)
12583 branch is to be computed. */
12585 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12587 bfd_boolean toofar
;
12591 && S_IS_DEFINED (fragp
->fr_symbol
)
12592 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12597 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12599 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12603 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12606 /* If the symbol is not defined or it's in a different segment,
12607 assume the user knows what's going on and emit a short
12613 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12615 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12616 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12617 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12623 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12626 if (mips_pic
!= NO_PIC
)
12628 /* Additional space for PIC loading of target address. */
12630 if (mips_opts
.isa
== ISA_MIPS1
)
12631 /* Additional space for $at-stabilizing nop. */
12635 /* If branch is conditional. */
12636 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12643 /* Estimate the size of a frag before relaxing. Unless this is the
12644 mips16, we are not really relaxing here, and the final size is
12645 encoded in the subtype information. For the mips16, we have to
12646 decide whether we are using an extended opcode or not. */
12649 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12653 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12656 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12658 return fragp
->fr_var
;
12661 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12662 /* We don't want to modify the EXTENDED bit here; it might get us
12663 into infinite loops. We change it only in mips_relax_frag(). */
12664 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12666 if (mips_pic
== NO_PIC
)
12667 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12668 else if (mips_pic
== SVR4_PIC
)
12669 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12675 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12676 return -RELAX_FIRST (fragp
->fr_subtype
);
12679 return -RELAX_SECOND (fragp
->fr_subtype
);
12682 /* This is called to see whether a reloc against a defined symbol
12683 should be converted into a reloc against a section. */
12686 mips_fix_adjustable (fixS
*fixp
)
12688 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12689 about the format of the offset in the .o file. */
12690 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12693 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12694 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12697 if (fixp
->fx_addsy
== NULL
)
12700 /* If symbol SYM is in a mergeable section, relocations of the form
12701 SYM + 0 can usually be made section-relative. The mergeable data
12702 is then identified by the section offset rather than by the symbol.
12704 However, if we're generating REL LO16 relocations, the offset is split
12705 between the LO16 and parterning high part relocation. The linker will
12706 need to recalculate the complete offset in order to correctly identify
12709 The linker has traditionally not looked for the parterning high part
12710 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12711 placed anywhere. Rather than break backwards compatibility by changing
12712 this, it seems better not to force the issue, and instead keep the
12713 original symbol. This will work with either linker behavior. */
12714 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
12715 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
12716 || reloc_needs_lo_p (fixp
->fx_r_type
))
12717 && HAVE_IN_PLACE_ADDENDS
12718 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12722 /* Don't adjust relocations against mips16 symbols, so that the linker
12723 can find them if it needs to set up a stub. */
12724 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12725 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12726 && fixp
->fx_subsy
== NULL
)
12733 /* Translate internal representation of relocation info to BFD target
12737 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12739 static arelent
*retval
[4];
12741 bfd_reloc_code_real_type code
;
12743 memset (retval
, 0, sizeof(retval
));
12744 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12745 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12746 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12747 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12749 assert (! fixp
->fx_pcrel
);
12750 reloc
->addend
= fixp
->fx_addnumber
;
12752 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12753 entry to be used in the relocation's section offset. */
12754 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12756 reloc
->address
= reloc
->addend
;
12760 code
= fixp
->fx_r_type
;
12762 /* To support a PC relative reloc, we used a Cygnus extension.
12763 We check for that here to make sure that we don't let such a
12764 reloc escape normally. (FIXME: This was formerly used by
12765 embedded-PIC support, but is now used by branch handling in
12766 general. That probably should be fixed.) */
12767 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12768 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12769 && code
== BFD_RELOC_16_PCREL_S2
)
12770 reloc
->howto
= NULL
;
12772 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12774 if (reloc
->howto
== NULL
)
12776 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12777 _("Can not represent %s relocation in this object file format"),
12778 bfd_get_reloc_code_name (code
));
12785 /* Relax a machine dependent frag. This returns the amount by which
12786 the current size of the frag should change. */
12789 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12791 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12793 offsetT old_var
= fragp
->fr_var
;
12795 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12797 return fragp
->fr_var
- old_var
;
12800 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12803 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12805 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12807 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12812 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12814 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12821 /* Convert a machine dependent frag. */
12824 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12826 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12829 unsigned long insn
;
12833 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12835 if (target_big_endian
)
12836 insn
= bfd_getb32 (buf
);
12838 insn
= bfd_getl32 (buf
);
12840 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12842 /* We generate a fixup instead of applying it right now
12843 because, if there are linker relaxations, we're going to
12844 need the relocations. */
12845 exp
.X_op
= O_symbol
;
12846 exp
.X_add_symbol
= fragp
->fr_symbol
;
12847 exp
.X_add_number
= fragp
->fr_offset
;
12849 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12851 BFD_RELOC_16_PCREL_S2
);
12852 fixp
->fx_file
= fragp
->fr_file
;
12853 fixp
->fx_line
= fragp
->fr_line
;
12855 md_number_to_chars ((char *) buf
, insn
, 4);
12862 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12863 _("relaxed out-of-range branch into a jump"));
12865 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12868 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12870 /* Reverse the branch. */
12871 switch ((insn
>> 28) & 0xf)
12874 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12875 have the condition reversed by tweaking a single
12876 bit, and their opcodes all have 0x4???????. */
12877 assert ((insn
& 0xf1000000) == 0x41000000);
12878 insn
^= 0x00010000;
12882 /* bltz 0x04000000 bgez 0x04010000
12883 bltzal 0x04100000 bgezal 0x04110000 */
12884 assert ((insn
& 0xfc0e0000) == 0x04000000);
12885 insn
^= 0x00010000;
12889 /* beq 0x10000000 bne 0x14000000
12890 blez 0x18000000 bgtz 0x1c000000 */
12891 insn
^= 0x04000000;
12899 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12901 /* Clear the and-link bit. */
12902 assert ((insn
& 0xfc1c0000) == 0x04100000);
12904 /* bltzal 0x04100000 bgezal 0x04110000
12905 bltzall 0x04120000 bgezall 0x04130000 */
12906 insn
&= ~0x00100000;
12909 /* Branch over the branch (if the branch was likely) or the
12910 full jump (not likely case). Compute the offset from the
12911 current instruction to branch to. */
12912 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12916 /* How many bytes in instructions we've already emitted? */
12917 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12918 /* How many bytes in instructions from here to the end? */
12919 i
= fragp
->fr_var
- i
;
12921 /* Convert to instruction count. */
12923 /* Branch counts from the next instruction. */
12926 /* Branch over the jump. */
12927 md_number_to_chars ((char *) buf
, insn
, 4);
12931 md_number_to_chars ((char *) buf
, 0, 4);
12934 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12936 /* beql $0, $0, 2f */
12938 /* Compute the PC offset from the current instruction to
12939 the end of the variable frag. */
12940 /* How many bytes in instructions we've already emitted? */
12941 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12942 /* How many bytes in instructions from here to the end? */
12943 i
= fragp
->fr_var
- i
;
12944 /* Convert to instruction count. */
12946 /* Don't decrement i, because we want to branch over the
12950 md_number_to_chars ((char *) buf
, insn
, 4);
12953 md_number_to_chars ((char *) buf
, 0, 4);
12958 if (mips_pic
== NO_PIC
)
12961 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12962 ? 0x0c000000 : 0x08000000);
12963 exp
.X_op
= O_symbol
;
12964 exp
.X_add_symbol
= fragp
->fr_symbol
;
12965 exp
.X_add_number
= fragp
->fr_offset
;
12967 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12968 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12969 fixp
->fx_file
= fragp
->fr_file
;
12970 fixp
->fx_line
= fragp
->fr_line
;
12972 md_number_to_chars ((char *) buf
, insn
, 4);
12977 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12978 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12979 exp
.X_op
= O_symbol
;
12980 exp
.X_add_symbol
= fragp
->fr_symbol
;
12981 exp
.X_add_number
= fragp
->fr_offset
;
12983 if (fragp
->fr_offset
)
12985 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12986 exp
.X_add_number
= 0;
12989 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12990 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12991 fixp
->fx_file
= fragp
->fr_file
;
12992 fixp
->fx_line
= fragp
->fr_line
;
12994 md_number_to_chars ((char *) buf
, insn
, 4);
12997 if (mips_opts
.isa
== ISA_MIPS1
)
13000 md_number_to_chars ((char *) buf
, 0, 4);
13004 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13005 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13007 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13008 4, &exp
, 0, BFD_RELOC_LO16
);
13009 fixp
->fx_file
= fragp
->fr_file
;
13010 fixp
->fx_line
= fragp
->fr_line
;
13012 md_number_to_chars ((char *) buf
, insn
, 4);
13016 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13021 md_number_to_chars ((char *) buf
, insn
, 4);
13026 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13027 + fragp
->fr_fix
+ fragp
->fr_var
);
13029 fragp
->fr_fix
+= fragp
->fr_var
;
13034 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13037 register const struct mips16_immed_operand
*op
;
13038 bfd_boolean small
, ext
;
13041 unsigned long insn
;
13042 bfd_boolean use_extend
;
13043 unsigned short extend
;
13045 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13046 op
= mips16_immed_operands
;
13047 while (op
->type
!= type
)
13050 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13061 resolve_symbol_value (fragp
->fr_symbol
);
13062 val
= S_GET_VALUE (fragp
->fr_symbol
);
13067 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13069 /* The rules for the base address of a PC relative reloc are
13070 complicated; see mips16_extended_frag. */
13071 if (type
== 'p' || type
== 'q')
13076 /* Ignore the low bit in the target, since it will be
13077 set for a text label. */
13078 if ((val
& 1) != 0)
13081 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13083 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13086 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13089 /* Make sure the section winds up with the alignment we have
13092 record_alignment (asec
, op
->shift
);
13096 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13097 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13098 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13099 _("extended instruction in delay slot"));
13101 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13103 if (target_big_endian
)
13104 insn
= bfd_getb16 (buf
);
13106 insn
= bfd_getl16 (buf
);
13108 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13109 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13110 small
, ext
, &insn
, &use_extend
, &extend
);
13114 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13115 fragp
->fr_fix
+= 2;
13119 md_number_to_chars ((char *) buf
, insn
, 2);
13120 fragp
->fr_fix
+= 2;
13128 first
= RELAX_FIRST (fragp
->fr_subtype
);
13129 second
= RELAX_SECOND (fragp
->fr_subtype
);
13130 fixp
= (fixS
*) fragp
->fr_opcode
;
13132 /* Possibly emit a warning if we've chosen the longer option. */
13133 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13134 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13136 const char *msg
= macro_warning (fragp
->fr_subtype
);
13138 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13141 /* Go through all the fixups for the first sequence. Disable them
13142 (by marking them as done) if we're going to use the second
13143 sequence instead. */
13145 && fixp
->fx_frag
== fragp
13146 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13148 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13150 fixp
= fixp
->fx_next
;
13153 /* Go through the fixups for the second sequence. Disable them if
13154 we're going to use the first sequence, otherwise adjust their
13155 addresses to account for the relaxation. */
13156 while (fixp
&& fixp
->fx_frag
== fragp
)
13158 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13159 fixp
->fx_where
-= first
;
13162 fixp
= fixp
->fx_next
;
13165 /* Now modify the frag contents. */
13166 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13170 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13171 memmove (start
, start
+ first
, second
);
13172 fragp
->fr_fix
-= first
;
13175 fragp
->fr_fix
-= second
;
13181 /* This function is called after the relocs have been generated.
13182 We've been storing mips16 text labels as odd. Here we convert them
13183 back to even for the convenience of the debugger. */
13186 mips_frob_file_after_relocs (void)
13189 unsigned int count
, i
;
13191 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13194 syms
= bfd_get_outsymbols (stdoutput
);
13195 count
= bfd_get_symcount (stdoutput
);
13196 for (i
= 0; i
< count
; i
++, syms
++)
13198 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13199 && ((*syms
)->value
& 1) != 0)
13201 (*syms
)->value
&= ~1;
13202 /* If the symbol has an odd size, it was probably computed
13203 incorrectly, so adjust that as well. */
13204 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13205 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13212 /* This function is called whenever a label is defined. It is used
13213 when handling branch delays; if a branch has a label, we assume we
13214 can not move it. */
13217 mips_define_label (symbolS
*sym
)
13219 struct insn_label_list
*l
;
13221 if (free_insn_labels
== NULL
)
13222 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13225 l
= free_insn_labels
;
13226 free_insn_labels
= l
->next
;
13230 l
->next
= insn_labels
;
13234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13236 /* Some special processing for a MIPS ELF file. */
13239 mips_elf_final_processing (void)
13241 /* Write out the register information. */
13242 if (mips_abi
!= N64_ABI
)
13246 s
.ri_gprmask
= mips_gprmask
;
13247 s
.ri_cprmask
[0] = mips_cprmask
[0];
13248 s
.ri_cprmask
[1] = mips_cprmask
[1];
13249 s
.ri_cprmask
[2] = mips_cprmask
[2];
13250 s
.ri_cprmask
[3] = mips_cprmask
[3];
13251 /* The gp_value field is set by the MIPS ELF backend. */
13253 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13254 ((Elf32_External_RegInfo
*)
13255 mips_regmask_frag
));
13259 Elf64_Internal_RegInfo s
;
13261 s
.ri_gprmask
= mips_gprmask
;
13263 s
.ri_cprmask
[0] = mips_cprmask
[0];
13264 s
.ri_cprmask
[1] = mips_cprmask
[1];
13265 s
.ri_cprmask
[2] = mips_cprmask
[2];
13266 s
.ri_cprmask
[3] = mips_cprmask
[3];
13267 /* The gp_value field is set by the MIPS ELF backend. */
13269 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13270 ((Elf64_External_RegInfo
*)
13271 mips_regmask_frag
));
13274 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13275 sort of BFD interface for this. */
13276 if (mips_any_noreorder
)
13277 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13278 if (mips_pic
!= NO_PIC
)
13280 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13281 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13284 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13286 /* Set MIPS ELF flags for ASEs. */
13287 if (file_ase_mips16
)
13288 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13289 #if 0 /* XXX FIXME */
13290 if (file_ase_mips3d
)
13291 elf_elfheader (stdoutput
)->e_flags
|= ???;
13294 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13296 /* Set the MIPS ELF ABI flags. */
13297 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13298 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13299 else if (mips_abi
== O64_ABI
)
13300 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13301 else if (mips_abi
== EABI_ABI
)
13303 if (!file_mips_gp32
)
13304 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13306 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13308 else if (mips_abi
== N32_ABI
)
13309 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13311 /* Nothing to do for N64_ABI. */
13313 if (mips_32bitmode
)
13314 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13317 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13319 typedef struct proc
{
13321 symbolS
*func_end_sym
;
13322 unsigned long reg_mask
;
13323 unsigned long reg_offset
;
13324 unsigned long fpreg_mask
;
13325 unsigned long fpreg_offset
;
13326 unsigned long frame_offset
;
13327 unsigned long frame_reg
;
13328 unsigned long pc_reg
;
13331 static procS cur_proc
;
13332 static procS
*cur_proc_ptr
;
13333 static int numprocs
;
13335 /* Fill in an rs_align_code fragment. */
13338 mips_handle_align (fragS
*fragp
)
13340 if (fragp
->fr_type
!= rs_align_code
)
13343 if (mips_opts
.mips16
)
13345 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13346 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13351 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13352 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13360 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13364 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13368 md_obj_begin (void)
13375 /* check for premature end, nesting errors, etc */
13377 as_warn (_("missing .end at end of assembly"));
13386 if (*input_line_pointer
== '-')
13388 ++input_line_pointer
;
13391 if (!ISDIGIT (*input_line_pointer
))
13392 as_bad (_("expected simple number"));
13393 if (input_line_pointer
[0] == '0')
13395 if (input_line_pointer
[1] == 'x')
13397 input_line_pointer
+= 2;
13398 while (ISXDIGIT (*input_line_pointer
))
13401 val
|= hex_value (*input_line_pointer
++);
13403 return negative
? -val
: val
;
13407 ++input_line_pointer
;
13408 while (ISDIGIT (*input_line_pointer
))
13411 val
|= *input_line_pointer
++ - '0';
13413 return negative
? -val
: val
;
13416 if (!ISDIGIT (*input_line_pointer
))
13418 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13419 *input_line_pointer
, *input_line_pointer
);
13420 as_warn (_("invalid number"));
13423 while (ISDIGIT (*input_line_pointer
))
13426 val
+= *input_line_pointer
++ - '0';
13428 return negative
? -val
: val
;
13431 /* The .file directive; just like the usual .file directive, but there
13432 is an initial number which is the ECOFF file index. In the non-ECOFF
13433 case .file implies DWARF-2. */
13436 s_mips_file (int x ATTRIBUTE_UNUSED
)
13438 static int first_file_directive
= 0;
13440 if (ECOFF_DEBUGGING
)
13449 filename
= dwarf2_directive_file (0);
13451 /* Versions of GCC up to 3.1 start files with a ".file"
13452 directive even for stabs output. Make sure that this
13453 ".file" is handled. Note that you need a version of GCC
13454 after 3.1 in order to support DWARF-2 on MIPS. */
13455 if (filename
!= NULL
&& ! first_file_directive
)
13457 (void) new_logical_line (filename
, -1);
13458 s_app_file_string (filename
, 0);
13460 first_file_directive
= 1;
13464 /* The .loc directive, implying DWARF-2. */
13467 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13469 if (!ECOFF_DEBUGGING
)
13470 dwarf2_directive_loc (0);
13473 /* The .end directive. */
13476 s_mips_end (int x ATTRIBUTE_UNUSED
)
13480 /* Following functions need their own .frame and .cprestore directives. */
13481 mips_frame_reg_valid
= 0;
13482 mips_cprestore_valid
= 0;
13484 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13487 demand_empty_rest_of_line ();
13492 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13493 as_warn (_(".end not in text section"));
13497 as_warn (_(".end directive without a preceding .ent directive."));
13498 demand_empty_rest_of_line ();
13504 assert (S_GET_NAME (p
));
13505 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13506 as_warn (_(".end symbol does not match .ent symbol."));
13508 if (debug_type
== DEBUG_STABS
)
13509 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13513 as_warn (_(".end directive missing or unknown symbol"));
13516 /* Create an expression to calculate the size of the function. */
13517 if (p
&& cur_proc_ptr
)
13519 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13520 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13523 exp
->X_op
= O_subtract
;
13524 exp
->X_add_symbol
= symbol_temp_new_now ();
13525 exp
->X_op_symbol
= p
;
13526 exp
->X_add_number
= 0;
13528 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13531 /* Generate a .pdr section. */
13532 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13535 segT saved_seg
= now_seg
;
13536 subsegT saved_subseg
= now_subseg
;
13541 dot
= frag_now_fix ();
13543 #ifdef md_flush_pending_output
13544 md_flush_pending_output ();
13548 subseg_set (pdr_seg
, 0);
13550 /* Write the symbol. */
13551 exp
.X_op
= O_symbol
;
13552 exp
.X_add_symbol
= p
;
13553 exp
.X_add_number
= 0;
13554 emit_expr (&exp
, 4);
13556 fragp
= frag_more (7 * 4);
13558 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13559 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13560 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13561 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13562 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13563 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13564 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13566 subseg_set (saved_seg
, saved_subseg
);
13568 #endif /* OBJ_ELF */
13570 cur_proc_ptr
= NULL
;
13573 /* The .aent and .ent directives. */
13576 s_mips_ent (int aent
)
13580 symbolP
= get_symbol ();
13581 if (*input_line_pointer
== ',')
13582 ++input_line_pointer
;
13583 SKIP_WHITESPACE ();
13584 if (ISDIGIT (*input_line_pointer
)
13585 || *input_line_pointer
== '-')
13588 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13589 as_warn (_(".ent or .aent not in text section."));
13591 if (!aent
&& cur_proc_ptr
)
13592 as_warn (_("missing .end"));
13596 /* This function needs its own .frame and .cprestore directives. */
13597 mips_frame_reg_valid
= 0;
13598 mips_cprestore_valid
= 0;
13600 cur_proc_ptr
= &cur_proc
;
13601 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13603 cur_proc_ptr
->func_sym
= symbolP
;
13605 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13609 if (debug_type
== DEBUG_STABS
)
13610 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13611 S_GET_NAME (symbolP
));
13614 demand_empty_rest_of_line ();
13617 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13618 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13619 s_mips_frame is used so that we can set the PDR information correctly.
13620 We can't use the ecoff routines because they make reference to the ecoff
13621 symbol table (in the mdebug section). */
13624 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13627 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13631 if (cur_proc_ptr
== (procS
*) NULL
)
13633 as_warn (_(".frame outside of .ent"));
13634 demand_empty_rest_of_line ();
13638 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13640 SKIP_WHITESPACE ();
13641 if (*input_line_pointer
++ != ','
13642 || get_absolute_expression_and_terminator (&val
) != ',')
13644 as_warn (_("Bad .frame directive"));
13645 --input_line_pointer
;
13646 demand_empty_rest_of_line ();
13650 cur_proc_ptr
->frame_offset
= val
;
13651 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13653 demand_empty_rest_of_line ();
13656 #endif /* OBJ_ELF */
13660 /* The .fmask and .mask directives. If the mdebug section is present
13661 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13662 embedded targets, s_mips_mask is used so that we can set the PDR
13663 information correctly. We can't use the ecoff routines because they
13664 make reference to the ecoff symbol table (in the mdebug section). */
13667 s_mips_mask (int reg_type
)
13670 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13674 if (cur_proc_ptr
== (procS
*) NULL
)
13676 as_warn (_(".mask/.fmask outside of .ent"));
13677 demand_empty_rest_of_line ();
13681 if (get_absolute_expression_and_terminator (&mask
) != ',')
13683 as_warn (_("Bad .mask/.fmask directive"));
13684 --input_line_pointer
;
13685 demand_empty_rest_of_line ();
13689 off
= get_absolute_expression ();
13691 if (reg_type
== 'F')
13693 cur_proc_ptr
->fpreg_mask
= mask
;
13694 cur_proc_ptr
->fpreg_offset
= off
;
13698 cur_proc_ptr
->reg_mask
= mask
;
13699 cur_proc_ptr
->reg_offset
= off
;
13702 demand_empty_rest_of_line ();
13705 #endif /* OBJ_ELF */
13706 s_ignore (reg_type
);
13709 /* A table describing all the processors gas knows about. Names are
13710 matched in the order listed.
13712 To ease comparison, please keep this table in the same order as
13713 gcc's mips_cpu_info_table[]. */
13714 static const struct mips_cpu_info mips_cpu_info_table
[] =
13716 /* Entries for generic ISAs */
13717 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13718 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13719 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13720 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13721 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13722 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13723 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13724 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13725 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13728 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13729 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13730 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13733 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13736 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13737 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13738 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13739 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13740 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13741 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13742 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13743 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13744 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13745 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13746 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13747 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13750 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13751 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13752 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13753 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13754 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13755 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13756 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13757 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13758 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13759 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13760 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13761 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13762 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13765 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13766 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13767 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13770 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13771 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13773 /* Broadcom SB-1 CPU core */
13774 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13781 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13782 with a final "000" replaced by "k". Ignore case.
13784 Note: this function is shared between GCC and GAS. */
13787 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13789 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13790 given
++, canonical
++;
13792 return ((*given
== 0 && *canonical
== 0)
13793 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13797 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13798 CPU name. We've traditionally allowed a lot of variation here.
13800 Note: this function is shared between GCC and GAS. */
13803 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13805 /* First see if the name matches exactly, or with a final "000"
13806 turned into "k". */
13807 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13810 /* If not, try comparing based on numerical designation alone.
13811 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13812 if (TOLOWER (*given
) == 'r')
13814 if (!ISDIGIT (*given
))
13817 /* Skip over some well-known prefixes in the canonical name,
13818 hoping to find a number there too. */
13819 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13821 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13823 else if (TOLOWER (canonical
[0]) == 'r')
13826 return mips_strict_matching_cpu_name_p (canonical
, given
);
13830 /* Parse an option that takes the name of a processor as its argument.
13831 OPTION is the name of the option and CPU_STRING is the argument.
13832 Return the corresponding processor enumeration if the CPU_STRING is
13833 recognized, otherwise report an error and return null.
13835 A similar function exists in GCC. */
13837 static const struct mips_cpu_info
*
13838 mips_parse_cpu (const char *option
, const char *cpu_string
)
13840 const struct mips_cpu_info
*p
;
13842 /* 'from-abi' selects the most compatible architecture for the given
13843 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13844 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13845 version. Look first at the -mgp options, if given, otherwise base
13846 the choice on MIPS_DEFAULT_64BIT.
13848 Treat NO_ABI like the EABIs. One reason to do this is that the
13849 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13850 architecture. This code picks MIPS I for 'mips' and MIPS III for
13851 'mips64', just as we did in the days before 'from-abi'. */
13852 if (strcasecmp (cpu_string
, "from-abi") == 0)
13854 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13855 return mips_cpu_info_from_isa (ISA_MIPS1
);
13857 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13858 return mips_cpu_info_from_isa (ISA_MIPS3
);
13860 if (file_mips_gp32
>= 0)
13861 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13863 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13868 /* 'default' has traditionally been a no-op. Probably not very useful. */
13869 if (strcasecmp (cpu_string
, "default") == 0)
13872 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13873 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13876 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13880 /* Return the canonical processor information for ISA (a member of the
13881 ISA_MIPS* enumeration). */
13883 static const struct mips_cpu_info
*
13884 mips_cpu_info_from_isa (int isa
)
13888 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13889 if (mips_cpu_info_table
[i
].is_isa
13890 && isa
== mips_cpu_info_table
[i
].isa
)
13891 return (&mips_cpu_info_table
[i
]);
13896 static const struct mips_cpu_info
*
13897 mips_cpu_info_from_arch (int arch
)
13901 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13902 if (arch
== mips_cpu_info_table
[i
].cpu
)
13903 return (&mips_cpu_info_table
[i
]);
13909 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13913 fprintf (stream
, "%24s", "");
13918 fprintf (stream
, ", ");
13922 if (*col_p
+ strlen (string
) > 72)
13924 fprintf (stream
, "\n%24s", "");
13928 fprintf (stream
, "%s", string
);
13929 *col_p
+= strlen (string
);
13935 md_show_usage (FILE *stream
)
13940 fprintf (stream
, _("\
13942 -EB generate big endian output\n\
13943 -EL generate little endian output\n\
13944 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13945 -G NUM allow referencing objects up to NUM bytes\n\
13946 implicitly with the gp register [default 8]\n"));
13947 fprintf (stream
, _("\
13948 -mips1 generate MIPS ISA I instructions\n\
13949 -mips2 generate MIPS ISA II instructions\n\
13950 -mips3 generate MIPS ISA III instructions\n\
13951 -mips4 generate MIPS ISA IV instructions\n\
13952 -mips5 generate MIPS ISA V instructions\n\
13953 -mips32 generate MIPS32 ISA instructions\n\
13954 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13955 -mips64 generate MIPS64 ISA instructions\n\
13956 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13957 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13961 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13962 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13963 show (stream
, "from-abi", &column
, &first
);
13964 fputc ('\n', stream
);
13966 fprintf (stream
, _("\
13967 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13968 -no-mCPU don't generate code specific to CPU.\n\
13969 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13973 show (stream
, "3900", &column
, &first
);
13974 show (stream
, "4010", &column
, &first
);
13975 show (stream
, "4100", &column
, &first
);
13976 show (stream
, "4650", &column
, &first
);
13977 fputc ('\n', stream
);
13979 fprintf (stream
, _("\
13980 -mips16 generate mips16 instructions\n\
13981 -no-mips16 do not generate mips16 instructions\n"));
13982 fprintf (stream
, _("\
13983 -mfix-vr4120 work around certain VR4120 errata\n\
13984 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
13985 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13986 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13987 -mno-shared optimize output for executables\n\
13988 -msym32 assume all symbols have 32-bit values\n\
13989 -O0 remove unneeded NOPs, do not swap branches\n\
13990 -O remove unneeded NOPs and swap branches\n\
13991 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13992 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13993 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13995 fprintf (stream
, _("\
13996 -KPIC, -call_shared generate SVR4 position independent code\n\
13997 -non_shared do not generate position independent code\n\
13998 -xgot assume a 32 bit GOT\n\
13999 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14000 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14002 -mabi=ABI create ABI conformant object file for:\n"));
14006 show (stream
, "32", &column
, &first
);
14007 show (stream
, "o64", &column
, &first
);
14008 show (stream
, "n32", &column
, &first
);
14009 show (stream
, "64", &column
, &first
);
14010 show (stream
, "eabi", &column
, &first
);
14012 fputc ('\n', stream
);
14014 fprintf (stream
, _("\
14015 -32 create o32 ABI object file (default)\n\
14016 -n32 create n32 ABI object file\n\
14017 -64 create 64 ABI object file\n"));
14022 mips_dwarf2_format (void)
14024 if (mips_abi
== N64_ABI
)
14027 return dwarf2_format_64bit_irix
;
14029 return dwarf2_format_64bit
;
14033 return dwarf2_format_32bit
;
14037 mips_dwarf2_addr_size (void)
14039 if (mips_abi
== N64_ABI
)
14045 /* Standard calling conventions leave the CFA at SP on entry. */
14047 mips_cfi_frame_initial_instructions (void)
14049 cfi_add_CFA_def_cfa_register (SP
);