1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether in the 32-bit
1155 instruction mode, whether the branch is unconditional, whether it is
1156 compact, whether there is no delay-slot instruction available to fill
1157 in, whether it stores the link address implicitly in $ra, whether
1158 relaxation of out-of-range 32-bit branches to a sequence of
1159 instructions is enabled, and whether the displacement of a branch is
1160 too large to fit as an immediate argument of a 16-bit and a 32-bit
1161 branch, respectively. */
1162 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, \
1163 uncond, compact, link, nods, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((insn32) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
1172 | ((nods) ? 0x20000 : 0) \
1173 | ((relax32) ? 0x40000 : 0) \
1174 | ((toofar16) ? 0x80000 : 0) \
1175 | ((toofar32) ? 0x100000 : 0))
1176 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1177 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1178 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1179 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
1183 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0)
1184 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0)
1187 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000)
1188 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000)
1189 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0)
1190 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000)
1191 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000)
1193 /* Sign-extend 16-bit value X. */
1194 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1196 /* Is the given value a sign-extended 32-bit value? */
1197 #define IS_SEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1201 /* Is the given value a sign-extended 16-bit value? */
1202 #define IS_SEXT_16BIT_NUM(x) \
1203 (((x) &~ (offsetT) 0x7fff) == 0 \
1204 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1206 /* Is the given value a sign-extended 12-bit value? */
1207 #define IS_SEXT_12BIT_NUM(x) \
1208 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1210 /* Is the given value a sign-extended 9-bit value? */
1211 #define IS_SEXT_9BIT_NUM(x) \
1212 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1214 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1215 #define IS_ZEXT_32BIT_NUM(x) \
1216 (((x) &~ (offsetT) 0xffffffff) == 0 \
1217 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1219 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1221 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1222 (((STRUCT) >> (SHIFT)) & (MASK))
1224 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1225 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1227 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1228 : EXTRACT_BITS ((INSN).insn_opcode, \
1229 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1230 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1231 EXTRACT_BITS ((INSN).insn_opcode, \
1232 MIPS16OP_MASK_##FIELD, \
1233 MIPS16OP_SH_##FIELD)
1235 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1236 #define MIPS16_EXTEND (0xf000U << 16)
1238 /* Whether or not we are emitting a branch-likely macro. */
1239 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1241 /* Global variables used when generating relaxable macros. See the
1242 comment above RELAX_ENCODE for more details about how relaxation
1245 /* 0 if we're not emitting a relaxable macro.
1246 1 if we're emitting the first of the two relaxation alternatives.
1247 2 if we're emitting the second alternative. */
1250 /* The first relaxable fixup in the current frag. (In other words,
1251 the first fixup that refers to relaxable code.) */
1254 /* sizes[0] says how many bytes of the first alternative are stored in
1255 the current frag. Likewise sizes[1] for the second alternative. */
1256 unsigned int sizes
[2];
1258 /* The symbol on which the choice of sequence depends. */
1262 /* Global variables used to decide whether a macro needs a warning. */
1264 /* True if the macro is in a branch delay slot. */
1265 bfd_boolean delay_slot_p
;
1267 /* Set to the length in bytes required if the macro is in a delay slot
1268 that requires a specific length of instruction, otherwise zero. */
1269 unsigned int delay_slot_length
;
1271 /* For relaxable macros, sizes[0] is the length of the first alternative
1272 in bytes and sizes[1] is the length of the second alternative.
1273 For non-relaxable macros, both elements give the length of the
1275 unsigned int sizes
[2];
1277 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1278 instruction of the first alternative in bytes and first_insn_sizes[1]
1279 is the length of the first instruction of the second alternative.
1280 For non-relaxable macros, both elements give the length of the first
1281 instruction in bytes.
1283 Set to zero if we haven't yet seen the first instruction. */
1284 unsigned int first_insn_sizes
[2];
1286 /* For relaxable macros, insns[0] is the number of instructions for the
1287 first alternative and insns[1] is the number of instructions for the
1290 For non-relaxable macros, both elements give the number of
1291 instructions for the macro. */
1292 unsigned int insns
[2];
1294 /* The first variant frag for this macro. */
1296 } mips_macro_warning
;
1298 /* Prototypes for static functions. */
1300 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1302 static void append_insn
1303 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1304 bfd_boolean expansionp
);
1305 static void mips_no_prev_insn (void);
1306 static void macro_build (expressionS
*, const char *, const char *, ...);
1307 static void mips16_macro_build
1308 (expressionS
*, const char *, const char *, va_list *);
1309 static void load_register (int, expressionS
*, int);
1310 static void macro_start (void);
1311 static void macro_end (void);
1312 static void macro (struct mips_cl_insn
*ip
, char *str
);
1313 static void mips16_macro (struct mips_cl_insn
* ip
);
1314 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1315 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1316 static void mips16_immed
1317 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1318 unsigned int, unsigned long *);
1319 static size_t my_getSmallExpression
1320 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1321 static void my_getExpression (expressionS
*, char *);
1322 static void s_align (int);
1323 static void s_change_sec (int);
1324 static void s_change_section (int);
1325 static void s_cons (int);
1326 static void s_float_cons (int);
1327 static void s_mips_globl (int);
1328 static void s_option (int);
1329 static void s_mipsset (int);
1330 static void s_abicalls (int);
1331 static void s_cpload (int);
1332 static void s_cpsetup (int);
1333 static void s_cplocal (int);
1334 static void s_cprestore (int);
1335 static void s_cpreturn (int);
1336 static void s_dtprelword (int);
1337 static void s_dtpreldword (int);
1338 static void s_tprelword (int);
1339 static void s_tpreldword (int);
1340 static void s_gpvalue (int);
1341 static void s_gpword (int);
1342 static void s_gpdword (int);
1343 static void s_ehword (int);
1344 static void s_cpadd (int);
1345 static void s_insn (int);
1346 static void s_nan (int);
1347 static void s_module (int);
1348 static void s_mips_ent (int);
1349 static void s_mips_end (int);
1350 static void s_mips_frame (int);
1351 static void s_mips_mask (int reg_type
);
1352 static void s_mips_stab (int);
1353 static void s_mips_weakext (int);
1354 static void s_mips_file (int);
1355 static void s_mips_loc (int);
1356 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1357 static int relaxed_branch_length (fragS
*, asection
*, int);
1358 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1359 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1360 static void file_mips_check_options (void);
1362 /* Table and functions used to map between CPU/ISA names, and
1363 ISA levels, and CPU numbers. */
1365 struct mips_cpu_info
1367 const char *name
; /* CPU or ISA name. */
1368 int flags
; /* MIPS_CPU_* flags. */
1369 int ase
; /* Set of ASEs implemented by the CPU. */
1370 int isa
; /* ISA level. */
1371 int cpu
; /* CPU number (default CPU if ISA). */
1374 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1376 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1377 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1378 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1380 /* Command-line options. */
1381 const char *md_shortopts
= "O::g::G:";
1385 OPTION_MARCH
= OPTION_MD_BASE
,
1417 OPTION_NO_SMARTMIPS
,
1427 OPTION_NO_MICROMIPS
,
1430 OPTION_COMPAT_ARCH_BASE
,
1439 OPTION_M7000_HILO_FIX
,
1440 OPTION_MNO_7000_HILO_FIX
,
1444 OPTION_NO_FIX_RM7000
,
1445 OPTION_FIX_LOONGSON2F_JUMP
,
1446 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1447 OPTION_FIX_LOONGSON2F_NOP
,
1448 OPTION_NO_FIX_LOONGSON2F_NOP
,
1450 OPTION_NO_FIX_VR4120
,
1452 OPTION_NO_FIX_VR4130
,
1453 OPTION_FIX_CN63XXP1
,
1454 OPTION_NO_FIX_CN63XXP1
,
1461 OPTION_CONSTRUCT_FLOATS
,
1462 OPTION_NO_CONSTRUCT_FLOATS
,
1466 OPTION_RELAX_BRANCH
,
1467 OPTION_NO_RELAX_BRANCH
,
1476 OPTION_SINGLE_FLOAT
,
1477 OPTION_DOUBLE_FLOAT
,
1490 OPTION_MVXWORKS_PIC
,
1493 OPTION_NO_ODD_SPREG
,
1497 struct option md_longopts
[] =
1499 /* Options which specify architecture. */
1500 {"march", required_argument
, NULL
, OPTION_MARCH
},
1501 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1502 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1503 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1504 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1505 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1506 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1507 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1508 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1509 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1510 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1511 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1512 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1513 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1514 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1515 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1516 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1517 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1519 /* Options which specify Application Specific Extensions (ASEs). */
1520 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1521 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1522 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1523 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1524 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1525 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1526 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1527 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1528 {"mmt", no_argument
, NULL
, OPTION_MT
},
1529 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1530 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1531 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1532 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1533 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1534 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1535 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1536 {"meva", no_argument
, NULL
, OPTION_EVA
},
1537 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1538 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1539 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1540 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1541 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1542 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1543 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1544 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1545 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1546 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1547 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1549 /* Old-style architecture options. Don't add more of these. */
1550 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1551 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1552 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1553 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1554 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1555 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1556 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1557 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1559 /* Options which enable bug fixes. */
1560 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1561 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1562 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1563 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1564 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1565 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1566 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1567 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1568 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1569 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1570 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1571 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1572 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1573 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1574 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1575 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1576 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1578 /* Miscellaneous options. */
1579 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1580 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1581 {"break", no_argument
, NULL
, OPTION_BREAK
},
1582 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1583 {"EB", no_argument
, NULL
, OPTION_EB
},
1584 {"EL", no_argument
, NULL
, OPTION_EL
},
1585 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1586 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1587 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1588 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1589 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1590 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1591 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1592 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1593 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1594 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1595 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1596 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1597 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1598 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1599 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1600 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1601 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1602 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1603 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1604 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1605 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1607 /* Strictly speaking this next option is ELF specific,
1608 but we allow it for other ports as well in order to
1609 make testing easier. */
1610 {"32", no_argument
, NULL
, OPTION_32
},
1612 /* ELF-specific options. */
1613 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1614 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1615 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1616 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1617 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1618 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1619 {"n32", no_argument
, NULL
, OPTION_N32
},
1620 {"64", no_argument
, NULL
, OPTION_64
},
1621 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1622 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1623 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1624 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1625 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1626 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1628 {NULL
, no_argument
, NULL
, 0}
1630 size_t md_longopts_size
= sizeof (md_longopts
);
1632 /* Information about either an Application Specific Extension or an
1633 optional architecture feature that, for simplicity, we treat in the
1634 same way as an ASE. */
1637 /* The name of the ASE, used in both the command-line and .set options. */
1640 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1641 and 64-bit architectures, the flags here refer to the subset that
1642 is available on both. */
1645 /* The ASE_* flag used for instructions that are available on 64-bit
1646 architectures but that are not included in FLAGS. */
1647 unsigned int flags64
;
1649 /* The command-line options that turn the ASE on and off. */
1653 /* The minimum required architecture revisions for MIPS32, MIPS64,
1654 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1657 int micromips32_rev
;
1658 int micromips64_rev
;
1660 /* The architecture where the ASE was removed or -1 if the extension has not
1665 /* A table of all supported ASEs. */
1666 static const struct mips_ase mips_ases
[] = {
1667 { "dsp", ASE_DSP
, ASE_DSP64
,
1668 OPTION_DSP
, OPTION_NO_DSP
,
1672 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1673 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1677 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1678 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1682 { "eva", ASE_EVA
, 0,
1683 OPTION_EVA
, OPTION_NO_EVA
,
1687 { "mcu", ASE_MCU
, 0,
1688 OPTION_MCU
, OPTION_NO_MCU
,
1692 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1693 { "mdmx", ASE_MDMX
, 0,
1694 OPTION_MDMX
, OPTION_NO_MDMX
,
1698 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1699 { "mips3d", ASE_MIPS3D
, 0,
1700 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1705 OPTION_MT
, OPTION_NO_MT
,
1709 { "smartmips", ASE_SMARTMIPS
, 0,
1710 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1714 { "virt", ASE_VIRT
, ASE_VIRT64
,
1715 OPTION_VIRT
, OPTION_NO_VIRT
,
1719 { "msa", ASE_MSA
, ASE_MSA64
,
1720 OPTION_MSA
, OPTION_NO_MSA
,
1724 { "xpa", ASE_XPA
, 0,
1725 OPTION_XPA
, OPTION_NO_XPA
,
1730 /* The set of ASEs that require -mfp64. */
1731 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1733 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1734 static const unsigned int mips_ase_groups
[] = {
1735 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1740 The following pseudo-ops from the Kane and Heinrich MIPS book
1741 should be defined here, but are currently unsupported: .alias,
1742 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1744 The following pseudo-ops from the Kane and Heinrich MIPS book are
1745 specific to the type of debugging information being generated, and
1746 should be defined by the object format: .aent, .begin, .bend,
1747 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1750 The following pseudo-ops from the Kane and Heinrich MIPS book are
1751 not MIPS CPU specific, but are also not specific to the object file
1752 format. This file is probably the best place to define them, but
1753 they are not currently supported: .asm0, .endr, .lab, .struct. */
1755 static const pseudo_typeS mips_pseudo_table
[] =
1757 /* MIPS specific pseudo-ops. */
1758 {"option", s_option
, 0},
1759 {"set", s_mipsset
, 0},
1760 {"rdata", s_change_sec
, 'r'},
1761 {"sdata", s_change_sec
, 's'},
1762 {"livereg", s_ignore
, 0},
1763 {"abicalls", s_abicalls
, 0},
1764 {"cpload", s_cpload
, 0},
1765 {"cpsetup", s_cpsetup
, 0},
1766 {"cplocal", s_cplocal
, 0},
1767 {"cprestore", s_cprestore
, 0},
1768 {"cpreturn", s_cpreturn
, 0},
1769 {"dtprelword", s_dtprelword
, 0},
1770 {"dtpreldword", s_dtpreldword
, 0},
1771 {"tprelword", s_tprelword
, 0},
1772 {"tpreldword", s_tpreldword
, 0},
1773 {"gpvalue", s_gpvalue
, 0},
1774 {"gpword", s_gpword
, 0},
1775 {"gpdword", s_gpdword
, 0},
1776 {"ehword", s_ehword
, 0},
1777 {"cpadd", s_cpadd
, 0},
1778 {"insn", s_insn
, 0},
1780 {"module", s_module
, 0},
1782 /* Relatively generic pseudo-ops that happen to be used on MIPS
1784 {"asciiz", stringer
, 8 + 1},
1785 {"bss", s_change_sec
, 'b'},
1787 {"half", s_cons
, 1},
1788 {"dword", s_cons
, 3},
1789 {"weakext", s_mips_weakext
, 0},
1790 {"origin", s_org
, 0},
1791 {"repeat", s_rept
, 0},
1793 /* For MIPS this is non-standard, but we define it for consistency. */
1794 {"sbss", s_change_sec
, 'B'},
1796 /* These pseudo-ops are defined in read.c, but must be overridden
1797 here for one reason or another. */
1798 {"align", s_align
, 0},
1799 {"byte", s_cons
, 0},
1800 {"data", s_change_sec
, 'd'},
1801 {"double", s_float_cons
, 'd'},
1802 {"float", s_float_cons
, 'f'},
1803 {"globl", s_mips_globl
, 0},
1804 {"global", s_mips_globl
, 0},
1805 {"hword", s_cons
, 1},
1807 {"long", s_cons
, 2},
1808 {"octa", s_cons
, 4},
1809 {"quad", s_cons
, 3},
1810 {"section", s_change_section
, 0},
1811 {"short", s_cons
, 1},
1812 {"single", s_float_cons
, 'f'},
1813 {"stabd", s_mips_stab
, 'd'},
1814 {"stabn", s_mips_stab
, 'n'},
1815 {"stabs", s_mips_stab
, 's'},
1816 {"text", s_change_sec
, 't'},
1817 {"word", s_cons
, 2},
1819 { "extern", ecoff_directive_extern
, 0},
1824 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1826 /* These pseudo-ops should be defined by the object file format.
1827 However, a.out doesn't support them, so we have versions here. */
1828 {"aent", s_mips_ent
, 1},
1829 {"bgnb", s_ignore
, 0},
1830 {"end", s_mips_end
, 0},
1831 {"endb", s_ignore
, 0},
1832 {"ent", s_mips_ent
, 0},
1833 {"file", s_mips_file
, 0},
1834 {"fmask", s_mips_mask
, 'F'},
1835 {"frame", s_mips_frame
, 0},
1836 {"loc", s_mips_loc
, 0},
1837 {"mask", s_mips_mask
, 'R'},
1838 {"verstamp", s_ignore
, 0},
1842 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1843 purpose of the `.dc.a' internal pseudo-op. */
1846 mips_address_bytes (void)
1848 file_mips_check_options ();
1849 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1852 extern void pop_insert (const pseudo_typeS
*);
1855 mips_pop_insert (void)
1857 pop_insert (mips_pseudo_table
);
1858 if (! ECOFF_DEBUGGING
)
1859 pop_insert (mips_nonecoff_pseudo_table
);
1862 /* Symbols labelling the current insn. */
1864 struct insn_label_list
1866 struct insn_label_list
*next
;
1870 static struct insn_label_list
*free_insn_labels
;
1871 #define label_list tc_segment_info_data.labels
1873 static void mips_clear_insn_labels (void);
1874 static void mips_mark_labels (void);
1875 static void mips_compressed_mark_labels (void);
1878 mips_clear_insn_labels (void)
1880 struct insn_label_list
**pl
;
1881 segment_info_type
*si
;
1885 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1888 si
= seg_info (now_seg
);
1889 *pl
= si
->label_list
;
1890 si
->label_list
= NULL
;
1894 /* Mark instruction labels in MIPS16/microMIPS mode. */
1897 mips_mark_labels (void)
1899 if (HAVE_CODE_COMPRESSION
)
1900 mips_compressed_mark_labels ();
1903 static char *expr_end
;
1905 /* An expression in a macro instruction. This is set by mips_ip and
1906 mips16_ip and when populated is always an O_constant. */
1908 static expressionS imm_expr
;
1910 /* The relocatable field in an instruction and the relocs associated
1911 with it. These variables are used for instructions like LUI and
1912 JAL as well as true offsets. They are also used for address
1913 operands in macros. */
1915 static expressionS offset_expr
;
1916 static bfd_reloc_code_real_type offset_reloc
[3]
1917 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1919 /* This is set to the resulting size of the instruction to be produced
1920 by mips16_ip if an explicit extension is used or by mips_ip if an
1921 explicit size is supplied. */
1923 static unsigned int forced_insn_length
;
1925 /* True if we are assembling an instruction. All dot symbols defined during
1926 this time should be treated as code labels. */
1928 static bfd_boolean mips_assembling_insn
;
1930 /* The pdr segment for per procedure frame/regmask info. Not used for
1933 static segT pdr_seg
;
1935 /* The default target format to use. */
1937 #if defined (TE_FreeBSD)
1938 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1939 #elif defined (TE_TMIPS)
1940 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1942 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1946 mips_target_format (void)
1948 switch (OUTPUT_FLAVOR
)
1950 case bfd_target_elf_flavour
:
1952 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1953 return (target_big_endian
1954 ? "elf32-bigmips-vxworks"
1955 : "elf32-littlemips-vxworks");
1957 return (target_big_endian
1958 ? (HAVE_64BIT_OBJECTS
1959 ? ELF_TARGET ("elf64-", "big")
1961 ? ELF_TARGET ("elf32-n", "big")
1962 : ELF_TARGET ("elf32-", "big")))
1963 : (HAVE_64BIT_OBJECTS
1964 ? ELF_TARGET ("elf64-", "little")
1966 ? ELF_TARGET ("elf32-n", "little")
1967 : ELF_TARGET ("elf32-", "little"))));
1974 /* Return the ISA revision that is currently in use, or 0 if we are
1975 generating code for MIPS V or below. */
1980 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1983 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1986 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1989 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
1992 /* microMIPS implies revision 2 or above. */
1993 if (mips_opts
.micromips
)
1996 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2002 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2005 mips_ase_mask (unsigned int flags
)
2009 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2010 if (flags
& mips_ase_groups
[i
])
2011 flags
|= mips_ase_groups
[i
];
2015 /* Check whether the current ISA supports ASE. Issue a warning if
2019 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2023 static unsigned int warned_isa
;
2024 static unsigned int warned_fp32
;
2026 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2027 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2029 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2030 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2031 && (warned_isa
& ase
->flags
) != ase
->flags
)
2033 warned_isa
|= ase
->flags
;
2034 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2035 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2037 as_warn (_("the %d-bit %s architecture does not support the"
2038 " `%s' extension"), size
, base
, ase
->name
);
2040 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2041 ase
->name
, base
, size
, min_rev
);
2043 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2044 && (warned_isa
& ase
->flags
) != ase
->flags
)
2046 warned_isa
|= ase
->flags
;
2047 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2048 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2049 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2050 ase
->name
, base
, size
, ase
->rem_rev
);
2053 if ((ase
->flags
& FP64_ASES
)
2054 && mips_opts
.fp
!= 64
2055 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2057 warned_fp32
|= ase
->flags
;
2058 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2062 /* Check all enabled ASEs to see whether they are supported by the
2063 chosen architecture. */
2066 mips_check_isa_supports_ases (void)
2068 unsigned int i
, mask
;
2070 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2072 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2073 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2074 mips_check_isa_supports_ase (&mips_ases
[i
]);
2078 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2079 that were affected. */
2082 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2083 bfd_boolean enabled_p
)
2087 mask
= mips_ase_mask (ase
->flags
);
2090 opts
->ase
|= ase
->flags
;
2094 /* Return the ASE called NAME, or null if none. */
2096 static const struct mips_ase
*
2097 mips_lookup_ase (const char *name
)
2101 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2102 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2103 return &mips_ases
[i
];
2107 /* Return the length of a microMIPS instruction in bytes. If bits of
2108 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2109 otherwise it is a 32-bit instruction. */
2111 static inline unsigned int
2112 micromips_insn_length (const struct mips_opcode
*mo
)
2114 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2117 /* Return the length of MIPS16 instruction OPCODE. */
2119 static inline unsigned int
2120 mips16_opcode_length (unsigned long opcode
)
2122 return (opcode
>> 16) == 0 ? 2 : 4;
2125 /* Return the length of instruction INSN. */
2127 static inline unsigned int
2128 insn_length (const struct mips_cl_insn
*insn
)
2130 if (mips_opts
.micromips
)
2131 return micromips_insn_length (insn
->insn_mo
);
2132 else if (mips_opts
.mips16
)
2133 return mips16_opcode_length (insn
->insn_opcode
);
2138 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2141 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2146 insn
->insn_opcode
= mo
->match
;
2149 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2150 insn
->fixp
[i
] = NULL
;
2151 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2152 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2153 insn
->mips16_absolute_jump_p
= 0;
2154 insn
->complete_p
= 0;
2155 insn
->cleared_p
= 0;
2158 /* Get a list of all the operands in INSN. */
2160 static const struct mips_operand_array
*
2161 insn_operands (const struct mips_cl_insn
*insn
)
2163 if (insn
->insn_mo
>= &mips_opcodes
[0]
2164 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2165 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2167 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2168 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2169 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2171 if (insn
->insn_mo
>= µmips_opcodes
[0]
2172 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2173 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2178 /* Get a description of operand OPNO of INSN. */
2180 static const struct mips_operand
*
2181 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2183 const struct mips_operand_array
*operands
;
2185 operands
= insn_operands (insn
);
2186 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2188 return operands
->operand
[opno
];
2191 /* Install UVAL as the value of OPERAND in INSN. */
2194 insn_insert_operand (struct mips_cl_insn
*insn
,
2195 const struct mips_operand
*operand
, unsigned int uval
)
2197 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2200 /* Extract the value of OPERAND from INSN. */
2202 static inline unsigned
2203 insn_extract_operand (const struct mips_cl_insn
*insn
,
2204 const struct mips_operand
*operand
)
2206 return mips_extract_operand (operand
, insn
->insn_opcode
);
2209 /* Record the current MIPS16/microMIPS mode in now_seg. */
2212 mips_record_compressed_mode (void)
2214 segment_info_type
*si
;
2216 si
= seg_info (now_seg
);
2217 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2218 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2219 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2220 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2223 /* Read a standard MIPS instruction from BUF. */
2225 static unsigned long
2226 read_insn (char *buf
)
2228 if (target_big_endian
)
2229 return bfd_getb32 ((bfd_byte
*) buf
);
2231 return bfd_getl32 ((bfd_byte
*) buf
);
2234 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2238 write_insn (char *buf
, unsigned int insn
)
2240 md_number_to_chars (buf
, insn
, 4);
2244 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2245 has length LENGTH. */
2247 static unsigned long
2248 read_compressed_insn (char *buf
, unsigned int length
)
2254 for (i
= 0; i
< length
; i
+= 2)
2257 if (target_big_endian
)
2258 insn
|= bfd_getb16 ((char *) buf
);
2260 insn
|= bfd_getl16 ((char *) buf
);
2266 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2267 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2270 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2274 for (i
= 0; i
< length
; i
+= 2)
2275 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2276 return buf
+ length
;
2279 /* Install INSN at the location specified by its "frag" and "where" fields. */
2282 install_insn (const struct mips_cl_insn
*insn
)
2284 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2285 if (HAVE_CODE_COMPRESSION
)
2286 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2288 write_insn (f
, insn
->insn_opcode
);
2289 mips_record_compressed_mode ();
2292 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2293 and install the opcode in the new location. */
2296 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2301 insn
->where
= where
;
2302 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2303 if (insn
->fixp
[i
] != NULL
)
2305 insn
->fixp
[i
]->fx_frag
= frag
;
2306 insn
->fixp
[i
]->fx_where
= where
;
2308 install_insn (insn
);
2311 /* Add INSN to the end of the output. */
2314 add_fixed_insn (struct mips_cl_insn
*insn
)
2316 char *f
= frag_more (insn_length (insn
));
2317 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2320 /* Start a variant frag and move INSN to the start of the variant part,
2321 marking it as fixed. The other arguments are as for frag_var. */
2324 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2325 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2327 frag_grow (max_chars
);
2328 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2330 frag_var (rs_machine_dependent
, max_chars
, var
,
2331 subtype
, symbol
, offset
, NULL
);
2334 /* Insert N copies of INSN into the history buffer, starting at
2335 position FIRST. Neither FIRST nor N need to be clipped. */
2338 insert_into_history (unsigned int first
, unsigned int n
,
2339 const struct mips_cl_insn
*insn
)
2341 if (mips_relax
.sequence
!= 2)
2345 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2347 history
[i
] = history
[i
- n
];
2353 /* Clear the error in insn_error. */
2356 clear_insn_error (void)
2358 memset (&insn_error
, 0, sizeof (insn_error
));
2361 /* Possibly record error message MSG for the current instruction.
2362 If the error is about a particular argument, ARGNUM is the 1-based
2363 number of that argument, otherwise it is 0. FORMAT is the format
2364 of MSG. Return true if MSG was used, false if the current message
2368 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2373 /* Give priority to errors against specific arguments, and to
2374 the first whole-instruction message. */
2380 /* Keep insn_error if it is against a later argument. */
2381 if (argnum
< insn_error
.min_argnum
)
2384 /* If both errors are against the same argument but are different,
2385 give up on reporting a specific error for this argument.
2386 See the comment about mips_insn_error for details. */
2387 if (argnum
== insn_error
.min_argnum
2389 && strcmp (insn_error
.msg
, msg
) != 0)
2392 insn_error
.min_argnum
+= 1;
2396 insn_error
.min_argnum
= argnum
;
2397 insn_error
.format
= format
;
2398 insn_error
.msg
= msg
;
2402 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2403 as for set_insn_error_format. */
2406 set_insn_error (int argnum
, const char *msg
)
2408 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2411 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2412 as for set_insn_error_format. */
2415 set_insn_error_i (int argnum
, const char *msg
, int i
)
2417 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2421 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2422 are as for set_insn_error_format. */
2425 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2427 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2429 insn_error
.u
.ss
[0] = s1
;
2430 insn_error
.u
.ss
[1] = s2
;
2434 /* Report the error in insn_error, which is against assembly code STR. */
2437 report_insn_error (const char *str
)
2439 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2441 switch (insn_error
.format
)
2448 as_bad (msg
, insn_error
.u
.i
, str
);
2452 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2456 free ((char *) msg
);
2459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2460 the idea is to make it obvious at a glance that each errata is
2464 init_vr4120_conflicts (void)
2466 #define CONFLICT(FIRST, SECOND) \
2467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2469 /* Errata 21 - [D]DIV[U] after [D]MACC */
2470 CONFLICT (MACC
, DIV
);
2471 CONFLICT (DMACC
, DIV
);
2473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2474 CONFLICT (DMULT
, DMULT
);
2475 CONFLICT (DMULT
, DMACC
);
2476 CONFLICT (DMACC
, DMULT
);
2477 CONFLICT (DMACC
, DMACC
);
2479 /* Errata 24 - MT{LO,HI} after [D]MACC */
2480 CONFLICT (MACC
, MTHILO
);
2481 CONFLICT (DMACC
, MTHILO
);
2483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2484 instruction is executed immediately after a MACC or DMACC
2485 instruction, the result of [either instruction] is incorrect." */
2486 CONFLICT (MACC
, MULT
);
2487 CONFLICT (MACC
, DMULT
);
2488 CONFLICT (DMACC
, MULT
);
2489 CONFLICT (DMACC
, DMULT
);
2491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2493 DDIV or DDIVU instruction, the result of the MACC or
2494 DMACC instruction is incorrect.". */
2495 CONFLICT (DMULT
, MACC
);
2496 CONFLICT (DMULT
, DMACC
);
2497 CONFLICT (DIV
, MACC
);
2498 CONFLICT (DIV
, DMACC
);
2508 #define RNUM_MASK 0x00000ff
2509 #define RTYPE_MASK 0x0ffff00
2510 #define RTYPE_NUM 0x0000100
2511 #define RTYPE_FPU 0x0000200
2512 #define RTYPE_FCC 0x0000400
2513 #define RTYPE_VEC 0x0000800
2514 #define RTYPE_GP 0x0001000
2515 #define RTYPE_CP0 0x0002000
2516 #define RTYPE_PC 0x0004000
2517 #define RTYPE_ACC 0x0008000
2518 #define RTYPE_CCC 0x0010000
2519 #define RTYPE_VI 0x0020000
2520 #define RTYPE_VF 0x0040000
2521 #define RTYPE_R5900_I 0x0080000
2522 #define RTYPE_R5900_Q 0x0100000
2523 #define RTYPE_R5900_R 0x0200000
2524 #define RTYPE_R5900_ACC 0x0400000
2525 #define RTYPE_MSA 0x0800000
2526 #define RWARN 0x8000000
2528 #define GENERIC_REGISTER_NUMBERS \
2529 {"$0", RTYPE_NUM | 0}, \
2530 {"$1", RTYPE_NUM | 1}, \
2531 {"$2", RTYPE_NUM | 2}, \
2532 {"$3", RTYPE_NUM | 3}, \
2533 {"$4", RTYPE_NUM | 4}, \
2534 {"$5", RTYPE_NUM | 5}, \
2535 {"$6", RTYPE_NUM | 6}, \
2536 {"$7", RTYPE_NUM | 7}, \
2537 {"$8", RTYPE_NUM | 8}, \
2538 {"$9", RTYPE_NUM | 9}, \
2539 {"$10", RTYPE_NUM | 10}, \
2540 {"$11", RTYPE_NUM | 11}, \
2541 {"$12", RTYPE_NUM | 12}, \
2542 {"$13", RTYPE_NUM | 13}, \
2543 {"$14", RTYPE_NUM | 14}, \
2544 {"$15", RTYPE_NUM | 15}, \
2545 {"$16", RTYPE_NUM | 16}, \
2546 {"$17", RTYPE_NUM | 17}, \
2547 {"$18", RTYPE_NUM | 18}, \
2548 {"$19", RTYPE_NUM | 19}, \
2549 {"$20", RTYPE_NUM | 20}, \
2550 {"$21", RTYPE_NUM | 21}, \
2551 {"$22", RTYPE_NUM | 22}, \
2552 {"$23", RTYPE_NUM | 23}, \
2553 {"$24", RTYPE_NUM | 24}, \
2554 {"$25", RTYPE_NUM | 25}, \
2555 {"$26", RTYPE_NUM | 26}, \
2556 {"$27", RTYPE_NUM | 27}, \
2557 {"$28", RTYPE_NUM | 28}, \
2558 {"$29", RTYPE_NUM | 29}, \
2559 {"$30", RTYPE_NUM | 30}, \
2560 {"$31", RTYPE_NUM | 31}
2562 #define FPU_REGISTER_NAMES \
2563 {"$f0", RTYPE_FPU | 0}, \
2564 {"$f1", RTYPE_FPU | 1}, \
2565 {"$f2", RTYPE_FPU | 2}, \
2566 {"$f3", RTYPE_FPU | 3}, \
2567 {"$f4", RTYPE_FPU | 4}, \
2568 {"$f5", RTYPE_FPU | 5}, \
2569 {"$f6", RTYPE_FPU | 6}, \
2570 {"$f7", RTYPE_FPU | 7}, \
2571 {"$f8", RTYPE_FPU | 8}, \
2572 {"$f9", RTYPE_FPU | 9}, \
2573 {"$f10", RTYPE_FPU | 10}, \
2574 {"$f11", RTYPE_FPU | 11}, \
2575 {"$f12", RTYPE_FPU | 12}, \
2576 {"$f13", RTYPE_FPU | 13}, \
2577 {"$f14", RTYPE_FPU | 14}, \
2578 {"$f15", RTYPE_FPU | 15}, \
2579 {"$f16", RTYPE_FPU | 16}, \
2580 {"$f17", RTYPE_FPU | 17}, \
2581 {"$f18", RTYPE_FPU | 18}, \
2582 {"$f19", RTYPE_FPU | 19}, \
2583 {"$f20", RTYPE_FPU | 20}, \
2584 {"$f21", RTYPE_FPU | 21}, \
2585 {"$f22", RTYPE_FPU | 22}, \
2586 {"$f23", RTYPE_FPU | 23}, \
2587 {"$f24", RTYPE_FPU | 24}, \
2588 {"$f25", RTYPE_FPU | 25}, \
2589 {"$f26", RTYPE_FPU | 26}, \
2590 {"$f27", RTYPE_FPU | 27}, \
2591 {"$f28", RTYPE_FPU | 28}, \
2592 {"$f29", RTYPE_FPU | 29}, \
2593 {"$f30", RTYPE_FPU | 30}, \
2594 {"$f31", RTYPE_FPU | 31}
2596 #define FPU_CONDITION_CODE_NAMES \
2597 {"$fcc0", RTYPE_FCC | 0}, \
2598 {"$fcc1", RTYPE_FCC | 1}, \
2599 {"$fcc2", RTYPE_FCC | 2}, \
2600 {"$fcc3", RTYPE_FCC | 3}, \
2601 {"$fcc4", RTYPE_FCC | 4}, \
2602 {"$fcc5", RTYPE_FCC | 5}, \
2603 {"$fcc6", RTYPE_FCC | 6}, \
2604 {"$fcc7", RTYPE_FCC | 7}
2606 #define COPROC_CONDITION_CODE_NAMES \
2607 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2608 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2609 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2610 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2611 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2612 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2613 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2614 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2616 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2617 {"$a4", RTYPE_GP | 8}, \
2618 {"$a5", RTYPE_GP | 9}, \
2619 {"$a6", RTYPE_GP | 10}, \
2620 {"$a7", RTYPE_GP | 11}, \
2621 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2622 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2623 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2624 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2625 {"$t0", RTYPE_GP | 12}, \
2626 {"$t1", RTYPE_GP | 13}, \
2627 {"$t2", RTYPE_GP | 14}, \
2628 {"$t3", RTYPE_GP | 15}
2630 #define O32_SYMBOLIC_REGISTER_NAMES \
2631 {"$t0", RTYPE_GP | 8}, \
2632 {"$t1", RTYPE_GP | 9}, \
2633 {"$t2", RTYPE_GP | 10}, \
2634 {"$t3", RTYPE_GP | 11}, \
2635 {"$t4", RTYPE_GP | 12}, \
2636 {"$t5", RTYPE_GP | 13}, \
2637 {"$t6", RTYPE_GP | 14}, \
2638 {"$t7", RTYPE_GP | 15}, \
2639 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2640 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2641 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2642 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2644 /* Remaining symbolic register names */
2645 #define SYMBOLIC_REGISTER_NAMES \
2646 {"$zero", RTYPE_GP | 0}, \
2647 {"$at", RTYPE_GP | 1}, \
2648 {"$AT", RTYPE_GP | 1}, \
2649 {"$v0", RTYPE_GP | 2}, \
2650 {"$v1", RTYPE_GP | 3}, \
2651 {"$a0", RTYPE_GP | 4}, \
2652 {"$a1", RTYPE_GP | 5}, \
2653 {"$a2", RTYPE_GP | 6}, \
2654 {"$a3", RTYPE_GP | 7}, \
2655 {"$s0", RTYPE_GP | 16}, \
2656 {"$s1", RTYPE_GP | 17}, \
2657 {"$s2", RTYPE_GP | 18}, \
2658 {"$s3", RTYPE_GP | 19}, \
2659 {"$s4", RTYPE_GP | 20}, \
2660 {"$s5", RTYPE_GP | 21}, \
2661 {"$s6", RTYPE_GP | 22}, \
2662 {"$s7", RTYPE_GP | 23}, \
2663 {"$t8", RTYPE_GP | 24}, \
2664 {"$t9", RTYPE_GP | 25}, \
2665 {"$k0", RTYPE_GP | 26}, \
2666 {"$kt0", RTYPE_GP | 26}, \
2667 {"$k1", RTYPE_GP | 27}, \
2668 {"$kt1", RTYPE_GP | 27}, \
2669 {"$gp", RTYPE_GP | 28}, \
2670 {"$sp", RTYPE_GP | 29}, \
2671 {"$s8", RTYPE_GP | 30}, \
2672 {"$fp", RTYPE_GP | 30}, \
2673 {"$ra", RTYPE_GP | 31}
2675 #define MIPS16_SPECIAL_REGISTER_NAMES \
2676 {"$pc", RTYPE_PC | 0}
2678 #define MDMX_VECTOR_REGISTER_NAMES \
2679 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2680 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2681 {"$v2", RTYPE_VEC | 2}, \
2682 {"$v3", RTYPE_VEC | 3}, \
2683 {"$v4", RTYPE_VEC | 4}, \
2684 {"$v5", RTYPE_VEC | 5}, \
2685 {"$v6", RTYPE_VEC | 6}, \
2686 {"$v7", RTYPE_VEC | 7}, \
2687 {"$v8", RTYPE_VEC | 8}, \
2688 {"$v9", RTYPE_VEC | 9}, \
2689 {"$v10", RTYPE_VEC | 10}, \
2690 {"$v11", RTYPE_VEC | 11}, \
2691 {"$v12", RTYPE_VEC | 12}, \
2692 {"$v13", RTYPE_VEC | 13}, \
2693 {"$v14", RTYPE_VEC | 14}, \
2694 {"$v15", RTYPE_VEC | 15}, \
2695 {"$v16", RTYPE_VEC | 16}, \
2696 {"$v17", RTYPE_VEC | 17}, \
2697 {"$v18", RTYPE_VEC | 18}, \
2698 {"$v19", RTYPE_VEC | 19}, \
2699 {"$v20", RTYPE_VEC | 20}, \
2700 {"$v21", RTYPE_VEC | 21}, \
2701 {"$v22", RTYPE_VEC | 22}, \
2702 {"$v23", RTYPE_VEC | 23}, \
2703 {"$v24", RTYPE_VEC | 24}, \
2704 {"$v25", RTYPE_VEC | 25}, \
2705 {"$v26", RTYPE_VEC | 26}, \
2706 {"$v27", RTYPE_VEC | 27}, \
2707 {"$v28", RTYPE_VEC | 28}, \
2708 {"$v29", RTYPE_VEC | 29}, \
2709 {"$v30", RTYPE_VEC | 30}, \
2710 {"$v31", RTYPE_VEC | 31}
2712 #define R5900_I_NAMES \
2713 {"$I", RTYPE_R5900_I | 0}
2715 #define R5900_Q_NAMES \
2716 {"$Q", RTYPE_R5900_Q | 0}
2718 #define R5900_R_NAMES \
2719 {"$R", RTYPE_R5900_R | 0}
2721 #define R5900_ACC_NAMES \
2722 {"$ACC", RTYPE_R5900_ACC | 0 }
2724 #define MIPS_DSP_ACCUMULATOR_NAMES \
2725 {"$ac0", RTYPE_ACC | 0}, \
2726 {"$ac1", RTYPE_ACC | 1}, \
2727 {"$ac2", RTYPE_ACC | 2}, \
2728 {"$ac3", RTYPE_ACC | 3}
2730 static const struct regname reg_names
[] = {
2731 GENERIC_REGISTER_NUMBERS
,
2733 FPU_CONDITION_CODE_NAMES
,
2734 COPROC_CONDITION_CODE_NAMES
,
2736 /* The $txx registers depends on the abi,
2737 these will be added later into the symbol table from
2738 one of the tables below once mips_abi is set after
2739 parsing of arguments from the command line. */
2740 SYMBOLIC_REGISTER_NAMES
,
2742 MIPS16_SPECIAL_REGISTER_NAMES
,
2743 MDMX_VECTOR_REGISTER_NAMES
,
2748 MIPS_DSP_ACCUMULATOR_NAMES
,
2752 static const struct regname reg_names_o32
[] = {
2753 O32_SYMBOLIC_REGISTER_NAMES
,
2757 static const struct regname reg_names_n32n64
[] = {
2758 N32N64_SYMBOLIC_REGISTER_NAMES
,
2762 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2763 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2764 of these register symbols, return the associated vector register,
2765 otherwise return SYMVAL itself. */
2768 mips_prefer_vec_regno (unsigned int symval
)
2770 if ((symval
& -2) == (RTYPE_GP
| 2))
2771 return RTYPE_VEC
| (symval
& 1);
2775 /* Return true if string [S, E) is a valid register name, storing its
2776 symbol value in *SYMVAL_PTR if so. */
2779 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2784 /* Terminate name. */
2788 /* Look up the name. */
2789 symbol
= symbol_find (s
);
2792 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2795 *symval_ptr
= S_GET_VALUE (symbol
);
2799 /* Return true if the string at *SPTR is a valid register name. Allow it
2800 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2803 When returning true, move *SPTR past the register, store the
2804 register's symbol value in *SYMVAL_PTR and the channel mask in
2805 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2806 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2807 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2810 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2811 unsigned int *channels_ptr
)
2815 unsigned int channels
, symval
, bit
;
2817 /* Find end of name. */
2819 if (is_name_beginner (*e
))
2821 while (is_part_of_name (*e
))
2825 if (!mips_parse_register_1 (s
, e
, &symval
))
2830 /* Eat characters from the end of the string that are valid
2831 channel suffixes. The preceding register must be $ACC or
2832 end with a digit, so there is no ambiguity. */
2835 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2836 if (m
> s
&& m
[-1] == *q
)
2843 || !mips_parse_register_1 (s
, m
, &symval
)
2844 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2849 *symval_ptr
= symval
;
2851 *channels_ptr
= channels
;
2855 /* Check if SPTR points at a valid register specifier according to TYPES.
2856 If so, then return 1, advance S to consume the specifier and store
2857 the register's number in REGNOP, otherwise return 0. */
2860 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2864 if (mips_parse_register (s
, ®no
, NULL
))
2866 if (types
& RTYPE_VEC
)
2867 regno
= mips_prefer_vec_regno (regno
);
2876 as_warn (_("unrecognized register name `%s'"), *s
);
2881 return regno
<= RNUM_MASK
;
2884 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2885 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2888 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2893 for (i
= 0; i
< 4; i
++)
2894 if (*s
== "xyzw"[i
])
2896 *channels
|= 1 << (3 - i
);
2902 /* Token types for parsed operand lists. */
2903 enum mips_operand_token_type
{
2904 /* A plain register, e.g. $f2. */
2907 /* A 4-bit XYZW channel mask. */
2910 /* A constant vector index, e.g. [1]. */
2913 /* A register vector index, e.g. [$2]. */
2916 /* A continuous range of registers, e.g. $s0-$s4. */
2919 /* A (possibly relocated) expression. */
2922 /* A floating-point value. */
2925 /* A single character. This can be '(', ')' or ',', but '(' only appears
2929 /* A doubled character, either "--" or "++". */
2932 /* The end of the operand list. */
2936 /* A parsed operand token. */
2937 struct mips_operand_token
2939 /* The type of token. */
2940 enum mips_operand_token_type type
;
2943 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2946 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2947 unsigned int channels
;
2949 /* The integer value of an OT_INTEGER_INDEX. */
2952 /* The two register symbol values involved in an OT_REG_RANGE. */
2954 unsigned int regno1
;
2955 unsigned int regno2
;
2958 /* The value of an OT_INTEGER. The value is represented as an
2959 expression and the relocation operators that were applied to
2960 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2961 relocation operators were used. */
2964 bfd_reloc_code_real_type relocs
[3];
2967 /* The binary data for an OT_FLOAT constant, and the number of bytes
2970 unsigned char data
[8];
2974 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2979 /* An obstack used to construct lists of mips_operand_tokens. */
2980 static struct obstack mips_operand_tokens
;
2982 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2985 mips_add_token (struct mips_operand_token
*token
,
2986 enum mips_operand_token_type type
)
2989 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2992 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2993 and OT_REG tokens for them if so, and return a pointer to the first
2994 unconsumed character. Return null otherwise. */
2997 mips_parse_base_start (char *s
)
2999 struct mips_operand_token token
;
3000 unsigned int regno
, channels
;
3001 bfd_boolean decrement_p
;
3007 SKIP_SPACE_TABS (s
);
3009 /* Only match "--" as part of a base expression. In other contexts "--X"
3010 is a double negative. */
3011 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3015 SKIP_SPACE_TABS (s
);
3018 /* Allow a channel specifier because that leads to better error messages
3019 than treating something like "$vf0x++" as an expression. */
3020 if (!mips_parse_register (&s
, ®no
, &channels
))
3024 mips_add_token (&token
, OT_CHAR
);
3029 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3032 token
.u
.regno
= regno
;
3033 mips_add_token (&token
, OT_REG
);
3037 token
.u
.channels
= channels
;
3038 mips_add_token (&token
, OT_CHANNELS
);
3041 /* For consistency, only match "++" as part of base expressions too. */
3042 SKIP_SPACE_TABS (s
);
3043 if (s
[0] == '+' && s
[1] == '+')
3047 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3053 /* Parse one or more tokens from S. Return a pointer to the first
3054 unconsumed character on success. Return null if an error was found
3055 and store the error text in insn_error. FLOAT_FORMAT is as for
3056 mips_parse_arguments. */
3059 mips_parse_argument_token (char *s
, char float_format
)
3061 char *end
, *save_in
;
3063 unsigned int regno1
, regno2
, channels
;
3064 struct mips_operand_token token
;
3066 /* First look for "($reg", since we want to treat that as an
3067 OT_CHAR and OT_REG rather than an expression. */
3068 end
= mips_parse_base_start (s
);
3072 /* Handle other characters that end up as OT_CHARs. */
3073 if (*s
== ')' || *s
== ',')
3076 mips_add_token (&token
, OT_CHAR
);
3081 /* Handle tokens that start with a register. */
3082 if (mips_parse_register (&s
, ®no1
, &channels
))
3086 /* A register and a VU0 channel suffix. */
3087 token
.u
.regno
= regno1
;
3088 mips_add_token (&token
, OT_REG
);
3090 token
.u
.channels
= channels
;
3091 mips_add_token (&token
, OT_CHANNELS
);
3095 SKIP_SPACE_TABS (s
);
3098 /* A register range. */
3100 SKIP_SPACE_TABS (s
);
3101 if (!mips_parse_register (&s
, ®no2
, NULL
))
3103 set_insn_error (0, _("invalid register range"));
3107 token
.u
.reg_range
.regno1
= regno1
;
3108 token
.u
.reg_range
.regno2
= regno2
;
3109 mips_add_token (&token
, OT_REG_RANGE
);
3113 /* Add the register itself. */
3114 token
.u
.regno
= regno1
;
3115 mips_add_token (&token
, OT_REG
);
3117 /* Check for a vector index. */
3121 SKIP_SPACE_TABS (s
);
3122 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3123 mips_add_token (&token
, OT_REG_INDEX
);
3126 expressionS element
;
3128 my_getExpression (&element
, s
);
3129 if (element
.X_op
!= O_constant
)
3131 set_insn_error (0, _("vector element must be constant"));
3135 token
.u
.index
= element
.X_add_number
;
3136 mips_add_token (&token
, OT_INTEGER_INDEX
);
3138 SKIP_SPACE_TABS (s
);
3141 set_insn_error (0, _("missing `]'"));
3151 /* First try to treat expressions as floats. */
3152 save_in
= input_line_pointer
;
3153 input_line_pointer
= s
;
3154 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3155 &token
.u
.flt
.length
);
3156 end
= input_line_pointer
;
3157 input_line_pointer
= save_in
;
3160 set_insn_error (0, err
);
3165 mips_add_token (&token
, OT_FLOAT
);
3170 /* Treat everything else as an integer expression. */
3171 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3172 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3173 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3174 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3176 mips_add_token (&token
, OT_INTEGER
);
3180 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3181 if expressions should be treated as 32-bit floating-point constants,
3182 'd' if they should be treated as 64-bit floating-point constants,
3183 or 0 if they should be treated as integer expressions (the usual case).
3185 Return a list of tokens on success, otherwise return 0. The caller
3186 must obstack_free the list after use. */
3188 static struct mips_operand_token
*
3189 mips_parse_arguments (char *s
, char float_format
)
3191 struct mips_operand_token token
;
3193 SKIP_SPACE_TABS (s
);
3196 s
= mips_parse_argument_token (s
, float_format
);
3199 obstack_free (&mips_operand_tokens
,
3200 obstack_finish (&mips_operand_tokens
));
3203 SKIP_SPACE_TABS (s
);
3205 mips_add_token (&token
, OT_END
);
3206 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3209 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3210 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3213 is_opcode_valid (const struct mips_opcode
*mo
)
3215 int isa
= mips_opts
.isa
;
3216 int ase
= mips_opts
.ase
;
3220 if (ISA_HAS_64BIT_REGS (isa
))
3221 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3222 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3223 ase
|= mips_ases
[i
].flags64
;
3225 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3228 /* Check whether the instruction or macro requires single-precision or
3229 double-precision floating-point support. Note that this information is
3230 stored differently in the opcode table for insns and macros. */
3231 if (mo
->pinfo
== INSN_MACRO
)
3233 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3234 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3238 fp_s
= mo
->pinfo
& FP_S
;
3239 fp_d
= mo
->pinfo
& FP_D
;
3242 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3245 if (fp_s
&& mips_opts
.soft_float
)
3251 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3252 selected ISA and architecture. */
3255 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3257 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3260 /* Return TRUE if the size of the microMIPS opcode MO matches one
3261 explicitly requested. Always TRUE in the standard MIPS mode.
3262 Use is_size_valid_16 for MIPS16 opcodes. */
3265 is_size_valid (const struct mips_opcode
*mo
)
3267 if (!mips_opts
.micromips
)
3270 if (mips_opts
.insn32
)
3272 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3274 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3277 if (!forced_insn_length
)
3279 if (mo
->pinfo
== INSN_MACRO
)
3281 return forced_insn_length
== micromips_insn_length (mo
);
3284 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3285 explicitly requested. */
3288 is_size_valid_16 (const struct mips_opcode
*mo
)
3290 if (!forced_insn_length
)
3292 if (mo
->pinfo
== INSN_MACRO
)
3294 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3299 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3300 of the preceding instruction. Always TRUE in the standard MIPS mode.
3302 We don't accept macros in 16-bit delay slots to avoid a case where
3303 a macro expansion fails because it relies on a preceding 32-bit real
3304 instruction to have matched and does not handle the operands correctly.
3305 The only macros that may expand to 16-bit instructions are JAL that
3306 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3307 and BGT (that likewise cannot be placed in a delay slot) that decay to
3308 a NOP. In all these cases the macros precede any corresponding real
3309 instruction definitions in the opcode table, so they will match in the
3310 second pass where the size of the delay slot is ignored and therefore
3311 produce correct code. */
3314 is_delay_slot_valid (const struct mips_opcode
*mo
)
3316 if (!mips_opts
.micromips
)
3319 if (mo
->pinfo
== INSN_MACRO
)
3320 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3321 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3322 && micromips_insn_length (mo
) != 4)
3324 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3325 && micromips_insn_length (mo
) != 2)
3331 /* For consistency checking, verify that all bits of OPCODE are specified
3332 either by the match/mask part of the instruction definition, or by the
3333 operand list. Also build up a list of operands in OPERANDS.
3335 INSN_BITS says which bits of the instruction are significant.
3336 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3337 provides the mips_operand description of each operand. DECODE_OPERAND
3338 is null for MIPS16 instructions. */
3341 validate_mips_insn (const struct mips_opcode
*opcode
,
3342 unsigned long insn_bits
,
3343 const struct mips_operand
*(*decode_operand
) (const char *),
3344 struct mips_operand_array
*operands
)
3347 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3348 const struct mips_operand
*operand
;
3350 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3351 if ((mask
& opcode
->match
) != opcode
->match
)
3353 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3354 opcode
->name
, opcode
->args
);
3359 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3360 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3361 for (s
= opcode
->args
; *s
; ++s
)
3374 if (!decode_operand
)
3375 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3377 operand
= decode_operand (s
);
3378 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3380 as_bad (_("internal: unknown operand type: %s %s"),
3381 opcode
->name
, opcode
->args
);
3384 gas_assert (opno
< MAX_OPERANDS
);
3385 operands
->operand
[opno
] = operand
;
3386 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3388 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3389 if (operand
->type
== OP_MDMX_IMM_REG
)
3390 /* Bit 5 is the format selector (OB vs QH). The opcode table
3391 has separate entries for each format. */
3392 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3393 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3394 used_bits
&= ~(mask
& 0x700);
3396 /* Skip prefix characters. */
3397 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3402 doubled
= used_bits
& mask
& insn_bits
;
3405 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3406 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3410 undefined
= ~used_bits
& insn_bits
;
3411 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3413 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3414 undefined
, opcode
->name
, opcode
->args
);
3417 used_bits
&= ~insn_bits
;
3420 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3421 used_bits
, opcode
->name
, opcode
->args
);
3427 /* The MIPS16 version of validate_mips_insn. */
3430 validate_mips16_insn (const struct mips_opcode
*opcode
,
3431 struct mips_operand_array
*operands
)
3433 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3435 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3438 /* The microMIPS version of validate_mips_insn. */
3441 validate_micromips_insn (const struct mips_opcode
*opc
,
3442 struct mips_operand_array
*operands
)
3444 unsigned long insn_bits
;
3445 unsigned long major
;
3446 unsigned int length
;
3448 if (opc
->pinfo
== INSN_MACRO
)
3449 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3452 length
= micromips_insn_length (opc
);
3453 if (length
!= 2 && length
!= 4)
3455 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3456 "%s %s"), length
, opc
->name
, opc
->args
);
3459 major
= opc
->match
>> (10 + 8 * (length
- 2));
3460 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3461 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3463 as_bad (_("internal error: bad microMIPS opcode "
3464 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3468 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3469 insn_bits
= 1 << 4 * length
;
3470 insn_bits
<<= 4 * length
;
3472 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3476 /* This function is called once, at assembler startup time. It should set up
3477 all the tables, etc. that the MD part of the assembler will need. */
3482 const char *retval
= NULL
;
3486 if (mips_pic
!= NO_PIC
)
3488 if (g_switch_seen
&& g_switch_value
!= 0)
3489 as_bad (_("-G may not be used in position-independent code"));
3492 else if (mips_abicalls
)
3494 if (g_switch_seen
&& g_switch_value
!= 0)
3495 as_bad (_("-G may not be used with abicalls"));
3499 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3500 as_warn (_("could not set architecture and machine"));
3502 op_hash
= hash_new ();
3504 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3505 for (i
= 0; i
< NUMOPCODES
;)
3507 const char *name
= mips_opcodes
[i
].name
;
3509 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3512 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3513 mips_opcodes
[i
].name
, retval
);
3514 /* Probably a memory allocation problem? Give up now. */
3515 as_fatal (_("broken assembler, no assembly attempted"));
3519 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3520 decode_mips_operand
, &mips_operands
[i
]))
3522 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3524 create_insn (&nop_insn
, mips_opcodes
+ i
);
3525 if (mips_fix_loongson2f_nop
)
3526 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3527 nop_insn
.fixed_p
= 1;
3531 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3534 mips16_op_hash
= hash_new ();
3535 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3536 bfd_mips16_num_opcodes
);
3539 while (i
< bfd_mips16_num_opcodes
)
3541 const char *name
= mips16_opcodes
[i
].name
;
3543 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3545 as_fatal (_("internal: can't hash `%s': %s"),
3546 mips16_opcodes
[i
].name
, retval
);
3549 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3551 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3553 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3554 mips16_nop_insn
.fixed_p
= 1;
3558 while (i
< bfd_mips16_num_opcodes
3559 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3562 micromips_op_hash
= hash_new ();
3563 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3564 bfd_micromips_num_opcodes
);
3567 while (i
< bfd_micromips_num_opcodes
)
3569 const char *name
= micromips_opcodes
[i
].name
;
3571 retval
= hash_insert (micromips_op_hash
, name
,
3572 (void *) µmips_opcodes
[i
]);
3574 as_fatal (_("internal: can't hash `%s': %s"),
3575 micromips_opcodes
[i
].name
, retval
);
3578 struct mips_cl_insn
*micromips_nop_insn
;
3580 if (!validate_micromips_insn (µmips_opcodes
[i
],
3581 µmips_operands
[i
]))
3584 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3586 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3587 micromips_nop_insn
= µmips_nop16_insn
;
3588 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3589 micromips_nop_insn
= µmips_nop32_insn
;
3593 if (micromips_nop_insn
->insn_mo
== NULL
3594 && strcmp (name
, "nop") == 0)
3596 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3597 micromips_nop_insn
->fixed_p
= 1;
3601 while (++i
< bfd_micromips_num_opcodes
3602 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3606 as_fatal (_("broken assembler, no assembly attempted"));
3608 /* We add all the general register names to the symbol table. This
3609 helps us detect invalid uses of them. */
3610 for (i
= 0; reg_names
[i
].name
; i
++)
3611 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3612 reg_names
[i
].num
, /* & RNUM_MASK, */
3613 &zero_address_frag
));
3615 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3616 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3617 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3618 &zero_address_frag
));
3620 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3621 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3622 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3623 &zero_address_frag
));
3625 for (i
= 0; i
< 32; i
++)
3629 /* R5900 VU0 floating-point register. */
3630 sprintf (regname
, "$vf%d", i
);
3631 symbol_table_insert (symbol_new (regname
, reg_section
,
3632 RTYPE_VF
| i
, &zero_address_frag
));
3634 /* R5900 VU0 integer register. */
3635 sprintf (regname
, "$vi%d", i
);
3636 symbol_table_insert (symbol_new (regname
, reg_section
,
3637 RTYPE_VI
| i
, &zero_address_frag
));
3640 sprintf (regname
, "$w%d", i
);
3641 symbol_table_insert (symbol_new (regname
, reg_section
,
3642 RTYPE_MSA
| i
, &zero_address_frag
));
3645 obstack_init (&mips_operand_tokens
);
3647 mips_no_prev_insn ();
3650 mips_cprmask
[0] = 0;
3651 mips_cprmask
[1] = 0;
3652 mips_cprmask
[2] = 0;
3653 mips_cprmask
[3] = 0;
3655 /* set the default alignment for the text section (2**2) */
3656 record_alignment (text_section
, 2);
3658 bfd_set_gp_size (stdoutput
, g_switch_value
);
3660 /* On a native system other than VxWorks, sections must be aligned
3661 to 16 byte boundaries. When configured for an embedded ELF
3662 target, we don't bother. */
3663 if (strncmp (TARGET_OS
, "elf", 3) != 0
3664 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3666 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3667 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3668 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3671 /* Create a .reginfo section for register masks and a .mdebug
3672 section for debugging information. */
3680 subseg
= now_subseg
;
3682 /* The ABI says this section should be loaded so that the
3683 running program can access it. However, we don't load it
3684 if we are configured for an embedded target */
3685 flags
= SEC_READONLY
| SEC_DATA
;
3686 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3687 flags
|= SEC_ALLOC
| SEC_LOAD
;
3689 if (mips_abi
!= N64_ABI
)
3691 sec
= subseg_new (".reginfo", (subsegT
) 0);
3693 bfd_set_section_flags (stdoutput
, sec
, flags
);
3694 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3696 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3700 /* The 64-bit ABI uses a .MIPS.options section rather than
3701 .reginfo section. */
3702 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3703 bfd_set_section_flags (stdoutput
, sec
, flags
);
3704 bfd_set_section_alignment (stdoutput
, sec
, 3);
3706 /* Set up the option header. */
3708 Elf_Internal_Options opthdr
;
3711 opthdr
.kind
= ODK_REGINFO
;
3712 opthdr
.size
= (sizeof (Elf_External_Options
)
3713 + sizeof (Elf64_External_RegInfo
));
3716 f
= frag_more (sizeof (Elf_External_Options
));
3717 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3718 (Elf_External_Options
*) f
);
3720 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3724 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3725 bfd_set_section_flags (stdoutput
, sec
,
3726 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3727 bfd_set_section_alignment (stdoutput
, sec
, 3);
3728 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3730 if (ECOFF_DEBUGGING
)
3732 sec
= subseg_new (".mdebug", (subsegT
) 0);
3733 (void) bfd_set_section_flags (stdoutput
, sec
,
3734 SEC_HAS_CONTENTS
| SEC_READONLY
);
3735 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3737 else if (mips_flag_pdr
)
3739 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3740 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3741 SEC_READONLY
| SEC_RELOC
3743 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3746 subseg_set (seg
, subseg
);
3749 if (mips_fix_vr4120
)
3750 init_vr4120_conflicts ();
3754 fpabi_incompatible_with (int fpabi
, const char *what
)
3756 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3757 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3761 fpabi_requires (int fpabi
, const char *what
)
3763 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3764 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3767 /* Check -mabi and register sizes against the specified FP ABI. */
3769 check_fpabi (int fpabi
)
3773 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3774 if (file_mips_opts
.soft_float
)
3775 fpabi_incompatible_with (fpabi
, "softfloat");
3776 else if (file_mips_opts
.single_float
)
3777 fpabi_incompatible_with (fpabi
, "singlefloat");
3778 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3779 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3780 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3781 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3784 case Val_GNU_MIPS_ABI_FP_XX
:
3785 if (mips_abi
!= O32_ABI
)
3786 fpabi_requires (fpabi
, "-mabi=32");
3787 else if (file_mips_opts
.soft_float
)
3788 fpabi_incompatible_with (fpabi
, "softfloat");
3789 else if (file_mips_opts
.single_float
)
3790 fpabi_incompatible_with (fpabi
, "singlefloat");
3791 else if (file_mips_opts
.fp
!= 0)
3792 fpabi_requires (fpabi
, "fp=xx");
3795 case Val_GNU_MIPS_ABI_FP_64A
:
3796 case Val_GNU_MIPS_ABI_FP_64
:
3797 if (mips_abi
!= O32_ABI
)
3798 fpabi_requires (fpabi
, "-mabi=32");
3799 else if (file_mips_opts
.soft_float
)
3800 fpabi_incompatible_with (fpabi
, "softfloat");
3801 else if (file_mips_opts
.single_float
)
3802 fpabi_incompatible_with (fpabi
, "singlefloat");
3803 else if (file_mips_opts
.fp
!= 64)
3804 fpabi_requires (fpabi
, "fp=64");
3805 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3806 fpabi_incompatible_with (fpabi
, "nooddspreg");
3807 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3808 fpabi_requires (fpabi
, "nooddspreg");
3811 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3812 if (file_mips_opts
.soft_float
)
3813 fpabi_incompatible_with (fpabi
, "softfloat");
3814 else if (!file_mips_opts
.single_float
)
3815 fpabi_requires (fpabi
, "singlefloat");
3818 case Val_GNU_MIPS_ABI_FP_SOFT
:
3819 if (!file_mips_opts
.soft_float
)
3820 fpabi_requires (fpabi
, "softfloat");
3823 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3824 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3825 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3828 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3829 /* Silently ignore compatibility value. */
3833 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3834 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3839 /* Perform consistency checks on the current options. */
3842 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3844 /* Check the size of integer registers agrees with the ABI and ISA. */
3845 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3846 as_bad (_("`gp=64' used with a 32-bit processor"));
3848 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3849 as_bad (_("`gp=32' used with a 64-bit ABI"));
3851 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3852 as_bad (_("`gp=64' used with a 32-bit ABI"));
3854 /* Check the size of the float registers agrees with the ABI and ISA. */
3858 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3859 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3860 else if (opts
->single_float
== 1)
3861 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3864 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3865 as_bad (_("`fp=64' used with a 32-bit fpu"));
3867 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3868 && !ISA_HAS_MXHC1 (opts
->isa
))
3869 as_warn (_("`fp=64' used with a 32-bit ABI"));
3873 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3874 as_warn (_("`fp=32' used with a 64-bit ABI"));
3875 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3876 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3879 as_bad (_("Unknown size of floating point registers"));
3883 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3884 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3886 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3887 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3888 else if (ISA_IS_R6 (opts
->isa
)
3889 && (opts
->micromips
== 1
3890 || opts
->mips16
== 1))
3891 as_fatal (_("`%s' cannot be used with `%s'"),
3892 opts
->micromips
? "micromips" : "mips16",
3893 mips_cpu_info_from_isa (opts
->isa
)->name
);
3895 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3896 as_fatal (_("branch relaxation is not supported in `%s'"),
3897 mips_cpu_info_from_isa (opts
->isa
)->name
);
3900 /* Perform consistency checks on the module level options exactly once.
3901 This is a deferred check that happens:
3902 at the first .set directive
3903 or, at the first pseudo op that generates code (inc .dc.a)
3904 or, at the first instruction
3908 file_mips_check_options (void)
3910 const struct mips_cpu_info
*arch_info
= 0;
3912 if (file_mips_opts_checked
)
3915 /* The following code determines the register size.
3916 Similar code was added to GCC 3.3 (see override_options() in
3917 config/mips/mips.c). The GAS and GCC code should be kept in sync
3918 as much as possible. */
3920 if (file_mips_opts
.gp
< 0)
3922 /* Infer the integer register size from the ABI and processor.
3923 Restrict ourselves to 32-bit registers if that's all the
3924 processor has, or if the ABI cannot handle 64-bit registers. */
3925 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3926 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3930 if (file_mips_opts
.fp
< 0)
3932 /* No user specified float register size.
3933 ??? GAS treats single-float processors as though they had 64-bit
3934 float registers (although it complains when double-precision
3935 instructions are used). As things stand, saying they have 32-bit
3936 registers would lead to spurious "register must be even" messages.
3937 So here we assume float registers are never smaller than the
3939 if (file_mips_opts
.gp
== 64)
3940 /* 64-bit integer registers implies 64-bit float registers. */
3941 file_mips_opts
.fp
= 64;
3942 else if ((file_mips_opts
.ase
& FP64_ASES
)
3943 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3944 /* Handle ASEs that require 64-bit float registers, if possible. */
3945 file_mips_opts
.fp
= 64;
3946 else if (ISA_IS_R6 (mips_opts
.isa
))
3947 /* R6 implies 64-bit float registers. */
3948 file_mips_opts
.fp
= 64;
3950 /* 32-bit float registers. */
3951 file_mips_opts
.fp
= 32;
3954 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3956 /* Disable operations on odd-numbered floating-point registers by default
3957 when using the FPXX ABI. */
3958 if (file_mips_opts
.oddspreg
< 0)
3960 if (file_mips_opts
.fp
== 0)
3961 file_mips_opts
.oddspreg
= 0;
3963 file_mips_opts
.oddspreg
= 1;
3966 /* End of GCC-shared inference code. */
3968 /* This flag is set when we have a 64-bit capable CPU but use only
3969 32-bit wide registers. Note that EABI does not use it. */
3970 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3971 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3972 || mips_abi
== O32_ABI
))
3975 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3976 as_bad (_("trap exception not supported at ISA 1"));
3978 /* If the selected architecture includes support for ASEs, enable
3979 generation of code for them. */
3980 if (file_mips_opts
.mips16
== -1)
3981 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
3982 if (file_mips_opts
.micromips
== -1)
3983 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
3986 if (mips_nan2008
== -1)
3987 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
3988 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
3989 as_fatal (_("`%s' does not support legacy NaN"),
3990 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
3992 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3993 being selected implicitly. */
3994 if (file_mips_opts
.fp
!= 64)
3995 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
3997 /* If the user didn't explicitly select or deselect a particular ASE,
3998 use the default setting for the CPU. */
3999 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4001 /* Set up the current options. These may change throughout assembly. */
4002 mips_opts
= file_mips_opts
;
4004 mips_check_isa_supports_ases ();
4005 mips_check_options (&file_mips_opts
, TRUE
);
4006 file_mips_opts_checked
= TRUE
;
4008 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4009 as_warn (_("could not set architecture and machine"));
4013 md_assemble (char *str
)
4015 struct mips_cl_insn insn
;
4016 bfd_reloc_code_real_type unused_reloc
[3]
4017 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4019 file_mips_check_options ();
4021 imm_expr
.X_op
= O_absent
;
4022 offset_expr
.X_op
= O_absent
;
4023 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4024 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4025 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4027 mips_mark_labels ();
4028 mips_assembling_insn
= TRUE
;
4029 clear_insn_error ();
4031 if (mips_opts
.mips16
)
4032 mips16_ip (str
, &insn
);
4035 mips_ip (str
, &insn
);
4036 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4037 str
, insn
.insn_opcode
));
4041 report_insn_error (str
);
4042 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4045 if (mips_opts
.mips16
)
4046 mips16_macro (&insn
);
4053 if (offset_expr
.X_op
!= O_absent
)
4054 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4056 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4059 mips_assembling_insn
= FALSE
;
4062 /* Convenience functions for abstracting away the differences between
4063 MIPS16 and non-MIPS16 relocations. */
4065 static inline bfd_boolean
4066 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4070 case BFD_RELOC_MIPS16_JMP
:
4071 case BFD_RELOC_MIPS16_GPREL
:
4072 case BFD_RELOC_MIPS16_GOT16
:
4073 case BFD_RELOC_MIPS16_CALL16
:
4074 case BFD_RELOC_MIPS16_HI16_S
:
4075 case BFD_RELOC_MIPS16_HI16
:
4076 case BFD_RELOC_MIPS16_LO16
:
4077 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4085 static inline bfd_boolean
4086 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4090 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4091 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4092 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4093 case BFD_RELOC_MICROMIPS_GPREL16
:
4094 case BFD_RELOC_MICROMIPS_JMP
:
4095 case BFD_RELOC_MICROMIPS_HI16
:
4096 case BFD_RELOC_MICROMIPS_HI16_S
:
4097 case BFD_RELOC_MICROMIPS_LO16
:
4098 case BFD_RELOC_MICROMIPS_LITERAL
:
4099 case BFD_RELOC_MICROMIPS_GOT16
:
4100 case BFD_RELOC_MICROMIPS_CALL16
:
4101 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4102 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4103 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4104 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4105 case BFD_RELOC_MICROMIPS_SUB
:
4106 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4107 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4108 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4109 case BFD_RELOC_MICROMIPS_HIGHEST
:
4110 case BFD_RELOC_MICROMIPS_HIGHER
:
4111 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4112 case BFD_RELOC_MICROMIPS_JALR
:
4120 static inline bfd_boolean
4121 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4123 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4126 static inline bfd_boolean
4127 b_reloc_p (bfd_reloc_code_real_type reloc
)
4129 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4130 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4131 || reloc
== BFD_RELOC_16_PCREL_S2
4132 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4133 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4134 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4135 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4138 static inline bfd_boolean
4139 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4141 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4142 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4145 static inline bfd_boolean
4146 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4148 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4149 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4152 static inline bfd_boolean
4153 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4155 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4156 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4159 static inline bfd_boolean
4160 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4162 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4165 static inline bfd_boolean
4166 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4168 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4169 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4172 /* Return true if RELOC is a PC-relative relocation that does not have
4173 full address range. */
4175 static inline bfd_boolean
4176 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4180 case BFD_RELOC_16_PCREL_S2
:
4181 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4182 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4183 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4184 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4185 case BFD_RELOC_MIPS_21_PCREL_S2
:
4186 case BFD_RELOC_MIPS_26_PCREL_S2
:
4187 case BFD_RELOC_MIPS_18_PCREL_S3
:
4188 case BFD_RELOC_MIPS_19_PCREL_S2
:
4191 case BFD_RELOC_32_PCREL
:
4192 case BFD_RELOC_HI16_S_PCREL
:
4193 case BFD_RELOC_LO16_PCREL
:
4194 return HAVE_64BIT_ADDRESSES
;
4201 /* Return true if the given relocation might need a matching %lo().
4202 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4203 need a matching %lo() when applied to local symbols. */
4205 static inline bfd_boolean
4206 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4208 return (HAVE_IN_PLACE_ADDENDS
4209 && (hi16_reloc_p (reloc
)
4210 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4211 all GOT16 relocations evaluate to "G". */
4212 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4215 /* Return the type of %lo() reloc needed by RELOC, given that
4216 reloc_needs_lo_p. */
4218 static inline bfd_reloc_code_real_type
4219 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4221 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4222 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4226 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4229 static inline bfd_boolean
4230 fixup_has_matching_lo_p (fixS
*fixp
)
4232 return (fixp
->fx_next
!= NULL
4233 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4234 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4235 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4238 /* Move all labels in LABELS to the current insertion point. TEXT_P
4239 says whether the labels refer to text or data. */
4242 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4244 struct insn_label_list
*l
;
4247 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4249 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4250 symbol_set_frag (l
->label
, frag_now
);
4251 val
= (valueT
) frag_now_fix ();
4252 /* MIPS16/microMIPS text labels are stored as odd. */
4253 if (text_p
&& HAVE_CODE_COMPRESSION
)
4255 S_SET_VALUE (l
->label
, val
);
4259 /* Move all labels in insn_labels to the current insertion point
4260 and treat them as text labels. */
4263 mips_move_text_labels (void)
4265 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4269 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4271 bfd_boolean linkonce
= FALSE
;
4272 segT symseg
= S_GET_SEGMENT (sym
);
4274 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4276 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4278 /* The GNU toolchain uses an extension for ELF: a section
4279 beginning with the magic string .gnu.linkonce is a
4280 linkonce section. */
4281 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4282 sizeof ".gnu.linkonce" - 1) == 0)
4288 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4289 linker to handle them specially, such as generating jalx instructions
4290 when needed. We also make them odd for the duration of the assembly,
4291 in order to generate the right sort of code. We will make them even
4292 in the adjust_symtab routine, while leaving them marked. This is
4293 convenient for the debugger and the disassembler. The linker knows
4294 to make them odd again. */
4297 mips_compressed_mark_label (symbolS
*label
)
4299 gas_assert (HAVE_CODE_COMPRESSION
);
4301 if (mips_opts
.mips16
)
4302 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4304 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4305 if ((S_GET_VALUE (label
) & 1) == 0
4306 /* Don't adjust the address if the label is global or weak, or
4307 in a link-once section, since we'll be emitting symbol reloc
4308 references to it which will be patched up by the linker, and
4309 the final value of the symbol may or may not be MIPS16/microMIPS. */
4310 && !S_IS_WEAK (label
)
4311 && !S_IS_EXTERNAL (label
)
4312 && !s_is_linkonce (label
, now_seg
))
4313 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4316 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4319 mips_compressed_mark_labels (void)
4321 struct insn_label_list
*l
;
4323 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4324 mips_compressed_mark_label (l
->label
);
4327 /* End the current frag. Make it a variant frag and record the
4331 relax_close_frag (void)
4333 mips_macro_warning
.first_frag
= frag_now
;
4334 frag_var (rs_machine_dependent
, 0, 0,
4335 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
4336 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4338 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4339 mips_relax
.first_fixup
= 0;
4342 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4343 See the comment above RELAX_ENCODE for more details. */
4346 relax_start (symbolS
*symbol
)
4348 gas_assert (mips_relax
.sequence
== 0);
4349 mips_relax
.sequence
= 1;
4350 mips_relax
.symbol
= symbol
;
4353 /* Start generating the second version of a relaxable sequence.
4354 See the comment above RELAX_ENCODE for more details. */
4359 gas_assert (mips_relax
.sequence
== 1);
4360 mips_relax
.sequence
= 2;
4363 /* End the current relaxable sequence. */
4368 gas_assert (mips_relax
.sequence
== 2);
4369 relax_close_frag ();
4370 mips_relax
.sequence
= 0;
4373 /* Return true if IP is a delayed branch or jump. */
4375 static inline bfd_boolean
4376 delayed_branch_p (const struct mips_cl_insn
*ip
)
4378 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4379 | INSN_COND_BRANCH_DELAY
4380 | INSN_COND_BRANCH_LIKELY
)) != 0;
4383 /* Return true if IP is a compact branch or jump. */
4385 static inline bfd_boolean
4386 compact_branch_p (const struct mips_cl_insn
*ip
)
4388 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4389 | INSN2_COND_BRANCH
)) != 0;
4392 /* Return true if IP is an unconditional branch or jump. */
4394 static inline bfd_boolean
4395 uncond_branch_p (const struct mips_cl_insn
*ip
)
4397 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4398 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4401 /* Return true if IP is a branch-likely instruction. */
4403 static inline bfd_boolean
4404 branch_likely_p (const struct mips_cl_insn
*ip
)
4406 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4409 /* Return the type of nop that should be used to fill the delay slot
4410 of delayed branch IP. */
4412 static struct mips_cl_insn
*
4413 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4415 if (mips_opts
.micromips
4416 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4417 return µmips_nop32_insn
;
4421 /* Return a mask that has bit N set if OPCODE reads the register(s)
4425 insn_read_mask (const struct mips_opcode
*opcode
)
4427 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4430 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4434 insn_write_mask (const struct mips_opcode
*opcode
)
4436 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4439 /* Return a mask of the registers specified by operand OPERAND of INSN.
4440 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4444 operand_reg_mask (const struct mips_cl_insn
*insn
,
4445 const struct mips_operand
*operand
,
4446 unsigned int type_mask
)
4448 unsigned int uval
, vsel
;
4450 switch (operand
->type
)
4457 case OP_ADDIUSP_INT
:
4458 case OP_ENTRY_EXIT_LIST
:
4459 case OP_REPEAT_DEST_REG
:
4460 case OP_REPEAT_PREV_REG
:
4463 case OP_VU0_MATCH_SUFFIX
:
4468 case OP_OPTIONAL_REG
:
4470 const struct mips_reg_operand
*reg_op
;
4472 reg_op
= (const struct mips_reg_operand
*) operand
;
4473 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4475 uval
= insn_extract_operand (insn
, operand
);
4476 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4481 const struct mips_reg_pair_operand
*pair_op
;
4483 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4484 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4486 uval
= insn_extract_operand (insn
, operand
);
4487 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4490 case OP_CLO_CLZ_DEST
:
4491 if (!(type_mask
& (1 << OP_REG_GP
)))
4493 uval
= insn_extract_operand (insn
, operand
);
4494 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4497 if (!(type_mask
& (1 << OP_REG_GP
)))
4499 uval
= insn_extract_operand (insn
, operand
);
4500 gas_assert ((uval
& 31) == (uval
>> 5));
4501 return 1 << (uval
& 31);
4504 case OP_NON_ZERO_REG
:
4505 if (!(type_mask
& (1 << OP_REG_GP
)))
4507 uval
= insn_extract_operand (insn
, operand
);
4508 return 1 << (uval
& 31);
4510 case OP_LWM_SWM_LIST
:
4513 case OP_SAVE_RESTORE_LIST
:
4516 case OP_MDMX_IMM_REG
:
4517 if (!(type_mask
& (1 << OP_REG_VEC
)))
4519 uval
= insn_extract_operand (insn
, operand
);
4521 if ((vsel
& 0x18) == 0x18)
4523 return 1 << (uval
& 31);
4526 if (!(type_mask
& (1 << OP_REG_GP
)))
4528 return 1 << insn_extract_operand (insn
, operand
);
4533 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4534 where bit N of OPNO_MASK is set if operand N should be included.
4535 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4539 insn_reg_mask (const struct mips_cl_insn
*insn
,
4540 unsigned int type_mask
, unsigned int opno_mask
)
4542 unsigned int opno
, reg_mask
;
4546 while (opno_mask
!= 0)
4549 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4556 /* Return the mask of core registers that IP reads. */
4559 gpr_read_mask (const struct mips_cl_insn
*ip
)
4561 unsigned long pinfo
, pinfo2
;
4564 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4565 pinfo
= ip
->insn_mo
->pinfo
;
4566 pinfo2
= ip
->insn_mo
->pinfo2
;
4567 if (pinfo
& INSN_UDI
)
4569 /* UDI instructions have traditionally been assumed to read RS
4571 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4572 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4574 if (pinfo
& INSN_READ_GPR_24
)
4576 if (pinfo2
& INSN2_READ_GPR_16
)
4578 if (pinfo2
& INSN2_READ_SP
)
4580 if (pinfo2
& INSN2_READ_GPR_31
)
4582 /* Don't include register 0. */
4586 /* Return the mask of core registers that IP writes. */
4589 gpr_write_mask (const struct mips_cl_insn
*ip
)
4591 unsigned long pinfo
, pinfo2
;
4594 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4595 pinfo
= ip
->insn_mo
->pinfo
;
4596 pinfo2
= ip
->insn_mo
->pinfo2
;
4597 if (pinfo
& INSN_WRITE_GPR_24
)
4599 if (pinfo
& INSN_WRITE_GPR_31
)
4601 if (pinfo
& INSN_UDI
)
4602 /* UDI instructions have traditionally been assumed to write to RD. */
4603 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4604 if (pinfo2
& INSN2_WRITE_SP
)
4606 /* Don't include register 0. */
4610 /* Return the mask of floating-point registers that IP reads. */
4613 fpr_read_mask (const struct mips_cl_insn
*ip
)
4615 unsigned long pinfo
;
4618 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4619 | (1 << OP_REG_MSA
)),
4620 insn_read_mask (ip
->insn_mo
));
4621 pinfo
= ip
->insn_mo
->pinfo
;
4622 /* Conservatively treat all operands to an FP_D instruction are doubles.
4623 (This is overly pessimistic for things like cvt.d.s.) */
4624 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4629 /* Return the mask of floating-point registers that IP writes. */
4632 fpr_write_mask (const struct mips_cl_insn
*ip
)
4634 unsigned long pinfo
;
4637 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4638 | (1 << OP_REG_MSA
)),
4639 insn_write_mask (ip
->insn_mo
));
4640 pinfo
= ip
->insn_mo
->pinfo
;
4641 /* Conservatively treat all operands to an FP_D instruction are doubles.
4642 (This is overly pessimistic for things like cvt.s.d.) */
4643 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4648 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4649 Check whether that is allowed. */
4652 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4654 const char *s
= insn
->name
;
4655 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4657 && mips_opts
.oddspreg
;
4659 if (insn
->pinfo
== INSN_MACRO
)
4660 /* Let a macro pass, we'll catch it later when it is expanded. */
4663 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4664 otherwise it depends on oddspreg. */
4665 if ((insn
->pinfo
& FP_S
)
4666 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4667 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4668 return FPR_SIZE
== 32 || oddspreg
;
4670 /* Allow odd registers for single-precision ops and double-precision if the
4671 floating-point registers are 64-bit wide. */
4672 switch (insn
->pinfo
& (FP_S
| FP_D
))
4678 return FPR_SIZE
== 64;
4683 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4684 s
= strchr (insn
->name
, '.');
4685 if (s
!= NULL
&& opnum
== 2)
4686 s
= strchr (s
+ 1, '.');
4687 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4690 return FPR_SIZE
== 64;
4693 /* Information about an instruction argument that we're trying to match. */
4694 struct mips_arg_info
4696 /* The instruction so far. */
4697 struct mips_cl_insn
*insn
;
4699 /* The first unconsumed operand token. */
4700 struct mips_operand_token
*token
;
4702 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4705 /* The 1-based argument number, for error reporting. This does not
4706 count elided optional registers, etc.. */
4709 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4710 unsigned int last_regno
;
4712 /* If the first operand was an OP_REG, this is the register that it
4713 specified, otherwise it is ILLEGAL_REG. */
4714 unsigned int dest_regno
;
4716 /* The value of the last OP_INT operand. Only used for OP_MSB,
4717 where it gives the lsb position. */
4718 unsigned int last_op_int
;
4720 /* If true, match routines should assume that no later instruction
4721 alternative matches and should therefore be as accommodating as
4722 possible. Match routines should not report errors if something
4723 is only invalid for !LAX_MATCH. */
4724 bfd_boolean lax_match
;
4726 /* True if a reference to the current AT register was seen. */
4727 bfd_boolean seen_at
;
4730 /* Record that the argument is out of range. */
4733 match_out_of_range (struct mips_arg_info
*arg
)
4735 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4738 /* Record that the argument isn't constant but needs to be. */
4741 match_not_constant (struct mips_arg_info
*arg
)
4743 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4747 /* Try to match an OT_CHAR token for character CH. Consume the token
4748 and return true on success, otherwise return false. */
4751 match_char (struct mips_arg_info
*arg
, char ch
)
4753 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4763 /* Try to get an expression from the next tokens in ARG. Consume the
4764 tokens and return true on success, storing the expression value in
4765 VALUE and relocation types in R. */
4768 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4769 bfd_reloc_code_real_type
*r
)
4771 /* If the next token is a '(' that was parsed as being part of a base
4772 expression, assume we have an elided offset. The later match will fail
4773 if this turns out to be wrong. */
4774 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4776 value
->X_op
= O_constant
;
4777 value
->X_add_number
= 0;
4778 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4782 /* Reject register-based expressions such as "0+$2" and "(($2))".
4783 For plain registers the default error seems more appropriate. */
4784 if (arg
->token
->type
== OT_INTEGER
4785 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4787 set_insn_error (arg
->argnum
, _("register value used as expression"));
4791 if (arg
->token
->type
== OT_INTEGER
)
4793 *value
= arg
->token
->u
.integer
.value
;
4794 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4800 (arg
->argnum
, _("operand %d must be an immediate expression"),
4805 /* Try to get a constant expression from the next tokens in ARG. Consume
4806 the tokens and return return true on success, storing the constant value
4807 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4811 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4814 bfd_reloc_code_real_type r
[3];
4816 if (!match_expression (arg
, &ex
, r
))
4819 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4820 *value
= ex
.X_add_number
;
4823 match_not_constant (arg
);
4829 /* Return the RTYPE_* flags for a register operand of type TYPE that
4830 appears in instruction OPCODE. */
4833 convert_reg_type (const struct mips_opcode
*opcode
,
4834 enum mips_reg_operand_type type
)
4839 return RTYPE_NUM
| RTYPE_GP
;
4842 /* Allow vector register names for MDMX if the instruction is a 64-bit
4843 FPR load, store or move (including moves to and from GPRs). */
4844 if ((mips_opts
.ase
& ASE_MDMX
)
4845 && (opcode
->pinfo
& FP_D
)
4846 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4847 | INSN_COPROC_MEMORY_DELAY
4850 | INSN_STORE_MEMORY
)))
4851 return RTYPE_FPU
| RTYPE_VEC
;
4855 if (opcode
->pinfo
& (FP_D
| FP_S
))
4856 return RTYPE_CCC
| RTYPE_FCC
;
4860 if (opcode
->membership
& INSN_5400
)
4862 return RTYPE_FPU
| RTYPE_VEC
;
4868 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4869 return RTYPE_NUM
| RTYPE_CP0
;
4876 return RTYPE_NUM
| RTYPE_VI
;
4879 return RTYPE_NUM
| RTYPE_VF
;
4881 case OP_REG_R5900_I
:
4882 return RTYPE_R5900_I
;
4884 case OP_REG_R5900_Q
:
4885 return RTYPE_R5900_Q
;
4887 case OP_REG_R5900_R
:
4888 return RTYPE_R5900_R
;
4890 case OP_REG_R5900_ACC
:
4891 return RTYPE_R5900_ACC
;
4896 case OP_REG_MSA_CTRL
:
4902 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4905 check_regno (struct mips_arg_info
*arg
,
4906 enum mips_reg_operand_type type
, unsigned int regno
)
4908 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4909 arg
->seen_at
= TRUE
;
4911 if (type
== OP_REG_FP
4913 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4915 /* This was a warning prior to introducing O32 FPXX and FP64 support
4916 so maintain a warning for FP32 but raise an error for the new
4919 as_warn (_("float register should be even, was %d"), regno
);
4921 as_bad (_("float register should be even, was %d"), regno
);
4924 if (type
== OP_REG_CCC
)
4929 name
= arg
->insn
->insn_mo
->name
;
4930 length
= strlen (name
);
4931 if ((regno
& 1) != 0
4932 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4933 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4934 as_warn (_("condition code register should be even for %s, was %d"),
4937 if ((regno
& 3) != 0
4938 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4939 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4944 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4945 a register of type TYPE. Return true on success, storing the register
4946 number in *REGNO and warning about any dubious uses. */
4949 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4950 unsigned int symval
, unsigned int *regno
)
4952 if (type
== OP_REG_VEC
)
4953 symval
= mips_prefer_vec_regno (symval
);
4954 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4957 *regno
= symval
& RNUM_MASK
;
4958 check_regno (arg
, type
, *regno
);
4962 /* Try to interpret the next token in ARG as a register of type TYPE.
4963 Consume the token and return true on success, storing the register
4964 number in *REGNO. Return false on failure. */
4967 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4968 unsigned int *regno
)
4970 if (arg
->token
->type
== OT_REG
4971 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4979 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4980 Consume the token and return true on success, storing the register numbers
4981 in *REGNO1 and *REGNO2. Return false on failure. */
4984 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4985 unsigned int *regno1
, unsigned int *regno2
)
4987 if (match_reg (arg
, type
, regno1
))
4992 if (arg
->token
->type
== OT_REG_RANGE
4993 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4994 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4995 && *regno1
<= *regno2
)
5003 /* OP_INT matcher. */
5006 match_int_operand (struct mips_arg_info
*arg
,
5007 const struct mips_operand
*operand_base
)
5009 const struct mips_int_operand
*operand
;
5011 int min_val
, max_val
, factor
;
5014 operand
= (const struct mips_int_operand
*) operand_base
;
5015 factor
= 1 << operand
->shift
;
5016 min_val
= mips_int_operand_min (operand
);
5017 max_val
= mips_int_operand_max (operand
);
5019 if (operand_base
->lsb
== 0
5020 && operand_base
->size
== 16
5021 && operand
->shift
== 0
5022 && operand
->bias
== 0
5023 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5025 /* The operand can be relocated. */
5026 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5029 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5030 /* Relocation operators were used. Accept the arguent and
5031 leave the relocation value in offset_expr and offset_relocs
5032 for the caller to process. */
5035 if (offset_expr
.X_op
!= O_constant
)
5037 /* Accept non-constant operands if no later alternative matches,
5038 leaving it for the caller to process. */
5039 if (!arg
->lax_match
)
5041 offset_reloc
[0] = BFD_RELOC_LO16
;
5045 /* Clear the global state; we're going to install the operand
5047 sval
= offset_expr
.X_add_number
;
5048 offset_expr
.X_op
= O_absent
;
5050 /* For compatibility with older assemblers, we accept
5051 0x8000-0xffff as signed 16-bit numbers when only
5052 signed numbers are allowed. */
5055 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5056 if (!arg
->lax_match
&& sval
<= max_val
)
5062 if (!match_const_int (arg
, &sval
))
5066 arg
->last_op_int
= sval
;
5068 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5070 match_out_of_range (arg
);
5074 uval
= (unsigned int) sval
>> operand
->shift
;
5075 uval
-= operand
->bias
;
5077 /* Handle -mfix-cn63xxp1. */
5079 && mips_fix_cn63xxp1
5080 && !mips_opts
.micromips
5081 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5096 /* The rest must be changed to 28. */
5101 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5105 /* OP_MAPPED_INT matcher. */
5108 match_mapped_int_operand (struct mips_arg_info
*arg
,
5109 const struct mips_operand
*operand_base
)
5111 const struct mips_mapped_int_operand
*operand
;
5112 unsigned int uval
, num_vals
;
5115 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5116 if (!match_const_int (arg
, &sval
))
5119 num_vals
= 1 << operand_base
->size
;
5120 for (uval
= 0; uval
< num_vals
; uval
++)
5121 if (operand
->int_map
[uval
] == sval
)
5123 if (uval
== num_vals
)
5125 match_out_of_range (arg
);
5129 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5133 /* OP_MSB matcher. */
5136 match_msb_operand (struct mips_arg_info
*arg
,
5137 const struct mips_operand
*operand_base
)
5139 const struct mips_msb_operand
*operand
;
5140 int min_val
, max_val
, max_high
;
5141 offsetT size
, sval
, high
;
5143 operand
= (const struct mips_msb_operand
*) operand_base
;
5144 min_val
= operand
->bias
;
5145 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5146 max_high
= operand
->opsize
;
5148 if (!match_const_int (arg
, &size
))
5151 high
= size
+ arg
->last_op_int
;
5152 sval
= operand
->add_lsb
? high
: size
;
5154 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5156 match_out_of_range (arg
);
5159 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5163 /* OP_REG matcher. */
5166 match_reg_operand (struct mips_arg_info
*arg
,
5167 const struct mips_operand
*operand_base
)
5169 const struct mips_reg_operand
*operand
;
5170 unsigned int regno
, uval
, num_vals
;
5172 operand
= (const struct mips_reg_operand
*) operand_base
;
5173 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5176 if (operand
->reg_map
)
5178 num_vals
= 1 << operand
->root
.size
;
5179 for (uval
= 0; uval
< num_vals
; uval
++)
5180 if (operand
->reg_map
[uval
] == regno
)
5182 if (num_vals
== uval
)
5188 arg
->last_regno
= regno
;
5189 if (arg
->opnum
== 1)
5190 arg
->dest_regno
= regno
;
5191 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5195 /* OP_REG_PAIR matcher. */
5198 match_reg_pair_operand (struct mips_arg_info
*arg
,
5199 const struct mips_operand
*operand_base
)
5201 const struct mips_reg_pair_operand
*operand
;
5202 unsigned int regno1
, regno2
, uval
, num_vals
;
5204 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5205 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5206 || !match_char (arg
, ',')
5207 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5210 num_vals
= 1 << operand_base
->size
;
5211 for (uval
= 0; uval
< num_vals
; uval
++)
5212 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5214 if (uval
== num_vals
)
5217 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5221 /* OP_PCREL matcher. The caller chooses the relocation type. */
5224 match_pcrel_operand (struct mips_arg_info
*arg
)
5226 bfd_reloc_code_real_type r
[3];
5228 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5231 /* OP_PERF_REG matcher. */
5234 match_perf_reg_operand (struct mips_arg_info
*arg
,
5235 const struct mips_operand
*operand
)
5239 if (!match_const_int (arg
, &sval
))
5244 || (mips_opts
.arch
== CPU_R5900
5245 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5246 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5248 set_insn_error (arg
->argnum
, _("invalid performance register"));
5252 insn_insert_operand (arg
->insn
, operand
, sval
);
5256 /* OP_ADDIUSP matcher. */
5259 match_addiusp_operand (struct mips_arg_info
*arg
,
5260 const struct mips_operand
*operand
)
5265 if (!match_const_int (arg
, &sval
))
5270 match_out_of_range (arg
);
5275 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5277 match_out_of_range (arg
);
5281 uval
= (unsigned int) sval
;
5282 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5283 insn_insert_operand (arg
->insn
, operand
, uval
);
5287 /* OP_CLO_CLZ_DEST matcher. */
5290 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5291 const struct mips_operand
*operand
)
5295 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5298 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5302 /* OP_CHECK_PREV matcher. */
5305 match_check_prev_operand (struct mips_arg_info
*arg
,
5306 const struct mips_operand
*operand_base
)
5308 const struct mips_check_prev_operand
*operand
;
5311 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5313 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5316 if (!operand
->zero_ok
&& regno
== 0)
5319 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5320 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5321 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5323 arg
->last_regno
= regno
;
5324 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5331 /* OP_SAME_RS_RT matcher. */
5334 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5335 const struct mips_operand
*operand
)
5339 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5344 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5348 arg
->last_regno
= regno
;
5350 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5354 /* OP_LWM_SWM_LIST matcher. */
5357 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5358 const struct mips_operand
*operand
)
5360 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5361 struct mips_arg_info reset
;
5364 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5368 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5373 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5376 while (match_char (arg
, ',')
5377 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5380 if (operand
->size
== 2)
5382 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5388 and any permutations of these. */
5389 if ((reglist
& 0xfff1ffff) != 0x80010000)
5392 sregs
= (reglist
>> 17) & 7;
5397 /* The list must include at least one of ra and s0-sN,
5398 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5399 which are $23 and $30 respectively.) E.g.:
5407 and any permutations of these. */
5408 if ((reglist
& 0x3f00ffff) != 0)
5411 ra
= (reglist
>> 27) & 0x10;
5412 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5415 if ((sregs
& -sregs
) != sregs
)
5418 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5422 /* OP_ENTRY_EXIT_LIST matcher. */
5425 match_entry_exit_operand (struct mips_arg_info
*arg
,
5426 const struct mips_operand
*operand
)
5429 bfd_boolean is_exit
;
5431 /* The format is the same for both ENTRY and EXIT, but the constraints
5433 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5434 mask
= (is_exit
? 7 << 3 : 0);
5437 unsigned int regno1
, regno2
;
5438 bfd_boolean is_freg
;
5440 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5442 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5447 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5450 mask
|= (5 + regno2
) << 3;
5452 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5453 mask
|= (regno2
- 3) << 3;
5454 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5455 mask
|= (regno2
- 15) << 1;
5456 else if (regno1
== RA
&& regno2
== RA
)
5461 while (match_char (arg
, ','));
5463 insn_insert_operand (arg
->insn
, operand
, mask
);
5467 /* OP_SAVE_RESTORE_LIST matcher. */
5470 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5472 unsigned int opcode
, args
, statics
, sregs
;
5473 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5476 opcode
= arg
->insn
->insn_opcode
;
5478 num_frame_sizes
= 0;
5484 unsigned int regno1
, regno2
;
5486 if (arg
->token
->type
== OT_INTEGER
)
5488 /* Handle the frame size. */
5489 if (!match_const_int (arg
, &frame_size
))
5491 num_frame_sizes
+= 1;
5495 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5498 while (regno1
<= regno2
)
5500 if (regno1
>= 4 && regno1
<= 7)
5502 if (num_frame_sizes
== 0)
5504 args
|= 1 << (regno1
- 4);
5506 /* statics $a0-$a3 */
5507 statics
|= 1 << (regno1
- 4);
5509 else if (regno1
>= 16 && regno1
<= 23)
5511 sregs
|= 1 << (regno1
- 16);
5512 else if (regno1
== 30)
5515 else if (regno1
== 31)
5516 /* Add $ra to insn. */
5526 while (match_char (arg
, ','));
5528 /* Encode args/statics combination. */
5531 else if (args
== 0xf)
5532 /* All $a0-$a3 are args. */
5533 opcode
|= MIPS16_ALL_ARGS
<< 16;
5534 else if (statics
== 0xf)
5535 /* All $a0-$a3 are statics. */
5536 opcode
|= MIPS16_ALL_STATICS
<< 16;
5539 /* Count arg registers. */
5549 /* Count static registers. */
5551 while (statics
& 0x8)
5553 statics
= (statics
<< 1) & 0xf;
5559 /* Encode args/statics. */
5560 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5563 /* Encode $s0/$s1. */
5564 if (sregs
& (1 << 0)) /* $s0 */
5566 if (sregs
& (1 << 1)) /* $s1 */
5570 /* Encode $s2-$s8. */
5579 opcode
|= num_sregs
<< 24;
5581 /* Encode frame size. */
5582 if (num_frame_sizes
== 0)
5584 set_insn_error (arg
->argnum
, _("missing frame size"));
5587 if (num_frame_sizes
> 1)
5589 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5592 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5594 set_insn_error (arg
->argnum
, _("invalid frame size"));
5597 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5600 opcode
|= (((frame_size
& 0xf0) << 16)
5601 | (frame_size
& 0x0f));
5604 /* Finally build the instruction. */
5605 if ((opcode
>> 16) != 0 || frame_size
== 0)
5606 opcode
|= MIPS16_EXTEND
;
5607 arg
->insn
->insn_opcode
= opcode
;
5611 /* OP_MDMX_IMM_REG matcher. */
5614 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5615 const struct mips_operand
*operand
)
5617 unsigned int regno
, uval
;
5619 const struct mips_opcode
*opcode
;
5621 /* The mips_opcode records whether this is an octobyte or quadhalf
5622 instruction. Start out with that bit in place. */
5623 opcode
= arg
->insn
->insn_mo
;
5624 uval
= mips_extract_operand (operand
, opcode
->match
);
5625 is_qh
= (uval
!= 0);
5627 if (arg
->token
->type
== OT_REG
)
5629 if ((opcode
->membership
& INSN_5400
)
5630 && strcmp (opcode
->name
, "rzu.ob") == 0)
5632 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5637 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5641 /* Check whether this is a vector register or a broadcast of
5642 a single element. */
5643 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5645 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5647 set_insn_error (arg
->argnum
, _("invalid element selector"));
5650 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5655 /* A full vector. */
5656 if ((opcode
->membership
& INSN_5400
)
5657 && (strcmp (opcode
->name
, "sll.ob") == 0
5658 || strcmp (opcode
->name
, "srl.ob") == 0))
5660 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5666 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5668 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5676 if (!match_const_int (arg
, &sval
))
5678 if (sval
< 0 || sval
> 31)
5680 match_out_of_range (arg
);
5683 uval
|= (sval
& 31);
5685 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5687 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5689 insn_insert_operand (arg
->insn
, operand
, uval
);
5693 /* OP_IMM_INDEX matcher. */
5696 match_imm_index_operand (struct mips_arg_info
*arg
,
5697 const struct mips_operand
*operand
)
5699 unsigned int max_val
;
5701 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5704 max_val
= (1 << operand
->size
) - 1;
5705 if (arg
->token
->u
.index
> max_val
)
5707 match_out_of_range (arg
);
5710 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5715 /* OP_REG_INDEX matcher. */
5718 match_reg_index_operand (struct mips_arg_info
*arg
,
5719 const struct mips_operand
*operand
)
5723 if (arg
->token
->type
!= OT_REG_INDEX
)
5726 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5729 insn_insert_operand (arg
->insn
, operand
, regno
);
5734 /* OP_PC matcher. */
5737 match_pc_operand (struct mips_arg_info
*arg
)
5739 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5747 /* OP_NON_ZERO_REG matcher. */
5750 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5751 const struct mips_operand
*operand
)
5755 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5761 arg
->last_regno
= regno
;
5762 insn_insert_operand (arg
->insn
, operand
, regno
);
5766 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5767 register that we need to match. */
5770 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5774 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5777 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5778 the length of the value in bytes (4 for float, 8 for double) and
5779 USING_GPRS says whether the destination is a GPR rather than an FPR.
5781 Return the constant in IMM and OFFSET as follows:
5783 - If the constant should be loaded via memory, set IMM to O_absent and
5784 OFFSET to the memory address.
5786 - Otherwise, if the constant should be loaded into two 32-bit registers,
5787 set IMM to the O_constant to load into the high register and OFFSET
5788 to the corresponding value for the low register.
5790 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5792 These constants only appear as the last operand in an instruction,
5793 and every instruction that accepts them in any variant accepts them
5794 in all variants. This means we don't have to worry about backing out
5795 any changes if the instruction does not match. We just match
5796 unconditionally and report an error if the constant is invalid. */
5799 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5800 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5805 const char *newname
;
5806 unsigned char *data
;
5808 /* Where the constant is placed is based on how the MIPS assembler
5811 length == 4 && using_gprs -- immediate value only
5812 length == 8 && using_gprs -- .rdata or immediate value
5813 length == 4 && !using_gprs -- .lit4 or immediate value
5814 length == 8 && !using_gprs -- .lit8 or immediate value
5816 The .lit4 and .lit8 sections are only used if permitted by the
5818 if (arg
->token
->type
!= OT_FLOAT
)
5820 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5824 gas_assert (arg
->token
->u
.flt
.length
== length
);
5825 data
= arg
->token
->u
.flt
.data
;
5828 /* Handle 32-bit constants for which an immediate value is best. */
5831 || g_switch_value
< 4
5832 || (data
[0] == 0 && data
[1] == 0)
5833 || (data
[2] == 0 && data
[3] == 0)))
5835 imm
->X_op
= O_constant
;
5836 if (!target_big_endian
)
5837 imm
->X_add_number
= bfd_getl32 (data
);
5839 imm
->X_add_number
= bfd_getb32 (data
);
5840 offset
->X_op
= O_absent
;
5844 /* Handle 64-bit constants for which an immediate value is best. */
5846 && !mips_disable_float_construction
5847 /* Constants can only be constructed in GPRs and copied to FPRs if the
5848 GPRs are at least as wide as the FPRs or MTHC1 is available.
5849 Unlike most tests for 32-bit floating-point registers this check
5850 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5851 permit 64-bit moves without MXHC1.
5852 Force the constant into memory otherwise. */
5855 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5857 && ((data
[0] == 0 && data
[1] == 0)
5858 || (data
[2] == 0 && data
[3] == 0))
5859 && ((data
[4] == 0 && data
[5] == 0)
5860 || (data
[6] == 0 && data
[7] == 0)))
5862 /* The value is simple enough to load with a couple of instructions.
5863 If using 32-bit registers, set IMM to the high order 32 bits and
5864 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5866 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5868 imm
->X_op
= O_constant
;
5869 offset
->X_op
= O_constant
;
5870 if (!target_big_endian
)
5872 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5873 offset
->X_add_number
= bfd_getl32 (data
);
5877 imm
->X_add_number
= bfd_getb32 (data
);
5878 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5880 if (offset
->X_add_number
== 0)
5881 offset
->X_op
= O_absent
;
5885 imm
->X_op
= O_constant
;
5886 if (!target_big_endian
)
5887 imm
->X_add_number
= bfd_getl64 (data
);
5889 imm
->X_add_number
= bfd_getb64 (data
);
5890 offset
->X_op
= O_absent
;
5895 /* Switch to the right section. */
5897 subseg
= now_subseg
;
5900 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5905 if (using_gprs
|| g_switch_value
< 8)
5906 newname
= RDATA_SECTION_NAME
;
5911 new_seg
= subseg_new (newname
, (subsegT
) 0);
5912 bfd_set_section_flags (stdoutput
, new_seg
,
5913 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5914 frag_align (length
== 4 ? 2 : 3, 0, 0);
5915 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5916 record_alignment (new_seg
, 4);
5918 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5920 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5922 /* Set the argument to the current address in the section. */
5923 imm
->X_op
= O_absent
;
5924 offset
->X_op
= O_symbol
;
5925 offset
->X_add_symbol
= symbol_temp_new_now ();
5926 offset
->X_add_number
= 0;
5928 /* Put the floating point number into the section. */
5929 p
= frag_more (length
);
5930 memcpy (p
, data
, length
);
5932 /* Switch back to the original section. */
5933 subseg_set (seg
, subseg
);
5937 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5941 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5942 const struct mips_operand
*operand
,
5943 bfd_boolean match_p
)
5947 /* The operand can be an XYZW mask or a single 2-bit channel index
5948 (with X being 0). */
5949 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5951 /* The suffix can be omitted when it is already part of the opcode. */
5952 if (arg
->token
->type
!= OT_CHANNELS
)
5955 uval
= arg
->token
->u
.channels
;
5956 if (operand
->size
== 2)
5958 /* Check that a single bit is set and convert it into a 2-bit index. */
5959 if ((uval
& -uval
) != uval
)
5961 uval
= 4 - ffs (uval
);
5964 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5969 insn_insert_operand (arg
->insn
, operand
, uval
);
5973 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5974 of the argument text if the match is successful, otherwise return null. */
5977 match_operand (struct mips_arg_info
*arg
,
5978 const struct mips_operand
*operand
)
5980 switch (operand
->type
)
5983 return match_int_operand (arg
, operand
);
5986 return match_mapped_int_operand (arg
, operand
);
5989 return match_msb_operand (arg
, operand
);
5992 case OP_OPTIONAL_REG
:
5993 return match_reg_operand (arg
, operand
);
5996 return match_reg_pair_operand (arg
, operand
);
5999 return match_pcrel_operand (arg
);
6002 return match_perf_reg_operand (arg
, operand
);
6004 case OP_ADDIUSP_INT
:
6005 return match_addiusp_operand (arg
, operand
);
6007 case OP_CLO_CLZ_DEST
:
6008 return match_clo_clz_dest_operand (arg
, operand
);
6010 case OP_LWM_SWM_LIST
:
6011 return match_lwm_swm_list_operand (arg
, operand
);
6013 case OP_ENTRY_EXIT_LIST
:
6014 return match_entry_exit_operand (arg
, operand
);
6016 case OP_SAVE_RESTORE_LIST
:
6017 return match_save_restore_list_operand (arg
);
6019 case OP_MDMX_IMM_REG
:
6020 return match_mdmx_imm_reg_operand (arg
, operand
);
6022 case OP_REPEAT_DEST_REG
:
6023 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6025 case OP_REPEAT_PREV_REG
:
6026 return match_tied_reg_operand (arg
, arg
->last_regno
);
6029 return match_pc_operand (arg
);
6032 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6034 case OP_VU0_MATCH_SUFFIX
:
6035 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6038 return match_imm_index_operand (arg
, operand
);
6041 return match_reg_index_operand (arg
, operand
);
6044 return match_same_rs_rt_operand (arg
, operand
);
6047 return match_check_prev_operand (arg
, operand
);
6049 case OP_NON_ZERO_REG
:
6050 return match_non_zero_reg_operand (arg
, operand
);
6055 /* ARG is the state after successfully matching an instruction.
6056 Issue any queued-up warnings. */
6059 check_completed_insn (struct mips_arg_info
*arg
)
6064 as_warn (_("used $at without \".set noat\""));
6066 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6070 /* Return true if modifying general-purpose register REG needs a delay. */
6073 reg_needs_delay (unsigned int reg
)
6075 unsigned long prev_pinfo
;
6077 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6078 if (!mips_opts
.noreorder
6079 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6080 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6081 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6087 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6088 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6089 by VR4120 errata. */
6092 classify_vr4120_insn (const char *name
)
6094 if (strncmp (name
, "macc", 4) == 0)
6095 return FIX_VR4120_MACC
;
6096 if (strncmp (name
, "dmacc", 5) == 0)
6097 return FIX_VR4120_DMACC
;
6098 if (strncmp (name
, "mult", 4) == 0)
6099 return FIX_VR4120_MULT
;
6100 if (strncmp (name
, "dmult", 5) == 0)
6101 return FIX_VR4120_DMULT
;
6102 if (strstr (name
, "div"))
6103 return FIX_VR4120_DIV
;
6104 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6105 return FIX_VR4120_MTHILO
;
6106 return NUM_FIX_VR4120_CLASSES
;
6109 #define INSN_ERET 0x42000018
6110 #define INSN_DERET 0x4200001f
6111 #define INSN_DMULT 0x1c
6112 #define INSN_DMULTU 0x1d
6114 /* Return the number of instructions that must separate INSN1 and INSN2,
6115 where INSN1 is the earlier instruction. Return the worst-case value
6116 for any INSN2 if INSN2 is null. */
6119 insns_between (const struct mips_cl_insn
*insn1
,
6120 const struct mips_cl_insn
*insn2
)
6122 unsigned long pinfo1
, pinfo2
;
6125 /* If INFO2 is null, pessimistically assume that all flags are set for
6126 the second instruction. */
6127 pinfo1
= insn1
->insn_mo
->pinfo
;
6128 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6130 /* For most targets, write-after-read dependencies on the HI and LO
6131 registers must be separated by at least two instructions. */
6132 if (!hilo_interlocks
)
6134 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6136 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6140 /* If we're working around r7000 errata, there must be two instructions
6141 between an mfhi or mflo and any instruction that uses the result. */
6142 if (mips_7000_hilo_fix
6143 && !mips_opts
.micromips
6144 && MF_HILO_INSN (pinfo1
)
6145 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6148 /* If we're working around 24K errata, one instruction is required
6149 if an ERET or DERET is followed by a branch instruction. */
6150 if (mips_fix_24k
&& !mips_opts
.micromips
)
6152 if (insn1
->insn_opcode
== INSN_ERET
6153 || insn1
->insn_opcode
== INSN_DERET
)
6156 || insn2
->insn_opcode
== INSN_ERET
6157 || insn2
->insn_opcode
== INSN_DERET
6158 || delayed_branch_p (insn2
))
6163 /* If we're working around PMC RM7000 errata, there must be three
6164 nops between a dmult and a load instruction. */
6165 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6167 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6168 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6170 if (pinfo2
& INSN_LOAD_MEMORY
)
6175 /* If working around VR4120 errata, check for combinations that need
6176 a single intervening instruction. */
6177 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6179 unsigned int class1
, class2
;
6181 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6182 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6186 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6187 if (vr4120_conflicts
[class1
] & (1 << class2
))
6192 if (!HAVE_CODE_COMPRESSION
)
6194 /* Check for GPR or coprocessor load delays. All such delays
6195 are on the RT register. */
6196 /* Itbl support may require additional care here. */
6197 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6198 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6200 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6204 /* Check for generic coprocessor hazards.
6206 This case is not handled very well. There is no special
6207 knowledge of CP0 handling, and the coprocessors other than
6208 the floating point unit are not distinguished at all. */
6209 /* Itbl support may require additional care here. FIXME!
6210 Need to modify this to include knowledge about
6211 user specified delays! */
6212 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6213 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6215 /* Handle cases where INSN1 writes to a known general coprocessor
6216 register. There must be a one instruction delay before INSN2
6217 if INSN2 reads that register, otherwise no delay is needed. */
6218 mask
= fpr_write_mask (insn1
);
6221 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6226 /* Read-after-write dependencies on the control registers
6227 require a two-instruction gap. */
6228 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6229 && (pinfo2
& INSN_READ_COND_CODE
))
6232 /* We don't know exactly what INSN1 does. If INSN2 is
6233 also a coprocessor instruction, assume there must be
6234 a one instruction gap. */
6235 if (pinfo2
& INSN_COP
)
6240 /* Check for read-after-write dependencies on the coprocessor
6241 control registers in cases where INSN1 does not need a general
6242 coprocessor delay. This means that INSN1 is a floating point
6243 comparison instruction. */
6244 /* Itbl support may require additional care here. */
6245 else if (!cop_interlocks
6246 && (pinfo1
& INSN_WRITE_COND_CODE
)
6247 && (pinfo2
& INSN_READ_COND_CODE
))
6251 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6252 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6254 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6255 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6256 || (insn2
&& delayed_branch_p (insn2
))))
6262 /* Return the number of nops that would be needed to work around the
6263 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6264 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6265 that are contained within the first IGNORE instructions of HIST. */
6268 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6269 const struct mips_cl_insn
*insn
)
6274 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6275 are not affected by the errata. */
6277 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6278 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6279 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6282 /* Search for the first MFLO or MFHI. */
6283 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6284 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6286 /* Extract the destination register. */
6287 mask
= gpr_write_mask (&hist
[i
]);
6289 /* No nops are needed if INSN reads that register. */
6290 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6293 /* ...or if any of the intervening instructions do. */
6294 for (j
= 0; j
< i
; j
++)
6295 if (gpr_read_mask (&hist
[j
]) & mask
)
6299 return MAX_VR4130_NOPS
- i
;
6304 #define BASE_REG_EQ(INSN1, INSN2) \
6305 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6306 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6308 /* Return the minimum alignment for this store instruction. */
6311 fix_24k_align_to (const struct mips_opcode
*mo
)
6313 if (strcmp (mo
->name
, "sh") == 0)
6316 if (strcmp (mo
->name
, "swc1") == 0
6317 || strcmp (mo
->name
, "swc2") == 0
6318 || strcmp (mo
->name
, "sw") == 0
6319 || strcmp (mo
->name
, "sc") == 0
6320 || strcmp (mo
->name
, "s.s") == 0)
6323 if (strcmp (mo
->name
, "sdc1") == 0
6324 || strcmp (mo
->name
, "sdc2") == 0
6325 || strcmp (mo
->name
, "s.d") == 0)
6332 struct fix_24k_store_info
6334 /* Immediate offset, if any, for this store instruction. */
6336 /* Alignment required by this store instruction. */
6338 /* True for register offsets. */
6339 int register_offset
;
6342 /* Comparison function used by qsort. */
6345 fix_24k_sort (const void *a
, const void *b
)
6347 const struct fix_24k_store_info
*pos1
= a
;
6348 const struct fix_24k_store_info
*pos2
= b
;
6350 return (pos1
->off
- pos2
->off
);
6353 /* INSN is a store instruction. Try to record the store information
6354 in STINFO. Return false if the information isn't known. */
6357 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6358 const struct mips_cl_insn
*insn
)
6360 /* The instruction must have a known offset. */
6361 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6364 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6365 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6369 /* Return the number of nops that would be needed to work around the 24k
6370 "lost data on stores during refill" errata if instruction INSN
6371 immediately followed the 2 instructions described by HIST.
6372 Ignore hazards that are contained within the first IGNORE
6373 instructions of HIST.
6375 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6376 for the data cache refills and store data. The following describes
6377 the scenario where the store data could be lost.
6379 * A data cache miss, due to either a load or a store, causing fill
6380 data to be supplied by the memory subsystem
6381 * The first three doublewords of fill data are returned and written
6383 * A sequence of four stores occurs in consecutive cycles around the
6384 final doubleword of the fill:
6388 * Zero, One or more instructions
6391 The four stores A-D must be to different doublewords of the line that
6392 is being filled. The fourth instruction in the sequence above permits
6393 the fill of the final doubleword to be transferred from the FSB into
6394 the cache. In the sequence above, the stores may be either integer
6395 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6396 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6397 different doublewords on the line. If the floating point unit is
6398 running in 1:2 mode, it is not possible to create the sequence above
6399 using only floating point store instructions.
6401 In this case, the cache line being filled is incorrectly marked
6402 invalid, thereby losing the data from any store to the line that
6403 occurs between the original miss and the completion of the five
6404 cycle sequence shown above.
6406 The workarounds are:
6408 * Run the data cache in write-through mode.
6409 * Insert a non-store instruction between
6410 Store A and Store B or Store B and Store C. */
6413 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6414 const struct mips_cl_insn
*insn
)
6416 struct fix_24k_store_info pos
[3];
6417 int align
, i
, base_offset
;
6422 /* If the previous instruction wasn't a store, there's nothing to
6424 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6427 /* If the instructions after the previous one are unknown, we have
6428 to assume the worst. */
6432 /* Check whether we are dealing with three consecutive stores. */
6433 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6434 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6437 /* If we don't know the relationship between the store addresses,
6438 assume the worst. */
6439 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6440 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6443 if (!fix_24k_record_store_info (&pos
[0], insn
)
6444 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6445 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6448 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6450 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6451 X bytes and such that the base register + X is known to be aligned
6454 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6458 align
= pos
[0].align_to
;
6459 base_offset
= pos
[0].off
;
6460 for (i
= 1; i
< 3; i
++)
6461 if (align
< pos
[i
].align_to
)
6463 align
= pos
[i
].align_to
;
6464 base_offset
= pos
[i
].off
;
6466 for (i
= 0; i
< 3; i
++)
6467 pos
[i
].off
-= base_offset
;
6470 pos
[0].off
&= ~align
+ 1;
6471 pos
[1].off
&= ~align
+ 1;
6472 pos
[2].off
&= ~align
+ 1;
6474 /* If any two stores write to the same chunk, they also write to the
6475 same doubleword. The offsets are still sorted at this point. */
6476 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6479 /* A range of at least 9 bytes is needed for the stores to be in
6480 non-overlapping doublewords. */
6481 if (pos
[2].off
- pos
[0].off
<= 8)
6484 if (pos
[2].off
- pos
[1].off
>= 24
6485 || pos
[1].off
- pos
[0].off
>= 24
6486 || pos
[2].off
- pos
[0].off
>= 32)
6492 /* Return the number of nops that would be needed if instruction INSN
6493 immediately followed the MAX_NOPS instructions given by HIST,
6494 where HIST[0] is the most recent instruction. Ignore hazards
6495 between INSN and the first IGNORE instructions in HIST.
6497 If INSN is null, return the worse-case number of nops for any
6501 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6502 const struct mips_cl_insn
*insn
)
6504 int i
, nops
, tmp_nops
;
6507 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6509 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6510 if (tmp_nops
> nops
)
6514 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6516 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6517 if (tmp_nops
> nops
)
6521 if (mips_fix_24k
&& !mips_opts
.micromips
)
6523 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6524 if (tmp_nops
> nops
)
6531 /* The variable arguments provide NUM_INSNS extra instructions that
6532 might be added to HIST. Return the largest number of nops that
6533 would be needed after the extended sequence, ignoring hazards
6534 in the first IGNORE instructions. */
6537 nops_for_sequence (int num_insns
, int ignore
,
6538 const struct mips_cl_insn
*hist
, ...)
6541 struct mips_cl_insn buffer
[MAX_NOPS
];
6542 struct mips_cl_insn
*cursor
;
6545 va_start (args
, hist
);
6546 cursor
= buffer
+ num_insns
;
6547 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6548 while (cursor
> buffer
)
6549 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6551 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6556 /* Like nops_for_insn, but if INSN is a branch, take into account the
6557 worst-case delay for the branch target. */
6560 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6561 const struct mips_cl_insn
*insn
)
6565 nops
= nops_for_insn (ignore
, hist
, insn
);
6566 if (delayed_branch_p (insn
))
6568 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6569 hist
, insn
, get_delay_slot_nop (insn
));
6570 if (tmp_nops
> nops
)
6573 else if (compact_branch_p (insn
))
6575 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6576 if (tmp_nops
> nops
)
6582 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6585 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6587 gas_assert (!HAVE_CODE_COMPRESSION
);
6588 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6589 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6592 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6593 jr target pc &= 'hffff_ffff_cfff_ffff. */
6596 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6598 gas_assert (!HAVE_CODE_COMPRESSION
);
6599 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6600 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6601 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6609 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6610 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6613 ep
.X_op
= O_constant
;
6614 ep
.X_add_number
= 0xcfff0000;
6615 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6616 ep
.X_add_number
= 0xffff;
6617 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6618 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6623 fix_loongson2f (struct mips_cl_insn
* ip
)
6625 if (mips_fix_loongson2f_nop
)
6626 fix_loongson2f_nop (ip
);
6628 if (mips_fix_loongson2f_jump
)
6629 fix_loongson2f_jump (ip
);
6632 /* IP is a branch that has a delay slot, and we need to fill it
6633 automatically. Return true if we can do that by swapping IP
6634 with the previous instruction.
6635 ADDRESS_EXPR is an operand of the instruction to be used with
6639 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6640 bfd_reloc_code_real_type
*reloc_type
)
6642 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6643 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6644 unsigned int fpr_read
, prev_fpr_write
;
6646 /* -O2 and above is required for this optimization. */
6647 if (mips_optimize
< 2)
6650 /* If we have seen .set volatile or .set nomove, don't optimize. */
6651 if (mips_opts
.nomove
)
6654 /* We can't swap if the previous instruction's position is fixed. */
6655 if (history
[0].fixed_p
)
6658 /* If the previous previous insn was in a .set noreorder, we can't
6659 swap. Actually, the MIPS assembler will swap in this situation.
6660 However, gcc configured -with-gnu-as will generate code like
6668 in which we can not swap the bne and INSN. If gcc is not configured
6669 -with-gnu-as, it does not output the .set pseudo-ops. */
6670 if (history
[1].noreorder_p
)
6673 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6674 This means that the previous instruction was a 4-byte one anyhow. */
6675 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6678 /* If the branch is itself the target of a branch, we can not swap.
6679 We cheat on this; all we check for is whether there is a label on
6680 this instruction. If there are any branches to anything other than
6681 a label, users must use .set noreorder. */
6682 if (seg_info (now_seg
)->label_list
)
6685 /* If the previous instruction is in a variant frag other than this
6686 branch's one, we cannot do the swap. This does not apply to
6687 MIPS16 code, which uses variant frags for different purposes. */
6688 if (!mips_opts
.mips16
6690 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6693 /* We do not swap with instructions that cannot architecturally
6694 be placed in a branch delay slot, such as SYNC or ERET. We
6695 also refrain from swapping with a trap instruction, since it
6696 complicates trap handlers to have the trap instruction be in
6698 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6699 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6702 /* Check for conflicts between the branch and the instructions
6703 before the candidate delay slot. */
6704 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6707 /* Check for conflicts between the swapped sequence and the
6708 target of the branch. */
6709 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6712 /* If the branch reads a register that the previous
6713 instruction sets, we can not swap. */
6714 gpr_read
= gpr_read_mask (ip
);
6715 prev_gpr_write
= gpr_write_mask (&history
[0]);
6716 if (gpr_read
& prev_gpr_write
)
6719 fpr_read
= fpr_read_mask (ip
);
6720 prev_fpr_write
= fpr_write_mask (&history
[0]);
6721 if (fpr_read
& prev_fpr_write
)
6724 /* If the branch writes a register that the previous
6725 instruction sets, we can not swap. */
6726 gpr_write
= gpr_write_mask (ip
);
6727 if (gpr_write
& prev_gpr_write
)
6730 /* If the branch writes a register that the previous
6731 instruction reads, we can not swap. */
6732 prev_gpr_read
= gpr_read_mask (&history
[0]);
6733 if (gpr_write
& prev_gpr_read
)
6736 /* If one instruction sets a condition code and the
6737 other one uses a condition code, we can not swap. */
6738 pinfo
= ip
->insn_mo
->pinfo
;
6739 if ((pinfo
& INSN_READ_COND_CODE
)
6740 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6742 if ((pinfo
& INSN_WRITE_COND_CODE
)
6743 && (prev_pinfo
& INSN_READ_COND_CODE
))
6746 /* If the previous instruction uses the PC, we can not swap. */
6747 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6748 if (prev_pinfo2
& INSN2_READ_PC
)
6751 /* If the previous instruction has an incorrect size for a fixed
6752 branch delay slot in microMIPS mode, we cannot swap. */
6753 pinfo2
= ip
->insn_mo
->pinfo2
;
6754 if (mips_opts
.micromips
6755 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6756 && insn_length (history
) != 2)
6758 if (mips_opts
.micromips
6759 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6760 && insn_length (history
) != 4)
6763 /* On R5900 short loops need to be fixed by inserting a nop in
6764 the branch delay slots.
6765 A short loop can be terminated too early. */
6766 if (mips_opts
.arch
== CPU_R5900
6767 /* Check if instruction has a parameter, ignore "j $31". */
6768 && (address_expr
!= NULL
)
6769 /* Parameter must be 16 bit. */
6770 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6771 /* Branch to same segment. */
6772 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6773 /* Branch to same code fragment. */
6774 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6775 /* Can only calculate branch offset if value is known. */
6776 && symbol_constant_p (address_expr
->X_add_symbol
)
6777 /* Check if branch is really conditional. */
6778 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6779 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6780 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6783 /* Check if loop is shorter than 6 instructions including
6784 branch and delay slot. */
6785 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6792 /* When the loop includes branches or jumps,
6793 it is not a short loop. */
6794 for (i
= 0; i
< (distance
/ 4); i
++)
6796 if ((history
[i
].cleared_p
)
6797 || delayed_branch_p (&history
[i
]))
6805 /* Insert nop after branch to fix short loop. */
6814 /* Decide how we should add IP to the instruction stream.
6815 ADDRESS_EXPR is an operand of the instruction to be used with
6818 static enum append_method
6819 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6820 bfd_reloc_code_real_type
*reloc_type
)
6822 /* The relaxed version of a macro sequence must be inherently
6824 if (mips_relax
.sequence
== 2)
6827 /* We must not dabble with instructions in a ".set noreorder" block. */
6828 if (mips_opts
.noreorder
)
6831 /* Otherwise, it's our responsibility to fill branch delay slots. */
6832 if (delayed_branch_p (ip
))
6834 if (!branch_likely_p (ip
)
6835 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6838 if (mips_opts
.mips16
6839 && ISA_SUPPORTS_MIPS16E
6840 && gpr_read_mask (ip
) != 0)
6841 return APPEND_ADD_COMPACT
;
6843 if (mips_opts
.micromips
6844 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6845 || (!forced_insn_length
6846 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6847 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6848 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6849 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6850 return APPEND_ADD_COMPACT
;
6852 return APPEND_ADD_WITH_NOP
;
6858 /* IP is an instruction whose opcode we have just changed, END points
6859 to the end of the opcode table processed. Point IP->insn_mo to the
6860 new opcode's definition. */
6863 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6865 const struct mips_opcode
*mo
;
6867 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6868 if (mo
->pinfo
!= INSN_MACRO
6869 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6877 /* IP is a MIPS16 instruction whose opcode we have just changed.
6878 Point IP->insn_mo to the new opcode's definition. */
6881 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6883 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6886 /* IP is a microMIPS instruction whose opcode we have just changed.
6887 Point IP->insn_mo to the new opcode's definition. */
6890 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6892 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6895 /* For microMIPS macros, we need to generate a local number label
6896 as the target of branches. */
6897 #define MICROMIPS_LABEL_CHAR '\037'
6898 static unsigned long micromips_target_label
;
6899 static char micromips_target_name
[32];
6902 micromips_label_name (void)
6904 char *p
= micromips_target_name
;
6905 char symbol_name_temporary
[24];
6913 l
= micromips_target_label
;
6914 #ifdef LOCAL_LABEL_PREFIX
6915 *p
++ = LOCAL_LABEL_PREFIX
;
6918 *p
++ = MICROMIPS_LABEL_CHAR
;
6921 symbol_name_temporary
[i
++] = l
% 10 + '0';
6926 *p
++ = symbol_name_temporary
[--i
];
6929 return micromips_target_name
;
6933 micromips_label_expr (expressionS
*label_expr
)
6935 label_expr
->X_op
= O_symbol
;
6936 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6937 label_expr
->X_add_number
= 0;
6941 micromips_label_inc (void)
6943 micromips_target_label
++;
6944 *micromips_target_name
= '\0';
6948 micromips_add_label (void)
6952 s
= colon (micromips_label_name ());
6953 micromips_label_inc ();
6954 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6957 /* If assembling microMIPS code, then return the microMIPS reloc
6958 corresponding to the requested one if any. Otherwise return
6959 the reloc unchanged. */
6961 static bfd_reloc_code_real_type
6962 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6964 static const bfd_reloc_code_real_type relocs
[][2] =
6966 /* Keep sorted incrementally by the left-hand key. */
6967 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6968 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6969 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6970 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6971 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6972 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6973 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6974 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6975 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6976 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6977 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6978 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6979 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6980 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6981 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6982 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6983 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6984 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6985 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6986 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6987 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6988 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6989 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6990 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6991 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6992 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6993 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6995 bfd_reloc_code_real_type r
;
6998 if (!mips_opts
.micromips
)
7000 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7006 return relocs
[i
][1];
7011 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7012 Return true on success, storing the resolved value in RESULT. */
7015 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7020 case BFD_RELOC_MIPS_HIGHEST
:
7021 case BFD_RELOC_MICROMIPS_HIGHEST
:
7022 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7025 case BFD_RELOC_MIPS_HIGHER
:
7026 case BFD_RELOC_MICROMIPS_HIGHER
:
7027 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7030 case BFD_RELOC_HI16_S
:
7031 case BFD_RELOC_HI16_S_PCREL
:
7032 case BFD_RELOC_MICROMIPS_HI16_S
:
7033 case BFD_RELOC_MIPS16_HI16_S
:
7034 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7037 case BFD_RELOC_HI16
:
7038 case BFD_RELOC_MICROMIPS_HI16
:
7039 case BFD_RELOC_MIPS16_HI16
:
7040 *result
= (operand
>> 16) & 0xffff;
7043 case BFD_RELOC_LO16
:
7044 case BFD_RELOC_LO16_PCREL
:
7045 case BFD_RELOC_MICROMIPS_LO16
:
7046 case BFD_RELOC_MIPS16_LO16
:
7047 *result
= operand
& 0xffff;
7050 case BFD_RELOC_UNUSED
:
7059 /* Output an instruction. IP is the instruction information.
7060 ADDRESS_EXPR is an operand of the instruction to be used with
7061 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7062 a macro expansion. */
7065 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7066 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7068 unsigned long prev_pinfo2
, pinfo
;
7069 bfd_boolean relaxed_branch
= FALSE
;
7070 enum append_method method
;
7071 bfd_boolean relax32
;
7074 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7075 fix_loongson2f (ip
);
7077 file_ase_mips16
|= mips_opts
.mips16
;
7078 file_ase_micromips
|= mips_opts
.micromips
;
7080 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7081 pinfo
= ip
->insn_mo
->pinfo
;
7083 /* Don't raise alarm about `nods' frags as they'll fill in the right
7084 kind of nop in relaxation if required. */
7085 if (mips_opts
.micromips
7087 && !(history
[0].frag
7088 && history
[0].frag
->fr_type
== rs_machine_dependent
7089 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7090 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7091 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7092 && micromips_insn_length (ip
->insn_mo
) != 2)
7093 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7094 && micromips_insn_length (ip
->insn_mo
) != 4)))
7095 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7096 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7098 if (address_expr
== NULL
)
7100 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7101 && reloc_type
[1] == BFD_RELOC_UNUSED
7102 && reloc_type
[2] == BFD_RELOC_UNUSED
7103 && address_expr
->X_op
== O_constant
)
7105 switch (*reloc_type
)
7107 case BFD_RELOC_MIPS_JMP
:
7111 /* Shift is 2, unusually, for microMIPS JALX. */
7112 shift
= (mips_opts
.micromips
7113 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7114 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7115 as_bad (_("jump to misaligned address (0x%lx)"),
7116 (unsigned long) address_expr
->X_add_number
);
7117 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7123 case BFD_RELOC_MIPS16_JMP
:
7124 if ((address_expr
->X_add_number
& 3) != 0)
7125 as_bad (_("jump to misaligned address (0x%lx)"),
7126 (unsigned long) address_expr
->X_add_number
);
7128 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7129 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7130 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7134 case BFD_RELOC_16_PCREL_S2
:
7138 shift
= mips_opts
.micromips
? 1 : 2;
7139 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7140 as_bad (_("branch to misaligned address (0x%lx)"),
7141 (unsigned long) address_expr
->X_add_number
);
7142 if (!mips_relax_branch
)
7144 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7145 & ~((1 << (shift
+ 16)) - 1))
7146 as_bad (_("branch address range overflow (0x%lx)"),
7147 (unsigned long) address_expr
->X_add_number
);
7148 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7154 case BFD_RELOC_MIPS_21_PCREL_S2
:
7159 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7160 as_bad (_("branch to misaligned address (0x%lx)"),
7161 (unsigned long) address_expr
->X_add_number
);
7162 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7163 & ~((1 << (shift
+ 21)) - 1))
7164 as_bad (_("branch address range overflow (0x%lx)"),
7165 (unsigned long) address_expr
->X_add_number
);
7166 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7171 case BFD_RELOC_MIPS_26_PCREL_S2
:
7176 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7177 as_bad (_("branch to misaligned address (0x%lx)"),
7178 (unsigned long) address_expr
->X_add_number
);
7179 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7180 & ~((1 << (shift
+ 26)) - 1))
7181 as_bad (_("branch address range overflow (0x%lx)"),
7182 (unsigned long) address_expr
->X_add_number
);
7183 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7192 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7195 ip
->insn_opcode
|= value
& 0xffff;
7203 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7205 /* There are a lot of optimizations we could do that we don't.
7206 In particular, we do not, in general, reorder instructions.
7207 If you use gcc with optimization, it will reorder
7208 instructions and generally do much more optimization then we
7209 do here; repeating all that work in the assembler would only
7210 benefit hand written assembly code, and does not seem worth
7212 int nops
= (mips_optimize
== 0
7213 ? nops_for_insn (0, history
, NULL
)
7214 : nops_for_insn_or_target (0, history
, ip
));
7218 unsigned long old_frag_offset
;
7221 old_frag
= frag_now
;
7222 old_frag_offset
= frag_now_fix ();
7224 for (i
= 0; i
< nops
; i
++)
7225 add_fixed_insn (NOP_INSN
);
7226 insert_into_history (0, nops
, NOP_INSN
);
7230 listing_prev_line ();
7231 /* We may be at the start of a variant frag. In case we
7232 are, make sure there is enough space for the frag
7233 after the frags created by listing_prev_line. The
7234 argument to frag_grow here must be at least as large
7235 as the argument to all other calls to frag_grow in
7236 this file. We don't have to worry about being in the
7237 middle of a variant frag, because the variants insert
7238 all needed nop instructions themselves. */
7242 mips_move_text_labels ();
7244 #ifndef NO_ECOFF_DEBUGGING
7245 if (ECOFF_DEBUGGING
)
7246 ecoff_fix_loc (old_frag
, old_frag_offset
);
7250 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7254 /* Work out how many nops in prev_nop_frag are needed by IP,
7255 ignoring hazards generated by the first prev_nop_frag_since
7257 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7258 gas_assert (nops
<= prev_nop_frag_holds
);
7260 /* Enforce NOPS as a minimum. */
7261 if (nops
> prev_nop_frag_required
)
7262 prev_nop_frag_required
= nops
;
7264 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7266 /* Settle for the current number of nops. Update the history
7267 accordingly (for the benefit of any future .set reorder code). */
7268 prev_nop_frag
= NULL
;
7269 insert_into_history (prev_nop_frag_since
,
7270 prev_nop_frag_holds
, NOP_INSN
);
7274 /* Allow this instruction to replace one of the nops that was
7275 tentatively added to prev_nop_frag. */
7276 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7277 prev_nop_frag_holds
--;
7278 prev_nop_frag_since
++;
7282 method
= get_append_method (ip
, address_expr
, reloc_type
);
7283 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7285 dwarf2_emit_insn (0);
7286 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7287 so "move" the instruction address accordingly.
7289 Also, it doesn't seem appropriate for the assembler to reorder .loc
7290 entries. If this instruction is a branch that we are going to swap
7291 with the previous instruction, the two instructions should be
7292 treated as a unit, and the debug information for both instructions
7293 should refer to the start of the branch sequence. Using the
7294 current position is certainly wrong when swapping a 32-bit branch
7295 and a 16-bit delay slot, since the current position would then be
7296 in the middle of a branch. */
7297 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7299 relax32
= (mips_relax_branch
7300 /* Don't try branch relaxation within .set nomacro, or within
7301 .set noat if we use $at for PIC computations. If it turns
7302 out that the branch was out-of-range, we'll get an error. */
7303 && !mips_opts
.warn_about_macros
7304 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7305 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7306 as they have no complementing branches. */
7307 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7309 if (!HAVE_CODE_COMPRESSION
7312 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7313 && delayed_branch_p (ip
))
7315 relaxed_branch
= TRUE
;
7316 add_relaxed_insn (ip
, (relaxed_branch_length
7318 uncond_branch_p (ip
) ? -1
7319 : branch_likely_p (ip
) ? 1
7323 uncond_branch_p (ip
),
7324 branch_likely_p (ip
),
7325 pinfo
& INSN_WRITE_GPR_31
,
7327 address_expr
->X_add_symbol
,
7328 address_expr
->X_add_number
);
7329 *reloc_type
= BFD_RELOC_UNUSED
;
7331 else if (mips_opts
.micromips
7333 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7334 || *reloc_type
> BFD_RELOC_UNUSED
)
7335 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7336 /* Don't try branch relaxation when users specify
7337 16-bit/32-bit instructions. */
7338 && !forced_insn_length
)
7340 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7341 && *reloc_type
> BFD_RELOC_UNUSED
);
7342 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7343 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7344 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7345 int nods
= method
== APPEND_ADD_WITH_NOP
;
7346 int al
= pinfo
& INSN_WRITE_GPR_31
;
7347 int length32
= nods
? 8 : 4;
7349 gas_assert (address_expr
!= NULL
);
7350 gas_assert (!mips_relax
.sequence
);
7352 relaxed_branch
= TRUE
;
7354 method
= APPEND_ADD
;
7356 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7357 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7358 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7359 uncond
, compact
, al
, nods
,
7361 address_expr
->X_add_symbol
,
7362 address_expr
->X_add_number
);
7363 *reloc_type
= BFD_RELOC_UNUSED
;
7365 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7367 bfd_boolean require_unextended
;
7368 bfd_boolean require_extended
;
7372 if (forced_insn_length
!= 0)
7374 require_unextended
= forced_insn_length
== 2;
7375 require_extended
= forced_insn_length
== 4;
7379 require_unextended
= (mips_opts
.noautoextend
7380 && !mips_opcode_32bit_p (ip
->insn_mo
));
7381 require_extended
= 0;
7384 /* We need to set up a variant frag. */
7385 gas_assert (address_expr
!= NULL
);
7386 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7387 symbol created by `make_expr_symbol' may not get a necessary
7388 external relocation produced. */
7389 if (address_expr
->X_op
== O_symbol
)
7391 symbol
= address_expr
->X_add_symbol
;
7392 offset
= address_expr
->X_add_number
;
7396 symbol
= make_expr_symbol (address_expr
);
7399 add_relaxed_insn (ip
, 4, 0,
7401 (*reloc_type
- BFD_RELOC_UNUSED
,
7402 require_unextended
, require_extended
,
7403 delayed_branch_p (&history
[0]),
7404 history
[0].mips16_absolute_jump_p
),
7407 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7409 if (!delayed_branch_p (ip
))
7410 /* Make sure there is enough room to swap this instruction with
7411 a following jump instruction. */
7413 add_fixed_insn (ip
);
7417 if (mips_opts
.mips16
7418 && mips_opts
.noreorder
7419 && delayed_branch_p (&history
[0]))
7420 as_warn (_("extended instruction in delay slot"));
7422 if (mips_relax
.sequence
)
7424 /* If we've reached the end of this frag, turn it into a variant
7425 frag and record the information for the instructions we've
7427 if (frag_room () < 4)
7428 relax_close_frag ();
7429 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7432 if (mips_relax
.sequence
!= 2)
7434 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7435 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7436 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7437 mips_macro_warning
.insns
[0]++;
7439 if (mips_relax
.sequence
!= 1)
7441 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7442 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7443 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7444 mips_macro_warning
.insns
[1]++;
7447 if (mips_opts
.mips16
)
7450 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7452 add_fixed_insn (ip
);
7455 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7457 bfd_reloc_code_real_type final_type
[3];
7458 reloc_howto_type
*howto0
;
7459 reloc_howto_type
*howto
;
7462 /* Perform any necessary conversion to microMIPS relocations
7463 and find out how many relocations there actually are. */
7464 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7465 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7467 /* In a compound relocation, it is the final (outermost)
7468 operator that determines the relocated field. */
7469 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7474 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7475 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7476 bfd_get_reloc_size (howto
),
7478 howto0
&& howto0
->pc_relative
,
7481 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7482 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7483 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7485 /* These relocations can have an addend that won't fit in
7486 4 octets for 64bit assembly. */
7488 && ! howto
->partial_inplace
7489 && (reloc_type
[0] == BFD_RELOC_16
7490 || reloc_type
[0] == BFD_RELOC_32
7491 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7492 || reloc_type
[0] == BFD_RELOC_GPREL16
7493 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7494 || reloc_type
[0] == BFD_RELOC_GPREL32
7495 || reloc_type
[0] == BFD_RELOC_64
7496 || reloc_type
[0] == BFD_RELOC_CTOR
7497 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7498 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7499 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7500 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7501 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7502 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7503 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7504 || hi16_reloc_p (reloc_type
[0])
7505 || lo16_reloc_p (reloc_type
[0])))
7506 ip
->fixp
[0]->fx_no_overflow
= 1;
7508 /* These relocations can have an addend that won't fit in 2 octets. */
7509 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7510 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7511 ip
->fixp
[0]->fx_no_overflow
= 1;
7513 if (mips_relax
.sequence
)
7515 if (mips_relax
.first_fixup
== 0)
7516 mips_relax
.first_fixup
= ip
->fixp
[0];
7518 else if (reloc_needs_lo_p (*reloc_type
))
7520 struct mips_hi_fixup
*hi_fixup
;
7522 /* Reuse the last entry if it already has a matching %lo. */
7523 hi_fixup
= mips_hi_fixup_list
;
7525 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7527 hi_fixup
= XNEW (struct mips_hi_fixup
);
7528 hi_fixup
->next
= mips_hi_fixup_list
;
7529 mips_hi_fixup_list
= hi_fixup
;
7531 hi_fixup
->fixp
= ip
->fixp
[0];
7532 hi_fixup
->seg
= now_seg
;
7535 /* Add fixups for the second and third relocations, if given.
7536 Note that the ABI allows the second relocation to be
7537 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7538 moment we only use RSS_UNDEF, but we could add support
7539 for the others if it ever becomes necessary. */
7540 for (i
= 1; i
< 3; i
++)
7541 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7543 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7544 ip
->fixp
[0]->fx_size
, NULL
, 0,
7545 FALSE
, final_type
[i
]);
7547 /* Use fx_tcbit to mark compound relocs. */
7548 ip
->fixp
[0]->fx_tcbit
= 1;
7549 ip
->fixp
[i
]->fx_tcbit
= 1;
7553 /* Update the register mask information. */
7554 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7555 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7560 insert_into_history (0, 1, ip
);
7563 case APPEND_ADD_WITH_NOP
:
7565 struct mips_cl_insn
*nop
;
7567 insert_into_history (0, 1, ip
);
7568 nop
= get_delay_slot_nop (ip
);
7569 add_fixed_insn (nop
);
7570 insert_into_history (0, 1, nop
);
7571 if (mips_relax
.sequence
)
7572 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7576 case APPEND_ADD_COMPACT
:
7577 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7578 if (mips_opts
.mips16
)
7580 ip
->insn_opcode
|= 0x0080;
7581 find_altered_mips16_opcode (ip
);
7583 /* Convert microMIPS instructions. */
7584 else if (mips_opts
.micromips
)
7587 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7588 ip
->insn_opcode
|= 0x0020;
7590 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7591 ip
->insn_opcode
= 0x40e00000;
7592 /* beqz16->beqzc, bnez16->bnezc */
7593 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7595 unsigned long regno
;
7597 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7598 regno
&= MICROMIPSOP_MASK_MD
;
7599 regno
= micromips_to_32_reg_d_map
[regno
];
7600 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7601 | (regno
<< MICROMIPSOP_SH_RS
)
7602 | 0x40a00000) ^ 0x00400000;
7604 /* beqz->beqzc, bnez->bnezc */
7605 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7606 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7607 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7608 | 0x40a00000) ^ 0x00400000;
7609 /* beq $0->beqzc, bne $0->bnezc */
7610 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7611 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7612 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7613 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7614 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7615 | 0x40a00000) ^ 0x00400000;
7618 find_altered_micromips_opcode (ip
);
7623 insert_into_history (0, 1, ip
);
7628 struct mips_cl_insn delay
= history
[0];
7630 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7632 /* Add the delay slot instruction to the end of the
7633 current frag and shrink the fixed part of the
7634 original frag. If the branch occupies the tail of
7635 the latter, move it backwards to cover the gap. */
7636 delay
.frag
->fr_fix
-= branch_disp
;
7637 if (delay
.frag
== ip
->frag
)
7638 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7639 add_fixed_insn (&delay
);
7643 /* If this is not a relaxed branch and we are in the
7644 same frag, then just swap the instructions. */
7645 move_insn (ip
, delay
.frag
, delay
.where
);
7646 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7650 insert_into_history (0, 1, &delay
);
7655 /* If we have just completed an unconditional branch, clear the history. */
7656 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7657 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7661 mips_no_prev_insn ();
7663 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7664 history
[i
].cleared_p
= 1;
7667 /* We need to emit a label at the end of branch-likely macros. */
7668 if (emit_branch_likely_macro
)
7670 emit_branch_likely_macro
= FALSE
;
7671 micromips_add_label ();
7674 /* We just output an insn, so the next one doesn't have a label. */
7675 mips_clear_insn_labels ();
7678 /* Forget that there was any previous instruction or label.
7679 When BRANCH is true, the branch history is also flushed. */
7682 mips_no_prev_insn (void)
7684 prev_nop_frag
= NULL
;
7685 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7686 mips_clear_insn_labels ();
7689 /* This function must be called before we emit something other than
7690 instructions. It is like mips_no_prev_insn except that it inserts
7691 any NOPS that might be needed by previous instructions. */
7694 mips_emit_delays (void)
7696 if (! mips_opts
.noreorder
)
7698 int nops
= nops_for_insn (0, history
, NULL
);
7702 add_fixed_insn (NOP_INSN
);
7703 mips_move_text_labels ();
7706 mips_no_prev_insn ();
7709 /* Start a (possibly nested) noreorder block. */
7712 start_noreorder (void)
7714 if (mips_opts
.noreorder
== 0)
7719 /* None of the instructions before the .set noreorder can be moved. */
7720 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7721 history
[i
].fixed_p
= 1;
7723 /* Insert any nops that might be needed between the .set noreorder
7724 block and the previous instructions. We will later remove any
7725 nops that turn out not to be needed. */
7726 nops
= nops_for_insn (0, history
, NULL
);
7729 if (mips_optimize
!= 0)
7731 /* Record the frag which holds the nop instructions, so
7732 that we can remove them if we don't need them. */
7733 frag_grow (nops
* NOP_INSN_SIZE
);
7734 prev_nop_frag
= frag_now
;
7735 prev_nop_frag_holds
= nops
;
7736 prev_nop_frag_required
= 0;
7737 prev_nop_frag_since
= 0;
7740 for (; nops
> 0; --nops
)
7741 add_fixed_insn (NOP_INSN
);
7743 /* Move on to a new frag, so that it is safe to simply
7744 decrease the size of prev_nop_frag. */
7745 frag_wane (frag_now
);
7747 mips_move_text_labels ();
7749 mips_mark_labels ();
7750 mips_clear_insn_labels ();
7752 mips_opts
.noreorder
++;
7753 mips_any_noreorder
= 1;
7756 /* End a nested noreorder block. */
7759 end_noreorder (void)
7761 mips_opts
.noreorder
--;
7762 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7764 /* Commit to inserting prev_nop_frag_required nops and go back to
7765 handling nop insertion the .set reorder way. */
7766 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7768 insert_into_history (prev_nop_frag_since
,
7769 prev_nop_frag_required
, NOP_INSN
);
7770 prev_nop_frag
= NULL
;
7774 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7775 higher bits unset. */
7778 normalize_constant_expr (expressionS
*ex
)
7780 if (ex
->X_op
== O_constant
7781 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7782 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7786 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7787 all higher bits unset. */
7790 normalize_address_expr (expressionS
*ex
)
7792 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7793 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7794 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7795 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7799 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7800 Return true if the match was successful.
7802 OPCODE_EXTRA is a value that should be ORed into the opcode
7803 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7804 there are more alternatives after OPCODE and SOFT_MATCH is
7805 as for mips_arg_info. */
7808 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7809 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7810 bfd_boolean lax_match
, bfd_boolean complete_p
)
7813 struct mips_arg_info arg
;
7814 const struct mips_operand
*operand
;
7817 imm_expr
.X_op
= O_absent
;
7818 offset_expr
.X_op
= O_absent
;
7819 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7820 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7821 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7823 create_insn (insn
, opcode
);
7824 /* When no opcode suffix is specified, assume ".xyzw". */
7825 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7826 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7828 insn
->insn_opcode
|= opcode_extra
;
7829 memset (&arg
, 0, sizeof (arg
));
7833 arg
.last_regno
= ILLEGAL_REG
;
7834 arg
.dest_regno
= ILLEGAL_REG
;
7835 arg
.lax_match
= lax_match
;
7836 for (args
= opcode
->args
;; ++args
)
7838 if (arg
.token
->type
== OT_END
)
7840 /* Handle unary instructions in which only one operand is given.
7841 The source is then the same as the destination. */
7842 if (arg
.opnum
== 1 && *args
== ',')
7844 operand
= (mips_opts
.micromips
7845 ? decode_micromips_operand (args
+ 1)
7846 : decode_mips_operand (args
+ 1));
7847 if (operand
&& mips_optional_operand_p (operand
))
7855 /* Treat elided base registers as $0. */
7856 if (strcmp (args
, "(b)") == 0)
7864 /* The register suffix is optional. */
7869 /* Fail the match if there were too few operands. */
7873 /* Successful match. */
7876 clear_insn_error ();
7877 if (arg
.dest_regno
== arg
.last_regno
7878 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7882 (0, _("source and destination must be different"));
7883 else if (arg
.last_regno
== 31)
7885 (0, _("a destination register must be supplied"));
7887 else if (arg
.last_regno
== 31
7888 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7889 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7890 set_insn_error (0, _("the source register must not be $31"));
7891 check_completed_insn (&arg
);
7895 /* Fail the match if the line has too many operands. */
7899 /* Handle characters that need to match exactly. */
7900 if (*args
== '(' || *args
== ')' || *args
== ',')
7902 if (match_char (&arg
, *args
))
7909 if (arg
.token
->type
== OT_DOUBLE_CHAR
7910 && arg
.token
->u
.ch
== *args
)
7918 /* Handle special macro operands. Work out the properties of
7927 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7931 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7940 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7944 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7948 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7954 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7956 imm_expr
.X_op
= O_constant
;
7958 normalize_constant_expr (&imm_expr
);
7962 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7964 /* Assume that the offset has been elided and that what
7965 we saw was a base register. The match will fail later
7966 if that assumption turns out to be wrong. */
7967 offset_expr
.X_op
= O_constant
;
7968 offset_expr
.X_add_number
= 0;
7972 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7974 normalize_address_expr (&offset_expr
);
7979 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7985 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7991 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7997 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8003 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8007 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8011 gas_assert (mips_opts
.micromips
);
8017 if (!forced_insn_length
)
8018 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8020 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8022 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8028 operand
= (mips_opts
.micromips
8029 ? decode_micromips_operand (args
)
8030 : decode_mips_operand (args
));
8034 /* Skip prefixes. */
8035 if (*args
== '+' || *args
== 'm' || *args
== '-')
8038 if (mips_optional_operand_p (operand
)
8040 && (arg
.token
[0].type
!= OT_REG
8041 || arg
.token
[1].type
== OT_END
))
8043 /* Assume that the register has been elided and is the
8044 same as the first operand. */
8049 if (!match_operand (&arg
, operand
))
8054 /* Like match_insn, but for MIPS16. */
8057 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8058 struct mips_operand_token
*tokens
)
8061 const struct mips_operand
*operand
;
8062 const struct mips_operand
*ext_operand
;
8063 int required_insn_length
;
8064 struct mips_arg_info arg
;
8067 if (forced_insn_length
)
8068 required_insn_length
= forced_insn_length
;
8069 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8070 required_insn_length
= 2;
8072 required_insn_length
= 0;
8074 create_insn (insn
, opcode
);
8075 imm_expr
.X_op
= O_absent
;
8076 offset_expr
.X_op
= O_absent
;
8077 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8078 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8079 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8082 memset (&arg
, 0, sizeof (arg
));
8086 arg
.last_regno
= ILLEGAL_REG
;
8087 arg
.dest_regno
= ILLEGAL_REG
;
8089 for (args
= opcode
->args
;; ++args
)
8093 if (arg
.token
->type
== OT_END
)
8097 /* Handle unary instructions in which only one operand is given.
8098 The source is then the same as the destination. */
8099 if (arg
.opnum
== 1 && *args
== ',')
8101 operand
= decode_mips16_operand (args
[1], FALSE
);
8102 if (operand
&& mips_optional_operand_p (operand
))
8110 /* Fail the match if there were too few operands. */
8114 /* Successful match. Stuff the immediate value in now, if
8116 clear_insn_error ();
8117 if (opcode
->pinfo
== INSN_MACRO
)
8119 gas_assert (relax_char
== 0 || relax_char
== 'p');
8120 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8123 && offset_expr
.X_op
== O_constant
8124 && calculate_reloc (*offset_reloc
,
8125 offset_expr
.X_add_number
,
8128 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8129 required_insn_length
, &insn
->insn_opcode
);
8130 offset_expr
.X_op
= O_absent
;
8131 *offset_reloc
= BFD_RELOC_UNUSED
;
8133 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8135 if (required_insn_length
== 2)
8136 set_insn_error (0, _("invalid unextended operand value"));
8137 forced_insn_length
= 4;
8138 insn
->insn_opcode
|= MIPS16_EXTEND
;
8140 else if (relax_char
)
8141 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8143 check_completed_insn (&arg
);
8147 /* Fail the match if the line has too many operands. */
8151 /* Handle characters that need to match exactly. */
8152 if (*args
== '(' || *args
== ')' || *args
== ',')
8154 if (match_char (&arg
, *args
))
8172 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8174 imm_expr
.X_op
= O_constant
;
8176 normalize_constant_expr (&imm_expr
);
8181 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8185 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8189 /* '6' is a special case. It is used for BREAK and SDBBP,
8190 whose operands are only meaningful to the software that decodes
8191 them. This means that there is no architectural reason why
8192 they cannot be prefixed by EXTEND, but in practice,
8193 exception handlers will only look at the instruction
8194 itself. We therefore allow '6' to be extended when
8195 disassembling but not when assembling. */
8196 if (operand
->type
!= OP_PCREL
&& c
!= '6')
8198 ext_operand
= decode_mips16_operand (c
, TRUE
);
8199 if (operand
!= ext_operand
)
8201 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8203 offset_expr
.X_op
= O_constant
;
8204 offset_expr
.X_add_number
= 0;
8209 /* We need the OT_INTEGER check because some MIPS16
8210 immediate variants are listed before the register ones. */
8211 if (arg
.token
->type
!= OT_INTEGER
8212 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8215 /* '8' is used for SLTI(U) and has traditionally not
8216 been allowed to take relocation operators. */
8217 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8218 && (ext_operand
->size
!= 16 || c
== '8'))
8226 if (mips_optional_operand_p (operand
)
8228 && (arg
.token
[0].type
!= OT_REG
8229 || arg
.token
[1].type
== OT_END
))
8231 /* Assume that the register has been elided and is the
8232 same as the first operand. */
8237 if (!match_operand (&arg
, operand
))
8242 /* Record that the current instruction is invalid for the current ISA. */
8245 match_invalid_for_isa (void)
8248 (0, _("opcode not supported on this processor: %s (%s)"),
8249 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8250 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8253 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8254 Return true if a definite match or failure was found, storing any match
8255 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8256 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8257 tried and failed to match under normal conditions and now want to try a
8258 more relaxed match. */
8261 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8262 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8263 int opcode_extra
, bfd_boolean lax_match
)
8265 const struct mips_opcode
*opcode
;
8266 const struct mips_opcode
*invalid_delay_slot
;
8267 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8269 /* Search for a match, ignoring alternatives that don't satisfy the
8270 current ISA or forced_length. */
8271 invalid_delay_slot
= 0;
8272 seen_valid_for_isa
= FALSE
;
8273 seen_valid_for_size
= FALSE
;
8277 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8278 if (is_opcode_valid (opcode
))
8280 seen_valid_for_isa
= TRUE
;
8281 if (is_size_valid (opcode
))
8283 bfd_boolean delay_slot_ok
;
8285 seen_valid_for_size
= TRUE
;
8286 delay_slot_ok
= is_delay_slot_valid (opcode
);
8287 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8288 lax_match
, delay_slot_ok
))
8292 if (!invalid_delay_slot
)
8293 invalid_delay_slot
= opcode
;
8302 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8304 /* If the only matches we found had the wrong length for the delay slot,
8305 pick the first such match. We'll issue an appropriate warning later. */
8306 if (invalid_delay_slot
)
8308 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8314 /* Handle the case where we didn't try to match an instruction because
8315 all the alternatives were incompatible with the current ISA. */
8316 if (!seen_valid_for_isa
)
8318 match_invalid_for_isa ();
8322 /* Handle the case where we didn't try to match an instruction because
8323 all the alternatives were of the wrong size. */
8324 if (!seen_valid_for_size
)
8326 if (mips_opts
.insn32
)
8327 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8330 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8331 8 * forced_insn_length
);
8338 /* Like match_insns, but for MIPS16. */
8341 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8342 struct mips_operand_token
*tokens
)
8344 const struct mips_opcode
*opcode
;
8345 bfd_boolean seen_valid_for_isa
;
8346 bfd_boolean seen_valid_for_size
;
8348 /* Search for a match, ignoring alternatives that don't satisfy the
8349 current ISA. There are no separate entries for extended forms so
8350 we deal with forced_length later. */
8351 seen_valid_for_isa
= FALSE
;
8352 seen_valid_for_size
= FALSE
;
8356 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8357 if (is_opcode_valid_16 (opcode
))
8359 seen_valid_for_isa
= TRUE
;
8360 if (is_size_valid_16 (opcode
))
8362 seen_valid_for_size
= TRUE
;
8363 if (match_mips16_insn (insn
, opcode
, tokens
))
8369 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8370 && strcmp (opcode
->name
, first
->name
) == 0);
8372 /* Handle the case where we didn't try to match an instruction because
8373 all the alternatives were incompatible with the current ISA. */
8374 if (!seen_valid_for_isa
)
8376 match_invalid_for_isa ();
8380 /* Handle the case where we didn't try to match an instruction because
8381 all the alternatives were of the wrong size. */
8382 if (!seen_valid_for_size
)
8384 if (forced_insn_length
== 2)
8386 (0, _("unrecognized unextended version of MIPS16 opcode"));
8389 (0, _("unrecognized extended version of MIPS16 opcode"));
8396 /* Set up global variables for the start of a new macro. */
8401 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8402 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8403 sizeof (mips_macro_warning
.first_insn_sizes
));
8404 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8405 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8406 && delayed_branch_p (&history
[0]));
8408 && history
[0].frag
->fr_type
== rs_machine_dependent
8409 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8410 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8411 mips_macro_warning
.delay_slot_length
= 0;
8413 switch (history
[0].insn_mo
->pinfo2
8414 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8416 case INSN2_BRANCH_DELAY_32BIT
:
8417 mips_macro_warning
.delay_slot_length
= 4;
8419 case INSN2_BRANCH_DELAY_16BIT
:
8420 mips_macro_warning
.delay_slot_length
= 2;
8423 mips_macro_warning
.delay_slot_length
= 0;
8426 mips_macro_warning
.first_frag
= NULL
;
8429 /* Given that a macro is longer than one instruction or of the wrong size,
8430 return the appropriate warning for it. Return null if no warning is
8431 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8432 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8433 and RELAX_NOMACRO. */
8436 macro_warning (relax_substateT subtype
)
8438 if (subtype
& RELAX_DELAY_SLOT
)
8439 return _("macro instruction expanded into multiple instructions"
8440 " in a branch delay slot");
8441 else if (subtype
& RELAX_NOMACRO
)
8442 return _("macro instruction expanded into multiple instructions");
8443 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8444 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8445 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8446 ? _("macro instruction expanded into a wrong size instruction"
8447 " in a 16-bit branch delay slot")
8448 : _("macro instruction expanded into a wrong size instruction"
8449 " in a 32-bit branch delay slot"));
8454 /* Finish up a macro. Emit warnings as appropriate. */
8459 /* Relaxation warning flags. */
8460 relax_substateT subtype
= 0;
8462 /* Check delay slot size requirements. */
8463 if (mips_macro_warning
.delay_slot_length
== 2)
8464 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8465 if (mips_macro_warning
.delay_slot_length
!= 0)
8467 if (mips_macro_warning
.delay_slot_length
8468 != mips_macro_warning
.first_insn_sizes
[0])
8469 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8470 if (mips_macro_warning
.delay_slot_length
8471 != mips_macro_warning
.first_insn_sizes
[1])
8472 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8475 /* Check instruction count requirements. */
8476 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8478 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8479 subtype
|= RELAX_SECOND_LONGER
;
8480 if (mips_opts
.warn_about_macros
)
8481 subtype
|= RELAX_NOMACRO
;
8482 if (mips_macro_warning
.delay_slot_p
)
8483 subtype
|= RELAX_DELAY_SLOT
;
8486 /* If both alternatives fail to fill a delay slot correctly,
8487 emit the warning now. */
8488 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8489 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8494 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8495 | RELAX_DELAY_SLOT_SIZE_FIRST
8496 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8497 msg
= macro_warning (s
);
8499 as_warn ("%s", msg
);
8503 /* If both implementations are longer than 1 instruction, then emit the
8505 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8510 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8511 msg
= macro_warning (s
);
8513 as_warn ("%s", msg
);
8517 /* If any flags still set, then one implementation might need a warning
8518 and the other either will need one of a different kind or none at all.
8519 Pass any remaining flags over to relaxation. */
8520 if (mips_macro_warning
.first_frag
!= NULL
)
8521 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8524 /* Instruction operand formats used in macros that vary between
8525 standard MIPS and microMIPS code. */
8527 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8528 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8529 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8530 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8531 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8532 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8533 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8534 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8536 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8537 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8538 : cop12_fmt[mips_opts.micromips])
8539 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8540 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8541 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8542 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8543 : mem12_fmt[mips_opts.micromips])
8544 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8545 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8546 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8548 /* Read a macro's relocation codes from *ARGS and store them in *R.
8549 The first argument in *ARGS will be either the code for a single
8550 relocation or -1 followed by the three codes that make up a
8551 composite relocation. */
8554 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8558 next
= va_arg (*args
, int);
8560 r
[0] = (bfd_reloc_code_real_type
) next
;
8563 for (i
= 0; i
< 3; i
++)
8564 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8565 /* This function is only used for 16-bit relocation fields.
8566 To make the macro code simpler, treat an unrelocated value
8567 in the same way as BFD_RELOC_LO16. */
8568 if (r
[0] == BFD_RELOC_UNUSED
)
8569 r
[0] = BFD_RELOC_LO16
;
8573 /* Build an instruction created by a macro expansion. This is passed
8574 a pointer to the count of instructions created so far, an
8575 expression, the name of the instruction to build, an operand format
8576 string, and corresponding arguments. */
8579 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8581 const struct mips_opcode
*mo
= NULL
;
8582 bfd_reloc_code_real_type r
[3];
8583 const struct mips_opcode
*amo
;
8584 const struct mips_operand
*operand
;
8585 struct hash_control
*hash
;
8586 struct mips_cl_insn insn
;
8590 va_start (args
, fmt
);
8592 if (mips_opts
.mips16
)
8594 mips16_macro_build (ep
, name
, fmt
, &args
);
8599 r
[0] = BFD_RELOC_UNUSED
;
8600 r
[1] = BFD_RELOC_UNUSED
;
8601 r
[2] = BFD_RELOC_UNUSED
;
8602 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8603 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8605 gas_assert (strcmp (name
, amo
->name
) == 0);
8609 /* Search until we get a match for NAME. It is assumed here that
8610 macros will never generate MDMX, MIPS-3D, or MT instructions.
8611 We try to match an instruction that fulfils the branch delay
8612 slot instruction length requirement (if any) of the previous
8613 instruction. While doing this we record the first instruction
8614 seen that matches all the other conditions and use it anyway
8615 if the requirement cannot be met; we will issue an appropriate
8616 warning later on. */
8617 if (strcmp (fmt
, amo
->args
) == 0
8618 && amo
->pinfo
!= INSN_MACRO
8619 && is_opcode_valid (amo
)
8620 && is_size_valid (amo
))
8622 if (is_delay_slot_valid (amo
))
8632 gas_assert (amo
->name
);
8634 while (strcmp (name
, amo
->name
) == 0);
8637 create_insn (&insn
, mo
);
8650 macro_read_relocs (&args
, r
);
8651 gas_assert (*r
== BFD_RELOC_GPREL16
8652 || *r
== BFD_RELOC_MIPS_HIGHER
8653 || *r
== BFD_RELOC_HI16_S
8654 || *r
== BFD_RELOC_LO16
8655 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8659 macro_read_relocs (&args
, r
);
8663 macro_read_relocs (&args
, r
);
8664 gas_assert (ep
!= NULL
8665 && (ep
->X_op
== O_constant
8666 || (ep
->X_op
== O_symbol
8667 && (*r
== BFD_RELOC_MIPS_HIGHEST
8668 || *r
== BFD_RELOC_HI16_S
8669 || *r
== BFD_RELOC_HI16
8670 || *r
== BFD_RELOC_GPREL16
8671 || *r
== BFD_RELOC_MIPS_GOT_HI16
8672 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8676 gas_assert (ep
!= NULL
);
8679 * This allows macro() to pass an immediate expression for
8680 * creating short branches without creating a symbol.
8682 * We don't allow branch relaxation for these branches, as
8683 * they should only appear in ".set nomacro" anyway.
8685 if (ep
->X_op
== O_constant
)
8687 /* For microMIPS we always use relocations for branches.
8688 So we should not resolve immediate values. */
8689 gas_assert (!mips_opts
.micromips
);
8691 if ((ep
->X_add_number
& 3) != 0)
8692 as_bad (_("branch to misaligned address (0x%lx)"),
8693 (unsigned long) ep
->X_add_number
);
8694 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8695 as_bad (_("branch address range overflow (0x%lx)"),
8696 (unsigned long) ep
->X_add_number
);
8697 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8701 *r
= BFD_RELOC_16_PCREL_S2
;
8705 gas_assert (ep
!= NULL
);
8706 *r
= BFD_RELOC_MIPS_JMP
;
8710 operand
= (mips_opts
.micromips
8711 ? decode_micromips_operand (fmt
)
8712 : decode_mips_operand (fmt
));
8716 uval
= va_arg (args
, int);
8717 if (operand
->type
== OP_CLO_CLZ_DEST
)
8718 uval
|= (uval
<< 5);
8719 insn_insert_operand (&insn
, operand
, uval
);
8721 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8727 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8729 append_insn (&insn
, ep
, r
, TRUE
);
8733 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8736 struct mips_opcode
*mo
;
8737 struct mips_cl_insn insn
;
8738 const struct mips_operand
*operand
;
8739 bfd_reloc_code_real_type r
[3]
8740 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8742 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8744 gas_assert (strcmp (name
, mo
->name
) == 0);
8746 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8749 gas_assert (mo
->name
);
8750 gas_assert (strcmp (name
, mo
->name
) == 0);
8753 create_insn (&insn
, mo
);
8790 gas_assert (ep
!= NULL
);
8792 if (ep
->X_op
!= O_constant
)
8793 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8794 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8796 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8798 *r
= BFD_RELOC_UNUSED
;
8804 operand
= decode_mips16_operand (c
, FALSE
);
8808 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8813 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8815 append_insn (&insn
, ep
, r
, TRUE
);
8819 * Generate a "jalr" instruction with a relocation hint to the called
8820 * function. This occurs in NewABI PIC code.
8823 macro_build_jalr (expressionS
*ep
, int cprestore
)
8825 static const bfd_reloc_code_real_type jalr_relocs
[2]
8826 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8827 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8831 if (MIPS_JALR_HINT_P (ep
))
8836 if (mips_opts
.micromips
)
8838 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8839 ? "jalr" : "jalrs");
8840 if (MIPS_JALR_HINT_P (ep
)
8842 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8843 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8845 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8848 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8849 if (MIPS_JALR_HINT_P (ep
))
8850 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8854 * Generate a "lui" instruction.
8857 macro_build_lui (expressionS
*ep
, int regnum
)
8859 gas_assert (! mips_opts
.mips16
);
8861 if (ep
->X_op
!= O_constant
)
8863 gas_assert (ep
->X_op
== O_symbol
);
8864 /* _gp_disp is a special case, used from s_cpload.
8865 __gnu_local_gp is used if mips_no_shared. */
8866 gas_assert (mips_pic
== NO_PIC
8868 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8869 || (! mips_in_shared
8870 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8871 "__gnu_local_gp") == 0));
8874 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8877 /* Generate a sequence of instructions to do a load or store from a constant
8878 offset off of a base register (breg) into/from a target register (treg),
8879 using AT if necessary. */
8881 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8882 int treg
, int breg
, int dbl
)
8884 gas_assert (ep
->X_op
== O_constant
);
8886 /* Sign-extending 32-bit constants makes their handling easier. */
8888 normalize_constant_expr (ep
);
8890 /* Right now, this routine can only handle signed 32-bit constants. */
8891 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8892 as_warn (_("operand overflow"));
8894 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8896 /* Signed 16-bit offset will fit in the op. Easy! */
8897 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8901 /* 32-bit offset, need multiple instructions and AT, like:
8902 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8903 addu $tempreg,$tempreg,$breg
8904 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8905 to handle the complete offset. */
8906 macro_build_lui (ep
, AT
);
8907 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8908 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8911 as_bad (_("macro used $at after \".set noat\""));
8916 * Generates code to set the $at register to true (one)
8917 * if reg is less than the immediate expression.
8920 set_at (int reg
, int unsignedp
)
8922 if (imm_expr
.X_add_number
>= -0x8000
8923 && imm_expr
.X_add_number
< 0x8000)
8924 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8925 AT
, reg
, BFD_RELOC_LO16
);
8928 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8929 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8933 /* Count the leading zeroes by performing a binary chop. This is a
8934 bulky bit of source, but performance is a LOT better for the
8935 majority of values than a simple loop to count the bits:
8936 for (lcnt = 0; (lcnt < 32); lcnt++)
8937 if ((v) & (1 << (31 - lcnt)))
8939 However it is not code size friendly, and the gain will drop a bit
8940 on certain cached systems.
8942 #define COUNT_TOP_ZEROES(v) \
8943 (((v) & ~0xffff) == 0 \
8944 ? ((v) & ~0xff) == 0 \
8945 ? ((v) & ~0xf) == 0 \
8946 ? ((v) & ~0x3) == 0 \
8947 ? ((v) & ~0x1) == 0 \
8952 : ((v) & ~0x7) == 0 \
8955 : ((v) & ~0x3f) == 0 \
8956 ? ((v) & ~0x1f) == 0 \
8959 : ((v) & ~0x7f) == 0 \
8962 : ((v) & ~0xfff) == 0 \
8963 ? ((v) & ~0x3ff) == 0 \
8964 ? ((v) & ~0x1ff) == 0 \
8967 : ((v) & ~0x7ff) == 0 \
8970 : ((v) & ~0x3fff) == 0 \
8971 ? ((v) & ~0x1fff) == 0 \
8974 : ((v) & ~0x7fff) == 0 \
8977 : ((v) & ~0xffffff) == 0 \
8978 ? ((v) & ~0xfffff) == 0 \
8979 ? ((v) & ~0x3ffff) == 0 \
8980 ? ((v) & ~0x1ffff) == 0 \
8983 : ((v) & ~0x7ffff) == 0 \
8986 : ((v) & ~0x3fffff) == 0 \
8987 ? ((v) & ~0x1fffff) == 0 \
8990 : ((v) & ~0x7fffff) == 0 \
8993 : ((v) & ~0xfffffff) == 0 \
8994 ? ((v) & ~0x3ffffff) == 0 \
8995 ? ((v) & ~0x1ffffff) == 0 \
8998 : ((v) & ~0x7ffffff) == 0 \
9001 : ((v) & ~0x3fffffff) == 0 \
9002 ? ((v) & ~0x1fffffff) == 0 \
9005 : ((v) & ~0x7fffffff) == 0 \
9010 * This routine generates the least number of instructions necessary to load
9011 * an absolute expression value into a register.
9014 load_register (int reg
, expressionS
*ep
, int dbl
)
9017 expressionS hi32
, lo32
;
9019 if (ep
->X_op
!= O_big
)
9021 gas_assert (ep
->X_op
== O_constant
);
9023 /* Sign-extending 32-bit constants makes their handling easier. */
9025 normalize_constant_expr (ep
);
9027 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9029 /* We can handle 16 bit signed values with an addiu to
9030 $zero. No need to ever use daddiu here, since $zero and
9031 the result are always correct in 32 bit mode. */
9032 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9035 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9037 /* We can handle 16 bit unsigned values with an ori to
9039 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9042 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9044 /* 32 bit values require an lui. */
9045 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9046 if ((ep
->X_add_number
& 0xffff) != 0)
9047 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9052 /* The value is larger than 32 bits. */
9054 if (!dbl
|| GPR_SIZE
== 32)
9058 sprintf_vma (value
, ep
->X_add_number
);
9059 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9060 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9064 if (ep
->X_op
!= O_big
)
9067 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9068 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9069 hi32
.X_add_number
&= 0xffffffff;
9071 lo32
.X_add_number
&= 0xffffffff;
9075 gas_assert (ep
->X_add_number
> 2);
9076 if (ep
->X_add_number
== 3)
9077 generic_bignum
[3] = 0;
9078 else if (ep
->X_add_number
> 4)
9079 as_bad (_("number larger than 64 bits"));
9080 lo32
.X_op
= O_constant
;
9081 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9082 hi32
.X_op
= O_constant
;
9083 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9086 if (hi32
.X_add_number
== 0)
9091 unsigned long hi
, lo
;
9093 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9095 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9097 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9100 if (lo32
.X_add_number
& 0x80000000)
9102 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9103 if (lo32
.X_add_number
& 0xffff)
9104 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9109 /* Check for 16bit shifted constant. We know that hi32 is
9110 non-zero, so start the mask on the first bit of the hi32
9115 unsigned long himask
, lomask
;
9119 himask
= 0xffff >> (32 - shift
);
9120 lomask
= (0xffff << shift
) & 0xffffffff;
9124 himask
= 0xffff << (shift
- 32);
9127 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9128 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9132 tmp
.X_op
= O_constant
;
9134 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9135 | (lo32
.X_add_number
>> shift
));
9137 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9138 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9139 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9140 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9145 while (shift
<= (64 - 16));
9147 /* Find the bit number of the lowest one bit, and store the
9148 shifted value in hi/lo. */
9149 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9150 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9154 while ((lo
& 1) == 0)
9159 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9165 while ((hi
& 1) == 0)
9174 /* Optimize if the shifted value is a (power of 2) - 1. */
9175 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9176 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9178 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9183 /* This instruction will set the register to be all
9185 tmp
.X_op
= O_constant
;
9186 tmp
.X_add_number
= (offsetT
) -1;
9187 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9191 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9192 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9194 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9195 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9200 /* Sign extend hi32 before calling load_register, because we can
9201 generally get better code when we load a sign extended value. */
9202 if ((hi32
.X_add_number
& 0x80000000) != 0)
9203 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9204 load_register (reg
, &hi32
, 0);
9207 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9211 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9219 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9221 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9222 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9228 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9232 mid16
.X_add_number
>>= 16;
9233 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9234 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9237 if ((lo32
.X_add_number
& 0xffff) != 0)
9238 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9242 load_delay_nop (void)
9244 if (!gpr_interlocks
)
9245 macro_build (NULL
, "nop", "");
9248 /* Load an address into a register. */
9251 load_address (int reg
, expressionS
*ep
, int *used_at
)
9253 if (ep
->X_op
!= O_constant
9254 && ep
->X_op
!= O_symbol
)
9256 as_bad (_("expression too complex"));
9257 ep
->X_op
= O_constant
;
9260 if (ep
->X_op
== O_constant
)
9262 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9266 if (mips_pic
== NO_PIC
)
9268 /* If this is a reference to a GP relative symbol, we want
9269 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9271 lui $reg,<sym> (BFD_RELOC_HI16_S)
9272 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9273 If we have an addend, we always use the latter form.
9275 With 64bit address space and a usable $at we want
9276 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9277 lui $at,<sym> (BFD_RELOC_HI16_S)
9278 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9279 daddiu $at,<sym> (BFD_RELOC_LO16)
9283 If $at is already in use, we use a path which is suboptimal
9284 on superscalar processors.
9285 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9286 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9288 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9290 daddiu $reg,<sym> (BFD_RELOC_LO16)
9292 For GP relative symbols in 64bit address space we can use
9293 the same sequence as in 32bit address space. */
9294 if (HAVE_64BIT_SYMBOLS
)
9296 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9297 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9299 relax_start (ep
->X_add_symbol
);
9300 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9301 mips_gp_register
, BFD_RELOC_GPREL16
);
9305 if (*used_at
== 0 && mips_opts
.at
)
9307 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9308 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9309 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9310 BFD_RELOC_MIPS_HIGHER
);
9311 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9312 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9313 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9318 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9319 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9320 BFD_RELOC_MIPS_HIGHER
);
9321 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9322 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9323 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9324 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9327 if (mips_relax
.sequence
)
9332 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9333 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9335 relax_start (ep
->X_add_symbol
);
9336 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9337 mips_gp_register
, BFD_RELOC_GPREL16
);
9340 macro_build_lui (ep
, reg
);
9341 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9342 reg
, reg
, BFD_RELOC_LO16
);
9343 if (mips_relax
.sequence
)
9347 else if (!mips_big_got
)
9351 /* If this is a reference to an external symbol, we want
9352 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9354 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9356 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9357 If there is a constant, it must be added in after.
9359 If we have NewABI, we want
9360 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9361 unless we're referencing a global symbol with a non-zero
9362 offset, in which case cst must be added separately. */
9365 if (ep
->X_add_number
)
9367 ex
.X_add_number
= ep
->X_add_number
;
9368 ep
->X_add_number
= 0;
9369 relax_start (ep
->X_add_symbol
);
9370 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9371 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9372 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9373 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9374 ex
.X_op
= O_constant
;
9375 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9376 reg
, reg
, BFD_RELOC_LO16
);
9377 ep
->X_add_number
= ex
.X_add_number
;
9380 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9381 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9382 if (mips_relax
.sequence
)
9387 ex
.X_add_number
= ep
->X_add_number
;
9388 ep
->X_add_number
= 0;
9389 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9390 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9392 relax_start (ep
->X_add_symbol
);
9394 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9398 if (ex
.X_add_number
!= 0)
9400 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9401 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9402 ex
.X_op
= O_constant
;
9403 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9404 reg
, reg
, BFD_RELOC_LO16
);
9408 else if (mips_big_got
)
9412 /* This is the large GOT case. If this is a reference to an
9413 external symbol, we want
9414 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9416 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9418 Otherwise, for a reference to a local symbol in old ABI, we want
9419 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9421 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9422 If there is a constant, it must be added in after.
9424 In the NewABI, for local symbols, with or without offsets, we want:
9425 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9426 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9430 ex
.X_add_number
= ep
->X_add_number
;
9431 ep
->X_add_number
= 0;
9432 relax_start (ep
->X_add_symbol
);
9433 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9435 reg
, reg
, mips_gp_register
);
9436 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9437 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9438 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9439 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9440 else if (ex
.X_add_number
)
9442 ex
.X_op
= O_constant
;
9443 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9447 ep
->X_add_number
= ex
.X_add_number
;
9449 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9450 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9451 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9452 BFD_RELOC_MIPS_GOT_OFST
);
9457 ex
.X_add_number
= ep
->X_add_number
;
9458 ep
->X_add_number
= 0;
9459 relax_start (ep
->X_add_symbol
);
9460 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9462 reg
, reg
, mips_gp_register
);
9463 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9464 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9466 if (reg_needs_delay (mips_gp_register
))
9468 /* We need a nop before loading from $gp. This special
9469 check is required because the lui which starts the main
9470 instruction stream does not refer to $gp, and so will not
9471 insert the nop which may be required. */
9472 macro_build (NULL
, "nop", "");
9474 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9475 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9477 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9481 if (ex
.X_add_number
!= 0)
9483 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9484 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9485 ex
.X_op
= O_constant
;
9486 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9494 if (!mips_opts
.at
&& *used_at
== 1)
9495 as_bad (_("macro used $at after \".set noat\""));
9498 /* Move the contents of register SOURCE into register DEST. */
9501 move_register (int dest
, int source
)
9503 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9504 instruction specifically requires a 32-bit one. */
9505 if (mips_opts
.micromips
9506 && !mips_opts
.insn32
9507 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9508 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9510 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9513 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9514 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9515 The two alternatives are:
9517 Global symbol Local sybmol
9518 ------------- ------------
9519 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9521 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9523 load_got_offset emits the first instruction and add_got_offset
9524 emits the second for a 16-bit offset or add_got_offset_hilo emits
9525 a sequence to add a 32-bit offset using a scratch register. */
9528 load_got_offset (int dest
, expressionS
*local
)
9533 global
.X_add_number
= 0;
9535 relax_start (local
->X_add_symbol
);
9536 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9537 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9539 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9540 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9545 add_got_offset (int dest
, expressionS
*local
)
9549 global
.X_op
= O_constant
;
9550 global
.X_op_symbol
= NULL
;
9551 global
.X_add_symbol
= NULL
;
9552 global
.X_add_number
= local
->X_add_number
;
9554 relax_start (local
->X_add_symbol
);
9555 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9556 dest
, dest
, BFD_RELOC_LO16
);
9558 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9563 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9566 int hold_mips_optimize
;
9568 global
.X_op
= O_constant
;
9569 global
.X_op_symbol
= NULL
;
9570 global
.X_add_symbol
= NULL
;
9571 global
.X_add_number
= local
->X_add_number
;
9573 relax_start (local
->X_add_symbol
);
9574 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9576 /* Set mips_optimize around the lui instruction to avoid
9577 inserting an unnecessary nop after the lw. */
9578 hold_mips_optimize
= mips_optimize
;
9580 macro_build_lui (&global
, tmp
);
9581 mips_optimize
= hold_mips_optimize
;
9582 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9585 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9588 /* Emit a sequence of instructions to emulate a branch likely operation.
9589 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9590 is its complementing branch with the original condition negated.
9591 CALL is set if the original branch specified the link operation.
9592 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9594 Code like this is produced in the noreorder mode:
9599 delay slot (executed only if branch taken)
9607 delay slot (executed only if branch taken)
9610 In the reorder mode the delay slot would be filled with a nop anyway,
9611 so code produced is simply:
9616 This function is used when producing code for the microMIPS ASE that
9617 does not implement branch likely instructions in hardware. */
9620 macro_build_branch_likely (const char *br
, const char *brneg
,
9621 int call
, expressionS
*ep
, const char *fmt
,
9622 unsigned int sreg
, unsigned int treg
)
9624 int noreorder
= mips_opts
.noreorder
;
9627 gas_assert (mips_opts
.micromips
);
9631 micromips_label_expr (&expr1
);
9632 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9633 macro_build (NULL
, "nop", "");
9634 macro_build (ep
, call
? "bal" : "b", "p");
9636 /* Set to true so that append_insn adds a label. */
9637 emit_branch_likely_macro
= TRUE
;
9641 macro_build (ep
, br
, fmt
, sreg
, treg
);
9642 macro_build (NULL
, "nop", "");
9647 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9648 the condition code tested. EP specifies the branch target. */
9651 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9678 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9681 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9682 the register tested. EP specifies the branch target. */
9685 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9687 const char *brneg
= NULL
;
9697 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9701 gas_assert (mips_opts
.micromips
);
9702 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9710 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9717 br
= mips_opts
.micromips
? "blez" : "blezl";
9724 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9728 gas_assert (mips_opts
.micromips
);
9729 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9736 if (mips_opts
.micromips
&& brneg
)
9737 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9739 macro_build (ep
, br
, "s,p", sreg
);
9742 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9743 TREG as the registers tested. EP specifies the branch target. */
9746 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9747 unsigned int sreg
, unsigned int treg
)
9749 const char *brneg
= NULL
;
9761 br
= mips_opts
.micromips
? "beq" : "beql";
9770 br
= mips_opts
.micromips
? "bne" : "bnel";
9776 if (mips_opts
.micromips
&& brneg
)
9777 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9779 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9782 /* Return the high part that should be loaded in order to make the low
9783 part of VALUE accessible using an offset of OFFBITS bits. */
9786 offset_high_part (offsetT value
, unsigned int offbits
)
9793 bias
= 1 << (offbits
- 1);
9794 low_mask
= bias
* 2 - 1;
9795 return (value
+ bias
) & ~low_mask
;
9798 /* Return true if the value stored in offset_expr and offset_reloc
9799 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9800 amount that the caller wants to add without inducing overflow
9801 and ALIGN is the known alignment of the value in bytes. */
9804 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9808 /* Accept any relocation operator if overflow isn't a concern. */
9809 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9812 /* These relocations are guaranteed not to overflow in correct links. */
9813 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9814 || gprel16_reloc_p (*offset_reloc
))
9817 if (offset_expr
.X_op
== O_constant
9818 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9819 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9826 * This routine implements the seemingly endless macro or synthesized
9827 * instructions and addressing modes in the mips assembly language. Many
9828 * of these macros are simple and are similar to each other. These could
9829 * probably be handled by some kind of table or grammar approach instead of
9830 * this verbose method. Others are not simple macros but are more like
9831 * optimizing code generation.
9832 * One interesting optimization is when several store macros appear
9833 * consecutively that would load AT with the upper half of the same address.
9834 * The ensuing load upper instructions are omitted. This implies some kind
9835 * of global optimization. We currently only optimize within a single macro.
9836 * For many of the load and store macros if the address is specified as a
9837 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9838 * first load register 'at' with zero and use it as the base register. The
9839 * mips assembler simply uses register $zero. Just one tiny optimization
9843 macro (struct mips_cl_insn
*ip
, char *str
)
9845 const struct mips_operand_array
*operands
;
9846 unsigned int breg
, i
;
9847 unsigned int tempreg
;
9850 expressionS label_expr
;
9865 bfd_boolean large_offset
;
9867 int hold_mips_optimize
;
9869 unsigned int op
[MAX_OPERANDS
];
9871 gas_assert (! mips_opts
.mips16
);
9873 operands
= insn_operands (ip
);
9874 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9875 if (operands
->operand
[i
])
9876 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9880 mask
= ip
->insn_mo
->mask
;
9882 label_expr
.X_op
= O_constant
;
9883 label_expr
.X_op_symbol
= NULL
;
9884 label_expr
.X_add_symbol
= NULL
;
9885 label_expr
.X_add_number
= 0;
9887 expr1
.X_op
= O_constant
;
9888 expr1
.X_op_symbol
= NULL
;
9889 expr1
.X_add_symbol
= NULL
;
9890 expr1
.X_add_number
= 1;
9907 if (mips_opts
.micromips
)
9908 micromips_label_expr (&label_expr
);
9910 label_expr
.X_add_number
= 8;
9911 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9913 macro_build (NULL
, "nop", "");
9915 move_register (op
[0], op
[1]);
9916 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9917 if (mips_opts
.micromips
)
9918 micromips_add_label ();
9935 if (!mips_opts
.micromips
)
9937 if (imm_expr
.X_add_number
>= -0x200
9938 && imm_expr
.X_add_number
< 0x200)
9940 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9941 (int) imm_expr
.X_add_number
);
9950 if (imm_expr
.X_add_number
>= -0x8000
9951 && imm_expr
.X_add_number
< 0x8000)
9953 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9958 load_register (AT
, &imm_expr
, dbl
);
9959 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9978 if (imm_expr
.X_add_number
>= 0
9979 && imm_expr
.X_add_number
< 0x10000)
9981 if (mask
!= M_NOR_I
)
9982 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9985 macro_build (&imm_expr
, "ori", "t,r,i",
9986 op
[0], op
[1], BFD_RELOC_LO16
);
9987 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9993 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9994 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9998 switch (imm_expr
.X_add_number
)
10001 macro_build (NULL
, "nop", "");
10004 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10008 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10009 (int) imm_expr
.X_add_number
);
10012 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10013 (unsigned long) imm_expr
.X_add_number
);
10022 gas_assert (mips_opts
.micromips
);
10023 macro_build_branch_ccl (mask
, &offset_expr
,
10024 EXTRACT_OPERAND (1, BCC
, *ip
));
10031 if (imm_expr
.X_add_number
== 0)
10037 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10039 /* Fall through. */
10042 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10047 /* Fall through. */
10050 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10051 else if (op
[0] == 0)
10052 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10056 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10057 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10058 &offset_expr
, AT
, ZERO
);
10068 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10073 /* Fall through. */
10075 /* Check for > max integer. */
10076 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10079 /* Result is always false. */
10081 macro_build (NULL
, "nop", "");
10083 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10086 ++imm_expr
.X_add_number
;
10090 if (mask
== M_BGEL_I
)
10092 if (imm_expr
.X_add_number
== 0)
10094 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10095 &offset_expr
, op
[0]);
10098 if (imm_expr
.X_add_number
== 1)
10100 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10101 &offset_expr
, op
[0]);
10104 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10107 /* result is always true */
10108 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10109 macro_build (&offset_expr
, "b", "p");
10114 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10115 &offset_expr
, AT
, ZERO
);
10120 /* Fall through. */
10124 else if (op
[0] == 0)
10125 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10126 &offset_expr
, ZERO
, op
[1]);
10130 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10131 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10132 &offset_expr
, AT
, ZERO
);
10138 /* Fall through. */
10142 && imm_expr
.X_add_number
== -1))
10144 ++imm_expr
.X_add_number
;
10148 if (mask
== M_BGEUL_I
)
10150 if (imm_expr
.X_add_number
== 0)
10152 else if (imm_expr
.X_add_number
== 1)
10153 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10154 &offset_expr
, op
[0], ZERO
);
10159 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10160 &offset_expr
, AT
, ZERO
);
10166 /* Fall through. */
10169 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10170 else if (op
[0] == 0)
10171 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10175 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10176 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10177 &offset_expr
, AT
, ZERO
);
10183 /* Fall through. */
10186 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10187 &offset_expr
, op
[0], ZERO
);
10188 else if (op
[0] == 0)
10193 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10194 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10195 &offset_expr
, AT
, ZERO
);
10201 /* Fall through. */
10204 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10205 else if (op
[0] == 0)
10206 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10210 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10211 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10212 &offset_expr
, AT
, ZERO
);
10218 /* Fall through. */
10220 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10222 ++imm_expr
.X_add_number
;
10226 if (mask
== M_BLTL_I
)
10228 if (imm_expr
.X_add_number
== 0)
10229 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10230 else if (imm_expr
.X_add_number
== 1)
10231 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10236 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10237 &offset_expr
, AT
, ZERO
);
10243 /* Fall through. */
10246 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10247 &offset_expr
, op
[0], ZERO
);
10248 else if (op
[0] == 0)
10253 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10254 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10255 &offset_expr
, AT
, ZERO
);
10261 /* Fall through. */
10265 && imm_expr
.X_add_number
== -1))
10267 ++imm_expr
.X_add_number
;
10271 if (mask
== M_BLTUL_I
)
10273 if (imm_expr
.X_add_number
== 0)
10275 else if (imm_expr
.X_add_number
== 1)
10276 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10277 &offset_expr
, op
[0], ZERO
);
10282 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10283 &offset_expr
, AT
, ZERO
);
10289 /* Fall through. */
10292 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10293 else if (op
[0] == 0)
10294 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10298 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10299 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10300 &offset_expr
, AT
, ZERO
);
10306 /* Fall through. */
10310 else if (op
[0] == 0)
10311 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10312 &offset_expr
, ZERO
, op
[1]);
10316 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10317 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10318 &offset_expr
, AT
, ZERO
);
10324 /* Fall through. */
10330 /* Fall through. */
10336 as_warn (_("divide by zero"));
10338 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10340 macro_build (NULL
, "break", BRK_FMT
, 7);
10344 start_noreorder ();
10347 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10348 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10352 if (mips_opts
.micromips
)
10353 micromips_label_expr (&label_expr
);
10355 label_expr
.X_add_number
= 8;
10356 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10357 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10358 macro_build (NULL
, "break", BRK_FMT
, 7);
10359 if (mips_opts
.micromips
)
10360 micromips_add_label ();
10362 expr1
.X_add_number
= -1;
10364 load_register (AT
, &expr1
, dbl
);
10365 if (mips_opts
.micromips
)
10366 micromips_label_expr (&label_expr
);
10368 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10369 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10372 expr1
.X_add_number
= 1;
10373 load_register (AT
, &expr1
, dbl
);
10374 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10378 expr1
.X_add_number
= 0x80000000;
10379 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10383 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10384 /* We want to close the noreorder block as soon as possible, so
10385 that later insns are available for delay slot filling. */
10390 if (mips_opts
.micromips
)
10391 micromips_label_expr (&label_expr
);
10393 label_expr
.X_add_number
= 8;
10394 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10395 macro_build (NULL
, "nop", "");
10397 /* We want to close the noreorder block as soon as possible, so
10398 that later insns are available for delay slot filling. */
10401 macro_build (NULL
, "break", BRK_FMT
, 6);
10403 if (mips_opts
.micromips
)
10404 micromips_add_label ();
10405 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10444 if (imm_expr
.X_add_number
== 0)
10446 as_warn (_("divide by zero"));
10448 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10450 macro_build (NULL
, "break", BRK_FMT
, 7);
10453 if (imm_expr
.X_add_number
== 1)
10455 if (strcmp (s2
, "mflo") == 0)
10456 move_register (op
[0], op
[1]);
10458 move_register (op
[0], ZERO
);
10461 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10463 if (strcmp (s2
, "mflo") == 0)
10464 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10466 move_register (op
[0], ZERO
);
10471 load_register (AT
, &imm_expr
, dbl
);
10472 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10473 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10492 start_noreorder ();
10495 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10496 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10497 /* We want to close the noreorder block as soon as possible, so
10498 that later insns are available for delay slot filling. */
10503 if (mips_opts
.micromips
)
10504 micromips_label_expr (&label_expr
);
10506 label_expr
.X_add_number
= 8;
10507 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10508 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10510 /* We want to close the noreorder block as soon as possible, so
10511 that later insns are available for delay slot filling. */
10513 macro_build (NULL
, "break", BRK_FMT
, 7);
10514 if (mips_opts
.micromips
)
10515 micromips_add_label ();
10517 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10522 /* Fall through. */
10528 /* Fall through. */
10531 /* Load the address of a symbol into a register. If breg is not
10532 zero, we then add a base register to it. */
10535 if (dbl
&& GPR_SIZE
== 32)
10536 as_warn (_("dla used to load 32-bit register; recommend using la "
10539 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10540 as_warn (_("la used to load 64-bit address; recommend using dla "
10543 if (small_offset_p (0, align
, 16))
10545 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10546 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10550 if (mips_opts
.at
&& (op
[0] == breg
))
10558 if (offset_expr
.X_op
!= O_symbol
10559 && offset_expr
.X_op
!= O_constant
)
10561 as_bad (_("expression too complex"));
10562 offset_expr
.X_op
= O_constant
;
10565 if (offset_expr
.X_op
== O_constant
)
10566 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10567 else if (mips_pic
== NO_PIC
)
10569 /* If this is a reference to a GP relative symbol, we want
10570 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10572 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10573 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10574 If we have a constant, we need two instructions anyhow,
10575 so we may as well always use the latter form.
10577 With 64bit address space and a usable $at we want
10578 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10579 lui $at,<sym> (BFD_RELOC_HI16_S)
10580 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10581 daddiu $at,<sym> (BFD_RELOC_LO16)
10583 daddu $tempreg,$tempreg,$at
10585 If $at is already in use, we use a path which is suboptimal
10586 on superscalar processors.
10587 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10588 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10590 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10592 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10594 For GP relative symbols in 64bit address space we can use
10595 the same sequence as in 32bit address space. */
10596 if (HAVE_64BIT_SYMBOLS
)
10598 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10599 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10601 relax_start (offset_expr
.X_add_symbol
);
10602 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10603 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10607 if (used_at
== 0 && mips_opts
.at
)
10609 macro_build (&offset_expr
, "lui", LUI_FMT
,
10610 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10611 macro_build (&offset_expr
, "lui", LUI_FMT
,
10612 AT
, BFD_RELOC_HI16_S
);
10613 macro_build (&offset_expr
, "daddiu", "t,r,j",
10614 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10615 macro_build (&offset_expr
, "daddiu", "t,r,j",
10616 AT
, AT
, BFD_RELOC_LO16
);
10617 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10618 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10623 macro_build (&offset_expr
, "lui", LUI_FMT
,
10624 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10625 macro_build (&offset_expr
, "daddiu", "t,r,j",
10626 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10627 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10628 macro_build (&offset_expr
, "daddiu", "t,r,j",
10629 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10630 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10631 macro_build (&offset_expr
, "daddiu", "t,r,j",
10632 tempreg
, tempreg
, BFD_RELOC_LO16
);
10635 if (mips_relax
.sequence
)
10640 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10641 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10643 relax_start (offset_expr
.X_add_symbol
);
10644 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10645 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10648 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10649 as_bad (_("offset too large"));
10650 macro_build_lui (&offset_expr
, tempreg
);
10651 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10652 tempreg
, tempreg
, BFD_RELOC_LO16
);
10653 if (mips_relax
.sequence
)
10657 else if (!mips_big_got
&& !HAVE_NEWABI
)
10659 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10661 /* If this is a reference to an external symbol, and there
10662 is no constant, we want
10663 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10664 or for lca or if tempreg is PIC_CALL_REG
10665 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10666 For a local symbol, we want
10667 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10669 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10671 If we have a small constant, and this is a reference to
10672 an external symbol, we want
10673 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10675 addiu $tempreg,$tempreg,<constant>
10676 For a local symbol, we want the same instruction
10677 sequence, but we output a BFD_RELOC_LO16 reloc on the
10680 If we have a large constant, and this is a reference to
10681 an external symbol, we want
10682 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10683 lui $at,<hiconstant>
10684 addiu $at,$at,<loconstant>
10685 addu $tempreg,$tempreg,$at
10686 For a local symbol, we want the same instruction
10687 sequence, but we output a BFD_RELOC_LO16 reloc on the
10691 if (offset_expr
.X_add_number
== 0)
10693 if (mips_pic
== SVR4_PIC
10695 && (call
|| tempreg
== PIC_CALL_REG
))
10696 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10698 relax_start (offset_expr
.X_add_symbol
);
10699 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10700 lw_reloc_type
, mips_gp_register
);
10703 /* We're going to put in an addu instruction using
10704 tempreg, so we may as well insert the nop right
10709 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10710 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10712 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10713 tempreg
, tempreg
, BFD_RELOC_LO16
);
10715 /* FIXME: If breg == 0, and the next instruction uses
10716 $tempreg, then if this variant case is used an extra
10717 nop will be generated. */
10719 else if (offset_expr
.X_add_number
>= -0x8000
10720 && offset_expr
.X_add_number
< 0x8000)
10722 load_got_offset (tempreg
, &offset_expr
);
10724 add_got_offset (tempreg
, &offset_expr
);
10728 expr1
.X_add_number
= offset_expr
.X_add_number
;
10729 offset_expr
.X_add_number
=
10730 SEXT_16BIT (offset_expr
.X_add_number
);
10731 load_got_offset (tempreg
, &offset_expr
);
10732 offset_expr
.X_add_number
= expr1
.X_add_number
;
10733 /* If we are going to add in a base register, and the
10734 target register and the base register are the same,
10735 then we are using AT as a temporary register. Since
10736 we want to load the constant into AT, we add our
10737 current AT (from the global offset table) and the
10738 register into the register now, and pretend we were
10739 not using a base register. */
10743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10748 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10752 else if (!mips_big_got
&& HAVE_NEWABI
)
10754 int add_breg_early
= 0;
10756 /* If this is a reference to an external, and there is no
10757 constant, or local symbol (*), with or without a
10759 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10760 or for lca or if tempreg is PIC_CALL_REG
10761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10763 If we have a small constant, and this is a reference to
10764 an external symbol, we want
10765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10766 addiu $tempreg,$tempreg,<constant>
10768 If we have a large constant, and this is a reference to
10769 an external symbol, we want
10770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10771 lui $at,<hiconstant>
10772 addiu $at,$at,<loconstant>
10773 addu $tempreg,$tempreg,$at
10775 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10776 local symbols, even though it introduces an additional
10779 if (offset_expr
.X_add_number
)
10781 expr1
.X_add_number
= offset_expr
.X_add_number
;
10782 offset_expr
.X_add_number
= 0;
10784 relax_start (offset_expr
.X_add_symbol
);
10785 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10786 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10788 if (expr1
.X_add_number
>= -0x8000
10789 && expr1
.X_add_number
< 0x8000)
10791 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10792 tempreg
, tempreg
, BFD_RELOC_LO16
);
10794 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10798 /* If we are going to add in a base register, and the
10799 target register and the base register are the same,
10800 then we are using AT as a temporary register. Since
10801 we want to load the constant into AT, we add our
10802 current AT (from the global offset table) and the
10803 register into the register now, and pretend we were
10804 not using a base register. */
10809 gas_assert (tempreg
== AT
);
10810 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10813 add_breg_early
= 1;
10816 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10817 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10823 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10826 offset_expr
.X_add_number
= expr1
.X_add_number
;
10828 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10829 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10830 if (add_breg_early
)
10832 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10833 op
[0], tempreg
, breg
);
10839 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10841 relax_start (offset_expr
.X_add_symbol
);
10842 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10843 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10845 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10846 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10852 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10855 else if (mips_big_got
&& !HAVE_NEWABI
)
10858 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10859 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10860 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10862 /* This is the large GOT case. If this is a reference to an
10863 external symbol, and there is no constant, we want
10864 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10865 addu $tempreg,$tempreg,$gp
10866 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10867 or for lca or if tempreg is PIC_CALL_REG
10868 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10869 addu $tempreg,$tempreg,$gp
10870 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10871 For a local symbol, we want
10872 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10874 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10876 If we have a small constant, and this is a reference to
10877 an external symbol, we want
10878 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10879 addu $tempreg,$tempreg,$gp
10880 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10882 addiu $tempreg,$tempreg,<constant>
10883 For a local symbol, we want
10884 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10886 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10888 If we have a large constant, and this is a reference to
10889 an external symbol, we want
10890 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10891 addu $tempreg,$tempreg,$gp
10892 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10893 lui $at,<hiconstant>
10894 addiu $at,$at,<loconstant>
10895 addu $tempreg,$tempreg,$at
10896 For a local symbol, we want
10897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10898 lui $at,<hiconstant>
10899 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10900 addu $tempreg,$tempreg,$at
10903 expr1
.X_add_number
= offset_expr
.X_add_number
;
10904 offset_expr
.X_add_number
= 0;
10905 relax_start (offset_expr
.X_add_symbol
);
10906 gpdelay
= reg_needs_delay (mips_gp_register
);
10907 if (expr1
.X_add_number
== 0 && breg
== 0
10908 && (call
|| tempreg
== PIC_CALL_REG
))
10910 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10911 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10913 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10915 tempreg
, tempreg
, mips_gp_register
);
10916 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10917 tempreg
, lw_reloc_type
, tempreg
);
10918 if (expr1
.X_add_number
== 0)
10922 /* We're going to put in an addu instruction using
10923 tempreg, so we may as well insert the nop right
10928 else if (expr1
.X_add_number
>= -0x8000
10929 && expr1
.X_add_number
< 0x8000)
10932 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10933 tempreg
, tempreg
, BFD_RELOC_LO16
);
10939 /* If we are going to add in a base register, and the
10940 target register and the base register are the same,
10941 then we are using AT as a temporary register. Since
10942 we want to load the constant into AT, we add our
10943 current AT (from the global offset table) and the
10944 register into the register now, and pretend we were
10945 not using a base register. */
10950 gas_assert (tempreg
== AT
);
10952 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10957 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10958 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10962 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10967 /* This is needed because this instruction uses $gp, but
10968 the first instruction on the main stream does not. */
10969 macro_build (NULL
, "nop", "");
10972 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10973 local_reloc_type
, mips_gp_register
);
10974 if (expr1
.X_add_number
>= -0x8000
10975 && expr1
.X_add_number
< 0x8000)
10978 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10979 tempreg
, tempreg
, BFD_RELOC_LO16
);
10980 /* FIXME: If add_number is 0, and there was no base
10981 register, the external symbol case ended with a load,
10982 so if the symbol turns out to not be external, and
10983 the next instruction uses tempreg, an unnecessary nop
10984 will be inserted. */
10990 /* We must add in the base register now, as in the
10991 external symbol case. */
10992 gas_assert (tempreg
== AT
);
10994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10997 /* We set breg to 0 because we have arranged to add
10998 it in in both cases. */
11002 macro_build_lui (&expr1
, AT
);
11003 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11004 AT
, AT
, BFD_RELOC_LO16
);
11005 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11006 tempreg
, tempreg
, AT
);
11011 else if (mips_big_got
&& HAVE_NEWABI
)
11013 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11014 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11015 int add_breg_early
= 0;
11017 /* This is the large GOT case. If this is a reference to an
11018 external symbol, and there is no constant, we want
11019 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11020 add $tempreg,$tempreg,$gp
11021 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11022 or for lca or if tempreg is PIC_CALL_REG
11023 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11024 add $tempreg,$tempreg,$gp
11025 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11027 If we have a small constant, and this is a reference to
11028 an external symbol, we want
11029 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11030 add $tempreg,$tempreg,$gp
11031 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11032 addi $tempreg,$tempreg,<constant>
11034 If we have a large constant, and this is a reference to
11035 an external symbol, we want
11036 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11037 addu $tempreg,$tempreg,$gp
11038 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11039 lui $at,<hiconstant>
11040 addi $at,$at,<loconstant>
11041 add $tempreg,$tempreg,$at
11043 If we have NewABI, and we know it's a local symbol, we want
11044 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11045 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11046 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11048 relax_start (offset_expr
.X_add_symbol
);
11050 expr1
.X_add_number
= offset_expr
.X_add_number
;
11051 offset_expr
.X_add_number
= 0;
11053 if (expr1
.X_add_number
== 0 && breg
== 0
11054 && (call
|| tempreg
== PIC_CALL_REG
))
11056 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11057 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11059 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11060 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11061 tempreg
, tempreg
, mips_gp_register
);
11062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11063 tempreg
, lw_reloc_type
, tempreg
);
11065 if (expr1
.X_add_number
== 0)
11067 else if (expr1
.X_add_number
>= -0x8000
11068 && expr1
.X_add_number
< 0x8000)
11070 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11071 tempreg
, tempreg
, BFD_RELOC_LO16
);
11073 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11077 /* If we are going to add in a base register, and the
11078 target register and the base register are the same,
11079 then we are using AT as a temporary register. Since
11080 we want to load the constant into AT, we add our
11081 current AT (from the global offset table) and the
11082 register into the register now, and pretend we were
11083 not using a base register. */
11088 gas_assert (tempreg
== AT
);
11089 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11092 add_breg_early
= 1;
11095 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11101 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11104 offset_expr
.X_add_number
= expr1
.X_add_number
;
11105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11106 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11107 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11108 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11109 if (add_breg_early
)
11111 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11112 op
[0], tempreg
, breg
);
11122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11126 gas_assert (!mips_opts
.micromips
);
11127 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11131 gas_assert (!mips_opts
.micromips
);
11132 macro_build (NULL
, "c2", "C", 0x02);
11136 gas_assert (!mips_opts
.micromips
);
11137 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11141 gas_assert (!mips_opts
.micromips
);
11142 macro_build (NULL
, "c2", "C", 3);
11146 gas_assert (!mips_opts
.micromips
);
11147 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11151 /* The j instruction may not be used in PIC code, since it
11152 requires an absolute address. We convert it to a b
11154 if (mips_pic
== NO_PIC
)
11155 macro_build (&offset_expr
, "j", "a");
11157 macro_build (&offset_expr
, "b", "p");
11160 /* The jal instructions must be handled as macros because when
11161 generating PIC code they expand to multi-instruction
11162 sequences. Normally they are simple instructions. */
11166 /* Fall through. */
11168 gas_assert (mips_opts
.micromips
);
11169 if (mips_opts
.insn32
)
11171 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11179 /* Fall through. */
11182 if (mips_pic
== NO_PIC
)
11184 s
= jals
? "jalrs" : "jalr";
11185 if (mips_opts
.micromips
11186 && !mips_opts
.insn32
11188 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11189 macro_build (NULL
, s
, "mj", op
[1]);
11191 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11195 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11196 && mips_cprestore_offset
>= 0);
11198 if (op
[1] != PIC_CALL_REG
)
11199 as_warn (_("MIPS PIC call to register other than $25"));
11201 s
= ((mips_opts
.micromips
11202 && !mips_opts
.insn32
11203 && (!mips_opts
.noreorder
|| cprestore
))
11204 ? "jalrs" : "jalr");
11205 if (mips_opts
.micromips
11206 && !mips_opts
.insn32
11208 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11209 macro_build (NULL
, s
, "mj", op
[1]);
11211 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11212 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11214 if (mips_cprestore_offset
< 0)
11215 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11218 if (!mips_frame_reg_valid
)
11220 as_warn (_("no .frame pseudo-op used in PIC code"));
11221 /* Quiet this warning. */
11222 mips_frame_reg_valid
= 1;
11224 if (!mips_cprestore_valid
)
11226 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11227 /* Quiet this warning. */
11228 mips_cprestore_valid
= 1;
11230 if (mips_opts
.noreorder
)
11231 macro_build (NULL
, "nop", "");
11232 expr1
.X_add_number
= mips_cprestore_offset
;
11233 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11236 HAVE_64BIT_ADDRESSES
);
11244 gas_assert (mips_opts
.micromips
);
11245 if (mips_opts
.insn32
)
11247 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11251 /* Fall through. */
11253 if (mips_pic
== NO_PIC
)
11254 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11255 else if (mips_pic
== SVR4_PIC
)
11257 /* If this is a reference to an external symbol, and we are
11258 using a small GOT, we want
11259 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11263 lw $gp,cprestore($sp)
11264 The cprestore value is set using the .cprestore
11265 pseudo-op. If we are using a big GOT, we want
11266 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11268 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11272 lw $gp,cprestore($sp)
11273 If the symbol is not external, we want
11274 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11276 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11279 lw $gp,cprestore($sp)
11281 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11282 sequences above, minus nops, unless the symbol is local,
11283 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11289 relax_start (offset_expr
.X_add_symbol
);
11290 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11291 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11294 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11295 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11301 relax_start (offset_expr
.X_add_symbol
);
11302 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11303 BFD_RELOC_MIPS_CALL_HI16
);
11304 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11305 PIC_CALL_REG
, mips_gp_register
);
11306 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11307 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11310 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11311 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11313 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11314 PIC_CALL_REG
, PIC_CALL_REG
,
11315 BFD_RELOC_MIPS_GOT_OFST
);
11319 macro_build_jalr (&offset_expr
, 0);
11323 relax_start (offset_expr
.X_add_symbol
);
11326 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11327 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11336 gpdelay
= reg_needs_delay (mips_gp_register
);
11337 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11338 BFD_RELOC_MIPS_CALL_HI16
);
11339 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11340 PIC_CALL_REG
, mips_gp_register
);
11341 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11342 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11347 macro_build (NULL
, "nop", "");
11349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11350 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11353 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11354 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11356 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11358 if (mips_cprestore_offset
< 0)
11359 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11362 if (!mips_frame_reg_valid
)
11364 as_warn (_("no .frame pseudo-op used in PIC code"));
11365 /* Quiet this warning. */
11366 mips_frame_reg_valid
= 1;
11368 if (!mips_cprestore_valid
)
11370 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11371 /* Quiet this warning. */
11372 mips_cprestore_valid
= 1;
11374 if (mips_opts
.noreorder
)
11375 macro_build (NULL
, "nop", "");
11376 expr1
.X_add_number
= mips_cprestore_offset
;
11377 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11380 HAVE_64BIT_ADDRESSES
);
11384 else if (mips_pic
== VXWORKS_PIC
)
11385 as_bad (_("non-PIC jump used in PIC library"));
11492 gas_assert (!mips_opts
.micromips
);
11495 /* Itbl support may require additional care here. */
11501 /* Itbl support may require additional care here. */
11507 offbits
= (mips_opts
.micromips
? 12
11508 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11510 /* Itbl support may require additional care here. */
11514 gas_assert (!mips_opts
.micromips
);
11517 /* Itbl support may require additional care here. */
11523 offbits
= (mips_opts
.micromips
? 12 : 16);
11528 offbits
= (mips_opts
.micromips
? 12 : 16);
11533 /* Itbl support may require additional care here. */
11539 offbits
= (mips_opts
.micromips
? 12
11540 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11542 /* Itbl support may require additional care here. */
11548 /* Itbl support may require additional care here. */
11554 /* Itbl support may require additional care here. */
11560 offbits
= (mips_opts
.micromips
? 12 : 16);
11565 offbits
= (mips_opts
.micromips
? 12 : 16);
11570 offbits
= (mips_opts
.micromips
? 12
11571 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11577 offbits
= (mips_opts
.micromips
? 12
11578 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11584 offbits
= (mips_opts
.micromips
? 12 : 16);
11587 gas_assert (mips_opts
.micromips
);
11594 gas_assert (mips_opts
.micromips
);
11601 gas_assert (mips_opts
.micromips
);
11607 gas_assert (mips_opts
.micromips
);
11614 /* We don't want to use $0 as tempreg. */
11615 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11618 tempreg
= op
[0] + lp
;
11634 gas_assert (!mips_opts
.micromips
);
11637 /* Itbl support may require additional care here. */
11643 /* Itbl support may require additional care here. */
11649 offbits
= (mips_opts
.micromips
? 12
11650 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11652 /* Itbl support may require additional care here. */
11656 gas_assert (!mips_opts
.micromips
);
11659 /* Itbl support may require additional care here. */
11665 offbits
= (mips_opts
.micromips
? 12 : 16);
11670 offbits
= (mips_opts
.micromips
? 12 : 16);
11675 offbits
= (mips_opts
.micromips
? 12
11676 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11682 offbits
= (mips_opts
.micromips
? 12
11683 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11688 fmt
= (mips_opts
.micromips
? "k,~(b)"
11689 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11691 offbits
= (mips_opts
.micromips
? 12
11692 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11702 fmt
= (mips_opts
.micromips
? "k,~(b)"
11703 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11705 offbits
= (mips_opts
.micromips
? 12
11706 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11718 /* Itbl support may require additional care here. */
11723 offbits
= (mips_opts
.micromips
? 12
11724 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11726 /* Itbl support may require additional care here. */
11732 /* Itbl support may require additional care here. */
11736 gas_assert (!mips_opts
.micromips
);
11739 /* Itbl support may require additional care here. */
11745 offbits
= (mips_opts
.micromips
? 12 : 16);
11750 offbits
= (mips_opts
.micromips
? 12 : 16);
11753 gas_assert (mips_opts
.micromips
);
11759 gas_assert (mips_opts
.micromips
);
11765 gas_assert (mips_opts
.micromips
);
11771 gas_assert (mips_opts
.micromips
);
11780 if (small_offset_p (0, align
, 16))
11782 /* The first case exists for M_LD_AB and M_SD_AB, which are
11783 macros for o32 but which should act like normal instructions
11786 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11787 offset_reloc
[1], offset_reloc
[2], breg
);
11788 else if (small_offset_p (0, align
, offbits
))
11791 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11793 macro_build (NULL
, s
, fmt
, op
[0],
11794 (int) offset_expr
.X_add_number
, breg
);
11800 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11801 tempreg
, breg
, -1, offset_reloc
[0],
11802 offset_reloc
[1], offset_reloc
[2]);
11804 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11806 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11814 if (offset_expr
.X_op
!= O_constant
11815 && offset_expr
.X_op
!= O_symbol
)
11817 as_bad (_("expression too complex"));
11818 offset_expr
.X_op
= O_constant
;
11821 if (HAVE_32BIT_ADDRESSES
11822 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11826 sprintf_vma (value
, offset_expr
.X_add_number
);
11827 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11830 /* A constant expression in PIC code can be handled just as it
11831 is in non PIC code. */
11832 if (offset_expr
.X_op
== O_constant
)
11834 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11835 offbits
== 0 ? 16 : offbits
);
11836 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11838 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11840 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11841 tempreg
, tempreg
, breg
);
11844 if (offset_expr
.X_add_number
!= 0)
11845 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11846 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11847 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11849 else if (offbits
== 16)
11850 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11852 macro_build (NULL
, s
, fmt
, op
[0],
11853 (int) offset_expr
.X_add_number
, tempreg
);
11855 else if (offbits
!= 16)
11857 /* The offset field is too narrow to be used for a low-part
11858 relocation, so load the whole address into the auxiliary
11860 load_address (tempreg
, &offset_expr
, &used_at
);
11862 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11863 tempreg
, tempreg
, breg
);
11865 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11867 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11869 else if (mips_pic
== NO_PIC
)
11871 /* If this is a reference to a GP relative symbol, and there
11872 is no base register, we want
11873 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11874 Otherwise, if there is no base register, we want
11875 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11876 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11877 If we have a constant, we need two instructions anyhow,
11878 so we always use the latter form.
11880 If we have a base register, and this is a reference to a
11881 GP relative symbol, we want
11882 addu $tempreg,$breg,$gp
11883 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11885 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11886 addu $tempreg,$tempreg,$breg
11887 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11888 With a constant we always use the latter case.
11890 With 64bit address space and no base register and $at usable,
11892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11893 lui $at,<sym> (BFD_RELOC_HI16_S)
11894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11897 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11898 If we have a base register, we want
11899 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11900 lui $at,<sym> (BFD_RELOC_HI16_S)
11901 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11905 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11907 Without $at we can't generate the optimal path for superscalar
11908 processors here since this would require two temporary registers.
11909 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11910 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11912 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11914 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11915 If we have a base register, we want
11916 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11917 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11919 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11921 daddu $tempreg,$tempreg,$breg
11922 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11924 For GP relative symbols in 64bit address space we can use
11925 the same sequence as in 32bit address space. */
11926 if (HAVE_64BIT_SYMBOLS
)
11928 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11929 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11931 relax_start (offset_expr
.X_add_symbol
);
11934 macro_build (&offset_expr
, s
, fmt
, op
[0],
11935 BFD_RELOC_GPREL16
, mips_gp_register
);
11939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11940 tempreg
, breg
, mips_gp_register
);
11941 macro_build (&offset_expr
, s
, fmt
, op
[0],
11942 BFD_RELOC_GPREL16
, tempreg
);
11947 if (used_at
== 0 && mips_opts
.at
)
11949 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11950 BFD_RELOC_MIPS_HIGHEST
);
11951 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11953 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11954 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11956 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11957 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11958 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11959 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11965 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11966 BFD_RELOC_MIPS_HIGHEST
);
11967 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11968 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11969 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11970 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11971 tempreg
, BFD_RELOC_HI16_S
);
11972 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11974 macro_build (NULL
, "daddu", "d,v,t",
11975 tempreg
, tempreg
, breg
);
11976 macro_build (&offset_expr
, s
, fmt
, op
[0],
11977 BFD_RELOC_LO16
, tempreg
);
11980 if (mips_relax
.sequence
)
11987 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11988 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11990 relax_start (offset_expr
.X_add_symbol
);
11991 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11995 macro_build_lui (&offset_expr
, tempreg
);
11996 macro_build (&offset_expr
, s
, fmt
, op
[0],
11997 BFD_RELOC_LO16
, tempreg
);
11998 if (mips_relax
.sequence
)
12003 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12004 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12006 relax_start (offset_expr
.X_add_symbol
);
12007 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12008 tempreg
, breg
, mips_gp_register
);
12009 macro_build (&offset_expr
, s
, fmt
, op
[0],
12010 BFD_RELOC_GPREL16
, tempreg
);
12013 macro_build_lui (&offset_expr
, tempreg
);
12014 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12015 tempreg
, tempreg
, breg
);
12016 macro_build (&offset_expr
, s
, fmt
, op
[0],
12017 BFD_RELOC_LO16
, tempreg
);
12018 if (mips_relax
.sequence
)
12022 else if (!mips_big_got
)
12024 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12026 /* If this is a reference to an external symbol, we want
12027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12029 <op> op[0],0($tempreg)
12031 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12033 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12034 <op> op[0],0($tempreg)
12036 For NewABI, we want
12037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12038 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12040 If there is a base register, we add it to $tempreg before
12041 the <op>. If there is a constant, we stick it in the
12042 <op> instruction. We don't handle constants larger than
12043 16 bits, because we have no way to load the upper 16 bits
12044 (actually, we could handle them for the subset of cases
12045 in which we are not using $at). */
12046 gas_assert (offset_expr
.X_op
== O_symbol
);
12049 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12050 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12052 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12053 tempreg
, tempreg
, breg
);
12054 macro_build (&offset_expr
, s
, fmt
, op
[0],
12055 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12058 expr1
.X_add_number
= offset_expr
.X_add_number
;
12059 offset_expr
.X_add_number
= 0;
12060 if (expr1
.X_add_number
< -0x8000
12061 || expr1
.X_add_number
>= 0x8000)
12062 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12063 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12064 lw_reloc_type
, mips_gp_register
);
12066 relax_start (offset_expr
.X_add_symbol
);
12068 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12069 tempreg
, BFD_RELOC_LO16
);
12072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12073 tempreg
, tempreg
, breg
);
12074 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12076 else if (mips_big_got
&& !HAVE_NEWABI
)
12080 /* If this is a reference to an external symbol, we want
12081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12082 addu $tempreg,$tempreg,$gp
12083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12084 <op> op[0],0($tempreg)
12086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12088 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12089 <op> op[0],0($tempreg)
12090 If there is a base register, we add it to $tempreg before
12091 the <op>. If there is a constant, we stick it in the
12092 <op> instruction. We don't handle constants larger than
12093 16 bits, because we have no way to load the upper 16 bits
12094 (actually, we could handle them for the subset of cases
12095 in which we are not using $at). */
12096 gas_assert (offset_expr
.X_op
== O_symbol
);
12097 expr1
.X_add_number
= offset_expr
.X_add_number
;
12098 offset_expr
.X_add_number
= 0;
12099 if (expr1
.X_add_number
< -0x8000
12100 || expr1
.X_add_number
>= 0x8000)
12101 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12102 gpdelay
= reg_needs_delay (mips_gp_register
);
12103 relax_start (offset_expr
.X_add_symbol
);
12104 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12105 BFD_RELOC_MIPS_GOT_HI16
);
12106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12108 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12109 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12112 macro_build (NULL
, "nop", "");
12113 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12114 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12116 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12117 tempreg
, BFD_RELOC_LO16
);
12121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12122 tempreg
, tempreg
, breg
);
12123 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12125 else if (mips_big_got
&& HAVE_NEWABI
)
12127 /* If this is a reference to an external symbol, we want
12128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12129 add $tempreg,$tempreg,$gp
12130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12131 <op> op[0],<ofst>($tempreg)
12132 Otherwise, for local symbols, we want:
12133 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12134 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12135 gas_assert (offset_expr
.X_op
== O_symbol
);
12136 expr1
.X_add_number
= offset_expr
.X_add_number
;
12137 offset_expr
.X_add_number
= 0;
12138 if (expr1
.X_add_number
< -0x8000
12139 || expr1
.X_add_number
>= 0x8000)
12140 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12141 relax_start (offset_expr
.X_add_symbol
);
12142 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12143 BFD_RELOC_MIPS_GOT_HI16
);
12144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12146 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12147 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12149 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12150 tempreg
, tempreg
, breg
);
12151 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12154 offset_expr
.X_add_number
= expr1
.X_add_number
;
12155 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12156 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12158 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12159 tempreg
, tempreg
, breg
);
12160 macro_build (&offset_expr
, s
, fmt
, op
[0],
12161 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12170 gas_assert (mips_opts
.micromips
);
12171 gas_assert (mips_opts
.insn32
);
12172 start_noreorder ();
12173 macro_build (NULL
, "jr", "s", RA
);
12174 expr1
.X_add_number
= op
[0] << 2;
12175 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12180 gas_assert (mips_opts
.micromips
);
12181 gas_assert (mips_opts
.insn32
);
12182 macro_build (NULL
, "jr", "s", op
[0]);
12183 if (mips_opts
.noreorder
)
12184 macro_build (NULL
, "nop", "");
12189 load_register (op
[0], &imm_expr
, 0);
12193 load_register (op
[0], &imm_expr
, 1);
12197 if (imm_expr
.X_op
== O_constant
)
12200 load_register (AT
, &imm_expr
, 0);
12201 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12206 gas_assert (imm_expr
.X_op
== O_absent
12207 && offset_expr
.X_op
== O_symbol
12208 && strcmp (segment_name (S_GET_SEGMENT
12209 (offset_expr
.X_add_symbol
)),
12211 && offset_expr
.X_add_number
== 0);
12212 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12213 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12218 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12219 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12220 order 32 bits of the value and the low order 32 bits are either
12221 zero or in OFFSET_EXPR. */
12222 if (imm_expr
.X_op
== O_constant
)
12224 if (GPR_SIZE
== 64)
12225 load_register (op
[0], &imm_expr
, 1);
12230 if (target_big_endian
)
12242 load_register (hreg
, &imm_expr
, 0);
12245 if (offset_expr
.X_op
== O_absent
)
12246 move_register (lreg
, 0);
12249 gas_assert (offset_expr
.X_op
== O_constant
);
12250 load_register (lreg
, &offset_expr
, 0);
12256 gas_assert (imm_expr
.X_op
== O_absent
);
12258 /* We know that sym is in the .rdata section. First we get the
12259 upper 16 bits of the address. */
12260 if (mips_pic
== NO_PIC
)
12262 macro_build_lui (&offset_expr
, AT
);
12267 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12268 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12272 /* Now we load the register(s). */
12273 if (GPR_SIZE
== 64)
12276 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12277 BFD_RELOC_LO16
, AT
);
12282 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12283 BFD_RELOC_LO16
, AT
);
12286 /* FIXME: How in the world do we deal with the possible
12288 offset_expr
.X_add_number
+= 4;
12289 macro_build (&offset_expr
, "lw", "t,o(b)",
12290 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12296 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12297 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12298 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12299 the value and the low order 32 bits are either zero or in
12301 if (imm_expr
.X_op
== O_constant
)
12304 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12305 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12306 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12309 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12310 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12311 else if (FPR_SIZE
!= 32)
12312 as_bad (_("Unable to generate `%s' compliant code "
12314 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12316 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12317 if (offset_expr
.X_op
== O_absent
)
12318 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12321 gas_assert (offset_expr
.X_op
== O_constant
);
12322 load_register (AT
, &offset_expr
, 0);
12323 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12329 gas_assert (imm_expr
.X_op
== O_absent
12330 && offset_expr
.X_op
== O_symbol
12331 && offset_expr
.X_add_number
== 0);
12332 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12333 if (strcmp (s
, ".lit8") == 0)
12335 op
[2] = mips_gp_register
;
12336 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12337 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12338 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12342 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12344 if (mips_pic
!= NO_PIC
)
12345 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12346 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12349 /* FIXME: This won't work for a 64 bit address. */
12350 macro_build_lui (&offset_expr
, AT
);
12354 offset_reloc
[0] = BFD_RELOC_LO16
;
12355 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12356 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12363 * The MIPS assembler seems to check for X_add_number not
12364 * being double aligned and generating:
12365 * lui at,%hi(foo+1)
12367 * addiu at,at,%lo(foo+1)
12370 * But, the resulting address is the same after relocation so why
12371 * generate the extra instruction?
12373 /* Itbl support may require additional care here. */
12376 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12385 gas_assert (!mips_opts
.micromips
);
12386 /* Itbl support may require additional care here. */
12389 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12409 if (GPR_SIZE
== 64)
12419 if (GPR_SIZE
== 64)
12427 /* Even on a big endian machine $fn comes before $fn+1. We have
12428 to adjust when loading from memory. We set coproc if we must
12429 load $fn+1 first. */
12430 /* Itbl support may require additional care here. */
12431 if (!target_big_endian
)
12435 if (small_offset_p (0, align
, 16))
12438 if (!small_offset_p (4, align
, 16))
12440 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12441 -1, offset_reloc
[0], offset_reloc
[1],
12443 expr1
.X_add_number
= 0;
12447 offset_reloc
[0] = BFD_RELOC_LO16
;
12448 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12449 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12451 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12453 ep
->X_add_number
+= 4;
12454 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12455 offset_reloc
[1], offset_reloc
[2], breg
);
12456 ep
->X_add_number
-= 4;
12457 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12458 offset_reloc
[1], offset_reloc
[2], breg
);
12462 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12463 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12465 ep
->X_add_number
+= 4;
12466 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12467 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12473 if (offset_expr
.X_op
!= O_symbol
12474 && offset_expr
.X_op
!= O_constant
)
12476 as_bad (_("expression too complex"));
12477 offset_expr
.X_op
= O_constant
;
12480 if (HAVE_32BIT_ADDRESSES
12481 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12485 sprintf_vma (value
, offset_expr
.X_add_number
);
12486 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12489 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12491 /* If this is a reference to a GP relative symbol, we want
12492 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12493 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12494 If we have a base register, we use this
12496 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12497 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12498 If this is not a GP relative symbol, we want
12499 lui $at,<sym> (BFD_RELOC_HI16_S)
12500 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12501 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12502 If there is a base register, we add it to $at after the
12503 lui instruction. If there is a constant, we always use
12505 if (offset_expr
.X_op
== O_symbol
12506 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12507 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12509 relax_start (offset_expr
.X_add_symbol
);
12512 tempreg
= mips_gp_register
;
12516 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12517 AT
, breg
, mips_gp_register
);
12522 /* Itbl support may require additional care here. */
12523 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12524 BFD_RELOC_GPREL16
, tempreg
);
12525 offset_expr
.X_add_number
+= 4;
12527 /* Set mips_optimize to 2 to avoid inserting an
12529 hold_mips_optimize
= mips_optimize
;
12531 /* Itbl support may require additional care here. */
12532 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12533 BFD_RELOC_GPREL16
, tempreg
);
12534 mips_optimize
= hold_mips_optimize
;
12538 offset_expr
.X_add_number
-= 4;
12541 if (offset_high_part (offset_expr
.X_add_number
, 16)
12542 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12544 load_address (AT
, &offset_expr
, &used_at
);
12545 offset_expr
.X_op
= O_constant
;
12546 offset_expr
.X_add_number
= 0;
12549 macro_build_lui (&offset_expr
, AT
);
12551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12552 /* Itbl support may require additional care here. */
12553 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12554 BFD_RELOC_LO16
, AT
);
12555 /* FIXME: How do we handle overflow here? */
12556 offset_expr
.X_add_number
+= 4;
12557 /* Itbl support may require additional care here. */
12558 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12559 BFD_RELOC_LO16
, AT
);
12560 if (mips_relax
.sequence
)
12563 else if (!mips_big_got
)
12565 /* If this is a reference to an external symbol, we want
12566 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12569 <op> op[0]+1,4($at)
12571 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12573 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12574 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12575 If there is a base register we add it to $at before the
12576 lwc1 instructions. If there is a constant we include it
12577 in the lwc1 instructions. */
12579 expr1
.X_add_number
= offset_expr
.X_add_number
;
12580 if (expr1
.X_add_number
< -0x8000
12581 || expr1
.X_add_number
>= 0x8000 - 4)
12582 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12583 load_got_offset (AT
, &offset_expr
);
12586 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12588 /* Set mips_optimize to 2 to avoid inserting an undesired
12590 hold_mips_optimize
= mips_optimize
;
12593 /* Itbl support may require additional care here. */
12594 relax_start (offset_expr
.X_add_symbol
);
12595 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12596 BFD_RELOC_LO16
, AT
);
12597 expr1
.X_add_number
+= 4;
12598 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12599 BFD_RELOC_LO16
, AT
);
12601 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12602 BFD_RELOC_LO16
, AT
);
12603 offset_expr
.X_add_number
+= 4;
12604 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12605 BFD_RELOC_LO16
, AT
);
12608 mips_optimize
= hold_mips_optimize
;
12610 else if (mips_big_got
)
12614 /* If this is a reference to an external symbol, we want
12615 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12617 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12620 <op> op[0]+1,4($at)
12622 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12624 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12625 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12626 If there is a base register we add it to $at before the
12627 lwc1 instructions. If there is a constant we include it
12628 in the lwc1 instructions. */
12630 expr1
.X_add_number
= offset_expr
.X_add_number
;
12631 offset_expr
.X_add_number
= 0;
12632 if (expr1
.X_add_number
< -0x8000
12633 || expr1
.X_add_number
>= 0x8000 - 4)
12634 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12635 gpdelay
= reg_needs_delay (mips_gp_register
);
12636 relax_start (offset_expr
.X_add_symbol
);
12637 macro_build (&offset_expr
, "lui", LUI_FMT
,
12638 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12640 AT
, AT
, mips_gp_register
);
12641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12642 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12645 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12646 /* Itbl support may require additional care here. */
12647 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12648 BFD_RELOC_LO16
, AT
);
12649 expr1
.X_add_number
+= 4;
12651 /* Set mips_optimize to 2 to avoid inserting an undesired
12653 hold_mips_optimize
= mips_optimize
;
12655 /* Itbl support may require additional care here. */
12656 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12657 BFD_RELOC_LO16
, AT
);
12658 mips_optimize
= hold_mips_optimize
;
12659 expr1
.X_add_number
-= 4;
12662 offset_expr
.X_add_number
= expr1
.X_add_number
;
12664 macro_build (NULL
, "nop", "");
12665 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12666 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12670 /* Itbl support may require additional care here. */
12671 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12672 BFD_RELOC_LO16
, AT
);
12673 offset_expr
.X_add_number
+= 4;
12675 /* Set mips_optimize to 2 to avoid inserting an undesired
12677 hold_mips_optimize
= mips_optimize
;
12679 /* Itbl support may require additional care here. */
12680 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12681 BFD_RELOC_LO16
, AT
);
12682 mips_optimize
= hold_mips_optimize
;
12696 gas_assert (!mips_opts
.micromips
);
12701 /* New code added to support COPZ instructions.
12702 This code builds table entries out of the macros in mip_opcodes.
12703 R4000 uses interlocks to handle coproc delays.
12704 Other chips (like the R3000) require nops to be inserted for delays.
12706 FIXME: Currently, we require that the user handle delays.
12707 In order to fill delay slots for non-interlocked chips,
12708 we must have a way to specify delays based on the coprocessor.
12709 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12710 What are the side-effects of the cop instruction?
12711 What cache support might we have and what are its effects?
12712 Both coprocessor & memory require delays. how long???
12713 What registers are read/set/modified?
12715 If an itbl is provided to interpret cop instructions,
12716 this knowledge can be encoded in the itbl spec. */
12730 gas_assert (!mips_opts
.micromips
);
12731 /* For now we just do C (same as Cz). The parameter will be
12732 stored in insn_opcode by mips_ip. */
12733 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12737 move_register (op
[0], op
[1]);
12741 gas_assert (mips_opts
.micromips
);
12742 gas_assert (mips_opts
.insn32
);
12743 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12744 micromips_to_32_reg_m_map
[op
[1]]);
12745 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12746 micromips_to_32_reg_n_map
[op
[2]]);
12751 /* Fall through. */
12753 if (mips_opts
.arch
== CPU_R5900
)
12754 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12758 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12759 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12765 /* Fall through. */
12767 /* The MIPS assembler some times generates shifts and adds. I'm
12768 not trying to be that fancy. GCC should do this for us
12771 load_register (AT
, &imm_expr
, dbl
);
12772 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12773 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12778 /* Fall through. */
12785 /* Fall through. */
12788 start_noreorder ();
12791 load_register (AT
, &imm_expr
, dbl
);
12792 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12793 op
[1], imm
? AT
: op
[2]);
12794 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12795 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12796 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12798 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12801 if (mips_opts
.micromips
)
12802 micromips_label_expr (&label_expr
);
12804 label_expr
.X_add_number
= 8;
12805 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12806 macro_build (NULL
, "nop", "");
12807 macro_build (NULL
, "break", BRK_FMT
, 6);
12808 if (mips_opts
.micromips
)
12809 micromips_add_label ();
12812 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12817 /* Fall through. */
12824 /* Fall through. */
12827 start_noreorder ();
12830 load_register (AT
, &imm_expr
, dbl
);
12831 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12832 op
[1], imm
? AT
: op
[2]);
12833 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12834 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12836 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12839 if (mips_opts
.micromips
)
12840 micromips_label_expr (&label_expr
);
12842 label_expr
.X_add_number
= 8;
12843 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12844 macro_build (NULL
, "nop", "");
12845 macro_build (NULL
, "break", BRK_FMT
, 6);
12846 if (mips_opts
.micromips
)
12847 micromips_add_label ();
12853 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12855 if (op
[0] == op
[1])
12862 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12863 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12867 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12868 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12869 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12870 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12874 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12876 if (op
[0] == op
[1])
12883 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12884 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12888 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12889 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12890 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12891 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12900 rot
= imm_expr
.X_add_number
& 0x3f;
12901 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12903 rot
= (64 - rot
) & 0x3f;
12905 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12907 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12912 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12915 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12916 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12919 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12920 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12921 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12929 rot
= imm_expr
.X_add_number
& 0x1f;
12930 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12932 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12933 (32 - rot
) & 0x1f);
12938 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12942 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12943 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12944 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12949 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12951 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12955 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12956 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12957 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12958 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12962 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12964 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12968 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12969 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12970 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12971 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12980 rot
= imm_expr
.X_add_number
& 0x3f;
12981 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12984 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12986 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12991 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12994 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12995 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12998 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12999 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13000 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13008 rot
= imm_expr
.X_add_number
& 0x1f;
13009 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13011 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13016 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13020 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13021 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13022 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13028 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13029 else if (op
[2] == 0)
13030 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13033 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13034 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13039 if (imm_expr
.X_add_number
== 0)
13041 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13046 as_warn (_("instruction %s: result is always false"),
13047 ip
->insn_mo
->name
);
13048 move_register (op
[0], 0);
13051 if (CPU_HAS_SEQ (mips_opts
.arch
)
13052 && -512 <= imm_expr
.X_add_number
13053 && imm_expr
.X_add_number
< 512)
13055 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13056 (int) imm_expr
.X_add_number
);
13059 if (imm_expr
.X_add_number
>= 0
13060 && imm_expr
.X_add_number
< 0x10000)
13061 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13062 else if (imm_expr
.X_add_number
> -0x8000
13063 && imm_expr
.X_add_number
< 0)
13065 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13066 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13067 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13069 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13072 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13073 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13078 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13079 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13082 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13085 case M_SGE
: /* X >= Y <==> not (X < Y) */
13091 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13092 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13095 case M_SGE_I
: /* X >= I <==> not (X < I) */
13097 if (imm_expr
.X_add_number
>= -0x8000
13098 && imm_expr
.X_add_number
< 0x8000)
13099 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13100 op
[0], op
[1], BFD_RELOC_LO16
);
13103 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13104 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13108 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13111 case M_SGT
: /* X > Y <==> Y < X */
13117 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13120 case M_SGT_I
: /* X > I <==> I < X */
13127 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13128 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13131 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13137 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13138 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13141 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13148 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13149 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13150 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13154 if (imm_expr
.X_add_number
>= -0x8000
13155 && imm_expr
.X_add_number
< 0x8000)
13157 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13162 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13163 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13167 if (imm_expr
.X_add_number
>= -0x8000
13168 && imm_expr
.X_add_number
< 0x8000)
13170 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13175 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13176 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13181 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13182 else if (op
[2] == 0)
13183 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13186 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13187 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13192 if (imm_expr
.X_add_number
== 0)
13194 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13199 as_warn (_("instruction %s: result is always true"),
13200 ip
->insn_mo
->name
);
13201 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13202 op
[0], 0, BFD_RELOC_LO16
);
13205 if (CPU_HAS_SEQ (mips_opts
.arch
)
13206 && -512 <= imm_expr
.X_add_number
13207 && imm_expr
.X_add_number
< 512)
13209 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13210 (int) imm_expr
.X_add_number
);
13213 if (imm_expr
.X_add_number
>= 0
13214 && imm_expr
.X_add_number
< 0x10000)
13216 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13219 else if (imm_expr
.X_add_number
> -0x8000
13220 && imm_expr
.X_add_number
< 0)
13222 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13223 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13224 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13226 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13229 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13230 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13235 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13236 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13239 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13254 if (!mips_opts
.micromips
)
13256 if (imm_expr
.X_add_number
> -0x200
13257 && imm_expr
.X_add_number
<= 0x200)
13259 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13260 (int) -imm_expr
.X_add_number
);
13269 if (imm_expr
.X_add_number
> -0x8000
13270 && imm_expr
.X_add_number
<= 0x8000)
13272 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13273 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13278 load_register (AT
, &imm_expr
, dbl
);
13279 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13301 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13302 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13307 gas_assert (!mips_opts
.micromips
);
13308 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13312 * Is the double cfc1 instruction a bug in the mips assembler;
13313 * or is there a reason for it?
13315 start_noreorder ();
13316 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13317 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13318 macro_build (NULL
, "nop", "");
13319 expr1
.X_add_number
= 3;
13320 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13321 expr1
.X_add_number
= 2;
13322 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13323 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13324 macro_build (NULL
, "nop", "");
13325 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13327 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13328 macro_build (NULL
, "nop", "");
13345 offbits
= (mips_opts
.micromips
? 12 : 16);
13351 offbits
= (mips_opts
.micromips
? 12 : 16);
13363 offbits
= (mips_opts
.micromips
? 12 : 16);
13370 offbits
= (mips_opts
.micromips
? 12 : 16);
13376 large_offset
= !small_offset_p (off
, align
, offbits
);
13378 expr1
.X_add_number
= 0;
13383 if (small_offset_p (0, align
, 16))
13384 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13385 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13388 load_address (tempreg
, ep
, &used_at
);
13390 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13391 tempreg
, tempreg
, breg
);
13393 offset_reloc
[0] = BFD_RELOC_LO16
;
13394 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13395 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13400 else if (!ust
&& op
[0] == breg
)
13411 if (!target_big_endian
)
13412 ep
->X_add_number
+= off
;
13414 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13416 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13417 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13419 if (!target_big_endian
)
13420 ep
->X_add_number
-= off
;
13422 ep
->X_add_number
+= off
;
13424 macro_build (NULL
, s2
, "t,~(b)",
13425 tempreg
, (int) ep
->X_add_number
, breg
);
13427 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13428 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13430 /* If necessary, move the result in tempreg to the final destination. */
13431 if (!ust
&& op
[0] != tempreg
)
13433 /* Protect second load's delay slot. */
13435 move_register (op
[0], tempreg
);
13441 if (target_big_endian
== ust
)
13442 ep
->X_add_number
+= off
;
13443 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13444 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13445 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13447 /* For halfword transfers we need a temporary register to shuffle
13448 bytes. Unfortunately for M_USH_A we have none available before
13449 the next store as AT holds the base address. We deal with this
13450 case by clobbering TREG and then restoring it as with ULH. */
13451 tempreg
= ust
== large_offset
? op
[0] : AT
;
13453 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13455 if (target_big_endian
== ust
)
13456 ep
->X_add_number
-= off
;
13458 ep
->X_add_number
+= off
;
13459 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13460 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13462 /* For M_USH_A re-retrieve the LSB. */
13463 if (ust
&& large_offset
)
13465 if (target_big_endian
)
13466 ep
->X_add_number
+= off
;
13468 ep
->X_add_number
-= off
;
13469 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13470 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13472 /* For ULH and M_USH_A OR the LSB in. */
13473 if (!ust
|| large_offset
)
13475 tempreg
= !large_offset
? AT
: op
[0];
13476 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13477 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13482 /* FIXME: Check if this is one of the itbl macros, since they
13483 are added dynamically. */
13484 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13487 if (!mips_opts
.at
&& used_at
)
13488 as_bad (_("macro used $at after \".set noat\""));
13491 /* Implement macros in mips16 mode. */
13494 mips16_macro (struct mips_cl_insn
*ip
)
13496 const struct mips_operand_array
*operands
;
13501 const char *s
, *s2
, *s3
;
13502 unsigned int op
[MAX_OPERANDS
];
13505 mask
= ip
->insn_mo
->mask
;
13507 operands
= insn_operands (ip
);
13508 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13509 if (operands
->operand
[i
])
13510 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13514 expr1
.X_op
= O_constant
;
13515 expr1
.X_op_symbol
= NULL
;
13516 expr1
.X_add_symbol
= NULL
;
13517 expr1
.X_add_number
= 1;
13528 /* Fall through. */
13534 /* Fall through. */
13538 start_noreorder ();
13539 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
13540 expr1
.X_add_number
= 2;
13541 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13542 macro_build (NULL
, "break", "6", 7);
13544 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13545 since that causes an overflow. We should do that as well,
13546 but I don't see how to do the comparisons without a temporary
13549 macro_build (NULL
, s
, "x", op
[0]);
13568 start_noreorder ();
13569 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
13570 expr1
.X_add_number
= 2;
13571 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13572 macro_build (NULL
, "break", "6", 7);
13574 macro_build (NULL
, s2
, "x", op
[0]);
13579 /* Fall through. */
13581 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13582 macro_build (NULL
, "mflo", "x", op
[0]);
13590 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13591 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
13595 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13596 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13600 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13601 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13623 goto do_reverse_branch
;
13627 goto do_reverse_branch
;
13639 goto do_reverse_branch
;
13650 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13651 macro_build (&offset_expr
, s2
, "p");
13678 goto do_addone_branch_i
;
13683 goto do_addone_branch_i
;
13698 goto do_addone_branch_i
;
13704 do_addone_branch_i
:
13705 ++imm_expr
.X_add_number
;
13708 macro_build (&imm_expr
, s
, s3
, op
[0]);
13709 macro_build (&offset_expr
, s2
, "p");
13713 expr1
.X_add_number
= 0;
13714 macro_build (&expr1
, "slti", "x,8", op
[1]);
13715 if (op
[0] != op
[1])
13716 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13717 expr1
.X_add_number
= 2;
13718 macro_build (&expr1
, "bteqz", "p");
13719 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13724 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13725 opcode bits in *OPCODE_EXTRA. */
13727 static struct mips_opcode
*
13728 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13729 ssize_t length
, unsigned int *opcode_extra
)
13731 char *name
, *dot
, *p
;
13732 unsigned int mask
, suffix
;
13734 struct mips_opcode
*insn
;
13736 /* Make a copy of the instruction so that we can fiddle with it. */
13737 name
= xstrndup (start
, length
);
13739 /* Look up the instruction as-is. */
13740 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13744 dot
= strchr (name
, '.');
13747 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13748 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13749 if (*p
== 0 && mask
!= 0)
13752 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13754 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13756 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13762 if (mips_opts
.micromips
)
13764 /* See if there's an instruction size override suffix,
13765 either `16' or `32', at the end of the mnemonic proper,
13766 that defines the operation, i.e. before the first `.'
13767 character if any. Strip it and retry. */
13768 opend
= dot
!= NULL
? dot
- name
: length
;
13769 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13771 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13777 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13778 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13781 forced_insn_length
= suffix
;
13793 /* Assemble an instruction into its binary format. If the instruction
13794 is a macro, set imm_expr and offset_expr to the values associated
13795 with "I" and "A" operands respectively. Otherwise store the value
13796 of the relocatable field (if any) in offset_expr. In both cases
13797 set offset_reloc to the relocation operators applied to offset_expr. */
13800 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13802 const struct mips_opcode
*first
, *past
;
13803 struct hash_control
*hash
;
13806 struct mips_operand_token
*tokens
;
13807 unsigned int opcode_extra
;
13809 if (mips_opts
.micromips
)
13811 hash
= micromips_op_hash
;
13812 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13817 past
= &mips_opcodes
[NUMOPCODES
];
13819 forced_insn_length
= 0;
13822 /* We first try to match an instruction up to a space or to the end. */
13823 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13826 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13829 set_insn_error (0, _("unrecognized opcode"));
13833 if (strcmp (first
->name
, "li.s") == 0)
13835 else if (strcmp (first
->name
, "li.d") == 0)
13839 tokens
= mips_parse_arguments (str
+ end
, format
);
13843 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13844 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13845 set_insn_error (0, _("invalid operands"));
13847 obstack_free (&mips_operand_tokens
, tokens
);
13850 /* As for mips_ip, but used when assembling MIPS16 code.
13851 Also set forced_insn_length to the resulting instruction size in
13852 bytes if the user explicitly requested a small or extended instruction. */
13855 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13858 struct mips_opcode
*first
;
13859 struct mips_operand_token
*tokens
;
13861 forced_insn_length
= 0;
13863 for (s
= str
; ISLOWER (*s
); ++s
)
13877 if (s
[1] == 't' && s
[2] == ' ')
13879 forced_insn_length
= 2;
13883 else if (s
[1] == 'e' && s
[2] == ' ')
13885 forced_insn_length
= 4;
13889 /* Fall through. */
13891 set_insn_error (0, _("unrecognized opcode"));
13896 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13901 set_insn_error (0, _("unrecognized opcode"));
13905 tokens
= mips_parse_arguments (s
, 0);
13909 if (!match_mips16_insns (insn
, first
, tokens
))
13910 set_insn_error (0, _("invalid operands"));
13912 obstack_free (&mips_operand_tokens
, tokens
);
13915 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13916 NBITS is the number of significant bits in VAL. */
13918 static unsigned long
13919 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13924 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13927 else if (nbits
== 15)
13929 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13934 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13937 return (extval
<< 16) | val
;
13940 /* Like decode_mips16_operand, but require the operand to be defined and
13941 require it to be an integer. */
13943 static const struct mips_int_operand
*
13944 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13946 const struct mips_operand
*operand
;
13948 operand
= decode_mips16_operand (type
, extended_p
);
13949 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13951 return (const struct mips_int_operand
*) operand
;
13954 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13957 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13958 bfd_reloc_code_real_type reloc
, offsetT sval
)
13960 int min_val
, max_val
;
13962 min_val
= mips_int_operand_min (operand
);
13963 max_val
= mips_int_operand_max (operand
);
13964 if (reloc
!= BFD_RELOC_UNUSED
)
13967 sval
= SEXT_16BIT (sval
);
13972 return (sval
>= min_val
13974 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13977 /* Install immediate value VAL into MIPS16 instruction *INSN,
13978 extending it if necessary. The instruction in *INSN may
13979 already be extended.
13981 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13982 if none. In the former case, VAL is a 16-bit number with no
13983 defined signedness.
13985 TYPE is the type of the immediate field. USER_INSN_LENGTH
13986 is the length that the user requested, or 0 if none. */
13989 mips16_immed (const char *file
, unsigned int line
, int type
,
13990 bfd_reloc_code_real_type reloc
, offsetT val
,
13991 unsigned int user_insn_length
, unsigned long *insn
)
13993 const struct mips_int_operand
*operand
;
13994 unsigned int uval
, length
;
13996 operand
= mips16_immed_operand (type
, FALSE
);
13997 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13999 /* We need an extended instruction. */
14000 if (user_insn_length
== 2)
14001 as_bad_where (file
, line
, _("invalid unextended operand value"));
14003 *insn
|= MIPS16_EXTEND
;
14005 else if (user_insn_length
== 4)
14007 /* The operand doesn't force an unextended instruction to be extended.
14008 Warn if the user wanted an extended instruction anyway. */
14009 *insn
|= MIPS16_EXTEND
;
14010 as_warn_where (file
, line
,
14011 _("extended operand requested but not required"));
14014 length
= mips16_opcode_length (*insn
);
14017 operand
= mips16_immed_operand (type
, TRUE
);
14018 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14019 as_bad_where (file
, line
,
14020 _("operand value out of range for instruction"));
14022 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14024 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14026 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14029 struct percent_op_match
14032 bfd_reloc_code_real_type reloc
;
14035 static const struct percent_op_match mips_percent_op
[] =
14037 {"%lo", BFD_RELOC_LO16
},
14038 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14039 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14040 {"%call16", BFD_RELOC_MIPS_CALL16
},
14041 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14042 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14043 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14044 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14045 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14046 {"%got", BFD_RELOC_MIPS_GOT16
},
14047 {"%gp_rel", BFD_RELOC_GPREL16
},
14048 {"%half", BFD_RELOC_16
},
14049 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14050 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14051 {"%neg", BFD_RELOC_MIPS_SUB
},
14052 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14053 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14054 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14055 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14056 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14057 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14058 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14059 {"%hi", BFD_RELOC_HI16_S
},
14060 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14061 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14064 static const struct percent_op_match mips16_percent_op
[] =
14066 {"%lo", BFD_RELOC_MIPS16_LO16
},
14067 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14068 {"%got", BFD_RELOC_MIPS16_GOT16
},
14069 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14070 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14071 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14072 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14073 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14074 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14075 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14076 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14077 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14081 /* Return true if *STR points to a relocation operator. When returning true,
14082 move *STR over the operator and store its relocation code in *RELOC.
14083 Leave both *STR and *RELOC alone when returning false. */
14086 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14088 const struct percent_op_match
*percent_op
;
14091 if (mips_opts
.mips16
)
14093 percent_op
= mips16_percent_op
;
14094 limit
= ARRAY_SIZE (mips16_percent_op
);
14098 percent_op
= mips_percent_op
;
14099 limit
= ARRAY_SIZE (mips_percent_op
);
14102 for (i
= 0; i
< limit
; i
++)
14103 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14105 int len
= strlen (percent_op
[i
].str
);
14107 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14110 *str
+= strlen (percent_op
[i
].str
);
14111 *reloc
= percent_op
[i
].reloc
;
14113 /* Check whether the output BFD supports this relocation.
14114 If not, issue an error and fall back on something safe. */
14115 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14117 as_bad (_("relocation %s isn't supported by the current ABI"),
14118 percent_op
[i
].str
);
14119 *reloc
= BFD_RELOC_UNUSED
;
14127 /* Parse string STR as a 16-bit relocatable operand. Store the
14128 expression in *EP and the relocations in the array starting
14129 at RELOC. Return the number of relocation operators used.
14131 On exit, EXPR_END points to the first character after the expression. */
14134 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14137 bfd_reloc_code_real_type reversed_reloc
[3];
14138 size_t reloc_index
, i
;
14139 int crux_depth
, str_depth
;
14142 /* Search for the start of the main expression, recoding relocations
14143 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14144 of the main expression and with CRUX_DEPTH containing the number
14145 of open brackets at that point. */
14152 crux_depth
= str_depth
;
14154 /* Skip over whitespace and brackets, keeping count of the number
14156 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14161 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14162 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14164 my_getExpression (ep
, crux
);
14167 /* Match every open bracket. */
14168 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14172 if (crux_depth
> 0)
14173 as_bad (_("unclosed '('"));
14177 if (reloc_index
!= 0)
14179 prev_reloc_op_frag
= frag_now
;
14180 for (i
= 0; i
< reloc_index
; i
++)
14181 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14184 return reloc_index
;
14188 my_getExpression (expressionS
*ep
, char *str
)
14192 save_in
= input_line_pointer
;
14193 input_line_pointer
= str
;
14195 expr_end
= input_line_pointer
;
14196 input_line_pointer
= save_in
;
14200 md_atof (int type
, char *litP
, int *sizeP
)
14202 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14206 md_number_to_chars (char *buf
, valueT val
, int n
)
14208 if (target_big_endian
)
14209 number_to_chars_bigendian (buf
, val
, n
);
14211 number_to_chars_littleendian (buf
, val
, n
);
14214 static int support_64bit_objects(void)
14216 const char **list
, **l
;
14219 list
= bfd_target_list ();
14220 for (l
= list
; *l
!= NULL
; l
++)
14221 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14222 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14224 yes
= (*l
!= NULL
);
14229 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14230 NEW_VALUE. Warn if another value was already specified. Note:
14231 we have to defer parsing the -march and -mtune arguments in order
14232 to handle 'from-abi' correctly, since the ABI might be specified
14233 in a later argument. */
14236 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14238 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14239 as_warn (_("a different %s was already specified, is now %s"),
14240 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14243 *string_ptr
= new_value
;
14247 md_parse_option (int c
, const char *arg
)
14251 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14252 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14254 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14255 c
== mips_ases
[i
].option_on
);
14261 case OPTION_CONSTRUCT_FLOATS
:
14262 mips_disable_float_construction
= 0;
14265 case OPTION_NO_CONSTRUCT_FLOATS
:
14266 mips_disable_float_construction
= 1;
14278 target_big_endian
= 1;
14282 target_big_endian
= 0;
14288 else if (arg
[0] == '0')
14290 else if (arg
[0] == '1')
14300 mips_debug
= atoi (arg
);
14304 file_mips_opts
.isa
= ISA_MIPS1
;
14308 file_mips_opts
.isa
= ISA_MIPS2
;
14312 file_mips_opts
.isa
= ISA_MIPS3
;
14316 file_mips_opts
.isa
= ISA_MIPS4
;
14320 file_mips_opts
.isa
= ISA_MIPS5
;
14323 case OPTION_MIPS32
:
14324 file_mips_opts
.isa
= ISA_MIPS32
;
14327 case OPTION_MIPS32R2
:
14328 file_mips_opts
.isa
= ISA_MIPS32R2
;
14331 case OPTION_MIPS32R3
:
14332 file_mips_opts
.isa
= ISA_MIPS32R3
;
14335 case OPTION_MIPS32R5
:
14336 file_mips_opts
.isa
= ISA_MIPS32R5
;
14339 case OPTION_MIPS32R6
:
14340 file_mips_opts
.isa
= ISA_MIPS32R6
;
14343 case OPTION_MIPS64R2
:
14344 file_mips_opts
.isa
= ISA_MIPS64R2
;
14347 case OPTION_MIPS64R3
:
14348 file_mips_opts
.isa
= ISA_MIPS64R3
;
14351 case OPTION_MIPS64R5
:
14352 file_mips_opts
.isa
= ISA_MIPS64R5
;
14355 case OPTION_MIPS64R6
:
14356 file_mips_opts
.isa
= ISA_MIPS64R6
;
14359 case OPTION_MIPS64
:
14360 file_mips_opts
.isa
= ISA_MIPS64
;
14364 mips_set_option_string (&mips_tune_string
, arg
);
14368 mips_set_option_string (&mips_arch_string
, arg
);
14372 mips_set_option_string (&mips_arch_string
, "4650");
14373 mips_set_option_string (&mips_tune_string
, "4650");
14376 case OPTION_NO_M4650
:
14380 mips_set_option_string (&mips_arch_string
, "4010");
14381 mips_set_option_string (&mips_tune_string
, "4010");
14384 case OPTION_NO_M4010
:
14388 mips_set_option_string (&mips_arch_string
, "4100");
14389 mips_set_option_string (&mips_tune_string
, "4100");
14392 case OPTION_NO_M4100
:
14396 mips_set_option_string (&mips_arch_string
, "3900");
14397 mips_set_option_string (&mips_tune_string
, "3900");
14400 case OPTION_NO_M3900
:
14403 case OPTION_MICROMIPS
:
14404 if (file_mips_opts
.mips16
== 1)
14406 as_bad (_("-mmicromips cannot be used with -mips16"));
14409 file_mips_opts
.micromips
= 1;
14410 mips_no_prev_insn ();
14413 case OPTION_NO_MICROMIPS
:
14414 file_mips_opts
.micromips
= 0;
14415 mips_no_prev_insn ();
14418 case OPTION_MIPS16
:
14419 if (file_mips_opts
.micromips
== 1)
14421 as_bad (_("-mips16 cannot be used with -micromips"));
14424 file_mips_opts
.mips16
= 1;
14425 mips_no_prev_insn ();
14428 case OPTION_NO_MIPS16
:
14429 file_mips_opts
.mips16
= 0;
14430 mips_no_prev_insn ();
14433 case OPTION_FIX_24K
:
14437 case OPTION_NO_FIX_24K
:
14441 case OPTION_FIX_RM7000
:
14442 mips_fix_rm7000
= 1;
14445 case OPTION_NO_FIX_RM7000
:
14446 mips_fix_rm7000
= 0;
14449 case OPTION_FIX_LOONGSON2F_JUMP
:
14450 mips_fix_loongson2f_jump
= TRUE
;
14453 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14454 mips_fix_loongson2f_jump
= FALSE
;
14457 case OPTION_FIX_LOONGSON2F_NOP
:
14458 mips_fix_loongson2f_nop
= TRUE
;
14461 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14462 mips_fix_loongson2f_nop
= FALSE
;
14465 case OPTION_FIX_VR4120
:
14466 mips_fix_vr4120
= 1;
14469 case OPTION_NO_FIX_VR4120
:
14470 mips_fix_vr4120
= 0;
14473 case OPTION_FIX_VR4130
:
14474 mips_fix_vr4130
= 1;
14477 case OPTION_NO_FIX_VR4130
:
14478 mips_fix_vr4130
= 0;
14481 case OPTION_FIX_CN63XXP1
:
14482 mips_fix_cn63xxp1
= TRUE
;
14485 case OPTION_NO_FIX_CN63XXP1
:
14486 mips_fix_cn63xxp1
= FALSE
;
14489 case OPTION_RELAX_BRANCH
:
14490 mips_relax_branch
= 1;
14493 case OPTION_NO_RELAX_BRANCH
:
14494 mips_relax_branch
= 0;
14497 case OPTION_INSN32
:
14498 file_mips_opts
.insn32
= TRUE
;
14501 case OPTION_NO_INSN32
:
14502 file_mips_opts
.insn32
= FALSE
;
14505 case OPTION_MSHARED
:
14506 mips_in_shared
= TRUE
;
14509 case OPTION_MNO_SHARED
:
14510 mips_in_shared
= FALSE
;
14513 case OPTION_MSYM32
:
14514 file_mips_opts
.sym32
= TRUE
;
14517 case OPTION_MNO_SYM32
:
14518 file_mips_opts
.sym32
= FALSE
;
14521 /* When generating ELF code, we permit -KPIC and -call_shared to
14522 select SVR4_PIC, and -non_shared to select no PIC. This is
14523 intended to be compatible with Irix 5. */
14524 case OPTION_CALL_SHARED
:
14525 mips_pic
= SVR4_PIC
;
14526 mips_abicalls
= TRUE
;
14529 case OPTION_CALL_NONPIC
:
14531 mips_abicalls
= TRUE
;
14534 case OPTION_NON_SHARED
:
14536 mips_abicalls
= FALSE
;
14539 /* The -xgot option tells the assembler to use 32 bit offsets
14540 when accessing the got in SVR4_PIC mode. It is for Irix
14547 g_switch_value
= atoi (arg
);
14551 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14554 mips_abi
= O32_ABI
;
14558 mips_abi
= N32_ABI
;
14562 mips_abi
= N64_ABI
;
14563 if (!support_64bit_objects())
14564 as_fatal (_("no compiled in support for 64 bit object file format"));
14568 file_mips_opts
.gp
= 32;
14572 file_mips_opts
.gp
= 64;
14576 file_mips_opts
.fp
= 32;
14580 file_mips_opts
.fp
= 0;
14584 file_mips_opts
.fp
= 64;
14587 case OPTION_ODD_SPREG
:
14588 file_mips_opts
.oddspreg
= 1;
14591 case OPTION_NO_ODD_SPREG
:
14592 file_mips_opts
.oddspreg
= 0;
14595 case OPTION_SINGLE_FLOAT
:
14596 file_mips_opts
.single_float
= 1;
14599 case OPTION_DOUBLE_FLOAT
:
14600 file_mips_opts
.single_float
= 0;
14603 case OPTION_SOFT_FLOAT
:
14604 file_mips_opts
.soft_float
= 1;
14607 case OPTION_HARD_FLOAT
:
14608 file_mips_opts
.soft_float
= 0;
14612 if (strcmp (arg
, "32") == 0)
14613 mips_abi
= O32_ABI
;
14614 else if (strcmp (arg
, "o64") == 0)
14615 mips_abi
= O64_ABI
;
14616 else if (strcmp (arg
, "n32") == 0)
14617 mips_abi
= N32_ABI
;
14618 else if (strcmp (arg
, "64") == 0)
14620 mips_abi
= N64_ABI
;
14621 if (! support_64bit_objects())
14622 as_fatal (_("no compiled in support for 64 bit object file "
14625 else if (strcmp (arg
, "eabi") == 0)
14626 mips_abi
= EABI_ABI
;
14629 as_fatal (_("invalid abi -mabi=%s"), arg
);
14634 case OPTION_M7000_HILO_FIX
:
14635 mips_7000_hilo_fix
= TRUE
;
14638 case OPTION_MNO_7000_HILO_FIX
:
14639 mips_7000_hilo_fix
= FALSE
;
14642 case OPTION_MDEBUG
:
14643 mips_flag_mdebug
= TRUE
;
14646 case OPTION_NO_MDEBUG
:
14647 mips_flag_mdebug
= FALSE
;
14651 mips_flag_pdr
= TRUE
;
14654 case OPTION_NO_PDR
:
14655 mips_flag_pdr
= FALSE
;
14658 case OPTION_MVXWORKS_PIC
:
14659 mips_pic
= VXWORKS_PIC
;
14663 if (strcmp (arg
, "2008") == 0)
14665 else if (strcmp (arg
, "legacy") == 0)
14669 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14678 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14683 /* Set up globals to tune for the ISA or processor described by INFO. */
14686 mips_set_tune (const struct mips_cpu_info
*info
)
14689 mips_tune
= info
->cpu
;
14694 mips_after_parse_args (void)
14696 const struct mips_cpu_info
*arch_info
= 0;
14697 const struct mips_cpu_info
*tune_info
= 0;
14699 /* GP relative stuff not working for PE */
14700 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14702 if (g_switch_seen
&& g_switch_value
!= 0)
14703 as_bad (_("-G not supported in this configuration"));
14704 g_switch_value
= 0;
14707 if (mips_abi
== NO_ABI
)
14708 mips_abi
= MIPS_DEFAULT_ABI
;
14710 /* The following code determines the architecture.
14711 Similar code was added to GCC 3.3 (see override_options() in
14712 config/mips/mips.c). The GAS and GCC code should be kept in sync
14713 as much as possible. */
14715 if (mips_arch_string
!= 0)
14716 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14718 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14720 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14721 ISA level specified by -mipsN, while arch_info->isa contains
14722 the -march selection (if any). */
14723 if (arch_info
!= 0)
14725 /* -march takes precedence over -mipsN, since it is more descriptive.
14726 There's no harm in specifying both as long as the ISA levels
14728 if (file_mips_opts
.isa
!= arch_info
->isa
)
14729 as_bad (_("-%s conflicts with the other architecture options,"
14730 " which imply -%s"),
14731 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14732 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14735 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14738 if (arch_info
== 0)
14740 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14741 gas_assert (arch_info
);
14744 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14745 as_bad (_("-march=%s is not compatible with the selected ABI"),
14748 file_mips_opts
.arch
= arch_info
->cpu
;
14749 file_mips_opts
.isa
= arch_info
->isa
;
14751 /* Set up initial mips_opts state. */
14752 mips_opts
= file_mips_opts
;
14754 /* The register size inference code is now placed in
14755 file_mips_check_options. */
14757 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14759 if (mips_tune_string
!= 0)
14760 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14762 if (tune_info
== 0)
14763 mips_set_tune (arch_info
);
14765 mips_set_tune (tune_info
);
14767 if (mips_flag_mdebug
< 0)
14768 mips_flag_mdebug
= 0;
14772 mips_init_after_args (void)
14774 /* initialize opcodes */
14775 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14776 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14780 md_pcrel_from (fixS
*fixP
)
14782 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14783 switch (fixP
->fx_r_type
)
14785 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14786 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14787 /* Return the address of the delay slot. */
14790 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14791 case BFD_RELOC_MICROMIPS_JMP
:
14792 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14793 case BFD_RELOC_16_PCREL_S2
:
14794 case BFD_RELOC_MIPS_21_PCREL_S2
:
14795 case BFD_RELOC_MIPS_26_PCREL_S2
:
14796 case BFD_RELOC_MIPS_JMP
:
14797 /* Return the address of the delay slot. */
14800 case BFD_RELOC_MIPS_18_PCREL_S3
:
14801 /* Return the aligned address of the doubleword containing
14802 the instruction. */
14810 /* This is called before the symbol table is processed. In order to
14811 work with gcc when using mips-tfile, we must keep all local labels.
14812 However, in other cases, we want to discard them. If we were
14813 called with -g, but we didn't see any debugging information, it may
14814 mean that gcc is smuggling debugging information through to
14815 mips-tfile, in which case we must generate all local labels. */
14818 mips_frob_file_before_adjust (void)
14820 #ifndef NO_ECOFF_DEBUGGING
14821 if (ECOFF_DEBUGGING
14823 && ! ecoff_debugging_seen
)
14824 flag_keep_locals
= 1;
14828 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14829 the corresponding LO16 reloc. This is called before md_apply_fix and
14830 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14831 relocation operators.
14833 For our purposes, a %lo() expression matches a %got() or %hi()
14836 (a) it refers to the same symbol; and
14837 (b) the offset applied in the %lo() expression is no lower than
14838 the offset applied in the %got() or %hi().
14840 (b) allows us to cope with code like:
14843 lh $4,%lo(foo+2)($4)
14845 ...which is legal on RELA targets, and has a well-defined behaviour
14846 if the user knows that adding 2 to "foo" will not induce a carry to
14849 When several %lo()s match a particular %got() or %hi(), we use the
14850 following rules to distinguish them:
14852 (1) %lo()s with smaller offsets are a better match than %lo()s with
14855 (2) %lo()s with no matching %got() or %hi() are better than those
14856 that already have a matching %got() or %hi().
14858 (3) later %lo()s are better than earlier %lo()s.
14860 These rules are applied in order.
14862 (1) means, among other things, that %lo()s with identical offsets are
14863 chosen if they exist.
14865 (2) means that we won't associate several high-part relocations with
14866 the same low-part relocation unless there's no alternative. Having
14867 several high parts for the same low part is a GNU extension; this rule
14868 allows careful users to avoid it.
14870 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14871 with the last high-part relocation being at the front of the list.
14872 It therefore makes sense to choose the last matching low-part
14873 relocation, all other things being equal. It's also easier
14874 to code that way. */
14877 mips_frob_file (void)
14879 struct mips_hi_fixup
*l
;
14880 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14882 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14884 segment_info_type
*seginfo
;
14885 bfd_boolean matched_lo_p
;
14886 fixS
**hi_pos
, **lo_pos
, **pos
;
14888 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14890 /* If a GOT16 relocation turns out to be against a global symbol,
14891 there isn't supposed to be a matching LO. Ignore %gots against
14892 constants; we'll report an error for those later. */
14893 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14894 && !(l
->fixp
->fx_addsy
14895 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14898 /* Check quickly whether the next fixup happens to be a matching %lo. */
14899 if (fixup_has_matching_lo_p (l
->fixp
))
14902 seginfo
= seg_info (l
->seg
);
14904 /* Set HI_POS to the position of this relocation in the chain.
14905 Set LO_POS to the position of the chosen low-part relocation.
14906 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14907 relocation that matches an immediately-preceding high-part
14911 matched_lo_p
= FALSE
;
14912 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14914 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14916 if (*pos
== l
->fixp
)
14919 if ((*pos
)->fx_r_type
== looking_for_rtype
14920 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14921 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14923 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14925 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14928 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14929 && fixup_has_matching_lo_p (*pos
));
14932 /* If we found a match, remove the high-part relocation from its
14933 current position and insert it before the low-part relocation.
14934 Make the offsets match so that fixup_has_matching_lo_p()
14937 We don't warn about unmatched high-part relocations since some
14938 versions of gcc have been known to emit dead "lui ...%hi(...)"
14940 if (lo_pos
!= NULL
)
14942 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14943 if (l
->fixp
->fx_next
!= *lo_pos
)
14945 *hi_pos
= l
->fixp
->fx_next
;
14946 l
->fixp
->fx_next
= *lo_pos
;
14954 mips_force_relocation (fixS
*fixp
)
14956 if (generic_force_reloc (fixp
))
14959 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14960 so that the linker relaxation can update targets. */
14961 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14962 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14963 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14966 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
14967 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
14968 microMIPS symbols so that we can do cross-mode branch diagnostics
14969 and BAL to JALX conversion by the linker. */
14970 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14971 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14972 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
14974 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
14977 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14978 if (ISA_IS_R6 (file_mips_opts
.isa
)
14979 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14980 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14981 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
14982 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
14983 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
14984 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
14985 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
14991 /* Implement TC_FORCE_RELOCATION_ABS. */
14994 mips_force_relocation_abs (fixS
*fixp
)
14996 if (generic_force_reloc (fixp
))
14999 /* These relocations do not have enough bits in the in-place addend
15000 to hold an arbitrary absolute section's offset. */
15001 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15007 /* Read the instruction associated with RELOC from BUF. */
15009 static unsigned int
15010 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15012 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15013 return read_compressed_insn (buf
, 4);
15015 return read_insn (buf
);
15018 /* Write instruction INSN to BUF, given that it has been relocated
15022 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15023 unsigned long insn
)
15025 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15026 write_compressed_insn (buf
, insn
, 4);
15028 write_insn (buf
, insn
);
15031 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15032 to a symbol in another ISA mode, which cannot be converted to JALX. */
15035 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15037 unsigned long opcode
;
15041 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15044 other
= S_GET_OTHER (fixP
->fx_addsy
);
15045 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15046 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15047 switch (fixP
->fx_r_type
)
15049 case BFD_RELOC_MIPS_JMP
:
15050 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15051 case BFD_RELOC_MICROMIPS_JMP
:
15052 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15058 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15059 jump to a symbol in the same ISA mode. */
15062 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15064 unsigned long opcode
;
15068 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15071 other
= S_GET_OTHER (fixP
->fx_addsy
);
15072 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15073 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15074 switch (fixP
->fx_r_type
)
15076 case BFD_RELOC_MIPS_JMP
:
15077 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15078 case BFD_RELOC_MIPS16_JMP
:
15079 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15080 case BFD_RELOC_MICROMIPS_JMP
:
15081 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15087 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15088 to a symbol whose value plus addend is not aligned according to the
15089 ultimate (after linker relaxation) jump instruction's immediate field
15090 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15091 regular MIPS code, to (1 << 2). */
15094 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15096 bfd_boolean micro_to_mips_p
;
15100 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15103 other
= S_GET_OTHER (fixP
->fx_addsy
);
15104 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15105 val
+= fixP
->fx_offset
;
15106 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15107 && !ELF_ST_IS_MICROMIPS (other
));
15108 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15109 != ELF_ST_IS_COMPRESSED (other
));
15112 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15113 to a symbol whose annotation indicates another ISA mode. For absolute
15114 symbols check the ISA bit instead.
15116 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15117 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15118 MIPS symbols and associated with BAL instructions as these instructions
15119 may be be converted to JALX by the linker. */
15122 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15124 bfd_boolean absolute_p
;
15125 unsigned long opcode
;
15131 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15134 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15135 absolute_p
= bfd_is_abs_section (symsec
);
15137 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15138 other
= S_GET_OTHER (fixP
->fx_addsy
);
15140 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15141 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15142 switch (fixP
->fx_r_type
)
15144 case BFD_RELOC_16_PCREL_S2
:
15145 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15146 && opcode
!= 0x0411);
15147 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15148 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15149 && opcode
!= 0x4060);
15150 case BFD_RELOC_MIPS_21_PCREL_S2
:
15151 case BFD_RELOC_MIPS_26_PCREL_S2
:
15152 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15153 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15154 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15155 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15156 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15157 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15163 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15164 branch instruction pointed to by FIXP is not aligned according to the
15165 branch instruction's immediate field requirement. We need the addend
15166 to preserve the ISA bit and also the sum must not have bit 2 set. We
15167 must explicitly OR in the ISA bit from symbol annotation as the bit
15168 won't be set in the symbol's value then. */
15171 fix_bad_misaligned_branch_p (fixS
*fixP
)
15173 bfd_boolean absolute_p
;
15180 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15183 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15184 absolute_p
= bfd_is_abs_section (symsec
);
15186 val
= S_GET_VALUE (fixP
->fx_addsy
);
15187 other
= S_GET_OTHER (fixP
->fx_addsy
);
15188 off
= fixP
->fx_offset
;
15190 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15191 val
|= ELF_ST_IS_COMPRESSED (other
);
15193 return (val
& 0x3) != isa_bit
;
15196 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15197 and its calculated value VAL. */
15200 fix_validate_branch (fixS
*fixP
, valueT val
)
15202 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15204 _("branch to misaligned address (0x%lx)"),
15205 (long) (val
+ md_pcrel_from (fixP
)));
15206 else if (fix_bad_cross_mode_branch_p (fixP
))
15207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15208 _("branch to a symbol in another ISA mode"));
15209 else if (fix_bad_misaligned_branch_p (fixP
))
15210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15211 _("branch to misaligned address (0x%lx)"),
15212 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15213 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15215 _("cannot encode misaligned addend "
15216 "in the relocatable field (0x%lx)"),
15217 (long) fixP
->fx_offset
);
15220 /* Apply a fixup to the object file. */
15223 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15226 unsigned long insn
;
15227 reloc_howto_type
*howto
;
15229 if (fixP
->fx_pcrel
)
15230 switch (fixP
->fx_r_type
)
15232 case BFD_RELOC_16_PCREL_S2
:
15233 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15234 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15235 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15236 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15237 case BFD_RELOC_32_PCREL
:
15238 case BFD_RELOC_MIPS_21_PCREL_S2
:
15239 case BFD_RELOC_MIPS_26_PCREL_S2
:
15240 case BFD_RELOC_MIPS_18_PCREL_S3
:
15241 case BFD_RELOC_MIPS_19_PCREL_S2
:
15242 case BFD_RELOC_HI16_S_PCREL
:
15243 case BFD_RELOC_LO16_PCREL
:
15247 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15252 _("PC-relative reference to a different section"));
15256 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15257 that have no MIPS ELF equivalent. */
15258 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15260 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15265 gas_assert (fixP
->fx_size
== 2
15266 || fixP
->fx_size
== 4
15267 || fixP
->fx_r_type
== BFD_RELOC_8
15268 || fixP
->fx_r_type
== BFD_RELOC_16
15269 || fixP
->fx_r_type
== BFD_RELOC_64
15270 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15271 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15272 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15273 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15274 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15275 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15276 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15278 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15280 /* Don't treat parts of a composite relocation as done. There are two
15283 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15284 should nevertheless be emitted if the first part is.
15286 (2) In normal usage, composite relocations are never assembly-time
15287 constants. The easiest way of dealing with the pathological
15288 exceptions is to generate a relocation against STN_UNDEF and
15289 leave everything up to the linker. */
15290 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15293 switch (fixP
->fx_r_type
)
15295 case BFD_RELOC_MIPS_TLS_GD
:
15296 case BFD_RELOC_MIPS_TLS_LDM
:
15297 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15298 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15299 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15300 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15301 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15302 case BFD_RELOC_MIPS_TLS_TPREL32
:
15303 case BFD_RELOC_MIPS_TLS_TPREL64
:
15304 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15305 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15306 case BFD_RELOC_MICROMIPS_TLS_GD
:
15307 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15308 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15309 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15310 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15311 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15312 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15313 case BFD_RELOC_MIPS16_TLS_GD
:
15314 case BFD_RELOC_MIPS16_TLS_LDM
:
15315 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15316 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15317 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15318 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15319 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15320 if (fixP
->fx_addsy
)
15321 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15324 _("TLS relocation against a constant"));
15327 case BFD_RELOC_MIPS_JMP
:
15328 case BFD_RELOC_MIPS16_JMP
:
15329 case BFD_RELOC_MICROMIPS_JMP
:
15333 gas_assert (!fixP
->fx_done
);
15335 /* Shift is 2, unusually, for microMIPS JALX. */
15336 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15337 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15342 if (fix_bad_cross_mode_jump_p (fixP
))
15343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15344 _("jump to a symbol in another ISA mode"));
15345 else if (fix_bad_same_mode_jalx_p (fixP
))
15346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15347 _("JALX to a symbol in the same ISA mode"));
15348 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15350 _("jump to misaligned address (0x%lx)"),
15351 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15352 + fixP
->fx_offset
));
15353 else if (HAVE_IN_PLACE_ADDENDS
15354 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15356 _("cannot encode misaligned addend "
15357 "in the relocatable field (0x%lx)"),
15358 (long) fixP
->fx_offset
);
15360 /* Fall through. */
15362 case BFD_RELOC_MIPS_SHIFT5
:
15363 case BFD_RELOC_MIPS_SHIFT6
:
15364 case BFD_RELOC_MIPS_GOT_DISP
:
15365 case BFD_RELOC_MIPS_GOT_PAGE
:
15366 case BFD_RELOC_MIPS_GOT_OFST
:
15367 case BFD_RELOC_MIPS_SUB
:
15368 case BFD_RELOC_MIPS_INSERT_A
:
15369 case BFD_RELOC_MIPS_INSERT_B
:
15370 case BFD_RELOC_MIPS_DELETE
:
15371 case BFD_RELOC_MIPS_HIGHEST
:
15372 case BFD_RELOC_MIPS_HIGHER
:
15373 case BFD_RELOC_MIPS_SCN_DISP
:
15374 case BFD_RELOC_MIPS_REL16
:
15375 case BFD_RELOC_MIPS_RELGOT
:
15376 case BFD_RELOC_MIPS_JALR
:
15377 case BFD_RELOC_HI16
:
15378 case BFD_RELOC_HI16_S
:
15379 case BFD_RELOC_LO16
:
15380 case BFD_RELOC_GPREL16
:
15381 case BFD_RELOC_MIPS_LITERAL
:
15382 case BFD_RELOC_MIPS_CALL16
:
15383 case BFD_RELOC_MIPS_GOT16
:
15384 case BFD_RELOC_GPREL32
:
15385 case BFD_RELOC_MIPS_GOT_HI16
:
15386 case BFD_RELOC_MIPS_GOT_LO16
:
15387 case BFD_RELOC_MIPS_CALL_HI16
:
15388 case BFD_RELOC_MIPS_CALL_LO16
:
15389 case BFD_RELOC_HI16_S_PCREL
:
15390 case BFD_RELOC_LO16_PCREL
:
15391 case BFD_RELOC_MIPS16_GPREL
:
15392 case BFD_RELOC_MIPS16_GOT16
:
15393 case BFD_RELOC_MIPS16_CALL16
:
15394 case BFD_RELOC_MIPS16_HI16
:
15395 case BFD_RELOC_MIPS16_HI16_S
:
15396 case BFD_RELOC_MIPS16_LO16
:
15397 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15398 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15399 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15400 case BFD_RELOC_MICROMIPS_SUB
:
15401 case BFD_RELOC_MICROMIPS_HIGHEST
:
15402 case BFD_RELOC_MICROMIPS_HIGHER
:
15403 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15404 case BFD_RELOC_MICROMIPS_JALR
:
15405 case BFD_RELOC_MICROMIPS_HI16
:
15406 case BFD_RELOC_MICROMIPS_HI16_S
:
15407 case BFD_RELOC_MICROMIPS_LO16
:
15408 case BFD_RELOC_MICROMIPS_GPREL16
:
15409 case BFD_RELOC_MICROMIPS_LITERAL
:
15410 case BFD_RELOC_MICROMIPS_CALL16
:
15411 case BFD_RELOC_MICROMIPS_GOT16
:
15412 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15413 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15414 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15415 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15416 case BFD_RELOC_MIPS_EH
:
15421 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15423 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15424 if (mips16_reloc_p (fixP
->fx_r_type
))
15425 insn
|= mips16_immed_extend (value
, 16);
15427 insn
|= (value
& 0xffff);
15428 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15432 _("unsupported constant in relocation"));
15437 /* This is handled like BFD_RELOC_32, but we output a sign
15438 extended value if we are only 32 bits. */
15441 if (8 <= sizeof (valueT
))
15442 md_number_to_chars (buf
, *valP
, 8);
15447 if ((*valP
& 0x80000000) != 0)
15451 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15452 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15457 case BFD_RELOC_RVA
:
15459 case BFD_RELOC_32_PCREL
:
15462 /* If we are deleting this reloc entry, we must fill in the
15463 value now. This can happen if we have a .word which is not
15464 resolved when it appears but is later defined. */
15466 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15469 case BFD_RELOC_MIPS_21_PCREL_S2
:
15470 fix_validate_branch (fixP
, *valP
);
15471 if (!fixP
->fx_done
)
15474 if (*valP
+ 0x400000 <= 0x7fffff)
15476 insn
= read_insn (buf
);
15477 insn
|= (*valP
>> 2) & 0x1fffff;
15478 write_insn (buf
, insn
);
15481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15482 _("branch out of range"));
15485 case BFD_RELOC_MIPS_26_PCREL_S2
:
15486 fix_validate_branch (fixP
, *valP
);
15487 if (!fixP
->fx_done
)
15490 if (*valP
+ 0x8000000 <= 0xfffffff)
15492 insn
= read_insn (buf
);
15493 insn
|= (*valP
>> 2) & 0x3ffffff;
15494 write_insn (buf
, insn
);
15497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15498 _("branch out of range"));
15501 case BFD_RELOC_MIPS_18_PCREL_S3
:
15502 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15504 _("PC-relative access using misaligned symbol (%lx)"),
15505 (long) S_GET_VALUE (fixP
->fx_addsy
));
15506 if ((fixP
->fx_offset
& 0x7) != 0)
15507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15508 _("PC-relative access using misaligned offset (%lx)"),
15509 (long) fixP
->fx_offset
);
15510 if (!fixP
->fx_done
)
15513 if (*valP
+ 0x100000 <= 0x1fffff)
15515 insn
= read_insn (buf
);
15516 insn
|= (*valP
>> 3) & 0x3ffff;
15517 write_insn (buf
, insn
);
15520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15521 _("PC-relative access out of range"));
15524 case BFD_RELOC_MIPS_19_PCREL_S2
:
15525 if ((*valP
& 0x3) != 0)
15526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15527 _("PC-relative access to misaligned address (%lx)"),
15529 if (!fixP
->fx_done
)
15532 if (*valP
+ 0x100000 <= 0x1fffff)
15534 insn
= read_insn (buf
);
15535 insn
|= (*valP
>> 2) & 0x7ffff;
15536 write_insn (buf
, insn
);
15539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15540 _("PC-relative access out of range"));
15543 case BFD_RELOC_16_PCREL_S2
:
15544 fix_validate_branch (fixP
, *valP
);
15546 /* We need to save the bits in the instruction since fixup_segment()
15547 might be deleting the relocation entry (i.e., a branch within
15548 the current segment). */
15549 if (! fixP
->fx_done
)
15552 /* Update old instruction data. */
15553 insn
= read_insn (buf
);
15555 if (*valP
+ 0x20000 <= 0x3ffff)
15557 insn
|= (*valP
>> 2) & 0xffff;
15558 write_insn (buf
, insn
);
15560 else if (mips_pic
== NO_PIC
15562 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15563 && (fixP
->fx_frag
->fr_address
15564 < text_section
->vma
+ bfd_get_section_size (text_section
))
15565 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15566 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15567 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15569 /* The branch offset is too large. If this is an
15570 unconditional branch, and we are not generating PIC code,
15571 we can convert it to an absolute jump instruction. */
15572 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15573 insn
= 0x0c000000; /* jal */
15575 insn
= 0x08000000; /* j */
15576 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15578 fixP
->fx_addsy
= section_symbol (text_section
);
15579 *valP
+= md_pcrel_from (fixP
);
15580 write_insn (buf
, insn
);
15584 /* If we got here, we have branch-relaxation disabled,
15585 and there's nothing we can do to fix this instruction
15586 without turning it into a longer sequence. */
15587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15588 _("branch out of range"));
15592 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15593 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15594 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15595 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15596 gas_assert (!fixP
->fx_done
);
15597 if (fix_bad_cross_mode_branch_p (fixP
))
15598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15599 _("branch to a symbol in another ISA mode"));
15600 else if (fixP
->fx_addsy
15601 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15602 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15603 && (fixP
->fx_offset
& 0x1) != 0)
15604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15605 _("branch to misaligned address (0x%lx)"),
15606 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15607 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15609 _("cannot encode misaligned addend "
15610 "in the relocatable field (0x%lx)"),
15611 (long) fixP
->fx_offset
);
15614 case BFD_RELOC_VTABLE_INHERIT
:
15617 && !S_IS_DEFINED (fixP
->fx_addsy
)
15618 && !S_IS_WEAK (fixP
->fx_addsy
))
15619 S_SET_WEAK (fixP
->fx_addsy
);
15622 case BFD_RELOC_NONE
:
15623 case BFD_RELOC_VTABLE_ENTRY
:
15631 /* Remember value for tc_gen_reloc. */
15632 fixP
->fx_addnumber
= *valP
;
15642 c
= get_symbol_name (&name
);
15643 p
= (symbolS
*) symbol_find_or_make (name
);
15644 (void) restore_line_pointer (c
);
15648 /* Align the current frag to a given power of two. If a particular
15649 fill byte should be used, FILL points to an integer that contains
15650 that byte, otherwise FILL is null.
15652 This function used to have the comment:
15654 The MIPS assembler also automatically adjusts any preceding label.
15656 The implementation therefore applied the adjustment to a maximum of
15657 one label. However, other label adjustments are applied to batches
15658 of labels, and adjusting just one caused problems when new labels
15659 were added for the sake of debugging or unwind information.
15660 We therefore adjust all preceding labels (given as LABELS) instead. */
15663 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15665 mips_emit_delays ();
15666 mips_record_compressed_mode ();
15667 if (fill
== NULL
&& subseg_text_p (now_seg
))
15668 frag_align_code (to
, 0);
15670 frag_align (to
, fill
? *fill
: 0, 0);
15671 record_alignment (now_seg
, to
);
15672 mips_move_labels (labels
, FALSE
);
15675 /* Align to a given power of two. .align 0 turns off the automatic
15676 alignment used by the data creating pseudo-ops. */
15679 s_align (int x ATTRIBUTE_UNUSED
)
15681 int temp
, fill_value
, *fill_ptr
;
15682 long max_alignment
= 28;
15684 /* o Note that the assembler pulls down any immediately preceding label
15685 to the aligned address.
15686 o It's not documented but auto alignment is reinstated by
15687 a .align pseudo instruction.
15688 o Note also that after auto alignment is turned off the mips assembler
15689 issues an error on attempt to assemble an improperly aligned data item.
15692 temp
= get_absolute_expression ();
15693 if (temp
> max_alignment
)
15694 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15697 as_warn (_("alignment negative, 0 assumed"));
15700 if (*input_line_pointer
== ',')
15702 ++input_line_pointer
;
15703 fill_value
= get_absolute_expression ();
15704 fill_ptr
= &fill_value
;
15710 segment_info_type
*si
= seg_info (now_seg
);
15711 struct insn_label_list
*l
= si
->label_list
;
15712 /* Auto alignment should be switched on by next section change. */
15714 mips_align (temp
, fill_ptr
, l
);
15721 demand_empty_rest_of_line ();
15725 s_change_sec (int sec
)
15729 /* The ELF backend needs to know that we are changing sections, so
15730 that .previous works correctly. We could do something like check
15731 for an obj_section_change_hook macro, but that might be confusing
15732 as it would not be appropriate to use it in the section changing
15733 functions in read.c, since obj-elf.c intercepts those. FIXME:
15734 This should be cleaner, somehow. */
15735 obj_elf_section_change_hook ();
15737 mips_emit_delays ();
15748 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15749 demand_empty_rest_of_line ();
15753 seg
= subseg_new (RDATA_SECTION_NAME
,
15754 (subsegT
) get_absolute_expression ());
15755 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15756 | SEC_READONLY
| SEC_RELOC
15758 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15759 record_alignment (seg
, 4);
15760 demand_empty_rest_of_line ();
15764 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15765 bfd_set_section_flags (stdoutput
, seg
,
15766 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15767 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15768 record_alignment (seg
, 4);
15769 demand_empty_rest_of_line ();
15773 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15774 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15775 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15776 record_alignment (seg
, 4);
15777 demand_empty_rest_of_line ();
15785 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15788 char *section_name
;
15793 int section_entry_size
;
15794 int section_alignment
;
15796 saved_ilp
= input_line_pointer
;
15797 endc
= get_symbol_name (§ion_name
);
15798 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15800 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15802 /* Do we have .section Name<,"flags">? */
15803 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15805 /* Just after name is now '\0'. */
15806 (void) restore_line_pointer (endc
);
15807 input_line_pointer
= saved_ilp
;
15808 obj_elf_section (ignore
);
15812 section_name
= xstrdup (section_name
);
15813 c
= restore_line_pointer (endc
);
15815 input_line_pointer
++;
15817 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15819 section_type
= get_absolute_expression ();
15823 if (*input_line_pointer
++ == ',')
15824 section_flag
= get_absolute_expression ();
15828 if (*input_line_pointer
++ == ',')
15829 section_entry_size
= get_absolute_expression ();
15831 section_entry_size
= 0;
15833 if (*input_line_pointer
++ == ',')
15834 section_alignment
= get_absolute_expression ();
15836 section_alignment
= 0;
15838 /* FIXME: really ignore? */
15839 (void) section_alignment
;
15841 /* When using the generic form of .section (as implemented by obj-elf.c),
15842 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15843 traditionally had to fall back on the more common @progbits instead.
15845 There's nothing really harmful in this, since bfd will correct
15846 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15847 means that, for backwards compatibility, the special_section entries
15848 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15850 Even so, we shouldn't force users of the MIPS .section syntax to
15851 incorrectly label the sections as SHT_PROGBITS. The best compromise
15852 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15853 generic type-checking code. */
15854 if (section_type
== SHT_MIPS_DWARF
)
15855 section_type
= SHT_PROGBITS
;
15857 obj_elf_change_section (section_name
, section_type
, section_flag
,
15858 section_entry_size
, 0, 0, 0);
15860 if (now_seg
->name
!= section_name
)
15861 free (section_name
);
15865 mips_enable_auto_align (void)
15871 s_cons (int log_size
)
15873 segment_info_type
*si
= seg_info (now_seg
);
15874 struct insn_label_list
*l
= si
->label_list
;
15876 mips_emit_delays ();
15877 if (log_size
> 0 && auto_align
)
15878 mips_align (log_size
, 0, l
);
15879 cons (1 << log_size
);
15880 mips_clear_insn_labels ();
15884 s_float_cons (int type
)
15886 segment_info_type
*si
= seg_info (now_seg
);
15887 struct insn_label_list
*l
= si
->label_list
;
15889 mips_emit_delays ();
15894 mips_align (3, 0, l
);
15896 mips_align (2, 0, l
);
15900 mips_clear_insn_labels ();
15903 /* Handle .globl. We need to override it because on Irix 5 you are
15906 where foo is an undefined symbol, to mean that foo should be
15907 considered to be the address of a function. */
15910 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15919 c
= get_symbol_name (&name
);
15920 symbolP
= symbol_find_or_make (name
);
15921 S_SET_EXTERNAL (symbolP
);
15923 *input_line_pointer
= c
;
15924 SKIP_WHITESPACE_AFTER_NAME ();
15926 /* On Irix 5, every global symbol that is not explicitly labelled as
15927 being a function is apparently labelled as being an object. */
15930 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15931 && (*input_line_pointer
!= ','))
15936 c
= get_symbol_name (&secname
);
15937 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15939 as_bad (_("%s: no such section"), secname
);
15940 (void) restore_line_pointer (c
);
15942 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15943 flag
= BSF_FUNCTION
;
15946 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15948 c
= *input_line_pointer
;
15951 input_line_pointer
++;
15952 SKIP_WHITESPACE ();
15953 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15959 demand_empty_rest_of_line ();
15963 s_option (int x ATTRIBUTE_UNUSED
)
15968 c
= get_symbol_name (&opt
);
15972 /* FIXME: What does this mean? */
15974 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
15978 i
= atoi (opt
+ 3);
15979 if (i
!= 0 && i
!= 2)
15980 as_bad (_(".option pic%d not supported"), i
);
15981 else if (mips_pic
== VXWORKS_PIC
)
15982 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
15987 mips_pic
= SVR4_PIC
;
15988 mips_abicalls
= TRUE
;
15991 if (mips_pic
== SVR4_PIC
)
15993 if (g_switch_seen
&& g_switch_value
!= 0)
15994 as_warn (_("-G may not be used with SVR4 PIC code"));
15995 g_switch_value
= 0;
15996 bfd_set_gp_size (stdoutput
, 0);
16000 as_warn (_("unrecognized option \"%s\""), opt
);
16002 (void) restore_line_pointer (c
);
16003 demand_empty_rest_of_line ();
16006 /* This structure is used to hold a stack of .set values. */
16008 struct mips_option_stack
16010 struct mips_option_stack
*next
;
16011 struct mips_set_options options
;
16014 static struct mips_option_stack
*mips_opts_stack
;
16016 /* Return status for .set/.module option handling. */
16018 enum code_option_type
16020 /* Unrecognized option. */
16021 OPTION_TYPE_BAD
= -1,
16023 /* Ordinary option. */
16024 OPTION_TYPE_NORMAL
,
16026 /* ISA changing option. */
16030 /* Handle common .set/.module options. Return status indicating option
16033 static enum code_option_type
16034 parse_code_option (char * name
)
16036 bfd_boolean isa_set
= FALSE
;
16037 const struct mips_ase
*ase
;
16039 if (strncmp (name
, "at=", 3) == 0)
16041 char *s
= name
+ 3;
16043 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16044 as_bad (_("unrecognized register name `%s'"), s
);
16046 else if (strcmp (name
, "at") == 0)
16047 mips_opts
.at
= ATREG
;
16048 else if (strcmp (name
, "noat") == 0)
16049 mips_opts
.at
= ZERO
;
16050 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16051 mips_opts
.nomove
= 0;
16052 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16053 mips_opts
.nomove
= 1;
16054 else if (strcmp (name
, "bopt") == 0)
16055 mips_opts
.nobopt
= 0;
16056 else if (strcmp (name
, "nobopt") == 0)
16057 mips_opts
.nobopt
= 1;
16058 else if (strcmp (name
, "gp=32") == 0)
16060 else if (strcmp (name
, "gp=64") == 0)
16062 else if (strcmp (name
, "fp=32") == 0)
16064 else if (strcmp (name
, "fp=xx") == 0)
16066 else if (strcmp (name
, "fp=64") == 0)
16068 else if (strcmp (name
, "softfloat") == 0)
16069 mips_opts
.soft_float
= 1;
16070 else if (strcmp (name
, "hardfloat") == 0)
16071 mips_opts
.soft_float
= 0;
16072 else if (strcmp (name
, "singlefloat") == 0)
16073 mips_opts
.single_float
= 1;
16074 else if (strcmp (name
, "doublefloat") == 0)
16075 mips_opts
.single_float
= 0;
16076 else if (strcmp (name
, "nooddspreg") == 0)
16077 mips_opts
.oddspreg
= 0;
16078 else if (strcmp (name
, "oddspreg") == 0)
16079 mips_opts
.oddspreg
= 1;
16080 else if (strcmp (name
, "mips16") == 0
16081 || strcmp (name
, "MIPS-16") == 0)
16082 mips_opts
.mips16
= 1;
16083 else if (strcmp (name
, "nomips16") == 0
16084 || strcmp (name
, "noMIPS-16") == 0)
16085 mips_opts
.mips16
= 0;
16086 else if (strcmp (name
, "micromips") == 0)
16087 mips_opts
.micromips
= 1;
16088 else if (strcmp (name
, "nomicromips") == 0)
16089 mips_opts
.micromips
= 0;
16090 else if (name
[0] == 'n'
16092 && (ase
= mips_lookup_ase (name
+ 2)))
16093 mips_set_ase (ase
, &mips_opts
, FALSE
);
16094 else if ((ase
= mips_lookup_ase (name
)))
16095 mips_set_ase (ase
, &mips_opts
, TRUE
);
16096 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16098 /* Permit the user to change the ISA and architecture on the fly.
16099 Needless to say, misuse can cause serious problems. */
16100 if (strncmp (name
, "arch=", 5) == 0)
16102 const struct mips_cpu_info
*p
;
16104 p
= mips_parse_cpu ("internal use", name
+ 5);
16106 as_bad (_("unknown architecture %s"), name
+ 5);
16109 mips_opts
.arch
= p
->cpu
;
16110 mips_opts
.isa
= p
->isa
;
16114 else if (strncmp (name
, "mips", 4) == 0)
16116 const struct mips_cpu_info
*p
;
16118 p
= mips_parse_cpu ("internal use", name
);
16120 as_bad (_("unknown ISA level %s"), name
+ 4);
16123 mips_opts
.arch
= p
->cpu
;
16124 mips_opts
.isa
= p
->isa
;
16129 as_bad (_("unknown ISA or architecture %s"), name
);
16131 else if (strcmp (name
, "autoextend") == 0)
16132 mips_opts
.noautoextend
= 0;
16133 else if (strcmp (name
, "noautoextend") == 0)
16134 mips_opts
.noautoextend
= 1;
16135 else if (strcmp (name
, "insn32") == 0)
16136 mips_opts
.insn32
= TRUE
;
16137 else if (strcmp (name
, "noinsn32") == 0)
16138 mips_opts
.insn32
= FALSE
;
16139 else if (strcmp (name
, "sym32") == 0)
16140 mips_opts
.sym32
= TRUE
;
16141 else if (strcmp (name
, "nosym32") == 0)
16142 mips_opts
.sym32
= FALSE
;
16144 return OPTION_TYPE_BAD
;
16146 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16149 /* Handle the .set pseudo-op. */
16152 s_mipsset (int x ATTRIBUTE_UNUSED
)
16154 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16155 char *name
= input_line_pointer
, ch
;
16157 file_mips_check_options ();
16159 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16160 ++input_line_pointer
;
16161 ch
= *input_line_pointer
;
16162 *input_line_pointer
= '\0';
16164 if (strchr (name
, ','))
16166 /* Generic ".set" directive; use the generic handler. */
16167 *input_line_pointer
= ch
;
16168 input_line_pointer
= name
;
16173 if (strcmp (name
, "reorder") == 0)
16175 if (mips_opts
.noreorder
)
16178 else if (strcmp (name
, "noreorder") == 0)
16180 if (!mips_opts
.noreorder
)
16181 start_noreorder ();
16183 else if (strcmp (name
, "macro") == 0)
16184 mips_opts
.warn_about_macros
= 0;
16185 else if (strcmp (name
, "nomacro") == 0)
16187 if (mips_opts
.noreorder
== 0)
16188 as_bad (_("`noreorder' must be set before `nomacro'"));
16189 mips_opts
.warn_about_macros
= 1;
16191 else if (strcmp (name
, "gp=default") == 0)
16192 mips_opts
.gp
= file_mips_opts
.gp
;
16193 else if (strcmp (name
, "fp=default") == 0)
16194 mips_opts
.fp
= file_mips_opts
.fp
;
16195 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16197 mips_opts
.isa
= file_mips_opts
.isa
;
16198 mips_opts
.arch
= file_mips_opts
.arch
;
16199 mips_opts
.gp
= file_mips_opts
.gp
;
16200 mips_opts
.fp
= file_mips_opts
.fp
;
16202 else if (strcmp (name
, "push") == 0)
16204 struct mips_option_stack
*s
;
16206 s
= XNEW (struct mips_option_stack
);
16207 s
->next
= mips_opts_stack
;
16208 s
->options
= mips_opts
;
16209 mips_opts_stack
= s
;
16211 else if (strcmp (name
, "pop") == 0)
16213 struct mips_option_stack
*s
;
16215 s
= mips_opts_stack
;
16217 as_bad (_(".set pop with no .set push"));
16220 /* If we're changing the reorder mode we need to handle
16221 delay slots correctly. */
16222 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16223 start_noreorder ();
16224 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16227 mips_opts
= s
->options
;
16228 mips_opts_stack
= s
->next
;
16234 type
= parse_code_option (name
);
16235 if (type
== OPTION_TYPE_BAD
)
16236 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16239 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16240 registers based on what is supported by the arch/cpu. */
16241 if (type
== OPTION_TYPE_ISA
)
16243 switch (mips_opts
.isa
)
16248 /* MIPS I cannot support FPXX. */
16250 /* fall-through. */
16257 if (mips_opts
.fp
!= 0)
16273 if (mips_opts
.fp
!= 0)
16275 if (mips_opts
.arch
== CPU_R5900
)
16282 as_bad (_("unknown ISA level %s"), name
+ 4);
16287 mips_check_options (&mips_opts
, FALSE
);
16289 mips_check_isa_supports_ases ();
16290 *input_line_pointer
= ch
;
16291 demand_empty_rest_of_line ();
16294 /* Handle the .module pseudo-op. */
16297 s_module (int ignore ATTRIBUTE_UNUSED
)
16299 char *name
= input_line_pointer
, ch
;
16301 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16302 ++input_line_pointer
;
16303 ch
= *input_line_pointer
;
16304 *input_line_pointer
= '\0';
16306 if (!file_mips_opts_checked
)
16308 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16309 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16311 /* Update module level settings from mips_opts. */
16312 file_mips_opts
= mips_opts
;
16315 as_bad (_(".module is not permitted after generating code"));
16317 *input_line_pointer
= ch
;
16318 demand_empty_rest_of_line ();
16321 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16322 .option pic2. It means to generate SVR4 PIC calls. */
16325 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16327 mips_pic
= SVR4_PIC
;
16328 mips_abicalls
= TRUE
;
16330 if (g_switch_seen
&& g_switch_value
!= 0)
16331 as_warn (_("-G may not be used with SVR4 PIC code"));
16332 g_switch_value
= 0;
16334 bfd_set_gp_size (stdoutput
, 0);
16335 demand_empty_rest_of_line ();
16338 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16339 PIC code. It sets the $gp register for the function based on the
16340 function address, which is in the register named in the argument.
16341 This uses a relocation against _gp_disp, which is handled specially
16342 by the linker. The result is:
16343 lui $gp,%hi(_gp_disp)
16344 addiu $gp,$gp,%lo(_gp_disp)
16345 addu $gp,$gp,.cpload argument
16346 The .cpload argument is normally $25 == $t9.
16348 The -mno-shared option changes this to:
16349 lui $gp,%hi(__gnu_local_gp)
16350 addiu $gp,$gp,%lo(__gnu_local_gp)
16351 and the argument is ignored. This saves an instruction, but the
16352 resulting code is not position independent; it uses an absolute
16353 address for __gnu_local_gp. Thus code assembled with -mno-shared
16354 can go into an ordinary executable, but not into a shared library. */
16357 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16363 file_mips_check_options ();
16365 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16366 .cpload is ignored. */
16367 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16373 if (mips_opts
.mips16
)
16375 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16376 ignore_rest_of_line ();
16380 /* .cpload should be in a .set noreorder section. */
16381 if (mips_opts
.noreorder
== 0)
16382 as_warn (_(".cpload not in noreorder section"));
16384 reg
= tc_get_register (0);
16386 /* If we need to produce a 64-bit address, we are better off using
16387 the default instruction sequence. */
16388 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16390 ex
.X_op
= O_symbol
;
16391 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16393 ex
.X_op_symbol
= NULL
;
16394 ex
.X_add_number
= 0;
16396 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16397 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16399 mips_mark_labels ();
16400 mips_assembling_insn
= TRUE
;
16403 macro_build_lui (&ex
, mips_gp_register
);
16404 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16405 mips_gp_register
, BFD_RELOC_LO16
);
16407 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16408 mips_gp_register
, reg
);
16411 mips_assembling_insn
= FALSE
;
16412 demand_empty_rest_of_line ();
16415 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16416 .cpsetup $reg1, offset|$reg2, label
16418 If offset is given, this results in:
16419 sd $gp, offset($sp)
16420 lui $gp, %hi(%neg(%gp_rel(label)))
16421 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16422 daddu $gp, $gp, $reg1
16424 If $reg2 is given, this results in:
16426 lui $gp, %hi(%neg(%gp_rel(label)))
16427 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16428 daddu $gp, $gp, $reg1
16429 $reg1 is normally $25 == $t9.
16431 The -mno-shared option replaces the last three instructions with
16433 addiu $gp,$gp,%lo(_gp) */
16436 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16438 expressionS ex_off
;
16439 expressionS ex_sym
;
16442 file_mips_check_options ();
16444 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16445 We also need NewABI support. */
16446 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16452 if (mips_opts
.mips16
)
16454 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16455 ignore_rest_of_line ();
16459 reg1
= tc_get_register (0);
16460 SKIP_WHITESPACE ();
16461 if (*input_line_pointer
!= ',')
16463 as_bad (_("missing argument separator ',' for .cpsetup"));
16467 ++input_line_pointer
;
16468 SKIP_WHITESPACE ();
16469 if (*input_line_pointer
== '$')
16471 mips_cpreturn_register
= tc_get_register (0);
16472 mips_cpreturn_offset
= -1;
16476 mips_cpreturn_offset
= get_absolute_expression ();
16477 mips_cpreturn_register
= -1;
16479 SKIP_WHITESPACE ();
16480 if (*input_line_pointer
!= ',')
16482 as_bad (_("missing argument separator ',' for .cpsetup"));
16486 ++input_line_pointer
;
16487 SKIP_WHITESPACE ();
16488 expression (&ex_sym
);
16490 mips_mark_labels ();
16491 mips_assembling_insn
= TRUE
;
16494 if (mips_cpreturn_register
== -1)
16496 ex_off
.X_op
= O_constant
;
16497 ex_off
.X_add_symbol
= NULL
;
16498 ex_off
.X_op_symbol
= NULL
;
16499 ex_off
.X_add_number
= mips_cpreturn_offset
;
16501 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16502 BFD_RELOC_LO16
, SP
);
16505 move_register (mips_cpreturn_register
, mips_gp_register
);
16507 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16509 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16510 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16513 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16514 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16515 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16517 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16518 mips_gp_register
, reg1
);
16524 ex
.X_op
= O_symbol
;
16525 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16526 ex
.X_op_symbol
= NULL
;
16527 ex
.X_add_number
= 0;
16529 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16530 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16532 macro_build_lui (&ex
, mips_gp_register
);
16533 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16534 mips_gp_register
, BFD_RELOC_LO16
);
16539 mips_assembling_insn
= FALSE
;
16540 demand_empty_rest_of_line ();
16544 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16546 file_mips_check_options ();
16548 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16549 .cplocal is ignored. */
16550 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16556 if (mips_opts
.mips16
)
16558 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16559 ignore_rest_of_line ();
16563 mips_gp_register
= tc_get_register (0);
16564 demand_empty_rest_of_line ();
16567 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16568 offset from $sp. The offset is remembered, and after making a PIC
16569 call $gp is restored from that location. */
16572 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16576 file_mips_check_options ();
16578 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16579 .cprestore is ignored. */
16580 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16586 if (mips_opts
.mips16
)
16588 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16589 ignore_rest_of_line ();
16593 mips_cprestore_offset
= get_absolute_expression ();
16594 mips_cprestore_valid
= 1;
16596 ex
.X_op
= O_constant
;
16597 ex
.X_add_symbol
= NULL
;
16598 ex
.X_op_symbol
= NULL
;
16599 ex
.X_add_number
= mips_cprestore_offset
;
16601 mips_mark_labels ();
16602 mips_assembling_insn
= TRUE
;
16605 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16606 SP
, HAVE_64BIT_ADDRESSES
);
16609 mips_assembling_insn
= FALSE
;
16610 demand_empty_rest_of_line ();
16613 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16614 was given in the preceding .cpsetup, it results in:
16615 ld $gp, offset($sp)
16617 If a register $reg2 was given there, it results in:
16618 or $gp, $reg2, $0 */
16621 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16625 file_mips_check_options ();
16627 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16628 We also need NewABI support. */
16629 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16635 if (mips_opts
.mips16
)
16637 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16638 ignore_rest_of_line ();
16642 mips_mark_labels ();
16643 mips_assembling_insn
= TRUE
;
16646 if (mips_cpreturn_register
== -1)
16648 ex
.X_op
= O_constant
;
16649 ex
.X_add_symbol
= NULL
;
16650 ex
.X_op_symbol
= NULL
;
16651 ex
.X_add_number
= mips_cpreturn_offset
;
16653 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16656 move_register (mips_gp_register
, mips_cpreturn_register
);
16660 mips_assembling_insn
= FALSE
;
16661 demand_empty_rest_of_line ();
16664 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16665 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16666 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16667 debug information or MIPS16 TLS. */
16670 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16671 bfd_reloc_code_real_type rtype
)
16678 if (ex
.X_op
!= O_symbol
)
16680 as_bad (_("unsupported use of %s"), dirstr
);
16681 ignore_rest_of_line ();
16684 p
= frag_more (bytes
);
16685 md_number_to_chars (p
, 0, bytes
);
16686 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16687 demand_empty_rest_of_line ();
16688 mips_clear_insn_labels ();
16691 /* Handle .dtprelword. */
16694 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16696 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16699 /* Handle .dtpreldword. */
16702 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16704 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16707 /* Handle .tprelword. */
16710 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16712 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16715 /* Handle .tpreldword. */
16718 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16720 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16723 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16724 code. It sets the offset to use in gp_rel relocations. */
16727 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16729 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16730 We also need NewABI support. */
16731 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16737 mips_gprel_offset
= get_absolute_expression ();
16739 demand_empty_rest_of_line ();
16742 /* Handle the .gpword pseudo-op. This is used when generating PIC
16743 code. It generates a 32 bit GP relative reloc. */
16746 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16748 segment_info_type
*si
;
16749 struct insn_label_list
*l
;
16753 /* When not generating PIC code, this is treated as .word. */
16754 if (mips_pic
!= SVR4_PIC
)
16760 si
= seg_info (now_seg
);
16761 l
= si
->label_list
;
16762 mips_emit_delays ();
16764 mips_align (2, 0, l
);
16767 mips_clear_insn_labels ();
16769 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16771 as_bad (_("unsupported use of .gpword"));
16772 ignore_rest_of_line ();
16776 md_number_to_chars (p
, 0, 4);
16777 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16778 BFD_RELOC_GPREL32
);
16780 demand_empty_rest_of_line ();
16784 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16786 segment_info_type
*si
;
16787 struct insn_label_list
*l
;
16791 /* When not generating PIC code, this is treated as .dword. */
16792 if (mips_pic
!= SVR4_PIC
)
16798 si
= seg_info (now_seg
);
16799 l
= si
->label_list
;
16800 mips_emit_delays ();
16802 mips_align (3, 0, l
);
16805 mips_clear_insn_labels ();
16807 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16809 as_bad (_("unsupported use of .gpdword"));
16810 ignore_rest_of_line ();
16814 md_number_to_chars (p
, 0, 8);
16815 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16816 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16818 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16819 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16820 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16822 demand_empty_rest_of_line ();
16825 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16826 tables. It generates a R_MIPS_EH reloc. */
16829 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16834 mips_emit_delays ();
16837 mips_clear_insn_labels ();
16839 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16841 as_bad (_("unsupported use of .ehword"));
16842 ignore_rest_of_line ();
16846 md_number_to_chars (p
, 0, 4);
16847 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16848 BFD_RELOC_32_PCREL
);
16850 demand_empty_rest_of_line ();
16853 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16854 tables in SVR4 PIC code. */
16857 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16861 file_mips_check_options ();
16863 /* This is ignored when not generating SVR4 PIC code. */
16864 if (mips_pic
!= SVR4_PIC
)
16870 mips_mark_labels ();
16871 mips_assembling_insn
= TRUE
;
16873 /* Add $gp to the register named as an argument. */
16875 reg
= tc_get_register (0);
16876 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16879 mips_assembling_insn
= FALSE
;
16880 demand_empty_rest_of_line ();
16883 /* Handle the .insn pseudo-op. This marks instruction labels in
16884 mips16/micromips mode. This permits the linker to handle them specially,
16885 such as generating jalx instructions when needed. We also make
16886 them odd for the duration of the assembly, in order to generate the
16887 right sort of code. We will make them even in the adjust_symtab
16888 routine, while leaving them marked. This is convenient for the
16889 debugger and the disassembler. The linker knows to make them odd
16893 s_insn (int ignore ATTRIBUTE_UNUSED
)
16895 file_mips_check_options ();
16896 file_ase_mips16
|= mips_opts
.mips16
;
16897 file_ase_micromips
|= mips_opts
.micromips
;
16899 mips_mark_labels ();
16901 demand_empty_rest_of_line ();
16904 /* Handle the .nan pseudo-op. */
16907 s_nan (int ignore ATTRIBUTE_UNUSED
)
16909 static const char str_legacy
[] = "legacy";
16910 static const char str_2008
[] = "2008";
16913 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16915 if (i
== sizeof (str_2008
) - 1
16916 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16918 else if (i
== sizeof (str_legacy
) - 1
16919 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16921 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16924 as_bad (_("`%s' does not support legacy NaN"),
16925 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16928 as_bad (_("bad .nan directive"));
16930 input_line_pointer
+= i
;
16931 demand_empty_rest_of_line ();
16934 /* Handle a .stab[snd] directive. Ideally these directives would be
16935 implemented in a transparent way, so that removing them would not
16936 have any effect on the generated instructions. However, s_stab
16937 internally changes the section, so in practice we need to decide
16938 now whether the preceding label marks compressed code. We do not
16939 support changing the compression mode of a label after a .stab*
16940 directive, such as in:
16946 so the current mode wins. */
16949 s_mips_stab (int type
)
16951 mips_mark_labels ();
16955 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16958 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16965 c
= get_symbol_name (&name
);
16966 symbolP
= symbol_find_or_make (name
);
16967 S_SET_WEAK (symbolP
);
16968 *input_line_pointer
= c
;
16970 SKIP_WHITESPACE_AFTER_NAME ();
16972 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16974 if (S_IS_DEFINED (symbolP
))
16976 as_bad (_("ignoring attempt to redefine symbol %s"),
16977 S_GET_NAME (symbolP
));
16978 ignore_rest_of_line ();
16982 if (*input_line_pointer
== ',')
16984 ++input_line_pointer
;
16985 SKIP_WHITESPACE ();
16989 if (exp
.X_op
!= O_symbol
)
16991 as_bad (_("bad .weakext directive"));
16992 ignore_rest_of_line ();
16995 symbol_set_value_expression (symbolP
, &exp
);
16998 demand_empty_rest_of_line ();
17001 /* Parse a register string into a number. Called from the ECOFF code
17002 to parse .frame. The argument is non-zero if this is the frame
17003 register, so that we can record it in mips_frame_reg. */
17006 tc_get_register (int frame
)
17010 SKIP_WHITESPACE ();
17011 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17015 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17016 mips_frame_reg_valid
= 1;
17017 mips_cprestore_valid
= 0;
17023 md_section_align (asection
*seg
, valueT addr
)
17025 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17027 /* We don't need to align ELF sections to the full alignment.
17028 However, Irix 5 may prefer that we align them at least to a 16
17029 byte boundary. We don't bother to align the sections if we
17030 are targeted for an embedded system. */
17031 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17036 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17039 /* Utility routine, called from above as well. If called while the
17040 input file is still being read, it's only an approximation. (For
17041 example, a symbol may later become defined which appeared to be
17042 undefined earlier.) */
17045 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17050 if (g_switch_value
> 0)
17052 const char *symname
;
17055 /* Find out whether this symbol can be referenced off the $gp
17056 register. It can be if it is smaller than the -G size or if
17057 it is in the .sdata or .sbss section. Certain symbols can
17058 not be referenced off the $gp, although it appears as though
17060 symname
= S_GET_NAME (sym
);
17061 if (symname
!= (const char *) NULL
17062 && (strcmp (symname
, "eprol") == 0
17063 || strcmp (symname
, "etext") == 0
17064 || strcmp (symname
, "_gp") == 0
17065 || strcmp (symname
, "edata") == 0
17066 || strcmp (symname
, "_fbss") == 0
17067 || strcmp (symname
, "_fdata") == 0
17068 || strcmp (symname
, "_ftext") == 0
17069 || strcmp (symname
, "end") == 0
17070 || strcmp (symname
, "_gp_disp") == 0))
17072 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17074 #ifndef NO_ECOFF_DEBUGGING
17075 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17076 && (symbol_get_obj (sym
)->ecoff_extern_size
17077 <= g_switch_value
))
17079 /* We must defer this decision until after the whole
17080 file has been read, since there might be a .extern
17081 after the first use of this symbol. */
17082 || (before_relaxing
17083 #ifndef NO_ECOFF_DEBUGGING
17084 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17086 && S_GET_VALUE (sym
) == 0)
17087 || (S_GET_VALUE (sym
) != 0
17088 && S_GET_VALUE (sym
) <= g_switch_value
)))
17092 const char *segname
;
17094 segname
= segment_name (S_GET_SEGMENT (sym
));
17095 gas_assert (strcmp (segname
, ".lit8") != 0
17096 && strcmp (segname
, ".lit4") != 0);
17097 change
= (strcmp (segname
, ".sdata") != 0
17098 && strcmp (segname
, ".sbss") != 0
17099 && strncmp (segname
, ".sdata.", 7) != 0
17100 && strncmp (segname
, ".sbss.", 6) != 0
17101 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17102 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17107 /* We are not optimizing for the $gp register. */
17112 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17115 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17119 /* Handle the case of a symbol equated to another symbol. */
17120 while (symbol_equated_reloc_p (sym
))
17124 /* It's possible to get a loop here in a badly written program. */
17125 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17131 if (symbol_section_p (sym
))
17134 symsec
= S_GET_SEGMENT (sym
);
17136 /* This must duplicate the test in adjust_reloc_syms. */
17137 return (!bfd_is_und_section (symsec
)
17138 && !bfd_is_abs_section (symsec
)
17139 && !bfd_is_com_section (symsec
)
17140 && !s_is_linkonce (sym
, segtype
)
17141 /* A global or weak symbol is treated as external. */
17142 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17146 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17147 extended opcode. SEC is the section the frag is in. */
17150 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17153 const struct mips_int_operand
*operand
;
17158 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17160 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17163 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17164 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17165 operand
= mips16_immed_operand (type
, FALSE
);
17166 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17167 || (operand
->root
.type
== OP_PCREL
17169 : !bfd_is_abs_section (symsec
)))
17172 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17173 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17175 if (operand
->root
.type
== OP_PCREL
)
17177 const struct mips_pcrel_operand
*pcrel_op
;
17181 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17184 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17186 /* If the relax_marker of the symbol fragment differs from the
17187 relax_marker of this fragment, we have not yet adjusted the
17188 symbol fragment fr_address. We want to add in STRETCH in
17189 order to get a better estimate of the address. This
17190 particularly matters because of the shift bits. */
17192 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17196 /* Adjust stretch for any alignment frag. Note that if have
17197 been expanding the earlier code, the symbol may be
17198 defined in what appears to be an earlier frag. FIXME:
17199 This doesn't handle the fr_subtype field, which specifies
17200 a maximum number of bytes to skip when doing an
17202 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17204 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17207 stretch
= - ((- stretch
)
17208 & ~ ((1 << (int) f
->fr_offset
) - 1));
17210 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17219 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17221 /* The base address rules are complicated. The base address of
17222 a branch is the following instruction. The base address of a
17223 PC relative load or add is the instruction itself, but if it
17224 is in a delay slot (in which case it can not be extended) use
17225 the address of the instruction whose delay slot it is in. */
17226 if (pcrel_op
->include_isa_bit
)
17230 /* If we are currently assuming that this frag should be
17231 extended, then, the current address is two bytes
17233 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17236 /* Ignore the low bit in the target, since it will be set
17237 for a text label. */
17240 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17242 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17245 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17247 /* If any of the shifted bits are set, we must use an extended
17248 opcode. If the address depends on the size of this
17249 instruction, this can lead to a loop, so we arrange to always
17250 use an extended opcode. */
17251 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17253 fragp
->fr_subtype
=
17254 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17258 /* If we are about to mark a frag as extended because the value
17259 is precisely the next value above maxtiny, then there is a
17260 chance of an infinite loop as in the following code:
17265 In this case when the la is extended, foo is 0x3fc bytes
17266 away, so the la can be shrunk, but then foo is 0x400 away, so
17267 the la must be extended. To avoid this loop, we mark the
17268 frag as extended if it was small, and is about to become
17269 extended with the next value above maxtiny. */
17270 maxtiny
= mips_int_operand_max (operand
);
17271 if (val
== maxtiny
+ (1 << operand
->shift
)
17272 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17274 fragp
->fr_subtype
=
17275 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17280 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17283 /* Compute the length of a branch sequence, and adjust the
17284 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17285 worst-case length is computed, with UPDATE being used to indicate
17286 whether an unconditional (-1), branch-likely (+1) or regular (0)
17287 branch is to be computed. */
17289 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17291 bfd_boolean toofar
;
17295 && S_IS_DEFINED (fragp
->fr_symbol
)
17296 && !S_IS_WEAK (fragp
->fr_symbol
)
17297 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17302 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17304 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17308 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17311 /* If the symbol is not defined or it's in a different segment,
17312 we emit the long sequence. */
17315 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17317 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17318 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17319 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17320 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17326 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17329 if (mips_pic
!= NO_PIC
)
17331 /* Additional space for PIC loading of target address. */
17333 if (mips_opts
.isa
== ISA_MIPS1
)
17334 /* Additional space for $at-stabilizing nop. */
17338 /* If branch is conditional. */
17339 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17346 /* Get a FRAG's branch instruction delay slot size, either from the
17347 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17348 or SHORT_INSN_SIZE otherwise. */
17351 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17353 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17356 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17358 return short_insn_size
;
17361 /* Compute the length of a branch sequence, and adjust the
17362 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17363 worst-case length is computed, with UPDATE being used to indicate
17364 whether an unconditional (-1), or regular (0) branch is to be
17368 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17370 bfd_boolean insn32
= TRUE
;
17371 bfd_boolean nods
= TRUE
;
17372 bfd_boolean al
= TRUE
;
17373 int short_insn_size
;
17374 bfd_boolean toofar
;
17379 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17380 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17381 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17383 short_insn_size
= insn32
? 4 : 2;
17386 && S_IS_DEFINED (fragp
->fr_symbol
)
17387 && !S_IS_WEAK (fragp
->fr_symbol
)
17388 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17393 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17394 /* Ignore the low bit in the target, since it will be set
17395 for a text label. */
17396 if ((val
& 1) != 0)
17399 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17403 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17406 /* If the symbol is not defined or it's in a different segment,
17407 we emit the long sequence. */
17410 if (fragp
&& update
17411 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17412 fragp
->fr_subtype
= (toofar
17413 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17414 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17419 bfd_boolean compact_known
= fragp
!= NULL
;
17420 bfd_boolean compact
= FALSE
;
17421 bfd_boolean uncond
;
17425 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17426 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17429 uncond
= update
< 0;
17431 /* If label is out of range, we turn branch <br>:
17433 <br> label # 4 bytes
17440 # compact && (!PIC || insn32)
17443 if ((mips_pic
== NO_PIC
|| insn32
) && (!compact_known
|| compact
))
17444 length
+= short_insn_size
;
17446 /* If assembling PIC code, we further turn:
17452 lw/ld at, %got(label)(gp) # 4 bytes
17453 d/addiu at, %lo(label) # 4 bytes
17454 jr/c at # 2/4 bytes
17456 if (mips_pic
!= NO_PIC
)
17457 length
+= 4 + short_insn_size
;
17459 /* Add an extra nop if the jump has no compact form and we need
17460 to fill the delay slot. */
17461 if ((mips_pic
== NO_PIC
|| al
) && nods
)
17463 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17464 : short_insn_size
);
17466 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17468 <brneg> 0f # 4 bytes
17469 nop # 2/4 bytes if !compact
17472 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17476 /* Add an extra nop to fill the delay slot. */
17477 gas_assert (fragp
);
17478 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17484 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17485 bit accordingly. */
17488 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17490 bfd_boolean toofar
;
17493 && S_IS_DEFINED (fragp
->fr_symbol
)
17494 && !S_IS_WEAK (fragp
->fr_symbol
)
17495 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17501 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17502 /* Ignore the low bit in the target, since it will be set
17503 for a text label. */
17504 if ((val
& 1) != 0)
17507 /* Assume this is a 2-byte branch. */
17508 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17510 /* We try to avoid the infinite loop by not adding 2 more bytes for
17515 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17517 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17518 else if (type
== 'E')
17519 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17524 /* If the symbol is not defined or it's in a different segment,
17525 we emit a normal 32-bit branch. */
17528 if (fragp
&& update
17529 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17531 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17532 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17540 /* Estimate the size of a frag before relaxing. Unless this is the
17541 mips16, we are not really relaxing here, and the final size is
17542 encoded in the subtype information. For the mips16, we have to
17543 decide whether we are using an extended opcode or not. */
17546 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17550 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17553 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17555 return fragp
->fr_var
;
17558 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17559 /* We don't want to modify the EXTENDED bit here; it might get us
17560 into infinite loops. We change it only in mips_relax_frag(). */
17561 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17563 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17567 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17568 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17569 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17570 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17571 fragp
->fr_var
= length
;
17576 if (mips_pic
== NO_PIC
)
17577 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17578 else if (mips_pic
== SVR4_PIC
)
17579 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17580 else if (mips_pic
== VXWORKS_PIC
)
17581 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17588 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17589 return -RELAX_FIRST (fragp
->fr_subtype
);
17592 return -RELAX_SECOND (fragp
->fr_subtype
);
17595 /* This is called to see whether a reloc against a defined symbol
17596 should be converted into a reloc against a section. */
17599 mips_fix_adjustable (fixS
*fixp
)
17601 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17602 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17605 if (fixp
->fx_addsy
== NULL
)
17608 /* Allow relocs used for EH tables. */
17609 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17612 /* If symbol SYM is in a mergeable section, relocations of the form
17613 SYM + 0 can usually be made section-relative. The mergeable data
17614 is then identified by the section offset rather than by the symbol.
17616 However, if we're generating REL LO16 relocations, the offset is split
17617 between the LO16 and parterning high part relocation. The linker will
17618 need to recalculate the complete offset in order to correctly identify
17621 The linker has traditionally not looked for the parterning high part
17622 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17623 placed anywhere. Rather than break backwards compatibility by changing
17624 this, it seems better not to force the issue, and instead keep the
17625 original symbol. This will work with either linker behavior. */
17626 if ((lo16_reloc_p (fixp
->fx_r_type
)
17627 || reloc_needs_lo_p (fixp
->fx_r_type
))
17628 && HAVE_IN_PLACE_ADDENDS
17629 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17632 /* There is no place to store an in-place offset for JALR relocations. */
17633 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17636 /* Likewise an in-range offset of limited PC-relative relocations may
17637 overflow the in-place relocatable field if recalculated against the
17638 start address of the symbol's containing section.
17640 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17641 section relative to allow linker relaxations to be performed later on. */
17642 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17643 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17646 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17647 to a floating-point stub. The same is true for non-R_MIPS16_26
17648 relocations against MIPS16 functions; in this case, the stub becomes
17649 the function's canonical address.
17651 Floating-point stubs are stored in unique .mips16.call.* or
17652 .mips16.fn.* sections. If a stub T for function F is in section S,
17653 the first relocation in section S must be against F; this is how the
17654 linker determines the target function. All relocations that might
17655 resolve to T must also be against F. We therefore have the following
17656 restrictions, which are given in an intentionally-redundant way:
17658 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17661 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17662 if that stub might be used.
17664 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17667 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17668 that stub might be used.
17670 There is a further restriction:
17672 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17673 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17674 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17675 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17676 against MIPS16 or microMIPS symbols because we need to keep the
17677 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17678 detection and JAL or BAL to JALX instruction conversion in the
17681 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17682 against a MIPS16 symbol. We deal with (5) by additionally leaving
17683 alone any jump and branch relocations against a microMIPS symbol.
17685 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17686 relocation against some symbol R, no relocation against R may be
17687 reduced. (Note that this deals with (2) as well as (1) because
17688 relocations against global symbols will never be reduced on ELF
17689 targets.) This approach is a little simpler than trying to detect
17690 stub sections, and gives the "all or nothing" per-symbol consistency
17691 that we have for MIPS16 symbols. */
17692 if (fixp
->fx_subsy
== NULL
17693 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17694 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17695 && (jmp_reloc_p (fixp
->fx_r_type
)
17696 || b_reloc_p (fixp
->fx_r_type
)))
17697 || *symbol_get_tc (fixp
->fx_addsy
)))
17703 /* Translate internal representation of relocation info to BFD target
17707 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17709 static arelent
*retval
[4];
17711 bfd_reloc_code_real_type code
;
17713 memset (retval
, 0, sizeof(retval
));
17714 reloc
= retval
[0] = XCNEW (arelent
);
17715 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17716 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17717 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17719 if (fixp
->fx_pcrel
)
17721 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17722 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17723 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17724 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17725 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17726 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17727 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17728 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17729 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17730 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17731 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17732 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17734 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17735 Relocations want only the symbol offset. */
17736 switch (fixp
->fx_r_type
)
17738 case BFD_RELOC_MIPS_18_PCREL_S3
:
17739 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17742 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17746 else if (HAVE_IN_PLACE_ADDENDS
17747 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17748 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17749 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17751 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17752 addend accordingly. */
17753 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17756 reloc
->addend
= fixp
->fx_addnumber
;
17758 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17759 entry to be used in the relocation's section offset. */
17760 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17762 reloc
->address
= reloc
->addend
;
17766 code
= fixp
->fx_r_type
;
17768 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17769 if (reloc
->howto
== NULL
)
17771 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17772 _("cannot represent %s relocation in this object file"
17774 bfd_get_reloc_code_name (code
));
17781 /* Relax a machine dependent frag. This returns the amount by which
17782 the current size of the frag should change. */
17785 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17787 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17789 offsetT old_var
= fragp
->fr_var
;
17791 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17793 return fragp
->fr_var
- old_var
;
17796 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17798 offsetT old_var
= fragp
->fr_var
;
17799 offsetT new_var
= 4;
17801 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17802 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17803 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17804 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17805 fragp
->fr_var
= new_var
;
17807 return new_var
- old_var
;
17810 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17813 if (mips16_extended_frag (fragp
, sec
, stretch
))
17815 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17817 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17822 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17824 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17831 /* Convert a machine dependent frag. */
17834 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17836 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17839 unsigned long insn
;
17843 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17844 insn
= read_insn (buf
);
17846 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17848 /* We generate a fixup instead of applying it right now
17849 because, if there are linker relaxations, we're going to
17850 need the relocations. */
17851 exp
.X_op
= O_symbol
;
17852 exp
.X_add_symbol
= fragp
->fr_symbol
;
17853 exp
.X_add_number
= fragp
->fr_offset
;
17855 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17856 BFD_RELOC_16_PCREL_S2
);
17857 fixp
->fx_file
= fragp
->fr_file
;
17858 fixp
->fx_line
= fragp
->fr_line
;
17860 buf
= write_insn (buf
, insn
);
17866 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17867 _("relaxed out-of-range branch into a jump"));
17869 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17872 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17874 /* Reverse the branch. */
17875 switch ((insn
>> 28) & 0xf)
17878 if ((insn
& 0xff000000) == 0x47000000
17879 || (insn
& 0xff600000) == 0x45600000)
17881 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17882 reversed by tweaking bit 23. */
17883 insn
^= 0x00800000;
17887 /* bc[0-3][tf]l? instructions can have the condition
17888 reversed by tweaking a single TF bit, and their
17889 opcodes all have 0x4???????. */
17890 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17891 insn
^= 0x00010000;
17896 /* bltz 0x04000000 bgez 0x04010000
17897 bltzal 0x04100000 bgezal 0x04110000 */
17898 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17899 insn
^= 0x00010000;
17903 /* beq 0x10000000 bne 0x14000000
17904 blez 0x18000000 bgtz 0x1c000000 */
17905 insn
^= 0x04000000;
17913 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17915 /* Clear the and-link bit. */
17916 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17918 /* bltzal 0x04100000 bgezal 0x04110000
17919 bltzall 0x04120000 bgezall 0x04130000 */
17920 insn
&= ~0x00100000;
17923 /* Branch over the branch (if the branch was likely) or the
17924 full jump (not likely case). Compute the offset from the
17925 current instruction to branch to. */
17926 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17930 /* How many bytes in instructions we've already emitted? */
17931 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17932 /* How many bytes in instructions from here to the end? */
17933 i
= fragp
->fr_var
- i
;
17935 /* Convert to instruction count. */
17937 /* Branch counts from the next instruction. */
17940 /* Branch over the jump. */
17941 buf
= write_insn (buf
, insn
);
17944 buf
= write_insn (buf
, 0);
17946 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17948 /* beql $0, $0, 2f */
17950 /* Compute the PC offset from the current instruction to
17951 the end of the variable frag. */
17952 /* How many bytes in instructions we've already emitted? */
17953 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17954 /* How many bytes in instructions from here to the end? */
17955 i
= fragp
->fr_var
- i
;
17956 /* Convert to instruction count. */
17958 /* Don't decrement i, because we want to branch over the
17962 buf
= write_insn (buf
, insn
);
17963 buf
= write_insn (buf
, 0);
17967 if (mips_pic
== NO_PIC
)
17970 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17971 ? 0x0c000000 : 0x08000000);
17972 exp
.X_op
= O_symbol
;
17973 exp
.X_add_symbol
= fragp
->fr_symbol
;
17974 exp
.X_add_number
= fragp
->fr_offset
;
17976 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17977 FALSE
, BFD_RELOC_MIPS_JMP
);
17978 fixp
->fx_file
= fragp
->fr_file
;
17979 fixp
->fx_line
= fragp
->fr_line
;
17981 buf
= write_insn (buf
, insn
);
17985 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17987 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17988 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17989 insn
|= at
<< OP_SH_RT
;
17990 exp
.X_op
= O_symbol
;
17991 exp
.X_add_symbol
= fragp
->fr_symbol
;
17992 exp
.X_add_number
= fragp
->fr_offset
;
17994 if (fragp
->fr_offset
)
17996 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17997 exp
.X_add_number
= 0;
18000 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18001 FALSE
, BFD_RELOC_MIPS_GOT16
);
18002 fixp
->fx_file
= fragp
->fr_file
;
18003 fixp
->fx_line
= fragp
->fr_line
;
18005 buf
= write_insn (buf
, insn
);
18007 if (mips_opts
.isa
== ISA_MIPS1
)
18009 buf
= write_insn (buf
, 0);
18011 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18012 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18013 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18015 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18016 FALSE
, BFD_RELOC_LO16
);
18017 fixp
->fx_file
= fragp
->fr_file
;
18018 fixp
->fx_line
= fragp
->fr_line
;
18020 buf
= write_insn (buf
, insn
);
18023 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18027 insn
|= at
<< OP_SH_RS
;
18029 buf
= write_insn (buf
, insn
);
18033 fragp
->fr_fix
+= fragp
->fr_var
;
18034 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18038 /* Relax microMIPS branches. */
18039 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18041 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18042 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18043 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18044 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18045 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18046 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18047 bfd_boolean short_ds
;
18048 unsigned long insn
;
18052 exp
.X_op
= O_symbol
;
18053 exp
.X_add_symbol
= fragp
->fr_symbol
;
18054 exp
.X_add_number
= fragp
->fr_offset
;
18056 fragp
->fr_fix
+= fragp
->fr_var
;
18058 /* Handle 16-bit branches that fit or are forced to fit. */
18059 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18061 /* We generate a fixup instead of applying it right now,
18062 because if there is linker relaxation, we're going to
18063 need the relocations. */
18065 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18066 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18067 else if (type
== 'E')
18068 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18069 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18073 fixp
->fx_file
= fragp
->fr_file
;
18074 fixp
->fx_line
= fragp
->fr_line
;
18076 /* These relocations can have an addend that won't fit in
18078 fixp
->fx_no_overflow
= 1;
18083 /* Handle 32-bit branches that fit or are forced to fit. */
18084 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18085 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18087 /* We generate a fixup instead of applying it right now,
18088 because if there is linker relaxation, we're going to
18089 need the relocations. */
18090 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18091 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18092 fixp
->fx_file
= fragp
->fr_file
;
18093 fixp
->fx_line
= fragp
->fr_line
;
18097 insn
= read_compressed_insn (buf
, 4);
18102 /* Check the short-delay-slot bit. */
18103 if (!al
|| (insn
& 0x02000000) != 0)
18104 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18106 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18109 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18114 /* Relax 16-bit branches to 32-bit branches. */
18117 insn
= read_compressed_insn (buf
, 2);
18119 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18120 insn
= 0x94000000; /* beq */
18121 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18123 unsigned long regno
;
18125 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18126 regno
= micromips_to_32_reg_d_map
[regno
];
18127 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18128 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18133 /* Nothing else to do, just write it out. */
18134 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18135 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18137 buf
= write_compressed_insn (buf
, insn
, 4);
18139 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18140 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18145 insn
= read_compressed_insn (buf
, 4);
18147 /* Relax 32-bit branches to a sequence of instructions. */
18148 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18149 _("relaxed out-of-range branch into a jump"));
18151 /* Set the short-delay-slot bit. */
18152 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18154 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18158 /* Reverse the branch. */
18159 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18160 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18161 insn
^= 0x20000000;
18162 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18163 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18164 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18165 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18166 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18167 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18168 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18169 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18170 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18171 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18172 insn
^= 0x00400000;
18173 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18174 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18175 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18176 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18177 insn
^= 0x00200000;
18178 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18180 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18182 insn
^= 0x00800000;
18188 /* Clear the and-link and short-delay-slot bits. */
18189 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18191 /* bltzal 0x40200000 bgezal 0x40600000 */
18192 /* bltzals 0x42200000 bgezals 0x42600000 */
18193 insn
&= ~0x02200000;
18196 /* Make a label at the end for use with the branch. */
18197 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18198 micromips_label_inc ();
18199 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18202 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18203 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18204 fixp
->fx_file
= fragp
->fr_file
;
18205 fixp
->fx_line
= fragp
->fr_line
;
18207 /* Branch over the jump. */
18208 buf
= write_compressed_insn (buf
, insn
, 4);
18214 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18216 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18220 if (mips_pic
== NO_PIC
)
18222 unsigned long jal
= (short_ds
|| nods
18223 ? 0x74000000 : 0xf4000000); /* jal/s */
18225 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18226 insn
= al
? jal
: 0xd4000000;
18228 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18229 BFD_RELOC_MICROMIPS_JMP
);
18230 fixp
->fx_file
= fragp
->fr_file
;
18231 fixp
->fx_line
= fragp
->fr_line
;
18233 buf
= write_compressed_insn (buf
, insn
, 4);
18235 if (compact
|| nods
)
18239 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18241 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18246 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18248 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18249 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18250 insn
|= at
<< MICROMIPSOP_SH_RT
;
18252 if (exp
.X_add_number
)
18254 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18255 exp
.X_add_number
= 0;
18258 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18259 BFD_RELOC_MICROMIPS_GOT16
);
18260 fixp
->fx_file
= fragp
->fr_file
;
18261 fixp
->fx_line
= fragp
->fr_line
;
18263 buf
= write_compressed_insn (buf
, insn
, 4);
18265 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18266 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18267 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18269 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18270 BFD_RELOC_MICROMIPS_LO16
);
18271 fixp
->fx_file
= fragp
->fr_file
;
18272 fixp
->fx_line
= fragp
->fr_line
;
18274 buf
= write_compressed_insn (buf
, insn
, 4);
18279 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18280 insn
|= at
<< MICROMIPSOP_SH_RS
;
18282 buf
= write_compressed_insn (buf
, insn
, 4);
18284 if (compact
|| nods
)
18286 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18290 /* jr/jrc/jalr/jalrs $at */
18291 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18292 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18294 insn
= al
? jalr
: jr
;
18295 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18297 buf
= write_compressed_insn (buf
, insn
, 2);
18302 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18304 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18309 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18313 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18316 const struct mips_int_operand
*operand
;
18319 unsigned int user_length
, length
;
18320 bfd_boolean need_reloc
;
18321 unsigned long insn
;
18325 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18326 operand
= mips16_immed_operand (type
, FALSE
);
18328 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18329 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18331 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18332 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18333 || (operand
->root
.type
== OP_PCREL
18335 : !bfd_is_abs_section (symsec
)));
18337 if (operand
->root
.type
== OP_PCREL
)
18339 const struct mips_pcrel_operand
*pcrel_op
;
18342 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18343 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18345 /* The rules for the base address of a PC relative reloc are
18346 complicated; see mips16_extended_frag. */
18347 if (pcrel_op
->include_isa_bit
)
18351 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18352 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18353 _("branch to a symbol in another ISA mode"));
18354 else if ((fragp
->fr_offset
& 0x1) != 0)
18355 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18356 _("branch to misaligned address (0x%lx)"),
18362 /* Ignore the low bit in the target, since it will be
18363 set for a text label. */
18366 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18368 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18371 addr
&= -(1 << pcrel_op
->align_log2
);
18374 /* Make sure the section winds up with the alignment we have
18376 if (operand
->shift
> 0)
18377 record_alignment (asec
, operand
->shift
);
18381 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18382 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18383 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18384 _("extended instruction in delay slot"));
18386 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18388 insn
= read_compressed_insn (buf
, 2);
18390 insn
|= MIPS16_EXTEND
;
18392 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18394 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18401 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18409 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18412 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18413 _("unsupported relocation"));
18416 if (reloc
== BFD_RELOC_NONE
)
18420 exp
.X_op
= O_symbol
;
18421 exp
.X_add_symbol
= fragp
->fr_symbol
;
18422 exp
.X_add_number
= fragp
->fr_offset
;
18424 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
,
18427 fixp
->fx_file
= fragp
->fr_file
;
18428 fixp
->fx_line
= fragp
->fr_line
;
18430 /* These relocations can have an addend that won't fit
18432 fixp
->fx_no_overflow
= 1;
18435 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18436 _("invalid unextended operand value"));
18439 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18440 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18442 length
= (ext
? 4 : 2);
18443 gas_assert (mips16_opcode_length (insn
) == length
);
18444 write_compressed_insn (buf
, insn
, length
);
18445 fragp
->fr_fix
+= length
;
18449 relax_substateT subtype
= fragp
->fr_subtype
;
18450 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18451 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18455 first
= RELAX_FIRST (subtype
);
18456 second
= RELAX_SECOND (subtype
);
18457 fixp
= (fixS
*) fragp
->fr_opcode
;
18459 /* If the delay slot chosen does not match the size of the instruction,
18460 then emit a warning. */
18461 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18462 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18467 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18468 | RELAX_DELAY_SLOT_SIZE_FIRST
18469 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18470 msg
= macro_warning (s
);
18472 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18476 /* Possibly emit a warning if we've chosen the longer option. */
18477 if (use_second
== second_longer
)
18483 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18484 msg
= macro_warning (s
);
18486 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18490 /* Go through all the fixups for the first sequence. Disable them
18491 (by marking them as done) if we're going to use the second
18492 sequence instead. */
18494 && fixp
->fx_frag
== fragp
18495 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18497 if (subtype
& RELAX_USE_SECOND
)
18499 fixp
= fixp
->fx_next
;
18502 /* Go through the fixups for the second sequence. Disable them if
18503 we're going to use the first sequence, otherwise adjust their
18504 addresses to account for the relaxation. */
18505 while (fixp
&& fixp
->fx_frag
== fragp
)
18507 if (subtype
& RELAX_USE_SECOND
)
18508 fixp
->fx_where
-= first
;
18511 fixp
= fixp
->fx_next
;
18514 /* Now modify the frag contents. */
18515 if (subtype
& RELAX_USE_SECOND
)
18519 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18520 memmove (start
, start
+ first
, second
);
18521 fragp
->fr_fix
-= first
;
18524 fragp
->fr_fix
-= second
;
18528 /* This function is called after the relocs have been generated.
18529 We've been storing mips16 text labels as odd. Here we convert them
18530 back to even for the convenience of the debugger. */
18533 mips_frob_file_after_relocs (void)
18536 unsigned int count
, i
;
18538 syms
= bfd_get_outsymbols (stdoutput
);
18539 count
= bfd_get_symcount (stdoutput
);
18540 for (i
= 0; i
< count
; i
++, syms
++)
18541 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18542 && ((*syms
)->value
& 1) != 0)
18544 (*syms
)->value
&= ~1;
18545 /* If the symbol has an odd size, it was probably computed
18546 incorrectly, so adjust that as well. */
18547 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18548 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18552 /* This function is called whenever a label is defined, including fake
18553 labels instantiated off the dot special symbol. It is used when
18554 handling branch delays; if a branch has a label, we assume we cannot
18555 move it. This also bumps the value of the symbol by 1 in compressed
18559 mips_record_label (symbolS
*sym
)
18561 segment_info_type
*si
= seg_info (now_seg
);
18562 struct insn_label_list
*l
;
18564 if (free_insn_labels
== NULL
)
18565 l
= XNEW (struct insn_label_list
);
18568 l
= free_insn_labels
;
18569 free_insn_labels
= l
->next
;
18573 l
->next
= si
->label_list
;
18574 si
->label_list
= l
;
18577 /* This function is called as tc_frob_label() whenever a label is defined
18578 and adds a DWARF-2 record we only want for true labels. */
18581 mips_define_label (symbolS
*sym
)
18583 mips_record_label (sym
);
18584 dwarf2_emit_label (sym
);
18587 /* This function is called by tc_new_dot_label whenever a new dot symbol
18591 mips_add_dot_label (symbolS
*sym
)
18593 mips_record_label (sym
);
18594 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18595 mips_compressed_mark_label (sym
);
18598 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18599 static unsigned int
18600 mips_convert_ase_flags (int ase
)
18602 unsigned int ext_ases
= 0;
18605 ext_ases
|= AFL_ASE_DSP
;
18606 if (ase
& ASE_DSPR2
)
18607 ext_ases
|= AFL_ASE_DSPR2
;
18608 if (ase
& ASE_DSPR3
)
18609 ext_ases
|= AFL_ASE_DSPR3
;
18611 ext_ases
|= AFL_ASE_EVA
;
18613 ext_ases
|= AFL_ASE_MCU
;
18614 if (ase
& ASE_MDMX
)
18615 ext_ases
|= AFL_ASE_MDMX
;
18616 if (ase
& ASE_MIPS3D
)
18617 ext_ases
|= AFL_ASE_MIPS3D
;
18619 ext_ases
|= AFL_ASE_MT
;
18620 if (ase
& ASE_SMARTMIPS
)
18621 ext_ases
|= AFL_ASE_SMARTMIPS
;
18622 if (ase
& ASE_VIRT
)
18623 ext_ases
|= AFL_ASE_VIRT
;
18625 ext_ases
|= AFL_ASE_MSA
;
18627 ext_ases
|= AFL_ASE_XPA
;
18631 /* Some special processing for a MIPS ELF file. */
18634 mips_elf_final_processing (void)
18637 Elf_Internal_ABIFlags_v0 flags
;
18641 switch (file_mips_opts
.isa
)
18644 flags
.isa_level
= 1;
18647 flags
.isa_level
= 2;
18650 flags
.isa_level
= 3;
18653 flags
.isa_level
= 4;
18656 flags
.isa_level
= 5;
18659 flags
.isa_level
= 32;
18663 flags
.isa_level
= 32;
18667 flags
.isa_level
= 32;
18671 flags
.isa_level
= 32;
18675 flags
.isa_level
= 32;
18679 flags
.isa_level
= 64;
18683 flags
.isa_level
= 64;
18687 flags
.isa_level
= 64;
18691 flags
.isa_level
= 64;
18695 flags
.isa_level
= 64;
18700 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18701 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18702 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18703 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18705 flags
.cpr2_size
= AFL_REG_NONE
;
18706 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18707 Tag_GNU_MIPS_ABI_FP
);
18708 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18709 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18710 if (file_ase_mips16
)
18711 flags
.ases
|= AFL_ASE_MIPS16
;
18712 if (file_ase_micromips
)
18713 flags
.ases
|= AFL_ASE_MICROMIPS
;
18715 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18716 || file_mips_opts
.fp
== 64)
18717 && file_mips_opts
.oddspreg
)
18718 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18721 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18722 ((Elf_External_ABIFlags_v0
*)
18725 /* Write out the register information. */
18726 if (mips_abi
!= N64_ABI
)
18730 s
.ri_gprmask
= mips_gprmask
;
18731 s
.ri_cprmask
[0] = mips_cprmask
[0];
18732 s
.ri_cprmask
[1] = mips_cprmask
[1];
18733 s
.ri_cprmask
[2] = mips_cprmask
[2];
18734 s
.ri_cprmask
[3] = mips_cprmask
[3];
18735 /* The gp_value field is set by the MIPS ELF backend. */
18737 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18738 ((Elf32_External_RegInfo
*)
18739 mips_regmask_frag
));
18743 Elf64_Internal_RegInfo s
;
18745 s
.ri_gprmask
= mips_gprmask
;
18747 s
.ri_cprmask
[0] = mips_cprmask
[0];
18748 s
.ri_cprmask
[1] = mips_cprmask
[1];
18749 s
.ri_cprmask
[2] = mips_cprmask
[2];
18750 s
.ri_cprmask
[3] = mips_cprmask
[3];
18751 /* The gp_value field is set by the MIPS ELF backend. */
18753 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18754 ((Elf64_External_RegInfo
*)
18755 mips_regmask_frag
));
18758 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18759 sort of BFD interface for this. */
18760 if (mips_any_noreorder
)
18761 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18762 if (mips_pic
!= NO_PIC
)
18764 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18765 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18768 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18770 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18771 defined at present; this might need to change in future. */
18772 if (file_ase_mips16
)
18773 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18774 if (file_ase_micromips
)
18775 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18776 if (file_mips_opts
.ase
& ASE_MDMX
)
18777 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18779 /* Set the MIPS ELF ABI flags. */
18780 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18781 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18782 else if (mips_abi
== O64_ABI
)
18783 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18784 else if (mips_abi
== EABI_ABI
)
18786 if (file_mips_opts
.gp
== 64)
18787 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18789 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18791 else if (mips_abi
== N32_ABI
)
18792 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18794 /* Nothing to do for N64_ABI. */
18796 if (mips_32bitmode
)
18797 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18799 if (mips_nan2008
== 1)
18800 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18802 /* 32 bit code with 64 bit FP registers. */
18803 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18804 Tag_GNU_MIPS_ABI_FP
);
18805 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18806 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18809 typedef struct proc
{
18811 symbolS
*func_end_sym
;
18812 unsigned long reg_mask
;
18813 unsigned long reg_offset
;
18814 unsigned long fpreg_mask
;
18815 unsigned long fpreg_offset
;
18816 unsigned long frame_offset
;
18817 unsigned long frame_reg
;
18818 unsigned long pc_reg
;
18821 static procS cur_proc
;
18822 static procS
*cur_proc_ptr
;
18823 static int numprocs
;
18825 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18826 as "2", and a normal nop as "0". */
18828 #define NOP_OPCODE_MIPS 0
18829 #define NOP_OPCODE_MIPS16 1
18830 #define NOP_OPCODE_MICROMIPS 2
18833 mips_nop_opcode (void)
18835 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18836 return NOP_OPCODE_MICROMIPS
;
18837 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18838 return NOP_OPCODE_MIPS16
;
18840 return NOP_OPCODE_MIPS
;
18843 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18844 32-bit microMIPS NOPs here (if applicable). */
18847 mips_handle_align (fragS
*fragp
)
18851 int bytes
, size
, excess
;
18854 if (fragp
->fr_type
!= rs_align_code
)
18857 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18859 switch (nop_opcode
)
18861 case NOP_OPCODE_MICROMIPS
:
18862 opcode
= micromips_nop32_insn
.insn_opcode
;
18865 case NOP_OPCODE_MIPS16
:
18866 opcode
= mips16_nop_insn
.insn_opcode
;
18869 case NOP_OPCODE_MIPS
:
18871 opcode
= nop_insn
.insn_opcode
;
18876 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18877 excess
= bytes
% size
;
18879 /* Handle the leading part if we're not inserting a whole number of
18880 instructions, and make it the end of the fixed part of the frag.
18881 Try to fit in a short microMIPS NOP if applicable and possible,
18882 and use zeroes otherwise. */
18883 gas_assert (excess
< 4);
18884 fragp
->fr_fix
+= excess
;
18889 /* Fall through. */
18891 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18893 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18897 /* Fall through. */
18900 /* Fall through. */
18905 md_number_to_chars (p
, opcode
, size
);
18906 fragp
->fr_var
= size
;
18915 if (*input_line_pointer
== '-')
18917 ++input_line_pointer
;
18920 if (!ISDIGIT (*input_line_pointer
))
18921 as_bad (_("expected simple number"));
18922 if (input_line_pointer
[0] == '0')
18924 if (input_line_pointer
[1] == 'x')
18926 input_line_pointer
+= 2;
18927 while (ISXDIGIT (*input_line_pointer
))
18930 val
|= hex_value (*input_line_pointer
++);
18932 return negative
? -val
: val
;
18936 ++input_line_pointer
;
18937 while (ISDIGIT (*input_line_pointer
))
18940 val
|= *input_line_pointer
++ - '0';
18942 return negative
? -val
: val
;
18945 if (!ISDIGIT (*input_line_pointer
))
18947 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18948 *input_line_pointer
, *input_line_pointer
);
18949 as_warn (_("invalid number"));
18952 while (ISDIGIT (*input_line_pointer
))
18955 val
+= *input_line_pointer
++ - '0';
18957 return negative
? -val
: val
;
18960 /* The .file directive; just like the usual .file directive, but there
18961 is an initial number which is the ECOFF file index. In the non-ECOFF
18962 case .file implies DWARF-2. */
18965 s_mips_file (int x ATTRIBUTE_UNUSED
)
18967 static int first_file_directive
= 0;
18969 if (ECOFF_DEBUGGING
)
18978 filename
= dwarf2_directive_file (0);
18980 /* Versions of GCC up to 3.1 start files with a ".file"
18981 directive even for stabs output. Make sure that this
18982 ".file" is handled. Note that you need a version of GCC
18983 after 3.1 in order to support DWARF-2 on MIPS. */
18984 if (filename
!= NULL
&& ! first_file_directive
)
18986 (void) new_logical_line (filename
, -1);
18987 s_app_file_string (filename
, 0);
18989 first_file_directive
= 1;
18993 /* The .loc directive, implying DWARF-2. */
18996 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18998 if (!ECOFF_DEBUGGING
)
18999 dwarf2_directive_loc (0);
19002 /* The .end directive. */
19005 s_mips_end (int x ATTRIBUTE_UNUSED
)
19009 /* Following functions need their own .frame and .cprestore directives. */
19010 mips_frame_reg_valid
= 0;
19011 mips_cprestore_valid
= 0;
19013 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19016 demand_empty_rest_of_line ();
19021 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19022 as_warn (_(".end not in text section"));
19026 as_warn (_(".end directive without a preceding .ent directive"));
19027 demand_empty_rest_of_line ();
19033 gas_assert (S_GET_NAME (p
));
19034 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19035 as_warn (_(".end symbol does not match .ent symbol"));
19037 if (debug_type
== DEBUG_STABS
)
19038 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19042 as_warn (_(".end directive missing or unknown symbol"));
19044 /* Create an expression to calculate the size of the function. */
19045 if (p
&& cur_proc_ptr
)
19047 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19048 expressionS
*exp
= XNEW (expressionS
);
19051 exp
->X_op
= O_subtract
;
19052 exp
->X_add_symbol
= symbol_temp_new_now ();
19053 exp
->X_op_symbol
= p
;
19054 exp
->X_add_number
= 0;
19056 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19059 /* Generate a .pdr section. */
19060 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19062 segT saved_seg
= now_seg
;
19063 subsegT saved_subseg
= now_subseg
;
19067 #ifdef md_flush_pending_output
19068 md_flush_pending_output ();
19071 gas_assert (pdr_seg
);
19072 subseg_set (pdr_seg
, 0);
19074 /* Write the symbol. */
19075 exp
.X_op
= O_symbol
;
19076 exp
.X_add_symbol
= p
;
19077 exp
.X_add_number
= 0;
19078 emit_expr (&exp
, 4);
19080 fragp
= frag_more (7 * 4);
19082 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19083 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19084 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19085 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19086 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19087 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19088 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19090 subseg_set (saved_seg
, saved_subseg
);
19093 cur_proc_ptr
= NULL
;
19096 /* The .aent and .ent directives. */
19099 s_mips_ent (int aent
)
19103 symbolP
= get_symbol ();
19104 if (*input_line_pointer
== ',')
19105 ++input_line_pointer
;
19106 SKIP_WHITESPACE ();
19107 if (ISDIGIT (*input_line_pointer
)
19108 || *input_line_pointer
== '-')
19111 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19112 as_warn (_(".ent or .aent not in text section"));
19114 if (!aent
&& cur_proc_ptr
)
19115 as_warn (_("missing .end"));
19119 /* This function needs its own .frame and .cprestore directives. */
19120 mips_frame_reg_valid
= 0;
19121 mips_cprestore_valid
= 0;
19123 cur_proc_ptr
= &cur_proc
;
19124 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19126 cur_proc_ptr
->func_sym
= symbolP
;
19130 if (debug_type
== DEBUG_STABS
)
19131 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19132 S_GET_NAME (symbolP
));
19135 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19137 demand_empty_rest_of_line ();
19140 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19141 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19142 s_mips_frame is used so that we can set the PDR information correctly.
19143 We can't use the ecoff routines because they make reference to the ecoff
19144 symbol table (in the mdebug section). */
19147 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19149 if (ECOFF_DEBUGGING
)
19155 if (cur_proc_ptr
== (procS
*) NULL
)
19157 as_warn (_(".frame outside of .ent"));
19158 demand_empty_rest_of_line ();
19162 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19164 SKIP_WHITESPACE ();
19165 if (*input_line_pointer
++ != ','
19166 || get_absolute_expression_and_terminator (&val
) != ',')
19168 as_warn (_("bad .frame directive"));
19169 --input_line_pointer
;
19170 demand_empty_rest_of_line ();
19174 cur_proc_ptr
->frame_offset
= val
;
19175 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19177 demand_empty_rest_of_line ();
19181 /* The .fmask and .mask directives. If the mdebug section is present
19182 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19183 embedded targets, s_mips_mask is used so that we can set the PDR
19184 information correctly. We can't use the ecoff routines because they
19185 make reference to the ecoff symbol table (in the mdebug section). */
19188 s_mips_mask (int reg_type
)
19190 if (ECOFF_DEBUGGING
)
19191 s_ignore (reg_type
);
19196 if (cur_proc_ptr
== (procS
*) NULL
)
19198 as_warn (_(".mask/.fmask outside of .ent"));
19199 demand_empty_rest_of_line ();
19203 if (get_absolute_expression_and_terminator (&mask
) != ',')
19205 as_warn (_("bad .mask/.fmask directive"));
19206 --input_line_pointer
;
19207 demand_empty_rest_of_line ();
19211 off
= get_absolute_expression ();
19213 if (reg_type
== 'F')
19215 cur_proc_ptr
->fpreg_mask
= mask
;
19216 cur_proc_ptr
->fpreg_offset
= off
;
19220 cur_proc_ptr
->reg_mask
= mask
;
19221 cur_proc_ptr
->reg_offset
= off
;
19224 demand_empty_rest_of_line ();
19228 /* A table describing all the processors gas knows about. Names are
19229 matched in the order listed.
19231 To ease comparison, please keep this table in the same order as
19232 gcc's mips_cpu_info_table[]. */
19233 static const struct mips_cpu_info mips_cpu_info_table
[] =
19235 /* Entries for generic ISAs */
19236 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19237 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19238 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19239 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19240 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19241 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19242 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19243 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19244 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19245 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19246 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19247 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19248 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19249 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19250 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19253 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19254 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19255 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19258 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19261 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19262 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19263 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19264 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19265 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19266 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19267 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19268 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19269 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19270 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19271 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19272 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19273 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19274 /* ST Microelectronics Loongson 2E and 2F cores */
19275 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19276 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19279 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19280 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19281 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19282 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19283 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19284 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19285 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19286 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19287 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19288 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19289 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19290 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19291 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19292 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19293 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19296 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19297 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19298 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19299 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19301 /* MIPS 32 Release 2 */
19302 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19303 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19304 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19305 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19306 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19307 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19308 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19309 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19310 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19311 ISA_MIPS32R2
, CPU_MIPS32R2
},
19312 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19313 ISA_MIPS32R2
, CPU_MIPS32R2
},
19314 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19315 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19316 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19317 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19318 /* Deprecated forms of the above. */
19319 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19320 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19321 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19322 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19323 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19324 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19325 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19326 /* Deprecated forms of the above. */
19327 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19328 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19329 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19330 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19331 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19332 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19333 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19334 /* Deprecated forms of the above. */
19335 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19336 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19337 /* 34Kn is a 34kc without DSP. */
19338 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19339 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19340 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19341 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19342 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19343 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19344 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19345 /* Deprecated forms of the above. */
19346 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19347 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19348 /* 1004K cores are multiprocessor versions of the 34K. */
19349 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19350 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19351 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19352 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19353 /* interaptiv is the new name for 1004kf */
19354 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19356 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19357 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19358 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19359 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19362 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19363 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19364 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19365 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19367 /* Broadcom SB-1 CPU core */
19368 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19369 /* Broadcom SB-1A CPU core */
19370 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19372 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19374 /* MIPS 64 Release 2 */
19376 /* Cavium Networks Octeon CPU core */
19377 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19378 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19379 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19380 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19383 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19386 XLP is mostly like XLR, with the prominent exception that it is
19387 MIPS64R2 rather than MIPS64. */
19388 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19390 /* MIPS 64 Release 6 */
19391 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19392 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19395 { NULL
, 0, 0, 0, 0 }
19399 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19400 with a final "000" replaced by "k". Ignore case.
19402 Note: this function is shared between GCC and GAS. */
19405 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19407 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19408 given
++, canonical
++;
19410 return ((*given
== 0 && *canonical
== 0)
19411 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19415 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19416 CPU name. We've traditionally allowed a lot of variation here.
19418 Note: this function is shared between GCC and GAS. */
19421 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19423 /* First see if the name matches exactly, or with a final "000"
19424 turned into "k". */
19425 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19428 /* If not, try comparing based on numerical designation alone.
19429 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19430 if (TOLOWER (*given
) == 'r')
19432 if (!ISDIGIT (*given
))
19435 /* Skip over some well-known prefixes in the canonical name,
19436 hoping to find a number there too. */
19437 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19439 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19441 else if (TOLOWER (canonical
[0]) == 'r')
19444 return mips_strict_matching_cpu_name_p (canonical
, given
);
19448 /* Parse an option that takes the name of a processor as its argument.
19449 OPTION is the name of the option and CPU_STRING is the argument.
19450 Return the corresponding processor enumeration if the CPU_STRING is
19451 recognized, otherwise report an error and return null.
19453 A similar function exists in GCC. */
19455 static const struct mips_cpu_info
*
19456 mips_parse_cpu (const char *option
, const char *cpu_string
)
19458 const struct mips_cpu_info
*p
;
19460 /* 'from-abi' selects the most compatible architecture for the given
19461 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19462 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19463 version. Look first at the -mgp options, if given, otherwise base
19464 the choice on MIPS_DEFAULT_64BIT.
19466 Treat NO_ABI like the EABIs. One reason to do this is that the
19467 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19468 architecture. This code picks MIPS I for 'mips' and MIPS III for
19469 'mips64', just as we did in the days before 'from-abi'. */
19470 if (strcasecmp (cpu_string
, "from-abi") == 0)
19472 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19473 return mips_cpu_info_from_isa (ISA_MIPS1
);
19475 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19476 return mips_cpu_info_from_isa (ISA_MIPS3
);
19478 if (file_mips_opts
.gp
>= 0)
19479 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19480 ? ISA_MIPS1
: ISA_MIPS3
);
19482 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19487 /* 'default' has traditionally been a no-op. Probably not very useful. */
19488 if (strcasecmp (cpu_string
, "default") == 0)
19491 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19492 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19495 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19499 /* Return the canonical processor information for ISA (a member of the
19500 ISA_MIPS* enumeration). */
19502 static const struct mips_cpu_info
*
19503 mips_cpu_info_from_isa (int isa
)
19507 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19508 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19509 && isa
== mips_cpu_info_table
[i
].isa
)
19510 return (&mips_cpu_info_table
[i
]);
19515 static const struct mips_cpu_info
*
19516 mips_cpu_info_from_arch (int arch
)
19520 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19521 if (arch
== mips_cpu_info_table
[i
].cpu
)
19522 return (&mips_cpu_info_table
[i
]);
19528 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19532 fprintf (stream
, "%24s", "");
19537 fprintf (stream
, ", ");
19541 if (*col_p
+ strlen (string
) > 72)
19543 fprintf (stream
, "\n%24s", "");
19547 fprintf (stream
, "%s", string
);
19548 *col_p
+= strlen (string
);
19554 md_show_usage (FILE *stream
)
19559 fprintf (stream
, _("\
19561 -EB generate big endian output\n\
19562 -EL generate little endian output\n\
19563 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19564 -G NUM allow referencing objects up to NUM bytes\n\
19565 implicitly with the gp register [default 8]\n"));
19566 fprintf (stream
, _("\
19567 -mips1 generate MIPS ISA I instructions\n\
19568 -mips2 generate MIPS ISA II instructions\n\
19569 -mips3 generate MIPS ISA III instructions\n\
19570 -mips4 generate MIPS ISA IV instructions\n\
19571 -mips5 generate MIPS ISA V instructions\n\
19572 -mips32 generate MIPS32 ISA instructions\n\
19573 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19574 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19575 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19576 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19577 -mips64 generate MIPS64 ISA instructions\n\
19578 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19579 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19580 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19581 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19582 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19586 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19587 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19588 show (stream
, "from-abi", &column
, &first
);
19589 fputc ('\n', stream
);
19591 fprintf (stream
, _("\
19592 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19593 -no-mCPU don't generate code specific to CPU.\n\
19594 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19598 show (stream
, "3900", &column
, &first
);
19599 show (stream
, "4010", &column
, &first
);
19600 show (stream
, "4100", &column
, &first
);
19601 show (stream
, "4650", &column
, &first
);
19602 fputc ('\n', stream
);
19604 fprintf (stream
, _("\
19605 -mips16 generate mips16 instructions\n\
19606 -no-mips16 do not generate mips16 instructions\n"));
19607 fprintf (stream
, _("\
19608 -mmicromips generate microMIPS instructions\n\
19609 -mno-micromips do not generate microMIPS instructions\n"));
19610 fprintf (stream
, _("\
19611 -msmartmips generate smartmips instructions\n\
19612 -mno-smartmips do not generate smartmips instructions\n"));
19613 fprintf (stream
, _("\
19614 -mdsp generate DSP instructions\n\
19615 -mno-dsp do not generate DSP instructions\n"));
19616 fprintf (stream
, _("\
19617 -mdspr2 generate DSP R2 instructions\n\
19618 -mno-dspr2 do not generate DSP R2 instructions\n"));
19619 fprintf (stream
, _("\
19620 -mdspr3 generate DSP R3 instructions\n\
19621 -mno-dspr3 do not generate DSP R3 instructions\n"));
19622 fprintf (stream
, _("\
19623 -mmt generate MT instructions\n\
19624 -mno-mt do not generate MT instructions\n"));
19625 fprintf (stream
, _("\
19626 -mmcu generate MCU instructions\n\
19627 -mno-mcu do not generate MCU instructions\n"));
19628 fprintf (stream
, _("\
19629 -mmsa generate MSA instructions\n\
19630 -mno-msa do not generate MSA instructions\n"));
19631 fprintf (stream
, _("\
19632 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19633 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19634 fprintf (stream
, _("\
19635 -mvirt generate Virtualization instructions\n\
19636 -mno-virt do not generate Virtualization instructions\n"));
19637 fprintf (stream
, _("\
19638 -minsn32 only generate 32-bit microMIPS instructions\n\
19639 -mno-insn32 generate all microMIPS instructions\n"));
19640 fprintf (stream
, _("\
19641 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19642 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19643 -mfix-vr4120 work around certain VR4120 errata\n\
19644 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19645 -mfix-24k insert a nop after ERET and DERET instructions\n\
19646 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19647 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19648 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19649 -msym32 assume all symbols have 32-bit values\n\
19650 -O0 remove unneeded NOPs, do not swap branches\n\
19651 -O remove unneeded NOPs and swap branches\n\
19652 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19653 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19654 fprintf (stream
, _("\
19655 -mhard-float allow floating-point instructions\n\
19656 -msoft-float do not allow floating-point instructions\n\
19657 -msingle-float only allow 32-bit floating-point operations\n\
19658 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19659 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19660 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19661 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19665 show (stream
, "legacy", &column
, &first
);
19666 show (stream
, "2008", &column
, &first
);
19668 fputc ('\n', stream
);
19670 fprintf (stream
, _("\
19671 -KPIC, -call_shared generate SVR4 position independent code\n\
19672 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19673 -mvxworks-pic generate VxWorks position independent code\n\
19674 -non_shared do not generate code that can operate with DSOs\n\
19675 -xgot assume a 32 bit GOT\n\
19676 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19677 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19678 position dependent (non shared) code\n\
19679 -mabi=ABI create ABI conformant object file for:\n"));
19683 show (stream
, "32", &column
, &first
);
19684 show (stream
, "o64", &column
, &first
);
19685 show (stream
, "n32", &column
, &first
);
19686 show (stream
, "64", &column
, &first
);
19687 show (stream
, "eabi", &column
, &first
);
19689 fputc ('\n', stream
);
19691 fprintf (stream
, _("\
19692 -32 create o32 ABI object file (default)\n\
19693 -n32 create n32 ABI object file\n\
19694 -64 create 64 ABI object file\n"));
19699 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19701 if (HAVE_64BIT_SYMBOLS
)
19702 return dwarf2_format_64bit_irix
;
19704 return dwarf2_format_32bit
;
19709 mips_dwarf2_addr_size (void)
19711 if (HAVE_64BIT_OBJECTS
)
19717 /* Standard calling conventions leave the CFA at SP on entry. */
19719 mips_cfi_frame_initial_instructions (void)
19721 cfi_add_CFA_def_cfa_register (SP
);
19725 tc_mips_regname_to_dw2regnum (char *regname
)
19727 unsigned int regnum
= -1;
19730 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19736 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19737 Given a symbolic attribute NAME, return the proper integer value.
19738 Returns -1 if the attribute is not known. */
19741 mips_convert_symbolic_attribute (const char *name
)
19743 static const struct
19748 attribute_table
[] =
19750 #define T(tag) {#tag, tag}
19751 T (Tag_GNU_MIPS_ABI_FP
),
19752 T (Tag_GNU_MIPS_ABI_MSA
),
19760 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19761 if (streq (name
, attribute_table
[i
].name
))
19762 return attribute_table
[i
].tag
;
19770 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19772 mips_emit_delays ();
19774 as_warn (_("missing .end at end of assembly"));
19776 /* Just in case no code was emitted, do the consistency check. */
19777 file_mips_check_options ();
19779 /* Set a floating-point ABI if the user did not. */
19780 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19782 /* Perform consistency checks on the floating-point ABI. */
19783 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19784 Tag_GNU_MIPS_ABI_FP
);
19785 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19786 check_fpabi (fpabi
);
19790 /* Soft-float gets precedence over single-float, the two options should
19791 not be used together so this should not matter. */
19792 if (file_mips_opts
.soft_float
== 1)
19793 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19794 /* Single-float gets precedence over all double_float cases. */
19795 else if (file_mips_opts
.single_float
== 1)
19796 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19799 switch (file_mips_opts
.fp
)
19802 if (file_mips_opts
.gp
== 32)
19803 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19806 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19809 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19810 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19811 else if (file_mips_opts
.gp
== 32)
19812 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19814 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19819 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19820 Tag_GNU_MIPS_ABI_FP
, fpabi
);
19824 /* Returns the relocation type required for a particular CFI encoding. */
19826 bfd_reloc_code_real_type
19827 mips_cfi_reloc_for_encoding (int encoding
)
19829 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
19830 return BFD_RELOC_32_PCREL
;
19831 else return BFD_RELOC_NONE
;