1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format
{
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error
{
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format
;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error
;
671 static int auto_align
= 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset
= -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset
= -1;
683 static int mips_cpreturn_register
= -1;
684 static int mips_gp_register
= GP
;
685 static int mips_gprel_offset
= 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid
= 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg
= SP
;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid
= 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize
= 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug
= 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history
[1 + MAX_NOPS
];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array
{
731 const struct mips_operand
*operand
[MAX_OPERANDS
];
733 static struct mips_operand_array
*mips_operands
;
734 static struct mips_operand_array
*mips16_operands
;
735 static struct mips_operand_array
*micromips_operands
;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn
;
739 static struct mips_cl_insn mips16_nop_insn
;
740 static struct mips_cl_insn micromips_nop16_insn
;
741 static struct mips_cl_insn micromips_nop32_insn
;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS
*prev_nop_frag
;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds
;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required
;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since
;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup
*next
;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup
*mips_hi_fixup_list
;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS
*prev_reloc_op_frag
;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map
[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1
[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2
[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map
[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump
;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop
;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f
;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120
;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130
;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k
;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1
;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch
;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes
[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p
;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length
;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes
[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes
[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns
[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning
;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1226 static void append_insn
1227 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1228 bfd_boolean expansionp
);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS
*, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS
*, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS
*, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn
*ip
, char *str
);
1237 static void mips16_macro (struct mips_cl_insn
* ip
);
1238 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1239 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1245 static void my_getExpression (expressionS
*, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type
);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1282 static int relaxed_branch_length (fragS
*, asection
*, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name
; /* CPU or ISA name. */
1292 int flags
; /* MIPS_CPU_* flags. */
1293 int ase
; /* Set of ASEs implemented by the CPU. */
1294 int isa
; /* ISA level. */
1295 int cpu
; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts
= "O::g::G:";
1309 OPTION_MARCH
= OPTION_MD_BASE
,
1333 OPTION_NO_SMARTMIPS
,
1339 OPTION_NO_MICROMIPS
,
1342 OPTION_COMPAT_ARCH_BASE
,
1351 OPTION_M7000_HILO_FIX
,
1352 OPTION_MNO_7000_HILO_FIX
,
1355 OPTION_FIX_LOONGSON2F_JUMP
,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1357 OPTION_FIX_LOONGSON2F_NOP
,
1358 OPTION_NO_FIX_LOONGSON2F_NOP
,
1360 OPTION_NO_FIX_VR4120
,
1362 OPTION_NO_FIX_VR4130
,
1363 OPTION_FIX_CN63XXP1
,
1364 OPTION_NO_FIX_CN63XXP1
,
1371 OPTION_CONSTRUCT_FLOATS
,
1372 OPTION_NO_CONSTRUCT_FLOATS
,
1375 OPTION_RELAX_BRANCH
,
1376 OPTION_NO_RELAX_BRANCH
,
1385 OPTION_SINGLE_FLOAT
,
1386 OPTION_DOUBLE_FLOAT
,
1399 OPTION_MVXWORKS_PIC
,
1404 struct option md_longopts
[] =
1406 /* Options which specify architecture. */
1407 {"march", required_argument
, NULL
, OPTION_MARCH
},
1408 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1409 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1410 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1411 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1412 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1413 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1414 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1415 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1416 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1417 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1418 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1422 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1423 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1424 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1425 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1426 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1427 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1428 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1429 {"mmt", no_argument
, NULL
, OPTION_MT
},
1430 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1431 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1432 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1433 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1434 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1435 {"meva", no_argument
, NULL
, OPTION_EVA
},
1436 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1437 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1438 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1439 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1440 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1441 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1442 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1446 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1447 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1448 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1449 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1450 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1451 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1452 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1456 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1457 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1458 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1459 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1460 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1461 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1462 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1463 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1464 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1465 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1466 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1467 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1468 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1469 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1471 /* Miscellaneous options. */
1472 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1473 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1474 {"break", no_argument
, NULL
, OPTION_BREAK
},
1475 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1476 {"EB", no_argument
, NULL
, OPTION_EB
},
1477 {"EL", no_argument
, NULL
, OPTION_EL
},
1478 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1479 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1480 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1481 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1482 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1483 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1484 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1485 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1486 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1487 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1488 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1489 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1490 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1491 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1492 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1493 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1494 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1495 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument
, NULL
, OPTION_32
},
1502 /* ELF-specific options. */
1503 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1504 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1505 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1506 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1507 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1508 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1509 {"n32", no_argument
, NULL
, OPTION_N32
},
1510 {"64", no_argument
, NULL
, OPTION_64
},
1511 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1512 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1513 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1514 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1515 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1516 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1518 {NULL
, no_argument
, NULL
, 0}
1520 size_t md_longopts_size
= sizeof (md_longopts
);
1522 /* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1527 /* The name of the ASE, used in both the command-line and .set options. */
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64
;
1539 /* The command-line options that turn the ASE on and off. */
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1547 int micromips32_rev
;
1548 int micromips64_rev
;
1551 /* A table of all supported ASEs. */
1552 static const struct mips_ase mips_ases
[] = {
1553 { "dsp", ASE_DSP
, ASE_DSP64
,
1554 OPTION_DSP
, OPTION_NO_DSP
,
1557 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1558 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1561 { "eva", ASE_EVA
, 0,
1562 OPTION_EVA
, OPTION_NO_EVA
,
1565 { "mcu", ASE_MCU
, 0,
1566 OPTION_MCU
, OPTION_NO_MCU
,
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX
, 0,
1571 OPTION_MDMX
, OPTION_NO_MDMX
,
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D
, 0,
1576 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1580 OPTION_MT
, OPTION_NO_MT
,
1583 { "smartmips", ASE_SMARTMIPS
, 0,
1584 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1587 { "virt", ASE_VIRT
, ASE_VIRT64
,
1588 OPTION_VIRT
, OPTION_NO_VIRT
,
1592 /* The set of ASEs that require -mfp64. */
1593 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1595 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1596 static const unsigned int mips_ase_groups
[] = {
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
1617 static const pseudo_typeS mips_pseudo_table
[] =
1619 /* MIPS specific pseudo-ops. */
1620 {"option", s_option
, 0},
1621 {"set", s_mipsset
, 0},
1622 {"rdata", s_change_sec
, 'r'},
1623 {"sdata", s_change_sec
, 's'},
1624 {"livereg", s_ignore
, 0},
1625 {"abicalls", s_abicalls
, 0},
1626 {"cpload", s_cpload
, 0},
1627 {"cpsetup", s_cpsetup
, 0},
1628 {"cplocal", s_cplocal
, 0},
1629 {"cprestore", s_cprestore
, 0},
1630 {"cpreturn", s_cpreturn
, 0},
1631 {"dtprelword", s_dtprelword
, 0},
1632 {"dtpreldword", s_dtpreldword
, 0},
1633 {"tprelword", s_tprelword
, 0},
1634 {"tpreldword", s_tpreldword
, 0},
1635 {"gpvalue", s_gpvalue
, 0},
1636 {"gpword", s_gpword
, 0},
1637 {"gpdword", s_gpdword
, 0},
1638 {"ehword", s_ehword
, 0},
1639 {"cpadd", s_cpadd
, 0},
1640 {"insn", s_insn
, 0},
1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
1645 {"asciiz", stringer
, 8 + 1},
1646 {"bss", s_change_sec
, 'b'},
1648 {"half", s_cons
, 1},
1649 {"dword", s_cons
, 3},
1650 {"weakext", s_mips_weakext
, 0},
1651 {"origin", s_org
, 0},
1652 {"repeat", s_rept
, 0},
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec
, 'B'},
1657 /* These pseudo-ops are defined in read.c, but must be overridden
1658 here for one reason or another. */
1659 {"align", s_align
, 0},
1660 {"byte", s_cons
, 0},
1661 {"data", s_change_sec
, 'd'},
1662 {"double", s_float_cons
, 'd'},
1663 {"float", s_float_cons
, 'f'},
1664 {"globl", s_mips_globl
, 0},
1665 {"global", s_mips_globl
, 0},
1666 {"hword", s_cons
, 1},
1668 {"long", s_cons
, 2},
1669 {"octa", s_cons
, 4},
1670 {"quad", s_cons
, 3},
1671 {"section", s_change_section
, 0},
1672 {"short", s_cons
, 1},
1673 {"single", s_float_cons
, 'f'},
1674 {"stabd", s_mips_stab
, 'd'},
1675 {"stabn", s_mips_stab
, 'n'},
1676 {"stabs", s_mips_stab
, 's'},
1677 {"text", s_change_sec
, 't'},
1678 {"word", s_cons
, 2},
1680 { "extern", ecoff_directive_extern
, 0},
1685 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
1689 {"aent", s_mips_ent
, 1},
1690 {"bgnb", s_ignore
, 0},
1691 {"end", s_mips_end
, 0},
1692 {"endb", s_ignore
, 0},
1693 {"ent", s_mips_ent
, 0},
1694 {"file", s_mips_file
, 0},
1695 {"fmask", s_mips_mask
, 'F'},
1696 {"frame", s_mips_frame
, 0},
1697 {"loc", s_mips_loc
, 0},
1698 {"mask", s_mips_mask
, 'R'},
1699 {"verstamp", s_ignore
, 0},
1703 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1707 mips_address_bytes (void)
1709 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1712 extern void pop_insert (const pseudo_typeS
*);
1715 mips_pop_insert (void)
1717 pop_insert (mips_pseudo_table
);
1718 if (! ECOFF_DEBUGGING
)
1719 pop_insert (mips_nonecoff_pseudo_table
);
1722 /* Symbols labelling the current insn. */
1724 struct insn_label_list
1726 struct insn_label_list
*next
;
1730 static struct insn_label_list
*free_insn_labels
;
1731 #define label_list tc_segment_info_data.labels
1733 static void mips_clear_insn_labels (void);
1734 static void mips_mark_labels (void);
1735 static void mips_compressed_mark_labels (void);
1738 mips_clear_insn_labels (void)
1740 register struct insn_label_list
**pl
;
1741 segment_info_type
*si
;
1745 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1748 si
= seg_info (now_seg
);
1749 *pl
= si
->label_list
;
1750 si
->label_list
= NULL
;
1754 /* Mark instruction labels in MIPS16/microMIPS mode. */
1757 mips_mark_labels (void)
1759 if (HAVE_CODE_COMPRESSION
)
1760 mips_compressed_mark_labels ();
1763 static char *expr_end
;
1765 /* An expression in a macro instruction. This is set by mips_ip and
1768 static expressionS imm_expr
;
1770 /* The relocatable field in an instruction and the relocs associated
1771 with it. These variables are used for instructions like LUI and
1772 JAL as well as true offsets. They are also used for address
1773 operands in macros. */
1775 static expressionS offset_expr
;
1776 static bfd_reloc_code_real_type offset_reloc
[3]
1777 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1779 /* This is set to the resulting size of the instruction to be produced
1780 by mips16_ip if an explicit extension is used or by mips_ip if an
1781 explicit size is supplied. */
1783 static unsigned int forced_insn_length
;
1785 /* True if we are assembling an instruction. All dot symbols defined during
1786 this time should be treated as code labels. */
1788 static bfd_boolean mips_assembling_insn
;
1790 /* The pdr segment for per procedure frame/regmask info. Not used for
1793 static segT pdr_seg
;
1795 /* The default target format to use. */
1797 #if defined (TE_FreeBSD)
1798 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1799 #elif defined (TE_TMIPS)
1800 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1802 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1806 mips_target_format (void)
1808 switch (OUTPUT_FLAVOR
)
1810 case bfd_target_elf_flavour
:
1812 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1813 return (target_big_endian
1814 ? "elf32-bigmips-vxworks"
1815 : "elf32-littlemips-vxworks");
1817 return (target_big_endian
1818 ? (HAVE_64BIT_OBJECTS
1819 ? ELF_TARGET ("elf64-", "big")
1821 ? ELF_TARGET ("elf32-n", "big")
1822 : ELF_TARGET ("elf32-", "big")))
1823 : (HAVE_64BIT_OBJECTS
1824 ? ELF_TARGET ("elf64-", "little")
1826 ? ELF_TARGET ("elf32-n", "little")
1827 : ELF_TARGET ("elf32-", "little"))));
1834 /* Return the ISA revision that is currently in use, or 0 if we are
1835 generating code for MIPS V or below. */
1840 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1843 /* microMIPS implies revision 2 or above. */
1844 if (mips_opts
.micromips
)
1847 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1853 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1856 mips_ase_mask (unsigned int flags
)
1860 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1861 if (flags
& mips_ase_groups
[i
])
1862 flags
|= mips_ase_groups
[i
];
1866 /* Check whether the current ISA supports ASE. Issue a warning if
1870 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1874 static unsigned int warned_isa
;
1875 static unsigned int warned_fp32
;
1877 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1878 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1880 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1881 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1882 && (warned_isa
& ase
->flags
) != ase
->flags
)
1884 warned_isa
|= ase
->flags
;
1885 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1886 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1888 as_warn (_("The %d-bit %s architecture does not support the"
1889 " `%s' extension"), size
, base
, ase
->name
);
1891 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1892 ase
->name
, base
, size
, min_rev
);
1894 if ((ase
->flags
& FP64_ASES
)
1896 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1898 warned_fp32
|= ase
->flags
;
1899 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1903 /* Check all enabled ASEs to see whether they are supported by the
1904 chosen architecture. */
1907 mips_check_isa_supports_ases (void)
1909 unsigned int i
, mask
;
1911 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1913 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1914 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1915 mips_check_isa_supports_ase (&mips_ases
[i
]);
1919 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1920 that were affected. */
1923 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1927 mask
= mips_ase_mask (ase
->flags
);
1928 mips_opts
.ase
&= ~mask
;
1930 mips_opts
.ase
|= ase
->flags
;
1934 /* Return the ASE called NAME, or null if none. */
1936 static const struct mips_ase
*
1937 mips_lookup_ase (const char *name
)
1941 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1942 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1943 return &mips_ases
[i
];
1947 /* Return the length of a microMIPS instruction in bytes. If bits of
1948 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1949 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1950 major opcode) will require further modifications to the opcode
1953 static inline unsigned int
1954 micromips_insn_length (const struct mips_opcode
*mo
)
1956 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1959 /* Return the length of MIPS16 instruction OPCODE. */
1961 static inline unsigned int
1962 mips16_opcode_length (unsigned long opcode
)
1964 return (opcode
>> 16) == 0 ? 2 : 4;
1967 /* Return the length of instruction INSN. */
1969 static inline unsigned int
1970 insn_length (const struct mips_cl_insn
*insn
)
1972 if (mips_opts
.micromips
)
1973 return micromips_insn_length (insn
->insn_mo
);
1974 else if (mips_opts
.mips16
)
1975 return mips16_opcode_length (insn
->insn_opcode
);
1980 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1983 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1988 insn
->insn_opcode
= mo
->match
;
1991 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1992 insn
->fixp
[i
] = NULL
;
1993 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1994 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1995 insn
->mips16_absolute_jump_p
= 0;
1996 insn
->complete_p
= 0;
1997 insn
->cleared_p
= 0;
2000 /* Get a list of all the operands in INSN. */
2002 static const struct mips_operand_array
*
2003 insn_operands (const struct mips_cl_insn
*insn
)
2005 if (insn
->insn_mo
>= &mips_opcodes
[0]
2006 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2007 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2009 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2010 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2011 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2013 if (insn
->insn_mo
>= µmips_opcodes
[0]
2014 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2015 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2020 /* Get a description of operand OPNO of INSN. */
2022 static const struct mips_operand
*
2023 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2025 const struct mips_operand_array
*operands
;
2027 operands
= insn_operands (insn
);
2028 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2030 return operands
->operand
[opno
];
2033 /* Install UVAL as the value of OPERAND in INSN. */
2036 insn_insert_operand (struct mips_cl_insn
*insn
,
2037 const struct mips_operand
*operand
, unsigned int uval
)
2039 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2042 /* Extract the value of OPERAND from INSN. */
2044 static inline unsigned
2045 insn_extract_operand (const struct mips_cl_insn
*insn
,
2046 const struct mips_operand
*operand
)
2048 return mips_extract_operand (operand
, insn
->insn_opcode
);
2051 /* Record the current MIPS16/microMIPS mode in now_seg. */
2054 mips_record_compressed_mode (void)
2056 segment_info_type
*si
;
2058 si
= seg_info (now_seg
);
2059 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2060 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2061 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2062 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2065 /* Read a standard MIPS instruction from BUF. */
2067 static unsigned long
2068 read_insn (char *buf
)
2070 if (target_big_endian
)
2071 return bfd_getb32 ((bfd_byte
*) buf
);
2073 return bfd_getl32 ((bfd_byte
*) buf
);
2076 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2080 write_insn (char *buf
, unsigned int insn
)
2082 md_number_to_chars (buf
, insn
, 4);
2086 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2087 has length LENGTH. */
2089 static unsigned long
2090 read_compressed_insn (char *buf
, unsigned int length
)
2096 for (i
= 0; i
< length
; i
+= 2)
2099 if (target_big_endian
)
2100 insn
|= bfd_getb16 ((char *) buf
);
2102 insn
|= bfd_getl16 ((char *) buf
);
2108 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2109 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2112 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2116 for (i
= 0; i
< length
; i
+= 2)
2117 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2118 return buf
+ length
;
2121 /* Install INSN at the location specified by its "frag" and "where" fields. */
2124 install_insn (const struct mips_cl_insn
*insn
)
2126 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2127 if (HAVE_CODE_COMPRESSION
)
2128 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2130 write_insn (f
, insn
->insn_opcode
);
2131 mips_record_compressed_mode ();
2134 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2135 and install the opcode in the new location. */
2138 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2143 insn
->where
= where
;
2144 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2145 if (insn
->fixp
[i
] != NULL
)
2147 insn
->fixp
[i
]->fx_frag
= frag
;
2148 insn
->fixp
[i
]->fx_where
= where
;
2150 install_insn (insn
);
2153 /* Add INSN to the end of the output. */
2156 add_fixed_insn (struct mips_cl_insn
*insn
)
2158 char *f
= frag_more (insn_length (insn
));
2159 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2162 /* Start a variant frag and move INSN to the start of the variant part,
2163 marking it as fixed. The other arguments are as for frag_var. */
2166 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2167 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2169 frag_grow (max_chars
);
2170 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2172 frag_var (rs_machine_dependent
, max_chars
, var
,
2173 subtype
, symbol
, offset
, NULL
);
2176 /* Insert N copies of INSN into the history buffer, starting at
2177 position FIRST. Neither FIRST nor N need to be clipped. */
2180 insert_into_history (unsigned int first
, unsigned int n
,
2181 const struct mips_cl_insn
*insn
)
2183 if (mips_relax
.sequence
!= 2)
2187 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2189 history
[i
] = history
[i
- n
];
2195 /* Clear the error in insn_error. */
2198 clear_insn_error (void)
2200 memset (&insn_error
, 0, sizeof (insn_error
));
2203 /* Possibly record error message MSG for the current instruction.
2204 If the error is about a particular argument, ARGNUM is the 1-based
2205 number of that argument, otherwise it is 0. FORMAT is the format
2206 of MSG. Return true if MSG was used, false if the current message
2210 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2215 /* Give priority to errors against specific arguments, and to
2216 the first whole-instruction message. */
2222 /* Keep insn_error if it is against a later argument. */
2223 if (argnum
< insn_error
.min_argnum
)
2226 /* If both errors are against the same argument but are different,
2227 give up on reporting a specific error for this argument.
2228 See the comment about mips_insn_error for details. */
2229 if (argnum
== insn_error
.min_argnum
2231 && strcmp (insn_error
.msg
, msg
) != 0)
2234 insn_error
.min_argnum
+= 1;
2238 insn_error
.min_argnum
= argnum
;
2239 insn_error
.format
= format
;
2240 insn_error
.msg
= msg
;
2244 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2245 as for set_insn_error_format. */
2248 set_insn_error (int argnum
, const char *msg
)
2250 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2253 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2254 as for set_insn_error_format. */
2257 set_insn_error_i (int argnum
, const char *msg
, int i
)
2259 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2263 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2264 are as for set_insn_error_format. */
2267 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2269 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2271 insn_error
.u
.ss
[0] = s1
;
2272 insn_error
.u
.ss
[1] = s2
;
2276 /* Report the error in insn_error, which is against assembly code STR. */
2279 report_insn_error (const char *str
)
2283 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2284 switch (insn_error
.format
)
2291 as_bad (msg
, insn_error
.u
.i
, str
);
2295 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2300 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2301 the idea is to make it obvious at a glance that each errata is
2305 init_vr4120_conflicts (void)
2307 #define CONFLICT(FIRST, SECOND) \
2308 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2310 /* Errata 21 - [D]DIV[U] after [D]MACC */
2311 CONFLICT (MACC
, DIV
);
2312 CONFLICT (DMACC
, DIV
);
2314 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2315 CONFLICT (DMULT
, DMULT
);
2316 CONFLICT (DMULT
, DMACC
);
2317 CONFLICT (DMACC
, DMULT
);
2318 CONFLICT (DMACC
, DMACC
);
2320 /* Errata 24 - MT{LO,HI} after [D]MACC */
2321 CONFLICT (MACC
, MTHILO
);
2322 CONFLICT (DMACC
, MTHILO
);
2324 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2325 instruction is executed immediately after a MACC or DMACC
2326 instruction, the result of [either instruction] is incorrect." */
2327 CONFLICT (MACC
, MULT
);
2328 CONFLICT (MACC
, DMULT
);
2329 CONFLICT (DMACC
, MULT
);
2330 CONFLICT (DMACC
, DMULT
);
2332 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2333 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2334 DDIV or DDIVU instruction, the result of the MACC or
2335 DMACC instruction is incorrect.". */
2336 CONFLICT (DMULT
, MACC
);
2337 CONFLICT (DMULT
, DMACC
);
2338 CONFLICT (DIV
, MACC
);
2339 CONFLICT (DIV
, DMACC
);
2349 #define RNUM_MASK 0x00000ff
2350 #define RTYPE_MASK 0x0efff00
2351 #define RTYPE_NUM 0x0000100
2352 #define RTYPE_FPU 0x0000200
2353 #define RTYPE_FCC 0x0000400
2354 #define RTYPE_VEC 0x0000800
2355 #define RTYPE_GP 0x0001000
2356 #define RTYPE_CP0 0x0002000
2357 #define RTYPE_PC 0x0004000
2358 #define RTYPE_ACC 0x0008000
2359 #define RTYPE_CCC 0x0010000
2360 #define RTYPE_VI 0x0020000
2361 #define RTYPE_VF 0x0040000
2362 #define RTYPE_R5900_I 0x0080000
2363 #define RTYPE_R5900_Q 0x0100000
2364 #define RTYPE_R5900_R 0x0200000
2365 #define RTYPE_R5900_ACC 0x0400000
2366 #define RWARN 0x8000000
2368 #define GENERIC_REGISTER_NUMBERS \
2369 {"$0", RTYPE_NUM | 0}, \
2370 {"$1", RTYPE_NUM | 1}, \
2371 {"$2", RTYPE_NUM | 2}, \
2372 {"$3", RTYPE_NUM | 3}, \
2373 {"$4", RTYPE_NUM | 4}, \
2374 {"$5", RTYPE_NUM | 5}, \
2375 {"$6", RTYPE_NUM | 6}, \
2376 {"$7", RTYPE_NUM | 7}, \
2377 {"$8", RTYPE_NUM | 8}, \
2378 {"$9", RTYPE_NUM | 9}, \
2379 {"$10", RTYPE_NUM | 10}, \
2380 {"$11", RTYPE_NUM | 11}, \
2381 {"$12", RTYPE_NUM | 12}, \
2382 {"$13", RTYPE_NUM | 13}, \
2383 {"$14", RTYPE_NUM | 14}, \
2384 {"$15", RTYPE_NUM | 15}, \
2385 {"$16", RTYPE_NUM | 16}, \
2386 {"$17", RTYPE_NUM | 17}, \
2387 {"$18", RTYPE_NUM | 18}, \
2388 {"$19", RTYPE_NUM | 19}, \
2389 {"$20", RTYPE_NUM | 20}, \
2390 {"$21", RTYPE_NUM | 21}, \
2391 {"$22", RTYPE_NUM | 22}, \
2392 {"$23", RTYPE_NUM | 23}, \
2393 {"$24", RTYPE_NUM | 24}, \
2394 {"$25", RTYPE_NUM | 25}, \
2395 {"$26", RTYPE_NUM | 26}, \
2396 {"$27", RTYPE_NUM | 27}, \
2397 {"$28", RTYPE_NUM | 28}, \
2398 {"$29", RTYPE_NUM | 29}, \
2399 {"$30", RTYPE_NUM | 30}, \
2400 {"$31", RTYPE_NUM | 31}
2402 #define FPU_REGISTER_NAMES \
2403 {"$f0", RTYPE_FPU | 0}, \
2404 {"$f1", RTYPE_FPU | 1}, \
2405 {"$f2", RTYPE_FPU | 2}, \
2406 {"$f3", RTYPE_FPU | 3}, \
2407 {"$f4", RTYPE_FPU | 4}, \
2408 {"$f5", RTYPE_FPU | 5}, \
2409 {"$f6", RTYPE_FPU | 6}, \
2410 {"$f7", RTYPE_FPU | 7}, \
2411 {"$f8", RTYPE_FPU | 8}, \
2412 {"$f9", RTYPE_FPU | 9}, \
2413 {"$f10", RTYPE_FPU | 10}, \
2414 {"$f11", RTYPE_FPU | 11}, \
2415 {"$f12", RTYPE_FPU | 12}, \
2416 {"$f13", RTYPE_FPU | 13}, \
2417 {"$f14", RTYPE_FPU | 14}, \
2418 {"$f15", RTYPE_FPU | 15}, \
2419 {"$f16", RTYPE_FPU | 16}, \
2420 {"$f17", RTYPE_FPU | 17}, \
2421 {"$f18", RTYPE_FPU | 18}, \
2422 {"$f19", RTYPE_FPU | 19}, \
2423 {"$f20", RTYPE_FPU | 20}, \
2424 {"$f21", RTYPE_FPU | 21}, \
2425 {"$f22", RTYPE_FPU | 22}, \
2426 {"$f23", RTYPE_FPU | 23}, \
2427 {"$f24", RTYPE_FPU | 24}, \
2428 {"$f25", RTYPE_FPU | 25}, \
2429 {"$f26", RTYPE_FPU | 26}, \
2430 {"$f27", RTYPE_FPU | 27}, \
2431 {"$f28", RTYPE_FPU | 28}, \
2432 {"$f29", RTYPE_FPU | 29}, \
2433 {"$f30", RTYPE_FPU | 30}, \
2434 {"$f31", RTYPE_FPU | 31}
2436 #define FPU_CONDITION_CODE_NAMES \
2437 {"$fcc0", RTYPE_FCC | 0}, \
2438 {"$fcc1", RTYPE_FCC | 1}, \
2439 {"$fcc2", RTYPE_FCC | 2}, \
2440 {"$fcc3", RTYPE_FCC | 3}, \
2441 {"$fcc4", RTYPE_FCC | 4}, \
2442 {"$fcc5", RTYPE_FCC | 5}, \
2443 {"$fcc6", RTYPE_FCC | 6}, \
2444 {"$fcc7", RTYPE_FCC | 7}
2446 #define COPROC_CONDITION_CODE_NAMES \
2447 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2448 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2449 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2450 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2451 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2452 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2453 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2454 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2456 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2457 {"$a4", RTYPE_GP | 8}, \
2458 {"$a5", RTYPE_GP | 9}, \
2459 {"$a6", RTYPE_GP | 10}, \
2460 {"$a7", RTYPE_GP | 11}, \
2461 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2462 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2463 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2464 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2465 {"$t0", RTYPE_GP | 12}, \
2466 {"$t1", RTYPE_GP | 13}, \
2467 {"$t2", RTYPE_GP | 14}, \
2468 {"$t3", RTYPE_GP | 15}
2470 #define O32_SYMBOLIC_REGISTER_NAMES \
2471 {"$t0", RTYPE_GP | 8}, \
2472 {"$t1", RTYPE_GP | 9}, \
2473 {"$t2", RTYPE_GP | 10}, \
2474 {"$t3", RTYPE_GP | 11}, \
2475 {"$t4", RTYPE_GP | 12}, \
2476 {"$t5", RTYPE_GP | 13}, \
2477 {"$t6", RTYPE_GP | 14}, \
2478 {"$t7", RTYPE_GP | 15}, \
2479 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2480 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2481 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2482 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2484 /* Remaining symbolic register names */
2485 #define SYMBOLIC_REGISTER_NAMES \
2486 {"$zero", RTYPE_GP | 0}, \
2487 {"$at", RTYPE_GP | 1}, \
2488 {"$AT", RTYPE_GP | 1}, \
2489 {"$v0", RTYPE_GP | 2}, \
2490 {"$v1", RTYPE_GP | 3}, \
2491 {"$a0", RTYPE_GP | 4}, \
2492 {"$a1", RTYPE_GP | 5}, \
2493 {"$a2", RTYPE_GP | 6}, \
2494 {"$a3", RTYPE_GP | 7}, \
2495 {"$s0", RTYPE_GP | 16}, \
2496 {"$s1", RTYPE_GP | 17}, \
2497 {"$s2", RTYPE_GP | 18}, \
2498 {"$s3", RTYPE_GP | 19}, \
2499 {"$s4", RTYPE_GP | 20}, \
2500 {"$s5", RTYPE_GP | 21}, \
2501 {"$s6", RTYPE_GP | 22}, \
2502 {"$s7", RTYPE_GP | 23}, \
2503 {"$t8", RTYPE_GP | 24}, \
2504 {"$t9", RTYPE_GP | 25}, \
2505 {"$k0", RTYPE_GP | 26}, \
2506 {"$kt0", RTYPE_GP | 26}, \
2507 {"$k1", RTYPE_GP | 27}, \
2508 {"$kt1", RTYPE_GP | 27}, \
2509 {"$gp", RTYPE_GP | 28}, \
2510 {"$sp", RTYPE_GP | 29}, \
2511 {"$s8", RTYPE_GP | 30}, \
2512 {"$fp", RTYPE_GP | 30}, \
2513 {"$ra", RTYPE_GP | 31}
2515 #define MIPS16_SPECIAL_REGISTER_NAMES \
2516 {"$pc", RTYPE_PC | 0}
2518 #define MDMX_VECTOR_REGISTER_NAMES \
2519 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2520 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2521 {"$v2", RTYPE_VEC | 2}, \
2522 {"$v3", RTYPE_VEC | 3}, \
2523 {"$v4", RTYPE_VEC | 4}, \
2524 {"$v5", RTYPE_VEC | 5}, \
2525 {"$v6", RTYPE_VEC | 6}, \
2526 {"$v7", RTYPE_VEC | 7}, \
2527 {"$v8", RTYPE_VEC | 8}, \
2528 {"$v9", RTYPE_VEC | 9}, \
2529 {"$v10", RTYPE_VEC | 10}, \
2530 {"$v11", RTYPE_VEC | 11}, \
2531 {"$v12", RTYPE_VEC | 12}, \
2532 {"$v13", RTYPE_VEC | 13}, \
2533 {"$v14", RTYPE_VEC | 14}, \
2534 {"$v15", RTYPE_VEC | 15}, \
2535 {"$v16", RTYPE_VEC | 16}, \
2536 {"$v17", RTYPE_VEC | 17}, \
2537 {"$v18", RTYPE_VEC | 18}, \
2538 {"$v19", RTYPE_VEC | 19}, \
2539 {"$v20", RTYPE_VEC | 20}, \
2540 {"$v21", RTYPE_VEC | 21}, \
2541 {"$v22", RTYPE_VEC | 22}, \
2542 {"$v23", RTYPE_VEC | 23}, \
2543 {"$v24", RTYPE_VEC | 24}, \
2544 {"$v25", RTYPE_VEC | 25}, \
2545 {"$v26", RTYPE_VEC | 26}, \
2546 {"$v27", RTYPE_VEC | 27}, \
2547 {"$v28", RTYPE_VEC | 28}, \
2548 {"$v29", RTYPE_VEC | 29}, \
2549 {"$v30", RTYPE_VEC | 30}, \
2550 {"$v31", RTYPE_VEC | 31}
2552 #define R5900_I_NAMES \
2553 {"$I", RTYPE_R5900_I | 0}
2555 #define R5900_Q_NAMES \
2556 {"$Q", RTYPE_R5900_Q | 0}
2558 #define R5900_R_NAMES \
2559 {"$R", RTYPE_R5900_R | 0}
2561 #define R5900_ACC_NAMES \
2562 {"$ACC", RTYPE_R5900_ACC | 0 }
2564 #define MIPS_DSP_ACCUMULATOR_NAMES \
2565 {"$ac0", RTYPE_ACC | 0}, \
2566 {"$ac1", RTYPE_ACC | 1}, \
2567 {"$ac2", RTYPE_ACC | 2}, \
2568 {"$ac3", RTYPE_ACC | 3}
2570 static const struct regname reg_names
[] = {
2571 GENERIC_REGISTER_NUMBERS
,
2573 FPU_CONDITION_CODE_NAMES
,
2574 COPROC_CONDITION_CODE_NAMES
,
2576 /* The $txx registers depends on the abi,
2577 these will be added later into the symbol table from
2578 one of the tables below once mips_abi is set after
2579 parsing of arguments from the command line. */
2580 SYMBOLIC_REGISTER_NAMES
,
2582 MIPS16_SPECIAL_REGISTER_NAMES
,
2583 MDMX_VECTOR_REGISTER_NAMES
,
2588 MIPS_DSP_ACCUMULATOR_NAMES
,
2592 static const struct regname reg_names_o32
[] = {
2593 O32_SYMBOLIC_REGISTER_NAMES
,
2597 static const struct regname reg_names_n32n64
[] = {
2598 N32N64_SYMBOLIC_REGISTER_NAMES
,
2602 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2603 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2604 of these register symbols, return the associated vector register,
2605 otherwise return SYMVAL itself. */
2608 mips_prefer_vec_regno (unsigned int symval
)
2610 if ((symval
& -2) == (RTYPE_GP
| 2))
2611 return RTYPE_VEC
| (symval
& 1);
2615 /* Return true if string [S, E) is a valid register name, storing its
2616 symbol value in *SYMVAL_PTR if so. */
2619 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2624 /* Terminate name. */
2628 /* Look up the name. */
2629 symbol
= symbol_find (s
);
2632 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2635 *symval_ptr
= S_GET_VALUE (symbol
);
2639 /* Return true if the string at *SPTR is a valid register name. Allow it
2640 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2643 When returning true, move *SPTR past the register, store the
2644 register's symbol value in *SYMVAL_PTR and the channel mask in
2645 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2646 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2647 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2650 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2651 unsigned int *channels_ptr
)
2655 unsigned int channels
, symval
, bit
;
2657 /* Find end of name. */
2659 if (is_name_beginner (*e
))
2661 while (is_part_of_name (*e
))
2665 if (!mips_parse_register_1 (s
, e
, &symval
))
2670 /* Eat characters from the end of the string that are valid
2671 channel suffixes. The preceding register must be $ACC or
2672 end with a digit, so there is no ambiguity. */
2675 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2676 if (m
> s
&& m
[-1] == *q
)
2683 || !mips_parse_register_1 (s
, m
, &symval
)
2684 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2689 *symval_ptr
= symval
;
2691 *channels_ptr
= channels
;
2695 /* Check if SPTR points at a valid register specifier according to TYPES.
2696 If so, then return 1, advance S to consume the specifier and store
2697 the register's number in REGNOP, otherwise return 0. */
2700 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2704 if (mips_parse_register (s
, ®no
, NULL
))
2706 if (types
& RTYPE_VEC
)
2707 regno
= mips_prefer_vec_regno (regno
);
2716 as_warn (_("Unrecognized register name `%s'"), *s
);
2721 return regno
<= RNUM_MASK
;
2724 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2725 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2728 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2733 for (i
= 0; i
< 4; i
++)
2734 if (*s
== "xyzw"[i
])
2736 *channels
|= 1 << (3 - i
);
2742 /* Token types for parsed operand lists. */
2743 enum mips_operand_token_type
{
2744 /* A plain register, e.g. $f2. */
2747 /* A 4-bit XYZW channel mask. */
2750 /* An element of a vector, e.g. $v0[1]. */
2753 /* A continuous range of registers, e.g. $s0-$s4. */
2756 /* A (possibly relocated) expression. */
2759 /* A floating-point value. */
2762 /* A single character. This can be '(', ')' or ',', but '(' only appears
2766 /* A doubled character, either "--" or "++". */
2769 /* The end of the operand list. */
2773 /* A parsed operand token. */
2774 struct mips_operand_token
2776 /* The type of token. */
2777 enum mips_operand_token_type type
;
2780 /* The register symbol value for an OT_REG. */
2783 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2784 unsigned int channels
;
2786 /* The register symbol value and index for an OT_REG_ELEMENT. */
2792 /* The two register symbol values involved in an OT_REG_RANGE. */
2794 unsigned int regno1
;
2795 unsigned int regno2
;
2798 /* The value of an OT_INTEGER. The value is represented as an
2799 expression and the relocation operators that were applied to
2800 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2801 relocation operators were used. */
2804 bfd_reloc_code_real_type relocs
[3];
2807 /* The binary data for an OT_FLOAT constant, and the number of bytes
2810 unsigned char data
[8];
2814 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2819 /* An obstack used to construct lists of mips_operand_tokens. */
2820 static struct obstack mips_operand_tokens
;
2822 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2825 mips_add_token (struct mips_operand_token
*token
,
2826 enum mips_operand_token_type type
)
2829 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2832 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2833 and OT_REG tokens for them if so, and return a pointer to the first
2834 unconsumed character. Return null otherwise. */
2837 mips_parse_base_start (char *s
)
2839 struct mips_operand_token token
;
2840 unsigned int regno
, channels
;
2841 bfd_boolean decrement_p
;
2847 SKIP_SPACE_TABS (s
);
2849 /* Only match "--" as part of a base expression. In other contexts "--X"
2850 is a double negative. */
2851 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2855 SKIP_SPACE_TABS (s
);
2858 /* Allow a channel specifier because that leads to better error messages
2859 than treating something like "$vf0x++" as an expression. */
2860 if (!mips_parse_register (&s
, ®no
, &channels
))
2864 mips_add_token (&token
, OT_CHAR
);
2869 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2872 token
.u
.regno
= regno
;
2873 mips_add_token (&token
, OT_REG
);
2877 token
.u
.channels
= channels
;
2878 mips_add_token (&token
, OT_CHANNELS
);
2881 /* For consistency, only match "++" as part of base expressions too. */
2882 SKIP_SPACE_TABS (s
);
2883 if (s
[0] == '+' && s
[1] == '+')
2887 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2893 /* Parse one or more tokens from S. Return a pointer to the first
2894 unconsumed character on success. Return null if an error was found
2895 and store the error text in insn_error. FLOAT_FORMAT is as for
2896 mips_parse_arguments. */
2899 mips_parse_argument_token (char *s
, char float_format
)
2901 char *end
, *save_in
, *err
;
2902 unsigned int regno1
, regno2
, channels
;
2903 struct mips_operand_token token
;
2905 /* First look for "($reg", since we want to treat that as an
2906 OT_CHAR and OT_REG rather than an expression. */
2907 end
= mips_parse_base_start (s
);
2911 /* Handle other characters that end up as OT_CHARs. */
2912 if (*s
== ')' || *s
== ',')
2915 mips_add_token (&token
, OT_CHAR
);
2920 /* Handle tokens that start with a register. */
2921 if (mips_parse_register (&s
, ®no1
, &channels
))
2925 /* A register and a VU0 channel suffix. */
2926 token
.u
.regno
= regno1
;
2927 mips_add_token (&token
, OT_REG
);
2929 token
.u
.channels
= channels
;
2930 mips_add_token (&token
, OT_CHANNELS
);
2934 SKIP_SPACE_TABS (s
);
2937 /* A register range. */
2939 SKIP_SPACE_TABS (s
);
2940 if (!mips_parse_register (&s
, ®no2
, NULL
))
2942 set_insn_error (0, _("Invalid register range"));
2946 token
.u
.reg_range
.regno1
= regno1
;
2947 token
.u
.reg_range
.regno2
= regno2
;
2948 mips_add_token (&token
, OT_REG_RANGE
);
2953 /* A vector element. */
2954 expressionS element
;
2957 SKIP_SPACE_TABS (s
);
2958 my_getExpression (&element
, s
);
2959 if (element
.X_op
!= O_constant
)
2961 set_insn_error (0, _("Vector element must be constant"));
2965 SKIP_SPACE_TABS (s
);
2968 set_insn_error (0, _("Missing `]'"));
2973 token
.u
.reg_element
.regno
= regno1
;
2974 token
.u
.reg_element
.index
= element
.X_add_number
;
2975 mips_add_token (&token
, OT_REG_ELEMENT
);
2979 /* Looks like just a plain register. */
2980 token
.u
.regno
= regno1
;
2981 mips_add_token (&token
, OT_REG
);
2987 /* First try to treat expressions as floats. */
2988 save_in
= input_line_pointer
;
2989 input_line_pointer
= s
;
2990 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2991 &token
.u
.flt
.length
);
2992 end
= input_line_pointer
;
2993 input_line_pointer
= save_in
;
2996 set_insn_error (0, err
);
3001 mips_add_token (&token
, OT_FLOAT
);
3006 /* Treat everything else as an integer expression. */
3007 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3008 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3009 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3010 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3012 mips_add_token (&token
, OT_INTEGER
);
3016 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3017 if expressions should be treated as 32-bit floating-point constants,
3018 'd' if they should be treated as 64-bit floating-point constants,
3019 or 0 if they should be treated as integer expressions (the usual case).
3021 Return a list of tokens on success, otherwise return 0. The caller
3022 must obstack_free the list after use. */
3024 static struct mips_operand_token
*
3025 mips_parse_arguments (char *s
, char float_format
)
3027 struct mips_operand_token token
;
3029 SKIP_SPACE_TABS (s
);
3032 s
= mips_parse_argument_token (s
, float_format
);
3035 obstack_free (&mips_operand_tokens
,
3036 obstack_finish (&mips_operand_tokens
));
3039 SKIP_SPACE_TABS (s
);
3041 mips_add_token (&token
, OT_END
);
3042 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3045 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3046 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3049 is_opcode_valid (const struct mips_opcode
*mo
)
3051 int isa
= mips_opts
.isa
;
3052 int ase
= mips_opts
.ase
;
3056 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3057 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3058 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3059 ase
|= mips_ases
[i
].flags64
;
3061 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3064 /* Check whether the instruction or macro requires single-precision or
3065 double-precision floating-point support. Note that this information is
3066 stored differently in the opcode table for insns and macros. */
3067 if (mo
->pinfo
== INSN_MACRO
)
3069 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3070 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3074 fp_s
= mo
->pinfo
& FP_S
;
3075 fp_d
= mo
->pinfo
& FP_D
;
3078 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3081 if (fp_s
&& mips_opts
.soft_float
)
3087 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3088 selected ISA and architecture. */
3091 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3093 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3096 /* Return TRUE if the size of the microMIPS opcode MO matches one
3097 explicitly requested. Always TRUE in the standard MIPS mode. */
3100 is_size_valid (const struct mips_opcode
*mo
)
3102 if (!mips_opts
.micromips
)
3105 if (mips_opts
.insn32
)
3107 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3109 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3112 if (!forced_insn_length
)
3114 if (mo
->pinfo
== INSN_MACRO
)
3116 return forced_insn_length
== micromips_insn_length (mo
);
3119 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3120 of the preceding instruction. Always TRUE in the standard MIPS mode.
3122 We don't accept macros in 16-bit delay slots to avoid a case where
3123 a macro expansion fails because it relies on a preceding 32-bit real
3124 instruction to have matched and does not handle the operands correctly.
3125 The only macros that may expand to 16-bit instructions are JAL that
3126 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3127 and BGT (that likewise cannot be placed in a delay slot) that decay to
3128 a NOP. In all these cases the macros precede any corresponding real
3129 instruction definitions in the opcode table, so they will match in the
3130 second pass where the size of the delay slot is ignored and therefore
3131 produce correct code. */
3134 is_delay_slot_valid (const struct mips_opcode
*mo
)
3136 if (!mips_opts
.micromips
)
3139 if (mo
->pinfo
== INSN_MACRO
)
3140 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3141 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3142 && micromips_insn_length (mo
) != 4)
3144 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3145 && micromips_insn_length (mo
) != 2)
3151 /* For consistency checking, verify that all bits of OPCODE are specified
3152 either by the match/mask part of the instruction definition, or by the
3153 operand list. Also build up a list of operands in OPERANDS.
3155 INSN_BITS says which bits of the instruction are significant.
3156 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3157 provides the mips_operand description of each operand. DECODE_OPERAND
3158 is null for MIPS16 instructions. */
3161 validate_mips_insn (const struct mips_opcode
*opcode
,
3162 unsigned long insn_bits
,
3163 const struct mips_operand
*(*decode_operand
) (const char *),
3164 struct mips_operand_array
*operands
)
3167 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3168 const struct mips_operand
*operand
;
3170 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3171 if ((mask
& opcode
->match
) != opcode
->match
)
3173 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3174 opcode
->name
, opcode
->args
);
3179 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3180 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3181 for (s
= opcode
->args
; *s
; ++s
)
3194 if (!decode_operand
)
3195 operand
= decode_mips16_operand (*s
, FALSE
);
3197 operand
= decode_operand (s
);
3198 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3200 as_bad (_("internal: unknown operand type: %s %s"),
3201 opcode
->name
, opcode
->args
);
3204 gas_assert (opno
< MAX_OPERANDS
);
3205 operands
->operand
[opno
] = operand
;
3206 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3208 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3209 if (operand
->type
== OP_MDMX_IMM_REG
)
3210 /* Bit 5 is the format selector (OB vs QH). The opcode table
3211 has separate entries for each format. */
3212 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3213 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3214 used_bits
&= ~(mask
& 0x700);
3216 /* Skip prefix characters. */
3217 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3222 doubled
= used_bits
& mask
& insn_bits
;
3225 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3226 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3230 undefined
= ~used_bits
& insn_bits
;
3231 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3233 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3234 undefined
, opcode
->name
, opcode
->args
);
3237 used_bits
&= ~insn_bits
;
3240 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3241 used_bits
, opcode
->name
, opcode
->args
);
3247 /* The MIPS16 version of validate_mips_insn. */
3250 validate_mips16_insn (const struct mips_opcode
*opcode
,
3251 struct mips_operand_array
*operands
)
3253 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3255 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3256 instruction. Use TMP to describe the full instruction. */
3257 struct mips_opcode tmp
;
3262 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3264 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3267 /* The microMIPS version of validate_mips_insn. */
3270 validate_micromips_insn (const struct mips_opcode
*opc
,
3271 struct mips_operand_array
*operands
)
3273 unsigned long insn_bits
;
3274 unsigned long major
;
3275 unsigned int length
;
3277 if (opc
->pinfo
== INSN_MACRO
)
3278 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3281 length
= micromips_insn_length (opc
);
3282 if (length
!= 2 && length
!= 4)
3284 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3285 "%s %s"), length
, opc
->name
, opc
->args
);
3288 major
= opc
->match
>> (10 + 8 * (length
- 2));
3289 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3290 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3292 as_bad (_("Internal error: bad microMIPS opcode "
3293 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3297 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3298 insn_bits
= 1 << 4 * length
;
3299 insn_bits
<<= 4 * length
;
3301 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3305 /* This function is called once, at assembler startup time. It should set up
3306 all the tables, etc. that the MD part of the assembler will need. */
3311 const char *retval
= NULL
;
3315 if (mips_pic
!= NO_PIC
)
3317 if (g_switch_seen
&& g_switch_value
!= 0)
3318 as_bad (_("-G may not be used in position-independent code"));
3322 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3323 as_warn (_("Could not set architecture and machine"));
3325 op_hash
= hash_new ();
3327 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3328 for (i
= 0; i
< NUMOPCODES
;)
3330 const char *name
= mips_opcodes
[i
].name
;
3332 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3335 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3336 mips_opcodes
[i
].name
, retval
);
3337 /* Probably a memory allocation problem? Give up now. */
3338 as_fatal (_("Broken assembler. No assembly attempted."));
3342 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3343 decode_mips_operand
, &mips_operands
[i
]))
3345 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3347 create_insn (&nop_insn
, mips_opcodes
+ i
);
3348 if (mips_fix_loongson2f_nop
)
3349 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3350 nop_insn
.fixed_p
= 1;
3354 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3357 mips16_op_hash
= hash_new ();
3358 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3359 bfd_mips16_num_opcodes
);
3362 while (i
< bfd_mips16_num_opcodes
)
3364 const char *name
= mips16_opcodes
[i
].name
;
3366 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3368 as_fatal (_("internal: can't hash `%s': %s"),
3369 mips16_opcodes
[i
].name
, retval
);
3372 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3374 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3376 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3377 mips16_nop_insn
.fixed_p
= 1;
3381 while (i
< bfd_mips16_num_opcodes
3382 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3385 micromips_op_hash
= hash_new ();
3386 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3387 bfd_micromips_num_opcodes
);
3390 while (i
< bfd_micromips_num_opcodes
)
3392 const char *name
= micromips_opcodes
[i
].name
;
3394 retval
= hash_insert (micromips_op_hash
, name
,
3395 (void *) µmips_opcodes
[i
]);
3397 as_fatal (_("internal: can't hash `%s': %s"),
3398 micromips_opcodes
[i
].name
, retval
);
3401 struct mips_cl_insn
*micromips_nop_insn
;
3403 if (!validate_micromips_insn (µmips_opcodes
[i
],
3404 µmips_operands
[i
]))
3407 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3409 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3410 micromips_nop_insn
= µmips_nop16_insn
;
3411 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3412 micromips_nop_insn
= µmips_nop32_insn
;
3416 if (micromips_nop_insn
->insn_mo
== NULL
3417 && strcmp (name
, "nop") == 0)
3419 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3420 micromips_nop_insn
->fixed_p
= 1;
3424 while (++i
< bfd_micromips_num_opcodes
3425 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3429 as_fatal (_("Broken assembler. No assembly attempted."));
3431 /* We add all the general register names to the symbol table. This
3432 helps us detect invalid uses of them. */
3433 for (i
= 0; reg_names
[i
].name
; i
++)
3434 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3435 reg_names
[i
].num
, /* & RNUM_MASK, */
3436 &zero_address_frag
));
3438 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3439 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3440 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3441 &zero_address_frag
));
3443 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3444 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3445 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3446 &zero_address_frag
));
3448 for (i
= 0; i
< 32; i
++)
3452 /* R5900 VU0 floating-point register. */
3453 regname
[sizeof (rename
) - 1] = 0;
3454 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3455 symbol_table_insert (symbol_new (regname
, reg_section
,
3456 RTYPE_VF
| i
, &zero_address_frag
));
3458 /* R5900 VU0 integer register. */
3459 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3460 symbol_table_insert (symbol_new (regname
, reg_section
,
3461 RTYPE_VI
| i
, &zero_address_frag
));
3465 obstack_init (&mips_operand_tokens
);
3467 mips_no_prev_insn ();
3470 mips_cprmask
[0] = 0;
3471 mips_cprmask
[1] = 0;
3472 mips_cprmask
[2] = 0;
3473 mips_cprmask
[3] = 0;
3475 /* set the default alignment for the text section (2**2) */
3476 record_alignment (text_section
, 2);
3478 bfd_set_gp_size (stdoutput
, g_switch_value
);
3480 /* On a native system other than VxWorks, sections must be aligned
3481 to 16 byte boundaries. When configured for an embedded ELF
3482 target, we don't bother. */
3483 if (strncmp (TARGET_OS
, "elf", 3) != 0
3484 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3486 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3487 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3488 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3491 /* Create a .reginfo section for register masks and a .mdebug
3492 section for debugging information. */
3500 subseg
= now_subseg
;
3502 /* The ABI says this section should be loaded so that the
3503 running program can access it. However, we don't load it
3504 if we are configured for an embedded target */
3505 flags
= SEC_READONLY
| SEC_DATA
;
3506 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3507 flags
|= SEC_ALLOC
| SEC_LOAD
;
3509 if (mips_abi
!= N64_ABI
)
3511 sec
= subseg_new (".reginfo", (subsegT
) 0);
3513 bfd_set_section_flags (stdoutput
, sec
, flags
);
3514 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3516 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3520 /* The 64-bit ABI uses a .MIPS.options section rather than
3521 .reginfo section. */
3522 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3523 bfd_set_section_flags (stdoutput
, sec
, flags
);
3524 bfd_set_section_alignment (stdoutput
, sec
, 3);
3526 /* Set up the option header. */
3528 Elf_Internal_Options opthdr
;
3531 opthdr
.kind
= ODK_REGINFO
;
3532 opthdr
.size
= (sizeof (Elf_External_Options
)
3533 + sizeof (Elf64_External_RegInfo
));
3536 f
= frag_more (sizeof (Elf_External_Options
));
3537 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3538 (Elf_External_Options
*) f
);
3540 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3544 if (ECOFF_DEBUGGING
)
3546 sec
= subseg_new (".mdebug", (subsegT
) 0);
3547 (void) bfd_set_section_flags (stdoutput
, sec
,
3548 SEC_HAS_CONTENTS
| SEC_READONLY
);
3549 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3551 else if (mips_flag_pdr
)
3553 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3554 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3555 SEC_READONLY
| SEC_RELOC
3557 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3560 subseg_set (seg
, subseg
);
3563 if (! ECOFF_DEBUGGING
)
3566 if (mips_fix_vr4120
)
3567 init_vr4120_conflicts ();
3573 mips_emit_delays ();
3574 if (! ECOFF_DEBUGGING
)
3579 md_assemble (char *str
)
3581 struct mips_cl_insn insn
;
3582 bfd_reloc_code_real_type unused_reloc
[3]
3583 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3585 imm_expr
.X_op
= O_absent
;
3586 offset_expr
.X_op
= O_absent
;
3587 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3588 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3589 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3591 mips_mark_labels ();
3592 mips_assembling_insn
= TRUE
;
3593 clear_insn_error ();
3595 if (mips_opts
.mips16
)
3596 mips16_ip (str
, &insn
);
3599 mips_ip (str
, &insn
);
3600 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3601 str
, insn
.insn_opcode
));
3605 report_insn_error (str
);
3606 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3609 if (mips_opts
.mips16
)
3610 mips16_macro (&insn
);
3617 if (offset_expr
.X_op
!= O_absent
)
3618 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3620 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3623 mips_assembling_insn
= FALSE
;
3626 /* Convenience functions for abstracting away the differences between
3627 MIPS16 and non-MIPS16 relocations. */
3629 static inline bfd_boolean
3630 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3634 case BFD_RELOC_MIPS16_JMP
:
3635 case BFD_RELOC_MIPS16_GPREL
:
3636 case BFD_RELOC_MIPS16_GOT16
:
3637 case BFD_RELOC_MIPS16_CALL16
:
3638 case BFD_RELOC_MIPS16_HI16_S
:
3639 case BFD_RELOC_MIPS16_HI16
:
3640 case BFD_RELOC_MIPS16_LO16
:
3648 static inline bfd_boolean
3649 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3653 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3654 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3655 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3656 case BFD_RELOC_MICROMIPS_GPREL16
:
3657 case BFD_RELOC_MICROMIPS_JMP
:
3658 case BFD_RELOC_MICROMIPS_HI16
:
3659 case BFD_RELOC_MICROMIPS_HI16_S
:
3660 case BFD_RELOC_MICROMIPS_LO16
:
3661 case BFD_RELOC_MICROMIPS_LITERAL
:
3662 case BFD_RELOC_MICROMIPS_GOT16
:
3663 case BFD_RELOC_MICROMIPS_CALL16
:
3664 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3665 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3666 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3667 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3668 case BFD_RELOC_MICROMIPS_SUB
:
3669 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3670 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3671 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3672 case BFD_RELOC_MICROMIPS_HIGHEST
:
3673 case BFD_RELOC_MICROMIPS_HIGHER
:
3674 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3675 case BFD_RELOC_MICROMIPS_JALR
:
3683 static inline bfd_boolean
3684 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3686 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3689 static inline bfd_boolean
3690 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3692 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3693 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3696 static inline bfd_boolean
3697 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3699 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3700 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3703 static inline bfd_boolean
3704 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3706 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3707 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3710 static inline bfd_boolean
3711 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3713 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3716 static inline bfd_boolean
3717 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3719 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3720 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3723 /* Return true if RELOC is a PC-relative relocation that does not have
3724 full address range. */
3726 static inline bfd_boolean
3727 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3731 case BFD_RELOC_16_PCREL_S2
:
3732 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3733 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3734 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3737 case BFD_RELOC_32_PCREL
:
3738 return HAVE_64BIT_ADDRESSES
;
3745 /* Return true if the given relocation might need a matching %lo().
3746 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3747 need a matching %lo() when applied to local symbols. */
3749 static inline bfd_boolean
3750 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3752 return (HAVE_IN_PLACE_ADDENDS
3753 && (hi16_reloc_p (reloc
)
3754 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3755 all GOT16 relocations evaluate to "G". */
3756 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3759 /* Return the type of %lo() reloc needed by RELOC, given that
3760 reloc_needs_lo_p. */
3762 static inline bfd_reloc_code_real_type
3763 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3765 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3766 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3770 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3773 static inline bfd_boolean
3774 fixup_has_matching_lo_p (fixS
*fixp
)
3776 return (fixp
->fx_next
!= NULL
3777 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3778 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3779 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3782 /* Move all labels in LABELS to the current insertion point. TEXT_P
3783 says whether the labels refer to text or data. */
3786 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3788 struct insn_label_list
*l
;
3791 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3793 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3794 symbol_set_frag (l
->label
, frag_now
);
3795 val
= (valueT
) frag_now_fix ();
3796 /* MIPS16/microMIPS text labels are stored as odd. */
3797 if (text_p
&& HAVE_CODE_COMPRESSION
)
3799 S_SET_VALUE (l
->label
, val
);
3803 /* Move all labels in insn_labels to the current insertion point
3804 and treat them as text labels. */
3807 mips_move_text_labels (void)
3809 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3813 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3815 bfd_boolean linkonce
= FALSE
;
3816 segT symseg
= S_GET_SEGMENT (sym
);
3818 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3820 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3822 /* The GNU toolchain uses an extension for ELF: a section
3823 beginning with the magic string .gnu.linkonce is a
3824 linkonce section. */
3825 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3826 sizeof ".gnu.linkonce" - 1) == 0)
3832 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3833 linker to handle them specially, such as generating jalx instructions
3834 when needed. We also make them odd for the duration of the assembly,
3835 in order to generate the right sort of code. We will make them even
3836 in the adjust_symtab routine, while leaving them marked. This is
3837 convenient for the debugger and the disassembler. The linker knows
3838 to make them odd again. */
3841 mips_compressed_mark_label (symbolS
*label
)
3843 gas_assert (HAVE_CODE_COMPRESSION
);
3845 if (mips_opts
.mips16
)
3846 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3848 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3849 if ((S_GET_VALUE (label
) & 1) == 0
3850 /* Don't adjust the address if the label is global or weak, or
3851 in a link-once section, since we'll be emitting symbol reloc
3852 references to it which will be patched up by the linker, and
3853 the final value of the symbol may or may not be MIPS16/microMIPS. */
3854 && !S_IS_WEAK (label
)
3855 && !S_IS_EXTERNAL (label
)
3856 && !s_is_linkonce (label
, now_seg
))
3857 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3860 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3863 mips_compressed_mark_labels (void)
3865 struct insn_label_list
*l
;
3867 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3868 mips_compressed_mark_label (l
->label
);
3871 /* End the current frag. Make it a variant frag and record the
3875 relax_close_frag (void)
3877 mips_macro_warning
.first_frag
= frag_now
;
3878 frag_var (rs_machine_dependent
, 0, 0,
3879 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3880 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3882 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3883 mips_relax
.first_fixup
= 0;
3886 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3887 See the comment above RELAX_ENCODE for more details. */
3890 relax_start (symbolS
*symbol
)
3892 gas_assert (mips_relax
.sequence
== 0);
3893 mips_relax
.sequence
= 1;
3894 mips_relax
.symbol
= symbol
;
3897 /* Start generating the second version of a relaxable sequence.
3898 See the comment above RELAX_ENCODE for more details. */
3903 gas_assert (mips_relax
.sequence
== 1);
3904 mips_relax
.sequence
= 2;
3907 /* End the current relaxable sequence. */
3912 gas_assert (mips_relax
.sequence
== 2);
3913 relax_close_frag ();
3914 mips_relax
.sequence
= 0;
3917 /* Return true if IP is a delayed branch or jump. */
3919 static inline bfd_boolean
3920 delayed_branch_p (const struct mips_cl_insn
*ip
)
3922 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3923 | INSN_COND_BRANCH_DELAY
3924 | INSN_COND_BRANCH_LIKELY
)) != 0;
3927 /* Return true if IP is a compact branch or jump. */
3929 static inline bfd_boolean
3930 compact_branch_p (const struct mips_cl_insn
*ip
)
3932 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3933 | INSN2_COND_BRANCH
)) != 0;
3936 /* Return true if IP is an unconditional branch or jump. */
3938 static inline bfd_boolean
3939 uncond_branch_p (const struct mips_cl_insn
*ip
)
3941 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3942 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3945 /* Return true if IP is a branch-likely instruction. */
3947 static inline bfd_boolean
3948 branch_likely_p (const struct mips_cl_insn
*ip
)
3950 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3953 /* Return the type of nop that should be used to fill the delay slot
3954 of delayed branch IP. */
3956 static struct mips_cl_insn
*
3957 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3959 if (mips_opts
.micromips
3960 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3961 return µmips_nop32_insn
;
3965 /* Return a mask that has bit N set if OPCODE reads the register(s)
3969 insn_read_mask (const struct mips_opcode
*opcode
)
3971 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3974 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3978 insn_write_mask (const struct mips_opcode
*opcode
)
3980 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3983 /* Return a mask of the registers specified by operand OPERAND of INSN.
3984 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3988 operand_reg_mask (const struct mips_cl_insn
*insn
,
3989 const struct mips_operand
*operand
,
3990 unsigned int type_mask
)
3992 unsigned int uval
, vsel
;
3994 switch (operand
->type
)
4001 case OP_ADDIUSP_INT
:
4002 case OP_ENTRY_EXIT_LIST
:
4003 case OP_REPEAT_DEST_REG
:
4004 case OP_REPEAT_PREV_REG
:
4007 case OP_VU0_MATCH_SUFFIX
:
4011 case OP_OPTIONAL_REG
:
4013 const struct mips_reg_operand
*reg_op
;
4015 reg_op
= (const struct mips_reg_operand
*) operand
;
4016 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4018 uval
= insn_extract_operand (insn
, operand
);
4019 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4024 const struct mips_reg_pair_operand
*pair_op
;
4026 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4027 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4029 uval
= insn_extract_operand (insn
, operand
);
4030 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4033 case OP_CLO_CLZ_DEST
:
4034 if (!(type_mask
& (1 << OP_REG_GP
)))
4036 uval
= insn_extract_operand (insn
, operand
);
4037 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4039 case OP_LWM_SWM_LIST
:
4042 case OP_SAVE_RESTORE_LIST
:
4045 case OP_MDMX_IMM_REG
:
4046 if (!(type_mask
& (1 << OP_REG_VEC
)))
4048 uval
= insn_extract_operand (insn
, operand
);
4050 if ((vsel
& 0x18) == 0x18)
4052 return 1 << (uval
& 31);
4057 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4058 where bit N of OPNO_MASK is set if operand N should be included.
4059 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4063 insn_reg_mask (const struct mips_cl_insn
*insn
,
4064 unsigned int type_mask
, unsigned int opno_mask
)
4066 unsigned int opno
, reg_mask
;
4070 while (opno_mask
!= 0)
4073 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4080 /* Return the mask of core registers that IP reads. */
4083 gpr_read_mask (const struct mips_cl_insn
*ip
)
4085 unsigned long pinfo
, pinfo2
;
4088 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4089 pinfo
= ip
->insn_mo
->pinfo
;
4090 pinfo2
= ip
->insn_mo
->pinfo2
;
4091 if (pinfo
& INSN_UDI
)
4093 /* UDI instructions have traditionally been assumed to read RS
4095 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4096 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4098 if (pinfo
& INSN_READ_GPR_24
)
4100 if (pinfo2
& INSN2_READ_GPR_16
)
4102 if (pinfo2
& INSN2_READ_SP
)
4104 if (pinfo2
& INSN2_READ_GPR_31
)
4106 /* Don't include register 0. */
4110 /* Return the mask of core registers that IP writes. */
4113 gpr_write_mask (const struct mips_cl_insn
*ip
)
4115 unsigned long pinfo
, pinfo2
;
4118 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4119 pinfo
= ip
->insn_mo
->pinfo
;
4120 pinfo2
= ip
->insn_mo
->pinfo2
;
4121 if (pinfo
& INSN_WRITE_GPR_24
)
4123 if (pinfo
& INSN_WRITE_GPR_31
)
4125 if (pinfo
& INSN_UDI
)
4126 /* UDI instructions have traditionally been assumed to write to RD. */
4127 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4128 if (pinfo2
& INSN2_WRITE_SP
)
4130 /* Don't include register 0. */
4134 /* Return the mask of floating-point registers that IP reads. */
4137 fpr_read_mask (const struct mips_cl_insn
*ip
)
4139 unsigned long pinfo
;
4142 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4143 insn_read_mask (ip
->insn_mo
));
4144 pinfo
= ip
->insn_mo
->pinfo
;
4145 /* Conservatively treat all operands to an FP_D instruction are doubles.
4146 (This is overly pessimistic for things like cvt.d.s.) */
4147 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4152 /* Return the mask of floating-point registers that IP writes. */
4155 fpr_write_mask (const struct mips_cl_insn
*ip
)
4157 unsigned long pinfo
;
4160 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4161 insn_write_mask (ip
->insn_mo
));
4162 pinfo
= ip
->insn_mo
->pinfo
;
4163 /* Conservatively treat all operands to an FP_D instruction are doubles.
4164 (This is overly pessimistic for things like cvt.s.d.) */
4165 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4170 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4171 Check whether that is allowed. */
4174 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4176 const char *s
= insn
->name
;
4178 if (insn
->pinfo
== INSN_MACRO
)
4179 /* Let a macro pass, we'll catch it later when it is expanded. */
4182 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4184 /* Allow odd registers for single-precision ops. */
4185 switch (insn
->pinfo
& (FP_S
| FP_D
))
4196 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4197 s
= strchr (insn
->name
, '.');
4198 if (s
!= NULL
&& opnum
== 2)
4199 s
= strchr (s
+ 1, '.');
4200 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4203 /* Single-precision coprocessor loads and moves are OK too. */
4204 if ((insn
->pinfo
& FP_S
)
4205 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4206 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4212 /* Information about an instruction argument that we're trying to match. */
4213 struct mips_arg_info
4215 /* The instruction so far. */
4216 struct mips_cl_insn
*insn
;
4218 /* The first unconsumed operand token. */
4219 struct mips_operand_token
*token
;
4221 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4224 /* The 1-based argument number, for error reporting. This does not
4225 count elided optional registers, etc.. */
4228 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4229 unsigned int last_regno
;
4231 /* If the first operand was an OP_REG, this is the register that it
4232 specified, otherwise it is ILLEGAL_REG. */
4233 unsigned int dest_regno
;
4235 /* The value of the last OP_INT operand. Only used for OP_MSB,
4236 where it gives the lsb position. */
4237 unsigned int last_op_int
;
4239 /* If true, match routines should assume that no later instruction
4240 alternative matches and should therefore be as accomodating as
4241 possible. Match routines should not report errors if something
4242 is only invalid for !LAX_MATCH. */
4243 bfd_boolean lax_match
;
4245 /* True if a reference to the current AT register was seen. */
4246 bfd_boolean seen_at
;
4249 /* Record that the argument is out of range. */
4252 match_out_of_range (struct mips_arg_info
*arg
)
4254 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4257 /* Record that the argument isn't constant but needs to be. */
4260 match_not_constant (struct mips_arg_info
*arg
)
4262 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4266 /* Try to match an OT_CHAR token for character CH. Consume the token
4267 and return true on success, otherwise return false. */
4270 match_char (struct mips_arg_info
*arg
, char ch
)
4272 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4282 /* Try to get an expression from the next tokens in ARG. Consume the
4283 tokens and return true on success, storing the expression value in
4284 VALUE and relocation types in R. */
4287 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4288 bfd_reloc_code_real_type
*r
)
4290 /* If the next token is a '(' that was parsed as being part of a base
4291 expression, assume we have an elided offset. The later match will fail
4292 if this turns out to be wrong. */
4293 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4295 value
->X_op
= O_constant
;
4296 value
->X_add_number
= 0;
4297 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4301 /* Reject register-based expressions such as "0+$2" and "(($2))".
4302 For plain registers the default error seems more appropriate. */
4303 if (arg
->token
->type
== OT_INTEGER
4304 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4306 set_insn_error (arg
->argnum
, _("register value used as expression"));
4310 if (arg
->token
->type
== OT_INTEGER
)
4312 *value
= arg
->token
->u
.integer
.value
;
4313 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4319 (arg
->argnum
, _("operand %d must be an immediate expression"),
4324 /* Try to get a constant expression from the next tokens in ARG. Consume
4325 the tokens and return return true on success, storing the constant value
4326 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4330 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4333 bfd_reloc_code_real_type r
[3];
4335 if (!match_expression (arg
, &ex
, r
))
4338 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4339 *value
= ex
.X_add_number
;
4342 match_not_constant (arg
);
4348 /* Return the RTYPE_* flags for a register operand of type TYPE that
4349 appears in instruction OPCODE. */
4352 convert_reg_type (const struct mips_opcode
*opcode
,
4353 enum mips_reg_operand_type type
)
4358 return RTYPE_NUM
| RTYPE_GP
;
4361 /* Allow vector register names for MDMX if the instruction is a 64-bit
4362 FPR load, store or move (including moves to and from GPRs). */
4363 if ((mips_opts
.ase
& ASE_MDMX
)
4364 && (opcode
->pinfo
& FP_D
)
4365 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4366 | INSN_COPROC_MEMORY_DELAY
4367 | INSN_LOAD_COPROC_DELAY
4368 | INSN_LOAD_MEMORY_DELAY
4369 | INSN_STORE_MEMORY
)))
4370 return RTYPE_FPU
| RTYPE_VEC
;
4374 if (opcode
->pinfo
& (FP_D
| FP_S
))
4375 return RTYPE_CCC
| RTYPE_FCC
;
4379 if (opcode
->membership
& INSN_5400
)
4381 return RTYPE_FPU
| RTYPE_VEC
;
4387 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4388 return RTYPE_NUM
| RTYPE_CP0
;
4395 return RTYPE_NUM
| RTYPE_VI
;
4398 return RTYPE_NUM
| RTYPE_VF
;
4400 case OP_REG_R5900_I
:
4401 return RTYPE_R5900_I
;
4403 case OP_REG_R5900_Q
:
4404 return RTYPE_R5900_Q
;
4406 case OP_REG_R5900_R
:
4407 return RTYPE_R5900_R
;
4409 case OP_REG_R5900_ACC
:
4410 return RTYPE_R5900_ACC
;
4415 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4418 check_regno (struct mips_arg_info
*arg
,
4419 enum mips_reg_operand_type type
, unsigned int regno
)
4421 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4422 arg
->seen_at
= TRUE
;
4424 if (type
== OP_REG_FP
4427 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4428 as_warn (_("Float register should be even, was %d"), regno
);
4430 if (type
== OP_REG_CCC
)
4435 name
= arg
->insn
->insn_mo
->name
;
4436 length
= strlen (name
);
4437 if ((regno
& 1) != 0
4438 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4439 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4440 as_warn (_("Condition code register should be even for %s, was %d"),
4443 if ((regno
& 3) != 0
4444 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4445 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4450 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4451 a register of type TYPE. Return true on success, storing the register
4452 number in *REGNO and warning about any dubious uses. */
4455 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4456 unsigned int symval
, unsigned int *regno
)
4458 if (type
== OP_REG_VEC
)
4459 symval
= mips_prefer_vec_regno (symval
);
4460 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4463 *regno
= symval
& RNUM_MASK
;
4464 check_regno (arg
, type
, *regno
);
4468 /* Try to interpret the next token in ARG as a register of type TYPE.
4469 Consume the token and return true on success, storing the register
4470 number in *REGNO. Return false on failure. */
4473 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4474 unsigned int *regno
)
4476 if (arg
->token
->type
== OT_REG
4477 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4485 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4486 Consume the token and return true on success, storing the register numbers
4487 in *REGNO1 and *REGNO2. Return false on failure. */
4490 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4491 unsigned int *regno1
, unsigned int *regno2
)
4493 if (match_reg (arg
, type
, regno1
))
4498 if (arg
->token
->type
== OT_REG_RANGE
4499 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4500 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4501 && *regno1
<= *regno2
)
4509 /* OP_INT matcher. */
4512 match_int_operand (struct mips_arg_info
*arg
,
4513 const struct mips_operand
*operand_base
)
4515 const struct mips_int_operand
*operand
;
4517 int min_val
, max_val
, factor
;
4520 operand
= (const struct mips_int_operand
*) operand_base
;
4521 factor
= 1 << operand
->shift
;
4522 min_val
= mips_int_operand_min (operand
);
4523 max_val
= mips_int_operand_max (operand
);
4525 if (operand_base
->lsb
== 0
4526 && operand_base
->size
== 16
4527 && operand
->shift
== 0
4528 && operand
->bias
== 0
4529 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4531 /* The operand can be relocated. */
4532 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4535 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4536 /* Relocation operators were used. Accept the arguent and
4537 leave the relocation value in offset_expr and offset_relocs
4538 for the caller to process. */
4541 if (offset_expr
.X_op
!= O_constant
)
4543 /* Accept non-constant operands if no later alternative matches,
4544 leaving it for the caller to process. */
4545 if (!arg
->lax_match
)
4547 offset_reloc
[0] = BFD_RELOC_LO16
;
4551 /* Clear the global state; we're going to install the operand
4553 sval
= offset_expr
.X_add_number
;
4554 offset_expr
.X_op
= O_absent
;
4556 /* For compatibility with older assemblers, we accept
4557 0x8000-0xffff as signed 16-bit numbers when only
4558 signed numbers are allowed. */
4561 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4562 if (!arg
->lax_match
&& sval
<= max_val
)
4568 if (!match_const_int (arg
, &sval
))
4572 arg
->last_op_int
= sval
;
4574 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4576 match_out_of_range (arg
);
4580 uval
= (unsigned int) sval
>> operand
->shift
;
4581 uval
-= operand
->bias
;
4583 /* Handle -mfix-cn63xxp1. */
4585 && mips_fix_cn63xxp1
4586 && !mips_opts
.micromips
4587 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4602 /* The rest must be changed to 28. */
4607 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4611 /* OP_MAPPED_INT matcher. */
4614 match_mapped_int_operand (struct mips_arg_info
*arg
,
4615 const struct mips_operand
*operand_base
)
4617 const struct mips_mapped_int_operand
*operand
;
4618 unsigned int uval
, num_vals
;
4621 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4622 if (!match_const_int (arg
, &sval
))
4625 num_vals
= 1 << operand_base
->size
;
4626 for (uval
= 0; uval
< num_vals
; uval
++)
4627 if (operand
->int_map
[uval
] == sval
)
4629 if (uval
== num_vals
)
4631 match_out_of_range (arg
);
4635 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4639 /* OP_MSB matcher. */
4642 match_msb_operand (struct mips_arg_info
*arg
,
4643 const struct mips_operand
*operand_base
)
4645 const struct mips_msb_operand
*operand
;
4646 int min_val
, max_val
, max_high
;
4647 offsetT size
, sval
, high
;
4649 operand
= (const struct mips_msb_operand
*) operand_base
;
4650 min_val
= operand
->bias
;
4651 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4652 max_high
= operand
->opsize
;
4654 if (!match_const_int (arg
, &size
))
4657 high
= size
+ arg
->last_op_int
;
4658 sval
= operand
->add_lsb
? high
: size
;
4660 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4662 match_out_of_range (arg
);
4665 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4669 /* OP_REG matcher. */
4672 match_reg_operand (struct mips_arg_info
*arg
,
4673 const struct mips_operand
*operand_base
)
4675 const struct mips_reg_operand
*operand
;
4676 unsigned int regno
, uval
, num_vals
;
4678 operand
= (const struct mips_reg_operand
*) operand_base
;
4679 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4682 if (operand
->reg_map
)
4684 num_vals
= 1 << operand
->root
.size
;
4685 for (uval
= 0; uval
< num_vals
; uval
++)
4686 if (operand
->reg_map
[uval
] == regno
)
4688 if (num_vals
== uval
)
4694 arg
->last_regno
= regno
;
4695 if (arg
->opnum
== 1)
4696 arg
->dest_regno
= regno
;
4697 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4701 /* OP_REG_PAIR matcher. */
4704 match_reg_pair_operand (struct mips_arg_info
*arg
,
4705 const struct mips_operand
*operand_base
)
4707 const struct mips_reg_pair_operand
*operand
;
4708 unsigned int regno1
, regno2
, uval
, num_vals
;
4710 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4711 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4712 || !match_char (arg
, ',')
4713 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4716 num_vals
= 1 << operand_base
->size
;
4717 for (uval
= 0; uval
< num_vals
; uval
++)
4718 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4720 if (uval
== num_vals
)
4723 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4727 /* OP_PCREL matcher. The caller chooses the relocation type. */
4730 match_pcrel_operand (struct mips_arg_info
*arg
)
4732 bfd_reloc_code_real_type r
[3];
4734 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4737 /* OP_PERF_REG matcher. */
4740 match_perf_reg_operand (struct mips_arg_info
*arg
,
4741 const struct mips_operand
*operand
)
4745 if (!match_const_int (arg
, &sval
))
4750 || (mips_opts
.arch
== CPU_R5900
4751 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4752 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4754 set_insn_error (arg
->argnum
, _("invalid performance register"));
4758 insn_insert_operand (arg
->insn
, operand
, sval
);
4762 /* OP_ADDIUSP matcher. */
4765 match_addiusp_operand (struct mips_arg_info
*arg
,
4766 const struct mips_operand
*operand
)
4771 if (!match_const_int (arg
, &sval
))
4776 match_out_of_range (arg
);
4781 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4783 match_out_of_range (arg
);
4787 uval
= (unsigned int) sval
;
4788 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4789 insn_insert_operand (arg
->insn
, operand
, uval
);
4793 /* OP_CLO_CLZ_DEST matcher. */
4796 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4797 const struct mips_operand
*operand
)
4801 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4804 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4808 /* OP_LWM_SWM_LIST matcher. */
4811 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4812 const struct mips_operand
*operand
)
4814 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4815 struct mips_arg_info reset
;
4818 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4822 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4827 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4830 while (match_char (arg
, ',')
4831 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4834 if (operand
->size
== 2)
4836 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4842 and any permutations of these. */
4843 if ((reglist
& 0xfff1ffff) != 0x80010000)
4846 sregs
= (reglist
>> 17) & 7;
4851 /* The list must include at least one of ra and s0-sN,
4852 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4853 which are $23 and $30 respectively.) E.g.:
4861 and any permutations of these. */
4862 if ((reglist
& 0x3f00ffff) != 0)
4865 ra
= (reglist
>> 27) & 0x10;
4866 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4869 if ((sregs
& -sregs
) != sregs
)
4872 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4876 /* OP_ENTRY_EXIT_LIST matcher. */
4879 match_entry_exit_operand (struct mips_arg_info
*arg
,
4880 const struct mips_operand
*operand
)
4883 bfd_boolean is_exit
;
4885 /* The format is the same for both ENTRY and EXIT, but the constraints
4887 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4888 mask
= (is_exit
? 7 << 3 : 0);
4891 unsigned int regno1
, regno2
;
4892 bfd_boolean is_freg
;
4894 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4896 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4901 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4904 mask
|= (5 + regno2
) << 3;
4906 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4907 mask
|= (regno2
- 3) << 3;
4908 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4909 mask
|= (regno2
- 15) << 1;
4910 else if (regno1
== RA
&& regno2
== RA
)
4915 while (match_char (arg
, ','));
4917 insn_insert_operand (arg
->insn
, operand
, mask
);
4921 /* OP_SAVE_RESTORE_LIST matcher. */
4924 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4926 unsigned int opcode
, args
, statics
, sregs
;
4927 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4930 opcode
= arg
->insn
->insn_opcode
;
4932 num_frame_sizes
= 0;
4938 unsigned int regno1
, regno2
;
4940 if (arg
->token
->type
== OT_INTEGER
)
4942 /* Handle the frame size. */
4943 if (!match_const_int (arg
, &frame_size
))
4945 num_frame_sizes
+= 1;
4949 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4952 while (regno1
<= regno2
)
4954 if (regno1
>= 4 && regno1
<= 7)
4956 if (num_frame_sizes
== 0)
4958 args
|= 1 << (regno1
- 4);
4960 /* statics $a0-$a3 */
4961 statics
|= 1 << (regno1
- 4);
4963 else if (regno1
>= 16 && regno1
<= 23)
4965 sregs
|= 1 << (regno1
- 16);
4966 else if (regno1
== 30)
4969 else if (regno1
== 31)
4970 /* Add $ra to insn. */
4980 while (match_char (arg
, ','));
4982 /* Encode args/statics combination. */
4985 else if (args
== 0xf)
4986 /* All $a0-$a3 are args. */
4987 opcode
|= MIPS16_ALL_ARGS
<< 16;
4988 else if (statics
== 0xf)
4989 /* All $a0-$a3 are statics. */
4990 opcode
|= MIPS16_ALL_STATICS
<< 16;
4993 /* Count arg registers. */
5003 /* Count static registers. */
5005 while (statics
& 0x8)
5007 statics
= (statics
<< 1) & 0xf;
5013 /* Encode args/statics. */
5014 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5017 /* Encode $s0/$s1. */
5018 if (sregs
& (1 << 0)) /* $s0 */
5020 if (sregs
& (1 << 1)) /* $s1 */
5024 /* Encode $s2-$s8. */
5033 opcode
|= num_sregs
<< 24;
5035 /* Encode frame size. */
5036 if (num_frame_sizes
== 0)
5038 set_insn_error (arg
->argnum
, _("missing frame size"));
5041 if (num_frame_sizes
> 1)
5043 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5046 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5048 set_insn_error (arg
->argnum
, _("invalid frame size"));
5051 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5054 opcode
|= (((frame_size
& 0xf0) << 16)
5055 | (frame_size
& 0x0f));
5058 /* Finally build the instruction. */
5059 if ((opcode
>> 16) != 0 || frame_size
== 0)
5060 opcode
|= MIPS16_EXTEND
;
5061 arg
->insn
->insn_opcode
= opcode
;
5065 /* OP_MDMX_IMM_REG matcher. */
5068 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5069 const struct mips_operand
*operand
)
5071 unsigned int regno
, uval
;
5073 const struct mips_opcode
*opcode
;
5075 /* The mips_opcode records whether this is an octobyte or quadhalf
5076 instruction. Start out with that bit in place. */
5077 opcode
= arg
->insn
->insn_mo
;
5078 uval
= mips_extract_operand (operand
, opcode
->match
);
5079 is_qh
= (uval
!= 0);
5081 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
5083 if ((opcode
->membership
& INSN_5400
)
5084 && strcmp (opcode
->name
, "rzu.ob") == 0)
5086 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5091 /* Check whether this is a vector register or a broadcast of
5092 a single element. */
5093 if (arg
->token
->type
== OT_REG_ELEMENT
)
5095 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
5098 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
5100 set_insn_error (arg
->argnum
, _("invalid element selector"));
5104 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
5108 /* A full vector. */
5109 if ((opcode
->membership
& INSN_5400
)
5110 && (strcmp (opcode
->name
, "sll.ob") == 0
5111 || strcmp (opcode
->name
, "srl.ob") == 0))
5113 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5118 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5121 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5123 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5132 if (!match_const_int (arg
, &sval
))
5134 if (sval
< 0 || sval
> 31)
5136 match_out_of_range (arg
);
5139 uval
|= (sval
& 31);
5141 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5143 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5145 insn_insert_operand (arg
->insn
, operand
, uval
);
5149 /* OP_PC matcher. */
5152 match_pc_operand (struct mips_arg_info
*arg
)
5154 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5162 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5163 register that we need to match. */
5166 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5170 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5173 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5174 the length of the value in bytes (4 for float, 8 for double) and
5175 USING_GPRS says whether the destination is a GPR rather than an FPR.
5177 Return the constant in IMM and OFFSET as follows:
5179 - If the constant should be loaded via memory, set IMM to O_absent and
5180 OFFSET to the memory address.
5182 - Otherwise, if the constant should be loaded into two 32-bit registers,
5183 set IMM to the O_constant to load into the high register and OFFSET
5184 to the corresponding value for the low register.
5186 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5188 These constants only appear as the last operand in an instruction,
5189 and every instruction that accepts them in any variant accepts them
5190 in all variants. This means we don't have to worry about backing out
5191 any changes if the instruction does not match. We just match
5192 unconditionally and report an error if the constant is invalid. */
5195 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5196 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5201 const char *newname
;
5202 unsigned char *data
;
5204 /* Where the constant is placed is based on how the MIPS assembler
5207 length == 4 && using_gprs -- immediate value only
5208 length == 8 && using_gprs -- .rdata or immediate value
5209 length == 4 && !using_gprs -- .lit4 or immediate value
5210 length == 8 && !using_gprs -- .lit8 or immediate value
5212 The .lit4 and .lit8 sections are only used if permitted by the
5214 if (arg
->token
->type
!= OT_FLOAT
)
5216 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5220 gas_assert (arg
->token
->u
.flt
.length
== length
);
5221 data
= arg
->token
->u
.flt
.data
;
5224 /* Handle 32-bit constants for which an immediate value is best. */
5227 || g_switch_value
< 4
5228 || (data
[0] == 0 && data
[1] == 0)
5229 || (data
[2] == 0 && data
[3] == 0)))
5231 imm
->X_op
= O_constant
;
5232 if (!target_big_endian
)
5233 imm
->X_add_number
= bfd_getl32 (data
);
5235 imm
->X_add_number
= bfd_getb32 (data
);
5236 offset
->X_op
= O_absent
;
5240 /* Handle 64-bit constants for which an immediate value is best. */
5242 && !mips_disable_float_construction
5243 /* Constants can only be constructed in GPRs and copied
5244 to FPRs if the GPRs are at least as wide as the FPRs.
5245 Force the constant into memory if we are using 64-bit FPRs
5246 but the GPRs are only 32 bits wide. */
5247 /* ??? No longer true with the addition of MTHC1, but this
5248 is legacy code... */
5249 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5250 && ((data
[0] == 0 && data
[1] == 0)
5251 || (data
[2] == 0 && data
[3] == 0))
5252 && ((data
[4] == 0 && data
[5] == 0)
5253 || (data
[6] == 0 && data
[7] == 0)))
5255 /* The value is simple enough to load with a couple of instructions.
5256 If using 32-bit registers, set IMM to the high order 32 bits and
5257 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5259 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5261 imm
->X_op
= O_constant
;
5262 offset
->X_op
= O_constant
;
5263 if (!target_big_endian
)
5265 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5266 offset
->X_add_number
= bfd_getl32 (data
);
5270 imm
->X_add_number
= bfd_getb32 (data
);
5271 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5273 if (offset
->X_add_number
== 0)
5274 offset
->X_op
= O_absent
;
5278 imm
->X_op
= O_constant
;
5279 if (!target_big_endian
)
5280 imm
->X_add_number
= bfd_getl64 (data
);
5282 imm
->X_add_number
= bfd_getb64 (data
);
5283 offset
->X_op
= O_absent
;
5288 /* Switch to the right section. */
5290 subseg
= now_subseg
;
5293 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5298 if (using_gprs
|| g_switch_value
< 8)
5299 newname
= RDATA_SECTION_NAME
;
5304 new_seg
= subseg_new (newname
, (subsegT
) 0);
5305 bfd_set_section_flags (stdoutput
, new_seg
,
5306 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5307 frag_align (length
== 4 ? 2 : 3, 0, 0);
5308 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5309 record_alignment (new_seg
, 4);
5311 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5313 as_bad (_("Can't use floating point insn in this section"));
5315 /* Set the argument to the current address in the section. */
5316 imm
->X_op
= O_absent
;
5317 offset
->X_op
= O_symbol
;
5318 offset
->X_add_symbol
= symbol_temp_new_now ();
5319 offset
->X_add_number
= 0;
5321 /* Put the floating point number into the section. */
5322 p
= frag_more (length
);
5323 memcpy (p
, data
, length
);
5325 /* Switch back to the original section. */
5326 subseg_set (seg
, subseg
);
5330 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5334 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5335 const struct mips_operand
*operand
,
5336 bfd_boolean match_p
)
5340 /* The operand can be an XYZW mask or a single 2-bit channel index
5341 (with X being 0). */
5342 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5344 /* The suffix can be omitted when it is already part of the opcode. */
5345 if (arg
->token
->type
!= OT_CHANNELS
)
5348 uval
= arg
->token
->u
.channels
;
5349 if (operand
->size
== 2)
5351 /* Check that a single bit is set and convert it into a 2-bit index. */
5352 if ((uval
& -uval
) != uval
)
5354 uval
= 4 - ffs (uval
);
5357 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5362 insn_insert_operand (arg
->insn
, operand
, uval
);
5366 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5367 of the argument text if the match is successful, otherwise return null. */
5370 match_operand (struct mips_arg_info
*arg
,
5371 const struct mips_operand
*operand
)
5373 switch (operand
->type
)
5376 return match_int_operand (arg
, operand
);
5379 return match_mapped_int_operand (arg
, operand
);
5382 return match_msb_operand (arg
, operand
);
5385 case OP_OPTIONAL_REG
:
5386 return match_reg_operand (arg
, operand
);
5389 return match_reg_pair_operand (arg
, operand
);
5392 return match_pcrel_operand (arg
);
5395 return match_perf_reg_operand (arg
, operand
);
5397 case OP_ADDIUSP_INT
:
5398 return match_addiusp_operand (arg
, operand
);
5400 case OP_CLO_CLZ_DEST
:
5401 return match_clo_clz_dest_operand (arg
, operand
);
5403 case OP_LWM_SWM_LIST
:
5404 return match_lwm_swm_list_operand (arg
, operand
);
5406 case OP_ENTRY_EXIT_LIST
:
5407 return match_entry_exit_operand (arg
, operand
);
5409 case OP_SAVE_RESTORE_LIST
:
5410 return match_save_restore_list_operand (arg
);
5412 case OP_MDMX_IMM_REG
:
5413 return match_mdmx_imm_reg_operand (arg
, operand
);
5415 case OP_REPEAT_DEST_REG
:
5416 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5418 case OP_REPEAT_PREV_REG
:
5419 return match_tied_reg_operand (arg
, arg
->last_regno
);
5422 return match_pc_operand (arg
);
5425 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5427 case OP_VU0_MATCH_SUFFIX
:
5428 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5433 /* ARG is the state after successfully matching an instruction.
5434 Issue any queued-up warnings. */
5437 check_completed_insn (struct mips_arg_info
*arg
)
5442 as_warn (_("Used $at without \".set noat\""));
5444 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5448 /* Return true if modifying general-purpose register REG needs a delay. */
5451 reg_needs_delay (unsigned int reg
)
5453 unsigned long prev_pinfo
;
5455 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5456 if (!mips_opts
.noreorder
5457 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5458 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5459 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5465 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5466 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5467 by VR4120 errata. */
5470 classify_vr4120_insn (const char *name
)
5472 if (strncmp (name
, "macc", 4) == 0)
5473 return FIX_VR4120_MACC
;
5474 if (strncmp (name
, "dmacc", 5) == 0)
5475 return FIX_VR4120_DMACC
;
5476 if (strncmp (name
, "mult", 4) == 0)
5477 return FIX_VR4120_MULT
;
5478 if (strncmp (name
, "dmult", 5) == 0)
5479 return FIX_VR4120_DMULT
;
5480 if (strstr (name
, "div"))
5481 return FIX_VR4120_DIV
;
5482 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5483 return FIX_VR4120_MTHILO
;
5484 return NUM_FIX_VR4120_CLASSES
;
5487 #define INSN_ERET 0x42000018
5488 #define INSN_DERET 0x4200001f
5490 /* Return the number of instructions that must separate INSN1 and INSN2,
5491 where INSN1 is the earlier instruction. Return the worst-case value
5492 for any INSN2 if INSN2 is null. */
5495 insns_between (const struct mips_cl_insn
*insn1
,
5496 const struct mips_cl_insn
*insn2
)
5498 unsigned long pinfo1
, pinfo2
;
5501 /* If INFO2 is null, pessimistically assume that all flags are set for
5502 the second instruction. */
5503 pinfo1
= insn1
->insn_mo
->pinfo
;
5504 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5506 /* For most targets, write-after-read dependencies on the HI and LO
5507 registers must be separated by at least two instructions. */
5508 if (!hilo_interlocks
)
5510 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5512 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5516 /* If we're working around r7000 errata, there must be two instructions
5517 between an mfhi or mflo and any instruction that uses the result. */
5518 if (mips_7000_hilo_fix
5519 && !mips_opts
.micromips
5520 && MF_HILO_INSN (pinfo1
)
5521 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5524 /* If we're working around 24K errata, one instruction is required
5525 if an ERET or DERET is followed by a branch instruction. */
5526 if (mips_fix_24k
&& !mips_opts
.micromips
)
5528 if (insn1
->insn_opcode
== INSN_ERET
5529 || insn1
->insn_opcode
== INSN_DERET
)
5532 || insn2
->insn_opcode
== INSN_ERET
5533 || insn2
->insn_opcode
== INSN_DERET
5534 || delayed_branch_p (insn2
))
5539 /* If working around VR4120 errata, check for combinations that need
5540 a single intervening instruction. */
5541 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5543 unsigned int class1
, class2
;
5545 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5546 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5550 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5551 if (vr4120_conflicts
[class1
] & (1 << class2
))
5556 if (!HAVE_CODE_COMPRESSION
)
5558 /* Check for GPR or coprocessor load delays. All such delays
5559 are on the RT register. */
5560 /* Itbl support may require additional care here. */
5561 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5562 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5564 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5568 /* Check for generic coprocessor hazards.
5570 This case is not handled very well. There is no special
5571 knowledge of CP0 handling, and the coprocessors other than
5572 the floating point unit are not distinguished at all. */
5573 /* Itbl support may require additional care here. FIXME!
5574 Need to modify this to include knowledge about
5575 user specified delays! */
5576 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5577 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5579 /* Handle cases where INSN1 writes to a known general coprocessor
5580 register. There must be a one instruction delay before INSN2
5581 if INSN2 reads that register, otherwise no delay is needed. */
5582 mask
= fpr_write_mask (insn1
);
5585 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5590 /* Read-after-write dependencies on the control registers
5591 require a two-instruction gap. */
5592 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5593 && (pinfo2
& INSN_READ_COND_CODE
))
5596 /* We don't know exactly what INSN1 does. If INSN2 is
5597 also a coprocessor instruction, assume there must be
5598 a one instruction gap. */
5599 if (pinfo2
& INSN_COP
)
5604 /* Check for read-after-write dependencies on the coprocessor
5605 control registers in cases where INSN1 does not need a general
5606 coprocessor delay. This means that INSN1 is a floating point
5607 comparison instruction. */
5608 /* Itbl support may require additional care here. */
5609 else if (!cop_interlocks
5610 && (pinfo1
& INSN_WRITE_COND_CODE
)
5611 && (pinfo2
& INSN_READ_COND_CODE
))
5618 /* Return the number of nops that would be needed to work around the
5619 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5620 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5621 that are contained within the first IGNORE instructions of HIST. */
5624 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5625 const struct mips_cl_insn
*insn
)
5630 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5631 are not affected by the errata. */
5633 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5634 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5635 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5638 /* Search for the first MFLO or MFHI. */
5639 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5640 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5642 /* Extract the destination register. */
5643 mask
= gpr_write_mask (&hist
[i
]);
5645 /* No nops are needed if INSN reads that register. */
5646 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5649 /* ...or if any of the intervening instructions do. */
5650 for (j
= 0; j
< i
; j
++)
5651 if (gpr_read_mask (&hist
[j
]) & mask
)
5655 return MAX_VR4130_NOPS
- i
;
5660 #define BASE_REG_EQ(INSN1, INSN2) \
5661 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5662 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5664 /* Return the minimum alignment for this store instruction. */
5667 fix_24k_align_to (const struct mips_opcode
*mo
)
5669 if (strcmp (mo
->name
, "sh") == 0)
5672 if (strcmp (mo
->name
, "swc1") == 0
5673 || strcmp (mo
->name
, "swc2") == 0
5674 || strcmp (mo
->name
, "sw") == 0
5675 || strcmp (mo
->name
, "sc") == 0
5676 || strcmp (mo
->name
, "s.s") == 0)
5679 if (strcmp (mo
->name
, "sdc1") == 0
5680 || strcmp (mo
->name
, "sdc2") == 0
5681 || strcmp (mo
->name
, "s.d") == 0)
5688 struct fix_24k_store_info
5690 /* Immediate offset, if any, for this store instruction. */
5692 /* Alignment required by this store instruction. */
5694 /* True for register offsets. */
5695 int register_offset
;
5698 /* Comparison function used by qsort. */
5701 fix_24k_sort (const void *a
, const void *b
)
5703 const struct fix_24k_store_info
*pos1
= a
;
5704 const struct fix_24k_store_info
*pos2
= b
;
5706 return (pos1
->off
- pos2
->off
);
5709 /* INSN is a store instruction. Try to record the store information
5710 in STINFO. Return false if the information isn't known. */
5713 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5714 const struct mips_cl_insn
*insn
)
5716 /* The instruction must have a known offset. */
5717 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5720 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5721 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5725 /* Return the number of nops that would be needed to work around the 24k
5726 "lost data on stores during refill" errata if instruction INSN
5727 immediately followed the 2 instructions described by HIST.
5728 Ignore hazards that are contained within the first IGNORE
5729 instructions of HIST.
5731 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5732 for the data cache refills and store data. The following describes
5733 the scenario where the store data could be lost.
5735 * A data cache miss, due to either a load or a store, causing fill
5736 data to be supplied by the memory subsystem
5737 * The first three doublewords of fill data are returned and written
5739 * A sequence of four stores occurs in consecutive cycles around the
5740 final doubleword of the fill:
5744 * Zero, One or more instructions
5747 The four stores A-D must be to different doublewords of the line that
5748 is being filled. The fourth instruction in the sequence above permits
5749 the fill of the final doubleword to be transferred from the FSB into
5750 the cache. In the sequence above, the stores may be either integer
5751 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5752 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5753 different doublewords on the line. If the floating point unit is
5754 running in 1:2 mode, it is not possible to create the sequence above
5755 using only floating point store instructions.
5757 In this case, the cache line being filled is incorrectly marked
5758 invalid, thereby losing the data from any store to the line that
5759 occurs between the original miss and the completion of the five
5760 cycle sequence shown above.
5762 The workarounds are:
5764 * Run the data cache in write-through mode.
5765 * Insert a non-store instruction between
5766 Store A and Store B or Store B and Store C. */
5769 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5770 const struct mips_cl_insn
*insn
)
5772 struct fix_24k_store_info pos
[3];
5773 int align
, i
, base_offset
;
5778 /* If the previous instruction wasn't a store, there's nothing to
5780 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5783 /* If the instructions after the previous one are unknown, we have
5784 to assume the worst. */
5788 /* Check whether we are dealing with three consecutive stores. */
5789 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5790 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5793 /* If we don't know the relationship between the store addresses,
5794 assume the worst. */
5795 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5796 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5799 if (!fix_24k_record_store_info (&pos
[0], insn
)
5800 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5801 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5804 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5806 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5807 X bytes and such that the base register + X is known to be aligned
5810 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5814 align
= pos
[0].align_to
;
5815 base_offset
= pos
[0].off
;
5816 for (i
= 1; i
< 3; i
++)
5817 if (align
< pos
[i
].align_to
)
5819 align
= pos
[i
].align_to
;
5820 base_offset
= pos
[i
].off
;
5822 for (i
= 0; i
< 3; i
++)
5823 pos
[i
].off
-= base_offset
;
5826 pos
[0].off
&= ~align
+ 1;
5827 pos
[1].off
&= ~align
+ 1;
5828 pos
[2].off
&= ~align
+ 1;
5830 /* If any two stores write to the same chunk, they also write to the
5831 same doubleword. The offsets are still sorted at this point. */
5832 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5835 /* A range of at least 9 bytes is needed for the stores to be in
5836 non-overlapping doublewords. */
5837 if (pos
[2].off
- pos
[0].off
<= 8)
5840 if (pos
[2].off
- pos
[1].off
>= 24
5841 || pos
[1].off
- pos
[0].off
>= 24
5842 || pos
[2].off
- pos
[0].off
>= 32)
5848 /* Return the number of nops that would be needed if instruction INSN
5849 immediately followed the MAX_NOPS instructions given by HIST,
5850 where HIST[0] is the most recent instruction. Ignore hazards
5851 between INSN and the first IGNORE instructions in HIST.
5853 If INSN is null, return the worse-case number of nops for any
5857 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5858 const struct mips_cl_insn
*insn
)
5860 int i
, nops
, tmp_nops
;
5863 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5865 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5866 if (tmp_nops
> nops
)
5870 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5872 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5873 if (tmp_nops
> nops
)
5877 if (mips_fix_24k
&& !mips_opts
.micromips
)
5879 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5880 if (tmp_nops
> nops
)
5887 /* The variable arguments provide NUM_INSNS extra instructions that
5888 might be added to HIST. Return the largest number of nops that
5889 would be needed after the extended sequence, ignoring hazards
5890 in the first IGNORE instructions. */
5893 nops_for_sequence (int num_insns
, int ignore
,
5894 const struct mips_cl_insn
*hist
, ...)
5897 struct mips_cl_insn buffer
[MAX_NOPS
];
5898 struct mips_cl_insn
*cursor
;
5901 va_start (args
, hist
);
5902 cursor
= buffer
+ num_insns
;
5903 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5904 while (cursor
> buffer
)
5905 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5907 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5912 /* Like nops_for_insn, but if INSN is a branch, take into account the
5913 worst-case delay for the branch target. */
5916 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5917 const struct mips_cl_insn
*insn
)
5921 nops
= nops_for_insn (ignore
, hist
, insn
);
5922 if (delayed_branch_p (insn
))
5924 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5925 hist
, insn
, get_delay_slot_nop (insn
));
5926 if (tmp_nops
> nops
)
5929 else if (compact_branch_p (insn
))
5931 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5932 if (tmp_nops
> nops
)
5938 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5941 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5943 gas_assert (!HAVE_CODE_COMPRESSION
);
5944 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5945 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5948 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5949 jr target pc &= 'hffff_ffff_cfff_ffff. */
5952 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5954 gas_assert (!HAVE_CODE_COMPRESSION
);
5955 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5956 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5957 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5965 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5966 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5969 ep
.X_op
= O_constant
;
5970 ep
.X_add_number
= 0xcfff0000;
5971 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5972 ep
.X_add_number
= 0xffff;
5973 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5974 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5979 fix_loongson2f (struct mips_cl_insn
* ip
)
5981 if (mips_fix_loongson2f_nop
)
5982 fix_loongson2f_nop (ip
);
5984 if (mips_fix_loongson2f_jump
)
5985 fix_loongson2f_jump (ip
);
5988 /* IP is a branch that has a delay slot, and we need to fill it
5989 automatically. Return true if we can do that by swapping IP
5990 with the previous instruction.
5991 ADDRESS_EXPR is an operand of the instruction to be used with
5995 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5996 bfd_reloc_code_real_type
*reloc_type
)
5998 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5999 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6001 /* -O2 and above is required for this optimization. */
6002 if (mips_optimize
< 2)
6005 /* If we have seen .set volatile or .set nomove, don't optimize. */
6006 if (mips_opts
.nomove
)
6009 /* We can't swap if the previous instruction's position is fixed. */
6010 if (history
[0].fixed_p
)
6013 /* If the previous previous insn was in a .set noreorder, we can't
6014 swap. Actually, the MIPS assembler will swap in this situation.
6015 However, gcc configured -with-gnu-as will generate code like
6023 in which we can not swap the bne and INSN. If gcc is not configured
6024 -with-gnu-as, it does not output the .set pseudo-ops. */
6025 if (history
[1].noreorder_p
)
6028 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6029 This means that the previous instruction was a 4-byte one anyhow. */
6030 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6033 /* If the branch is itself the target of a branch, we can not swap.
6034 We cheat on this; all we check for is whether there is a label on
6035 this instruction. If there are any branches to anything other than
6036 a label, users must use .set noreorder. */
6037 if (seg_info (now_seg
)->label_list
)
6040 /* If the previous instruction is in a variant frag other than this
6041 branch's one, we cannot do the swap. This does not apply to
6042 MIPS16 code, which uses variant frags for different purposes. */
6043 if (!mips_opts
.mips16
6045 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6048 /* We do not swap with instructions that cannot architecturally
6049 be placed in a branch delay slot, such as SYNC or ERET. We
6050 also refrain from swapping with a trap instruction, since it
6051 complicates trap handlers to have the trap instruction be in
6053 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6054 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6057 /* Check for conflicts between the branch and the instructions
6058 before the candidate delay slot. */
6059 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6062 /* Check for conflicts between the swapped sequence and the
6063 target of the branch. */
6064 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6067 /* If the branch reads a register that the previous
6068 instruction sets, we can not swap. */
6069 gpr_read
= gpr_read_mask (ip
);
6070 prev_gpr_write
= gpr_write_mask (&history
[0]);
6071 if (gpr_read
& prev_gpr_write
)
6074 /* If the branch writes a register that the previous
6075 instruction sets, we can not swap. */
6076 gpr_write
= gpr_write_mask (ip
);
6077 if (gpr_write
& prev_gpr_write
)
6080 /* If the branch writes a register that the previous
6081 instruction reads, we can not swap. */
6082 prev_gpr_read
= gpr_read_mask (&history
[0]);
6083 if (gpr_write
& prev_gpr_read
)
6086 /* If one instruction sets a condition code and the
6087 other one uses a condition code, we can not swap. */
6088 pinfo
= ip
->insn_mo
->pinfo
;
6089 if ((pinfo
& INSN_READ_COND_CODE
)
6090 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6092 if ((pinfo
& INSN_WRITE_COND_CODE
)
6093 && (prev_pinfo
& INSN_READ_COND_CODE
))
6096 /* If the previous instruction uses the PC, we can not swap. */
6097 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6098 if (prev_pinfo2
& INSN2_READ_PC
)
6101 /* If the previous instruction has an incorrect size for a fixed
6102 branch delay slot in microMIPS mode, we cannot swap. */
6103 pinfo2
= ip
->insn_mo
->pinfo2
;
6104 if (mips_opts
.micromips
6105 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6106 && insn_length (history
) != 2)
6108 if (mips_opts
.micromips
6109 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6110 && insn_length (history
) != 4)
6113 /* On R5900 short loops need to be fixed by inserting a nop in
6114 the branch delay slots.
6115 A short loop can be terminated too early. */
6116 if (mips_opts
.arch
== CPU_R5900
6117 /* Check if instruction has a parameter, ignore "j $31". */
6118 && (address_expr
!= NULL
)
6119 /* Parameter must be 16 bit. */
6120 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6121 /* Branch to same segment. */
6122 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6123 /* Branch to same code fragment. */
6124 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6125 /* Can only calculate branch offset if value is known. */
6126 && symbol_constant_p(address_expr
->X_add_symbol
)
6127 /* Check if branch is really conditional. */
6128 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6129 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6130 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6133 /* Check if loop is shorter than 6 instructions including
6134 branch and delay slot. */
6135 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6142 /* When the loop includes branches or jumps,
6143 it is not a short loop. */
6144 for (i
= 0; i
< (distance
/ 4); i
++)
6146 if ((history
[i
].cleared_p
)
6147 || delayed_branch_p(&history
[i
]))
6155 /* Insert nop after branch to fix short loop. */
6164 /* Decide how we should add IP to the instruction stream.
6165 ADDRESS_EXPR is an operand of the instruction to be used with
6168 static enum append_method
6169 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6170 bfd_reloc_code_real_type
*reloc_type
)
6172 /* The relaxed version of a macro sequence must be inherently
6174 if (mips_relax
.sequence
== 2)
6177 /* We must not dabble with instructions in a ".set norerorder" block. */
6178 if (mips_opts
.noreorder
)
6181 /* Otherwise, it's our responsibility to fill branch delay slots. */
6182 if (delayed_branch_p (ip
))
6184 if (!branch_likely_p (ip
)
6185 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6188 if (mips_opts
.mips16
6189 && ISA_SUPPORTS_MIPS16E
6190 && gpr_read_mask (ip
) != 0)
6191 return APPEND_ADD_COMPACT
;
6193 return APPEND_ADD_WITH_NOP
;
6199 /* IP is a MIPS16 instruction whose opcode we have just changed.
6200 Point IP->insn_mo to the new opcode's definition. */
6203 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6205 const struct mips_opcode
*mo
, *end
;
6207 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6208 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6209 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6217 /* For microMIPS macros, we need to generate a local number label
6218 as the target of branches. */
6219 #define MICROMIPS_LABEL_CHAR '\037'
6220 static unsigned long micromips_target_label
;
6221 static char micromips_target_name
[32];
6224 micromips_label_name (void)
6226 char *p
= micromips_target_name
;
6227 char symbol_name_temporary
[24];
6235 l
= micromips_target_label
;
6236 #ifdef LOCAL_LABEL_PREFIX
6237 *p
++ = LOCAL_LABEL_PREFIX
;
6240 *p
++ = MICROMIPS_LABEL_CHAR
;
6243 symbol_name_temporary
[i
++] = l
% 10 + '0';
6248 *p
++ = symbol_name_temporary
[--i
];
6251 return micromips_target_name
;
6255 micromips_label_expr (expressionS
*label_expr
)
6257 label_expr
->X_op
= O_symbol
;
6258 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6259 label_expr
->X_add_number
= 0;
6263 micromips_label_inc (void)
6265 micromips_target_label
++;
6266 *micromips_target_name
= '\0';
6270 micromips_add_label (void)
6274 s
= colon (micromips_label_name ());
6275 micromips_label_inc ();
6276 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6279 /* If assembling microMIPS code, then return the microMIPS reloc
6280 corresponding to the requested one if any. Otherwise return
6281 the reloc unchanged. */
6283 static bfd_reloc_code_real_type
6284 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6286 static const bfd_reloc_code_real_type relocs
[][2] =
6288 /* Keep sorted incrementally by the left-hand key. */
6289 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6290 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6291 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6292 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6293 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6294 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6295 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6296 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6297 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6298 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6299 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6300 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6301 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6302 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6303 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6304 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6305 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6306 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6307 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6308 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6309 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6310 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6311 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6312 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6313 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6314 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6315 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6317 bfd_reloc_code_real_type r
;
6320 if (!mips_opts
.micromips
)
6322 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6328 return relocs
[i
][1];
6333 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6334 Return true on success, storing the resolved value in RESULT. */
6337 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6342 case BFD_RELOC_MIPS_HIGHEST
:
6343 case BFD_RELOC_MICROMIPS_HIGHEST
:
6344 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6347 case BFD_RELOC_MIPS_HIGHER
:
6348 case BFD_RELOC_MICROMIPS_HIGHER
:
6349 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6352 case BFD_RELOC_HI16_S
:
6353 case BFD_RELOC_MICROMIPS_HI16_S
:
6354 case BFD_RELOC_MIPS16_HI16_S
:
6355 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6358 case BFD_RELOC_HI16
:
6359 case BFD_RELOC_MICROMIPS_HI16
:
6360 case BFD_RELOC_MIPS16_HI16
:
6361 *result
= (operand
>> 16) & 0xffff;
6364 case BFD_RELOC_LO16
:
6365 case BFD_RELOC_MICROMIPS_LO16
:
6366 case BFD_RELOC_MIPS16_LO16
:
6367 *result
= operand
& 0xffff;
6370 case BFD_RELOC_UNUSED
:
6379 /* Output an instruction. IP is the instruction information.
6380 ADDRESS_EXPR is an operand of the instruction to be used with
6381 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6382 a macro expansion. */
6385 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6386 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6388 unsigned long prev_pinfo2
, pinfo
;
6389 bfd_boolean relaxed_branch
= FALSE
;
6390 enum append_method method
;
6391 bfd_boolean relax32
;
6394 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6395 fix_loongson2f (ip
);
6397 file_ase_mips16
|= mips_opts
.mips16
;
6398 file_ase_micromips
|= mips_opts
.micromips
;
6400 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6401 pinfo
= ip
->insn_mo
->pinfo
;
6403 if (mips_opts
.micromips
6405 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6406 && micromips_insn_length (ip
->insn_mo
) != 2)
6407 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6408 && micromips_insn_length (ip
->insn_mo
) != 4)))
6409 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6410 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6412 if (address_expr
== NULL
)
6414 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6415 && reloc_type
[1] == BFD_RELOC_UNUSED
6416 && reloc_type
[2] == BFD_RELOC_UNUSED
6417 && address_expr
->X_op
== O_constant
)
6419 switch (*reloc_type
)
6421 case BFD_RELOC_MIPS_JMP
:
6425 shift
= mips_opts
.micromips
? 1 : 2;
6426 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6427 as_bad (_("jump to misaligned address (0x%lx)"),
6428 (unsigned long) address_expr
->X_add_number
);
6429 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6435 case BFD_RELOC_MIPS16_JMP
:
6436 if ((address_expr
->X_add_number
& 3) != 0)
6437 as_bad (_("jump to misaligned address (0x%lx)"),
6438 (unsigned long) address_expr
->X_add_number
);
6440 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6441 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6442 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6446 case BFD_RELOC_16_PCREL_S2
:
6450 shift
= mips_opts
.micromips
? 1 : 2;
6451 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6452 as_bad (_("branch to misaligned address (0x%lx)"),
6453 (unsigned long) address_expr
->X_add_number
);
6454 if (!mips_relax_branch
)
6456 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6457 & ~((1 << (shift
+ 16)) - 1))
6458 as_bad (_("branch address range overflow (0x%lx)"),
6459 (unsigned long) address_expr
->X_add_number
);
6460 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6470 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6473 ip
->insn_opcode
|= value
& 0xffff;
6481 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6483 /* There are a lot of optimizations we could do that we don't.
6484 In particular, we do not, in general, reorder instructions.
6485 If you use gcc with optimization, it will reorder
6486 instructions and generally do much more optimization then we
6487 do here; repeating all that work in the assembler would only
6488 benefit hand written assembly code, and does not seem worth
6490 int nops
= (mips_optimize
== 0
6491 ? nops_for_insn (0, history
, NULL
)
6492 : nops_for_insn_or_target (0, history
, ip
));
6496 unsigned long old_frag_offset
;
6499 old_frag
= frag_now
;
6500 old_frag_offset
= frag_now_fix ();
6502 for (i
= 0; i
< nops
; i
++)
6503 add_fixed_insn (NOP_INSN
);
6504 insert_into_history (0, nops
, NOP_INSN
);
6508 listing_prev_line ();
6509 /* We may be at the start of a variant frag. In case we
6510 are, make sure there is enough space for the frag
6511 after the frags created by listing_prev_line. The
6512 argument to frag_grow here must be at least as large
6513 as the argument to all other calls to frag_grow in
6514 this file. We don't have to worry about being in the
6515 middle of a variant frag, because the variants insert
6516 all needed nop instructions themselves. */
6520 mips_move_text_labels ();
6522 #ifndef NO_ECOFF_DEBUGGING
6523 if (ECOFF_DEBUGGING
)
6524 ecoff_fix_loc (old_frag
, old_frag_offset
);
6528 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6532 /* Work out how many nops in prev_nop_frag are needed by IP,
6533 ignoring hazards generated by the first prev_nop_frag_since
6535 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6536 gas_assert (nops
<= prev_nop_frag_holds
);
6538 /* Enforce NOPS as a minimum. */
6539 if (nops
> prev_nop_frag_required
)
6540 prev_nop_frag_required
= nops
;
6542 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6544 /* Settle for the current number of nops. Update the history
6545 accordingly (for the benefit of any future .set reorder code). */
6546 prev_nop_frag
= NULL
;
6547 insert_into_history (prev_nop_frag_since
,
6548 prev_nop_frag_holds
, NOP_INSN
);
6552 /* Allow this instruction to replace one of the nops that was
6553 tentatively added to prev_nop_frag. */
6554 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6555 prev_nop_frag_holds
--;
6556 prev_nop_frag_since
++;
6560 method
= get_append_method (ip
, address_expr
, reloc_type
);
6561 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6563 dwarf2_emit_insn (0);
6564 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6565 so "move" the instruction address accordingly.
6567 Also, it doesn't seem appropriate for the assembler to reorder .loc
6568 entries. If this instruction is a branch that we are going to swap
6569 with the previous instruction, the two instructions should be
6570 treated as a unit, and the debug information for both instructions
6571 should refer to the start of the branch sequence. Using the
6572 current position is certainly wrong when swapping a 32-bit branch
6573 and a 16-bit delay slot, since the current position would then be
6574 in the middle of a branch. */
6575 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6577 relax32
= (mips_relax_branch
6578 /* Don't try branch relaxation within .set nomacro, or within
6579 .set noat if we use $at for PIC computations. If it turns
6580 out that the branch was out-of-range, we'll get an error. */
6581 && !mips_opts
.warn_about_macros
6582 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6583 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6584 as they have no complementing branches. */
6585 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6587 if (!HAVE_CODE_COMPRESSION
6590 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6591 && delayed_branch_p (ip
))
6593 relaxed_branch
= TRUE
;
6594 add_relaxed_insn (ip
, (relaxed_branch_length
6596 uncond_branch_p (ip
) ? -1
6597 : branch_likely_p (ip
) ? 1
6601 uncond_branch_p (ip
),
6602 branch_likely_p (ip
),
6603 pinfo
& INSN_WRITE_GPR_31
,
6605 address_expr
->X_add_symbol
,
6606 address_expr
->X_add_number
);
6607 *reloc_type
= BFD_RELOC_UNUSED
;
6609 else if (mips_opts
.micromips
6611 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6612 || *reloc_type
> BFD_RELOC_UNUSED
)
6613 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6614 /* Don't try branch relaxation when users specify
6615 16-bit/32-bit instructions. */
6616 && !forced_insn_length
)
6618 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6619 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6620 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6621 int compact
= compact_branch_p (ip
);
6622 int al
= pinfo
& INSN_WRITE_GPR_31
;
6625 gas_assert (address_expr
!= NULL
);
6626 gas_assert (!mips_relax
.sequence
);
6628 relaxed_branch
= TRUE
;
6629 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6630 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6631 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6633 address_expr
->X_add_symbol
,
6634 address_expr
->X_add_number
);
6635 *reloc_type
= BFD_RELOC_UNUSED
;
6637 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6639 /* We need to set up a variant frag. */
6640 gas_assert (address_expr
!= NULL
);
6641 add_relaxed_insn (ip
, 4, 0,
6643 (*reloc_type
- BFD_RELOC_UNUSED
,
6644 forced_insn_length
== 2, forced_insn_length
== 4,
6645 delayed_branch_p (&history
[0]),
6646 history
[0].mips16_absolute_jump_p
),
6647 make_expr_symbol (address_expr
), 0);
6649 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6651 if (!delayed_branch_p (ip
))
6652 /* Make sure there is enough room to swap this instruction with
6653 a following jump instruction. */
6655 add_fixed_insn (ip
);
6659 if (mips_opts
.mips16
6660 && mips_opts
.noreorder
6661 && delayed_branch_p (&history
[0]))
6662 as_warn (_("extended instruction in delay slot"));
6664 if (mips_relax
.sequence
)
6666 /* If we've reached the end of this frag, turn it into a variant
6667 frag and record the information for the instructions we've
6669 if (frag_room () < 4)
6670 relax_close_frag ();
6671 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6674 if (mips_relax
.sequence
!= 2)
6676 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6677 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6678 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6679 mips_macro_warning
.insns
[0]++;
6681 if (mips_relax
.sequence
!= 1)
6683 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6684 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6685 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6686 mips_macro_warning
.insns
[1]++;
6689 if (mips_opts
.mips16
)
6692 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6694 add_fixed_insn (ip
);
6697 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6699 bfd_reloc_code_real_type final_type
[3];
6700 reloc_howto_type
*howto0
;
6701 reloc_howto_type
*howto
;
6704 /* Perform any necessary conversion to microMIPS relocations
6705 and find out how many relocations there actually are. */
6706 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6707 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6709 /* In a compound relocation, it is the final (outermost)
6710 operator that determines the relocated field. */
6711 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6716 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6717 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6718 bfd_get_reloc_size (howto
),
6720 howto0
&& howto0
->pc_relative
,
6723 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6724 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6725 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6727 /* These relocations can have an addend that won't fit in
6728 4 octets for 64bit assembly. */
6730 && ! howto
->partial_inplace
6731 && (reloc_type
[0] == BFD_RELOC_16
6732 || reloc_type
[0] == BFD_RELOC_32
6733 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6734 || reloc_type
[0] == BFD_RELOC_GPREL16
6735 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6736 || reloc_type
[0] == BFD_RELOC_GPREL32
6737 || reloc_type
[0] == BFD_RELOC_64
6738 || reloc_type
[0] == BFD_RELOC_CTOR
6739 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6740 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6741 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6742 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6743 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6744 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6745 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6746 || hi16_reloc_p (reloc_type
[0])
6747 || lo16_reloc_p (reloc_type
[0])))
6748 ip
->fixp
[0]->fx_no_overflow
= 1;
6750 /* These relocations can have an addend that won't fit in 2 octets. */
6751 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6752 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6753 ip
->fixp
[0]->fx_no_overflow
= 1;
6755 if (mips_relax
.sequence
)
6757 if (mips_relax
.first_fixup
== 0)
6758 mips_relax
.first_fixup
= ip
->fixp
[0];
6760 else if (reloc_needs_lo_p (*reloc_type
))
6762 struct mips_hi_fixup
*hi_fixup
;
6764 /* Reuse the last entry if it already has a matching %lo. */
6765 hi_fixup
= mips_hi_fixup_list
;
6767 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6769 hi_fixup
= ((struct mips_hi_fixup
*)
6770 xmalloc (sizeof (struct mips_hi_fixup
)));
6771 hi_fixup
->next
= mips_hi_fixup_list
;
6772 mips_hi_fixup_list
= hi_fixup
;
6774 hi_fixup
->fixp
= ip
->fixp
[0];
6775 hi_fixup
->seg
= now_seg
;
6778 /* Add fixups for the second and third relocations, if given.
6779 Note that the ABI allows the second relocation to be
6780 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6781 moment we only use RSS_UNDEF, but we could add support
6782 for the others if it ever becomes necessary. */
6783 for (i
= 1; i
< 3; i
++)
6784 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6786 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6787 ip
->fixp
[0]->fx_size
, NULL
, 0,
6788 FALSE
, final_type
[i
]);
6790 /* Use fx_tcbit to mark compound relocs. */
6791 ip
->fixp
[0]->fx_tcbit
= 1;
6792 ip
->fixp
[i
]->fx_tcbit
= 1;
6797 /* Update the register mask information. */
6798 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6799 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6804 insert_into_history (0, 1, ip
);
6807 case APPEND_ADD_WITH_NOP
:
6809 struct mips_cl_insn
*nop
;
6811 insert_into_history (0, 1, ip
);
6812 nop
= get_delay_slot_nop (ip
);
6813 add_fixed_insn (nop
);
6814 insert_into_history (0, 1, nop
);
6815 if (mips_relax
.sequence
)
6816 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6820 case APPEND_ADD_COMPACT
:
6821 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6822 gas_assert (mips_opts
.mips16
);
6823 ip
->insn_opcode
|= 0x0080;
6824 find_altered_mips16_opcode (ip
);
6826 insert_into_history (0, 1, ip
);
6831 struct mips_cl_insn delay
= history
[0];
6832 if (mips_opts
.mips16
)
6834 know (delay
.frag
== ip
->frag
);
6835 move_insn (ip
, delay
.frag
, delay
.where
);
6836 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6838 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6840 /* Add the delay slot instruction to the end of the
6841 current frag and shrink the fixed part of the
6842 original frag. If the branch occupies the tail of
6843 the latter, move it backwards to cover the gap. */
6844 delay
.frag
->fr_fix
-= branch_disp
;
6845 if (delay
.frag
== ip
->frag
)
6846 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6847 add_fixed_insn (&delay
);
6851 move_insn (&delay
, ip
->frag
,
6852 ip
->where
- branch_disp
+ insn_length (ip
));
6853 move_insn (ip
, history
[0].frag
, history
[0].where
);
6857 insert_into_history (0, 1, &delay
);
6862 /* If we have just completed an unconditional branch, clear the history. */
6863 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6864 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6868 mips_no_prev_insn ();
6870 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6871 history
[i
].cleared_p
= 1;
6874 /* We need to emit a label at the end of branch-likely macros. */
6875 if (emit_branch_likely_macro
)
6877 emit_branch_likely_macro
= FALSE
;
6878 micromips_add_label ();
6881 /* We just output an insn, so the next one doesn't have a label. */
6882 mips_clear_insn_labels ();
6885 /* Forget that there was any previous instruction or label.
6886 When BRANCH is true, the branch history is also flushed. */
6889 mips_no_prev_insn (void)
6891 prev_nop_frag
= NULL
;
6892 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6893 mips_clear_insn_labels ();
6896 /* This function must be called before we emit something other than
6897 instructions. It is like mips_no_prev_insn except that it inserts
6898 any NOPS that might be needed by previous instructions. */
6901 mips_emit_delays (void)
6903 if (! mips_opts
.noreorder
)
6905 int nops
= nops_for_insn (0, history
, NULL
);
6909 add_fixed_insn (NOP_INSN
);
6910 mips_move_text_labels ();
6913 mips_no_prev_insn ();
6916 /* Start a (possibly nested) noreorder block. */
6919 start_noreorder (void)
6921 if (mips_opts
.noreorder
== 0)
6926 /* None of the instructions before the .set noreorder can be moved. */
6927 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6928 history
[i
].fixed_p
= 1;
6930 /* Insert any nops that might be needed between the .set noreorder
6931 block and the previous instructions. We will later remove any
6932 nops that turn out not to be needed. */
6933 nops
= nops_for_insn (0, history
, NULL
);
6936 if (mips_optimize
!= 0)
6938 /* Record the frag which holds the nop instructions, so
6939 that we can remove them if we don't need them. */
6940 frag_grow (nops
* NOP_INSN_SIZE
);
6941 prev_nop_frag
= frag_now
;
6942 prev_nop_frag_holds
= nops
;
6943 prev_nop_frag_required
= 0;
6944 prev_nop_frag_since
= 0;
6947 for (; nops
> 0; --nops
)
6948 add_fixed_insn (NOP_INSN
);
6950 /* Move on to a new frag, so that it is safe to simply
6951 decrease the size of prev_nop_frag. */
6952 frag_wane (frag_now
);
6954 mips_move_text_labels ();
6956 mips_mark_labels ();
6957 mips_clear_insn_labels ();
6959 mips_opts
.noreorder
++;
6960 mips_any_noreorder
= 1;
6963 /* End a nested noreorder block. */
6966 end_noreorder (void)
6968 mips_opts
.noreorder
--;
6969 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6971 /* Commit to inserting prev_nop_frag_required nops and go back to
6972 handling nop insertion the .set reorder way. */
6973 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6975 insert_into_history (prev_nop_frag_since
,
6976 prev_nop_frag_required
, NOP_INSN
);
6977 prev_nop_frag
= NULL
;
6981 /* Sign-extend 32-bit mode constants that have bit 31 set and all
6982 higher bits unset. */
6985 normalize_constant_expr (expressionS
*ex
)
6987 if (ex
->X_op
== O_constant
6988 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
6989 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
6993 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
6994 all higher bits unset. */
6997 normalize_address_expr (expressionS
*ex
)
6999 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7000 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7001 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7002 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7006 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7007 Return true if the match was successful.
7009 OPCODE_EXTRA is a value that should be ORed into the opcode
7010 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7011 there are more alternatives after OPCODE and SOFT_MATCH is
7012 as for mips_arg_info. */
7015 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7016 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7017 bfd_boolean lax_match
, bfd_boolean complete_p
)
7020 struct mips_arg_info arg
;
7021 const struct mips_operand
*operand
;
7024 imm_expr
.X_op
= O_absent
;
7025 offset_expr
.X_op
= O_absent
;
7026 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7027 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7028 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7030 create_insn (insn
, opcode
);
7031 /* When no opcode suffix is specified, assume ".xyzw". */
7032 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7033 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7035 insn
->insn_opcode
|= opcode_extra
;
7036 memset (&arg
, 0, sizeof (arg
));
7040 arg
.last_regno
= ILLEGAL_REG
;
7041 arg
.dest_regno
= ILLEGAL_REG
;
7042 arg
.lax_match
= lax_match
;
7043 for (args
= opcode
->args
;; ++args
)
7045 if (arg
.token
->type
== OT_END
)
7047 /* Handle unary instructions in which only one operand is given.
7048 The source is then the same as the destination. */
7049 if (arg
.opnum
== 1 && *args
== ',')
7051 operand
= (mips_opts
.micromips
7052 ? decode_micromips_operand (args
+ 1)
7053 : decode_mips_operand (args
+ 1));
7054 if (operand
&& mips_optional_operand_p (operand
))
7062 /* Treat elided base registers as $0. */
7063 if (strcmp (args
, "(b)") == 0)
7071 /* The register suffix is optional. */
7076 /* Fail the match if there were too few operands. */
7080 /* Successful match. */
7083 clear_insn_error ();
7084 if (arg
.dest_regno
== arg
.last_regno
7085 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7089 (0, _("Source and destination must be different"));
7090 else if (arg
.last_regno
== 31)
7092 (0, _("A destination register must be supplied"));
7094 check_completed_insn (&arg
);
7098 /* Fail the match if the line has too many operands. */
7102 /* Handle characters that need to match exactly. */
7103 if (*args
== '(' || *args
== ')' || *args
== ',')
7105 if (match_char (&arg
, *args
))
7112 if (arg
.token
->type
== OT_DOUBLE_CHAR
7113 && arg
.token
->u
.ch
== *args
)
7121 /* Handle special macro operands. Work out the properties of
7130 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7136 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7138 imm_expr
.X_op
= O_constant
;
7139 if (HAVE_32BIT_GPRS
)
7140 normalize_constant_expr (&imm_expr
);
7144 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7146 /* Assume that the offset has been elided and that what
7147 we saw was a base register. The match will fail later
7148 if that assumption turns out to be wrong. */
7149 offset_expr
.X_op
= O_constant
;
7150 offset_expr
.X_add_number
= 0;
7154 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7156 normalize_address_expr (&offset_expr
);
7161 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7167 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7173 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7179 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7185 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7189 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7193 gas_assert (mips_opts
.micromips
);
7199 if (!forced_insn_length
)
7200 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7202 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7204 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7210 operand
= (mips_opts
.micromips
7211 ? decode_micromips_operand (args
)
7212 : decode_mips_operand (args
));
7216 /* Skip prefixes. */
7217 if (*args
== '+' || *args
== 'm')
7220 if (mips_optional_operand_p (operand
)
7222 && (arg
.token
[0].type
!= OT_REG
7223 || arg
.token
[1].type
== OT_END
))
7225 /* Assume that the register has been elided and is the
7226 same as the first operand. */
7231 if (!match_operand (&arg
, operand
))
7236 /* Like match_insn, but for MIPS16. */
7239 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7240 struct mips_operand_token
*tokens
)
7243 const struct mips_operand
*operand
;
7244 const struct mips_operand
*ext_operand
;
7245 struct mips_arg_info arg
;
7248 create_insn (insn
, opcode
);
7249 imm_expr
.X_op
= O_absent
;
7250 offset_expr
.X_op
= O_absent
;
7251 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7252 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7253 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7256 memset (&arg
, 0, sizeof (arg
));
7260 arg
.last_regno
= ILLEGAL_REG
;
7261 arg
.dest_regno
= ILLEGAL_REG
;
7263 for (args
= opcode
->args
;; ++args
)
7267 if (arg
.token
->type
== OT_END
)
7271 /* Handle unary instructions in which only one operand is given.
7272 The source is then the same as the destination. */
7273 if (arg
.opnum
== 1 && *args
== ',')
7275 operand
= decode_mips16_operand (args
[1], FALSE
);
7276 if (operand
&& mips_optional_operand_p (operand
))
7284 /* Fail the match if there were too few operands. */
7288 /* Successful match. Stuff the immediate value in now, if
7290 clear_insn_error ();
7291 if (opcode
->pinfo
== INSN_MACRO
)
7293 gas_assert (relax_char
== 0 || relax_char
== 'p');
7294 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7297 && offset_expr
.X_op
== O_constant
7298 && calculate_reloc (*offset_reloc
,
7299 offset_expr
.X_add_number
,
7302 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7303 forced_insn_length
, &insn
->insn_opcode
);
7304 offset_expr
.X_op
= O_absent
;
7305 *offset_reloc
= BFD_RELOC_UNUSED
;
7307 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7309 if (forced_insn_length
== 2)
7310 set_insn_error (0, _("invalid unextended operand value"));
7311 forced_insn_length
= 4;
7312 insn
->insn_opcode
|= MIPS16_EXTEND
;
7314 else if (relax_char
)
7315 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7317 check_completed_insn (&arg
);
7321 /* Fail the match if the line has too many operands. */
7325 /* Handle characters that need to match exactly. */
7326 if (*args
== '(' || *args
== ')' || *args
== ',')
7328 if (match_char (&arg
, *args
))
7346 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7348 imm_expr
.X_op
= O_constant
;
7349 if (HAVE_32BIT_GPRS
)
7350 normalize_constant_expr (&imm_expr
);
7355 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7356 insn
->insn_opcode
<<= 16;
7360 operand
= decode_mips16_operand (c
, FALSE
);
7364 /* '6' is a special case. It is used for BREAK and SDBBP,
7365 whose operands are only meaningful to the software that decodes
7366 them. This means that there is no architectural reason why
7367 they cannot be prefixed by EXTEND, but in practice,
7368 exception handlers will only look at the instruction
7369 itself. We therefore allow '6' to be extended when
7370 disassembling but not when assembling. */
7371 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7373 ext_operand
= decode_mips16_operand (c
, TRUE
);
7374 if (operand
!= ext_operand
)
7376 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7378 offset_expr
.X_op
= O_constant
;
7379 offset_expr
.X_add_number
= 0;
7384 /* We need the OT_INTEGER check because some MIPS16
7385 immediate variants are listed before the register ones. */
7386 if (arg
.token
->type
!= OT_INTEGER
7387 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7390 /* '8' is used for SLTI(U) and has traditionally not
7391 been allowed to take relocation operators. */
7392 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7393 && (ext_operand
->size
!= 16 || c
== '8'))
7401 if (mips_optional_operand_p (operand
)
7403 && (arg
.token
[0].type
!= OT_REG
7404 || arg
.token
[1].type
== OT_END
))
7406 /* Assume that the register has been elided and is the
7407 same as the first operand. */
7412 if (!match_operand (&arg
, operand
))
7417 /* Record that the current instruction is invalid for the current ISA. */
7420 match_invalid_for_isa (void)
7423 (0, _("Opcode not supported on this processor: %s (%s)"),
7424 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7425 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7428 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7429 Return true if a definite match or failure was found, storing any match
7430 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7431 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7432 tried and failed to match under normal conditions and now want to try a
7433 more relaxed match. */
7436 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7437 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7438 int opcode_extra
, bfd_boolean lax_match
)
7440 const struct mips_opcode
*opcode
;
7441 const struct mips_opcode
*invalid_delay_slot
;
7442 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7444 /* Search for a match, ignoring alternatives that don't satisfy the
7445 current ISA or forced_length. */
7446 invalid_delay_slot
= 0;
7447 seen_valid_for_isa
= FALSE
;
7448 seen_valid_for_size
= FALSE
;
7452 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7453 if (is_opcode_valid (opcode
))
7455 seen_valid_for_isa
= TRUE
;
7456 if (is_size_valid (opcode
))
7458 bfd_boolean delay_slot_ok
;
7460 seen_valid_for_size
= TRUE
;
7461 delay_slot_ok
= is_delay_slot_valid (opcode
);
7462 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7463 lax_match
, delay_slot_ok
))
7467 if (!invalid_delay_slot
)
7468 invalid_delay_slot
= opcode
;
7477 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7479 /* If the only matches we found had the wrong length for the delay slot,
7480 pick the first such match. We'll issue an appropriate warning later. */
7481 if (invalid_delay_slot
)
7483 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7489 /* Handle the case where we didn't try to match an instruction because
7490 all the alternatives were incompatible with the current ISA. */
7491 if (!seen_valid_for_isa
)
7493 match_invalid_for_isa ();
7497 /* Handle the case where we didn't try to match an instruction because
7498 all the alternatives were of the wrong size. */
7499 if (!seen_valid_for_size
)
7501 if (mips_opts
.insn32
)
7502 set_insn_error (0, _("Opcode not supported in the `insn32' mode"));
7505 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
7506 8 * forced_insn_length
);
7513 /* Like match_insns, but for MIPS16. */
7516 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7517 struct mips_operand_token
*tokens
)
7519 const struct mips_opcode
*opcode
;
7520 bfd_boolean seen_valid_for_isa
;
7522 /* Search for a match, ignoring alternatives that don't satisfy the
7523 current ISA. There are no separate entries for extended forms so
7524 we deal with forced_length later. */
7525 seen_valid_for_isa
= FALSE
;
7529 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7530 if (is_opcode_valid_16 (opcode
))
7532 seen_valid_for_isa
= TRUE
;
7533 if (match_mips16_insn (insn
, opcode
, tokens
))
7538 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7539 && strcmp (opcode
->name
, first
->name
) == 0);
7541 /* Handle the case where we didn't try to match an instruction because
7542 all the alternatives were incompatible with the current ISA. */
7543 if (!seen_valid_for_isa
)
7545 match_invalid_for_isa ();
7552 /* Set up global variables for the start of a new macro. */
7557 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7558 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7559 sizeof (mips_macro_warning
.first_insn_sizes
));
7560 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7561 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7562 && delayed_branch_p (&history
[0]));
7563 switch (history
[0].insn_mo
->pinfo2
7564 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7566 case INSN2_BRANCH_DELAY_32BIT
:
7567 mips_macro_warning
.delay_slot_length
= 4;
7569 case INSN2_BRANCH_DELAY_16BIT
:
7570 mips_macro_warning
.delay_slot_length
= 2;
7573 mips_macro_warning
.delay_slot_length
= 0;
7576 mips_macro_warning
.first_frag
= NULL
;
7579 /* Given that a macro is longer than one instruction or of the wrong size,
7580 return the appropriate warning for it. Return null if no warning is
7581 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7582 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7583 and RELAX_NOMACRO. */
7586 macro_warning (relax_substateT subtype
)
7588 if (subtype
& RELAX_DELAY_SLOT
)
7589 return _("Macro instruction expanded into multiple instructions"
7590 " in a branch delay slot");
7591 else if (subtype
& RELAX_NOMACRO
)
7592 return _("Macro instruction expanded into multiple instructions");
7593 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7594 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7595 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7596 ? _("Macro instruction expanded into a wrong size instruction"
7597 " in a 16-bit branch delay slot")
7598 : _("Macro instruction expanded into a wrong size instruction"
7599 " in a 32-bit branch delay slot"));
7604 /* Finish up a macro. Emit warnings as appropriate. */
7609 /* Relaxation warning flags. */
7610 relax_substateT subtype
= 0;
7612 /* Check delay slot size requirements. */
7613 if (mips_macro_warning
.delay_slot_length
== 2)
7614 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7615 if (mips_macro_warning
.delay_slot_length
!= 0)
7617 if (mips_macro_warning
.delay_slot_length
7618 != mips_macro_warning
.first_insn_sizes
[0])
7619 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7620 if (mips_macro_warning
.delay_slot_length
7621 != mips_macro_warning
.first_insn_sizes
[1])
7622 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7625 /* Check instruction count requirements. */
7626 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7628 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7629 subtype
|= RELAX_SECOND_LONGER
;
7630 if (mips_opts
.warn_about_macros
)
7631 subtype
|= RELAX_NOMACRO
;
7632 if (mips_macro_warning
.delay_slot_p
)
7633 subtype
|= RELAX_DELAY_SLOT
;
7636 /* If both alternatives fail to fill a delay slot correctly,
7637 emit the warning now. */
7638 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7639 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7644 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7645 | RELAX_DELAY_SLOT_SIZE_FIRST
7646 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7647 msg
= macro_warning (s
);
7649 as_warn ("%s", msg
);
7653 /* If both implementations are longer than 1 instruction, then emit the
7655 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7660 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7661 msg
= macro_warning (s
);
7663 as_warn ("%s", msg
);
7667 /* If any flags still set, then one implementation might need a warning
7668 and the other either will need one of a different kind or none at all.
7669 Pass any remaining flags over to relaxation. */
7670 if (mips_macro_warning
.first_frag
!= NULL
)
7671 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7674 /* Instruction operand formats used in macros that vary between
7675 standard MIPS and microMIPS code. */
7677 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7678 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7679 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7680 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7681 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7682 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7683 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7684 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7686 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7687 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7688 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7689 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7690 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7691 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7692 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7693 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7695 /* Read a macro's relocation codes from *ARGS and store them in *R.
7696 The first argument in *ARGS will be either the code for a single
7697 relocation or -1 followed by the three codes that make up a
7698 composite relocation. */
7701 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7705 next
= va_arg (*args
, int);
7707 r
[0] = (bfd_reloc_code_real_type
) next
;
7710 for (i
= 0; i
< 3; i
++)
7711 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7712 /* This function is only used for 16-bit relocation fields.
7713 To make the macro code simpler, treat an unrelocated value
7714 in the same way as BFD_RELOC_LO16. */
7715 if (r
[0] == BFD_RELOC_UNUSED
)
7716 r
[0] = BFD_RELOC_LO16
;
7720 /* Build an instruction created by a macro expansion. This is passed
7721 a pointer to the count of instructions created so far, an
7722 expression, the name of the instruction to build, an operand format
7723 string, and corresponding arguments. */
7726 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7728 const struct mips_opcode
*mo
= NULL
;
7729 bfd_reloc_code_real_type r
[3];
7730 const struct mips_opcode
*amo
;
7731 const struct mips_operand
*operand
;
7732 struct hash_control
*hash
;
7733 struct mips_cl_insn insn
;
7737 va_start (args
, fmt
);
7739 if (mips_opts
.mips16
)
7741 mips16_macro_build (ep
, name
, fmt
, &args
);
7746 r
[0] = BFD_RELOC_UNUSED
;
7747 r
[1] = BFD_RELOC_UNUSED
;
7748 r
[2] = BFD_RELOC_UNUSED
;
7749 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7750 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7752 gas_assert (strcmp (name
, amo
->name
) == 0);
7756 /* Search until we get a match for NAME. It is assumed here that
7757 macros will never generate MDMX, MIPS-3D, or MT instructions.
7758 We try to match an instruction that fulfils the branch delay
7759 slot instruction length requirement (if any) of the previous
7760 instruction. While doing this we record the first instruction
7761 seen that matches all the other conditions and use it anyway
7762 if the requirement cannot be met; we will issue an appropriate
7763 warning later on. */
7764 if (strcmp (fmt
, amo
->args
) == 0
7765 && amo
->pinfo
!= INSN_MACRO
7766 && is_opcode_valid (amo
)
7767 && is_size_valid (amo
))
7769 if (is_delay_slot_valid (amo
))
7779 gas_assert (amo
->name
);
7781 while (strcmp (name
, amo
->name
) == 0);
7784 create_insn (&insn
, mo
);
7797 macro_read_relocs (&args
, r
);
7798 gas_assert (*r
== BFD_RELOC_GPREL16
7799 || *r
== BFD_RELOC_MIPS_HIGHER
7800 || *r
== BFD_RELOC_HI16_S
7801 || *r
== BFD_RELOC_LO16
7802 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7806 macro_read_relocs (&args
, r
);
7810 macro_read_relocs (&args
, r
);
7811 gas_assert (ep
!= NULL
7812 && (ep
->X_op
== O_constant
7813 || (ep
->X_op
== O_symbol
7814 && (*r
== BFD_RELOC_MIPS_HIGHEST
7815 || *r
== BFD_RELOC_HI16_S
7816 || *r
== BFD_RELOC_HI16
7817 || *r
== BFD_RELOC_GPREL16
7818 || *r
== BFD_RELOC_MIPS_GOT_HI16
7819 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7823 gas_assert (ep
!= NULL
);
7826 * This allows macro() to pass an immediate expression for
7827 * creating short branches without creating a symbol.
7829 * We don't allow branch relaxation for these branches, as
7830 * they should only appear in ".set nomacro" anyway.
7832 if (ep
->X_op
== O_constant
)
7834 /* For microMIPS we always use relocations for branches.
7835 So we should not resolve immediate values. */
7836 gas_assert (!mips_opts
.micromips
);
7838 if ((ep
->X_add_number
& 3) != 0)
7839 as_bad (_("branch to misaligned address (0x%lx)"),
7840 (unsigned long) ep
->X_add_number
);
7841 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7842 as_bad (_("branch address range overflow (0x%lx)"),
7843 (unsigned long) ep
->X_add_number
);
7844 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7848 *r
= BFD_RELOC_16_PCREL_S2
;
7852 gas_assert (ep
!= NULL
);
7853 *r
= BFD_RELOC_MIPS_JMP
;
7857 operand
= (mips_opts
.micromips
7858 ? decode_micromips_operand (fmt
)
7859 : decode_mips_operand (fmt
));
7863 uval
= va_arg (args
, int);
7864 if (operand
->type
== OP_CLO_CLZ_DEST
)
7865 uval
|= (uval
<< 5);
7866 insn_insert_operand (&insn
, operand
, uval
);
7868 if (*fmt
== '+' || *fmt
== 'm')
7874 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7876 append_insn (&insn
, ep
, r
, TRUE
);
7880 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7883 struct mips_opcode
*mo
;
7884 struct mips_cl_insn insn
;
7885 const struct mips_operand
*operand
;
7886 bfd_reloc_code_real_type r
[3]
7887 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7889 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7891 gas_assert (strcmp (name
, mo
->name
) == 0);
7893 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7896 gas_assert (mo
->name
);
7897 gas_assert (strcmp (name
, mo
->name
) == 0);
7900 create_insn (&insn
, mo
);
7938 gas_assert (ep
!= NULL
);
7940 if (ep
->X_op
!= O_constant
)
7941 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7942 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7944 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7946 *r
= BFD_RELOC_UNUSED
;
7952 operand
= decode_mips16_operand (c
, FALSE
);
7956 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7961 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7963 append_insn (&insn
, ep
, r
, TRUE
);
7967 * Generate a "jalr" instruction with a relocation hint to the called
7968 * function. This occurs in NewABI PIC code.
7971 macro_build_jalr (expressionS
*ep
, int cprestore
)
7973 static const bfd_reloc_code_real_type jalr_relocs
[2]
7974 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7975 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7979 if (MIPS_JALR_HINT_P (ep
))
7984 if (mips_opts
.micromips
)
7986 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7987 ? "jalr" : "jalrs");
7988 if (MIPS_JALR_HINT_P (ep
)
7990 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7991 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7993 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7996 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7997 if (MIPS_JALR_HINT_P (ep
))
7998 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8002 * Generate a "lui" instruction.
8005 macro_build_lui (expressionS
*ep
, int regnum
)
8007 gas_assert (! mips_opts
.mips16
);
8009 if (ep
->X_op
!= O_constant
)
8011 gas_assert (ep
->X_op
== O_symbol
);
8012 /* _gp_disp is a special case, used from s_cpload.
8013 __gnu_local_gp is used if mips_no_shared. */
8014 gas_assert (mips_pic
== NO_PIC
8016 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8017 || (! mips_in_shared
8018 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8019 "__gnu_local_gp") == 0));
8022 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8025 /* Generate a sequence of instructions to do a load or store from a constant
8026 offset off of a base register (breg) into/from a target register (treg),
8027 using AT if necessary. */
8029 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8030 int treg
, int breg
, int dbl
)
8032 gas_assert (ep
->X_op
== O_constant
);
8034 /* Sign-extending 32-bit constants makes their handling easier. */
8036 normalize_constant_expr (ep
);
8038 /* Right now, this routine can only handle signed 32-bit constants. */
8039 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8040 as_warn (_("operand overflow"));
8042 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8044 /* Signed 16-bit offset will fit in the op. Easy! */
8045 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8049 /* 32-bit offset, need multiple instructions and AT, like:
8050 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8051 addu $tempreg,$tempreg,$breg
8052 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8053 to handle the complete offset. */
8054 macro_build_lui (ep
, AT
);
8055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8056 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8059 as_bad (_("Macro used $at after \".set noat\""));
8064 * Generates code to set the $at register to true (one)
8065 * if reg is less than the immediate expression.
8068 set_at (int reg
, int unsignedp
)
8070 if (imm_expr
.X_op
== O_constant
8071 && imm_expr
.X_add_number
>= -0x8000
8072 && imm_expr
.X_add_number
< 0x8000)
8073 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8074 AT
, reg
, BFD_RELOC_LO16
);
8077 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8078 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8082 /* Count the leading zeroes by performing a binary chop. This is a
8083 bulky bit of source, but performance is a LOT better for the
8084 majority of values than a simple loop to count the bits:
8085 for (lcnt = 0; (lcnt < 32); lcnt++)
8086 if ((v) & (1 << (31 - lcnt)))
8088 However it is not code size friendly, and the gain will drop a bit
8089 on certain cached systems.
8091 #define COUNT_TOP_ZEROES(v) \
8092 (((v) & ~0xffff) == 0 \
8093 ? ((v) & ~0xff) == 0 \
8094 ? ((v) & ~0xf) == 0 \
8095 ? ((v) & ~0x3) == 0 \
8096 ? ((v) & ~0x1) == 0 \
8101 : ((v) & ~0x7) == 0 \
8104 : ((v) & ~0x3f) == 0 \
8105 ? ((v) & ~0x1f) == 0 \
8108 : ((v) & ~0x7f) == 0 \
8111 : ((v) & ~0xfff) == 0 \
8112 ? ((v) & ~0x3ff) == 0 \
8113 ? ((v) & ~0x1ff) == 0 \
8116 : ((v) & ~0x7ff) == 0 \
8119 : ((v) & ~0x3fff) == 0 \
8120 ? ((v) & ~0x1fff) == 0 \
8123 : ((v) & ~0x7fff) == 0 \
8126 : ((v) & ~0xffffff) == 0 \
8127 ? ((v) & ~0xfffff) == 0 \
8128 ? ((v) & ~0x3ffff) == 0 \
8129 ? ((v) & ~0x1ffff) == 0 \
8132 : ((v) & ~0x7ffff) == 0 \
8135 : ((v) & ~0x3fffff) == 0 \
8136 ? ((v) & ~0x1fffff) == 0 \
8139 : ((v) & ~0x7fffff) == 0 \
8142 : ((v) & ~0xfffffff) == 0 \
8143 ? ((v) & ~0x3ffffff) == 0 \
8144 ? ((v) & ~0x1ffffff) == 0 \
8147 : ((v) & ~0x7ffffff) == 0 \
8150 : ((v) & ~0x3fffffff) == 0 \
8151 ? ((v) & ~0x1fffffff) == 0 \
8154 : ((v) & ~0x7fffffff) == 0 \
8159 * This routine generates the least number of instructions necessary to load
8160 * an absolute expression value into a register.
8163 load_register (int reg
, expressionS
*ep
, int dbl
)
8166 expressionS hi32
, lo32
;
8168 if (ep
->X_op
!= O_big
)
8170 gas_assert (ep
->X_op
== O_constant
);
8172 /* Sign-extending 32-bit constants makes their handling easier. */
8174 normalize_constant_expr (ep
);
8176 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8178 /* We can handle 16 bit signed values with an addiu to
8179 $zero. No need to ever use daddiu here, since $zero and
8180 the result are always correct in 32 bit mode. */
8181 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8184 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8186 /* We can handle 16 bit unsigned values with an ori to
8188 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8191 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8193 /* 32 bit values require an lui. */
8194 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8195 if ((ep
->X_add_number
& 0xffff) != 0)
8196 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8201 /* The value is larger than 32 bits. */
8203 if (!dbl
|| HAVE_32BIT_GPRS
)
8207 sprintf_vma (value
, ep
->X_add_number
);
8208 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8209 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8213 if (ep
->X_op
!= O_big
)
8216 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8217 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8218 hi32
.X_add_number
&= 0xffffffff;
8220 lo32
.X_add_number
&= 0xffffffff;
8224 gas_assert (ep
->X_add_number
> 2);
8225 if (ep
->X_add_number
== 3)
8226 generic_bignum
[3] = 0;
8227 else if (ep
->X_add_number
> 4)
8228 as_bad (_("Number larger than 64 bits"));
8229 lo32
.X_op
= O_constant
;
8230 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8231 hi32
.X_op
= O_constant
;
8232 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8235 if (hi32
.X_add_number
== 0)
8240 unsigned long hi
, lo
;
8242 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8244 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8246 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8249 if (lo32
.X_add_number
& 0x80000000)
8251 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8252 if (lo32
.X_add_number
& 0xffff)
8253 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8258 /* Check for 16bit shifted constant. We know that hi32 is
8259 non-zero, so start the mask on the first bit of the hi32
8264 unsigned long himask
, lomask
;
8268 himask
= 0xffff >> (32 - shift
);
8269 lomask
= (0xffff << shift
) & 0xffffffff;
8273 himask
= 0xffff << (shift
- 32);
8276 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8277 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8281 tmp
.X_op
= O_constant
;
8283 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8284 | (lo32
.X_add_number
>> shift
));
8286 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8287 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8288 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8289 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8294 while (shift
<= (64 - 16));
8296 /* Find the bit number of the lowest one bit, and store the
8297 shifted value in hi/lo. */
8298 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8299 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8303 while ((lo
& 1) == 0)
8308 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8314 while ((hi
& 1) == 0)
8323 /* Optimize if the shifted value is a (power of 2) - 1. */
8324 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8325 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8327 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8332 /* This instruction will set the register to be all
8334 tmp
.X_op
= O_constant
;
8335 tmp
.X_add_number
= (offsetT
) -1;
8336 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8340 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8341 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8343 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8344 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8349 /* Sign extend hi32 before calling load_register, because we can
8350 generally get better code when we load a sign extended value. */
8351 if ((hi32
.X_add_number
& 0x80000000) != 0)
8352 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8353 load_register (reg
, &hi32
, 0);
8356 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8360 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8368 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8370 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8371 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8377 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8381 mid16
.X_add_number
>>= 16;
8382 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8383 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8386 if ((lo32
.X_add_number
& 0xffff) != 0)
8387 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8391 load_delay_nop (void)
8393 if (!gpr_interlocks
)
8394 macro_build (NULL
, "nop", "");
8397 /* Load an address into a register. */
8400 load_address (int reg
, expressionS
*ep
, int *used_at
)
8402 if (ep
->X_op
!= O_constant
8403 && ep
->X_op
!= O_symbol
)
8405 as_bad (_("expression too complex"));
8406 ep
->X_op
= O_constant
;
8409 if (ep
->X_op
== O_constant
)
8411 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8415 if (mips_pic
== NO_PIC
)
8417 /* If this is a reference to a GP relative symbol, we want
8418 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8420 lui $reg,<sym> (BFD_RELOC_HI16_S)
8421 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8422 If we have an addend, we always use the latter form.
8424 With 64bit address space and a usable $at we want
8425 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8426 lui $at,<sym> (BFD_RELOC_HI16_S)
8427 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8428 daddiu $at,<sym> (BFD_RELOC_LO16)
8432 If $at is already in use, we use a path which is suboptimal
8433 on superscalar processors.
8434 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8435 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8437 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8439 daddiu $reg,<sym> (BFD_RELOC_LO16)
8441 For GP relative symbols in 64bit address space we can use
8442 the same sequence as in 32bit address space. */
8443 if (HAVE_64BIT_SYMBOLS
)
8445 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8446 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8448 relax_start (ep
->X_add_symbol
);
8449 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8450 mips_gp_register
, BFD_RELOC_GPREL16
);
8454 if (*used_at
== 0 && mips_opts
.at
)
8456 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8457 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8458 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8459 BFD_RELOC_MIPS_HIGHER
);
8460 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8461 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8462 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8467 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8468 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8469 BFD_RELOC_MIPS_HIGHER
);
8470 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8471 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8472 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8473 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8476 if (mips_relax
.sequence
)
8481 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8482 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8484 relax_start (ep
->X_add_symbol
);
8485 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8486 mips_gp_register
, BFD_RELOC_GPREL16
);
8489 macro_build_lui (ep
, reg
);
8490 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8491 reg
, reg
, BFD_RELOC_LO16
);
8492 if (mips_relax
.sequence
)
8496 else if (!mips_big_got
)
8500 /* If this is a reference to an external symbol, we want
8501 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8503 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8505 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8506 If there is a constant, it must be added in after.
8508 If we have NewABI, we want
8509 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8510 unless we're referencing a global symbol with a non-zero
8511 offset, in which case cst must be added separately. */
8514 if (ep
->X_add_number
)
8516 ex
.X_add_number
= ep
->X_add_number
;
8517 ep
->X_add_number
= 0;
8518 relax_start (ep
->X_add_symbol
);
8519 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8520 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8521 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8522 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8523 ex
.X_op
= O_constant
;
8524 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8525 reg
, reg
, BFD_RELOC_LO16
);
8526 ep
->X_add_number
= ex
.X_add_number
;
8529 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8530 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8531 if (mips_relax
.sequence
)
8536 ex
.X_add_number
= ep
->X_add_number
;
8537 ep
->X_add_number
= 0;
8538 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8539 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8541 relax_start (ep
->X_add_symbol
);
8543 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8547 if (ex
.X_add_number
!= 0)
8549 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8550 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8551 ex
.X_op
= O_constant
;
8552 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8553 reg
, reg
, BFD_RELOC_LO16
);
8557 else if (mips_big_got
)
8561 /* This is the large GOT case. If this is a reference to an
8562 external symbol, we want
8563 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8565 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8567 Otherwise, for a reference to a local symbol in old ABI, we want
8568 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8570 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8571 If there is a constant, it must be added in after.
8573 In the NewABI, for local symbols, with or without offsets, we want:
8574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8575 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8579 ex
.X_add_number
= ep
->X_add_number
;
8580 ep
->X_add_number
= 0;
8581 relax_start (ep
->X_add_symbol
);
8582 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8583 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8584 reg
, reg
, mips_gp_register
);
8585 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8586 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8587 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8588 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8589 else if (ex
.X_add_number
)
8591 ex
.X_op
= O_constant
;
8592 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8596 ep
->X_add_number
= ex
.X_add_number
;
8598 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8599 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8600 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8601 BFD_RELOC_MIPS_GOT_OFST
);
8606 ex
.X_add_number
= ep
->X_add_number
;
8607 ep
->X_add_number
= 0;
8608 relax_start (ep
->X_add_symbol
);
8609 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8611 reg
, reg
, mips_gp_register
);
8612 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8613 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8615 if (reg_needs_delay (mips_gp_register
))
8617 /* We need a nop before loading from $gp. This special
8618 check is required because the lui which starts the main
8619 instruction stream does not refer to $gp, and so will not
8620 insert the nop which may be required. */
8621 macro_build (NULL
, "nop", "");
8623 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8624 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8626 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8630 if (ex
.X_add_number
!= 0)
8632 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8633 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8634 ex
.X_op
= O_constant
;
8635 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8643 if (!mips_opts
.at
&& *used_at
== 1)
8644 as_bad (_("Macro used $at after \".set noat\""));
8647 /* Move the contents of register SOURCE into register DEST. */
8650 move_register (int dest
, int source
)
8652 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8653 instruction specifically requires a 32-bit one. */
8654 if (mips_opts
.micromips
8655 && !mips_opts
.insn32
8656 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8657 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8659 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8663 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8664 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8665 The two alternatives are:
8667 Global symbol Local sybmol
8668 ------------- ------------
8669 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8671 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8673 load_got_offset emits the first instruction and add_got_offset
8674 emits the second for a 16-bit offset or add_got_offset_hilo emits
8675 a sequence to add a 32-bit offset using a scratch register. */
8678 load_got_offset (int dest
, expressionS
*local
)
8683 global
.X_add_number
= 0;
8685 relax_start (local
->X_add_symbol
);
8686 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8687 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8689 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8690 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8695 add_got_offset (int dest
, expressionS
*local
)
8699 global
.X_op
= O_constant
;
8700 global
.X_op_symbol
= NULL
;
8701 global
.X_add_symbol
= NULL
;
8702 global
.X_add_number
= local
->X_add_number
;
8704 relax_start (local
->X_add_symbol
);
8705 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8706 dest
, dest
, BFD_RELOC_LO16
);
8708 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8713 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8716 int hold_mips_optimize
;
8718 global
.X_op
= O_constant
;
8719 global
.X_op_symbol
= NULL
;
8720 global
.X_add_symbol
= NULL
;
8721 global
.X_add_number
= local
->X_add_number
;
8723 relax_start (local
->X_add_symbol
);
8724 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8726 /* Set mips_optimize around the lui instruction to avoid
8727 inserting an unnecessary nop after the lw. */
8728 hold_mips_optimize
= mips_optimize
;
8730 macro_build_lui (&global
, tmp
);
8731 mips_optimize
= hold_mips_optimize
;
8732 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8735 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8738 /* Emit a sequence of instructions to emulate a branch likely operation.
8739 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8740 is its complementing branch with the original condition negated.
8741 CALL is set if the original branch specified the link operation.
8742 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8744 Code like this is produced in the noreorder mode:
8749 delay slot (executed only if branch taken)
8757 delay slot (executed only if branch taken)
8760 In the reorder mode the delay slot would be filled with a nop anyway,
8761 so code produced is simply:
8766 This function is used when producing code for the microMIPS ASE that
8767 does not implement branch likely instructions in hardware. */
8770 macro_build_branch_likely (const char *br
, const char *brneg
,
8771 int call
, expressionS
*ep
, const char *fmt
,
8772 unsigned int sreg
, unsigned int treg
)
8774 int noreorder
= mips_opts
.noreorder
;
8777 gas_assert (mips_opts
.micromips
);
8781 micromips_label_expr (&expr1
);
8782 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8783 macro_build (NULL
, "nop", "");
8784 macro_build (ep
, call
? "bal" : "b", "p");
8786 /* Set to true so that append_insn adds a label. */
8787 emit_branch_likely_macro
= TRUE
;
8791 macro_build (ep
, br
, fmt
, sreg
, treg
);
8792 macro_build (NULL
, "nop", "");
8797 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8798 the condition code tested. EP specifies the branch target. */
8801 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8828 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8831 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8832 the register tested. EP specifies the branch target. */
8835 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8837 const char *brneg
= NULL
;
8847 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8851 gas_assert (mips_opts
.micromips
);
8852 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8860 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8867 br
= mips_opts
.micromips
? "blez" : "blezl";
8874 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8878 gas_assert (mips_opts
.micromips
);
8879 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8886 if (mips_opts
.micromips
&& brneg
)
8887 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8889 macro_build (ep
, br
, "s,p", sreg
);
8892 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8893 TREG as the registers tested. EP specifies the branch target. */
8896 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8897 unsigned int sreg
, unsigned int treg
)
8899 const char *brneg
= NULL
;
8911 br
= mips_opts
.micromips
? "beq" : "beql";
8920 br
= mips_opts
.micromips
? "bne" : "bnel";
8926 if (mips_opts
.micromips
&& brneg
)
8927 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8929 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8932 /* Return the high part that should be loaded in order to make the low
8933 part of VALUE accessible using an offset of OFFBITS bits. */
8936 offset_high_part (offsetT value
, unsigned int offbits
)
8943 bias
= 1 << (offbits
- 1);
8944 low_mask
= bias
* 2 - 1;
8945 return (value
+ bias
) & ~low_mask
;
8948 /* Return true if the value stored in offset_expr and offset_reloc
8949 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8950 amount that the caller wants to add without inducing overflow
8951 and ALIGN is the known alignment of the value in bytes. */
8954 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8958 /* Accept any relocation operator if overflow isn't a concern. */
8959 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8962 /* These relocations are guaranteed not to overflow in correct links. */
8963 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8964 || gprel16_reloc_p (*offset_reloc
))
8967 if (offset_expr
.X_op
== O_constant
8968 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8969 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8976 * This routine implements the seemingly endless macro or synthesized
8977 * instructions and addressing modes in the mips assembly language. Many
8978 * of these macros are simple and are similar to each other. These could
8979 * probably be handled by some kind of table or grammar approach instead of
8980 * this verbose method. Others are not simple macros but are more like
8981 * optimizing code generation.
8982 * One interesting optimization is when several store macros appear
8983 * consecutively that would load AT with the upper half of the same address.
8984 * The ensuing load upper instructions are ommited. This implies some kind
8985 * of global optimization. We currently only optimize within a single macro.
8986 * For many of the load and store macros if the address is specified as a
8987 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8988 * first load register 'at' with zero and use it as the base register. The
8989 * mips assembler simply uses register $zero. Just one tiny optimization
8993 macro (struct mips_cl_insn
*ip
, char *str
)
8995 const struct mips_operand_array
*operands
;
8996 unsigned int breg
, i
;
8997 unsigned int tempreg
;
9000 expressionS label_expr
;
9015 bfd_boolean large_offset
;
9017 int hold_mips_optimize
;
9019 unsigned int op
[MAX_OPERANDS
];
9021 gas_assert (! mips_opts
.mips16
);
9023 operands
= insn_operands (ip
);
9024 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9025 if (operands
->operand
[i
])
9026 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9030 mask
= ip
->insn_mo
->mask
;
9032 label_expr
.X_op
= O_constant
;
9033 label_expr
.X_op_symbol
= NULL
;
9034 label_expr
.X_add_symbol
= NULL
;
9035 label_expr
.X_add_number
= 0;
9037 expr1
.X_op
= O_constant
;
9038 expr1
.X_op_symbol
= NULL
;
9039 expr1
.X_add_symbol
= NULL
;
9040 expr1
.X_add_number
= 1;
9056 if (mips_opts
.micromips
)
9057 micromips_label_expr (&label_expr
);
9059 label_expr
.X_add_number
= 8;
9060 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9062 macro_build (NULL
, "nop", "");
9064 move_register (op
[0], op
[1]);
9065 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9066 if (mips_opts
.micromips
)
9067 micromips_add_label ();
9084 if (!mips_opts
.micromips
)
9086 if (imm_expr
.X_op
== O_constant
9087 && imm_expr
.X_add_number
>= -0x200
9088 && imm_expr
.X_add_number
< 0x200)
9090 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], imm_expr
.X_add_number
);
9099 if (imm_expr
.X_op
== O_constant
9100 && imm_expr
.X_add_number
>= -0x8000
9101 && imm_expr
.X_add_number
< 0x8000)
9103 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9108 load_register (AT
, &imm_expr
, dbl
);
9109 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9128 if (imm_expr
.X_op
== O_constant
9129 && imm_expr
.X_add_number
>= 0
9130 && imm_expr
.X_add_number
< 0x10000)
9132 if (mask
!= M_NOR_I
)
9133 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9136 macro_build (&imm_expr
, "ori", "t,r,i",
9137 op
[0], op
[1], BFD_RELOC_LO16
);
9138 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9144 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9145 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9149 switch (imm_expr
.X_add_number
)
9152 macro_build (NULL
, "nop", "");
9155 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9159 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9160 (int) imm_expr
.X_add_number
);
9163 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9164 (unsigned long) imm_expr
.X_add_number
);
9173 gas_assert (mips_opts
.micromips
);
9174 macro_build_branch_ccl (mask
, &offset_expr
,
9175 EXTRACT_OPERAND (1, BCC
, *ip
));
9182 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9188 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9193 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9200 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9201 else if (op
[0] == 0)
9202 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9206 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9207 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9208 &offset_expr
, AT
, ZERO
);
9218 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9224 /* Check for > max integer. */
9225 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9228 /* Result is always false. */
9230 macro_build (NULL
, "nop", "");
9232 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9235 if (imm_expr
.X_op
!= O_constant
)
9236 as_bad (_("Unsupported large constant"));
9237 ++imm_expr
.X_add_number
;
9241 if (mask
== M_BGEL_I
)
9243 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9245 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9246 &offset_expr
, op
[0]);
9249 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9251 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9252 &offset_expr
, op
[0]);
9255 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
9258 /* result is always true */
9259 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
9260 macro_build (&offset_expr
, "b", "p");
9265 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9266 &offset_expr
, AT
, ZERO
);
9274 else if (op
[0] == 0)
9275 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9276 &offset_expr
, ZERO
, op
[1]);
9280 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9281 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9282 &offset_expr
, AT
, ZERO
);
9291 && imm_expr
.X_op
== O_constant
9292 && imm_expr
.X_add_number
== -1))
9294 if (imm_expr
.X_op
!= O_constant
)
9295 as_bad (_("Unsupported large constant"));
9296 ++imm_expr
.X_add_number
;
9300 if (mask
== M_BGEUL_I
)
9302 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9304 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9305 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9306 &offset_expr
, op
[0], ZERO
);
9311 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9312 &offset_expr
, AT
, ZERO
);
9320 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9321 else if (op
[0] == 0)
9322 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9326 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9327 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9328 &offset_expr
, AT
, ZERO
);
9336 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9337 &offset_expr
, op
[0], ZERO
);
9338 else if (op
[0] == 0)
9343 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9344 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9345 &offset_expr
, AT
, ZERO
);
9353 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9354 else if (op
[0] == 0)
9355 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9359 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9360 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9361 &offset_expr
, AT
, ZERO
);
9368 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9370 if (imm_expr
.X_op
!= O_constant
)
9371 as_bad (_("Unsupported large constant"));
9372 ++imm_expr
.X_add_number
;
9376 if (mask
== M_BLTL_I
)
9378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9379 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9380 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9381 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9386 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9387 &offset_expr
, AT
, ZERO
);
9395 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9396 &offset_expr
, op
[0], ZERO
);
9397 else if (op
[0] == 0)
9402 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9403 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9404 &offset_expr
, AT
, ZERO
);
9413 && imm_expr
.X_op
== O_constant
9414 && imm_expr
.X_add_number
== -1))
9416 if (imm_expr
.X_op
!= O_constant
)
9417 as_bad (_("Unsupported large constant"));
9418 ++imm_expr
.X_add_number
;
9422 if (mask
== M_BLTUL_I
)
9424 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9426 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9427 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9428 &offset_expr
, op
[0], ZERO
);
9433 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9434 &offset_expr
, AT
, ZERO
);
9442 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9443 else if (op
[0] == 0)
9444 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9448 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9449 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9450 &offset_expr
, AT
, ZERO
);
9459 else if (op
[0] == 0)
9460 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9461 &offset_expr
, ZERO
, op
[1]);
9465 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9466 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9467 &offset_expr
, AT
, ZERO
);
9483 as_warn (_("Divide by zero."));
9485 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9487 macro_build (NULL
, "break", BRK_FMT
, 7);
9494 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9495 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9499 if (mips_opts
.micromips
)
9500 micromips_label_expr (&label_expr
);
9502 label_expr
.X_add_number
= 8;
9503 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9504 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9505 macro_build (NULL
, "break", BRK_FMT
, 7);
9506 if (mips_opts
.micromips
)
9507 micromips_add_label ();
9509 expr1
.X_add_number
= -1;
9511 load_register (AT
, &expr1
, dbl
);
9512 if (mips_opts
.micromips
)
9513 micromips_label_expr (&label_expr
);
9515 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9516 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9519 expr1
.X_add_number
= 1;
9520 load_register (AT
, &expr1
, dbl
);
9521 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9525 expr1
.X_add_number
= 0x80000000;
9526 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9530 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9531 /* We want to close the noreorder block as soon as possible, so
9532 that later insns are available for delay slot filling. */
9537 if (mips_opts
.micromips
)
9538 micromips_label_expr (&label_expr
);
9540 label_expr
.X_add_number
= 8;
9541 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9542 macro_build (NULL
, "nop", "");
9544 /* We want to close the noreorder block as soon as possible, so
9545 that later insns are available for delay slot filling. */
9548 macro_build (NULL
, "break", BRK_FMT
, 6);
9550 if (mips_opts
.micromips
)
9551 micromips_add_label ();
9552 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9591 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9593 as_warn (_("Divide by zero."));
9595 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9597 macro_build (NULL
, "break", BRK_FMT
, 7);
9600 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9602 if (strcmp (s2
, "mflo") == 0)
9603 move_register (op
[0], op
[1]);
9605 move_register (op
[0], ZERO
);
9608 if (imm_expr
.X_op
== O_constant
9609 && imm_expr
.X_add_number
== -1
9610 && s
[strlen (s
) - 1] != 'u')
9612 if (strcmp (s2
, "mflo") == 0)
9613 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9615 move_register (op
[0], ZERO
);
9620 load_register (AT
, &imm_expr
, dbl
);
9621 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9622 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9644 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9645 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9646 /* We want to close the noreorder block as soon as possible, so
9647 that later insns are available for delay slot filling. */
9652 if (mips_opts
.micromips
)
9653 micromips_label_expr (&label_expr
);
9655 label_expr
.X_add_number
= 8;
9656 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9657 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9659 /* We want to close the noreorder block as soon as possible, so
9660 that later insns are available for delay slot filling. */
9662 macro_build (NULL
, "break", BRK_FMT
, 7);
9663 if (mips_opts
.micromips
)
9664 micromips_add_label ();
9666 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9678 /* Load the address of a symbol into a register. If breg is not
9679 zero, we then add a base register to it. */
9682 if (dbl
&& HAVE_32BIT_GPRS
)
9683 as_warn (_("dla used to load 32-bit register"));
9685 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9686 as_warn (_("la used to load 64-bit address"));
9688 if (small_offset_p (0, align
, 16))
9690 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9691 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9695 if (mips_opts
.at
&& (op
[0] == breg
))
9703 if (offset_expr
.X_op
!= O_symbol
9704 && offset_expr
.X_op
!= O_constant
)
9706 as_bad (_("Expression too complex"));
9707 offset_expr
.X_op
= O_constant
;
9710 if (offset_expr
.X_op
== O_constant
)
9711 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9712 else if (mips_pic
== NO_PIC
)
9714 /* If this is a reference to a GP relative symbol, we want
9715 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9717 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9718 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9719 If we have a constant, we need two instructions anyhow,
9720 so we may as well always use the latter form.
9722 With 64bit address space and a usable $at we want
9723 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9724 lui $at,<sym> (BFD_RELOC_HI16_S)
9725 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9726 daddiu $at,<sym> (BFD_RELOC_LO16)
9728 daddu $tempreg,$tempreg,$at
9730 If $at is already in use, we use a path which is suboptimal
9731 on superscalar processors.
9732 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9733 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9735 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9737 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9739 For GP relative symbols in 64bit address space we can use
9740 the same sequence as in 32bit address space. */
9741 if (HAVE_64BIT_SYMBOLS
)
9743 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9744 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9746 relax_start (offset_expr
.X_add_symbol
);
9747 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9748 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9752 if (used_at
== 0 && mips_opts
.at
)
9754 macro_build (&offset_expr
, "lui", LUI_FMT
,
9755 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9756 macro_build (&offset_expr
, "lui", LUI_FMT
,
9757 AT
, BFD_RELOC_HI16_S
);
9758 macro_build (&offset_expr
, "daddiu", "t,r,j",
9759 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9760 macro_build (&offset_expr
, "daddiu", "t,r,j",
9761 AT
, AT
, BFD_RELOC_LO16
);
9762 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9763 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9768 macro_build (&offset_expr
, "lui", LUI_FMT
,
9769 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9770 macro_build (&offset_expr
, "daddiu", "t,r,j",
9771 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9772 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9773 macro_build (&offset_expr
, "daddiu", "t,r,j",
9774 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9775 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9776 macro_build (&offset_expr
, "daddiu", "t,r,j",
9777 tempreg
, tempreg
, BFD_RELOC_LO16
);
9780 if (mips_relax
.sequence
)
9785 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9786 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9788 relax_start (offset_expr
.X_add_symbol
);
9789 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9790 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9793 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9794 as_bad (_("Offset too large"));
9795 macro_build_lui (&offset_expr
, tempreg
);
9796 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9797 tempreg
, tempreg
, BFD_RELOC_LO16
);
9798 if (mips_relax
.sequence
)
9802 else if (!mips_big_got
&& !HAVE_NEWABI
)
9804 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9806 /* If this is a reference to an external symbol, and there
9807 is no constant, we want
9808 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9809 or for lca or if tempreg is PIC_CALL_REG
9810 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9811 For a local symbol, we want
9812 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9814 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9816 If we have a small constant, and this is a reference to
9817 an external symbol, we want
9818 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9820 addiu $tempreg,$tempreg,<constant>
9821 For a local symbol, we want the same instruction
9822 sequence, but we output a BFD_RELOC_LO16 reloc on the
9825 If we have a large constant, and this is a reference to
9826 an external symbol, we want
9827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9828 lui $at,<hiconstant>
9829 addiu $at,$at,<loconstant>
9830 addu $tempreg,$tempreg,$at
9831 For a local symbol, we want the same instruction
9832 sequence, but we output a BFD_RELOC_LO16 reloc on the
9836 if (offset_expr
.X_add_number
== 0)
9838 if (mips_pic
== SVR4_PIC
9840 && (call
|| tempreg
== PIC_CALL_REG
))
9841 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9843 relax_start (offset_expr
.X_add_symbol
);
9844 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9845 lw_reloc_type
, mips_gp_register
);
9848 /* We're going to put in an addu instruction using
9849 tempreg, so we may as well insert the nop right
9854 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9855 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9857 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9858 tempreg
, tempreg
, BFD_RELOC_LO16
);
9860 /* FIXME: If breg == 0, and the next instruction uses
9861 $tempreg, then if this variant case is used an extra
9862 nop will be generated. */
9864 else if (offset_expr
.X_add_number
>= -0x8000
9865 && offset_expr
.X_add_number
< 0x8000)
9867 load_got_offset (tempreg
, &offset_expr
);
9869 add_got_offset (tempreg
, &offset_expr
);
9873 expr1
.X_add_number
= offset_expr
.X_add_number
;
9874 offset_expr
.X_add_number
=
9875 SEXT_16BIT (offset_expr
.X_add_number
);
9876 load_got_offset (tempreg
, &offset_expr
);
9877 offset_expr
.X_add_number
= expr1
.X_add_number
;
9878 /* If we are going to add in a base register, and the
9879 target register and the base register are the same,
9880 then we are using AT as a temporary register. Since
9881 we want to load the constant into AT, we add our
9882 current AT (from the global offset table) and the
9883 register into the register now, and pretend we were
9884 not using a base register. */
9888 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9893 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9897 else if (!mips_big_got
&& HAVE_NEWABI
)
9899 int add_breg_early
= 0;
9901 /* If this is a reference to an external, and there is no
9902 constant, or local symbol (*), with or without a
9904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9905 or for lca or if tempreg is PIC_CALL_REG
9906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9908 If we have a small constant, and this is a reference to
9909 an external symbol, we want
9910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9911 addiu $tempreg,$tempreg,<constant>
9913 If we have a large constant, and this is a reference to
9914 an external symbol, we want
9915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9916 lui $at,<hiconstant>
9917 addiu $at,$at,<loconstant>
9918 addu $tempreg,$tempreg,$at
9920 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9921 local symbols, even though it introduces an additional
9924 if (offset_expr
.X_add_number
)
9926 expr1
.X_add_number
= offset_expr
.X_add_number
;
9927 offset_expr
.X_add_number
= 0;
9929 relax_start (offset_expr
.X_add_symbol
);
9930 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9931 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9933 if (expr1
.X_add_number
>= -0x8000
9934 && expr1
.X_add_number
< 0x8000)
9936 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9937 tempreg
, tempreg
, BFD_RELOC_LO16
);
9939 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9943 /* If we are going to add in a base register, and the
9944 target register and the base register are the same,
9945 then we are using AT as a temporary register. Since
9946 we want to load the constant into AT, we add our
9947 current AT (from the global offset table) and the
9948 register into the register now, and pretend we were
9949 not using a base register. */
9954 gas_assert (tempreg
== AT
);
9955 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9961 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9962 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9968 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9971 offset_expr
.X_add_number
= expr1
.X_add_number
;
9973 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9974 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9977 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9978 op
[0], tempreg
, breg
);
9984 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
9986 relax_start (offset_expr
.X_add_symbol
);
9987 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9988 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
9990 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9991 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9996 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9997 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10000 else if (mips_big_got
&& !HAVE_NEWABI
)
10003 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10004 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10005 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10007 /* This is the large GOT case. If this is a reference to an
10008 external symbol, and there is no constant, we want
10009 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10010 addu $tempreg,$tempreg,$gp
10011 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10012 or for lca or if tempreg is PIC_CALL_REG
10013 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10014 addu $tempreg,$tempreg,$gp
10015 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10016 For a local symbol, we want
10017 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10019 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10021 If we have a small constant, and this is a reference to
10022 an external symbol, we want
10023 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10024 addu $tempreg,$tempreg,$gp
10025 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10027 addiu $tempreg,$tempreg,<constant>
10028 For a local symbol, we want
10029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10031 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10033 If we have a large constant, and this is a reference to
10034 an external symbol, we want
10035 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10036 addu $tempreg,$tempreg,$gp
10037 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10038 lui $at,<hiconstant>
10039 addiu $at,$at,<loconstant>
10040 addu $tempreg,$tempreg,$at
10041 For a local symbol, we want
10042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10043 lui $at,<hiconstant>
10044 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10045 addu $tempreg,$tempreg,$at
10048 expr1
.X_add_number
= offset_expr
.X_add_number
;
10049 offset_expr
.X_add_number
= 0;
10050 relax_start (offset_expr
.X_add_symbol
);
10051 gpdelay
= reg_needs_delay (mips_gp_register
);
10052 if (expr1
.X_add_number
== 0 && breg
== 0
10053 && (call
|| tempreg
== PIC_CALL_REG
))
10055 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10056 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10058 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10059 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10060 tempreg
, tempreg
, mips_gp_register
);
10061 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10062 tempreg
, lw_reloc_type
, tempreg
);
10063 if (expr1
.X_add_number
== 0)
10067 /* We're going to put in an addu instruction using
10068 tempreg, so we may as well insert the nop right
10073 else if (expr1
.X_add_number
>= -0x8000
10074 && expr1
.X_add_number
< 0x8000)
10077 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10078 tempreg
, tempreg
, BFD_RELOC_LO16
);
10084 /* If we are going to add in a base register, and the
10085 target register and the base register are the same,
10086 then we are using AT as a temporary register. Since
10087 we want to load the constant into AT, we add our
10088 current AT (from the global offset table) and the
10089 register into the register now, and pretend we were
10090 not using a base register. */
10095 gas_assert (tempreg
== AT
);
10097 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10102 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10107 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10112 /* This is needed because this instruction uses $gp, but
10113 the first instruction on the main stream does not. */
10114 macro_build (NULL
, "nop", "");
10117 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10118 local_reloc_type
, mips_gp_register
);
10119 if (expr1
.X_add_number
>= -0x8000
10120 && expr1
.X_add_number
< 0x8000)
10123 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10124 tempreg
, tempreg
, BFD_RELOC_LO16
);
10125 /* FIXME: If add_number is 0, and there was no base
10126 register, the external symbol case ended with a load,
10127 so if the symbol turns out to not be external, and
10128 the next instruction uses tempreg, an unnecessary nop
10129 will be inserted. */
10135 /* We must add in the base register now, as in the
10136 external symbol case. */
10137 gas_assert (tempreg
== AT
);
10139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10142 /* We set breg to 0 because we have arranged to add
10143 it in in both cases. */
10147 macro_build_lui (&expr1
, AT
);
10148 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10149 AT
, AT
, BFD_RELOC_LO16
);
10150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10151 tempreg
, tempreg
, AT
);
10156 else if (mips_big_got
&& HAVE_NEWABI
)
10158 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10159 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10160 int add_breg_early
= 0;
10162 /* This is the large GOT case. If this is a reference to an
10163 external symbol, and there is no constant, we want
10164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10165 add $tempreg,$tempreg,$gp
10166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10167 or for lca or if tempreg is PIC_CALL_REG
10168 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10169 add $tempreg,$tempreg,$gp
10170 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10172 If we have a small constant, and this is a reference to
10173 an external symbol, we want
10174 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10175 add $tempreg,$tempreg,$gp
10176 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10177 addi $tempreg,$tempreg,<constant>
10179 If we have a large constant, and this is a reference to
10180 an external symbol, we want
10181 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10182 addu $tempreg,$tempreg,$gp
10183 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10184 lui $at,<hiconstant>
10185 addi $at,$at,<loconstant>
10186 add $tempreg,$tempreg,$at
10188 If we have NewABI, and we know it's a local symbol, we want
10189 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10190 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10191 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10193 relax_start (offset_expr
.X_add_symbol
);
10195 expr1
.X_add_number
= offset_expr
.X_add_number
;
10196 offset_expr
.X_add_number
= 0;
10198 if (expr1
.X_add_number
== 0 && breg
== 0
10199 && (call
|| tempreg
== PIC_CALL_REG
))
10201 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10202 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10204 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10206 tempreg
, tempreg
, mips_gp_register
);
10207 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10208 tempreg
, lw_reloc_type
, tempreg
);
10210 if (expr1
.X_add_number
== 0)
10212 else if (expr1
.X_add_number
>= -0x8000
10213 && expr1
.X_add_number
< 0x8000)
10215 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10216 tempreg
, tempreg
, BFD_RELOC_LO16
);
10218 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10222 /* If we are going to add in a base register, and the
10223 target register and the base register are the same,
10224 then we are using AT as a temporary register. Since
10225 we want to load the constant into AT, we add our
10226 current AT (from the global offset table) and the
10227 register into the register now, and pretend we were
10228 not using a base register. */
10233 gas_assert (tempreg
== AT
);
10234 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10237 add_breg_early
= 1;
10240 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10241 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10246 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10249 offset_expr
.X_add_number
= expr1
.X_add_number
;
10250 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10251 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10252 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10253 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10254 if (add_breg_early
)
10256 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10257 op
[0], tempreg
, breg
);
10267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10271 gas_assert (!mips_opts
.micromips
);
10272 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10276 gas_assert (!mips_opts
.micromips
);
10277 macro_build (NULL
, "c2", "C", 0x02);
10281 gas_assert (!mips_opts
.micromips
);
10282 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10286 gas_assert (!mips_opts
.micromips
);
10287 macro_build (NULL
, "c2", "C", 3);
10291 gas_assert (!mips_opts
.micromips
);
10292 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10296 /* The j instruction may not be used in PIC code, since it
10297 requires an absolute address. We convert it to a b
10299 if (mips_pic
== NO_PIC
)
10300 macro_build (&offset_expr
, "j", "a");
10302 macro_build (&offset_expr
, "b", "p");
10305 /* The jal instructions must be handled as macros because when
10306 generating PIC code they expand to multi-instruction
10307 sequences. Normally they are simple instructions. */
10311 /* Fall through. */
10313 gas_assert (mips_opts
.micromips
);
10314 if (mips_opts
.insn32
)
10316 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10324 /* Fall through. */
10327 if (mips_pic
== NO_PIC
)
10329 s
= jals
? "jalrs" : "jalr";
10330 if (mips_opts
.micromips
10331 && !mips_opts
.insn32
10333 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10334 macro_build (NULL
, s
, "mj", op
[1]);
10336 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10340 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10341 && mips_cprestore_offset
>= 0);
10343 if (op
[1] != PIC_CALL_REG
)
10344 as_warn (_("MIPS PIC call to register other than $25"));
10346 s
= ((mips_opts
.micromips
10347 && !mips_opts
.insn32
10348 && (!mips_opts
.noreorder
|| cprestore
))
10349 ? "jalrs" : "jalr");
10350 if (mips_opts
.micromips
10351 && !mips_opts
.insn32
10353 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10354 macro_build (NULL
, s
, "mj", op
[1]);
10356 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10357 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10359 if (mips_cprestore_offset
< 0)
10360 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10363 if (!mips_frame_reg_valid
)
10365 as_warn (_("No .frame pseudo-op used in PIC code"));
10366 /* Quiet this warning. */
10367 mips_frame_reg_valid
= 1;
10369 if (!mips_cprestore_valid
)
10371 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10372 /* Quiet this warning. */
10373 mips_cprestore_valid
= 1;
10375 if (mips_opts
.noreorder
)
10376 macro_build (NULL
, "nop", "");
10377 expr1
.X_add_number
= mips_cprestore_offset
;
10378 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10381 HAVE_64BIT_ADDRESSES
);
10389 gas_assert (mips_opts
.micromips
);
10390 if (mips_opts
.insn32
)
10392 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10396 /* Fall through. */
10398 if (mips_pic
== NO_PIC
)
10399 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10400 else if (mips_pic
== SVR4_PIC
)
10402 /* If this is a reference to an external symbol, and we are
10403 using a small GOT, we want
10404 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10408 lw $gp,cprestore($sp)
10409 The cprestore value is set using the .cprestore
10410 pseudo-op. If we are using a big GOT, we want
10411 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10413 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10417 lw $gp,cprestore($sp)
10418 If the symbol is not external, we want
10419 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10421 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10424 lw $gp,cprestore($sp)
10426 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10427 sequences above, minus nops, unless the symbol is local,
10428 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10434 relax_start (offset_expr
.X_add_symbol
);
10435 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10436 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10439 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10440 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10446 relax_start (offset_expr
.X_add_symbol
);
10447 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10448 BFD_RELOC_MIPS_CALL_HI16
);
10449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10450 PIC_CALL_REG
, mips_gp_register
);
10451 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10452 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10455 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10456 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10458 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10459 PIC_CALL_REG
, PIC_CALL_REG
,
10460 BFD_RELOC_MIPS_GOT_OFST
);
10464 macro_build_jalr (&offset_expr
, 0);
10468 relax_start (offset_expr
.X_add_symbol
);
10471 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10472 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10481 gpdelay
= reg_needs_delay (mips_gp_register
);
10482 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10483 BFD_RELOC_MIPS_CALL_HI16
);
10484 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10485 PIC_CALL_REG
, mips_gp_register
);
10486 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10487 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10492 macro_build (NULL
, "nop", "");
10494 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10495 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10498 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10499 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10501 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10503 if (mips_cprestore_offset
< 0)
10504 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10507 if (!mips_frame_reg_valid
)
10509 as_warn (_("No .frame pseudo-op used in PIC code"));
10510 /* Quiet this warning. */
10511 mips_frame_reg_valid
= 1;
10513 if (!mips_cprestore_valid
)
10515 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10516 /* Quiet this warning. */
10517 mips_cprestore_valid
= 1;
10519 if (mips_opts
.noreorder
)
10520 macro_build (NULL
, "nop", "");
10521 expr1
.X_add_number
= mips_cprestore_offset
;
10522 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10525 HAVE_64BIT_ADDRESSES
);
10529 else if (mips_pic
== VXWORKS_PIC
)
10530 as_bad (_("Non-PIC jump used in PIC library"));
10637 gas_assert (!mips_opts
.micromips
);
10640 /* Itbl support may require additional care here. */
10646 /* Itbl support may require additional care here. */
10652 offbits
= (mips_opts
.micromips
? 12 : 16);
10653 /* Itbl support may require additional care here. */
10657 gas_assert (!mips_opts
.micromips
);
10660 /* Itbl support may require additional care here. */
10666 offbits
= (mips_opts
.micromips
? 12 : 16);
10671 offbits
= (mips_opts
.micromips
? 12 : 16);
10676 /* Itbl support may require additional care here. */
10682 offbits
= (mips_opts
.micromips
? 12 : 16);
10683 /* Itbl support may require additional care here. */
10689 /* Itbl support may require additional care here. */
10695 /* Itbl support may require additional care here. */
10701 offbits
= (mips_opts
.micromips
? 12 : 16);
10706 offbits
= (mips_opts
.micromips
? 12 : 16);
10711 offbits
= (mips_opts
.micromips
? 12 : 16);
10716 offbits
= (mips_opts
.micromips
? 12 : 16);
10721 offbits
= (mips_opts
.micromips
? 12 : 16);
10724 gas_assert (mips_opts
.micromips
);
10731 gas_assert (mips_opts
.micromips
);
10738 gas_assert (mips_opts
.micromips
);
10744 gas_assert (mips_opts
.micromips
);
10751 /* We don't want to use $0 as tempreg. */
10752 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10755 tempreg
= op
[0] + lp
;
10771 gas_assert (!mips_opts
.micromips
);
10774 /* Itbl support may require additional care here. */
10780 /* Itbl support may require additional care here. */
10786 offbits
= (mips_opts
.micromips
? 12 : 16);
10787 /* Itbl support may require additional care here. */
10791 gas_assert (!mips_opts
.micromips
);
10794 /* Itbl support may require additional care here. */
10800 offbits
= (mips_opts
.micromips
? 12 : 16);
10805 offbits
= (mips_opts
.micromips
? 12 : 16);
10810 offbits
= (mips_opts
.micromips
? 12 : 16);
10815 offbits
= (mips_opts
.micromips
? 12 : 16);
10819 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10820 offbits
= (mips_opts
.micromips
? 12 : 16);
10829 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10830 offbits
= (mips_opts
.micromips
? 12 : 16);
10841 /* Itbl support may require additional care here. */
10846 offbits
= (mips_opts
.micromips
? 12 : 16);
10847 /* Itbl support may require additional care here. */
10853 /* Itbl support may require additional care here. */
10857 gas_assert (!mips_opts
.micromips
);
10860 /* Itbl support may require additional care here. */
10866 offbits
= (mips_opts
.micromips
? 12 : 16);
10871 offbits
= (mips_opts
.micromips
? 12 : 16);
10874 gas_assert (mips_opts
.micromips
);
10880 gas_assert (mips_opts
.micromips
);
10886 gas_assert (mips_opts
.micromips
);
10892 gas_assert (mips_opts
.micromips
);
10901 if (small_offset_p (0, align
, 16))
10903 /* The first case exists for M_LD_AB and M_SD_AB, which are
10904 macros for o32 but which should act like normal instructions
10907 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
10908 offset_reloc
[1], offset_reloc
[2], breg
);
10909 else if (small_offset_p (0, align
, offbits
))
10912 macro_build (NULL
, s
, fmt
, op
[0], breg
);
10914 macro_build (NULL
, s
, fmt
, op
[0],
10915 (int) offset_expr
.X_add_number
, breg
);
10921 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10922 tempreg
, breg
, -1, offset_reloc
[0],
10923 offset_reloc
[1], offset_reloc
[2]);
10925 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10927 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10935 if (offset_expr
.X_op
!= O_constant
10936 && offset_expr
.X_op
!= O_symbol
)
10938 as_bad (_("Expression too complex"));
10939 offset_expr
.X_op
= O_constant
;
10942 if (HAVE_32BIT_ADDRESSES
10943 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10947 sprintf_vma (value
, offset_expr
.X_add_number
);
10948 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10951 /* A constant expression in PIC code can be handled just as it
10952 is in non PIC code. */
10953 if (offset_expr
.X_op
== O_constant
)
10955 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
10956 offbits
== 0 ? 16 : offbits
);
10957 offset_expr
.X_add_number
-= expr1
.X_add_number
;
10959 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
10961 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10962 tempreg
, tempreg
, breg
);
10965 if (offset_expr
.X_add_number
!= 0)
10966 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
10967 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
10968 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10970 else if (offbits
== 16)
10971 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10973 macro_build (NULL
, s
, fmt
, op
[0],
10974 (int) offset_expr
.X_add_number
, tempreg
);
10976 else if (offbits
!= 16)
10978 /* The offset field is too narrow to be used for a low-part
10979 relocation, so load the whole address into the auxillary
10981 load_address (tempreg
, &offset_expr
, &used_at
);
10983 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10984 tempreg
, tempreg
, breg
);
10986 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10988 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10990 else if (mips_pic
== NO_PIC
)
10992 /* If this is a reference to a GP relative symbol, and there
10993 is no base register, we want
10994 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10995 Otherwise, if there is no base register, we want
10996 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10997 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10998 If we have a constant, we need two instructions anyhow,
10999 so we always use the latter form.
11001 If we have a base register, and this is a reference to a
11002 GP relative symbol, we want
11003 addu $tempreg,$breg,$gp
11004 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11006 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11007 addu $tempreg,$tempreg,$breg
11008 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11009 With a constant we always use the latter case.
11011 With 64bit address space and no base register and $at usable,
11013 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11014 lui $at,<sym> (BFD_RELOC_HI16_S)
11015 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11018 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11019 If we have a base register, we want
11020 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11021 lui $at,<sym> (BFD_RELOC_HI16_S)
11022 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11026 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11028 Without $at we can't generate the optimal path for superscalar
11029 processors here since this would require two temporary registers.
11030 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11031 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11033 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11035 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11036 If we have a base register, we want
11037 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11038 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11040 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11042 daddu $tempreg,$tempreg,$breg
11043 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11045 For GP relative symbols in 64bit address space we can use
11046 the same sequence as in 32bit address space. */
11047 if (HAVE_64BIT_SYMBOLS
)
11049 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11050 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11052 relax_start (offset_expr
.X_add_symbol
);
11055 macro_build (&offset_expr
, s
, fmt
, op
[0],
11056 BFD_RELOC_GPREL16
, mips_gp_register
);
11060 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11061 tempreg
, breg
, mips_gp_register
);
11062 macro_build (&offset_expr
, s
, fmt
, op
[0],
11063 BFD_RELOC_GPREL16
, tempreg
);
11068 if (used_at
== 0 && mips_opts
.at
)
11070 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11071 BFD_RELOC_MIPS_HIGHEST
);
11072 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11074 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11075 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11077 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11078 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11079 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11080 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11086 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11087 BFD_RELOC_MIPS_HIGHEST
);
11088 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11089 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11090 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11091 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11092 tempreg
, BFD_RELOC_HI16_S
);
11093 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11095 macro_build (NULL
, "daddu", "d,v,t",
11096 tempreg
, tempreg
, breg
);
11097 macro_build (&offset_expr
, s
, fmt
, op
[0],
11098 BFD_RELOC_LO16
, tempreg
);
11101 if (mips_relax
.sequence
)
11108 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11109 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11111 relax_start (offset_expr
.X_add_symbol
);
11112 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11116 macro_build_lui (&offset_expr
, tempreg
);
11117 macro_build (&offset_expr
, s
, fmt
, op
[0],
11118 BFD_RELOC_LO16
, tempreg
);
11119 if (mips_relax
.sequence
)
11124 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11125 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11127 relax_start (offset_expr
.X_add_symbol
);
11128 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11129 tempreg
, breg
, mips_gp_register
);
11130 macro_build (&offset_expr
, s
, fmt
, op
[0],
11131 BFD_RELOC_GPREL16
, tempreg
);
11134 macro_build_lui (&offset_expr
, tempreg
);
11135 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11136 tempreg
, tempreg
, breg
);
11137 macro_build (&offset_expr
, s
, fmt
, op
[0],
11138 BFD_RELOC_LO16
, tempreg
);
11139 if (mips_relax
.sequence
)
11143 else if (!mips_big_got
)
11145 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11147 /* If this is a reference to an external symbol, we want
11148 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11150 <op> op[0],0($tempreg)
11152 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11154 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11155 <op> op[0],0($tempreg)
11157 For NewABI, we want
11158 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11159 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11161 If there is a base register, we add it to $tempreg before
11162 the <op>. If there is a constant, we stick it in the
11163 <op> instruction. We don't handle constants larger than
11164 16 bits, because we have no way to load the upper 16 bits
11165 (actually, we could handle them for the subset of cases
11166 in which we are not using $at). */
11167 gas_assert (offset_expr
.X_op
== O_symbol
);
11170 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11171 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11174 tempreg
, tempreg
, breg
);
11175 macro_build (&offset_expr
, s
, fmt
, op
[0],
11176 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11179 expr1
.X_add_number
= offset_expr
.X_add_number
;
11180 offset_expr
.X_add_number
= 0;
11181 if (expr1
.X_add_number
< -0x8000
11182 || expr1
.X_add_number
>= 0x8000)
11183 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11184 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11185 lw_reloc_type
, mips_gp_register
);
11187 relax_start (offset_expr
.X_add_symbol
);
11189 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11190 tempreg
, BFD_RELOC_LO16
);
11193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11194 tempreg
, tempreg
, breg
);
11195 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11197 else if (mips_big_got
&& !HAVE_NEWABI
)
11201 /* If this is a reference to an external symbol, we want
11202 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11203 addu $tempreg,$tempreg,$gp
11204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11205 <op> op[0],0($tempreg)
11207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11209 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11210 <op> op[0],0($tempreg)
11211 If there is a base register, we add it to $tempreg before
11212 the <op>. If there is a constant, we stick it in the
11213 <op> instruction. We don't handle constants larger than
11214 16 bits, because we have no way to load the upper 16 bits
11215 (actually, we could handle them for the subset of cases
11216 in which we are not using $at). */
11217 gas_assert (offset_expr
.X_op
== O_symbol
);
11218 expr1
.X_add_number
= offset_expr
.X_add_number
;
11219 offset_expr
.X_add_number
= 0;
11220 if (expr1
.X_add_number
< -0x8000
11221 || expr1
.X_add_number
>= 0x8000)
11222 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11223 gpdelay
= reg_needs_delay (mips_gp_register
);
11224 relax_start (offset_expr
.X_add_symbol
);
11225 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11226 BFD_RELOC_MIPS_GOT_HI16
);
11227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11230 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11233 macro_build (NULL
, "nop", "");
11234 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11235 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11237 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11238 tempreg
, BFD_RELOC_LO16
);
11242 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11243 tempreg
, tempreg
, breg
);
11244 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11246 else if (mips_big_got
&& HAVE_NEWABI
)
11248 /* If this is a reference to an external symbol, we want
11249 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11250 add $tempreg,$tempreg,$gp
11251 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11252 <op> op[0],<ofst>($tempreg)
11253 Otherwise, for local symbols, we want:
11254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11255 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11256 gas_assert (offset_expr
.X_op
== O_symbol
);
11257 expr1
.X_add_number
= offset_expr
.X_add_number
;
11258 offset_expr
.X_add_number
= 0;
11259 if (expr1
.X_add_number
< -0x8000
11260 || expr1
.X_add_number
>= 0x8000)
11261 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11262 relax_start (offset_expr
.X_add_symbol
);
11263 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11264 BFD_RELOC_MIPS_GOT_HI16
);
11265 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11267 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11268 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11270 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11271 tempreg
, tempreg
, breg
);
11272 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11275 offset_expr
.X_add_number
= expr1
.X_add_number
;
11276 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11277 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11280 tempreg
, tempreg
, breg
);
11281 macro_build (&offset_expr
, s
, fmt
, op
[0],
11282 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11291 gas_assert (mips_opts
.micromips
);
11292 gas_assert (mips_opts
.insn32
);
11293 start_noreorder ();
11294 macro_build (NULL
, "jr", "s", RA
);
11295 expr1
.X_add_number
= op
[0] << 2;
11296 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11301 gas_assert (mips_opts
.micromips
);
11302 gas_assert (mips_opts
.insn32
);
11303 macro_build (NULL
, "jr", "s", op
[0]);
11304 if (mips_opts
.noreorder
)
11305 macro_build (NULL
, "nop", "");
11310 load_register (op
[0], &imm_expr
, 0);
11314 load_register (op
[0], &imm_expr
, 1);
11318 if (imm_expr
.X_op
== O_constant
)
11321 load_register (AT
, &imm_expr
, 0);
11322 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11327 gas_assert (offset_expr
.X_op
== O_symbol
11328 && strcmp (segment_name (S_GET_SEGMENT
11329 (offset_expr
.X_add_symbol
)),
11331 && offset_expr
.X_add_number
== 0);
11332 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11333 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11338 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11339 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11340 order 32 bits of the value and the low order 32 bits are either
11341 zero or in OFFSET_EXPR. */
11342 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11344 if (HAVE_64BIT_GPRS
)
11345 load_register (op
[0], &imm_expr
, 1);
11350 if (target_big_endian
)
11362 load_register (hreg
, &imm_expr
, 0);
11365 if (offset_expr
.X_op
== O_absent
)
11366 move_register (lreg
, 0);
11369 gas_assert (offset_expr
.X_op
== O_constant
);
11370 load_register (lreg
, &offset_expr
, 0);
11377 /* We know that sym is in the .rdata section. First we get the
11378 upper 16 bits of the address. */
11379 if (mips_pic
== NO_PIC
)
11381 macro_build_lui (&offset_expr
, AT
);
11386 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11387 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11391 /* Now we load the register(s). */
11392 if (HAVE_64BIT_GPRS
)
11395 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11396 BFD_RELOC_LO16
, AT
);
11401 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11402 BFD_RELOC_LO16
, AT
);
11405 /* FIXME: How in the world do we deal with the possible
11407 offset_expr
.X_add_number
+= 4;
11408 macro_build (&offset_expr
, "lw", "t,o(b)",
11409 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11415 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11416 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11417 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11418 the value and the low order 32 bits are either zero or in
11420 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11423 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11424 if (HAVE_64BIT_FPRS
)
11426 gas_assert (HAVE_64BIT_GPRS
);
11427 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11431 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11432 if (offset_expr
.X_op
== O_absent
)
11433 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11436 gas_assert (offset_expr
.X_op
== O_constant
);
11437 load_register (AT
, &offset_expr
, 0);
11438 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11444 gas_assert (offset_expr
.X_op
== O_symbol
11445 && offset_expr
.X_add_number
== 0);
11446 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11447 if (strcmp (s
, ".lit8") == 0)
11449 op
[2] = mips_gp_register
;
11450 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11451 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11452 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11456 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11458 if (mips_pic
!= NO_PIC
)
11459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11460 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11463 /* FIXME: This won't work for a 64 bit address. */
11464 macro_build_lui (&offset_expr
, AT
);
11468 offset_reloc
[0] = BFD_RELOC_LO16
;
11469 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11470 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11477 * The MIPS assembler seems to check for X_add_number not
11478 * being double aligned and generating:
11479 * lui at,%hi(foo+1)
11481 * addiu at,at,%lo(foo+1)
11484 * But, the resulting address is the same after relocation so why
11485 * generate the extra instruction?
11487 /* Itbl support may require additional care here. */
11490 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11499 gas_assert (!mips_opts
.micromips
);
11500 /* Itbl support may require additional care here. */
11503 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11523 if (HAVE_64BIT_GPRS
)
11533 if (HAVE_64BIT_GPRS
)
11541 /* Even on a big endian machine $fn comes before $fn+1. We have
11542 to adjust when loading from memory. We set coproc if we must
11543 load $fn+1 first. */
11544 /* Itbl support may require additional care here. */
11545 if (!target_big_endian
)
11549 if (small_offset_p (0, align
, 16))
11552 if (!small_offset_p (4, align
, 16))
11554 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11555 -1, offset_reloc
[0], offset_reloc
[1],
11557 expr1
.X_add_number
= 0;
11561 offset_reloc
[0] = BFD_RELOC_LO16
;
11562 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11563 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11565 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11567 ep
->X_add_number
+= 4;
11568 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11569 offset_reloc
[1], offset_reloc
[2], breg
);
11570 ep
->X_add_number
-= 4;
11571 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11572 offset_reloc
[1], offset_reloc
[2], breg
);
11576 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11577 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11579 ep
->X_add_number
+= 4;
11580 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11581 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11587 if (offset_expr
.X_op
!= O_symbol
11588 && offset_expr
.X_op
!= O_constant
)
11590 as_bad (_("Expression too complex"));
11591 offset_expr
.X_op
= O_constant
;
11594 if (HAVE_32BIT_ADDRESSES
11595 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11599 sprintf_vma (value
, offset_expr
.X_add_number
);
11600 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11603 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11605 /* If this is a reference to a GP relative symbol, we want
11606 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11607 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11608 If we have a base register, we use this
11610 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11611 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11612 If this is not a GP relative symbol, we want
11613 lui $at,<sym> (BFD_RELOC_HI16_S)
11614 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11615 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11616 If there is a base register, we add it to $at after the
11617 lui instruction. If there is a constant, we always use
11619 if (offset_expr
.X_op
== O_symbol
11620 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11621 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11623 relax_start (offset_expr
.X_add_symbol
);
11626 tempreg
= mips_gp_register
;
11630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11631 AT
, breg
, mips_gp_register
);
11636 /* Itbl support may require additional care here. */
11637 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11638 BFD_RELOC_GPREL16
, tempreg
);
11639 offset_expr
.X_add_number
+= 4;
11641 /* Set mips_optimize to 2 to avoid inserting an
11643 hold_mips_optimize
= mips_optimize
;
11645 /* Itbl support may require additional care here. */
11646 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11647 BFD_RELOC_GPREL16
, tempreg
);
11648 mips_optimize
= hold_mips_optimize
;
11652 offset_expr
.X_add_number
-= 4;
11655 if (offset_high_part (offset_expr
.X_add_number
, 16)
11656 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11658 load_address (AT
, &offset_expr
, &used_at
);
11659 offset_expr
.X_op
= O_constant
;
11660 offset_expr
.X_add_number
= 0;
11663 macro_build_lui (&offset_expr
, AT
);
11665 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11666 /* Itbl support may require additional care here. */
11667 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11668 BFD_RELOC_LO16
, AT
);
11669 /* FIXME: How do we handle overflow here? */
11670 offset_expr
.X_add_number
+= 4;
11671 /* Itbl support may require additional care here. */
11672 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11673 BFD_RELOC_LO16
, AT
);
11674 if (mips_relax
.sequence
)
11677 else if (!mips_big_got
)
11679 /* If this is a reference to an external symbol, we want
11680 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11683 <op> op[0]+1,4($at)
11685 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11687 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11688 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11689 If there is a base register we add it to $at before the
11690 lwc1 instructions. If there is a constant we include it
11691 in the lwc1 instructions. */
11693 expr1
.X_add_number
= offset_expr
.X_add_number
;
11694 if (expr1
.X_add_number
< -0x8000
11695 || expr1
.X_add_number
>= 0x8000 - 4)
11696 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11697 load_got_offset (AT
, &offset_expr
);
11700 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11702 /* Set mips_optimize to 2 to avoid inserting an undesired
11704 hold_mips_optimize
= mips_optimize
;
11707 /* Itbl support may require additional care here. */
11708 relax_start (offset_expr
.X_add_symbol
);
11709 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11710 BFD_RELOC_LO16
, AT
);
11711 expr1
.X_add_number
+= 4;
11712 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11713 BFD_RELOC_LO16
, AT
);
11715 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11716 BFD_RELOC_LO16
, AT
);
11717 offset_expr
.X_add_number
+= 4;
11718 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11719 BFD_RELOC_LO16
, AT
);
11722 mips_optimize
= hold_mips_optimize
;
11724 else if (mips_big_got
)
11728 /* If this is a reference to an external symbol, we want
11729 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11731 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11734 <op> op[0]+1,4($at)
11736 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11738 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11739 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11740 If there is a base register we add it to $at before the
11741 lwc1 instructions. If there is a constant we include it
11742 in the lwc1 instructions. */
11744 expr1
.X_add_number
= offset_expr
.X_add_number
;
11745 offset_expr
.X_add_number
= 0;
11746 if (expr1
.X_add_number
< -0x8000
11747 || expr1
.X_add_number
>= 0x8000 - 4)
11748 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11749 gpdelay
= reg_needs_delay (mips_gp_register
);
11750 relax_start (offset_expr
.X_add_symbol
);
11751 macro_build (&offset_expr
, "lui", LUI_FMT
,
11752 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11753 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11754 AT
, AT
, mips_gp_register
);
11755 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11756 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11759 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11760 /* Itbl support may require additional care here. */
11761 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11762 BFD_RELOC_LO16
, AT
);
11763 expr1
.X_add_number
+= 4;
11765 /* Set mips_optimize to 2 to avoid inserting an undesired
11767 hold_mips_optimize
= mips_optimize
;
11769 /* Itbl support may require additional care here. */
11770 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11771 BFD_RELOC_LO16
, AT
);
11772 mips_optimize
= hold_mips_optimize
;
11773 expr1
.X_add_number
-= 4;
11776 offset_expr
.X_add_number
= expr1
.X_add_number
;
11778 macro_build (NULL
, "nop", "");
11779 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11780 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11783 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11784 /* Itbl support may require additional care here. */
11785 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11786 BFD_RELOC_LO16
, AT
);
11787 offset_expr
.X_add_number
+= 4;
11789 /* Set mips_optimize to 2 to avoid inserting an undesired
11791 hold_mips_optimize
= mips_optimize
;
11793 /* Itbl support may require additional care here. */
11794 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11795 BFD_RELOC_LO16
, AT
);
11796 mips_optimize
= hold_mips_optimize
;
11815 /* New code added to support COPZ instructions.
11816 This code builds table entries out of the macros in mip_opcodes.
11817 R4000 uses interlocks to handle coproc delays.
11818 Other chips (like the R3000) require nops to be inserted for delays.
11820 FIXME: Currently, we require that the user handle delays.
11821 In order to fill delay slots for non-interlocked chips,
11822 we must have a way to specify delays based on the coprocessor.
11823 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11824 What are the side-effects of the cop instruction?
11825 What cache support might we have and what are its effects?
11826 Both coprocessor & memory require delays. how long???
11827 What registers are read/set/modified?
11829 If an itbl is provided to interpret cop instructions,
11830 this knowledge can be encoded in the itbl spec. */
11844 gas_assert (!mips_opts
.micromips
);
11845 /* For now we just do C (same as Cz). The parameter will be
11846 stored in insn_opcode by mips_ip. */
11847 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11851 move_register (op
[0], op
[1]);
11855 gas_assert (mips_opts
.micromips
);
11856 gas_assert (mips_opts
.insn32
);
11857 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11858 micromips_to_32_reg_m_map
[op
[1]]);
11859 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11860 micromips_to_32_reg_n_map
[op
[2]]);
11866 if (mips_opts
.arch
== CPU_R5900
)
11867 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
11871 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
11872 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11879 /* The MIPS assembler some times generates shifts and adds. I'm
11880 not trying to be that fancy. GCC should do this for us
11883 load_register (AT
, &imm_expr
, dbl
);
11884 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
11885 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11898 start_noreorder ();
11901 load_register (AT
, &imm_expr
, dbl
);
11902 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
11903 op
[1], imm
? AT
: op
[2]);
11904 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11905 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
11906 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11908 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
11911 if (mips_opts
.micromips
)
11912 micromips_label_expr (&label_expr
);
11914 label_expr
.X_add_number
= 8;
11915 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
11916 macro_build (NULL
, "nop", "");
11917 macro_build (NULL
, "break", BRK_FMT
, 6);
11918 if (mips_opts
.micromips
)
11919 micromips_add_label ();
11922 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11935 start_noreorder ();
11938 load_register (AT
, &imm_expr
, dbl
);
11939 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
11940 op
[1], imm
? AT
: op
[2]);
11941 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11942 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11944 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
11947 if (mips_opts
.micromips
)
11948 micromips_label_expr (&label_expr
);
11950 label_expr
.X_add_number
= 8;
11951 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
11952 macro_build (NULL
, "nop", "");
11953 macro_build (NULL
, "break", BRK_FMT
, 6);
11954 if (mips_opts
.micromips
)
11955 micromips_add_label ();
11961 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11963 if (op
[0] == op
[1])
11970 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
11971 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
11975 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
11976 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
11977 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
11978 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11982 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11984 if (op
[0] == op
[1])
11991 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
11992 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
11996 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
11997 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
11998 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
11999 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12008 if (imm_expr
.X_op
!= O_constant
)
12009 as_bad (_("Improper rotate count"));
12010 rot
= imm_expr
.X_add_number
& 0x3f;
12011 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12013 rot
= (64 - rot
) & 0x3f;
12015 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12017 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12022 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12025 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12026 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12029 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12030 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12031 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12039 if (imm_expr
.X_op
!= O_constant
)
12040 as_bad (_("Improper rotate count"));
12041 rot
= imm_expr
.X_add_number
& 0x1f;
12042 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12044 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12045 (32 - rot
) & 0x1f);
12050 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12054 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12055 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12056 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12061 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12063 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12067 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12068 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12069 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12070 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12074 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12076 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12080 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12081 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12082 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12083 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12092 if (imm_expr
.X_op
!= O_constant
)
12093 as_bad (_("Improper rotate count"));
12094 rot
= imm_expr
.X_add_number
& 0x3f;
12095 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12098 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12100 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12105 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12108 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12109 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12112 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12113 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12114 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12122 if (imm_expr
.X_op
!= O_constant
)
12123 as_bad (_("Improper rotate count"));
12124 rot
= imm_expr
.X_add_number
& 0x1f;
12125 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12127 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12132 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12136 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12137 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12138 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12144 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12145 else if (op
[2] == 0)
12146 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12149 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12150 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12155 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12157 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12162 as_warn (_("Instruction %s: result is always false"),
12163 ip
->insn_mo
->name
);
12164 move_register (op
[0], 0);
12167 if (CPU_HAS_SEQ (mips_opts
.arch
)
12168 && -512 <= imm_expr
.X_add_number
12169 && imm_expr
.X_add_number
< 512)
12171 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12172 (int) imm_expr
.X_add_number
);
12175 if (imm_expr
.X_op
== O_constant
12176 && imm_expr
.X_add_number
>= 0
12177 && imm_expr
.X_add_number
< 0x10000)
12178 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12179 else if (imm_expr
.X_op
== O_constant
12180 && imm_expr
.X_add_number
> -0x8000
12181 && imm_expr
.X_add_number
< 0)
12183 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12184 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12185 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12187 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12190 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12191 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12196 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12197 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12200 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12203 case M_SGE
: /* X >= Y <==> not (X < Y) */
12209 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12210 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12213 case M_SGE_I
: /* X >= I <==> not (X < I) */
12215 if (imm_expr
.X_op
== O_constant
12216 && imm_expr
.X_add_number
>= -0x8000
12217 && imm_expr
.X_add_number
< 0x8000)
12218 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12219 op
[0], op
[1], BFD_RELOC_LO16
);
12222 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12223 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12227 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12230 case M_SGT
: /* X > Y <==> Y < X */
12236 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12239 case M_SGT_I
: /* X > I <==> I < X */
12246 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12247 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12250 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12256 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12257 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12260 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12267 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12268 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12269 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12273 if (imm_expr
.X_op
== O_constant
12274 && imm_expr
.X_add_number
>= -0x8000
12275 && imm_expr
.X_add_number
< 0x8000)
12277 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12282 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12283 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12287 if (imm_expr
.X_op
== O_constant
12288 && imm_expr
.X_add_number
>= -0x8000
12289 && imm_expr
.X_add_number
< 0x8000)
12291 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12296 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12297 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12302 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12303 else if (op
[2] == 0)
12304 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12307 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12308 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12313 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12315 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12320 as_warn (_("Instruction %s: result is always true"),
12321 ip
->insn_mo
->name
);
12322 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12323 op
[0], 0, BFD_RELOC_LO16
);
12326 if (CPU_HAS_SEQ (mips_opts
.arch
)
12327 && -512 <= imm_expr
.X_add_number
12328 && imm_expr
.X_add_number
< 512)
12330 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12331 (int) imm_expr
.X_add_number
);
12334 if (imm_expr
.X_op
== O_constant
12335 && imm_expr
.X_add_number
>= 0
12336 && imm_expr
.X_add_number
< 0x10000)
12338 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12341 else if (imm_expr
.X_op
== O_constant
12342 && imm_expr
.X_add_number
> -0x8000
12343 && imm_expr
.X_add_number
< 0)
12345 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12346 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12347 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12349 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12352 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12353 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12358 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12359 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12362 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12377 if (!mips_opts
.micromips
)
12379 if (imm_expr
.X_op
== O_constant
12380 && imm_expr
.X_add_number
> -0x200
12381 && imm_expr
.X_add_number
<= 0x200)
12383 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], -imm_expr
.X_add_number
);
12392 if (imm_expr
.X_op
== O_constant
12393 && imm_expr
.X_add_number
> -0x8000
12394 && imm_expr
.X_add_number
<= 0x8000)
12396 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12397 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12402 load_register (AT
, &imm_expr
, dbl
);
12403 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12425 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12426 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12431 gas_assert (!mips_opts
.micromips
);
12432 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12436 * Is the double cfc1 instruction a bug in the mips assembler;
12437 * or is there a reason for it?
12439 start_noreorder ();
12440 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12441 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12442 macro_build (NULL
, "nop", "");
12443 expr1
.X_add_number
= 3;
12444 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12445 expr1
.X_add_number
= 2;
12446 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12447 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12448 macro_build (NULL
, "nop", "");
12449 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12451 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12452 macro_build (NULL
, "nop", "");
12469 offbits
= (mips_opts
.micromips
? 12 : 16);
12475 offbits
= (mips_opts
.micromips
? 12 : 16);
12487 offbits
= (mips_opts
.micromips
? 12 : 16);
12494 offbits
= (mips_opts
.micromips
? 12 : 16);
12500 large_offset
= !small_offset_p (off
, align
, offbits
);
12502 expr1
.X_add_number
= 0;
12507 if (small_offset_p (0, align
, 16))
12508 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12509 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12512 load_address (tempreg
, ep
, &used_at
);
12514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12515 tempreg
, tempreg
, breg
);
12517 offset_reloc
[0] = BFD_RELOC_LO16
;
12518 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12519 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12524 else if (!ust
&& op
[0] == breg
)
12535 if (!target_big_endian
)
12536 ep
->X_add_number
+= off
;
12538 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12540 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12541 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12543 if (!target_big_endian
)
12544 ep
->X_add_number
-= off
;
12546 ep
->X_add_number
+= off
;
12548 macro_build (NULL
, s2
, "t,~(b)",
12549 tempreg
, (int) ep
->X_add_number
, breg
);
12551 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12552 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12554 /* If necessary, move the result in tempreg to the final destination. */
12555 if (!ust
&& op
[0] != tempreg
)
12557 /* Protect second load's delay slot. */
12559 move_register (op
[0], tempreg
);
12565 if (target_big_endian
== ust
)
12566 ep
->X_add_number
+= off
;
12567 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12568 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12569 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12571 /* For halfword transfers we need a temporary register to shuffle
12572 bytes. Unfortunately for M_USH_A we have none available before
12573 the next store as AT holds the base address. We deal with this
12574 case by clobbering TREG and then restoring it as with ULH. */
12575 tempreg
= ust
== large_offset
? op
[0] : AT
;
12577 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12579 if (target_big_endian
== ust
)
12580 ep
->X_add_number
-= off
;
12582 ep
->X_add_number
+= off
;
12583 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12584 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12586 /* For M_USH_A re-retrieve the LSB. */
12587 if (ust
&& large_offset
)
12589 if (target_big_endian
)
12590 ep
->X_add_number
+= off
;
12592 ep
->X_add_number
-= off
;
12593 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12594 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12596 /* For ULH and M_USH_A OR the LSB in. */
12597 if (!ust
|| large_offset
)
12599 tempreg
= !large_offset
? AT
: op
[0];
12600 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12601 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12606 /* FIXME: Check if this is one of the itbl macros, since they
12607 are added dynamically. */
12608 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
12611 if (!mips_opts
.at
&& used_at
)
12612 as_bad (_("Macro used $at after \".set noat\""));
12615 /* Implement macros in mips16 mode. */
12618 mips16_macro (struct mips_cl_insn
*ip
)
12620 const struct mips_operand_array
*operands
;
12625 const char *s
, *s2
, *s3
;
12626 unsigned int op
[MAX_OPERANDS
];
12629 mask
= ip
->insn_mo
->mask
;
12631 operands
= insn_operands (ip
);
12632 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12633 if (operands
->operand
[i
])
12634 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12638 expr1
.X_op
= O_constant
;
12639 expr1
.X_op_symbol
= NULL
;
12640 expr1
.X_add_symbol
= NULL
;
12641 expr1
.X_add_number
= 1;
12660 start_noreorder ();
12661 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12662 expr1
.X_add_number
= 2;
12663 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12664 macro_build (NULL
, "break", "6", 7);
12666 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12667 since that causes an overflow. We should do that as well,
12668 but I don't see how to do the comparisons without a temporary
12671 macro_build (NULL
, s
, "x", op
[0]);
12690 start_noreorder ();
12691 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12692 expr1
.X_add_number
= 2;
12693 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12694 macro_build (NULL
, "break", "6", 7);
12696 macro_build (NULL
, s2
, "x", op
[0]);
12702 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12703 macro_build (NULL
, "mflo", "x", op
[0]);
12711 if (imm_expr
.X_op
!= O_constant
)
12712 as_bad (_("Unsupported large constant"));
12713 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12714 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12718 if (imm_expr
.X_op
!= O_constant
)
12719 as_bad (_("Unsupported large constant"));
12720 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12721 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12725 if (imm_expr
.X_op
!= O_constant
)
12726 as_bad (_("Unsupported large constant"));
12727 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12728 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12750 goto do_reverse_branch
;
12754 goto do_reverse_branch
;
12766 goto do_reverse_branch
;
12777 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12778 macro_build (&offset_expr
, s2
, "p");
12805 goto do_addone_branch_i
;
12810 goto do_addone_branch_i
;
12825 goto do_addone_branch_i
;
12831 do_addone_branch_i
:
12832 if (imm_expr
.X_op
!= O_constant
)
12833 as_bad (_("Unsupported large constant"));
12834 ++imm_expr
.X_add_number
;
12837 macro_build (&imm_expr
, s
, s3
, op
[0]);
12838 macro_build (&offset_expr
, s2
, "p");
12842 expr1
.X_add_number
= 0;
12843 macro_build (&expr1
, "slti", "x,8", op
[1]);
12844 if (op
[0] != op
[1])
12845 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12846 expr1
.X_add_number
= 2;
12847 macro_build (&expr1
, "bteqz", "p");
12848 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12853 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12854 opcode bits in *OPCODE_EXTRA. */
12856 static struct mips_opcode
*
12857 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12858 ssize_t length
, unsigned int *opcode_extra
)
12860 char *name
, *dot
, *p
;
12861 unsigned int mask
, suffix
;
12863 struct mips_opcode
*insn
;
12865 /* Make a copy of the instruction so that we can fiddle with it. */
12866 name
= alloca (length
+ 1);
12867 memcpy (name
, start
, length
);
12868 name
[length
] = '\0';
12870 /* Look up the instruction as-is. */
12871 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12875 dot
= strchr (name
, '.');
12878 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12879 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12880 if (*p
== 0 && mask
!= 0)
12883 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12885 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
12887 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
12893 if (mips_opts
.micromips
)
12895 /* See if there's an instruction size override suffix,
12896 either `16' or `32', at the end of the mnemonic proper,
12897 that defines the operation, i.e. before the first `.'
12898 character if any. Strip it and retry. */
12899 opend
= dot
!= NULL
? dot
- name
: length
;
12900 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12902 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12908 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
12909 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12912 forced_insn_length
= suffix
;
12921 /* Assemble an instruction into its binary format. If the instruction
12922 is a macro, set imm_expr and offset_expr to the values associated
12923 with "I" and "A" operands respectively. Otherwise store the value
12924 of the relocatable field (if any) in offset_expr. In both cases
12925 set offset_reloc to the relocation operators applied to offset_expr. */
12928 mips_ip (char *str
, struct mips_cl_insn
*insn
)
12930 const struct mips_opcode
*first
, *past
;
12931 struct hash_control
*hash
;
12934 struct mips_operand_token
*tokens
;
12935 unsigned int opcode_extra
;
12937 if (mips_opts
.micromips
)
12939 hash
= micromips_op_hash
;
12940 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12945 past
= &mips_opcodes
[NUMOPCODES
];
12947 forced_insn_length
= 0;
12950 /* We first try to match an instruction up to a space or to the end. */
12951 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
12954 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
12957 set_insn_error (0, _("Unrecognized opcode"));
12961 if (strcmp (first
->name
, "li.s") == 0)
12963 else if (strcmp (first
->name
, "li.d") == 0)
12967 tokens
= mips_parse_arguments (str
+ end
, format
);
12971 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
12972 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
12973 set_insn_error (0, _("Illegal operands"));
12975 obstack_free (&mips_operand_tokens
, tokens
);
12978 /* As for mips_ip, but used when assembling MIPS16 code.
12979 Also set forced_insn_length to the resulting instruction size in
12980 bytes if the user explicitly requested a small or extended instruction. */
12983 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
12986 struct mips_opcode
*first
;
12987 struct mips_operand_token
*tokens
;
12989 forced_insn_length
= 0;
12991 for (s
= str
; ISLOWER (*s
); ++s
)
13005 if (s
[1] == 't' && s
[2] == ' ')
13007 forced_insn_length
= 2;
13011 else if (s
[1] == 'e' && s
[2] == ' ')
13013 forced_insn_length
= 4;
13017 /* Fall through. */
13019 set_insn_error (0, _("Unrecognized opcode"));
13023 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13024 forced_insn_length
= 2;
13027 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13032 set_insn_error (0, _("Unrecognized opcode"));
13036 tokens
= mips_parse_arguments (s
, 0);
13040 if (!match_mips16_insns (insn
, first
, tokens
))
13041 set_insn_error (0, _("Illegal operands"));
13043 obstack_free (&mips_operand_tokens
, tokens
);
13046 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13047 NBITS is the number of significant bits in VAL. */
13049 static unsigned long
13050 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13055 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13058 else if (nbits
== 15)
13060 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13065 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13068 return (extval
<< 16) | val
;
13071 /* Like decode_mips16_operand, but require the operand to be defined and
13072 require it to be an integer. */
13074 static const struct mips_int_operand
*
13075 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13077 const struct mips_operand
*operand
;
13079 operand
= decode_mips16_operand (type
, extended_p
);
13080 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13082 return (const struct mips_int_operand
*) operand
;
13085 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13088 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13089 bfd_reloc_code_real_type reloc
, offsetT sval
)
13091 int min_val
, max_val
;
13093 min_val
= mips_int_operand_min (operand
);
13094 max_val
= mips_int_operand_max (operand
);
13095 if (reloc
!= BFD_RELOC_UNUSED
)
13098 sval
= SEXT_16BIT (sval
);
13103 return (sval
>= min_val
13105 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13108 /* Install immediate value VAL into MIPS16 instruction *INSN,
13109 extending it if necessary. The instruction in *INSN may
13110 already be extended.
13112 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13113 if none. In the former case, VAL is a 16-bit number with no
13114 defined signedness.
13116 TYPE is the type of the immediate field. USER_INSN_LENGTH
13117 is the length that the user requested, or 0 if none. */
13120 mips16_immed (char *file
, unsigned int line
, int type
,
13121 bfd_reloc_code_real_type reloc
, offsetT val
,
13122 unsigned int user_insn_length
, unsigned long *insn
)
13124 const struct mips_int_operand
*operand
;
13125 unsigned int uval
, length
;
13127 operand
= mips16_immed_operand (type
, FALSE
);
13128 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13130 /* We need an extended instruction. */
13131 if (user_insn_length
== 2)
13132 as_bad_where (file
, line
, _("invalid unextended operand value"));
13134 *insn
|= MIPS16_EXTEND
;
13136 else if (user_insn_length
== 4)
13138 /* The operand doesn't force an unextended instruction to be extended.
13139 Warn if the user wanted an extended instruction anyway. */
13140 *insn
|= MIPS16_EXTEND
;
13141 as_warn_where (file
, line
,
13142 _("extended operand requested but not required"));
13145 length
= mips16_opcode_length (*insn
);
13148 operand
= mips16_immed_operand (type
, TRUE
);
13149 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13150 as_bad_where (file
, line
,
13151 _("operand value out of range for instruction"));
13153 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13155 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13157 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13160 struct percent_op_match
13163 bfd_reloc_code_real_type reloc
;
13166 static const struct percent_op_match mips_percent_op
[] =
13168 {"%lo", BFD_RELOC_LO16
},
13169 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13170 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13171 {"%call16", BFD_RELOC_MIPS_CALL16
},
13172 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13173 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13174 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13175 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13176 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13177 {"%got", BFD_RELOC_MIPS_GOT16
},
13178 {"%gp_rel", BFD_RELOC_GPREL16
},
13179 {"%half", BFD_RELOC_16
},
13180 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13181 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13182 {"%neg", BFD_RELOC_MIPS_SUB
},
13183 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13184 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13185 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13186 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13187 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13188 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13189 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13190 {"%hi", BFD_RELOC_HI16_S
}
13193 static const struct percent_op_match mips16_percent_op
[] =
13195 {"%lo", BFD_RELOC_MIPS16_LO16
},
13196 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13197 {"%got", BFD_RELOC_MIPS16_GOT16
},
13198 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13199 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13200 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13201 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13202 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13203 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13204 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13205 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13206 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13210 /* Return true if *STR points to a relocation operator. When returning true,
13211 move *STR over the operator and store its relocation code in *RELOC.
13212 Leave both *STR and *RELOC alone when returning false. */
13215 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13217 const struct percent_op_match
*percent_op
;
13220 if (mips_opts
.mips16
)
13222 percent_op
= mips16_percent_op
;
13223 limit
= ARRAY_SIZE (mips16_percent_op
);
13227 percent_op
= mips_percent_op
;
13228 limit
= ARRAY_SIZE (mips_percent_op
);
13231 for (i
= 0; i
< limit
; i
++)
13232 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13234 int len
= strlen (percent_op
[i
].str
);
13236 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13239 *str
+= strlen (percent_op
[i
].str
);
13240 *reloc
= percent_op
[i
].reloc
;
13242 /* Check whether the output BFD supports this relocation.
13243 If not, issue an error and fall back on something safe. */
13244 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13246 as_bad (_("relocation %s isn't supported by the current ABI"),
13247 percent_op
[i
].str
);
13248 *reloc
= BFD_RELOC_UNUSED
;
13256 /* Parse string STR as a 16-bit relocatable operand. Store the
13257 expression in *EP and the relocations in the array starting
13258 at RELOC. Return the number of relocation operators used.
13260 On exit, EXPR_END points to the first character after the expression. */
13263 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13266 bfd_reloc_code_real_type reversed_reloc
[3];
13267 size_t reloc_index
, i
;
13268 int crux_depth
, str_depth
;
13271 /* Search for the start of the main expression, recoding relocations
13272 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13273 of the main expression and with CRUX_DEPTH containing the number
13274 of open brackets at that point. */
13281 crux_depth
= str_depth
;
13283 /* Skip over whitespace and brackets, keeping count of the number
13285 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13290 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13291 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13293 my_getExpression (ep
, crux
);
13296 /* Match every open bracket. */
13297 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13301 if (crux_depth
> 0)
13302 as_bad (_("unclosed '('"));
13306 if (reloc_index
!= 0)
13308 prev_reloc_op_frag
= frag_now
;
13309 for (i
= 0; i
< reloc_index
; i
++)
13310 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13313 return reloc_index
;
13317 my_getExpression (expressionS
*ep
, char *str
)
13321 save_in
= input_line_pointer
;
13322 input_line_pointer
= str
;
13324 expr_end
= input_line_pointer
;
13325 input_line_pointer
= save_in
;
13329 md_atof (int type
, char *litP
, int *sizeP
)
13331 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13335 md_number_to_chars (char *buf
, valueT val
, int n
)
13337 if (target_big_endian
)
13338 number_to_chars_bigendian (buf
, val
, n
);
13340 number_to_chars_littleendian (buf
, val
, n
);
13343 static int support_64bit_objects(void)
13345 const char **list
, **l
;
13348 list
= bfd_target_list ();
13349 for (l
= list
; *l
!= NULL
; l
++)
13350 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13351 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13353 yes
= (*l
!= NULL
);
13358 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13359 NEW_VALUE. Warn if another value was already specified. Note:
13360 we have to defer parsing the -march and -mtune arguments in order
13361 to handle 'from-abi' correctly, since the ABI might be specified
13362 in a later argument. */
13365 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13367 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13368 as_warn (_("A different %s was already specified, is now %s"),
13369 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13372 *string_ptr
= new_value
;
13376 md_parse_option (int c
, char *arg
)
13380 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13381 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13383 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13384 c
== mips_ases
[i
].option_on
);
13390 case OPTION_CONSTRUCT_FLOATS
:
13391 mips_disable_float_construction
= 0;
13394 case OPTION_NO_CONSTRUCT_FLOATS
:
13395 mips_disable_float_construction
= 1;
13407 target_big_endian
= 1;
13411 target_big_endian
= 0;
13417 else if (arg
[0] == '0')
13419 else if (arg
[0] == '1')
13429 mips_debug
= atoi (arg
);
13433 file_mips_isa
= ISA_MIPS1
;
13437 file_mips_isa
= ISA_MIPS2
;
13441 file_mips_isa
= ISA_MIPS3
;
13445 file_mips_isa
= ISA_MIPS4
;
13449 file_mips_isa
= ISA_MIPS5
;
13452 case OPTION_MIPS32
:
13453 file_mips_isa
= ISA_MIPS32
;
13456 case OPTION_MIPS32R2
:
13457 file_mips_isa
= ISA_MIPS32R2
;
13460 case OPTION_MIPS64R2
:
13461 file_mips_isa
= ISA_MIPS64R2
;
13464 case OPTION_MIPS64
:
13465 file_mips_isa
= ISA_MIPS64
;
13469 mips_set_option_string (&mips_tune_string
, arg
);
13473 mips_set_option_string (&mips_arch_string
, arg
);
13477 mips_set_option_string (&mips_arch_string
, "4650");
13478 mips_set_option_string (&mips_tune_string
, "4650");
13481 case OPTION_NO_M4650
:
13485 mips_set_option_string (&mips_arch_string
, "4010");
13486 mips_set_option_string (&mips_tune_string
, "4010");
13489 case OPTION_NO_M4010
:
13493 mips_set_option_string (&mips_arch_string
, "4100");
13494 mips_set_option_string (&mips_tune_string
, "4100");
13497 case OPTION_NO_M4100
:
13501 mips_set_option_string (&mips_arch_string
, "3900");
13502 mips_set_option_string (&mips_tune_string
, "3900");
13505 case OPTION_NO_M3900
:
13508 case OPTION_MICROMIPS
:
13509 if (mips_opts
.mips16
== 1)
13511 as_bad (_("-mmicromips cannot be used with -mips16"));
13514 mips_opts
.micromips
= 1;
13515 mips_no_prev_insn ();
13518 case OPTION_NO_MICROMIPS
:
13519 mips_opts
.micromips
= 0;
13520 mips_no_prev_insn ();
13523 case OPTION_MIPS16
:
13524 if (mips_opts
.micromips
== 1)
13526 as_bad (_("-mips16 cannot be used with -micromips"));
13529 mips_opts
.mips16
= 1;
13530 mips_no_prev_insn ();
13533 case OPTION_NO_MIPS16
:
13534 mips_opts
.mips16
= 0;
13535 mips_no_prev_insn ();
13538 case OPTION_FIX_24K
:
13542 case OPTION_NO_FIX_24K
:
13546 case OPTION_FIX_LOONGSON2F_JUMP
:
13547 mips_fix_loongson2f_jump
= TRUE
;
13550 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13551 mips_fix_loongson2f_jump
= FALSE
;
13554 case OPTION_FIX_LOONGSON2F_NOP
:
13555 mips_fix_loongson2f_nop
= TRUE
;
13558 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13559 mips_fix_loongson2f_nop
= FALSE
;
13562 case OPTION_FIX_VR4120
:
13563 mips_fix_vr4120
= 1;
13566 case OPTION_NO_FIX_VR4120
:
13567 mips_fix_vr4120
= 0;
13570 case OPTION_FIX_VR4130
:
13571 mips_fix_vr4130
= 1;
13574 case OPTION_NO_FIX_VR4130
:
13575 mips_fix_vr4130
= 0;
13578 case OPTION_FIX_CN63XXP1
:
13579 mips_fix_cn63xxp1
= TRUE
;
13582 case OPTION_NO_FIX_CN63XXP1
:
13583 mips_fix_cn63xxp1
= FALSE
;
13586 case OPTION_RELAX_BRANCH
:
13587 mips_relax_branch
= 1;
13590 case OPTION_NO_RELAX_BRANCH
:
13591 mips_relax_branch
= 0;
13594 case OPTION_INSN32
:
13595 mips_opts
.insn32
= TRUE
;
13598 case OPTION_NO_INSN32
:
13599 mips_opts
.insn32
= FALSE
;
13602 case OPTION_MSHARED
:
13603 mips_in_shared
= TRUE
;
13606 case OPTION_MNO_SHARED
:
13607 mips_in_shared
= FALSE
;
13610 case OPTION_MSYM32
:
13611 mips_opts
.sym32
= TRUE
;
13614 case OPTION_MNO_SYM32
:
13615 mips_opts
.sym32
= FALSE
;
13618 /* When generating ELF code, we permit -KPIC and -call_shared to
13619 select SVR4_PIC, and -non_shared to select no PIC. This is
13620 intended to be compatible with Irix 5. */
13621 case OPTION_CALL_SHARED
:
13622 mips_pic
= SVR4_PIC
;
13623 mips_abicalls
= TRUE
;
13626 case OPTION_CALL_NONPIC
:
13628 mips_abicalls
= TRUE
;
13631 case OPTION_NON_SHARED
:
13633 mips_abicalls
= FALSE
;
13636 /* The -xgot option tells the assembler to use 32 bit offsets
13637 when accessing the got in SVR4_PIC mode. It is for Irix
13644 g_switch_value
= atoi (arg
);
13648 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13651 mips_abi
= O32_ABI
;
13655 mips_abi
= N32_ABI
;
13659 mips_abi
= N64_ABI
;
13660 if (!support_64bit_objects())
13661 as_fatal (_("No compiled in support for 64 bit object file format"));
13665 file_mips_gp32
= 1;
13669 file_mips_gp32
= 0;
13673 file_mips_fp32
= 1;
13677 file_mips_fp32
= 0;
13680 case OPTION_SINGLE_FLOAT
:
13681 file_mips_single_float
= 1;
13684 case OPTION_DOUBLE_FLOAT
:
13685 file_mips_single_float
= 0;
13688 case OPTION_SOFT_FLOAT
:
13689 file_mips_soft_float
= 1;
13692 case OPTION_HARD_FLOAT
:
13693 file_mips_soft_float
= 0;
13697 if (strcmp (arg
, "32") == 0)
13698 mips_abi
= O32_ABI
;
13699 else if (strcmp (arg
, "o64") == 0)
13700 mips_abi
= O64_ABI
;
13701 else if (strcmp (arg
, "n32") == 0)
13702 mips_abi
= N32_ABI
;
13703 else if (strcmp (arg
, "64") == 0)
13705 mips_abi
= N64_ABI
;
13706 if (! support_64bit_objects())
13707 as_fatal (_("No compiled in support for 64 bit object file "
13710 else if (strcmp (arg
, "eabi") == 0)
13711 mips_abi
= EABI_ABI
;
13714 as_fatal (_("invalid abi -mabi=%s"), arg
);
13719 case OPTION_M7000_HILO_FIX
:
13720 mips_7000_hilo_fix
= TRUE
;
13723 case OPTION_MNO_7000_HILO_FIX
:
13724 mips_7000_hilo_fix
= FALSE
;
13727 case OPTION_MDEBUG
:
13728 mips_flag_mdebug
= TRUE
;
13731 case OPTION_NO_MDEBUG
:
13732 mips_flag_mdebug
= FALSE
;
13736 mips_flag_pdr
= TRUE
;
13739 case OPTION_NO_PDR
:
13740 mips_flag_pdr
= FALSE
;
13743 case OPTION_MVXWORKS_PIC
:
13744 mips_pic
= VXWORKS_PIC
;
13748 if (strcmp (arg
, "2008") == 0)
13749 mips_flag_nan2008
= TRUE
;
13750 else if (strcmp (arg
, "legacy") == 0)
13751 mips_flag_nan2008
= FALSE
;
13754 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13763 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13768 /* Set up globals to generate code for the ISA or processor
13769 described by INFO. */
13772 mips_set_architecture (const struct mips_cpu_info
*info
)
13776 file_mips_arch
= info
->cpu
;
13777 mips_opts
.arch
= info
->cpu
;
13778 mips_opts
.isa
= info
->isa
;
13783 /* Likewise for tuning. */
13786 mips_set_tune (const struct mips_cpu_info
*info
)
13789 mips_tune
= info
->cpu
;
13794 mips_after_parse_args (void)
13796 const struct mips_cpu_info
*arch_info
= 0;
13797 const struct mips_cpu_info
*tune_info
= 0;
13799 /* GP relative stuff not working for PE */
13800 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13802 if (g_switch_seen
&& g_switch_value
!= 0)
13803 as_bad (_("-G not supported in this configuration."));
13804 g_switch_value
= 0;
13807 if (mips_abi
== NO_ABI
)
13808 mips_abi
= MIPS_DEFAULT_ABI
;
13810 /* The following code determines the architecture and register size.
13811 Similar code was added to GCC 3.3 (see override_options() in
13812 config/mips/mips.c). The GAS and GCC code should be kept in sync
13813 as much as possible. */
13815 if (mips_arch_string
!= 0)
13816 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13818 if (file_mips_isa
!= ISA_UNKNOWN
)
13820 /* Handle -mipsN. At this point, file_mips_isa contains the
13821 ISA level specified by -mipsN, while arch_info->isa contains
13822 the -march selection (if any). */
13823 if (arch_info
!= 0)
13825 /* -march takes precedence over -mipsN, since it is more descriptive.
13826 There's no harm in specifying both as long as the ISA levels
13828 if (file_mips_isa
!= arch_info
->isa
)
13829 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13830 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13831 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13834 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13837 if (arch_info
== 0)
13839 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13840 gas_assert (arch_info
);
13843 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13844 as_bad (_("-march=%s is not compatible with the selected ABI"),
13847 mips_set_architecture (arch_info
);
13849 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13850 if (mips_tune_string
!= 0)
13851 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13853 if (tune_info
== 0)
13854 mips_set_tune (arch_info
);
13856 mips_set_tune (tune_info
);
13858 if (file_mips_gp32
>= 0)
13860 /* The user specified the size of the integer registers. Make sure
13861 it agrees with the ABI and ISA. */
13862 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13863 as_bad (_("-mgp64 used with a 32-bit processor"));
13864 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13865 as_bad (_("-mgp32 used with a 64-bit ABI"));
13866 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13867 as_bad (_("-mgp64 used with a 32-bit ABI"));
13871 /* Infer the integer register size from the ABI and processor.
13872 Restrict ourselves to 32-bit registers if that's all the
13873 processor has, or if the ABI cannot handle 64-bit registers. */
13874 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13875 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13878 switch (file_mips_fp32
)
13882 /* No user specified float register size.
13883 ??? GAS treats single-float processors as though they had 64-bit
13884 float registers (although it complains when double-precision
13885 instructions are used). As things stand, saying they have 32-bit
13886 registers would lead to spurious "register must be even" messages.
13887 So here we assume float registers are never smaller than the
13889 if (file_mips_gp32
== 0)
13890 /* 64-bit integer registers implies 64-bit float registers. */
13891 file_mips_fp32
= 0;
13892 else if ((mips_opts
.ase
& FP64_ASES
)
13893 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13894 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13895 file_mips_fp32
= 0;
13897 /* 32-bit float registers. */
13898 file_mips_fp32
= 1;
13901 /* The user specified the size of the float registers. Check if it
13902 agrees with the ABI and ISA. */
13904 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13905 as_bad (_("-mfp64 used with a 32-bit fpu"));
13906 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13907 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13908 as_warn (_("-mfp64 used with a 32-bit ABI"));
13911 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13912 as_warn (_("-mfp32 used with a 64-bit ABI"));
13916 /* End of GCC-shared inference code. */
13918 /* This flag is set when we have a 64-bit capable CPU but use only
13919 32-bit wide registers. Note that EABI does not use it. */
13920 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13921 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13922 || mips_abi
== O32_ABI
))
13923 mips_32bitmode
= 1;
13925 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13926 as_bad (_("trap exception not supported at ISA 1"));
13928 /* If the selected architecture includes support for ASEs, enable
13929 generation of code for them. */
13930 if (mips_opts
.mips16
== -1)
13931 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13932 if (mips_opts
.micromips
== -1)
13933 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13935 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13936 ASEs from being selected implicitly. */
13937 if (file_mips_fp32
== 1)
13938 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13940 /* If the user didn't explicitly select or deselect a particular ASE,
13941 use the default setting for the CPU. */
13942 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13944 file_mips_isa
= mips_opts
.isa
;
13945 file_ase
= mips_opts
.ase
;
13946 mips_opts
.gp32
= file_mips_gp32
;
13947 mips_opts
.fp32
= file_mips_fp32
;
13948 mips_opts
.soft_float
= file_mips_soft_float
;
13949 mips_opts
.single_float
= file_mips_single_float
;
13951 mips_check_isa_supports_ases ();
13953 if (mips_flag_mdebug
< 0)
13954 mips_flag_mdebug
= 0;
13958 mips_init_after_args (void)
13960 /* initialize opcodes */
13961 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
13962 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
13966 md_pcrel_from (fixS
*fixP
)
13968 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13969 switch (fixP
->fx_r_type
)
13971 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
13972 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
13973 /* Return the address of the delay slot. */
13976 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
13977 case BFD_RELOC_MICROMIPS_JMP
:
13978 case BFD_RELOC_16_PCREL_S2
:
13979 case BFD_RELOC_MIPS_JMP
:
13980 /* Return the address of the delay slot. */
13983 case BFD_RELOC_32_PCREL
:
13987 /* We have no relocation type for PC relative MIPS16 instructions. */
13988 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
13989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
13990 _("PC relative MIPS16 instruction references a different section"));
13995 /* This is called before the symbol table is processed. In order to
13996 work with gcc when using mips-tfile, we must keep all local labels.
13997 However, in other cases, we want to discard them. If we were
13998 called with -g, but we didn't see any debugging information, it may
13999 mean that gcc is smuggling debugging information through to
14000 mips-tfile, in which case we must generate all local labels. */
14003 mips_frob_file_before_adjust (void)
14005 #ifndef NO_ECOFF_DEBUGGING
14006 if (ECOFF_DEBUGGING
14008 && ! ecoff_debugging_seen
)
14009 flag_keep_locals
= 1;
14013 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14014 the corresponding LO16 reloc. This is called before md_apply_fix and
14015 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14016 relocation operators.
14018 For our purposes, a %lo() expression matches a %got() or %hi()
14021 (a) it refers to the same symbol; and
14022 (b) the offset applied in the %lo() expression is no lower than
14023 the offset applied in the %got() or %hi().
14025 (b) allows us to cope with code like:
14028 lh $4,%lo(foo+2)($4)
14030 ...which is legal on RELA targets, and has a well-defined behaviour
14031 if the user knows that adding 2 to "foo" will not induce a carry to
14034 When several %lo()s match a particular %got() or %hi(), we use the
14035 following rules to distinguish them:
14037 (1) %lo()s with smaller offsets are a better match than %lo()s with
14040 (2) %lo()s with no matching %got() or %hi() are better than those
14041 that already have a matching %got() or %hi().
14043 (3) later %lo()s are better than earlier %lo()s.
14045 These rules are applied in order.
14047 (1) means, among other things, that %lo()s with identical offsets are
14048 chosen if they exist.
14050 (2) means that we won't associate several high-part relocations with
14051 the same low-part relocation unless there's no alternative. Having
14052 several high parts for the same low part is a GNU extension; this rule
14053 allows careful users to avoid it.
14055 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14056 with the last high-part relocation being at the front of the list.
14057 It therefore makes sense to choose the last matching low-part
14058 relocation, all other things being equal. It's also easier
14059 to code that way. */
14062 mips_frob_file (void)
14064 struct mips_hi_fixup
*l
;
14065 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14067 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14069 segment_info_type
*seginfo
;
14070 bfd_boolean matched_lo_p
;
14071 fixS
**hi_pos
, **lo_pos
, **pos
;
14073 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14075 /* If a GOT16 relocation turns out to be against a global symbol,
14076 there isn't supposed to be a matching LO. Ignore %gots against
14077 constants; we'll report an error for those later. */
14078 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14079 && !(l
->fixp
->fx_addsy
14080 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14083 /* Check quickly whether the next fixup happens to be a matching %lo. */
14084 if (fixup_has_matching_lo_p (l
->fixp
))
14087 seginfo
= seg_info (l
->seg
);
14089 /* Set HI_POS to the position of this relocation in the chain.
14090 Set LO_POS to the position of the chosen low-part relocation.
14091 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14092 relocation that matches an immediately-preceding high-part
14096 matched_lo_p
= FALSE
;
14097 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14099 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14101 if (*pos
== l
->fixp
)
14104 if ((*pos
)->fx_r_type
== looking_for_rtype
14105 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14106 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14108 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14110 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14113 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14114 && fixup_has_matching_lo_p (*pos
));
14117 /* If we found a match, remove the high-part relocation from its
14118 current position and insert it before the low-part relocation.
14119 Make the offsets match so that fixup_has_matching_lo_p()
14122 We don't warn about unmatched high-part relocations since some
14123 versions of gcc have been known to emit dead "lui ...%hi(...)"
14125 if (lo_pos
!= NULL
)
14127 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14128 if (l
->fixp
->fx_next
!= *lo_pos
)
14130 *hi_pos
= l
->fixp
->fx_next
;
14131 l
->fixp
->fx_next
= *lo_pos
;
14139 mips_force_relocation (fixS
*fixp
)
14141 if (generic_force_reloc (fixp
))
14144 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14145 so that the linker relaxation can update targets. */
14146 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14147 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14148 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14154 /* Read the instruction associated with RELOC from BUF. */
14156 static unsigned int
14157 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14159 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14160 return read_compressed_insn (buf
, 4);
14162 return read_insn (buf
);
14165 /* Write instruction INSN to BUF, given that it has been relocated
14169 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14170 unsigned long insn
)
14172 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14173 write_compressed_insn (buf
, insn
, 4);
14175 write_insn (buf
, insn
);
14178 /* Apply a fixup to the object file. */
14181 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14184 unsigned long insn
;
14185 reloc_howto_type
*howto
;
14187 /* We ignore generic BFD relocations we don't know about. */
14188 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14192 gas_assert (fixP
->fx_size
== 2
14193 || fixP
->fx_size
== 4
14194 || fixP
->fx_r_type
== BFD_RELOC_16
14195 || fixP
->fx_r_type
== BFD_RELOC_64
14196 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14197 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14198 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14199 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14200 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14201 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14203 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14205 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14206 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14207 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14208 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14209 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14211 /* Don't treat parts of a composite relocation as done. There are two
14214 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14215 should nevertheless be emitted if the first part is.
14217 (2) In normal usage, composite relocations are never assembly-time
14218 constants. The easiest way of dealing with the pathological
14219 exceptions is to generate a relocation against STN_UNDEF and
14220 leave everything up to the linker. */
14221 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14224 switch (fixP
->fx_r_type
)
14226 case BFD_RELOC_MIPS_TLS_GD
:
14227 case BFD_RELOC_MIPS_TLS_LDM
:
14228 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14229 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14230 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14231 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14232 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14233 case BFD_RELOC_MIPS_TLS_TPREL32
:
14234 case BFD_RELOC_MIPS_TLS_TPREL64
:
14235 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14236 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14237 case BFD_RELOC_MICROMIPS_TLS_GD
:
14238 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14239 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14240 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14241 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14242 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14243 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14244 case BFD_RELOC_MIPS16_TLS_GD
:
14245 case BFD_RELOC_MIPS16_TLS_LDM
:
14246 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14247 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14248 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14249 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14250 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14251 if (!fixP
->fx_addsy
)
14253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14254 _("TLS relocation against a constant"));
14257 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14260 case BFD_RELOC_MIPS_JMP
:
14261 case BFD_RELOC_MIPS_SHIFT5
:
14262 case BFD_RELOC_MIPS_SHIFT6
:
14263 case BFD_RELOC_MIPS_GOT_DISP
:
14264 case BFD_RELOC_MIPS_GOT_PAGE
:
14265 case BFD_RELOC_MIPS_GOT_OFST
:
14266 case BFD_RELOC_MIPS_SUB
:
14267 case BFD_RELOC_MIPS_INSERT_A
:
14268 case BFD_RELOC_MIPS_INSERT_B
:
14269 case BFD_RELOC_MIPS_DELETE
:
14270 case BFD_RELOC_MIPS_HIGHEST
:
14271 case BFD_RELOC_MIPS_HIGHER
:
14272 case BFD_RELOC_MIPS_SCN_DISP
:
14273 case BFD_RELOC_MIPS_REL16
:
14274 case BFD_RELOC_MIPS_RELGOT
:
14275 case BFD_RELOC_MIPS_JALR
:
14276 case BFD_RELOC_HI16
:
14277 case BFD_RELOC_HI16_S
:
14278 case BFD_RELOC_LO16
:
14279 case BFD_RELOC_GPREL16
:
14280 case BFD_RELOC_MIPS_LITERAL
:
14281 case BFD_RELOC_MIPS_CALL16
:
14282 case BFD_RELOC_MIPS_GOT16
:
14283 case BFD_RELOC_GPREL32
:
14284 case BFD_RELOC_MIPS_GOT_HI16
:
14285 case BFD_RELOC_MIPS_GOT_LO16
:
14286 case BFD_RELOC_MIPS_CALL_HI16
:
14287 case BFD_RELOC_MIPS_CALL_LO16
:
14288 case BFD_RELOC_MIPS16_GPREL
:
14289 case BFD_RELOC_MIPS16_GOT16
:
14290 case BFD_RELOC_MIPS16_CALL16
:
14291 case BFD_RELOC_MIPS16_HI16
:
14292 case BFD_RELOC_MIPS16_HI16_S
:
14293 case BFD_RELOC_MIPS16_LO16
:
14294 case BFD_RELOC_MIPS16_JMP
:
14295 case BFD_RELOC_MICROMIPS_JMP
:
14296 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14297 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14298 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14299 case BFD_RELOC_MICROMIPS_SUB
:
14300 case BFD_RELOC_MICROMIPS_HIGHEST
:
14301 case BFD_RELOC_MICROMIPS_HIGHER
:
14302 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14303 case BFD_RELOC_MICROMIPS_JALR
:
14304 case BFD_RELOC_MICROMIPS_HI16
:
14305 case BFD_RELOC_MICROMIPS_HI16_S
:
14306 case BFD_RELOC_MICROMIPS_LO16
:
14307 case BFD_RELOC_MICROMIPS_GPREL16
:
14308 case BFD_RELOC_MICROMIPS_LITERAL
:
14309 case BFD_RELOC_MICROMIPS_CALL16
:
14310 case BFD_RELOC_MICROMIPS_GOT16
:
14311 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14312 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14313 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14314 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14315 case BFD_RELOC_MIPS_EH
:
14320 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14322 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14323 if (mips16_reloc_p (fixP
->fx_r_type
))
14324 insn
|= mips16_immed_extend (value
, 16);
14326 insn
|= (value
& 0xffff);
14327 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14331 _("Unsupported constant in relocation"));
14336 /* This is handled like BFD_RELOC_32, but we output a sign
14337 extended value if we are only 32 bits. */
14340 if (8 <= sizeof (valueT
))
14341 md_number_to_chars (buf
, *valP
, 8);
14346 if ((*valP
& 0x80000000) != 0)
14350 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14351 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14356 case BFD_RELOC_RVA
:
14358 case BFD_RELOC_32_PCREL
:
14360 /* If we are deleting this reloc entry, we must fill in the
14361 value now. This can happen if we have a .word which is not
14362 resolved when it appears but is later defined. */
14364 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14367 case BFD_RELOC_16_PCREL_S2
:
14368 if ((*valP
& 0x3) != 0)
14369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14370 _("Branch to misaligned address (%lx)"), (long) *valP
);
14372 /* We need to save the bits in the instruction since fixup_segment()
14373 might be deleting the relocation entry (i.e., a branch within
14374 the current segment). */
14375 if (! fixP
->fx_done
)
14378 /* Update old instruction data. */
14379 insn
= read_insn (buf
);
14381 if (*valP
+ 0x20000 <= 0x3ffff)
14383 insn
|= (*valP
>> 2) & 0xffff;
14384 write_insn (buf
, insn
);
14386 else if (mips_pic
== NO_PIC
14388 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14389 && (fixP
->fx_frag
->fr_address
14390 < text_section
->vma
+ bfd_get_section_size (text_section
))
14391 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14392 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14393 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14395 /* The branch offset is too large. If this is an
14396 unconditional branch, and we are not generating PIC code,
14397 we can convert it to an absolute jump instruction. */
14398 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14399 insn
= 0x0c000000; /* jal */
14401 insn
= 0x08000000; /* j */
14402 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14404 fixP
->fx_addsy
= section_symbol (text_section
);
14405 *valP
+= md_pcrel_from (fixP
);
14406 write_insn (buf
, insn
);
14410 /* If we got here, we have branch-relaxation disabled,
14411 and there's nothing we can do to fix this instruction
14412 without turning it into a longer sequence. */
14413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14414 _("Branch out of range"));
14418 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14419 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14420 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14421 /* We adjust the offset back to even. */
14422 if ((*valP
& 0x1) != 0)
14425 if (! fixP
->fx_done
)
14428 /* Should never visit here, because we keep the relocation. */
14432 case BFD_RELOC_VTABLE_INHERIT
:
14435 && !S_IS_DEFINED (fixP
->fx_addsy
)
14436 && !S_IS_WEAK (fixP
->fx_addsy
))
14437 S_SET_WEAK (fixP
->fx_addsy
);
14440 case BFD_RELOC_VTABLE_ENTRY
:
14448 /* Remember value for tc_gen_reloc. */
14449 fixP
->fx_addnumber
= *valP
;
14459 name
= input_line_pointer
;
14460 c
= get_symbol_end ();
14461 p
= (symbolS
*) symbol_find_or_make (name
);
14462 *input_line_pointer
= c
;
14466 /* Align the current frag to a given power of two. If a particular
14467 fill byte should be used, FILL points to an integer that contains
14468 that byte, otherwise FILL is null.
14470 This function used to have the comment:
14472 The MIPS assembler also automatically adjusts any preceding label.
14474 The implementation therefore applied the adjustment to a maximum of
14475 one label. However, other label adjustments are applied to batches
14476 of labels, and adjusting just one caused problems when new labels
14477 were added for the sake of debugging or unwind information.
14478 We therefore adjust all preceding labels (given as LABELS) instead. */
14481 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14483 mips_emit_delays ();
14484 mips_record_compressed_mode ();
14485 if (fill
== NULL
&& subseg_text_p (now_seg
))
14486 frag_align_code (to
, 0);
14488 frag_align (to
, fill
? *fill
: 0, 0);
14489 record_alignment (now_seg
, to
);
14490 mips_move_labels (labels
, FALSE
);
14493 /* Align to a given power of two. .align 0 turns off the automatic
14494 alignment used by the data creating pseudo-ops. */
14497 s_align (int x ATTRIBUTE_UNUSED
)
14499 int temp
, fill_value
, *fill_ptr
;
14500 long max_alignment
= 28;
14502 /* o Note that the assembler pulls down any immediately preceding label
14503 to the aligned address.
14504 o It's not documented but auto alignment is reinstated by
14505 a .align pseudo instruction.
14506 o Note also that after auto alignment is turned off the mips assembler
14507 issues an error on attempt to assemble an improperly aligned data item.
14510 temp
= get_absolute_expression ();
14511 if (temp
> max_alignment
)
14512 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14515 as_warn (_("Alignment negative: 0 assumed."));
14518 if (*input_line_pointer
== ',')
14520 ++input_line_pointer
;
14521 fill_value
= get_absolute_expression ();
14522 fill_ptr
= &fill_value
;
14528 segment_info_type
*si
= seg_info (now_seg
);
14529 struct insn_label_list
*l
= si
->label_list
;
14530 /* Auto alignment should be switched on by next section change. */
14532 mips_align (temp
, fill_ptr
, l
);
14539 demand_empty_rest_of_line ();
14543 s_change_sec (int sec
)
14547 /* The ELF backend needs to know that we are changing sections, so
14548 that .previous works correctly. We could do something like check
14549 for an obj_section_change_hook macro, but that might be confusing
14550 as it would not be appropriate to use it in the section changing
14551 functions in read.c, since obj-elf.c intercepts those. FIXME:
14552 This should be cleaner, somehow. */
14553 obj_elf_section_change_hook ();
14555 mips_emit_delays ();
14566 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14567 demand_empty_rest_of_line ();
14571 seg
= subseg_new (RDATA_SECTION_NAME
,
14572 (subsegT
) get_absolute_expression ());
14573 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14574 | SEC_READONLY
| SEC_RELOC
14576 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14577 record_alignment (seg
, 4);
14578 demand_empty_rest_of_line ();
14582 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14583 bfd_set_section_flags (stdoutput
, seg
,
14584 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14585 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14586 record_alignment (seg
, 4);
14587 demand_empty_rest_of_line ();
14591 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14592 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14593 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14594 record_alignment (seg
, 4);
14595 demand_empty_rest_of_line ();
14603 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14605 char *section_name
;
14610 int section_entry_size
;
14611 int section_alignment
;
14613 section_name
= input_line_pointer
;
14614 c
= get_symbol_end ();
14616 next_c
= *(input_line_pointer
+ 1);
14618 /* Do we have .section Name<,"flags">? */
14619 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14621 /* just after name is now '\0'. */
14622 *input_line_pointer
= c
;
14623 input_line_pointer
= section_name
;
14624 obj_elf_section (ignore
);
14627 input_line_pointer
++;
14629 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14631 section_type
= get_absolute_expression ();
14634 if (*input_line_pointer
++ == ',')
14635 section_flag
= get_absolute_expression ();
14638 if (*input_line_pointer
++ == ',')
14639 section_entry_size
= get_absolute_expression ();
14641 section_entry_size
= 0;
14642 if (*input_line_pointer
++ == ',')
14643 section_alignment
= get_absolute_expression ();
14645 section_alignment
= 0;
14646 /* FIXME: really ignore? */
14647 (void) section_alignment
;
14649 section_name
= xstrdup (section_name
);
14651 /* When using the generic form of .section (as implemented by obj-elf.c),
14652 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14653 traditionally had to fall back on the more common @progbits instead.
14655 There's nothing really harmful in this, since bfd will correct
14656 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14657 means that, for backwards compatibility, the special_section entries
14658 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14660 Even so, we shouldn't force users of the MIPS .section syntax to
14661 incorrectly label the sections as SHT_PROGBITS. The best compromise
14662 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14663 generic type-checking code. */
14664 if (section_type
== SHT_MIPS_DWARF
)
14665 section_type
= SHT_PROGBITS
;
14667 obj_elf_change_section (section_name
, section_type
, section_flag
,
14668 section_entry_size
, 0, 0, 0);
14670 if (now_seg
->name
!= section_name
)
14671 free (section_name
);
14675 mips_enable_auto_align (void)
14681 s_cons (int log_size
)
14683 segment_info_type
*si
= seg_info (now_seg
);
14684 struct insn_label_list
*l
= si
->label_list
;
14686 mips_emit_delays ();
14687 if (log_size
> 0 && auto_align
)
14688 mips_align (log_size
, 0, l
);
14689 cons (1 << log_size
);
14690 mips_clear_insn_labels ();
14694 s_float_cons (int type
)
14696 segment_info_type
*si
= seg_info (now_seg
);
14697 struct insn_label_list
*l
= si
->label_list
;
14699 mips_emit_delays ();
14704 mips_align (3, 0, l
);
14706 mips_align (2, 0, l
);
14710 mips_clear_insn_labels ();
14713 /* Handle .globl. We need to override it because on Irix 5 you are
14716 where foo is an undefined symbol, to mean that foo should be
14717 considered to be the address of a function. */
14720 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14729 name
= input_line_pointer
;
14730 c
= get_symbol_end ();
14731 symbolP
= symbol_find_or_make (name
);
14732 S_SET_EXTERNAL (symbolP
);
14734 *input_line_pointer
= c
;
14735 SKIP_WHITESPACE ();
14737 /* On Irix 5, every global symbol that is not explicitly labelled as
14738 being a function is apparently labelled as being an object. */
14741 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14742 && (*input_line_pointer
!= ','))
14747 secname
= input_line_pointer
;
14748 c
= get_symbol_end ();
14749 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14751 as_bad (_("%s: no such section"), secname
);
14752 *input_line_pointer
= c
;
14754 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14755 flag
= BSF_FUNCTION
;
14758 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14760 c
= *input_line_pointer
;
14763 input_line_pointer
++;
14764 SKIP_WHITESPACE ();
14765 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14771 demand_empty_rest_of_line ();
14775 s_option (int x ATTRIBUTE_UNUSED
)
14780 opt
= input_line_pointer
;
14781 c
= get_symbol_end ();
14785 /* FIXME: What does this mean? */
14787 else if (strncmp (opt
, "pic", 3) == 0)
14791 i
= atoi (opt
+ 3);
14796 mips_pic
= SVR4_PIC
;
14797 mips_abicalls
= TRUE
;
14800 as_bad (_(".option pic%d not supported"), i
);
14802 if (mips_pic
== SVR4_PIC
)
14804 if (g_switch_seen
&& g_switch_value
!= 0)
14805 as_warn (_("-G may not be used with SVR4 PIC code"));
14806 g_switch_value
= 0;
14807 bfd_set_gp_size (stdoutput
, 0);
14811 as_warn (_("Unrecognized option \"%s\""), opt
);
14813 *input_line_pointer
= c
;
14814 demand_empty_rest_of_line ();
14817 /* This structure is used to hold a stack of .set values. */
14819 struct mips_option_stack
14821 struct mips_option_stack
*next
;
14822 struct mips_set_options options
;
14825 static struct mips_option_stack
*mips_opts_stack
;
14827 /* Handle the .set pseudo-op. */
14830 s_mipsset (int x ATTRIBUTE_UNUSED
)
14832 char *name
= input_line_pointer
, ch
;
14833 const struct mips_ase
*ase
;
14835 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14836 ++input_line_pointer
;
14837 ch
= *input_line_pointer
;
14838 *input_line_pointer
= '\0';
14840 if (strcmp (name
, "reorder") == 0)
14842 if (mips_opts
.noreorder
)
14845 else if (strcmp (name
, "noreorder") == 0)
14847 if (!mips_opts
.noreorder
)
14848 start_noreorder ();
14850 else if (strncmp (name
, "at=", 3) == 0)
14852 char *s
= name
+ 3;
14854 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14855 as_bad (_("Unrecognized register name `%s'"), s
);
14857 else if (strcmp (name
, "at") == 0)
14859 mips_opts
.at
= ATREG
;
14861 else if (strcmp (name
, "noat") == 0)
14863 mips_opts
.at
= ZERO
;
14865 else if (strcmp (name
, "macro") == 0)
14867 mips_opts
.warn_about_macros
= 0;
14869 else if (strcmp (name
, "nomacro") == 0)
14871 if (mips_opts
.noreorder
== 0)
14872 as_bad (_("`noreorder' must be set before `nomacro'"));
14873 mips_opts
.warn_about_macros
= 1;
14875 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14877 mips_opts
.nomove
= 0;
14879 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14881 mips_opts
.nomove
= 1;
14883 else if (strcmp (name
, "bopt") == 0)
14885 mips_opts
.nobopt
= 0;
14887 else if (strcmp (name
, "nobopt") == 0)
14889 mips_opts
.nobopt
= 1;
14891 else if (strcmp (name
, "gp=default") == 0)
14892 mips_opts
.gp32
= file_mips_gp32
;
14893 else if (strcmp (name
, "gp=32") == 0)
14894 mips_opts
.gp32
= 1;
14895 else if (strcmp (name
, "gp=64") == 0)
14897 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14898 as_warn (_("%s isa does not support 64-bit registers"),
14899 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14900 mips_opts
.gp32
= 0;
14902 else if (strcmp (name
, "fp=default") == 0)
14903 mips_opts
.fp32
= file_mips_fp32
;
14904 else if (strcmp (name
, "fp=32") == 0)
14905 mips_opts
.fp32
= 1;
14906 else if (strcmp (name
, "fp=64") == 0)
14908 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14909 as_warn (_("%s isa does not support 64-bit floating point registers"),
14910 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14911 mips_opts
.fp32
= 0;
14913 else if (strcmp (name
, "softfloat") == 0)
14914 mips_opts
.soft_float
= 1;
14915 else if (strcmp (name
, "hardfloat") == 0)
14916 mips_opts
.soft_float
= 0;
14917 else if (strcmp (name
, "singlefloat") == 0)
14918 mips_opts
.single_float
= 1;
14919 else if (strcmp (name
, "doublefloat") == 0)
14920 mips_opts
.single_float
= 0;
14921 else if (strcmp (name
, "mips16") == 0
14922 || strcmp (name
, "MIPS-16") == 0)
14924 if (mips_opts
.micromips
== 1)
14925 as_fatal (_("`mips16' cannot be used with `micromips'"));
14926 mips_opts
.mips16
= 1;
14928 else if (strcmp (name
, "nomips16") == 0
14929 || strcmp (name
, "noMIPS-16") == 0)
14930 mips_opts
.mips16
= 0;
14931 else if (strcmp (name
, "micromips") == 0)
14933 if (mips_opts
.mips16
== 1)
14934 as_fatal (_("`micromips' cannot be used with `mips16'"));
14935 mips_opts
.micromips
= 1;
14937 else if (strcmp (name
, "nomicromips") == 0)
14938 mips_opts
.micromips
= 0;
14939 else if (name
[0] == 'n'
14941 && (ase
= mips_lookup_ase (name
+ 2)))
14942 mips_set_ase (ase
, FALSE
);
14943 else if ((ase
= mips_lookup_ase (name
)))
14944 mips_set_ase (ase
, TRUE
);
14945 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
14949 /* Permit the user to change the ISA and architecture on the fly.
14950 Needless to say, misuse can cause serious problems. */
14951 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
14954 mips_opts
.isa
= file_mips_isa
;
14955 mips_opts
.arch
= file_mips_arch
;
14957 else if (strncmp (name
, "arch=", 5) == 0)
14959 const struct mips_cpu_info
*p
;
14961 p
= mips_parse_cpu("internal use", name
+ 5);
14963 as_bad (_("unknown architecture %s"), name
+ 5);
14966 mips_opts
.arch
= p
->cpu
;
14967 mips_opts
.isa
= p
->isa
;
14970 else if (strncmp (name
, "mips", 4) == 0)
14972 const struct mips_cpu_info
*p
;
14974 p
= mips_parse_cpu("internal use", name
);
14976 as_bad (_("unknown ISA level %s"), name
+ 4);
14979 mips_opts
.arch
= p
->cpu
;
14980 mips_opts
.isa
= p
->isa
;
14984 as_bad (_("unknown ISA or architecture %s"), name
);
14986 switch (mips_opts
.isa
)
14994 mips_opts
.gp32
= 1;
14995 mips_opts
.fp32
= 1;
15002 mips_opts
.gp32
= 0;
15003 if (mips_opts
.arch
== CPU_R5900
)
15005 mips_opts
.fp32
= 1;
15009 mips_opts
.fp32
= 0;
15013 as_bad (_("unknown ISA level %s"), name
+ 4);
15018 mips_opts
.gp32
= file_mips_gp32
;
15019 mips_opts
.fp32
= file_mips_fp32
;
15022 else if (strcmp (name
, "autoextend") == 0)
15023 mips_opts
.noautoextend
= 0;
15024 else if (strcmp (name
, "noautoextend") == 0)
15025 mips_opts
.noautoextend
= 1;
15026 else if (strcmp (name
, "insn32") == 0)
15027 mips_opts
.insn32
= TRUE
;
15028 else if (strcmp (name
, "noinsn32") == 0)
15029 mips_opts
.insn32
= FALSE
;
15030 else if (strcmp (name
, "push") == 0)
15032 struct mips_option_stack
*s
;
15034 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15035 s
->next
= mips_opts_stack
;
15036 s
->options
= mips_opts
;
15037 mips_opts_stack
= s
;
15039 else if (strcmp (name
, "pop") == 0)
15041 struct mips_option_stack
*s
;
15043 s
= mips_opts_stack
;
15045 as_bad (_(".set pop with no .set push"));
15048 /* If we're changing the reorder mode we need to handle
15049 delay slots correctly. */
15050 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15051 start_noreorder ();
15052 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15055 mips_opts
= s
->options
;
15056 mips_opts_stack
= s
->next
;
15060 else if (strcmp (name
, "sym32") == 0)
15061 mips_opts
.sym32
= TRUE
;
15062 else if (strcmp (name
, "nosym32") == 0)
15063 mips_opts
.sym32
= FALSE
;
15064 else if (strchr (name
, ','))
15066 /* Generic ".set" directive; use the generic handler. */
15067 *input_line_pointer
= ch
;
15068 input_line_pointer
= name
;
15074 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
15076 mips_check_isa_supports_ases ();
15077 *input_line_pointer
= ch
;
15078 demand_empty_rest_of_line ();
15081 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15082 .option pic2. It means to generate SVR4 PIC calls. */
15085 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15087 mips_pic
= SVR4_PIC
;
15088 mips_abicalls
= TRUE
;
15090 if (g_switch_seen
&& g_switch_value
!= 0)
15091 as_warn (_("-G may not be used with SVR4 PIC code"));
15092 g_switch_value
= 0;
15094 bfd_set_gp_size (stdoutput
, 0);
15095 demand_empty_rest_of_line ();
15098 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15099 PIC code. It sets the $gp register for the function based on the
15100 function address, which is in the register named in the argument.
15101 This uses a relocation against _gp_disp, which is handled specially
15102 by the linker. The result is:
15103 lui $gp,%hi(_gp_disp)
15104 addiu $gp,$gp,%lo(_gp_disp)
15105 addu $gp,$gp,.cpload argument
15106 The .cpload argument is normally $25 == $t9.
15108 The -mno-shared option changes this to:
15109 lui $gp,%hi(__gnu_local_gp)
15110 addiu $gp,$gp,%lo(__gnu_local_gp)
15111 and the argument is ignored. This saves an instruction, but the
15112 resulting code is not position independent; it uses an absolute
15113 address for __gnu_local_gp. Thus code assembled with -mno-shared
15114 can go into an ordinary executable, but not into a shared library. */
15117 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15123 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15124 .cpload is ignored. */
15125 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15131 if (mips_opts
.mips16
)
15133 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15134 ignore_rest_of_line ();
15138 /* .cpload should be in a .set noreorder section. */
15139 if (mips_opts
.noreorder
== 0)
15140 as_warn (_(".cpload not in noreorder section"));
15142 reg
= tc_get_register (0);
15144 /* If we need to produce a 64-bit address, we are better off using
15145 the default instruction sequence. */
15146 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15148 ex
.X_op
= O_symbol
;
15149 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15151 ex
.X_op_symbol
= NULL
;
15152 ex
.X_add_number
= 0;
15154 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15155 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15157 mips_mark_labels ();
15158 mips_assembling_insn
= TRUE
;
15161 macro_build_lui (&ex
, mips_gp_register
);
15162 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15163 mips_gp_register
, BFD_RELOC_LO16
);
15165 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15166 mips_gp_register
, reg
);
15169 mips_assembling_insn
= FALSE
;
15170 demand_empty_rest_of_line ();
15173 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15174 .cpsetup $reg1, offset|$reg2, label
15176 If offset is given, this results in:
15177 sd $gp, offset($sp)
15178 lui $gp, %hi(%neg(%gp_rel(label)))
15179 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15180 daddu $gp, $gp, $reg1
15182 If $reg2 is given, this results in:
15183 daddu $reg2, $gp, $0
15184 lui $gp, %hi(%neg(%gp_rel(label)))
15185 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15186 daddu $gp, $gp, $reg1
15187 $reg1 is normally $25 == $t9.
15189 The -mno-shared option replaces the last three instructions with
15191 addiu $gp,$gp,%lo(_gp) */
15194 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15196 expressionS ex_off
;
15197 expressionS ex_sym
;
15200 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15201 We also need NewABI support. */
15202 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15208 if (mips_opts
.mips16
)
15210 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15211 ignore_rest_of_line ();
15215 reg1
= tc_get_register (0);
15216 SKIP_WHITESPACE ();
15217 if (*input_line_pointer
!= ',')
15219 as_bad (_("missing argument separator ',' for .cpsetup"));
15223 ++input_line_pointer
;
15224 SKIP_WHITESPACE ();
15225 if (*input_line_pointer
== '$')
15227 mips_cpreturn_register
= tc_get_register (0);
15228 mips_cpreturn_offset
= -1;
15232 mips_cpreturn_offset
= get_absolute_expression ();
15233 mips_cpreturn_register
= -1;
15235 SKIP_WHITESPACE ();
15236 if (*input_line_pointer
!= ',')
15238 as_bad (_("missing argument separator ',' for .cpsetup"));
15242 ++input_line_pointer
;
15243 SKIP_WHITESPACE ();
15244 expression (&ex_sym
);
15246 mips_mark_labels ();
15247 mips_assembling_insn
= TRUE
;
15250 if (mips_cpreturn_register
== -1)
15252 ex_off
.X_op
= O_constant
;
15253 ex_off
.X_add_symbol
= NULL
;
15254 ex_off
.X_op_symbol
= NULL
;
15255 ex_off
.X_add_number
= mips_cpreturn_offset
;
15257 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15258 BFD_RELOC_LO16
, SP
);
15261 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15262 mips_gp_register
, 0);
15264 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15266 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15267 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15270 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15271 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15272 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15275 mips_gp_register
, reg1
);
15281 ex
.X_op
= O_symbol
;
15282 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15283 ex
.X_op_symbol
= NULL
;
15284 ex
.X_add_number
= 0;
15286 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15287 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15289 macro_build_lui (&ex
, mips_gp_register
);
15290 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15291 mips_gp_register
, BFD_RELOC_LO16
);
15296 mips_assembling_insn
= FALSE
;
15297 demand_empty_rest_of_line ();
15301 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15303 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15304 .cplocal is ignored. */
15305 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15311 if (mips_opts
.mips16
)
15313 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15314 ignore_rest_of_line ();
15318 mips_gp_register
= tc_get_register (0);
15319 demand_empty_rest_of_line ();
15322 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15323 offset from $sp. The offset is remembered, and after making a PIC
15324 call $gp is restored from that location. */
15327 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15331 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15332 .cprestore is ignored. */
15333 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15339 if (mips_opts
.mips16
)
15341 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15342 ignore_rest_of_line ();
15346 mips_cprestore_offset
= get_absolute_expression ();
15347 mips_cprestore_valid
= 1;
15349 ex
.X_op
= O_constant
;
15350 ex
.X_add_symbol
= NULL
;
15351 ex
.X_op_symbol
= NULL
;
15352 ex
.X_add_number
= mips_cprestore_offset
;
15354 mips_mark_labels ();
15355 mips_assembling_insn
= TRUE
;
15358 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15359 SP
, HAVE_64BIT_ADDRESSES
);
15362 mips_assembling_insn
= FALSE
;
15363 demand_empty_rest_of_line ();
15366 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15367 was given in the preceding .cpsetup, it results in:
15368 ld $gp, offset($sp)
15370 If a register $reg2 was given there, it results in:
15371 daddu $gp, $reg2, $0 */
15374 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15378 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15379 We also need NewABI support. */
15380 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15386 if (mips_opts
.mips16
)
15388 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15389 ignore_rest_of_line ();
15393 mips_mark_labels ();
15394 mips_assembling_insn
= TRUE
;
15397 if (mips_cpreturn_register
== -1)
15399 ex
.X_op
= O_constant
;
15400 ex
.X_add_symbol
= NULL
;
15401 ex
.X_op_symbol
= NULL
;
15402 ex
.X_add_number
= mips_cpreturn_offset
;
15404 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15407 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15408 mips_cpreturn_register
, 0);
15411 mips_assembling_insn
= FALSE
;
15412 demand_empty_rest_of_line ();
15415 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15416 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15417 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15418 debug information or MIPS16 TLS. */
15421 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15422 bfd_reloc_code_real_type rtype
)
15429 if (ex
.X_op
!= O_symbol
)
15431 as_bad (_("Unsupported use of %s"), dirstr
);
15432 ignore_rest_of_line ();
15435 p
= frag_more (bytes
);
15436 md_number_to_chars (p
, 0, bytes
);
15437 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15438 demand_empty_rest_of_line ();
15439 mips_clear_insn_labels ();
15442 /* Handle .dtprelword. */
15445 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15447 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15450 /* Handle .dtpreldword. */
15453 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15455 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15458 /* Handle .tprelword. */
15461 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15463 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15466 /* Handle .tpreldword. */
15469 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15471 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15474 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15475 code. It sets the offset to use in gp_rel relocations. */
15478 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15480 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15481 We also need NewABI support. */
15482 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15488 mips_gprel_offset
= get_absolute_expression ();
15490 demand_empty_rest_of_line ();
15493 /* Handle the .gpword pseudo-op. This is used when generating PIC
15494 code. It generates a 32 bit GP relative reloc. */
15497 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15499 segment_info_type
*si
;
15500 struct insn_label_list
*l
;
15504 /* When not generating PIC code, this is treated as .word. */
15505 if (mips_pic
!= SVR4_PIC
)
15511 si
= seg_info (now_seg
);
15512 l
= si
->label_list
;
15513 mips_emit_delays ();
15515 mips_align (2, 0, l
);
15518 mips_clear_insn_labels ();
15520 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15522 as_bad (_("Unsupported use of .gpword"));
15523 ignore_rest_of_line ();
15527 md_number_to_chars (p
, 0, 4);
15528 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15529 BFD_RELOC_GPREL32
);
15531 demand_empty_rest_of_line ();
15535 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15537 segment_info_type
*si
;
15538 struct insn_label_list
*l
;
15542 /* When not generating PIC code, this is treated as .dword. */
15543 if (mips_pic
!= SVR4_PIC
)
15549 si
= seg_info (now_seg
);
15550 l
= si
->label_list
;
15551 mips_emit_delays ();
15553 mips_align (3, 0, l
);
15556 mips_clear_insn_labels ();
15558 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15560 as_bad (_("Unsupported use of .gpdword"));
15561 ignore_rest_of_line ();
15565 md_number_to_chars (p
, 0, 8);
15566 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15567 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15569 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15570 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15571 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15573 demand_empty_rest_of_line ();
15576 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15577 tables. It generates a R_MIPS_EH reloc. */
15580 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15585 mips_emit_delays ();
15588 mips_clear_insn_labels ();
15590 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15592 as_bad (_("Unsupported use of .ehword"));
15593 ignore_rest_of_line ();
15597 md_number_to_chars (p
, 0, 4);
15598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15599 BFD_RELOC_MIPS_EH
);
15601 demand_empty_rest_of_line ();
15604 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15605 tables in SVR4 PIC code. */
15608 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15612 /* This is ignored when not generating SVR4 PIC code. */
15613 if (mips_pic
!= SVR4_PIC
)
15619 mips_mark_labels ();
15620 mips_assembling_insn
= TRUE
;
15622 /* Add $gp to the register named as an argument. */
15624 reg
= tc_get_register (0);
15625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15628 mips_assembling_insn
= FALSE
;
15629 demand_empty_rest_of_line ();
15632 /* Handle the .insn pseudo-op. This marks instruction labels in
15633 mips16/micromips mode. This permits the linker to handle them specially,
15634 such as generating jalx instructions when needed. We also make
15635 them odd for the duration of the assembly, in order to generate the
15636 right sort of code. We will make them even in the adjust_symtab
15637 routine, while leaving them marked. This is convenient for the
15638 debugger and the disassembler. The linker knows to make them odd
15642 s_insn (int ignore ATTRIBUTE_UNUSED
)
15644 mips_mark_labels ();
15646 demand_empty_rest_of_line ();
15649 /* Handle the .nan pseudo-op. */
15652 s_nan (int ignore ATTRIBUTE_UNUSED
)
15654 static const char str_legacy
[] = "legacy";
15655 static const char str_2008
[] = "2008";
15658 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15660 if (i
== sizeof (str_2008
) - 1
15661 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15662 mips_flag_nan2008
= TRUE
;
15663 else if (i
== sizeof (str_legacy
) - 1
15664 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15665 mips_flag_nan2008
= FALSE
;
15667 as_bad (_("Bad .nan directive"));
15669 input_line_pointer
+= i
;
15670 demand_empty_rest_of_line ();
15673 /* Handle a .stab[snd] directive. Ideally these directives would be
15674 implemented in a transparent way, so that removing them would not
15675 have any effect on the generated instructions. However, s_stab
15676 internally changes the section, so in practice we need to decide
15677 now whether the preceding label marks compressed code. We do not
15678 support changing the compression mode of a label after a .stab*
15679 directive, such as in:
15685 so the current mode wins. */
15688 s_mips_stab (int type
)
15690 mips_mark_labels ();
15694 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15697 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15704 name
= input_line_pointer
;
15705 c
= get_symbol_end ();
15706 symbolP
= symbol_find_or_make (name
);
15707 S_SET_WEAK (symbolP
);
15708 *input_line_pointer
= c
;
15710 SKIP_WHITESPACE ();
15712 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15714 if (S_IS_DEFINED (symbolP
))
15716 as_bad (_("ignoring attempt to redefine symbol %s"),
15717 S_GET_NAME (symbolP
));
15718 ignore_rest_of_line ();
15722 if (*input_line_pointer
== ',')
15724 ++input_line_pointer
;
15725 SKIP_WHITESPACE ();
15729 if (exp
.X_op
!= O_symbol
)
15731 as_bad (_("bad .weakext directive"));
15732 ignore_rest_of_line ();
15735 symbol_set_value_expression (symbolP
, &exp
);
15738 demand_empty_rest_of_line ();
15741 /* Parse a register string into a number. Called from the ECOFF code
15742 to parse .frame. The argument is non-zero if this is the frame
15743 register, so that we can record it in mips_frame_reg. */
15746 tc_get_register (int frame
)
15750 SKIP_WHITESPACE ();
15751 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15755 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15756 mips_frame_reg_valid
= 1;
15757 mips_cprestore_valid
= 0;
15763 md_section_align (asection
*seg
, valueT addr
)
15765 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15767 /* We don't need to align ELF sections to the full alignment.
15768 However, Irix 5 may prefer that we align them at least to a 16
15769 byte boundary. We don't bother to align the sections if we
15770 are targeted for an embedded system. */
15771 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15776 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15779 /* Utility routine, called from above as well. If called while the
15780 input file is still being read, it's only an approximation. (For
15781 example, a symbol may later become defined which appeared to be
15782 undefined earlier.) */
15785 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15790 if (g_switch_value
> 0)
15792 const char *symname
;
15795 /* Find out whether this symbol can be referenced off the $gp
15796 register. It can be if it is smaller than the -G size or if
15797 it is in the .sdata or .sbss section. Certain symbols can
15798 not be referenced off the $gp, although it appears as though
15800 symname
= S_GET_NAME (sym
);
15801 if (symname
!= (const char *) NULL
15802 && (strcmp (symname
, "eprol") == 0
15803 || strcmp (symname
, "etext") == 0
15804 || strcmp (symname
, "_gp") == 0
15805 || strcmp (symname
, "edata") == 0
15806 || strcmp (symname
, "_fbss") == 0
15807 || strcmp (symname
, "_fdata") == 0
15808 || strcmp (symname
, "_ftext") == 0
15809 || strcmp (symname
, "end") == 0
15810 || strcmp (symname
, "_gp_disp") == 0))
15812 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15814 #ifndef NO_ECOFF_DEBUGGING
15815 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15816 && (symbol_get_obj (sym
)->ecoff_extern_size
15817 <= g_switch_value
))
15819 /* We must defer this decision until after the whole
15820 file has been read, since there might be a .extern
15821 after the first use of this symbol. */
15822 || (before_relaxing
15823 #ifndef NO_ECOFF_DEBUGGING
15824 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15826 && S_GET_VALUE (sym
) == 0)
15827 || (S_GET_VALUE (sym
) != 0
15828 && S_GET_VALUE (sym
) <= g_switch_value
)))
15832 const char *segname
;
15834 segname
= segment_name (S_GET_SEGMENT (sym
));
15835 gas_assert (strcmp (segname
, ".lit8") != 0
15836 && strcmp (segname
, ".lit4") != 0);
15837 change
= (strcmp (segname
, ".sdata") != 0
15838 && strcmp (segname
, ".sbss") != 0
15839 && strncmp (segname
, ".sdata.", 7) != 0
15840 && strncmp (segname
, ".sbss.", 6) != 0
15841 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15842 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15847 /* We are not optimizing for the $gp register. */
15852 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15855 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15859 /* Handle the case of a symbol equated to another symbol. */
15860 while (symbol_equated_reloc_p (sym
))
15864 /* It's possible to get a loop here in a badly written program. */
15865 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15871 if (symbol_section_p (sym
))
15874 symsec
= S_GET_SEGMENT (sym
);
15876 /* This must duplicate the test in adjust_reloc_syms. */
15877 return (!bfd_is_und_section (symsec
)
15878 && !bfd_is_abs_section (symsec
)
15879 && !bfd_is_com_section (symsec
)
15880 && !s_is_linkonce (sym
, segtype
)
15881 /* A global or weak symbol is treated as external. */
15882 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15886 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15887 extended opcode. SEC is the section the frag is in. */
15890 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15893 const struct mips_int_operand
*operand
;
15898 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15900 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15903 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15904 operand
= mips16_immed_operand (type
, FALSE
);
15906 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15907 val
= S_GET_VALUE (fragp
->fr_symbol
);
15908 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15910 if (operand
->root
.type
== OP_PCREL
)
15912 const struct mips_pcrel_operand
*pcrel_op
;
15916 /* We won't have the section when we are called from
15917 mips_relax_frag. However, we will always have been called
15918 from md_estimate_size_before_relax first. If this is a
15919 branch to a different section, we mark it as such. If SEC is
15920 NULL, and the frag is not marked, then it must be a branch to
15921 the same section. */
15922 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
15925 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15930 /* Must have been called from md_estimate_size_before_relax. */
15933 fragp
->fr_subtype
=
15934 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15936 /* FIXME: We should support this, and let the linker
15937 catch branches and loads that are out of range. */
15938 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15939 _("unsupported PC relative reference to different section"));
15943 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15944 /* Assume non-extended on the first relaxation pass.
15945 The address we have calculated will be bogus if this is
15946 a forward branch to another frag, as the forward frag
15947 will have fr_address == 0. */
15951 /* In this case, we know for sure that the symbol fragment is in
15952 the same section. If the relax_marker of the symbol fragment
15953 differs from the relax_marker of this fragment, we have not
15954 yet adjusted the symbol fragment fr_address. We want to add
15955 in STRETCH in order to get a better estimate of the address.
15956 This particularly matters because of the shift bits. */
15958 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
15962 /* Adjust stretch for any alignment frag. Note that if have
15963 been expanding the earlier code, the symbol may be
15964 defined in what appears to be an earlier frag. FIXME:
15965 This doesn't handle the fr_subtype field, which specifies
15966 a maximum number of bytes to skip when doing an
15968 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
15970 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
15973 stretch
= - ((- stretch
)
15974 & ~ ((1 << (int) f
->fr_offset
) - 1));
15976 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
15985 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
15987 /* The base address rules are complicated. The base address of
15988 a branch is the following instruction. The base address of a
15989 PC relative load or add is the instruction itself, but if it
15990 is in a delay slot (in which case it can not be extended) use
15991 the address of the instruction whose delay slot it is in. */
15992 if (pcrel_op
->include_isa_bit
)
15996 /* If we are currently assuming that this frag should be
15997 extended, then, the current address is two bytes
15999 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16002 /* Ignore the low bit in the target, since it will be set
16003 for a text label. */
16006 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16008 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16011 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16013 /* If any of the shifted bits are set, we must use an extended
16014 opcode. If the address depends on the size of this
16015 instruction, this can lead to a loop, so we arrange to always
16016 use an extended opcode. We only check this when we are in
16017 the main relaxation loop, when SEC is NULL. */
16018 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16020 fragp
->fr_subtype
=
16021 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16025 /* If we are about to mark a frag as extended because the value
16026 is precisely the next value above maxtiny, then there is a
16027 chance of an infinite loop as in the following code:
16032 In this case when the la is extended, foo is 0x3fc bytes
16033 away, so the la can be shrunk, but then foo is 0x400 away, so
16034 the la must be extended. To avoid this loop, we mark the
16035 frag as extended if it was small, and is about to become
16036 extended with the next value above maxtiny. */
16037 maxtiny
= mips_int_operand_max (operand
);
16038 if (val
== maxtiny
+ (1 << operand
->shift
)
16039 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16042 fragp
->fr_subtype
=
16043 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16047 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16048 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16050 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16053 /* Compute the length of a branch sequence, and adjust the
16054 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16055 worst-case length is computed, with UPDATE being used to indicate
16056 whether an unconditional (-1), branch-likely (+1) or regular (0)
16057 branch is to be computed. */
16059 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16061 bfd_boolean toofar
;
16065 && S_IS_DEFINED (fragp
->fr_symbol
)
16066 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16071 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16073 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16077 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16080 /* If the symbol is not defined or it's in a different segment,
16081 assume the user knows what's going on and emit a short
16087 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16089 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16090 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16091 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16092 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16098 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16101 if (mips_pic
!= NO_PIC
)
16103 /* Additional space for PIC loading of target address. */
16105 if (mips_opts
.isa
== ISA_MIPS1
)
16106 /* Additional space for $at-stabilizing nop. */
16110 /* If branch is conditional. */
16111 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16118 /* Compute the length of a branch sequence, and adjust the
16119 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16120 worst-case length is computed, with UPDATE being used to indicate
16121 whether an unconditional (-1), or regular (0) branch is to be
16125 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16127 bfd_boolean toofar
;
16131 && S_IS_DEFINED (fragp
->fr_symbol
)
16132 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16137 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16138 /* Ignore the low bit in the target, since it will be set
16139 for a text label. */
16140 if ((val
& 1) != 0)
16143 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16147 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16150 /* If the symbol is not defined or it's in a different segment,
16151 assume the user knows what's going on and emit a short
16157 if (fragp
&& update
16158 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16159 fragp
->fr_subtype
= (toofar
16160 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16161 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16166 bfd_boolean compact_known
= fragp
!= NULL
;
16167 bfd_boolean compact
= FALSE
;
16168 bfd_boolean uncond
;
16171 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16173 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16175 uncond
= update
< 0;
16177 /* If label is out of range, we turn branch <br>:
16179 <br> label # 4 bytes
16185 nop # 2 bytes if compact && !PIC
16188 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16191 /* If assembling PIC code, we further turn:
16197 lw/ld at, %got(label)(gp) # 4 bytes
16198 d/addiu at, %lo(label) # 4 bytes
16201 if (mips_pic
!= NO_PIC
)
16204 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16206 <brneg> 0f # 4 bytes
16207 nop # 2 bytes if !compact
16210 length
+= (compact_known
&& compact
) ? 4 : 6;
16216 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16217 bit accordingly. */
16220 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16222 bfd_boolean toofar
;
16225 && S_IS_DEFINED (fragp
->fr_symbol
)
16226 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16232 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16233 /* Ignore the low bit in the target, since it will be set
16234 for a text label. */
16235 if ((val
& 1) != 0)
16238 /* Assume this is a 2-byte branch. */
16239 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16241 /* We try to avoid the infinite loop by not adding 2 more bytes for
16246 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16248 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16249 else if (type
== 'E')
16250 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16255 /* If the symbol is not defined or it's in a different segment,
16256 we emit a normal 32-bit branch. */
16259 if (fragp
&& update
16260 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16262 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16263 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16271 /* Estimate the size of a frag before relaxing. Unless this is the
16272 mips16, we are not really relaxing here, and the final size is
16273 encoded in the subtype information. For the mips16, we have to
16274 decide whether we are using an extended opcode or not. */
16277 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16281 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16284 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16286 return fragp
->fr_var
;
16289 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16290 /* We don't want to modify the EXTENDED bit here; it might get us
16291 into infinite loops. We change it only in mips_relax_frag(). */
16292 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16294 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16298 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16299 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16300 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16301 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16302 fragp
->fr_var
= length
;
16307 if (mips_pic
== NO_PIC
)
16308 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16309 else if (mips_pic
== SVR4_PIC
)
16310 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16311 else if (mips_pic
== VXWORKS_PIC
)
16312 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16319 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16320 return -RELAX_FIRST (fragp
->fr_subtype
);
16323 return -RELAX_SECOND (fragp
->fr_subtype
);
16326 /* This is called to see whether a reloc against a defined symbol
16327 should be converted into a reloc against a section. */
16330 mips_fix_adjustable (fixS
*fixp
)
16332 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16333 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16336 if (fixp
->fx_addsy
== NULL
)
16339 /* If symbol SYM is in a mergeable section, relocations of the form
16340 SYM + 0 can usually be made section-relative. The mergeable data
16341 is then identified by the section offset rather than by the symbol.
16343 However, if we're generating REL LO16 relocations, the offset is split
16344 between the LO16 and parterning high part relocation. The linker will
16345 need to recalculate the complete offset in order to correctly identify
16348 The linker has traditionally not looked for the parterning high part
16349 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16350 placed anywhere. Rather than break backwards compatibility by changing
16351 this, it seems better not to force the issue, and instead keep the
16352 original symbol. This will work with either linker behavior. */
16353 if ((lo16_reloc_p (fixp
->fx_r_type
)
16354 || reloc_needs_lo_p (fixp
->fx_r_type
))
16355 && HAVE_IN_PLACE_ADDENDS
16356 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16359 /* There is no place to store an in-place offset for JALR relocations.
16360 Likewise an in-range offset of limited PC-relative relocations may
16361 overflow the in-place relocatable field if recalculated against the
16362 start address of the symbol's containing section. */
16363 if (HAVE_IN_PLACE_ADDENDS
16364 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16365 || jalr_reloc_p (fixp
->fx_r_type
)))
16368 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16369 to a floating-point stub. The same is true for non-R_MIPS16_26
16370 relocations against MIPS16 functions; in this case, the stub becomes
16371 the function's canonical address.
16373 Floating-point stubs are stored in unique .mips16.call.* or
16374 .mips16.fn.* sections. If a stub T for function F is in section S,
16375 the first relocation in section S must be against F; this is how the
16376 linker determines the target function. All relocations that might
16377 resolve to T must also be against F. We therefore have the following
16378 restrictions, which are given in an intentionally-redundant way:
16380 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16383 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16384 if that stub might be used.
16386 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16389 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16390 that stub might be used.
16392 There is a further restriction:
16394 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16395 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16396 targets with in-place addends; the relocation field cannot
16397 encode the low bit.
16399 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16400 against a MIPS16 symbol. We deal with (5) by by not reducing any
16401 such relocations on REL targets.
16403 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16404 relocation against some symbol R, no relocation against R may be
16405 reduced. (Note that this deals with (2) as well as (1) because
16406 relocations against global symbols will never be reduced on ELF
16407 targets.) This approach is a little simpler than trying to detect
16408 stub sections, and gives the "all or nothing" per-symbol consistency
16409 that we have for MIPS16 symbols. */
16410 if (fixp
->fx_subsy
== NULL
16411 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16412 || *symbol_get_tc (fixp
->fx_addsy
)
16413 || (HAVE_IN_PLACE_ADDENDS
16414 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16415 && jmp_reloc_p (fixp
->fx_r_type
))))
16421 /* Translate internal representation of relocation info to BFD target
16425 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16427 static arelent
*retval
[4];
16429 bfd_reloc_code_real_type code
;
16431 memset (retval
, 0, sizeof(retval
));
16432 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16433 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16434 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16435 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16437 if (fixp
->fx_pcrel
)
16439 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16440 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16441 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16442 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16443 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16445 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16446 Relocations want only the symbol offset. */
16447 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16450 reloc
->addend
= fixp
->fx_addnumber
;
16452 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16453 entry to be used in the relocation's section offset. */
16454 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16456 reloc
->address
= reloc
->addend
;
16460 code
= fixp
->fx_r_type
;
16462 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16463 if (reloc
->howto
== NULL
)
16465 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16466 _("Can not represent %s relocation in this object file format"),
16467 bfd_get_reloc_code_name (code
));
16474 /* Relax a machine dependent frag. This returns the amount by which
16475 the current size of the frag should change. */
16478 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16480 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16482 offsetT old_var
= fragp
->fr_var
;
16484 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16486 return fragp
->fr_var
- old_var
;
16489 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16491 offsetT old_var
= fragp
->fr_var
;
16492 offsetT new_var
= 4;
16494 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16495 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16496 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16497 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16498 fragp
->fr_var
= new_var
;
16500 return new_var
- old_var
;
16503 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16506 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16508 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16510 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16515 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16517 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16524 /* Convert a machine dependent frag. */
16527 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16529 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16532 unsigned long insn
;
16536 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16537 insn
= read_insn (buf
);
16539 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16541 /* We generate a fixup instead of applying it right now
16542 because, if there are linker relaxations, we're going to
16543 need the relocations. */
16544 exp
.X_op
= O_symbol
;
16545 exp
.X_add_symbol
= fragp
->fr_symbol
;
16546 exp
.X_add_number
= fragp
->fr_offset
;
16548 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16549 BFD_RELOC_16_PCREL_S2
);
16550 fixp
->fx_file
= fragp
->fr_file
;
16551 fixp
->fx_line
= fragp
->fr_line
;
16553 buf
= write_insn (buf
, insn
);
16559 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16560 _("Relaxed out-of-range branch into a jump"));
16562 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16565 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16567 /* Reverse the branch. */
16568 switch ((insn
>> 28) & 0xf)
16571 /* bc[0-3][tf]l? instructions can have the condition
16572 reversed by tweaking a single TF bit, and their
16573 opcodes all have 0x4???????. */
16574 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16575 insn
^= 0x00010000;
16579 /* bltz 0x04000000 bgez 0x04010000
16580 bltzal 0x04100000 bgezal 0x04110000 */
16581 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16582 insn
^= 0x00010000;
16586 /* beq 0x10000000 bne 0x14000000
16587 blez 0x18000000 bgtz 0x1c000000 */
16588 insn
^= 0x04000000;
16596 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16598 /* Clear the and-link bit. */
16599 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16601 /* bltzal 0x04100000 bgezal 0x04110000
16602 bltzall 0x04120000 bgezall 0x04130000 */
16603 insn
&= ~0x00100000;
16606 /* Branch over the branch (if the branch was likely) or the
16607 full jump (not likely case). Compute the offset from the
16608 current instruction to branch to. */
16609 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16613 /* How many bytes in instructions we've already emitted? */
16614 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16615 /* How many bytes in instructions from here to the end? */
16616 i
= fragp
->fr_var
- i
;
16618 /* Convert to instruction count. */
16620 /* Branch counts from the next instruction. */
16623 /* Branch over the jump. */
16624 buf
= write_insn (buf
, insn
);
16627 buf
= write_insn (buf
, 0);
16629 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16631 /* beql $0, $0, 2f */
16633 /* Compute the PC offset from the current instruction to
16634 the end of the variable frag. */
16635 /* How many bytes in instructions we've already emitted? */
16636 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16637 /* How many bytes in instructions from here to the end? */
16638 i
= fragp
->fr_var
- i
;
16639 /* Convert to instruction count. */
16641 /* Don't decrement i, because we want to branch over the
16645 buf
= write_insn (buf
, insn
);
16646 buf
= write_insn (buf
, 0);
16650 if (mips_pic
== NO_PIC
)
16653 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16654 ? 0x0c000000 : 0x08000000);
16655 exp
.X_op
= O_symbol
;
16656 exp
.X_add_symbol
= fragp
->fr_symbol
;
16657 exp
.X_add_number
= fragp
->fr_offset
;
16659 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16660 FALSE
, BFD_RELOC_MIPS_JMP
);
16661 fixp
->fx_file
= fragp
->fr_file
;
16662 fixp
->fx_line
= fragp
->fr_line
;
16664 buf
= write_insn (buf
, insn
);
16668 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16670 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16671 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16672 insn
|= at
<< OP_SH_RT
;
16673 exp
.X_op
= O_symbol
;
16674 exp
.X_add_symbol
= fragp
->fr_symbol
;
16675 exp
.X_add_number
= fragp
->fr_offset
;
16677 if (fragp
->fr_offset
)
16679 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16680 exp
.X_add_number
= 0;
16683 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16684 FALSE
, BFD_RELOC_MIPS_GOT16
);
16685 fixp
->fx_file
= fragp
->fr_file
;
16686 fixp
->fx_line
= fragp
->fr_line
;
16688 buf
= write_insn (buf
, insn
);
16690 if (mips_opts
.isa
== ISA_MIPS1
)
16692 buf
= write_insn (buf
, 0);
16694 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16695 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16696 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16698 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16699 FALSE
, BFD_RELOC_LO16
);
16700 fixp
->fx_file
= fragp
->fr_file
;
16701 fixp
->fx_line
= fragp
->fr_line
;
16703 buf
= write_insn (buf
, insn
);
16706 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16710 insn
|= at
<< OP_SH_RS
;
16712 buf
= write_insn (buf
, insn
);
16716 fragp
->fr_fix
+= fragp
->fr_var
;
16717 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16721 /* Relax microMIPS branches. */
16722 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16724 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16725 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16726 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16727 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16728 bfd_boolean short_ds
;
16729 unsigned long insn
;
16733 exp
.X_op
= O_symbol
;
16734 exp
.X_add_symbol
= fragp
->fr_symbol
;
16735 exp
.X_add_number
= fragp
->fr_offset
;
16737 fragp
->fr_fix
+= fragp
->fr_var
;
16739 /* Handle 16-bit branches that fit or are forced to fit. */
16740 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16742 /* We generate a fixup instead of applying it right now,
16743 because if there is linker relaxation, we're going to
16744 need the relocations. */
16746 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16747 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16748 else if (type
== 'E')
16749 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16750 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16754 fixp
->fx_file
= fragp
->fr_file
;
16755 fixp
->fx_line
= fragp
->fr_line
;
16757 /* These relocations can have an addend that won't fit in
16759 fixp
->fx_no_overflow
= 1;
16764 /* Handle 32-bit branches that fit or are forced to fit. */
16765 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16766 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16768 /* We generate a fixup instead of applying it right now,
16769 because if there is linker relaxation, we're going to
16770 need the relocations. */
16771 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16772 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16773 fixp
->fx_file
= fragp
->fr_file
;
16774 fixp
->fx_line
= fragp
->fr_line
;
16780 /* Relax 16-bit branches to 32-bit branches. */
16783 insn
= read_compressed_insn (buf
, 2);
16785 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16786 insn
= 0x94000000; /* beq */
16787 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16789 unsigned long regno
;
16791 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16792 regno
= micromips_to_32_reg_d_map
[regno
];
16793 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16794 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16799 /* Nothing else to do, just write it out. */
16800 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16801 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16803 buf
= write_compressed_insn (buf
, insn
, 4);
16804 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16809 insn
= read_compressed_insn (buf
, 4);
16811 /* Relax 32-bit branches to a sequence of instructions. */
16812 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16813 _("Relaxed out-of-range branch into a jump"));
16815 /* Set the short-delay-slot bit. */
16816 short_ds
= al
&& (insn
& 0x02000000) != 0;
16818 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16822 /* Reverse the branch. */
16823 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16824 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16825 insn
^= 0x20000000;
16826 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16827 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16828 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16829 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16830 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16831 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16832 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16833 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16834 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16835 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16836 insn
^= 0x00400000;
16837 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16838 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16839 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16840 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16841 insn
^= 0x00200000;
16847 /* Clear the and-link and short-delay-slot bits. */
16848 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16850 /* bltzal 0x40200000 bgezal 0x40600000 */
16851 /* bltzals 0x42200000 bgezals 0x42600000 */
16852 insn
&= ~0x02200000;
16855 /* Make a label at the end for use with the branch. */
16856 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16857 micromips_label_inc ();
16858 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16861 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16862 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16863 fixp
->fx_file
= fragp
->fr_file
;
16864 fixp
->fx_line
= fragp
->fr_line
;
16866 /* Branch over the jump. */
16867 buf
= write_compressed_insn (buf
, insn
, 4);
16870 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16873 if (mips_pic
== NO_PIC
)
16875 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16877 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16878 insn
= al
? jal
: 0xd4000000;
16880 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16881 BFD_RELOC_MICROMIPS_JMP
);
16882 fixp
->fx_file
= fragp
->fr_file
;
16883 fixp
->fx_line
= fragp
->fr_line
;
16885 buf
= write_compressed_insn (buf
, insn
, 4);
16888 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16892 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16893 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16894 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16896 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16897 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16898 insn
|= at
<< MICROMIPSOP_SH_RT
;
16900 if (exp
.X_add_number
)
16902 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16903 exp
.X_add_number
= 0;
16906 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16907 BFD_RELOC_MICROMIPS_GOT16
);
16908 fixp
->fx_file
= fragp
->fr_file
;
16909 fixp
->fx_line
= fragp
->fr_line
;
16911 buf
= write_compressed_insn (buf
, insn
, 4);
16913 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16914 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16915 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16917 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16918 BFD_RELOC_MICROMIPS_LO16
);
16919 fixp
->fx_file
= fragp
->fr_file
;
16920 fixp
->fx_line
= fragp
->fr_line
;
16922 buf
= write_compressed_insn (buf
, insn
, 4);
16924 /* jr/jrc/jalr/jalrs $at */
16925 insn
= al
? jalr
: jr
;
16926 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16928 buf
= write_compressed_insn (buf
, insn
, 2);
16931 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16935 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16938 const struct mips_int_operand
*operand
;
16941 unsigned int user_length
, length
;
16942 unsigned long insn
;
16945 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16946 operand
= mips16_immed_operand (type
, FALSE
);
16948 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
16949 val
= resolve_symbol_value (fragp
->fr_symbol
);
16950 if (operand
->root
.type
== OP_PCREL
)
16952 const struct mips_pcrel_operand
*pcrel_op
;
16955 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16956 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16958 /* The rules for the base address of a PC relative reloc are
16959 complicated; see mips16_extended_frag. */
16960 if (pcrel_op
->include_isa_bit
)
16965 /* Ignore the low bit in the target, since it will be
16966 set for a text label. */
16969 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16971 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16974 addr
&= -(1 << pcrel_op
->align_log2
);
16977 /* Make sure the section winds up with the alignment we have
16979 if (operand
->shift
> 0)
16980 record_alignment (asec
, operand
->shift
);
16984 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
16985 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
16986 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16987 _("extended instruction in delay slot"));
16989 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16991 insn
= read_compressed_insn (buf
, 2);
16993 insn
|= MIPS16_EXTEND
;
16995 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16997 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17002 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17003 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17005 length
= (ext
? 4 : 2);
17006 gas_assert (mips16_opcode_length (insn
) == length
);
17007 write_compressed_insn (buf
, insn
, length
);
17008 fragp
->fr_fix
+= length
;
17012 relax_substateT subtype
= fragp
->fr_subtype
;
17013 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17014 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17018 first
= RELAX_FIRST (subtype
);
17019 second
= RELAX_SECOND (subtype
);
17020 fixp
= (fixS
*) fragp
->fr_opcode
;
17022 /* If the delay slot chosen does not match the size of the instruction,
17023 then emit a warning. */
17024 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17025 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17030 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17031 | RELAX_DELAY_SLOT_SIZE_FIRST
17032 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17033 msg
= macro_warning (s
);
17035 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17039 /* Possibly emit a warning if we've chosen the longer option. */
17040 if (use_second
== second_longer
)
17046 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17047 msg
= macro_warning (s
);
17049 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17053 /* Go through all the fixups for the first sequence. Disable them
17054 (by marking them as done) if we're going to use the second
17055 sequence instead. */
17057 && fixp
->fx_frag
== fragp
17058 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17060 if (subtype
& RELAX_USE_SECOND
)
17062 fixp
= fixp
->fx_next
;
17065 /* Go through the fixups for the second sequence. Disable them if
17066 we're going to use the first sequence, otherwise adjust their
17067 addresses to account for the relaxation. */
17068 while (fixp
&& fixp
->fx_frag
== fragp
)
17070 if (subtype
& RELAX_USE_SECOND
)
17071 fixp
->fx_where
-= first
;
17074 fixp
= fixp
->fx_next
;
17077 /* Now modify the frag contents. */
17078 if (subtype
& RELAX_USE_SECOND
)
17082 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17083 memmove (start
, start
+ first
, second
);
17084 fragp
->fr_fix
-= first
;
17087 fragp
->fr_fix
-= second
;
17091 /* This function is called after the relocs have been generated.
17092 We've been storing mips16 text labels as odd. Here we convert them
17093 back to even for the convenience of the debugger. */
17096 mips_frob_file_after_relocs (void)
17099 unsigned int count
, i
;
17101 syms
= bfd_get_outsymbols (stdoutput
);
17102 count
= bfd_get_symcount (stdoutput
);
17103 for (i
= 0; i
< count
; i
++, syms
++)
17104 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17105 && ((*syms
)->value
& 1) != 0)
17107 (*syms
)->value
&= ~1;
17108 /* If the symbol has an odd size, it was probably computed
17109 incorrectly, so adjust that as well. */
17110 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17111 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17115 /* This function is called whenever a label is defined, including fake
17116 labels instantiated off the dot special symbol. It is used when
17117 handling branch delays; if a branch has a label, we assume we cannot
17118 move it. This also bumps the value of the symbol by 1 in compressed
17122 mips_record_label (symbolS
*sym
)
17124 segment_info_type
*si
= seg_info (now_seg
);
17125 struct insn_label_list
*l
;
17127 if (free_insn_labels
== NULL
)
17128 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17131 l
= free_insn_labels
;
17132 free_insn_labels
= l
->next
;
17136 l
->next
= si
->label_list
;
17137 si
->label_list
= l
;
17140 /* This function is called as tc_frob_label() whenever a label is defined
17141 and adds a DWARF-2 record we only want for true labels. */
17144 mips_define_label (symbolS
*sym
)
17146 mips_record_label (sym
);
17147 dwarf2_emit_label (sym
);
17150 /* This function is called by tc_new_dot_label whenever a new dot symbol
17154 mips_add_dot_label (symbolS
*sym
)
17156 mips_record_label (sym
);
17157 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17158 mips_compressed_mark_label (sym
);
17161 /* Some special processing for a MIPS ELF file. */
17164 mips_elf_final_processing (void)
17166 /* Write out the register information. */
17167 if (mips_abi
!= N64_ABI
)
17171 s
.ri_gprmask
= mips_gprmask
;
17172 s
.ri_cprmask
[0] = mips_cprmask
[0];
17173 s
.ri_cprmask
[1] = mips_cprmask
[1];
17174 s
.ri_cprmask
[2] = mips_cprmask
[2];
17175 s
.ri_cprmask
[3] = mips_cprmask
[3];
17176 /* The gp_value field is set by the MIPS ELF backend. */
17178 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17179 ((Elf32_External_RegInfo
*)
17180 mips_regmask_frag
));
17184 Elf64_Internal_RegInfo s
;
17186 s
.ri_gprmask
= mips_gprmask
;
17188 s
.ri_cprmask
[0] = mips_cprmask
[0];
17189 s
.ri_cprmask
[1] = mips_cprmask
[1];
17190 s
.ri_cprmask
[2] = mips_cprmask
[2];
17191 s
.ri_cprmask
[3] = mips_cprmask
[3];
17192 /* The gp_value field is set by the MIPS ELF backend. */
17194 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17195 ((Elf64_External_RegInfo
*)
17196 mips_regmask_frag
));
17199 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17200 sort of BFD interface for this. */
17201 if (mips_any_noreorder
)
17202 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17203 if (mips_pic
!= NO_PIC
)
17205 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17206 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17209 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17211 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17212 defined at present; this might need to change in future. */
17213 if (file_ase_mips16
)
17214 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17215 if (file_ase_micromips
)
17216 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17217 if (file_ase
& ASE_MDMX
)
17218 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17220 /* Set the MIPS ELF ABI flags. */
17221 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17222 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17223 else if (mips_abi
== O64_ABI
)
17224 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17225 else if (mips_abi
== EABI_ABI
)
17227 if (!file_mips_gp32
)
17228 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17230 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17232 else if (mips_abi
== N32_ABI
)
17233 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17235 /* Nothing to do for N64_ABI. */
17237 if (mips_32bitmode
)
17238 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17240 if (mips_flag_nan2008
)
17241 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17243 #if 0 /* XXX FIXME */
17244 /* 32 bit code with 64 bit FP registers. */
17245 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17246 elf_elfheader (stdoutput
)->e_flags
|= ???;
17250 typedef struct proc
{
17252 symbolS
*func_end_sym
;
17253 unsigned long reg_mask
;
17254 unsigned long reg_offset
;
17255 unsigned long fpreg_mask
;
17256 unsigned long fpreg_offset
;
17257 unsigned long frame_offset
;
17258 unsigned long frame_reg
;
17259 unsigned long pc_reg
;
17262 static procS cur_proc
;
17263 static procS
*cur_proc_ptr
;
17264 static int numprocs
;
17266 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17267 as "2", and a normal nop as "0". */
17269 #define NOP_OPCODE_MIPS 0
17270 #define NOP_OPCODE_MIPS16 1
17271 #define NOP_OPCODE_MICROMIPS 2
17274 mips_nop_opcode (void)
17276 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17277 return NOP_OPCODE_MICROMIPS
;
17278 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17279 return NOP_OPCODE_MIPS16
;
17281 return NOP_OPCODE_MIPS
;
17284 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17285 32-bit microMIPS NOPs here (if applicable). */
17288 mips_handle_align (fragS
*fragp
)
17292 int bytes
, size
, excess
;
17295 if (fragp
->fr_type
!= rs_align_code
)
17298 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17300 switch (nop_opcode
)
17302 case NOP_OPCODE_MICROMIPS
:
17303 opcode
= micromips_nop32_insn
.insn_opcode
;
17306 case NOP_OPCODE_MIPS16
:
17307 opcode
= mips16_nop_insn
.insn_opcode
;
17310 case NOP_OPCODE_MIPS
:
17312 opcode
= nop_insn
.insn_opcode
;
17317 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17318 excess
= bytes
% size
;
17320 /* Handle the leading part if we're not inserting a whole number of
17321 instructions, and make it the end of the fixed part of the frag.
17322 Try to fit in a short microMIPS NOP if applicable and possible,
17323 and use zeroes otherwise. */
17324 gas_assert (excess
< 4);
17325 fragp
->fr_fix
+= excess
;
17330 /* Fall through. */
17332 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17334 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17338 /* Fall through. */
17341 /* Fall through. */
17346 md_number_to_chars (p
, opcode
, size
);
17347 fragp
->fr_var
= size
;
17351 md_obj_begin (void)
17358 /* Check for premature end, nesting errors, etc. */
17360 as_warn (_("missing .end at end of assembly"));
17369 if (*input_line_pointer
== '-')
17371 ++input_line_pointer
;
17374 if (!ISDIGIT (*input_line_pointer
))
17375 as_bad (_("expected simple number"));
17376 if (input_line_pointer
[0] == '0')
17378 if (input_line_pointer
[1] == 'x')
17380 input_line_pointer
+= 2;
17381 while (ISXDIGIT (*input_line_pointer
))
17384 val
|= hex_value (*input_line_pointer
++);
17386 return negative
? -val
: val
;
17390 ++input_line_pointer
;
17391 while (ISDIGIT (*input_line_pointer
))
17394 val
|= *input_line_pointer
++ - '0';
17396 return negative
? -val
: val
;
17399 if (!ISDIGIT (*input_line_pointer
))
17401 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17402 *input_line_pointer
, *input_line_pointer
);
17403 as_warn (_("invalid number"));
17406 while (ISDIGIT (*input_line_pointer
))
17409 val
+= *input_line_pointer
++ - '0';
17411 return negative
? -val
: val
;
17414 /* The .file directive; just like the usual .file directive, but there
17415 is an initial number which is the ECOFF file index. In the non-ECOFF
17416 case .file implies DWARF-2. */
17419 s_mips_file (int x ATTRIBUTE_UNUSED
)
17421 static int first_file_directive
= 0;
17423 if (ECOFF_DEBUGGING
)
17432 filename
= dwarf2_directive_file (0);
17434 /* Versions of GCC up to 3.1 start files with a ".file"
17435 directive even for stabs output. Make sure that this
17436 ".file" is handled. Note that you need a version of GCC
17437 after 3.1 in order to support DWARF-2 on MIPS. */
17438 if (filename
!= NULL
&& ! first_file_directive
)
17440 (void) new_logical_line (filename
, -1);
17441 s_app_file_string (filename
, 0);
17443 first_file_directive
= 1;
17447 /* The .loc directive, implying DWARF-2. */
17450 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17452 if (!ECOFF_DEBUGGING
)
17453 dwarf2_directive_loc (0);
17456 /* The .end directive. */
17459 s_mips_end (int x ATTRIBUTE_UNUSED
)
17463 /* Following functions need their own .frame and .cprestore directives. */
17464 mips_frame_reg_valid
= 0;
17465 mips_cprestore_valid
= 0;
17467 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17470 demand_empty_rest_of_line ();
17475 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17476 as_warn (_(".end not in text section"));
17480 as_warn (_(".end directive without a preceding .ent directive."));
17481 demand_empty_rest_of_line ();
17487 gas_assert (S_GET_NAME (p
));
17488 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17489 as_warn (_(".end symbol does not match .ent symbol."));
17491 if (debug_type
== DEBUG_STABS
)
17492 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17496 as_warn (_(".end directive missing or unknown symbol"));
17498 /* Create an expression to calculate the size of the function. */
17499 if (p
&& cur_proc_ptr
)
17501 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17502 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17505 exp
->X_op
= O_subtract
;
17506 exp
->X_add_symbol
= symbol_temp_new_now ();
17507 exp
->X_op_symbol
= p
;
17508 exp
->X_add_number
= 0;
17510 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17513 /* Generate a .pdr section. */
17514 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17516 segT saved_seg
= now_seg
;
17517 subsegT saved_subseg
= now_subseg
;
17521 #ifdef md_flush_pending_output
17522 md_flush_pending_output ();
17525 gas_assert (pdr_seg
);
17526 subseg_set (pdr_seg
, 0);
17528 /* Write the symbol. */
17529 exp
.X_op
= O_symbol
;
17530 exp
.X_add_symbol
= p
;
17531 exp
.X_add_number
= 0;
17532 emit_expr (&exp
, 4);
17534 fragp
= frag_more (7 * 4);
17536 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17537 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17538 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17539 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17540 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17541 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17542 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17544 subseg_set (saved_seg
, saved_subseg
);
17547 cur_proc_ptr
= NULL
;
17550 /* The .aent and .ent directives. */
17553 s_mips_ent (int aent
)
17557 symbolP
= get_symbol ();
17558 if (*input_line_pointer
== ',')
17559 ++input_line_pointer
;
17560 SKIP_WHITESPACE ();
17561 if (ISDIGIT (*input_line_pointer
)
17562 || *input_line_pointer
== '-')
17565 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17566 as_warn (_(".ent or .aent not in text section."));
17568 if (!aent
&& cur_proc_ptr
)
17569 as_warn (_("missing .end"));
17573 /* This function needs its own .frame and .cprestore directives. */
17574 mips_frame_reg_valid
= 0;
17575 mips_cprestore_valid
= 0;
17577 cur_proc_ptr
= &cur_proc
;
17578 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17580 cur_proc_ptr
->func_sym
= symbolP
;
17584 if (debug_type
== DEBUG_STABS
)
17585 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17586 S_GET_NAME (symbolP
));
17589 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17591 demand_empty_rest_of_line ();
17594 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17595 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17596 s_mips_frame is used so that we can set the PDR information correctly.
17597 We can't use the ecoff routines because they make reference to the ecoff
17598 symbol table (in the mdebug section). */
17601 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17603 if (ECOFF_DEBUGGING
)
17609 if (cur_proc_ptr
== (procS
*) NULL
)
17611 as_warn (_(".frame outside of .ent"));
17612 demand_empty_rest_of_line ();
17616 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17618 SKIP_WHITESPACE ();
17619 if (*input_line_pointer
++ != ','
17620 || get_absolute_expression_and_terminator (&val
) != ',')
17622 as_warn (_("Bad .frame directive"));
17623 --input_line_pointer
;
17624 demand_empty_rest_of_line ();
17628 cur_proc_ptr
->frame_offset
= val
;
17629 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17631 demand_empty_rest_of_line ();
17635 /* The .fmask and .mask directives. If the mdebug section is present
17636 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17637 embedded targets, s_mips_mask is used so that we can set the PDR
17638 information correctly. We can't use the ecoff routines because they
17639 make reference to the ecoff symbol table (in the mdebug section). */
17642 s_mips_mask (int reg_type
)
17644 if (ECOFF_DEBUGGING
)
17645 s_ignore (reg_type
);
17650 if (cur_proc_ptr
== (procS
*) NULL
)
17652 as_warn (_(".mask/.fmask outside of .ent"));
17653 demand_empty_rest_of_line ();
17657 if (get_absolute_expression_and_terminator (&mask
) != ',')
17659 as_warn (_("Bad .mask/.fmask directive"));
17660 --input_line_pointer
;
17661 demand_empty_rest_of_line ();
17665 off
= get_absolute_expression ();
17667 if (reg_type
== 'F')
17669 cur_proc_ptr
->fpreg_mask
= mask
;
17670 cur_proc_ptr
->fpreg_offset
= off
;
17674 cur_proc_ptr
->reg_mask
= mask
;
17675 cur_proc_ptr
->reg_offset
= off
;
17678 demand_empty_rest_of_line ();
17682 /* A table describing all the processors gas knows about. Names are
17683 matched in the order listed.
17685 To ease comparison, please keep this table in the same order as
17686 gcc's mips_cpu_info_table[]. */
17687 static const struct mips_cpu_info mips_cpu_info_table
[] =
17689 /* Entries for generic ISAs */
17690 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17691 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17692 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17693 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17694 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17695 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17696 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17697 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17698 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17701 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17702 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17703 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17706 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17709 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17710 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17711 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17712 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17713 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17714 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17715 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17716 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17717 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17718 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17719 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17720 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17721 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17722 /* ST Microelectronics Loongson 2E and 2F cores */
17723 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17724 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17727 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17728 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17729 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17730 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17731 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17732 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17733 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17734 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17735 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17736 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17737 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17738 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17739 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17740 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17741 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17744 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17745 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17746 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17747 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17749 /* MIPS 32 Release 2 */
17750 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17751 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17752 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17753 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17754 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17755 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17756 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17757 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17758 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17759 ISA_MIPS32R2
, CPU_MIPS32R2
},
17760 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17761 ISA_MIPS32R2
, CPU_MIPS32R2
},
17762 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17763 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17764 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17765 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17766 /* Deprecated forms of the above. */
17767 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17768 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17769 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17770 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17771 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17772 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17773 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17774 /* Deprecated forms of the above. */
17775 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17776 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17777 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17778 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17779 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17780 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17781 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17782 /* Deprecated forms of the above. */
17783 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17784 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17785 /* 34Kn is a 34kc without DSP. */
17786 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17787 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17788 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17789 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17790 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17791 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17792 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17793 /* Deprecated forms of the above. */
17794 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17795 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17796 /* 1004K cores are multiprocessor versions of the 34K. */
17797 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17798 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17799 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17800 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17803 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17804 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17805 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17806 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17808 /* Broadcom SB-1 CPU core */
17809 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17810 /* Broadcom SB-1A CPU core */
17811 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17813 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17815 /* MIPS 64 Release 2 */
17817 /* Cavium Networks Octeon CPU core */
17818 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17819 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17820 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17823 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17826 XLP is mostly like XLR, with the prominent exception that it is
17827 MIPS64R2 rather than MIPS64. */
17828 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17831 { NULL
, 0, 0, 0, 0 }
17835 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17836 with a final "000" replaced by "k". Ignore case.
17838 Note: this function is shared between GCC and GAS. */
17841 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17843 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17844 given
++, canonical
++;
17846 return ((*given
== 0 && *canonical
== 0)
17847 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17851 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17852 CPU name. We've traditionally allowed a lot of variation here.
17854 Note: this function is shared between GCC and GAS. */
17857 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17859 /* First see if the name matches exactly, or with a final "000"
17860 turned into "k". */
17861 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17864 /* If not, try comparing based on numerical designation alone.
17865 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17866 if (TOLOWER (*given
) == 'r')
17868 if (!ISDIGIT (*given
))
17871 /* Skip over some well-known prefixes in the canonical name,
17872 hoping to find a number there too. */
17873 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17875 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17877 else if (TOLOWER (canonical
[0]) == 'r')
17880 return mips_strict_matching_cpu_name_p (canonical
, given
);
17884 /* Parse an option that takes the name of a processor as its argument.
17885 OPTION is the name of the option and CPU_STRING is the argument.
17886 Return the corresponding processor enumeration if the CPU_STRING is
17887 recognized, otherwise report an error and return null.
17889 A similar function exists in GCC. */
17891 static const struct mips_cpu_info
*
17892 mips_parse_cpu (const char *option
, const char *cpu_string
)
17894 const struct mips_cpu_info
*p
;
17896 /* 'from-abi' selects the most compatible architecture for the given
17897 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17898 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17899 version. Look first at the -mgp options, if given, otherwise base
17900 the choice on MIPS_DEFAULT_64BIT.
17902 Treat NO_ABI like the EABIs. One reason to do this is that the
17903 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17904 architecture. This code picks MIPS I for 'mips' and MIPS III for
17905 'mips64', just as we did in the days before 'from-abi'. */
17906 if (strcasecmp (cpu_string
, "from-abi") == 0)
17908 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17909 return mips_cpu_info_from_isa (ISA_MIPS1
);
17911 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17912 return mips_cpu_info_from_isa (ISA_MIPS3
);
17914 if (file_mips_gp32
>= 0)
17915 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17917 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17922 /* 'default' has traditionally been a no-op. Probably not very useful. */
17923 if (strcasecmp (cpu_string
, "default") == 0)
17926 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17927 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17930 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
17934 /* Return the canonical processor information for ISA (a member of the
17935 ISA_MIPS* enumeration). */
17937 static const struct mips_cpu_info
*
17938 mips_cpu_info_from_isa (int isa
)
17942 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17943 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
17944 && isa
== mips_cpu_info_table
[i
].isa
)
17945 return (&mips_cpu_info_table
[i
]);
17950 static const struct mips_cpu_info
*
17951 mips_cpu_info_from_arch (int arch
)
17955 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
17956 if (arch
== mips_cpu_info_table
[i
].cpu
)
17957 return (&mips_cpu_info_table
[i
]);
17963 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
17967 fprintf (stream
, "%24s", "");
17972 fprintf (stream
, ", ");
17976 if (*col_p
+ strlen (string
) > 72)
17978 fprintf (stream
, "\n%24s", "");
17982 fprintf (stream
, "%s", string
);
17983 *col_p
+= strlen (string
);
17989 md_show_usage (FILE *stream
)
17994 fprintf (stream
, _("\
17996 -EB generate big endian output\n\
17997 -EL generate little endian output\n\
17998 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17999 -G NUM allow referencing objects up to NUM bytes\n\
18000 implicitly with the gp register [default 8]\n"));
18001 fprintf (stream
, _("\
18002 -mips1 generate MIPS ISA I instructions\n\
18003 -mips2 generate MIPS ISA II instructions\n\
18004 -mips3 generate MIPS ISA III instructions\n\
18005 -mips4 generate MIPS ISA IV instructions\n\
18006 -mips5 generate MIPS ISA V instructions\n\
18007 -mips32 generate MIPS32 ISA instructions\n\
18008 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18009 -mips64 generate MIPS64 ISA instructions\n\
18010 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18011 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18015 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18016 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18017 show (stream
, "from-abi", &column
, &first
);
18018 fputc ('\n', stream
);
18020 fprintf (stream
, _("\
18021 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18022 -no-mCPU don't generate code specific to CPU.\n\
18023 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18027 show (stream
, "3900", &column
, &first
);
18028 show (stream
, "4010", &column
, &first
);
18029 show (stream
, "4100", &column
, &first
);
18030 show (stream
, "4650", &column
, &first
);
18031 fputc ('\n', stream
);
18033 fprintf (stream
, _("\
18034 -mips16 generate mips16 instructions\n\
18035 -no-mips16 do not generate mips16 instructions\n"));
18036 fprintf (stream
, _("\
18037 -mmicromips generate microMIPS instructions\n\
18038 -mno-micromips do not generate microMIPS instructions\n"));
18039 fprintf (stream
, _("\
18040 -msmartmips generate smartmips instructions\n\
18041 -mno-smartmips do not generate smartmips instructions\n"));
18042 fprintf (stream
, _("\
18043 -mdsp generate DSP instructions\n\
18044 -mno-dsp do not generate DSP instructions\n"));
18045 fprintf (stream
, _("\
18046 -mdspr2 generate DSP R2 instructions\n\
18047 -mno-dspr2 do not generate DSP R2 instructions\n"));
18048 fprintf (stream
, _("\
18049 -mmt generate MT instructions\n\
18050 -mno-mt do not generate MT instructions\n"));
18051 fprintf (stream
, _("\
18052 -mmcu generate MCU instructions\n\
18053 -mno-mcu do not generate MCU instructions\n"));
18054 fprintf (stream
, _("\
18055 -mvirt generate Virtualization instructions\n\
18056 -mno-virt do not generate Virtualization instructions\n"));
18057 fprintf (stream
, _("\
18058 -minsn32 only generate 32-bit microMIPS instructions\n\
18059 -mno-insn32 generate all microMIPS instructions\n"));
18060 fprintf (stream
, _("\
18061 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18062 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18063 -mfix-vr4120 work around certain VR4120 errata\n\
18064 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18065 -mfix-24k insert a nop after ERET and DERET instructions\n\
18066 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18067 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18068 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18069 -msym32 assume all symbols have 32-bit values\n\
18070 -O0 remove unneeded NOPs, do not swap branches\n\
18071 -O remove unneeded NOPs and swap branches\n\
18072 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18073 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18074 fprintf (stream
, _("\
18075 -mhard-float allow floating-point instructions\n\
18076 -msoft-float do not allow floating-point instructions\n\
18077 -msingle-float only allow 32-bit floating-point operations\n\
18078 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18079 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18080 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18081 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18085 show (stream
, "legacy", &column
, &first
);
18086 show (stream
, "2008", &column
, &first
);
18088 fputc ('\n', stream
);
18090 fprintf (stream
, _("\
18091 -KPIC, -call_shared generate SVR4 position independent code\n\
18092 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18093 -mvxworks-pic generate VxWorks position independent code\n\
18094 -non_shared do not generate code that can operate with DSOs\n\
18095 -xgot assume a 32 bit GOT\n\
18096 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18097 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18098 position dependent (non shared) code\n\
18099 -mabi=ABI create ABI conformant object file for:\n"));
18103 show (stream
, "32", &column
, &first
);
18104 show (stream
, "o64", &column
, &first
);
18105 show (stream
, "n32", &column
, &first
);
18106 show (stream
, "64", &column
, &first
);
18107 show (stream
, "eabi", &column
, &first
);
18109 fputc ('\n', stream
);
18111 fprintf (stream
, _("\
18112 -32 create o32 ABI object file (default)\n\
18113 -n32 create n32 ABI object file\n\
18114 -64 create 64 ABI object file\n"));
18119 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18121 if (HAVE_64BIT_SYMBOLS
)
18122 return dwarf2_format_64bit_irix
;
18124 return dwarf2_format_32bit
;
18129 mips_dwarf2_addr_size (void)
18131 if (HAVE_64BIT_OBJECTS
)
18137 /* Standard calling conventions leave the CFA at SP on entry. */
18139 mips_cfi_frame_initial_instructions (void)
18141 cfi_add_CFA_def_cfa_register (SP
);
18145 tc_mips_regname_to_dw2regnum (char *regname
)
18147 unsigned int regnum
= -1;
18150 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))