1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p
: 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi
= NO_ABI
;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls
= FALSE
;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared
= TRUE
;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros
;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float
;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float
;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32
= -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32
= -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float
= 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float
= 0;
292 static struct mips_set_options mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
299 /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
300 /* soft_float */ FALSE
, /* single_float */ FALSE
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* MIPS ISA we are using for this output file. */
310 static int file_mips_isa
= ISA_UNKNOWN
;
312 /* True if any MIPS16 code was produced. */
313 static int file_ase_mips16
;
315 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
316 || mips_opts.isa == ISA_MIPS32R2 \
317 || mips_opts.isa == ISA_MIPS64 \
318 || mips_opts.isa == ISA_MIPS64R2)
320 /* True if any microMIPS code was produced. */
321 static int file_ase_micromips
;
323 /* True if we want to create R_MIPS_JALR for jalr $25. */
325 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
327 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
328 because there's no place for any addend, the only acceptable
329 expression is a bare symbol. */
330 #define MIPS_JALR_HINT_P(EXPR) \
331 (!HAVE_IN_PLACE_ADDENDS \
332 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
335 /* True if -mips3d was passed or implied by arguments passed on the
336 command line (e.g., by -march). */
337 static int file_ase_mips3d
;
339 /* True if -mdmx was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mdmx
;
343 /* True if -msmartmips was passed or implied by arguments passed on the
344 command line (e.g., by -march). */
345 static int file_ase_smartmips
;
347 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
348 || mips_opts.isa == ISA_MIPS32R2)
350 /* True if -mdsp was passed or implied by arguments passed on the
351 command line (e.g., by -march). */
352 static int file_ase_dsp
;
354 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
355 || mips_opts.isa == ISA_MIPS64R2 \
356 || mips_opts.micromips)
358 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
360 /* True if -mdspr2 was passed or implied by arguments passed on the
361 command line (e.g., by -march). */
362 static int file_ase_dspr2
;
364 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
365 || mips_opts.isa == ISA_MIPS64R2 \
366 || mips_opts.micromips)
368 /* True if -mmt was passed or implied by arguments passed on the
369 command line (e.g., by -march). */
370 static int file_ase_mt
;
372 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
376 || mips_opts.isa == ISA_MIPS64R2 \
377 || mips_opts.micromips)
379 /* True if -mvirt was passed or implied by arguments passed on the
380 command line (e.g., by -march). */
381 static int file_ase_virt
;
383 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
384 || mips_opts.isa == ISA_MIPS64R2)
386 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2)
388 /* The argument of the -march= flag. The architecture we are assembling. */
389 static int file_mips_arch
= CPU_UNKNOWN
;
390 static const char *mips_arch_string
;
392 /* The argument of the -mtune= flag. The architecture for which we
394 static int mips_tune
= CPU_UNKNOWN
;
395 static const char *mips_tune_string
;
397 /* True when generating 32-bit code for a 64-bit processor. */
398 static int mips_32bitmode
= 0;
400 /* True if the given ABI requires 32-bit registers. */
401 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
403 /* Likewise 64-bit registers. */
404 #define ABI_NEEDS_64BIT_REGS(ABI) \
406 || (ABI) == N64_ABI \
409 /* Return true if ISA supports 64 bit wide gp registers. */
410 #define ISA_HAS_64BIT_REGS(ISA) \
411 ((ISA) == ISA_MIPS3 \
412 || (ISA) == ISA_MIPS4 \
413 || (ISA) == ISA_MIPS5 \
414 || (ISA) == ISA_MIPS64 \
415 || (ISA) == ISA_MIPS64R2)
417 /* Return true if ISA supports 64 bit wide float registers. */
418 #define ISA_HAS_64BIT_FPRS(ISA) \
419 ((ISA) == ISA_MIPS3 \
420 || (ISA) == ISA_MIPS4 \
421 || (ISA) == ISA_MIPS5 \
422 || (ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64 \
424 || (ISA) == ISA_MIPS64R2)
426 /* Return true if ISA supports 64-bit right rotate (dror et al.)
428 #define ISA_HAS_DROR(ISA) \
429 ((ISA) == ISA_MIPS64R2 \
430 || (mips_opts.micromips \
431 && ISA_HAS_64BIT_REGS (ISA)) \
434 /* Return true if ISA supports 32-bit right rotate (ror et al.)
436 #define ISA_HAS_ROR(ISA) \
437 ((ISA) == ISA_MIPS32R2 \
438 || (ISA) == ISA_MIPS64R2 \
439 || mips_opts.ase_smartmips \
440 || mips_opts.micromips \
443 /* Return true if ISA supports single-precision floats in odd registers. */
444 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
445 ((ISA) == ISA_MIPS32 \
446 || (ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS64 \
448 || (ISA) == ISA_MIPS64R2)
450 /* Return true if ISA supports move to/from high part of a 64-bit
451 floating-point register. */
452 #define ISA_HAS_MXHC1(ISA) \
453 ((ISA) == ISA_MIPS32R2 \
454 || (ISA) == ISA_MIPS64R2)
456 #define HAVE_32BIT_GPRS \
457 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
459 #define HAVE_32BIT_FPRS \
460 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
462 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
463 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
515 /* True if CPU has seq/sne and seqi/snei instructions. */
516 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
518 /* True, if CPU has support for ldc1 and sdc1. */
519 #define CPU_HAS_LDC1_SDC1(CPU) \
520 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
522 /* True if mflo and mfhi can be immediately followed by instructions
523 which write to the HI and LO registers.
525 According to MIPS specifications, MIPS ISAs I, II, and III need
526 (at least) two instructions between the reads of HI/LO and
527 instructions which write them, and later ISAs do not. Contradicting
528 the MIPS specifications, some MIPS IV processor user manuals (e.g.
529 the UM for the NEC Vr5000) document needing the instructions between
530 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
531 MIPS64 and later ISAs to have the interlocks, plus any specific
532 earlier-ISA CPUs for which CPU documentation declares that the
533 instructions are really interlocked. */
534 #define hilo_interlocks \
535 (mips_opts.isa == ISA_MIPS32 \
536 || mips_opts.isa == ISA_MIPS32R2 \
537 || mips_opts.isa == ISA_MIPS64 \
538 || mips_opts.isa == ISA_MIPS64R2 \
539 || mips_opts.arch == CPU_R4010 \
540 || mips_opts.arch == CPU_R5900 \
541 || mips_opts.arch == CPU_R10000 \
542 || mips_opts.arch == CPU_R12000 \
543 || mips_opts.arch == CPU_R14000 \
544 || mips_opts.arch == CPU_R16000 \
545 || mips_opts.arch == CPU_RM7000 \
546 || mips_opts.arch == CPU_VR5500 \
547 || mips_opts.micromips \
550 /* Whether the processor uses hardware interlocks to protect reads
551 from the GPRs after they are loaded from memory, and thus does not
552 require nops to be inserted. This applies to instructions marked
553 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
554 level I and microMIPS mode instructions are always interlocked. */
555 #define gpr_interlocks \
556 (mips_opts.isa != ISA_MIPS1 \
557 || mips_opts.arch == CPU_R3900 \
558 || mips_opts.arch == CPU_R5900 \
559 || mips_opts.micromips \
562 /* Whether the processor uses hardware interlocks to avoid delays
563 required by coprocessor instructions, and thus does not require
564 nops to be inserted. This applies to instructions marked
565 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
566 between instructions marked INSN_WRITE_COND_CODE and ones marked
567 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
568 levels I, II, and III and microMIPS mode instructions are always
570 /* Itbl support may require additional care here. */
571 #define cop_interlocks \
572 ((mips_opts.isa != ISA_MIPS1 \
573 && mips_opts.isa != ISA_MIPS2 \
574 && mips_opts.isa != ISA_MIPS3) \
575 || mips_opts.arch == CPU_R4300 \
576 || mips_opts.micromips \
579 /* Whether the processor uses hardware interlocks to protect reads
580 from coprocessor registers after they are loaded from memory, and
581 thus does not require nops to be inserted. This applies to
582 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
583 requires at MIPS ISA level I and microMIPS mode instructions are
584 always interlocked. */
585 #define cop_mem_interlocks \
586 (mips_opts.isa != ISA_MIPS1 \
587 || mips_opts.micromips \
590 /* Is this a mfhi or mflo instruction? */
591 #define MF_HILO_INSN(PINFO) \
592 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
594 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
595 has been selected. This implies, in particular, that addresses of text
596 labels have their LSB set. */
597 #define HAVE_CODE_COMPRESSION \
598 ((mips_opts.mips16 | mips_opts.micromips) != 0)
600 /* MIPS PIC level. */
602 enum mips_pic_level mips_pic
;
604 /* 1 if we should generate 32 bit offsets from the $gp register in
605 SVR4_PIC mode. Currently has no meaning in other modes. */
606 static int mips_big_got
= 0;
608 /* 1 if trap instructions should used for overflow rather than break
610 static int mips_trap
= 0;
612 /* 1 if double width floating point constants should not be constructed
613 by assembling two single width halves into two single width floating
614 point registers which just happen to alias the double width destination
615 register. On some architectures this aliasing can be disabled by a bit
616 in the status register, and the setting of this bit cannot be determined
617 automatically at assemble time. */
618 static int mips_disable_float_construction
;
620 /* Non-zero if any .set noreorder directives were used. */
622 static int mips_any_noreorder
;
624 /* Non-zero if nops should be inserted when the register referenced in
625 an mfhi/mflo instruction is read in the next two instructions. */
626 static int mips_7000_hilo_fix
;
628 /* The size of objects in the small data section. */
629 static unsigned int g_switch_value
= 8;
630 /* Whether the -G option was used. */
631 static int g_switch_seen
= 0;
636 /* If we can determine in advance that GP optimization won't be
637 possible, we can skip the relaxation stuff that tries to produce
638 GP-relative references. This makes delay slot optimization work
641 This function can only provide a guess, but it seems to work for
642 gcc output. It needs to guess right for gcc, otherwise gcc
643 will put what it thinks is a GP-relative instruction in a branch
646 I don't know if a fix is needed for the SVR4_PIC mode. I've only
647 fixed it for the non-PIC mode. KR 95/04/07 */
648 static int nopic_need_relax (symbolS
*, int);
650 /* handle of the OPCODE hash table */
651 static struct hash_control
*op_hash
= NULL
;
653 /* The opcode hash table we use for the mips16. */
654 static struct hash_control
*mips16_op_hash
= NULL
;
656 /* The opcode hash table we use for the microMIPS ASE. */
657 static struct hash_control
*micromips_op_hash
= NULL
;
659 /* This array holds the chars that always start a comment. If the
660 pre-processor is disabled, these aren't very useful */
661 const char comment_chars
[] = "#";
663 /* This array holds the chars that only start a comment at the beginning of
664 a line. If the line seems to have the form '# 123 filename'
665 .line and .file directives will appear in the pre-processed output */
666 /* Note that input_file.c hand checks for '#' at the beginning of the
667 first line of the input file. This is because the compiler outputs
668 #NO_APP at the beginning of its output. */
669 /* Also note that C style comments are always supported. */
670 const char line_comment_chars
[] = "#";
672 /* This array holds machine specific line separator characters. */
673 const char line_separator_chars
[] = ";";
675 /* Chars that can be used to separate mant from exp in floating point nums */
676 const char EXP_CHARS
[] = "eE";
678 /* Chars that mean this number is a floating point constant */
681 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
683 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
684 changed in read.c . Ideally it shouldn't have to know about it at all,
685 but nothing is ideal around here.
688 static char *insn_error
;
690 static int auto_align
= 1;
692 /* When outputting SVR4 PIC code, the assembler needs to know the
693 offset in the stack frame from which to restore the $gp register.
694 This is set by the .cprestore pseudo-op, and saved in this
696 static offsetT mips_cprestore_offset
= -1;
698 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
699 more optimizations, it can use a register value instead of a memory-saved
700 offset and even an other register than $gp as global pointer. */
701 static offsetT mips_cpreturn_offset
= -1;
702 static int mips_cpreturn_register
= -1;
703 static int mips_gp_register
= GP
;
704 static int mips_gprel_offset
= 0;
706 /* Whether mips_cprestore_offset has been set in the current function
707 (or whether it has already been warned about, if not). */
708 static int mips_cprestore_valid
= 0;
710 /* This is the register which holds the stack frame, as set by the
711 .frame pseudo-op. This is needed to implement .cprestore. */
712 static int mips_frame_reg
= SP
;
714 /* Whether mips_frame_reg has been set in the current function
715 (or whether it has already been warned about, if not). */
716 static int mips_frame_reg_valid
= 0;
718 /* To output NOP instructions correctly, we need to keep information
719 about the previous two instructions. */
721 /* Whether we are optimizing. The default value of 2 means to remove
722 unneeded NOPs and swap branch instructions when possible. A value
723 of 1 means to not swap branches. A value of 0 means to always
725 static int mips_optimize
= 2;
727 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
728 equivalent to seeing no -g option at all. */
729 static int mips_debug
= 0;
731 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
732 #define MAX_VR4130_NOPS 4
734 /* The maximum number of NOPs needed to fill delay slots. */
735 #define MAX_DELAY_NOPS 2
737 /* The maximum number of NOPs needed for any purpose. */
740 /* A list of previous instructions, with index 0 being the most recent.
741 We need to look back MAX_NOPS instructions when filling delay slots
742 or working around processor errata. We need to look back one
743 instruction further if we're thinking about using history[0] to
744 fill a branch delay slot. */
745 static struct mips_cl_insn history
[1 + MAX_NOPS
];
747 /* Nop instructions used by emit_nop. */
748 static struct mips_cl_insn nop_insn
;
749 static struct mips_cl_insn mips16_nop_insn
;
750 static struct mips_cl_insn micromips_nop16_insn
;
751 static struct mips_cl_insn micromips_nop32_insn
;
753 /* The appropriate nop for the current mode. */
754 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
755 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
757 /* The size of NOP_INSN in bytes. */
758 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
760 /* If this is set, it points to a frag holding nop instructions which
761 were inserted before the start of a noreorder section. If those
762 nops turn out to be unnecessary, the size of the frag can be
764 static fragS
*prev_nop_frag
;
766 /* The number of nop instructions we created in prev_nop_frag. */
767 static int prev_nop_frag_holds
;
769 /* The number of nop instructions that we know we need in
771 static int prev_nop_frag_required
;
773 /* The number of instructions we've seen since prev_nop_frag. */
774 static int prev_nop_frag_since
;
776 /* For ECOFF and ELF, relocations against symbols are done in two
777 parts, with a HI relocation and a LO relocation. Each relocation
778 has only 16 bits of space to store an addend. This means that in
779 order for the linker to handle carries correctly, it must be able
780 to locate both the HI and the LO relocation. This means that the
781 relocations must appear in order in the relocation table.
783 In order to implement this, we keep track of each unmatched HI
784 relocation. We then sort them so that they immediately precede the
785 corresponding LO relocation. */
790 struct mips_hi_fixup
*next
;
793 /* The section this fixup is in. */
797 /* The list of unmatched HI relocs. */
799 static struct mips_hi_fixup
*mips_hi_fixup_list
;
801 /* The frag containing the last explicit relocation operator.
802 Null if explicit relocations have not been used. */
804 static fragS
*prev_reloc_op_frag
;
806 /* Map normal MIPS register numbers to mips16 register numbers. */
808 #define X ILLEGAL_REG
809 static const int mips32_to_16_reg_map
[] =
811 X
, X
, 2, 3, 4, 5, 6, 7,
812 X
, X
, X
, X
, X
, X
, X
, X
,
813 0, 1, X
, X
, X
, X
, X
, X
,
814 X
, X
, X
, X
, X
, X
, X
, X
818 /* Map mips16 register numbers to normal MIPS register numbers. */
820 static const unsigned int mips16_to_32_reg_map
[] =
822 16, 17, 2, 3, 4, 5, 6, 7
825 /* Map normal MIPS register numbers to microMIPS register numbers. */
827 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
828 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
829 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
830 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
831 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
832 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
833 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
835 #define X ILLEGAL_REG
836 /* reg type h: 4, 5, 6. */
837 static const int mips32_to_micromips_reg_h_map
[] =
839 X
, X
, X
, X
, 4, 5, 6, X
,
840 X
, X
, X
, X
, X
, X
, X
, X
,
841 X
, X
, X
, X
, X
, X
, X
, X
,
842 X
, X
, X
, X
, X
, X
, X
, X
845 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
846 static const int mips32_to_micromips_reg_m_map
[] =
848 0, X
, 2, 3, X
, X
, X
, X
,
849 X
, X
, X
, X
, X
, X
, X
, X
,
850 4, 1, 5, 6, 7, X
, X
, X
,
851 X
, X
, X
, X
, X
, X
, X
, X
854 /* reg type q: 0, 2-7. 17. */
855 static const int mips32_to_micromips_reg_q_map
[] =
857 0, X
, 2, 3, 4, 5, 6, 7,
858 X
, X
, X
, X
, X
, X
, X
, X
,
859 X
, 1, X
, X
, X
, X
, X
, X
,
860 X
, X
, X
, X
, X
, X
, X
, X
863 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
866 /* Map microMIPS register numbers to normal MIPS register numbers. */
868 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
869 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
870 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
871 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
872 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
873 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
875 /* The microMIPS registers with type h. */
876 static const unsigned int micromips_to_32_reg_h_map
[] =
878 5, 5, 6, 4, 4, 4, 4, 4
881 /* The microMIPS registers with type i. */
882 static const unsigned int micromips_to_32_reg_i_map
[] =
884 6, 7, 7, 21, 22, 5, 6, 7
887 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
889 /* The microMIPS registers with type m. */
890 static const unsigned int micromips_to_32_reg_m_map
[] =
892 0, 17, 2, 3, 16, 18, 19, 20
895 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
897 /* The microMIPS registers with type q. */
898 static const unsigned int micromips_to_32_reg_q_map
[] =
900 0, 17, 2, 3, 4, 5, 6, 7
903 /* microMIPS imm type B. */
904 static const int micromips_imm_b_map
[] =
906 1, 4, 8, 12, 16, 20, 24, -1
909 /* microMIPS imm type C. */
910 static const int micromips_imm_c_map
[] =
912 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
915 /* Classifies the kind of instructions we're interested in when
916 implementing -mfix-vr4120. */
917 enum fix_vr4120_class
925 NUM_FIX_VR4120_CLASSES
928 /* ...likewise -mfix-loongson2f-jump. */
929 static bfd_boolean mips_fix_loongson2f_jump
;
931 /* ...likewise -mfix-loongson2f-nop. */
932 static bfd_boolean mips_fix_loongson2f_nop
;
934 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
935 static bfd_boolean mips_fix_loongson2f
;
937 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
938 there must be at least one other instruction between an instruction
939 of type X and an instruction of type Y. */
940 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
942 /* True if -mfix-vr4120 is in force. */
943 static int mips_fix_vr4120
;
945 /* ...likewise -mfix-vr4130. */
946 static int mips_fix_vr4130
;
948 /* ...likewise -mfix-24k. */
949 static int mips_fix_24k
;
951 /* ...likewise -mfix-cn63xxp1 */
952 static bfd_boolean mips_fix_cn63xxp1
;
954 /* We don't relax branches by default, since this causes us to expand
955 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
956 fail to compute the offset before expanding the macro to the most
957 efficient expansion. */
959 static int mips_relax_branch
;
961 /* The expansion of many macros depends on the type of symbol that
962 they refer to. For example, when generating position-dependent code,
963 a macro that refers to a symbol may have two different expansions,
964 one which uses GP-relative addresses and one which uses absolute
965 addresses. When generating SVR4-style PIC, a macro may have
966 different expansions for local and global symbols.
968 We handle these situations by generating both sequences and putting
969 them in variant frags. In position-dependent code, the first sequence
970 will be the GP-relative one and the second sequence will be the
971 absolute one. In SVR4 PIC, the first sequence will be for global
972 symbols and the second will be for local symbols.
974 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
975 SECOND are the lengths of the two sequences in bytes. These fields
976 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
977 the subtype has the following flags:
980 Set if it has been decided that we should use the second
981 sequence instead of the first.
984 Set in the first variant frag if the macro's second implementation
985 is longer than its first. This refers to the macro as a whole,
986 not an individual relaxation.
989 Set in the first variant frag if the macro appeared in a .set nomacro
990 block and if one alternative requires a warning but the other does not.
993 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
996 RELAX_DELAY_SLOT_16BIT
997 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1000 RELAX_DELAY_SLOT_SIZE_FIRST
1001 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1002 the macro is of the wrong size for the branch delay slot.
1004 RELAX_DELAY_SLOT_SIZE_SECOND
1005 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1006 the macro is of the wrong size for the branch delay slot.
1008 The frag's "opcode" points to the first fixup for relaxable code.
1010 Relaxable macros are generated using a sequence such as:
1012 relax_start (SYMBOL);
1013 ... generate first expansion ...
1015 ... generate second expansion ...
1018 The code and fixups for the unwanted alternative are discarded
1019 by md_convert_frag. */
1020 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1022 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1023 #define RELAX_SECOND(X) ((X) & 0xff)
1024 #define RELAX_USE_SECOND 0x10000
1025 #define RELAX_SECOND_LONGER 0x20000
1026 #define RELAX_NOMACRO 0x40000
1027 #define RELAX_DELAY_SLOT 0x80000
1028 #define RELAX_DELAY_SLOT_16BIT 0x100000
1029 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1030 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1032 /* Branch without likely bit. If label is out of range, we turn:
1034 beq reg1, reg2, label
1044 with the following opcode replacements:
1051 bltzal <-> bgezal (with jal label instead of j label)
1053 Even though keeping the delay slot instruction in the delay slot of
1054 the branch would be more efficient, it would be very tricky to do
1055 correctly, because we'd have to introduce a variable frag *after*
1056 the delay slot instruction, and expand that instead. Let's do it
1057 the easy way for now, even if the branch-not-taken case now costs
1058 one additional instruction. Out-of-range branches are not supposed
1059 to be common, anyway.
1061 Branch likely. If label is out of range, we turn:
1063 beql reg1, reg2, label
1064 delay slot (annulled if branch not taken)
1073 delay slot (executed only if branch taken)
1076 It would be possible to generate a shorter sequence by losing the
1077 likely bit, generating something like:
1082 delay slot (executed only if branch taken)
1094 bltzall -> bgezal (with jal label instead of j label)
1095 bgezall -> bltzal (ditto)
1098 but it's not clear that it would actually improve performance. */
1099 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1100 ((relax_substateT) \
1103 | ((toofar) ? 0x20 : 0) \
1104 | ((link) ? 0x40 : 0) \
1105 | ((likely) ? 0x80 : 0) \
1106 | ((uncond) ? 0x100 : 0)))
1107 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1108 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1109 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1110 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1111 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1112 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1114 /* For mips16 code, we use an entirely different form of relaxation.
1115 mips16 supports two versions of most instructions which take
1116 immediate values: a small one which takes some small value, and a
1117 larger one which takes a 16 bit value. Since branches also follow
1118 this pattern, relaxing these values is required.
1120 We can assemble both mips16 and normal MIPS code in a single
1121 object. Therefore, we need to support this type of relaxation at
1122 the same time that we support the relaxation described above. We
1123 use the high bit of the subtype field to distinguish these cases.
1125 The information we store for this type of relaxation is the
1126 argument code found in the opcode file for this relocation, whether
1127 the user explicitly requested a small or extended form, and whether
1128 the relocation is in a jump or jal delay slot. That tells us the
1129 size of the value, and how it should be stored. We also store
1130 whether the fragment is considered to be extended or not. We also
1131 store whether this is known to be a branch to a different section,
1132 whether we have tried to relax this frag yet, and whether we have
1133 ever extended a PC relative fragment because of a shift count. */
1134 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1137 | ((small) ? 0x100 : 0) \
1138 | ((ext) ? 0x200 : 0) \
1139 | ((dslot) ? 0x400 : 0) \
1140 | ((jal_dslot) ? 0x800 : 0))
1141 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1142 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1143 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1144 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1145 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1146 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1147 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1148 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1149 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1150 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1151 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1152 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1154 /* For microMIPS code, we use relaxation similar to one we use for
1155 MIPS16 code. Some instructions that take immediate values support
1156 two encodings: a small one which takes some small value, and a
1157 larger one which takes a 16 bit value. As some branches also follow
1158 this pattern, relaxing these values is required.
1160 We can assemble both microMIPS and normal MIPS code in a single
1161 object. Therefore, we need to support this type of relaxation at
1162 the same time that we support the relaxation described above. We
1163 use one of the high bits of the subtype field to distinguish these
1166 The information we store for this type of relaxation is the argument
1167 code found in the opcode file for this relocation, the register
1168 selected as the assembler temporary, whether the branch is
1169 unconditional, whether it is compact, whether it stores the link
1170 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1171 branches to a sequence of instructions is enabled, and whether the
1172 displacement of a branch is too large to fit as an immediate argument
1173 of a 16-bit and a 32-bit branch, respectively. */
1174 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1175 relax32, toofar16, toofar32) \
1178 | (((at) & 0x1f) << 8) \
1179 | ((uncond) ? 0x2000 : 0) \
1180 | ((compact) ? 0x4000 : 0) \
1181 | ((link) ? 0x8000 : 0) \
1182 | ((relax32) ? 0x10000 : 0) \
1183 | ((toofar16) ? 0x20000 : 0) \
1184 | ((toofar32) ? 0x40000 : 0))
1185 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1186 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1187 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1188 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1189 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1190 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1191 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1193 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1195 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1196 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1198 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1200 /* Sign-extend 16-bit value X. */
1201 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1203 /* Is the given value a sign-extended 32-bit value? */
1204 #define IS_SEXT_32BIT_NUM(x) \
1205 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1206 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1208 /* Is the given value a sign-extended 16-bit value? */
1209 #define IS_SEXT_16BIT_NUM(x) \
1210 (((x) &~ (offsetT) 0x7fff) == 0 \
1211 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1213 /* Is the given value a sign-extended 12-bit value? */
1214 #define IS_SEXT_12BIT_NUM(x) \
1215 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1217 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1218 #define IS_ZEXT_32BIT_NUM(x) \
1219 (((x) &~ (offsetT) 0xffffffff) == 0 \
1220 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1222 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1223 VALUE << SHIFT. VALUE is evaluated exactly once. */
1224 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1225 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1226 | (((VALUE) & (MASK)) << (SHIFT)))
1228 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1230 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1231 (((STRUCT) >> (SHIFT)) & (MASK))
1233 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1234 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1236 include/opcode/mips.h specifies operand fields using the macros
1237 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1238 with "MIPS16OP" instead of "OP". */
1239 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1242 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1243 OP_MASK_##FIELD, OP_SH_##FIELD); \
1245 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1248 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1249 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1250 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes
[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p
;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length
;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes
[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes
[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns
[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning
;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1330 static void append_insn
1331 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1332 bfd_boolean expansionp
);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS
*, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS
*, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS
*, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn
* ip
);
1341 static void mips16_macro (struct mips_cl_insn
* ip
);
1342 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1343 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1344 static void mips16_immed
1345 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1349 static void my_getExpression (expressionS
*, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_cpadd (int);
1372 static void s_insn (int);
1373 static void md_obj_begin (void);
1374 static void md_obj_end (void);
1375 static void s_mips_ent (int);
1376 static void s_mips_end (int);
1377 static void s_mips_frame (int);
1378 static void s_mips_mask (int reg_type
);
1379 static void s_mips_stab (int);
1380 static void s_mips_weakext (int);
1381 static void s_mips_file (int);
1382 static void s_mips_loc (int);
1383 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1384 static int relaxed_branch_length (fragS
*, asection
*, int);
1385 static int validate_mips_insn (const struct mips_opcode
*);
1386 static int validate_micromips_insn (const struct mips_opcode
*);
1387 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1388 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name
; /* CPU or ISA name. */
1396 int flags
; /* ASEs available, or ISA flag. */
1397 int isa
; /* ISA level. */
1398 int cpu
; /* CPU number (default CPU if ISA). */
1401 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1402 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1403 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1404 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1405 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1406 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1407 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1408 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1409 #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
1411 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1412 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1413 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1417 The following pseudo-ops from the Kane and Heinrich MIPS book
1418 should be defined here, but are currently unsupported: .alias,
1419 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1421 The following pseudo-ops from the Kane and Heinrich MIPS book are
1422 specific to the type of debugging information being generated, and
1423 should be defined by the object format: .aent, .begin, .bend,
1424 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1427 The following pseudo-ops from the Kane and Heinrich MIPS book are
1428 not MIPS CPU specific, but are also not specific to the object file
1429 format. This file is probably the best place to define them, but
1430 they are not currently supported: .asm0, .endr, .lab, .struct. */
1432 static const pseudo_typeS mips_pseudo_table
[] =
1434 /* MIPS specific pseudo-ops. */
1435 {"option", s_option
, 0},
1436 {"set", s_mipsset
, 0},
1437 {"rdata", s_change_sec
, 'r'},
1438 {"sdata", s_change_sec
, 's'},
1439 {"livereg", s_ignore
, 0},
1440 {"abicalls", s_abicalls
, 0},
1441 {"cpload", s_cpload
, 0},
1442 {"cpsetup", s_cpsetup
, 0},
1443 {"cplocal", s_cplocal
, 0},
1444 {"cprestore", s_cprestore
, 0},
1445 {"cpreturn", s_cpreturn
, 0},
1446 {"dtprelword", s_dtprelword
, 0},
1447 {"dtpreldword", s_dtpreldword
, 0},
1448 {"tprelword", s_tprelword
, 0},
1449 {"tpreldword", s_tpreldword
, 0},
1450 {"gpvalue", s_gpvalue
, 0},
1451 {"gpword", s_gpword
, 0},
1452 {"gpdword", s_gpdword
, 0},
1453 {"cpadd", s_cpadd
, 0},
1454 {"insn", s_insn
, 0},
1456 /* Relatively generic pseudo-ops that happen to be used on MIPS
1458 {"asciiz", stringer
, 8 + 1},
1459 {"bss", s_change_sec
, 'b'},
1461 {"half", s_cons
, 1},
1462 {"dword", s_cons
, 3},
1463 {"weakext", s_mips_weakext
, 0},
1464 {"origin", s_org
, 0},
1465 {"repeat", s_rept
, 0},
1467 /* For MIPS this is non-standard, but we define it for consistency. */
1468 {"sbss", s_change_sec
, 'B'},
1470 /* These pseudo-ops are defined in read.c, but must be overridden
1471 here for one reason or another. */
1472 {"align", s_align
, 0},
1473 {"byte", s_cons
, 0},
1474 {"data", s_change_sec
, 'd'},
1475 {"double", s_float_cons
, 'd'},
1476 {"float", s_float_cons
, 'f'},
1477 {"globl", s_mips_globl
, 0},
1478 {"global", s_mips_globl
, 0},
1479 {"hword", s_cons
, 1},
1481 {"long", s_cons
, 2},
1482 {"octa", s_cons
, 4},
1483 {"quad", s_cons
, 3},
1484 {"section", s_change_section
, 0},
1485 {"short", s_cons
, 1},
1486 {"single", s_float_cons
, 'f'},
1487 {"stabd", s_mips_stab
, 'd'},
1488 {"stabn", s_mips_stab
, 'n'},
1489 {"stabs", s_mips_stab
, 's'},
1490 {"text", s_change_sec
, 't'},
1491 {"word", s_cons
, 2},
1493 { "extern", ecoff_directive_extern
, 0},
1498 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1500 /* These pseudo-ops should be defined by the object file format.
1501 However, a.out doesn't support them, so we have versions here. */
1502 {"aent", s_mips_ent
, 1},
1503 {"bgnb", s_ignore
, 0},
1504 {"end", s_mips_end
, 0},
1505 {"endb", s_ignore
, 0},
1506 {"ent", s_mips_ent
, 0},
1507 {"file", s_mips_file
, 0},
1508 {"fmask", s_mips_mask
, 'F'},
1509 {"frame", s_mips_frame
, 0},
1510 {"loc", s_mips_loc
, 0},
1511 {"mask", s_mips_mask
, 'R'},
1512 {"verstamp", s_ignore
, 0},
1516 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1517 purpose of the `.dc.a' internal pseudo-op. */
1520 mips_address_bytes (void)
1522 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1525 extern void pop_insert (const pseudo_typeS
*);
1528 mips_pop_insert (void)
1530 pop_insert (mips_pseudo_table
);
1531 if (! ECOFF_DEBUGGING
)
1532 pop_insert (mips_nonecoff_pseudo_table
);
1535 /* Symbols labelling the current insn. */
1537 struct insn_label_list
1539 struct insn_label_list
*next
;
1543 static struct insn_label_list
*free_insn_labels
;
1544 #define label_list tc_segment_info_data.labels
1546 static void mips_clear_insn_labels (void);
1547 static void mips_mark_labels (void);
1548 static void mips_compressed_mark_labels (void);
1551 mips_clear_insn_labels (void)
1553 register struct insn_label_list
**pl
;
1554 segment_info_type
*si
;
1558 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1561 si
= seg_info (now_seg
);
1562 *pl
= si
->label_list
;
1563 si
->label_list
= NULL
;
1567 /* Mark instruction labels in MIPS16/microMIPS mode. */
1570 mips_mark_labels (void)
1572 if (HAVE_CODE_COMPRESSION
)
1573 mips_compressed_mark_labels ();
1576 static char *expr_end
;
1578 /* Expressions which appear in instructions. These are set by
1581 static expressionS imm_expr
;
1582 static expressionS imm2_expr
;
1583 static expressionS offset_expr
;
1585 /* Relocs associated with imm_expr and offset_expr. */
1587 static bfd_reloc_code_real_type imm_reloc
[3]
1588 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1589 static bfd_reloc_code_real_type offset_reloc
[3]
1590 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1592 /* This is set to the resulting size of the instruction to be produced
1593 by mips16_ip if an explicit extension is used or by mips_ip if an
1594 explicit size is supplied. */
1596 static unsigned int forced_insn_length
;
1598 /* True if we are assembling an instruction. All dot symbols defined during
1599 this time should be treated as code labels. */
1601 static bfd_boolean mips_assembling_insn
;
1604 /* The pdr segment for per procedure frame/regmask info. Not used for
1607 static segT pdr_seg
;
1610 /* The default target format to use. */
1612 #if defined (TE_FreeBSD)
1613 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1614 #elif defined (TE_TMIPS)
1615 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1617 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1621 mips_target_format (void)
1623 switch (OUTPUT_FLAVOR
)
1625 case bfd_target_ecoff_flavour
:
1626 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1627 case bfd_target_coff_flavour
:
1629 case bfd_target_elf_flavour
:
1631 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1632 return (target_big_endian
1633 ? "elf32-bigmips-vxworks"
1634 : "elf32-littlemips-vxworks");
1636 return (target_big_endian
1637 ? (HAVE_64BIT_OBJECTS
1638 ? ELF_TARGET ("elf64-", "big")
1640 ? ELF_TARGET ("elf32-n", "big")
1641 : ELF_TARGET ("elf32-", "big")))
1642 : (HAVE_64BIT_OBJECTS
1643 ? ELF_TARGET ("elf64-", "little")
1645 ? ELF_TARGET ("elf32-n", "little")
1646 : ELF_TARGET ("elf32-", "little"))));
1653 /* Return the length of a microMIPS instruction in bytes. If bits of
1654 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1655 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1656 major opcode) will require further modifications to the opcode
1659 static inline unsigned int
1660 micromips_insn_length (const struct mips_opcode
*mo
)
1662 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1665 /* Return the length of MIPS16 instruction OPCODE. */
1667 static inline unsigned int
1668 mips16_opcode_length (unsigned long opcode
)
1670 return (opcode
>> 16) == 0 ? 2 : 4;
1673 /* Return the length of instruction INSN. */
1675 static inline unsigned int
1676 insn_length (const struct mips_cl_insn
*insn
)
1678 if (mips_opts
.micromips
)
1679 return micromips_insn_length (insn
->insn_mo
);
1680 else if (mips_opts
.mips16
)
1681 return mips16_opcode_length (insn
->insn_opcode
);
1686 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1689 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1694 insn
->insn_opcode
= mo
->match
;
1697 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1698 insn
->fixp
[i
] = NULL
;
1699 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1700 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1701 insn
->mips16_absolute_jump_p
= 0;
1702 insn
->complete_p
= 0;
1703 insn
->cleared_p
= 0;
1706 /* Record the current MIPS16/microMIPS mode in now_seg. */
1709 mips_record_compressed_mode (void)
1711 segment_info_type
*si
;
1713 si
= seg_info (now_seg
);
1714 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1715 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1716 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1717 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1720 /* Read a standard MIPS instruction from BUF. */
1722 static unsigned long
1723 read_insn (char *buf
)
1725 if (target_big_endian
)
1726 return bfd_getb32 ((bfd_byte
*) buf
);
1728 return bfd_getl32 ((bfd_byte
*) buf
);
1731 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1735 write_insn (char *buf
, unsigned int insn
)
1737 md_number_to_chars (buf
, insn
, 4);
1741 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1742 has length LENGTH. */
1744 static unsigned long
1745 read_compressed_insn (char *buf
, unsigned int length
)
1751 for (i
= 0; i
< length
; i
+= 2)
1754 if (target_big_endian
)
1755 insn
|= bfd_getb16 ((char *) buf
);
1757 insn
|= bfd_getl16 ((char *) buf
);
1763 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1764 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1767 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1771 for (i
= 0; i
< length
; i
+= 2)
1772 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1773 return buf
+ length
;
1776 /* Install INSN at the location specified by its "frag" and "where" fields. */
1779 install_insn (const struct mips_cl_insn
*insn
)
1781 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1782 if (HAVE_CODE_COMPRESSION
)
1783 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1785 write_insn (f
, insn
->insn_opcode
);
1786 mips_record_compressed_mode ();
1789 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1790 and install the opcode in the new location. */
1793 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1798 insn
->where
= where
;
1799 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1800 if (insn
->fixp
[i
] != NULL
)
1802 insn
->fixp
[i
]->fx_frag
= frag
;
1803 insn
->fixp
[i
]->fx_where
= where
;
1805 install_insn (insn
);
1808 /* Add INSN to the end of the output. */
1811 add_fixed_insn (struct mips_cl_insn
*insn
)
1813 char *f
= frag_more (insn_length (insn
));
1814 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1817 /* Start a variant frag and move INSN to the start of the variant part,
1818 marking it as fixed. The other arguments are as for frag_var. */
1821 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1822 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1824 frag_grow (max_chars
);
1825 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1827 frag_var (rs_machine_dependent
, max_chars
, var
,
1828 subtype
, symbol
, offset
, NULL
);
1831 /* Insert N copies of INSN into the history buffer, starting at
1832 position FIRST. Neither FIRST nor N need to be clipped. */
1835 insert_into_history (unsigned int first
, unsigned int n
,
1836 const struct mips_cl_insn
*insn
)
1838 if (mips_relax
.sequence
!= 2)
1842 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1844 history
[i
] = history
[i
- n
];
1850 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1851 the idea is to make it obvious at a glance that each errata is
1855 init_vr4120_conflicts (void)
1857 #define CONFLICT(FIRST, SECOND) \
1858 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1860 /* Errata 21 - [D]DIV[U] after [D]MACC */
1861 CONFLICT (MACC
, DIV
);
1862 CONFLICT (DMACC
, DIV
);
1864 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1865 CONFLICT (DMULT
, DMULT
);
1866 CONFLICT (DMULT
, DMACC
);
1867 CONFLICT (DMACC
, DMULT
);
1868 CONFLICT (DMACC
, DMACC
);
1870 /* Errata 24 - MT{LO,HI} after [D]MACC */
1871 CONFLICT (MACC
, MTHILO
);
1872 CONFLICT (DMACC
, MTHILO
);
1874 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1875 instruction is executed immediately after a MACC or DMACC
1876 instruction, the result of [either instruction] is incorrect." */
1877 CONFLICT (MACC
, MULT
);
1878 CONFLICT (MACC
, DMULT
);
1879 CONFLICT (DMACC
, MULT
);
1880 CONFLICT (DMACC
, DMULT
);
1882 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1883 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1884 DDIV or DDIVU instruction, the result of the MACC or
1885 DMACC instruction is incorrect.". */
1886 CONFLICT (DMULT
, MACC
);
1887 CONFLICT (DMULT
, DMACC
);
1888 CONFLICT (DIV
, MACC
);
1889 CONFLICT (DIV
, DMACC
);
1899 #define RTYPE_MASK 0x1ff00
1900 #define RTYPE_NUM 0x00100
1901 #define RTYPE_FPU 0x00200
1902 #define RTYPE_FCC 0x00400
1903 #define RTYPE_VEC 0x00800
1904 #define RTYPE_GP 0x01000
1905 #define RTYPE_CP0 0x02000
1906 #define RTYPE_PC 0x04000
1907 #define RTYPE_ACC 0x08000
1908 #define RTYPE_CCC 0x10000
1909 #define RNUM_MASK 0x000ff
1910 #define RWARN 0x80000
1912 #define GENERIC_REGISTER_NUMBERS \
1913 {"$0", RTYPE_NUM | 0}, \
1914 {"$1", RTYPE_NUM | 1}, \
1915 {"$2", RTYPE_NUM | 2}, \
1916 {"$3", RTYPE_NUM | 3}, \
1917 {"$4", RTYPE_NUM | 4}, \
1918 {"$5", RTYPE_NUM | 5}, \
1919 {"$6", RTYPE_NUM | 6}, \
1920 {"$7", RTYPE_NUM | 7}, \
1921 {"$8", RTYPE_NUM | 8}, \
1922 {"$9", RTYPE_NUM | 9}, \
1923 {"$10", RTYPE_NUM | 10}, \
1924 {"$11", RTYPE_NUM | 11}, \
1925 {"$12", RTYPE_NUM | 12}, \
1926 {"$13", RTYPE_NUM | 13}, \
1927 {"$14", RTYPE_NUM | 14}, \
1928 {"$15", RTYPE_NUM | 15}, \
1929 {"$16", RTYPE_NUM | 16}, \
1930 {"$17", RTYPE_NUM | 17}, \
1931 {"$18", RTYPE_NUM | 18}, \
1932 {"$19", RTYPE_NUM | 19}, \
1933 {"$20", RTYPE_NUM | 20}, \
1934 {"$21", RTYPE_NUM | 21}, \
1935 {"$22", RTYPE_NUM | 22}, \
1936 {"$23", RTYPE_NUM | 23}, \
1937 {"$24", RTYPE_NUM | 24}, \
1938 {"$25", RTYPE_NUM | 25}, \
1939 {"$26", RTYPE_NUM | 26}, \
1940 {"$27", RTYPE_NUM | 27}, \
1941 {"$28", RTYPE_NUM | 28}, \
1942 {"$29", RTYPE_NUM | 29}, \
1943 {"$30", RTYPE_NUM | 30}, \
1944 {"$31", RTYPE_NUM | 31}
1946 #define FPU_REGISTER_NAMES \
1947 {"$f0", RTYPE_FPU | 0}, \
1948 {"$f1", RTYPE_FPU | 1}, \
1949 {"$f2", RTYPE_FPU | 2}, \
1950 {"$f3", RTYPE_FPU | 3}, \
1951 {"$f4", RTYPE_FPU | 4}, \
1952 {"$f5", RTYPE_FPU | 5}, \
1953 {"$f6", RTYPE_FPU | 6}, \
1954 {"$f7", RTYPE_FPU | 7}, \
1955 {"$f8", RTYPE_FPU | 8}, \
1956 {"$f9", RTYPE_FPU | 9}, \
1957 {"$f10", RTYPE_FPU | 10}, \
1958 {"$f11", RTYPE_FPU | 11}, \
1959 {"$f12", RTYPE_FPU | 12}, \
1960 {"$f13", RTYPE_FPU | 13}, \
1961 {"$f14", RTYPE_FPU | 14}, \
1962 {"$f15", RTYPE_FPU | 15}, \
1963 {"$f16", RTYPE_FPU | 16}, \
1964 {"$f17", RTYPE_FPU | 17}, \
1965 {"$f18", RTYPE_FPU | 18}, \
1966 {"$f19", RTYPE_FPU | 19}, \
1967 {"$f20", RTYPE_FPU | 20}, \
1968 {"$f21", RTYPE_FPU | 21}, \
1969 {"$f22", RTYPE_FPU | 22}, \
1970 {"$f23", RTYPE_FPU | 23}, \
1971 {"$f24", RTYPE_FPU | 24}, \
1972 {"$f25", RTYPE_FPU | 25}, \
1973 {"$f26", RTYPE_FPU | 26}, \
1974 {"$f27", RTYPE_FPU | 27}, \
1975 {"$f28", RTYPE_FPU | 28}, \
1976 {"$f29", RTYPE_FPU | 29}, \
1977 {"$f30", RTYPE_FPU | 30}, \
1978 {"$f31", RTYPE_FPU | 31}
1980 #define FPU_CONDITION_CODE_NAMES \
1981 {"$fcc0", RTYPE_FCC | 0}, \
1982 {"$fcc1", RTYPE_FCC | 1}, \
1983 {"$fcc2", RTYPE_FCC | 2}, \
1984 {"$fcc3", RTYPE_FCC | 3}, \
1985 {"$fcc4", RTYPE_FCC | 4}, \
1986 {"$fcc5", RTYPE_FCC | 5}, \
1987 {"$fcc6", RTYPE_FCC | 6}, \
1988 {"$fcc7", RTYPE_FCC | 7}
1990 #define COPROC_CONDITION_CODE_NAMES \
1991 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1992 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1993 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1994 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1995 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1996 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1997 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1998 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2000 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2001 {"$a4", RTYPE_GP | 8}, \
2002 {"$a5", RTYPE_GP | 9}, \
2003 {"$a6", RTYPE_GP | 10}, \
2004 {"$a7", RTYPE_GP | 11}, \
2005 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2006 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2007 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2008 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2009 {"$t0", RTYPE_GP | 12}, \
2010 {"$t1", RTYPE_GP | 13}, \
2011 {"$t2", RTYPE_GP | 14}, \
2012 {"$t3", RTYPE_GP | 15}
2014 #define O32_SYMBOLIC_REGISTER_NAMES \
2015 {"$t0", RTYPE_GP | 8}, \
2016 {"$t1", RTYPE_GP | 9}, \
2017 {"$t2", RTYPE_GP | 10}, \
2018 {"$t3", RTYPE_GP | 11}, \
2019 {"$t4", RTYPE_GP | 12}, \
2020 {"$t5", RTYPE_GP | 13}, \
2021 {"$t6", RTYPE_GP | 14}, \
2022 {"$t7", RTYPE_GP | 15}, \
2023 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2024 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2025 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2026 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2028 /* Remaining symbolic register names */
2029 #define SYMBOLIC_REGISTER_NAMES \
2030 {"$zero", RTYPE_GP | 0}, \
2031 {"$at", RTYPE_GP | 1}, \
2032 {"$AT", RTYPE_GP | 1}, \
2033 {"$v0", RTYPE_GP | 2}, \
2034 {"$v1", RTYPE_GP | 3}, \
2035 {"$a0", RTYPE_GP | 4}, \
2036 {"$a1", RTYPE_GP | 5}, \
2037 {"$a2", RTYPE_GP | 6}, \
2038 {"$a3", RTYPE_GP | 7}, \
2039 {"$s0", RTYPE_GP | 16}, \
2040 {"$s1", RTYPE_GP | 17}, \
2041 {"$s2", RTYPE_GP | 18}, \
2042 {"$s3", RTYPE_GP | 19}, \
2043 {"$s4", RTYPE_GP | 20}, \
2044 {"$s5", RTYPE_GP | 21}, \
2045 {"$s6", RTYPE_GP | 22}, \
2046 {"$s7", RTYPE_GP | 23}, \
2047 {"$t8", RTYPE_GP | 24}, \
2048 {"$t9", RTYPE_GP | 25}, \
2049 {"$k0", RTYPE_GP | 26}, \
2050 {"$kt0", RTYPE_GP | 26}, \
2051 {"$k1", RTYPE_GP | 27}, \
2052 {"$kt1", RTYPE_GP | 27}, \
2053 {"$gp", RTYPE_GP | 28}, \
2054 {"$sp", RTYPE_GP | 29}, \
2055 {"$s8", RTYPE_GP | 30}, \
2056 {"$fp", RTYPE_GP | 30}, \
2057 {"$ra", RTYPE_GP | 31}
2059 #define MIPS16_SPECIAL_REGISTER_NAMES \
2060 {"$pc", RTYPE_PC | 0}
2062 #define MDMX_VECTOR_REGISTER_NAMES \
2063 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2064 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2065 {"$v2", RTYPE_VEC | 2}, \
2066 {"$v3", RTYPE_VEC | 3}, \
2067 {"$v4", RTYPE_VEC | 4}, \
2068 {"$v5", RTYPE_VEC | 5}, \
2069 {"$v6", RTYPE_VEC | 6}, \
2070 {"$v7", RTYPE_VEC | 7}, \
2071 {"$v8", RTYPE_VEC | 8}, \
2072 {"$v9", RTYPE_VEC | 9}, \
2073 {"$v10", RTYPE_VEC | 10}, \
2074 {"$v11", RTYPE_VEC | 11}, \
2075 {"$v12", RTYPE_VEC | 12}, \
2076 {"$v13", RTYPE_VEC | 13}, \
2077 {"$v14", RTYPE_VEC | 14}, \
2078 {"$v15", RTYPE_VEC | 15}, \
2079 {"$v16", RTYPE_VEC | 16}, \
2080 {"$v17", RTYPE_VEC | 17}, \
2081 {"$v18", RTYPE_VEC | 18}, \
2082 {"$v19", RTYPE_VEC | 19}, \
2083 {"$v20", RTYPE_VEC | 20}, \
2084 {"$v21", RTYPE_VEC | 21}, \
2085 {"$v22", RTYPE_VEC | 22}, \
2086 {"$v23", RTYPE_VEC | 23}, \
2087 {"$v24", RTYPE_VEC | 24}, \
2088 {"$v25", RTYPE_VEC | 25}, \
2089 {"$v26", RTYPE_VEC | 26}, \
2090 {"$v27", RTYPE_VEC | 27}, \
2091 {"$v28", RTYPE_VEC | 28}, \
2092 {"$v29", RTYPE_VEC | 29}, \
2093 {"$v30", RTYPE_VEC | 30}, \
2094 {"$v31", RTYPE_VEC | 31}
2096 #define MIPS_DSP_ACCUMULATOR_NAMES \
2097 {"$ac0", RTYPE_ACC | 0}, \
2098 {"$ac1", RTYPE_ACC | 1}, \
2099 {"$ac2", RTYPE_ACC | 2}, \
2100 {"$ac3", RTYPE_ACC | 3}
2102 static const struct regname reg_names
[] = {
2103 GENERIC_REGISTER_NUMBERS
,
2105 FPU_CONDITION_CODE_NAMES
,
2106 COPROC_CONDITION_CODE_NAMES
,
2108 /* The $txx registers depends on the abi,
2109 these will be added later into the symbol table from
2110 one of the tables below once mips_abi is set after
2111 parsing of arguments from the command line. */
2112 SYMBOLIC_REGISTER_NAMES
,
2114 MIPS16_SPECIAL_REGISTER_NAMES
,
2115 MDMX_VECTOR_REGISTER_NAMES
,
2116 MIPS_DSP_ACCUMULATOR_NAMES
,
2120 static const struct regname reg_names_o32
[] = {
2121 O32_SYMBOLIC_REGISTER_NAMES
,
2125 static const struct regname reg_names_n32n64
[] = {
2126 N32N64_SYMBOLIC_REGISTER_NAMES
,
2130 /* Check if S points at a valid register specifier according to TYPES.
2131 If so, then return 1, advance S to consume the specifier and store
2132 the register's number in REGNOP, otherwise return 0. */
2135 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2142 /* Find end of name. */
2144 if (is_name_beginner (*e
))
2146 while (is_part_of_name (*e
))
2149 /* Terminate name. */
2153 /* Look for a register symbol. */
2154 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2156 int r
= S_GET_VALUE (symbolP
);
2158 reg
= r
& RNUM_MASK
;
2159 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2160 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2161 reg
= (r
& RNUM_MASK
) - 2;
2163 /* Else see if this is a register defined in an itbl entry. */
2164 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2171 if (itbl_get_reg_val (n
, &r
))
2172 reg
= r
& RNUM_MASK
;
2175 /* Advance to next token if a register was recognised. */
2178 else if (types
& RWARN
)
2179 as_warn (_("Unrecognized register name `%s'"), *s
);
2187 /* Check if S points at a valid register list according to TYPES.
2188 If so, then return 1, advance S to consume the list and store
2189 the registers present on the list as a bitmask of ones in REGLISTP,
2190 otherwise return 0. A valid list comprises a comma-separated
2191 enumeration of valid single registers and/or dash-separated
2192 contiguous register ranges as determined by their numbers.
2194 As a special exception if one of s0-s7 registers is specified as
2195 the range's lower delimiter and s8 (fp) is its upper one, then no
2196 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2197 are selected; they have to be listed separately if needed. */
2200 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2202 unsigned int reglist
= 0;
2203 unsigned int lastregno
;
2204 bfd_boolean ok
= TRUE
;
2205 unsigned int regmask
;
2206 char *s_endlist
= *s
;
2210 while (reg_lookup (s
, types
, ®no
))
2216 ok
= reg_lookup (s
, types
, &lastregno
);
2217 if (ok
&& lastregno
< regno
)
2223 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2228 regmask
= 1 << lastregno
;
2229 regmask
= (regmask
<< 1) - 1;
2230 regmask
^= (1 << regno
) - 1;
2244 *reglistp
= reglist
;
2245 return ok
&& reglist
!= 0;
2248 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2249 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2252 is_opcode_valid (const struct mips_opcode
*mo
)
2254 int isa
= mips_opts
.isa
;
2257 if (mips_opts
.ase_mdmx
)
2259 if (mips_opts
.ase_dsp
)
2261 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2263 if (mips_opts
.ase_dspr2
)
2265 if (mips_opts
.ase_mt
)
2267 if (mips_opts
.ase_mips3d
)
2269 if (mips_opts
.ase_smartmips
)
2270 isa
|= INSN_SMARTMIPS
;
2271 if (mips_opts
.ase_mcu
)
2273 if (mips_opts
.ase_virt
)
2275 if (mips_opts
.ase_virt
&& ISA_SUPPORTS_VIRT64_ASE
)
2278 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2281 /* Check whether the instruction or macro requires single-precision or
2282 double-precision floating-point support. Note that this information is
2283 stored differently in the opcode table for insns and macros. */
2284 if (mo
->pinfo
== INSN_MACRO
)
2286 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2287 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2291 fp_s
= mo
->pinfo
& FP_S
;
2292 fp_d
= mo
->pinfo
& FP_D
;
2295 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2298 if (fp_s
&& mips_opts
.soft_float
)
2304 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2305 selected ISA and architecture. */
2308 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2310 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2313 /* Return TRUE if the size of the microMIPS opcode MO matches one
2314 explicitly requested. Always TRUE in the standard MIPS mode. */
2317 is_size_valid (const struct mips_opcode
*mo
)
2319 if (!mips_opts
.micromips
)
2322 if (!forced_insn_length
)
2324 if (mo
->pinfo
== INSN_MACRO
)
2326 return forced_insn_length
== micromips_insn_length (mo
);
2329 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2330 of the preceding instruction. Always TRUE in the standard MIPS mode.
2332 We don't accept macros in 16-bit delay slots to avoid a case where
2333 a macro expansion fails because it relies on a preceding 32-bit real
2334 instruction to have matched and does not handle the operands correctly.
2335 The only macros that may expand to 16-bit instructions are JAL that
2336 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2337 and BGT (that likewise cannot be placed in a delay slot) that decay to
2338 a NOP. In all these cases the macros precede any corresponding real
2339 instruction definitions in the opcode table, so they will match in the
2340 second pass where the size of the delay slot is ignored and therefore
2341 produce correct code. */
2344 is_delay_slot_valid (const struct mips_opcode
*mo
)
2346 if (!mips_opts
.micromips
)
2349 if (mo
->pinfo
== INSN_MACRO
)
2350 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2351 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2352 && micromips_insn_length (mo
) != 4)
2354 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2355 && micromips_insn_length (mo
) != 2)
2361 /* This function is called once, at assembler startup time. It should set up
2362 all the tables, etc. that the MD part of the assembler will need. */
2367 const char *retval
= NULL
;
2371 if (mips_pic
!= NO_PIC
)
2373 if (g_switch_seen
&& g_switch_value
!= 0)
2374 as_bad (_("-G may not be used in position-independent code"));
2378 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2379 as_warn (_("Could not set architecture and machine"));
2381 op_hash
= hash_new ();
2383 for (i
= 0; i
< NUMOPCODES
;)
2385 const char *name
= mips_opcodes
[i
].name
;
2387 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2390 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2391 mips_opcodes
[i
].name
, retval
);
2392 /* Probably a memory allocation problem? Give up now. */
2393 as_fatal (_("Broken assembler. No assembly attempted."));
2397 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2399 if (!validate_mips_insn (&mips_opcodes
[i
]))
2401 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2403 create_insn (&nop_insn
, mips_opcodes
+ i
);
2404 if (mips_fix_loongson2f_nop
)
2405 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2406 nop_insn
.fixed_p
= 1;
2411 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2414 mips16_op_hash
= hash_new ();
2417 while (i
< bfd_mips16_num_opcodes
)
2419 const char *name
= mips16_opcodes
[i
].name
;
2421 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2423 as_fatal (_("internal: can't hash `%s': %s"),
2424 mips16_opcodes
[i
].name
, retval
);
2427 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2428 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2429 != mips16_opcodes
[i
].match
))
2431 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2432 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2435 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2437 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2438 mips16_nop_insn
.fixed_p
= 1;
2442 while (i
< bfd_mips16_num_opcodes
2443 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2446 micromips_op_hash
= hash_new ();
2449 while (i
< bfd_micromips_num_opcodes
)
2451 const char *name
= micromips_opcodes
[i
].name
;
2453 retval
= hash_insert (micromips_op_hash
, name
,
2454 (void *) µmips_opcodes
[i
]);
2456 as_fatal (_("internal: can't hash `%s': %s"),
2457 micromips_opcodes
[i
].name
, retval
);
2459 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2461 struct mips_cl_insn
*micromips_nop_insn
;
2463 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2466 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2467 micromips_nop_insn
= µmips_nop16_insn
;
2468 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2469 micromips_nop_insn
= µmips_nop32_insn
;
2473 if (micromips_nop_insn
->insn_mo
== NULL
2474 && strcmp (name
, "nop") == 0)
2476 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2477 micromips_nop_insn
->fixed_p
= 1;
2480 while (++i
< bfd_micromips_num_opcodes
2481 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2485 as_fatal (_("Broken assembler. No assembly attempted."));
2487 /* We add all the general register names to the symbol table. This
2488 helps us detect invalid uses of them. */
2489 for (i
= 0; reg_names
[i
].name
; i
++)
2490 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2491 reg_names
[i
].num
, /* & RNUM_MASK, */
2492 &zero_address_frag
));
2494 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2495 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2496 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2497 &zero_address_frag
));
2499 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2500 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2501 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2502 &zero_address_frag
));
2504 mips_no_prev_insn ();
2507 mips_cprmask
[0] = 0;
2508 mips_cprmask
[1] = 0;
2509 mips_cprmask
[2] = 0;
2510 mips_cprmask
[3] = 0;
2512 /* set the default alignment for the text section (2**2) */
2513 record_alignment (text_section
, 2);
2515 bfd_set_gp_size (stdoutput
, g_switch_value
);
2520 /* On a native system other than VxWorks, sections must be aligned
2521 to 16 byte boundaries. When configured for an embedded ELF
2522 target, we don't bother. */
2523 if (strncmp (TARGET_OS
, "elf", 3) != 0
2524 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2526 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2527 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2528 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2531 /* Create a .reginfo section for register masks and a .mdebug
2532 section for debugging information. */
2540 subseg
= now_subseg
;
2542 /* The ABI says this section should be loaded so that the
2543 running program can access it. However, we don't load it
2544 if we are configured for an embedded target */
2545 flags
= SEC_READONLY
| SEC_DATA
;
2546 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2547 flags
|= SEC_ALLOC
| SEC_LOAD
;
2549 if (mips_abi
!= N64_ABI
)
2551 sec
= subseg_new (".reginfo", (subsegT
) 0);
2553 bfd_set_section_flags (stdoutput
, sec
, flags
);
2554 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2556 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2560 /* The 64-bit ABI uses a .MIPS.options section rather than
2561 .reginfo section. */
2562 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2563 bfd_set_section_flags (stdoutput
, sec
, flags
);
2564 bfd_set_section_alignment (stdoutput
, sec
, 3);
2566 /* Set up the option header. */
2568 Elf_Internal_Options opthdr
;
2571 opthdr
.kind
= ODK_REGINFO
;
2572 opthdr
.size
= (sizeof (Elf_External_Options
)
2573 + sizeof (Elf64_External_RegInfo
));
2576 f
= frag_more (sizeof (Elf_External_Options
));
2577 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2578 (Elf_External_Options
*) f
);
2580 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2584 if (ECOFF_DEBUGGING
)
2586 sec
= subseg_new (".mdebug", (subsegT
) 0);
2587 (void) bfd_set_section_flags (stdoutput
, sec
,
2588 SEC_HAS_CONTENTS
| SEC_READONLY
);
2589 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2591 else if (mips_flag_pdr
)
2593 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2594 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2595 SEC_READONLY
| SEC_RELOC
2597 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2600 subseg_set (seg
, subseg
);
2603 #endif /* OBJ_ELF */
2605 if (! ECOFF_DEBUGGING
)
2608 if (mips_fix_vr4120
)
2609 init_vr4120_conflicts ();
2615 mips_emit_delays ();
2616 if (! ECOFF_DEBUGGING
)
2621 md_assemble (char *str
)
2623 struct mips_cl_insn insn
;
2624 bfd_reloc_code_real_type unused_reloc
[3]
2625 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2627 imm_expr
.X_op
= O_absent
;
2628 imm2_expr
.X_op
= O_absent
;
2629 offset_expr
.X_op
= O_absent
;
2630 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2631 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2632 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2633 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2634 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2635 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2637 mips_mark_labels ();
2638 mips_assembling_insn
= TRUE
;
2640 if (mips_opts
.mips16
)
2641 mips16_ip (str
, &insn
);
2644 mips_ip (str
, &insn
);
2645 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2646 str
, insn
.insn_opcode
));
2650 as_bad ("%s `%s'", insn_error
, str
);
2651 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2654 if (mips_opts
.mips16
)
2655 mips16_macro (&insn
);
2662 if (imm_expr
.X_op
!= O_absent
)
2663 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2664 else if (offset_expr
.X_op
!= O_absent
)
2665 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2667 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2670 mips_assembling_insn
= FALSE
;
2673 /* Convenience functions for abstracting away the differences between
2674 MIPS16 and non-MIPS16 relocations. */
2676 static inline bfd_boolean
2677 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2681 case BFD_RELOC_MIPS16_JMP
:
2682 case BFD_RELOC_MIPS16_GPREL
:
2683 case BFD_RELOC_MIPS16_GOT16
:
2684 case BFD_RELOC_MIPS16_CALL16
:
2685 case BFD_RELOC_MIPS16_HI16_S
:
2686 case BFD_RELOC_MIPS16_HI16
:
2687 case BFD_RELOC_MIPS16_LO16
:
2695 static inline bfd_boolean
2696 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2700 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2701 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2702 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2703 case BFD_RELOC_MICROMIPS_GPREL16
:
2704 case BFD_RELOC_MICROMIPS_JMP
:
2705 case BFD_RELOC_MICROMIPS_HI16
:
2706 case BFD_RELOC_MICROMIPS_HI16_S
:
2707 case BFD_RELOC_MICROMIPS_LO16
:
2708 case BFD_RELOC_MICROMIPS_LITERAL
:
2709 case BFD_RELOC_MICROMIPS_GOT16
:
2710 case BFD_RELOC_MICROMIPS_CALL16
:
2711 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2712 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2713 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2714 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2715 case BFD_RELOC_MICROMIPS_SUB
:
2716 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2717 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2718 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2719 case BFD_RELOC_MICROMIPS_HIGHEST
:
2720 case BFD_RELOC_MICROMIPS_HIGHER
:
2721 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2722 case BFD_RELOC_MICROMIPS_JALR
:
2730 static inline bfd_boolean
2731 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2733 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2736 static inline bfd_boolean
2737 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2739 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2740 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2743 static inline bfd_boolean
2744 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2746 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2747 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2750 static inline bfd_boolean
2751 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2753 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2754 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2757 static inline bfd_boolean
2758 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2760 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2763 /* Return true if RELOC is a PC-relative relocation that does not have
2764 full address range. */
2766 static inline bfd_boolean
2767 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
2771 case BFD_RELOC_16_PCREL_S2
:
2772 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2773 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2774 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2777 case BFD_RELOC_32_PCREL
:
2778 return HAVE_64BIT_ADDRESSES
;
2785 /* Return true if the given relocation might need a matching %lo().
2786 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2787 need a matching %lo() when applied to local symbols. */
2789 static inline bfd_boolean
2790 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2792 return (HAVE_IN_PLACE_ADDENDS
2793 && (hi16_reloc_p (reloc
)
2794 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2795 all GOT16 relocations evaluate to "G". */
2796 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2799 /* Return the type of %lo() reloc needed by RELOC, given that
2800 reloc_needs_lo_p. */
2802 static inline bfd_reloc_code_real_type
2803 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2805 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2806 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2810 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2813 static inline bfd_boolean
2814 fixup_has_matching_lo_p (fixS
*fixp
)
2816 return (fixp
->fx_next
!= NULL
2817 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2818 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2819 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2822 /* This function returns true if modifying a register requires a
2826 reg_needs_delay (unsigned int reg
)
2828 unsigned long prev_pinfo
;
2830 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2831 if (! mips_opts
.noreorder
2832 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2833 && ! gpr_interlocks
)
2834 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2835 && ! cop_interlocks
)))
2837 /* A load from a coprocessor or from memory. All load delays
2838 delay the use of general register rt for one instruction. */
2839 /* Itbl support may require additional care here. */
2840 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2841 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2848 /* Move all labels in LABELS to the current insertion point. TEXT_P
2849 says whether the labels refer to text or data. */
2852 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2854 struct insn_label_list
*l
;
2857 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2859 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2860 symbol_set_frag (l
->label
, frag_now
);
2861 val
= (valueT
) frag_now_fix ();
2862 /* MIPS16/microMIPS text labels are stored as odd. */
2863 if (text_p
&& HAVE_CODE_COMPRESSION
)
2865 S_SET_VALUE (l
->label
, val
);
2869 /* Move all labels in insn_labels to the current insertion point
2870 and treat them as text labels. */
2873 mips_move_text_labels (void)
2875 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2879 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2881 bfd_boolean linkonce
= FALSE
;
2882 segT symseg
= S_GET_SEGMENT (sym
);
2884 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2886 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2889 /* The GNU toolchain uses an extension for ELF: a section
2890 beginning with the magic string .gnu.linkonce is a
2891 linkonce section. */
2892 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2893 sizeof ".gnu.linkonce" - 1) == 0)
2900 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2901 linker to handle them specially, such as generating jalx instructions
2902 when needed. We also make them odd for the duration of the assembly,
2903 in order to generate the right sort of code. We will make them even
2904 in the adjust_symtab routine, while leaving them marked. This is
2905 convenient for the debugger and the disassembler. The linker knows
2906 to make them odd again. */
2909 mips_compressed_mark_label (symbolS
*label
)
2911 gas_assert (HAVE_CODE_COMPRESSION
);
2913 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2916 if (mips_opts
.mips16
)
2917 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2919 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2922 if ((S_GET_VALUE (label
) & 1) == 0
2923 /* Don't adjust the address if the label is global or weak, or
2924 in a link-once section, since we'll be emitting symbol reloc
2925 references to it which will be patched up by the linker, and
2926 the final value of the symbol may or may not be MIPS16/microMIPS. */
2927 && !S_IS_WEAK (label
)
2928 && !S_IS_EXTERNAL (label
)
2929 && !s_is_linkonce (label
, now_seg
))
2930 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2933 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2936 mips_compressed_mark_labels (void)
2938 struct insn_label_list
*l
;
2940 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2941 mips_compressed_mark_label (l
->label
);
2944 /* End the current frag. Make it a variant frag and record the
2948 relax_close_frag (void)
2950 mips_macro_warning
.first_frag
= frag_now
;
2951 frag_var (rs_machine_dependent
, 0, 0,
2952 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2953 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2955 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2956 mips_relax
.first_fixup
= 0;
2959 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2960 See the comment above RELAX_ENCODE for more details. */
2963 relax_start (symbolS
*symbol
)
2965 gas_assert (mips_relax
.sequence
== 0);
2966 mips_relax
.sequence
= 1;
2967 mips_relax
.symbol
= symbol
;
2970 /* Start generating the second version of a relaxable sequence.
2971 See the comment above RELAX_ENCODE for more details. */
2976 gas_assert (mips_relax
.sequence
== 1);
2977 mips_relax
.sequence
= 2;
2980 /* End the current relaxable sequence. */
2985 gas_assert (mips_relax
.sequence
== 2);
2986 relax_close_frag ();
2987 mips_relax
.sequence
= 0;
2990 /* Return true if IP is a delayed branch or jump. */
2992 static inline bfd_boolean
2993 delayed_branch_p (const struct mips_cl_insn
*ip
)
2995 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2996 | INSN_COND_BRANCH_DELAY
2997 | INSN_COND_BRANCH_LIKELY
)) != 0;
3000 /* Return true if IP is a compact branch or jump. */
3002 static inline bfd_boolean
3003 compact_branch_p (const struct mips_cl_insn
*ip
)
3005 if (mips_opts
.mips16
)
3006 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3007 | MIPS16_INSN_COND_BRANCH
)) != 0;
3009 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3010 | INSN2_COND_BRANCH
)) != 0;
3013 /* Return true if IP is an unconditional branch or jump. */
3015 static inline bfd_boolean
3016 uncond_branch_p (const struct mips_cl_insn
*ip
)
3018 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3019 || (mips_opts
.mips16
3020 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3021 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3024 /* Return true if IP is a branch-likely instruction. */
3026 static inline bfd_boolean
3027 branch_likely_p (const struct mips_cl_insn
*ip
)
3029 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3032 /* Return the type of nop that should be used to fill the delay slot
3033 of delayed branch IP. */
3035 static struct mips_cl_insn
*
3036 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3038 if (mips_opts
.micromips
3039 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3040 return µmips_nop32_insn
;
3044 /* Return the mask of core registers that IP reads or writes. */
3047 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3049 unsigned long pinfo2
;
3053 pinfo2
= ip
->insn_mo
->pinfo2
;
3054 if (mips_opts
.micromips
)
3056 if (pinfo2
& INSN2_MOD_GPR_MD
)
3057 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3058 if (pinfo2
& INSN2_MOD_GPR_MF
)
3059 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3060 if (pinfo2
& INSN2_MOD_SP
)
3066 /* Return the mask of core registers that IP reads. */
3069 gpr_read_mask (const struct mips_cl_insn
*ip
)
3071 unsigned long pinfo
, pinfo2
;
3074 mask
= gpr_mod_mask (ip
);
3075 pinfo
= ip
->insn_mo
->pinfo
;
3076 pinfo2
= ip
->insn_mo
->pinfo2
;
3077 if (mips_opts
.mips16
)
3079 if (pinfo
& MIPS16_INSN_READ_X
)
3080 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3081 if (pinfo
& MIPS16_INSN_READ_Y
)
3082 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3083 if (pinfo
& MIPS16_INSN_READ_T
)
3085 if (pinfo
& MIPS16_INSN_READ_SP
)
3087 if (pinfo
& MIPS16_INSN_READ_31
)
3089 if (pinfo
& MIPS16_INSN_READ_Z
)
3090 mask
|= 1 << (mips16_to_32_reg_map
3091 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3092 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3093 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3097 if (pinfo2
& INSN2_READ_GPR_D
)
3098 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3099 if (pinfo
& INSN_READ_GPR_T
)
3100 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3101 if (pinfo
& INSN_READ_GPR_S
)
3102 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3103 if (pinfo2
& INSN2_READ_GP
)
3105 if (pinfo2
& INSN2_READ_GPR_31
)
3107 if (pinfo2
& INSN2_READ_GPR_Z
)
3108 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3110 if (mips_opts
.micromips
)
3112 if (pinfo2
& INSN2_READ_GPR_MC
)
3113 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3114 if (pinfo2
& INSN2_READ_GPR_ME
)
3115 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3116 if (pinfo2
& INSN2_READ_GPR_MG
)
3117 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3118 if (pinfo2
& INSN2_READ_GPR_MJ
)
3119 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3120 if (pinfo2
& INSN2_READ_GPR_MMN
)
3122 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3123 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3125 if (pinfo2
& INSN2_READ_GPR_MP
)
3126 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3127 if (pinfo2
& INSN2_READ_GPR_MQ
)
3128 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3130 /* Don't include register 0. */
3134 /* Return the mask of core registers that IP writes. */
3137 gpr_write_mask (const struct mips_cl_insn
*ip
)
3139 unsigned long pinfo
, pinfo2
;
3142 mask
= gpr_mod_mask (ip
);
3143 pinfo
= ip
->insn_mo
->pinfo
;
3144 pinfo2
= ip
->insn_mo
->pinfo2
;
3145 if (mips_opts
.mips16
)
3147 if (pinfo
& MIPS16_INSN_WRITE_X
)
3148 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3149 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3150 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3151 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3152 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3153 if (pinfo
& MIPS16_INSN_WRITE_T
)
3155 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3157 if (pinfo
& MIPS16_INSN_WRITE_31
)
3159 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3160 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3164 if (pinfo
& INSN_WRITE_GPR_D
)
3165 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3166 if (pinfo
& INSN_WRITE_GPR_T
)
3167 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3168 if (pinfo
& INSN_WRITE_GPR_S
)
3169 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3170 if (pinfo
& INSN_WRITE_GPR_31
)
3172 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3173 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3175 if (mips_opts
.micromips
)
3177 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3178 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3179 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3181 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3182 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3184 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3185 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3186 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3187 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3189 /* Don't include register 0. */
3193 /* Return the mask of floating-point registers that IP reads. */
3196 fpr_read_mask (const struct mips_cl_insn
*ip
)
3198 unsigned long pinfo
, pinfo2
;
3202 pinfo
= ip
->insn_mo
->pinfo
;
3203 pinfo2
= ip
->insn_mo
->pinfo2
;
3204 if (!mips_opts
.mips16
)
3206 if (pinfo2
& INSN2_READ_FPR_D
)
3207 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3208 if (pinfo
& INSN_READ_FPR_S
)
3209 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3210 if (pinfo
& INSN_READ_FPR_T
)
3211 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3212 if (pinfo
& INSN_READ_FPR_R
)
3213 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3214 if (pinfo2
& INSN2_READ_FPR_Z
)
3215 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3217 /* Conservatively treat all operands to an FP_D instruction are doubles.
3218 (This is overly pessimistic for things like cvt.d.s.) */
3219 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3224 /* Return the mask of floating-point registers that IP writes. */
3227 fpr_write_mask (const struct mips_cl_insn
*ip
)
3229 unsigned long pinfo
, pinfo2
;
3233 pinfo
= ip
->insn_mo
->pinfo
;
3234 pinfo2
= ip
->insn_mo
->pinfo2
;
3235 if (!mips_opts
.mips16
)
3237 if (pinfo
& INSN_WRITE_FPR_D
)
3238 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3239 if (pinfo
& INSN_WRITE_FPR_S
)
3240 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3241 if (pinfo
& INSN_WRITE_FPR_T
)
3242 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3243 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3244 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3246 /* Conservatively treat all operands to an FP_D instruction are doubles.
3247 (This is overly pessimistic for things like cvt.s.d.) */
3248 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3253 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3254 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3255 by VR4120 errata. */
3258 classify_vr4120_insn (const char *name
)
3260 if (strncmp (name
, "macc", 4) == 0)
3261 return FIX_VR4120_MACC
;
3262 if (strncmp (name
, "dmacc", 5) == 0)
3263 return FIX_VR4120_DMACC
;
3264 if (strncmp (name
, "mult", 4) == 0)
3265 return FIX_VR4120_MULT
;
3266 if (strncmp (name
, "dmult", 5) == 0)
3267 return FIX_VR4120_DMULT
;
3268 if (strstr (name
, "div"))
3269 return FIX_VR4120_DIV
;
3270 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3271 return FIX_VR4120_MTHILO
;
3272 return NUM_FIX_VR4120_CLASSES
;
3275 #define INSN_ERET 0x42000018
3276 #define INSN_DERET 0x4200001f
3278 /* Return the number of instructions that must separate INSN1 and INSN2,
3279 where INSN1 is the earlier instruction. Return the worst-case value
3280 for any INSN2 if INSN2 is null. */
3283 insns_between (const struct mips_cl_insn
*insn1
,
3284 const struct mips_cl_insn
*insn2
)
3286 unsigned long pinfo1
, pinfo2
;
3289 /* This function needs to know which pinfo flags are set for INSN2
3290 and which registers INSN2 uses. The former is stored in PINFO2 and
3291 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3292 will have every flag set and INSN2_USES_GPR will always return true. */
3293 pinfo1
= insn1
->insn_mo
->pinfo
;
3294 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3296 #define INSN2_USES_GPR(REG) \
3297 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3299 /* For most targets, write-after-read dependencies on the HI and LO
3300 registers must be separated by at least two instructions. */
3301 if (!hilo_interlocks
)
3303 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3305 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3309 /* If we're working around r7000 errata, there must be two instructions
3310 between an mfhi or mflo and any instruction that uses the result. */
3311 if (mips_7000_hilo_fix
3312 && !mips_opts
.micromips
3313 && MF_HILO_INSN (pinfo1
)
3314 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3317 /* If we're working around 24K errata, one instruction is required
3318 if an ERET or DERET is followed by a branch instruction. */
3319 if (mips_fix_24k
&& !mips_opts
.micromips
)
3321 if (insn1
->insn_opcode
== INSN_ERET
3322 || insn1
->insn_opcode
== INSN_DERET
)
3325 || insn2
->insn_opcode
== INSN_ERET
3326 || insn2
->insn_opcode
== INSN_DERET
3327 || delayed_branch_p (insn2
))
3332 /* If working around VR4120 errata, check for combinations that need
3333 a single intervening instruction. */
3334 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3336 unsigned int class1
, class2
;
3338 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3339 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3343 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3344 if (vr4120_conflicts
[class1
] & (1 << class2
))
3349 if (!HAVE_CODE_COMPRESSION
)
3351 /* Check for GPR or coprocessor load delays. All such delays
3352 are on the RT register. */
3353 /* Itbl support may require additional care here. */
3354 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3355 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3357 know (pinfo1
& INSN_WRITE_GPR_T
);
3358 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3362 /* Check for generic coprocessor hazards.
3364 This case is not handled very well. There is no special
3365 knowledge of CP0 handling, and the coprocessors other than
3366 the floating point unit are not distinguished at all. */
3367 /* Itbl support may require additional care here. FIXME!
3368 Need to modify this to include knowledge about
3369 user specified delays! */
3370 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3371 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3373 /* Handle cases where INSN1 writes to a known general coprocessor
3374 register. There must be a one instruction delay before INSN2
3375 if INSN2 reads that register, otherwise no delay is needed. */
3376 mask
= fpr_write_mask (insn1
);
3379 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3384 /* Read-after-write dependencies on the control registers
3385 require a two-instruction gap. */
3386 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3387 && (pinfo2
& INSN_READ_COND_CODE
))
3390 /* We don't know exactly what INSN1 does. If INSN2 is
3391 also a coprocessor instruction, assume there must be
3392 a one instruction gap. */
3393 if (pinfo2
& INSN_COP
)
3398 /* Check for read-after-write dependencies on the coprocessor
3399 control registers in cases where INSN1 does not need a general
3400 coprocessor delay. This means that INSN1 is a floating point
3401 comparison instruction. */
3402 /* Itbl support may require additional care here. */
3403 else if (!cop_interlocks
3404 && (pinfo1
& INSN_WRITE_COND_CODE
)
3405 && (pinfo2
& INSN_READ_COND_CODE
))
3409 #undef INSN2_USES_GPR
3414 /* Return the number of nops that would be needed to work around the
3415 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3416 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3417 that are contained within the first IGNORE instructions of HIST. */
3420 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3421 const struct mips_cl_insn
*insn
)
3426 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3427 are not affected by the errata. */
3429 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3430 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3431 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3434 /* Search for the first MFLO or MFHI. */
3435 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3436 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3438 /* Extract the destination register. */
3439 mask
= gpr_write_mask (&hist
[i
]);
3441 /* No nops are needed if INSN reads that register. */
3442 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3445 /* ...or if any of the intervening instructions do. */
3446 for (j
= 0; j
< i
; j
++)
3447 if (gpr_read_mask (&hist
[j
]) & mask
)
3451 return MAX_VR4130_NOPS
- i
;
3456 #define BASE_REG_EQ(INSN1, INSN2) \
3457 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3458 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3460 /* Return the minimum alignment for this store instruction. */
3463 fix_24k_align_to (const struct mips_opcode
*mo
)
3465 if (strcmp (mo
->name
, "sh") == 0)
3468 if (strcmp (mo
->name
, "swc1") == 0
3469 || strcmp (mo
->name
, "swc2") == 0
3470 || strcmp (mo
->name
, "sw") == 0
3471 || strcmp (mo
->name
, "sc") == 0
3472 || strcmp (mo
->name
, "s.s") == 0)
3475 if (strcmp (mo
->name
, "sdc1") == 0
3476 || strcmp (mo
->name
, "sdc2") == 0
3477 || strcmp (mo
->name
, "s.d") == 0)
3484 struct fix_24k_store_info
3486 /* Immediate offset, if any, for this store instruction. */
3488 /* Alignment required by this store instruction. */
3490 /* True for register offsets. */
3491 int register_offset
;
3494 /* Comparison function used by qsort. */
3497 fix_24k_sort (const void *a
, const void *b
)
3499 const struct fix_24k_store_info
*pos1
= a
;
3500 const struct fix_24k_store_info
*pos2
= b
;
3502 return (pos1
->off
- pos2
->off
);
3505 /* INSN is a store instruction. Try to record the store information
3506 in STINFO. Return false if the information isn't known. */
3509 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3510 const struct mips_cl_insn
*insn
)
3512 /* The instruction must have a known offset. */
3513 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3516 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3517 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3521 /* Return the number of nops that would be needed to work around the 24k
3522 "lost data on stores during refill" errata if instruction INSN
3523 immediately followed the 2 instructions described by HIST.
3524 Ignore hazards that are contained within the first IGNORE
3525 instructions of HIST.
3527 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3528 for the data cache refills and store data. The following describes
3529 the scenario where the store data could be lost.
3531 * A data cache miss, due to either a load or a store, causing fill
3532 data to be supplied by the memory subsystem
3533 * The first three doublewords of fill data are returned and written
3535 * A sequence of four stores occurs in consecutive cycles around the
3536 final doubleword of the fill:
3540 * Zero, One or more instructions
3543 The four stores A-D must be to different doublewords of the line that
3544 is being filled. The fourth instruction in the sequence above permits
3545 the fill of the final doubleword to be transferred from the FSB into
3546 the cache. In the sequence above, the stores may be either integer
3547 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3548 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3549 different doublewords on the line. If the floating point unit is
3550 running in 1:2 mode, it is not possible to create the sequence above
3551 using only floating point store instructions.
3553 In this case, the cache line being filled is incorrectly marked
3554 invalid, thereby losing the data from any store to the line that
3555 occurs between the original miss and the completion of the five
3556 cycle sequence shown above.
3558 The workarounds are:
3560 * Run the data cache in write-through mode.
3561 * Insert a non-store instruction between
3562 Store A and Store B or Store B and Store C. */
3565 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3566 const struct mips_cl_insn
*insn
)
3568 struct fix_24k_store_info pos
[3];
3569 int align
, i
, base_offset
;
3574 /* If the previous instruction wasn't a store, there's nothing to
3576 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3579 /* If the instructions after the previous one are unknown, we have
3580 to assume the worst. */
3584 /* Check whether we are dealing with three consecutive stores. */
3585 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3586 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3589 /* If we don't know the relationship between the store addresses,
3590 assume the worst. */
3591 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3592 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3595 if (!fix_24k_record_store_info (&pos
[0], insn
)
3596 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3597 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3600 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3602 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3603 X bytes and such that the base register + X is known to be aligned
3606 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3610 align
= pos
[0].align_to
;
3611 base_offset
= pos
[0].off
;
3612 for (i
= 1; i
< 3; i
++)
3613 if (align
< pos
[i
].align_to
)
3615 align
= pos
[i
].align_to
;
3616 base_offset
= pos
[i
].off
;
3618 for (i
= 0; i
< 3; i
++)
3619 pos
[i
].off
-= base_offset
;
3622 pos
[0].off
&= ~align
+ 1;
3623 pos
[1].off
&= ~align
+ 1;
3624 pos
[2].off
&= ~align
+ 1;
3626 /* If any two stores write to the same chunk, they also write to the
3627 same doubleword. The offsets are still sorted at this point. */
3628 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3631 /* A range of at least 9 bytes is needed for the stores to be in
3632 non-overlapping doublewords. */
3633 if (pos
[2].off
- pos
[0].off
<= 8)
3636 if (pos
[2].off
- pos
[1].off
>= 24
3637 || pos
[1].off
- pos
[0].off
>= 24
3638 || pos
[2].off
- pos
[0].off
>= 32)
3644 /* Return the number of nops that would be needed if instruction INSN
3645 immediately followed the MAX_NOPS instructions given by HIST,
3646 where HIST[0] is the most recent instruction. Ignore hazards
3647 between INSN and the first IGNORE instructions in HIST.
3649 If INSN is null, return the worse-case number of nops for any
3653 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3654 const struct mips_cl_insn
*insn
)
3656 int i
, nops
, tmp_nops
;
3659 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3661 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3662 if (tmp_nops
> nops
)
3666 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3668 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3669 if (tmp_nops
> nops
)
3673 if (mips_fix_24k
&& !mips_opts
.micromips
)
3675 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3676 if (tmp_nops
> nops
)
3683 /* The variable arguments provide NUM_INSNS extra instructions that
3684 might be added to HIST. Return the largest number of nops that
3685 would be needed after the extended sequence, ignoring hazards
3686 in the first IGNORE instructions. */
3689 nops_for_sequence (int num_insns
, int ignore
,
3690 const struct mips_cl_insn
*hist
, ...)
3693 struct mips_cl_insn buffer
[MAX_NOPS
];
3694 struct mips_cl_insn
*cursor
;
3697 va_start (args
, hist
);
3698 cursor
= buffer
+ num_insns
;
3699 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3700 while (cursor
> buffer
)
3701 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3703 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3708 /* Like nops_for_insn, but if INSN is a branch, take into account the
3709 worst-case delay for the branch target. */
3712 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3713 const struct mips_cl_insn
*insn
)
3717 nops
= nops_for_insn (ignore
, hist
, insn
);
3718 if (delayed_branch_p (insn
))
3720 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3721 hist
, insn
, get_delay_slot_nop (insn
));
3722 if (tmp_nops
> nops
)
3725 else if (compact_branch_p (insn
))
3727 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3728 if (tmp_nops
> nops
)
3734 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3737 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3739 gas_assert (!HAVE_CODE_COMPRESSION
);
3740 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3741 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3744 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3745 jr target pc &= 'hffff_ffff_cfff_ffff. */
3748 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3750 gas_assert (!HAVE_CODE_COMPRESSION
);
3751 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3752 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3753 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3761 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3762 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3765 ep
.X_op
= O_constant
;
3766 ep
.X_add_number
= 0xcfff0000;
3767 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3768 ep
.X_add_number
= 0xffff;
3769 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3770 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3775 fix_loongson2f (struct mips_cl_insn
* ip
)
3777 if (mips_fix_loongson2f_nop
)
3778 fix_loongson2f_nop (ip
);
3780 if (mips_fix_loongson2f_jump
)
3781 fix_loongson2f_jump (ip
);
3784 /* IP is a branch that has a delay slot, and we need to fill it
3785 automatically. Return true if we can do that by swapping IP
3786 with the previous instruction.
3787 ADDRESS_EXPR is an operand of the instruction to be used with
3791 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3792 bfd_reloc_code_real_type
*reloc_type
)
3794 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3795 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3797 /* -O2 and above is required for this optimization. */
3798 if (mips_optimize
< 2)
3801 /* If we have seen .set volatile or .set nomove, don't optimize. */
3802 if (mips_opts
.nomove
)
3805 /* We can't swap if the previous instruction's position is fixed. */
3806 if (history
[0].fixed_p
)
3809 /* If the previous previous insn was in a .set noreorder, we can't
3810 swap. Actually, the MIPS assembler will swap in this situation.
3811 However, gcc configured -with-gnu-as will generate code like
3819 in which we can not swap the bne and INSN. If gcc is not configured
3820 -with-gnu-as, it does not output the .set pseudo-ops. */
3821 if (history
[1].noreorder_p
)
3824 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3825 This means that the previous instruction was a 4-byte one anyhow. */
3826 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3829 /* If the branch is itself the target of a branch, we can not swap.
3830 We cheat on this; all we check for is whether there is a label on
3831 this instruction. If there are any branches to anything other than
3832 a label, users must use .set noreorder. */
3833 if (seg_info (now_seg
)->label_list
)
3836 /* If the previous instruction is in a variant frag other than this
3837 branch's one, we cannot do the swap. This does not apply to
3838 MIPS16 code, which uses variant frags for different purposes. */
3839 if (!mips_opts
.mips16
3841 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3844 /* We do not swap with instructions that cannot architecturally
3845 be placed in a branch delay slot, such as SYNC or ERET. We
3846 also refrain from swapping with a trap instruction, since it
3847 complicates trap handlers to have the trap instruction be in
3849 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3850 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3853 /* Check for conflicts between the branch and the instructions
3854 before the candidate delay slot. */
3855 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3858 /* Check for conflicts between the swapped sequence and the
3859 target of the branch. */
3860 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3863 /* If the branch reads a register that the previous
3864 instruction sets, we can not swap. */
3865 gpr_read
= gpr_read_mask (ip
);
3866 prev_gpr_write
= gpr_write_mask (&history
[0]);
3867 if (gpr_read
& prev_gpr_write
)
3870 /* If the branch writes a register that the previous
3871 instruction sets, we can not swap. */
3872 gpr_write
= gpr_write_mask (ip
);
3873 if (gpr_write
& prev_gpr_write
)
3876 /* If the branch writes a register that the previous
3877 instruction reads, we can not swap. */
3878 prev_gpr_read
= gpr_read_mask (&history
[0]);
3879 if (gpr_write
& prev_gpr_read
)
3882 /* If one instruction sets a condition code and the
3883 other one uses a condition code, we can not swap. */
3884 pinfo
= ip
->insn_mo
->pinfo
;
3885 if ((pinfo
& INSN_READ_COND_CODE
)
3886 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3888 if ((pinfo
& INSN_WRITE_COND_CODE
)
3889 && (prev_pinfo
& INSN_READ_COND_CODE
))
3892 /* If the previous instruction uses the PC, we can not swap. */
3893 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3894 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3896 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3899 /* If the previous instruction has an incorrect size for a fixed
3900 branch delay slot in microMIPS mode, we cannot swap. */
3901 pinfo2
= ip
->insn_mo
->pinfo2
;
3902 if (mips_opts
.micromips
3903 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3904 && insn_length (history
) != 2)
3906 if (mips_opts
.micromips
3907 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3908 && insn_length (history
) != 4)
3911 /* On R5900 short loops need to be fixed by inserting a nop in
3912 the branch delay slots.
3913 A short loop can be terminated too early. */
3914 if (mips_opts
.arch
== CPU_R5900
3915 /* Check if instruction has a parameter, ignore "j $31". */
3916 && (address_expr
!= NULL
)
3917 /* Parameter must be 16 bit. */
3918 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
3919 /* Branch to same segment. */
3920 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
3921 /* Branch to same code fragment. */
3922 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
3923 /* Can only calculate branch offset if value is known. */
3924 && symbol_constant_p(address_expr
->X_add_symbol
)
3925 /* Check if branch is really conditional. */
3926 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
3927 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
3928 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
3931 /* Check if loop is shorter than 6 instructions including
3932 branch and delay slot. */
3933 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
3940 /* When the loop includes branches or jumps,
3941 it is not a short loop. */
3942 for (i
= 0; i
< (distance
/ 4); i
++)
3944 if ((history
[i
].cleared_p
)
3945 || delayed_branch_p(&history
[i
]))
3953 /* Insert nop after branch to fix short loop. */
3962 /* Decide how we should add IP to the instruction stream.
3963 ADDRESS_EXPR is an operand of the instruction to be used with
3966 static enum append_method
3967 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3968 bfd_reloc_code_real_type
*reloc_type
)
3970 unsigned long pinfo
;
3972 /* The relaxed version of a macro sequence must be inherently
3974 if (mips_relax
.sequence
== 2)
3977 /* We must not dabble with instructions in a ".set norerorder" block. */
3978 if (mips_opts
.noreorder
)
3981 /* Otherwise, it's our responsibility to fill branch delay slots. */
3982 if (delayed_branch_p (ip
))
3984 if (!branch_likely_p (ip
)
3985 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
3988 pinfo
= ip
->insn_mo
->pinfo
;
3989 if (mips_opts
.mips16
3990 && ISA_SUPPORTS_MIPS16E
3991 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3992 return APPEND_ADD_COMPACT
;
3994 return APPEND_ADD_WITH_NOP
;
4000 /* IP is a MIPS16 instruction whose opcode we have just changed.
4001 Point IP->insn_mo to the new opcode's definition. */
4004 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4006 const struct mips_opcode
*mo
, *end
;
4008 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4009 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4010 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4018 /* For microMIPS macros, we need to generate a local number label
4019 as the target of branches. */
4020 #define MICROMIPS_LABEL_CHAR '\037'
4021 static unsigned long micromips_target_label
;
4022 static char micromips_target_name
[32];
4025 micromips_label_name (void)
4027 char *p
= micromips_target_name
;
4028 char symbol_name_temporary
[24];
4036 l
= micromips_target_label
;
4037 #ifdef LOCAL_LABEL_PREFIX
4038 *p
++ = LOCAL_LABEL_PREFIX
;
4041 *p
++ = MICROMIPS_LABEL_CHAR
;
4044 symbol_name_temporary
[i
++] = l
% 10 + '0';
4049 *p
++ = symbol_name_temporary
[--i
];
4052 return micromips_target_name
;
4056 micromips_label_expr (expressionS
*label_expr
)
4058 label_expr
->X_op
= O_symbol
;
4059 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4060 label_expr
->X_add_number
= 0;
4064 micromips_label_inc (void)
4066 micromips_target_label
++;
4067 *micromips_target_name
= '\0';
4071 micromips_add_label (void)
4075 s
= colon (micromips_label_name ());
4076 micromips_label_inc ();
4077 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4079 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4085 /* If assembling microMIPS code, then return the microMIPS reloc
4086 corresponding to the requested one if any. Otherwise return
4087 the reloc unchanged. */
4089 static bfd_reloc_code_real_type
4090 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4092 static const bfd_reloc_code_real_type relocs
[][2] =
4094 /* Keep sorted incrementally by the left-hand key. */
4095 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4096 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4097 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4098 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4099 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4100 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4101 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4102 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4103 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4104 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4105 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4106 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4107 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4108 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4109 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4110 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4111 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4112 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4113 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4114 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4115 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4116 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4117 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4118 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4119 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4120 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4121 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4123 bfd_reloc_code_real_type r
;
4126 if (!mips_opts
.micromips
)
4128 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4134 return relocs
[i
][1];
4139 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4140 Return true on success, storing the resolved value in RESULT. */
4143 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4148 case BFD_RELOC_MIPS_HIGHEST
:
4149 case BFD_RELOC_MICROMIPS_HIGHEST
:
4150 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4153 case BFD_RELOC_MIPS_HIGHER
:
4154 case BFD_RELOC_MICROMIPS_HIGHER
:
4155 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4158 case BFD_RELOC_HI16_S
:
4159 case BFD_RELOC_MICROMIPS_HI16_S
:
4160 case BFD_RELOC_MIPS16_HI16_S
:
4161 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4164 case BFD_RELOC_HI16
:
4165 case BFD_RELOC_MICROMIPS_HI16
:
4166 case BFD_RELOC_MIPS16_HI16
:
4167 *result
= (operand
>> 16) & 0xffff;
4170 case BFD_RELOC_LO16
:
4171 case BFD_RELOC_MICROMIPS_LO16
:
4172 case BFD_RELOC_MIPS16_LO16
:
4173 *result
= operand
& 0xffff;
4176 case BFD_RELOC_UNUSED
:
4185 /* Output an instruction. IP is the instruction information.
4186 ADDRESS_EXPR is an operand of the instruction to be used with
4187 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4188 a macro expansion. */
4191 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4192 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4194 unsigned long prev_pinfo2
, pinfo
;
4195 bfd_boolean relaxed_branch
= FALSE
;
4196 enum append_method method
;
4197 bfd_boolean relax32
;
4200 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4201 fix_loongson2f (ip
);
4203 file_ase_mips16
|= mips_opts
.mips16
;
4204 file_ase_micromips
|= mips_opts
.micromips
;
4206 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4207 pinfo
= ip
->insn_mo
->pinfo
;
4209 if (mips_opts
.micromips
4211 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4212 && micromips_insn_length (ip
->insn_mo
) != 2)
4213 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4214 && micromips_insn_length (ip
->insn_mo
) != 4)))
4215 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4216 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4218 if (address_expr
== NULL
)
4220 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4221 && reloc_type
[1] == BFD_RELOC_UNUSED
4222 && reloc_type
[2] == BFD_RELOC_UNUSED
4223 && address_expr
->X_op
== O_constant
)
4225 switch (*reloc_type
)
4227 case BFD_RELOC_MIPS_JMP
:
4231 shift
= mips_opts
.micromips
? 1 : 2;
4232 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4233 as_bad (_("jump to misaligned address (0x%lx)"),
4234 (unsigned long) address_expr
->X_add_number
);
4235 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4241 case BFD_RELOC_MIPS16_JMP
:
4242 if ((address_expr
->X_add_number
& 3) != 0)
4243 as_bad (_("jump to misaligned address (0x%lx)"),
4244 (unsigned long) address_expr
->X_add_number
);
4246 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4247 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4248 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4252 case BFD_RELOC_16_PCREL_S2
:
4256 shift
= mips_opts
.micromips
? 1 : 2;
4257 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4258 as_bad (_("branch to misaligned address (0x%lx)"),
4259 (unsigned long) address_expr
->X_add_number
);
4260 if (!mips_relax_branch
)
4262 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4263 & ~((1 << (shift
+ 16)) - 1))
4264 as_bad (_("branch address range overflow (0x%lx)"),
4265 (unsigned long) address_expr
->X_add_number
);
4266 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4276 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4279 ip
->insn_opcode
|= value
& 0xffff;
4287 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4289 /* There are a lot of optimizations we could do that we don't.
4290 In particular, we do not, in general, reorder instructions.
4291 If you use gcc with optimization, it will reorder
4292 instructions and generally do much more optimization then we
4293 do here; repeating all that work in the assembler would only
4294 benefit hand written assembly code, and does not seem worth
4296 int nops
= (mips_optimize
== 0
4297 ? nops_for_insn (0, history
, NULL
)
4298 : nops_for_insn_or_target (0, history
, ip
));
4302 unsigned long old_frag_offset
;
4305 old_frag
= frag_now
;
4306 old_frag_offset
= frag_now_fix ();
4308 for (i
= 0; i
< nops
; i
++)
4309 add_fixed_insn (NOP_INSN
);
4310 insert_into_history (0, nops
, NOP_INSN
);
4314 listing_prev_line ();
4315 /* We may be at the start of a variant frag. In case we
4316 are, make sure there is enough space for the frag
4317 after the frags created by listing_prev_line. The
4318 argument to frag_grow here must be at least as large
4319 as the argument to all other calls to frag_grow in
4320 this file. We don't have to worry about being in the
4321 middle of a variant frag, because the variants insert
4322 all needed nop instructions themselves. */
4326 mips_move_text_labels ();
4328 #ifndef NO_ECOFF_DEBUGGING
4329 if (ECOFF_DEBUGGING
)
4330 ecoff_fix_loc (old_frag
, old_frag_offset
);
4334 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4338 /* Work out how many nops in prev_nop_frag are needed by IP,
4339 ignoring hazards generated by the first prev_nop_frag_since
4341 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4342 gas_assert (nops
<= prev_nop_frag_holds
);
4344 /* Enforce NOPS as a minimum. */
4345 if (nops
> prev_nop_frag_required
)
4346 prev_nop_frag_required
= nops
;
4348 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4350 /* Settle for the current number of nops. Update the history
4351 accordingly (for the benefit of any future .set reorder code). */
4352 prev_nop_frag
= NULL
;
4353 insert_into_history (prev_nop_frag_since
,
4354 prev_nop_frag_holds
, NOP_INSN
);
4358 /* Allow this instruction to replace one of the nops that was
4359 tentatively added to prev_nop_frag. */
4360 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4361 prev_nop_frag_holds
--;
4362 prev_nop_frag_since
++;
4366 method
= get_append_method (ip
, address_expr
, reloc_type
);
4367 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4370 /* The value passed to dwarf2_emit_insn is the distance between
4371 the beginning of the current instruction and the address that
4372 should be recorded in the debug tables. This is normally the
4375 For MIPS16/microMIPS debug info we want to use ISA-encoded
4376 addresses, so we use -1 for an address higher by one than the
4379 If the instruction produced is a branch that we will swap with
4380 the preceding instruction, then we add the displacement by which
4381 the branch will be moved backwards. This is more appropriate
4382 and for MIPS16/microMIPS code also prevents a debugger from
4383 placing a breakpoint in the middle of the branch (and corrupting
4384 code if software breakpoints are used). */
4385 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4388 relax32
= (mips_relax_branch
4389 /* Don't try branch relaxation within .set nomacro, or within
4390 .set noat if we use $at for PIC computations. If it turns
4391 out that the branch was out-of-range, we'll get an error. */
4392 && !mips_opts
.warn_about_macros
4393 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4394 /* Don't relax BPOSGE32/64 as they have no complementing
4396 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4398 if (!HAVE_CODE_COMPRESSION
4401 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4402 && delayed_branch_p (ip
))
4404 relaxed_branch
= TRUE
;
4405 add_relaxed_insn (ip
, (relaxed_branch_length
4407 uncond_branch_p (ip
) ? -1
4408 : branch_likely_p (ip
) ? 1
4412 uncond_branch_p (ip
),
4413 branch_likely_p (ip
),
4414 pinfo
& INSN_WRITE_GPR_31
,
4416 address_expr
->X_add_symbol
,
4417 address_expr
->X_add_number
);
4418 *reloc_type
= BFD_RELOC_UNUSED
;
4420 else if (mips_opts
.micromips
4422 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4423 || *reloc_type
> BFD_RELOC_UNUSED
)
4424 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4425 /* Don't try branch relaxation when users specify
4426 16-bit/32-bit instructions. */
4427 && !forced_insn_length
)
4429 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4430 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4431 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4432 int compact
= compact_branch_p (ip
);
4433 int al
= pinfo
& INSN_WRITE_GPR_31
;
4436 gas_assert (address_expr
!= NULL
);
4437 gas_assert (!mips_relax
.sequence
);
4439 relaxed_branch
= TRUE
;
4440 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4441 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4442 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4444 address_expr
->X_add_symbol
,
4445 address_expr
->X_add_number
);
4446 *reloc_type
= BFD_RELOC_UNUSED
;
4448 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4450 /* We need to set up a variant frag. */
4451 gas_assert (address_expr
!= NULL
);
4452 add_relaxed_insn (ip
, 4, 0,
4454 (*reloc_type
- BFD_RELOC_UNUSED
,
4455 forced_insn_length
== 2, forced_insn_length
== 4,
4456 delayed_branch_p (&history
[0]),
4457 history
[0].mips16_absolute_jump_p
),
4458 make_expr_symbol (address_expr
), 0);
4460 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4462 if (!delayed_branch_p (ip
))
4463 /* Make sure there is enough room to swap this instruction with
4464 a following jump instruction. */
4466 add_fixed_insn (ip
);
4470 if (mips_opts
.mips16
4471 && mips_opts
.noreorder
4472 && delayed_branch_p (&history
[0]))
4473 as_warn (_("extended instruction in delay slot"));
4475 if (mips_relax
.sequence
)
4477 /* If we've reached the end of this frag, turn it into a variant
4478 frag and record the information for the instructions we've
4480 if (frag_room () < 4)
4481 relax_close_frag ();
4482 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4485 if (mips_relax
.sequence
!= 2)
4487 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4488 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4489 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4490 mips_macro_warning
.insns
[0]++;
4492 if (mips_relax
.sequence
!= 1)
4494 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4495 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4496 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4497 mips_macro_warning
.insns
[1]++;
4500 if (mips_opts
.mips16
)
4503 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4505 add_fixed_insn (ip
);
4508 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4510 bfd_reloc_code_real_type final_type
[3];
4511 reloc_howto_type
*howto0
;
4512 reloc_howto_type
*howto
;
4515 /* Perform any necessary conversion to microMIPS relocations
4516 and find out how many relocations there actually are. */
4517 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4518 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4520 /* In a compound relocation, it is the final (outermost)
4521 operator that determines the relocated field. */
4522 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4526 /* To reproduce this failure try assembling gas/testsuites/
4527 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4529 as_bad (_("Unsupported MIPS relocation number %d"),
4531 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4535 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4536 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4537 bfd_get_reloc_size (howto
),
4539 howto0
&& howto0
->pc_relative
,
4542 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4543 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4544 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4546 /* These relocations can have an addend that won't fit in
4547 4 octets for 64bit assembly. */
4549 && ! howto
->partial_inplace
4550 && (reloc_type
[0] == BFD_RELOC_16
4551 || reloc_type
[0] == BFD_RELOC_32
4552 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4553 || reloc_type
[0] == BFD_RELOC_GPREL16
4554 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4555 || reloc_type
[0] == BFD_RELOC_GPREL32
4556 || reloc_type
[0] == BFD_RELOC_64
4557 || reloc_type
[0] == BFD_RELOC_CTOR
4558 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4559 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4560 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4561 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4562 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4563 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4564 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4565 || hi16_reloc_p (reloc_type
[0])
4566 || lo16_reloc_p (reloc_type
[0])))
4567 ip
->fixp
[0]->fx_no_overflow
= 1;
4569 /* These relocations can have an addend that won't fit in 2 octets. */
4570 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4571 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4572 ip
->fixp
[0]->fx_no_overflow
= 1;
4574 if (mips_relax
.sequence
)
4576 if (mips_relax
.first_fixup
== 0)
4577 mips_relax
.first_fixup
= ip
->fixp
[0];
4579 else if (reloc_needs_lo_p (*reloc_type
))
4581 struct mips_hi_fixup
*hi_fixup
;
4583 /* Reuse the last entry if it already has a matching %lo. */
4584 hi_fixup
= mips_hi_fixup_list
;
4586 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4588 hi_fixup
= ((struct mips_hi_fixup
*)
4589 xmalloc (sizeof (struct mips_hi_fixup
)));
4590 hi_fixup
->next
= mips_hi_fixup_list
;
4591 mips_hi_fixup_list
= hi_fixup
;
4593 hi_fixup
->fixp
= ip
->fixp
[0];
4594 hi_fixup
->seg
= now_seg
;
4597 /* Add fixups for the second and third relocations, if given.
4598 Note that the ABI allows the second relocation to be
4599 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4600 moment we only use RSS_UNDEF, but we could add support
4601 for the others if it ever becomes necessary. */
4602 for (i
= 1; i
< 3; i
++)
4603 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4605 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4606 ip
->fixp
[0]->fx_size
, NULL
, 0,
4607 FALSE
, final_type
[i
]);
4609 /* Use fx_tcbit to mark compound relocs. */
4610 ip
->fixp
[0]->fx_tcbit
= 1;
4611 ip
->fixp
[i
]->fx_tcbit
= 1;
4616 /* Update the register mask information. */
4617 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4618 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4623 insert_into_history (0, 1, ip
);
4626 case APPEND_ADD_WITH_NOP
:
4628 struct mips_cl_insn
*nop
;
4630 insert_into_history (0, 1, ip
);
4631 nop
= get_delay_slot_nop (ip
);
4632 add_fixed_insn (nop
);
4633 insert_into_history (0, 1, nop
);
4634 if (mips_relax
.sequence
)
4635 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4639 case APPEND_ADD_COMPACT
:
4640 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4641 gas_assert (mips_opts
.mips16
);
4642 ip
->insn_opcode
|= 0x0080;
4643 find_altered_mips16_opcode (ip
);
4645 insert_into_history (0, 1, ip
);
4650 struct mips_cl_insn delay
= history
[0];
4651 if (mips_opts
.mips16
)
4653 know (delay
.frag
== ip
->frag
);
4654 move_insn (ip
, delay
.frag
, delay
.where
);
4655 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4657 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4659 /* Add the delay slot instruction to the end of the
4660 current frag and shrink the fixed part of the
4661 original frag. If the branch occupies the tail of
4662 the latter, move it backwards to cover the gap. */
4663 delay
.frag
->fr_fix
-= branch_disp
;
4664 if (delay
.frag
== ip
->frag
)
4665 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4666 add_fixed_insn (&delay
);
4670 move_insn (&delay
, ip
->frag
,
4671 ip
->where
- branch_disp
+ insn_length (ip
));
4672 move_insn (ip
, history
[0].frag
, history
[0].where
);
4676 insert_into_history (0, 1, &delay
);
4681 /* If we have just completed an unconditional branch, clear the history. */
4682 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4683 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4687 mips_no_prev_insn ();
4689 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4690 history
[i
].cleared_p
= 1;
4693 /* We need to emit a label at the end of branch-likely macros. */
4694 if (emit_branch_likely_macro
)
4696 emit_branch_likely_macro
= FALSE
;
4697 micromips_add_label ();
4700 /* We just output an insn, so the next one doesn't have a label. */
4701 mips_clear_insn_labels ();
4704 /* Forget that there was any previous instruction or label.
4705 When BRANCH is true, the branch history is also flushed. */
4708 mips_no_prev_insn (void)
4710 prev_nop_frag
= NULL
;
4711 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4712 mips_clear_insn_labels ();
4715 /* This function must be called before we emit something other than
4716 instructions. It is like mips_no_prev_insn except that it inserts
4717 any NOPS that might be needed by previous instructions. */
4720 mips_emit_delays (void)
4722 if (! mips_opts
.noreorder
)
4724 int nops
= nops_for_insn (0, history
, NULL
);
4728 add_fixed_insn (NOP_INSN
);
4729 mips_move_text_labels ();
4732 mips_no_prev_insn ();
4735 /* Start a (possibly nested) noreorder block. */
4738 start_noreorder (void)
4740 if (mips_opts
.noreorder
== 0)
4745 /* None of the instructions before the .set noreorder can be moved. */
4746 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4747 history
[i
].fixed_p
= 1;
4749 /* Insert any nops that might be needed between the .set noreorder
4750 block and the previous instructions. We will later remove any
4751 nops that turn out not to be needed. */
4752 nops
= nops_for_insn (0, history
, NULL
);
4755 if (mips_optimize
!= 0)
4757 /* Record the frag which holds the nop instructions, so
4758 that we can remove them if we don't need them. */
4759 frag_grow (nops
* NOP_INSN_SIZE
);
4760 prev_nop_frag
= frag_now
;
4761 prev_nop_frag_holds
= nops
;
4762 prev_nop_frag_required
= 0;
4763 prev_nop_frag_since
= 0;
4766 for (; nops
> 0; --nops
)
4767 add_fixed_insn (NOP_INSN
);
4769 /* Move on to a new frag, so that it is safe to simply
4770 decrease the size of prev_nop_frag. */
4771 frag_wane (frag_now
);
4773 mips_move_text_labels ();
4775 mips_mark_labels ();
4776 mips_clear_insn_labels ();
4778 mips_opts
.noreorder
++;
4779 mips_any_noreorder
= 1;
4782 /* End a nested noreorder block. */
4785 end_noreorder (void)
4787 mips_opts
.noreorder
--;
4788 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4790 /* Commit to inserting prev_nop_frag_required nops and go back to
4791 handling nop insertion the .set reorder way. */
4792 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4794 insert_into_history (prev_nop_frag_since
,
4795 prev_nop_frag_required
, NOP_INSN
);
4796 prev_nop_frag
= NULL
;
4800 /* Set up global variables for the start of a new macro. */
4805 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4806 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4807 sizeof (mips_macro_warning
.first_insn_sizes
));
4808 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4809 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4810 && delayed_branch_p (&history
[0]));
4811 switch (history
[0].insn_mo
->pinfo2
4812 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4814 case INSN2_BRANCH_DELAY_32BIT
:
4815 mips_macro_warning
.delay_slot_length
= 4;
4817 case INSN2_BRANCH_DELAY_16BIT
:
4818 mips_macro_warning
.delay_slot_length
= 2;
4821 mips_macro_warning
.delay_slot_length
= 0;
4824 mips_macro_warning
.first_frag
= NULL
;
4827 /* Given that a macro is longer than one instruction or of the wrong size,
4828 return the appropriate warning for it. Return null if no warning is
4829 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4830 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4831 and RELAX_NOMACRO. */
4834 macro_warning (relax_substateT subtype
)
4836 if (subtype
& RELAX_DELAY_SLOT
)
4837 return _("Macro instruction expanded into multiple instructions"
4838 " in a branch delay slot");
4839 else if (subtype
& RELAX_NOMACRO
)
4840 return _("Macro instruction expanded into multiple instructions");
4841 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4842 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4843 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4844 ? _("Macro instruction expanded into a wrong size instruction"
4845 " in a 16-bit branch delay slot")
4846 : _("Macro instruction expanded into a wrong size instruction"
4847 " in a 32-bit branch delay slot"));
4852 /* Finish up a macro. Emit warnings as appropriate. */
4857 /* Relaxation warning flags. */
4858 relax_substateT subtype
= 0;
4860 /* Check delay slot size requirements. */
4861 if (mips_macro_warning
.delay_slot_length
== 2)
4862 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4863 if (mips_macro_warning
.delay_slot_length
!= 0)
4865 if (mips_macro_warning
.delay_slot_length
4866 != mips_macro_warning
.first_insn_sizes
[0])
4867 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4868 if (mips_macro_warning
.delay_slot_length
4869 != mips_macro_warning
.first_insn_sizes
[1])
4870 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4873 /* Check instruction count requirements. */
4874 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4876 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4877 subtype
|= RELAX_SECOND_LONGER
;
4878 if (mips_opts
.warn_about_macros
)
4879 subtype
|= RELAX_NOMACRO
;
4880 if (mips_macro_warning
.delay_slot_p
)
4881 subtype
|= RELAX_DELAY_SLOT
;
4884 /* If both alternatives fail to fill a delay slot correctly,
4885 emit the warning now. */
4886 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4887 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4892 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4893 | RELAX_DELAY_SLOT_SIZE_FIRST
4894 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4895 msg
= macro_warning (s
);
4897 as_warn ("%s", msg
);
4901 /* If both implementations are longer than 1 instruction, then emit the
4903 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4908 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4909 msg
= macro_warning (s
);
4911 as_warn ("%s", msg
);
4915 /* If any flags still set, then one implementation might need a warning
4916 and the other either will need one of a different kind or none at all.
4917 Pass any remaining flags over to relaxation. */
4918 if (mips_macro_warning
.first_frag
!= NULL
)
4919 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4922 /* Instruction operand formats used in macros that vary between
4923 standard MIPS and microMIPS code. */
4925 static const char * const brk_fmt
[2] = { "c", "mF" };
4926 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4927 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4928 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4929 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4930 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4931 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4932 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4934 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4935 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4936 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4937 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4938 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4939 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4940 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4941 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4943 /* Read a macro's relocation codes from *ARGS and store them in *R.
4944 The first argument in *ARGS will be either the code for a single
4945 relocation or -1 followed by the three codes that make up a
4946 composite relocation. */
4949 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4953 next
= va_arg (*args
, int);
4955 r
[0] = (bfd_reloc_code_real_type
) next
;
4957 for (i
= 0; i
< 3; i
++)
4958 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4961 /* Build an instruction created by a macro expansion. This is passed
4962 a pointer to the count of instructions created so far, an
4963 expression, the name of the instruction to build, an operand format
4964 string, and corresponding arguments. */
4967 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4969 const struct mips_opcode
*mo
= NULL
;
4970 bfd_reloc_code_real_type r
[3];
4971 const struct mips_opcode
*amo
;
4972 struct hash_control
*hash
;
4973 struct mips_cl_insn insn
;
4976 va_start (args
, fmt
);
4978 if (mips_opts
.mips16
)
4980 mips16_macro_build (ep
, name
, fmt
, &args
);
4985 r
[0] = BFD_RELOC_UNUSED
;
4986 r
[1] = BFD_RELOC_UNUSED
;
4987 r
[2] = BFD_RELOC_UNUSED
;
4988 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4989 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4991 gas_assert (strcmp (name
, amo
->name
) == 0);
4995 /* Search until we get a match for NAME. It is assumed here that
4996 macros will never generate MDMX, MIPS-3D, or MT instructions.
4997 We try to match an instruction that fulfils the branch delay
4998 slot instruction length requirement (if any) of the previous
4999 instruction. While doing this we record the first instruction
5000 seen that matches all the other conditions and use it anyway
5001 if the requirement cannot be met; we will issue an appropriate
5002 warning later on. */
5003 if (strcmp (fmt
, amo
->args
) == 0
5004 && amo
->pinfo
!= INSN_MACRO
5005 && is_opcode_valid (amo
)
5006 && is_size_valid (amo
))
5008 if (is_delay_slot_valid (amo
))
5018 gas_assert (amo
->name
);
5020 while (strcmp (name
, amo
->name
) == 0);
5023 create_insn (&insn
, mo
);
5041 INSERT_OPERAND (mips_opts
.micromips
,
5042 EXTLSB
, insn
, va_arg (args
, int));
5047 /* Note that in the macro case, these arguments are already
5048 in MSB form. (When handling the instruction in the
5049 non-macro case, these arguments are sizes from which
5050 MSB values must be calculated.) */
5051 INSERT_OPERAND (mips_opts
.micromips
,
5052 INSMSB
, insn
, va_arg (args
, int));
5056 gas_assert (!mips_opts
.micromips
);
5057 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5063 /* Note that in the macro case, these arguments are already
5064 in MSBD form. (When handling the instruction in the
5065 non-macro case, these arguments are sizes from which
5066 MSBD values must be calculated.) */
5067 INSERT_OPERAND (mips_opts
.micromips
,
5068 EXTMSBD
, insn
, va_arg (args
, int));
5072 gas_assert (!mips_opts
.micromips
);
5073 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5082 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5086 gas_assert (mips_opts
.micromips
);
5090 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5094 gas_assert (!mips_opts
.micromips
);
5095 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5099 gas_assert (!mips_opts
.micromips
);
5101 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5105 if (mips_opts
.micromips
)
5106 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5108 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5112 gas_assert (!mips_opts
.micromips
);
5114 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5118 gas_assert (!mips_opts
.micromips
);
5120 int tmp
= va_arg (args
, int);
5122 INSERT_OPERAND (0, RT
, insn
, tmp
);
5123 INSERT_OPERAND (0, RD
, insn
, tmp
);
5129 gas_assert (!mips_opts
.micromips
);
5130 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5137 INSERT_OPERAND (mips_opts
.micromips
,
5138 SHAMT
, insn
, va_arg (args
, int));
5142 gas_assert (!mips_opts
.micromips
);
5143 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5147 gas_assert (!mips_opts
.micromips
);
5148 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5152 gas_assert (!mips_opts
.micromips
);
5153 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5157 gas_assert (!mips_opts
.micromips
);
5158 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5165 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5170 macro_read_relocs (&args
, r
);
5171 gas_assert (*r
== BFD_RELOC_GPREL16
5172 || *r
== BFD_RELOC_MIPS_HIGHER
5173 || *r
== BFD_RELOC_HI16_S
5174 || *r
== BFD_RELOC_LO16
5175 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5179 macro_read_relocs (&args
, r
);
5183 macro_read_relocs (&args
, r
);
5184 gas_assert (ep
!= NULL
5185 && (ep
->X_op
== O_constant
5186 || (ep
->X_op
== O_symbol
5187 && (*r
== BFD_RELOC_MIPS_HIGHEST
5188 || *r
== BFD_RELOC_HI16_S
5189 || *r
== BFD_RELOC_HI16
5190 || *r
== BFD_RELOC_GPREL16
5191 || *r
== BFD_RELOC_MIPS_GOT_HI16
5192 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5196 gas_assert (ep
!= NULL
);
5199 * This allows macro() to pass an immediate expression for
5200 * creating short branches without creating a symbol.
5202 * We don't allow branch relaxation for these branches, as
5203 * they should only appear in ".set nomacro" anyway.
5205 if (ep
->X_op
== O_constant
)
5207 /* For microMIPS we always use relocations for branches.
5208 So we should not resolve immediate values. */
5209 gas_assert (!mips_opts
.micromips
);
5211 if ((ep
->X_add_number
& 3) != 0)
5212 as_bad (_("branch to misaligned address (0x%lx)"),
5213 (unsigned long) ep
->X_add_number
);
5214 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5215 as_bad (_("branch address range overflow (0x%lx)"),
5216 (unsigned long) ep
->X_add_number
);
5217 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5221 *r
= BFD_RELOC_16_PCREL_S2
;
5225 gas_assert (ep
!= NULL
);
5226 *r
= BFD_RELOC_MIPS_JMP
;
5230 gas_assert (!mips_opts
.micromips
);
5231 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5235 INSERT_OPERAND (mips_opts
.micromips
,
5236 CACHE
, insn
, va_arg (args
, unsigned long));
5240 gas_assert (mips_opts
.micromips
);
5241 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5245 gas_assert (mips_opts
.micromips
);
5246 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5250 INSERT_OPERAND (mips_opts
.micromips
,
5251 3BITPOS
, insn
, va_arg (args
, unsigned int));
5255 INSERT_OPERAND (mips_opts
.micromips
,
5256 OFFSET12
, insn
, va_arg (args
, unsigned long));
5260 gas_assert (mips_opts
.micromips
);
5261 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5264 case 'm': /* Opcode extension character. */
5265 gas_assert (mips_opts
.micromips
);
5269 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5273 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5277 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5291 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5293 append_insn (&insn
, ep
, r
, TRUE
);
5297 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5300 struct mips_opcode
*mo
;
5301 struct mips_cl_insn insn
;
5302 bfd_reloc_code_real_type r
[3]
5303 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5305 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5307 gas_assert (strcmp (name
, mo
->name
) == 0);
5309 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5312 gas_assert (mo
->name
);
5313 gas_assert (strcmp (name
, mo
->name
) == 0);
5316 create_insn (&insn
, mo
);
5334 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5339 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5343 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5347 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5357 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5364 regno
= va_arg (*args
, int);
5365 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5366 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5389 gas_assert (ep
!= NULL
);
5391 if (ep
->X_op
!= O_constant
)
5392 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5393 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5395 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5397 *r
= BFD_RELOC_UNUSED
;
5403 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5410 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5412 append_insn (&insn
, ep
, r
, TRUE
);
5416 * Sign-extend 32-bit mode constants that have bit 31 set and all
5417 * higher bits unset.
5420 normalize_constant_expr (expressionS
*ex
)
5422 if (ex
->X_op
== O_constant
5423 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5424 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5429 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5430 * all higher bits unset.
5433 normalize_address_expr (expressionS
*ex
)
5435 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5436 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5437 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5438 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5443 * Generate a "jalr" instruction with a relocation hint to the called
5444 * function. This occurs in NewABI PIC code.
5447 macro_build_jalr (expressionS
*ep
, int cprestore
)
5449 static const bfd_reloc_code_real_type jalr_relocs
[2]
5450 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5451 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5455 if (MIPS_JALR_HINT_P (ep
))
5460 if (mips_opts
.micromips
)
5462 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5463 if (MIPS_JALR_HINT_P (ep
)
5464 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5465 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5467 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5470 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5471 if (MIPS_JALR_HINT_P (ep
))
5472 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5476 * Generate a "lui" instruction.
5479 macro_build_lui (expressionS
*ep
, int regnum
)
5481 gas_assert (! mips_opts
.mips16
);
5483 if (ep
->X_op
!= O_constant
)
5485 gas_assert (ep
->X_op
== O_symbol
);
5486 /* _gp_disp is a special case, used from s_cpload.
5487 __gnu_local_gp is used if mips_no_shared. */
5488 gas_assert (mips_pic
== NO_PIC
5490 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5491 || (! mips_in_shared
5492 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5493 "__gnu_local_gp") == 0));
5496 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5499 /* Generate a sequence of instructions to do a load or store from a constant
5500 offset off of a base register (breg) into/from a target register (treg),
5501 using AT if necessary. */
5503 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5504 int treg
, int breg
, int dbl
)
5506 gas_assert (ep
->X_op
== O_constant
);
5508 /* Sign-extending 32-bit constants makes their handling easier. */
5510 normalize_constant_expr (ep
);
5512 /* Right now, this routine can only handle signed 32-bit constants. */
5513 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5514 as_warn (_("operand overflow"));
5516 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5518 /* Signed 16-bit offset will fit in the op. Easy! */
5519 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5523 /* 32-bit offset, need multiple instructions and AT, like:
5524 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5525 addu $tempreg,$tempreg,$breg
5526 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5527 to handle the complete offset. */
5528 macro_build_lui (ep
, AT
);
5529 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5530 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5533 as_bad (_("Macro used $at after \".set noat\""));
5538 * Generates code to set the $at register to true (one)
5539 * if reg is less than the immediate expression.
5542 set_at (int reg
, int unsignedp
)
5544 if (imm_expr
.X_op
== O_constant
5545 && imm_expr
.X_add_number
>= -0x8000
5546 && imm_expr
.X_add_number
< 0x8000)
5547 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5548 AT
, reg
, BFD_RELOC_LO16
);
5551 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5552 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5556 /* Warn if an expression is not a constant. */
5559 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5561 if (ex
->X_op
== O_big
)
5562 as_bad (_("unsupported large constant"));
5563 else if (ex
->X_op
!= O_constant
)
5564 as_bad (_("Instruction %s requires absolute expression"),
5567 if (HAVE_32BIT_GPRS
)
5568 normalize_constant_expr (ex
);
5571 /* Count the leading zeroes by performing a binary chop. This is a
5572 bulky bit of source, but performance is a LOT better for the
5573 majority of values than a simple loop to count the bits:
5574 for (lcnt = 0; (lcnt < 32); lcnt++)
5575 if ((v) & (1 << (31 - lcnt)))
5577 However it is not code size friendly, and the gain will drop a bit
5578 on certain cached systems.
5580 #define COUNT_TOP_ZEROES(v) \
5581 (((v) & ~0xffff) == 0 \
5582 ? ((v) & ~0xff) == 0 \
5583 ? ((v) & ~0xf) == 0 \
5584 ? ((v) & ~0x3) == 0 \
5585 ? ((v) & ~0x1) == 0 \
5590 : ((v) & ~0x7) == 0 \
5593 : ((v) & ~0x3f) == 0 \
5594 ? ((v) & ~0x1f) == 0 \
5597 : ((v) & ~0x7f) == 0 \
5600 : ((v) & ~0xfff) == 0 \
5601 ? ((v) & ~0x3ff) == 0 \
5602 ? ((v) & ~0x1ff) == 0 \
5605 : ((v) & ~0x7ff) == 0 \
5608 : ((v) & ~0x3fff) == 0 \
5609 ? ((v) & ~0x1fff) == 0 \
5612 : ((v) & ~0x7fff) == 0 \
5615 : ((v) & ~0xffffff) == 0 \
5616 ? ((v) & ~0xfffff) == 0 \
5617 ? ((v) & ~0x3ffff) == 0 \
5618 ? ((v) & ~0x1ffff) == 0 \
5621 : ((v) & ~0x7ffff) == 0 \
5624 : ((v) & ~0x3fffff) == 0 \
5625 ? ((v) & ~0x1fffff) == 0 \
5628 : ((v) & ~0x7fffff) == 0 \
5631 : ((v) & ~0xfffffff) == 0 \
5632 ? ((v) & ~0x3ffffff) == 0 \
5633 ? ((v) & ~0x1ffffff) == 0 \
5636 : ((v) & ~0x7ffffff) == 0 \
5639 : ((v) & ~0x3fffffff) == 0 \
5640 ? ((v) & ~0x1fffffff) == 0 \
5643 : ((v) & ~0x7fffffff) == 0 \
5648 * This routine generates the least number of instructions necessary to load
5649 * an absolute expression value into a register.
5652 load_register (int reg
, expressionS
*ep
, int dbl
)
5655 expressionS hi32
, lo32
;
5657 if (ep
->X_op
!= O_big
)
5659 gas_assert (ep
->X_op
== O_constant
);
5661 /* Sign-extending 32-bit constants makes their handling easier. */
5663 normalize_constant_expr (ep
);
5665 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5667 /* We can handle 16 bit signed values with an addiu to
5668 $zero. No need to ever use daddiu here, since $zero and
5669 the result are always correct in 32 bit mode. */
5670 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5673 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5675 /* We can handle 16 bit unsigned values with an ori to
5677 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5680 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5682 /* 32 bit values require an lui. */
5683 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5684 if ((ep
->X_add_number
& 0xffff) != 0)
5685 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5690 /* The value is larger than 32 bits. */
5692 if (!dbl
|| HAVE_32BIT_GPRS
)
5696 sprintf_vma (value
, ep
->X_add_number
);
5697 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5698 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5702 if (ep
->X_op
!= O_big
)
5705 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5706 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5707 hi32
.X_add_number
&= 0xffffffff;
5709 lo32
.X_add_number
&= 0xffffffff;
5713 gas_assert (ep
->X_add_number
> 2);
5714 if (ep
->X_add_number
== 3)
5715 generic_bignum
[3] = 0;
5716 else if (ep
->X_add_number
> 4)
5717 as_bad (_("Number larger than 64 bits"));
5718 lo32
.X_op
= O_constant
;
5719 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5720 hi32
.X_op
= O_constant
;
5721 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5724 if (hi32
.X_add_number
== 0)
5729 unsigned long hi
, lo
;
5731 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5733 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5735 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5738 if (lo32
.X_add_number
& 0x80000000)
5740 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5741 if (lo32
.X_add_number
& 0xffff)
5742 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5747 /* Check for 16bit shifted constant. We know that hi32 is
5748 non-zero, so start the mask on the first bit of the hi32
5753 unsigned long himask
, lomask
;
5757 himask
= 0xffff >> (32 - shift
);
5758 lomask
= (0xffff << shift
) & 0xffffffff;
5762 himask
= 0xffff << (shift
- 32);
5765 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5766 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5770 tmp
.X_op
= O_constant
;
5772 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5773 | (lo32
.X_add_number
>> shift
));
5775 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5776 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5777 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5778 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5783 while (shift
<= (64 - 16));
5785 /* Find the bit number of the lowest one bit, and store the
5786 shifted value in hi/lo. */
5787 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5788 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5792 while ((lo
& 1) == 0)
5797 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5803 while ((hi
& 1) == 0)
5812 /* Optimize if the shifted value is a (power of 2) - 1. */
5813 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5814 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5816 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5821 /* This instruction will set the register to be all
5823 tmp
.X_op
= O_constant
;
5824 tmp
.X_add_number
= (offsetT
) -1;
5825 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5829 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5830 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5832 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5833 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5838 /* Sign extend hi32 before calling load_register, because we can
5839 generally get better code when we load a sign extended value. */
5840 if ((hi32
.X_add_number
& 0x80000000) != 0)
5841 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5842 load_register (reg
, &hi32
, 0);
5845 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5849 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5857 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5859 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5860 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5866 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5870 mid16
.X_add_number
>>= 16;
5871 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5872 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5875 if ((lo32
.X_add_number
& 0xffff) != 0)
5876 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5880 load_delay_nop (void)
5882 if (!gpr_interlocks
)
5883 macro_build (NULL
, "nop", "");
5886 /* Load an address into a register. */
5889 load_address (int reg
, expressionS
*ep
, int *used_at
)
5891 if (ep
->X_op
!= O_constant
5892 && ep
->X_op
!= O_symbol
)
5894 as_bad (_("expression too complex"));
5895 ep
->X_op
= O_constant
;
5898 if (ep
->X_op
== O_constant
)
5900 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5904 if (mips_pic
== NO_PIC
)
5906 /* If this is a reference to a GP relative symbol, we want
5907 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5909 lui $reg,<sym> (BFD_RELOC_HI16_S)
5910 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5911 If we have an addend, we always use the latter form.
5913 With 64bit address space and a usable $at we want
5914 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5915 lui $at,<sym> (BFD_RELOC_HI16_S)
5916 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5917 daddiu $at,<sym> (BFD_RELOC_LO16)
5921 If $at is already in use, we use a path which is suboptimal
5922 on superscalar processors.
5923 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5924 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5926 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5928 daddiu $reg,<sym> (BFD_RELOC_LO16)
5930 For GP relative symbols in 64bit address space we can use
5931 the same sequence as in 32bit address space. */
5932 if (HAVE_64BIT_SYMBOLS
)
5934 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5935 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5937 relax_start (ep
->X_add_symbol
);
5938 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5939 mips_gp_register
, BFD_RELOC_GPREL16
);
5943 if (*used_at
== 0 && mips_opts
.at
)
5945 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5946 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5947 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5948 BFD_RELOC_MIPS_HIGHER
);
5949 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5950 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5951 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5956 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5957 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5958 BFD_RELOC_MIPS_HIGHER
);
5959 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5960 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5961 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5962 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5965 if (mips_relax
.sequence
)
5970 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5971 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5973 relax_start (ep
->X_add_symbol
);
5974 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5975 mips_gp_register
, BFD_RELOC_GPREL16
);
5978 macro_build_lui (ep
, reg
);
5979 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5980 reg
, reg
, BFD_RELOC_LO16
);
5981 if (mips_relax
.sequence
)
5985 else if (!mips_big_got
)
5989 /* If this is a reference to an external symbol, we want
5990 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5992 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5995 If there is a constant, it must be added in after.
5997 If we have NewABI, we want
5998 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5999 unless we're referencing a global symbol with a non-zero
6000 offset, in which case cst must be added separately. */
6003 if (ep
->X_add_number
)
6005 ex
.X_add_number
= ep
->X_add_number
;
6006 ep
->X_add_number
= 0;
6007 relax_start (ep
->X_add_symbol
);
6008 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6009 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6010 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6012 ex
.X_op
= O_constant
;
6013 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6014 reg
, reg
, BFD_RELOC_LO16
);
6015 ep
->X_add_number
= ex
.X_add_number
;
6018 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6019 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6020 if (mips_relax
.sequence
)
6025 ex
.X_add_number
= ep
->X_add_number
;
6026 ep
->X_add_number
= 0;
6027 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6028 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6030 relax_start (ep
->X_add_symbol
);
6032 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6036 if (ex
.X_add_number
!= 0)
6038 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6039 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6040 ex
.X_op
= O_constant
;
6041 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6042 reg
, reg
, BFD_RELOC_LO16
);
6046 else if (mips_big_got
)
6050 /* This is the large GOT case. If this is a reference to an
6051 external symbol, we want
6052 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6054 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6056 Otherwise, for a reference to a local symbol in old ABI, we want
6057 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6059 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6060 If there is a constant, it must be added in after.
6062 In the NewABI, for local symbols, with or without offsets, we want:
6063 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6064 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6068 ex
.X_add_number
= ep
->X_add_number
;
6069 ep
->X_add_number
= 0;
6070 relax_start (ep
->X_add_symbol
);
6071 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6073 reg
, reg
, mips_gp_register
);
6074 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6075 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6076 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6077 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6078 else if (ex
.X_add_number
)
6080 ex
.X_op
= O_constant
;
6081 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6085 ep
->X_add_number
= ex
.X_add_number
;
6087 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6088 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6089 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6090 BFD_RELOC_MIPS_GOT_OFST
);
6095 ex
.X_add_number
= ep
->X_add_number
;
6096 ep
->X_add_number
= 0;
6097 relax_start (ep
->X_add_symbol
);
6098 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6099 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6100 reg
, reg
, mips_gp_register
);
6101 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6102 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6104 if (reg_needs_delay (mips_gp_register
))
6106 /* We need a nop before loading from $gp. This special
6107 check is required because the lui which starts the main
6108 instruction stream does not refer to $gp, and so will not
6109 insert the nop which may be required. */
6110 macro_build (NULL
, "nop", "");
6112 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6113 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6115 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6119 if (ex
.X_add_number
!= 0)
6121 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6122 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6123 ex
.X_op
= O_constant
;
6124 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6132 if (!mips_opts
.at
&& *used_at
== 1)
6133 as_bad (_("Macro used $at after \".set noat\""));
6136 /* Move the contents of register SOURCE into register DEST. */
6139 move_register (int dest
, int source
)
6141 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6142 instruction specifically requires a 32-bit one. */
6143 if (mips_opts
.micromips
6144 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6145 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6147 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6151 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6152 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6153 The two alternatives are:
6155 Global symbol Local sybmol
6156 ------------- ------------
6157 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6159 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6161 load_got_offset emits the first instruction and add_got_offset
6162 emits the second for a 16-bit offset or add_got_offset_hilo emits
6163 a sequence to add a 32-bit offset using a scratch register. */
6166 load_got_offset (int dest
, expressionS
*local
)
6171 global
.X_add_number
= 0;
6173 relax_start (local
->X_add_symbol
);
6174 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6175 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6177 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6178 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6183 add_got_offset (int dest
, expressionS
*local
)
6187 global
.X_op
= O_constant
;
6188 global
.X_op_symbol
= NULL
;
6189 global
.X_add_symbol
= NULL
;
6190 global
.X_add_number
= local
->X_add_number
;
6192 relax_start (local
->X_add_symbol
);
6193 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6194 dest
, dest
, BFD_RELOC_LO16
);
6196 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6201 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6204 int hold_mips_optimize
;
6206 global
.X_op
= O_constant
;
6207 global
.X_op_symbol
= NULL
;
6208 global
.X_add_symbol
= NULL
;
6209 global
.X_add_number
= local
->X_add_number
;
6211 relax_start (local
->X_add_symbol
);
6212 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6214 /* Set mips_optimize around the lui instruction to avoid
6215 inserting an unnecessary nop after the lw. */
6216 hold_mips_optimize
= mips_optimize
;
6218 macro_build_lui (&global
, tmp
);
6219 mips_optimize
= hold_mips_optimize
;
6220 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6223 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6226 /* Emit a sequence of instructions to emulate a branch likely operation.
6227 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6228 is its complementing branch with the original condition negated.
6229 CALL is set if the original branch specified the link operation.
6230 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6232 Code like this is produced in the noreorder mode:
6237 delay slot (executed only if branch taken)
6245 delay slot (executed only if branch taken)
6248 In the reorder mode the delay slot would be filled with a nop anyway,
6249 so code produced is simply:
6254 This function is used when producing code for the microMIPS ASE that
6255 does not implement branch likely instructions in hardware. */
6258 macro_build_branch_likely (const char *br
, const char *brneg
,
6259 int call
, expressionS
*ep
, const char *fmt
,
6260 unsigned int sreg
, unsigned int treg
)
6262 int noreorder
= mips_opts
.noreorder
;
6265 gas_assert (mips_opts
.micromips
);
6269 micromips_label_expr (&expr1
);
6270 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6271 macro_build (NULL
, "nop", "");
6272 macro_build (ep
, call
? "bal" : "b", "p");
6274 /* Set to true so that append_insn adds a label. */
6275 emit_branch_likely_macro
= TRUE
;
6279 macro_build (ep
, br
, fmt
, sreg
, treg
);
6280 macro_build (NULL
, "nop", "");
6285 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6286 the condition code tested. EP specifies the branch target. */
6289 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6316 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6319 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6320 the register tested. EP specifies the branch target. */
6323 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6325 const char *brneg
= NULL
;
6335 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6339 gas_assert (mips_opts
.micromips
);
6348 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6355 br
= mips_opts
.micromips
? "blez" : "blezl";
6362 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6366 gas_assert (mips_opts
.micromips
);
6374 if (mips_opts
.micromips
&& brneg
)
6375 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6377 macro_build (ep
, br
, "s,p", sreg
);
6380 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6381 TREG as the registers tested. EP specifies the branch target. */
6384 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6385 unsigned int sreg
, unsigned int treg
)
6387 const char *brneg
= NULL
;
6399 br
= mips_opts
.micromips
? "beq" : "beql";
6408 br
= mips_opts
.micromips
? "bne" : "bnel";
6414 if (mips_opts
.micromips
&& brneg
)
6415 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6417 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6422 * This routine implements the seemingly endless macro or synthesized
6423 * instructions and addressing modes in the mips assembly language. Many
6424 * of these macros are simple and are similar to each other. These could
6425 * probably be handled by some kind of table or grammar approach instead of
6426 * this verbose method. Others are not simple macros but are more like
6427 * optimizing code generation.
6428 * One interesting optimization is when several store macros appear
6429 * consecutively that would load AT with the upper half of the same address.
6430 * The ensuing load upper instructions are ommited. This implies some kind
6431 * of global optimization. We currently only optimize within a single macro.
6432 * For many of the load and store macros if the address is specified as a
6433 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6434 * first load register 'at' with zero and use it as the base register. The
6435 * mips assembler simply uses register $zero. Just one tiny optimization
6439 macro (struct mips_cl_insn
*ip
)
6441 unsigned int treg
, sreg
, dreg
, breg
;
6442 unsigned int tempreg
;
6445 expressionS label_expr
;
6464 bfd_reloc_code_real_type r
;
6465 int hold_mips_optimize
;
6467 gas_assert (! mips_opts
.mips16
);
6469 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6470 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6471 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6472 mask
= ip
->insn_mo
->mask
;
6474 label_expr
.X_op
= O_constant
;
6475 label_expr
.X_op_symbol
= NULL
;
6476 label_expr
.X_add_symbol
= NULL
;
6477 label_expr
.X_add_number
= 0;
6479 expr1
.X_op
= O_constant
;
6480 expr1
.X_op_symbol
= NULL
;
6481 expr1
.X_add_symbol
= NULL
;
6482 expr1
.X_add_number
= 1;
6497 if (mips_opts
.micromips
)
6498 micromips_label_expr (&label_expr
);
6500 label_expr
.X_add_number
= 8;
6501 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6503 macro_build (NULL
, "nop", "");
6505 move_register (dreg
, sreg
);
6506 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6507 if (mips_opts
.micromips
)
6508 micromips_add_label ();
6525 if (!mips_opts
.micromips
)
6527 if (imm_expr
.X_op
== O_constant
6528 && imm_expr
.X_add_number
>= -0x200
6529 && imm_expr
.X_add_number
< 0x200)
6531 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6540 if (imm_expr
.X_op
== O_constant
6541 && imm_expr
.X_add_number
>= -0x8000
6542 && imm_expr
.X_add_number
< 0x8000)
6544 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6549 load_register (AT
, &imm_expr
, dbl
);
6550 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6569 if (imm_expr
.X_op
== O_constant
6570 && imm_expr
.X_add_number
>= 0
6571 && imm_expr
.X_add_number
< 0x10000)
6573 if (mask
!= M_NOR_I
)
6574 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6577 macro_build (&imm_expr
, "ori", "t,r,i",
6578 treg
, sreg
, BFD_RELOC_LO16
);
6579 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6585 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6586 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6590 switch (imm_expr
.X_add_number
)
6593 macro_build (NULL
, "nop", "");
6596 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6600 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6601 (int) imm_expr
.X_add_number
);
6604 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6605 (unsigned long) imm_expr
.X_add_number
);
6614 gas_assert (mips_opts
.micromips
);
6615 macro_build_branch_ccl (mask
, &offset_expr
,
6616 EXTRACT_OPERAND (1, BCC
, *ip
));
6623 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6629 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6634 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6641 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6643 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6647 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6648 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6649 &offset_expr
, AT
, ZERO
);
6659 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6665 /* Check for > max integer. */
6666 maxnum
= 0x7fffffff;
6667 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6674 if (imm_expr
.X_op
== O_constant
6675 && imm_expr
.X_add_number
>= maxnum
6676 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6679 /* Result is always false. */
6681 macro_build (NULL
, "nop", "");
6683 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6686 if (imm_expr
.X_op
!= O_constant
)
6687 as_bad (_("Unsupported large constant"));
6688 ++imm_expr
.X_add_number
;
6692 if (mask
== M_BGEL_I
)
6694 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6696 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6697 &offset_expr
, sreg
);
6700 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6702 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6703 &offset_expr
, sreg
);
6706 maxnum
= 0x7fffffff;
6707 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6714 maxnum
= - maxnum
- 1;
6715 if (imm_expr
.X_op
== O_constant
6716 && imm_expr
.X_add_number
<= maxnum
6717 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6720 /* result is always true */
6721 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6722 macro_build (&offset_expr
, "b", "p");
6727 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6728 &offset_expr
, AT
, ZERO
);
6737 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6738 &offset_expr
, ZERO
, treg
);
6742 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6743 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6744 &offset_expr
, AT
, ZERO
);
6753 && imm_expr
.X_op
== O_constant
6754 && imm_expr
.X_add_number
== -1))
6756 if (imm_expr
.X_op
!= O_constant
)
6757 as_bad (_("Unsupported large constant"));
6758 ++imm_expr
.X_add_number
;
6762 if (mask
== M_BGEUL_I
)
6764 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6766 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6767 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6768 &offset_expr
, sreg
, ZERO
);
6773 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6774 &offset_expr
, AT
, ZERO
);
6782 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6784 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6788 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6789 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6790 &offset_expr
, AT
, ZERO
);
6798 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6799 &offset_expr
, sreg
, ZERO
);
6805 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6806 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6807 &offset_expr
, AT
, ZERO
);
6815 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6817 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6821 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6822 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6823 &offset_expr
, AT
, ZERO
);
6830 maxnum
= 0x7fffffff;
6831 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6838 if (imm_expr
.X_op
== O_constant
6839 && imm_expr
.X_add_number
>= maxnum
6840 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6842 if (imm_expr
.X_op
!= O_constant
)
6843 as_bad (_("Unsupported large constant"));
6844 ++imm_expr
.X_add_number
;
6848 if (mask
== M_BLTL_I
)
6850 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6851 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6852 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6853 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6858 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6859 &offset_expr
, AT
, ZERO
);
6867 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6868 &offset_expr
, sreg
, ZERO
);
6874 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6875 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6876 &offset_expr
, AT
, ZERO
);
6885 && imm_expr
.X_op
== O_constant
6886 && imm_expr
.X_add_number
== -1))
6888 if (imm_expr
.X_op
!= O_constant
)
6889 as_bad (_("Unsupported large constant"));
6890 ++imm_expr
.X_add_number
;
6894 if (mask
== M_BLTUL_I
)
6896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6898 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6899 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6900 &offset_expr
, sreg
, ZERO
);
6905 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6906 &offset_expr
, AT
, ZERO
);
6914 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6916 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6920 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6921 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6922 &offset_expr
, AT
, ZERO
);
6932 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6933 &offset_expr
, ZERO
, treg
);
6937 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6938 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6939 &offset_expr
, AT
, ZERO
);
6945 /* Use unsigned arithmetic. */
6949 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6951 as_bad (_("Unsupported large constant"));
6956 pos
= imm_expr
.X_add_number
;
6957 size
= imm2_expr
.X_add_number
;
6962 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6965 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6967 as_bad (_("Improper extract size (%lu, position %lu)"),
6968 (unsigned long) size
, (unsigned long) pos
);
6972 if (size
<= 32 && pos
< 32)
6977 else if (size
<= 32)
6987 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6994 /* Use unsigned arithmetic. */
6998 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7000 as_bad (_("Unsupported large constant"));
7005 pos
= imm_expr
.X_add_number
;
7006 size
= imm2_expr
.X_add_number
;
7011 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7014 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7016 as_bad (_("Improper insert size (%lu, position %lu)"),
7017 (unsigned long) size
, (unsigned long) pos
);
7021 if (pos
< 32 && (pos
+ size
- 1) < 32)
7036 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7037 (int) (pos
+ size
- 1));
7053 as_warn (_("Divide by zero."));
7055 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7057 macro_build (NULL
, "break", BRK_FMT
, 7);
7064 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7065 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7069 if (mips_opts
.micromips
)
7070 micromips_label_expr (&label_expr
);
7072 label_expr
.X_add_number
= 8;
7073 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7074 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7075 macro_build (NULL
, "break", BRK_FMT
, 7);
7076 if (mips_opts
.micromips
)
7077 micromips_add_label ();
7079 expr1
.X_add_number
= -1;
7081 load_register (AT
, &expr1
, dbl
);
7082 if (mips_opts
.micromips
)
7083 micromips_label_expr (&label_expr
);
7085 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7086 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7089 expr1
.X_add_number
= 1;
7090 load_register (AT
, &expr1
, dbl
);
7091 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7095 expr1
.X_add_number
= 0x80000000;
7096 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7100 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7101 /* We want to close the noreorder block as soon as possible, so
7102 that later insns are available for delay slot filling. */
7107 if (mips_opts
.micromips
)
7108 micromips_label_expr (&label_expr
);
7110 label_expr
.X_add_number
= 8;
7111 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7112 macro_build (NULL
, "nop", "");
7114 /* We want to close the noreorder block as soon as possible, so
7115 that later insns are available for delay slot filling. */
7118 macro_build (NULL
, "break", BRK_FMT
, 6);
7120 if (mips_opts
.micromips
)
7121 micromips_add_label ();
7122 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7161 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7163 as_warn (_("Divide by zero."));
7165 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7167 macro_build (NULL
, "break", BRK_FMT
, 7);
7170 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7172 if (strcmp (s2
, "mflo") == 0)
7173 move_register (dreg
, sreg
);
7175 move_register (dreg
, ZERO
);
7178 if (imm_expr
.X_op
== O_constant
7179 && imm_expr
.X_add_number
== -1
7180 && s
[strlen (s
) - 1] != 'u')
7182 if (strcmp (s2
, "mflo") == 0)
7184 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7187 move_register (dreg
, ZERO
);
7192 load_register (AT
, &imm_expr
, dbl
);
7193 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7194 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7216 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7217 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7218 /* We want to close the noreorder block as soon as possible, so
7219 that later insns are available for delay slot filling. */
7224 if (mips_opts
.micromips
)
7225 micromips_label_expr (&label_expr
);
7227 label_expr
.X_add_number
= 8;
7228 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7229 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7231 /* We want to close the noreorder block as soon as possible, so
7232 that later insns are available for delay slot filling. */
7234 macro_build (NULL
, "break", BRK_FMT
, 7);
7235 if (mips_opts
.micromips
)
7236 micromips_add_label ();
7238 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7250 /* Load the address of a symbol into a register. If breg is not
7251 zero, we then add a base register to it. */
7253 if (dbl
&& HAVE_32BIT_GPRS
)
7254 as_warn (_("dla used to load 32-bit register"));
7256 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7257 as_warn (_("la used to load 64-bit address"));
7259 if (offset_expr
.X_op
== O_constant
7260 && offset_expr
.X_add_number
>= -0x8000
7261 && offset_expr
.X_add_number
< 0x8000)
7263 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7264 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7268 if (mips_opts
.at
&& (treg
== breg
))
7278 if (offset_expr
.X_op
!= O_symbol
7279 && offset_expr
.X_op
!= O_constant
)
7281 as_bad (_("Expression too complex"));
7282 offset_expr
.X_op
= O_constant
;
7285 if (offset_expr
.X_op
== O_constant
)
7286 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7287 else if (mips_pic
== NO_PIC
)
7289 /* If this is a reference to a GP relative symbol, we want
7290 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7292 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7293 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7294 If we have a constant, we need two instructions anyhow,
7295 so we may as well always use the latter form.
7297 With 64bit address space and a usable $at we want
7298 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7299 lui $at,<sym> (BFD_RELOC_HI16_S)
7300 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7301 daddiu $at,<sym> (BFD_RELOC_LO16)
7303 daddu $tempreg,$tempreg,$at
7305 If $at is already in use, we use a path which is suboptimal
7306 on superscalar processors.
7307 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7308 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7310 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7312 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7314 For GP relative symbols in 64bit address space we can use
7315 the same sequence as in 32bit address space. */
7316 if (HAVE_64BIT_SYMBOLS
)
7318 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7319 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7321 relax_start (offset_expr
.X_add_symbol
);
7322 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7323 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7327 if (used_at
== 0 && mips_opts
.at
)
7329 macro_build (&offset_expr
, "lui", LUI_FMT
,
7330 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7331 macro_build (&offset_expr
, "lui", LUI_FMT
,
7332 AT
, BFD_RELOC_HI16_S
);
7333 macro_build (&offset_expr
, "daddiu", "t,r,j",
7334 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7335 macro_build (&offset_expr
, "daddiu", "t,r,j",
7336 AT
, AT
, BFD_RELOC_LO16
);
7337 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7338 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7343 macro_build (&offset_expr
, "lui", LUI_FMT
,
7344 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7345 macro_build (&offset_expr
, "daddiu", "t,r,j",
7346 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7347 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7348 macro_build (&offset_expr
, "daddiu", "t,r,j",
7349 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7350 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7351 macro_build (&offset_expr
, "daddiu", "t,r,j",
7352 tempreg
, tempreg
, BFD_RELOC_LO16
);
7355 if (mips_relax
.sequence
)
7360 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7361 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7363 relax_start (offset_expr
.X_add_symbol
);
7364 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7365 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7368 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7369 as_bad (_("Offset too large"));
7370 macro_build_lui (&offset_expr
, tempreg
);
7371 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7372 tempreg
, tempreg
, BFD_RELOC_LO16
);
7373 if (mips_relax
.sequence
)
7377 else if (!mips_big_got
&& !HAVE_NEWABI
)
7379 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7381 /* If this is a reference to an external symbol, and there
7382 is no constant, we want
7383 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7384 or for lca or if tempreg is PIC_CALL_REG
7385 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7386 For a local symbol, we want
7387 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7389 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7391 If we have a small constant, and this is a reference to
7392 an external symbol, we want
7393 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7395 addiu $tempreg,$tempreg,<constant>
7396 For a local symbol, we want the same instruction
7397 sequence, but we output a BFD_RELOC_LO16 reloc on the
7400 If we have a large constant, and this is a reference to
7401 an external symbol, we want
7402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7403 lui $at,<hiconstant>
7404 addiu $at,$at,<loconstant>
7405 addu $tempreg,$tempreg,$at
7406 For a local symbol, we want the same instruction
7407 sequence, but we output a BFD_RELOC_LO16 reloc on the
7411 if (offset_expr
.X_add_number
== 0)
7413 if (mips_pic
== SVR4_PIC
7415 && (call
|| tempreg
== PIC_CALL_REG
))
7416 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7418 relax_start (offset_expr
.X_add_symbol
);
7419 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7420 lw_reloc_type
, mips_gp_register
);
7423 /* We're going to put in an addu instruction using
7424 tempreg, so we may as well insert the nop right
7429 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7430 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7432 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7433 tempreg
, tempreg
, BFD_RELOC_LO16
);
7435 /* FIXME: If breg == 0, and the next instruction uses
7436 $tempreg, then if this variant case is used an extra
7437 nop will be generated. */
7439 else if (offset_expr
.X_add_number
>= -0x8000
7440 && offset_expr
.X_add_number
< 0x8000)
7442 load_got_offset (tempreg
, &offset_expr
);
7444 add_got_offset (tempreg
, &offset_expr
);
7448 expr1
.X_add_number
= offset_expr
.X_add_number
;
7449 offset_expr
.X_add_number
=
7450 SEXT_16BIT (offset_expr
.X_add_number
);
7451 load_got_offset (tempreg
, &offset_expr
);
7452 offset_expr
.X_add_number
= expr1
.X_add_number
;
7453 /* If we are going to add in a base register, and the
7454 target register and the base register are the same,
7455 then we are using AT as a temporary register. Since
7456 we want to load the constant into AT, we add our
7457 current AT (from the global offset table) and the
7458 register into the register now, and pretend we were
7459 not using a base register. */
7463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7468 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7472 else if (!mips_big_got
&& HAVE_NEWABI
)
7474 int add_breg_early
= 0;
7476 /* If this is a reference to an external, and there is no
7477 constant, or local symbol (*), with or without a
7479 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7480 or for lca or if tempreg is PIC_CALL_REG
7481 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7483 If we have a small constant, and this is a reference to
7484 an external symbol, we want
7485 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7486 addiu $tempreg,$tempreg,<constant>
7488 If we have a large constant, and this is a reference to
7489 an external symbol, we want
7490 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7491 lui $at,<hiconstant>
7492 addiu $at,$at,<loconstant>
7493 addu $tempreg,$tempreg,$at
7495 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7496 local symbols, even though it introduces an additional
7499 if (offset_expr
.X_add_number
)
7501 expr1
.X_add_number
= offset_expr
.X_add_number
;
7502 offset_expr
.X_add_number
= 0;
7504 relax_start (offset_expr
.X_add_symbol
);
7505 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7506 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7508 if (expr1
.X_add_number
>= -0x8000
7509 && expr1
.X_add_number
< 0x8000)
7511 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7512 tempreg
, tempreg
, BFD_RELOC_LO16
);
7514 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7516 /* If we are going to add in a base register, and the
7517 target register and the base register are the same,
7518 then we are using AT as a temporary register. Since
7519 we want to load the constant into AT, we add our
7520 current AT (from the global offset table) and the
7521 register into the register now, and pretend we were
7522 not using a base register. */
7527 gas_assert (tempreg
== AT
);
7528 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7534 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7535 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7541 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7544 offset_expr
.X_add_number
= expr1
.X_add_number
;
7546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7547 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7551 treg
, tempreg
, breg
);
7557 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7559 relax_start (offset_expr
.X_add_symbol
);
7560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7561 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7563 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7564 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7570 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7573 else if (mips_big_got
&& !HAVE_NEWABI
)
7576 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7577 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7578 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7580 /* This is the large GOT case. If this is a reference to an
7581 external symbol, and there is no constant, we want
7582 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7583 addu $tempreg,$tempreg,$gp
7584 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7585 or for lca or if tempreg is PIC_CALL_REG
7586 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7587 addu $tempreg,$tempreg,$gp
7588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7589 For a local symbol, we want
7590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7594 If we have a small constant, and this is a reference to
7595 an external symbol, we want
7596 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7597 addu $tempreg,$tempreg,$gp
7598 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7600 addiu $tempreg,$tempreg,<constant>
7601 For a local symbol, we want
7602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7604 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7606 If we have a large constant, and this is a reference to
7607 an external symbol, we want
7608 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7609 addu $tempreg,$tempreg,$gp
7610 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7611 lui $at,<hiconstant>
7612 addiu $at,$at,<loconstant>
7613 addu $tempreg,$tempreg,$at
7614 For a local symbol, we want
7615 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7616 lui $at,<hiconstant>
7617 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7618 addu $tempreg,$tempreg,$at
7621 expr1
.X_add_number
= offset_expr
.X_add_number
;
7622 offset_expr
.X_add_number
= 0;
7623 relax_start (offset_expr
.X_add_symbol
);
7624 gpdelay
= reg_needs_delay (mips_gp_register
);
7625 if (expr1
.X_add_number
== 0 && breg
== 0
7626 && (call
|| tempreg
== PIC_CALL_REG
))
7628 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7629 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7631 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7632 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7633 tempreg
, tempreg
, mips_gp_register
);
7634 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7635 tempreg
, lw_reloc_type
, tempreg
);
7636 if (expr1
.X_add_number
== 0)
7640 /* We're going to put in an addu instruction using
7641 tempreg, so we may as well insert the nop right
7646 else if (expr1
.X_add_number
>= -0x8000
7647 && expr1
.X_add_number
< 0x8000)
7650 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7651 tempreg
, tempreg
, BFD_RELOC_LO16
);
7655 /* If we are going to add in a base register, and the
7656 target register and the base register are the same,
7657 then we are using AT as a temporary register. Since
7658 we want to load the constant into AT, we add our
7659 current AT (from the global offset table) and the
7660 register into the register now, and pretend we were
7661 not using a base register. */
7666 gas_assert (tempreg
== AT
);
7668 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7673 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7674 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7678 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7683 /* This is needed because this instruction uses $gp, but
7684 the first instruction on the main stream does not. */
7685 macro_build (NULL
, "nop", "");
7688 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7689 local_reloc_type
, mips_gp_register
);
7690 if (expr1
.X_add_number
>= -0x8000
7691 && expr1
.X_add_number
< 0x8000)
7694 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7695 tempreg
, tempreg
, BFD_RELOC_LO16
);
7696 /* FIXME: If add_number is 0, and there was no base
7697 register, the external symbol case ended with a load,
7698 so if the symbol turns out to not be external, and
7699 the next instruction uses tempreg, an unnecessary nop
7700 will be inserted. */
7706 /* We must add in the base register now, as in the
7707 external symbol case. */
7708 gas_assert (tempreg
== AT
);
7710 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7713 /* We set breg to 0 because we have arranged to add
7714 it in in both cases. */
7718 macro_build_lui (&expr1
, AT
);
7719 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7720 AT
, AT
, BFD_RELOC_LO16
);
7721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7722 tempreg
, tempreg
, AT
);
7727 else if (mips_big_got
&& HAVE_NEWABI
)
7729 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7730 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7731 int add_breg_early
= 0;
7733 /* This is the large GOT case. If this is a reference to an
7734 external symbol, and there is no constant, we want
7735 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7736 add $tempreg,$tempreg,$gp
7737 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7738 or for lca or if tempreg is PIC_CALL_REG
7739 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7740 add $tempreg,$tempreg,$gp
7741 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7743 If we have a small constant, and this is a reference to
7744 an external symbol, we want
7745 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7746 add $tempreg,$tempreg,$gp
7747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7748 addi $tempreg,$tempreg,<constant>
7750 If we have a large constant, and this is a reference to
7751 an external symbol, we want
7752 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7753 addu $tempreg,$tempreg,$gp
7754 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7755 lui $at,<hiconstant>
7756 addi $at,$at,<loconstant>
7757 add $tempreg,$tempreg,$at
7759 If we have NewABI, and we know it's a local symbol, we want
7760 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7761 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7762 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7764 relax_start (offset_expr
.X_add_symbol
);
7766 expr1
.X_add_number
= offset_expr
.X_add_number
;
7767 offset_expr
.X_add_number
= 0;
7769 if (expr1
.X_add_number
== 0 && breg
== 0
7770 && (call
|| tempreg
== PIC_CALL_REG
))
7772 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7773 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7775 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7776 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7777 tempreg
, tempreg
, mips_gp_register
);
7778 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7779 tempreg
, lw_reloc_type
, tempreg
);
7781 if (expr1
.X_add_number
== 0)
7783 else if (expr1
.X_add_number
>= -0x8000
7784 && expr1
.X_add_number
< 0x8000)
7786 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7787 tempreg
, tempreg
, BFD_RELOC_LO16
);
7789 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7791 /* If we are going to add in a base register, and the
7792 target register and the base register are the same,
7793 then we are using AT as a temporary register. Since
7794 we want to load the constant into AT, we add our
7795 current AT (from the global offset table) and the
7796 register into the register now, and pretend we were
7797 not using a base register. */
7802 gas_assert (tempreg
== AT
);
7803 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7809 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7810 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7815 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7818 offset_expr
.X_add_number
= expr1
.X_add_number
;
7819 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7820 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7821 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7822 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7825 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7826 treg
, tempreg
, breg
);
7836 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7840 gas_assert (!mips_opts
.micromips
);
7842 unsigned long temp
= (treg
<< 16) | (0x01);
7843 macro_build (NULL
, "c2", "C", temp
);
7848 gas_assert (!mips_opts
.micromips
);
7850 unsigned long temp
= (0x02);
7851 macro_build (NULL
, "c2", "C", temp
);
7856 gas_assert (!mips_opts
.micromips
);
7858 unsigned long temp
= (treg
<< 16) | (0x02);
7859 macro_build (NULL
, "c2", "C", temp
);
7864 gas_assert (!mips_opts
.micromips
);
7865 macro_build (NULL
, "c2", "C", 3);
7869 gas_assert (!mips_opts
.micromips
);
7871 unsigned long temp
= (treg
<< 16) | 0x03;
7872 macro_build (NULL
, "c2", "C", temp
);
7877 /* The j instruction may not be used in PIC code, since it
7878 requires an absolute address. We convert it to a b
7880 if (mips_pic
== NO_PIC
)
7881 macro_build (&offset_expr
, "j", "a");
7883 macro_build (&offset_expr
, "b", "p");
7886 /* The jal instructions must be handled as macros because when
7887 generating PIC code they expand to multi-instruction
7888 sequences. Normally they are simple instructions. */
7893 gas_assert (mips_opts
.micromips
);
7901 if (mips_pic
== NO_PIC
)
7903 s
= jals
? "jalrs" : "jalr";
7904 if (mips_opts
.micromips
7906 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7907 macro_build (NULL
, s
, "mj", sreg
);
7909 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7913 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7914 && mips_cprestore_offset
>= 0);
7916 if (sreg
!= PIC_CALL_REG
)
7917 as_warn (_("MIPS PIC call to register other than $25"));
7919 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7920 ? "jalrs" : "jalr");
7921 if (mips_opts
.micromips
7923 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7924 macro_build (NULL
, s
, "mj", sreg
);
7926 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7927 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7929 if (mips_cprestore_offset
< 0)
7930 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7933 if (!mips_frame_reg_valid
)
7935 as_warn (_("No .frame pseudo-op used in PIC code"));
7936 /* Quiet this warning. */
7937 mips_frame_reg_valid
= 1;
7939 if (!mips_cprestore_valid
)
7941 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7942 /* Quiet this warning. */
7943 mips_cprestore_valid
= 1;
7945 if (mips_opts
.noreorder
)
7946 macro_build (NULL
, "nop", "");
7947 expr1
.X_add_number
= mips_cprestore_offset
;
7948 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7951 HAVE_64BIT_ADDRESSES
);
7959 gas_assert (mips_opts
.micromips
);
7963 if (mips_pic
== NO_PIC
)
7964 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7965 else if (mips_pic
== SVR4_PIC
)
7967 /* If this is a reference to an external symbol, and we are
7968 using a small GOT, we want
7969 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7973 lw $gp,cprestore($sp)
7974 The cprestore value is set using the .cprestore
7975 pseudo-op. If we are using a big GOT, we want
7976 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7978 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7982 lw $gp,cprestore($sp)
7983 If the symbol is not external, we want
7984 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7986 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7989 lw $gp,cprestore($sp)
7991 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7992 sequences above, minus nops, unless the symbol is local,
7993 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7999 relax_start (offset_expr
.X_add_symbol
);
8000 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8001 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8004 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8005 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8011 relax_start (offset_expr
.X_add_symbol
);
8012 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8013 BFD_RELOC_MIPS_CALL_HI16
);
8014 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8015 PIC_CALL_REG
, mips_gp_register
);
8016 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8017 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8020 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8021 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8023 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8024 PIC_CALL_REG
, PIC_CALL_REG
,
8025 BFD_RELOC_MIPS_GOT_OFST
);
8029 macro_build_jalr (&offset_expr
, 0);
8033 relax_start (offset_expr
.X_add_symbol
);
8036 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8037 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8046 gpdelay
= reg_needs_delay (mips_gp_register
);
8047 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8048 BFD_RELOC_MIPS_CALL_HI16
);
8049 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8050 PIC_CALL_REG
, mips_gp_register
);
8051 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8052 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8057 macro_build (NULL
, "nop", "");
8059 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8060 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8063 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8064 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8066 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8068 if (mips_cprestore_offset
< 0)
8069 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8072 if (!mips_frame_reg_valid
)
8074 as_warn (_("No .frame pseudo-op used in PIC code"));
8075 /* Quiet this warning. */
8076 mips_frame_reg_valid
= 1;
8078 if (!mips_cprestore_valid
)
8080 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8081 /* Quiet this warning. */
8082 mips_cprestore_valid
= 1;
8084 if (mips_opts
.noreorder
)
8085 macro_build (NULL
, "nop", "");
8086 expr1
.X_add_number
= mips_cprestore_offset
;
8087 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8090 HAVE_64BIT_ADDRESSES
);
8094 else if (mips_pic
== VXWORKS_PIC
)
8095 as_bad (_("Non-PIC jump used in PIC library"));
8105 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8113 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8144 gas_assert (!mips_opts
.micromips
);
8147 /* Itbl support may require additional care here. */
8154 /* Itbl support may require additional care here. */
8162 off12
= mips_opts
.micromips
;
8163 /* Itbl support may require additional care here. */
8168 gas_assert (!mips_opts
.micromips
);
8171 /* Itbl support may require additional care here. */
8179 off12
= mips_opts
.micromips
;
8186 off12
= mips_opts
.micromips
;
8192 /* Itbl support may require additional care here. */
8200 off12
= mips_opts
.micromips
;
8201 /* Itbl support may require additional care here. */
8208 /* Itbl support may require additional care here. */
8216 off12
= mips_opts
.micromips
;
8223 off12
= mips_opts
.micromips
;
8230 off12
= mips_opts
.micromips
;
8237 off12
= mips_opts
.micromips
;
8244 off12
= mips_opts
.micromips
;
8249 gas_assert (mips_opts
.micromips
);
8258 gas_assert (mips_opts
.micromips
);
8267 gas_assert (mips_opts
.micromips
);
8275 gas_assert (mips_opts
.micromips
);
8282 if (breg
== treg
+ lp
)
8285 tempreg
= treg
+ lp
;
8305 gas_assert (!mips_opts
.micromips
);
8308 /* Itbl support may require additional care here. */
8315 /* Itbl support may require additional care here. */
8323 off12
= mips_opts
.micromips
;
8324 /* Itbl support may require additional care here. */
8329 gas_assert (!mips_opts
.micromips
);
8332 /* Itbl support may require additional care here. */
8340 off12
= mips_opts
.micromips
;
8347 off12
= mips_opts
.micromips
;
8354 off12
= mips_opts
.micromips
;
8361 off12
= mips_opts
.micromips
;
8367 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8368 off12
= mips_opts
.micromips
;
8374 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8375 off12
= mips_opts
.micromips
;
8382 /* Itbl support may require additional care here. */
8389 off12
= mips_opts
.micromips
;
8390 /* Itbl support may require additional care here. */
8395 gas_assert (!mips_opts
.micromips
);
8398 /* Itbl support may require additional care here. */
8406 off12
= mips_opts
.micromips
;
8413 off12
= mips_opts
.micromips
;
8418 gas_assert (mips_opts
.micromips
);
8426 gas_assert (mips_opts
.micromips
);
8434 gas_assert (mips_opts
.micromips
);
8442 gas_assert (mips_opts
.micromips
);
8451 if (offset_expr
.X_op
!= O_constant
8452 && offset_expr
.X_op
!= O_symbol
)
8454 as_bad (_("Expression too complex"));
8455 offset_expr
.X_op
= O_constant
;
8458 if (HAVE_32BIT_ADDRESSES
8459 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8463 sprintf_vma (value
, offset_expr
.X_add_number
);
8464 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8467 /* A constant expression in PIC code can be handled just as it
8468 is in non PIC code. */
8469 if (offset_expr
.X_op
== O_constant
)
8473 expr1
.X_add_number
= offset_expr
.X_add_number
;
8474 normalize_address_expr (&expr1
);
8475 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8477 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8478 & ~(bfd_vma
) 0xffff);
8481 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8483 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8484 & ~(bfd_vma
) 0xfff);
8489 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8491 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8492 tempreg
, tempreg
, breg
);
8497 if (offset_expr
.X_add_number
== 0)
8500 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8501 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8502 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8505 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8507 macro_build (NULL
, s
, fmt
,
8508 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8510 else if (off12
|| off0
)
8512 /* A 12-bit or 0-bit offset field is too narrow to be used
8513 for a low-part relocation, so load the whole address into
8514 the auxillary register. In the case of "A(b)" addresses,
8515 we first load absolute address "A" into the register and
8516 then add base register "b". In the case of "o(b)" addresses,
8517 we simply need to add 16-bit offset "o" to base register "b", and
8518 offset_reloc already contains the relocations associated
8522 load_address (tempreg
, &offset_expr
, &used_at
);
8524 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8525 tempreg
, tempreg
, breg
);
8528 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8530 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8531 expr1
.X_add_number
= 0;
8533 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8535 macro_build (NULL
, s
, fmt
,
8536 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8538 else if (mips_pic
== NO_PIC
)
8540 /* If this is a reference to a GP relative symbol, and there
8541 is no base register, we want
8542 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8543 Otherwise, if there is no base register, we want
8544 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8545 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8546 If we have a constant, we need two instructions anyhow,
8547 so we always use the latter form.
8549 If we have a base register, and this is a reference to a
8550 GP relative symbol, we want
8551 addu $tempreg,$breg,$gp
8552 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8554 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8555 addu $tempreg,$tempreg,$breg
8556 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8557 With a constant we always use the latter case.
8559 With 64bit address space and no base register and $at usable,
8561 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8562 lui $at,<sym> (BFD_RELOC_HI16_S)
8563 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8566 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8567 If we have a base register, we want
8568 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8569 lui $at,<sym> (BFD_RELOC_HI16_S)
8570 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8574 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8576 Without $at we can't generate the optimal path for superscalar
8577 processors here since this would require two temporary registers.
8578 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8579 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8581 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8583 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8584 If we have a base register, we want
8585 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8586 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8588 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8590 daddu $tempreg,$tempreg,$breg
8591 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8593 For GP relative symbols in 64bit address space we can use
8594 the same sequence as in 32bit address space. */
8595 if (HAVE_64BIT_SYMBOLS
)
8597 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8598 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8600 relax_start (offset_expr
.X_add_symbol
);
8603 macro_build (&offset_expr
, s
, fmt
, treg
,
8604 BFD_RELOC_GPREL16
, mips_gp_register
);
8608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8609 tempreg
, breg
, mips_gp_register
);
8610 macro_build (&offset_expr
, s
, fmt
, treg
,
8611 BFD_RELOC_GPREL16
, tempreg
);
8616 if (used_at
== 0 && mips_opts
.at
)
8618 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8619 BFD_RELOC_MIPS_HIGHEST
);
8620 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8622 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8623 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8625 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8626 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8627 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8628 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8634 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8635 BFD_RELOC_MIPS_HIGHEST
);
8636 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8637 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8638 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8639 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8640 tempreg
, BFD_RELOC_HI16_S
);
8641 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8643 macro_build (NULL
, "daddu", "d,v,t",
8644 tempreg
, tempreg
, breg
);
8645 macro_build (&offset_expr
, s
, fmt
, treg
,
8646 BFD_RELOC_LO16
, tempreg
);
8649 if (mips_relax
.sequence
)
8656 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8657 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8659 relax_start (offset_expr
.X_add_symbol
);
8660 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8664 macro_build_lui (&offset_expr
, tempreg
);
8665 macro_build (&offset_expr
, s
, fmt
, treg
,
8666 BFD_RELOC_LO16
, tempreg
);
8667 if (mips_relax
.sequence
)
8672 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8673 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8675 relax_start (offset_expr
.X_add_symbol
);
8676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8677 tempreg
, breg
, mips_gp_register
);
8678 macro_build (&offset_expr
, s
, fmt
, treg
,
8679 BFD_RELOC_GPREL16
, tempreg
);
8682 macro_build_lui (&offset_expr
, tempreg
);
8683 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8684 tempreg
, tempreg
, breg
);
8685 macro_build (&offset_expr
, s
, fmt
, treg
,
8686 BFD_RELOC_LO16
, tempreg
);
8687 if (mips_relax
.sequence
)
8691 else if (!mips_big_got
)
8693 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8695 /* If this is a reference to an external symbol, we want
8696 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8698 <op> $treg,0($tempreg)
8700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8702 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8703 <op> $treg,0($tempreg)
8706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8707 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8709 If there is a base register, we add it to $tempreg before
8710 the <op>. If there is a constant, we stick it in the
8711 <op> instruction. We don't handle constants larger than
8712 16 bits, because we have no way to load the upper 16 bits
8713 (actually, we could handle them for the subset of cases
8714 in which we are not using $at). */
8715 gas_assert (offset_expr
.X_op
== O_symbol
);
8718 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8719 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8722 tempreg
, tempreg
, breg
);
8723 macro_build (&offset_expr
, s
, fmt
, treg
,
8724 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8727 expr1
.X_add_number
= offset_expr
.X_add_number
;
8728 offset_expr
.X_add_number
= 0;
8729 if (expr1
.X_add_number
< -0x8000
8730 || expr1
.X_add_number
>= 0x8000)
8731 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8732 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8733 lw_reloc_type
, mips_gp_register
);
8735 relax_start (offset_expr
.X_add_symbol
);
8737 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8738 tempreg
, BFD_RELOC_LO16
);
8741 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8742 tempreg
, tempreg
, breg
);
8743 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8745 else if (mips_big_got
&& !HAVE_NEWABI
)
8749 /* If this is a reference to an external symbol, we want
8750 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8751 addu $tempreg,$tempreg,$gp
8752 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8753 <op> $treg,0($tempreg)
8755 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8757 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8758 <op> $treg,0($tempreg)
8759 If there is a base register, we add it to $tempreg before
8760 the <op>. If there is a constant, we stick it in the
8761 <op> instruction. We don't handle constants larger than
8762 16 bits, because we have no way to load the upper 16 bits
8763 (actually, we could handle them for the subset of cases
8764 in which we are not using $at). */
8765 gas_assert (offset_expr
.X_op
== O_symbol
);
8766 expr1
.X_add_number
= offset_expr
.X_add_number
;
8767 offset_expr
.X_add_number
= 0;
8768 if (expr1
.X_add_number
< -0x8000
8769 || expr1
.X_add_number
>= 0x8000)
8770 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8771 gpdelay
= reg_needs_delay (mips_gp_register
);
8772 relax_start (offset_expr
.X_add_symbol
);
8773 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8774 BFD_RELOC_MIPS_GOT_HI16
);
8775 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8777 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8778 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8781 macro_build (NULL
, "nop", "");
8782 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8783 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8785 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8786 tempreg
, BFD_RELOC_LO16
);
8790 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8791 tempreg
, tempreg
, breg
);
8792 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8794 else if (mips_big_got
&& HAVE_NEWABI
)
8796 /* If this is a reference to an external symbol, we want
8797 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8798 add $tempreg,$tempreg,$gp
8799 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8800 <op> $treg,<ofst>($tempreg)
8801 Otherwise, for local symbols, we want:
8802 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8803 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8804 gas_assert (offset_expr
.X_op
== O_symbol
);
8805 expr1
.X_add_number
= offset_expr
.X_add_number
;
8806 offset_expr
.X_add_number
= 0;
8807 if (expr1
.X_add_number
< -0x8000
8808 || expr1
.X_add_number
>= 0x8000)
8809 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8810 relax_start (offset_expr
.X_add_symbol
);
8811 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8812 BFD_RELOC_MIPS_GOT_HI16
);
8813 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8815 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8816 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8818 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8819 tempreg
, tempreg
, breg
);
8820 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8823 offset_expr
.X_add_number
= expr1
.X_add_number
;
8824 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8825 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8827 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8828 tempreg
, tempreg
, breg
);
8829 macro_build (&offset_expr
, s
, fmt
, treg
,
8830 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8840 load_register (treg
, &imm_expr
, 0);
8844 load_register (treg
, &imm_expr
, 1);
8848 if (imm_expr
.X_op
== O_constant
)
8851 load_register (AT
, &imm_expr
, 0);
8852 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8857 gas_assert (offset_expr
.X_op
== O_symbol
8858 && strcmp (segment_name (S_GET_SEGMENT
8859 (offset_expr
.X_add_symbol
)),
8861 && offset_expr
.X_add_number
== 0);
8862 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8863 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8868 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8869 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8870 order 32 bits of the value and the low order 32 bits are either
8871 zero or in OFFSET_EXPR. */
8872 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8874 if (HAVE_64BIT_GPRS
)
8875 load_register (treg
, &imm_expr
, 1);
8880 if (target_big_endian
)
8892 load_register (hreg
, &imm_expr
, 0);
8895 if (offset_expr
.X_op
== O_absent
)
8896 move_register (lreg
, 0);
8899 gas_assert (offset_expr
.X_op
== O_constant
);
8900 load_register (lreg
, &offset_expr
, 0);
8907 /* We know that sym is in the .rdata section. First we get the
8908 upper 16 bits of the address. */
8909 if (mips_pic
== NO_PIC
)
8911 macro_build_lui (&offset_expr
, AT
);
8916 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8917 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8921 /* Now we load the register(s). */
8922 if (HAVE_64BIT_GPRS
)
8925 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8930 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8933 /* FIXME: How in the world do we deal with the possible
8935 offset_expr
.X_add_number
+= 4;
8936 macro_build (&offset_expr
, "lw", "t,o(b)",
8937 treg
+ 1, BFD_RELOC_LO16
, AT
);
8943 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8944 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8945 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8946 the value and the low order 32 bits are either zero or in
8948 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8951 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8952 if (HAVE_64BIT_FPRS
)
8954 gas_assert (HAVE_64BIT_GPRS
);
8955 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8959 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8960 if (offset_expr
.X_op
== O_absent
)
8961 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8964 gas_assert (offset_expr
.X_op
== O_constant
);
8965 load_register (AT
, &offset_expr
, 0);
8966 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8972 gas_assert (offset_expr
.X_op
== O_symbol
8973 && offset_expr
.X_add_number
== 0);
8974 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8975 if (strcmp (s
, ".lit8") == 0)
8977 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
8979 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8980 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8983 breg
= mips_gp_register
;
8984 r
= BFD_RELOC_MIPS_LITERAL
;
8989 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8991 if (mips_pic
!= NO_PIC
)
8992 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8993 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8996 /* FIXME: This won't work for a 64 bit address. */
8997 macro_build_lui (&offset_expr
, AT
);
9000 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9002 macro_build (&offset_expr
, "ldc1", "T,o(b)",
9003 treg
, BFD_RELOC_LO16
, AT
);
9012 /* Even on a big endian machine $fn comes before $fn+1. We have
9013 to adjust when loading from memory. */
9016 gas_assert (!mips_opts
.micromips
);
9017 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9018 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9019 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
9020 /* FIXME: A possible overflow which I don't know how to deal
9022 offset_expr
.X_add_number
+= 4;
9023 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9024 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9028 gas_assert (!mips_opts
.micromips
);
9029 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9030 /* Even on a big endian machine $fn comes before $fn+1. We have
9031 to adjust when storing to memory. */
9032 macro_build (&offset_expr
, "swc1", "T,o(b)",
9033 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9034 offset_expr
.X_add_number
+= 4;
9035 macro_build (&offset_expr
, "swc1", "T,o(b)",
9036 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9040 gas_assert (!mips_opts
.micromips
);
9042 * The MIPS assembler seems to check for X_add_number not
9043 * being double aligned and generating:
9046 * addiu at,at,%lo(foo+1)
9049 * But, the resulting address is the same after relocation so why
9050 * generate the extra instruction?
9052 /* Itbl support may require additional care here. */
9055 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9064 gas_assert (!mips_opts
.micromips
);
9065 /* Itbl support may require additional care here. */
9068 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9088 if (HAVE_64BIT_GPRS
)
9098 if (HAVE_64BIT_GPRS
)
9106 if (offset_expr
.X_op
!= O_symbol
9107 && offset_expr
.X_op
!= O_constant
)
9109 as_bad (_("Expression too complex"));
9110 offset_expr
.X_op
= O_constant
;
9113 if (HAVE_32BIT_ADDRESSES
9114 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9118 sprintf_vma (value
, offset_expr
.X_add_number
);
9119 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9122 /* Even on a big endian machine $fn comes before $fn+1. We have
9123 to adjust when loading from memory. We set coproc if we must
9124 load $fn+1 first. */
9125 /* Itbl support may require additional care here. */
9126 if (!target_big_endian
)
9129 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9131 /* If this is a reference to a GP relative symbol, we want
9132 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9133 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9134 If we have a base register, we use this
9136 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9137 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9138 If this is not a GP relative symbol, we want
9139 lui $at,<sym> (BFD_RELOC_HI16_S)
9140 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9141 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9142 If there is a base register, we add it to $at after the
9143 lui instruction. If there is a constant, we always use
9145 if (offset_expr
.X_op
== O_symbol
9146 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9147 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9149 relax_start (offset_expr
.X_add_symbol
);
9152 tempreg
= mips_gp_register
;
9156 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9157 AT
, breg
, mips_gp_register
);
9162 /* Itbl support may require additional care here. */
9163 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9164 BFD_RELOC_GPREL16
, tempreg
);
9165 offset_expr
.X_add_number
+= 4;
9167 /* Set mips_optimize to 2 to avoid inserting an
9169 hold_mips_optimize
= mips_optimize
;
9171 /* Itbl support may require additional care here. */
9172 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9173 BFD_RELOC_GPREL16
, tempreg
);
9174 mips_optimize
= hold_mips_optimize
;
9178 offset_expr
.X_add_number
-= 4;
9181 macro_build_lui (&offset_expr
, AT
);
9183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9184 /* Itbl support may require additional care here. */
9185 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9186 BFD_RELOC_LO16
, AT
);
9187 /* FIXME: How do we handle overflow here? */
9188 offset_expr
.X_add_number
+= 4;
9189 /* Itbl support may require additional care here. */
9190 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9191 BFD_RELOC_LO16
, AT
);
9192 if (mips_relax
.sequence
)
9195 else if (!mips_big_got
)
9197 /* If this is a reference to an external symbol, we want
9198 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9203 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9205 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9206 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9207 If there is a base register we add it to $at before the
9208 lwc1 instructions. If there is a constant we include it
9209 in the lwc1 instructions. */
9211 expr1
.X_add_number
= offset_expr
.X_add_number
;
9212 if (expr1
.X_add_number
< -0x8000
9213 || expr1
.X_add_number
>= 0x8000 - 4)
9214 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9215 load_got_offset (AT
, &offset_expr
);
9218 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9220 /* Set mips_optimize to 2 to avoid inserting an undesired
9222 hold_mips_optimize
= mips_optimize
;
9225 /* Itbl support may require additional care here. */
9226 relax_start (offset_expr
.X_add_symbol
);
9227 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9228 BFD_RELOC_LO16
, AT
);
9229 expr1
.X_add_number
+= 4;
9230 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9231 BFD_RELOC_LO16
, AT
);
9233 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9234 BFD_RELOC_LO16
, AT
);
9235 offset_expr
.X_add_number
+= 4;
9236 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9237 BFD_RELOC_LO16
, AT
);
9240 mips_optimize
= hold_mips_optimize
;
9242 else if (mips_big_got
)
9246 /* If this is a reference to an external symbol, we want
9247 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9249 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9254 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9256 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9257 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9258 If there is a base register we add it to $at before the
9259 lwc1 instructions. If there is a constant we include it
9260 in the lwc1 instructions. */
9262 expr1
.X_add_number
= offset_expr
.X_add_number
;
9263 offset_expr
.X_add_number
= 0;
9264 if (expr1
.X_add_number
< -0x8000
9265 || expr1
.X_add_number
>= 0x8000 - 4)
9266 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9267 gpdelay
= reg_needs_delay (mips_gp_register
);
9268 relax_start (offset_expr
.X_add_symbol
);
9269 macro_build (&offset_expr
, "lui", LUI_FMT
,
9270 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9272 AT
, AT
, mips_gp_register
);
9273 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9274 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9277 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9278 /* Itbl support may require additional care here. */
9279 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9280 BFD_RELOC_LO16
, AT
);
9281 expr1
.X_add_number
+= 4;
9283 /* Set mips_optimize to 2 to avoid inserting an undesired
9285 hold_mips_optimize
= mips_optimize
;
9287 /* Itbl support may require additional care here. */
9288 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9289 BFD_RELOC_LO16
, AT
);
9290 mips_optimize
= hold_mips_optimize
;
9291 expr1
.X_add_number
-= 4;
9294 offset_expr
.X_add_number
= expr1
.X_add_number
;
9296 macro_build (NULL
, "nop", "");
9297 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9298 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9302 /* Itbl support may require additional care here. */
9303 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9304 BFD_RELOC_LO16
, AT
);
9305 offset_expr
.X_add_number
+= 4;
9307 /* Set mips_optimize to 2 to avoid inserting an undesired
9309 hold_mips_optimize
= mips_optimize
;
9311 /* Itbl support may require additional care here. */
9312 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9313 BFD_RELOC_LO16
, AT
);
9314 mips_optimize
= hold_mips_optimize
;
9323 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9326 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9328 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9329 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9331 if (!HAVE_64BIT_GPRS
)
9333 offset_expr
.X_add_number
+= 4;
9334 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9335 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9356 /* New code added to support COPZ instructions.
9357 This code builds table entries out of the macros in mip_opcodes.
9358 R4000 uses interlocks to handle coproc delays.
9359 Other chips (like the R3000) require nops to be inserted for delays.
9361 FIXME: Currently, we require that the user handle delays.
9362 In order to fill delay slots for non-interlocked chips,
9363 we must have a way to specify delays based on the coprocessor.
9364 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9365 What are the side-effects of the cop instruction?
9366 What cache support might we have and what are its effects?
9367 Both coprocessor & memory require delays. how long???
9368 What registers are read/set/modified?
9370 If an itbl is provided to interpret cop instructions,
9371 this knowledge can be encoded in the itbl spec. */
9385 gas_assert (!mips_opts
.micromips
);
9386 /* For now we just do C (same as Cz). The parameter will be
9387 stored in insn_opcode by mips_ip. */
9388 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9392 move_register (dreg
, sreg
);
9398 if (mips_opts
.arch
== CPU_R5900
)
9400 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9404 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9405 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9412 /* The MIPS assembler some times generates shifts and adds. I'm
9413 not trying to be that fancy. GCC should do this for us
9416 load_register (AT
, &imm_expr
, dbl
);
9417 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9418 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9434 load_register (AT
, &imm_expr
, dbl
);
9435 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9436 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9437 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9438 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9440 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9443 if (mips_opts
.micromips
)
9444 micromips_label_expr (&label_expr
);
9446 label_expr
.X_add_number
= 8;
9447 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9448 macro_build (NULL
, "nop", "");
9449 macro_build (NULL
, "break", BRK_FMT
, 6);
9450 if (mips_opts
.micromips
)
9451 micromips_add_label ();
9454 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9470 load_register (AT
, &imm_expr
, dbl
);
9471 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9472 sreg
, imm
? AT
: treg
);
9473 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9474 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9476 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9479 if (mips_opts
.micromips
)
9480 micromips_label_expr (&label_expr
);
9482 label_expr
.X_add_number
= 8;
9483 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9484 macro_build (NULL
, "nop", "");
9485 macro_build (NULL
, "break", BRK_FMT
, 6);
9486 if (mips_opts
.micromips
)
9487 micromips_add_label ();
9493 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9504 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9505 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9509 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9510 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9511 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9512 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9516 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9527 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9528 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9532 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9533 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9534 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9535 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9544 if (imm_expr
.X_op
!= O_constant
)
9545 as_bad (_("Improper rotate count"));
9546 rot
= imm_expr
.X_add_number
& 0x3f;
9547 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9549 rot
= (64 - rot
) & 0x3f;
9551 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9553 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9558 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9561 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9562 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9565 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9566 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9567 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9575 if (imm_expr
.X_op
!= O_constant
)
9576 as_bad (_("Improper rotate count"));
9577 rot
= imm_expr
.X_add_number
& 0x1f;
9578 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9580 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9585 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9589 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9590 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9591 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9596 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9598 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9602 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9603 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9604 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9605 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9609 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9611 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9615 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9616 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9617 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9618 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9627 if (imm_expr
.X_op
!= O_constant
)
9628 as_bad (_("Improper rotate count"));
9629 rot
= imm_expr
.X_add_number
& 0x3f;
9630 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9633 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9635 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9640 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9643 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9644 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9647 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9648 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9649 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9657 if (imm_expr
.X_op
!= O_constant
)
9658 as_bad (_("Improper rotate count"));
9659 rot
= imm_expr
.X_add_number
& 0x1f;
9660 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9662 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9667 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9671 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9672 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9673 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9679 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9681 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9684 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9685 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9690 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9692 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9697 as_warn (_("Instruction %s: result is always false"),
9699 move_register (dreg
, 0);
9702 if (CPU_HAS_SEQ (mips_opts
.arch
)
9703 && -512 <= imm_expr
.X_add_number
9704 && imm_expr
.X_add_number
< 512)
9706 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9707 (int) imm_expr
.X_add_number
);
9710 if (imm_expr
.X_op
== O_constant
9711 && imm_expr
.X_add_number
>= 0
9712 && imm_expr
.X_add_number
< 0x10000)
9714 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9716 else if (imm_expr
.X_op
== O_constant
9717 && imm_expr
.X_add_number
> -0x8000
9718 && imm_expr
.X_add_number
< 0)
9720 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9721 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9722 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9724 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9727 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9728 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9733 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9734 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9737 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9740 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9746 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9747 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9750 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9752 if (imm_expr
.X_op
== O_constant
9753 && imm_expr
.X_add_number
>= -0x8000
9754 && imm_expr
.X_add_number
< 0x8000)
9756 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9757 dreg
, sreg
, BFD_RELOC_LO16
);
9761 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9762 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9766 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9769 case M_SGT
: /* sreg > treg <==> treg < sreg */
9775 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9778 case M_SGT_I
: /* sreg > I <==> I < sreg */
9785 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9786 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9789 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9795 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9796 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9799 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9806 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9807 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9808 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9812 if (imm_expr
.X_op
== O_constant
9813 && imm_expr
.X_add_number
>= -0x8000
9814 && imm_expr
.X_add_number
< 0x8000)
9816 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9820 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9821 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9825 if (imm_expr
.X_op
== O_constant
9826 && imm_expr
.X_add_number
>= -0x8000
9827 && imm_expr
.X_add_number
< 0x8000)
9829 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9834 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9835 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9840 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9842 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9845 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9846 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9851 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9853 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9858 as_warn (_("Instruction %s: result is always true"),
9860 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9861 dreg
, 0, BFD_RELOC_LO16
);
9864 if (CPU_HAS_SEQ (mips_opts
.arch
)
9865 && -512 <= imm_expr
.X_add_number
9866 && imm_expr
.X_add_number
< 512)
9868 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9869 (int) imm_expr
.X_add_number
);
9872 if (imm_expr
.X_op
== O_constant
9873 && imm_expr
.X_add_number
>= 0
9874 && imm_expr
.X_add_number
< 0x10000)
9876 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9878 else if (imm_expr
.X_op
== O_constant
9879 && imm_expr
.X_add_number
> -0x8000
9880 && imm_expr
.X_add_number
< 0)
9882 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9883 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9884 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9886 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9889 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9890 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9895 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9896 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9899 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9914 if (!mips_opts
.micromips
)
9916 if (imm_expr
.X_op
== O_constant
9917 && imm_expr
.X_add_number
> -0x200
9918 && imm_expr
.X_add_number
<= 0x200)
9920 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9929 if (imm_expr
.X_op
== O_constant
9930 && imm_expr
.X_add_number
> -0x8000
9931 && imm_expr
.X_add_number
<= 0x8000)
9933 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9934 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9939 load_register (AT
, &imm_expr
, dbl
);
9940 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9962 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9963 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9968 gas_assert (!mips_opts
.micromips
);
9969 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9971 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9972 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9975 * Is the double cfc1 instruction a bug in the mips assembler;
9976 * or is there a reason for it?
9979 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9980 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9981 macro_build (NULL
, "nop", "");
9982 expr1
.X_add_number
= 3;
9983 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9984 expr1
.X_add_number
= 2;
9985 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9986 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9987 macro_build (NULL
, "nop", "");
9988 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9990 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9991 macro_build (NULL
, "nop", "");
10014 off12
= mips_opts
.micromips
;
10022 off12
= mips_opts
.micromips
;
10038 off12
= mips_opts
.micromips
;
10047 off12
= mips_opts
.micromips
;
10052 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10053 as_bad (_("Operand overflow"));
10056 expr1
.X_add_number
= 0;
10061 load_address (tempreg
, ep
, &used_at
);
10063 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10064 tempreg
, tempreg
, breg
);
10070 && (offset_expr
.X_op
!= O_constant
10071 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10072 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10076 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10077 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10082 else if (!ust
&& treg
== breg
)
10093 if (!target_big_endian
)
10094 ep
->X_add_number
+= off
;
10096 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10098 macro_build (NULL
, s
, "t,~(b)",
10099 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10101 if (!target_big_endian
)
10102 ep
->X_add_number
-= off
;
10104 ep
->X_add_number
+= off
;
10106 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10108 macro_build (NULL
, s2
, "t,~(b)",
10109 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10111 /* If necessary, move the result in tempreg to the final destination. */
10112 if (!ust
&& treg
!= tempreg
)
10114 /* Protect second load's delay slot. */
10116 move_register (treg
, tempreg
);
10122 if (target_big_endian
== ust
)
10123 ep
->X_add_number
+= off
;
10124 tempreg
= ust
|| ab
? treg
: AT
;
10125 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10127 /* For halfword transfers we need a temporary register to shuffle
10128 bytes. Unfortunately for M_USH_A we have none available before
10129 the next store as AT holds the base address. We deal with this
10130 case by clobbering TREG and then restoring it as with ULH. */
10131 tempreg
= ust
== ab
? treg
: AT
;
10133 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10135 if (target_big_endian
== ust
)
10136 ep
->X_add_number
-= off
;
10138 ep
->X_add_number
+= off
;
10139 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10141 /* For M_USH_A re-retrieve the LSB. */
10144 if (target_big_endian
)
10145 ep
->X_add_number
+= off
;
10147 ep
->X_add_number
-= off
;
10148 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10150 /* For ULH and M_USH_A OR the LSB in. */
10153 tempreg
= !ab
? AT
: treg
;
10154 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10155 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10160 /* FIXME: Check if this is one of the itbl macros, since they
10161 are added dynamically. */
10162 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10165 if (!mips_opts
.at
&& used_at
)
10166 as_bad (_("Macro used $at after \".set noat\""));
10169 /* Implement macros in mips16 mode. */
10172 mips16_macro (struct mips_cl_insn
*ip
)
10175 int xreg
, yreg
, zreg
, tmp
;
10178 const char *s
, *s2
, *s3
;
10180 mask
= ip
->insn_mo
->mask
;
10182 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10183 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10184 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10186 expr1
.X_op
= O_constant
;
10187 expr1
.X_op_symbol
= NULL
;
10188 expr1
.X_add_symbol
= NULL
;
10189 expr1
.X_add_number
= 1;
10208 start_noreorder ();
10209 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10210 expr1
.X_add_number
= 2;
10211 macro_build (&expr1
, "bnez", "x,p", yreg
);
10212 macro_build (NULL
, "break", "6", 7);
10214 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10215 since that causes an overflow. We should do that as well,
10216 but I don't see how to do the comparisons without a temporary
10219 macro_build (NULL
, s
, "x", zreg
);
10238 start_noreorder ();
10239 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10240 expr1
.X_add_number
= 2;
10241 macro_build (&expr1
, "bnez", "x,p", yreg
);
10242 macro_build (NULL
, "break", "6", 7);
10244 macro_build (NULL
, s2
, "x", zreg
);
10250 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10251 macro_build (NULL
, "mflo", "x", zreg
);
10259 if (imm_expr
.X_op
!= O_constant
)
10260 as_bad (_("Unsupported large constant"));
10261 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10262 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10266 if (imm_expr
.X_op
!= O_constant
)
10267 as_bad (_("Unsupported large constant"));
10268 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10269 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10273 if (imm_expr
.X_op
!= O_constant
)
10274 as_bad (_("Unsupported large constant"));
10275 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10276 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10298 goto do_reverse_branch
;
10302 goto do_reverse_branch
;
10314 goto do_reverse_branch
;
10325 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10326 macro_build (&offset_expr
, s2
, "p");
10353 goto do_addone_branch_i
;
10358 goto do_addone_branch_i
;
10373 goto do_addone_branch_i
;
10379 do_addone_branch_i
:
10380 if (imm_expr
.X_op
!= O_constant
)
10381 as_bad (_("Unsupported large constant"));
10382 ++imm_expr
.X_add_number
;
10385 macro_build (&imm_expr
, s
, s3
, xreg
);
10386 macro_build (&offset_expr
, s2
, "p");
10390 expr1
.X_add_number
= 0;
10391 macro_build (&expr1
, "slti", "x,8", yreg
);
10393 move_register (xreg
, yreg
);
10394 expr1
.X_add_number
= 2;
10395 macro_build (&expr1
, "bteqz", "p");
10396 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10400 /* For consistency checking, verify that all bits are specified either
10401 by the match/mask part of the instruction definition, or by the
10404 validate_mips_insn (const struct mips_opcode
*opc
)
10406 const char *p
= opc
->args
;
10408 unsigned long used_bits
= opc
->mask
;
10410 if ((used_bits
& opc
->match
) != opc
->match
)
10412 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10413 opc
->name
, opc
->args
);
10416 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10426 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10427 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10428 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10429 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10430 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10431 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10432 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10433 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10434 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10435 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10436 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10437 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10438 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10440 case 'J': USE_BITS (OP_MASK_CODE10
, OP_SH_CODE10
); break;
10441 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10442 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10443 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10444 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10445 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10446 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10447 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10448 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10449 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10450 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10451 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10452 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10453 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10454 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10455 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10458 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10459 c
, opc
->name
, opc
->args
);
10463 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10464 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10466 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10467 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10468 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10469 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10471 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10472 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10474 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10475 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10477 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10478 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10479 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10480 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10481 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10482 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10483 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10484 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10485 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10486 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10487 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10488 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10489 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10490 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10491 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10492 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10493 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10495 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10496 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10497 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10498 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10500 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10501 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10502 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10503 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10504 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10505 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10506 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10507 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10508 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10511 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10512 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10513 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10514 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10515 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10518 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10519 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10520 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10521 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10522 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10523 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10524 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10525 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10526 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10527 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10528 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10529 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10530 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10531 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10532 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10533 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10534 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10535 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10536 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10537 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10539 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10540 c
, opc
->name
, opc
->args
);
10544 if (used_bits
!= 0xffffffff)
10546 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10547 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10553 /* For consistency checking, verify that the length implied matches the
10554 major opcode and that all bits are specified either by the match/mask
10555 part of the instruction definition, or by the operand list. */
10558 validate_micromips_insn (const struct mips_opcode
*opc
)
10560 unsigned long match
= opc
->match
;
10561 unsigned long mask
= opc
->mask
;
10562 const char *p
= opc
->args
;
10563 unsigned long insn_bits
;
10564 unsigned long used_bits
;
10565 unsigned long major
;
10566 unsigned int length
;
10570 if ((mask
& match
) != match
)
10572 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10573 opc
->name
, opc
->args
);
10576 length
= micromips_insn_length (opc
);
10577 if (length
!= 2 && length
!= 4)
10579 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10580 "%s %s"), length
, opc
->name
, opc
->args
);
10583 major
= match
>> (10 + 8 * (length
- 2));
10584 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10585 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10587 as_bad (_("Internal error: bad microMIPS opcode "
10588 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10592 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10593 insn_bits
= 1 << 4 * length
;
10594 insn_bits
<<= 4 * length
;
10597 #define USE_BITS(field) \
10598 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10609 case 'A': USE_BITS (EXTLSB
); break;
10610 case 'B': USE_BITS (INSMSB
); break;
10611 case 'C': USE_BITS (EXTMSBD
); break;
10612 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10613 case 'E': USE_BITS (EXTLSB
); break;
10614 case 'F': USE_BITS (INSMSB
); break;
10615 case 'G': USE_BITS (EXTMSBD
); break;
10616 case 'H': USE_BITS (EXTMSBD
); break;
10618 as_bad (_("Internal error: bad mips opcode "
10619 "(unknown extension operand type `%c%c'): %s %s"),
10620 e
, c
, opc
->name
, opc
->args
);
10628 case 'A': USE_BITS (IMMA
); break;
10629 case 'B': USE_BITS (IMMB
); break;
10630 case 'C': USE_BITS (IMMC
); break;
10631 case 'D': USE_BITS (IMMD
); break;
10632 case 'E': USE_BITS (IMME
); break;
10633 case 'F': USE_BITS (IMMF
); break;
10634 case 'G': USE_BITS (IMMG
); break;
10635 case 'H': USE_BITS (IMMH
); break;
10636 case 'I': USE_BITS (IMMI
); break;
10637 case 'J': USE_BITS (IMMJ
); break;
10638 case 'L': USE_BITS (IMML
); break;
10639 case 'M': USE_BITS (IMMM
); break;
10640 case 'N': USE_BITS (IMMN
); break;
10641 case 'O': USE_BITS (IMMO
); break;
10642 case 'P': USE_BITS (IMMP
); break;
10643 case 'Q': USE_BITS (IMMQ
); break;
10644 case 'U': USE_BITS (IMMU
); break;
10645 case 'W': USE_BITS (IMMW
); break;
10646 case 'X': USE_BITS (IMMX
); break;
10647 case 'Y': USE_BITS (IMMY
); break;
10650 case 'b': USE_BITS (MB
); break;
10651 case 'c': USE_BITS (MC
); break;
10652 case 'd': USE_BITS (MD
); break;
10653 case 'e': USE_BITS (ME
); break;
10654 case 'f': USE_BITS (MF
); break;
10655 case 'g': USE_BITS (MG
); break;
10656 case 'h': USE_BITS (MH
); break;
10657 case 'i': USE_BITS (MI
); break;
10658 case 'j': USE_BITS (MJ
); break;
10659 case 'l': USE_BITS (ML
); break;
10660 case 'm': USE_BITS (MM
); break;
10661 case 'n': USE_BITS (MN
); break;
10662 case 'p': USE_BITS (MP
); break;
10663 case 'q': USE_BITS (MQ
); break;
10671 as_bad (_("Internal error: bad mips opcode "
10672 "(unknown extension operand type `%c%c'): %s %s"),
10673 e
, c
, opc
->name
, opc
->args
);
10677 case '.': USE_BITS (OFFSET10
); break;
10678 case '1': USE_BITS (STYPE
); break;
10679 case '2': USE_BITS (BP
); break;
10680 case '3': USE_BITS (SA3
); break;
10681 case '4': USE_BITS (SA4
); break;
10682 case '5': USE_BITS (IMM8
); break;
10683 case '6': USE_BITS (RS
); break;
10684 case '7': USE_BITS (DSPACC
); break;
10685 case '8': USE_BITS (WRDSP
); break;
10686 case '0': USE_BITS (DSPSFT
); break;
10687 case '<': USE_BITS (SHAMT
); break;
10688 case '>': USE_BITS (SHAMT
); break;
10689 case '@': USE_BITS (IMM10
); break;
10690 case 'B': USE_BITS (CODE10
); break;
10691 case 'C': USE_BITS (COPZ
); break;
10692 case 'D': USE_BITS (FD
); break;
10693 case 'E': USE_BITS (RT
); break;
10694 case 'G': USE_BITS (RS
); break;
10695 case 'H': USE_BITS (SEL
); break;
10696 case 'K': USE_BITS (RS
); break;
10697 case 'M': USE_BITS (CCC
); break;
10698 case 'N': USE_BITS (BCC
); break;
10699 case 'R': USE_BITS (FR
); break;
10700 case 'S': USE_BITS (FS
); break;
10701 case 'T': USE_BITS (FT
); break;
10702 case 'V': USE_BITS (FS
); break;
10703 case '\\': USE_BITS (3BITPOS
); break;
10704 case '^': USE_BITS (RD
); break;
10705 case 'a': USE_BITS (TARGET
); break;
10706 case 'b': USE_BITS (RS
); break;
10707 case 'c': USE_BITS (CODE
); break;
10708 case 'd': USE_BITS (RD
); break;
10709 case 'h': USE_BITS (PREFX
); break;
10710 case 'i': USE_BITS (IMMEDIATE
); break;
10711 case 'j': USE_BITS (DELTA
); break;
10712 case 'k': USE_BITS (CACHE
); break;
10713 case 'n': USE_BITS (RT
); break;
10714 case 'o': USE_BITS (DELTA
); break;
10715 case 'p': USE_BITS (DELTA
); break;
10716 case 'q': USE_BITS (CODE2
); break;
10717 case 'r': USE_BITS (RS
); break;
10718 case 's': USE_BITS (RS
); break;
10719 case 't': USE_BITS (RT
); break;
10720 case 'u': USE_BITS (IMMEDIATE
); break;
10721 case 'v': USE_BITS (RS
); break;
10722 case 'w': USE_BITS (RT
); break;
10723 case 'y': USE_BITS (RS3
); break;
10725 case '|': USE_BITS (TRAP
); break;
10726 case '~': USE_BITS (OFFSET12
); break;
10728 as_bad (_("Internal error: bad microMIPS opcode "
10729 "(unknown operand type `%c'): %s %s"),
10730 c
, opc
->name
, opc
->args
);
10734 if (used_bits
!= insn_bits
)
10736 if (~used_bits
& insn_bits
)
10737 as_bad (_("Internal error: bad microMIPS opcode "
10738 "(bits 0x%lx undefined): %s %s"),
10739 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10740 if (used_bits
& ~insn_bits
)
10741 as_bad (_("Internal error: bad microMIPS opcode "
10742 "(bits 0x%lx defined): %s %s"),
10743 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10749 /* UDI immediates. */
10750 struct mips_immed
{
10752 unsigned int shift
;
10753 unsigned long mask
;
10757 static const struct mips_immed mips_immed
[] = {
10758 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10759 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10760 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10761 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10765 /* Check whether an odd floating-point register is allowed. */
10767 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10769 const char *s
= insn
->name
;
10771 if (insn
->pinfo
== INSN_MACRO
)
10772 /* Let a macro pass, we'll catch it later when it is expanded. */
10775 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10777 /* Allow odd registers for single-precision ops. */
10778 switch (insn
->pinfo
& (FP_S
| FP_D
))
10782 return 1; /* both single precision - ok */
10784 return 0; /* both double precision - fail */
10789 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10790 s
= strchr (insn
->name
, '.');
10792 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10793 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10796 /* Single-precision coprocessor loads and moves are OK too. */
10797 if ((insn
->pinfo
& FP_S
)
10798 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10799 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10805 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10806 taking bits from BIT up. */
10808 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10810 return (ep
->X_op
== O_constant
10811 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10812 && ep
->X_add_number
>= min
<< bit
10813 && ep
->X_add_number
< max
<< bit
);
10816 /* This routine assembles an instruction into its binary format. As a
10817 side effect, it sets one of the global variables imm_reloc or
10818 offset_reloc to the type of relocation to do if one of the operands
10819 is an address expression. */
10822 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10824 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10825 bfd_boolean need_delay_slot_ok
= TRUE
;
10826 struct mips_opcode
*firstinsn
= NULL
;
10827 const struct mips_opcode
*past
;
10828 struct hash_control
*hash
;
10832 struct mips_opcode
*insn
;
10834 unsigned int regno
;
10835 unsigned int lastregno
;
10836 unsigned int destregno
= 0;
10837 unsigned int lastpos
= 0;
10838 unsigned int limlo
, limhi
;
10841 offsetT min_range
, max_range
;
10845 unsigned int rtype
;
10851 if (mips_opts
.micromips
)
10853 hash
= micromips_op_hash
;
10854 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10859 past
= &mips_opcodes
[NUMOPCODES
];
10861 forced_insn_length
= 0;
10864 /* We first try to match an instruction up to a space or to the end. */
10865 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10868 /* Make a copy of the instruction so that we can fiddle with it. */
10869 name
= alloca (end
+ 1);
10870 memcpy (name
, str
, end
);
10875 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10877 if (insn
!= NULL
|| !mips_opts
.micromips
)
10879 if (forced_insn_length
)
10882 /* See if there's an instruction size override suffix,
10883 either `16' or `32', at the end of the mnemonic proper,
10884 that defines the operation, i.e. before the first `.'
10885 character if any. Strip it and retry. */
10886 dot
= strchr (name
, '.');
10887 opend
= dot
!= NULL
? dot
- name
: end
;
10890 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10891 forced_insn_length
= 2;
10892 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10893 forced_insn_length
= 4;
10896 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10900 insn_error
= _("Unrecognized opcode");
10904 /* For microMIPS instructions placed in a fixed-length branch delay slot
10905 we make up to two passes over the relevant fragment of the opcode
10906 table. First we try instructions that meet the delay slot's length
10907 requirement. If none matched, then we retry with the remaining ones
10908 and if one matches, then we use it and then issue an appropriate
10909 warning later on. */
10910 argsStart
= s
= str
+ end
;
10913 bfd_boolean delay_slot_ok
;
10914 bfd_boolean size_ok
;
10917 gas_assert (strcmp (insn
->name
, name
) == 0);
10919 ok
= is_opcode_valid (insn
);
10920 size_ok
= is_size_valid (insn
);
10921 delay_slot_ok
= is_delay_slot_valid (insn
);
10922 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10925 wrong_delay_slot_insns
= TRUE
;
10927 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10929 static char buf
[256];
10931 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10936 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10938 gas_assert (firstinsn
);
10939 need_delay_slot_ok
= FALSE
;
10949 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10950 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10951 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10953 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10954 8 * forced_insn_length
);
10960 create_insn (ip
, insn
);
10963 lastregno
= 0xffffffff;
10964 for (args
= insn
->args
;; ++args
)
10968 s
+= strspn (s
, " \t");
10972 case '\0': /* end of args */
10978 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10979 code) or 14 (for microMIPS code). */
10980 my_getExpression (&imm_expr
, s
);
10981 check_absolute_expr (ip
, &imm_expr
);
10982 if ((unsigned long) imm_expr
.X_add_number
!= 1
10983 && (unsigned long) imm_expr
.X_add_number
!= 3)
10985 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10986 (unsigned long) imm_expr
.X_add_number
);
10988 INSERT_OPERAND (mips_opts
.micromips
,
10989 BP
, *ip
, imm_expr
.X_add_number
);
10990 imm_expr
.X_op
= O_absent
;
10995 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10996 code) or 21 (for microMIPS code). */
10998 unsigned long mask
= (mips_opts
.micromips
10999 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11001 my_getExpression (&imm_expr
, s
);
11002 check_absolute_expr (ip
, &imm_expr
);
11003 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11004 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11005 mask
, (unsigned long) imm_expr
.X_add_number
);
11006 INSERT_OPERAND (mips_opts
.micromips
,
11007 SA3
, *ip
, imm_expr
.X_add_number
);
11008 imm_expr
.X_op
= O_absent
;
11014 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11015 code) or 21 (for microMIPS code). */
11017 unsigned long mask
= (mips_opts
.micromips
11018 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11020 my_getExpression (&imm_expr
, s
);
11021 check_absolute_expr (ip
, &imm_expr
);
11022 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11023 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11024 mask
, (unsigned long) imm_expr
.X_add_number
);
11025 INSERT_OPERAND (mips_opts
.micromips
,
11026 SA4
, *ip
, imm_expr
.X_add_number
);
11027 imm_expr
.X_op
= O_absent
;
11033 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11034 code) or 16 (for microMIPS code). */
11036 unsigned long mask
= (mips_opts
.micromips
11037 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11039 my_getExpression (&imm_expr
, s
);
11040 check_absolute_expr (ip
, &imm_expr
);
11041 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11042 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11043 mask
, (unsigned long) imm_expr
.X_add_number
);
11044 INSERT_OPERAND (mips_opts
.micromips
,
11045 IMM8
, *ip
, imm_expr
.X_add_number
);
11046 imm_expr
.X_op
= O_absent
;
11052 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11053 code) or 21 (for microMIPS code). */
11055 unsigned long mask
= (mips_opts
.micromips
11056 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11058 my_getExpression (&imm_expr
, s
);
11059 check_absolute_expr (ip
, &imm_expr
);
11060 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11061 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11062 mask
, (unsigned long) imm_expr
.X_add_number
);
11063 INSERT_OPERAND (mips_opts
.micromips
,
11064 RS
, *ip
, imm_expr
.X_add_number
);
11065 imm_expr
.X_op
= O_absent
;
11070 case '7': /* Four DSP accumulators in bits 11,12. */
11071 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11072 && s
[3] >= '0' && s
[3] <= '3')
11074 regno
= s
[3] - '0';
11076 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11080 as_bad (_("Invalid dsp acc register"));
11084 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11085 code) or 14 (for microMIPS code). */
11087 unsigned long mask
= (mips_opts
.micromips
11088 ? MICROMIPSOP_MASK_WRDSP
11091 my_getExpression (&imm_expr
, s
);
11092 check_absolute_expr (ip
, &imm_expr
);
11093 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11094 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11095 mask
, (unsigned long) imm_expr
.X_add_number
);
11096 INSERT_OPERAND (mips_opts
.micromips
,
11097 WRDSP
, *ip
, imm_expr
.X_add_number
);
11098 imm_expr
.X_op
= O_absent
;
11103 case '9': /* Four DSP accumulators in bits 21,22. */
11104 gas_assert (!mips_opts
.micromips
);
11105 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11106 && s
[3] >= '0' && s
[3] <= '3')
11108 regno
= s
[3] - '0';
11110 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11114 as_bad (_("Invalid dsp acc register"));
11118 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11119 code) or 20 (for microMIPS code). */
11121 long mask
= (mips_opts
.micromips
11122 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11124 my_getExpression (&imm_expr
, s
);
11125 check_absolute_expr (ip
, &imm_expr
);
11126 min_range
= -((mask
+ 1) >> 1);
11127 max_range
= ((mask
+ 1) >> 1) - 1;
11128 if (imm_expr
.X_add_number
< min_range
11129 || imm_expr
.X_add_number
> max_range
)
11130 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11131 (long) min_range
, (long) max_range
,
11132 (long) imm_expr
.X_add_number
);
11133 INSERT_OPERAND (mips_opts
.micromips
,
11134 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11135 imm_expr
.X_op
= O_absent
;
11140 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11141 gas_assert (!mips_opts
.micromips
);
11142 my_getExpression (&imm_expr
, s
);
11143 check_absolute_expr (ip
, &imm_expr
);
11144 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11146 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11148 (unsigned long) imm_expr
.X_add_number
);
11150 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11151 imm_expr
.X_op
= O_absent
;
11155 case ':': /* DSP 7-bit signed immediate in bit 19. */
11156 gas_assert (!mips_opts
.micromips
);
11157 my_getExpression (&imm_expr
, s
);
11158 check_absolute_expr (ip
, &imm_expr
);
11159 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11160 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11161 if (imm_expr
.X_add_number
< min_range
||
11162 imm_expr
.X_add_number
> max_range
)
11164 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11165 (long) min_range
, (long) max_range
,
11166 (long) imm_expr
.X_add_number
);
11168 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11169 imm_expr
.X_op
= O_absent
;
11173 case '@': /* DSP 10-bit signed immediate in bit 16. */
11175 long mask
= (mips_opts
.micromips
11176 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11178 my_getExpression (&imm_expr
, s
);
11179 check_absolute_expr (ip
, &imm_expr
);
11180 min_range
= -((mask
+ 1) >> 1);
11181 max_range
= ((mask
+ 1) >> 1) - 1;
11182 if (imm_expr
.X_add_number
< min_range
11183 || imm_expr
.X_add_number
> max_range
)
11184 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11185 (long) min_range
, (long) max_range
,
11186 (long) imm_expr
.X_add_number
);
11187 INSERT_OPERAND (mips_opts
.micromips
,
11188 IMM10
, *ip
, imm_expr
.X_add_number
);
11189 imm_expr
.X_op
= O_absent
;
11194 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11195 gas_assert (mips_opts
.micromips
);
11196 my_getExpression (&imm_expr
, s
);
11197 check_absolute_expr (ip
, &imm_expr
);
11198 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11199 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11200 MICROMIPSOP_MASK_RD
,
11201 (unsigned long) imm_expr
.X_add_number
);
11202 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11203 imm_expr
.X_op
= O_absent
;
11207 case '!': /* MT usermode flag bit. */
11208 gas_assert (!mips_opts
.micromips
);
11209 my_getExpression (&imm_expr
, s
);
11210 check_absolute_expr (ip
, &imm_expr
);
11211 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11212 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11213 (unsigned long) imm_expr
.X_add_number
);
11214 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11215 imm_expr
.X_op
= O_absent
;
11219 case '$': /* MT load high flag bit. */
11220 gas_assert (!mips_opts
.micromips
);
11221 my_getExpression (&imm_expr
, s
);
11222 check_absolute_expr (ip
, &imm_expr
);
11223 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11224 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11225 (unsigned long) imm_expr
.X_add_number
);
11226 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11227 imm_expr
.X_op
= O_absent
;
11231 case '*': /* Four DSP accumulators in bits 18,19. */
11232 gas_assert (!mips_opts
.micromips
);
11233 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11234 s
[3] >= '0' && s
[3] <= '3')
11236 regno
= s
[3] - '0';
11238 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11242 as_bad (_("Invalid dsp/smartmips acc register"));
11245 case '&': /* Four DSP accumulators in bits 13,14. */
11246 gas_assert (!mips_opts
.micromips
);
11247 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11248 s
[3] >= '0' && s
[3] <= '3')
11250 regno
= s
[3] - '0';
11252 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11256 as_bad (_("Invalid dsp/smartmips acc register"));
11259 case '\\': /* 3-bit bit position. */
11261 unsigned long mask
= (mips_opts
.micromips
11262 ? MICROMIPSOP_MASK_3BITPOS
11263 : OP_MASK_3BITPOS
);
11265 my_getExpression (&imm_expr
, s
);
11266 check_absolute_expr (ip
, &imm_expr
);
11267 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11268 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11270 mask
, (unsigned long) imm_expr
.X_add_number
);
11271 INSERT_OPERAND (mips_opts
.micromips
,
11272 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11273 imm_expr
.X_op
= O_absent
;
11287 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11291 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11295 gas_assert (!mips_opts
.micromips
);
11296 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11300 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11306 /* Handle optional base register.
11307 Either the base register is omitted or
11308 we must have a left paren. */
11309 /* This is dependent on the next operand specifier
11310 is a base register specification. */
11311 gas_assert (args
[1] == 'b'
11312 || (mips_opts
.micromips
11314 && (args
[2] == 'l' || args
[2] == 'n'
11315 || args
[2] == 's' || args
[2] == 'a')));
11316 if (*s
== '\0' && args
[1] == 'b')
11318 /* Fall through. */
11320 case ')': /* These must match exactly. */
11325 case '[': /* These must match exactly. */
11327 gas_assert (!mips_opts
.micromips
);
11332 case '+': /* Opcode extension character. */
11335 case '1': /* UDI immediates. */
11339 gas_assert (!mips_opts
.micromips
);
11341 const struct mips_immed
*imm
= mips_immed
;
11343 while (imm
->type
&& imm
->type
!= *args
)
11347 my_getExpression (&imm_expr
, s
);
11348 check_absolute_expr (ip
, &imm_expr
);
11349 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11351 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11352 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11353 (unsigned long) imm_expr
.X_add_number
,
11354 (unsigned long) imm_expr
.X_add_number
);
11355 imm_expr
.X_add_number
&= imm
->mask
;
11357 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11359 imm_expr
.X_op
= O_absent
;
11364 case 'J': /* 10-bit hypcall code. */
11365 gas_assert (!mips_opts
.micromips
);
11367 unsigned long mask
= OP_MASK_CODE10
;
11369 my_getExpression (&imm_expr
, s
);
11370 check_absolute_expr (ip
, &imm_expr
);
11371 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11372 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11374 mask
, (unsigned long) imm_expr
.X_add_number
);
11375 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11376 imm_expr
.X_op
= O_absent
;
11381 case 'A': /* ins/ext position, becomes LSB. */
11390 my_getExpression (&imm_expr
, s
);
11391 check_absolute_expr (ip
, &imm_expr
);
11392 if ((unsigned long) imm_expr
.X_add_number
< limlo
11393 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11395 as_bad (_("Improper position (%lu)"),
11396 (unsigned long) imm_expr
.X_add_number
);
11397 imm_expr
.X_add_number
= limlo
;
11399 lastpos
= imm_expr
.X_add_number
;
11400 INSERT_OPERAND (mips_opts
.micromips
,
11401 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11402 imm_expr
.X_op
= O_absent
;
11406 case 'B': /* ins size, becomes MSB. */
11415 my_getExpression (&imm_expr
, s
);
11416 check_absolute_expr (ip
, &imm_expr
);
11417 /* Check for negative input so that small negative numbers
11418 will not succeed incorrectly. The checks against
11419 (pos+size) transitively check "size" itself,
11420 assuming that "pos" is reasonable. */
11421 if ((long) imm_expr
.X_add_number
< 0
11422 || ((unsigned long) imm_expr
.X_add_number
11424 || ((unsigned long) imm_expr
.X_add_number
11425 + lastpos
) > limhi
)
11427 as_bad (_("Improper insert size (%lu, position %lu)"),
11428 (unsigned long) imm_expr
.X_add_number
,
11429 (unsigned long) lastpos
);
11430 imm_expr
.X_add_number
= limlo
- lastpos
;
11432 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11433 lastpos
+ imm_expr
.X_add_number
- 1);
11434 imm_expr
.X_op
= O_absent
;
11438 case 'C': /* ext size, becomes MSBD. */
11454 my_getExpression (&imm_expr
, s
);
11455 check_absolute_expr (ip
, &imm_expr
);
11456 /* The checks against (pos+size) don't transitively check
11457 "size" itself, assuming that "pos" is reasonable.
11458 We also need to check the lower bound of "size". */
11459 if ((long) imm_expr
.X_add_number
< sizelo
11460 || ((unsigned long) imm_expr
.X_add_number
11462 || ((unsigned long) imm_expr
.X_add_number
11463 + lastpos
) > limhi
)
11465 as_bad (_("Improper extract size (%lu, position %lu)"),
11466 (unsigned long) imm_expr
.X_add_number
,
11467 (unsigned long) lastpos
);
11468 imm_expr
.X_add_number
= limlo
- lastpos
;
11470 INSERT_OPERAND (mips_opts
.micromips
,
11471 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11472 imm_expr
.X_op
= O_absent
;
11477 /* +D is for disassembly only; never match. */
11481 /* "+I" is like "I", except that imm2_expr is used. */
11482 my_getExpression (&imm2_expr
, s
);
11483 if (imm2_expr
.X_op
!= O_big
11484 && imm2_expr
.X_op
!= O_constant
)
11485 insn_error
= _("absolute expression required");
11486 if (HAVE_32BIT_GPRS
)
11487 normalize_constant_expr (&imm2_expr
);
11491 case 'T': /* Coprocessor register. */
11492 gas_assert (!mips_opts
.micromips
);
11493 /* +T is for disassembly only; never match. */
11496 case 't': /* Coprocessor register number. */
11497 gas_assert (!mips_opts
.micromips
);
11498 if (s
[0] == '$' && ISDIGIT (s
[1]))
11508 while (ISDIGIT (*s
));
11510 as_bad (_("Invalid register number (%d)"), regno
);
11513 INSERT_OPERAND (0, RT
, *ip
, regno
);
11518 as_bad (_("Invalid coprocessor 0 register number"));
11522 /* bbit[01] and bbit[01]32 bit index. Give error if index
11523 is not in the valid range. */
11524 gas_assert (!mips_opts
.micromips
);
11525 my_getExpression (&imm_expr
, s
);
11526 check_absolute_expr (ip
, &imm_expr
);
11527 if ((unsigned) imm_expr
.X_add_number
> 31)
11529 as_bad (_("Improper bit index (%lu)"),
11530 (unsigned long) imm_expr
.X_add_number
);
11531 imm_expr
.X_add_number
= 0;
11533 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11534 imm_expr
.X_op
= O_absent
;
11539 /* bbit[01] bit index when bbit is used but we generate
11540 bbit[01]32 because the index is over 32. Move to the
11541 next candidate if index is not in the valid range. */
11542 gas_assert (!mips_opts
.micromips
);
11543 my_getExpression (&imm_expr
, s
);
11544 check_absolute_expr (ip
, &imm_expr
);
11545 if ((unsigned) imm_expr
.X_add_number
< 32
11546 || (unsigned) imm_expr
.X_add_number
> 63)
11548 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11549 imm_expr
.X_op
= O_absent
;
11554 /* cins, cins32, exts and exts32 position field. Give error
11555 if it's not in the valid range. */
11556 gas_assert (!mips_opts
.micromips
);
11557 my_getExpression (&imm_expr
, s
);
11558 check_absolute_expr (ip
, &imm_expr
);
11559 if ((unsigned) imm_expr
.X_add_number
> 31)
11561 as_bad (_("Improper position (%lu)"),
11562 (unsigned long) imm_expr
.X_add_number
);
11563 imm_expr
.X_add_number
= 0;
11565 /* Make the pos explicit to simplify +S. */
11566 lastpos
= imm_expr
.X_add_number
+ 32;
11567 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11568 imm_expr
.X_op
= O_absent
;
11573 /* cins, cins32, exts and exts32 position field. Move to
11574 the next candidate if it's not in the valid range. */
11575 gas_assert (!mips_opts
.micromips
);
11576 my_getExpression (&imm_expr
, s
);
11577 check_absolute_expr (ip
, &imm_expr
);
11578 if ((unsigned) imm_expr
.X_add_number
< 32
11579 || (unsigned) imm_expr
.X_add_number
> 63)
11581 lastpos
= imm_expr
.X_add_number
;
11582 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11583 imm_expr
.X_op
= O_absent
;
11588 /* cins and exts length-minus-one field. */
11589 gas_assert (!mips_opts
.micromips
);
11590 my_getExpression (&imm_expr
, s
);
11591 check_absolute_expr (ip
, &imm_expr
);
11592 if ((unsigned long) imm_expr
.X_add_number
> 31)
11594 as_bad (_("Improper size (%lu)"),
11595 (unsigned long) imm_expr
.X_add_number
);
11596 imm_expr
.X_add_number
= 0;
11598 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11599 imm_expr
.X_op
= O_absent
;
11604 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11605 length-minus-one field. */
11606 gas_assert (!mips_opts
.micromips
);
11607 my_getExpression (&imm_expr
, s
);
11608 check_absolute_expr (ip
, &imm_expr
);
11609 if ((long) imm_expr
.X_add_number
< 0
11610 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11612 as_bad (_("Improper size (%lu)"),
11613 (unsigned long) imm_expr
.X_add_number
);
11614 imm_expr
.X_add_number
= 0;
11616 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11617 imm_expr
.X_op
= O_absent
;
11622 /* seqi/snei immediate field. */
11623 gas_assert (!mips_opts
.micromips
);
11624 my_getExpression (&imm_expr
, s
);
11625 check_absolute_expr (ip
, &imm_expr
);
11626 if ((long) imm_expr
.X_add_number
< -512
11627 || (long) imm_expr
.X_add_number
>= 512)
11629 as_bad (_("Improper immediate (%ld)"),
11630 (long) imm_expr
.X_add_number
);
11631 imm_expr
.X_add_number
= 0;
11633 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11634 imm_expr
.X_op
= O_absent
;
11638 case 'a': /* 8-bit signed offset in bit 6 */
11639 gas_assert (!mips_opts
.micromips
);
11640 my_getExpression (&imm_expr
, s
);
11641 check_absolute_expr (ip
, &imm_expr
);
11642 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11643 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11644 if (imm_expr
.X_add_number
< min_range
11645 || imm_expr
.X_add_number
> max_range
)
11647 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11648 (long) min_range
, (long) max_range
,
11649 (long) imm_expr
.X_add_number
);
11651 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11652 imm_expr
.X_op
= O_absent
;
11656 case 'b': /* 8-bit signed offset in bit 3 */
11657 gas_assert (!mips_opts
.micromips
);
11658 my_getExpression (&imm_expr
, s
);
11659 check_absolute_expr (ip
, &imm_expr
);
11660 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11661 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11662 if (imm_expr
.X_add_number
< min_range
11663 || imm_expr
.X_add_number
> max_range
)
11665 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11666 (long) min_range
, (long) max_range
,
11667 (long) imm_expr
.X_add_number
);
11669 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11670 imm_expr
.X_op
= O_absent
;
11674 case 'c': /* 9-bit signed offset in bit 6 */
11675 gas_assert (!mips_opts
.micromips
);
11676 my_getExpression (&imm_expr
, s
);
11677 check_absolute_expr (ip
, &imm_expr
);
11678 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11679 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11680 /* We check the offset range before adjusted. */
11683 if (imm_expr
.X_add_number
< min_range
11684 || imm_expr
.X_add_number
> max_range
)
11686 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11687 (long) min_range
, (long) max_range
,
11688 (long) imm_expr
.X_add_number
);
11690 if (imm_expr
.X_add_number
& 0xf)
11692 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11693 (long) imm_expr
.X_add_number
);
11695 /* Right shift 4 bits to adjust the offset operand. */
11696 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11697 imm_expr
.X_add_number
>> 4);
11698 imm_expr
.X_op
= O_absent
;
11703 gas_assert (!mips_opts
.micromips
);
11704 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11706 if (regno
== AT
&& mips_opts
.at
)
11708 if (mips_opts
.at
== ATREG
)
11709 as_warn (_("used $at without \".set noat\""));
11711 as_warn (_("used $%u with \".set at=$%u\""),
11712 regno
, mips_opts
.at
);
11714 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11718 gas_assert (!mips_opts
.micromips
);
11719 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11721 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11725 as_bad (_("Internal error: bad %s opcode "
11726 "(unknown extension operand type `+%c'): %s %s"),
11727 mips_opts
.micromips
? "microMIPS" : "MIPS",
11728 *args
, insn
->name
, insn
->args
);
11729 /* Further processing is fruitless. */
11734 case '.': /* 10-bit offset. */
11735 gas_assert (mips_opts
.micromips
);
11736 case '~': /* 12-bit offset. */
11738 int shift
= *args
== '.' ? 9 : 11;
11741 /* Check whether there is only a single bracketed expression
11742 left. If so, it must be the base register and the
11743 constant must be zero. */
11744 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11747 /* If this value won't fit into the offset, then go find
11748 a macro that will generate a 16- or 32-bit offset code
11750 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11751 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11752 || imm_expr
.X_add_number
>= 1 << shift
11753 || imm_expr
.X_add_number
< -1 << shift
))
11756 imm_expr
.X_op
= O_absent
;
11760 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11762 INSERT_OPERAND (mips_opts
.micromips
,
11763 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11764 imm_expr
.X_op
= O_absent
;
11769 case '<': /* must be at least one digit */
11771 * According to the manual, if the shift amount is greater
11772 * than 31 or less than 0, then the shift amount should be
11773 * mod 32. In reality the mips assembler issues an error.
11774 * We issue a warning and mask out all but the low 5 bits.
11776 my_getExpression (&imm_expr
, s
);
11777 check_absolute_expr (ip
, &imm_expr
);
11778 if ((unsigned long) imm_expr
.X_add_number
> 31)
11779 as_warn (_("Improper shift amount (%lu)"),
11780 (unsigned long) imm_expr
.X_add_number
);
11781 INSERT_OPERAND (mips_opts
.micromips
,
11782 SHAMT
, *ip
, imm_expr
.X_add_number
);
11783 imm_expr
.X_op
= O_absent
;
11787 case '>': /* shift amount minus 32 */
11788 my_getExpression (&imm_expr
, s
);
11789 check_absolute_expr (ip
, &imm_expr
);
11790 if ((unsigned long) imm_expr
.X_add_number
< 32
11791 || (unsigned long) imm_expr
.X_add_number
> 63)
11793 INSERT_OPERAND (mips_opts
.micromips
,
11794 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11795 imm_expr
.X_op
= O_absent
;
11799 case 'k': /* CACHE code. */
11800 case 'h': /* PREFX code. */
11801 case '1': /* SYNC type. */
11802 my_getExpression (&imm_expr
, s
);
11803 check_absolute_expr (ip
, &imm_expr
);
11804 if ((unsigned long) imm_expr
.X_add_number
> 31)
11805 as_warn (_("Invalid value for `%s' (%lu)"),
11807 (unsigned long) imm_expr
.X_add_number
);
11811 if (mips_fix_cn63xxp1
11812 && !mips_opts
.micromips
11813 && strcmp ("pref", insn
->name
) == 0)
11814 switch (imm_expr
.X_add_number
)
11823 case 31: /* These are ok. */
11826 default: /* The rest must be changed to 28. */
11827 imm_expr
.X_add_number
= 28;
11830 INSERT_OPERAND (mips_opts
.micromips
,
11831 CACHE
, *ip
, imm_expr
.X_add_number
);
11834 INSERT_OPERAND (mips_opts
.micromips
,
11835 PREFX
, *ip
, imm_expr
.X_add_number
);
11838 INSERT_OPERAND (mips_opts
.micromips
,
11839 STYPE
, *ip
, imm_expr
.X_add_number
);
11842 imm_expr
.X_op
= O_absent
;
11846 case 'c': /* BREAK code. */
11848 unsigned long mask
= (mips_opts
.micromips
11849 ? MICROMIPSOP_MASK_CODE
11852 my_getExpression (&imm_expr
, s
);
11853 check_absolute_expr (ip
, &imm_expr
);
11854 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11855 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11857 mask
, (unsigned long) imm_expr
.X_add_number
);
11858 INSERT_OPERAND (mips_opts
.micromips
,
11859 CODE
, *ip
, imm_expr
.X_add_number
);
11860 imm_expr
.X_op
= O_absent
;
11865 case 'q': /* Lower BREAK code. */
11867 unsigned long mask
= (mips_opts
.micromips
11868 ? MICROMIPSOP_MASK_CODE2
11871 my_getExpression (&imm_expr
, s
);
11872 check_absolute_expr (ip
, &imm_expr
);
11873 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11874 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11876 mask
, (unsigned long) imm_expr
.X_add_number
);
11877 INSERT_OPERAND (mips_opts
.micromips
,
11878 CODE2
, *ip
, imm_expr
.X_add_number
);
11879 imm_expr
.X_op
= O_absent
;
11884 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11886 unsigned long mask
= (mips_opts
.micromips
11887 ? MICROMIPSOP_MASK_CODE10
11890 my_getExpression (&imm_expr
, s
);
11891 check_absolute_expr (ip
, &imm_expr
);
11892 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11893 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11895 mask
, (unsigned long) imm_expr
.X_add_number
);
11896 if (mips_opts
.micromips
)
11897 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11899 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11900 imm_expr
.X_op
= O_absent
;
11905 case 'C': /* 25- or 23-bit coprocessor code. */
11907 unsigned long mask
= (mips_opts
.micromips
11908 ? MICROMIPSOP_MASK_COPZ
11911 my_getExpression (&imm_expr
, s
);
11912 check_absolute_expr (ip
, &imm_expr
);
11913 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11914 as_warn (_("Coproccesor code > %u bits (%lu)"),
11915 mips_opts
.micromips
? 23U : 25U,
11916 (unsigned long) imm_expr
.X_add_number
);
11917 INSERT_OPERAND (mips_opts
.micromips
,
11918 COPZ
, *ip
, imm_expr
.X_add_number
);
11919 imm_expr
.X_op
= O_absent
;
11924 case 'J': /* 19-bit WAIT code. */
11925 gas_assert (!mips_opts
.micromips
);
11926 my_getExpression (&imm_expr
, s
);
11927 check_absolute_expr (ip
, &imm_expr
);
11928 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11930 as_warn (_("Illegal 19-bit code (%lu)"),
11931 (unsigned long) imm_expr
.X_add_number
);
11932 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11934 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11935 imm_expr
.X_op
= O_absent
;
11939 case 'P': /* Performance register. */
11940 gas_assert (!mips_opts
.micromips
);
11941 my_getExpression (&imm_expr
, s
);
11942 check_absolute_expr (ip
, &imm_expr
);
11943 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11944 as_warn (_("Invalid performance register (%lu)"),
11945 (unsigned long) imm_expr
.X_add_number
);
11946 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
11947 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
11948 as_warn (_("Invalid performance register (%lu)"),
11949 (unsigned long) imm_expr
.X_add_number
);
11950 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11951 imm_expr
.X_op
= O_absent
;
11955 case 'G': /* Coprocessor destination register. */
11957 unsigned long opcode
= ip
->insn_opcode
;
11958 unsigned long mask
;
11959 unsigned int types
;
11962 if (mips_opts
.micromips
)
11964 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11965 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11966 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11970 case 0x000000fc: /* mfc0 */
11971 case 0x000002fc: /* mtc0 */
11972 case 0x580000fc: /* dmfc0 */
11973 case 0x580002fc: /* dmtc0 */
11983 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11984 cop0
= opcode
== OP_OP_COP0
;
11986 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11987 ok
= reg_lookup (&s
, types
, ®no
);
11988 if (mips_opts
.micromips
)
11989 INSERT_OPERAND (1, RS
, *ip
, regno
);
11991 INSERT_OPERAND (0, RD
, *ip
, regno
);
12000 case 'y': /* ALNV.PS source register. */
12001 gas_assert (mips_opts
.micromips
);
12003 case 'x': /* Ignore register name. */
12004 case 'U': /* Destination register (CLO/CLZ). */
12005 case 'g': /* Coprocessor destination register. */
12006 gas_assert (!mips_opts
.micromips
);
12007 case 'b': /* Base register. */
12008 case 'd': /* Destination register. */
12009 case 's': /* Source register. */
12010 case 't': /* Target register. */
12011 case 'r': /* Both target and source. */
12012 case 'v': /* Both dest and source. */
12013 case 'w': /* Both dest and target. */
12014 case 'E': /* Coprocessor target register. */
12015 case 'K': /* RDHWR destination register. */
12016 case 'z': /* Must be zero register. */
12019 if (*args
== 'E' || *args
== 'K')
12020 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12023 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12024 if (regno
== AT
&& mips_opts
.at
)
12026 if (mips_opts
.at
== ATREG
)
12027 as_warn (_("Used $at without \".set noat\""));
12029 as_warn (_("Used $%u with \".set at=$%u\""),
12030 regno
, mips_opts
.at
);
12040 if (c
== 'r' || c
== 'v' || c
== 'w')
12047 /* 'z' only matches $0. */
12048 if (c
== 'z' && regno
!= 0)
12051 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12053 if (regno
== lastregno
)
12056 = _("Source and destination must be different");
12059 if (regno
== 31 && lastregno
== 0xffffffff)
12062 = _("A destination register must be supplied");
12066 /* Now that we have assembled one operand, we use the args
12067 string to figure out where it goes in the instruction. */
12074 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12078 if (mips_opts
.micromips
)
12079 INSERT_OPERAND (1, RS
, *ip
, regno
);
12081 INSERT_OPERAND (0, RD
, *ip
, regno
);
12086 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12090 gas_assert (!mips_opts
.micromips
);
12091 INSERT_OPERAND (0, RD
, *ip
, regno
);
12092 INSERT_OPERAND (0, RT
, *ip
, regno
);
12098 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12102 gas_assert (mips_opts
.micromips
);
12103 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12107 /* This case exists because on the r3000 trunc
12108 expands into a macro which requires a gp
12109 register. On the r6000 or r4000 it is
12110 assembled into a single instruction which
12111 ignores the register. Thus the insn version
12112 is MIPS_ISA2 and uses 'x', and the macro
12113 version is MIPS_ISA1 and uses 't'. */
12117 /* This case is for the div instruction, which
12118 acts differently if the destination argument
12119 is $0. This only matches $0, and is checked
12120 outside the switch. */
12130 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12134 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12139 case 'O': /* MDMX alignment immediate constant. */
12140 gas_assert (!mips_opts
.micromips
);
12141 my_getExpression (&imm_expr
, s
);
12142 check_absolute_expr (ip
, &imm_expr
);
12143 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12144 as_warn (_("Improper align amount (%ld), using low bits"),
12145 (long) imm_expr
.X_add_number
);
12146 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12147 imm_expr
.X_op
= O_absent
;
12151 case 'Q': /* MDMX vector, element sel, or const. */
12154 /* MDMX Immediate. */
12155 gas_assert (!mips_opts
.micromips
);
12156 my_getExpression (&imm_expr
, s
);
12157 check_absolute_expr (ip
, &imm_expr
);
12158 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12159 as_warn (_("Invalid MDMX Immediate (%ld)"),
12160 (long) imm_expr
.X_add_number
);
12161 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12162 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12163 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12165 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12166 imm_expr
.X_op
= O_absent
;
12170 /* Not MDMX Immediate. Fall through. */
12171 case 'X': /* MDMX destination register. */
12172 case 'Y': /* MDMX source register. */
12173 case 'Z': /* MDMX target register. */
12176 gas_assert (!mips_opts
.micromips
);
12177 case 'D': /* Floating point destination register. */
12178 case 'S': /* Floating point source register. */
12179 case 'T': /* Floating point target register. */
12180 case 'R': /* Floating point source register. */
12184 || (mips_opts
.ase_mdmx
12185 && (ip
->insn_mo
->pinfo
& FP_D
)
12186 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12187 | INSN_COPROC_MEMORY_DELAY
12188 | INSN_LOAD_COPROC_DELAY
12189 | INSN_LOAD_MEMORY_DELAY
12190 | INSN_STORE_MEMORY
))))
12191 rtype
|= RTYPE_VEC
;
12193 if (reg_lookup (&s
, rtype
, ®no
))
12195 if ((regno
& 1) != 0
12197 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12198 as_warn (_("Float register should be even, was %d"),
12206 if (c
== 'V' || c
== 'W')
12217 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12223 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12227 /* This is like 'Z', but also needs to fix the MDMX
12228 vector/scalar select bits. Note that the
12229 scalar immediate case is handled above. */
12232 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12233 int max_el
= (is_qh
? 3 : 7);
12235 my_getExpression(&imm_expr
, s
);
12236 check_absolute_expr (ip
, &imm_expr
);
12238 if (imm_expr
.X_add_number
> max_el
)
12239 as_bad (_("Bad element selector %ld"),
12240 (long) imm_expr
.X_add_number
);
12241 imm_expr
.X_add_number
&= max_el
;
12242 ip
->insn_opcode
|= (imm_expr
.X_add_number
12245 imm_expr
.X_op
= O_absent
;
12247 as_warn (_("Expecting ']' found '%s'"), s
);
12253 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12254 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12257 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12260 /* Fall through. */
12264 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12268 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12278 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12282 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12288 my_getExpression (&imm_expr
, s
);
12289 if (imm_expr
.X_op
!= O_big
12290 && imm_expr
.X_op
!= O_constant
)
12291 insn_error
= _("absolute expression required");
12292 if (HAVE_32BIT_GPRS
)
12293 normalize_constant_expr (&imm_expr
);
12298 my_getExpression (&offset_expr
, s
);
12299 normalize_address_expr (&offset_expr
);
12300 *imm_reloc
= BFD_RELOC_32
;
12313 unsigned char temp
[8];
12315 unsigned int length
;
12320 /* These only appear as the last operand in an
12321 instruction, and every instruction that accepts
12322 them in any variant accepts them in all variants.
12323 This means we don't have to worry about backing out
12324 any changes if the instruction does not match.
12326 The difference between them is the size of the
12327 floating point constant and where it goes. For 'F'
12328 and 'L' the constant is 64 bits; for 'f' and 'l' it
12329 is 32 bits. Where the constant is placed is based
12330 on how the MIPS assembler does things:
12333 f -- immediate value
12336 The .lit4 and .lit8 sections are only used if
12337 permitted by the -G argument.
12339 The code below needs to know whether the target register
12340 is 32 or 64 bits wide. It relies on the fact 'f' and
12341 'F' are used with GPR-based instructions and 'l' and
12342 'L' are used with FPR-based instructions. */
12344 f64
= *args
== 'F' || *args
== 'L';
12345 using_gprs
= *args
== 'F' || *args
== 'f';
12347 save_in
= input_line_pointer
;
12348 input_line_pointer
= s
;
12349 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12351 s
= input_line_pointer
;
12352 input_line_pointer
= save_in
;
12353 if (err
!= NULL
&& *err
!= '\0')
12355 as_bad (_("Bad floating point constant: %s"), err
);
12356 memset (temp
, '\0', sizeof temp
);
12357 length
= f64
? 8 : 4;
12360 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12364 && (g_switch_value
< 4
12365 || (temp
[0] == 0 && temp
[1] == 0)
12366 || (temp
[2] == 0 && temp
[3] == 0))))
12368 imm_expr
.X_op
= O_constant
;
12369 if (!target_big_endian
)
12370 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12372 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12374 else if (length
> 4
12375 && !mips_disable_float_construction
12376 /* Constants can only be constructed in GPRs and
12377 copied to FPRs if the GPRs are at least as wide
12378 as the FPRs. Force the constant into memory if
12379 we are using 64-bit FPRs but the GPRs are only
12382 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12383 && ((temp
[0] == 0 && temp
[1] == 0)
12384 || (temp
[2] == 0 && temp
[3] == 0))
12385 && ((temp
[4] == 0 && temp
[5] == 0)
12386 || (temp
[6] == 0 && temp
[7] == 0)))
12388 /* The value is simple enough to load with a couple of
12389 instructions. If using 32-bit registers, set
12390 imm_expr to the high order 32 bits and offset_expr to
12391 the low order 32 bits. Otherwise, set imm_expr to
12392 the entire 64 bit constant. */
12393 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12395 imm_expr
.X_op
= O_constant
;
12396 offset_expr
.X_op
= O_constant
;
12397 if (!target_big_endian
)
12399 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12400 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12404 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12405 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12407 if (offset_expr
.X_add_number
== 0)
12408 offset_expr
.X_op
= O_absent
;
12410 else if (sizeof (imm_expr
.X_add_number
) > 4)
12412 imm_expr
.X_op
= O_constant
;
12413 if (!target_big_endian
)
12414 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12416 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12420 imm_expr
.X_op
= O_big
;
12421 imm_expr
.X_add_number
= 4;
12422 if (!target_big_endian
)
12424 generic_bignum
[0] = bfd_getl16 (temp
);
12425 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12426 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12427 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12431 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12432 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12433 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12434 generic_bignum
[3] = bfd_getb16 (temp
);
12440 const char *newname
;
12443 /* Switch to the right section. */
12445 subseg
= now_subseg
;
12448 default: /* unused default case avoids warnings. */
12450 newname
= RDATA_SECTION_NAME
;
12451 if (g_switch_value
>= 8)
12455 newname
= RDATA_SECTION_NAME
;
12458 gas_assert (g_switch_value
>= 4);
12462 new_seg
= subseg_new (newname
, (subsegT
) 0);
12464 bfd_set_section_flags (stdoutput
, new_seg
,
12469 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12470 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12471 record_alignment (new_seg
, 4);
12473 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12474 if (seg
== now_seg
)
12475 as_bad (_("Can't use floating point insn in this section"));
12477 /* Set the argument to the current address in the
12479 offset_expr
.X_op
= O_symbol
;
12480 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12481 offset_expr
.X_add_number
= 0;
12483 /* Put the floating point number into the section. */
12484 p
= frag_more ((int) length
);
12485 memcpy (p
, temp
, length
);
12487 /* Switch back to the original section. */
12488 subseg_set (seg
, subseg
);
12493 case 'i': /* 16-bit unsigned immediate. */
12494 case 'j': /* 16-bit signed immediate. */
12495 *imm_reloc
= BFD_RELOC_LO16
;
12496 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12499 offsetT minval
, maxval
;
12501 more
= (insn
+ 1 < past
12502 && strcmp (insn
->name
, insn
[1].name
) == 0);
12504 /* If the expression was written as an unsigned number,
12505 only treat it as signed if there are no more
12509 && sizeof (imm_expr
.X_add_number
) <= 4
12510 && imm_expr
.X_op
== O_constant
12511 && imm_expr
.X_add_number
< 0
12512 && imm_expr
.X_unsigned
12513 && HAVE_64BIT_GPRS
)
12516 /* For compatibility with older assemblers, we accept
12517 0x8000-0xffff as signed 16-bit numbers when only
12518 signed numbers are allowed. */
12520 minval
= 0, maxval
= 0xffff;
12522 minval
= -0x8000, maxval
= 0x7fff;
12524 minval
= -0x8000, maxval
= 0xffff;
12526 if (imm_expr
.X_op
!= O_constant
12527 || imm_expr
.X_add_number
< minval
12528 || imm_expr
.X_add_number
> maxval
)
12532 if (imm_expr
.X_op
== O_constant
12533 || imm_expr
.X_op
== O_big
)
12534 as_bad (_("Expression out of range"));
12540 case 'o': /* 16-bit offset. */
12541 offset_reloc
[0] = BFD_RELOC_LO16
;
12542 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12543 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12545 /* Check whether there is only a single bracketed expression
12546 left. If so, it must be the base register and the
12547 constant must be zero. */
12548 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12550 offset_expr
.X_op
= O_constant
;
12551 offset_expr
.X_add_number
= 0;
12555 /* If this value won't fit into a 16 bit offset, then go
12556 find a macro that will generate the 32 bit offset
12558 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12559 && (offset_expr
.X_op
!= O_constant
12560 || offset_expr
.X_add_number
>= 0x8000
12561 || offset_expr
.X_add_number
< -0x8000))
12567 case 'p': /* PC-relative offset. */
12568 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12569 my_getExpression (&offset_expr
, s
);
12573 case 'u': /* Upper 16 bits. */
12574 *imm_reloc
= BFD_RELOC_LO16
;
12575 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12576 && imm_expr
.X_op
== O_constant
12577 && (imm_expr
.X_add_number
< 0
12578 || imm_expr
.X_add_number
>= 0x10000))
12579 as_bad (_("lui expression (%lu) not in range 0..65535"),
12580 (unsigned long) imm_expr
.X_add_number
);
12584 case 'a': /* 26-bit address. */
12585 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12586 my_getExpression (&offset_expr
, s
);
12590 case 'N': /* 3-bit branch condition code. */
12591 case 'M': /* 3-bit compare condition code. */
12593 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12594 rtype
|= RTYPE_FCC
;
12595 if (!reg_lookup (&s
, rtype
, ®no
))
12597 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12598 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12599 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12600 && (regno
& 1) != 0)
12601 as_warn (_("Condition code register should be even for %s, "
12604 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12605 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12606 && (regno
& 3) != 0)
12607 as_warn (_("Condition code register should be 0 or 4 for %s, "
12611 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12613 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12617 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12628 while (ISDIGIT (*s
));
12631 c
= 8; /* Invalid sel value. */
12634 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12635 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12639 gas_assert (!mips_opts
.micromips
);
12640 /* Must be at least one digit. */
12641 my_getExpression (&imm_expr
, s
);
12642 check_absolute_expr (ip
, &imm_expr
);
12644 if ((unsigned long) imm_expr
.X_add_number
12645 > (unsigned long) OP_MASK_VECBYTE
)
12647 as_bad (_("bad byte vector index (%ld)"),
12648 (long) imm_expr
.X_add_number
);
12649 imm_expr
.X_add_number
= 0;
12652 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12653 imm_expr
.X_op
= O_absent
;
12658 gas_assert (!mips_opts
.micromips
);
12659 my_getExpression (&imm_expr
, s
);
12660 check_absolute_expr (ip
, &imm_expr
);
12662 if ((unsigned long) imm_expr
.X_add_number
12663 > (unsigned long) OP_MASK_VECALIGN
)
12665 as_bad (_("bad byte vector index (%ld)"),
12666 (long) imm_expr
.X_add_number
);
12667 imm_expr
.X_add_number
= 0;
12670 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12671 imm_expr
.X_op
= O_absent
;
12675 case 'm': /* Opcode extension character. */
12676 gas_assert (mips_opts
.micromips
);
12681 if (strncmp (s
, "$pc", 3) == 0)
12709 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12710 if (regno
== AT
&& mips_opts
.at
)
12712 if (mips_opts
.at
== ATREG
)
12713 as_warn (_("Used $at without \".set noat\""));
12715 as_warn (_("Used $%u with \".set at=$%u\""),
12716 regno
, mips_opts
.at
);
12722 gas_assert (args
[1] == ',');
12728 gas_assert (args
[1] == ',');
12730 continue; /* Nothing to do. */
12736 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12738 if (regno
== lastregno
)
12741 = _("Source and destination must be different");
12744 if (regno
== 31 && lastregno
== 0xffffffff)
12747 = _("A destination register must be supplied");
12758 gas_assert (args
[1] == ',');
12765 gas_assert (args
[1] == ',');
12768 continue; /* Nothing to do. */
12772 /* Make sure regno is the same as lastregno. */
12773 if (c
== 't' && regno
!= lastregno
)
12776 /* Make sure regno is the same as destregno. */
12777 if (c
== 'x' && regno
!= destregno
)
12780 /* We need to save regno, before regno maps to the
12781 microMIPS register encoding. */
12791 regno
= ILLEGAL_REG
;
12795 regno
= mips32_to_micromips_reg_b_map
[regno
];
12799 regno
= mips32_to_micromips_reg_c_map
[regno
];
12803 regno
= mips32_to_micromips_reg_d_map
[regno
];
12807 regno
= mips32_to_micromips_reg_e_map
[regno
];
12811 regno
= mips32_to_micromips_reg_f_map
[regno
];
12815 regno
= mips32_to_micromips_reg_g_map
[regno
];
12819 regno
= mips32_to_micromips_reg_h_map
[regno
];
12823 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12828 else if (regno
== 22)
12830 else if (regno
== 5)
12832 else if (regno
== 6)
12834 else if (regno
== 7)
12837 regno
= ILLEGAL_REG
;
12843 else if (regno
== 7)
12846 regno
= ILLEGAL_REG
;
12853 regno
= ILLEGAL_REG
;
12857 regno
= ILLEGAL_REG
;
12863 regno
= mips32_to_micromips_reg_l_map
[regno
];
12867 regno
= mips32_to_micromips_reg_m_map
[regno
];
12871 regno
= mips32_to_micromips_reg_n_map
[regno
];
12875 regno
= mips32_to_micromips_reg_q_map
[regno
];
12880 regno
= ILLEGAL_REG
;
12885 regno
= ILLEGAL_REG
;
12890 regno
= ILLEGAL_REG
;
12893 case 'j': /* Do nothing. */
12903 if (regno
== ILLEGAL_REG
)
12909 INSERT_OPERAND (1, MB
, *ip
, regno
);
12913 INSERT_OPERAND (1, MC
, *ip
, regno
);
12917 INSERT_OPERAND (1, MD
, *ip
, regno
);
12921 INSERT_OPERAND (1, ME
, *ip
, regno
);
12925 INSERT_OPERAND (1, MF
, *ip
, regno
);
12929 INSERT_OPERAND (1, MG
, *ip
, regno
);
12933 INSERT_OPERAND (1, MH
, *ip
, regno
);
12937 INSERT_OPERAND (1, MI
, *ip
, regno
);
12941 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12945 INSERT_OPERAND (1, ML
, *ip
, regno
);
12949 INSERT_OPERAND (1, MM
, *ip
, regno
);
12953 INSERT_OPERAND (1, MN
, *ip
, regno
);
12957 INSERT_OPERAND (1, MP
, *ip
, regno
);
12961 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12964 case 'a': /* Do nothing. */
12965 case 's': /* Do nothing. */
12966 case 't': /* Do nothing. */
12967 case 'x': /* Do nothing. */
12968 case 'y': /* Do nothing. */
12969 case 'z': /* Do nothing. */
12979 bfd_reloc_code_real_type r
[3];
12983 /* Check whether there is only a single bracketed
12984 expression left. If so, it must be the base register
12985 and the constant must be zero. */
12986 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12988 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12992 if (my_getSmallExpression (&ep
, r
, s
) > 0
12993 || !expr_const_in_range (&ep
, -64, 64, 2))
12996 imm
= ep
.X_add_number
>> 2;
12997 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13004 bfd_reloc_code_real_type r
[3];
13008 if (my_getSmallExpression (&ep
, r
, s
) > 0
13009 || ep
.X_op
!= O_constant
)
13012 for (imm
= 0; imm
< 8; imm
++)
13013 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13018 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13025 bfd_reloc_code_real_type r
[3];
13029 if (my_getSmallExpression (&ep
, r
, s
) > 0
13030 || ep
.X_op
!= O_constant
)
13033 for (imm
= 0; imm
< 16; imm
++)
13034 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13039 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13044 case 'D': /* pc relative offset */
13045 case 'E': /* pc relative offset */
13046 my_getExpression (&offset_expr
, s
);
13047 if (offset_expr
.X_op
== O_register
)
13050 if (!forced_insn_length
)
13051 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13053 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13055 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13061 bfd_reloc_code_real_type r
[3];
13065 if (my_getSmallExpression (&ep
, r
, s
) > 0
13066 || !expr_const_in_range (&ep
, 0, 16, 0))
13069 imm
= ep
.X_add_number
;
13070 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13077 bfd_reloc_code_real_type r
[3];
13081 /* Check whether there is only a single bracketed
13082 expression left. If so, it must be the base register
13083 and the constant must be zero. */
13084 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13086 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13090 if (my_getSmallExpression (&ep
, r
, s
) > 0
13091 || !expr_const_in_range (&ep
, -1, 15, 0))
13094 imm
= ep
.X_add_number
& 15;
13095 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13102 bfd_reloc_code_real_type r
[3];
13106 /* Check whether there is only a single bracketed
13107 expression left. If so, it must be the base register
13108 and the constant must be zero. */
13109 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13111 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13115 if (my_getSmallExpression (&ep
, r
, s
) > 0
13116 || !expr_const_in_range (&ep
, 0, 16, 1))
13119 imm
= ep
.X_add_number
>> 1;
13120 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13127 bfd_reloc_code_real_type r
[3];
13131 if (my_getSmallExpression (&ep
, r
, s
) > 0
13132 || !expr_const_in_range (&ep
, -1, 127, 0))
13135 imm
= ep
.X_add_number
& 127;
13136 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13143 bfd_reloc_code_real_type r
[3];
13147 /* Check whether there is only a single bracketed
13148 expression left. If so, it must be the base register
13149 and the constant must be zero. */
13150 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13152 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13156 if (my_getSmallExpression (&ep
, r
, s
) > 0
13157 || !expr_const_in_range (&ep
, 0, 16, 2))
13160 imm
= ep
.X_add_number
>> 2;
13161 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13168 bfd_reloc_code_real_type r
[3];
13172 /* Check whether there is only a single bracketed
13173 expression left. If so, it must be the base register
13174 and the constant must be zero. */
13175 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13177 INSERT_OPERAND (1, IMML
, *ip
, 0);
13181 if (my_getSmallExpression (&ep
, r
, s
) > 0
13182 || !expr_const_in_range (&ep
, 0, 16, 0))
13185 imm
= ep
.X_add_number
;
13186 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13193 bfd_reloc_code_real_type r
[3];
13197 if (my_getSmallExpression (&ep
, r
, s
) > 0
13198 || !expr_const_in_range (&ep
, 1, 9, 0))
13201 imm
= ep
.X_add_number
& 7;
13202 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13207 case 'N': /* Register list for lwm and swm. */
13209 /* A comma-separated list of registers and/or
13210 dash-separated contiguous ranges including
13211 both ra and a set of one or more registers
13212 starting at s0 up to s3 which have to be
13219 and any permutations of these. */
13220 unsigned int reglist
;
13223 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13226 if ((reglist
& 0xfff1ffff) != 0x80010000)
13229 reglist
= (reglist
>> 17) & 7;
13231 if ((reglist
& -reglist
) != reglist
)
13234 imm
= ffs (reglist
) - 1;
13235 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13239 case 'O': /* sdbbp 4-bit code. */
13241 bfd_reloc_code_real_type r
[3];
13245 if (my_getSmallExpression (&ep
, r
, s
) > 0
13246 || !expr_const_in_range (&ep
, 0, 16, 0))
13249 imm
= ep
.X_add_number
;
13250 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13257 bfd_reloc_code_real_type r
[3];
13261 if (my_getSmallExpression (&ep
, r
, s
) > 0
13262 || !expr_const_in_range (&ep
, 0, 32, 2))
13265 imm
= ep
.X_add_number
>> 2;
13266 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13273 bfd_reloc_code_real_type r
[3];
13277 if (my_getSmallExpression (&ep
, r
, s
) > 0
13278 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13281 imm
= ep
.X_add_number
>> 2;
13282 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13289 bfd_reloc_code_real_type r
[3];
13293 /* Check whether there is only a single bracketed
13294 expression left. If so, it must be the base register
13295 and the constant must be zero. */
13296 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13298 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13302 if (my_getSmallExpression (&ep
, r
, s
) > 0
13303 || !expr_const_in_range (&ep
, 0, 32, 2))
13306 imm
= ep
.X_add_number
>> 2;
13307 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13314 bfd_reloc_code_real_type r
[3];
13318 if (my_getSmallExpression (&ep
, r
, s
) > 0
13319 || !expr_const_in_range (&ep
, 0, 64, 2))
13322 imm
= ep
.X_add_number
>> 2;
13323 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13330 bfd_reloc_code_real_type r
[3];
13334 if (my_getSmallExpression (&ep
, r
, s
) > 0
13335 || !expr_const_in_range (&ep
, -8, 8, 0))
13338 imm
= ep
.X_add_number
;
13339 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13346 bfd_reloc_code_real_type r
[3];
13350 if (my_getSmallExpression (&ep
, r
, s
) > 0
13351 || expr_const_in_range (&ep
, -2, 2, 2)
13352 || !expr_const_in_range (&ep
, -258, 258, 2))
13355 imm
= ep
.X_add_number
>> 2;
13356 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13357 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13364 bfd_reloc_code_real_type r
[3];
13367 if (my_getSmallExpression (&ep
, r
, s
) > 0
13368 || !expr_const_in_range (&ep
, 0, 1, 0))
13375 as_bad (_("Internal error: bad microMIPS opcode "
13376 "(unknown extension operand type `m%c'): %s %s"),
13377 *args
, insn
->name
, insn
->args
);
13378 /* Further processing is fruitless. */
13383 case 'n': /* Register list for 32-bit lwm and swm. */
13384 gas_assert (mips_opts
.micromips
);
13386 /* A comma-separated list of registers and/or
13387 dash-separated contiguous ranges including
13388 at least one of ra and a set of one or more
13389 registers starting at s0 up to s7 and then
13390 s8 which have to be consecutive, e.g.:
13398 and any permutations of these. */
13399 unsigned int reglist
;
13403 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13406 if ((reglist
& 0x3f00ffff) != 0)
13409 ra
= (reglist
>> 27) & 0x10;
13410 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13412 if ((reglist
& -reglist
) != reglist
)
13415 imm
= (ffs (reglist
) - 1) | ra
;
13416 INSERT_OPERAND (1, RT
, *ip
, imm
);
13417 imm_expr
.X_op
= O_absent
;
13421 case '|': /* 4-bit trap code. */
13422 gas_assert (mips_opts
.micromips
);
13423 my_getExpression (&imm_expr
, s
);
13424 check_absolute_expr (ip
, &imm_expr
);
13425 if ((unsigned long) imm_expr
.X_add_number
13426 > MICROMIPSOP_MASK_TRAP
)
13427 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13428 (unsigned long) imm_expr
.X_add_number
,
13429 ip
->insn_mo
->name
);
13430 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13431 imm_expr
.X_op
= O_absent
;
13436 as_bad (_("Bad char = '%c'\n"), *args
);
13441 /* Args don't match. */
13443 insn_error
= _("Illegal operands");
13444 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13449 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13451 gas_assert (firstinsn
);
13452 need_delay_slot_ok
= FALSE
;
13461 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13463 /* This routine assembles an instruction into its binary format when
13464 assembling for the mips16. As a side effect, it sets one of the
13465 global variables imm_reloc or offset_reloc to the type of relocation
13466 to do if one of the operands is an address expression. It also sets
13467 forced_insn_length to the resulting instruction size in bytes if the
13468 user explicitly requested a small or extended instruction. */
13471 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13475 struct mips_opcode
*insn
;
13477 unsigned int regno
;
13478 unsigned int lastregno
= 0;
13484 forced_insn_length
= 0;
13486 for (s
= str
; ISLOWER (*s
); ++s
)
13498 if (s
[1] == 't' && s
[2] == ' ')
13501 forced_insn_length
= 2;
13505 else if (s
[1] == 'e' && s
[2] == ' ')
13508 forced_insn_length
= 4;
13512 /* Fall through. */
13514 insn_error
= _("unknown opcode");
13518 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13519 forced_insn_length
= 2;
13521 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13523 insn_error
= _("unrecognized opcode");
13532 gas_assert (strcmp (insn
->name
, str
) == 0);
13534 ok
= is_opcode_valid_16 (insn
);
13537 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13538 && strcmp (insn
->name
, insn
[1].name
) == 0)
13547 static char buf
[100];
13549 _("Opcode not supported on this processor: %s (%s)"),
13550 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13551 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13558 create_insn (ip
, insn
);
13559 imm_expr
.X_op
= O_absent
;
13560 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13561 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13562 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13563 imm2_expr
.X_op
= O_absent
;
13564 offset_expr
.X_op
= O_absent
;
13565 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13566 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13567 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13568 for (args
= insn
->args
; 1; ++args
)
13575 /* In this switch statement we call break if we did not find
13576 a match, continue if we did find a match, or return if we
13587 /* Stuff the immediate value in now, if we can. */
13588 if (imm_expr
.X_op
== O_constant
13589 && *imm_reloc
> BFD_RELOC_UNUSED
13590 && insn
->pinfo
!= INSN_MACRO
13591 && calculate_reloc (*offset_reloc
,
13592 imm_expr
.X_add_number
, &value
))
13594 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13595 *offset_reloc
, value
, forced_insn_length
,
13597 imm_expr
.X_op
= O_absent
;
13598 *imm_reloc
= BFD_RELOC_UNUSED
;
13599 *offset_reloc
= BFD_RELOC_UNUSED
;
13613 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13616 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13632 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13634 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13638 /* Fall through. */
13649 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13651 if (c
== 'v' || c
== 'w')
13654 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13656 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13667 if (c
== 'v' || c
== 'w')
13669 regno
= mips16_to_32_reg_map
[lastregno
];
13683 regno
= mips32_to_16_reg_map
[regno
];
13688 regno
= ILLEGAL_REG
;
13693 regno
= ILLEGAL_REG
;
13698 regno
= ILLEGAL_REG
;
13703 if (regno
== AT
&& mips_opts
.at
)
13705 if (mips_opts
.at
== ATREG
)
13706 as_warn (_("used $at without \".set noat\""));
13708 as_warn (_("used $%u with \".set at=$%u\""),
13709 regno
, mips_opts
.at
);
13717 if (regno
== ILLEGAL_REG
)
13724 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13728 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13731 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13734 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13740 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13743 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13744 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13754 if (strncmp (s
, "$pc", 3) == 0)
13771 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13774 if (imm_expr
.X_op
!= O_constant
)
13776 forced_insn_length
= 4;
13777 ip
->insn_opcode
|= MIPS16_EXTEND
;
13781 /* We need to relax this instruction. */
13782 *offset_reloc
= *imm_reloc
;
13783 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13788 *imm_reloc
= BFD_RELOC_UNUSED
;
13789 /* Fall through. */
13796 my_getExpression (&imm_expr
, s
);
13797 if (imm_expr
.X_op
== O_register
)
13799 /* What we thought was an expression turned out to
13802 if (s
[0] == '(' && args
[1] == '(')
13804 /* It looks like the expression was omitted
13805 before a register indirection, which means
13806 that the expression is implicitly zero. We
13807 still set up imm_expr, so that we handle
13808 explicit extensions correctly. */
13809 imm_expr
.X_op
= O_constant
;
13810 imm_expr
.X_add_number
= 0;
13811 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13818 /* We need to relax this instruction. */
13819 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13828 /* We use offset_reloc rather than imm_reloc for the PC
13829 relative operands. This lets macros with both
13830 immediate and address operands work correctly. */
13831 my_getExpression (&offset_expr
, s
);
13833 if (offset_expr
.X_op
== O_register
)
13836 /* We need to relax this instruction. */
13837 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13841 case '6': /* break code */
13842 my_getExpression (&imm_expr
, s
);
13843 check_absolute_expr (ip
, &imm_expr
);
13844 if ((unsigned long) imm_expr
.X_add_number
> 63)
13845 as_warn (_("Invalid value for `%s' (%lu)"),
13847 (unsigned long) imm_expr
.X_add_number
);
13848 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13849 imm_expr
.X_op
= O_absent
;
13853 case 'a': /* 26 bit address */
13854 my_getExpression (&offset_expr
, s
);
13856 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13857 ip
->insn_opcode
<<= 16;
13860 case 'l': /* register list for entry macro */
13861 case 'L': /* register list for exit macro */
13871 unsigned int freg
, reg1
, reg2
;
13873 while (*s
== ' ' || *s
== ',')
13875 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13877 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13881 as_bad (_("can't parse register list"));
13891 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13892 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13894 as_bad (_("invalid register list"));
13898 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13900 mask
&= ~ (7 << 3);
13903 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13905 mask
&= ~ (7 << 3);
13908 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13909 mask
|= (reg2
- 3) << 3;
13910 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13911 mask
|= (reg2
- 15) << 1;
13912 else if (reg1
== RA
&& reg2
== RA
)
13916 as_bad (_("invalid register list"));
13920 /* The mask is filled in in the opcode table for the
13921 benefit of the disassembler. We remove it before
13922 applying the actual mask. */
13923 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13924 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13928 case 'm': /* Register list for save insn. */
13929 case 'M': /* Register list for restore insn. */
13931 int opcode
= ip
->insn_opcode
;
13932 int framesz
= 0, seen_framesz
= 0;
13933 int nargs
= 0, statics
= 0, sregs
= 0;
13937 unsigned int reg1
, reg2
;
13939 SKIP_SPACE_TABS (s
);
13942 SKIP_SPACE_TABS (s
);
13944 my_getExpression (&imm_expr
, s
);
13945 if (imm_expr
.X_op
== O_constant
)
13947 /* Handle the frame size. */
13950 as_bad (_("more than one frame size in list"));
13954 framesz
= imm_expr
.X_add_number
;
13955 imm_expr
.X_op
= O_absent
;
13960 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13962 as_bad (_("can't parse register list"));
13974 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13977 as_bad (_("can't parse register list"));
13982 while (reg1
<= reg2
)
13984 if (reg1
>= 4 && reg1
<= 7)
13988 nargs
|= 1 << (reg1
- 4);
13990 /* statics $a0-$a3 */
13991 statics
|= 1 << (reg1
- 4);
13993 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13996 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13998 else if (reg1
== 31)
14000 /* Add $ra to insn. */
14005 as_bad (_("unexpected register in list"));
14013 /* Encode args/statics combination. */
14014 if (nargs
& statics
)
14015 as_bad (_("arg/static registers overlap"));
14016 else if (nargs
== 0xf)
14017 /* All $a0-$a3 are args. */
14018 opcode
|= MIPS16_ALL_ARGS
<< 16;
14019 else if (statics
== 0xf)
14020 /* All $a0-$a3 are statics. */
14021 opcode
|= MIPS16_ALL_STATICS
<< 16;
14024 int narg
= 0, nstat
= 0;
14026 /* Count arg registers. */
14027 while (nargs
& 0x1)
14033 as_bad (_("invalid arg register list"));
14035 /* Count static registers. */
14036 while (statics
& 0x8)
14038 statics
= (statics
<< 1) & 0xf;
14042 as_bad (_("invalid static register list"));
14044 /* Encode args/statics. */
14045 opcode
|= ((narg
<< 2) | nstat
) << 16;
14048 /* Encode $s0/$s1. */
14049 if (sregs
& (1 << 0)) /* $s0 */
14051 if (sregs
& (1 << 1)) /* $s1 */
14057 /* Count regs $s2-$s8. */
14065 as_bad (_("invalid static register list"));
14066 /* Encode $s2-$s8. */
14067 opcode
|= nsreg
<< 24;
14070 /* Encode frame size. */
14072 as_bad (_("missing frame size"));
14073 else if ((framesz
& 7) != 0 || framesz
< 0
14074 || framesz
> 0xff * 8)
14075 as_bad (_("invalid frame size"));
14076 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14079 opcode
|= (((framesz
& 0xf0) << 16)
14080 | (framesz
& 0x0f));
14083 /* Finally build the instruction. */
14084 if ((opcode
>> 16) != 0 || framesz
== 0)
14085 opcode
|= MIPS16_EXTEND
;
14086 ip
->insn_opcode
= opcode
;
14090 case 'e': /* extend code */
14091 my_getExpression (&imm_expr
, s
);
14092 check_absolute_expr (ip
, &imm_expr
);
14093 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14095 as_warn (_("Invalid value for `%s' (%lu)"),
14097 (unsigned long) imm_expr
.X_add_number
);
14098 imm_expr
.X_add_number
&= 0x7ff;
14100 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14101 imm_expr
.X_op
= O_absent
;
14111 /* Args don't match. */
14112 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14113 strcmp (insn
->name
, insn
[1].name
) == 0)
14120 insn_error
= _("illegal operands");
14126 /* This structure holds information we know about a mips16 immediate
14129 struct mips16_immed_operand
14131 /* The type code used in the argument string in the opcode table. */
14133 /* The number of bits in the short form of the opcode. */
14135 /* The number of bits in the extended form of the opcode. */
14137 /* The amount by which the short form is shifted when it is used;
14138 for example, the sw instruction has a shift count of 2. */
14140 /* The amount by which the short form is shifted when it is stored
14141 into the instruction code. */
14143 /* Non-zero if the short form is unsigned. */
14145 /* Non-zero if the extended form is unsigned. */
14147 /* Non-zero if the value is PC relative. */
14151 /* The mips16 immediate operand types. */
14153 static const struct mips16_immed_operand mips16_immed_operands
[] =
14155 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14156 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14157 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14158 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14159 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14160 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14161 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14162 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14163 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14164 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14165 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14166 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14167 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14168 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14169 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14170 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14171 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14172 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14173 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14174 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14175 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14178 #define MIPS16_NUM_IMMED \
14179 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14181 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14182 NBITS is the number of significant bits in VAL. */
14184 static unsigned long
14185 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14190 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14193 else if (nbits
== 15)
14195 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14200 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14203 return (extval
<< 16) | val
;
14206 /* Install immediate value VAL into MIPS16 instruction *INSN,
14207 extending it if necessary. The instruction in *INSN may
14208 already be extended.
14210 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14211 if none. In the former case, VAL is a 16-bit number with no
14212 defined signedness.
14214 TYPE is the type of the immediate field. USER_INSN_LENGTH
14215 is the length that the user requested, or 0 if none. */
14218 mips16_immed (char *file
, unsigned int line
, int type
,
14219 bfd_reloc_code_real_type reloc
, offsetT val
,
14220 unsigned int user_insn_length
, unsigned long *insn
)
14222 const struct mips16_immed_operand
*op
;
14223 int mintiny
, maxtiny
;
14225 op
= mips16_immed_operands
;
14226 while (op
->type
!= type
)
14229 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14234 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14237 maxtiny
= 1 << op
->nbits
;
14242 maxtiny
= (1 << op
->nbits
) - 1;
14244 if (reloc
!= BFD_RELOC_UNUSED
)
14249 mintiny
= - (1 << (op
->nbits
- 1));
14250 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14251 if (reloc
!= BFD_RELOC_UNUSED
)
14252 val
= SEXT_16BIT (val
);
14255 /* Branch offsets have an implicit 0 in the lowest bit. */
14256 if (type
== 'p' || type
== 'q')
14259 if ((val
& ((1 << op
->shift
) - 1)) != 0
14260 || val
< (mintiny
<< op
->shift
)
14261 || val
> (maxtiny
<< op
->shift
))
14263 /* We need an extended instruction. */
14264 if (user_insn_length
== 2)
14265 as_bad_where (file
, line
, _("invalid unextended operand value"));
14267 *insn
|= MIPS16_EXTEND
;
14269 else if (user_insn_length
== 4)
14271 /* The operand doesn't force an unextended instruction to be extended.
14272 Warn if the user wanted an extended instruction anyway. */
14273 *insn
|= MIPS16_EXTEND
;
14274 as_warn_where (file
, line
,
14275 _("extended operand requested but not required"));
14278 if (mips16_opcode_length (*insn
) == 2)
14282 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14283 insnval
<<= op
->op_shift
;
14288 long minext
, maxext
;
14290 if (reloc
== BFD_RELOC_UNUSED
)
14295 maxext
= (1 << op
->extbits
) - 1;
14299 minext
= - (1 << (op
->extbits
- 1));
14300 maxext
= (1 << (op
->extbits
- 1)) - 1;
14302 if (val
< minext
|| val
> maxext
)
14303 as_bad_where (file
, line
,
14304 _("operand value out of range for instruction"));
14307 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14311 struct percent_op_match
14314 bfd_reloc_code_real_type reloc
;
14317 static const struct percent_op_match mips_percent_op
[] =
14319 {"%lo", BFD_RELOC_LO16
},
14321 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14322 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14323 {"%call16", BFD_RELOC_MIPS_CALL16
},
14324 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14325 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14326 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14327 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14328 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14329 {"%got", BFD_RELOC_MIPS_GOT16
},
14330 {"%gp_rel", BFD_RELOC_GPREL16
},
14331 {"%half", BFD_RELOC_16
},
14332 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14333 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14334 {"%neg", BFD_RELOC_MIPS_SUB
},
14335 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14336 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14337 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14338 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14339 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14340 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14341 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14343 {"%hi", BFD_RELOC_HI16_S
}
14346 static const struct percent_op_match mips16_percent_op
[] =
14348 {"%lo", BFD_RELOC_MIPS16_LO16
},
14349 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14350 {"%got", BFD_RELOC_MIPS16_GOT16
},
14351 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14352 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14353 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14354 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14355 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14356 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14357 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14358 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14359 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14363 /* Return true if *STR points to a relocation operator. When returning true,
14364 move *STR over the operator and store its relocation code in *RELOC.
14365 Leave both *STR and *RELOC alone when returning false. */
14368 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14370 const struct percent_op_match
*percent_op
;
14373 if (mips_opts
.mips16
)
14375 percent_op
= mips16_percent_op
;
14376 limit
= ARRAY_SIZE (mips16_percent_op
);
14380 percent_op
= mips_percent_op
;
14381 limit
= ARRAY_SIZE (mips_percent_op
);
14384 for (i
= 0; i
< limit
; i
++)
14385 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14387 int len
= strlen (percent_op
[i
].str
);
14389 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14392 *str
+= strlen (percent_op
[i
].str
);
14393 *reloc
= percent_op
[i
].reloc
;
14395 /* Check whether the output BFD supports this relocation.
14396 If not, issue an error and fall back on something safe. */
14397 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14399 as_bad (_("relocation %s isn't supported by the current ABI"),
14400 percent_op
[i
].str
);
14401 *reloc
= BFD_RELOC_UNUSED
;
14409 /* Parse string STR as a 16-bit relocatable operand. Store the
14410 expression in *EP and the relocations in the array starting
14411 at RELOC. Return the number of relocation operators used.
14413 On exit, EXPR_END points to the first character after the expression. */
14416 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14419 bfd_reloc_code_real_type reversed_reloc
[3];
14420 size_t reloc_index
, i
;
14421 int crux_depth
, str_depth
;
14424 /* Search for the start of the main expression, recoding relocations
14425 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14426 of the main expression and with CRUX_DEPTH containing the number
14427 of open brackets at that point. */
14434 crux_depth
= str_depth
;
14436 /* Skip over whitespace and brackets, keeping count of the number
14438 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14443 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14444 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14446 my_getExpression (ep
, crux
);
14449 /* Match every open bracket. */
14450 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14454 if (crux_depth
> 0)
14455 as_bad (_("unclosed '('"));
14459 if (reloc_index
!= 0)
14461 prev_reloc_op_frag
= frag_now
;
14462 for (i
= 0; i
< reloc_index
; i
++)
14463 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14466 return reloc_index
;
14470 my_getExpression (expressionS
*ep
, char *str
)
14474 save_in
= input_line_pointer
;
14475 input_line_pointer
= str
;
14477 expr_end
= input_line_pointer
;
14478 input_line_pointer
= save_in
;
14482 md_atof (int type
, char *litP
, int *sizeP
)
14484 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14488 md_number_to_chars (char *buf
, valueT val
, int n
)
14490 if (target_big_endian
)
14491 number_to_chars_bigendian (buf
, val
, n
);
14493 number_to_chars_littleendian (buf
, val
, n
);
14497 static int support_64bit_objects(void)
14499 const char **list
, **l
;
14502 list
= bfd_target_list ();
14503 for (l
= list
; *l
!= NULL
; l
++)
14504 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14505 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14507 yes
= (*l
!= NULL
);
14511 #endif /* OBJ_ELF */
14513 const char *md_shortopts
= "O::g::G:";
14517 OPTION_MARCH
= OPTION_MD_BASE
,
14541 OPTION_NO_SMARTMIPS
,
14545 OPTION_NO_MICROMIPS
,
14548 OPTION_COMPAT_ARCH_BASE
,
14557 OPTION_M7000_HILO_FIX
,
14558 OPTION_MNO_7000_HILO_FIX
,
14561 OPTION_FIX_LOONGSON2F_JUMP
,
14562 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14563 OPTION_FIX_LOONGSON2F_NOP
,
14564 OPTION_NO_FIX_LOONGSON2F_NOP
,
14566 OPTION_NO_FIX_VR4120
,
14568 OPTION_NO_FIX_VR4130
,
14569 OPTION_FIX_CN63XXP1
,
14570 OPTION_NO_FIX_CN63XXP1
,
14577 OPTION_CONSTRUCT_FLOATS
,
14578 OPTION_NO_CONSTRUCT_FLOATS
,
14581 OPTION_RELAX_BRANCH
,
14582 OPTION_NO_RELAX_BRANCH
,
14589 OPTION_SINGLE_FLOAT
,
14590 OPTION_DOUBLE_FLOAT
,
14593 OPTION_CALL_SHARED
,
14594 OPTION_CALL_NONPIC
,
14604 OPTION_MVXWORKS_PIC
,
14605 #endif /* OBJ_ELF */
14609 struct option md_longopts
[] =
14611 /* Options which specify architecture. */
14612 {"march", required_argument
, NULL
, OPTION_MARCH
},
14613 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14614 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14615 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14616 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14617 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14618 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14619 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14620 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14621 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14622 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14623 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14625 /* Options which specify Application Specific Extensions (ASEs). */
14626 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14627 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14628 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14629 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14630 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14631 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14632 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14633 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14634 {"mmt", no_argument
, NULL
, OPTION_MT
},
14635 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14636 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14637 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14638 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14639 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14640 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14641 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14642 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14643 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14644 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
14645 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
14647 /* Old-style architecture options. Don't add more of these. */
14648 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14649 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14650 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14651 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14652 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14653 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14654 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14655 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14657 /* Options which enable bug fixes. */
14658 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14659 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14660 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14671 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14672 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14674 /* Miscellaneous options. */
14675 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14676 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14677 {"break", no_argument
, NULL
, OPTION_BREAK
},
14678 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14679 {"EB", no_argument
, NULL
, OPTION_EB
},
14680 {"EL", no_argument
, NULL
, OPTION_EL
},
14681 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14682 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14683 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14684 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14685 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14686 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14687 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14688 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14689 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14690 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14691 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14692 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14693 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14694 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14695 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14696 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14698 /* Strictly speaking this next option is ELF specific,
14699 but we allow it for other ports as well in order to
14700 make testing easier. */
14701 {"32", no_argument
, NULL
, OPTION_32
},
14703 /* ELF-specific options. */
14705 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14706 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14707 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14708 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14709 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14710 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14711 {"n32", no_argument
, NULL
, OPTION_N32
},
14712 {"64", no_argument
, NULL
, OPTION_64
},
14713 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14714 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14715 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14716 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14717 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14718 #endif /* OBJ_ELF */
14720 {NULL
, no_argument
, NULL
, 0}
14722 size_t md_longopts_size
= sizeof (md_longopts
);
14724 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14725 NEW_VALUE. Warn if another value was already specified. Note:
14726 we have to defer parsing the -march and -mtune arguments in order
14727 to handle 'from-abi' correctly, since the ABI might be specified
14728 in a later argument. */
14731 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14733 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14734 as_warn (_("A different %s was already specified, is now %s"),
14735 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14738 *string_ptr
= new_value
;
14742 md_parse_option (int c
, char *arg
)
14746 case OPTION_CONSTRUCT_FLOATS
:
14747 mips_disable_float_construction
= 0;
14750 case OPTION_NO_CONSTRUCT_FLOATS
:
14751 mips_disable_float_construction
= 1;
14763 target_big_endian
= 1;
14767 target_big_endian
= 0;
14773 else if (arg
[0] == '0')
14775 else if (arg
[0] == '1')
14785 mips_debug
= atoi (arg
);
14789 file_mips_isa
= ISA_MIPS1
;
14793 file_mips_isa
= ISA_MIPS2
;
14797 file_mips_isa
= ISA_MIPS3
;
14801 file_mips_isa
= ISA_MIPS4
;
14805 file_mips_isa
= ISA_MIPS5
;
14808 case OPTION_MIPS32
:
14809 file_mips_isa
= ISA_MIPS32
;
14812 case OPTION_MIPS32R2
:
14813 file_mips_isa
= ISA_MIPS32R2
;
14816 case OPTION_MIPS64R2
:
14817 file_mips_isa
= ISA_MIPS64R2
;
14820 case OPTION_MIPS64
:
14821 file_mips_isa
= ISA_MIPS64
;
14825 mips_set_option_string (&mips_tune_string
, arg
);
14829 mips_set_option_string (&mips_arch_string
, arg
);
14833 mips_set_option_string (&mips_arch_string
, "4650");
14834 mips_set_option_string (&mips_tune_string
, "4650");
14837 case OPTION_NO_M4650
:
14841 mips_set_option_string (&mips_arch_string
, "4010");
14842 mips_set_option_string (&mips_tune_string
, "4010");
14845 case OPTION_NO_M4010
:
14849 mips_set_option_string (&mips_arch_string
, "4100");
14850 mips_set_option_string (&mips_tune_string
, "4100");
14853 case OPTION_NO_M4100
:
14857 mips_set_option_string (&mips_arch_string
, "3900");
14858 mips_set_option_string (&mips_tune_string
, "3900");
14861 case OPTION_NO_M3900
:
14865 mips_opts
.ase_mdmx
= 1;
14868 case OPTION_NO_MDMX
:
14869 mips_opts
.ase_mdmx
= 0;
14873 mips_opts
.ase_dsp
= 1;
14874 mips_opts
.ase_dspr2
= 0;
14877 case OPTION_NO_DSP
:
14878 mips_opts
.ase_dsp
= 0;
14879 mips_opts
.ase_dspr2
= 0;
14883 mips_opts
.ase_dspr2
= 1;
14884 mips_opts
.ase_dsp
= 1;
14887 case OPTION_NO_DSPR2
:
14888 mips_opts
.ase_dspr2
= 0;
14889 mips_opts
.ase_dsp
= 0;
14893 mips_opts
.ase_mt
= 1;
14897 mips_opts
.ase_mt
= 0;
14901 mips_opts
.ase_mcu
= 1;
14904 case OPTION_NO_MCU
:
14905 mips_opts
.ase_mcu
= 0;
14908 case OPTION_MICROMIPS
:
14909 if (mips_opts
.mips16
== 1)
14911 as_bad (_("-mmicromips cannot be used with -mips16"));
14914 mips_opts
.micromips
= 1;
14915 mips_no_prev_insn ();
14918 case OPTION_NO_MICROMIPS
:
14919 mips_opts
.micromips
= 0;
14920 mips_no_prev_insn ();
14924 mips_opts
.ase_virt
= 1;
14927 case OPTION_NO_VIRT
:
14928 mips_opts
.ase_virt
= 0;
14931 case OPTION_MIPS16
:
14932 if (mips_opts
.micromips
== 1)
14934 as_bad (_("-mips16 cannot be used with -micromips"));
14937 mips_opts
.mips16
= 1;
14938 mips_no_prev_insn ();
14941 case OPTION_NO_MIPS16
:
14942 mips_opts
.mips16
= 0;
14943 mips_no_prev_insn ();
14946 case OPTION_MIPS3D
:
14947 mips_opts
.ase_mips3d
= 1;
14950 case OPTION_NO_MIPS3D
:
14951 mips_opts
.ase_mips3d
= 0;
14954 case OPTION_SMARTMIPS
:
14955 mips_opts
.ase_smartmips
= 1;
14958 case OPTION_NO_SMARTMIPS
:
14959 mips_opts
.ase_smartmips
= 0;
14962 case OPTION_FIX_24K
:
14966 case OPTION_NO_FIX_24K
:
14970 case OPTION_FIX_LOONGSON2F_JUMP
:
14971 mips_fix_loongson2f_jump
= TRUE
;
14974 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14975 mips_fix_loongson2f_jump
= FALSE
;
14978 case OPTION_FIX_LOONGSON2F_NOP
:
14979 mips_fix_loongson2f_nop
= TRUE
;
14982 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14983 mips_fix_loongson2f_nop
= FALSE
;
14986 case OPTION_FIX_VR4120
:
14987 mips_fix_vr4120
= 1;
14990 case OPTION_NO_FIX_VR4120
:
14991 mips_fix_vr4120
= 0;
14994 case OPTION_FIX_VR4130
:
14995 mips_fix_vr4130
= 1;
14998 case OPTION_NO_FIX_VR4130
:
14999 mips_fix_vr4130
= 0;
15002 case OPTION_FIX_CN63XXP1
:
15003 mips_fix_cn63xxp1
= TRUE
;
15006 case OPTION_NO_FIX_CN63XXP1
:
15007 mips_fix_cn63xxp1
= FALSE
;
15010 case OPTION_RELAX_BRANCH
:
15011 mips_relax_branch
= 1;
15014 case OPTION_NO_RELAX_BRANCH
:
15015 mips_relax_branch
= 0;
15018 case OPTION_MSHARED
:
15019 mips_in_shared
= TRUE
;
15022 case OPTION_MNO_SHARED
:
15023 mips_in_shared
= FALSE
;
15026 case OPTION_MSYM32
:
15027 mips_opts
.sym32
= TRUE
;
15030 case OPTION_MNO_SYM32
:
15031 mips_opts
.sym32
= FALSE
;
15035 /* When generating ELF code, we permit -KPIC and -call_shared to
15036 select SVR4_PIC, and -non_shared to select no PIC. This is
15037 intended to be compatible with Irix 5. */
15038 case OPTION_CALL_SHARED
:
15041 as_bad (_("-call_shared is supported only for ELF format"));
15044 mips_pic
= SVR4_PIC
;
15045 mips_abicalls
= TRUE
;
15048 case OPTION_CALL_NONPIC
:
15051 as_bad (_("-call_nonpic is supported only for ELF format"));
15055 mips_abicalls
= TRUE
;
15058 case OPTION_NON_SHARED
:
15061 as_bad (_("-non_shared is supported only for ELF format"));
15065 mips_abicalls
= FALSE
;
15068 /* The -xgot option tells the assembler to use 32 bit offsets
15069 when accessing the got in SVR4_PIC mode. It is for Irix
15074 #endif /* OBJ_ELF */
15077 g_switch_value
= atoi (arg
);
15081 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15085 mips_abi
= O32_ABI
;
15086 /* We silently ignore -32 for non-ELF targets. This greatly
15087 simplifies the construction of the MIPS GAS test cases. */
15094 as_bad (_("-n32 is supported for ELF format only"));
15097 mips_abi
= N32_ABI
;
15103 as_bad (_("-64 is supported for ELF format only"));
15106 mips_abi
= N64_ABI
;
15107 if (!support_64bit_objects())
15108 as_fatal (_("No compiled in support for 64 bit object file format"));
15110 #endif /* OBJ_ELF */
15113 file_mips_gp32
= 1;
15117 file_mips_gp32
= 0;
15121 file_mips_fp32
= 1;
15125 file_mips_fp32
= 0;
15128 case OPTION_SINGLE_FLOAT
:
15129 file_mips_single_float
= 1;
15132 case OPTION_DOUBLE_FLOAT
:
15133 file_mips_single_float
= 0;
15136 case OPTION_SOFT_FLOAT
:
15137 file_mips_soft_float
= 1;
15140 case OPTION_HARD_FLOAT
:
15141 file_mips_soft_float
= 0;
15148 as_bad (_("-mabi is supported for ELF format only"));
15151 if (strcmp (arg
, "32") == 0)
15152 mips_abi
= O32_ABI
;
15153 else if (strcmp (arg
, "o64") == 0)
15154 mips_abi
= O64_ABI
;
15155 else if (strcmp (arg
, "n32") == 0)
15156 mips_abi
= N32_ABI
;
15157 else if (strcmp (arg
, "64") == 0)
15159 mips_abi
= N64_ABI
;
15160 if (! support_64bit_objects())
15161 as_fatal (_("No compiled in support for 64 bit object file "
15164 else if (strcmp (arg
, "eabi") == 0)
15165 mips_abi
= EABI_ABI
;
15168 as_fatal (_("invalid abi -mabi=%s"), arg
);
15172 #endif /* OBJ_ELF */
15174 case OPTION_M7000_HILO_FIX
:
15175 mips_7000_hilo_fix
= TRUE
;
15178 case OPTION_MNO_7000_HILO_FIX
:
15179 mips_7000_hilo_fix
= FALSE
;
15183 case OPTION_MDEBUG
:
15184 mips_flag_mdebug
= TRUE
;
15187 case OPTION_NO_MDEBUG
:
15188 mips_flag_mdebug
= FALSE
;
15192 mips_flag_pdr
= TRUE
;
15195 case OPTION_NO_PDR
:
15196 mips_flag_pdr
= FALSE
;
15199 case OPTION_MVXWORKS_PIC
:
15200 mips_pic
= VXWORKS_PIC
;
15202 #endif /* OBJ_ELF */
15208 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15213 /* Set up globals to generate code for the ISA or processor
15214 described by INFO. */
15217 mips_set_architecture (const struct mips_cpu_info
*info
)
15221 file_mips_arch
= info
->cpu
;
15222 mips_opts
.arch
= info
->cpu
;
15223 mips_opts
.isa
= info
->isa
;
15228 /* Likewise for tuning. */
15231 mips_set_tune (const struct mips_cpu_info
*info
)
15234 mips_tune
= info
->cpu
;
15239 mips_after_parse_args (void)
15241 const struct mips_cpu_info
*arch_info
= 0;
15242 const struct mips_cpu_info
*tune_info
= 0;
15244 /* GP relative stuff not working for PE */
15245 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15247 if (g_switch_seen
&& g_switch_value
!= 0)
15248 as_bad (_("-G not supported in this configuration."));
15249 g_switch_value
= 0;
15252 if (mips_abi
== NO_ABI
)
15253 mips_abi
= MIPS_DEFAULT_ABI
;
15255 /* The following code determines the architecture and register size.
15256 Similar code was added to GCC 3.3 (see override_options() in
15257 config/mips/mips.c). The GAS and GCC code should be kept in sync
15258 as much as possible. */
15260 if (mips_arch_string
!= 0)
15261 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15263 if (file_mips_isa
!= ISA_UNKNOWN
)
15265 /* Handle -mipsN. At this point, file_mips_isa contains the
15266 ISA level specified by -mipsN, while arch_info->isa contains
15267 the -march selection (if any). */
15268 if (arch_info
!= 0)
15270 /* -march takes precedence over -mipsN, since it is more descriptive.
15271 There's no harm in specifying both as long as the ISA levels
15273 if (file_mips_isa
!= arch_info
->isa
)
15274 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15275 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15276 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15279 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15282 if (arch_info
== 0)
15284 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15285 gas_assert (arch_info
);
15288 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15289 as_bad (_("-march=%s is not compatible with the selected ABI"),
15292 mips_set_architecture (arch_info
);
15294 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15295 if (mips_tune_string
!= 0)
15296 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15298 if (tune_info
== 0)
15299 mips_set_tune (arch_info
);
15301 mips_set_tune (tune_info
);
15303 if (file_mips_gp32
>= 0)
15305 /* The user specified the size of the integer registers. Make sure
15306 it agrees with the ABI and ISA. */
15307 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15308 as_bad (_("-mgp64 used with a 32-bit processor"));
15309 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15310 as_bad (_("-mgp32 used with a 64-bit ABI"));
15311 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15312 as_bad (_("-mgp64 used with a 32-bit ABI"));
15316 /* Infer the integer register size from the ABI and processor.
15317 Restrict ourselves to 32-bit registers if that's all the
15318 processor has, or if the ABI cannot handle 64-bit registers. */
15319 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15320 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15323 switch (file_mips_fp32
)
15327 /* No user specified float register size.
15328 ??? GAS treats single-float processors as though they had 64-bit
15329 float registers (although it complains when double-precision
15330 instructions are used). As things stand, saying they have 32-bit
15331 registers would lead to spurious "register must be even" messages.
15332 So here we assume float registers are never smaller than the
15334 if (file_mips_gp32
== 0)
15335 /* 64-bit integer registers implies 64-bit float registers. */
15336 file_mips_fp32
= 0;
15337 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15338 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15339 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15340 file_mips_fp32
= 0;
15342 /* 32-bit float registers. */
15343 file_mips_fp32
= 1;
15346 /* The user specified the size of the float registers. Check if it
15347 agrees with the ABI and ISA. */
15349 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15350 as_bad (_("-mfp64 used with a 32-bit fpu"));
15351 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15352 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15353 as_warn (_("-mfp64 used with a 32-bit ABI"));
15356 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15357 as_warn (_("-mfp32 used with a 64-bit ABI"));
15361 /* End of GCC-shared inference code. */
15363 /* This flag is set when we have a 64-bit capable CPU but use only
15364 32-bit wide registers. Note that EABI does not use it. */
15365 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15366 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15367 || mips_abi
== O32_ABI
))
15368 mips_32bitmode
= 1;
15370 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15371 as_bad (_("trap exception not supported at ISA 1"));
15373 /* If the selected architecture includes support for ASEs, enable
15374 generation of code for them. */
15375 if (mips_opts
.mips16
== -1)
15376 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15377 if (mips_opts
.micromips
== -1)
15378 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15379 if (mips_opts
.ase_mips3d
== -1)
15380 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15381 && file_mips_fp32
== 0) ? 1 : 0;
15382 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15383 as_bad (_("-mfp32 used with -mips3d"));
15385 if (mips_opts
.ase_mdmx
== -1)
15386 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15387 && file_mips_fp32
== 0) ? 1 : 0;
15388 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15389 as_bad (_("-mfp32 used with -mdmx"));
15391 if (mips_opts
.ase_smartmips
== -1)
15392 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15393 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15394 as_warn (_("%s ISA does not support SmartMIPS"),
15395 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15397 if (mips_opts
.ase_dsp
== -1)
15398 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15399 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15400 as_warn (_("%s ISA does not support DSP ASE"),
15401 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15403 if (mips_opts
.ase_dspr2
== -1)
15405 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15406 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15408 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15409 as_warn (_("%s ISA does not support DSP R2 ASE"),
15410 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15412 if (mips_opts
.ase_mt
== -1)
15413 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15414 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15415 as_warn (_("%s ISA does not support MT ASE"),
15416 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15418 if (mips_opts
.ase_mcu
== -1)
15419 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15420 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15421 as_warn (_("%s ISA does not support MCU ASE"),
15422 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15424 if (mips_opts
.ase_virt
== -1)
15425 mips_opts
.ase_virt
= (arch_info
->flags
& MIPS_CPU_ASE_VIRT
) ? 1 : 0;
15426 if (mips_opts
.ase_virt
&& !ISA_SUPPORTS_VIRT_ASE
)
15427 as_warn (_("%s ISA does not support Virtualization ASE"),
15428 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15430 file_mips_isa
= mips_opts
.isa
;
15431 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15432 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15433 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15434 file_ase_dsp
= mips_opts
.ase_dsp
;
15435 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15436 file_ase_mt
= mips_opts
.ase_mt
;
15437 file_ase_virt
= mips_opts
.ase_virt
;
15438 mips_opts
.gp32
= file_mips_gp32
;
15439 mips_opts
.fp32
= file_mips_fp32
;
15440 mips_opts
.soft_float
= file_mips_soft_float
;
15441 mips_opts
.single_float
= file_mips_single_float
;
15443 if (mips_flag_mdebug
< 0)
15445 #ifdef OBJ_MAYBE_ECOFF
15446 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15447 mips_flag_mdebug
= 1;
15449 #endif /* OBJ_MAYBE_ECOFF */
15450 mips_flag_mdebug
= 0;
15455 mips_init_after_args (void)
15457 /* initialize opcodes */
15458 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15459 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15463 md_pcrel_from (fixS
*fixP
)
15465 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15466 switch (fixP
->fx_r_type
)
15468 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15469 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15470 /* Return the address of the delay slot. */
15473 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15474 case BFD_RELOC_MICROMIPS_JMP
:
15475 case BFD_RELOC_16_PCREL_S2
:
15476 case BFD_RELOC_MIPS_JMP
:
15477 /* Return the address of the delay slot. */
15480 case BFD_RELOC_32_PCREL
:
15484 /* We have no relocation type for PC relative MIPS16 instructions. */
15485 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15487 _("PC relative MIPS16 instruction references a different section"));
15492 /* This is called before the symbol table is processed. In order to
15493 work with gcc when using mips-tfile, we must keep all local labels.
15494 However, in other cases, we want to discard them. If we were
15495 called with -g, but we didn't see any debugging information, it may
15496 mean that gcc is smuggling debugging information through to
15497 mips-tfile, in which case we must generate all local labels. */
15500 mips_frob_file_before_adjust (void)
15502 #ifndef NO_ECOFF_DEBUGGING
15503 if (ECOFF_DEBUGGING
15505 && ! ecoff_debugging_seen
)
15506 flag_keep_locals
= 1;
15510 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15511 the corresponding LO16 reloc. This is called before md_apply_fix and
15512 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15513 relocation operators.
15515 For our purposes, a %lo() expression matches a %got() or %hi()
15518 (a) it refers to the same symbol; and
15519 (b) the offset applied in the %lo() expression is no lower than
15520 the offset applied in the %got() or %hi().
15522 (b) allows us to cope with code like:
15525 lh $4,%lo(foo+2)($4)
15527 ...which is legal on RELA targets, and has a well-defined behaviour
15528 if the user knows that adding 2 to "foo" will not induce a carry to
15531 When several %lo()s match a particular %got() or %hi(), we use the
15532 following rules to distinguish them:
15534 (1) %lo()s with smaller offsets are a better match than %lo()s with
15537 (2) %lo()s with no matching %got() or %hi() are better than those
15538 that already have a matching %got() or %hi().
15540 (3) later %lo()s are better than earlier %lo()s.
15542 These rules are applied in order.
15544 (1) means, among other things, that %lo()s with identical offsets are
15545 chosen if they exist.
15547 (2) means that we won't associate several high-part relocations with
15548 the same low-part relocation unless there's no alternative. Having
15549 several high parts for the same low part is a GNU extension; this rule
15550 allows careful users to avoid it.
15552 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15553 with the last high-part relocation being at the front of the list.
15554 It therefore makes sense to choose the last matching low-part
15555 relocation, all other things being equal. It's also easier
15556 to code that way. */
15559 mips_frob_file (void)
15561 struct mips_hi_fixup
*l
;
15562 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15564 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15566 segment_info_type
*seginfo
;
15567 bfd_boolean matched_lo_p
;
15568 fixS
**hi_pos
, **lo_pos
, **pos
;
15570 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15572 /* If a GOT16 relocation turns out to be against a global symbol,
15573 there isn't supposed to be a matching LO. Ignore %gots against
15574 constants; we'll report an error for those later. */
15575 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15576 && !(l
->fixp
->fx_addsy
15577 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15580 /* Check quickly whether the next fixup happens to be a matching %lo. */
15581 if (fixup_has_matching_lo_p (l
->fixp
))
15584 seginfo
= seg_info (l
->seg
);
15586 /* Set HI_POS to the position of this relocation in the chain.
15587 Set LO_POS to the position of the chosen low-part relocation.
15588 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15589 relocation that matches an immediately-preceding high-part
15593 matched_lo_p
= FALSE
;
15594 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15596 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15598 if (*pos
== l
->fixp
)
15601 if ((*pos
)->fx_r_type
== looking_for_rtype
15602 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15603 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15605 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15607 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15610 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15611 && fixup_has_matching_lo_p (*pos
));
15614 /* If we found a match, remove the high-part relocation from its
15615 current position and insert it before the low-part relocation.
15616 Make the offsets match so that fixup_has_matching_lo_p()
15619 We don't warn about unmatched high-part relocations since some
15620 versions of gcc have been known to emit dead "lui ...%hi(...)"
15622 if (lo_pos
!= NULL
)
15624 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15625 if (l
->fixp
->fx_next
!= *lo_pos
)
15627 *hi_pos
= l
->fixp
->fx_next
;
15628 l
->fixp
->fx_next
= *lo_pos
;
15636 mips_force_relocation (fixS
*fixp
)
15638 if (generic_force_reloc (fixp
))
15641 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15642 so that the linker relaxation can update targets. */
15643 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15644 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15645 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15651 /* Read the instruction associated with RELOC from BUF. */
15653 static unsigned int
15654 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15656 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15657 return read_compressed_insn (buf
, 4);
15659 return read_insn (buf
);
15662 /* Write instruction INSN to BUF, given that it has been relocated
15666 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15667 unsigned long insn
)
15669 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15670 write_compressed_insn (buf
, insn
, 4);
15672 write_insn (buf
, insn
);
15675 /* Apply a fixup to the object file. */
15678 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15681 unsigned long insn
;
15682 reloc_howto_type
*howto
;
15684 /* We ignore generic BFD relocations we don't know about. */
15685 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15689 gas_assert (fixP
->fx_size
== 2
15690 || fixP
->fx_size
== 4
15691 || fixP
->fx_r_type
== BFD_RELOC_16
15692 || fixP
->fx_r_type
== BFD_RELOC_64
15693 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15694 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15695 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15696 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15697 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15698 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15700 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15702 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15703 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15704 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15705 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15706 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15708 /* Don't treat parts of a composite relocation as done. There are two
15711 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15712 should nevertheless be emitted if the first part is.
15714 (2) In normal usage, composite relocations are never assembly-time
15715 constants. The easiest way of dealing with the pathological
15716 exceptions is to generate a relocation against STN_UNDEF and
15717 leave everything up to the linker. */
15718 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15721 switch (fixP
->fx_r_type
)
15723 case BFD_RELOC_MIPS_TLS_GD
:
15724 case BFD_RELOC_MIPS_TLS_LDM
:
15725 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15726 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15727 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15728 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15729 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15730 case BFD_RELOC_MIPS_TLS_TPREL32
:
15731 case BFD_RELOC_MIPS_TLS_TPREL64
:
15732 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15733 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15734 case BFD_RELOC_MICROMIPS_TLS_GD
:
15735 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15736 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15737 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15738 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15739 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15740 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15741 case BFD_RELOC_MIPS16_TLS_GD
:
15742 case BFD_RELOC_MIPS16_TLS_LDM
:
15743 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15744 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15745 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15746 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15747 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15748 if (!fixP
->fx_addsy
)
15750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15751 _("TLS relocation against a constant"));
15754 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15757 case BFD_RELOC_MIPS_JMP
:
15758 case BFD_RELOC_MIPS_SHIFT5
:
15759 case BFD_RELOC_MIPS_SHIFT6
:
15760 case BFD_RELOC_MIPS_GOT_DISP
:
15761 case BFD_RELOC_MIPS_GOT_PAGE
:
15762 case BFD_RELOC_MIPS_GOT_OFST
:
15763 case BFD_RELOC_MIPS_SUB
:
15764 case BFD_RELOC_MIPS_INSERT_A
:
15765 case BFD_RELOC_MIPS_INSERT_B
:
15766 case BFD_RELOC_MIPS_DELETE
:
15767 case BFD_RELOC_MIPS_HIGHEST
:
15768 case BFD_RELOC_MIPS_HIGHER
:
15769 case BFD_RELOC_MIPS_SCN_DISP
:
15770 case BFD_RELOC_MIPS_REL16
:
15771 case BFD_RELOC_MIPS_RELGOT
:
15772 case BFD_RELOC_MIPS_JALR
:
15773 case BFD_RELOC_HI16
:
15774 case BFD_RELOC_HI16_S
:
15775 case BFD_RELOC_LO16
:
15776 case BFD_RELOC_GPREL16
:
15777 case BFD_RELOC_MIPS_LITERAL
:
15778 case BFD_RELOC_MIPS_CALL16
:
15779 case BFD_RELOC_MIPS_GOT16
:
15780 case BFD_RELOC_GPREL32
:
15781 case BFD_RELOC_MIPS_GOT_HI16
:
15782 case BFD_RELOC_MIPS_GOT_LO16
:
15783 case BFD_RELOC_MIPS_CALL_HI16
:
15784 case BFD_RELOC_MIPS_CALL_LO16
:
15785 case BFD_RELOC_MIPS16_GPREL
:
15786 case BFD_RELOC_MIPS16_GOT16
:
15787 case BFD_RELOC_MIPS16_CALL16
:
15788 case BFD_RELOC_MIPS16_HI16
:
15789 case BFD_RELOC_MIPS16_HI16_S
:
15790 case BFD_RELOC_MIPS16_LO16
:
15791 case BFD_RELOC_MIPS16_JMP
:
15792 case BFD_RELOC_MICROMIPS_JMP
:
15793 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15794 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15795 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15796 case BFD_RELOC_MICROMIPS_SUB
:
15797 case BFD_RELOC_MICROMIPS_HIGHEST
:
15798 case BFD_RELOC_MICROMIPS_HIGHER
:
15799 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15800 case BFD_RELOC_MICROMIPS_JALR
:
15801 case BFD_RELOC_MICROMIPS_HI16
:
15802 case BFD_RELOC_MICROMIPS_HI16_S
:
15803 case BFD_RELOC_MICROMIPS_LO16
:
15804 case BFD_RELOC_MICROMIPS_GPREL16
:
15805 case BFD_RELOC_MICROMIPS_LITERAL
:
15806 case BFD_RELOC_MICROMIPS_CALL16
:
15807 case BFD_RELOC_MICROMIPS_GOT16
:
15808 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15809 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15810 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15811 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15816 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15818 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15819 if (mips16_reloc_p (fixP
->fx_r_type
))
15820 insn
|= mips16_immed_extend (value
, 16);
15822 insn
|= (value
& 0xffff);
15823 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15827 _("Unsupported constant in relocation"));
15832 /* This is handled like BFD_RELOC_32, but we output a sign
15833 extended value if we are only 32 bits. */
15836 if (8 <= sizeof (valueT
))
15837 md_number_to_chars (buf
, *valP
, 8);
15842 if ((*valP
& 0x80000000) != 0)
15846 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15847 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15852 case BFD_RELOC_RVA
:
15854 case BFD_RELOC_32_PCREL
:
15856 /* If we are deleting this reloc entry, we must fill in the
15857 value now. This can happen if we have a .word which is not
15858 resolved when it appears but is later defined. */
15860 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15863 case BFD_RELOC_16_PCREL_S2
:
15864 if ((*valP
& 0x3) != 0)
15865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15866 _("Branch to misaligned address (%lx)"), (long) *valP
);
15868 /* We need to save the bits in the instruction since fixup_segment()
15869 might be deleting the relocation entry (i.e., a branch within
15870 the current segment). */
15871 if (! fixP
->fx_done
)
15874 /* Update old instruction data. */
15875 insn
= read_insn (buf
);
15877 if (*valP
+ 0x20000 <= 0x3ffff)
15879 insn
|= (*valP
>> 2) & 0xffff;
15880 write_insn (buf
, insn
);
15882 else if (mips_pic
== NO_PIC
15884 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15885 && (fixP
->fx_frag
->fr_address
15886 < text_section
->vma
+ bfd_get_section_size (text_section
))
15887 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15888 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15889 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15891 /* The branch offset is too large. If this is an
15892 unconditional branch, and we are not generating PIC code,
15893 we can convert it to an absolute jump instruction. */
15894 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15895 insn
= 0x0c000000; /* jal */
15897 insn
= 0x08000000; /* j */
15898 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15900 fixP
->fx_addsy
= section_symbol (text_section
);
15901 *valP
+= md_pcrel_from (fixP
);
15902 write_insn (buf
, insn
);
15906 /* If we got here, we have branch-relaxation disabled,
15907 and there's nothing we can do to fix this instruction
15908 without turning it into a longer sequence. */
15909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15910 _("Branch out of range"));
15914 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15915 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15916 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15917 /* We adjust the offset back to even. */
15918 if ((*valP
& 0x1) != 0)
15921 if (! fixP
->fx_done
)
15924 /* Should never visit here, because we keep the relocation. */
15928 case BFD_RELOC_VTABLE_INHERIT
:
15931 && !S_IS_DEFINED (fixP
->fx_addsy
)
15932 && !S_IS_WEAK (fixP
->fx_addsy
))
15933 S_SET_WEAK (fixP
->fx_addsy
);
15936 case BFD_RELOC_VTABLE_ENTRY
:
15944 /* Remember value for tc_gen_reloc. */
15945 fixP
->fx_addnumber
= *valP
;
15955 name
= input_line_pointer
;
15956 c
= get_symbol_end ();
15957 p
= (symbolS
*) symbol_find_or_make (name
);
15958 *input_line_pointer
= c
;
15962 /* Align the current frag to a given power of two. If a particular
15963 fill byte should be used, FILL points to an integer that contains
15964 that byte, otherwise FILL is null.
15966 This function used to have the comment:
15968 The MIPS assembler also automatically adjusts any preceding label.
15970 The implementation therefore applied the adjustment to a maximum of
15971 one label. However, other label adjustments are applied to batches
15972 of labels, and adjusting just one caused problems when new labels
15973 were added for the sake of debugging or unwind information.
15974 We therefore adjust all preceding labels (given as LABELS) instead. */
15977 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15979 mips_emit_delays ();
15980 mips_record_compressed_mode ();
15981 if (fill
== NULL
&& subseg_text_p (now_seg
))
15982 frag_align_code (to
, 0);
15984 frag_align (to
, fill
? *fill
: 0, 0);
15985 record_alignment (now_seg
, to
);
15986 mips_move_labels (labels
, FALSE
);
15989 /* Align to a given power of two. .align 0 turns off the automatic
15990 alignment used by the data creating pseudo-ops. */
15993 s_align (int x ATTRIBUTE_UNUSED
)
15995 int temp
, fill_value
, *fill_ptr
;
15996 long max_alignment
= 28;
15998 /* o Note that the assembler pulls down any immediately preceding label
15999 to the aligned address.
16000 o It's not documented but auto alignment is reinstated by
16001 a .align pseudo instruction.
16002 o Note also that after auto alignment is turned off the mips assembler
16003 issues an error on attempt to assemble an improperly aligned data item.
16006 temp
= get_absolute_expression ();
16007 if (temp
> max_alignment
)
16008 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16011 as_warn (_("Alignment negative: 0 assumed."));
16014 if (*input_line_pointer
== ',')
16016 ++input_line_pointer
;
16017 fill_value
= get_absolute_expression ();
16018 fill_ptr
= &fill_value
;
16024 segment_info_type
*si
= seg_info (now_seg
);
16025 struct insn_label_list
*l
= si
->label_list
;
16026 /* Auto alignment should be switched on by next section change. */
16028 mips_align (temp
, fill_ptr
, l
);
16035 demand_empty_rest_of_line ();
16039 s_change_sec (int sec
)
16044 /* The ELF backend needs to know that we are changing sections, so
16045 that .previous works correctly. We could do something like check
16046 for an obj_section_change_hook macro, but that might be confusing
16047 as it would not be appropriate to use it in the section changing
16048 functions in read.c, since obj-elf.c intercepts those. FIXME:
16049 This should be cleaner, somehow. */
16051 obj_elf_section_change_hook ();
16054 mips_emit_delays ();
16065 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16066 demand_empty_rest_of_line ();
16070 seg
= subseg_new (RDATA_SECTION_NAME
,
16071 (subsegT
) get_absolute_expression ());
16074 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16075 | SEC_READONLY
| SEC_RELOC
16077 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16078 record_alignment (seg
, 4);
16080 demand_empty_rest_of_line ();
16084 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16087 bfd_set_section_flags (stdoutput
, seg
,
16088 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16089 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16090 record_alignment (seg
, 4);
16092 demand_empty_rest_of_line ();
16096 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16099 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16100 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16101 record_alignment (seg
, 4);
16103 demand_empty_rest_of_line ();
16111 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16114 char *section_name
;
16119 int section_entry_size
;
16120 int section_alignment
;
16125 section_name
= input_line_pointer
;
16126 c
= get_symbol_end ();
16128 next_c
= *(input_line_pointer
+ 1);
16130 /* Do we have .section Name<,"flags">? */
16131 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16133 /* just after name is now '\0'. */
16134 *input_line_pointer
= c
;
16135 input_line_pointer
= section_name
;
16136 obj_elf_section (ignore
);
16139 input_line_pointer
++;
16141 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16143 section_type
= get_absolute_expression ();
16146 if (*input_line_pointer
++ == ',')
16147 section_flag
= get_absolute_expression ();
16150 if (*input_line_pointer
++ == ',')
16151 section_entry_size
= get_absolute_expression ();
16153 section_entry_size
= 0;
16154 if (*input_line_pointer
++ == ',')
16155 section_alignment
= get_absolute_expression ();
16157 section_alignment
= 0;
16158 /* FIXME: really ignore? */
16159 (void) section_alignment
;
16161 section_name
= xstrdup (section_name
);
16163 /* When using the generic form of .section (as implemented by obj-elf.c),
16164 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16165 traditionally had to fall back on the more common @progbits instead.
16167 There's nothing really harmful in this, since bfd will correct
16168 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16169 means that, for backwards compatibility, the special_section entries
16170 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16172 Even so, we shouldn't force users of the MIPS .section syntax to
16173 incorrectly label the sections as SHT_PROGBITS. The best compromise
16174 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16175 generic type-checking code. */
16176 if (section_type
== SHT_MIPS_DWARF
)
16177 section_type
= SHT_PROGBITS
;
16179 obj_elf_change_section (section_name
, section_type
, section_flag
,
16180 section_entry_size
, 0, 0, 0);
16182 if (now_seg
->name
!= section_name
)
16183 free (section_name
);
16184 #endif /* OBJ_ELF */
16188 mips_enable_auto_align (void)
16194 s_cons (int log_size
)
16196 segment_info_type
*si
= seg_info (now_seg
);
16197 struct insn_label_list
*l
= si
->label_list
;
16199 mips_emit_delays ();
16200 if (log_size
> 0 && auto_align
)
16201 mips_align (log_size
, 0, l
);
16202 cons (1 << log_size
);
16203 mips_clear_insn_labels ();
16207 s_float_cons (int type
)
16209 segment_info_type
*si
= seg_info (now_seg
);
16210 struct insn_label_list
*l
= si
->label_list
;
16212 mips_emit_delays ();
16217 mips_align (3, 0, l
);
16219 mips_align (2, 0, l
);
16223 mips_clear_insn_labels ();
16226 /* Handle .globl. We need to override it because on Irix 5 you are
16229 where foo is an undefined symbol, to mean that foo should be
16230 considered to be the address of a function. */
16233 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16242 name
= input_line_pointer
;
16243 c
= get_symbol_end ();
16244 symbolP
= symbol_find_or_make (name
);
16245 S_SET_EXTERNAL (symbolP
);
16247 *input_line_pointer
= c
;
16248 SKIP_WHITESPACE ();
16250 /* On Irix 5, every global symbol that is not explicitly labelled as
16251 being a function is apparently labelled as being an object. */
16254 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16255 && (*input_line_pointer
!= ','))
16260 secname
= input_line_pointer
;
16261 c
= get_symbol_end ();
16262 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16264 as_bad (_("%s: no such section"), secname
);
16265 *input_line_pointer
= c
;
16267 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16268 flag
= BSF_FUNCTION
;
16271 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16273 c
= *input_line_pointer
;
16276 input_line_pointer
++;
16277 SKIP_WHITESPACE ();
16278 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16284 demand_empty_rest_of_line ();
16288 s_option (int x ATTRIBUTE_UNUSED
)
16293 opt
= input_line_pointer
;
16294 c
= get_symbol_end ();
16298 /* FIXME: What does this mean? */
16300 else if (strncmp (opt
, "pic", 3) == 0)
16304 i
= atoi (opt
+ 3);
16309 mips_pic
= SVR4_PIC
;
16310 mips_abicalls
= TRUE
;
16313 as_bad (_(".option pic%d not supported"), i
);
16315 if (mips_pic
== SVR4_PIC
)
16317 if (g_switch_seen
&& g_switch_value
!= 0)
16318 as_warn (_("-G may not be used with SVR4 PIC code"));
16319 g_switch_value
= 0;
16320 bfd_set_gp_size (stdoutput
, 0);
16324 as_warn (_("Unrecognized option \"%s\""), opt
);
16326 *input_line_pointer
= c
;
16327 demand_empty_rest_of_line ();
16330 /* This structure is used to hold a stack of .set values. */
16332 struct mips_option_stack
16334 struct mips_option_stack
*next
;
16335 struct mips_set_options options
;
16338 static struct mips_option_stack
*mips_opts_stack
;
16340 /* Handle the .set pseudo-op. */
16343 s_mipsset (int x ATTRIBUTE_UNUSED
)
16345 char *name
= input_line_pointer
, ch
;
16347 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16348 ++input_line_pointer
;
16349 ch
= *input_line_pointer
;
16350 *input_line_pointer
= '\0';
16352 if (strcmp (name
, "reorder") == 0)
16354 if (mips_opts
.noreorder
)
16357 else if (strcmp (name
, "noreorder") == 0)
16359 if (!mips_opts
.noreorder
)
16360 start_noreorder ();
16362 else if (strncmp (name
, "at=", 3) == 0)
16364 char *s
= name
+ 3;
16366 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16367 as_bad (_("Unrecognized register name `%s'"), s
);
16369 else if (strcmp (name
, "at") == 0)
16371 mips_opts
.at
= ATREG
;
16373 else if (strcmp (name
, "noat") == 0)
16375 mips_opts
.at
= ZERO
;
16377 else if (strcmp (name
, "macro") == 0)
16379 mips_opts
.warn_about_macros
= 0;
16381 else if (strcmp (name
, "nomacro") == 0)
16383 if (mips_opts
.noreorder
== 0)
16384 as_bad (_("`noreorder' must be set before `nomacro'"));
16385 mips_opts
.warn_about_macros
= 1;
16387 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16389 mips_opts
.nomove
= 0;
16391 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16393 mips_opts
.nomove
= 1;
16395 else if (strcmp (name
, "bopt") == 0)
16397 mips_opts
.nobopt
= 0;
16399 else if (strcmp (name
, "nobopt") == 0)
16401 mips_opts
.nobopt
= 1;
16403 else if (strcmp (name
, "gp=default") == 0)
16404 mips_opts
.gp32
= file_mips_gp32
;
16405 else if (strcmp (name
, "gp=32") == 0)
16406 mips_opts
.gp32
= 1;
16407 else if (strcmp (name
, "gp=64") == 0)
16409 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16410 as_warn (_("%s isa does not support 64-bit registers"),
16411 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16412 mips_opts
.gp32
= 0;
16414 else if (strcmp (name
, "fp=default") == 0)
16415 mips_opts
.fp32
= file_mips_fp32
;
16416 else if (strcmp (name
, "fp=32") == 0)
16417 mips_opts
.fp32
= 1;
16418 else if (strcmp (name
, "fp=64") == 0)
16420 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16421 as_warn (_("%s isa does not support 64-bit floating point registers"),
16422 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16423 mips_opts
.fp32
= 0;
16425 else if (strcmp (name
, "softfloat") == 0)
16426 mips_opts
.soft_float
= 1;
16427 else if (strcmp (name
, "hardfloat") == 0)
16428 mips_opts
.soft_float
= 0;
16429 else if (strcmp (name
, "singlefloat") == 0)
16430 mips_opts
.single_float
= 1;
16431 else if (strcmp (name
, "doublefloat") == 0)
16432 mips_opts
.single_float
= 0;
16433 else if (strcmp (name
, "mips16") == 0
16434 || strcmp (name
, "MIPS-16") == 0)
16436 if (mips_opts
.micromips
== 1)
16437 as_fatal (_("`mips16' cannot be used with `micromips'"));
16438 mips_opts
.mips16
= 1;
16440 else if (strcmp (name
, "nomips16") == 0
16441 || strcmp (name
, "noMIPS-16") == 0)
16442 mips_opts
.mips16
= 0;
16443 else if (strcmp (name
, "micromips") == 0)
16445 if (mips_opts
.mips16
== 1)
16446 as_fatal (_("`micromips' cannot be used with `mips16'"));
16447 mips_opts
.micromips
= 1;
16449 else if (strcmp (name
, "nomicromips") == 0)
16450 mips_opts
.micromips
= 0;
16451 else if (strcmp (name
, "smartmips") == 0)
16453 if (!ISA_SUPPORTS_SMARTMIPS
)
16454 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16455 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16456 mips_opts
.ase_smartmips
= 1;
16458 else if (strcmp (name
, "nosmartmips") == 0)
16459 mips_opts
.ase_smartmips
= 0;
16460 else if (strcmp (name
, "mips3d") == 0)
16461 mips_opts
.ase_mips3d
= 1;
16462 else if (strcmp (name
, "nomips3d") == 0)
16463 mips_opts
.ase_mips3d
= 0;
16464 else if (strcmp (name
, "mdmx") == 0)
16465 mips_opts
.ase_mdmx
= 1;
16466 else if (strcmp (name
, "nomdmx") == 0)
16467 mips_opts
.ase_mdmx
= 0;
16468 else if (strcmp (name
, "dsp") == 0)
16470 if (!ISA_SUPPORTS_DSP_ASE
)
16471 as_warn (_("%s ISA does not support DSP ASE"),
16472 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16473 mips_opts
.ase_dsp
= 1;
16474 mips_opts
.ase_dspr2
= 0;
16476 else if (strcmp (name
, "nodsp") == 0)
16478 mips_opts
.ase_dsp
= 0;
16479 mips_opts
.ase_dspr2
= 0;
16481 else if (strcmp (name
, "dspr2") == 0)
16483 if (!ISA_SUPPORTS_DSPR2_ASE
)
16484 as_warn (_("%s ISA does not support DSP R2 ASE"),
16485 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16486 mips_opts
.ase_dspr2
= 1;
16487 mips_opts
.ase_dsp
= 1;
16489 else if (strcmp (name
, "nodspr2") == 0)
16491 mips_opts
.ase_dspr2
= 0;
16492 mips_opts
.ase_dsp
= 0;
16494 else if (strcmp (name
, "mt") == 0)
16496 if (!ISA_SUPPORTS_MT_ASE
)
16497 as_warn (_("%s ISA does not support MT ASE"),
16498 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16499 mips_opts
.ase_mt
= 1;
16501 else if (strcmp (name
, "nomt") == 0)
16502 mips_opts
.ase_mt
= 0;
16503 else if (strcmp (name
, "mcu") == 0)
16504 mips_opts
.ase_mcu
= 1;
16505 else if (strcmp (name
, "nomcu") == 0)
16506 mips_opts
.ase_mcu
= 0;
16507 else if (strcmp (name
, "virt") == 0)
16509 if (!ISA_SUPPORTS_VIRT_ASE
)
16510 as_warn (_("%s ISA does not support Virtualization ASE"),
16511 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16512 mips_opts
.ase_virt
= 1;
16514 else if (strcmp (name
, "novirt") == 0)
16515 mips_opts
.ase_virt
= 0;
16516 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16520 /* Permit the user to change the ISA and architecture on the fly.
16521 Needless to say, misuse can cause serious problems. */
16522 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16525 mips_opts
.isa
= file_mips_isa
;
16526 mips_opts
.arch
= file_mips_arch
;
16528 else if (strncmp (name
, "arch=", 5) == 0)
16530 const struct mips_cpu_info
*p
;
16532 p
= mips_parse_cpu("internal use", name
+ 5);
16534 as_bad (_("unknown architecture %s"), name
+ 5);
16537 mips_opts
.arch
= p
->cpu
;
16538 mips_opts
.isa
= p
->isa
;
16541 else if (strncmp (name
, "mips", 4) == 0)
16543 const struct mips_cpu_info
*p
;
16545 p
= mips_parse_cpu("internal use", name
);
16547 as_bad (_("unknown ISA level %s"), name
+ 4);
16550 mips_opts
.arch
= p
->cpu
;
16551 mips_opts
.isa
= p
->isa
;
16555 as_bad (_("unknown ISA or architecture %s"), name
);
16557 switch (mips_opts
.isa
)
16565 mips_opts
.gp32
= 1;
16566 mips_opts
.fp32
= 1;
16573 mips_opts
.gp32
= 0;
16574 if (mips_opts
.arch
== CPU_R5900
)
16576 mips_opts
.fp32
= 1;
16580 mips_opts
.fp32
= 0;
16584 as_bad (_("unknown ISA level %s"), name
+ 4);
16589 mips_opts
.gp32
= file_mips_gp32
;
16590 mips_opts
.fp32
= file_mips_fp32
;
16593 else if (strcmp (name
, "autoextend") == 0)
16594 mips_opts
.noautoextend
= 0;
16595 else if (strcmp (name
, "noautoextend") == 0)
16596 mips_opts
.noautoextend
= 1;
16597 else if (strcmp (name
, "push") == 0)
16599 struct mips_option_stack
*s
;
16601 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16602 s
->next
= mips_opts_stack
;
16603 s
->options
= mips_opts
;
16604 mips_opts_stack
= s
;
16606 else if (strcmp (name
, "pop") == 0)
16608 struct mips_option_stack
*s
;
16610 s
= mips_opts_stack
;
16612 as_bad (_(".set pop with no .set push"));
16615 /* If we're changing the reorder mode we need to handle
16616 delay slots correctly. */
16617 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16618 start_noreorder ();
16619 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16622 mips_opts
= s
->options
;
16623 mips_opts_stack
= s
->next
;
16627 else if (strcmp (name
, "sym32") == 0)
16628 mips_opts
.sym32
= TRUE
;
16629 else if (strcmp (name
, "nosym32") == 0)
16630 mips_opts
.sym32
= FALSE
;
16631 else if (strchr (name
, ','))
16633 /* Generic ".set" directive; use the generic handler. */
16634 *input_line_pointer
= ch
;
16635 input_line_pointer
= name
;
16641 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16643 *input_line_pointer
= ch
;
16644 demand_empty_rest_of_line ();
16647 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16648 .option pic2. It means to generate SVR4 PIC calls. */
16651 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16653 mips_pic
= SVR4_PIC
;
16654 mips_abicalls
= TRUE
;
16656 if (g_switch_seen
&& g_switch_value
!= 0)
16657 as_warn (_("-G may not be used with SVR4 PIC code"));
16658 g_switch_value
= 0;
16660 bfd_set_gp_size (stdoutput
, 0);
16661 demand_empty_rest_of_line ();
16664 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16665 PIC code. It sets the $gp register for the function based on the
16666 function address, which is in the register named in the argument.
16667 This uses a relocation against _gp_disp, which is handled specially
16668 by the linker. The result is:
16669 lui $gp,%hi(_gp_disp)
16670 addiu $gp,$gp,%lo(_gp_disp)
16671 addu $gp,$gp,.cpload argument
16672 The .cpload argument is normally $25 == $t9.
16674 The -mno-shared option changes this to:
16675 lui $gp,%hi(__gnu_local_gp)
16676 addiu $gp,$gp,%lo(__gnu_local_gp)
16677 and the argument is ignored. This saves an instruction, but the
16678 resulting code is not position independent; it uses an absolute
16679 address for __gnu_local_gp. Thus code assembled with -mno-shared
16680 can go into an ordinary executable, but not into a shared library. */
16683 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16689 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16690 .cpload is ignored. */
16691 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16697 if (mips_opts
.mips16
)
16699 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16700 ignore_rest_of_line ();
16704 /* .cpload should be in a .set noreorder section. */
16705 if (mips_opts
.noreorder
== 0)
16706 as_warn (_(".cpload not in noreorder section"));
16708 reg
= tc_get_register (0);
16710 /* If we need to produce a 64-bit address, we are better off using
16711 the default instruction sequence. */
16712 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16714 ex
.X_op
= O_symbol
;
16715 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16717 ex
.X_op_symbol
= NULL
;
16718 ex
.X_add_number
= 0;
16720 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16721 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16723 mips_mark_labels ();
16724 mips_assembling_insn
= TRUE
;
16727 macro_build_lui (&ex
, mips_gp_register
);
16728 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16729 mips_gp_register
, BFD_RELOC_LO16
);
16731 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16732 mips_gp_register
, reg
);
16735 mips_assembling_insn
= FALSE
;
16736 demand_empty_rest_of_line ();
16739 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16740 .cpsetup $reg1, offset|$reg2, label
16742 If offset is given, this results in:
16743 sd $gp, offset($sp)
16744 lui $gp, %hi(%neg(%gp_rel(label)))
16745 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16746 daddu $gp, $gp, $reg1
16748 If $reg2 is given, this results in:
16749 daddu $reg2, $gp, $0
16750 lui $gp, %hi(%neg(%gp_rel(label)))
16751 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16752 daddu $gp, $gp, $reg1
16753 $reg1 is normally $25 == $t9.
16755 The -mno-shared option replaces the last three instructions with
16757 addiu $gp,$gp,%lo(_gp) */
16760 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16762 expressionS ex_off
;
16763 expressionS ex_sym
;
16766 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16767 We also need NewABI support. */
16768 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16774 if (mips_opts
.mips16
)
16776 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16777 ignore_rest_of_line ();
16781 reg1
= tc_get_register (0);
16782 SKIP_WHITESPACE ();
16783 if (*input_line_pointer
!= ',')
16785 as_bad (_("missing argument separator ',' for .cpsetup"));
16789 ++input_line_pointer
;
16790 SKIP_WHITESPACE ();
16791 if (*input_line_pointer
== '$')
16793 mips_cpreturn_register
= tc_get_register (0);
16794 mips_cpreturn_offset
= -1;
16798 mips_cpreturn_offset
= get_absolute_expression ();
16799 mips_cpreturn_register
= -1;
16801 SKIP_WHITESPACE ();
16802 if (*input_line_pointer
!= ',')
16804 as_bad (_("missing argument separator ',' for .cpsetup"));
16808 ++input_line_pointer
;
16809 SKIP_WHITESPACE ();
16810 expression (&ex_sym
);
16812 mips_mark_labels ();
16813 mips_assembling_insn
= TRUE
;
16816 if (mips_cpreturn_register
== -1)
16818 ex_off
.X_op
= O_constant
;
16819 ex_off
.X_add_symbol
= NULL
;
16820 ex_off
.X_op_symbol
= NULL
;
16821 ex_off
.X_add_number
= mips_cpreturn_offset
;
16823 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16824 BFD_RELOC_LO16
, SP
);
16827 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16828 mips_gp_register
, 0);
16830 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16832 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16833 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16836 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16837 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16838 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16840 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16841 mips_gp_register
, reg1
);
16847 ex
.X_op
= O_symbol
;
16848 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16849 ex
.X_op_symbol
= NULL
;
16850 ex
.X_add_number
= 0;
16852 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16853 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16855 macro_build_lui (&ex
, mips_gp_register
);
16856 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16857 mips_gp_register
, BFD_RELOC_LO16
);
16862 mips_assembling_insn
= FALSE
;
16863 demand_empty_rest_of_line ();
16867 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16869 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16870 .cplocal is ignored. */
16871 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16877 if (mips_opts
.mips16
)
16879 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16880 ignore_rest_of_line ();
16884 mips_gp_register
= tc_get_register (0);
16885 demand_empty_rest_of_line ();
16888 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16889 offset from $sp. The offset is remembered, and after making a PIC
16890 call $gp is restored from that location. */
16893 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16897 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16898 .cprestore is ignored. */
16899 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16905 if (mips_opts
.mips16
)
16907 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16908 ignore_rest_of_line ();
16912 mips_cprestore_offset
= get_absolute_expression ();
16913 mips_cprestore_valid
= 1;
16915 ex
.X_op
= O_constant
;
16916 ex
.X_add_symbol
= NULL
;
16917 ex
.X_op_symbol
= NULL
;
16918 ex
.X_add_number
= mips_cprestore_offset
;
16920 mips_mark_labels ();
16921 mips_assembling_insn
= TRUE
;
16924 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16925 SP
, HAVE_64BIT_ADDRESSES
);
16928 mips_assembling_insn
= FALSE
;
16929 demand_empty_rest_of_line ();
16932 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16933 was given in the preceding .cpsetup, it results in:
16934 ld $gp, offset($sp)
16936 If a register $reg2 was given there, it results in:
16937 daddu $gp, $reg2, $0 */
16940 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16944 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16945 We also need NewABI support. */
16946 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16952 if (mips_opts
.mips16
)
16954 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16955 ignore_rest_of_line ();
16959 mips_mark_labels ();
16960 mips_assembling_insn
= TRUE
;
16963 if (mips_cpreturn_register
== -1)
16965 ex
.X_op
= O_constant
;
16966 ex
.X_add_symbol
= NULL
;
16967 ex
.X_op_symbol
= NULL
;
16968 ex
.X_add_number
= mips_cpreturn_offset
;
16970 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16973 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16974 mips_cpreturn_register
, 0);
16977 mips_assembling_insn
= FALSE
;
16978 demand_empty_rest_of_line ();
16981 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16982 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16983 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16984 debug information or MIPS16 TLS. */
16987 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16988 bfd_reloc_code_real_type rtype
)
16995 if (ex
.X_op
!= O_symbol
)
16997 as_bad (_("Unsupported use of %s"), dirstr
);
16998 ignore_rest_of_line ();
17001 p
= frag_more (bytes
);
17002 md_number_to_chars (p
, 0, bytes
);
17003 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17004 demand_empty_rest_of_line ();
17005 mips_clear_insn_labels ();
17008 /* Handle .dtprelword. */
17011 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17013 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17016 /* Handle .dtpreldword. */
17019 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17021 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17024 /* Handle .tprelword. */
17027 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17029 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17032 /* Handle .tpreldword. */
17035 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17037 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17040 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17041 code. It sets the offset to use in gp_rel relocations. */
17044 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17046 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17047 We also need NewABI support. */
17048 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17054 mips_gprel_offset
= get_absolute_expression ();
17056 demand_empty_rest_of_line ();
17059 /* Handle the .gpword pseudo-op. This is used when generating PIC
17060 code. It generates a 32 bit GP relative reloc. */
17063 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17065 segment_info_type
*si
;
17066 struct insn_label_list
*l
;
17070 /* When not generating PIC code, this is treated as .word. */
17071 if (mips_pic
!= SVR4_PIC
)
17077 si
= seg_info (now_seg
);
17078 l
= si
->label_list
;
17079 mips_emit_delays ();
17081 mips_align (2, 0, l
);
17084 mips_clear_insn_labels ();
17086 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17088 as_bad (_("Unsupported use of .gpword"));
17089 ignore_rest_of_line ();
17093 md_number_to_chars (p
, 0, 4);
17094 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17095 BFD_RELOC_GPREL32
);
17097 demand_empty_rest_of_line ();
17101 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17103 segment_info_type
*si
;
17104 struct insn_label_list
*l
;
17108 /* When not generating PIC code, this is treated as .dword. */
17109 if (mips_pic
!= SVR4_PIC
)
17115 si
= seg_info (now_seg
);
17116 l
= si
->label_list
;
17117 mips_emit_delays ();
17119 mips_align (3, 0, l
);
17122 mips_clear_insn_labels ();
17124 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17126 as_bad (_("Unsupported use of .gpdword"));
17127 ignore_rest_of_line ();
17131 md_number_to_chars (p
, 0, 8);
17132 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17133 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17135 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17136 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17137 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17139 demand_empty_rest_of_line ();
17142 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17143 tables in SVR4 PIC code. */
17146 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17150 /* This is ignored when not generating SVR4 PIC code. */
17151 if (mips_pic
!= SVR4_PIC
)
17157 mips_mark_labels ();
17158 mips_assembling_insn
= TRUE
;
17160 /* Add $gp to the register named as an argument. */
17162 reg
= tc_get_register (0);
17163 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17166 mips_assembling_insn
= FALSE
;
17167 demand_empty_rest_of_line ();
17170 /* Handle the .insn pseudo-op. This marks instruction labels in
17171 mips16/micromips mode. This permits the linker to handle them specially,
17172 such as generating jalx instructions when needed. We also make
17173 them odd for the duration of the assembly, in order to generate the
17174 right sort of code. We will make them even in the adjust_symtab
17175 routine, while leaving them marked. This is convenient for the
17176 debugger and the disassembler. The linker knows to make them odd
17180 s_insn (int ignore ATTRIBUTE_UNUSED
)
17182 mips_mark_labels ();
17184 demand_empty_rest_of_line ();
17187 /* Handle a .stab[snd] directive. Ideally these directives would be
17188 implemented in a transparent way, so that removing them would not
17189 have any effect on the generated instructions. However, s_stab
17190 internally changes the section, so in practice we need to decide
17191 now whether the preceding label marks compressed code. We do not
17192 support changing the compression mode of a label after a .stab*
17193 directive, such as in:
17199 so the current mode wins. */
17202 s_mips_stab (int type
)
17204 mips_mark_labels ();
17208 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17211 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17218 name
= input_line_pointer
;
17219 c
= get_symbol_end ();
17220 symbolP
= symbol_find_or_make (name
);
17221 S_SET_WEAK (symbolP
);
17222 *input_line_pointer
= c
;
17224 SKIP_WHITESPACE ();
17226 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17228 if (S_IS_DEFINED (symbolP
))
17230 as_bad (_("ignoring attempt to redefine symbol %s"),
17231 S_GET_NAME (symbolP
));
17232 ignore_rest_of_line ();
17236 if (*input_line_pointer
== ',')
17238 ++input_line_pointer
;
17239 SKIP_WHITESPACE ();
17243 if (exp
.X_op
!= O_symbol
)
17245 as_bad (_("bad .weakext directive"));
17246 ignore_rest_of_line ();
17249 symbol_set_value_expression (symbolP
, &exp
);
17252 demand_empty_rest_of_line ();
17255 /* Parse a register string into a number. Called from the ECOFF code
17256 to parse .frame. The argument is non-zero if this is the frame
17257 register, so that we can record it in mips_frame_reg. */
17260 tc_get_register (int frame
)
17264 SKIP_WHITESPACE ();
17265 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17269 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17270 mips_frame_reg_valid
= 1;
17271 mips_cprestore_valid
= 0;
17277 md_section_align (asection
*seg
, valueT addr
)
17279 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17283 /* We don't need to align ELF sections to the full alignment.
17284 However, Irix 5 may prefer that we align them at least to a 16
17285 byte boundary. We don't bother to align the sections if we
17286 are targeted for an embedded system. */
17287 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17293 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17296 /* Utility routine, called from above as well. If called while the
17297 input file is still being read, it's only an approximation. (For
17298 example, a symbol may later become defined which appeared to be
17299 undefined earlier.) */
17302 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17307 if (g_switch_value
> 0)
17309 const char *symname
;
17312 /* Find out whether this symbol can be referenced off the $gp
17313 register. It can be if it is smaller than the -G size or if
17314 it is in the .sdata or .sbss section. Certain symbols can
17315 not be referenced off the $gp, although it appears as though
17317 symname
= S_GET_NAME (sym
);
17318 if (symname
!= (const char *) NULL
17319 && (strcmp (symname
, "eprol") == 0
17320 || strcmp (symname
, "etext") == 0
17321 || strcmp (symname
, "_gp") == 0
17322 || strcmp (symname
, "edata") == 0
17323 || strcmp (symname
, "_fbss") == 0
17324 || strcmp (symname
, "_fdata") == 0
17325 || strcmp (symname
, "_ftext") == 0
17326 || strcmp (symname
, "end") == 0
17327 || strcmp (symname
, "_gp_disp") == 0))
17329 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17331 #ifndef NO_ECOFF_DEBUGGING
17332 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17333 && (symbol_get_obj (sym
)->ecoff_extern_size
17334 <= g_switch_value
))
17336 /* We must defer this decision until after the whole
17337 file has been read, since there might be a .extern
17338 after the first use of this symbol. */
17339 || (before_relaxing
17340 #ifndef NO_ECOFF_DEBUGGING
17341 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17343 && S_GET_VALUE (sym
) == 0)
17344 || (S_GET_VALUE (sym
) != 0
17345 && S_GET_VALUE (sym
) <= g_switch_value
)))
17349 const char *segname
;
17351 segname
= segment_name (S_GET_SEGMENT (sym
));
17352 gas_assert (strcmp (segname
, ".lit8") != 0
17353 && strcmp (segname
, ".lit4") != 0);
17354 change
= (strcmp (segname
, ".sdata") != 0
17355 && strcmp (segname
, ".sbss") != 0
17356 && strncmp (segname
, ".sdata.", 7) != 0
17357 && strncmp (segname
, ".sbss.", 6) != 0
17358 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17359 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17364 /* We are not optimizing for the $gp register. */
17369 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17372 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17376 /* Handle the case of a symbol equated to another symbol. */
17377 while (symbol_equated_reloc_p (sym
))
17381 /* It's possible to get a loop here in a badly written program. */
17382 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17388 if (symbol_section_p (sym
))
17391 symsec
= S_GET_SEGMENT (sym
);
17393 /* This must duplicate the test in adjust_reloc_syms. */
17394 return (!bfd_is_und_section (symsec
)
17395 && !bfd_is_abs_section (symsec
)
17396 && !bfd_is_com_section (symsec
)
17397 && !s_is_linkonce (sym
, segtype
)
17399 /* A global or weak symbol is treated as external. */
17400 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17406 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17407 extended opcode. SEC is the section the frag is in. */
17410 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17413 const struct mips16_immed_operand
*op
;
17415 int mintiny
, maxtiny
;
17419 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17421 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17424 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17425 op
= mips16_immed_operands
;
17426 while (op
->type
!= type
)
17429 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17434 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17437 maxtiny
= 1 << op
->nbits
;
17442 maxtiny
= (1 << op
->nbits
) - 1;
17447 mintiny
= - (1 << (op
->nbits
- 1));
17448 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17451 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17452 val
= S_GET_VALUE (fragp
->fr_symbol
);
17453 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17459 /* We won't have the section when we are called from
17460 mips_relax_frag. However, we will always have been called
17461 from md_estimate_size_before_relax first. If this is a
17462 branch to a different section, we mark it as such. If SEC is
17463 NULL, and the frag is not marked, then it must be a branch to
17464 the same section. */
17467 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17472 /* Must have been called from md_estimate_size_before_relax. */
17475 fragp
->fr_subtype
=
17476 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17478 /* FIXME: We should support this, and let the linker
17479 catch branches and loads that are out of range. */
17480 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17481 _("unsupported PC relative reference to different section"));
17485 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17486 /* Assume non-extended on the first relaxation pass.
17487 The address we have calculated will be bogus if this is
17488 a forward branch to another frag, as the forward frag
17489 will have fr_address == 0. */
17493 /* In this case, we know for sure that the symbol fragment is in
17494 the same section. If the relax_marker of the symbol fragment
17495 differs from the relax_marker of this fragment, we have not
17496 yet adjusted the symbol fragment fr_address. We want to add
17497 in STRETCH in order to get a better estimate of the address.
17498 This particularly matters because of the shift bits. */
17500 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17504 /* Adjust stretch for any alignment frag. Note that if have
17505 been expanding the earlier code, the symbol may be
17506 defined in what appears to be an earlier frag. FIXME:
17507 This doesn't handle the fr_subtype field, which specifies
17508 a maximum number of bytes to skip when doing an
17510 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17512 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17515 stretch
= - ((- stretch
)
17516 & ~ ((1 << (int) f
->fr_offset
) - 1));
17518 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17527 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17529 /* The base address rules are complicated. The base address of
17530 a branch is the following instruction. The base address of a
17531 PC relative load or add is the instruction itself, but if it
17532 is in a delay slot (in which case it can not be extended) use
17533 the address of the instruction whose delay slot it is in. */
17534 if (type
== 'p' || type
== 'q')
17538 /* If we are currently assuming that this frag should be
17539 extended, then, the current address is two bytes
17541 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17544 /* Ignore the low bit in the target, since it will be set
17545 for a text label. */
17546 if ((val
& 1) != 0)
17549 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17551 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17554 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17556 /* Branch offsets have an implicit 0 in the lowest bit. */
17557 if (type
== 'p' || type
== 'q')
17560 /* If any of the shifted bits are set, we must use an extended
17561 opcode. If the address depends on the size of this
17562 instruction, this can lead to a loop, so we arrange to always
17563 use an extended opcode. We only check this when we are in
17564 the main relaxation loop, when SEC is NULL. */
17565 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17567 fragp
->fr_subtype
=
17568 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17572 /* If we are about to mark a frag as extended because the value
17573 is precisely maxtiny + 1, then there is a chance of an
17574 infinite loop as in the following code:
17579 In this case when the la is extended, foo is 0x3fc bytes
17580 away, so the la can be shrunk, but then foo is 0x400 away, so
17581 the la must be extended. To avoid this loop, we mark the
17582 frag as extended if it was small, and is about to become
17583 extended with a value of maxtiny + 1. */
17584 if (val
== ((maxtiny
+ 1) << op
->shift
)
17585 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17588 fragp
->fr_subtype
=
17589 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17593 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17594 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17596 if ((val
& ((1 << op
->shift
) - 1)) != 0
17597 || val
< (mintiny
<< op
->shift
)
17598 || val
> (maxtiny
<< op
->shift
))
17604 /* Compute the length of a branch sequence, and adjust the
17605 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17606 worst-case length is computed, with UPDATE being used to indicate
17607 whether an unconditional (-1), branch-likely (+1) or regular (0)
17608 branch is to be computed. */
17610 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17612 bfd_boolean toofar
;
17616 && S_IS_DEFINED (fragp
->fr_symbol
)
17617 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17622 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17624 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17628 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17631 /* If the symbol is not defined or it's in a different segment,
17632 assume the user knows what's going on and emit a short
17638 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17640 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17641 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17642 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17643 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17649 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17652 if (mips_pic
!= NO_PIC
)
17654 /* Additional space for PIC loading of target address. */
17656 if (mips_opts
.isa
== ISA_MIPS1
)
17657 /* Additional space for $at-stabilizing nop. */
17661 /* If branch is conditional. */
17662 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17669 /* Compute the length of a branch sequence, and adjust the
17670 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17671 worst-case length is computed, with UPDATE being used to indicate
17672 whether an unconditional (-1), or regular (0) branch is to be
17676 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17678 bfd_boolean toofar
;
17682 && S_IS_DEFINED (fragp
->fr_symbol
)
17683 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17688 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17689 /* Ignore the low bit in the target, since it will be set
17690 for a text label. */
17691 if ((val
& 1) != 0)
17694 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17698 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17701 /* If the symbol is not defined or it's in a different segment,
17702 assume the user knows what's going on and emit a short
17708 if (fragp
&& update
17709 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17710 fragp
->fr_subtype
= (toofar
17711 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17712 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17717 bfd_boolean compact_known
= fragp
!= NULL
;
17718 bfd_boolean compact
= FALSE
;
17719 bfd_boolean uncond
;
17722 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17724 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17726 uncond
= update
< 0;
17728 /* If label is out of range, we turn branch <br>:
17730 <br> label # 4 bytes
17736 nop # 2 bytes if compact && !PIC
17739 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17742 /* If assembling PIC code, we further turn:
17748 lw/ld at, %got(label)(gp) # 4 bytes
17749 d/addiu at, %lo(label) # 4 bytes
17752 if (mips_pic
!= NO_PIC
)
17755 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17757 <brneg> 0f # 4 bytes
17758 nop # 2 bytes if !compact
17761 length
+= (compact_known
&& compact
) ? 4 : 6;
17767 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17768 bit accordingly. */
17771 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17773 bfd_boolean toofar
;
17776 && S_IS_DEFINED (fragp
->fr_symbol
)
17777 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17783 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17784 /* Ignore the low bit in the target, since it will be set
17785 for a text label. */
17786 if ((val
& 1) != 0)
17789 /* Assume this is a 2-byte branch. */
17790 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17792 /* We try to avoid the infinite loop by not adding 2 more bytes for
17797 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17799 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17800 else if (type
== 'E')
17801 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17806 /* If the symbol is not defined or it's in a different segment,
17807 we emit a normal 32-bit branch. */
17810 if (fragp
&& update
17811 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17813 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17814 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17822 /* Estimate the size of a frag before relaxing. Unless this is the
17823 mips16, we are not really relaxing here, and the final size is
17824 encoded in the subtype information. For the mips16, we have to
17825 decide whether we are using an extended opcode or not. */
17828 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17832 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17835 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17837 return fragp
->fr_var
;
17840 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17841 /* We don't want to modify the EXTENDED bit here; it might get us
17842 into infinite loops. We change it only in mips_relax_frag(). */
17843 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17845 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17849 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17850 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17851 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17852 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17853 fragp
->fr_var
= length
;
17858 if (mips_pic
== NO_PIC
)
17859 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17860 else if (mips_pic
== SVR4_PIC
)
17861 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17862 else if (mips_pic
== VXWORKS_PIC
)
17863 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17870 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17871 return -RELAX_FIRST (fragp
->fr_subtype
);
17874 return -RELAX_SECOND (fragp
->fr_subtype
);
17877 /* This is called to see whether a reloc against a defined symbol
17878 should be converted into a reloc against a section. */
17881 mips_fix_adjustable (fixS
*fixp
)
17883 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17884 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17887 if (fixp
->fx_addsy
== NULL
)
17890 /* If symbol SYM is in a mergeable section, relocations of the form
17891 SYM + 0 can usually be made section-relative. The mergeable data
17892 is then identified by the section offset rather than by the symbol.
17894 However, if we're generating REL LO16 relocations, the offset is split
17895 between the LO16 and parterning high part relocation. The linker will
17896 need to recalculate the complete offset in order to correctly identify
17899 The linker has traditionally not looked for the parterning high part
17900 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17901 placed anywhere. Rather than break backwards compatibility by changing
17902 this, it seems better not to force the issue, and instead keep the
17903 original symbol. This will work with either linker behavior. */
17904 if ((lo16_reloc_p (fixp
->fx_r_type
)
17905 || reloc_needs_lo_p (fixp
->fx_r_type
))
17906 && HAVE_IN_PLACE_ADDENDS
17907 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17910 /* There is no place to store an in-place offset for JALR relocations.
17911 Likewise an in-range offset of limited PC-relative relocations may
17912 overflow the in-place relocatable field if recalculated against the
17913 start address of the symbol's containing section. */
17914 if (HAVE_IN_PLACE_ADDENDS
17915 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17916 || jalr_reloc_p (fixp
->fx_r_type
)))
17920 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17921 to a floating-point stub. The same is true for non-R_MIPS16_26
17922 relocations against MIPS16 functions; in this case, the stub becomes
17923 the function's canonical address.
17925 Floating-point stubs are stored in unique .mips16.call.* or
17926 .mips16.fn.* sections. If a stub T for function F is in section S,
17927 the first relocation in section S must be against F; this is how the
17928 linker determines the target function. All relocations that might
17929 resolve to T must also be against F. We therefore have the following
17930 restrictions, which are given in an intentionally-redundant way:
17932 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17935 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17936 if that stub might be used.
17938 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17941 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17942 that stub might be used.
17944 There is a further restriction:
17946 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17947 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17948 targets with in-place addends; the relocation field cannot
17949 encode the low bit.
17951 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17952 against a MIPS16 symbol. We deal with (5) by by not reducing any
17953 such relocations on REL targets.
17955 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17956 relocation against some symbol R, no relocation against R may be
17957 reduced. (Note that this deals with (2) as well as (1) because
17958 relocations against global symbols will never be reduced on ELF
17959 targets.) This approach is a little simpler than trying to detect
17960 stub sections, and gives the "all or nothing" per-symbol consistency
17961 that we have for MIPS16 symbols. */
17963 && fixp
->fx_subsy
== NULL
17964 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17965 || *symbol_get_tc (fixp
->fx_addsy
)
17966 || (HAVE_IN_PLACE_ADDENDS
17967 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17968 && jmp_reloc_p (fixp
->fx_r_type
))))
17975 /* Translate internal representation of relocation info to BFD target
17979 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17981 static arelent
*retval
[4];
17983 bfd_reloc_code_real_type code
;
17985 memset (retval
, 0, sizeof(retval
));
17986 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17987 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17988 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17989 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17991 if (fixp
->fx_pcrel
)
17993 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17994 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17995 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17996 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17997 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
17999 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18000 Relocations want only the symbol offset. */
18001 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18004 /* A gruesome hack which is a result of the gruesome gas
18005 reloc handling. What's worse, for COFF (as opposed to
18006 ECOFF), we might need yet another copy of reloc->address.
18007 See bfd_install_relocation. */
18008 reloc
->addend
+= reloc
->address
;
18012 reloc
->addend
= fixp
->fx_addnumber
;
18014 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18015 entry to be used in the relocation's section offset. */
18016 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18018 reloc
->address
= reloc
->addend
;
18022 code
= fixp
->fx_r_type
;
18024 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18025 if (reloc
->howto
== NULL
)
18027 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18028 _("Can not represent %s relocation in this object file format"),
18029 bfd_get_reloc_code_name (code
));
18036 /* Relax a machine dependent frag. This returns the amount by which
18037 the current size of the frag should change. */
18040 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18042 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18044 offsetT old_var
= fragp
->fr_var
;
18046 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18048 return fragp
->fr_var
- old_var
;
18051 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18053 offsetT old_var
= fragp
->fr_var
;
18054 offsetT new_var
= 4;
18056 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18057 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18058 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18059 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18060 fragp
->fr_var
= new_var
;
18062 return new_var
- old_var
;
18065 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18068 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18070 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18072 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18077 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18079 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18086 /* Convert a machine dependent frag. */
18089 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18091 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18094 unsigned long insn
;
18098 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18099 insn
= read_insn (buf
);
18101 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18103 /* We generate a fixup instead of applying it right now
18104 because, if there are linker relaxations, we're going to
18105 need the relocations. */
18106 exp
.X_op
= O_symbol
;
18107 exp
.X_add_symbol
= fragp
->fr_symbol
;
18108 exp
.X_add_number
= fragp
->fr_offset
;
18110 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18111 BFD_RELOC_16_PCREL_S2
);
18112 fixp
->fx_file
= fragp
->fr_file
;
18113 fixp
->fx_line
= fragp
->fr_line
;
18115 buf
= write_insn (buf
, insn
);
18121 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18122 _("Relaxed out-of-range branch into a jump"));
18124 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18127 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18129 /* Reverse the branch. */
18130 switch ((insn
>> 28) & 0xf)
18133 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18134 have the condition reversed by tweaking a single
18135 bit, and their opcodes all have 0x4???????. */
18136 gas_assert ((insn
& 0xf1000000) == 0x41000000);
18137 insn
^= 0x00010000;
18141 /* bltz 0x04000000 bgez 0x04010000
18142 bltzal 0x04100000 bgezal 0x04110000 */
18143 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18144 insn
^= 0x00010000;
18148 /* beq 0x10000000 bne 0x14000000
18149 blez 0x18000000 bgtz 0x1c000000 */
18150 insn
^= 0x04000000;
18158 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18160 /* Clear the and-link bit. */
18161 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18163 /* bltzal 0x04100000 bgezal 0x04110000
18164 bltzall 0x04120000 bgezall 0x04130000 */
18165 insn
&= ~0x00100000;
18168 /* Branch over the branch (if the branch was likely) or the
18169 full jump (not likely case). Compute the offset from the
18170 current instruction to branch to. */
18171 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18175 /* How many bytes in instructions we've already emitted? */
18176 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18177 /* How many bytes in instructions from here to the end? */
18178 i
= fragp
->fr_var
- i
;
18180 /* Convert to instruction count. */
18182 /* Branch counts from the next instruction. */
18185 /* Branch over the jump. */
18186 buf
= write_insn (buf
, insn
);
18189 buf
= write_insn (buf
, 0);
18191 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18193 /* beql $0, $0, 2f */
18195 /* Compute the PC offset from the current instruction to
18196 the end of the variable frag. */
18197 /* How many bytes in instructions we've already emitted? */
18198 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18199 /* How many bytes in instructions from here to the end? */
18200 i
= fragp
->fr_var
- i
;
18201 /* Convert to instruction count. */
18203 /* Don't decrement i, because we want to branch over the
18207 buf
= write_insn (buf
, insn
);
18208 buf
= write_insn (buf
, 0);
18212 if (mips_pic
== NO_PIC
)
18215 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18216 ? 0x0c000000 : 0x08000000);
18217 exp
.X_op
= O_symbol
;
18218 exp
.X_add_symbol
= fragp
->fr_symbol
;
18219 exp
.X_add_number
= fragp
->fr_offset
;
18221 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18222 FALSE
, BFD_RELOC_MIPS_JMP
);
18223 fixp
->fx_file
= fragp
->fr_file
;
18224 fixp
->fx_line
= fragp
->fr_line
;
18226 buf
= write_insn (buf
, insn
);
18230 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18232 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18233 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18234 insn
|= at
<< OP_SH_RT
;
18235 exp
.X_op
= O_symbol
;
18236 exp
.X_add_symbol
= fragp
->fr_symbol
;
18237 exp
.X_add_number
= fragp
->fr_offset
;
18239 if (fragp
->fr_offset
)
18241 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18242 exp
.X_add_number
= 0;
18245 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18246 FALSE
, BFD_RELOC_MIPS_GOT16
);
18247 fixp
->fx_file
= fragp
->fr_file
;
18248 fixp
->fx_line
= fragp
->fr_line
;
18250 buf
= write_insn (buf
, insn
);
18252 if (mips_opts
.isa
== ISA_MIPS1
)
18254 buf
= write_insn (buf
, 0);
18256 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18257 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18258 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18260 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18261 FALSE
, BFD_RELOC_LO16
);
18262 fixp
->fx_file
= fragp
->fr_file
;
18263 fixp
->fx_line
= fragp
->fr_line
;
18265 buf
= write_insn (buf
, insn
);
18268 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18272 insn
|= at
<< OP_SH_RS
;
18274 buf
= write_insn (buf
, insn
);
18278 fragp
->fr_fix
+= fragp
->fr_var
;
18279 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18283 /* Relax microMIPS branches. */
18284 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18286 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18287 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18288 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18289 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18290 bfd_boolean short_ds
;
18291 unsigned long insn
;
18295 exp
.X_op
= O_symbol
;
18296 exp
.X_add_symbol
= fragp
->fr_symbol
;
18297 exp
.X_add_number
= fragp
->fr_offset
;
18299 fragp
->fr_fix
+= fragp
->fr_var
;
18301 /* Handle 16-bit branches that fit or are forced to fit. */
18302 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18304 /* We generate a fixup instead of applying it right now,
18305 because if there is linker relaxation, we're going to
18306 need the relocations. */
18308 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18309 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18310 else if (type
== 'E')
18311 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18312 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18316 fixp
->fx_file
= fragp
->fr_file
;
18317 fixp
->fx_line
= fragp
->fr_line
;
18319 /* These relocations can have an addend that won't fit in
18321 fixp
->fx_no_overflow
= 1;
18326 /* Handle 32-bit branches that fit or are forced to fit. */
18327 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18328 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18330 /* We generate a fixup instead of applying it right now,
18331 because if there is linker relaxation, we're going to
18332 need the relocations. */
18333 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18334 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18335 fixp
->fx_file
= fragp
->fr_file
;
18336 fixp
->fx_line
= fragp
->fr_line
;
18342 /* Relax 16-bit branches to 32-bit branches. */
18345 insn
= read_compressed_insn (buf
, 2);
18347 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18348 insn
= 0x94000000; /* beq */
18349 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18351 unsigned long regno
;
18353 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18354 regno
= micromips_to_32_reg_d_map
[regno
];
18355 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18356 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18361 /* Nothing else to do, just write it out. */
18362 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18363 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18365 buf
= write_compressed_insn (buf
, insn
, 4);
18366 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18371 insn
= read_compressed_insn (buf
, 4);
18373 /* Relax 32-bit branches to a sequence of instructions. */
18374 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18375 _("Relaxed out-of-range branch into a jump"));
18377 /* Set the short-delay-slot bit. */
18378 short_ds
= al
&& (insn
& 0x02000000) != 0;
18380 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18384 /* Reverse the branch. */
18385 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18386 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18387 insn
^= 0x20000000;
18388 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18389 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18390 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18391 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18392 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18393 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18394 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18395 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18396 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18397 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18398 insn
^= 0x00400000;
18399 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18400 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18401 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18402 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18403 insn
^= 0x00200000;
18409 /* Clear the and-link and short-delay-slot bits. */
18410 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18412 /* bltzal 0x40200000 bgezal 0x40600000 */
18413 /* bltzals 0x42200000 bgezals 0x42600000 */
18414 insn
&= ~0x02200000;
18417 /* Make a label at the end for use with the branch. */
18418 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18419 micromips_label_inc ();
18420 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18422 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18426 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18427 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18428 fixp
->fx_file
= fragp
->fr_file
;
18429 fixp
->fx_line
= fragp
->fr_line
;
18431 /* Branch over the jump. */
18432 buf
= write_compressed_insn (buf
, insn
, 4);
18435 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18438 if (mips_pic
== NO_PIC
)
18440 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18442 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18443 insn
= al
? jal
: 0xd4000000;
18445 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18446 BFD_RELOC_MICROMIPS_JMP
);
18447 fixp
->fx_file
= fragp
->fr_file
;
18448 fixp
->fx_line
= fragp
->fr_line
;
18450 buf
= write_compressed_insn (buf
, insn
, 4);
18453 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18457 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18458 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18459 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18461 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18462 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18463 insn
|= at
<< MICROMIPSOP_SH_RT
;
18465 if (exp
.X_add_number
)
18467 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18468 exp
.X_add_number
= 0;
18471 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18472 BFD_RELOC_MICROMIPS_GOT16
);
18473 fixp
->fx_file
= fragp
->fr_file
;
18474 fixp
->fx_line
= fragp
->fr_line
;
18476 buf
= write_compressed_insn (buf
, insn
, 4);
18478 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18479 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18480 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18482 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18483 BFD_RELOC_MICROMIPS_LO16
);
18484 fixp
->fx_file
= fragp
->fr_file
;
18485 fixp
->fx_line
= fragp
->fr_line
;
18487 buf
= write_compressed_insn (buf
, insn
, 4);
18489 /* jr/jrc/jalr/jalrs $at */
18490 insn
= al
? jalr
: jr
;
18491 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18493 buf
= write_compressed_insn (buf
, insn
, 2);
18496 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18500 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18503 const struct mips16_immed_operand
*op
;
18506 unsigned int user_length
, length
;
18507 unsigned long insn
;
18510 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18511 op
= mips16_immed_operands
;
18512 while (op
->type
!= type
)
18515 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18516 val
= resolve_symbol_value (fragp
->fr_symbol
);
18521 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18523 /* The rules for the base address of a PC relative reloc are
18524 complicated; see mips16_extended_frag. */
18525 if (type
== 'p' || type
== 'q')
18530 /* Ignore the low bit in the target, since it will be
18531 set for a text label. */
18532 if ((val
& 1) != 0)
18535 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18537 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18540 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18543 /* Make sure the section winds up with the alignment we have
18546 record_alignment (asec
, op
->shift
);
18550 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18551 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18552 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18553 _("extended instruction in delay slot"));
18555 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18557 insn
= read_compressed_insn (buf
, 2);
18559 insn
|= MIPS16_EXTEND
;
18561 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18563 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18568 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18569 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18571 length
= (ext
? 4 : 2);
18572 gas_assert (mips16_opcode_length (insn
) == length
);
18573 write_compressed_insn (buf
, insn
, length
);
18574 fragp
->fr_fix
+= length
;
18578 relax_substateT subtype
= fragp
->fr_subtype
;
18579 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18580 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18584 first
= RELAX_FIRST (subtype
);
18585 second
= RELAX_SECOND (subtype
);
18586 fixp
= (fixS
*) fragp
->fr_opcode
;
18588 /* If the delay slot chosen does not match the size of the instruction,
18589 then emit a warning. */
18590 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18591 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18596 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18597 | RELAX_DELAY_SLOT_SIZE_FIRST
18598 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18599 msg
= macro_warning (s
);
18601 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18605 /* Possibly emit a warning if we've chosen the longer option. */
18606 if (use_second
== second_longer
)
18612 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18613 msg
= macro_warning (s
);
18615 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18619 /* Go through all the fixups for the first sequence. Disable them
18620 (by marking them as done) if we're going to use the second
18621 sequence instead. */
18623 && fixp
->fx_frag
== fragp
18624 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18626 if (subtype
& RELAX_USE_SECOND
)
18628 fixp
= fixp
->fx_next
;
18631 /* Go through the fixups for the second sequence. Disable them if
18632 we're going to use the first sequence, otherwise adjust their
18633 addresses to account for the relaxation. */
18634 while (fixp
&& fixp
->fx_frag
== fragp
)
18636 if (subtype
& RELAX_USE_SECOND
)
18637 fixp
->fx_where
-= first
;
18640 fixp
= fixp
->fx_next
;
18643 /* Now modify the frag contents. */
18644 if (subtype
& RELAX_USE_SECOND
)
18648 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18649 memmove (start
, start
+ first
, second
);
18650 fragp
->fr_fix
-= first
;
18653 fragp
->fr_fix
-= second
;
18659 /* This function is called after the relocs have been generated.
18660 We've been storing mips16 text labels as odd. Here we convert them
18661 back to even for the convenience of the debugger. */
18664 mips_frob_file_after_relocs (void)
18667 unsigned int count
, i
;
18672 syms
= bfd_get_outsymbols (stdoutput
);
18673 count
= bfd_get_symcount (stdoutput
);
18674 for (i
= 0; i
< count
; i
++, syms
++)
18675 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18676 && ((*syms
)->value
& 1) != 0)
18678 (*syms
)->value
&= ~1;
18679 /* If the symbol has an odd size, it was probably computed
18680 incorrectly, so adjust that as well. */
18681 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18682 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18688 /* This function is called whenever a label is defined, including fake
18689 labels instantiated off the dot special symbol. It is used when
18690 handling branch delays; if a branch has a label, we assume we cannot
18691 move it. This also bumps the value of the symbol by 1 in compressed
18695 mips_record_label (symbolS
*sym
)
18697 segment_info_type
*si
= seg_info (now_seg
);
18698 struct insn_label_list
*l
;
18700 if (free_insn_labels
== NULL
)
18701 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18704 l
= free_insn_labels
;
18705 free_insn_labels
= l
->next
;
18709 l
->next
= si
->label_list
;
18710 si
->label_list
= l
;
18713 /* This function is called as tc_frob_label() whenever a label is defined
18714 and adds a DWARF-2 record we only want for true labels. */
18717 mips_define_label (symbolS
*sym
)
18719 mips_record_label (sym
);
18721 dwarf2_emit_label (sym
);
18725 /* This function is called by tc_new_dot_label whenever a new dot symbol
18729 mips_add_dot_label (symbolS
*sym
)
18731 mips_record_label (sym
);
18732 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18733 mips_compressed_mark_label (sym
);
18736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18738 /* Some special processing for a MIPS ELF file. */
18741 mips_elf_final_processing (void)
18743 /* Write out the register information. */
18744 if (mips_abi
!= N64_ABI
)
18748 s
.ri_gprmask
= mips_gprmask
;
18749 s
.ri_cprmask
[0] = mips_cprmask
[0];
18750 s
.ri_cprmask
[1] = mips_cprmask
[1];
18751 s
.ri_cprmask
[2] = mips_cprmask
[2];
18752 s
.ri_cprmask
[3] = mips_cprmask
[3];
18753 /* The gp_value field is set by the MIPS ELF backend. */
18755 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18756 ((Elf32_External_RegInfo
*)
18757 mips_regmask_frag
));
18761 Elf64_Internal_RegInfo s
;
18763 s
.ri_gprmask
= mips_gprmask
;
18765 s
.ri_cprmask
[0] = mips_cprmask
[0];
18766 s
.ri_cprmask
[1] = mips_cprmask
[1];
18767 s
.ri_cprmask
[2] = mips_cprmask
[2];
18768 s
.ri_cprmask
[3] = mips_cprmask
[3];
18769 /* The gp_value field is set by the MIPS ELF backend. */
18771 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18772 ((Elf64_External_RegInfo
*)
18773 mips_regmask_frag
));
18776 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18777 sort of BFD interface for this. */
18778 if (mips_any_noreorder
)
18779 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18780 if (mips_pic
!= NO_PIC
)
18782 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18783 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18786 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18788 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18789 defined at present; this might need to change in future. */
18790 if (file_ase_mips16
)
18791 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18792 if (file_ase_micromips
)
18793 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18794 #if 0 /* XXX FIXME */
18795 if (file_ase_mips3d
)
18796 elf_elfheader (stdoutput
)->e_flags
|= ???;
18799 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18801 /* Set the MIPS ELF ABI flags. */
18802 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18803 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18804 else if (mips_abi
== O64_ABI
)
18805 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18806 else if (mips_abi
== EABI_ABI
)
18808 if (!file_mips_gp32
)
18809 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18811 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18813 else if (mips_abi
== N32_ABI
)
18814 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18816 /* Nothing to do for N64_ABI. */
18818 if (mips_32bitmode
)
18819 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18821 #if 0 /* XXX FIXME */
18822 /* 32 bit code with 64 bit FP registers. */
18823 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18824 elf_elfheader (stdoutput
)->e_flags
|= ???;
18828 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18830 typedef struct proc
{
18832 symbolS
*func_end_sym
;
18833 unsigned long reg_mask
;
18834 unsigned long reg_offset
;
18835 unsigned long fpreg_mask
;
18836 unsigned long fpreg_offset
;
18837 unsigned long frame_offset
;
18838 unsigned long frame_reg
;
18839 unsigned long pc_reg
;
18842 static procS cur_proc
;
18843 static procS
*cur_proc_ptr
;
18844 static int numprocs
;
18846 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18847 as "2", and a normal nop as "0". */
18849 #define NOP_OPCODE_MIPS 0
18850 #define NOP_OPCODE_MIPS16 1
18851 #define NOP_OPCODE_MICROMIPS 2
18854 mips_nop_opcode (void)
18856 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18857 return NOP_OPCODE_MICROMIPS
;
18858 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18859 return NOP_OPCODE_MIPS16
;
18861 return NOP_OPCODE_MIPS
;
18864 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18865 32-bit microMIPS NOPs here (if applicable). */
18868 mips_handle_align (fragS
*fragp
)
18872 int bytes
, size
, excess
;
18875 if (fragp
->fr_type
!= rs_align_code
)
18878 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18880 switch (nop_opcode
)
18882 case NOP_OPCODE_MICROMIPS
:
18883 opcode
= micromips_nop32_insn
.insn_opcode
;
18886 case NOP_OPCODE_MIPS16
:
18887 opcode
= mips16_nop_insn
.insn_opcode
;
18890 case NOP_OPCODE_MIPS
:
18892 opcode
= nop_insn
.insn_opcode
;
18897 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18898 excess
= bytes
% size
;
18900 /* Handle the leading part if we're not inserting a whole number of
18901 instructions, and make it the end of the fixed part of the frag.
18902 Try to fit in a short microMIPS NOP if applicable and possible,
18903 and use zeroes otherwise. */
18904 gas_assert (excess
< 4);
18905 fragp
->fr_fix
+= excess
;
18910 /* Fall through. */
18912 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18914 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18918 /* Fall through. */
18921 /* Fall through. */
18926 md_number_to_chars (p
, opcode
, size
);
18927 fragp
->fr_var
= size
;
18931 md_obj_begin (void)
18938 /* Check for premature end, nesting errors, etc. */
18940 as_warn (_("missing .end at end of assembly"));
18949 if (*input_line_pointer
== '-')
18951 ++input_line_pointer
;
18954 if (!ISDIGIT (*input_line_pointer
))
18955 as_bad (_("expected simple number"));
18956 if (input_line_pointer
[0] == '0')
18958 if (input_line_pointer
[1] == 'x')
18960 input_line_pointer
+= 2;
18961 while (ISXDIGIT (*input_line_pointer
))
18964 val
|= hex_value (*input_line_pointer
++);
18966 return negative
? -val
: val
;
18970 ++input_line_pointer
;
18971 while (ISDIGIT (*input_line_pointer
))
18974 val
|= *input_line_pointer
++ - '0';
18976 return negative
? -val
: val
;
18979 if (!ISDIGIT (*input_line_pointer
))
18981 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18982 *input_line_pointer
, *input_line_pointer
);
18983 as_warn (_("invalid number"));
18986 while (ISDIGIT (*input_line_pointer
))
18989 val
+= *input_line_pointer
++ - '0';
18991 return negative
? -val
: val
;
18994 /* The .file directive; just like the usual .file directive, but there
18995 is an initial number which is the ECOFF file index. In the non-ECOFF
18996 case .file implies DWARF-2. */
18999 s_mips_file (int x ATTRIBUTE_UNUSED
)
19001 static int first_file_directive
= 0;
19003 if (ECOFF_DEBUGGING
)
19012 filename
= dwarf2_directive_file (0);
19014 /* Versions of GCC up to 3.1 start files with a ".file"
19015 directive even for stabs output. Make sure that this
19016 ".file" is handled. Note that you need a version of GCC
19017 after 3.1 in order to support DWARF-2 on MIPS. */
19018 if (filename
!= NULL
&& ! first_file_directive
)
19020 (void) new_logical_line (filename
, -1);
19021 s_app_file_string (filename
, 0);
19023 first_file_directive
= 1;
19027 /* The .loc directive, implying DWARF-2. */
19030 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19032 if (!ECOFF_DEBUGGING
)
19033 dwarf2_directive_loc (0);
19036 /* The .end directive. */
19039 s_mips_end (int x ATTRIBUTE_UNUSED
)
19043 /* Following functions need their own .frame and .cprestore directives. */
19044 mips_frame_reg_valid
= 0;
19045 mips_cprestore_valid
= 0;
19047 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19050 demand_empty_rest_of_line ();
19055 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19056 as_warn (_(".end not in text section"));
19060 as_warn (_(".end directive without a preceding .ent directive."));
19061 demand_empty_rest_of_line ();
19067 gas_assert (S_GET_NAME (p
));
19068 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19069 as_warn (_(".end symbol does not match .ent symbol."));
19071 if (debug_type
== DEBUG_STABS
)
19072 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19076 as_warn (_(".end directive missing or unknown symbol"));
19079 /* Create an expression to calculate the size of the function. */
19080 if (p
&& cur_proc_ptr
)
19082 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19083 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19086 exp
->X_op
= O_subtract
;
19087 exp
->X_add_symbol
= symbol_temp_new_now ();
19088 exp
->X_op_symbol
= p
;
19089 exp
->X_add_number
= 0;
19091 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19094 /* Generate a .pdr section. */
19095 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
19097 segT saved_seg
= now_seg
;
19098 subsegT saved_subseg
= now_subseg
;
19102 #ifdef md_flush_pending_output
19103 md_flush_pending_output ();
19106 gas_assert (pdr_seg
);
19107 subseg_set (pdr_seg
, 0);
19109 /* Write the symbol. */
19110 exp
.X_op
= O_symbol
;
19111 exp
.X_add_symbol
= p
;
19112 exp
.X_add_number
= 0;
19113 emit_expr (&exp
, 4);
19115 fragp
= frag_more (7 * 4);
19117 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19118 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19119 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19120 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19121 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19122 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19123 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19125 subseg_set (saved_seg
, saved_subseg
);
19127 #endif /* OBJ_ELF */
19129 cur_proc_ptr
= NULL
;
19132 /* The .aent and .ent directives. */
19135 s_mips_ent (int aent
)
19139 symbolP
= get_symbol ();
19140 if (*input_line_pointer
== ',')
19141 ++input_line_pointer
;
19142 SKIP_WHITESPACE ();
19143 if (ISDIGIT (*input_line_pointer
)
19144 || *input_line_pointer
== '-')
19147 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19148 as_warn (_(".ent or .aent not in text section."));
19150 if (!aent
&& cur_proc_ptr
)
19151 as_warn (_("missing .end"));
19155 /* This function needs its own .frame and .cprestore directives. */
19156 mips_frame_reg_valid
= 0;
19157 mips_cprestore_valid
= 0;
19159 cur_proc_ptr
= &cur_proc
;
19160 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19162 cur_proc_ptr
->func_sym
= symbolP
;
19166 if (debug_type
== DEBUG_STABS
)
19167 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19168 S_GET_NAME (symbolP
));
19171 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19173 demand_empty_rest_of_line ();
19176 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19177 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19178 s_mips_frame is used so that we can set the PDR information correctly.
19179 We can't use the ecoff routines because they make reference to the ecoff
19180 symbol table (in the mdebug section). */
19183 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19186 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19190 if (cur_proc_ptr
== (procS
*) NULL
)
19192 as_warn (_(".frame outside of .ent"));
19193 demand_empty_rest_of_line ();
19197 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19199 SKIP_WHITESPACE ();
19200 if (*input_line_pointer
++ != ','
19201 || get_absolute_expression_and_terminator (&val
) != ',')
19203 as_warn (_("Bad .frame directive"));
19204 --input_line_pointer
;
19205 demand_empty_rest_of_line ();
19209 cur_proc_ptr
->frame_offset
= val
;
19210 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19212 demand_empty_rest_of_line ();
19215 #endif /* OBJ_ELF */
19219 /* The .fmask and .mask directives. If the mdebug section is present
19220 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19221 embedded targets, s_mips_mask is used so that we can set the PDR
19222 information correctly. We can't use the ecoff routines because they
19223 make reference to the ecoff symbol table (in the mdebug section). */
19226 s_mips_mask (int reg_type
)
19229 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19233 if (cur_proc_ptr
== (procS
*) NULL
)
19235 as_warn (_(".mask/.fmask outside of .ent"));
19236 demand_empty_rest_of_line ();
19240 if (get_absolute_expression_and_terminator (&mask
) != ',')
19242 as_warn (_("Bad .mask/.fmask directive"));
19243 --input_line_pointer
;
19244 demand_empty_rest_of_line ();
19248 off
= get_absolute_expression ();
19250 if (reg_type
== 'F')
19252 cur_proc_ptr
->fpreg_mask
= mask
;
19253 cur_proc_ptr
->fpreg_offset
= off
;
19257 cur_proc_ptr
->reg_mask
= mask
;
19258 cur_proc_ptr
->reg_offset
= off
;
19261 demand_empty_rest_of_line ();
19264 #endif /* OBJ_ELF */
19265 s_ignore (reg_type
);
19268 /* A table describing all the processors gas knows about. Names are
19269 matched in the order listed.
19271 To ease comparison, please keep this table in the same order as
19272 gcc's mips_cpu_info_table[]. */
19273 static const struct mips_cpu_info mips_cpu_info_table
[] =
19275 /* Entries for generic ISAs */
19276 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19277 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19278 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19279 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19280 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19281 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19282 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19283 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19284 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19287 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19288 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19289 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19292 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19295 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19296 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19297 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19298 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19299 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19300 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19301 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19302 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19303 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19304 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19305 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19306 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19307 { "r5900", 0, ISA_MIPS3
, CPU_R5900
},
19308 /* ST Microelectronics Loongson 2E and 2F cores */
19309 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19310 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19313 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19314 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19315 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19316 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19317 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19318 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19319 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19320 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19321 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19322 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19323 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19324 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19325 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19326 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19327 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19330 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19331 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19332 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19333 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19335 /* MIPS 32 Release 2 */
19336 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19337 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19338 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19339 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19340 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19341 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19342 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19343 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19344 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19345 ISA_MIPS32R2
, CPU_MIPS32R2
},
19346 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19347 ISA_MIPS32R2
, CPU_MIPS32R2
},
19348 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19349 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19350 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19351 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19352 /* Deprecated forms of the above. */
19353 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19354 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19355 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19356 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19357 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19358 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19359 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19360 /* Deprecated forms of the above. */
19361 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19362 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19363 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19364 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19365 ISA_MIPS32R2
, CPU_MIPS32R2
},
19366 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19367 ISA_MIPS32R2
, CPU_MIPS32R2
},
19368 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19369 ISA_MIPS32R2
, CPU_MIPS32R2
},
19370 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19371 ISA_MIPS32R2
, CPU_MIPS32R2
},
19372 /* Deprecated forms of the above. */
19373 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19374 ISA_MIPS32R2
, CPU_MIPS32R2
},
19375 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19376 ISA_MIPS32R2
, CPU_MIPS32R2
},
19377 /* 34Kn is a 34kc without DSP. */
19378 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19379 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19380 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19381 ISA_MIPS32R2
, CPU_MIPS32R2
},
19382 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19383 ISA_MIPS32R2
, CPU_MIPS32R2
},
19384 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19385 ISA_MIPS32R2
, CPU_MIPS32R2
},
19386 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19387 ISA_MIPS32R2
, CPU_MIPS32R2
},
19388 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19389 ISA_MIPS32R2
, CPU_MIPS32R2
},
19390 /* Deprecated forms of the above. */
19391 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19392 ISA_MIPS32R2
, CPU_MIPS32R2
},
19393 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19394 ISA_MIPS32R2
, CPU_MIPS32R2
},
19395 /* 1004K cores are multiprocessor versions of the 34K. */
19396 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19397 ISA_MIPS32R2
, CPU_MIPS32R2
},
19398 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19399 ISA_MIPS32R2
, CPU_MIPS32R2
},
19400 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19401 ISA_MIPS32R2
, CPU_MIPS32R2
},
19402 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19403 ISA_MIPS32R2
, CPU_MIPS32R2
},
19406 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19407 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19408 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19409 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19411 /* Broadcom SB-1 CPU core */
19412 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19413 ISA_MIPS64
, CPU_SB1
},
19414 /* Broadcom SB-1A CPU core */
19415 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19416 ISA_MIPS64
, CPU_SB1
},
19418 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19420 /* MIPS 64 Release 2 */
19422 /* Cavium Networks Octeon CPU core */
19423 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19424 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19425 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19428 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19431 XLP is mostly like XLR, with the prominent exception that it is
19432 MIPS64R2 rather than MIPS64. */
19433 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19440 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19441 with a final "000" replaced by "k". Ignore case.
19443 Note: this function is shared between GCC and GAS. */
19446 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19448 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19449 given
++, canonical
++;
19451 return ((*given
== 0 && *canonical
== 0)
19452 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19456 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19457 CPU name. We've traditionally allowed a lot of variation here.
19459 Note: this function is shared between GCC and GAS. */
19462 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19464 /* First see if the name matches exactly, or with a final "000"
19465 turned into "k". */
19466 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19469 /* If not, try comparing based on numerical designation alone.
19470 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19471 if (TOLOWER (*given
) == 'r')
19473 if (!ISDIGIT (*given
))
19476 /* Skip over some well-known prefixes in the canonical name,
19477 hoping to find a number there too. */
19478 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19480 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19482 else if (TOLOWER (canonical
[0]) == 'r')
19485 return mips_strict_matching_cpu_name_p (canonical
, given
);
19489 /* Parse an option that takes the name of a processor as its argument.
19490 OPTION is the name of the option and CPU_STRING is the argument.
19491 Return the corresponding processor enumeration if the CPU_STRING is
19492 recognized, otherwise report an error and return null.
19494 A similar function exists in GCC. */
19496 static const struct mips_cpu_info
*
19497 mips_parse_cpu (const char *option
, const char *cpu_string
)
19499 const struct mips_cpu_info
*p
;
19501 /* 'from-abi' selects the most compatible architecture for the given
19502 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19503 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19504 version. Look first at the -mgp options, if given, otherwise base
19505 the choice on MIPS_DEFAULT_64BIT.
19507 Treat NO_ABI like the EABIs. One reason to do this is that the
19508 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19509 architecture. This code picks MIPS I for 'mips' and MIPS III for
19510 'mips64', just as we did in the days before 'from-abi'. */
19511 if (strcasecmp (cpu_string
, "from-abi") == 0)
19513 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19514 return mips_cpu_info_from_isa (ISA_MIPS1
);
19516 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19517 return mips_cpu_info_from_isa (ISA_MIPS3
);
19519 if (file_mips_gp32
>= 0)
19520 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19522 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19527 /* 'default' has traditionally been a no-op. Probably not very useful. */
19528 if (strcasecmp (cpu_string
, "default") == 0)
19531 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19532 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19535 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19539 /* Return the canonical processor information for ISA (a member of the
19540 ISA_MIPS* enumeration). */
19542 static const struct mips_cpu_info
*
19543 mips_cpu_info_from_isa (int isa
)
19547 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19548 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19549 && isa
== mips_cpu_info_table
[i
].isa
)
19550 return (&mips_cpu_info_table
[i
]);
19555 static const struct mips_cpu_info
*
19556 mips_cpu_info_from_arch (int arch
)
19560 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19561 if (arch
== mips_cpu_info_table
[i
].cpu
)
19562 return (&mips_cpu_info_table
[i
]);
19568 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19572 fprintf (stream
, "%24s", "");
19577 fprintf (stream
, ", ");
19581 if (*col_p
+ strlen (string
) > 72)
19583 fprintf (stream
, "\n%24s", "");
19587 fprintf (stream
, "%s", string
);
19588 *col_p
+= strlen (string
);
19594 md_show_usage (FILE *stream
)
19599 fprintf (stream
, _("\
19601 -EB generate big endian output\n\
19602 -EL generate little endian output\n\
19603 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19604 -G NUM allow referencing objects up to NUM bytes\n\
19605 implicitly with the gp register [default 8]\n"));
19606 fprintf (stream
, _("\
19607 -mips1 generate MIPS ISA I instructions\n\
19608 -mips2 generate MIPS ISA II instructions\n\
19609 -mips3 generate MIPS ISA III instructions\n\
19610 -mips4 generate MIPS ISA IV instructions\n\
19611 -mips5 generate MIPS ISA V instructions\n\
19612 -mips32 generate MIPS32 ISA instructions\n\
19613 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19614 -mips64 generate MIPS64 ISA instructions\n\
19615 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19616 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19620 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19621 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19622 show (stream
, "from-abi", &column
, &first
);
19623 fputc ('\n', stream
);
19625 fprintf (stream
, _("\
19626 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19627 -no-mCPU don't generate code specific to CPU.\n\
19628 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19632 show (stream
, "3900", &column
, &first
);
19633 show (stream
, "4010", &column
, &first
);
19634 show (stream
, "4100", &column
, &first
);
19635 show (stream
, "4650", &column
, &first
);
19636 fputc ('\n', stream
);
19638 fprintf (stream
, _("\
19639 -mips16 generate mips16 instructions\n\
19640 -no-mips16 do not generate mips16 instructions\n"));
19641 fprintf (stream
, _("\
19642 -mmicromips generate microMIPS instructions\n\
19643 -mno-micromips do not generate microMIPS instructions\n"));
19644 fprintf (stream
, _("\
19645 -msmartmips generate smartmips instructions\n\
19646 -mno-smartmips do not generate smartmips instructions\n"));
19647 fprintf (stream
, _("\
19648 -mdsp generate DSP instructions\n\
19649 -mno-dsp do not generate DSP instructions\n"));
19650 fprintf (stream
, _("\
19651 -mdspr2 generate DSP R2 instructions\n\
19652 -mno-dspr2 do not generate DSP R2 instructions\n"));
19653 fprintf (stream
, _("\
19654 -mmt generate MT instructions\n\
19655 -mno-mt do not generate MT instructions\n"));
19656 fprintf (stream
, _("\
19657 -mmcu generate MCU instructions\n\
19658 -mno-mcu do not generate MCU instructions\n"));
19659 fprintf (stream
, _("\
19660 -mvirt generate Virtualization instructions\n\
19661 -mno-virt do not generate Virtualization instructions\n"));
19662 fprintf (stream
, _("\
19663 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19664 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19665 -mfix-vr4120 work around certain VR4120 errata\n\
19666 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19667 -mfix-24k insert a nop after ERET and DERET instructions\n\
19668 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19669 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19670 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19671 -msym32 assume all symbols have 32-bit values\n\
19672 -O0 remove unneeded NOPs, do not swap branches\n\
19673 -O remove unneeded NOPs and swap branches\n\
19674 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19675 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19676 fprintf (stream
, _("\
19677 -mhard-float allow floating-point instructions\n\
19678 -msoft-float do not allow floating-point instructions\n\
19679 -msingle-float only allow 32-bit floating-point operations\n\
19680 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19681 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19684 fprintf (stream
, _("\
19685 -KPIC, -call_shared generate SVR4 position independent code\n\
19686 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19687 -mvxworks-pic generate VxWorks position independent code\n\
19688 -non_shared do not generate code that can operate with DSOs\n\
19689 -xgot assume a 32 bit GOT\n\
19690 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19691 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19692 position dependent (non shared) code\n\
19693 -mabi=ABI create ABI conformant object file for:\n"));
19697 show (stream
, "32", &column
, &first
);
19698 show (stream
, "o64", &column
, &first
);
19699 show (stream
, "n32", &column
, &first
);
19700 show (stream
, "64", &column
, &first
);
19701 show (stream
, "eabi", &column
, &first
);
19703 fputc ('\n', stream
);
19705 fprintf (stream
, _("\
19706 -32 create o32 ABI object file (default)\n\
19707 -n32 create n32 ABI object file\n\
19708 -64 create 64 ABI object file\n"));
19714 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19716 if (HAVE_64BIT_SYMBOLS
)
19717 return dwarf2_format_64bit_irix
;
19719 return dwarf2_format_32bit
;
19724 mips_dwarf2_addr_size (void)
19726 if (HAVE_64BIT_OBJECTS
)
19732 /* Standard calling conventions leave the CFA at SP on entry. */
19734 mips_cfi_frame_initial_instructions (void)
19736 cfi_add_CFA_def_cfa_register (SP
);
19740 tc_mips_regname_to_dw2regnum (char *regname
)
19742 unsigned int regnum
= -1;
19745 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))