1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_elf_flavour
:
122 return (target_big_endian
123 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
124 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
131 /* The name of the readonly data section. */
132 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
134 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
136 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
140 /* This is the set of options which may be modified by the .set
141 pseudo-op. We use a struct so that .set push and .set pop are more
144 struct mips_set_options
146 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
147 if it has not been initialized. Changed by `.set mipsN', and the
148 -mipsN command line option, and the default CPU. */
150 /* Whether we are assembling for the mips16 processor. 0 if we are
151 not, 1 if we are, and -1 if the value has not been initialized.
152 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
153 -nomips16 command line options, and the default CPU. */
155 /* Non-zero if we should not reorder instructions. Changed by `.set
156 reorder' and `.set noreorder'. */
158 /* Non-zero if we should not permit the $at ($1) register to be used
159 in instructions. Changed by `.set at' and `.set noat'. */
161 /* Non-zero if we should warn when a macro instruction expands into
162 more than one machine instruction. Changed by `.set nomacro' and
164 int warn_about_macros
;
165 /* Non-zero if we should not move instructions. Changed by `.set
166 move', `.set volatile', `.set nomove', and `.set novolatile'. */
168 /* Non-zero if we should not optimize branches by moving the target
169 of the branch into the delay slot. Actually, we don't perform
170 this optimization anyhow. Changed by `.set bopt' and `.set
173 /* Non-zero if we should not autoextend mips16 instructions.
174 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* This is the struct we use to hold the current set of options. Note
179 that we must set the isa and mips16 fields to -1 to indicate that
180 they have not been initialized. */
182 static struct mips_set_options mips_opts
= { -1, -1 };
184 /* These variables are filled in with the masks of registers used.
185 The object format code reads them and puts them in the appropriate
187 unsigned long mips_gprmask
;
188 unsigned long mips_cprmask
[4];
190 /* MIPS ISA we are using for this output file. */
191 static int file_mips_isa
;
193 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
194 static int mips_cpu
= -1;
196 /* The argument of the -mabi= flag. */
197 static char* mips_abi_string
= 0;
199 /* Wether we should mark the file EABI64 or EABI32. */
200 static int mips_eabi64
= 0;
202 /* If they asked for mips1 or mips2 and a cpu that is
203 mips3 or greater, then mark the object file 32BITMODE. */
204 static int mips_32bitmode
= 0;
206 /* True if -mgp32 was passed. */
207 static int mips_gp32
= 0;
209 /* Some ISA's have delay slots for instructions which read or write
210 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
211 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
212 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
213 delay slot in this ISA. The uses of this macro assume that any
214 ISA that has delay slots for one of these, has them for all. They
215 also assume that ISAs which don't have delays for these insns, don't
216 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
217 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
223 /* Return true if ISA supports 64 bit gp register instructions. */
224 #define ISA_HAS_64BIT_REGS(ISA) ( \
229 /* Whether the processor uses hardware interlocks to protect
230 reads from the HI and LO registers, and thus does not
231 require nops to be inserted.
233 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
234 -mcpu=FOO schedules for FOO, but still produces code that meets the
235 requirements of MIPS ISA I. For example, it won't generate any
236 FOO-specific instructions, and it will still assume that any
237 scheduling hazards described in MIPS ISA I are there, even if FOO
238 has interlocks. -mFOO gives GCC permission to generate code that
239 will only run on a FOO; it will generate FOO-specific instructions,
240 and assume interlocks provided by a FOO.
242 However, GAS currently doesn't make this distinction; before Jan 28
243 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
244 assumptions. The GCC driver passes these flags through to GAS, so
245 if GAS actually does anything that doesn't meet MIPS ISA I with
246 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
248 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
249 which seems senseless --- why generate code which will only run on
250 a FOO, but schedule for something else?
252 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
254 -- Jim Blandy <jimb@cygnus.com> */
256 #define hilo_interlocks (mips_cpu == 4010 \
259 /* Whether the processor uses hardware interlocks to protect reads
260 from the GPRs, and thus does not require nops to be inserted. */
261 #define gpr_interlocks \
262 (mips_opts.isa != 1 \
265 /* As with other "interlocks" this is used by hardware that has FP
266 (co-processor) interlocks. */
267 /* Itbl support may require additional care here. */
268 #define cop_interlocks (mips_cpu == 4300 \
271 /* Is this a mfhi or mflo instruction? */
272 #define MF_HILO_INSN(PINFO) \
273 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
275 /* MIPS PIC level. */
279 /* Do not generate PIC code. */
282 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
283 not sure what it is supposed to do. */
286 /* Generate PIC code as in the SVR4 MIPS ABI. */
289 /* Generate PIC code without using a global offset table: the data
290 segment has a maximum size of 64K, all data references are off
291 the $gp register, and all text references are PC relative. This
292 is used on some embedded systems. */
296 static enum mips_pic_level mips_pic
;
298 /* 1 if we should generate 32 bit offsets from the GP register in
299 SVR4_PIC mode. Currently has no meaning in other modes. */
300 static int mips_big_got
;
302 /* 1 if trap instructions should used for overflow rather than break
304 static int mips_trap
;
306 /* Non-zero if any .set noreorder directives were used. */
308 static int mips_any_noreorder
;
310 /* Non-zero if nops should be inserted when the register referenced in
311 an mfhi/mflo instruction is read in the next two instructions. */
312 static int mips_7000_hilo_fix
;
314 /* The size of the small data section. */
315 static int g_switch_value
= 8;
316 /* Whether the -G option was used. */
317 static int g_switch_seen
= 0;
322 /* If we can determine in advance that GP optimization won't be
323 possible, we can skip the relaxation stuff that tries to produce
324 GP-relative references. This makes delay slot optimization work
327 This function can only provide a guess, but it seems to work for
328 gcc output. It needs to guess right for gcc, otherwise gcc
329 will put what it thinks is a GP-relative instruction in a branch
332 I don't know if a fix is needed for the SVR4_PIC mode. I've only
333 fixed it for the non-PIC mode. KR 95/04/07 */
334 static int nopic_need_relax
PARAMS ((symbolS
*, int));
336 /* handle of the OPCODE hash table */
337 static struct hash_control
*op_hash
= NULL
;
339 /* The opcode hash table we use for the mips16. */
340 static struct hash_control
*mips16_op_hash
= NULL
;
342 /* This array holds the chars that always start a comment. If the
343 pre-processor is disabled, these aren't very useful */
344 const char comment_chars
[] = "#";
346 /* This array holds the chars that only start a comment at the beginning of
347 a line. If the line seems to have the form '# 123 filename'
348 .line and .file directives will appear in the pre-processed output */
349 /* Note that input_file.c hand checks for '#' at the beginning of the
350 first line of the input file. This is because the compiler outputs
351 #NO_APP at the beginning of its output. */
352 /* Also note that C style comments are always supported. */
353 const char line_comment_chars
[] = "#";
355 /* This array holds machine specific line separator characters. */
356 const char line_separator_chars
[] = "";
358 /* Chars that can be used to separate mant from exp in floating point nums */
359 const char EXP_CHARS
[] = "eE";
361 /* Chars that mean this number is a floating point constant */
364 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
366 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
367 changed in read.c . Ideally it shouldn't have to know about it at all,
368 but nothing is ideal around here.
371 static char *insn_error
;
373 static int auto_align
= 1;
375 /* When outputting SVR4 PIC code, the assembler needs to know the
376 offset in the stack frame from which to restore the $gp register.
377 This is set by the .cprestore pseudo-op, and saved in this
379 static offsetT mips_cprestore_offset
= -1;
381 /* This is the register which holds the stack frame, as set by the
382 .frame pseudo-op. This is needed to implement .cprestore. */
383 static int mips_frame_reg
= SP
;
385 /* To output NOP instructions correctly, we need to keep information
386 about the previous two instructions. */
388 /* Whether we are optimizing. The default value of 2 means to remove
389 unneeded NOPs and swap branch instructions when possible. A value
390 of 1 means to not swap branches. A value of 0 means to always
392 static int mips_optimize
= 2;
394 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
395 equivalent to seeing no -g option at all. */
396 static int mips_debug
= 0;
398 /* The previous instruction. */
399 static struct mips_cl_insn prev_insn
;
401 /* The instruction before prev_insn. */
402 static struct mips_cl_insn prev_prev_insn
;
404 /* If we don't want information for prev_insn or prev_prev_insn, we
405 point the insn_mo field at this dummy integer. */
406 static const struct mips_opcode dummy_opcode
= { 0 };
408 /* Non-zero if prev_insn is valid. */
409 static int prev_insn_valid
;
411 /* The frag for the previous instruction. */
412 static struct frag
*prev_insn_frag
;
414 /* The offset into prev_insn_frag for the previous instruction. */
415 static long prev_insn_where
;
417 /* The reloc type for the previous instruction, if any. */
418 static bfd_reloc_code_real_type prev_insn_reloc_type
;
420 /* The reloc for the previous instruction, if any. */
421 static fixS
*prev_insn_fixp
;
423 /* Non-zero if the previous instruction was in a delay slot. */
424 static int prev_insn_is_delay_slot
;
426 /* Non-zero if the previous instruction was in a .set noreorder. */
427 static int prev_insn_unreordered
;
429 /* Non-zero if the previous instruction uses an extend opcode (if
431 static int prev_insn_extended
;
433 /* Non-zero if the previous previous instruction was in a .set
435 static int prev_prev_insn_unreordered
;
437 /* If this is set, it points to a frag holding nop instructions which
438 were inserted before the start of a noreorder section. If those
439 nops turn out to be unnecessary, the size of the frag can be
441 static fragS
*prev_nop_frag
;
443 /* The number of nop instructions we created in prev_nop_frag. */
444 static int prev_nop_frag_holds
;
446 /* The number of nop instructions that we know we need in
448 static int prev_nop_frag_required
;
450 /* The number of instructions we've seen since prev_nop_frag. */
451 static int prev_nop_frag_since
;
453 /* For ECOFF and ELF, relocations against symbols are done in two
454 parts, with a HI relocation and a LO relocation. Each relocation
455 has only 16 bits of space to store an addend. This means that in
456 order for the linker to handle carries correctly, it must be able
457 to locate both the HI and the LO relocation. This means that the
458 relocations must appear in order in the relocation table.
460 In order to implement this, we keep track of each unmatched HI
461 relocation. We then sort them so that they immediately precede the
462 corresponding LO relocation. */
467 struct mips_hi_fixup
*next
;
470 /* The section this fixup is in. */
474 /* The list of unmatched HI relocs. */
476 static struct mips_hi_fixup
*mips_hi_fixup_list
;
478 /* Map normal MIPS register numbers to mips16 register numbers. */
480 #define X ILLEGAL_REG
481 static const int mips32_to_16_reg_map
[] =
483 X
, X
, 2, 3, 4, 5, 6, 7,
484 X
, X
, X
, X
, X
, X
, X
, X
,
485 0, 1, X
, X
, X
, X
, X
, X
,
486 X
, X
, X
, X
, X
, X
, X
, X
490 /* Map mips16 register numbers to normal MIPS register numbers. */
492 static const int mips16_to_32_reg_map
[] =
494 16, 17, 2, 3, 4, 5, 6, 7
497 /* Since the MIPS does not have multiple forms of PC relative
498 instructions, we do not have to do relaxing as is done on other
499 platforms. However, we do have to handle GP relative addressing
500 correctly, which turns out to be a similar problem.
502 Every macro that refers to a symbol can occur in (at least) two
503 forms, one with GP relative addressing and one without. For
504 example, loading a global variable into a register generally uses
505 a macro instruction like this:
507 If i can be addressed off the GP register (this is true if it is in
508 the .sbss or .sdata section, or if it is known to be smaller than
509 the -G argument) this will generate the following instruction:
511 This instruction will use a GPREL reloc. If i can not be addressed
512 off the GP register, the following instruction sequence will be used:
515 In this case the first instruction will have a HI16 reloc, and the
516 second reloc will have a LO16 reloc. Both relocs will be against
519 The issue here is that we may not know whether i is GP addressable
520 until after we see the instruction that uses it. Therefore, we
521 want to be able to choose the final instruction sequence only at
522 the end of the assembly. This is similar to the way other
523 platforms choose the size of a PC relative instruction only at the
526 When generating position independent code we do not use GP
527 addressing in quite the same way, but the issue still arises as
528 external symbols and local symbols must be handled differently.
530 We handle these issues by actually generating both possible
531 instruction sequences. The longer one is put in a frag_var with
532 type rs_machine_dependent. We encode what to do with the frag in
533 the subtype field. We encode (1) the number of existing bytes to
534 replace, (2) the number of new bytes to use, (3) the offset from
535 the start of the existing bytes to the first reloc we must generate
536 (that is, the offset is applied from the start of the existing
537 bytes after they are replaced by the new bytes, if any), (4) the
538 offset from the start of the existing bytes to the second reloc,
539 (5) whether a third reloc is needed (the third reloc is always four
540 bytes after the second reloc), and (6) whether to warn if this
541 variant is used (this is sometimes needed if .set nomacro or .set
542 noat is in effect). All these numbers are reasonably small.
544 Generating two instruction sequences must be handled carefully to
545 ensure that delay slots are handled correctly. Fortunately, there
546 are a limited number of cases. When the second instruction
547 sequence is generated, append_insn is directed to maintain the
548 existing delay slot information, so it continues to apply to any
549 code after the second instruction sequence. This means that the
550 second instruction sequence must not impose any requirements not
551 required by the first instruction sequence.
553 These variant frags are then handled in functions called by the
554 machine independent code. md_estimate_size_before_relax returns
555 the final size of the frag. md_convert_frag sets up the final form
556 of the frag. tc_gen_reloc adjust the first reloc and adds a second
558 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
562 | (((reloc1) + 64) << 9) \
563 | (((reloc2) + 64) << 2) \
564 | ((reloc3) ? (1 << 1) : 0) \
566 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
567 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
568 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
569 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
570 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
571 #define RELAX_WARN(i) ((i) & 1)
573 /* For mips16 code, we use an entirely different form of relaxation.
574 mips16 supports two versions of most instructions which take
575 immediate values: a small one which takes some small value, and a
576 larger one which takes a 16 bit value. Since branches also follow
577 this pattern, relaxing these values is required.
579 We can assemble both mips16 and normal MIPS code in a single
580 object. Therefore, we need to support this type of relaxation at
581 the same time that we support the relaxation described above. We
582 use the high bit of the subtype field to distinguish these cases.
584 The information we store for this type of relaxation is the
585 argument code found in the opcode file for this relocation, whether
586 the user explicitly requested a small or extended form, and whether
587 the relocation is in a jump or jal delay slot. That tells us the
588 size of the value, and how it should be stored. We also store
589 whether the fragment is considered to be extended or not. We also
590 store whether this is known to be a branch to a different section,
591 whether we have tried to relax this frag yet, and whether we have
592 ever extended a PC relative fragment because of a shift count. */
593 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
596 | ((small) ? 0x100 : 0) \
597 | ((ext) ? 0x200 : 0) \
598 | ((dslot) ? 0x400 : 0) \
599 | ((jal_dslot) ? 0x800 : 0))
600 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
601 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
602 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
603 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
604 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
605 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
606 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
607 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
608 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
609 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
610 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
611 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
613 /* Prototypes for static functions. */
616 #define internalError() \
617 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
619 #define internalError() as_fatal (_("MIPS internal Error"));
622 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
624 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
625 unsigned int reg
, enum mips_regclass
class));
626 static int reg_needs_delay
PARAMS ((int));
627 static void mips16_mark_labels
PARAMS ((void));
628 static void append_insn
PARAMS ((char *place
,
629 struct mips_cl_insn
* ip
,
631 bfd_reloc_code_real_type r
,
633 static void mips_no_prev_insn
PARAMS ((int));
634 static void mips_emit_delays
PARAMS ((boolean
));
636 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
637 const char *name
, const char *fmt
,
640 static void macro_build ();
642 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
643 const char *, const char *,
645 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
646 expressionS
* ep
, int regnum
));
647 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
648 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
650 static void load_register
PARAMS ((int *, int, expressionS
*, int));
651 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
652 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
653 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
654 #ifdef LOSING_COMPILER
655 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
657 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
658 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
659 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
660 boolean
, boolean
, unsigned long *,
661 boolean
*, unsigned short *));
662 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
663 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
664 static symbolS
*get_symbol
PARAMS ((void));
665 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
666 static void s_align
PARAMS ((int));
667 static void s_change_sec
PARAMS ((int));
668 static void s_cons
PARAMS ((int));
669 static void s_float_cons
PARAMS ((int));
670 static void s_mips_globl
PARAMS ((int));
671 static void s_option
PARAMS ((int));
672 static void s_mipsset
PARAMS ((int));
673 static void s_abicalls
PARAMS ((int));
674 static void s_cpload
PARAMS ((int));
675 static void s_cprestore
PARAMS ((int));
676 static void s_gpword
PARAMS ((int));
677 static void s_cpadd
PARAMS ((int));
678 static void s_insn
PARAMS ((int));
679 static void md_obj_begin
PARAMS ((void));
680 static void md_obj_end
PARAMS ((void));
681 static long get_number
PARAMS ((void));
682 static void s_mips_ent
PARAMS ((int));
683 static void s_mips_end
PARAMS ((int));
684 static void s_mips_frame
PARAMS ((int));
685 static void s_mips_mask
PARAMS ((int));
686 static void s_mips_stab
PARAMS ((int));
687 static void s_mips_weakext
PARAMS ((int));
688 static void s_file
PARAMS ((int));
689 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
692 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
696 The following pseudo-ops from the Kane and Heinrich MIPS book
697 should be defined here, but are currently unsupported: .alias,
698 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
700 The following pseudo-ops from the Kane and Heinrich MIPS book are
701 specific to the type of debugging information being generated, and
702 should be defined by the object format: .aent, .begin, .bend,
703 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
706 The following pseudo-ops from the Kane and Heinrich MIPS book are
707 not MIPS CPU specific, but are also not specific to the object file
708 format. This file is probably the best place to define them, but
709 they are not currently supported: .asm0, .endr, .lab, .repeat,
712 static const pseudo_typeS mips_pseudo_table
[] =
714 /* MIPS specific pseudo-ops. */
715 {"option", s_option
, 0},
716 {"set", s_mipsset
, 0},
717 {"rdata", s_change_sec
, 'r'},
718 {"sdata", s_change_sec
, 's'},
719 {"livereg", s_ignore
, 0},
720 {"abicalls", s_abicalls
, 0},
721 {"cpload", s_cpload
, 0},
722 {"cprestore", s_cprestore
, 0},
723 {"gpword", s_gpword
, 0},
724 {"cpadd", s_cpadd
, 0},
727 /* Relatively generic pseudo-ops that happen to be used on MIPS
729 {"asciiz", stringer
, 1},
730 {"bss", s_change_sec
, 'b'},
733 {"dword", s_cons
, 3},
734 {"weakext", s_mips_weakext
, 0},
736 /* These pseudo-ops are defined in read.c, but must be overridden
737 here for one reason or another. */
738 {"align", s_align
, 0},
740 {"data", s_change_sec
, 'd'},
741 {"double", s_float_cons
, 'd'},
742 {"float", s_float_cons
, 'f'},
743 {"globl", s_mips_globl
, 0},
744 {"global", s_mips_globl
, 0},
745 {"hword", s_cons
, 1},
750 {"short", s_cons
, 1},
751 {"single", s_float_cons
, 'f'},
752 {"stabn", s_mips_stab
, 'n'},
753 {"text", s_change_sec
, 't'},
758 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
759 /* These pseudo-ops should be defined by the object file format.
760 However, a.out doesn't support them, so we have versions here. */
761 {"aent", s_mips_ent
, 1},
762 {"bgnb", s_ignore
, 0},
763 {"end", s_mips_end
, 0},
764 {"endb", s_ignore
, 0},
765 {"ent", s_mips_ent
, 0},
767 {"fmask", s_mips_mask
, 'F'},
768 {"frame", s_mips_frame
, 0},
769 {"loc", s_ignore
, 0},
770 {"mask", s_mips_mask
, 'R'},
771 {"verstamp", s_ignore
, 0},
775 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
780 pop_insert (mips_pseudo_table
);
781 if (! ECOFF_DEBUGGING
)
782 pop_insert (mips_nonecoff_pseudo_table
);
785 /* Symbols labelling the current insn. */
787 struct insn_label_list
789 struct insn_label_list
*next
;
793 static struct insn_label_list
*insn_labels
;
794 static struct insn_label_list
*free_insn_labels
;
796 static void mips_clear_insn_labels
PARAMS ((void));
799 mips_clear_insn_labels ()
801 register struct insn_label_list
**pl
;
803 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
809 static char *expr_end
;
811 /* Expressions which appear in instructions. These are set by
814 static expressionS imm_expr
;
815 static expressionS offset_expr
;
817 /* Relocs associated with imm_expr and offset_expr. */
819 static bfd_reloc_code_real_type imm_reloc
;
820 static bfd_reloc_code_real_type offset_reloc
;
822 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
824 static boolean imm_unmatched_hi
;
826 /* These are set by mips16_ip if an explicit extension is used. */
828 static boolean mips16_small
, mips16_ext
;
830 #ifdef MIPS_STABS_ELF
831 /* The pdr segment for per procedure frame/regmask info */
837 * This function is called once, at assembler startup time. It should
838 * set up all the tables, etc. that the MD part of the assembler will need.
844 register const char *retval
= NULL
;
845 register unsigned int i
= 0;
849 int mips_isa_from_cpu
;
852 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
854 a
= xmalloc (sizeof TARGET_CPU
);
855 strcpy (a
, TARGET_CPU
);
856 a
[(sizeof TARGET_CPU
) - 3] = '\0';
862 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
863 just the generic 'mips', in which case set mips_cpu based
864 on the given ISA, if any. */
866 if (strcmp (cpu
, "mips") == 0)
868 if (mips_opts
.isa
< 0)
871 else if (mips_opts
.isa
== 2)
874 else if (mips_opts
.isa
== 3)
877 else if (mips_opts
.isa
== 4)
884 else if (strcmp (cpu
, "r3900") == 0
885 || strcmp (cpu
, "mipstx39") == 0
889 else if (strcmp (cpu
, "r6000") == 0
890 || strcmp (cpu
, "mips2") == 0)
893 else if (strcmp (cpu
, "mips64") == 0
894 || strcmp (cpu
, "r4000") == 0
895 || strcmp (cpu
, "mips3") == 0)
898 else if (strcmp (cpu
, "r4400") == 0)
901 else if (strcmp (cpu
, "mips64orion") == 0
902 || strcmp (cpu
, "r4600") == 0)
905 else if (strcmp (cpu
, "r4650") == 0)
908 else if (strcmp (cpu
, "mips64vr4300") == 0)
911 else if (strcmp (cpu
, "mips64vr4111") == 0)
914 else if (strcmp (cpu
, "mips64vr4100") == 0)
917 else if (strcmp (cpu
, "r4010") == 0)
921 else if (strcmp (cpu
, "r5000") == 0
922 || strcmp (cpu
, "mips64vr5000") == 0)
927 else if (strcmp (cpu
, "r8000") == 0
928 || strcmp (cpu
, "mips4") == 0)
931 else if (strcmp (cpu
, "r10000") == 0)
934 else if (strcmp (cpu
, "mips16") == 0)
935 mips_cpu
= 0; /* FIXME */
943 mips_isa_from_cpu
= 1;
945 else if (mips_cpu
== 6000
947 mips_isa_from_cpu
= 2;
949 else if (mips_cpu
== 4000
956 mips_isa_from_cpu
= 3;
958 else if (mips_cpu
== 5000
960 || mips_cpu
== 10000)
961 mips_isa_from_cpu
= 4;
964 mips_isa_from_cpu
= -1;
966 if (mips_opts
.isa
== -1)
968 if (mips_isa_from_cpu
!= -1)
969 mips_opts
.isa
= mips_isa_from_cpu
;
974 if (mips_opts
.mips16
< 0)
976 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
977 mips_opts
.mips16
= 1;
979 mips_opts
.mips16
= 0;
982 /* End of TARGET_CPU processing, get rid of malloced memory
991 if (mips_opts
.isa
== 1 && mips_trap
)
992 as_bad (_("trap exception not supported at ISA 1"));
994 /* Set the EABI kind based on the ISA before the user gets
995 to change the ISA with directives. This isn't really
996 the best, but then neither is basing the abi on the isa. */
997 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
999 && 0 == strcmp (mips_abi_string
,"eabi"))
1002 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1004 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1006 /* If they asked for mips1 or mips2 and a cpu that is
1007 mips3 or greater, then mark the object file 32BITMODE. */
1008 if (mips_isa_from_cpu
!= -1
1009 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1010 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1015 switch (mips_opts
.isa
)
1018 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1021 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1024 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1027 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1033 as_warn (_("Could not set architecture and machine"));
1035 file_mips_isa
= mips_opts
.isa
;
1037 op_hash
= hash_new ();
1039 for (i
= 0; i
< NUMOPCODES
;)
1041 const char *name
= mips_opcodes
[i
].name
;
1043 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1046 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1047 mips_opcodes
[i
].name
, retval
);
1048 /* Probably a memory allocation problem? Give up now. */
1049 as_fatal (_("Broken assembler. No assembly attempted."));
1053 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1055 if (!validate_mips_insn (&mips_opcodes
[i
]))
1060 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1063 mips16_op_hash
= hash_new ();
1066 while (i
< bfd_mips16_num_opcodes
)
1068 const char *name
= mips16_opcodes
[i
].name
;
1070 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1072 as_fatal (_("internal: can't hash `%s': %s"),
1073 mips16_opcodes
[i
].name
, retval
);
1076 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1077 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1078 != mips16_opcodes
[i
].match
))
1080 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1081 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1086 while (i
< bfd_mips16_num_opcodes
1087 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1091 as_fatal (_("Broken assembler. No assembly attempted."));
1093 /* We add all the general register names to the symbol table. This
1094 helps us detect invalid uses of them. */
1095 for (i
= 0; i
< 32; i
++)
1099 sprintf (buf
, "$%d", i
);
1100 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1101 &zero_address_frag
));
1103 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1104 &zero_address_frag
));
1105 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1106 &zero_address_frag
));
1107 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1108 &zero_address_frag
));
1109 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1110 &zero_address_frag
));
1111 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1112 &zero_address_frag
));
1113 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1114 &zero_address_frag
));
1115 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1116 &zero_address_frag
));
1118 mips_no_prev_insn (false);
1121 mips_cprmask
[0] = 0;
1122 mips_cprmask
[1] = 0;
1123 mips_cprmask
[2] = 0;
1124 mips_cprmask
[3] = 0;
1126 /* set the default alignment for the text section (2**2) */
1127 record_alignment (text_section
, 2);
1129 if (USE_GLOBAL_POINTER_OPT
)
1130 bfd_set_gp_size (stdoutput
, g_switch_value
);
1132 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1134 /* On a native system, sections must be aligned to 16 byte
1135 boundaries. When configured for an embedded ELF target, we
1137 if (strcmp (TARGET_OS
, "elf") != 0)
1139 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1140 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1141 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1144 /* Create a .reginfo section for register masks and a .mdebug
1145 section for debugging information. */
1153 subseg
= now_subseg
;
1155 /* The ABI says this section should be loaded so that the
1156 running program can access it. However, we don't load it
1157 if we are configured for an embedded target */
1158 flags
= SEC_READONLY
| SEC_DATA
;
1159 if (strcmp (TARGET_OS
, "elf") != 0)
1160 flags
|= SEC_ALLOC
| SEC_LOAD
;
1164 sec
= subseg_new (".reginfo", (subsegT
) 0);
1167 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1168 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1171 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1176 /* The 64-bit ABI uses a .MIPS.options section rather than
1177 .reginfo section. */
1178 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1179 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1180 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1183 /* Set up the option header. */
1185 Elf_Internal_Options opthdr
;
1188 opthdr
.kind
= ODK_REGINFO
;
1189 opthdr
.size
= (sizeof (Elf_External_Options
)
1190 + sizeof (Elf64_External_RegInfo
));
1193 f
= frag_more (sizeof (Elf_External_Options
));
1194 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1195 (Elf_External_Options
*) f
);
1197 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1202 if (ECOFF_DEBUGGING
)
1204 sec
= subseg_new (".mdebug", (subsegT
) 0);
1205 (void) bfd_set_section_flags (stdoutput
, sec
,
1206 SEC_HAS_CONTENTS
| SEC_READONLY
);
1207 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1210 #ifdef MIPS_STABS_ELF
1211 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1212 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1213 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1214 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1217 subseg_set (seg
, subseg
);
1221 if (! ECOFF_DEBUGGING
)
1228 if (! ECOFF_DEBUGGING
)
1236 struct mips_cl_insn insn
;
1238 imm_expr
.X_op
= O_absent
;
1239 imm_reloc
= BFD_RELOC_UNUSED
;
1240 imm_unmatched_hi
= false;
1241 offset_expr
.X_op
= O_absent
;
1242 offset_reloc
= BFD_RELOC_UNUSED
;
1244 if (mips_opts
.mips16
)
1245 mips16_ip (str
, &insn
);
1248 mips_ip (str
, &insn
);
1249 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1250 str
, insn
.insn_opcode
));
1255 as_bad ("%s `%s'", insn_error
, str
);
1259 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1261 if (mips_opts
.mips16
)
1262 mips16_macro (&insn
);
1268 if (imm_expr
.X_op
!= O_absent
)
1269 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1271 else if (offset_expr
.X_op
!= O_absent
)
1272 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1274 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1278 /* See whether instruction IP reads register REG. CLASS is the type
1282 insn_uses_reg (ip
, reg
, class)
1283 struct mips_cl_insn
*ip
;
1285 enum mips_regclass
class;
1287 if (class == MIPS16_REG
)
1289 assert (mips_opts
.mips16
);
1290 reg
= mips16_to_32_reg_map
[reg
];
1291 class = MIPS_GR_REG
;
1294 /* Don't report on general register 0, since it never changes. */
1295 if (class == MIPS_GR_REG
&& reg
== 0)
1298 if (class == MIPS_FP_REG
)
1300 assert (! mips_opts
.mips16
);
1301 /* If we are called with either $f0 or $f1, we must check $f0.
1302 This is not optimal, because it will introduce an unnecessary
1303 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1304 need to distinguish reading both $f0 and $f1 or just one of
1305 them. Note that we don't have to check the other way,
1306 because there is no instruction that sets both $f0 and $f1
1307 and requires a delay. */
1308 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1309 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1310 == (reg
&~ (unsigned) 1)))
1312 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1313 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1314 == (reg
&~ (unsigned) 1)))
1317 else if (! mips_opts
.mips16
)
1319 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1320 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1322 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1323 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1328 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1329 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1330 & MIPS16OP_MASK_RX
)]
1333 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1334 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1335 & MIPS16OP_MASK_RY
)]
1338 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1339 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1340 & MIPS16OP_MASK_MOVE32Z
)]
1343 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1345 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1347 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1349 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1350 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1351 & MIPS16OP_MASK_REGR32
) == reg
)
1358 /* This function returns true if modifying a register requires a
1362 reg_needs_delay (reg
)
1365 unsigned long prev_pinfo
;
1367 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1368 if (! mips_opts
.noreorder
1369 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1370 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1371 || (! gpr_interlocks
1372 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1374 /* A load from a coprocessor or from memory. All load
1375 delays delay the use of general register rt for one
1376 instruction on the r3000. The r6000 and r4000 use
1378 /* Itbl support may require additional care here. */
1379 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1380 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1387 /* Mark instruction labels in mips16 mode. This permits the linker to
1388 handle them specially, such as generating jalx instructions when
1389 needed. We also make them odd for the duration of the assembly, in
1390 order to generate the right sort of code. We will make them even
1391 in the adjust_symtab routine, while leaving them marked. This is
1392 convenient for the debugger and the disassembler. The linker knows
1393 to make them odd again. */
1396 mips16_mark_labels ()
1398 if (mips_opts
.mips16
)
1400 struct insn_label_list
*l
;
1402 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1405 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1406 S_SET_OTHER (l
->label
, STO_MIPS16
);
1408 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1409 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1414 /* Output an instruction. PLACE is where to put the instruction; if
1415 it is NULL, this uses frag_more to get room. IP is the instruction
1416 information. ADDRESS_EXPR is an operand of the instruction to be
1417 used with RELOC_TYPE. */
1420 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1422 struct mips_cl_insn
*ip
;
1423 expressionS
*address_expr
;
1424 bfd_reloc_code_real_type reloc_type
;
1425 boolean unmatched_hi
;
1427 register unsigned long prev_pinfo
, pinfo
;
1432 /* Mark instruction labels in mips16 mode. */
1433 if (mips_opts
.mips16
)
1434 mips16_mark_labels ();
1436 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1437 pinfo
= ip
->insn_mo
->pinfo
;
1439 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1443 /* If the previous insn required any delay slots, see if we need
1444 to insert a NOP or two. There are eight kinds of possible
1445 hazards, of which an instruction can have at most one type.
1446 (1) a load from memory delay
1447 (2) a load from a coprocessor delay
1448 (3) an unconditional branch delay
1449 (4) a conditional branch delay
1450 (5) a move to coprocessor register delay
1451 (6) a load coprocessor register from memory delay
1452 (7) a coprocessor condition code delay
1453 (8) a HI/LO special register delay
1455 There are a lot of optimizations we could do that we don't.
1456 In particular, we do not, in general, reorder instructions.
1457 If you use gcc with optimization, it will reorder
1458 instructions and generally do much more optimization then we
1459 do here; repeating all that work in the assembler would only
1460 benefit hand written assembly code, and does not seem worth
1463 /* This is how a NOP is emitted. */
1464 #define emit_nop() \
1466 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1467 : md_number_to_chars (frag_more (4), 0, 4))
1469 /* The previous insn might require a delay slot, depending upon
1470 the contents of the current insn. */
1471 if (! mips_opts
.mips16
1472 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1473 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1474 && ! cop_interlocks
)
1475 || (! gpr_interlocks
1476 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1478 /* A load from a coprocessor or from memory. All load
1479 delays delay the use of general register rt for one
1480 instruction on the r3000. The r6000 and r4000 use
1482 /* Itbl support may require additional care here. */
1483 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1484 if (mips_optimize
== 0
1485 || insn_uses_reg (ip
,
1486 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1491 else if (! mips_opts
.mips16
1492 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1493 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1494 && ! cop_interlocks
)
1495 || (mips_opts
.isa
== 1
1496 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1498 /* A generic coprocessor delay. The previous instruction
1499 modified a coprocessor general or control register. If
1500 it modified a control register, we need to avoid any
1501 coprocessor instruction (this is probably not always
1502 required, but it sometimes is). If it modified a general
1503 register, we avoid using that register.
1505 On the r6000 and r4000 loading a coprocessor register
1506 from memory is interlocked, and does not require a delay.
1508 This case is not handled very well. There is no special
1509 knowledge of CP0 handling, and the coprocessors other
1510 than the floating point unit are not distinguished at
1512 /* Itbl support may require additional care here. FIXME!
1513 Need to modify this to include knowledge about
1514 user specified delays! */
1515 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1517 if (mips_optimize
== 0
1518 || insn_uses_reg (ip
,
1519 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1524 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1526 if (mips_optimize
== 0
1527 || insn_uses_reg (ip
,
1528 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1535 /* We don't know exactly what the previous instruction
1536 does. If the current instruction uses a coprocessor
1537 register, we must insert a NOP. If previous
1538 instruction may set the condition codes, and the
1539 current instruction uses them, we must insert two
1541 /* Itbl support may require additional care here. */
1542 if (mips_optimize
== 0
1543 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1544 && (pinfo
& INSN_READ_COND_CODE
)))
1546 else if (pinfo
& INSN_COP
)
1550 else if (! mips_opts
.mips16
1551 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1552 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1553 && ! cop_interlocks
)
1555 /* The previous instruction sets the coprocessor condition
1556 codes, but does not require a general coprocessor delay
1557 (this means it is a floating point comparison
1558 instruction). If this instruction uses the condition
1559 codes, we need to insert a single NOP. */
1560 /* Itbl support may require additional care here. */
1561 if (mips_optimize
== 0
1562 || (pinfo
& INSN_READ_COND_CODE
))
1566 /* If we're fixing up mfhi/mflo for the r7000 and the
1567 previous insn was an mfhi/mflo and the current insn
1568 reads the register that the mfhi/mflo wrote to, then
1571 else if (mips_7000_hilo_fix
1572 && MF_HILO_INSN (prev_pinfo
)
1573 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1581 /* If we're fixing up mfhi/mflo for the r7000 and the
1582 2nd previous insn was an mfhi/mflo and the current insn
1583 reads the register that the mfhi/mflo wrote to, then
1586 else if (mips_7000_hilo_fix
1587 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1588 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1596 else if (prev_pinfo
& INSN_READ_LO
)
1598 /* The previous instruction reads the LO register; if the
1599 current instruction writes to the LO register, we must
1600 insert two NOPS. Some newer processors have interlocks.
1601 Also the tx39's multiply instructions can be exectuted
1602 immediatly after a read from HI/LO (without the delay),
1603 though the tx39's divide insns still do require the
1605 if (! (hilo_interlocks
1606 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1607 && (mips_optimize
== 0
1608 || (pinfo
& INSN_WRITE_LO
)))
1610 /* Most mips16 branch insns don't have a delay slot.
1611 If a read from LO is immediately followed by a branch
1612 to a write to LO we have a read followed by a write
1613 less than 2 insns away. We assume the target of
1614 a branch might be a write to LO, and insert a nop
1615 between a read and an immediately following branch. */
1616 else if (mips_opts
.mips16
1617 && (mips_optimize
== 0
1618 || (pinfo
& MIPS16_INSN_BRANCH
)))
1621 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1623 /* The previous instruction reads the HI register; if the
1624 current instruction writes to the HI register, we must
1625 insert a NOP. Some newer processors have interlocks.
1626 Also the note tx39's multiply above. */
1627 if (! (hilo_interlocks
1628 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1629 && (mips_optimize
== 0
1630 || (pinfo
& INSN_WRITE_HI
)))
1632 /* Most mips16 branch insns don't have a delay slot.
1633 If a read from HI is immediately followed by a branch
1634 to a write to HI we have a read followed by a write
1635 less than 2 insns away. We assume the target of
1636 a branch might be a write to HI, and insert a nop
1637 between a read and an immediately following branch. */
1638 else if (mips_opts
.mips16
1639 && (mips_optimize
== 0
1640 || (pinfo
& MIPS16_INSN_BRANCH
)))
1644 /* If the previous instruction was in a noreorder section, then
1645 we don't want to insert the nop after all. */
1646 /* Itbl support may require additional care here. */
1647 if (prev_insn_unreordered
)
1650 /* There are two cases which require two intervening
1651 instructions: 1) setting the condition codes using a move to
1652 coprocessor instruction which requires a general coprocessor
1653 delay and then reading the condition codes 2) reading the HI
1654 or LO register and then writing to it (except on processors
1655 which have interlocks). If we are not already emitting a NOP
1656 instruction, we must check for these cases compared to the
1657 instruction previous to the previous instruction. */
1658 if ((! mips_opts
.mips16
1659 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1660 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1661 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1662 && (pinfo
& INSN_READ_COND_CODE
)
1663 && ! cop_interlocks
)
1664 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1665 && (pinfo
& INSN_WRITE_LO
)
1666 && ! (hilo_interlocks
1667 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1668 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1669 && (pinfo
& INSN_WRITE_HI
)
1670 && ! (hilo_interlocks
1671 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1676 if (prev_prev_insn_unreordered
)
1679 if (prev_prev_nop
&& nops
== 0)
1682 /* If we are being given a nop instruction, don't bother with
1683 one of the nops we would otherwise output. This will only
1684 happen when a nop instruction is used with mips_optimize set
1687 && ! mips_opts
.noreorder
1688 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1691 /* Now emit the right number of NOP instructions. */
1692 if (nops
> 0 && ! mips_opts
.noreorder
)
1695 unsigned long old_frag_offset
;
1697 struct insn_label_list
*l
;
1699 old_frag
= frag_now
;
1700 old_frag_offset
= frag_now_fix ();
1702 for (i
= 0; i
< nops
; i
++)
1707 listing_prev_line ();
1708 /* We may be at the start of a variant frag. In case we
1709 are, make sure there is enough space for the frag
1710 after the frags created by listing_prev_line. The
1711 argument to frag_grow here must be at least as large
1712 as the argument to all other calls to frag_grow in
1713 this file. We don't have to worry about being in the
1714 middle of a variant frag, because the variants insert
1715 all needed nop instructions themselves. */
1719 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1721 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1722 symbol_set_frag (l
->label
, frag_now
);
1723 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1724 /* mips16 text labels are stored as odd. */
1725 if (mips_opts
.mips16
)
1726 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1729 #ifndef NO_ECOFF_DEBUGGING
1730 if (ECOFF_DEBUGGING
)
1731 ecoff_fix_loc (old_frag
, old_frag_offset
);
1734 else if (prev_nop_frag
!= NULL
)
1736 /* We have a frag holding nops we may be able to remove. If
1737 we don't need any nops, we can decrease the size of
1738 prev_nop_frag by the size of one instruction. If we do
1739 need some nops, we count them in prev_nops_required. */
1740 if (prev_nop_frag_since
== 0)
1744 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1745 --prev_nop_frag_holds
;
1748 prev_nop_frag_required
+= nops
;
1752 if (prev_prev_nop
== 0)
1754 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1755 --prev_nop_frag_holds
;
1758 ++prev_nop_frag_required
;
1761 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1762 prev_nop_frag
= NULL
;
1764 ++prev_nop_frag_since
;
1766 /* Sanity check: by the time we reach the second instruction
1767 after prev_nop_frag, we should have used up all the nops
1768 one way or another. */
1769 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1773 if (reloc_type
> BFD_RELOC_UNUSED
)
1775 /* We need to set up a variant frag. */
1776 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1777 f
= frag_var (rs_machine_dependent
, 4, 0,
1778 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1779 mips16_small
, mips16_ext
,
1781 & INSN_UNCOND_BRANCH_DELAY
),
1782 (prev_insn_reloc_type
1783 == BFD_RELOC_MIPS16_JMP
)),
1784 make_expr_symbol (address_expr
), (offsetT
) 0,
1787 else if (place
!= NULL
)
1789 else if (mips_opts
.mips16
1791 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1793 /* Make sure there is enough room to swap this instruction with
1794 a following jump instruction. */
1800 if (mips_opts
.mips16
1801 && mips_opts
.noreorder
1802 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1803 as_warn (_("extended instruction in delay slot"));
1809 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1811 if (address_expr
->X_op
== O_constant
)
1816 ip
->insn_opcode
|= address_expr
->X_add_number
;
1819 case BFD_RELOC_LO16
:
1820 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1823 case BFD_RELOC_MIPS_JMP
:
1824 if ((address_expr
->X_add_number
& 3) != 0)
1825 as_bad (_("jump to misaligned address (0x%lx)"),
1826 (unsigned long) address_expr
->X_add_number
);
1827 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1830 case BFD_RELOC_MIPS16_JMP
:
1831 if ((address_expr
->X_add_number
& 3) != 0)
1832 as_bad (_("jump to misaligned address (0x%lx)"),
1833 (unsigned long) address_expr
->X_add_number
);
1835 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1836 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1837 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1841 case BFD_RELOC_16_PCREL_S2
:
1851 /* Don't generate a reloc if we are writing into a variant
1855 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1857 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1861 struct mips_hi_fixup
*hi_fixup
;
1863 assert (reloc_type
== BFD_RELOC_HI16_S
);
1864 hi_fixup
= ((struct mips_hi_fixup
*)
1865 xmalloc (sizeof (struct mips_hi_fixup
)));
1866 hi_fixup
->fixp
= fixp
;
1867 hi_fixup
->seg
= now_seg
;
1868 hi_fixup
->next
= mips_hi_fixup_list
;
1869 mips_hi_fixup_list
= hi_fixup
;
1875 if (! mips_opts
.mips16
)
1876 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1877 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1879 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1880 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1886 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1889 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1892 /* Update the register mask information. */
1893 if (! mips_opts
.mips16
)
1895 if (pinfo
& INSN_WRITE_GPR_D
)
1896 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1897 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1898 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1899 if (pinfo
& INSN_READ_GPR_S
)
1900 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1901 if (pinfo
& INSN_WRITE_GPR_31
)
1902 mips_gprmask
|= 1 << 31;
1903 if (pinfo
& INSN_WRITE_FPR_D
)
1904 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1905 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1906 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1907 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1908 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1909 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1910 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1911 if (pinfo
& INSN_COP
)
1913 /* We don't keep enough information to sort these cases out.
1914 The itbl support does keep this information however, although
1915 we currently don't support itbl fprmats as part of the cop
1916 instruction. May want to add this support in the future. */
1918 /* Never set the bit for $0, which is always zero. */
1919 mips_gprmask
&=~ 1 << 0;
1923 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1924 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1925 & MIPS16OP_MASK_RX
);
1926 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1928 & MIPS16OP_MASK_RY
);
1929 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1930 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1931 & MIPS16OP_MASK_RZ
);
1932 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1933 mips_gprmask
|= 1 << TREG
;
1934 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1935 mips_gprmask
|= 1 << SP
;
1936 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1937 mips_gprmask
|= 1 << RA
;
1938 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1939 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1940 if (pinfo
& MIPS16_INSN_READ_Z
)
1941 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1942 & MIPS16OP_MASK_MOVE32Z
);
1943 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1944 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1945 & MIPS16OP_MASK_REGR32
);
1948 if (place
== NULL
&& ! mips_opts
.noreorder
)
1950 /* Filling the branch delay slot is more complex. We try to
1951 switch the branch with the previous instruction, which we can
1952 do if the previous instruction does not set up a condition
1953 that the branch tests and if the branch is not itself the
1954 target of any branch. */
1955 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1956 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1958 if (mips_optimize
< 2
1959 /* If we have seen .set volatile or .set nomove, don't
1961 || mips_opts
.nomove
!= 0
1962 /* If we had to emit any NOP instructions, then we
1963 already know we can not swap. */
1965 /* If we don't even know the previous insn, we can not
1967 || ! prev_insn_valid
1968 /* If the previous insn is already in a branch delay
1969 slot, then we can not swap. */
1970 || prev_insn_is_delay_slot
1971 /* If the previous previous insn was in a .set
1972 noreorder, we can't swap. Actually, the MIPS
1973 assembler will swap in this situation. However, gcc
1974 configured -with-gnu-as will generate code like
1980 in which we can not swap the bne and INSN. If gcc is
1981 not configured -with-gnu-as, it does not output the
1982 .set pseudo-ops. We don't have to check
1983 prev_insn_unreordered, because prev_insn_valid will
1984 be 0 in that case. We don't want to use
1985 prev_prev_insn_valid, because we do want to be able
1986 to swap at the start of a function. */
1987 || prev_prev_insn_unreordered
1988 /* If the branch is itself the target of a branch, we
1989 can not swap. We cheat on this; all we check for is
1990 whether there is a label on this instruction. If
1991 there are any branches to anything other than a
1992 label, users must use .set noreorder. */
1993 || insn_labels
!= NULL
1994 /* If the previous instruction is in a variant frag, we
1995 can not do the swap. This does not apply to the
1996 mips16, which uses variant frags for different
1998 || (! mips_opts
.mips16
1999 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2000 /* If the branch reads the condition codes, we don't
2001 even try to swap, because in the sequence
2006 we can not swap, and I don't feel like handling that
2008 || (! mips_opts
.mips16
2009 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2010 && (pinfo
& INSN_READ_COND_CODE
))
2011 /* We can not swap with an instruction that requires a
2012 delay slot, becase the target of the branch might
2013 interfere with that instruction. */
2014 || (! mips_opts
.mips16
2015 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2017 /* Itbl support may require additional care here. */
2018 & (INSN_LOAD_COPROC_DELAY
2019 | INSN_COPROC_MOVE_DELAY
2020 | INSN_WRITE_COND_CODE
)))
2021 || (! (hilo_interlocks
2022 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2026 || (! mips_opts
.mips16
2028 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2029 || (! mips_opts
.mips16
2030 && mips_opts
.isa
== 1
2031 /* Itbl support may require additional care here. */
2032 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2033 /* We can not swap with a branch instruction. */
2035 & (INSN_UNCOND_BRANCH_DELAY
2036 | INSN_COND_BRANCH_DELAY
2037 | INSN_COND_BRANCH_LIKELY
))
2038 /* We do not swap with a trap instruction, since it
2039 complicates trap handlers to have the trap
2040 instruction be in a delay slot. */
2041 || (prev_pinfo
& INSN_TRAP
)
2042 /* If the branch reads a register that the previous
2043 instruction sets, we can not swap. */
2044 || (! mips_opts
.mips16
2045 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2046 && insn_uses_reg (ip
,
2047 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2050 || (! mips_opts
.mips16
2051 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2052 && insn_uses_reg (ip
,
2053 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2056 || (mips_opts
.mips16
2057 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2058 && insn_uses_reg (ip
,
2059 ((prev_insn
.insn_opcode
2061 & MIPS16OP_MASK_RX
),
2063 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2064 && insn_uses_reg (ip
,
2065 ((prev_insn
.insn_opcode
2067 & MIPS16OP_MASK_RY
),
2069 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2070 && insn_uses_reg (ip
,
2071 ((prev_insn
.insn_opcode
2073 & MIPS16OP_MASK_RZ
),
2075 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2076 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2077 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2078 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2079 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2080 && insn_uses_reg (ip
,
2081 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2084 /* If the branch writes a register that the previous
2085 instruction sets, we can not swap (we know that
2086 branches write only to RD or to $31). */
2087 || (! mips_opts
.mips16
2088 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2089 && (((pinfo
& INSN_WRITE_GPR_D
)
2090 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2091 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2092 || ((pinfo
& INSN_WRITE_GPR_31
)
2093 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2096 || (! mips_opts
.mips16
2097 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2098 && (((pinfo
& INSN_WRITE_GPR_D
)
2099 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2100 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2101 || ((pinfo
& INSN_WRITE_GPR_31
)
2102 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2105 || (mips_opts
.mips16
2106 && (pinfo
& MIPS16_INSN_WRITE_31
)
2107 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2108 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2109 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2111 /* If the branch writes a register that the previous
2112 instruction reads, we can not swap (we know that
2113 branches only write to RD or to $31). */
2114 || (! mips_opts
.mips16
2115 && (pinfo
& INSN_WRITE_GPR_D
)
2116 && insn_uses_reg (&prev_insn
,
2117 ((ip
->insn_opcode
>> OP_SH_RD
)
2120 || (! mips_opts
.mips16
2121 && (pinfo
& INSN_WRITE_GPR_31
)
2122 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2123 || (mips_opts
.mips16
2124 && (pinfo
& MIPS16_INSN_WRITE_31
)
2125 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2126 /* If we are generating embedded PIC code, the branch
2127 might be expanded into a sequence which uses $at, so
2128 we can't swap with an instruction which reads it. */
2129 || (mips_pic
== EMBEDDED_PIC
2130 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2131 /* If the previous previous instruction has a load
2132 delay, and sets a register that the branch reads, we
2134 || (! mips_opts
.mips16
2135 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2136 /* Itbl support may require additional care here. */
2137 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2138 || (! gpr_interlocks
2139 && (prev_prev_insn
.insn_mo
->pinfo
2140 & INSN_LOAD_MEMORY_DELAY
)))
2141 && insn_uses_reg (ip
,
2142 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2145 /* If one instruction sets a condition code and the
2146 other one uses a condition code, we can not swap. */
2147 || ((pinfo
& INSN_READ_COND_CODE
)
2148 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2149 || ((pinfo
& INSN_WRITE_COND_CODE
)
2150 && (prev_pinfo
& INSN_READ_COND_CODE
))
2151 /* If the previous instruction uses the PC, we can not
2153 || (mips_opts
.mips16
2154 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2155 /* If the previous instruction was extended, we can not
2157 || (mips_opts
.mips16
&& prev_insn_extended
)
2158 /* If the previous instruction had a fixup in mips16
2159 mode, we can not swap. This normally means that the
2160 previous instruction was a 4 byte branch anyhow. */
2161 || (mips_opts
.mips16
&& prev_insn_fixp
)
2162 /* If the previous instruction is a sync, sync.l, or
2163 sync.p, we can not swap. */
2164 || (prev_pinfo
& INSN_SYNC
))
2166 /* We could do even better for unconditional branches to
2167 portions of this object file; we could pick up the
2168 instruction at the destination, put it in the delay
2169 slot, and bump the destination address. */
2171 /* Update the previous insn information. */
2172 prev_prev_insn
= *ip
;
2173 prev_insn
.insn_mo
= &dummy_opcode
;
2177 /* It looks like we can actually do the swap. */
2178 if (! mips_opts
.mips16
)
2183 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2184 memcpy (temp
, prev_f
, 4);
2185 memcpy (prev_f
, f
, 4);
2186 memcpy (f
, temp
, 4);
2189 prev_insn_fixp
->fx_frag
= frag_now
;
2190 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2194 fixp
->fx_frag
= prev_insn_frag
;
2195 fixp
->fx_where
= prev_insn_where
;
2203 assert (prev_insn_fixp
== NULL
);
2204 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2205 memcpy (temp
, prev_f
, 2);
2206 memcpy (prev_f
, f
, 2);
2207 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2209 assert (reloc_type
== BFD_RELOC_UNUSED
);
2210 memcpy (f
, temp
, 2);
2214 memcpy (f
, f
+ 2, 2);
2215 memcpy (f
+ 2, temp
, 2);
2219 fixp
->fx_frag
= prev_insn_frag
;
2220 fixp
->fx_where
= prev_insn_where
;
2224 /* Update the previous insn information; leave prev_insn
2226 prev_prev_insn
= *ip
;
2228 prev_insn_is_delay_slot
= 1;
2230 /* If that was an unconditional branch, forget the previous
2231 insn information. */
2232 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2234 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2235 prev_insn
.insn_mo
= &dummy_opcode
;
2238 prev_insn_fixp
= NULL
;
2239 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2240 prev_insn_extended
= 0;
2242 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2244 /* We don't yet optimize a branch likely. What we should do
2245 is look at the target, copy the instruction found there
2246 into the delay slot, and increment the branch to jump to
2247 the next instruction. */
2249 /* Update the previous insn information. */
2250 prev_prev_insn
= *ip
;
2251 prev_insn
.insn_mo
= &dummy_opcode
;
2252 prev_insn_fixp
= NULL
;
2253 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2254 prev_insn_extended
= 0;
2258 /* Update the previous insn information. */
2260 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2262 prev_prev_insn
= prev_insn
;
2265 /* Any time we see a branch, we always fill the delay slot
2266 immediately; since this insn is not a branch, we know it
2267 is not in a delay slot. */
2268 prev_insn_is_delay_slot
= 0;
2270 prev_insn_fixp
= fixp
;
2271 prev_insn_reloc_type
= reloc_type
;
2272 if (mips_opts
.mips16
)
2273 prev_insn_extended
= (ip
->use_extend
2274 || reloc_type
> BFD_RELOC_UNUSED
);
2277 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2278 prev_insn_unreordered
= 0;
2279 prev_insn_frag
= frag_now
;
2280 prev_insn_where
= f
- frag_now
->fr_literal
;
2281 prev_insn_valid
= 1;
2283 else if (place
== NULL
)
2285 /* We need to record a bit of information even when we are not
2286 reordering, in order to determine the base address for mips16
2287 PC relative relocs. */
2288 prev_prev_insn
= prev_insn
;
2290 prev_insn_reloc_type
= reloc_type
;
2291 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2292 prev_insn_unreordered
= 1;
2295 /* We just output an insn, so the next one doesn't have a label. */
2296 mips_clear_insn_labels ();
2298 /* We must ensure that a fixup associated with an unmatched %hi
2299 reloc does not become a variant frag. Otherwise, the
2300 rearrangement of %hi relocs in frob_file may confuse
2304 frag_wane (frag_now
);
2309 /* This function forgets that there was any previous instruction or
2310 label. If PRESERVE is non-zero, it remembers enough information to
2311 know whether nops are needed before a noreorder section. */
2314 mips_no_prev_insn (preserve
)
2319 prev_insn
.insn_mo
= &dummy_opcode
;
2320 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2321 prev_nop_frag
= NULL
;
2322 prev_nop_frag_holds
= 0;
2323 prev_nop_frag_required
= 0;
2324 prev_nop_frag_since
= 0;
2326 prev_insn_valid
= 0;
2327 prev_insn_is_delay_slot
= 0;
2328 prev_insn_unreordered
= 0;
2329 prev_insn_extended
= 0;
2330 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2331 prev_prev_insn_unreordered
= 0;
2332 mips_clear_insn_labels ();
2335 /* This function must be called whenever we turn on noreorder or emit
2336 something other than instructions. It inserts any NOPS which might
2337 be needed by the previous instruction, and clears the information
2338 kept for the previous instructions. The INSNS parameter is true if
2339 instructions are to follow. */
2342 mips_emit_delays (insns
)
2345 if (! mips_opts
.noreorder
)
2350 if ((! mips_opts
.mips16
2351 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2352 && (! cop_interlocks
2353 && (prev_insn
.insn_mo
->pinfo
2354 & (INSN_LOAD_COPROC_DELAY
2355 | INSN_COPROC_MOVE_DELAY
2356 | INSN_WRITE_COND_CODE
))))
2357 || (! hilo_interlocks
2358 && (prev_insn
.insn_mo
->pinfo
2361 || (! mips_opts
.mips16
2363 && (prev_insn
.insn_mo
->pinfo
2364 & INSN_LOAD_MEMORY_DELAY
))
2365 || (! mips_opts
.mips16
2366 && mips_opts
.isa
== 1
2367 && (prev_insn
.insn_mo
->pinfo
2368 & INSN_COPROC_MEMORY_DELAY
)))
2370 /* Itbl support may require additional care here. */
2372 if ((! mips_opts
.mips16
2373 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2374 && (! cop_interlocks
2375 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2376 || (! hilo_interlocks
2377 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2378 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2381 if (prev_insn_unreordered
)
2384 else if ((! mips_opts
.mips16
2385 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2386 && (! cop_interlocks
2387 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2388 || (! hilo_interlocks
2389 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2390 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2392 /* Itbl support may require additional care here. */
2393 if (! prev_prev_insn_unreordered
)
2399 struct insn_label_list
*l
;
2403 /* Record the frag which holds the nop instructions, so
2404 that we can remove them if we don't need them. */
2405 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2406 prev_nop_frag
= frag_now
;
2407 prev_nop_frag_holds
= nops
;
2408 prev_nop_frag_required
= 0;
2409 prev_nop_frag_since
= 0;
2412 for (; nops
> 0; --nops
)
2417 /* Move on to a new frag, so that it is safe to simply
2418 decrease the size of prev_nop_frag. */
2419 frag_wane (frag_now
);
2423 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2425 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2426 symbol_set_frag (l
->label
, frag_now
);
2427 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2428 /* mips16 text labels are stored as odd. */
2429 if (mips_opts
.mips16
)
2430 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2435 /* Mark instruction labels in mips16 mode. */
2436 if (mips_opts
.mips16
&& insns
)
2437 mips16_mark_labels ();
2439 mips_no_prev_insn (insns
);
2442 /* Build an instruction created by a macro expansion. This is passed
2443 a pointer to the count of instructions created so far, an
2444 expression, the name of the instruction to build, an operand format
2445 string, and corresponding arguments. */
2449 macro_build (char *place
,
2457 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2466 struct mips_cl_insn insn
;
2467 bfd_reloc_code_real_type r
;
2471 va_start (args
, fmt
);
2477 * If the macro is about to expand into a second instruction,
2478 * print a warning if needed. We need to pass ip as a parameter
2479 * to generate a better warning message here...
2481 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2482 as_warn (_("Macro instruction expanded into multiple instructions"));
2485 *counter
+= 1; /* bump instruction counter */
2487 if (mips_opts
.mips16
)
2489 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2494 r
= BFD_RELOC_UNUSED
;
2495 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2496 assert (insn
.insn_mo
);
2497 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2499 /* Search until we get a match for NAME. */
2502 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2503 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2504 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2506 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2510 assert (insn
.insn_mo
->name
);
2511 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2514 insn
.insn_opcode
= insn
.insn_mo
->match
;
2530 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2536 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2541 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2546 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2553 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2557 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2561 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2565 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2572 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2578 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2579 assert (r
== BFD_RELOC_MIPS_GPREL
2580 || r
== BFD_RELOC_MIPS_LITERAL
2581 || r
== BFD_RELOC_LO16
2582 || r
== BFD_RELOC_MIPS_GOT16
2583 || r
== BFD_RELOC_MIPS_CALL16
2584 || r
== BFD_RELOC_MIPS_GOT_LO16
2585 || r
== BFD_RELOC_MIPS_CALL_LO16
2586 || (ep
->X_op
== O_subtract
2587 && now_seg
== text_section
2588 && r
== BFD_RELOC_PCREL_LO16
));
2592 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2594 && (ep
->X_op
== O_constant
2595 || (ep
->X_op
== O_symbol
2596 && (r
== BFD_RELOC_HI16_S
2597 || r
== BFD_RELOC_HI16
2598 || r
== BFD_RELOC_MIPS_GOT_HI16
2599 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2600 || (ep
->X_op
== O_subtract
2601 && now_seg
== text_section
2602 && r
== BFD_RELOC_PCREL_HI16_S
)));
2603 if (ep
->X_op
== O_constant
)
2605 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2607 r
= BFD_RELOC_UNUSED
;
2612 assert (ep
!= NULL
);
2614 * This allows macro() to pass an immediate expression for
2615 * creating short branches without creating a symbol.
2616 * Note that the expression still might come from the assembly
2617 * input, in which case the value is not checked for range nor
2618 * is a relocation entry generated (yuck).
2620 if (ep
->X_op
== O_constant
)
2622 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2626 r
= BFD_RELOC_16_PCREL_S2
;
2630 assert (ep
!= NULL
);
2631 r
= BFD_RELOC_MIPS_JMP
;
2635 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2644 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2646 append_insn (place
, &insn
, ep
, r
, false);
2650 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2658 struct mips_cl_insn insn
;
2659 bfd_reloc_code_real_type r
;
2661 r
= BFD_RELOC_UNUSED
;
2662 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2663 assert (insn
.insn_mo
);
2664 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2666 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2667 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2670 assert (insn
.insn_mo
->name
);
2671 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2674 insn
.insn_opcode
= insn
.insn_mo
->match
;
2675 insn
.use_extend
= false;
2694 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2699 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2703 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2707 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2717 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2724 regno
= va_arg (args
, int);
2725 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2726 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2747 assert (ep
!= NULL
);
2749 if (ep
->X_op
!= O_constant
)
2750 r
= BFD_RELOC_UNUSED
+ c
;
2753 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2754 false, false, &insn
.insn_opcode
,
2755 &insn
.use_extend
, &insn
.extend
);
2757 r
= BFD_RELOC_UNUSED
;
2763 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2770 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2772 append_insn (place
, &insn
, ep
, r
, false);
2776 * Generate a "lui" instruction.
2779 macro_build_lui (place
, counter
, ep
, regnum
)
2785 expressionS high_expr
;
2786 struct mips_cl_insn insn
;
2787 bfd_reloc_code_real_type r
;
2788 CONST
char *name
= "lui";
2789 CONST
char *fmt
= "t,u";
2791 assert (! mips_opts
.mips16
);
2797 high_expr
.X_op
= O_constant
;
2798 high_expr
.X_add_number
= ep
->X_add_number
;
2801 if (high_expr
.X_op
== O_constant
)
2803 /* we can compute the instruction now without a relocation entry */
2804 if (high_expr
.X_add_number
& 0x8000)
2805 high_expr
.X_add_number
+= 0x10000;
2806 high_expr
.X_add_number
=
2807 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2808 r
= BFD_RELOC_UNUSED
;
2812 assert (ep
->X_op
== O_symbol
);
2813 /* _gp_disp is a special case, used from s_cpload. */
2814 assert (mips_pic
== NO_PIC
2815 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2816 r
= BFD_RELOC_HI16_S
;
2820 * If the macro is about to expand into a second instruction,
2821 * print a warning if needed. We need to pass ip as a parameter
2822 * to generate a better warning message here...
2824 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2825 as_warn (_("Macro instruction expanded into multiple instructions"));
2828 *counter
+= 1; /* bump instruction counter */
2830 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2831 assert (insn
.insn_mo
);
2832 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2833 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2835 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2836 if (r
== BFD_RELOC_UNUSED
)
2838 insn
.insn_opcode
|= high_expr
.X_add_number
;
2839 append_insn (place
, &insn
, NULL
, r
, false);
2842 append_insn (place
, &insn
, &high_expr
, r
, false);
2846 * Generates code to set the $at register to true (one)
2847 * if reg is less than the immediate expression.
2850 set_at (counter
, reg
, unsignedp
)
2855 if (imm_expr
.X_op
== O_constant
2856 && imm_expr
.X_add_number
>= -0x8000
2857 && imm_expr
.X_add_number
< 0x8000)
2858 macro_build ((char *) NULL
, counter
, &imm_expr
,
2859 unsignedp
? "sltiu" : "slti",
2860 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2863 load_register (counter
, AT
, &imm_expr
, 0);
2864 macro_build ((char *) NULL
, counter
, NULL
,
2865 unsignedp
? "sltu" : "slt",
2866 "d,v,t", AT
, reg
, AT
);
2870 /* Warn if an expression is not a constant. */
2873 check_absolute_expr (ip
, ex
)
2874 struct mips_cl_insn
*ip
;
2877 if (ex
->X_op
== O_big
)
2878 as_bad (_("unsupported large constant"));
2879 else if (ex
->X_op
!= O_constant
)
2880 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2883 /* Count the leading zeroes by performing a binary chop. This is a
2884 bulky bit of source, but performance is a LOT better for the
2885 majority of values than a simple loop to count the bits:
2886 for (lcnt = 0; (lcnt < 32); lcnt++)
2887 if ((v) & (1 << (31 - lcnt)))
2889 However it is not code size friendly, and the gain will drop a bit
2890 on certain cached systems.
2892 #define COUNT_TOP_ZEROES(v) \
2893 (((v) & ~0xffff) == 0 \
2894 ? ((v) & ~0xff) == 0 \
2895 ? ((v) & ~0xf) == 0 \
2896 ? ((v) & ~0x3) == 0 \
2897 ? ((v) & ~0x1) == 0 \
2902 : ((v) & ~0x7) == 0 \
2905 : ((v) & ~0x3f) == 0 \
2906 ? ((v) & ~0x1f) == 0 \
2909 : ((v) & ~0x7f) == 0 \
2912 : ((v) & ~0xfff) == 0 \
2913 ? ((v) & ~0x3ff) == 0 \
2914 ? ((v) & ~0x1ff) == 0 \
2917 : ((v) & ~0x7ff) == 0 \
2920 : ((v) & ~0x3fff) == 0 \
2921 ? ((v) & ~0x1fff) == 0 \
2924 : ((v) & ~0x7fff) == 0 \
2927 : ((v) & ~0xffffff) == 0 \
2928 ? ((v) & ~0xfffff) == 0 \
2929 ? ((v) & ~0x3ffff) == 0 \
2930 ? ((v) & ~0x1ffff) == 0 \
2933 : ((v) & ~0x7ffff) == 0 \
2936 : ((v) & ~0x3fffff) == 0 \
2937 ? ((v) & ~0x1fffff) == 0 \
2940 : ((v) & ~0x7fffff) == 0 \
2943 : ((v) & ~0xfffffff) == 0 \
2944 ? ((v) & ~0x3ffffff) == 0 \
2945 ? ((v) & ~0x1ffffff) == 0 \
2948 : ((v) & ~0x7ffffff) == 0 \
2951 : ((v) & ~0x3fffffff) == 0 \
2952 ? ((v) & ~0x1fffffff) == 0 \
2955 : ((v) & ~0x7fffffff) == 0 \
2960 * This routine generates the least number of instructions neccessary to load
2961 * an absolute expression value into a register.
2964 load_register (counter
, reg
, ep
, dbl
)
2971 expressionS hi32
, lo32
;
2973 if (ep
->X_op
!= O_big
)
2975 assert (ep
->X_op
== O_constant
);
2976 if (ep
->X_add_number
< 0x8000
2977 && (ep
->X_add_number
>= 0
2978 || (ep
->X_add_number
>= -0x8000
2981 || sizeof (ep
->X_add_number
) > 4))))
2983 /* We can handle 16 bit signed values with an addiu to
2984 $zero. No need to ever use daddiu here, since $zero and
2985 the result are always correct in 32 bit mode. */
2986 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2987 (int) BFD_RELOC_LO16
);
2990 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2992 /* We can handle 16 bit unsigned values with an ori to
2994 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2995 (int) BFD_RELOC_LO16
);
2998 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2999 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3000 == ~ (offsetT
) 0x7fffffff))
3003 || sizeof (ep
->X_add_number
) > 4
3004 || (ep
->X_add_number
& 0x80000000) == 0))
3005 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3006 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3007 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3009 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3010 == ~ (offsetT
) 0xffffffff)))
3012 /* 32 bit values require an lui. */
3013 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3014 (int) BFD_RELOC_HI16
);
3015 if ((ep
->X_add_number
& 0xffff) != 0)
3016 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3017 (int) BFD_RELOC_LO16
);
3022 /* The value is larger than 32 bits. */
3024 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3026 as_bad (_("Number larger than 32 bits"));
3027 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3028 (int) BFD_RELOC_LO16
);
3032 if (ep
->X_op
!= O_big
)
3035 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3036 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3037 hi32
.X_add_number
&= 0xffffffff;
3039 lo32
.X_add_number
&= 0xffffffff;
3043 assert (ep
->X_add_number
> 2);
3044 if (ep
->X_add_number
== 3)
3045 generic_bignum
[3] = 0;
3046 else if (ep
->X_add_number
> 4)
3047 as_bad (_("Number larger than 64 bits"));
3048 lo32
.X_op
= O_constant
;
3049 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3050 hi32
.X_op
= O_constant
;
3051 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3054 if (hi32
.X_add_number
== 0)
3059 unsigned long hi
, lo
;
3061 if (hi32
.X_add_number
== 0xffffffff)
3063 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3065 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3066 reg
, 0, (int) BFD_RELOC_LO16
);
3069 if (lo32
.X_add_number
& 0x80000000)
3071 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3072 (int) BFD_RELOC_HI16
);
3073 if (lo32
.X_add_number
& 0xffff)
3074 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3075 reg
, reg
, (int) BFD_RELOC_LO16
);
3080 /* Check for 16bit shifted constant. We know that hi32 is
3081 non-zero, so start the mask on the first bit of the hi32
3086 unsigned long himask
, lomask
;
3090 himask
= 0xffff >> (32 - shift
);
3091 lomask
= (0xffff << shift
) & 0xffffffff;
3095 himask
= 0xffff << (shift
- 32);
3098 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3099 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3103 tmp
.X_op
= O_constant
;
3105 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3106 | (lo32
.X_add_number
>> shift
));
3108 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3109 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3110 (int) BFD_RELOC_LO16
);
3111 macro_build ((char *) NULL
, counter
, NULL
,
3112 (shift
>= 32) ? "dsll32" : "dsll",
3114 (shift
>= 32) ? shift
- 32 : shift
);
3118 } while (shift
<= (64 - 16));
3120 /* Find the bit number of the lowest one bit, and store the
3121 shifted value in hi/lo. */
3122 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3123 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3127 while ((lo
& 1) == 0)
3132 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3138 while ((hi
& 1) == 0)
3147 /* Optimize if the shifted value is a (power of 2) - 1. */
3148 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3149 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3151 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3156 /* This instruction will set the register to be all
3158 tmp
.X_op
= O_constant
;
3159 tmp
.X_add_number
= (offsetT
) -1;
3160 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3161 reg
, 0, (int) BFD_RELOC_LO16
);
3165 macro_build ((char *) NULL
, counter
, NULL
,
3166 (bit
>= 32) ? "dsll32" : "dsll",
3168 (bit
>= 32) ? bit
- 32 : bit
);
3170 macro_build ((char *) NULL
, counter
, NULL
,
3171 (shift
>= 32) ? "dsrl32" : "dsrl",
3173 (shift
>= 32) ? shift
- 32 : shift
);
3178 /* Sign extend hi32 before calling load_register, because we can
3179 generally get better code when we load a sign extended value. */
3180 if ((hi32
.X_add_number
& 0x80000000) != 0)
3181 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3182 load_register (counter
, reg
, &hi32
, 0);
3185 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3189 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3198 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3200 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3201 (int) BFD_RELOC_HI16
);
3202 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3209 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3214 mid16
.X_add_number
>>= 16;
3215 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3216 freg
, (int) BFD_RELOC_LO16
);
3217 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3221 if ((lo32
.X_add_number
& 0xffff) != 0)
3222 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3223 (int) BFD_RELOC_LO16
);
3226 /* Load an address into a register. */
3229 load_address (counter
, reg
, ep
)
3236 if (ep
->X_op
!= O_constant
3237 && ep
->X_op
!= O_symbol
)
3239 as_bad (_("expression too complex"));
3240 ep
->X_op
= O_constant
;
3243 if (ep
->X_op
== O_constant
)
3245 load_register (counter
, reg
, ep
, 0);
3249 if (mips_pic
== NO_PIC
)
3251 /* If this is a reference to a GP relative symbol, we want
3252 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3254 lui $reg,<sym> (BFD_RELOC_HI16_S)
3255 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3256 If we have an addend, we always use the latter form. */
3257 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3258 || nopic_need_relax (ep
->X_add_symbol
, 1))
3263 macro_build ((char *) NULL
, counter
, ep
,
3264 ((bfd_arch_bits_per_address (stdoutput
) == 32
3265 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3266 ? "addiu" : "daddiu"),
3267 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3268 p
= frag_var (rs_machine_dependent
, 8, 0,
3269 RELAX_ENCODE (4, 8, 0, 4, 0,
3270 mips_opts
.warn_about_macros
),
3271 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3273 macro_build_lui (p
, counter
, ep
, reg
);
3276 macro_build (p
, counter
, ep
,
3277 ((bfd_arch_bits_per_address (stdoutput
) == 32
3278 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3279 ? "addiu" : "daddiu"),
3280 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3282 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3286 /* If this is a reference to an external symbol, we want
3287 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3289 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3291 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3292 If there is a constant, it must be added in after. */
3293 ex
.X_add_number
= ep
->X_add_number
;
3294 ep
->X_add_number
= 0;
3296 macro_build ((char *) NULL
, counter
, ep
,
3297 ((bfd_arch_bits_per_address (stdoutput
) == 32
3298 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3300 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3301 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3302 p
= frag_var (rs_machine_dependent
, 4, 0,
3303 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3304 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3305 macro_build (p
, counter
, ep
,
3306 ((bfd_arch_bits_per_address (stdoutput
) == 32
3307 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3308 ? "addiu" : "daddiu"),
3309 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3310 if (ex
.X_add_number
!= 0)
3312 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3313 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3314 ex
.X_op
= O_constant
;
3315 macro_build ((char *) NULL
, counter
, &ex
,
3316 ((bfd_arch_bits_per_address (stdoutput
) == 32
3317 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3318 ? "addiu" : "daddiu"),
3319 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3322 else if (mips_pic
== SVR4_PIC
)
3327 /* This is the large GOT case. If this is a reference to an
3328 external symbol, we want
3329 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3331 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3332 Otherwise, for a reference to a local symbol, we want
3333 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3335 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3336 If there is a constant, it must be added in after. */
3337 ex
.X_add_number
= ep
->X_add_number
;
3338 ep
->X_add_number
= 0;
3339 if (reg_needs_delay (GP
))
3344 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3345 (int) BFD_RELOC_MIPS_GOT_HI16
);
3346 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3347 ((bfd_arch_bits_per_address (stdoutput
) == 32
3348 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3349 ? "addu" : "daddu"),
3350 "d,v,t", reg
, reg
, GP
);
3351 macro_build ((char *) NULL
, counter
, ep
,
3352 ((bfd_arch_bits_per_address (stdoutput
) == 32
3353 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3355 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3356 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3357 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3358 mips_opts
.warn_about_macros
),
3359 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3362 /* We need a nop before loading from $gp. This special
3363 check is required because the lui which starts the main
3364 instruction stream does not refer to $gp, and so will not
3365 insert the nop which may be required. */
3366 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3369 macro_build (p
, counter
, ep
,
3370 ((bfd_arch_bits_per_address (stdoutput
) == 32
3371 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3373 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3375 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3377 macro_build (p
, counter
, ep
,
3378 ((bfd_arch_bits_per_address (stdoutput
) == 32
3379 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3380 ? "addiu" : "daddiu"),
3381 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3382 if (ex
.X_add_number
!= 0)
3384 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3385 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3386 ex
.X_op
= O_constant
;
3387 macro_build ((char *) NULL
, counter
, &ex
,
3388 ((bfd_arch_bits_per_address (stdoutput
) == 32
3389 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3390 ? "addiu" : "daddiu"),
3391 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3394 else if (mips_pic
== EMBEDDED_PIC
)
3397 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3399 macro_build ((char *) NULL
, counter
, ep
,
3400 ((bfd_arch_bits_per_address (stdoutput
) == 32
3401 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3402 ? "addiu" : "daddiu"),
3403 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3411 * This routine implements the seemingly endless macro or synthesized
3412 * instructions and addressing modes in the mips assembly language. Many
3413 * of these macros are simple and are similar to each other. These could
3414 * probably be handled by some kind of table or grammer aproach instead of
3415 * this verbose method. Others are not simple macros but are more like
3416 * optimizing code generation.
3417 * One interesting optimization is when several store macros appear
3418 * consecutivly that would load AT with the upper half of the same address.
3419 * The ensuing load upper instructions are ommited. This implies some kind
3420 * of global optimization. We currently only optimize within a single macro.
3421 * For many of the load and store macros if the address is specified as a
3422 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3423 * first load register 'at' with zero and use it as the base register. The
3424 * mips assembler simply uses register $zero. Just one tiny optimization
3429 struct mips_cl_insn
*ip
;
3431 register int treg
, sreg
, dreg
, breg
;
3447 bfd_reloc_code_real_type r
;
3449 int hold_mips_optimize
;
3451 assert (! mips_opts
.mips16
);
3453 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3454 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3455 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3456 mask
= ip
->insn_mo
->mask
;
3458 expr1
.X_op
= O_constant
;
3459 expr1
.X_op_symbol
= NULL
;
3460 expr1
.X_add_symbol
= NULL
;
3461 expr1
.X_add_number
= 1;
3473 mips_emit_delays (true);
3474 ++mips_opts
.noreorder
;
3475 mips_any_noreorder
= 1;
3477 expr1
.X_add_number
= 8;
3478 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3480 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3482 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3483 macro_build ((char *) NULL
, &icnt
, NULL
,
3484 dbl
? "dsub" : "sub",
3485 "d,v,t", dreg
, 0, sreg
);
3487 --mips_opts
.noreorder
;
3508 if (imm_expr
.X_op
== O_constant
3509 && imm_expr
.X_add_number
>= -0x8000
3510 && imm_expr
.X_add_number
< 0x8000)
3512 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3513 (int) BFD_RELOC_LO16
);
3516 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3517 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3536 if (imm_expr
.X_op
== O_constant
3537 && imm_expr
.X_add_number
>= 0
3538 && imm_expr
.X_add_number
< 0x10000)
3540 if (mask
!= M_NOR_I
)
3541 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3542 sreg
, (int) BFD_RELOC_LO16
);
3545 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3546 treg
, sreg
, (int) BFD_RELOC_LO16
);
3547 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3553 load_register (&icnt
, AT
, &imm_expr
, 0);
3554 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3571 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3577 load_register (&icnt
, AT
, &imm_expr
, 0);
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3587 likely
? "bgezl" : "bgez",
3593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3594 likely
? "blezl" : "blez",
3598 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3600 likely
? "beql" : "beq",
3607 /* check for > max integer */
3608 maxnum
= 0x7fffffff;
3609 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3616 if (imm_expr
.X_op
== O_constant
3617 && imm_expr
.X_add_number
>= maxnum
3618 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3621 /* result is always false */
3624 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3625 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3629 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3635 if (imm_expr
.X_op
!= O_constant
)
3636 as_bad (_("Unsupported large constant"));
3637 imm_expr
.X_add_number
++;
3641 if (mask
== M_BGEL_I
)
3643 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3645 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3646 likely
? "bgezl" : "bgez",
3650 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3653 likely
? "bgtzl" : "bgtz",
3657 maxnum
= 0x7fffffff;
3658 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3665 maxnum
= - maxnum
- 1;
3666 if (imm_expr
.X_op
== O_constant
3667 && imm_expr
.X_add_number
<= maxnum
3668 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3671 /* result is always true */
3672 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3673 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3676 set_at (&icnt
, sreg
, 0);
3677 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3678 likely
? "beql" : "beq",
3689 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3690 likely
? "beql" : "beq",
3694 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3696 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3697 likely
? "beql" : "beq",
3705 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3706 && imm_expr
.X_op
== O_constant
3707 && imm_expr
.X_add_number
== 0xffffffff))
3709 if (imm_expr
.X_op
!= O_constant
)
3710 as_bad (_("Unsupported large constant"));
3711 imm_expr
.X_add_number
++;
3715 if (mask
== M_BGEUL_I
)
3717 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3719 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3722 likely
? "bnel" : "bne",
3726 set_at (&icnt
, sreg
, 1);
3727 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3728 likely
? "beql" : "beq",
3737 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3738 likely
? "bgtzl" : "bgtz",
3744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3745 likely
? "bltzl" : "bltz",
3749 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "bnel" : "bne",
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3761 likely
? "bnel" : "bne",
3767 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3769 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3770 likely
? "bnel" : "bne",
3779 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3780 likely
? "blezl" : "blez",
3786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3787 likely
? "bgezl" : "bgez",
3791 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3793 likely
? "beql" : "beq",
3800 maxnum
= 0x7fffffff;
3801 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3808 if (imm_expr
.X_op
== O_constant
3809 && imm_expr
.X_add_number
>= maxnum
3810 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3812 if (imm_expr
.X_op
!= O_constant
)
3813 as_bad (_("Unsupported large constant"));
3814 imm_expr
.X_add_number
++;
3818 if (mask
== M_BLTL_I
)
3820 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3822 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3823 likely
? "bltzl" : "bltz",
3827 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3830 likely
? "blezl" : "blez",
3834 set_at (&icnt
, sreg
, 0);
3835 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3836 likely
? "bnel" : "bne",
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 likely
? "beql" : "beq",
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3855 likely
? "beql" : "beq",
3863 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3864 && imm_expr
.X_op
== O_constant
3865 && imm_expr
.X_add_number
== 0xffffffff))
3867 if (imm_expr
.X_op
!= O_constant
)
3868 as_bad (_("Unsupported large constant"));
3869 imm_expr
.X_add_number
++;
3873 if (mask
== M_BLTUL_I
)
3875 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3877 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3880 likely
? "beql" : "beq",
3884 set_at (&icnt
, sreg
, 1);
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3886 likely
? "bnel" : "bne",
3895 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3896 likely
? "bltzl" : "bltz",
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "bgtzl" : "bgtz",
3907 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3909 likely
? "bnel" : "bne",
3920 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3921 likely
? "bnel" : "bne",
3925 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3927 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3928 likely
? "bnel" : "bne",
3944 as_warn (_("Divide by zero."));
3946 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3948 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3952 mips_emit_delays (true);
3953 ++mips_opts
.noreorder
;
3954 mips_any_noreorder
= 1;
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3958 macro_build ((char *) NULL
, &icnt
, NULL
,
3959 dbl
? "ddiv" : "div",
3960 "z,s,t", sreg
, treg
);
3964 expr1
.X_add_number
= 8;
3965 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3966 macro_build ((char *) NULL
, &icnt
, NULL
,
3967 dbl
? "ddiv" : "div",
3968 "z,s,t", sreg
, treg
);
3969 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3971 expr1
.X_add_number
= -1;
3972 macro_build ((char *) NULL
, &icnt
, &expr1
,
3973 dbl
? "daddiu" : "addiu",
3974 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3975 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3976 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3979 expr1
.X_add_number
= 1;
3980 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3981 (int) BFD_RELOC_LO16
);
3982 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3987 expr1
.X_add_number
= 0x80000000;
3988 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3989 (int) BFD_RELOC_HI16
);
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3994 /* We want to close the noreorder block as soon as possible, so
3995 that later insns are available for delay slot filling. */
3996 --mips_opts
.noreorder
;
4000 expr1
.X_add_number
= 8;
4001 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4002 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4004 /* We want to close the noreorder block as soon as possible, so
4005 that later insns are available for delay slot filling. */
4006 --mips_opts
.noreorder
;
4008 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4010 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4049 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4051 as_warn (_("Divide by zero."));
4053 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4055 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4058 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4060 if (strcmp (s2
, "mflo") == 0)
4061 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4067 if (imm_expr
.X_op
== O_constant
4068 && imm_expr
.X_add_number
== -1
4069 && s
[strlen (s
) - 1] != 'u')
4071 if (strcmp (s2
, "mflo") == 0)
4074 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4077 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4081 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4085 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4086 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4087 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4106 mips_emit_delays (true);
4107 ++mips_opts
.noreorder
;
4108 mips_any_noreorder
= 1;
4111 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4112 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4113 /* We want to close the noreorder block as soon as possible, so
4114 that later insns are available for delay slot filling. */
4115 --mips_opts
.noreorder
;
4119 expr1
.X_add_number
= 8;
4120 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4121 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4123 /* We want to close the noreorder block as soon as possible, so
4124 that later insns are available for delay slot filling. */
4125 --mips_opts
.noreorder
;
4126 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4128 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4134 /* Load the address of a symbol into a register. If breg is not
4135 zero, we then add a base register to it. */
4137 /* When generating embedded PIC code, we permit expressions of
4140 where bar is an address in the .text section. These are used
4141 when getting the addresses of functions. We don't permit
4142 X_add_number to be non-zero, because if the symbol is
4143 external the relaxing code needs to know that any addend is
4144 purely the offset to X_op_symbol. */
4145 if (mips_pic
== EMBEDDED_PIC
4146 && offset_expr
.X_op
== O_subtract
4147 && now_seg
== text_section
4148 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4149 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4150 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4152 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4156 && offset_expr
.X_add_number
== 0)
4158 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4159 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 ((bfd_arch_bits_per_address (stdoutput
) == 32
4162 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4163 ? "addiu" : "daddiu"),
4164 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4168 if (offset_expr
.X_op
!= O_symbol
4169 && offset_expr
.X_op
!= O_constant
)
4171 as_bad (_("expression too complex"));
4172 offset_expr
.X_op
= O_constant
;
4186 if (offset_expr
.X_op
== O_constant
)
4187 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4188 else if (mips_pic
== NO_PIC
)
4190 /* If this is a reference to an GP relative symbol, we want
4191 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4193 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4194 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4195 If we have a constant, we need two instructions anyhow,
4196 so we may as well always use the latter form. */
4197 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4198 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4204 ((bfd_arch_bits_per_address (stdoutput
) == 32
4205 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4206 ? "addiu" : "daddiu"),
4207 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4208 p
= frag_var (rs_machine_dependent
, 8, 0,
4209 RELAX_ENCODE (4, 8, 0, 4, 0,
4210 mips_opts
.warn_about_macros
),
4211 offset_expr
.X_add_symbol
, (offsetT
) 0,
4214 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4217 macro_build (p
, &icnt
, &offset_expr
,
4218 ((bfd_arch_bits_per_address (stdoutput
) == 32
4219 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4220 ? "addiu" : "daddiu"),
4221 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4223 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4225 /* If this is a reference to an external symbol, and there
4226 is no constant, we want
4227 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4228 For a local symbol, we want
4229 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4231 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4233 If we have a small constant, and this is a reference to
4234 an external symbol, we want
4235 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4237 addiu $tempreg,$tempreg,<constant>
4238 For a local symbol, we want the same instruction
4239 sequence, but we output a BFD_RELOC_LO16 reloc on the
4242 If we have a large constant, and this is a reference to
4243 an external symbol, we want
4244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4245 lui $at,<hiconstant>
4246 addiu $at,$at,<loconstant>
4247 addu $tempreg,$tempreg,$at
4248 For a local symbol, we want the same instruction
4249 sequence, but we output a BFD_RELOC_LO16 reloc on the
4250 addiu instruction. */
4251 expr1
.X_add_number
= offset_expr
.X_add_number
;
4252 offset_expr
.X_add_number
= 0;
4254 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4256 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4257 if (expr1
.X_add_number
== 0)
4265 /* We're going to put in an addu instruction using
4266 tempreg, so we may as well insert the nop right
4268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4272 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4273 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4275 ? mips_opts
.warn_about_macros
4277 offset_expr
.X_add_symbol
, (offsetT
) 0,
4281 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4284 macro_build (p
, &icnt
, &expr1
,
4285 ((bfd_arch_bits_per_address (stdoutput
) == 32
4286 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4287 ? "addiu" : "daddiu"),
4288 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4289 /* FIXME: If breg == 0, and the next instruction uses
4290 $tempreg, then if this variant case is used an extra
4291 nop will be generated. */
4293 else if (expr1
.X_add_number
>= -0x8000
4294 && expr1
.X_add_number
< 0x8000)
4296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4298 macro_build ((char *) NULL
, &icnt
, &expr1
,
4299 ((bfd_arch_bits_per_address (stdoutput
) == 32
4300 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4301 ? "addiu" : "daddiu"),
4302 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4303 (void) frag_var (rs_machine_dependent
, 0, 0,
4304 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4305 offset_expr
.X_add_symbol
, (offsetT
) 0,
4312 /* If we are going to add in a base register, and the
4313 target register and the base register are the same,
4314 then we are using AT as a temporary register. Since
4315 we want to load the constant into AT, we add our
4316 current AT (from the global offset table) and the
4317 register into the register now, and pretend we were
4318 not using a base register. */
4323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4326 ((bfd_arch_bits_per_address (stdoutput
) == 32
4327 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4328 ? "addu" : "daddu"),
4329 "d,v,t", treg
, AT
, breg
);
4335 /* Set mips_optimize around the lui instruction to avoid
4336 inserting an unnecessary nop after the lw. */
4337 hold_mips_optimize
= mips_optimize
;
4339 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4340 mips_optimize
= hold_mips_optimize
;
4342 macro_build ((char *) NULL
, &icnt
, &expr1
,
4343 ((bfd_arch_bits_per_address (stdoutput
) == 32
4344 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4345 ? "addiu" : "daddiu"),
4346 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4348 ((bfd_arch_bits_per_address (stdoutput
) == 32
4349 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4350 ? "addu" : "daddu"),
4351 "d,v,t", tempreg
, tempreg
, AT
);
4352 (void) frag_var (rs_machine_dependent
, 0, 0,
4353 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4354 offset_expr
.X_add_symbol
, (offsetT
) 0,
4359 else if (mips_pic
== SVR4_PIC
)
4363 /* This is the large GOT case. If this is a reference to an
4364 external symbol, and there is no constant, we want
4365 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4366 addu $tempreg,$tempreg,$gp
4367 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4368 For a local symbol, we want
4369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4371 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4373 If we have a small constant, and this is a reference to
4374 an external symbol, we want
4375 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4376 addu $tempreg,$tempreg,$gp
4377 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4379 addiu $tempreg,$tempreg,<constant>
4380 For a local symbol, we want
4381 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4383 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4385 If we have a large constant, and this is a reference to
4386 an external symbol, we want
4387 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4388 addu $tempreg,$tempreg,$gp
4389 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4390 lui $at,<hiconstant>
4391 addiu $at,$at,<loconstant>
4392 addu $tempreg,$tempreg,$at
4393 For a local symbol, we want
4394 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4395 lui $at,<hiconstant>
4396 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4397 addu $tempreg,$tempreg,$at
4399 expr1
.X_add_number
= offset_expr
.X_add_number
;
4400 offset_expr
.X_add_number
= 0;
4402 if (reg_needs_delay (GP
))
4406 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4407 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4408 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4409 ((bfd_arch_bits_per_address (stdoutput
) == 32
4410 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4411 ? "addu" : "daddu"),
4412 "d,v,t", tempreg
, tempreg
, GP
);
4413 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4415 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4417 if (expr1
.X_add_number
== 0)
4425 /* We're going to put in an addu instruction using
4426 tempreg, so we may as well insert the nop right
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4433 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4434 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4437 ? mips_opts
.warn_about_macros
4439 offset_expr
.X_add_symbol
, (offsetT
) 0,
4442 else if (expr1
.X_add_number
>= -0x8000
4443 && expr1
.X_add_number
< 0x8000)
4445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4447 macro_build ((char *) NULL
, &icnt
, &expr1
,
4448 ((bfd_arch_bits_per_address (stdoutput
) == 32
4449 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4450 ? "addiu" : "daddiu"),
4451 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4453 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4454 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4456 ? mips_opts
.warn_about_macros
4458 offset_expr
.X_add_symbol
, (offsetT
) 0,
4465 /* If we are going to add in a base register, and the
4466 target register and the base register are the same,
4467 then we are using AT as a temporary register. Since
4468 we want to load the constant into AT, we add our
4469 current AT (from the global offset table) and the
4470 register into the register now, and pretend we were
4471 not using a base register. */
4479 assert (tempreg
== AT
);
4480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4483 ((bfd_arch_bits_per_address (stdoutput
) == 32
4484 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4485 ? "addu" : "daddu"),
4486 "d,v,t", treg
, AT
, breg
);
4491 /* Set mips_optimize around the lui instruction to avoid
4492 inserting an unnecessary nop after the lw. */
4493 hold_mips_optimize
= mips_optimize
;
4495 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4496 mips_optimize
= hold_mips_optimize
;
4498 macro_build ((char *) NULL
, &icnt
, &expr1
,
4499 ((bfd_arch_bits_per_address (stdoutput
) == 32
4500 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4501 ? "addiu" : "daddiu"),
4502 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4504 ((bfd_arch_bits_per_address (stdoutput
) == 32
4505 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4506 ? "addu" : "daddu"),
4507 "d,v,t", dreg
, dreg
, AT
);
4509 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4510 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4513 ? mips_opts
.warn_about_macros
4515 offset_expr
.X_add_symbol
, (offsetT
) 0,
4523 /* This is needed because this instruction uses $gp, but
4524 the first instruction on the main stream does not. */
4525 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4528 macro_build (p
, &icnt
, &offset_expr
,
4530 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4532 if (expr1
.X_add_number
>= -0x8000
4533 && expr1
.X_add_number
< 0x8000)
4535 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4537 macro_build (p
, &icnt
, &expr1
,
4538 ((bfd_arch_bits_per_address (stdoutput
) == 32
4539 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4540 ? "addiu" : "daddiu"),
4541 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4542 /* FIXME: If add_number is 0, and there was no base
4543 register, the external symbol case ended with a load,
4544 so if the symbol turns out to not be external, and
4545 the next instruction uses tempreg, an unnecessary nop
4546 will be inserted. */
4552 /* We must add in the base register now, as in the
4553 external symbol case. */
4554 assert (tempreg
== AT
);
4555 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4557 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4558 ((bfd_arch_bits_per_address (stdoutput
) == 32
4559 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4560 ? "addu" : "daddu"),
4561 "d,v,t", treg
, AT
, breg
);
4564 /* We set breg to 0 because we have arranged to add
4565 it in in both cases. */
4569 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4571 macro_build (p
, &icnt
, &expr1
,
4572 ((bfd_arch_bits_per_address (stdoutput
) == 32
4573 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4574 ? "addiu" : "daddiu"),
4575 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4577 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4578 ((bfd_arch_bits_per_address (stdoutput
) == 32
4579 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4580 ? "addu" : "daddu"),
4581 "d,v,t", tempreg
, tempreg
, AT
);
4585 else if (mips_pic
== EMBEDDED_PIC
)
4588 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4591 ((bfd_arch_bits_per_address (stdoutput
) == 32
4592 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4593 ? "addiu" : "daddiu"),
4594 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4600 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4601 ((bfd_arch_bits_per_address (stdoutput
) == 32
4602 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4603 ? "addu" : "daddu"),
4604 "d,v,t", treg
, tempreg
, breg
);
4612 /* The j instruction may not be used in PIC code, since it
4613 requires an absolute address. We convert it to a b
4615 if (mips_pic
== NO_PIC
)
4616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4621 /* The jal instructions must be handled as macros because when
4622 generating PIC code they expand to multi-instruction
4623 sequences. Normally they are simple instructions. */
4628 if (mips_pic
== NO_PIC
4629 || mips_pic
== EMBEDDED_PIC
)
4630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4632 else if (mips_pic
== SVR4_PIC
)
4634 if (sreg
!= PIC_CALL_REG
)
4635 as_warn (_("MIPS PIC call to register other than $25"));
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4639 if (mips_cprestore_offset
< 0)
4640 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4643 expr1
.X_add_number
= mips_cprestore_offset
;
4644 macro_build ((char *) NULL
, &icnt
, &expr1
,
4645 ((bfd_arch_bits_per_address (stdoutput
) == 32
4646 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4648 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4657 if (mips_pic
== NO_PIC
)
4658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4659 else if (mips_pic
== SVR4_PIC
)
4661 /* If this is a reference to an external symbol, and we are
4662 using a small GOT, we want
4663 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4667 lw $gp,cprestore($sp)
4668 The cprestore value is set using the .cprestore
4669 pseudo-op. If we are using a big GOT, we want
4670 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4672 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4676 lw $gp,cprestore($sp)
4677 If the symbol is not external, we want
4678 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4680 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4683 lw $gp,cprestore($sp) */
4687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4688 ((bfd_arch_bits_per_address (stdoutput
) == 32
4689 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4691 "t,o(b)", PIC_CALL_REG
,
4692 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4695 p
= frag_var (rs_machine_dependent
, 4, 0,
4696 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4697 offset_expr
.X_add_symbol
, (offsetT
) 0,
4704 if (reg_needs_delay (GP
))
4708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4709 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4711 ((bfd_arch_bits_per_address (stdoutput
) == 32
4712 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4713 ? "addu" : "daddu"),
4714 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4715 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4716 ((bfd_arch_bits_per_address (stdoutput
) == 32
4717 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4719 "t,o(b)", PIC_CALL_REG
,
4720 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4721 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4723 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4724 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4726 offset_expr
.X_add_symbol
, (offsetT
) 0,
4730 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4733 macro_build (p
, &icnt
, &offset_expr
,
4734 ((bfd_arch_bits_per_address (stdoutput
) == 32
4735 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4737 "t,o(b)", PIC_CALL_REG
,
4738 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4740 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4743 macro_build (p
, &icnt
, &offset_expr
,
4744 ((bfd_arch_bits_per_address (stdoutput
) == 32
4745 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4746 ? "addiu" : "daddiu"),
4747 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4748 (int) BFD_RELOC_LO16
);
4749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4750 "jalr", "s", PIC_CALL_REG
);
4751 if (mips_cprestore_offset
< 0)
4752 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4755 if (mips_opts
.noreorder
)
4756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4758 expr1
.X_add_number
= mips_cprestore_offset
;
4759 macro_build ((char *) NULL
, &icnt
, &expr1
,
4760 ((bfd_arch_bits_per_address (stdoutput
) == 32
4761 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4763 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4767 else if (mips_pic
== EMBEDDED_PIC
)
4769 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4770 /* The linker may expand the call to a longer sequence which
4771 uses $at, so we must break rather than return. */
4796 /* Itbl support may require additional care here. */
4801 /* Itbl support may require additional care here. */
4806 /* Itbl support may require additional care here. */
4811 /* Itbl support may require additional care here. */
4823 if (mips_cpu
== 4650)
4825 as_bad (_("opcode not supported on this processor"));
4829 /* Itbl support may require additional care here. */
4834 /* Itbl support may require additional care here. */
4839 /* Itbl support may require additional care here. */
4859 if (breg
== treg
|| coproc
|| lr
)
4881 /* Itbl support may require additional care here. */
4886 /* Itbl support may require additional care here. */
4891 /* Itbl support may require additional care here. */
4896 /* Itbl support may require additional care here. */
4912 if (mips_cpu
== 4650)
4914 as_bad (_("opcode not supported on this processor"));
4919 /* Itbl support may require additional care here. */
4923 /* Itbl support may require additional care here. */
4928 /* Itbl support may require additional care here. */
4940 /* Itbl support may require additional care here. */
4941 if (mask
== M_LWC1_AB
4942 || mask
== M_SWC1_AB
4943 || mask
== M_LDC1_AB
4944 || mask
== M_SDC1_AB
4953 if (offset_expr
.X_op
!= O_constant
4954 && offset_expr
.X_op
!= O_symbol
)
4956 as_bad (_("expression too complex"));
4957 offset_expr
.X_op
= O_constant
;
4960 /* A constant expression in PIC code can be handled just as it
4961 is in non PIC code. */
4962 if (mips_pic
== NO_PIC
4963 || offset_expr
.X_op
== O_constant
)
4965 /* If this is a reference to a GP relative symbol, and there
4966 is no base register, we want
4967 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4968 Otherwise, if there is no base register, we want
4969 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4970 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4971 If we have a constant, we need two instructions anyhow,
4972 so we always use the latter form.
4974 If we have a base register, and this is a reference to a
4975 GP relative symbol, we want
4976 addu $tempreg,$breg,$gp
4977 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4979 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4980 addu $tempreg,$tempreg,$breg
4981 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4982 With a constant we always use the latter case. */
4985 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4986 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4992 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4993 p
= frag_var (rs_machine_dependent
, 8, 0,
4994 RELAX_ENCODE (4, 8, 0, 4, 0,
4995 (mips_opts
.warn_about_macros
4997 && mips_opts
.noat
))),
4998 offset_expr
.X_add_symbol
, (offsetT
) 0,
5002 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5005 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5006 (int) BFD_RELOC_LO16
, tempreg
);
5010 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5011 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5017 ((bfd_arch_bits_per_address (stdoutput
) == 32
5018 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5019 ? "addu" : "daddu"),
5020 "d,v,t", tempreg
, breg
, GP
);
5021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5022 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5023 p
= frag_var (rs_machine_dependent
, 12, 0,
5024 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5025 offset_expr
.X_add_symbol
, (offsetT
) 0,
5028 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5031 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5032 ((bfd_arch_bits_per_address (stdoutput
) == 32
5033 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5034 ? "addu" : "daddu"),
5035 "d,v,t", tempreg
, tempreg
, breg
);
5038 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5039 (int) BFD_RELOC_LO16
, tempreg
);
5042 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5044 /* If this is a reference to an external symbol, we want
5045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5047 <op> $treg,0($tempreg)
5049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5051 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5052 <op> $treg,0($tempreg)
5053 If there is a base register, we add it to $tempreg before
5054 the <op>. If there is a constant, we stick it in the
5055 <op> instruction. We don't handle constants larger than
5056 16 bits, because we have no way to load the upper 16 bits
5057 (actually, we could handle them for the subset of cases
5058 in which we are not using $at). */
5059 assert (offset_expr
.X_op
== O_symbol
);
5060 expr1
.X_add_number
= offset_expr
.X_add_number
;
5061 offset_expr
.X_add_number
= 0;
5062 if (expr1
.X_add_number
< -0x8000
5063 || expr1
.X_add_number
>= 0x8000)
5064 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5066 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5067 ((bfd_arch_bits_per_address (stdoutput
) == 32
5068 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5070 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5072 p
= frag_var (rs_machine_dependent
, 4, 0,
5073 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5074 offset_expr
.X_add_symbol
, (offsetT
) 0,
5076 macro_build (p
, &icnt
, &offset_expr
,
5077 ((bfd_arch_bits_per_address (stdoutput
) == 32
5078 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5079 ? "addiu" : "daddiu"),
5080 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5083 ((bfd_arch_bits_per_address (stdoutput
) == 32
5084 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5085 ? "addu" : "daddu"),
5086 "d,v,t", tempreg
, tempreg
, breg
);
5087 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5088 (int) BFD_RELOC_LO16
, tempreg
);
5090 else if (mips_pic
== SVR4_PIC
)
5094 /* If this is a reference to an external symbol, we want
5095 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5096 addu $tempreg,$tempreg,$gp
5097 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5098 <op> $treg,0($tempreg)
5100 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5102 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5103 <op> $treg,0($tempreg)
5104 If there is a base register, we add it to $tempreg before
5105 the <op>. If there is a constant, we stick it in the
5106 <op> instruction. We don't handle constants larger than
5107 16 bits, because we have no way to load the upper 16 bits
5108 (actually, we could handle them for the subset of cases
5109 in which we are not using $at). */
5110 assert (offset_expr
.X_op
== O_symbol
);
5111 expr1
.X_add_number
= offset_expr
.X_add_number
;
5112 offset_expr
.X_add_number
= 0;
5113 if (expr1
.X_add_number
< -0x8000
5114 || expr1
.X_add_number
>= 0x8000)
5115 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5116 if (reg_needs_delay (GP
))
5121 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5122 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5123 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5124 ((bfd_arch_bits_per_address (stdoutput
) == 32
5125 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5126 ? "addu" : "daddu"),
5127 "d,v,t", tempreg
, tempreg
, GP
);
5128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5129 ((bfd_arch_bits_per_address (stdoutput
) == 32
5130 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5132 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5134 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5135 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5136 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5139 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5142 macro_build (p
, &icnt
, &offset_expr
,
5143 ((bfd_arch_bits_per_address (stdoutput
) == 32
5144 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5146 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5148 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5150 macro_build (p
, &icnt
, &offset_expr
,
5151 ((bfd_arch_bits_per_address (stdoutput
) == 32
5152 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5153 ? "addiu" : "daddiu"),
5154 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5157 ((bfd_arch_bits_per_address (stdoutput
) == 32
5158 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5159 ? "addu" : "daddu"),
5160 "d,v,t", tempreg
, tempreg
, breg
);
5161 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5162 (int) BFD_RELOC_LO16
, tempreg
);
5164 else if (mips_pic
== EMBEDDED_PIC
)
5166 /* If there is no base register, we want
5167 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5168 If there is a base register, we want
5169 addu $tempreg,$breg,$gp
5170 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5172 assert (offset_expr
.X_op
== O_symbol
);
5175 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5176 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5182 ((bfd_arch_bits_per_address (stdoutput
) == 32
5183 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5184 ? "addu" : "daddu"),
5185 "d,v,t", tempreg
, breg
, GP
);
5186 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5187 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5200 load_register (&icnt
, treg
, &imm_expr
, 0);
5204 load_register (&icnt
, treg
, &imm_expr
, 1);
5208 if (imm_expr
.X_op
== O_constant
)
5210 load_register (&icnt
, AT
, &imm_expr
, 0);
5211 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5212 "mtc1", "t,G", AT
, treg
);
5217 assert (offset_expr
.X_op
== O_symbol
5218 && strcmp (segment_name (S_GET_SEGMENT
5219 (offset_expr
.X_add_symbol
)),
5221 && offset_expr
.X_add_number
== 0);
5222 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5223 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5228 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5229 the entire value, and in mips1 mode it is the high order 32
5230 bits of the value and the low order 32 bits are either zero
5231 or in offset_expr. */
5232 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5234 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5235 load_register (&icnt
, treg
, &imm_expr
, 1);
5240 if (target_big_endian
)
5252 load_register (&icnt
, hreg
, &imm_expr
, 0);
5255 if (offset_expr
.X_op
== O_absent
)
5256 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5260 assert (offset_expr
.X_op
== O_constant
);
5261 load_register (&icnt
, lreg
, &offset_expr
, 0);
5268 /* We know that sym is in the .rdata section. First we get the
5269 upper 16 bits of the address. */
5270 if (mips_pic
== NO_PIC
)
5272 /* FIXME: This won't work for a 64 bit address. */
5273 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5275 else if (mips_pic
== SVR4_PIC
)
5277 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5278 ((bfd_arch_bits_per_address (stdoutput
) == 32
5279 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5281 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5283 else if (mips_pic
== EMBEDDED_PIC
)
5285 /* For embedded PIC we pick up the entire address off $gp in
5286 a single instruction. */
5287 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5288 ((bfd_arch_bits_per_address (stdoutput
) == 32
5289 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5290 ? "addiu" : "daddiu"),
5291 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5292 offset_expr
.X_op
= O_constant
;
5293 offset_expr
.X_add_number
= 0;
5298 /* Now we load the register(s). */
5299 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5301 treg
, (int) BFD_RELOC_LO16
, AT
);
5304 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5305 treg
, (int) BFD_RELOC_LO16
, AT
);
5308 /* FIXME: How in the world do we deal with the possible
5310 offset_expr
.X_add_number
+= 4;
5311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5312 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5316 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5317 does not become a variant frag. */
5318 frag_wane (frag_now
);
5324 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5325 the entire value, and in mips1 mode it is the high order 32
5326 bits of the value and the low order 32 bits are either zero
5327 or in offset_expr. */
5328 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5330 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5331 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5333 "dmtc1", "t,S", AT
, treg
);
5336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5337 "mtc1", "t,G", AT
, treg
+ 1);
5338 if (offset_expr
.X_op
== O_absent
)
5339 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5340 "mtc1", "t,G", 0, treg
);
5343 assert (offset_expr
.X_op
== O_constant
);
5344 load_register (&icnt
, AT
, &offset_expr
, 0);
5345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5346 "mtc1", "t,G", AT
, treg
);
5352 assert (offset_expr
.X_op
== O_symbol
5353 && offset_expr
.X_add_number
== 0);
5354 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5355 if (strcmp (s
, ".lit8") == 0)
5357 if (mips_opts
.isa
!= 1)
5359 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5360 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5364 r
= BFD_RELOC_MIPS_LITERAL
;
5369 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5370 if (mips_pic
== SVR4_PIC
)
5371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5372 ((bfd_arch_bits_per_address (stdoutput
) == 32
5373 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5375 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5378 /* FIXME: This won't work for a 64 bit address. */
5379 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5382 if (mips_opts
.isa
!= 1)
5384 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5385 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5387 /* To avoid confusion in tc_gen_reloc, we must ensure
5388 that this does not become a variant frag. */
5389 frag_wane (frag_now
);
5400 if (mips_cpu
== 4650)
5402 as_bad (_("opcode not supported on this processor"));
5405 /* Even on a big endian machine $fn comes before $fn+1. We have
5406 to adjust when loading from memory. */
5409 assert (mips_opts
.isa
== 1);
5410 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5411 target_big_endian
? treg
+ 1 : treg
,
5413 /* FIXME: A possible overflow which I don't know how to deal
5415 offset_expr
.X_add_number
+= 4;
5416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5417 target_big_endian
? treg
: treg
+ 1,
5420 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5421 does not become a variant frag. */
5422 frag_wane (frag_now
);
5431 * The MIPS assembler seems to check for X_add_number not
5432 * being double aligned and generating:
5435 * addiu at,at,%lo(foo+1)
5438 * But, the resulting address is the same after relocation so why
5439 * generate the extra instruction?
5441 if (mips_cpu
== 4650)
5443 as_bad (_("opcode not supported on this processor"));
5446 /* Itbl support may require additional care here. */
5448 if (mips_opts
.isa
!= 1)
5459 if (mips_cpu
== 4650)
5461 as_bad (_("opcode not supported on this processor"));
5465 if (mips_opts
.isa
!= 1)
5473 /* Itbl support may require additional care here. */
5478 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5489 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5499 if (offset_expr
.X_op
!= O_symbol
5500 && offset_expr
.X_op
!= O_constant
)
5502 as_bad (_("expression too complex"));
5503 offset_expr
.X_op
= O_constant
;
5506 /* Even on a big endian machine $fn comes before $fn+1. We have
5507 to adjust when loading from memory. We set coproc if we must
5508 load $fn+1 first. */
5509 /* Itbl support may require additional care here. */
5510 if (! target_big_endian
)
5513 if (mips_pic
== NO_PIC
5514 || offset_expr
.X_op
== O_constant
)
5516 /* If this is a reference to a GP relative symbol, we want
5517 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5518 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5519 If we have a base register, we use this
5521 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5522 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5523 If this is not a GP relative symbol, we want
5524 lui $at,<sym> (BFD_RELOC_HI16_S)
5525 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5526 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5527 If there is a base register, we add it to $at after the
5528 lui instruction. If there is a constant, we always use
5530 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5531 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5551 ((bfd_arch_bits_per_address (stdoutput
) == 32
5552 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5553 ? "addu" : "daddu"),
5554 "d,v,t", AT
, breg
, GP
);
5560 /* Itbl support may require additional care here. */
5561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5562 coproc
? treg
+ 1 : treg
,
5563 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5564 offset_expr
.X_add_number
+= 4;
5566 /* Set mips_optimize to 2 to avoid inserting an
5568 hold_mips_optimize
= mips_optimize
;
5570 /* Itbl support may require additional care here. */
5571 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5572 coproc
? treg
: treg
+ 1,
5573 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5574 mips_optimize
= hold_mips_optimize
;
5576 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5577 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5578 used_at
&& mips_opts
.noat
),
5579 offset_expr
.X_add_symbol
, (offsetT
) 0,
5582 /* We just generated two relocs. When tc_gen_reloc
5583 handles this case, it will skip the first reloc and
5584 handle the second. The second reloc already has an
5585 extra addend of 4, which we added above. We must
5586 subtract it out, and then subtract another 4 to make
5587 the first reloc come out right. The second reloc
5588 will come out right because we are going to add 4 to
5589 offset_expr when we build its instruction below.
5591 If we have a symbol, then we don't want to include
5592 the offset, because it will wind up being included
5593 when we generate the reloc. */
5595 if (offset_expr
.X_op
== O_constant
)
5596 offset_expr
.X_add_number
-= 8;
5599 offset_expr
.X_add_number
= -4;
5600 offset_expr
.X_op
= O_constant
;
5603 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5608 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5609 ((bfd_arch_bits_per_address (stdoutput
) == 32
5610 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5611 ? "addu" : "daddu"),
5612 "d,v,t", AT
, breg
, AT
);
5616 /* Itbl support may require additional care here. */
5617 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5618 coproc
? treg
+ 1 : treg
,
5619 (int) BFD_RELOC_LO16
, AT
);
5622 /* FIXME: How do we handle overflow here? */
5623 offset_expr
.X_add_number
+= 4;
5624 /* Itbl support may require additional care here. */
5625 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5626 coproc
? treg
: treg
+ 1,
5627 (int) BFD_RELOC_LO16
, AT
);
5629 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5633 /* If this is a reference to an external symbol, we want
5634 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5639 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5641 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5642 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5643 If there is a base register we add it to $at before the
5644 lwc1 instructions. If there is a constant we include it
5645 in the lwc1 instructions. */
5647 expr1
.X_add_number
= offset_expr
.X_add_number
;
5648 offset_expr
.X_add_number
= 0;
5649 if (expr1
.X_add_number
< -0x8000
5650 || expr1
.X_add_number
>= 0x8000 - 4)
5651 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5656 frag_grow (24 + off
);
5657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5658 ((bfd_arch_bits_per_address (stdoutput
) == 32
5659 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5661 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5665 ((bfd_arch_bits_per_address (stdoutput
) == 32
5666 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5667 ? "addu" : "daddu"),
5668 "d,v,t", AT
, breg
, AT
);
5669 /* Itbl support may require additional care here. */
5670 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5671 coproc
? treg
+ 1 : treg
,
5672 (int) BFD_RELOC_LO16
, AT
);
5673 expr1
.X_add_number
+= 4;
5675 /* Set mips_optimize to 2 to avoid inserting an undesired
5677 hold_mips_optimize
= mips_optimize
;
5679 /* Itbl support may require additional care here. */
5680 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5681 coproc
? treg
: treg
+ 1,
5682 (int) BFD_RELOC_LO16
, AT
);
5683 mips_optimize
= hold_mips_optimize
;
5685 (void) frag_var (rs_machine_dependent
, 0, 0,
5686 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5687 offset_expr
.X_add_symbol
, (offsetT
) 0,
5690 else if (mips_pic
== SVR4_PIC
)
5694 /* If this is a reference to an external symbol, we want
5695 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5697 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5702 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5704 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5705 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5706 If there is a base register we add it to $at before the
5707 lwc1 instructions. If there is a constant we include it
5708 in the lwc1 instructions. */
5710 expr1
.X_add_number
= offset_expr
.X_add_number
;
5711 offset_expr
.X_add_number
= 0;
5712 if (expr1
.X_add_number
< -0x8000
5713 || expr1
.X_add_number
>= 0x8000 - 4)
5714 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5715 if (reg_needs_delay (GP
))
5724 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5725 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5727 ((bfd_arch_bits_per_address (stdoutput
) == 32
5728 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5729 ? "addu" : "daddu"),
5730 "d,v,t", AT
, AT
, GP
);
5731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5732 ((bfd_arch_bits_per_address (stdoutput
) == 32
5733 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5735 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5738 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5739 ((bfd_arch_bits_per_address (stdoutput
) == 32
5740 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5741 ? "addu" : "daddu"),
5742 "d,v,t", AT
, breg
, AT
);
5743 /* Itbl support may require additional care here. */
5744 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5745 coproc
? treg
+ 1 : treg
,
5746 (int) BFD_RELOC_LO16
, AT
);
5747 expr1
.X_add_number
+= 4;
5749 /* Set mips_optimize to 2 to avoid inserting an undesired
5751 hold_mips_optimize
= mips_optimize
;
5753 /* Itbl support may require additional care here. */
5754 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5755 coproc
? treg
: treg
+ 1,
5756 (int) BFD_RELOC_LO16
, AT
);
5757 mips_optimize
= hold_mips_optimize
;
5758 expr1
.X_add_number
-= 4;
5760 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5761 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5762 8 + gpdel
+ off
, 1, 0),
5763 offset_expr
.X_add_symbol
, (offsetT
) 0,
5767 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5770 macro_build (p
, &icnt
, &offset_expr
,
5771 ((bfd_arch_bits_per_address (stdoutput
) == 32
5772 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5774 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5776 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5780 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5781 ((bfd_arch_bits_per_address (stdoutput
) == 32
5782 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5783 ? "addu" : "daddu"),
5784 "d,v,t", AT
, breg
, AT
);
5787 /* Itbl support may require additional care here. */
5788 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5789 coproc
? treg
+ 1 : treg
,
5790 (int) BFD_RELOC_LO16
, AT
);
5792 expr1
.X_add_number
+= 4;
5794 /* Set mips_optimize to 2 to avoid inserting an undesired
5796 hold_mips_optimize
= mips_optimize
;
5798 /* Itbl support may require additional care here. */
5799 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5800 coproc
? treg
: treg
+ 1,
5801 (int) BFD_RELOC_LO16
, AT
);
5802 mips_optimize
= hold_mips_optimize
;
5804 else if (mips_pic
== EMBEDDED_PIC
)
5806 /* If there is no base register, we use
5807 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5808 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5809 If we have a base register, we use
5811 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5812 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5821 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5822 ((bfd_arch_bits_per_address (stdoutput
) == 32
5823 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5824 ? "addu" : "daddu"),
5825 "d,v,t", AT
, breg
, GP
);
5830 /* Itbl support may require additional care here. */
5831 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5832 coproc
? treg
+ 1 : treg
,
5833 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5834 offset_expr
.X_add_number
+= 4;
5835 /* Itbl support may require additional care here. */
5836 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5837 coproc
? treg
: treg
+ 1,
5838 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5854 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5855 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5856 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5857 (int) BFD_RELOC_LO16
, breg
);
5858 offset_expr
.X_add_number
+= 4;
5859 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5860 (int) BFD_RELOC_LO16
, breg
);
5863 /* New code added to support COPZ instructions.
5864 This code builds table entries out of the macros in mip_opcodes.
5865 R4000 uses interlocks to handle coproc delays.
5866 Other chips (like the R3000) require nops to be inserted for delays.
5868 FIXME: Currently, we require that the user handle delays.
5869 In order to fill delay slots for non-interlocked chips,
5870 we must have a way to specify delays based on the coprocessor.
5871 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5872 What are the side-effects of the cop instruction?
5873 What cache support might we have and what are its effects?
5874 Both coprocessor & memory require delays. how long???
5875 What registers are read/set/modified?
5877 If an itbl is provided to interpret cop instructions,
5878 this knowledge can be encoded in the itbl spec. */
5892 /* For now we just do C (same as Cz). The parameter will be
5893 stored in insn_opcode by mips_ip. */
5894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5898 #ifdef LOSING_COMPILER
5900 /* Try and see if this is a new itbl instruction.
5901 This code builds table entries out of the macros in mip_opcodes.
5902 FIXME: For now we just assemble the expression and pass it's
5903 value along as a 32-bit immediate.
5904 We may want to have the assembler assemble this value,
5905 so that we gain the assembler's knowledge of delay slots,
5907 Would it be more efficient to use mask (id) here? */
5908 if (itbl_have_entries
5909 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5911 s
= ip
->insn_mo
->name
;
5913 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5914 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5921 as_warn (_("Macro used $at after \".set noat\""));
5926 struct mips_cl_insn
*ip
;
5928 register int treg
, sreg
, dreg
, breg
;
5944 bfd_reloc_code_real_type r
;
5947 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5948 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5949 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5950 mask
= ip
->insn_mo
->mask
;
5952 expr1
.X_op
= O_constant
;
5953 expr1
.X_op_symbol
= NULL
;
5954 expr1
.X_add_symbol
= NULL
;
5955 expr1
.X_add_number
= 1;
5959 #endif /* LOSING_COMPILER */
5964 macro_build ((char *) NULL
, &icnt
, NULL
,
5965 dbl
? "dmultu" : "multu",
5967 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5973 /* The MIPS assembler some times generates shifts and adds. I'm
5974 not trying to be that fancy. GCC should do this for us
5976 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5977 macro_build ((char *) NULL
, &icnt
, NULL
,
5978 dbl
? "dmult" : "mult",
5980 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5993 mips_emit_delays (true);
5994 ++mips_opts
.noreorder
;
5995 mips_any_noreorder
= 1;
5997 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5998 macro_build ((char *) NULL
, &icnt
, NULL
,
5999 dbl
? "dmult" : "mult",
6000 "s,t", sreg
, imm
? AT
: treg
);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6002 macro_build ((char *) NULL
, &icnt
, NULL
,
6003 dbl
? "dsra32" : "sra",
6004 "d,w,<", dreg
, dreg
, 31);
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6010 expr1
.X_add_number
= 8;
6011 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6013 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6015 --mips_opts
.noreorder
;
6016 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6029 mips_emit_delays (true);
6030 ++mips_opts
.noreorder
;
6031 mips_any_noreorder
= 1;
6033 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6034 macro_build ((char *) NULL
, &icnt
, NULL
,
6035 dbl
? "dmultu" : "multu",
6036 "s,t", sreg
, imm
? AT
: treg
);
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6040 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6043 expr1
.X_add_number
= 8;
6044 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6045 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6046 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6048 --mips_opts
.noreorder
;
6052 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6053 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6056 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6060 if (imm_expr
.X_op
!= O_constant
)
6061 as_bad (_("rotate count too large"));
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6063 (int) (imm_expr
.X_add_number
& 0x1f));
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6065 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6072 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6074 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6078 if (imm_expr
.X_op
!= O_constant
)
6079 as_bad (_("rotate count too large"));
6080 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6081 (int) (imm_expr
.X_add_number
& 0x1f));
6082 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6083 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6084 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6088 if (mips_cpu
== 4650)
6090 as_bad (_("opcode not supported on this processor"));
6093 assert (mips_opts
.isa
== 1);
6094 /* Even on a big endian machine $fn comes before $fn+1. We have
6095 to adjust when storing to memory. */
6096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6097 target_big_endian
? treg
+ 1 : treg
,
6098 (int) BFD_RELOC_LO16
, breg
);
6099 offset_expr
.X_add_number
+= 4;
6100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6101 target_big_endian
? treg
: treg
+ 1,
6102 (int) BFD_RELOC_LO16
, breg
);
6107 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6108 treg
, (int) BFD_RELOC_LO16
);
6110 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6111 sreg
, (int) BFD_RELOC_LO16
);
6114 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6116 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6117 dreg
, (int) BFD_RELOC_LO16
);
6122 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6124 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6125 sreg
, (int) BFD_RELOC_LO16
);
6130 as_warn (_("Instruction %s: result is always false"),
6132 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6135 if (imm_expr
.X_op
== O_constant
6136 && imm_expr
.X_add_number
>= 0
6137 && imm_expr
.X_add_number
< 0x10000)
6139 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6140 sreg
, (int) BFD_RELOC_LO16
);
6143 else if (imm_expr
.X_op
== O_constant
6144 && imm_expr
.X_add_number
> -0x8000
6145 && imm_expr
.X_add_number
< 0)
6147 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6148 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6149 ((bfd_arch_bits_per_address (stdoutput
) == 32
6150 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6151 ? "addiu" : "daddiu"),
6152 "t,r,j", dreg
, sreg
,
6153 (int) BFD_RELOC_LO16
);
6158 load_register (&icnt
, AT
, &imm_expr
, 0);
6159 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6163 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6164 (int) BFD_RELOC_LO16
);
6169 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6175 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6176 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6177 (int) BFD_RELOC_LO16
);
6180 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6182 if (imm_expr
.X_op
== O_constant
6183 && imm_expr
.X_add_number
>= -0x8000
6184 && imm_expr
.X_add_number
< 0x8000)
6186 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6187 mask
== M_SGE_I
? "slti" : "sltiu",
6188 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6193 load_register (&icnt
, AT
, &imm_expr
, 0);
6194 macro_build ((char *) NULL
, &icnt
, NULL
,
6195 mask
== M_SGE_I
? "slt" : "sltu",
6196 "d,v,t", dreg
, sreg
, AT
);
6199 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6200 (int) BFD_RELOC_LO16
);
6205 case M_SGT
: /* sreg > treg <==> treg < sreg */
6211 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6214 case M_SGT_I
: /* sreg > I <==> I < sreg */
6220 load_register (&icnt
, AT
, &imm_expr
, 0);
6221 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6224 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6230 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6231 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6232 (int) BFD_RELOC_LO16
);
6235 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6241 load_register (&icnt
, AT
, &imm_expr
, 0);
6242 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6243 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6244 (int) BFD_RELOC_LO16
);
6248 if (imm_expr
.X_op
== O_constant
6249 && imm_expr
.X_add_number
>= -0x8000
6250 && imm_expr
.X_add_number
< 0x8000)
6252 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6253 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6256 load_register (&icnt
, AT
, &imm_expr
, 0);
6257 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6261 if (imm_expr
.X_op
== O_constant
6262 && imm_expr
.X_add_number
>= -0x8000
6263 && imm_expr
.X_add_number
< 0x8000)
6265 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6266 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6269 load_register (&icnt
, AT
, &imm_expr
, 0);
6270 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6276 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6279 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6283 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6285 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6291 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6293 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6299 as_warn (_("Instruction %s: result is always true"),
6301 macro_build ((char *) NULL
, &icnt
, &expr1
,
6302 ((bfd_arch_bits_per_address (stdoutput
) == 32
6303 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6304 ? "addiu" : "daddiu"),
6305 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6308 if (imm_expr
.X_op
== O_constant
6309 && imm_expr
.X_add_number
>= 0
6310 && imm_expr
.X_add_number
< 0x10000)
6312 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6313 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6316 else if (imm_expr
.X_op
== O_constant
6317 && imm_expr
.X_add_number
> -0x8000
6318 && imm_expr
.X_add_number
< 0)
6320 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6321 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6322 ((bfd_arch_bits_per_address (stdoutput
) == 32
6323 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6324 ? "addiu" : "daddiu"),
6325 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6330 load_register (&icnt
, AT
, &imm_expr
, 0);
6331 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6335 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6343 if (imm_expr
.X_op
== O_constant
6344 && imm_expr
.X_add_number
> -0x8000
6345 && imm_expr
.X_add_number
<= 0x8000)
6347 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6348 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6349 dbl
? "daddi" : "addi",
6350 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6353 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6354 macro_build ((char *) NULL
, &icnt
, NULL
,
6355 dbl
? "dsub" : "sub",
6356 "d,v,t", dreg
, sreg
, AT
);
6362 if (imm_expr
.X_op
== O_constant
6363 && imm_expr
.X_add_number
> -0x8000
6364 && imm_expr
.X_add_number
<= 0x8000)
6366 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6367 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6368 dbl
? "daddiu" : "addiu",
6369 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6372 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6373 macro_build ((char *) NULL
, &icnt
, NULL
,
6374 dbl
? "dsubu" : "subu",
6375 "d,v,t", dreg
, sreg
, AT
);
6396 load_register (&icnt
, AT
, &imm_expr
, 0);
6397 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6402 assert (mips_opts
.isa
== 1);
6403 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6404 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6407 * Is the double cfc1 instruction a bug in the mips assembler;
6408 * or is there a reason for it?
6410 mips_emit_delays (true);
6411 ++mips_opts
.noreorder
;
6412 mips_any_noreorder
= 1;
6413 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6414 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6415 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6416 expr1
.X_add_number
= 3;
6417 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6418 (int) BFD_RELOC_LO16
);
6419 expr1
.X_add_number
= 2;
6420 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6421 (int) BFD_RELOC_LO16
);
6422 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6423 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6424 macro_build ((char *) NULL
, &icnt
, NULL
,
6425 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6426 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6427 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6428 --mips_opts
.noreorder
;
6437 if (offset_expr
.X_add_number
>= 0x7fff)
6438 as_bad (_("operand overflow"));
6439 /* avoid load delay */
6440 if (! target_big_endian
)
6441 offset_expr
.X_add_number
+= 1;
6442 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6443 (int) BFD_RELOC_LO16
, breg
);
6444 if (! target_big_endian
)
6445 offset_expr
.X_add_number
-= 1;
6447 offset_expr
.X_add_number
+= 1;
6448 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6449 (int) BFD_RELOC_LO16
, breg
);
6450 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6451 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6464 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6465 as_bad (_("operand overflow"));
6466 if (! target_big_endian
)
6467 offset_expr
.X_add_number
+= off
;
6468 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6469 (int) BFD_RELOC_LO16
, breg
);
6470 if (! target_big_endian
)
6471 offset_expr
.X_add_number
-= off
;
6473 offset_expr
.X_add_number
+= off
;
6474 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6475 (int) BFD_RELOC_LO16
, breg
);
6488 load_address (&icnt
, AT
, &offset_expr
);
6490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6491 ((bfd_arch_bits_per_address (stdoutput
) == 32
6492 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6493 ? "addu" : "daddu"),
6494 "d,v,t", AT
, AT
, breg
);
6495 if (! target_big_endian
)
6496 expr1
.X_add_number
= off
;
6498 expr1
.X_add_number
= 0;
6499 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6500 (int) BFD_RELOC_LO16
, AT
);
6501 if (! target_big_endian
)
6502 expr1
.X_add_number
= 0;
6504 expr1
.X_add_number
= off
;
6505 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6506 (int) BFD_RELOC_LO16
, AT
);
6511 load_address (&icnt
, AT
, &offset_expr
);
6513 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6514 ((bfd_arch_bits_per_address (stdoutput
) == 32
6515 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6516 ? "addu" : "daddu"),
6517 "d,v,t", AT
, AT
, breg
);
6518 if (target_big_endian
)
6519 expr1
.X_add_number
= 0;
6520 macro_build ((char *) NULL
, &icnt
, &expr1
,
6521 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6522 (int) BFD_RELOC_LO16
, AT
);
6523 if (target_big_endian
)
6524 expr1
.X_add_number
= 1;
6526 expr1
.X_add_number
= 0;
6527 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6528 (int) BFD_RELOC_LO16
, AT
);
6529 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6531 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6536 if (offset_expr
.X_add_number
>= 0x7fff)
6537 as_bad (_("operand overflow"));
6538 if (target_big_endian
)
6539 offset_expr
.X_add_number
+= 1;
6540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6541 (int) BFD_RELOC_LO16
, breg
);
6542 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6543 if (target_big_endian
)
6544 offset_expr
.X_add_number
-= 1;
6546 offset_expr
.X_add_number
+= 1;
6547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6548 (int) BFD_RELOC_LO16
, breg
);
6561 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6562 as_bad (_("operand overflow"));
6563 if (! target_big_endian
)
6564 offset_expr
.X_add_number
+= off
;
6565 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6566 (int) BFD_RELOC_LO16
, breg
);
6567 if (! target_big_endian
)
6568 offset_expr
.X_add_number
-= off
;
6570 offset_expr
.X_add_number
+= off
;
6571 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6572 (int) BFD_RELOC_LO16
, breg
);
6585 load_address (&icnt
, AT
, &offset_expr
);
6587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6588 ((bfd_arch_bits_per_address (stdoutput
) == 32
6589 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6590 ? "addu" : "daddu"),
6591 "d,v,t", AT
, AT
, breg
);
6592 if (! target_big_endian
)
6593 expr1
.X_add_number
= off
;
6595 expr1
.X_add_number
= 0;
6596 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6597 (int) BFD_RELOC_LO16
, AT
);
6598 if (! target_big_endian
)
6599 expr1
.X_add_number
= 0;
6601 expr1
.X_add_number
= off
;
6602 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6603 (int) BFD_RELOC_LO16
, AT
);
6607 load_address (&icnt
, AT
, &offset_expr
);
6609 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6610 ((bfd_arch_bits_per_address (stdoutput
) == 32
6611 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6612 ? "addu" : "daddu"),
6613 "d,v,t", AT
, AT
, breg
);
6614 if (! target_big_endian
)
6615 expr1
.X_add_number
= 0;
6616 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6617 (int) BFD_RELOC_LO16
, AT
);
6618 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6620 if (! target_big_endian
)
6621 expr1
.X_add_number
= 1;
6623 expr1
.X_add_number
= 0;
6624 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6625 (int) BFD_RELOC_LO16
, AT
);
6626 if (! target_big_endian
)
6627 expr1
.X_add_number
= 0;
6629 expr1
.X_add_number
= 1;
6630 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6631 (int) BFD_RELOC_LO16
, AT
);
6632 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6634 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6639 /* FIXME: Check if this is one of the itbl macros, since they
6640 are added dynamically. */
6641 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6645 as_warn (_("Macro used $at after \".set noat\""));
6648 /* Implement macros in mips16 mode. */
6652 struct mips_cl_insn
*ip
;
6655 int xreg
, yreg
, zreg
, tmp
;
6659 const char *s
, *s2
, *s3
;
6661 mask
= ip
->insn_mo
->mask
;
6663 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6664 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6665 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6669 expr1
.X_op
= O_constant
;
6670 expr1
.X_op_symbol
= NULL
;
6671 expr1
.X_add_symbol
= NULL
;
6672 expr1
.X_add_number
= 1;
6691 mips_emit_delays (true);
6692 ++mips_opts
.noreorder
;
6693 mips_any_noreorder
= 1;
6694 macro_build ((char *) NULL
, &icnt
, NULL
,
6695 dbl
? "ddiv" : "div",
6696 "0,x,y", xreg
, yreg
);
6697 expr1
.X_add_number
= 2;
6698 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6699 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6701 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6702 since that causes an overflow. We should do that as well,
6703 but I don't see how to do the comparisons without a temporary
6705 --mips_opts
.noreorder
;
6706 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6725 mips_emit_delays (true);
6726 ++mips_opts
.noreorder
;
6727 mips_any_noreorder
= 1;
6728 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6729 expr1
.X_add_number
= 2;
6730 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6731 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6732 --mips_opts
.noreorder
;
6733 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6739 macro_build ((char *) NULL
, &icnt
, NULL
,
6740 dbl
? "dmultu" : "multu",
6742 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6750 if (imm_expr
.X_op
!= O_constant
)
6751 as_bad (_("Unsupported large constant"));
6752 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6753 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6754 dbl
? "daddiu" : "addiu",
6755 "y,x,4", yreg
, xreg
);
6759 if (imm_expr
.X_op
!= O_constant
)
6760 as_bad (_("Unsupported large constant"));
6761 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6762 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6767 if (imm_expr
.X_op
!= O_constant
)
6768 as_bad (_("Unsupported large constant"));
6769 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6770 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6793 goto do_reverse_branch
;
6797 goto do_reverse_branch
;
6809 goto do_reverse_branch
;
6820 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6849 goto do_addone_branch_i
;
6854 goto do_addone_branch_i
;
6869 goto do_addone_branch_i
;
6876 if (imm_expr
.X_op
!= O_constant
)
6877 as_bad (_("Unsupported large constant"));
6878 ++imm_expr
.X_add_number
;
6881 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6886 expr1
.X_add_number
= 0;
6887 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6890 "move", "y,X", xreg
, yreg
);
6891 expr1
.X_add_number
= 2;
6892 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6893 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6894 "neg", "x,w", xreg
, xreg
);
6898 /* For consistency checking, verify that all bits are specified either
6899 by the match/mask part of the instruction definition, or by the
6902 validate_mips_insn (opc
)
6903 const struct mips_opcode
*opc
;
6905 const char *p
= opc
->args
;
6907 unsigned long used_bits
= opc
->mask
;
6909 if ((used_bits
& opc
->match
) != opc
->match
)
6911 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6912 opc
->name
, opc
->args
);
6915 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6922 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6923 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6925 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6926 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6927 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6928 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6930 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6933 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6934 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6935 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6936 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6937 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6938 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6939 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6940 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6941 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6942 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6943 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6945 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6946 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6947 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6948 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6950 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6951 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6952 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6953 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6954 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6955 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6956 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6957 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6958 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6961 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6963 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6964 c
, opc
->name
, opc
->args
);
6968 if (used_bits
!= 0xffffffff)
6970 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6971 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6977 /* This routine assembles an instruction into its binary format. As a
6978 side effect, it sets one of the global variables imm_reloc or
6979 offset_reloc to the type of relocation to do if one of the operands
6980 is an address expression. */
6985 struct mips_cl_insn
*ip
;
6990 struct mips_opcode
*insn
;
6993 unsigned int lastregno
= 0;
6996 int full_opcode_match
= 1;
7000 /* If the instruction contains a '.', we first try to match an instruction
7001 including the '.'. Then we try again without the '.'. */
7003 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7006 /* If we stopped on whitespace, then replace the whitespace with null for
7007 the call to hash_find. Save the character we replaced just in case we
7008 have to re-parse the instruction. */
7009 if (isspace ((unsigned char) *s
))
7015 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7017 /* If we didn't find the instruction in the opcode table, try again, but
7018 this time with just the instruction up to, but not including the
7022 /* Restore the character we overwrite above (if any). */
7026 /* Scan up to the first '.' or whitespace. */
7027 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7030 /* If we did not find a '.', then we can quit now. */
7033 insn_error
= "unrecognized opcode";
7037 /* Lookup the instruction in the hash table. */
7039 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7041 insn_error
= "unrecognized opcode";
7045 full_opcode_match
= 0;
7053 assert (strcmp (insn
->name
, str
) == 0);
7055 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7060 if (insn
->pinfo
!= INSN_MACRO
)
7062 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7068 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7069 && strcmp (insn
->name
, insn
[1].name
) == 0)
7076 static char buf
[100];
7078 _("opcode not supported on this processor: %d (MIPS%d)"),
7079 mips_cpu
, mips_opts
.isa
);
7087 ip
->insn_opcode
= insn
->match
;
7088 for (args
= insn
->args
;; ++args
)
7094 case '\0': /* end of args */
7107 ip
->insn_opcode
|= lastregno
<< 21;
7112 ip
->insn_opcode
|= lastregno
<< 16;
7116 ip
->insn_opcode
|= lastregno
<< 11;
7122 /* Handle optional base register.
7123 Either the base register is omitted or
7124 we must have a left paren. */
7125 /* This is dependent on the next operand specifier
7126 is a base register specification. */
7127 assert (args
[1] == 'b' || args
[1] == '5'
7128 || args
[1] == '-' || args
[1] == '4');
7132 case ')': /* these must match exactly */
7137 case '<': /* must be at least one digit */
7139 * According to the manual, if the shift amount is greater
7140 * than 31 or less than 0 the the shift amount should be
7141 * mod 32. In reality the mips assembler issues an error.
7142 * We issue a warning and mask out all but the low 5 bits.
7144 my_getExpression (&imm_expr
, s
);
7145 check_absolute_expr (ip
, &imm_expr
);
7146 if ((unsigned long) imm_expr
.X_add_number
> 31)
7148 as_warn (_("Improper shift amount (%ld)"),
7149 (long) imm_expr
.X_add_number
);
7150 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7152 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7153 imm_expr
.X_op
= O_absent
;
7157 case '>': /* shift amount minus 32 */
7158 my_getExpression (&imm_expr
, s
);
7159 check_absolute_expr (ip
, &imm_expr
);
7160 if ((unsigned long) imm_expr
.X_add_number
< 32
7161 || (unsigned long) imm_expr
.X_add_number
> 63)
7163 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7164 imm_expr
.X_op
= O_absent
;
7169 case 'k': /* cache code */
7170 case 'h': /* prefx code */
7171 my_getExpression (&imm_expr
, s
);
7172 check_absolute_expr (ip
, &imm_expr
);
7173 if ((unsigned long) imm_expr
.X_add_number
> 31)
7175 as_warn (_("Invalid value for `%s' (%lu)"),
7177 (unsigned long) imm_expr
.X_add_number
);
7178 imm_expr
.X_add_number
&= 0x1f;
7181 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7183 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7184 imm_expr
.X_op
= O_absent
;
7188 case 'c': /* break code */
7189 my_getExpression (&imm_expr
, s
);
7190 check_absolute_expr (ip
, &imm_expr
);
7191 if ((unsigned) imm_expr
.X_add_number
> 1023)
7193 as_warn (_("Illegal break code (%ld)"),
7194 (long) imm_expr
.X_add_number
);
7195 imm_expr
.X_add_number
&= 0x3ff;
7197 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7198 imm_expr
.X_op
= O_absent
;
7202 case 'q': /* lower break code */
7203 my_getExpression (&imm_expr
, s
);
7204 check_absolute_expr (ip
, &imm_expr
);
7205 if ((unsigned) imm_expr
.X_add_number
> 1023)
7207 as_warn (_("Illegal lower break code (%ld)"),
7208 (long) imm_expr
.X_add_number
);
7209 imm_expr
.X_add_number
&= 0x3ff;
7211 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7212 imm_expr
.X_op
= O_absent
;
7216 case 'B': /* syscall code */
7217 my_getExpression (&imm_expr
, s
);
7218 check_absolute_expr (ip
, &imm_expr
);
7219 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7220 as_warn (_("Illegal syscall code (%ld)"),
7221 (long) imm_expr
.X_add_number
);
7222 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7223 imm_expr
.X_op
= O_absent
;
7227 case 'C': /* Coprocessor code */
7228 my_getExpression (&imm_expr
, s
);
7229 check_absolute_expr (ip
, &imm_expr
);
7230 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7232 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7233 (long) imm_expr
.X_add_number
);
7234 imm_expr
.X_add_number
&= ((1<<25) - 1);
7236 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7237 imm_expr
.X_op
= O_absent
;
7241 case 'P': /* Performance register */
7242 my_getExpression (&imm_expr
, s
);
7243 check_absolute_expr (ip
, &imm_expr
);
7244 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7246 as_warn (_("Invalidate performance regster (%ld)"),
7247 (long) imm_expr
.X_add_number
);
7248 imm_expr
.X_add_number
&= 1;
7250 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7251 imm_expr
.X_op
= O_absent
;
7255 case 'b': /* base register */
7256 case 'd': /* destination register */
7257 case 's': /* source register */
7258 case 't': /* target register */
7259 case 'r': /* both target and source */
7260 case 'v': /* both dest and source */
7261 case 'w': /* both dest and target */
7262 case 'E': /* coprocessor target register */
7263 case 'G': /* coprocessor destination register */
7264 case 'x': /* ignore register name */
7265 case 'z': /* must be zero register */
7270 if (isdigit ((unsigned char) s
[1]))
7280 while (isdigit ((unsigned char) *s
));
7282 as_bad (_("Invalid register number (%d)"), regno
);
7284 else if (*args
== 'E' || *args
== 'G')
7288 if (s
[1] == 'f' && s
[2] == 'p')
7293 else if (s
[1] == 's' && s
[2] == 'p')
7298 else if (s
[1] == 'g' && s
[2] == 'p')
7303 else if (s
[1] == 'a' && s
[2] == 't')
7308 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7313 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7318 else if (itbl_have_entries
)
7323 p
= s
+ 1; /* advance past '$' */
7324 n
= itbl_get_field (&p
); /* n is name */
7326 /* See if this is a register defined in an
7328 if (itbl_get_reg_val (n
, &r
))
7330 /* Get_field advances to the start of
7331 the next field, so we need to back
7332 rack to the end of the last field. */
7336 s
= strchr (s
, '\0');
7349 as_warn (_("Used $at without \".set noat\""));
7355 if (c
== 'r' || c
== 'v' || c
== 'w')
7362 /* 'z' only matches $0. */
7363 if (c
== 'z' && regno
!= 0)
7366 /* Now that we have assembled one operand, we use the args string
7367 * to figure out where it goes in the instruction. */
7374 ip
->insn_opcode
|= regno
<< 21;
7378 ip
->insn_opcode
|= regno
<< 11;
7383 ip
->insn_opcode
|= regno
<< 16;
7386 /* This case exists because on the r3000 trunc
7387 expands into a macro which requires a gp
7388 register. On the r6000 or r4000 it is
7389 assembled into a single instruction which
7390 ignores the register. Thus the insn version
7391 is MIPS_ISA2 and uses 'x', and the macro
7392 version is MIPS_ISA1 and uses 't'. */
7395 /* This case is for the div instruction, which
7396 acts differently if the destination argument
7397 is $0. This only matches $0, and is checked
7398 outside the switch. */
7401 /* Itbl operand; not yet implemented. FIXME ?? */
7403 /* What about all other operands like 'i', which
7404 can be specified in the opcode table? */
7414 ip
->insn_opcode
|= lastregno
<< 21;
7417 ip
->insn_opcode
|= lastregno
<< 16;
7422 case 'D': /* floating point destination register */
7423 case 'S': /* floating point source register */
7424 case 'T': /* floating point target register */
7425 case 'R': /* floating point source register */
7429 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7439 while (isdigit ((unsigned char) *s
));
7442 as_bad (_("Invalid float register number (%d)"), regno
);
7444 if ((regno
& 1) != 0
7445 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7446 && ! (strcmp (str
, "mtc1") == 0
7447 || strcmp (str
, "mfc1") == 0
7448 || strcmp (str
, "lwc1") == 0
7449 || strcmp (str
, "swc1") == 0
7450 || strcmp (str
, "l.s") == 0
7451 || strcmp (str
, "s.s") == 0))
7452 as_warn (_("Float register should be even, was %d"),
7460 if (c
== 'V' || c
== 'W')
7470 ip
->insn_opcode
|= regno
<< 6;
7474 ip
->insn_opcode
|= regno
<< 11;
7478 ip
->insn_opcode
|= regno
<< 16;
7481 ip
->insn_opcode
|= regno
<< 21;
7492 ip
->insn_opcode
|= lastregno
<< 11;
7495 ip
->insn_opcode
|= lastregno
<< 16;
7501 my_getExpression (&imm_expr
, s
);
7502 if (imm_expr
.X_op
!= O_big
7503 && imm_expr
.X_op
!= O_constant
)
7504 insn_error
= _("absolute expression required");
7509 my_getExpression (&offset_expr
, s
);
7510 imm_reloc
= BFD_RELOC_32
;
7522 unsigned char temp
[8];
7524 unsigned int length
;
7529 /* These only appear as the last operand in an
7530 instruction, and every instruction that accepts
7531 them in any variant accepts them in all variants.
7532 This means we don't have to worry about backing out
7533 any changes if the instruction does not match.
7535 The difference between them is the size of the
7536 floating point constant and where it goes. For 'F'
7537 and 'L' the constant is 64 bits; for 'f' and 'l' it
7538 is 32 bits. Where the constant is placed is based
7539 on how the MIPS assembler does things:
7542 f -- immediate value
7545 The .lit4 and .lit8 sections are only used if
7546 permitted by the -G argument.
7548 When generating embedded PIC code, we use the
7549 .lit8 section but not the .lit4 section (we can do
7550 .lit4 inline easily; we need to put .lit8
7551 somewhere in the data segment, and using .lit8
7552 permits the linker to eventually combine identical
7555 f64
= *args
== 'F' || *args
== 'L';
7557 save_in
= input_line_pointer
;
7558 input_line_pointer
= s
;
7559 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7561 s
= input_line_pointer
;
7562 input_line_pointer
= save_in
;
7563 if (err
!= NULL
&& *err
!= '\0')
7565 as_bad (_("Bad floating point constant: %s"), err
);
7566 memset (temp
, '\0', sizeof temp
);
7567 length
= f64
? 8 : 4;
7570 assert (length
== (f64
? 8 : 4));
7574 && (! USE_GLOBAL_POINTER_OPT
7575 || mips_pic
== EMBEDDED_PIC
7576 || g_switch_value
< 4
7577 || (temp
[0] == 0 && temp
[1] == 0)
7578 || (temp
[2] == 0 && temp
[3] == 0))))
7580 imm_expr
.X_op
= O_constant
;
7581 if (! target_big_endian
)
7582 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7584 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7587 && ((temp
[0] == 0 && temp
[1] == 0)
7588 || (temp
[2] == 0 && temp
[3] == 0))
7589 && ((temp
[4] == 0 && temp
[5] == 0)
7590 || (temp
[6] == 0 && temp
[7] == 0)))
7592 /* The value is simple enough to load with a
7593 couple of instructions. In mips1 mode, set
7594 imm_expr to the high order 32 bits and
7595 offset_expr to the low order 32 bits.
7596 Otherwise, set imm_expr to the entire 64 bit
7598 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7600 imm_expr
.X_op
= O_constant
;
7601 offset_expr
.X_op
= O_constant
;
7602 if (! target_big_endian
)
7604 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7605 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7609 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7610 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7612 if (offset_expr
.X_add_number
== 0)
7613 offset_expr
.X_op
= O_absent
;
7615 else if (sizeof (imm_expr
.X_add_number
) > 4)
7617 imm_expr
.X_op
= O_constant
;
7618 if (! target_big_endian
)
7619 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7621 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7625 imm_expr
.X_op
= O_big
;
7626 imm_expr
.X_add_number
= 4;
7627 if (! target_big_endian
)
7629 generic_bignum
[0] = bfd_getl16 (temp
);
7630 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7631 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7632 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7636 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7637 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7638 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7639 generic_bignum
[3] = bfd_getb16 (temp
);
7645 const char *newname
;
7648 /* Switch to the right section. */
7650 subseg
= now_subseg
;
7653 default: /* unused default case avoids warnings. */
7655 newname
= RDATA_SECTION_NAME
;
7656 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7660 newname
= RDATA_SECTION_NAME
;
7663 assert (!USE_GLOBAL_POINTER_OPT
7664 || g_switch_value
>= 4);
7668 new_seg
= subseg_new (newname
, (subsegT
) 0);
7669 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7670 bfd_set_section_flags (stdoutput
, new_seg
,
7675 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7676 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7677 && strcmp (TARGET_OS
, "elf") != 0)
7678 record_alignment (new_seg
, 4);
7680 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7682 as_bad (_("Can't use floating point insn in this section"));
7684 /* Set the argument to the current address in the
7686 offset_expr
.X_op
= O_symbol
;
7687 offset_expr
.X_add_symbol
=
7688 symbol_new ("L0\001", now_seg
,
7689 (valueT
) frag_now_fix (), frag_now
);
7690 offset_expr
.X_add_number
= 0;
7692 /* Put the floating point number into the section. */
7693 p
= frag_more ((int) length
);
7694 memcpy (p
, temp
, length
);
7696 /* Switch back to the original section. */
7697 subseg_set (seg
, subseg
);
7702 case 'i': /* 16 bit unsigned immediate */
7703 case 'j': /* 16 bit signed immediate */
7704 imm_reloc
= BFD_RELOC_LO16
;
7705 c
= my_getSmallExpression (&imm_expr
, s
);
7710 if (imm_expr
.X_op
== O_constant
)
7711 imm_expr
.X_add_number
=
7712 (imm_expr
.X_add_number
>> 16) & 0xffff;
7715 imm_reloc
= BFD_RELOC_HI16_S
;
7716 imm_unmatched_hi
= true;
7719 imm_reloc
= BFD_RELOC_HI16
;
7721 else if (imm_expr
.X_op
== O_constant
)
7722 imm_expr
.X_add_number
&= 0xffff;
7726 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7727 || ((imm_expr
.X_add_number
< 0
7728 || imm_expr
.X_add_number
>= 0x10000)
7729 && imm_expr
.X_op
== O_constant
))
7731 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7732 !strcmp (insn
->name
, insn
[1].name
))
7734 if (imm_expr
.X_op
!= O_constant
7735 && imm_expr
.X_op
!= O_big
)
7736 insn_error
= _("absolute expression required");
7738 as_bad (_("16 bit expression not in range 0..65535"));
7746 /* The upper bound should be 0x8000, but
7747 unfortunately the MIPS assembler accepts numbers
7748 from 0x8000 to 0xffff and sign extends them, and
7749 we want to be compatible. We only permit this
7750 extended range for an instruction which does not
7751 provide any further alternates, since those
7752 alternates may handle other cases. People should
7753 use the numbers they mean, rather than relying on
7754 a mysterious sign extension. */
7755 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7756 strcmp (insn
->name
, insn
[1].name
) == 0);
7761 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7762 || ((imm_expr
.X_add_number
< -0x8000
7763 || imm_expr
.X_add_number
>= max
)
7764 && imm_expr
.X_op
== O_constant
)
7766 && imm_expr
.X_add_number
< 0
7767 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7768 && imm_expr
.X_unsigned
7769 && sizeof (imm_expr
.X_add_number
) <= 4))
7773 if (imm_expr
.X_op
!= O_constant
7774 && imm_expr
.X_op
!= O_big
)
7775 insn_error
= _("absolute expression required");
7777 as_bad (_("16 bit expression not in range -32768..32767"));
7783 case 'o': /* 16 bit offset */
7784 c
= my_getSmallExpression (&offset_expr
, s
);
7786 /* If this value won't fit into a 16 bit offset, then go
7787 find a macro that will generate the 32 bit offset
7788 code pattern. As a special hack, we accept the
7789 difference of two local symbols as a constant. This
7790 is required to suppose embedded PIC switches, which
7791 use an instruction which looks like
7792 lw $4,$L12-$LS12($4)
7793 The problem with handling this in a more general
7794 fashion is that the macro function doesn't expect to
7795 see anything which can be handled in a single
7796 constant instruction. */
7798 && (offset_expr
.X_op
!= O_constant
7799 || offset_expr
.X_add_number
>= 0x8000
7800 || offset_expr
.X_add_number
< -0x8000)
7801 && (mips_pic
!= EMBEDDED_PIC
7802 || offset_expr
.X_op
!= O_subtract
7803 || now_seg
!= text_section
7804 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7808 if (c
== 'h' || c
== 'H')
7810 if (offset_expr
.X_op
!= O_constant
)
7812 offset_expr
.X_add_number
=
7813 (offset_expr
.X_add_number
>> 16) & 0xffff;
7815 offset_reloc
= BFD_RELOC_LO16
;
7819 case 'p': /* pc relative offset */
7820 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7821 my_getExpression (&offset_expr
, s
);
7825 case 'u': /* upper 16 bits */
7826 c
= my_getSmallExpression (&imm_expr
, s
);
7827 imm_reloc
= BFD_RELOC_LO16
;
7832 if (imm_expr
.X_op
== O_constant
)
7833 imm_expr
.X_add_number
=
7834 (imm_expr
.X_add_number
>> 16) & 0xffff;
7837 imm_reloc
= BFD_RELOC_HI16_S
;
7838 imm_unmatched_hi
= true;
7841 imm_reloc
= BFD_RELOC_HI16
;
7843 else if (imm_expr
.X_op
== O_constant
)
7844 imm_expr
.X_add_number
&= 0xffff;
7846 if (imm_expr
.X_op
== O_constant
7847 && (imm_expr
.X_add_number
< 0
7848 || imm_expr
.X_add_number
>= 0x10000))
7849 as_bad (_("lui expression not in range 0..65535"));
7853 case 'a': /* 26 bit address */
7854 my_getExpression (&offset_expr
, s
);
7856 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7859 case 'N': /* 3 bit branch condition code */
7860 case 'M': /* 3 bit compare condition code */
7861 if (strncmp (s
, "$fcc", 4) != 0)
7871 while (isdigit ((unsigned char) *s
));
7873 as_bad (_("invalid condition code register $fcc%d"), regno
);
7875 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7877 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7881 as_bad (_("bad char = '%c'\n"), *args
);
7886 /* Args don't match. */
7887 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7888 !strcmp (insn
->name
, insn
[1].name
))
7894 insn_error
= _("illegal operands");
7899 /* This routine assembles an instruction into its binary format when
7900 assembling for the mips16. As a side effect, it sets one of the
7901 global variables imm_reloc or offset_reloc to the type of
7902 relocation to do if one of the operands is an address expression.
7903 It also sets mips16_small and mips16_ext if the user explicitly
7904 requested a small or extended instruction. */
7909 struct mips_cl_insn
*ip
;
7913 struct mips_opcode
*insn
;
7916 unsigned int lastregno
= 0;
7921 mips16_small
= false;
7924 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7936 if (s
[1] == 't' && s
[2] == ' ')
7939 mips16_small
= true;
7943 else if (s
[1] == 'e' && s
[2] == ' ')
7952 insn_error
= _("unknown opcode");
7956 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7957 mips16_small
= true;
7959 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7961 insn_error
= _("unrecognized opcode");
7968 assert (strcmp (insn
->name
, str
) == 0);
7971 ip
->insn_opcode
= insn
->match
;
7972 ip
->use_extend
= false;
7973 imm_expr
.X_op
= O_absent
;
7974 imm_reloc
= BFD_RELOC_UNUSED
;
7975 offset_expr
.X_op
= O_absent
;
7976 offset_reloc
= BFD_RELOC_UNUSED
;
7977 for (args
= insn
->args
; 1; ++args
)
7984 /* In this switch statement we call break if we did not find
7985 a match, continue if we did find a match, or return if we
7994 /* Stuff the immediate value in now, if we can. */
7995 if (imm_expr
.X_op
== O_constant
7996 && imm_reloc
> BFD_RELOC_UNUSED
7997 && insn
->pinfo
!= INSN_MACRO
)
7999 mips16_immed ((char *) NULL
, 0,
8000 imm_reloc
- BFD_RELOC_UNUSED
,
8001 imm_expr
.X_add_number
, true, mips16_small
,
8002 mips16_ext
, &ip
->insn_opcode
,
8003 &ip
->use_extend
, &ip
->extend
);
8004 imm_expr
.X_op
= O_absent
;
8005 imm_reloc
= BFD_RELOC_UNUSED
;
8019 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8022 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8038 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8040 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8057 if (isdigit ((unsigned char) s
[1]))
8067 while (isdigit ((unsigned char) *s
));
8070 as_bad (_("invalid register number (%d)"), regno
);
8076 if (s
[1] == 'f' && s
[2] == 'p')
8081 else if (s
[1] == 's' && s
[2] == 'p')
8086 else if (s
[1] == 'g' && s
[2] == 'p')
8091 else if (s
[1] == 'a' && s
[2] == 't')
8096 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8101 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8114 if (c
== 'v' || c
== 'w')
8116 regno
= mips16_to_32_reg_map
[lastregno
];
8130 regno
= mips32_to_16_reg_map
[regno
];
8135 regno
= ILLEGAL_REG
;
8140 regno
= ILLEGAL_REG
;
8145 regno
= ILLEGAL_REG
;
8150 if (regno
== AT
&& ! mips_opts
.noat
)
8151 as_warn (_("used $at without \".set noat\""));
8158 if (regno
== ILLEGAL_REG
)
8165 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8169 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8172 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8175 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8181 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8184 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8185 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8195 if (strncmp (s
, "$pc", 3) == 0)
8219 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8221 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8222 and generate the appropriate reloc. If the text
8223 inside %gprel is not a symbol name with an
8224 optional offset, then we generate a normal reloc
8225 and will probably fail later. */
8226 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8227 if (imm_expr
.X_op
== O_symbol
)
8230 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8232 ip
->use_extend
= true;
8239 /* Just pick up a normal expression. */
8240 my_getExpression (&imm_expr
, s
);
8243 if (imm_expr
.X_op
== O_register
)
8245 /* What we thought was an expression turned out to
8248 if (s
[0] == '(' && args
[1] == '(')
8250 /* It looks like the expression was omitted
8251 before a register indirection, which means
8252 that the expression is implicitly zero. We
8253 still set up imm_expr, so that we handle
8254 explicit extensions correctly. */
8255 imm_expr
.X_op
= O_constant
;
8256 imm_expr
.X_add_number
= 0;
8257 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8264 /* We need to relax this instruction. */
8265 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8274 /* We use offset_reloc rather than imm_reloc for the PC
8275 relative operands. This lets macros with both
8276 immediate and address operands work correctly. */
8277 my_getExpression (&offset_expr
, s
);
8279 if (offset_expr
.X_op
== O_register
)
8282 /* We need to relax this instruction. */
8283 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8287 case '6': /* break code */
8288 my_getExpression (&imm_expr
, s
);
8289 check_absolute_expr (ip
, &imm_expr
);
8290 if ((unsigned long) imm_expr
.X_add_number
> 63)
8292 as_warn (_("Invalid value for `%s' (%lu)"),
8294 (unsigned long) imm_expr
.X_add_number
);
8295 imm_expr
.X_add_number
&= 0x3f;
8297 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8298 imm_expr
.X_op
= O_absent
;
8302 case 'a': /* 26 bit address */
8303 my_getExpression (&offset_expr
, s
);
8305 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8306 ip
->insn_opcode
<<= 16;
8309 case 'l': /* register list for entry macro */
8310 case 'L': /* register list for exit macro */
8320 int freg
, reg1
, reg2
;
8322 while (*s
== ' ' || *s
== ',')
8326 as_bad (_("can't parse register list"));
8338 while (isdigit ((unsigned char) *s
))
8360 as_bad (_("invalid register list"));
8365 while (isdigit ((unsigned char) *s
))
8372 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8377 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8382 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8383 mask
|= (reg2
- 3) << 3;
8384 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8385 mask
|= (reg2
- 15) << 1;
8386 else if (reg1
== 31 && reg2
== 31)
8390 as_bad (_("invalid register list"));
8394 /* The mask is filled in in the opcode table for the
8395 benefit of the disassembler. We remove it before
8396 applying the actual mask. */
8397 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8398 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8402 case 'e': /* extend code */
8403 my_getExpression (&imm_expr
, s
);
8404 check_absolute_expr (ip
, &imm_expr
);
8405 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8407 as_warn (_("Invalid value for `%s' (%lu)"),
8409 (unsigned long) imm_expr
.X_add_number
);
8410 imm_expr
.X_add_number
&= 0x7ff;
8412 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8413 imm_expr
.X_op
= O_absent
;
8423 /* Args don't match. */
8424 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8425 strcmp (insn
->name
, insn
[1].name
) == 0)
8432 insn_error
= _("illegal operands");
8438 /* This structure holds information we know about a mips16 immediate
8441 struct mips16_immed_operand
8443 /* The type code used in the argument string in the opcode table. */
8445 /* The number of bits in the short form of the opcode. */
8447 /* The number of bits in the extended form of the opcode. */
8449 /* The amount by which the short form is shifted when it is used;
8450 for example, the sw instruction has a shift count of 2. */
8452 /* The amount by which the short form is shifted when it is stored
8453 into the instruction code. */
8455 /* Non-zero if the short form is unsigned. */
8457 /* Non-zero if the extended form is unsigned. */
8459 /* Non-zero if the value is PC relative. */
8463 /* The mips16 immediate operand types. */
8465 static const struct mips16_immed_operand mips16_immed_operands
[] =
8467 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8468 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8469 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8470 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8471 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8472 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8473 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8474 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8475 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8476 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8477 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8478 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8479 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8480 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8481 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8482 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8483 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8484 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8485 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8486 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8487 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8490 #define MIPS16_NUM_IMMED \
8491 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8493 /* Handle a mips16 instruction with an immediate value. This or's the
8494 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8495 whether an extended value is needed; if one is needed, it sets
8496 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8497 If SMALL is true, an unextended opcode was explicitly requested.
8498 If EXT is true, an extended opcode was explicitly requested. If
8499 WARN is true, warn if EXT does not match reality. */
8502 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8511 unsigned long *insn
;
8512 boolean
*use_extend
;
8513 unsigned short *extend
;
8515 register const struct mips16_immed_operand
*op
;
8516 int mintiny
, maxtiny
;
8519 op
= mips16_immed_operands
;
8520 while (op
->type
!= type
)
8523 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8528 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8531 maxtiny
= 1 << op
->nbits
;
8536 maxtiny
= (1 << op
->nbits
) - 1;
8541 mintiny
= - (1 << (op
->nbits
- 1));
8542 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8545 /* Branch offsets have an implicit 0 in the lowest bit. */
8546 if (type
== 'p' || type
== 'q')
8549 if ((val
& ((1 << op
->shift
) - 1)) != 0
8550 || val
< (mintiny
<< op
->shift
)
8551 || val
> (maxtiny
<< op
->shift
))
8556 if (warn
&& ext
&& ! needext
)
8557 as_warn_where (file
, line
, _("extended operand requested but not required"));
8558 if (small
&& needext
)
8559 as_bad_where (file
, line
, _("invalid unextended operand value"));
8561 if (small
|| (! ext
&& ! needext
))
8565 *use_extend
= false;
8566 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8567 insnval
<<= op
->op_shift
;
8572 long minext
, maxext
;
8578 maxext
= (1 << op
->extbits
) - 1;
8582 minext
= - (1 << (op
->extbits
- 1));
8583 maxext
= (1 << (op
->extbits
- 1)) - 1;
8585 if (val
< minext
|| val
> maxext
)
8586 as_bad_where (file
, line
,
8587 _("operand value out of range for instruction"));
8590 if (op
->extbits
== 16)
8592 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8595 else if (op
->extbits
== 15)
8597 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8602 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8606 *extend
= (unsigned short) extval
;
8615 my_getSmallExpression (ep
, str
)
8626 ((str
[1] == 'h' && str
[2] == 'i')
8627 || (str
[1] == 'H' && str
[2] == 'I')
8628 || (str
[1] == 'l' && str
[2] == 'o'))
8640 * A small expression may be followed by a base register.
8641 * Scan to the end of this operand, and then back over a possible
8642 * base register. Then scan the small expression up to that
8643 * point. (Based on code in sparc.c...)
8645 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8647 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8649 if (isdigit ((unsigned char) sp
[-2]))
8651 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8653 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8659 else if (sp
- 5 >= str
8662 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8663 || (sp
[-3] == 's' && sp
[-2] == 'p')
8664 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8665 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8671 /* no expression means zero offset */
8674 /* %xx(reg) is an error */
8675 ep
->X_op
= O_absent
;
8680 ep
->X_op
= O_constant
;
8683 ep
->X_add_symbol
= NULL
;
8684 ep
->X_op_symbol
= NULL
;
8685 ep
->X_add_number
= 0;
8690 my_getExpression (ep
, str
);
8697 my_getExpression (ep
, str
);
8698 return c
; /* => %hi or %lo encountered */
8702 my_getExpression (ep
, str
)
8708 save_in
= input_line_pointer
;
8709 input_line_pointer
= str
;
8711 expr_end
= input_line_pointer
;
8712 input_line_pointer
= save_in
;
8714 /* If we are in mips16 mode, and this is an expression based on `.',
8715 then we bump the value of the symbol by 1 since that is how other
8716 text symbols are handled. We don't bother to handle complex
8717 expressions, just `.' plus or minus a constant. */
8718 if (mips_opts
.mips16
8719 && ep
->X_op
== O_symbol
8720 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8721 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8722 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8723 && symbol_constant_p (ep
->X_add_symbol
)
8724 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8725 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8728 /* Turn a string in input_line_pointer into a floating point constant
8729 of type type, and store the appropriate bytes in *litP. The number
8730 of LITTLENUMS emitted is stored in *sizeP . An error message is
8731 returned, or NULL on OK. */
8734 md_atof (type
, litP
, sizeP
)
8740 LITTLENUM_TYPE words
[4];
8756 return _("bad call to md_atof");
8759 t
= atof_ieee (input_line_pointer
, type
, words
);
8761 input_line_pointer
= t
;
8765 if (! target_big_endian
)
8767 for (i
= prec
- 1; i
>= 0; i
--)
8769 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8775 for (i
= 0; i
< prec
; i
++)
8777 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8786 md_number_to_chars (buf
, val
, n
)
8791 if (target_big_endian
)
8792 number_to_chars_bigendian (buf
, val
, n
);
8794 number_to_chars_littleendian (buf
, val
, n
);
8797 CONST
char *md_shortopts
= "O::g::G:";
8799 struct option md_longopts
[] = {
8800 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8801 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8802 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8803 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8804 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8805 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8806 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8807 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8808 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8809 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8810 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8811 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8812 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8813 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8814 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8815 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8816 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8817 {"break", no_argument
, NULL
, OPTION_BREAK
},
8818 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8819 #define OPTION_EB (OPTION_MD_BASE + 11)
8820 {"EB", no_argument
, NULL
, OPTION_EB
},
8821 #define OPTION_EL (OPTION_MD_BASE + 12)
8822 {"EL", no_argument
, NULL
, OPTION_EL
},
8823 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8824 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8825 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8826 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8827 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8828 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8829 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8830 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8831 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8832 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8833 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8834 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8835 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8836 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8837 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8838 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8839 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8840 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8841 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8842 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8845 #define OPTION_MABI (OPTION_MD_BASE + 38)
8846 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8848 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8849 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8850 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8851 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8853 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8854 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8855 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8856 #define OPTION_32 (OPTION_MD_BASE + 20)
8857 #define OPTION_64 (OPTION_MD_BASE + 21)
8859 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8860 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8861 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8862 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8863 {"32", no_argument
, NULL
, OPTION_32
},
8864 {"64", no_argument
, NULL
, OPTION_64
},
8867 #define OPTION_GP32 (OPTION_MD_BASE + 41)
8868 #define OPTION_GP64 (OPTION_MD_BASE + 42)
8869 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8870 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8872 {NULL
, no_argument
, NULL
, 0}
8874 size_t md_longopts_size
= sizeof(md_longopts
);
8877 md_parse_option (c
, arg
)
8892 target_big_endian
= 1;
8896 target_big_endian
= 0;
8900 if (arg
&& arg
[1] == '0')
8910 mips_debug
= atoi (arg
);
8911 /* When the MIPS assembler sees -g or -g2, it does not do
8912 optimizations which limit full symbolic debugging. We take
8913 that to be equivalent to -O0. */
8914 if (mips_debug
== 2)
8938 /* Identify the processor type */
8940 if (strcmp (p
, "default") == 0
8941 || strcmp (p
, "DEFAULT") == 0)
8947 /* We need to cope with the various "vr" prefixes for the 4300
8949 if (*p
== 'v' || *p
== 'V')
8955 if (*p
== 'r' || *p
== 'R')
8962 if (strcmp (p
, "10000") == 0
8963 || strcmp (p
, "10k") == 0
8964 || strcmp (p
, "10K") == 0)
8969 if (strcmp (p
, "2000") == 0
8970 || strcmp (p
, "2k") == 0
8971 || strcmp (p
, "2K") == 0)
8976 if (strcmp (p
, "3000") == 0
8977 || strcmp (p
, "3k") == 0
8978 || strcmp (p
, "3K") == 0)
8980 else if (strcmp (p
, "3900") == 0)
8985 if (strcmp (p
, "4000") == 0
8986 || strcmp (p
, "4k") == 0
8987 || strcmp (p
, "4K") == 0)
8989 else if (strcmp (p
, "4100") == 0)
8991 else if (strcmp (p
, "4111") == 0)
8993 else if (strcmp (p
, "4300") == 0)
8995 else if (strcmp (p
, "4400") == 0)
8997 else if (strcmp (p
, "4600") == 0)
8999 else if (strcmp (p
, "4650") == 0)
9001 else if (strcmp (p
, "4010") == 0)
9006 if (strcmp (p
, "5000") == 0
9007 || strcmp (p
, "5k") == 0
9008 || strcmp (p
, "5K") == 0)
9013 if (strcmp (p
, "6000") == 0
9014 || strcmp (p
, "6k") == 0
9015 || strcmp (p
, "6K") == 0)
9020 if (strcmp (p
, "8000") == 0
9021 || strcmp (p
, "8k") == 0
9022 || strcmp (p
, "8K") == 0)
9027 if (strcmp (p
, "orion") == 0)
9033 && (mips_cpu
!= 4300
9036 && mips_cpu
!= 5000))
9038 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9044 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9055 case OPTION_NO_M4650
:
9062 case OPTION_NO_M4010
:
9069 case OPTION_NO_M4100
:
9077 case OPTION_NO_M3900
:
9081 mips_opts
.mips16
= 1;
9082 mips_no_prev_insn (false);
9085 case OPTION_NO_MIPS16
:
9086 mips_opts
.mips16
= 0;
9087 mips_no_prev_insn (false);
9090 case OPTION_MEMBEDDED_PIC
:
9091 mips_pic
= EMBEDDED_PIC
;
9092 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9094 as_bad (_("-G may not be used with embedded PIC code"));
9097 g_switch_value
= 0x7fffffff;
9100 /* When generating ELF code, we permit -KPIC and -call_shared to
9101 select SVR4_PIC, and -non_shared to select no PIC. This is
9102 intended to be compatible with Irix 5. */
9103 case OPTION_CALL_SHARED
:
9104 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9106 as_bad (_("-call_shared is supported only for ELF format"));
9109 mips_pic
= SVR4_PIC
;
9110 if (g_switch_seen
&& g_switch_value
!= 0)
9112 as_bad (_("-G may not be used with SVR4 PIC code"));
9118 case OPTION_NON_SHARED
:
9119 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9121 as_bad (_("-non_shared is supported only for ELF format"));
9127 /* The -xgot option tells the assembler to use 32 offsets when
9128 accessing the got in SVR4_PIC mode. It is for Irix
9135 if (! USE_GLOBAL_POINTER_OPT
)
9137 as_bad (_("-G is not supported for this configuration"));
9140 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9142 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9146 g_switch_value
= atoi (arg
);
9150 /* The -32 and -64 options tell the assembler to output the 32
9151 bit or the 64 bit MIPS ELF format. */
9158 const char **list
, **l
;
9160 list
= bfd_target_list ();
9161 for (l
= list
; *l
!= NULL
; l
++)
9162 if (strcmp (*l
, "elf64-bigmips") == 0
9163 || strcmp (*l
, "elf64-littlemips") == 0)
9166 as_fatal (_("No compiled in support for 64 bit object file format"));
9176 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9177 flag in object files because to do so would make it
9178 impossible to link with libraries compiled without "-gp32".
9179 This is unnecessarily restrictive.
9181 We could solve this problem by adding "-gp32" multilibs to
9182 gcc, but to set this flag before gcc is built with such
9183 multilibs will break too many systems. */
9185 /* mips_32bitmode = 1; */
9191 /* mips_32bitmode = 0; */
9195 if (strcmp (arg
,"32") == 0
9196 || strcmp (arg
,"n32") == 0
9197 || strcmp (arg
,"64") == 0
9198 || strcmp (arg
,"o64") == 0
9199 || strcmp (arg
,"eabi") == 0)
9200 mips_abi_string
= arg
;
9203 case OPTION_M7000_HILO_FIX
:
9204 mips_7000_hilo_fix
= true;
9207 case OPTION_NO_M7000_HILO_FIX
:
9208 mips_7000_hilo_fix
= false;
9220 show (stream
, string
, col_p
, first_p
)
9228 fprintf (stream
, "%24s", "");
9233 fprintf (stream
, ", ");
9237 if (*col_p
+ strlen (string
) > 72)
9239 fprintf (stream
, "\n%24s", "");
9243 fprintf (stream
, "%s", string
);
9244 *col_p
+= strlen (string
);
9251 md_show_usage (stream
)
9256 fprintf(stream
, _("\
9258 -membedded-pic generate embedded position independent code\n\
9259 -EB generate big endian output\n\
9260 -EL generate little endian output\n\
9261 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9262 -G NUM allow referencing objects up to NUM bytes\n\
9263 implicitly with the gp register [default 8]\n"));
9264 fprintf(stream
, _("\
9265 -mips1 generate MIPS ISA I instructions\n\
9266 -mips2 generate MIPS ISA II instructions\n\
9267 -mips3 generate MIPS ISA III instructions\n\
9268 -mips4 generate MIPS ISA IV instructions\n\
9269 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9273 show (stream
, "2000", &column
, &first
);
9274 show (stream
, "3000", &column
, &first
);
9275 show (stream
, "3900", &column
, &first
);
9276 show (stream
, "4000", &column
, &first
);
9277 show (stream
, "4010", &column
, &first
);
9278 show (stream
, "4100", &column
, &first
);
9279 show (stream
, "4111", &column
, &first
);
9280 show (stream
, "4300", &column
, &first
);
9281 show (stream
, "4400", &column
, &first
);
9282 show (stream
, "4600", &column
, &first
);
9283 show (stream
, "4650", &column
, &first
);
9284 show (stream
, "5000", &column
, &first
);
9285 show (stream
, "6000", &column
, &first
);
9286 show (stream
, "8000", &column
, &first
);
9287 show (stream
, "10000", &column
, &first
);
9288 fputc ('\n', stream
);
9290 fprintf (stream
, _("\
9291 -mCPU equivalent to -mcpu=CPU.\n\
9292 -no-mCPU don't generate code specific to CPU.\n\
9293 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9297 show (stream
, "3900", &column
, &first
);
9298 show (stream
, "4010", &column
, &first
);
9299 show (stream
, "4100", &column
, &first
);
9300 show (stream
, "4650", &column
, &first
);
9301 fputc ('\n', stream
);
9303 fprintf(stream
, _("\
9304 -mips16 generate mips16 instructions\n\
9305 -no-mips16 do not generate mips16 instructions\n"));
9306 fprintf(stream
, _("\
9307 -O0 remove unneeded NOPs, do not swap branches\n\
9308 -O remove unneeded NOPs and swap branches\n\
9309 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9310 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9312 fprintf(stream
, _("\
9313 -KPIC, -call_shared generate SVR4 position independent code\n\
9314 -non_shared do not generate position independent code\n\
9315 -xgot assume a 32 bit GOT\n\
9316 -32 create 32 bit object file (default)\n\
9317 -64 create 64 bit object file\n"));
9322 mips_init_after_args ()
9324 /* initialize opcodes */
9325 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9326 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9330 md_pcrel_from (fixP
)
9333 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9334 && fixP
->fx_addsy
!= (symbolS
*) NULL
9335 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9337 /* This makes a branch to an undefined symbol be a branch to the
9338 current location. */
9342 /* return the address of the delay slot */
9343 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9346 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9347 reloc for a cons. We could use the definition there, except that
9348 we want to handle 64 bit relocs specially. */
9351 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9354 unsigned int nbytes
;
9358 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9360 if (nbytes
== 8 && ! mips_64
)
9362 if (target_big_endian
)
9368 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9369 as_bad (_("Unsupported reloc size %d"), nbytes
);
9371 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9374 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9377 /* This is called before the symbol table is processed. In order to
9378 work with gcc when using mips-tfile, we must keep all local labels.
9379 However, in other cases, we want to discard them. If we were
9380 called with -g, but we didn't see any debugging information, it may
9381 mean that gcc is smuggling debugging information through to
9382 mips-tfile, in which case we must generate all local labels. */
9385 mips_frob_file_before_adjust ()
9387 #ifndef NO_ECOFF_DEBUGGING
9390 && ! ecoff_debugging_seen
)
9391 flag_keep_locals
= 1;
9395 /* Sort any unmatched HI16_S relocs so that they immediately precede
9396 the corresponding LO reloc. This is called before md_apply_fix and
9397 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9398 explicit use of the %hi modifier. */
9403 struct mips_hi_fixup
*l
;
9405 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9407 segment_info_type
*seginfo
;
9410 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9412 /* Check quickly whether the next fixup happens to be a matching
9414 if (l
->fixp
->fx_next
!= NULL
9415 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9416 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9417 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9420 /* Look through the fixups for this segment for a matching %lo.
9421 When we find one, move the %hi just in front of it. We do
9422 this in two passes. In the first pass, we try to find a
9423 unique %lo. In the second pass, we permit multiple %hi
9424 relocs for a single %lo (this is a GNU extension). */
9425 seginfo
= seg_info (l
->seg
);
9426 for (pass
= 0; pass
< 2; pass
++)
9431 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9433 /* Check whether this is a %lo fixup which matches l->fixp. */
9434 if (f
->fx_r_type
== BFD_RELOC_LO16
9435 && f
->fx_addsy
== l
->fixp
->fx_addsy
9436 && f
->fx_offset
== l
->fixp
->fx_offset
9439 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9440 || prev
->fx_addsy
!= f
->fx_addsy
9441 || prev
->fx_offset
!= f
->fx_offset
))
9445 /* Move l->fixp before f. */
9446 for (pf
= &seginfo
->fix_root
;
9448 pf
= &(*pf
)->fx_next
)
9449 assert (*pf
!= NULL
);
9451 *pf
= l
->fixp
->fx_next
;
9453 l
->fixp
->fx_next
= f
;
9455 seginfo
->fix_root
= l
->fixp
;
9457 prev
->fx_next
= l
->fixp
;
9468 #if 0 /* GCC code motion plus incomplete dead code elimination
9469 can leave a %hi without a %lo. */
9471 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9472 _("Unmatched %%hi reloc"));
9478 /* When generating embedded PIC code we need to use a special
9479 relocation to represent the difference of two symbols in the .text
9480 section (switch tables use a difference of this sort). See
9481 include/coff/mips.h for details. This macro checks whether this
9482 fixup requires the special reloc. */
9483 #define SWITCH_TABLE(fixp) \
9484 ((fixp)->fx_r_type == BFD_RELOC_32 \
9485 && (fixp)->fx_addsy != NULL \
9486 && (fixp)->fx_subsy != NULL \
9487 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9488 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9490 /* When generating embedded PIC code we must keep all PC relative
9491 relocations, in case the linker has to relax a call. We also need
9492 to keep relocations for switch table entries. */
9496 mips_force_relocation (fixp
)
9499 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9500 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9503 return (mips_pic
== EMBEDDED_PIC
9505 || SWITCH_TABLE (fixp
)
9506 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9507 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9510 /* Apply a fixup to the object file. */
9513 md_apply_fix (fixP
, valueP
)
9520 assert (fixP
->fx_size
== 4
9521 || fixP
->fx_r_type
== BFD_RELOC_16
9522 || fixP
->fx_r_type
== BFD_RELOC_64
9523 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9524 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9528 /* If we aren't adjusting this fixup to be against the section
9529 symbol, we need to adjust the value. */
9531 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9532 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9533 || S_IS_WEAK (fixP
->fx_addsy
)
9534 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9535 && (((bfd_get_section_flags (stdoutput
,
9536 S_GET_SEGMENT (fixP
->fx_addsy
))
9537 & SEC_LINK_ONCE
) != 0)
9538 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9540 sizeof (".gnu.linkonce") - 1))))
9543 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9544 if (value
!= 0 && ! fixP
->fx_pcrel
)
9546 /* In this case, the bfd_install_relocation routine will
9547 incorrectly add the symbol value back in. We just want
9548 the addend to appear in the object file. */
9549 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9555 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9557 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9560 switch (fixP
->fx_r_type
)
9562 case BFD_RELOC_MIPS_JMP
:
9563 case BFD_RELOC_HI16
:
9564 case BFD_RELOC_HI16_S
:
9565 case BFD_RELOC_MIPS_GPREL
:
9566 case BFD_RELOC_MIPS_LITERAL
:
9567 case BFD_RELOC_MIPS_CALL16
:
9568 case BFD_RELOC_MIPS_GOT16
:
9569 case BFD_RELOC_MIPS_GPREL32
:
9570 case BFD_RELOC_MIPS_GOT_HI16
:
9571 case BFD_RELOC_MIPS_GOT_LO16
:
9572 case BFD_RELOC_MIPS_CALL_HI16
:
9573 case BFD_RELOC_MIPS_CALL_LO16
:
9574 case BFD_RELOC_MIPS16_GPREL
:
9576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9577 _("Invalid PC relative reloc"));
9578 /* Nothing needed to do. The value comes from the reloc entry */
9581 case BFD_RELOC_MIPS16_JMP
:
9582 /* We currently always generate a reloc against a symbol, which
9583 means that we don't want an addend even if the symbol is
9585 fixP
->fx_addnumber
= 0;
9588 case BFD_RELOC_PCREL_HI16_S
:
9589 /* The addend for this is tricky if it is internal, so we just
9590 do everything here rather than in bfd_install_relocation. */
9591 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9593 /* For an external symbol adjust by the address to make it
9594 pcrel_offset. We use the address of the RELLO reloc
9595 which follows this one. */
9596 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9597 + fixP
->fx_next
->fx_where
);
9602 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9603 if (target_big_endian
)
9605 md_number_to_chars (buf
, value
, 2);
9608 case BFD_RELOC_PCREL_LO16
:
9609 /* The addend for this is tricky if it is internal, so we just
9610 do everything here rather than in bfd_install_relocation. */
9611 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9612 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9613 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9614 if (target_big_endian
)
9616 md_number_to_chars (buf
, value
, 2);
9620 /* This is handled like BFD_RELOC_32, but we output a sign
9621 extended value if we are only 32 bits. */
9623 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9625 if (8 <= sizeof (valueT
))
9626 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9633 w1
= w2
= fixP
->fx_where
;
9634 if (target_big_endian
)
9638 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9639 if ((value
& 0x80000000) != 0)
9643 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9649 /* If we are deleting this reloc entry, we must fill in the
9650 value now. This can happen if we have a .word which is not
9651 resolved when it appears but is later defined. We also need
9652 to fill in the value if this is an embedded PIC switch table
9655 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9656 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9661 /* If we are deleting this reloc entry, we must fill in the
9663 assert (fixP
->fx_size
== 2);
9665 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9669 case BFD_RELOC_LO16
:
9670 /* When handling an embedded PIC switch statement, we can wind
9671 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9674 if (value
< -0x8000 || value
> 0x7fff)
9675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9676 _("relocation overflow"));
9677 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9678 if (target_big_endian
)
9680 md_number_to_chars (buf
, value
, 2);
9684 case BFD_RELOC_16_PCREL_S2
:
9686 * We need to save the bits in the instruction since fixup_segment()
9687 * might be deleting the relocation entry (i.e., a branch within
9688 * the current segment).
9690 if ((value
& 0x3) != 0)
9691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9692 _("Branch to odd address (%lx)"), value
);
9695 /* update old instruction data */
9696 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9697 if (target_big_endian
)
9698 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9700 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9702 if (value
>= -0x8000 && value
< 0x8000)
9703 insn
|= value
& 0xffff;
9706 /* The branch offset is too large. If this is an
9707 unconditional branch, and we are not generating PIC code,
9708 we can convert it to an absolute jump instruction. */
9709 if (mips_pic
== NO_PIC
9711 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9712 && (fixP
->fx_frag
->fr_address
9713 < text_section
->vma
+ text_section
->_raw_size
)
9714 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9715 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9716 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9718 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9719 insn
= 0x0c000000; /* jal */
9721 insn
= 0x08000000; /* j */
9722 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9724 fixP
->fx_addsy
= section_symbol (text_section
);
9725 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9729 /* FIXME. It would be possible in principle to handle
9730 conditional branches which overflow. They could be
9731 transformed into a branch around a jump. This would
9732 require setting up variant frags for each different
9733 branch type. The native MIPS assembler attempts to
9734 handle these cases, but it appears to do it
9736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9737 _("Branch out of range"));
9741 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9744 case BFD_RELOC_VTABLE_INHERIT
:
9747 && !S_IS_DEFINED (fixP
->fx_addsy
)
9748 && !S_IS_WEAK (fixP
->fx_addsy
))
9749 S_SET_WEAK (fixP
->fx_addsy
);
9752 case BFD_RELOC_VTABLE_ENTRY
:
9768 const struct mips_opcode
*p
;
9769 int treg
, sreg
, dreg
, shamt
;
9774 for (i
= 0; i
< NUMOPCODES
; ++i
)
9776 p
= &mips_opcodes
[i
];
9777 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9779 printf ("%08lx %s\t", oc
, p
->name
);
9780 treg
= (oc
>> 16) & 0x1f;
9781 sreg
= (oc
>> 21) & 0x1f;
9782 dreg
= (oc
>> 11) & 0x1f;
9783 shamt
= (oc
>> 6) & 0x1f;
9785 for (args
= p
->args
;; ++args
)
9796 printf ("%c", *args
);
9800 assert (treg
== sreg
);
9801 printf ("$%d,$%d", treg
, sreg
);
9806 printf ("$%d", dreg
);
9811 printf ("$%d", treg
);
9815 printf ("0x%x", treg
);
9820 printf ("$%d", sreg
);
9824 printf ("0x%08lx", oc
& 0x1ffffff);
9836 printf ("$%d", shamt
);
9847 printf (_("%08lx UNDEFINED\n"), oc
);
9858 name
= input_line_pointer
;
9859 c
= get_symbol_end ();
9860 p
= (symbolS
*) symbol_find_or_make (name
);
9861 *input_line_pointer
= c
;
9865 /* Align the current frag to a given power of two. The MIPS assembler
9866 also automatically adjusts any preceding label. */
9869 mips_align (to
, fill
, label
)
9874 mips_emit_delays (false);
9875 frag_align (to
, fill
, 0);
9876 record_alignment (now_seg
, to
);
9879 assert (S_GET_SEGMENT (label
) == now_seg
);
9880 symbol_set_frag (label
, frag_now
);
9881 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9885 /* Align to a given power of two. .align 0 turns off the automatic
9886 alignment used by the data creating pseudo-ops. */
9893 register long temp_fill
;
9894 long max_alignment
= 15;
9898 o Note that the assembler pulls down any immediately preceeding label
9899 to the aligned address.
9900 o It's not documented but auto alignment is reinstated by
9901 a .align pseudo instruction.
9902 o Note also that after auto alignment is turned off the mips assembler
9903 issues an error on attempt to assemble an improperly aligned data item.
9908 temp
= get_absolute_expression ();
9909 if (temp
> max_alignment
)
9910 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9913 as_warn (_("Alignment negative: 0 assumed."));
9916 if (*input_line_pointer
== ',')
9918 input_line_pointer
++;
9919 temp_fill
= get_absolute_expression ();
9926 mips_align (temp
, (int) temp_fill
,
9927 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9934 demand_empty_rest_of_line ();
9938 mips_flush_pending_output ()
9940 mips_emit_delays (false);
9941 mips_clear_insn_labels ();
9950 /* When generating embedded PIC code, we only use the .text, .lit8,
9951 .sdata and .sbss sections. We change the .data and .rdata
9952 pseudo-ops to use .sdata. */
9953 if (mips_pic
== EMBEDDED_PIC
9954 && (sec
== 'd' || sec
== 'r'))
9958 /* The ELF backend needs to know that we are changing sections, so
9959 that .previous works correctly. We could do something like check
9960 for a obj_section_change_hook macro, but that might be confusing
9961 as it would not be appropriate to use it in the section changing
9962 functions in read.c, since obj-elf.c intercepts those. FIXME:
9963 This should be cleaner, somehow. */
9964 obj_elf_section_change_hook ();
9967 mips_emit_delays (false);
9977 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9978 demand_empty_rest_of_line ();
9982 if (USE_GLOBAL_POINTER_OPT
)
9984 seg
= subseg_new (RDATA_SECTION_NAME
,
9985 (subsegT
) get_absolute_expression ());
9986 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9988 bfd_set_section_flags (stdoutput
, seg
,
9994 if (strcmp (TARGET_OS
, "elf") != 0)
9995 bfd_set_section_alignment (stdoutput
, seg
, 4);
9997 demand_empty_rest_of_line ();
10001 as_bad (_("No read only data section in this object file format"));
10002 demand_empty_rest_of_line ();
10008 if (USE_GLOBAL_POINTER_OPT
)
10010 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10011 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10013 bfd_set_section_flags (stdoutput
, seg
,
10014 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10016 if (strcmp (TARGET_OS
, "elf") != 0)
10017 bfd_set_section_alignment (stdoutput
, seg
, 4);
10019 demand_empty_rest_of_line ();
10024 as_bad (_("Global pointers not supported; recompile -G 0"));
10025 demand_empty_rest_of_line ();
10034 mips_enable_auto_align ()
10045 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10046 mips_emit_delays (false);
10047 if (log_size
> 0 && auto_align
)
10048 mips_align (log_size
, 0, label
);
10049 mips_clear_insn_labels ();
10050 cons (1 << log_size
);
10054 s_float_cons (type
)
10059 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10061 mips_emit_delays (false);
10066 mips_align (3, 0, label
);
10068 mips_align (2, 0, label
);
10071 mips_clear_insn_labels ();
10076 /* Handle .globl. We need to override it because on Irix 5 you are
10079 where foo is an undefined symbol, to mean that foo should be
10080 considered to be the address of a function. */
10091 name
= input_line_pointer
;
10092 c
= get_symbol_end ();
10093 symbolP
= symbol_find_or_make (name
);
10094 *input_line_pointer
= c
;
10095 SKIP_WHITESPACE ();
10097 /* On Irix 5, every global symbol that is not explicitly labelled as
10098 being a function is apparently labelled as being an object. */
10101 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10106 secname
= input_line_pointer
;
10107 c
= get_symbol_end ();
10108 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10110 as_bad (_("%s: no such section"), secname
);
10111 *input_line_pointer
= c
;
10113 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10114 flag
= BSF_FUNCTION
;
10117 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10119 S_SET_EXTERNAL (symbolP
);
10120 demand_empty_rest_of_line ();
10130 opt
= input_line_pointer
;
10131 c
= get_symbol_end ();
10135 /* FIXME: What does this mean? */
10137 else if (strncmp (opt
, "pic", 3) == 0)
10141 i
= atoi (opt
+ 3);
10145 mips_pic
= SVR4_PIC
;
10147 as_bad (_(".option pic%d not supported"), i
);
10149 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10151 if (g_switch_seen
&& g_switch_value
!= 0)
10152 as_warn (_("-G may not be used with SVR4 PIC code"));
10153 g_switch_value
= 0;
10154 bfd_set_gp_size (stdoutput
, 0);
10158 as_warn (_("Unrecognized option \"%s\""), opt
);
10160 *input_line_pointer
= c
;
10161 demand_empty_rest_of_line ();
10164 /* This structure is used to hold a stack of .set values. */
10166 struct mips_option_stack
10168 struct mips_option_stack
*next
;
10169 struct mips_set_options options
;
10172 static struct mips_option_stack
*mips_opts_stack
;
10174 /* Handle the .set pseudo-op. */
10180 char *name
= input_line_pointer
, ch
;
10182 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10183 input_line_pointer
++;
10184 ch
= *input_line_pointer
;
10185 *input_line_pointer
= '\0';
10187 if (strcmp (name
, "reorder") == 0)
10189 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10191 /* If we still have pending nops, we can discard them. The
10192 usual nop handling will insert any that are still
10194 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10195 * (mips_opts
.mips16
? 2 : 4));
10196 prev_nop_frag
= NULL
;
10198 mips_opts
.noreorder
= 0;
10200 else if (strcmp (name
, "noreorder") == 0)
10202 mips_emit_delays (true);
10203 mips_opts
.noreorder
= 1;
10204 mips_any_noreorder
= 1;
10206 else if (strcmp (name
, "at") == 0)
10208 mips_opts
.noat
= 0;
10210 else if (strcmp (name
, "noat") == 0)
10212 mips_opts
.noat
= 1;
10214 else if (strcmp (name
, "macro") == 0)
10216 mips_opts
.warn_about_macros
= 0;
10218 else if (strcmp (name
, "nomacro") == 0)
10220 if (mips_opts
.noreorder
== 0)
10221 as_bad (_("`noreorder' must be set before `nomacro'"));
10222 mips_opts
.warn_about_macros
= 1;
10224 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10226 mips_opts
.nomove
= 0;
10228 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10230 mips_opts
.nomove
= 1;
10232 else if (strcmp (name
, "bopt") == 0)
10234 mips_opts
.nobopt
= 0;
10236 else if (strcmp (name
, "nobopt") == 0)
10238 mips_opts
.nobopt
= 1;
10240 else if (strcmp (name
, "mips16") == 0
10241 || strcmp (name
, "MIPS-16") == 0)
10242 mips_opts
.mips16
= 1;
10243 else if (strcmp (name
, "nomips16") == 0
10244 || strcmp (name
, "noMIPS-16") == 0)
10245 mips_opts
.mips16
= 0;
10246 else if (strncmp (name
, "mips", 4) == 0)
10250 /* Permit the user to change the ISA on the fly. Needless to
10251 say, misuse can cause serious problems. */
10252 isa
= atoi (name
+ 4);
10254 mips_opts
.isa
= file_mips_isa
;
10255 else if (isa
< 1 || isa
> 4)
10256 as_bad (_("unknown ISA level"));
10258 mips_opts
.isa
= isa
;
10260 else if (strcmp (name
, "autoextend") == 0)
10261 mips_opts
.noautoextend
= 0;
10262 else if (strcmp (name
, "noautoextend") == 0)
10263 mips_opts
.noautoextend
= 1;
10264 else if (strcmp (name
, "push") == 0)
10266 struct mips_option_stack
*s
;
10268 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10269 s
->next
= mips_opts_stack
;
10270 s
->options
= mips_opts
;
10271 mips_opts_stack
= s
;
10273 else if (strcmp (name
, "pop") == 0)
10275 struct mips_option_stack
*s
;
10277 s
= mips_opts_stack
;
10279 as_bad (_(".set pop with no .set push"));
10282 /* If we're changing the reorder mode we need to handle
10283 delay slots correctly. */
10284 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10285 mips_emit_delays (true);
10286 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10288 if (prev_nop_frag
!= NULL
)
10290 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10291 * (mips_opts
.mips16
? 2 : 4));
10292 prev_nop_frag
= NULL
;
10296 mips_opts
= s
->options
;
10297 mips_opts_stack
= s
->next
;
10303 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10305 *input_line_pointer
= ch
;
10306 demand_empty_rest_of_line ();
10309 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10310 .option pic2. It means to generate SVR4 PIC calls. */
10313 s_abicalls (ignore
)
10316 mips_pic
= SVR4_PIC
;
10317 if (USE_GLOBAL_POINTER_OPT
)
10319 if (g_switch_seen
&& g_switch_value
!= 0)
10320 as_warn (_("-G may not be used with SVR4 PIC code"));
10321 g_switch_value
= 0;
10323 bfd_set_gp_size (stdoutput
, 0);
10324 demand_empty_rest_of_line ();
10327 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10328 PIC code. It sets the $gp register for the function based on the
10329 function address, which is in the register named in the argument.
10330 This uses a relocation against _gp_disp, which is handled specially
10331 by the linker. The result is:
10332 lui $gp,%hi(_gp_disp)
10333 addiu $gp,$gp,%lo(_gp_disp)
10334 addu $gp,$gp,.cpload argument
10335 The .cpload argument is normally $25 == $t9. */
10344 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10345 if (mips_pic
!= SVR4_PIC
)
10351 /* .cpload should be a in .set noreorder section. */
10352 if (mips_opts
.noreorder
== 0)
10353 as_warn (_(".cpload not in noreorder section"));
10355 ex
.X_op
= O_symbol
;
10356 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10357 ex
.X_op_symbol
= NULL
;
10358 ex
.X_add_number
= 0;
10360 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10361 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10363 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10364 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10365 (int) BFD_RELOC_LO16
);
10367 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10368 GP
, GP
, tc_get_register (0));
10370 demand_empty_rest_of_line ();
10373 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10374 offset from $sp. The offset is remembered, and after making a PIC
10375 call $gp is restored from that location. */
10378 s_cprestore (ignore
)
10384 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10385 if (mips_pic
!= SVR4_PIC
)
10391 mips_cprestore_offset
= get_absolute_expression ();
10393 ex
.X_op
= O_constant
;
10394 ex
.X_add_symbol
= NULL
;
10395 ex
.X_op_symbol
= NULL
;
10396 ex
.X_add_number
= mips_cprestore_offset
;
10398 macro_build ((char *) NULL
, &icnt
, &ex
,
10399 ((bfd_arch_bits_per_address (stdoutput
) == 32
10400 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10402 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10404 demand_empty_rest_of_line ();
10407 /* Handle the .gpword pseudo-op. This is used when generating PIC
10408 code. It generates a 32 bit GP relative reloc. */
10418 /* When not generating PIC code, this is treated as .word. */
10419 if (mips_pic
!= SVR4_PIC
)
10425 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10426 mips_emit_delays (true);
10428 mips_align (2, 0, label
);
10429 mips_clear_insn_labels ();
10433 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10435 as_bad (_("Unsupported use of .gpword"));
10436 ignore_rest_of_line ();
10440 md_number_to_chars (p
, (valueT
) 0, 4);
10441 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10442 BFD_RELOC_MIPS_GPREL32
);
10444 demand_empty_rest_of_line ();
10447 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10448 tables in SVR4 PIC code. */
10457 /* This is ignored when not generating SVR4 PIC code. */
10458 if (mips_pic
!= SVR4_PIC
)
10464 /* Add $gp to the register named as an argument. */
10465 reg
= tc_get_register (0);
10466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10467 ((bfd_arch_bits_per_address (stdoutput
) == 32
10468 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10469 ? "addu" : "daddu"),
10470 "d,v,t", reg
, reg
, GP
);
10472 demand_empty_rest_of_line ();
10475 /* Handle the .insn pseudo-op. This marks instruction labels in
10476 mips16 mode. This permits the linker to handle them specially,
10477 such as generating jalx instructions when needed. We also make
10478 them odd for the duration of the assembly, in order to generate the
10479 right sort of code. We will make them even in the adjust_symtab
10480 routine, while leaving them marked. This is convenient for the
10481 debugger and the disassembler. The linker knows to make them odd
10488 if (mips_opts
.mips16
)
10489 mips16_mark_labels ();
10491 demand_empty_rest_of_line ();
10494 /* Handle a .stabn directive. We need these in order to mark a label
10495 as being a mips16 text label correctly. Sometimes the compiler
10496 will emit a label, followed by a .stabn, and then switch sections.
10497 If the label and .stabn are in mips16 mode, then the label is
10498 really a mips16 text label. */
10504 if (type
== 'n' && mips_opts
.mips16
)
10505 mips16_mark_labels ();
10510 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10514 s_mips_weakext (ignore
)
10522 name
= input_line_pointer
;
10523 c
= get_symbol_end ();
10524 symbolP
= symbol_find_or_make (name
);
10525 S_SET_WEAK (symbolP
);
10526 *input_line_pointer
= c
;
10528 SKIP_WHITESPACE ();
10530 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10532 if (S_IS_DEFINED (symbolP
))
10534 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10535 S_GET_NAME (symbolP
));
10536 ignore_rest_of_line ();
10540 if (*input_line_pointer
== ',')
10542 ++input_line_pointer
;
10543 SKIP_WHITESPACE ();
10547 if (exp
.X_op
!= O_symbol
)
10549 as_bad ("bad .weakext directive");
10550 ignore_rest_of_line();
10553 symbol_set_value_expression (symbolP
, &exp
);
10556 demand_empty_rest_of_line ();
10559 /* Parse a register string into a number. Called from the ECOFF code
10560 to parse .frame. The argument is non-zero if this is the frame
10561 register, so that we can record it in mips_frame_reg. */
10564 tc_get_register (frame
)
10569 SKIP_WHITESPACE ();
10570 if (*input_line_pointer
++ != '$')
10572 as_warn (_("expected `$'"));
10575 else if (isdigit ((unsigned char) *input_line_pointer
))
10577 reg
= get_absolute_expression ();
10578 if (reg
< 0 || reg
>= 32)
10580 as_warn (_("Bad register number"));
10586 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10588 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10590 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10592 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10596 as_warn (_("Unrecognized register name"));
10599 input_line_pointer
+= 2;
10602 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10607 md_section_align (seg
, addr
)
10611 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10614 /* We don't need to align ELF sections to the full alignment.
10615 However, Irix 5 may prefer that we align them at least to a 16
10616 byte boundary. We don't bother to align the sections if we are
10617 targeted for an embedded system. */
10618 if (strcmp (TARGET_OS
, "elf") == 0)
10624 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10627 /* Utility routine, called from above as well. If called while the
10628 input file is still being read, it's only an approximation. (For
10629 example, a symbol may later become defined which appeared to be
10630 undefined earlier.) */
10633 nopic_need_relax (sym
, before_relaxing
)
10635 int before_relaxing
;
10640 if (USE_GLOBAL_POINTER_OPT
)
10642 const char *symname
;
10645 /* Find out whether this symbol can be referenced off the GP
10646 register. It can be if it is smaller than the -G size or if
10647 it is in the .sdata or .sbss section. Certain symbols can
10648 not be referenced off the GP, although it appears as though
10650 symname
= S_GET_NAME (sym
);
10651 if (symname
!= (const char *) NULL
10652 && (strcmp (symname
, "eprol") == 0
10653 || strcmp (symname
, "etext") == 0
10654 || strcmp (symname
, "_gp") == 0
10655 || strcmp (symname
, "edata") == 0
10656 || strcmp (symname
, "_fbss") == 0
10657 || strcmp (symname
, "_fdata") == 0
10658 || strcmp (symname
, "_ftext") == 0
10659 || strcmp (symname
, "end") == 0
10660 || strcmp (symname
, "_gp_disp") == 0))
10662 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10664 #ifndef NO_ECOFF_DEBUGGING
10665 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10666 && (symbol_get_obj (sym
)->ecoff_extern_size
10667 <= g_switch_value
))
10669 /* We must defer this decision until after the whole
10670 file has been read, since there might be a .extern
10671 after the first use of this symbol. */
10672 || (before_relaxing
10673 #ifndef NO_ECOFF_DEBUGGING
10674 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10676 && S_GET_VALUE (sym
) == 0)
10677 || (S_GET_VALUE (sym
) != 0
10678 && S_GET_VALUE (sym
) <= g_switch_value
)))
10682 const char *segname
;
10684 segname
= segment_name (S_GET_SEGMENT (sym
));
10685 assert (strcmp (segname
, ".lit8") != 0
10686 && strcmp (segname
, ".lit4") != 0);
10687 change
= (strcmp (segname
, ".sdata") != 0
10688 && strcmp (segname
, ".sbss") != 0
10689 && strncmp (segname
, ".sdata.", 7) != 0
10690 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10695 /* We are not optimizing for the GP register. */
10699 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10700 extended opcode. SEC is the section the frag is in. */
10703 mips16_extended_frag (fragp
, sec
, stretch
)
10709 register const struct mips16_immed_operand
*op
;
10711 int mintiny
, maxtiny
;
10714 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10716 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10719 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10720 op
= mips16_immed_operands
;
10721 while (op
->type
!= type
)
10724 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10729 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10732 maxtiny
= 1 << op
->nbits
;
10737 maxtiny
= (1 << op
->nbits
) - 1;
10742 mintiny
= - (1 << (op
->nbits
- 1));
10743 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10746 /* We can't always call S_GET_VALUE here, because we don't want to
10747 lock in a particular frag address. */
10748 if (symbol_constant_p (fragp
->fr_symbol
))
10750 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10751 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10752 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10754 else if (symbol_equated_p (fragp
->fr_symbol
)
10755 && (symbol_constant_p
10756 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10760 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10761 val
= (S_GET_VALUE (eqsym
)
10762 + symbol_get_frag (eqsym
)->fr_address
10763 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10764 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10765 symsec
= S_GET_SEGMENT (eqsym
);
10774 /* We won't have the section when we are called from
10775 mips_relax_frag. However, we will always have been called
10776 from md_estimate_size_before_relax first. If this is a
10777 branch to a different section, we mark it as such. If SEC is
10778 NULL, and the frag is not marked, then it must be a branch to
10779 the same section. */
10782 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10789 fragp
->fr_subtype
=
10790 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10792 /* FIXME: We should support this, and let the linker
10793 catch branches and loads that are out of range. */
10794 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10795 _("unsupported PC relative reference to different section"));
10801 /* In this case, we know for sure that the symbol fragment is in
10802 the same section. If the fr_address of the symbol fragment
10803 is greater then the address of this fragment we want to add
10804 in STRETCH in order to get a better estimate of the address.
10805 This particularly matters because of the shift bits. */
10807 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10808 >= fragp
->fr_address
))
10812 /* Adjust stretch for any alignment frag. Note that if have
10813 been expanding the earlier code, the symbol may be
10814 defined in what appears to be an earlier frag. FIXME:
10815 This doesn't handle the fr_subtype field, which specifies
10816 a maximum number of bytes to skip when doing an
10819 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10822 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10825 stretch
= - ((- stretch
)
10826 & ~ ((1 << (int) f
->fr_offset
) - 1));
10828 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10837 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10839 /* The base address rules are complicated. The base address of
10840 a branch is the following instruction. The base address of a
10841 PC relative load or add is the instruction itself, but if it
10842 is in a delay slot (in which case it can not be extended) use
10843 the address of the instruction whose delay slot it is in. */
10844 if (type
== 'p' || type
== 'q')
10848 /* If we are currently assuming that this frag should be
10849 extended, then, the current address is two bytes
10851 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10854 /* Ignore the low bit in the target, since it will be set
10855 for a text label. */
10856 if ((val
& 1) != 0)
10859 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10861 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10864 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10866 /* Branch offsets have an implicit 0 in the lowest bit. */
10867 if (type
== 'p' || type
== 'q')
10870 /* If any of the shifted bits are set, we must use an extended
10871 opcode. If the address depends on the size of this
10872 instruction, this can lead to a loop, so we arrange to always
10873 use an extended opcode. We only check this when we are in
10874 the main relaxation loop, when SEC is NULL. */
10875 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10877 fragp
->fr_subtype
=
10878 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10882 /* If we are about to mark a frag as extended because the value
10883 is precisely maxtiny + 1, then there is a chance of an
10884 infinite loop as in the following code:
10889 In this case when the la is extended, foo is 0x3fc bytes
10890 away, so the la can be shrunk, but then foo is 0x400 away, so
10891 the la must be extended. To avoid this loop, we mark the
10892 frag as extended if it was small, and is about to become
10893 extended with a value of maxtiny + 1. */
10894 if (val
== ((maxtiny
+ 1) << op
->shift
)
10895 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10898 fragp
->fr_subtype
=
10899 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10903 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10904 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10906 if ((val
& ((1 << op
->shift
) - 1)) != 0
10907 || val
< (mintiny
<< op
->shift
)
10908 || val
> (maxtiny
<< op
->shift
))
10914 /* Estimate the size of a frag before relaxing. Unless this is the
10915 mips16, we are not really relaxing here, and the final size is
10916 encoded in the subtype information. For the mips16, we have to
10917 decide whether we are using an extended opcode or not. */
10921 md_estimate_size_before_relax (fragp
, segtype
)
10927 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10929 if (mips16_extended_frag (fragp
, segtype
, 0))
10931 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10936 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10941 if (mips_pic
== NO_PIC
)
10943 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10945 else if (mips_pic
== SVR4_PIC
)
10950 sym
= fragp
->fr_symbol
;
10952 /* Handle the case of a symbol equated to another symbol. */
10953 while (symbol_equated_p (sym
)
10954 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10958 /* It's possible to get a loop here in a badly written
10960 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10966 symsec
= S_GET_SEGMENT (sym
);
10968 /* This must duplicate the test in adjust_reloc_syms. */
10969 change
= (symsec
!= &bfd_und_section
10970 && symsec
!= &bfd_abs_section
10971 && ! bfd_is_com_section (symsec
));
10978 /* Record the offset to the first reloc in the fr_opcode field.
10979 This lets md_convert_frag and tc_gen_reloc know that the code
10980 must be expanded. */
10981 fragp
->fr_opcode
= (fragp
->fr_literal
10983 - RELAX_OLD (fragp
->fr_subtype
)
10984 + RELAX_RELOC1 (fragp
->fr_subtype
));
10985 /* FIXME: This really needs as_warn_where. */
10986 if (RELAX_WARN (fragp
->fr_subtype
))
10987 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
10993 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10996 /* This is called to see whether a reloc against a defined symbol
10997 should be converted into a reloc against a section. Don't adjust
10998 MIPS16 jump relocations, so we don't have to worry about the format
10999 of the offset in the .o file. Don't adjust relocations against
11000 mips16 symbols, so that the linker can find them if it needs to set
11004 mips_fix_adjustable (fixp
)
11007 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11009 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11010 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11012 if (fixp
->fx_addsy
== NULL
)
11015 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11016 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11017 && fixp
->fx_subsy
== NULL
)
11023 /* Translate internal representation of relocation info to BFD target
11027 tc_gen_reloc (section
, fixp
)
11031 static arelent
*retval
[4];
11033 bfd_reloc_code_real_type code
;
11035 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11038 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11039 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11040 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11042 if (mips_pic
== EMBEDDED_PIC
11043 && SWITCH_TABLE (fixp
))
11045 /* For a switch table entry we use a special reloc. The addend
11046 is actually the difference between the reloc address and the
11048 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11049 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11050 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11051 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11053 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11055 /* We use a special addend for an internal RELLO reloc. */
11056 if (symbol_section_p (fixp
->fx_addsy
))
11057 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11059 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11061 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11063 assert (fixp
->fx_next
!= NULL
11064 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11065 /* We use a special addend for an internal RELHI reloc. The
11066 reloc is relative to the RELLO; adjust the addend
11068 if (symbol_section_p (fixp
->fx_addsy
))
11069 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11070 + fixp
->fx_next
->fx_where
11071 - S_GET_VALUE (fixp
->fx_subsy
));
11073 reloc
->addend
= (fixp
->fx_addnumber
11074 + fixp
->fx_next
->fx_frag
->fr_address
11075 + fixp
->fx_next
->fx_where
);
11077 else if (fixp
->fx_pcrel
== 0)
11078 reloc
->addend
= fixp
->fx_addnumber
;
11081 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11082 /* A gruesome hack which is a result of the gruesome gas reloc
11084 reloc
->addend
= reloc
->address
;
11086 reloc
->addend
= -reloc
->address
;
11089 /* If this is a variant frag, we may need to adjust the existing
11090 reloc and generate a new one. */
11091 if (fixp
->fx_frag
->fr_opcode
!= NULL
11092 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11093 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11094 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11095 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11096 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11097 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11098 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11102 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11104 /* If this is not the last reloc in this frag, then we have two
11105 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11106 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11107 the second one handle all of them. */
11108 if (fixp
->fx_next
!= NULL
11109 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11111 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11112 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11113 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11114 && (fixp
->fx_next
->fx_r_type
11115 == BFD_RELOC_MIPS_GOT_LO16
))
11116 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11117 && (fixp
->fx_next
->fx_r_type
11118 == BFD_RELOC_MIPS_CALL_LO16
)));
11123 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11124 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11125 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11127 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11128 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11129 reloc2
->address
= (reloc
->address
11130 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11131 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11132 reloc2
->addend
= fixp
->fx_addnumber
;
11133 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11134 assert (reloc2
->howto
!= NULL
);
11136 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11140 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11143 reloc3
->address
+= 4;
11146 if (mips_pic
== NO_PIC
)
11148 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11149 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11151 else if (mips_pic
== SVR4_PIC
)
11153 switch (fixp
->fx_r_type
)
11157 case BFD_RELOC_MIPS_GOT16
:
11159 case BFD_RELOC_MIPS_CALL16
:
11160 case BFD_RELOC_MIPS_GOT_LO16
:
11161 case BFD_RELOC_MIPS_CALL_LO16
:
11162 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11170 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11171 to be used in the relocation's section offset. */
11172 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11174 reloc
->address
= reloc
->addend
;
11178 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11179 fixup_segment converted a non-PC relative reloc into a PC
11180 relative reloc. In such a case, we need to convert the reloc
11182 code
= fixp
->fx_r_type
;
11183 if (fixp
->fx_pcrel
)
11188 code
= BFD_RELOC_8_PCREL
;
11191 code
= BFD_RELOC_16_PCREL
;
11194 code
= BFD_RELOC_32_PCREL
;
11197 code
= BFD_RELOC_64_PCREL
;
11199 case BFD_RELOC_8_PCREL
:
11200 case BFD_RELOC_16_PCREL
:
11201 case BFD_RELOC_32_PCREL
:
11202 case BFD_RELOC_64_PCREL
:
11203 case BFD_RELOC_16_PCREL_S2
:
11204 case BFD_RELOC_PCREL_HI16_S
:
11205 case BFD_RELOC_PCREL_LO16
:
11208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11209 _("Cannot make %s relocation PC relative"),
11210 bfd_get_reloc_code_name (code
));
11214 /* To support a PC relative reloc when generating embedded PIC code
11215 for ECOFF, we use a Cygnus extension. We check for that here to
11216 make sure that we don't let such a reloc escape normally. */
11217 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11218 && code
== BFD_RELOC_16_PCREL_S2
11219 && mips_pic
!= EMBEDDED_PIC
)
11220 reloc
->howto
= NULL
;
11222 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11224 if (reloc
->howto
== NULL
)
11226 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11227 _("Can not represent %s relocation in this object file format"),
11228 bfd_get_reloc_code_name (code
));
11235 /* Relax a machine dependent frag. This returns the amount by which
11236 the current size of the frag should change. */
11239 mips_relax_frag (fragp
, stretch
)
11243 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11246 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11248 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11250 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11255 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11257 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11264 /* Convert a machine dependent frag. */
11267 md_convert_frag (abfd
, asec
, fragp
)
11275 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11278 register const struct mips16_immed_operand
*op
;
11279 boolean small
, ext
;
11282 unsigned long insn
;
11283 boolean use_extend
;
11284 unsigned short extend
;
11286 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11287 op
= mips16_immed_operands
;
11288 while (op
->type
!= type
)
11291 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11302 resolve_symbol_value (fragp
->fr_symbol
, 1);
11303 val
= S_GET_VALUE (fragp
->fr_symbol
);
11308 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11310 /* The rules for the base address of a PC relative reloc are
11311 complicated; see mips16_extended_frag. */
11312 if (type
== 'p' || type
== 'q')
11317 /* Ignore the low bit in the target, since it will be
11318 set for a text label. */
11319 if ((val
& 1) != 0)
11322 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11324 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11327 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11330 /* Make sure the section winds up with the alignment we have
11333 record_alignment (asec
, op
->shift
);
11337 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11338 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11339 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11340 _("extended instruction in delay slot"));
11342 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11344 if (target_big_endian
)
11345 insn
= bfd_getb16 (buf
);
11347 insn
= bfd_getl16 (buf
);
11349 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11350 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11351 small
, ext
, &insn
, &use_extend
, &extend
);
11355 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11356 fragp
->fr_fix
+= 2;
11360 md_number_to_chars (buf
, insn
, 2);
11361 fragp
->fr_fix
+= 2;
11366 if (fragp
->fr_opcode
== NULL
)
11369 old
= RELAX_OLD (fragp
->fr_subtype
);
11370 new = RELAX_NEW (fragp
->fr_subtype
);
11371 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11374 memcpy (fixptr
- old
, fixptr
, new);
11376 fragp
->fr_fix
+= new - old
;
11382 /* This function is called after the relocs have been generated.
11383 We've been storing mips16 text labels as odd. Here we convert them
11384 back to even for the convenience of the debugger. */
11387 mips_frob_file_after_relocs ()
11390 unsigned int count
, i
;
11392 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11395 syms
= bfd_get_outsymbols (stdoutput
);
11396 count
= bfd_get_symcount (stdoutput
);
11397 for (i
= 0; i
< count
; i
++, syms
++)
11399 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11400 && ((*syms
)->value
& 1) != 0)
11402 (*syms
)->value
&= ~1;
11403 /* If the symbol has an odd size, it was probably computed
11404 incorrectly, so adjust that as well. */
11405 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11406 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11413 /* This function is called whenever a label is defined. It is used
11414 when handling branch delays; if a branch has a label, we assume we
11415 can not move it. */
11418 mips_define_label (sym
)
11421 struct insn_label_list
*l
;
11423 if (free_insn_labels
== NULL
)
11424 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11427 l
= free_insn_labels
;
11428 free_insn_labels
= l
->next
;
11432 l
->next
= insn_labels
;
11436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11438 /* Some special processing for a MIPS ELF file. */
11441 mips_elf_final_processing ()
11443 /* Write out the register information. */
11448 s
.ri_gprmask
= mips_gprmask
;
11449 s
.ri_cprmask
[0] = mips_cprmask
[0];
11450 s
.ri_cprmask
[1] = mips_cprmask
[1];
11451 s
.ri_cprmask
[2] = mips_cprmask
[2];
11452 s
.ri_cprmask
[3] = mips_cprmask
[3];
11453 /* The gp_value field is set by the MIPS ELF backend. */
11455 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11456 ((Elf32_External_RegInfo
*)
11457 mips_regmask_frag
));
11461 Elf64_Internal_RegInfo s
;
11463 s
.ri_gprmask
= mips_gprmask
;
11465 s
.ri_cprmask
[0] = mips_cprmask
[0];
11466 s
.ri_cprmask
[1] = mips_cprmask
[1];
11467 s
.ri_cprmask
[2] = mips_cprmask
[2];
11468 s
.ri_cprmask
[3] = mips_cprmask
[3];
11469 /* The gp_value field is set by the MIPS ELF backend. */
11471 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11472 ((Elf64_External_RegInfo
*)
11473 mips_regmask_frag
));
11476 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11477 sort of BFD interface for this. */
11478 if (mips_any_noreorder
)
11479 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11480 if (mips_pic
!= NO_PIC
)
11481 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11483 /* Set the MIPS ELF ABI flags. */
11484 if (mips_abi_string
== 0)
11486 else if (strcmp (mips_abi_string
,"32") == 0)
11487 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11488 else if (strcmp (mips_abi_string
,"o64") == 0)
11489 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11490 else if (strcmp (mips_abi_string
,"eabi") == 0)
11493 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11495 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11498 if (mips_32bitmode
)
11499 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11502 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11504 typedef struct proc
11507 unsigned long reg_mask
;
11508 unsigned long reg_offset
;
11509 unsigned long fpreg_mask
;
11510 unsigned long fpreg_offset
;
11511 unsigned long frame_offset
;
11512 unsigned long frame_reg
;
11513 unsigned long pc_reg
;
11517 static procS cur_proc
;
11518 static procS
*cur_proc_ptr
;
11519 static int numprocs
;
11521 /* When we align code in the .text section of mips16, use the correct two
11522 byte nop pattern of 0x6500 (move $0,$0) */
11525 mips_do_align (n
, fill
, len
, max
)
11532 && subseg_text_p (now_seg
)
11534 && mips_opts
.mips16
)
11536 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11537 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11539 frag_align (1, 0, 0);
11541 if (target_big_endian
)
11542 frag_align_pattern (n
, be_nop
, 2, max
);
11544 frag_align_pattern (n
, le_nop
, 2, max
);
11559 /* check for premature end, nesting errors, etc */
11561 as_warn (_("missing `.end' at end of assembly"));
11570 if (*input_line_pointer
== '-')
11572 ++input_line_pointer
;
11575 if (!isdigit ((unsigned char) *input_line_pointer
))
11576 as_bad (_("Expected simple number."));
11577 if (input_line_pointer
[0] == '0')
11579 if (input_line_pointer
[1] == 'x')
11581 input_line_pointer
+= 2;
11582 while (isxdigit ((unsigned char) *input_line_pointer
))
11585 val
|= hex_value (*input_line_pointer
++);
11587 return negative
? -val
: val
;
11591 ++input_line_pointer
;
11592 while (isdigit ((unsigned char) *input_line_pointer
))
11595 val
|= *input_line_pointer
++ - '0';
11597 return negative
? -val
: val
;
11600 if (!isdigit ((unsigned char) *input_line_pointer
))
11602 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11603 *input_line_pointer
, *input_line_pointer
);
11604 as_warn (_("Invalid number"));
11607 while (isdigit ((unsigned char) *input_line_pointer
))
11610 val
+= *input_line_pointer
++ - '0';
11612 return negative
? -val
: val
;
11615 /* The .file directive; just like the usual .file directive, but there
11616 is an initial number which is the ECOFF file index. */
11624 line
= get_number ();
11629 /* The .end directive. */
11638 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11641 demand_empty_rest_of_line ();
11646 #ifdef BFD_ASSEMBLER
11647 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11652 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11659 as_warn (_(".end not in text section"));
11663 as_warn (_(".end directive without a preceding .ent directive."));
11664 demand_empty_rest_of_line ();
11670 assert (S_GET_NAME (p
));
11671 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11672 as_warn (_(".end symbol does not match .ent symbol."));
11675 as_warn (_(".end directive missing or unknown symbol"));
11677 #ifdef MIPS_STABS_ELF
11679 segT saved_seg
= now_seg
;
11680 subsegT saved_subseg
= now_subseg
;
11681 fragS
*saved_frag
= frag_now
;
11687 dot
= frag_now_fix ();
11689 #ifdef md_flush_pending_output
11690 md_flush_pending_output ();
11694 subseg_set (pdr_seg
, 0);
11696 /* Write the symbol */
11697 exp
.X_op
= O_symbol
;
11698 exp
.X_add_symbol
= p
;
11699 exp
.X_add_number
= 0;
11700 emit_expr (&exp
, 4);
11702 fragp
= frag_more (7*4);
11704 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11705 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11706 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11707 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11708 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11709 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11710 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11712 subseg_set (saved_seg
, saved_subseg
);
11716 cur_proc_ptr
= NULL
;
11719 /* The .aent and .ent directives. */
11729 symbolP
= get_symbol ();
11730 if (*input_line_pointer
== ',')
11731 input_line_pointer
++;
11732 SKIP_WHITESPACE ();
11733 if (isdigit ((unsigned char) *input_line_pointer
)
11734 || *input_line_pointer
== '-')
11735 number
= get_number ();
11737 #ifdef BFD_ASSEMBLER
11738 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11743 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11750 as_warn (_(".ent or .aent not in text section."));
11752 if (!aent
&& cur_proc_ptr
)
11753 as_warn (_("missing `.end'"));
11757 cur_proc_ptr
= &cur_proc
;
11758 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11760 cur_proc_ptr
->isym
= symbolP
;
11762 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11767 demand_empty_rest_of_line ();
11770 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11771 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11772 s_mips_frame is used so that we can set the PDR information correctly.
11773 We can't use the ecoff routines because they make reference to the ecoff
11774 symbol table (in the mdebug section). */
11777 s_mips_frame (ignore
)
11780 #ifdef MIPS_STABS_ELF
11784 if (cur_proc_ptr
== (procS
*) NULL
)
11786 as_warn (_(".frame outside of .ent"));
11787 demand_empty_rest_of_line ();
11791 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11793 SKIP_WHITESPACE ();
11794 if (*input_line_pointer
++ != ','
11795 || get_absolute_expression_and_terminator (&val
) != ',')
11797 as_warn (_("Bad .frame directive"));
11798 --input_line_pointer
;
11799 demand_empty_rest_of_line ();
11803 cur_proc_ptr
->frame_offset
= val
;
11804 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11806 demand_empty_rest_of_line ();
11809 #endif /* MIPS_STABS_ELF */
11812 /* The .fmask and .mask directives. If the mdebug section is present
11813 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11814 embedded targets, s_mips_mask is used so that we can set the PDR
11815 information correctly. We can't use the ecoff routines because they
11816 make reference to the ecoff symbol table (in the mdebug section). */
11819 s_mips_mask (reg_type
)
11822 #ifdef MIPS_STABS_ELF
11825 if (cur_proc_ptr
== (procS
*) NULL
)
11827 as_warn (_(".mask/.fmask outside of .ent"));
11828 demand_empty_rest_of_line ();
11832 if (get_absolute_expression_and_terminator (&mask
) != ',')
11834 as_warn (_("Bad .mask/.fmask directive"));
11835 --input_line_pointer
;
11836 demand_empty_rest_of_line ();
11840 off
= get_absolute_expression ();
11842 if (reg_type
== 'F')
11844 cur_proc_ptr
->fpreg_mask
= mask
;
11845 cur_proc_ptr
->fpreg_offset
= off
;
11849 cur_proc_ptr
->reg_mask
= mask
;
11850 cur_proc_ptr
->reg_offset
= off
;
11853 demand_empty_rest_of_line ();
11855 s_ignore (reg_type
);
11856 #endif /* MIPS_STABS_ELF */
11859 /* The .loc directive. */
11870 assert (now_seg
== text_section
);
11872 lineno
= get_number ();
11873 addroff
= frag_now_fix ();
11875 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11876 S_SET_TYPE (symbolP
, N_SLINE
);
11877 S_SET_OTHER (symbolP
, 0);
11878 S_SET_DESC (symbolP
, lineno
);
11879 symbolP
->sy_segment
= now_seg
;