1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
290 /* Return true if the given CPU supports the MIPS3D ASE. */
291 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
294 /* Return true if the given CPU supports the MDMX ASE. */
295 #define CPU_HAS_MDMX(cpu) (false \
298 /* Whether the processor uses hardware interlocks to protect
299 reads from the HI and LO registers, and thus does not
300 require nops to be inserted. */
302 #define hilo_interlocks (mips_arch == CPU_R4010 \
303 || mips_arch == CPU_SB1 \
306 /* Whether the processor uses hardware interlocks to protect reads
307 from the GPRs, and thus does not require nops to be inserted. */
308 #define gpr_interlocks \
309 (mips_opts.isa != ISA_MIPS1 \
310 || mips_arch == CPU_R3900)
312 /* As with other "interlocks" this is used by hardware that has FP
313 (co-processor) interlocks. */
314 /* Itbl support may require additional care here. */
315 #define cop_interlocks (mips_arch == CPU_R4300 \
316 || mips_arch == CPU_SB1 \
319 /* Is this a mfhi or mflo instruction? */
320 #define MF_HILO_INSN(PINFO) \
321 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
323 /* MIPS PIC level. */
325 enum mips_pic_level mips_pic
;
327 /* Warn about all NOPS that the assembler generates. */
328 static int warn_nops
= 0;
330 /* 1 if we should generate 32 bit offsets from the $gp register in
331 SVR4_PIC mode. Currently has no meaning in other modes. */
332 static int mips_big_got
= 0;
334 /* 1 if trap instructions should used for overflow rather than break
336 static int mips_trap
= 0;
338 /* 1 if double width floating point constants should not be constructed
339 by assembling two single width halves into two single width floating
340 point registers which just happen to alias the double width destination
341 register. On some architectures this aliasing can be disabled by a bit
342 in the status register, and the setting of this bit cannot be determined
343 automatically at assemble time. */
344 static int mips_disable_float_construction
;
346 /* Non-zero if any .set noreorder directives were used. */
348 static int mips_any_noreorder
;
350 /* Non-zero if nops should be inserted when the register referenced in
351 an mfhi/mflo instruction is read in the next two instructions. */
352 static int mips_7000_hilo_fix
;
354 /* The size of the small data section. */
355 static unsigned int g_switch_value
= 8;
356 /* Whether the -G option was used. */
357 static int g_switch_seen
= 0;
362 /* If we can determine in advance that GP optimization won't be
363 possible, we can skip the relaxation stuff that tries to produce
364 GP-relative references. This makes delay slot optimization work
367 This function can only provide a guess, but it seems to work for
368 gcc output. It needs to guess right for gcc, otherwise gcc
369 will put what it thinks is a GP-relative instruction in a branch
372 I don't know if a fix is needed for the SVR4_PIC mode. I've only
373 fixed it for the non-PIC mode. KR 95/04/07 */
374 static int nopic_need_relax
PARAMS ((symbolS
*, int));
376 /* handle of the OPCODE hash table */
377 static struct hash_control
*op_hash
= NULL
;
379 /* The opcode hash table we use for the mips16. */
380 static struct hash_control
*mips16_op_hash
= NULL
;
382 /* This array holds the chars that always start a comment. If the
383 pre-processor is disabled, these aren't very useful */
384 const char comment_chars
[] = "#";
386 /* This array holds the chars that only start a comment at the beginning of
387 a line. If the line seems to have the form '# 123 filename'
388 .line and .file directives will appear in the pre-processed output */
389 /* Note that input_file.c hand checks for '#' at the beginning of the
390 first line of the input file. This is because the compiler outputs
391 #NO_APP at the beginning of its output. */
392 /* Also note that C style comments are always supported. */
393 const char line_comment_chars
[] = "#";
395 /* This array holds machine specific line separator characters. */
396 const char line_separator_chars
[] = ";";
398 /* Chars that can be used to separate mant from exp in floating point nums */
399 const char EXP_CHARS
[] = "eE";
401 /* Chars that mean this number is a floating point constant */
404 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
406 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
407 changed in read.c . Ideally it shouldn't have to know about it at all,
408 but nothing is ideal around here.
411 static char *insn_error
;
413 static int auto_align
= 1;
415 /* When outputting SVR4 PIC code, the assembler needs to know the
416 offset in the stack frame from which to restore the $gp register.
417 This is set by the .cprestore pseudo-op, and saved in this
419 static offsetT mips_cprestore_offset
= -1;
421 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
422 more optimizations, it can use a register value instead of a memory-saved
423 offset and even an other register than $gp as global pointer. */
424 static offsetT mips_cpreturn_offset
= -1;
425 static int mips_cpreturn_register
= -1;
426 static int mips_gp_register
= GP
;
427 static int mips_gprel_offset
= 0;
429 /* Whether mips_cprestore_offset has been set in the current function
430 (or whether it has already been warned about, if not). */
431 static int mips_cprestore_valid
= 0;
433 /* This is the register which holds the stack frame, as set by the
434 .frame pseudo-op. This is needed to implement .cprestore. */
435 static int mips_frame_reg
= SP
;
437 /* Whether mips_frame_reg has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_frame_reg_valid
= 0;
441 /* To output NOP instructions correctly, we need to keep information
442 about the previous two instructions. */
444 /* Whether we are optimizing. The default value of 2 means to remove
445 unneeded NOPs and swap branch instructions when possible. A value
446 of 1 means to not swap branches. A value of 0 means to always
448 static int mips_optimize
= 2;
450 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
451 equivalent to seeing no -g option at all. */
452 static int mips_debug
= 0;
454 /* The previous instruction. */
455 static struct mips_cl_insn prev_insn
;
457 /* The instruction before prev_insn. */
458 static struct mips_cl_insn prev_prev_insn
;
460 /* If we don't want information for prev_insn or prev_prev_insn, we
461 point the insn_mo field at this dummy integer. */
462 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
464 /* Non-zero if prev_insn is valid. */
465 static int prev_insn_valid
;
467 /* The frag for the previous instruction. */
468 static struct frag
*prev_insn_frag
;
470 /* The offset into prev_insn_frag for the previous instruction. */
471 static long prev_insn_where
;
473 /* The reloc type for the previous instruction, if any. */
474 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
476 /* The reloc for the previous instruction, if any. */
477 static fixS
*prev_insn_fixp
[3];
479 /* Non-zero if the previous instruction was in a delay slot. */
480 static int prev_insn_is_delay_slot
;
482 /* Non-zero if the previous instruction was in a .set noreorder. */
483 static int prev_insn_unreordered
;
485 /* Non-zero if the previous instruction uses an extend opcode (if
487 static int prev_insn_extended
;
489 /* Non-zero if the previous previous instruction was in a .set
491 static int prev_prev_insn_unreordered
;
493 /* If this is set, it points to a frag holding nop instructions which
494 were inserted before the start of a noreorder section. If those
495 nops turn out to be unnecessary, the size of the frag can be
497 static fragS
*prev_nop_frag
;
499 /* The number of nop instructions we created in prev_nop_frag. */
500 static int prev_nop_frag_holds
;
502 /* The number of nop instructions that we know we need in
504 static int prev_nop_frag_required
;
506 /* The number of instructions we've seen since prev_nop_frag. */
507 static int prev_nop_frag_since
;
509 /* For ECOFF and ELF, relocations against symbols are done in two
510 parts, with a HI relocation and a LO relocation. Each relocation
511 has only 16 bits of space to store an addend. This means that in
512 order for the linker to handle carries correctly, it must be able
513 to locate both the HI and the LO relocation. This means that the
514 relocations must appear in order in the relocation table.
516 In order to implement this, we keep track of each unmatched HI
517 relocation. We then sort them so that they immediately precede the
518 corresponding LO relocation. */
523 struct mips_hi_fixup
*next
;
526 /* The section this fixup is in. */
530 /* The list of unmatched HI relocs. */
532 static struct mips_hi_fixup
*mips_hi_fixup_list
;
534 /* Map normal MIPS register numbers to mips16 register numbers. */
536 #define X ILLEGAL_REG
537 static const int mips32_to_16_reg_map
[] =
539 X
, X
, 2, 3, 4, 5, 6, 7,
540 X
, X
, X
, X
, X
, X
, X
, X
,
541 0, 1, X
, X
, X
, X
, X
, X
,
542 X
, X
, X
, X
, X
, X
, X
, X
546 /* Map mips16 register numbers to normal MIPS register numbers. */
548 static const unsigned int mips16_to_32_reg_map
[] =
550 16, 17, 2, 3, 4, 5, 6, 7
553 /* Since the MIPS does not have multiple forms of PC relative
554 instructions, we do not have to do relaxing as is done on other
555 platforms. However, we do have to handle GP relative addressing
556 correctly, which turns out to be a similar problem.
558 Every macro that refers to a symbol can occur in (at least) two
559 forms, one with GP relative addressing and one without. For
560 example, loading a global variable into a register generally uses
561 a macro instruction like this:
563 If i can be addressed off the GP register (this is true if it is in
564 the .sbss or .sdata section, or if it is known to be smaller than
565 the -G argument) this will generate the following instruction:
567 This instruction will use a GPREL reloc. If i can not be addressed
568 off the GP register, the following instruction sequence will be used:
571 In this case the first instruction will have a HI16 reloc, and the
572 second reloc will have a LO16 reloc. Both relocs will be against
575 The issue here is that we may not know whether i is GP addressable
576 until after we see the instruction that uses it. Therefore, we
577 want to be able to choose the final instruction sequence only at
578 the end of the assembly. This is similar to the way other
579 platforms choose the size of a PC relative instruction only at the
582 When generating position independent code we do not use GP
583 addressing in quite the same way, but the issue still arises as
584 external symbols and local symbols must be handled differently.
586 We handle these issues by actually generating both possible
587 instruction sequences. The longer one is put in a frag_var with
588 type rs_machine_dependent. We encode what to do with the frag in
589 the subtype field. We encode (1) the number of existing bytes to
590 replace, (2) the number of new bytes to use, (3) the offset from
591 the start of the existing bytes to the first reloc we must generate
592 (that is, the offset is applied from the start of the existing
593 bytes after they are replaced by the new bytes, if any), (4) the
594 offset from the start of the existing bytes to the second reloc,
595 (5) whether a third reloc is needed (the third reloc is always four
596 bytes after the second reloc), and (6) whether to warn if this
597 variant is used (this is sometimes needed if .set nomacro or .set
598 noat is in effect). All these numbers are reasonably small.
600 Generating two instruction sequences must be handled carefully to
601 ensure that delay slots are handled correctly. Fortunately, there
602 are a limited number of cases. When the second instruction
603 sequence is generated, append_insn is directed to maintain the
604 existing delay slot information, so it continues to apply to any
605 code after the second instruction sequence. This means that the
606 second instruction sequence must not impose any requirements not
607 required by the first instruction sequence.
609 These variant frags are then handled in functions called by the
610 machine independent code. md_estimate_size_before_relax returns
611 the final size of the frag. md_convert_frag sets up the final form
612 of the frag. tc_gen_reloc adjust the first reloc and adds a second
614 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
618 | (((reloc1) + 64) << 9) \
619 | (((reloc2) + 64) << 2) \
620 | ((reloc3) ? (1 << 1) : 0) \
622 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
623 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
624 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
625 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
626 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
627 #define RELAX_WARN(i) ((i) & 1)
629 /* For mips16 code, we use an entirely different form of relaxation.
630 mips16 supports two versions of most instructions which take
631 immediate values: a small one which takes some small value, and a
632 larger one which takes a 16 bit value. Since branches also follow
633 this pattern, relaxing these values is required.
635 We can assemble both mips16 and normal MIPS code in a single
636 object. Therefore, we need to support this type of relaxation at
637 the same time that we support the relaxation described above. We
638 use the high bit of the subtype field to distinguish these cases.
640 The information we store for this type of relaxation is the
641 argument code found in the opcode file for this relocation, whether
642 the user explicitly requested a small or extended form, and whether
643 the relocation is in a jump or jal delay slot. That tells us the
644 size of the value, and how it should be stored. We also store
645 whether the fragment is considered to be extended or not. We also
646 store whether this is known to be a branch to a different section,
647 whether we have tried to relax this frag yet, and whether we have
648 ever extended a PC relative fragment because of a shift count. */
649 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
652 | ((small) ? 0x100 : 0) \
653 | ((ext) ? 0x200 : 0) \
654 | ((dslot) ? 0x400 : 0) \
655 | ((jal_dslot) ? 0x800 : 0))
656 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
657 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
658 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
659 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
660 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
661 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
662 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
663 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
664 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
665 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
666 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
667 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
669 /* Is the given value a sign-extended 32-bit value? */
670 #define IS_SEXT_32BIT_NUM(x) \
671 (((x) &~ (offsetT) 0x7fffffff) == 0 \
672 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
674 /* Is the given value a sign-extended 16-bit value? */
675 #define IS_SEXT_16BIT_NUM(x) \
676 (((x) &~ (offsetT) 0x7fff) == 0 \
677 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
680 /* Prototypes for static functions. */
683 #define internalError() \
684 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
686 #define internalError() as_fatal (_("MIPS internal Error"));
689 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
691 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
692 unsigned int reg
, enum mips_regclass
class));
693 static int reg_needs_delay
PARAMS ((unsigned int));
694 static void mips16_mark_labels
PARAMS ((void));
695 static void append_insn
PARAMS ((char *place
,
696 struct mips_cl_insn
* ip
,
698 bfd_reloc_code_real_type
*r
,
700 static void mips_no_prev_insn
PARAMS ((int));
701 static void mips_emit_delays
PARAMS ((boolean
));
703 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
704 const char *name
, const char *fmt
,
707 static void macro_build ();
709 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
710 const char *, const char *,
712 static void macro_build_jalr
PARAMS ((int, expressionS
*));
713 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
714 expressionS
* ep
, int regnum
));
715 static void macro_build_ldst_constoffset
PARAMS ((char *place
, int *counter
,
716 expressionS
* ep
, const char *op
,
717 int valreg
, int breg
));
718 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
719 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
721 static void load_register
PARAMS ((int *, int, expressionS
*, int));
722 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
723 static void move_register
PARAMS ((int *, int, int));
724 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
725 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
726 #ifdef LOSING_COMPILER
727 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
729 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
730 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
731 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
732 boolean
, boolean
, unsigned long *,
733 boolean
*, unsigned short *));
734 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
735 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
737 static void my_getExpression
PARAMS ((expressionS
*, char *));
739 static int support_64bit_objects
PARAMS((void));
741 static void mips_set_option_string
PARAMS ((const char **, const char *));
742 static symbolS
*get_symbol
PARAMS ((void));
743 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
744 static void s_align
PARAMS ((int));
745 static void s_change_sec
PARAMS ((int));
746 static void s_change_section
PARAMS ((int));
747 static void s_cons
PARAMS ((int));
748 static void s_float_cons
PARAMS ((int));
749 static void s_mips_globl
PARAMS ((int));
750 static void s_option
PARAMS ((int));
751 static void s_mipsset
PARAMS ((int));
752 static void s_abicalls
PARAMS ((int));
753 static void s_cpload
PARAMS ((int));
754 static void s_cpsetup
PARAMS ((int));
755 static void s_cplocal
PARAMS ((int));
756 static void s_cprestore
PARAMS ((int));
757 static void s_cpreturn
PARAMS ((int));
758 static void s_gpvalue
PARAMS ((int));
759 static void s_gpword
PARAMS ((int));
760 static void s_cpadd
PARAMS ((int));
761 static void s_insn
PARAMS ((int));
762 static void md_obj_begin
PARAMS ((void));
763 static void md_obj_end
PARAMS ((void));
764 static long get_number
PARAMS ((void));
765 static void s_mips_ent
PARAMS ((int));
766 static void s_mips_end
PARAMS ((int));
767 static void s_mips_frame
PARAMS ((int));
768 static void s_mips_mask
PARAMS ((int));
769 static void s_mips_stab
PARAMS ((int));
770 static void s_mips_weakext
PARAMS ((int));
771 static void s_mips_file
PARAMS ((int));
772 static void s_mips_loc
PARAMS ((int));
773 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
774 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
775 static void show
PARAMS ((FILE *, const char *, int *, int *));
777 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
780 /* Return values of my_getSmallExpression(). */
787 /* Direct relocation creation by %percent_op(). */
806 /* Table and functions used to map between CPU/ISA names, and
807 ISA levels, and CPU numbers. */
811 const char *name
; /* CPU or ISA name. */
812 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
813 int isa
; /* ISA level. */
814 int cpu
; /* CPU number (default CPU if ISA). */
817 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
818 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
819 static boolean mips_strict_matching_cpu_name_p
PARAMS ((const char *,
821 static boolean mips_matching_cpu_name_p
PARAMS ((const char *, const char *));
822 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
824 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
828 The following pseudo-ops from the Kane and Heinrich MIPS book
829 should be defined here, but are currently unsupported: .alias,
830 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
832 The following pseudo-ops from the Kane and Heinrich MIPS book are
833 specific to the type of debugging information being generated, and
834 should be defined by the object format: .aent, .begin, .bend,
835 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
838 The following pseudo-ops from the Kane and Heinrich MIPS book are
839 not MIPS CPU specific, but are also not specific to the object file
840 format. This file is probably the best place to define them, but
841 they are not currently supported: .asm0, .endr, .lab, .repeat,
844 static const pseudo_typeS mips_pseudo_table
[] =
846 /* MIPS specific pseudo-ops. */
847 {"option", s_option
, 0},
848 {"set", s_mipsset
, 0},
849 {"rdata", s_change_sec
, 'r'},
850 {"sdata", s_change_sec
, 's'},
851 {"livereg", s_ignore
, 0},
852 {"abicalls", s_abicalls
, 0},
853 {"cpload", s_cpload
, 0},
854 {"cpsetup", s_cpsetup
, 0},
855 {"cplocal", s_cplocal
, 0},
856 {"cprestore", s_cprestore
, 0},
857 {"cpreturn", s_cpreturn
, 0},
858 {"gpvalue", s_gpvalue
, 0},
859 {"gpword", s_gpword
, 0},
860 {"cpadd", s_cpadd
, 0},
863 /* Relatively generic pseudo-ops that happen to be used on MIPS
865 {"asciiz", stringer
, 1},
866 {"bss", s_change_sec
, 'b'},
869 {"dword", s_cons
, 3},
870 {"weakext", s_mips_weakext
, 0},
872 /* These pseudo-ops are defined in read.c, but must be overridden
873 here for one reason or another. */
874 {"align", s_align
, 0},
876 {"data", s_change_sec
, 'd'},
877 {"double", s_float_cons
, 'd'},
878 {"float", s_float_cons
, 'f'},
879 {"globl", s_mips_globl
, 0},
880 {"global", s_mips_globl
, 0},
881 {"hword", s_cons
, 1},
886 {"section", s_change_section
, 0},
887 {"short", s_cons
, 1},
888 {"single", s_float_cons
, 'f'},
889 {"stabn", s_mips_stab
, 'n'},
890 {"text", s_change_sec
, 't'},
893 { "extern", ecoff_directive_extern
, 0},
898 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
900 /* These pseudo-ops should be defined by the object file format.
901 However, a.out doesn't support them, so we have versions here. */
902 {"aent", s_mips_ent
, 1},
903 {"bgnb", s_ignore
, 0},
904 {"end", s_mips_end
, 0},
905 {"endb", s_ignore
, 0},
906 {"ent", s_mips_ent
, 0},
907 {"file", s_mips_file
, 0},
908 {"fmask", s_mips_mask
, 'F'},
909 {"frame", s_mips_frame
, 0},
910 {"loc", s_mips_loc
, 0},
911 {"mask", s_mips_mask
, 'R'},
912 {"verstamp", s_ignore
, 0},
916 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
921 pop_insert (mips_pseudo_table
);
922 if (! ECOFF_DEBUGGING
)
923 pop_insert (mips_nonecoff_pseudo_table
);
926 /* Symbols labelling the current insn. */
928 struct insn_label_list
930 struct insn_label_list
*next
;
934 static struct insn_label_list
*insn_labels
;
935 static struct insn_label_list
*free_insn_labels
;
937 static void mips_clear_insn_labels
PARAMS ((void));
940 mips_clear_insn_labels ()
942 register struct insn_label_list
**pl
;
944 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 static char *expr_end
;
952 /* Expressions which appear in instructions. These are set by
955 static expressionS imm_expr
;
956 static expressionS offset_expr
;
958 /* Relocs associated with imm_expr and offset_expr. */
960 static bfd_reloc_code_real_type imm_reloc
[3]
961 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
962 static bfd_reloc_code_real_type offset_reloc
[3]
963 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
965 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
967 static boolean imm_unmatched_hi
;
969 /* These are set by mips16_ip if an explicit extension is used. */
971 static boolean mips16_small
, mips16_ext
;
974 /* The pdr segment for per procedure frame/regmask info. Not used for
980 /* The default target format to use. */
983 mips_target_format ()
985 switch (OUTPUT_FLAVOR
)
987 case bfd_target_aout_flavour
:
988 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
989 case bfd_target_ecoff_flavour
:
990 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
991 case bfd_target_coff_flavour
:
993 case bfd_target_elf_flavour
:
995 /* This is traditional mips. */
996 return (target_big_endian
997 ? (HAVE_64BIT_OBJECTS
998 ? "elf64-tradbigmips"
1000 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1001 : (HAVE_64BIT_OBJECTS
1002 ? "elf64-tradlittlemips"
1004 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1006 return (target_big_endian
1007 ? (HAVE_64BIT_OBJECTS
1010 ? "elf32-nbigmips" : "elf32-bigmips"))
1011 : (HAVE_64BIT_OBJECTS
1012 ? "elf64-littlemips"
1014 ? "elf32-nlittlemips" : "elf32-littlemips")));
1022 /* This function is called once, at assembler startup time. It should
1023 set up all the tables, etc. that the MD part of the assembler will need. */
1028 register const char *retval
= NULL
;
1032 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1033 as_warn (_("Could not set architecture and machine"));
1035 op_hash
= hash_new ();
1037 for (i
= 0; i
< NUMOPCODES
;)
1039 const char *name
= mips_opcodes
[i
].name
;
1041 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1044 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1045 mips_opcodes
[i
].name
, retval
);
1046 /* Probably a memory allocation problem? Give up now. */
1047 as_fatal (_("Broken assembler. No assembly attempted."));
1051 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1053 if (!validate_mips_insn (&mips_opcodes
[i
]))
1058 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1061 mips16_op_hash
= hash_new ();
1064 while (i
< bfd_mips16_num_opcodes
)
1066 const char *name
= mips16_opcodes
[i
].name
;
1068 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1070 as_fatal (_("internal: can't hash `%s': %s"),
1071 mips16_opcodes
[i
].name
, retval
);
1074 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1075 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1076 != mips16_opcodes
[i
].match
))
1078 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1079 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1084 while (i
< bfd_mips16_num_opcodes
1085 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1089 as_fatal (_("Broken assembler. No assembly attempted."));
1091 /* We add all the general register names to the symbol table. This
1092 helps us detect invalid uses of them. */
1093 for (i
= 0; i
< 32; i
++)
1097 sprintf (buf
, "$%d", i
);
1098 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1099 &zero_address_frag
));
1101 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1102 &zero_address_frag
));
1103 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1104 &zero_address_frag
));
1105 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1106 &zero_address_frag
));
1107 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1108 &zero_address_frag
));
1109 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1110 &zero_address_frag
));
1111 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1112 &zero_address_frag
));
1113 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1114 &zero_address_frag
));
1115 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1116 &zero_address_frag
));
1117 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1118 &zero_address_frag
));
1120 mips_no_prev_insn (false);
1123 mips_cprmask
[0] = 0;
1124 mips_cprmask
[1] = 0;
1125 mips_cprmask
[2] = 0;
1126 mips_cprmask
[3] = 0;
1128 /* set the default alignment for the text section (2**2) */
1129 record_alignment (text_section
, 2);
1131 if (USE_GLOBAL_POINTER_OPT
)
1132 bfd_set_gp_size (stdoutput
, g_switch_value
);
1134 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1136 /* On a native system, sections must be aligned to 16 byte
1137 boundaries. When configured for an embedded ELF target, we
1139 if (strcmp (TARGET_OS
, "elf") != 0)
1141 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1142 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1143 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1146 /* Create a .reginfo section for register masks and a .mdebug
1147 section for debugging information. */
1155 subseg
= now_subseg
;
1157 /* The ABI says this section should be loaded so that the
1158 running program can access it. However, we don't load it
1159 if we are configured for an embedded target */
1160 flags
= SEC_READONLY
| SEC_DATA
;
1161 if (strcmp (TARGET_OS
, "elf") != 0)
1162 flags
|= SEC_ALLOC
| SEC_LOAD
;
1164 if (mips_abi
!= N64_ABI
)
1166 sec
= subseg_new (".reginfo", (subsegT
) 0);
1168 bfd_set_section_flags (stdoutput
, sec
, flags
);
1169 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1172 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1177 /* The 64-bit ABI uses a .MIPS.options section rather than
1178 .reginfo section. */
1179 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1180 bfd_set_section_flags (stdoutput
, sec
, flags
);
1181 bfd_set_section_alignment (stdoutput
, sec
, 3);
1184 /* Set up the option header. */
1186 Elf_Internal_Options opthdr
;
1189 opthdr
.kind
= ODK_REGINFO
;
1190 opthdr
.size
= (sizeof (Elf_External_Options
)
1191 + sizeof (Elf64_External_RegInfo
));
1194 f
= frag_more (sizeof (Elf_External_Options
));
1195 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1196 (Elf_External_Options
*) f
);
1198 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1203 if (ECOFF_DEBUGGING
)
1205 sec
= subseg_new (".mdebug", (subsegT
) 0);
1206 (void) bfd_set_section_flags (stdoutput
, sec
,
1207 SEC_HAS_CONTENTS
| SEC_READONLY
);
1208 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1211 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1213 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1214 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1215 SEC_READONLY
| SEC_RELOC
1217 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1221 subseg_set (seg
, subseg
);
1225 if (! ECOFF_DEBUGGING
)
1232 if (! ECOFF_DEBUGGING
)
1240 struct mips_cl_insn insn
;
1241 bfd_reloc_code_real_type unused_reloc
[3]
1242 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1244 imm_expr
.X_op
= O_absent
;
1245 imm_unmatched_hi
= false;
1246 offset_expr
.X_op
= O_absent
;
1247 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1248 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1249 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1250 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1251 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1252 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1254 if (mips_opts
.mips16
)
1255 mips16_ip (str
, &insn
);
1258 mips_ip (str
, &insn
);
1259 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1260 str
, insn
.insn_opcode
));
1265 as_bad ("%s `%s'", insn_error
, str
);
1269 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1271 if (mips_opts
.mips16
)
1272 mips16_macro (&insn
);
1278 if (imm_expr
.X_op
!= O_absent
)
1279 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1280 else if (offset_expr
.X_op
!= O_absent
)
1281 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1283 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1287 /* See whether instruction IP reads register REG. CLASS is the type
1291 insn_uses_reg (ip
, reg
, class)
1292 struct mips_cl_insn
*ip
;
1294 enum mips_regclass
class;
1296 if (class == MIPS16_REG
)
1298 assert (mips_opts
.mips16
);
1299 reg
= mips16_to_32_reg_map
[reg
];
1300 class = MIPS_GR_REG
;
1303 /* Don't report on general register ZERO, since it never changes. */
1304 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1307 if (class == MIPS_FP_REG
)
1309 assert (! mips_opts
.mips16
);
1310 /* If we are called with either $f0 or $f1, we must check $f0.
1311 This is not optimal, because it will introduce an unnecessary
1312 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1313 need to distinguish reading both $f0 and $f1 or just one of
1314 them. Note that we don't have to check the other way,
1315 because there is no instruction that sets both $f0 and $f1
1316 and requires a delay. */
1317 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1318 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1319 == (reg
&~ (unsigned) 1)))
1321 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1322 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1323 == (reg
&~ (unsigned) 1)))
1326 else if (! mips_opts
.mips16
)
1328 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1329 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1331 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1332 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1337 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1338 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1339 & MIPS16OP_MASK_RX
)]
1342 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1343 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1344 & MIPS16OP_MASK_RY
)]
1347 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1348 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1349 & MIPS16OP_MASK_MOVE32Z
)]
1352 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1354 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1356 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1358 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1359 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1360 & MIPS16OP_MASK_REGR32
) == reg
)
1367 /* This function returns true if modifying a register requires a
1371 reg_needs_delay (reg
)
1374 unsigned long prev_pinfo
;
1376 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1377 if (! mips_opts
.noreorder
1378 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1379 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1380 || (! gpr_interlocks
1381 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1383 /* A load from a coprocessor or from memory. All load
1384 delays delay the use of general register rt for one
1385 instruction on the r3000. The r6000 and r4000 use
1387 /* Itbl support may require additional care here. */
1388 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1389 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1396 /* Mark instruction labels in mips16 mode. This permits the linker to
1397 handle them specially, such as generating jalx instructions when
1398 needed. We also make them odd for the duration of the assembly, in
1399 order to generate the right sort of code. We will make them even
1400 in the adjust_symtab routine, while leaving them marked. This is
1401 convenient for the debugger and the disassembler. The linker knows
1402 to make them odd again. */
1405 mips16_mark_labels ()
1407 if (mips_opts
.mips16
)
1409 struct insn_label_list
*l
;
1412 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1415 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1416 S_SET_OTHER (l
->label
, STO_MIPS16
);
1418 val
= S_GET_VALUE (l
->label
);
1420 S_SET_VALUE (l
->label
, val
+ 1);
1425 /* Output an instruction. PLACE is where to put the instruction; if
1426 it is NULL, this uses frag_more to get room. IP is the instruction
1427 information. ADDRESS_EXPR is an operand of the instruction to be
1428 used with RELOC_TYPE. */
1431 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1433 struct mips_cl_insn
*ip
;
1434 expressionS
*address_expr
;
1435 bfd_reloc_code_real_type
*reloc_type
;
1436 boolean unmatched_hi
;
1438 register unsigned long prev_pinfo
, pinfo
;
1443 /* Mark instruction labels in mips16 mode. */
1444 mips16_mark_labels ();
1446 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1447 pinfo
= ip
->insn_mo
->pinfo
;
1449 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1453 /* If the previous insn required any delay slots, see if we need
1454 to insert a NOP or two. There are eight kinds of possible
1455 hazards, of which an instruction can have at most one type.
1456 (1) a load from memory delay
1457 (2) a load from a coprocessor delay
1458 (3) an unconditional branch delay
1459 (4) a conditional branch delay
1460 (5) a move to coprocessor register delay
1461 (6) a load coprocessor register from memory delay
1462 (7) a coprocessor condition code delay
1463 (8) a HI/LO special register delay
1465 There are a lot of optimizations we could do that we don't.
1466 In particular, we do not, in general, reorder instructions.
1467 If you use gcc with optimization, it will reorder
1468 instructions and generally do much more optimization then we
1469 do here; repeating all that work in the assembler would only
1470 benefit hand written assembly code, and does not seem worth
1473 /* This is how a NOP is emitted. */
1474 #define emit_nop() \
1476 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1477 : md_number_to_chars (frag_more (4), 0, 4))
1479 /* The previous insn might require a delay slot, depending upon
1480 the contents of the current insn. */
1481 if (! mips_opts
.mips16
1482 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1483 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1484 && ! cop_interlocks
)
1485 || (! gpr_interlocks
1486 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1488 /* A load from a coprocessor or from memory. All load
1489 delays delay the use of general register rt for one
1490 instruction on the r3000. The r6000 and r4000 use
1492 /* Itbl support may require additional care here. */
1493 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1494 if (mips_optimize
== 0
1495 || insn_uses_reg (ip
,
1496 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1501 else if (! mips_opts
.mips16
1502 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1503 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1504 && ! cop_interlocks
)
1505 || (mips_opts
.isa
== ISA_MIPS1
1506 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1508 /* A generic coprocessor delay. The previous instruction
1509 modified a coprocessor general or control register. If
1510 it modified a control register, we need to avoid any
1511 coprocessor instruction (this is probably not always
1512 required, but it sometimes is). If it modified a general
1513 register, we avoid using that register.
1515 On the r6000 and r4000 loading a coprocessor register
1516 from memory is interlocked, and does not require a delay.
1518 This case is not handled very well. There is no special
1519 knowledge of CP0 handling, and the coprocessors other
1520 than the floating point unit are not distinguished at
1522 /* Itbl support may require additional care here. FIXME!
1523 Need to modify this to include knowledge about
1524 user specified delays! */
1525 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1527 if (mips_optimize
== 0
1528 || insn_uses_reg (ip
,
1529 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1534 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1536 if (mips_optimize
== 0
1537 || insn_uses_reg (ip
,
1538 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1545 /* We don't know exactly what the previous instruction
1546 does. If the current instruction uses a coprocessor
1547 register, we must insert a NOP. If previous
1548 instruction may set the condition codes, and the
1549 current instruction uses them, we must insert two
1551 /* Itbl support may require additional care here. */
1552 if (mips_optimize
== 0
1553 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1554 && (pinfo
& INSN_READ_COND_CODE
)))
1556 else if (pinfo
& INSN_COP
)
1560 else if (! mips_opts
.mips16
1561 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1562 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1563 && ! cop_interlocks
)
1565 /* The previous instruction sets the coprocessor condition
1566 codes, but does not require a general coprocessor delay
1567 (this means it is a floating point comparison
1568 instruction). If this instruction uses the condition
1569 codes, we need to insert a single NOP. */
1570 /* Itbl support may require additional care here. */
1571 if (mips_optimize
== 0
1572 || (pinfo
& INSN_READ_COND_CODE
))
1576 /* If we're fixing up mfhi/mflo for the r7000 and the
1577 previous insn was an mfhi/mflo and the current insn
1578 reads the register that the mfhi/mflo wrote to, then
1581 else if (mips_7000_hilo_fix
1582 && MF_HILO_INSN (prev_pinfo
)
1583 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1590 /* If we're fixing up mfhi/mflo for the r7000 and the
1591 2nd previous insn was an mfhi/mflo and the current insn
1592 reads the register that the mfhi/mflo wrote to, then
1595 else if (mips_7000_hilo_fix
1596 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1597 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1605 else if (prev_pinfo
& INSN_READ_LO
)
1607 /* The previous instruction reads the LO register; if the
1608 current instruction writes to the LO register, we must
1609 insert two NOPS. Some newer processors have interlocks.
1610 Also the tx39's multiply instructions can be exectuted
1611 immediatly after a read from HI/LO (without the delay),
1612 though the tx39's divide insns still do require the
1614 if (! (hilo_interlocks
1615 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1616 && (mips_optimize
== 0
1617 || (pinfo
& INSN_WRITE_LO
)))
1619 /* Most mips16 branch insns don't have a delay slot.
1620 If a read from LO is immediately followed by a branch
1621 to a write to LO we have a read followed by a write
1622 less than 2 insns away. We assume the target of
1623 a branch might be a write to LO, and insert a nop
1624 between a read and an immediately following branch. */
1625 else if (mips_opts
.mips16
1626 && (mips_optimize
== 0
1627 || (pinfo
& MIPS16_INSN_BRANCH
)))
1630 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1632 /* The previous instruction reads the HI register; if the
1633 current instruction writes to the HI register, we must
1634 insert a NOP. Some newer processors have interlocks.
1635 Also the note tx39's multiply above. */
1636 if (! (hilo_interlocks
1637 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1638 && (mips_optimize
== 0
1639 || (pinfo
& INSN_WRITE_HI
)))
1641 /* Most mips16 branch insns don't have a delay slot.
1642 If a read from HI is immediately followed by a branch
1643 to a write to HI we have a read followed by a write
1644 less than 2 insns away. We assume the target of
1645 a branch might be a write to HI, and insert a nop
1646 between a read and an immediately following branch. */
1647 else if (mips_opts
.mips16
1648 && (mips_optimize
== 0
1649 || (pinfo
& MIPS16_INSN_BRANCH
)))
1653 /* If the previous instruction was in a noreorder section, then
1654 we don't want to insert the nop after all. */
1655 /* Itbl support may require additional care here. */
1656 if (prev_insn_unreordered
)
1659 /* There are two cases which require two intervening
1660 instructions: 1) setting the condition codes using a move to
1661 coprocessor instruction which requires a general coprocessor
1662 delay and then reading the condition codes 2) reading the HI
1663 or LO register and then writing to it (except on processors
1664 which have interlocks). If we are not already emitting a NOP
1665 instruction, we must check for these cases compared to the
1666 instruction previous to the previous instruction. */
1667 if ((! mips_opts
.mips16
1668 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1669 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1670 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1671 && (pinfo
& INSN_READ_COND_CODE
)
1672 && ! cop_interlocks
)
1673 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1674 && (pinfo
& INSN_WRITE_LO
)
1675 && ! (hilo_interlocks
1676 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1677 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1678 && (pinfo
& INSN_WRITE_HI
)
1679 && ! (hilo_interlocks
1680 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1685 if (prev_prev_insn_unreordered
)
1688 if (prev_prev_nop
&& nops
== 0)
1691 /* If we are being given a nop instruction, don't bother with
1692 one of the nops we would otherwise output. This will only
1693 happen when a nop instruction is used with mips_optimize set
1696 && ! mips_opts
.noreorder
1697 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1700 /* Now emit the right number of NOP instructions. */
1701 if (nops
> 0 && ! mips_opts
.noreorder
)
1704 unsigned long old_frag_offset
;
1706 struct insn_label_list
*l
;
1708 old_frag
= frag_now
;
1709 old_frag_offset
= frag_now_fix ();
1711 for (i
= 0; i
< nops
; i
++)
1716 listing_prev_line ();
1717 /* We may be at the start of a variant frag. In case we
1718 are, make sure there is enough space for the frag
1719 after the frags created by listing_prev_line. The
1720 argument to frag_grow here must be at least as large
1721 as the argument to all other calls to frag_grow in
1722 this file. We don't have to worry about being in the
1723 middle of a variant frag, because the variants insert
1724 all needed nop instructions themselves. */
1728 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1732 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1733 symbol_set_frag (l
->label
, frag_now
);
1734 val
= (valueT
) frag_now_fix ();
1735 /* mips16 text labels are stored as odd. */
1736 if (mips_opts
.mips16
)
1738 S_SET_VALUE (l
->label
, val
);
1741 #ifndef NO_ECOFF_DEBUGGING
1742 if (ECOFF_DEBUGGING
)
1743 ecoff_fix_loc (old_frag
, old_frag_offset
);
1746 else if (prev_nop_frag
!= NULL
)
1748 /* We have a frag holding nops we may be able to remove. If
1749 we don't need any nops, we can decrease the size of
1750 prev_nop_frag by the size of one instruction. If we do
1751 need some nops, we count them in prev_nops_required. */
1752 if (prev_nop_frag_since
== 0)
1756 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1757 --prev_nop_frag_holds
;
1760 prev_nop_frag_required
+= nops
;
1764 if (prev_prev_nop
== 0)
1766 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1767 --prev_nop_frag_holds
;
1770 ++prev_nop_frag_required
;
1773 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1774 prev_nop_frag
= NULL
;
1776 ++prev_nop_frag_since
;
1778 /* Sanity check: by the time we reach the second instruction
1779 after prev_nop_frag, we should have used up all the nops
1780 one way or another. */
1781 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1785 if (*reloc_type
> BFD_RELOC_UNUSED
)
1787 /* We need to set up a variant frag. */
1788 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1789 f
= frag_var (rs_machine_dependent
, 4, 0,
1790 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1791 mips16_small
, mips16_ext
,
1793 & INSN_UNCOND_BRANCH_DELAY
),
1794 (*prev_insn_reloc_type
1795 == BFD_RELOC_MIPS16_JMP
)),
1796 make_expr_symbol (address_expr
), 0, NULL
);
1798 else if (place
!= NULL
)
1800 else if (mips_opts
.mips16
1802 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1804 /* Make sure there is enough room to swap this instruction with
1805 a following jump instruction. */
1811 if (mips_opts
.mips16
1812 && mips_opts
.noreorder
1813 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1814 as_warn (_("extended instruction in delay slot"));
1819 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1820 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1822 if (address_expr
->X_op
== O_constant
)
1826 switch (*reloc_type
)
1829 ip
->insn_opcode
|= address_expr
->X_add_number
;
1832 case BFD_RELOC_MIPS_HIGHEST
:
1833 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1835 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1838 case BFD_RELOC_MIPS_HIGHER
:
1839 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1840 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1843 case BFD_RELOC_HI16_S
:
1844 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1848 case BFD_RELOC_HI16
:
1849 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1852 case BFD_RELOC_LO16
:
1853 case BFD_RELOC_MIPS_GOT_DISP
:
1854 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1857 case BFD_RELOC_MIPS_JMP
:
1858 if ((address_expr
->X_add_number
& 3) != 0)
1859 as_bad (_("jump to misaligned address (0x%lx)"),
1860 (unsigned long) address_expr
->X_add_number
);
1861 if (address_expr
->X_add_number
& ~0xfffffff
1862 || address_expr
->X_add_number
> 0x7fffffc)
1863 as_bad (_("jump address range overflow (0x%lx)"),
1864 (unsigned long) address_expr
->X_add_number
);
1865 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1868 case BFD_RELOC_MIPS16_JMP
:
1869 if ((address_expr
->X_add_number
& 3) != 0)
1870 as_bad (_("jump to misaligned address (0x%lx)"),
1871 (unsigned long) address_expr
->X_add_number
);
1872 if (address_expr
->X_add_number
& ~0xfffffff
1873 || address_expr
->X_add_number
> 0x7fffffc)
1874 as_bad (_("jump address range overflow (0x%lx)"),
1875 (unsigned long) address_expr
->X_add_number
);
1877 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1878 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1879 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1882 case BFD_RELOC_16_PCREL
:
1883 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1886 case BFD_RELOC_16_PCREL_S2
:
1896 /* Don't generate a reloc if we are writing into a variant frag. */
1899 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1901 (*reloc_type
== BFD_RELOC_16_PCREL
1902 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
1905 /* These relocations can have an addend that won't fit in
1906 4 octets for 64bit assembly. */
1907 if (HAVE_64BIT_GPRS
&&
1908 (*reloc_type
== BFD_RELOC_16
1909 || *reloc_type
== BFD_RELOC_32
1910 || *reloc_type
== BFD_RELOC_MIPS_JMP
1911 || *reloc_type
== BFD_RELOC_HI16_S
1912 || *reloc_type
== BFD_RELOC_LO16
1913 || *reloc_type
== BFD_RELOC_GPREL16
1914 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1915 || *reloc_type
== BFD_RELOC_GPREL32
1916 || *reloc_type
== BFD_RELOC_64
1917 || *reloc_type
== BFD_RELOC_CTOR
1918 || *reloc_type
== BFD_RELOC_MIPS_SUB
1919 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1920 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1921 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1922 || *reloc_type
== BFD_RELOC_MIPS_REL16
1923 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1924 fixp
[0]->fx_no_overflow
= 1;
1928 struct mips_hi_fixup
*hi_fixup
;
1930 assert (*reloc_type
== BFD_RELOC_HI16_S
);
1931 hi_fixup
= ((struct mips_hi_fixup
*)
1932 xmalloc (sizeof (struct mips_hi_fixup
)));
1933 hi_fixup
->fixp
= fixp
[0];
1934 hi_fixup
->seg
= now_seg
;
1935 hi_fixup
->next
= mips_hi_fixup_list
;
1936 mips_hi_fixup_list
= hi_fixup
;
1939 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
1941 /* FIXME: This symbol can be one of
1942 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1943 address_expr
->X_op
= O_absent
;
1944 address_expr
->X_add_symbol
= 0;
1945 address_expr
->X_add_number
= 0;
1947 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
1948 4, address_expr
, false,
1951 /* These relocations can have an addend that won't fit in
1952 4 octets for 64bit assembly. */
1953 if (HAVE_64BIT_GPRS
&&
1954 (*reloc_type
== BFD_RELOC_16
1955 || *reloc_type
== BFD_RELOC_32
1956 || *reloc_type
== BFD_RELOC_MIPS_JMP
1957 || *reloc_type
== BFD_RELOC_HI16_S
1958 || *reloc_type
== BFD_RELOC_LO16
1959 || *reloc_type
== BFD_RELOC_GPREL16
1960 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1961 || *reloc_type
== BFD_RELOC_GPREL32
1962 || *reloc_type
== BFD_RELOC_64
1963 || *reloc_type
== BFD_RELOC_CTOR
1964 || *reloc_type
== BFD_RELOC_MIPS_SUB
1965 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1966 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1967 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1968 || *reloc_type
== BFD_RELOC_MIPS_REL16
1969 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1970 fixp
[1]->fx_no_overflow
= 1;
1972 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
1974 address_expr
->X_op
= O_absent
;
1975 address_expr
->X_add_symbol
= 0;
1976 address_expr
->X_add_number
= 0;
1978 fixp
[2] = fix_new_exp (frag_now
,
1979 f
- frag_now
->fr_literal
, 4,
1980 address_expr
, false,
1983 /* These relocations can have an addend that won't fit in
1984 4 octets for 64bit assembly. */
1985 if (HAVE_64BIT_GPRS
&&
1986 (*reloc_type
== BFD_RELOC_16
1987 || *reloc_type
== BFD_RELOC_32
1988 || *reloc_type
== BFD_RELOC_MIPS_JMP
1989 || *reloc_type
== BFD_RELOC_HI16_S
1990 || *reloc_type
== BFD_RELOC_LO16
1991 || *reloc_type
== BFD_RELOC_GPREL16
1992 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1993 || *reloc_type
== BFD_RELOC_GPREL32
1994 || *reloc_type
== BFD_RELOC_64
1995 || *reloc_type
== BFD_RELOC_CTOR
1996 || *reloc_type
== BFD_RELOC_MIPS_SUB
1997 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1998 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1999 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2000 || *reloc_type
== BFD_RELOC_MIPS_REL16
2001 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2002 fixp
[2]->fx_no_overflow
= 1;
2009 if (! mips_opts
.mips16
)
2011 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2013 dwarf2_emit_insn (4);
2016 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2018 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2019 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2021 dwarf2_emit_insn (4);
2028 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2031 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2033 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2037 /* Update the register mask information. */
2038 if (! mips_opts
.mips16
)
2040 if (pinfo
& INSN_WRITE_GPR_D
)
2041 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2042 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2043 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2044 if (pinfo
& INSN_READ_GPR_S
)
2045 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2046 if (pinfo
& INSN_WRITE_GPR_31
)
2047 mips_gprmask
|= 1 << RA
;
2048 if (pinfo
& INSN_WRITE_FPR_D
)
2049 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2050 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2051 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2052 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2053 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2054 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2055 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2056 if (pinfo
& INSN_COP
)
2058 /* We don't keep enough information to sort these cases out.
2059 The itbl support does keep this information however, although
2060 we currently don't support itbl fprmats as part of the cop
2061 instruction. May want to add this support in the future. */
2063 /* Never set the bit for $0, which is always zero. */
2064 mips_gprmask
&= ~1 << 0;
2068 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2069 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2070 & MIPS16OP_MASK_RX
);
2071 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2072 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2073 & MIPS16OP_MASK_RY
);
2074 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2075 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2076 & MIPS16OP_MASK_RZ
);
2077 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2078 mips_gprmask
|= 1 << TREG
;
2079 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2080 mips_gprmask
|= 1 << SP
;
2081 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2082 mips_gprmask
|= 1 << RA
;
2083 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2084 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2085 if (pinfo
& MIPS16_INSN_READ_Z
)
2086 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2087 & MIPS16OP_MASK_MOVE32Z
);
2088 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2089 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2090 & MIPS16OP_MASK_REGR32
);
2093 if (place
== NULL
&& ! mips_opts
.noreorder
)
2095 /* Filling the branch delay slot is more complex. We try to
2096 switch the branch with the previous instruction, which we can
2097 do if the previous instruction does not set up a condition
2098 that the branch tests and if the branch is not itself the
2099 target of any branch. */
2100 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2101 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2103 if (mips_optimize
< 2
2104 /* If we have seen .set volatile or .set nomove, don't
2106 || mips_opts
.nomove
!= 0
2107 /* If we had to emit any NOP instructions, then we
2108 already know we can not swap. */
2110 /* If we don't even know the previous insn, we can not
2112 || ! prev_insn_valid
2113 /* If the previous insn is already in a branch delay
2114 slot, then we can not swap. */
2115 || prev_insn_is_delay_slot
2116 /* If the previous previous insn was in a .set
2117 noreorder, we can't swap. Actually, the MIPS
2118 assembler will swap in this situation. However, gcc
2119 configured -with-gnu-as will generate code like
2125 in which we can not swap the bne and INSN. If gcc is
2126 not configured -with-gnu-as, it does not output the
2127 .set pseudo-ops. We don't have to check
2128 prev_insn_unreordered, because prev_insn_valid will
2129 be 0 in that case. We don't want to use
2130 prev_prev_insn_valid, because we do want to be able
2131 to swap at the start of a function. */
2132 || prev_prev_insn_unreordered
2133 /* If the branch is itself the target of a branch, we
2134 can not swap. We cheat on this; all we check for is
2135 whether there is a label on this instruction. If
2136 there are any branches to anything other than a
2137 label, users must use .set noreorder. */
2138 || insn_labels
!= NULL
2139 /* If the previous instruction is in a variant frag, we
2140 can not do the swap. This does not apply to the
2141 mips16, which uses variant frags for different
2143 || (! mips_opts
.mips16
2144 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2145 /* If the branch reads the condition codes, we don't
2146 even try to swap, because in the sequence
2151 we can not swap, and I don't feel like handling that
2153 || (! mips_opts
.mips16
2154 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2155 && (pinfo
& INSN_READ_COND_CODE
))
2156 /* We can not swap with an instruction that requires a
2157 delay slot, becase the target of the branch might
2158 interfere with that instruction. */
2159 || (! mips_opts
.mips16
2160 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2162 /* Itbl support may require additional care here. */
2163 & (INSN_LOAD_COPROC_DELAY
2164 | INSN_COPROC_MOVE_DELAY
2165 | INSN_WRITE_COND_CODE
)))
2166 || (! (hilo_interlocks
2167 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2171 || (! mips_opts
.mips16
2173 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2174 || (! mips_opts
.mips16
2175 && mips_opts
.isa
== ISA_MIPS1
2176 /* Itbl support may require additional care here. */
2177 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2178 /* We can not swap with a branch instruction. */
2180 & (INSN_UNCOND_BRANCH_DELAY
2181 | INSN_COND_BRANCH_DELAY
2182 | INSN_COND_BRANCH_LIKELY
))
2183 /* We do not swap with a trap instruction, since it
2184 complicates trap handlers to have the trap
2185 instruction be in a delay slot. */
2186 || (prev_pinfo
& INSN_TRAP
)
2187 /* If the branch reads a register that the previous
2188 instruction sets, we can not swap. */
2189 || (! mips_opts
.mips16
2190 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2191 && insn_uses_reg (ip
,
2192 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2195 || (! mips_opts
.mips16
2196 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2197 && insn_uses_reg (ip
,
2198 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2201 || (mips_opts
.mips16
2202 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2203 && insn_uses_reg (ip
,
2204 ((prev_insn
.insn_opcode
2206 & MIPS16OP_MASK_RX
),
2208 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2209 && insn_uses_reg (ip
,
2210 ((prev_insn
.insn_opcode
2212 & MIPS16OP_MASK_RY
),
2214 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2215 && insn_uses_reg (ip
,
2216 ((prev_insn
.insn_opcode
2218 & MIPS16OP_MASK_RZ
),
2220 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2221 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2222 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2223 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2224 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2225 && insn_uses_reg (ip
,
2226 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2229 /* If the branch writes a register that the previous
2230 instruction sets, we can not swap (we know that
2231 branches write only to RD or to $31). */
2232 || (! mips_opts
.mips16
2233 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2234 && (((pinfo
& INSN_WRITE_GPR_D
)
2235 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2236 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2237 || ((pinfo
& INSN_WRITE_GPR_31
)
2238 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2241 || (! mips_opts
.mips16
2242 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2243 && (((pinfo
& INSN_WRITE_GPR_D
)
2244 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2245 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2246 || ((pinfo
& INSN_WRITE_GPR_31
)
2247 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2250 || (mips_opts
.mips16
2251 && (pinfo
& MIPS16_INSN_WRITE_31
)
2252 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2253 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2254 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2256 /* If the branch writes a register that the previous
2257 instruction reads, we can not swap (we know that
2258 branches only write to RD or to $31). */
2259 || (! mips_opts
.mips16
2260 && (pinfo
& INSN_WRITE_GPR_D
)
2261 && insn_uses_reg (&prev_insn
,
2262 ((ip
->insn_opcode
>> OP_SH_RD
)
2265 || (! mips_opts
.mips16
2266 && (pinfo
& INSN_WRITE_GPR_31
)
2267 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2268 || (mips_opts
.mips16
2269 && (pinfo
& MIPS16_INSN_WRITE_31
)
2270 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2271 /* If we are generating embedded PIC code, the branch
2272 might be expanded into a sequence which uses $at, so
2273 we can't swap with an instruction which reads it. */
2274 || (mips_pic
== EMBEDDED_PIC
2275 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2276 /* If the previous previous instruction has a load
2277 delay, and sets a register that the branch reads, we
2279 || (! mips_opts
.mips16
2280 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2281 /* Itbl support may require additional care here. */
2282 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2283 || (! gpr_interlocks
2284 && (prev_prev_insn
.insn_mo
->pinfo
2285 & INSN_LOAD_MEMORY_DELAY
)))
2286 && insn_uses_reg (ip
,
2287 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2290 /* If one instruction sets a condition code and the
2291 other one uses a condition code, we can not swap. */
2292 || ((pinfo
& INSN_READ_COND_CODE
)
2293 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2294 || ((pinfo
& INSN_WRITE_COND_CODE
)
2295 && (prev_pinfo
& INSN_READ_COND_CODE
))
2296 /* If the previous instruction uses the PC, we can not
2298 || (mips_opts
.mips16
2299 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2300 /* If the previous instruction was extended, we can not
2302 || (mips_opts
.mips16
&& prev_insn_extended
)
2303 /* If the previous instruction had a fixup in mips16
2304 mode, we can not swap. This normally means that the
2305 previous instruction was a 4 byte branch anyhow. */
2306 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2307 /* If the previous instruction is a sync, sync.l, or
2308 sync.p, we can not swap. */
2309 || (prev_pinfo
& INSN_SYNC
))
2311 /* We could do even better for unconditional branches to
2312 portions of this object file; we could pick up the
2313 instruction at the destination, put it in the delay
2314 slot, and bump the destination address. */
2316 /* Update the previous insn information. */
2317 prev_prev_insn
= *ip
;
2318 prev_insn
.insn_mo
= &dummy_opcode
;
2322 /* It looks like we can actually do the swap. */
2323 if (! mips_opts
.mips16
)
2328 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2329 memcpy (temp
, prev_f
, 4);
2330 memcpy (prev_f
, f
, 4);
2331 memcpy (f
, temp
, 4);
2332 if (prev_insn_fixp
[0])
2334 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2335 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2337 if (prev_insn_fixp
[1])
2339 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2340 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2342 if (prev_insn_fixp
[2])
2344 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2345 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2349 fixp
[0]->fx_frag
= prev_insn_frag
;
2350 fixp
[0]->fx_where
= prev_insn_where
;
2354 fixp
[1]->fx_frag
= prev_insn_frag
;
2355 fixp
[1]->fx_where
= prev_insn_where
;
2359 fixp
[2]->fx_frag
= prev_insn_frag
;
2360 fixp
[2]->fx_where
= prev_insn_where
;
2368 assert (prev_insn_fixp
[0] == NULL
);
2369 assert (prev_insn_fixp
[1] == NULL
);
2370 assert (prev_insn_fixp
[2] == NULL
);
2371 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2372 memcpy (temp
, prev_f
, 2);
2373 memcpy (prev_f
, f
, 2);
2374 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2376 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2377 memcpy (f
, temp
, 2);
2381 memcpy (f
, f
+ 2, 2);
2382 memcpy (f
+ 2, temp
, 2);
2386 fixp
[0]->fx_frag
= prev_insn_frag
;
2387 fixp
[0]->fx_where
= prev_insn_where
;
2391 fixp
[1]->fx_frag
= prev_insn_frag
;
2392 fixp
[1]->fx_where
= prev_insn_where
;
2396 fixp
[2]->fx_frag
= prev_insn_frag
;
2397 fixp
[2]->fx_where
= prev_insn_where
;
2401 /* Update the previous insn information; leave prev_insn
2403 prev_prev_insn
= *ip
;
2405 prev_insn_is_delay_slot
= 1;
2407 /* If that was an unconditional branch, forget the previous
2408 insn information. */
2409 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2411 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2412 prev_insn
.insn_mo
= &dummy_opcode
;
2415 prev_insn_fixp
[0] = NULL
;
2416 prev_insn_fixp
[1] = NULL
;
2417 prev_insn_fixp
[2] = NULL
;
2418 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2419 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2420 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2421 prev_insn_extended
= 0;
2423 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2425 /* We don't yet optimize a branch likely. What we should do
2426 is look at the target, copy the instruction found there
2427 into the delay slot, and increment the branch to jump to
2428 the next instruction. */
2430 /* Update the previous insn information. */
2431 prev_prev_insn
= *ip
;
2432 prev_insn
.insn_mo
= &dummy_opcode
;
2433 prev_insn_fixp
[0] = NULL
;
2434 prev_insn_fixp
[1] = NULL
;
2435 prev_insn_fixp
[2] = NULL
;
2436 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2437 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2438 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2439 prev_insn_extended
= 0;
2443 /* Update the previous insn information. */
2445 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2447 prev_prev_insn
= prev_insn
;
2450 /* Any time we see a branch, we always fill the delay slot
2451 immediately; since this insn is not a branch, we know it
2452 is not in a delay slot. */
2453 prev_insn_is_delay_slot
= 0;
2455 prev_insn_fixp
[0] = fixp
[0];
2456 prev_insn_fixp
[1] = fixp
[1];
2457 prev_insn_fixp
[2] = fixp
[2];
2458 prev_insn_reloc_type
[0] = reloc_type
[0];
2459 prev_insn_reloc_type
[1] = reloc_type
[1];
2460 prev_insn_reloc_type
[2] = reloc_type
[2];
2461 if (mips_opts
.mips16
)
2462 prev_insn_extended
= (ip
->use_extend
2463 || *reloc_type
> BFD_RELOC_UNUSED
);
2466 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2467 prev_insn_unreordered
= 0;
2468 prev_insn_frag
= frag_now
;
2469 prev_insn_where
= f
- frag_now
->fr_literal
;
2470 prev_insn_valid
= 1;
2472 else if (place
== NULL
)
2474 /* We need to record a bit of information even when we are not
2475 reordering, in order to determine the base address for mips16
2476 PC relative relocs. */
2477 prev_prev_insn
= prev_insn
;
2479 prev_insn_reloc_type
[0] = reloc_type
[0];
2480 prev_insn_reloc_type
[1] = reloc_type
[1];
2481 prev_insn_reloc_type
[2] = reloc_type
[2];
2482 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2483 prev_insn_unreordered
= 1;
2486 /* We just output an insn, so the next one doesn't have a label. */
2487 mips_clear_insn_labels ();
2489 /* We must ensure that a fixup associated with an unmatched %hi
2490 reloc does not become a variant frag. Otherwise, the
2491 rearrangement of %hi relocs in frob_file may confuse
2495 frag_wane (frag_now
);
2500 /* This function forgets that there was any previous instruction or
2501 label. If PRESERVE is non-zero, it remembers enough information to
2502 know whether nops are needed before a noreorder section. */
2505 mips_no_prev_insn (preserve
)
2510 prev_insn
.insn_mo
= &dummy_opcode
;
2511 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2512 prev_nop_frag
= NULL
;
2513 prev_nop_frag_holds
= 0;
2514 prev_nop_frag_required
= 0;
2515 prev_nop_frag_since
= 0;
2517 prev_insn_valid
= 0;
2518 prev_insn_is_delay_slot
= 0;
2519 prev_insn_unreordered
= 0;
2520 prev_insn_extended
= 0;
2521 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2522 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2523 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2524 prev_prev_insn_unreordered
= 0;
2525 mips_clear_insn_labels ();
2528 /* This function must be called whenever we turn on noreorder or emit
2529 something other than instructions. It inserts any NOPS which might
2530 be needed by the previous instruction, and clears the information
2531 kept for the previous instructions. The INSNS parameter is true if
2532 instructions are to follow. */
2535 mips_emit_delays (insns
)
2538 if (! mips_opts
.noreorder
)
2543 if ((! mips_opts
.mips16
2544 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2545 && (! cop_interlocks
2546 && (prev_insn
.insn_mo
->pinfo
2547 & (INSN_LOAD_COPROC_DELAY
2548 | INSN_COPROC_MOVE_DELAY
2549 | INSN_WRITE_COND_CODE
))))
2550 || (! hilo_interlocks
2551 && (prev_insn
.insn_mo
->pinfo
2554 || (! mips_opts
.mips16
2556 && (prev_insn
.insn_mo
->pinfo
2557 & INSN_LOAD_MEMORY_DELAY
))
2558 || (! mips_opts
.mips16
2559 && mips_opts
.isa
== ISA_MIPS1
2560 && (prev_insn
.insn_mo
->pinfo
2561 & INSN_COPROC_MEMORY_DELAY
)))
2563 /* Itbl support may require additional care here. */
2565 if ((! mips_opts
.mips16
2566 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2567 && (! cop_interlocks
2568 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2569 || (! hilo_interlocks
2570 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2571 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2574 if (prev_insn_unreordered
)
2577 else if ((! mips_opts
.mips16
2578 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2579 && (! cop_interlocks
2580 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2581 || (! hilo_interlocks
2582 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2583 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2585 /* Itbl support may require additional care here. */
2586 if (! prev_prev_insn_unreordered
)
2592 struct insn_label_list
*l
;
2596 /* Record the frag which holds the nop instructions, so
2597 that we can remove them if we don't need them. */
2598 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2599 prev_nop_frag
= frag_now
;
2600 prev_nop_frag_holds
= nops
;
2601 prev_nop_frag_required
= 0;
2602 prev_nop_frag_since
= 0;
2605 for (; nops
> 0; --nops
)
2610 /* Move on to a new frag, so that it is safe to simply
2611 decrease the size of prev_nop_frag. */
2612 frag_wane (frag_now
);
2616 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2620 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2621 symbol_set_frag (l
->label
, frag_now
);
2622 val
= (valueT
) frag_now_fix ();
2623 /* mips16 text labels are stored as odd. */
2624 if (mips_opts
.mips16
)
2626 S_SET_VALUE (l
->label
, val
);
2631 /* Mark instruction labels in mips16 mode. */
2633 mips16_mark_labels ();
2635 mips_no_prev_insn (insns
);
2638 /* Build an instruction created by a macro expansion. This is passed
2639 a pointer to the count of instructions created so far, an
2640 expression, the name of the instruction to build, an operand format
2641 string, and corresponding arguments. */
2645 macro_build (char *place
,
2653 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2662 struct mips_cl_insn insn
;
2663 bfd_reloc_code_real_type r
[3];
2667 va_start (args
, fmt
);
2673 * If the macro is about to expand into a second instruction,
2674 * print a warning if needed. We need to pass ip as a parameter
2675 * to generate a better warning message here...
2677 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2678 as_warn (_("Macro instruction expanded into multiple instructions"));
2681 * If the macro is about to expand into a second instruction,
2682 * and it is in a delay slot, print a warning.
2686 && mips_opts
.noreorder
2687 && (prev_prev_insn
.insn_mo
->pinfo
2688 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2689 | INSN_COND_BRANCH_LIKELY
)) != 0)
2690 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2693 ++*counter
; /* bump instruction counter */
2695 if (mips_opts
.mips16
)
2697 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2702 r
[0] = BFD_RELOC_UNUSED
;
2703 r
[1] = BFD_RELOC_UNUSED
;
2704 r
[2] = BFD_RELOC_UNUSED
;
2705 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2706 assert (insn
.insn_mo
);
2707 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2709 /* Search until we get a match for NAME. */
2712 /* It is assumed here that macros will never generate
2713 MDMX or MIPS-3D instructions. */
2714 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2715 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2716 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2718 | (mips_opts
.mips16
? INSN_MIPS16
: 0)),
2720 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2724 assert (insn
.insn_mo
->name
);
2725 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2728 insn
.insn_opcode
= insn
.insn_mo
->match
;
2744 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2748 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2753 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2758 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2763 int tmp
= va_arg (args
, int);
2765 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2766 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2772 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2779 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2783 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2787 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2791 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2795 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2802 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2808 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2809 assert (*r
== BFD_RELOC_GPREL16
2810 || *r
== BFD_RELOC_MIPS_LITERAL
2811 || *r
== BFD_RELOC_MIPS_HIGHER
2812 || *r
== BFD_RELOC_HI16_S
2813 || *r
== BFD_RELOC_LO16
2814 || *r
== BFD_RELOC_MIPS_GOT16
2815 || *r
== BFD_RELOC_MIPS_CALL16
2816 || *r
== BFD_RELOC_MIPS_GOT_DISP
2817 || *r
== BFD_RELOC_MIPS_GOT_PAGE
2818 || *r
== BFD_RELOC_MIPS_GOT_OFST
2819 || *r
== BFD_RELOC_MIPS_GOT_LO16
2820 || *r
== BFD_RELOC_MIPS_CALL_LO16
2821 || (ep
->X_op
== O_subtract
2822 && *r
== BFD_RELOC_PCREL_LO16
));
2826 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2828 && (ep
->X_op
== O_constant
2829 || (ep
->X_op
== O_symbol
2830 && (*r
== BFD_RELOC_MIPS_HIGHEST
2831 || *r
== BFD_RELOC_HI16_S
2832 || *r
== BFD_RELOC_HI16
2833 || *r
== BFD_RELOC_GPREL16
2834 || *r
== BFD_RELOC_MIPS_GOT_HI16
2835 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2836 || (ep
->X_op
== O_subtract
2837 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2841 assert (ep
!= NULL
);
2843 * This allows macro() to pass an immediate expression for
2844 * creating short branches without creating a symbol.
2845 * Note that the expression still might come from the assembly
2846 * input, in which case the value is not checked for range nor
2847 * is a relocation entry generated (yuck).
2849 if (ep
->X_op
== O_constant
)
2851 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2855 if (mips_pic
== EMBEDDED_PIC
)
2856 *r
= BFD_RELOC_16_PCREL_S2
;
2858 *r
= BFD_RELOC_16_PCREL
;
2862 assert (ep
!= NULL
);
2863 *r
= BFD_RELOC_MIPS_JMP
;
2867 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2876 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2878 append_insn (place
, &insn
, ep
, r
, false);
2882 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2884 int *counter ATTRIBUTE_UNUSED
;
2890 struct mips_cl_insn insn
;
2891 bfd_reloc_code_real_type r
[3]
2892 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2894 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2895 assert (insn
.insn_mo
);
2896 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2898 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2899 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2902 assert (insn
.insn_mo
->name
);
2903 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2906 insn
.insn_opcode
= insn
.insn_mo
->match
;
2907 insn
.use_extend
= false;
2926 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2931 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2935 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2939 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2949 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2956 regno
= va_arg (args
, int);
2957 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2958 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2979 assert (ep
!= NULL
);
2981 if (ep
->X_op
!= O_constant
)
2982 *r
= (int) BFD_RELOC_UNUSED
+ c
;
2985 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
2986 false, &insn
.insn_opcode
, &insn
.use_extend
,
2989 *r
= BFD_RELOC_UNUSED
;
2995 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3002 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3004 append_insn (place
, &insn
, ep
, r
, false);
3008 * Generate a "jalr" instruction with a relocation hint to the called
3009 * function. This occurs in NewABI PIC code.
3012 macro_build_jalr (icnt
, ep
)
3023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3026 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3027 0, ep
, false, BFD_RELOC_MIPS_JALR
);
3031 * Generate a "lui" instruction.
3034 macro_build_lui (place
, counter
, ep
, regnum
)
3040 expressionS high_expr
;
3041 struct mips_cl_insn insn
;
3042 bfd_reloc_code_real_type r
[3]
3043 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3044 const char *name
= "lui";
3045 const char *fmt
= "t,u";
3047 assert (! mips_opts
.mips16
);
3053 high_expr
.X_op
= O_constant
;
3054 high_expr
.X_add_number
= ep
->X_add_number
;
3057 if (high_expr
.X_op
== O_constant
)
3059 /* we can compute the instruction now without a relocation entry */
3060 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3062 *r
= BFD_RELOC_UNUSED
;
3064 else if (! HAVE_NEWABI
)
3066 assert (ep
->X_op
== O_symbol
);
3067 /* _gp_disp is a special case, used from s_cpload. */
3068 assert (mips_pic
== NO_PIC
3069 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3070 *r
= BFD_RELOC_HI16_S
;
3074 * If the macro is about to expand into a second instruction,
3075 * print a warning if needed. We need to pass ip as a parameter
3076 * to generate a better warning message here...
3078 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3079 as_warn (_("Macro instruction expanded into multiple instructions"));
3082 ++*counter
; /* bump instruction counter */
3084 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3085 assert (insn
.insn_mo
);
3086 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3087 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3089 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3090 if (*r
== BFD_RELOC_UNUSED
)
3092 insn
.insn_opcode
|= high_expr
.X_add_number
;
3093 append_insn (place
, &insn
, NULL
, r
, false);
3096 append_insn (place
, &insn
, &high_expr
, r
, false);
3099 /* Generate a sequence of instructions to do a load or store from a constant
3100 offset off of a base register (breg) into/from a target register (treg),
3101 using AT if necessary. */
3103 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3110 assert (ep
->X_op
== O_constant
);
3112 /* Right now, this routine can only handle signed 32-bit contants. */
3113 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3114 as_warn (_("operand overflow"));
3116 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3118 /* Signed 16-bit offset will fit in the op. Easy! */
3119 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3120 (int) BFD_RELOC_LO16
, breg
);
3124 /* 32-bit offset, need multiple instructions and AT, like:
3125 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3126 addu $tempreg,$tempreg,$breg
3127 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3128 to handle the complete offset. */
3129 macro_build_lui (place
, counter
, ep
, AT
);
3132 macro_build (place
, counter
, (expressionS
*) NULL
,
3133 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3134 "d,v,t", AT
, AT
, breg
);
3137 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3138 (int) BFD_RELOC_LO16
, AT
);
3141 as_warn (_("Macro used $at after \".set noat\""));
3146 * Generates code to set the $at register to true (one)
3147 * if reg is less than the immediate expression.
3150 set_at (counter
, reg
, unsignedp
)
3155 if (imm_expr
.X_op
== O_constant
3156 && imm_expr
.X_add_number
>= -0x8000
3157 && imm_expr
.X_add_number
< 0x8000)
3158 macro_build ((char *) NULL
, counter
, &imm_expr
,
3159 unsignedp
? "sltiu" : "slti",
3160 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3163 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3164 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3165 unsignedp
? "sltu" : "slt",
3166 "d,v,t", AT
, reg
, AT
);
3170 /* Warn if an expression is not a constant. */
3173 check_absolute_expr (ip
, ex
)
3174 struct mips_cl_insn
*ip
;
3177 if (ex
->X_op
== O_big
)
3178 as_bad (_("unsupported large constant"));
3179 else if (ex
->X_op
!= O_constant
)
3180 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3183 /* Count the leading zeroes by performing a binary chop. This is a
3184 bulky bit of source, but performance is a LOT better for the
3185 majority of values than a simple loop to count the bits:
3186 for (lcnt = 0; (lcnt < 32); lcnt++)
3187 if ((v) & (1 << (31 - lcnt)))
3189 However it is not code size friendly, and the gain will drop a bit
3190 on certain cached systems.
3192 #define COUNT_TOP_ZEROES(v) \
3193 (((v) & ~0xffff) == 0 \
3194 ? ((v) & ~0xff) == 0 \
3195 ? ((v) & ~0xf) == 0 \
3196 ? ((v) & ~0x3) == 0 \
3197 ? ((v) & ~0x1) == 0 \
3202 : ((v) & ~0x7) == 0 \
3205 : ((v) & ~0x3f) == 0 \
3206 ? ((v) & ~0x1f) == 0 \
3209 : ((v) & ~0x7f) == 0 \
3212 : ((v) & ~0xfff) == 0 \
3213 ? ((v) & ~0x3ff) == 0 \
3214 ? ((v) & ~0x1ff) == 0 \
3217 : ((v) & ~0x7ff) == 0 \
3220 : ((v) & ~0x3fff) == 0 \
3221 ? ((v) & ~0x1fff) == 0 \
3224 : ((v) & ~0x7fff) == 0 \
3227 : ((v) & ~0xffffff) == 0 \
3228 ? ((v) & ~0xfffff) == 0 \
3229 ? ((v) & ~0x3ffff) == 0 \
3230 ? ((v) & ~0x1ffff) == 0 \
3233 : ((v) & ~0x7ffff) == 0 \
3236 : ((v) & ~0x3fffff) == 0 \
3237 ? ((v) & ~0x1fffff) == 0 \
3240 : ((v) & ~0x7fffff) == 0 \
3243 : ((v) & ~0xfffffff) == 0 \
3244 ? ((v) & ~0x3ffffff) == 0 \
3245 ? ((v) & ~0x1ffffff) == 0 \
3248 : ((v) & ~0x7ffffff) == 0 \
3251 : ((v) & ~0x3fffffff) == 0 \
3252 ? ((v) & ~0x1fffffff) == 0 \
3255 : ((v) & ~0x7fffffff) == 0 \
3260 * This routine generates the least number of instructions neccessary to load
3261 * an absolute expression value into a register.
3264 load_register (counter
, reg
, ep
, dbl
)
3271 expressionS hi32
, lo32
;
3273 if (ep
->X_op
!= O_big
)
3275 assert (ep
->X_op
== O_constant
);
3276 if (ep
->X_add_number
< 0x8000
3277 && (ep
->X_add_number
>= 0
3278 || (ep
->X_add_number
>= -0x8000
3281 || sizeof (ep
->X_add_number
) > 4))))
3283 /* We can handle 16 bit signed values with an addiu to
3284 $zero. No need to ever use daddiu here, since $zero and
3285 the result are always correct in 32 bit mode. */
3286 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3287 (int) BFD_RELOC_LO16
);
3290 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3292 /* We can handle 16 bit unsigned values with an ori to
3294 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3295 (int) BFD_RELOC_LO16
);
3298 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3301 || sizeof (ep
->X_add_number
) > 4
3302 || (ep
->X_add_number
& 0x80000000) == 0))
3303 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3304 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3307 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3308 == ~ (offsetT
) 0xffffffff)))
3310 /* 32 bit values require an lui. */
3311 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3312 (int) BFD_RELOC_HI16
);
3313 if ((ep
->X_add_number
& 0xffff) != 0)
3314 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3315 (int) BFD_RELOC_LO16
);
3320 /* The value is larger than 32 bits. */
3322 if (HAVE_32BIT_GPRS
)
3324 as_bad (_("Number (0x%lx) larger than 32 bits"),
3325 (unsigned long) ep
->X_add_number
);
3326 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3327 (int) BFD_RELOC_LO16
);
3331 if (ep
->X_op
!= O_big
)
3334 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3335 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3336 hi32
.X_add_number
&= 0xffffffff;
3338 lo32
.X_add_number
&= 0xffffffff;
3342 assert (ep
->X_add_number
> 2);
3343 if (ep
->X_add_number
== 3)
3344 generic_bignum
[3] = 0;
3345 else if (ep
->X_add_number
> 4)
3346 as_bad (_("Number larger than 64 bits"));
3347 lo32
.X_op
= O_constant
;
3348 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3349 hi32
.X_op
= O_constant
;
3350 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3353 if (hi32
.X_add_number
== 0)
3358 unsigned long hi
, lo
;
3360 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3362 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3364 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3365 reg
, 0, (int) BFD_RELOC_LO16
);
3368 if (lo32
.X_add_number
& 0x80000000)
3370 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3371 (int) BFD_RELOC_HI16
);
3372 if (lo32
.X_add_number
& 0xffff)
3373 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3374 reg
, reg
, (int) BFD_RELOC_LO16
);
3379 /* Check for 16bit shifted constant. We know that hi32 is
3380 non-zero, so start the mask on the first bit of the hi32
3385 unsigned long himask
, lomask
;
3389 himask
= 0xffff >> (32 - shift
);
3390 lomask
= (0xffff << shift
) & 0xffffffff;
3394 himask
= 0xffff << (shift
- 32);
3397 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3398 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3402 tmp
.X_op
= O_constant
;
3404 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3405 | (lo32
.X_add_number
>> shift
));
3407 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3408 macro_build ((char *) NULL
, counter
, &tmp
,
3409 "ori", "t,r,i", reg
, 0,
3410 (int) BFD_RELOC_LO16
);
3411 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3412 (shift
>= 32) ? "dsll32" : "dsll",
3414 (shift
>= 32) ? shift
- 32 : shift
);
3419 while (shift
<= (64 - 16));
3421 /* Find the bit number of the lowest one bit, and store the
3422 shifted value in hi/lo. */
3423 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3424 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3428 while ((lo
& 1) == 0)
3433 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3439 while ((hi
& 1) == 0)
3448 /* Optimize if the shifted value is a (power of 2) - 1. */
3449 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3450 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3452 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3457 /* This instruction will set the register to be all
3459 tmp
.X_op
= O_constant
;
3460 tmp
.X_add_number
= (offsetT
) -1;
3461 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3462 reg
, 0, (int) BFD_RELOC_LO16
);
3466 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3467 (bit
>= 32) ? "dsll32" : "dsll",
3469 (bit
>= 32) ? bit
- 32 : bit
);
3471 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3472 (shift
>= 32) ? "dsrl32" : "dsrl",
3474 (shift
>= 32) ? shift
- 32 : shift
);
3479 /* Sign extend hi32 before calling load_register, because we can
3480 generally get better code when we load a sign extended value. */
3481 if ((hi32
.X_add_number
& 0x80000000) != 0)
3482 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3483 load_register (counter
, reg
, &hi32
, 0);
3486 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3490 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3491 "dsll32", "d,w,<", reg
, freg
, 0);
3499 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3501 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3502 (int) BFD_RELOC_HI16
);
3503 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3504 "dsrl32", "d,w,<", reg
, reg
, 0);
3510 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3511 "d,w,<", reg
, freg
, 16);
3515 mid16
.X_add_number
>>= 16;
3516 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3517 freg
, (int) BFD_RELOC_LO16
);
3518 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3519 "d,w,<", reg
, reg
, 16);
3522 if ((lo32
.X_add_number
& 0xffff) != 0)
3523 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3524 (int) BFD_RELOC_LO16
);
3527 /* Load an address into a register. */
3530 load_address (counter
, reg
, ep
, used_at
)
3538 if (ep
->X_op
!= O_constant
3539 && ep
->X_op
!= O_symbol
)
3541 as_bad (_("expression too complex"));
3542 ep
->X_op
= O_constant
;
3545 if (ep
->X_op
== O_constant
)
3547 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3551 if (mips_pic
== NO_PIC
)
3553 /* If this is a reference to a GP relative symbol, we want
3554 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3556 lui $reg,<sym> (BFD_RELOC_HI16_S)
3557 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3558 If we have an addend, we always use the latter form.
3560 With 64bit address space and a usable $at we want
3561 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3562 lui $at,<sym> (BFD_RELOC_HI16_S)
3563 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3564 daddiu $at,<sym> (BFD_RELOC_LO16)
3568 If $at is already in use, we use an path which is suboptimal
3569 on superscalar processors.
3570 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3571 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3573 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3575 daddiu $reg,<sym> (BFD_RELOC_LO16)
3577 if (HAVE_64BIT_ADDRESSES
)
3579 /* We don't do GP optimization for now because RELAX_ENCODE can't
3580 hold the data for such large chunks. */
3582 if (*used_at
== 0 && ! mips_opts
.noat
)
3584 macro_build (p
, counter
, ep
, "lui", "t,u",
3585 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3586 macro_build (p
, counter
, ep
, "lui", "t,u",
3587 AT
, (int) BFD_RELOC_HI16_S
);
3588 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3589 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3590 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3591 AT
, AT
, (int) BFD_RELOC_LO16
);
3592 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3593 "d,w,<", reg
, reg
, 0);
3594 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3595 "d,v,t", reg
, reg
, AT
);
3600 macro_build (p
, counter
, ep
, "lui", "t,u",
3601 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3602 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3603 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3604 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3605 "d,w,<", reg
, reg
, 16);
3606 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3607 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3608 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3609 "d,w,<", reg
, reg
, 16);
3610 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3611 reg
, reg
, (int) BFD_RELOC_LO16
);
3616 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3617 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3620 macro_build ((char *) NULL
, counter
, ep
,
3621 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3622 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3623 p
= frag_var (rs_machine_dependent
, 8, 0,
3624 RELAX_ENCODE (4, 8, 0, 4, 0,
3625 mips_opts
.warn_about_macros
),
3626 ep
->X_add_symbol
, 0, NULL
);
3628 macro_build_lui (p
, counter
, ep
, reg
);
3631 macro_build (p
, counter
, ep
,
3632 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3633 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3636 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3640 /* If this is a reference to an external symbol, we want
3641 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3643 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3645 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3646 If we have NewABI, we want
3647 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3648 If there is a constant, it must be added in after. */
3649 ex
.X_add_number
= ep
->X_add_number
;
3650 ep
->X_add_number
= 0;
3654 macro_build ((char *) NULL
, counter
, ep
,
3655 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3656 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3660 macro_build ((char *) NULL
, counter
, ep
,
3661 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3662 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3663 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3664 p
= frag_var (rs_machine_dependent
, 4, 0,
3665 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3666 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3667 macro_build (p
, counter
, ep
,
3668 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3669 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3672 if (ex
.X_add_number
!= 0)
3674 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3675 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3676 ex
.X_op
= O_constant
;
3677 macro_build ((char *) NULL
, counter
, &ex
,
3678 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3679 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3682 else if (mips_pic
== SVR4_PIC
)
3687 /* This is the large GOT case. If this is a reference to an
3688 external symbol, we want
3689 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3691 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3692 Otherwise, for a reference to a local symbol, we want
3693 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3695 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3696 If we have NewABI, we want
3697 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3698 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3699 If there is a constant, it must be added in after. */
3700 ex
.X_add_number
= ep
->X_add_number
;
3701 ep
->X_add_number
= 0;
3704 macro_build ((char *) NULL
, counter
, ep
,
3705 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3706 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3707 macro_build (p
, counter
, ep
,
3708 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3709 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3713 if (reg_needs_delay (mips_gp_register
))
3718 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3719 (int) BFD_RELOC_MIPS_GOT_HI16
);
3720 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3721 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3722 reg
, mips_gp_register
);
3723 macro_build ((char *) NULL
, counter
, ep
,
3724 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3725 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3726 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3727 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3728 mips_opts
.warn_about_macros
),
3729 ep
->X_add_symbol
, 0, NULL
);
3732 /* We need a nop before loading from $gp. This special
3733 check is required because the lui which starts the main
3734 instruction stream does not refer to $gp, and so will not
3735 insert the nop which may be required. */
3736 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3739 macro_build (p
, counter
, ep
,
3740 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3741 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3743 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3745 macro_build (p
, counter
, ep
,
3746 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3747 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3750 if (ex
.X_add_number
!= 0)
3752 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3753 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3754 ex
.X_op
= O_constant
;
3755 macro_build ((char *) NULL
, counter
, &ex
,
3756 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3757 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3760 else if (mips_pic
== EMBEDDED_PIC
)
3763 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3765 macro_build ((char *) NULL
, counter
, ep
,
3766 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3767 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3773 /* Move the contents of register SOURCE into register DEST. */
3776 move_register (counter
, dest
, source
)
3781 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3782 HAVE_32BIT_GPRS
? "addu" : "daddu",
3783 "d,v,t", dest
, source
, 0);
3788 * This routine implements the seemingly endless macro or synthesized
3789 * instructions and addressing modes in the mips assembly language. Many
3790 * of these macros are simple and are similar to each other. These could
3791 * probably be handled by some kind of table or grammer aproach instead of
3792 * this verbose method. Others are not simple macros but are more like
3793 * optimizing code generation.
3794 * One interesting optimization is when several store macros appear
3795 * consecutivly that would load AT with the upper half of the same address.
3796 * The ensuing load upper instructions are ommited. This implies some kind
3797 * of global optimization. We currently only optimize within a single macro.
3798 * For many of the load and store macros if the address is specified as a
3799 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3800 * first load register 'at' with zero and use it as the base register. The
3801 * mips assembler simply uses register $zero. Just one tiny optimization
3806 struct mips_cl_insn
*ip
;
3808 register int treg
, sreg
, dreg
, breg
;
3824 bfd_reloc_code_real_type r
;
3825 int hold_mips_optimize
;
3827 assert (! mips_opts
.mips16
);
3829 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3830 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3831 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3832 mask
= ip
->insn_mo
->mask
;
3834 expr1
.X_op
= O_constant
;
3835 expr1
.X_op_symbol
= NULL
;
3836 expr1
.X_add_symbol
= NULL
;
3837 expr1
.X_add_number
= 1;
3849 mips_emit_delays (true);
3850 ++mips_opts
.noreorder
;
3851 mips_any_noreorder
= 1;
3853 expr1
.X_add_number
= 8;
3854 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3859 move_register (&icnt
, dreg
, sreg
);
3860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3861 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3863 --mips_opts
.noreorder
;
3884 if (imm_expr
.X_op
== O_constant
3885 && imm_expr
.X_add_number
>= -0x8000
3886 && imm_expr
.X_add_number
< 0x8000)
3888 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3889 (int) BFD_RELOC_LO16
);
3892 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3893 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3913 if (imm_expr
.X_op
== O_constant
3914 && imm_expr
.X_add_number
>= 0
3915 && imm_expr
.X_add_number
< 0x10000)
3917 if (mask
!= M_NOR_I
)
3918 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3919 sreg
, (int) BFD_RELOC_LO16
);
3922 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3923 treg
, sreg
, (int) BFD_RELOC_LO16
);
3924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3925 "d,v,t", treg
, treg
, 0);
3930 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3931 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3949 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3955 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3956 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3965 likely
? "bgezl" : "bgez", "s,p", sreg
);
3970 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3971 likely
? "blezl" : "blez", "s,p", treg
);
3974 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
3976 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3977 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3983 /* check for > max integer */
3984 maxnum
= 0x7fffffff;
3985 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3992 if (imm_expr
.X_op
== O_constant
3993 && imm_expr
.X_add_number
>= maxnum
3994 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3997 /* result is always false */
4001 as_warn (_("Branch %s is always false (nop)"),
4003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4009 as_warn (_("Branch likely %s is always false"),
4011 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4016 if (imm_expr
.X_op
!= O_constant
)
4017 as_bad (_("Unsupported large constant"));
4018 ++imm_expr
.X_add_number
;
4022 if (mask
== M_BGEL_I
)
4024 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4027 likely
? "bgezl" : "bgez", "s,p", sreg
);
4030 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4033 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4036 maxnum
= 0x7fffffff;
4037 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4044 maxnum
= - maxnum
- 1;
4045 if (imm_expr
.X_op
== O_constant
4046 && imm_expr
.X_add_number
<= maxnum
4047 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4050 /* result is always true */
4051 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4055 set_at (&icnt
, sreg
, 0);
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4057 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4068 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4072 "d,v,t", AT
, sreg
, treg
);
4073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4074 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4082 && imm_expr
.X_op
== O_constant
4083 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4085 if (imm_expr
.X_op
!= O_constant
)
4086 as_bad (_("Unsupported large constant"));
4087 ++imm_expr
.X_add_number
;
4091 if (mask
== M_BGEUL_I
)
4093 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4095 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4098 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4101 set_at (&icnt
, sreg
, 1);
4102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4103 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4111 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4112 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4118 likely
? "bltzl" : "bltz", "s,p", treg
);
4121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4124 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4132 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4133 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4139 "d,v,t", AT
, treg
, sreg
);
4140 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4141 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4149 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4150 likely
? "blezl" : "blez", "s,p", sreg
);
4155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4156 likely
? "bgezl" : "bgez", "s,p", treg
);
4159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4162 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4168 maxnum
= 0x7fffffff;
4169 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4176 if (imm_expr
.X_op
== O_constant
4177 && imm_expr
.X_add_number
>= maxnum
4178 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4180 if (imm_expr
.X_op
!= O_constant
)
4181 as_bad (_("Unsupported large constant"));
4182 ++imm_expr
.X_add_number
;
4186 if (mask
== M_BLTL_I
)
4188 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4190 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4191 likely
? "bltzl" : "bltz", "s,p", sreg
);
4194 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4196 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4197 likely
? "blezl" : "blez", "s,p", sreg
);
4200 set_at (&icnt
, sreg
, 0);
4201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4202 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4211 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4217 "d,v,t", AT
, treg
, sreg
);
4218 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4219 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4227 && imm_expr
.X_op
== O_constant
4228 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4230 if (imm_expr
.X_op
!= O_constant
)
4231 as_bad (_("Unsupported large constant"));
4232 ++imm_expr
.X_add_number
;
4236 if (mask
== M_BLTUL_I
)
4238 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4240 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4243 likely
? "beql" : "beq",
4247 set_at (&icnt
, sreg
, 1);
4248 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4249 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4257 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4258 likely
? "bltzl" : "bltz", "s,p", sreg
);
4263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4264 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4270 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4280 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4281 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4287 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4288 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4303 as_warn (_("Divide by zero."));
4305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4313 mips_emit_delays (true);
4314 ++mips_opts
.noreorder
;
4315 mips_any_noreorder
= 1;
4318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4319 "s,t,q", treg
, 0, 7);
4320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4321 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4325 expr1
.X_add_number
= 8;
4326 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4328 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4329 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4332 expr1
.X_add_number
= -1;
4333 macro_build ((char *) NULL
, &icnt
, &expr1
,
4334 dbl
? "daddiu" : "addiu",
4335 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4336 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4337 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4340 expr1
.X_add_number
= 1;
4341 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4342 (int) BFD_RELOC_LO16
);
4343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4344 "d,w,<", AT
, AT
, 31);
4348 expr1
.X_add_number
= 0x80000000;
4349 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4350 (int) BFD_RELOC_HI16
);
4354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4355 "s,t,q", sreg
, AT
, 6);
4356 /* We want to close the noreorder block as soon as possible, so
4357 that later insns are available for delay slot filling. */
4358 --mips_opts
.noreorder
;
4362 expr1
.X_add_number
= 8;
4363 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4367 /* We want to close the noreorder block as soon as possible, so
4368 that later insns are available for delay slot filling. */
4369 --mips_opts
.noreorder
;
4371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4413 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4415 as_warn (_("Divide by zero."));
4417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4420 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4424 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4426 if (strcmp (s2
, "mflo") == 0)
4427 move_register (&icnt
, dreg
, sreg
);
4429 move_register (&icnt
, dreg
, 0);
4432 if (imm_expr
.X_op
== O_constant
4433 && imm_expr
.X_add_number
== -1
4434 && s
[strlen (s
) - 1] != 'u')
4436 if (strcmp (s2
, "mflo") == 0)
4438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4439 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4442 move_register (&icnt
, dreg
, 0);
4446 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4468 mips_emit_delays (true);
4469 ++mips_opts
.noreorder
;
4470 mips_any_noreorder
= 1;
4473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4474 "s,t,q", treg
, 0, 7);
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4477 /* We want to close the noreorder block as soon as possible, so
4478 that later insns are available for delay slot filling. */
4479 --mips_opts
.noreorder
;
4483 expr1
.X_add_number
= 8;
4484 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4488 /* We want to close the noreorder block as soon as possible, so
4489 that later insns are available for delay slot filling. */
4490 --mips_opts
.noreorder
;
4491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4500 /* Load the address of a symbol into a register. If breg is not
4501 zero, we then add a base register to it. */
4503 if (dbl
&& HAVE_32BIT_GPRS
)
4504 as_warn (_("dla used to load 32-bit register"));
4506 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4507 as_warn (_("la used to load 64-bit address"));
4509 if (offset_expr
.X_op
== O_constant
4510 && offset_expr
.X_add_number
>= -0x8000
4511 && offset_expr
.X_add_number
< 0x8000)
4513 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4514 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4515 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4530 /* When generating embedded PIC code, we permit expressions of
4533 la $treg,foo-bar($breg)
4534 where bar is an address in the current section. These are used
4535 when getting the addresses of functions. We don't permit
4536 X_add_number to be non-zero, because if the symbol is
4537 external the relaxing code needs to know that any addend is
4538 purely the offset to X_op_symbol. */
4539 if (mips_pic
== EMBEDDED_PIC
4540 && offset_expr
.X_op
== O_subtract
4541 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4542 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4543 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4545 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4548 && (offset_expr
.X_add_number
== 0
4549 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4556 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4560 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4561 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4563 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4564 "d,v,t", tempreg
, tempreg
, breg
);
4566 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4567 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4568 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4574 if (offset_expr
.X_op
!= O_symbol
4575 && offset_expr
.X_op
!= O_constant
)
4577 as_bad (_("expression too complex"));
4578 offset_expr
.X_op
= O_constant
;
4581 if (offset_expr
.X_op
== O_constant
)
4582 load_register (&icnt
, tempreg
, &offset_expr
,
4583 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4584 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4585 : HAVE_64BIT_ADDRESSES
));
4586 else if (mips_pic
== NO_PIC
)
4588 /* If this is a reference to a GP relative symbol, we want
4589 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4591 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4593 If we have a constant, we need two instructions anyhow,
4594 so we may as well always use the latter form.
4596 With 64bit address space and a usable $at we want
4597 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4598 lui $at,<sym> (BFD_RELOC_HI16_S)
4599 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4600 daddiu $at,<sym> (BFD_RELOC_LO16)
4602 daddu $tempreg,$tempreg,$at
4604 If $at is already in use, we use an path which is suboptimal
4605 on superscalar processors.
4606 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4607 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4609 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4611 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4614 if (HAVE_64BIT_ADDRESSES
)
4616 /* We don't do GP optimization for now because RELAX_ENCODE can't
4617 hold the data for such large chunks. */
4619 if (used_at
== 0 && ! mips_opts
.noat
)
4621 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4622 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4623 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4624 AT
, (int) BFD_RELOC_HI16_S
);
4625 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4626 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4627 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4628 AT
, AT
, (int) BFD_RELOC_LO16
);
4629 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4630 "d,w,<", tempreg
, tempreg
, 0);
4631 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4632 "d,v,t", tempreg
, tempreg
, AT
);
4637 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4638 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4639 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4640 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4641 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4642 tempreg
, tempreg
, 16);
4643 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4644 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4645 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4646 tempreg
, tempreg
, 16);
4647 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4648 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4653 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4654 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4657 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4658 "t,r,j", tempreg
, mips_gp_register
,
4659 (int) BFD_RELOC_GPREL16
);
4660 p
= frag_var (rs_machine_dependent
, 8, 0,
4661 RELAX_ENCODE (4, 8, 0, 4, 0,
4662 mips_opts
.warn_about_macros
),
4663 offset_expr
.X_add_symbol
, 0, NULL
);
4665 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4668 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4669 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4672 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4674 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4676 /* If this is a reference to an external symbol, and there
4677 is no constant, we want
4678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4679 or if tempreg is PIC_CALL_REG
4680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4681 For a local symbol, we want
4682 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4684 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4686 If we have a small constant, and this is a reference to
4687 an external symbol, we want
4688 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4690 addiu $tempreg,$tempreg,<constant>
4691 For a local symbol, we want the same instruction
4692 sequence, but we output a BFD_RELOC_LO16 reloc on the
4695 If we have a large constant, and this is a reference to
4696 an external symbol, we want
4697 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4698 lui $at,<hiconstant>
4699 addiu $at,$at,<loconstant>
4700 addu $tempreg,$tempreg,$at
4701 For a local symbol, we want the same instruction
4702 sequence, but we output a BFD_RELOC_LO16 reloc on the
4705 For NewABI, we want for local or external data addresses
4706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4707 For a local function symbol, we want
4708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4710 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4713 expr1
.X_add_number
= offset_expr
.X_add_number
;
4714 offset_expr
.X_add_number
= 0;
4716 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4717 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4718 else if (HAVE_NEWABI
)
4719 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4720 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4721 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4722 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4723 if (expr1
.X_add_number
== 0)
4732 /* We're going to put in an addu instruction using
4733 tempreg, so we may as well insert the nop right
4735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4739 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4740 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4742 ? mips_opts
.warn_about_macros
4744 offset_expr
.X_add_symbol
, 0, NULL
);
4747 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4750 macro_build (p
, &icnt
, &expr1
,
4751 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4752 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4753 /* FIXME: If breg == 0, and the next instruction uses
4754 $tempreg, then if this variant case is used an extra
4755 nop will be generated. */
4757 else if (expr1
.X_add_number
>= -0x8000
4758 && expr1
.X_add_number
< 0x8000)
4760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4762 macro_build ((char *) NULL
, &icnt
, &expr1
,
4763 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4764 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4765 frag_var (rs_machine_dependent
, 0, 0,
4766 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4767 offset_expr
.X_add_symbol
, 0, NULL
);
4773 /* If we are going to add in a base register, and the
4774 target register and the base register are the same,
4775 then we are using AT as a temporary register. Since
4776 we want to load the constant into AT, we add our
4777 current AT (from the global offset table) and the
4778 register into the register now, and pretend we were
4779 not using a base register. */
4784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4787 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4788 "d,v,t", treg
, AT
, breg
);
4794 /* Set mips_optimize around the lui instruction to avoid
4795 inserting an unnecessary nop after the lw. */
4796 hold_mips_optimize
= mips_optimize
;
4798 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4799 mips_optimize
= hold_mips_optimize
;
4801 macro_build ((char *) NULL
, &icnt
, &expr1
,
4802 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4803 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4804 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4805 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4806 "d,v,t", tempreg
, tempreg
, AT
);
4807 frag_var (rs_machine_dependent
, 0, 0,
4808 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4809 offset_expr
.X_add_symbol
, 0, NULL
);
4813 else if (mips_pic
== SVR4_PIC
)
4817 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4818 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4819 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4821 /* This is the large GOT case. If this is a reference to an
4822 external symbol, and there is no constant, we want
4823 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4824 addu $tempreg,$tempreg,$gp
4825 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4826 or if tempreg is PIC_CALL_REG
4827 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4828 addu $tempreg,$tempreg,$gp
4829 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4830 For a local symbol, we want
4831 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4833 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4835 If we have a small constant, and this is a reference to
4836 an external symbol, we want
4837 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4838 addu $tempreg,$tempreg,$gp
4839 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4841 addiu $tempreg,$tempreg,<constant>
4842 For a local symbol, we want
4843 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4845 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4847 If we have a large constant, and this is a reference to
4848 an external symbol, we want
4849 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4850 addu $tempreg,$tempreg,$gp
4851 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4852 lui $at,<hiconstant>
4853 addiu $at,$at,<loconstant>
4854 addu $tempreg,$tempreg,$at
4855 For a local symbol, we want
4856 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4857 lui $at,<hiconstant>
4858 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4859 addu $tempreg,$tempreg,$at
4861 For NewABI, we want for local data addresses
4862 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4865 expr1
.X_add_number
= offset_expr
.X_add_number
;
4866 offset_expr
.X_add_number
= 0;
4868 if (reg_needs_delay (mips_gp_register
))
4872 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4874 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4875 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4877 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4878 tempreg
, lui_reloc_type
);
4879 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4880 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4881 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
4882 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4883 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4884 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4885 if (expr1
.X_add_number
== 0)
4893 /* We're going to put in an addu instruction using
4894 tempreg, so we may as well insert the nop right
4896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4901 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4902 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4905 ? mips_opts
.warn_about_macros
4907 offset_expr
.X_add_symbol
, 0, NULL
);
4909 else if (expr1
.X_add_number
>= -0x8000
4910 && expr1
.X_add_number
< 0x8000)
4912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4914 macro_build ((char *) NULL
, &icnt
, &expr1
,
4915 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4916 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4918 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4919 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4921 ? mips_opts
.warn_about_macros
4923 offset_expr
.X_add_symbol
, 0, NULL
);
4929 /* If we are going to add in a base register, and the
4930 target register and the base register are the same,
4931 then we are using AT as a temporary register. Since
4932 we want to load the constant into AT, we add our
4933 current AT (from the global offset table) and the
4934 register into the register now, and pretend we were
4935 not using a base register. */
4943 assert (tempreg
== AT
);
4944 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4947 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4948 "d,v,t", treg
, AT
, breg
);
4953 /* Set mips_optimize around the lui instruction to avoid
4954 inserting an unnecessary nop after the lw. */
4955 hold_mips_optimize
= mips_optimize
;
4957 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4958 mips_optimize
= hold_mips_optimize
;
4960 macro_build ((char *) NULL
, &icnt
, &expr1
,
4961 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4962 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4964 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4965 "d,v,t", dreg
, dreg
, AT
);
4967 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4968 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4971 ? mips_opts
.warn_about_macros
4973 offset_expr
.X_add_symbol
, 0, NULL
);
4980 /* This is needed because this instruction uses $gp, but
4981 the first instruction on the main stream does not. */
4982 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4987 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4988 macro_build (p
, &icnt
, &offset_expr
,
4989 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4994 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
4996 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
4999 if (expr1
.X_add_number
>= -0x8000
5000 && expr1
.X_add_number
< 0x8000)
5002 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5004 macro_build (p
, &icnt
, &expr1
,
5005 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5006 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5007 /* FIXME: If add_number is 0, and there was no base
5008 register, the external symbol case ended with a load,
5009 so if the symbol turns out to not be external, and
5010 the next instruction uses tempreg, an unnecessary nop
5011 will be inserted. */
5017 /* We must add in the base register now, as in the
5018 external symbol case. */
5019 assert (tempreg
== AT
);
5020 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5022 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5023 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5024 "d,v,t", treg
, AT
, breg
);
5027 /* We set breg to 0 because we have arranged to add
5028 it in in both cases. */
5032 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5034 macro_build (p
, &icnt
, &expr1
,
5035 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5036 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5038 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5039 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5040 "d,v,t", tempreg
, tempreg
, AT
);
5044 else if (mips_pic
== EMBEDDED_PIC
)
5047 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5050 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5051 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5060 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5061 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5063 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5065 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5066 "d,v,t", treg
, tempreg
, breg
);
5075 /* The j instruction may not be used in PIC code, since it
5076 requires an absolute address. We convert it to a b
5078 if (mips_pic
== NO_PIC
)
5079 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5084 /* The jal instructions must be handled as macros because when
5085 generating PIC code they expand to multi-instruction
5086 sequences. Normally they are simple instructions. */
5091 if (mips_pic
== NO_PIC
5092 || mips_pic
== EMBEDDED_PIC
)
5093 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5095 else if (mips_pic
== SVR4_PIC
)
5097 if (sreg
!= PIC_CALL_REG
)
5098 as_warn (_("MIPS PIC call to register other than $25"));
5100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5104 if (mips_cprestore_offset
< 0)
5105 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5108 if (! mips_frame_reg_valid
)
5110 as_warn (_("No .frame pseudo-op used in PIC code"));
5111 /* Quiet this warning. */
5112 mips_frame_reg_valid
= 1;
5114 if (! mips_cprestore_valid
)
5116 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5117 /* Quiet this warning. */
5118 mips_cprestore_valid
= 1;
5120 expr1
.X_add_number
= mips_cprestore_offset
;
5121 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5122 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5123 mips_gp_register
, mips_frame_reg
);
5133 if (mips_pic
== NO_PIC
)
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5135 else if (mips_pic
== SVR4_PIC
)
5139 /* If this is a reference to an external symbol, and we are
5140 using a small GOT, we want
5141 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5145 lw $gp,cprestore($sp)
5146 The cprestore value is set using the .cprestore
5147 pseudo-op. If we are using a big GOT, we want
5148 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5150 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5154 lw $gp,cprestore($sp)
5155 If the symbol is not external, we want
5156 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5158 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5161 lw $gp,cprestore($sp)
5163 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5164 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5169 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5170 "t,o(b)", PIC_CALL_REG
,
5171 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5172 macro_build_jalr (icnt
, &offset_expr
);
5179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5180 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5181 "t,o(b)", PIC_CALL_REG
,
5182 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5185 p
= frag_var (rs_machine_dependent
, 4, 0,
5186 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5187 offset_expr
.X_add_symbol
, 0, NULL
);
5193 if (reg_needs_delay (mips_gp_register
))
5197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5198 "t,u", PIC_CALL_REG
,
5199 (int) BFD_RELOC_MIPS_CALL_HI16
);
5200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5201 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5202 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5205 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5206 "t,o(b)", PIC_CALL_REG
,
5207 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5210 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5211 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5213 offset_expr
.X_add_symbol
, 0, NULL
);
5216 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5219 macro_build (p
, &icnt
, &offset_expr
,
5220 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5221 "t,o(b)", PIC_CALL_REG
,
5222 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5224 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5227 macro_build (p
, &icnt
, &offset_expr
,
5228 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5229 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5230 (int) BFD_RELOC_LO16
);
5231 macro_build_jalr (icnt
, &offset_expr
);
5233 if (mips_cprestore_offset
< 0)
5234 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5237 if (! mips_frame_reg_valid
)
5239 as_warn (_("No .frame pseudo-op used in PIC code"));
5240 /* Quiet this warning. */
5241 mips_frame_reg_valid
= 1;
5243 if (! mips_cprestore_valid
)
5245 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5246 /* Quiet this warning. */
5247 mips_cprestore_valid
= 1;
5249 if (mips_opts
.noreorder
)
5250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5252 expr1
.X_add_number
= mips_cprestore_offset
;
5253 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5254 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5255 mips_gp_register
, mips_frame_reg
);
5259 else if (mips_pic
== EMBEDDED_PIC
)
5261 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5262 /* The linker may expand the call to a longer sequence which
5263 uses $at, so we must break rather than return. */
5288 /* Itbl support may require additional care here. */
5293 /* Itbl support may require additional care here. */
5298 /* Itbl support may require additional care here. */
5303 /* Itbl support may require additional care here. */
5315 if (mips_arch
== CPU_R4650
)
5317 as_bad (_("opcode not supported on this processor"));
5321 /* Itbl support may require additional care here. */
5326 /* Itbl support may require additional care here. */
5331 /* Itbl support may require additional care here. */
5351 if (breg
== treg
|| coproc
|| lr
)
5373 /* Itbl support may require additional care here. */
5378 /* Itbl support may require additional care here. */
5383 /* Itbl support may require additional care here. */
5388 /* Itbl support may require additional care here. */
5404 if (mips_arch
== CPU_R4650
)
5406 as_bad (_("opcode not supported on this processor"));
5411 /* Itbl support may require additional care here. */
5415 /* Itbl support may require additional care here. */
5420 /* Itbl support may require additional care here. */
5432 /* Itbl support may require additional care here. */
5433 if (mask
== M_LWC1_AB
5434 || mask
== M_SWC1_AB
5435 || mask
== M_LDC1_AB
5436 || mask
== M_SDC1_AB
5445 /* For embedded PIC, we allow loads where the offset is calculated
5446 by subtracting a symbol in the current segment from an unknown
5447 symbol, relative to a base register, e.g.:
5448 <op> $treg, <sym>-<localsym>($breg)
5449 This is used by the compiler for switch statements. */
5450 if (mips_pic
== EMBEDDED_PIC
5451 && offset_expr
.X_op
== O_subtract
5452 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5453 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5454 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5456 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5460 && (offset_expr
.X_add_number
== 0
5461 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5463 /* For this case, we output the instructions:
5464 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5465 addiu $tempreg,$tempreg,$breg
5466 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5467 If the relocation would fit entirely in 16 bits, it would be
5469 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5470 instead, but that seems quite difficult. */
5471 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5472 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5474 ((bfd_arch_bits_per_address (stdoutput
) == 32
5475 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5476 ? "addu" : "daddu"),
5477 "d,v,t", tempreg
, tempreg
, breg
);
5478 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5479 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5485 if (offset_expr
.X_op
!= O_constant
5486 && offset_expr
.X_op
!= O_symbol
)
5488 as_bad (_("expression too complex"));
5489 offset_expr
.X_op
= O_constant
;
5492 /* A constant expression in PIC code can be handled just as it
5493 is in non PIC code. */
5494 if (mips_pic
== NO_PIC
5495 || offset_expr
.X_op
== O_constant
)
5499 /* If this is a reference to a GP relative symbol, and there
5500 is no base register, we want
5501 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5502 Otherwise, if there is no base register, we want
5503 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5504 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5505 If we have a constant, we need two instructions anyhow,
5506 so we always use the latter form.
5508 If we have a base register, and this is a reference to a
5509 GP relative symbol, we want
5510 addu $tempreg,$breg,$gp
5511 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5513 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5514 addu $tempreg,$tempreg,$breg
5515 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5516 With a constant we always use the latter case.
5518 With 64bit address space and no base register and $at usable,
5520 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5521 lui $at,<sym> (BFD_RELOC_HI16_S)
5522 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5525 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5526 If we have a base register, we want
5527 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5528 lui $at,<sym> (BFD_RELOC_HI16_S)
5529 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5533 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5535 Without $at we can't generate the optimal path for superscalar
5536 processors here since this would require two temporary registers.
5537 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5538 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5540 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5542 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5543 If we have a base register, we want
5544 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5545 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5547 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5549 daddu $tempreg,$tempreg,$breg
5550 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5552 If we have 64-bit addresses, as an optimization, for
5553 addresses which are 32-bit constants (e.g. kseg0/kseg1
5554 addresses) we fall back to the 32-bit address generation
5555 mechanism since it is more efficient. Note that due to
5556 the signed offset used by memory operations, the 32-bit
5557 range is shifted down by 32768 here. This code should
5558 probably attempt to generate 64-bit constants more
5559 efficiently in general.
5561 if (HAVE_64BIT_ADDRESSES
5562 && !(offset_expr
.X_op
== O_constant
5563 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5567 /* We don't do GP optimization for now because RELAX_ENCODE can't
5568 hold the data for such large chunks. */
5570 if (used_at
== 0 && ! mips_opts
.noat
)
5572 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5573 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5574 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5575 AT
, (int) BFD_RELOC_HI16_S
);
5576 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5577 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5579 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5580 "d,v,t", AT
, AT
, breg
);
5581 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5582 "d,w,<", tempreg
, tempreg
, 0);
5583 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5584 "d,v,t", tempreg
, tempreg
, AT
);
5585 macro_build (p
, &icnt
, &offset_expr
, s
,
5586 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5591 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5592 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5593 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5594 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5595 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5596 "d,w,<", tempreg
, tempreg
, 16);
5597 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5598 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5599 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5600 "d,w,<", tempreg
, tempreg
, 16);
5602 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5603 "d,v,t", tempreg
, tempreg
, breg
);
5604 macro_build (p
, &icnt
, &offset_expr
, s
,
5605 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5613 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5614 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5619 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5620 treg
, (int) BFD_RELOC_GPREL16
,
5622 p
= frag_var (rs_machine_dependent
, 8, 0,
5623 RELAX_ENCODE (4, 8, 0, 4, 0,
5624 (mips_opts
.warn_about_macros
5626 && mips_opts
.noat
))),
5627 offset_expr
.X_add_symbol
, 0, NULL
);
5630 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5633 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5634 (int) BFD_RELOC_LO16
, tempreg
);
5638 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5639 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5645 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5646 "d,v,t", tempreg
, breg
, mips_gp_register
);
5647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5648 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5649 p
= frag_var (rs_machine_dependent
, 12, 0,
5650 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5651 offset_expr
.X_add_symbol
, 0, NULL
);
5653 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5656 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5657 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5658 "d,v,t", tempreg
, tempreg
, breg
);
5661 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5662 (int) BFD_RELOC_LO16
, tempreg
);
5665 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5668 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5670 /* If this is a reference to an external symbol, we want
5671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5673 <op> $treg,0($tempreg)
5675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5677 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5678 <op> $treg,0($tempreg)
5679 If we have NewABI, we want
5680 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5681 If there is a base register, we add it to $tempreg before
5682 the <op>. If there is a constant, we stick it in the
5683 <op> instruction. We don't handle constants larger than
5684 16 bits, because we have no way to load the upper 16 bits
5685 (actually, we could handle them for the subset of cases
5686 in which we are not using $at). */
5687 assert (offset_expr
.X_op
== O_symbol
);
5688 expr1
.X_add_number
= offset_expr
.X_add_number
;
5689 offset_expr
.X_add_number
= 0;
5691 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5692 if (expr1
.X_add_number
< -0x8000
5693 || expr1
.X_add_number
>= 0x8000)
5694 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5696 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5697 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5698 (int) lw_reloc_type
, mips_gp_register
);
5699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5700 p
= frag_var (rs_machine_dependent
, 4, 0,
5701 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5702 offset_expr
.X_add_symbol
, 0, NULL
);
5703 macro_build (p
, &icnt
, &offset_expr
,
5704 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5705 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5708 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5709 "d,v,t", tempreg
, tempreg
, breg
);
5710 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5711 (int) BFD_RELOC_LO16
, tempreg
);
5713 else if (mips_pic
== SVR4_PIC
)
5718 /* If this is a reference to an external symbol, we want
5719 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5720 addu $tempreg,$tempreg,$gp
5721 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5722 <op> $treg,0($tempreg)
5724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5726 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5727 <op> $treg,0($tempreg)
5728 If there is a base register, we add it to $tempreg before
5729 the <op>. If there is a constant, we stick it in the
5730 <op> instruction. We don't handle constants larger than
5731 16 bits, because we have no way to load the upper 16 bits
5732 (actually, we could handle them for the subset of cases
5733 in which we are not using $at).
5736 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5737 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5738 <op> $treg,0($tempreg)
5740 assert (offset_expr
.X_op
== O_symbol
);
5741 expr1
.X_add_number
= offset_expr
.X_add_number
;
5742 offset_expr
.X_add_number
= 0;
5743 if (expr1
.X_add_number
< -0x8000
5744 || expr1
.X_add_number
>= 0x8000)
5745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5749 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5750 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5752 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5753 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5754 "t,r,j", tempreg
, tempreg
,
5755 BFD_RELOC_MIPS_GOT_OFST
);
5757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5758 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5759 "d,v,t", tempreg
, tempreg
, breg
);
5760 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5761 (int) BFD_RELOC_LO16
, tempreg
);
5768 if (reg_needs_delay (mips_gp_register
))
5773 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5774 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5776 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5777 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5779 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5780 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5782 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5783 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5784 offset_expr
.X_add_symbol
, 0, NULL
);
5787 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5790 macro_build (p
, &icnt
, &offset_expr
,
5791 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5792 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5795 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5797 macro_build (p
, &icnt
, &offset_expr
,
5798 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5799 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5802 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5803 "d,v,t", tempreg
, tempreg
, breg
);
5804 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5805 (int) BFD_RELOC_LO16
, tempreg
);
5807 else if (mips_pic
== EMBEDDED_PIC
)
5809 /* If there is no base register, we want
5810 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5811 If there is a base register, we want
5812 addu $tempreg,$breg,$gp
5813 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5815 assert (offset_expr
.X_op
== O_symbol
);
5818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5819 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
5824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5825 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5826 "d,v,t", tempreg
, breg
, mips_gp_register
);
5827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5828 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5841 load_register (&icnt
, treg
, &imm_expr
, 0);
5845 load_register (&icnt
, treg
, &imm_expr
, 1);
5849 if (imm_expr
.X_op
== O_constant
)
5851 load_register (&icnt
, AT
, &imm_expr
, 0);
5852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5853 "mtc1", "t,G", AT
, treg
);
5858 assert (offset_expr
.X_op
== O_symbol
5859 && strcmp (segment_name (S_GET_SEGMENT
5860 (offset_expr
.X_add_symbol
)),
5862 && offset_expr
.X_add_number
== 0);
5863 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5864 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
5869 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5870 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5871 order 32 bits of the value and the low order 32 bits are either
5872 zero or in OFFSET_EXPR. */
5873 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5875 if (HAVE_64BIT_GPRS
)
5876 load_register (&icnt
, treg
, &imm_expr
, 1);
5881 if (target_big_endian
)
5893 load_register (&icnt
, hreg
, &imm_expr
, 0);
5896 if (offset_expr
.X_op
== O_absent
)
5897 move_register (&icnt
, lreg
, 0);
5900 assert (offset_expr
.X_op
== O_constant
);
5901 load_register (&icnt
, lreg
, &offset_expr
, 0);
5908 /* We know that sym is in the .rdata section. First we get the
5909 upper 16 bits of the address. */
5910 if (mips_pic
== NO_PIC
)
5912 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5914 else if (mips_pic
== SVR4_PIC
)
5916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5917 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5918 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
5921 else if (mips_pic
== EMBEDDED_PIC
)
5923 /* For embedded PIC we pick up the entire address off $gp in
5924 a single instruction. */
5925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5926 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
5927 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5928 offset_expr
.X_op
= O_constant
;
5929 offset_expr
.X_add_number
= 0;
5934 /* Now we load the register(s). */
5935 if (HAVE_64BIT_GPRS
)
5936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5937 treg
, (int) BFD_RELOC_LO16
, AT
);
5940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5941 treg
, (int) BFD_RELOC_LO16
, AT
);
5944 /* FIXME: How in the world do we deal with the possible
5946 offset_expr
.X_add_number
+= 4;
5947 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5948 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5952 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5953 does not become a variant frag. */
5954 frag_wane (frag_now
);
5960 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5961 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5962 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5963 the value and the low order 32 bits are either zero or in
5965 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5967 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5968 if (HAVE_64BIT_FPRS
)
5970 assert (HAVE_64BIT_GPRS
);
5971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5972 "dmtc1", "t,S", AT
, treg
);
5976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5977 "mtc1", "t,G", AT
, treg
+ 1);
5978 if (offset_expr
.X_op
== O_absent
)
5979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5980 "mtc1", "t,G", 0, treg
);
5983 assert (offset_expr
.X_op
== O_constant
);
5984 load_register (&icnt
, AT
, &offset_expr
, 0);
5985 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5986 "mtc1", "t,G", AT
, treg
);
5992 assert (offset_expr
.X_op
== O_symbol
5993 && offset_expr
.X_add_number
== 0);
5994 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5995 if (strcmp (s
, ".lit8") == 0)
5997 if (mips_opts
.isa
!= ISA_MIPS1
)
5999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6000 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6004 breg
= mips_gp_register
;
6005 r
= BFD_RELOC_MIPS_LITERAL
;
6010 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6011 if (mips_pic
== SVR4_PIC
)
6012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6013 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6014 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6018 /* FIXME: This won't work for a 64 bit address. */
6019 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6022 if (mips_opts
.isa
!= ISA_MIPS1
)
6024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6025 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6027 /* To avoid confusion in tc_gen_reloc, we must ensure
6028 that this does not become a variant frag. */
6029 frag_wane (frag_now
);
6040 if (mips_arch
== CPU_R4650
)
6042 as_bad (_("opcode not supported on this processor"));
6045 /* Even on a big endian machine $fn comes before $fn+1. We have
6046 to adjust when loading from memory. */
6049 assert (mips_opts
.isa
== ISA_MIPS1
);
6050 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6051 target_big_endian
? treg
+ 1 : treg
,
6053 /* FIXME: A possible overflow which I don't know how to deal
6055 offset_expr
.X_add_number
+= 4;
6056 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6057 target_big_endian
? treg
: treg
+ 1,
6060 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6061 does not become a variant frag. */
6062 frag_wane (frag_now
);
6071 * The MIPS assembler seems to check for X_add_number not
6072 * being double aligned and generating:
6075 * addiu at,at,%lo(foo+1)
6078 * But, the resulting address is the same after relocation so why
6079 * generate the extra instruction?
6081 if (mips_arch
== CPU_R4650
)
6083 as_bad (_("opcode not supported on this processor"));
6086 /* Itbl support may require additional care here. */
6088 if (mips_opts
.isa
!= ISA_MIPS1
)
6099 if (mips_arch
== CPU_R4650
)
6101 as_bad (_("opcode not supported on this processor"));
6105 if (mips_opts
.isa
!= ISA_MIPS1
)
6113 /* Itbl support may require additional care here. */
6118 if (HAVE_64BIT_GPRS
)
6129 if (HAVE_64BIT_GPRS
)
6139 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6140 loads for the case of doing a pair of loads to simulate an 'ld'.
6141 This is not currently done by the compiler, and assembly coders
6142 writing embedded-pic code can cope. */
6144 if (offset_expr
.X_op
!= O_symbol
6145 && offset_expr
.X_op
!= O_constant
)
6147 as_bad (_("expression too complex"));
6148 offset_expr
.X_op
= O_constant
;
6151 /* Even on a big endian machine $fn comes before $fn+1. We have
6152 to adjust when loading from memory. We set coproc if we must
6153 load $fn+1 first. */
6154 /* Itbl support may require additional care here. */
6155 if (! target_big_endian
)
6158 if (mips_pic
== NO_PIC
6159 || offset_expr
.X_op
== O_constant
)
6163 /* If this is a reference to a GP relative symbol, we want
6164 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6165 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6166 If we have a base register, we use this
6168 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6169 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6170 If this is not a GP relative symbol, we want
6171 lui $at,<sym> (BFD_RELOC_HI16_S)
6172 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6173 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6174 If there is a base register, we add it to $at after the
6175 lui instruction. If there is a constant, we always use
6177 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6178 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6190 tempreg
= mips_gp_register
;
6197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6198 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6199 "d,v,t", AT
, breg
, mips_gp_register
);
6205 /* Itbl support may require additional care here. */
6206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6207 coproc
? treg
+ 1 : treg
,
6208 (int) BFD_RELOC_GPREL16
, tempreg
);
6209 offset_expr
.X_add_number
+= 4;
6211 /* Set mips_optimize to 2 to avoid inserting an
6213 hold_mips_optimize
= mips_optimize
;
6215 /* Itbl support may require additional care here. */
6216 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6217 coproc
? treg
: treg
+ 1,
6218 (int) BFD_RELOC_GPREL16
, tempreg
);
6219 mips_optimize
= hold_mips_optimize
;
6221 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6222 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6223 used_at
&& mips_opts
.noat
),
6224 offset_expr
.X_add_symbol
, 0, NULL
);
6226 /* We just generated two relocs. When tc_gen_reloc
6227 handles this case, it will skip the first reloc and
6228 handle the second. The second reloc already has an
6229 extra addend of 4, which we added above. We must
6230 subtract it out, and then subtract another 4 to make
6231 the first reloc come out right. The second reloc
6232 will come out right because we are going to add 4 to
6233 offset_expr when we build its instruction below.
6235 If we have a symbol, then we don't want to include
6236 the offset, because it will wind up being included
6237 when we generate the reloc. */
6239 if (offset_expr
.X_op
== O_constant
)
6240 offset_expr
.X_add_number
-= 8;
6243 offset_expr
.X_add_number
= -4;
6244 offset_expr
.X_op
= O_constant
;
6247 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6252 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6253 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6254 "d,v,t", AT
, breg
, AT
);
6258 /* Itbl support may require additional care here. */
6259 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6260 coproc
? treg
+ 1 : treg
,
6261 (int) BFD_RELOC_LO16
, AT
);
6264 /* FIXME: How do we handle overflow here? */
6265 offset_expr
.X_add_number
+= 4;
6266 /* Itbl support may require additional care here. */
6267 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6268 coproc
? treg
: treg
+ 1,
6269 (int) BFD_RELOC_LO16
, AT
);
6271 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6275 /* If this is a reference to an external symbol, we want
6276 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6281 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6283 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6284 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6285 If there is a base register we add it to $at before the
6286 lwc1 instructions. If there is a constant we include it
6287 in the lwc1 instructions. */
6289 expr1
.X_add_number
= offset_expr
.X_add_number
;
6290 offset_expr
.X_add_number
= 0;
6291 if (expr1
.X_add_number
< -0x8000
6292 || expr1
.X_add_number
>= 0x8000 - 4)
6293 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6298 frag_grow (24 + off
);
6299 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6300 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6301 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6305 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6306 "d,v,t", AT
, breg
, AT
);
6307 /* Itbl support may require additional care here. */
6308 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6309 coproc
? treg
+ 1 : treg
,
6310 (int) BFD_RELOC_LO16
, AT
);
6311 expr1
.X_add_number
+= 4;
6313 /* Set mips_optimize to 2 to avoid inserting an undesired
6315 hold_mips_optimize
= mips_optimize
;
6317 /* Itbl support may require additional care here. */
6318 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6319 coproc
? treg
: treg
+ 1,
6320 (int) BFD_RELOC_LO16
, AT
);
6321 mips_optimize
= hold_mips_optimize
;
6323 (void) frag_var (rs_machine_dependent
, 0, 0,
6324 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6325 offset_expr
.X_add_symbol
, 0, NULL
);
6327 else if (mips_pic
== SVR4_PIC
)
6332 /* If this is a reference to an external symbol, we want
6333 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6335 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6340 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6342 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6343 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6344 If there is a base register we add it to $at before the
6345 lwc1 instructions. If there is a constant we include it
6346 in the lwc1 instructions. */
6348 expr1
.X_add_number
= offset_expr
.X_add_number
;
6349 offset_expr
.X_add_number
= 0;
6350 if (expr1
.X_add_number
< -0x8000
6351 || expr1
.X_add_number
>= 0x8000 - 4)
6352 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6353 if (reg_needs_delay (mips_gp_register
))
6362 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6363 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6365 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6366 "d,v,t", AT
, AT
, mips_gp_register
);
6367 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6368 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6369 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6373 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6374 "d,v,t", AT
, breg
, AT
);
6375 /* Itbl support may require additional care here. */
6376 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6377 coproc
? treg
+ 1 : treg
,
6378 (int) BFD_RELOC_LO16
, AT
);
6379 expr1
.X_add_number
+= 4;
6381 /* Set mips_optimize to 2 to avoid inserting an undesired
6383 hold_mips_optimize
= mips_optimize
;
6385 /* Itbl support may require additional care here. */
6386 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6387 coproc
? treg
: treg
+ 1,
6388 (int) BFD_RELOC_LO16
, AT
);
6389 mips_optimize
= hold_mips_optimize
;
6390 expr1
.X_add_number
-= 4;
6392 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6393 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6394 8 + gpdel
+ off
, 1, 0),
6395 offset_expr
.X_add_symbol
, 0, NULL
);
6398 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6401 macro_build (p
, &icnt
, &offset_expr
,
6402 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6403 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6406 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6410 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6411 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6412 "d,v,t", AT
, breg
, AT
);
6415 /* Itbl support may require additional care here. */
6416 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6417 coproc
? treg
+ 1 : treg
,
6418 (int) BFD_RELOC_LO16
, AT
);
6420 expr1
.X_add_number
+= 4;
6422 /* Set mips_optimize to 2 to avoid inserting an undesired
6424 hold_mips_optimize
= mips_optimize
;
6426 /* Itbl support may require additional care here. */
6427 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6428 coproc
? treg
: treg
+ 1,
6429 (int) BFD_RELOC_LO16
, AT
);
6430 mips_optimize
= hold_mips_optimize
;
6432 else if (mips_pic
== EMBEDDED_PIC
)
6434 /* If there is no base register, we use
6435 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6436 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6437 If we have a base register, we use
6439 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6440 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6444 tempreg
= mips_gp_register
;
6449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6450 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6451 "d,v,t", AT
, breg
, mips_gp_register
);
6456 /* Itbl support may require additional care here. */
6457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6458 coproc
? treg
+ 1 : treg
,
6459 (int) BFD_RELOC_GPREL16
, tempreg
);
6460 offset_expr
.X_add_number
+= 4;
6461 /* Itbl support may require additional care here. */
6462 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6463 coproc
? treg
: treg
+ 1,
6464 (int) BFD_RELOC_GPREL16
, tempreg
);
6480 assert (HAVE_32BIT_ADDRESSES
);
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, breg
);
6483 offset_expr
.X_add_number
+= 4;
6484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6485 (int) BFD_RELOC_LO16
, breg
);
6488 /* New code added to support COPZ instructions.
6489 This code builds table entries out of the macros in mip_opcodes.
6490 R4000 uses interlocks to handle coproc delays.
6491 Other chips (like the R3000) require nops to be inserted for delays.
6493 FIXME: Currently, we require that the user handle delays.
6494 In order to fill delay slots for non-interlocked chips,
6495 we must have a way to specify delays based on the coprocessor.
6496 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6497 What are the side-effects of the cop instruction?
6498 What cache support might we have and what are its effects?
6499 Both coprocessor & memory require delays. how long???
6500 What registers are read/set/modified?
6502 If an itbl is provided to interpret cop instructions,
6503 this knowledge can be encoded in the itbl spec. */
6517 /* For now we just do C (same as Cz). The parameter will be
6518 stored in insn_opcode by mips_ip. */
6519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6524 move_register (&icnt
, dreg
, sreg
);
6527 #ifdef LOSING_COMPILER
6529 /* Try and see if this is a new itbl instruction.
6530 This code builds table entries out of the macros in mip_opcodes.
6531 FIXME: For now we just assemble the expression and pass it's
6532 value along as a 32-bit immediate.
6533 We may want to have the assembler assemble this value,
6534 so that we gain the assembler's knowledge of delay slots,
6536 Would it be more efficient to use mask (id) here? */
6537 if (itbl_have_entries
6538 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6540 s
= ip
->insn_mo
->name
;
6542 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6543 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6550 as_warn (_("Macro used $at after \".set noat\""));
6555 struct mips_cl_insn
*ip
;
6557 register int treg
, sreg
, dreg
, breg
;
6573 bfd_reloc_code_real_type r
;
6576 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6577 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6578 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6579 mask
= ip
->insn_mo
->mask
;
6581 expr1
.X_op
= O_constant
;
6582 expr1
.X_op_symbol
= NULL
;
6583 expr1
.X_add_symbol
= NULL
;
6584 expr1
.X_add_number
= 1;
6588 #endif /* LOSING_COMPILER */
6593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6594 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6602 /* The MIPS assembler some times generates shifts and adds. I'm
6603 not trying to be that fancy. GCC should do this for us
6605 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6607 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6622 mips_emit_delays (true);
6623 ++mips_opts
.noreorder
;
6624 mips_any_noreorder
= 1;
6626 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6628 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6629 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6632 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6636 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6637 "s,t,q", dreg
, AT
, 6);
6640 expr1
.X_add_number
= 8;
6641 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6648 --mips_opts
.noreorder
;
6649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6662 mips_emit_delays (true);
6663 ++mips_opts
.noreorder
;
6664 mips_any_noreorder
= 1;
6666 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6668 dbl
? "dmultu" : "multu",
6669 "s,t", sreg
, imm
? AT
: treg
);
6670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6679 expr1
.X_add_number
= 8;
6680 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6686 --mips_opts
.noreorder
;
6690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6691 "d,v,t", AT
, 0, treg
);
6692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6693 "d,t,s", AT
, sreg
, AT
);
6694 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6695 "d,t,s", dreg
, sreg
, treg
);
6696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6697 "d,v,t", dreg
, dreg
, AT
);
6701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6702 "d,v,t", AT
, 0, treg
);
6703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6704 "d,t,s", AT
, sreg
, AT
);
6705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6706 "d,t,s", dreg
, sreg
, treg
);
6707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6708 "d,v,t", dreg
, dreg
, AT
);
6715 if (imm_expr
.X_op
!= O_constant
)
6716 as_bad (_("rotate count too large"));
6717 rot
= imm_expr
.X_add_number
& 0x3f;
6719 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6720 "d,w,<", dreg
, sreg
, 0);
6725 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6726 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6729 "d,w,<", AT
, sreg
, rot
);
6730 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6731 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6732 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6733 "d,v,t", dreg
, dreg
, AT
);
6742 if (imm_expr
.X_op
!= O_constant
)
6743 as_bad (_("rotate count too large"));
6744 rot
= imm_expr
.X_add_number
& 0x1f;
6746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6747 "d,w,<", dreg
, sreg
, 0);
6750 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6751 "d,w,<", AT
, sreg
, rot
);
6752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6753 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6754 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6755 "d,v,t", dreg
, dreg
, AT
);
6761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6762 "d,v,t", AT
, 0, treg
);
6763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6764 "d,t,s", AT
, sreg
, AT
);
6765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6766 "d,t,s", dreg
, sreg
, treg
);
6767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6768 "d,v,t", dreg
, dreg
, AT
);
6772 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6773 "d,v,t", AT
, 0, treg
);
6774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6775 "d,t,s", AT
, sreg
, AT
);
6776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6777 "d,t,s", dreg
, sreg
, treg
);
6778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6779 "d,v,t", dreg
, dreg
, AT
);
6786 if (imm_expr
.X_op
!= O_constant
)
6787 as_bad (_("rotate count too large"));
6788 rot
= imm_expr
.X_add_number
& 0x3f;
6790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6791 "d,w,<", dreg
, sreg
, 0);
6796 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6797 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6800 "d,w,<", AT
, sreg
, rot
);
6801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6802 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6804 "d,v,t", dreg
, dreg
, AT
);
6813 if (imm_expr
.X_op
!= O_constant
)
6814 as_bad (_("rotate count too large"));
6815 rot
= imm_expr
.X_add_number
& 0x1f;
6817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6818 "d,w,<", dreg
, sreg
, 0);
6821 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6822 "d,w,<", AT
, sreg
, rot
);
6823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6824 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6826 "d,v,t", dreg
, dreg
, AT
);
6832 if (mips_arch
== CPU_R4650
)
6834 as_bad (_("opcode not supported on this processor"));
6837 assert (mips_opts
.isa
== ISA_MIPS1
);
6838 /* Even on a big endian machine $fn comes before $fn+1. We have
6839 to adjust when storing to memory. */
6840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6841 target_big_endian
? treg
+ 1 : treg
,
6842 (int) BFD_RELOC_LO16
, breg
);
6843 offset_expr
.X_add_number
+= 4;
6844 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6845 target_big_endian
? treg
: treg
+ 1,
6846 (int) BFD_RELOC_LO16
, breg
);
6851 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6852 treg
, (int) BFD_RELOC_LO16
);
6854 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6855 sreg
, (int) BFD_RELOC_LO16
);
6858 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6859 "d,v,t", dreg
, sreg
, treg
);
6860 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6861 dreg
, (int) BFD_RELOC_LO16
);
6866 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6868 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6869 sreg
, (int) BFD_RELOC_LO16
);
6874 as_warn (_("Instruction %s: result is always false"),
6876 move_register (&icnt
, dreg
, 0);
6879 if (imm_expr
.X_op
== O_constant
6880 && imm_expr
.X_add_number
>= 0
6881 && imm_expr
.X_add_number
< 0x10000)
6883 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6884 sreg
, (int) BFD_RELOC_LO16
);
6887 else if (imm_expr
.X_op
== O_constant
6888 && imm_expr
.X_add_number
> -0x8000
6889 && imm_expr
.X_add_number
< 0)
6891 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6892 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6893 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6894 "t,r,j", dreg
, sreg
,
6895 (int) BFD_RELOC_LO16
);
6900 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6902 "d,v,t", dreg
, sreg
, AT
);
6905 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6906 (int) BFD_RELOC_LO16
);
6911 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6917 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6919 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6920 (int) BFD_RELOC_LO16
);
6923 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6925 if (imm_expr
.X_op
== O_constant
6926 && imm_expr
.X_add_number
>= -0x8000
6927 && imm_expr
.X_add_number
< 0x8000)
6929 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6930 mask
== M_SGE_I
? "slti" : "sltiu",
6931 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6936 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6938 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6942 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6943 (int) BFD_RELOC_LO16
);
6948 case M_SGT
: /* sreg > treg <==> treg < sreg */
6954 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6958 case M_SGT_I
: /* sreg > I <==> I < sreg */
6964 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6969 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6977 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6978 (int) BFD_RELOC_LO16
);
6981 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6987 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6990 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6991 (int) BFD_RELOC_LO16
);
6995 if (imm_expr
.X_op
== O_constant
6996 && imm_expr
.X_add_number
>= -0x8000
6997 && imm_expr
.X_add_number
< 0x8000)
6999 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7000 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7003 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7009 if (imm_expr
.X_op
== O_constant
7010 && imm_expr
.X_add_number
>= -0x8000
7011 && imm_expr
.X_add_number
< 0x8000)
7013 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7014 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7017 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7018 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7019 "d,v,t", dreg
, sreg
, AT
);
7024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7025 "d,v,t", dreg
, 0, treg
);
7027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7028 "d,v,t", dreg
, 0, sreg
);
7031 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7032 "d,v,t", dreg
, sreg
, treg
);
7033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7034 "d,v,t", dreg
, 0, dreg
);
7039 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7042 "d,v,t", dreg
, 0, sreg
);
7047 as_warn (_("Instruction %s: result is always true"),
7049 macro_build ((char *) NULL
, &icnt
, &expr1
,
7050 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7051 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7054 if (imm_expr
.X_op
== O_constant
7055 && imm_expr
.X_add_number
>= 0
7056 && imm_expr
.X_add_number
< 0x10000)
7058 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7059 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7062 else if (imm_expr
.X_op
== O_constant
7063 && imm_expr
.X_add_number
> -0x8000
7064 && imm_expr
.X_add_number
< 0)
7066 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7067 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7068 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7069 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7074 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7076 "d,v,t", dreg
, sreg
, AT
);
7079 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7080 "d,v,t", dreg
, 0, dreg
);
7088 if (imm_expr
.X_op
== O_constant
7089 && imm_expr
.X_add_number
> -0x8000
7090 && imm_expr
.X_add_number
<= 0x8000)
7092 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7093 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7094 dbl
? "daddi" : "addi",
7095 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7098 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7099 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7100 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7106 if (imm_expr
.X_op
== O_constant
7107 && imm_expr
.X_add_number
> -0x8000
7108 && imm_expr
.X_add_number
<= 0x8000)
7110 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7111 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7112 dbl
? "daddiu" : "addiu",
7113 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7116 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7118 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7139 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7140 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7146 assert (mips_opts
.isa
== ISA_MIPS1
);
7147 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7148 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7151 * Is the double cfc1 instruction a bug in the mips assembler;
7152 * or is there a reason for it?
7154 mips_emit_delays (true);
7155 ++mips_opts
.noreorder
;
7156 mips_any_noreorder
= 1;
7157 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7161 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7162 expr1
.X_add_number
= 3;
7163 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7164 (int) BFD_RELOC_LO16
);
7165 expr1
.X_add_number
= 2;
7166 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7167 (int) BFD_RELOC_LO16
);
7168 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7170 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7172 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7176 --mips_opts
.noreorder
;
7185 if (offset_expr
.X_add_number
>= 0x7fff)
7186 as_bad (_("operand overflow"));
7187 /* avoid load delay */
7188 if (! target_big_endian
)
7189 ++offset_expr
.X_add_number
;
7190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7191 (int) BFD_RELOC_LO16
, breg
);
7192 if (! target_big_endian
)
7193 --offset_expr
.X_add_number
;
7195 ++offset_expr
.X_add_number
;
7196 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7197 (int) BFD_RELOC_LO16
, breg
);
7198 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7214 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7215 as_bad (_("operand overflow"));
7216 if (! target_big_endian
)
7217 offset_expr
.X_add_number
+= off
;
7218 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7219 (int) BFD_RELOC_LO16
, breg
);
7220 if (! target_big_endian
)
7221 offset_expr
.X_add_number
-= off
;
7223 offset_expr
.X_add_number
+= off
;
7224 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7225 (int) BFD_RELOC_LO16
, breg
);
7239 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7242 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7243 "d,v,t", AT
, AT
, breg
);
7244 if (! target_big_endian
)
7245 expr1
.X_add_number
= off
;
7247 expr1
.X_add_number
= 0;
7248 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7249 (int) BFD_RELOC_LO16
, AT
);
7250 if (! target_big_endian
)
7251 expr1
.X_add_number
= 0;
7253 expr1
.X_add_number
= off
;
7254 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7255 (int) BFD_RELOC_LO16
, AT
);
7261 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7264 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7265 "d,v,t", AT
, AT
, breg
);
7266 if (target_big_endian
)
7267 expr1
.X_add_number
= 0;
7268 macro_build ((char *) NULL
, &icnt
, &expr1
,
7269 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7270 (int) BFD_RELOC_LO16
, AT
);
7271 if (target_big_endian
)
7272 expr1
.X_add_number
= 1;
7274 expr1
.X_add_number
= 0;
7275 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7276 (int) BFD_RELOC_LO16
, AT
);
7277 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7284 if (offset_expr
.X_add_number
>= 0x7fff)
7285 as_bad (_("operand overflow"));
7286 if (target_big_endian
)
7287 ++offset_expr
.X_add_number
;
7288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7289 (int) BFD_RELOC_LO16
, breg
);
7290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7292 if (target_big_endian
)
7293 --offset_expr
.X_add_number
;
7295 ++offset_expr
.X_add_number
;
7296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7297 (int) BFD_RELOC_LO16
, breg
);
7310 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7311 as_bad (_("operand overflow"));
7312 if (! target_big_endian
)
7313 offset_expr
.X_add_number
+= off
;
7314 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7315 (int) BFD_RELOC_LO16
, breg
);
7316 if (! target_big_endian
)
7317 offset_expr
.X_add_number
-= off
;
7319 offset_expr
.X_add_number
+= off
;
7320 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7321 (int) BFD_RELOC_LO16
, breg
);
7335 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7338 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7339 "d,v,t", AT
, AT
, breg
);
7340 if (! target_big_endian
)
7341 expr1
.X_add_number
= off
;
7343 expr1
.X_add_number
= 0;
7344 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7345 (int) BFD_RELOC_LO16
, AT
);
7346 if (! target_big_endian
)
7347 expr1
.X_add_number
= 0;
7349 expr1
.X_add_number
= off
;
7350 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7351 (int) BFD_RELOC_LO16
, AT
);
7356 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7359 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7360 "d,v,t", AT
, AT
, breg
);
7361 if (! target_big_endian
)
7362 expr1
.X_add_number
= 0;
7363 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7364 (int) BFD_RELOC_LO16
, AT
);
7365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7367 if (! target_big_endian
)
7368 expr1
.X_add_number
= 1;
7370 expr1
.X_add_number
= 0;
7371 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7372 (int) BFD_RELOC_LO16
, AT
);
7373 if (! target_big_endian
)
7374 expr1
.X_add_number
= 0;
7376 expr1
.X_add_number
= 1;
7377 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7378 (int) BFD_RELOC_LO16
, AT
);
7379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7386 /* FIXME: Check if this is one of the itbl macros, since they
7387 are added dynamically. */
7388 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7392 as_warn (_("Macro used $at after \".set noat\""));
7395 /* Implement macros in mips16 mode. */
7399 struct mips_cl_insn
*ip
;
7402 int xreg
, yreg
, zreg
, tmp
;
7406 const char *s
, *s2
, *s3
;
7408 mask
= ip
->insn_mo
->mask
;
7410 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7411 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7412 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7416 expr1
.X_op
= O_constant
;
7417 expr1
.X_op_symbol
= NULL
;
7418 expr1
.X_add_symbol
= NULL
;
7419 expr1
.X_add_number
= 1;
7438 mips_emit_delays (true);
7439 ++mips_opts
.noreorder
;
7440 mips_any_noreorder
= 1;
7441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7442 dbl
? "ddiv" : "div",
7443 "0,x,y", xreg
, yreg
);
7444 expr1
.X_add_number
= 2;
7445 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7449 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7450 since that causes an overflow. We should do that as well,
7451 but I don't see how to do the comparisons without a temporary
7453 --mips_opts
.noreorder
;
7454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7473 mips_emit_delays (true);
7474 ++mips_opts
.noreorder
;
7475 mips_any_noreorder
= 1;
7476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7478 expr1
.X_add_number
= 2;
7479 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7482 --mips_opts
.noreorder
;
7483 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7490 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7500 if (imm_expr
.X_op
!= O_constant
)
7501 as_bad (_("Unsupported large constant"));
7502 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7503 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7504 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7508 if (imm_expr
.X_op
!= O_constant
)
7509 as_bad (_("Unsupported large constant"));
7510 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7511 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7516 if (imm_expr
.X_op
!= O_constant
)
7517 as_bad (_("Unsupported large constant"));
7518 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7519 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7542 goto do_reverse_branch
;
7546 goto do_reverse_branch
;
7558 goto do_reverse_branch
;
7569 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7571 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7598 goto do_addone_branch_i
;
7603 goto do_addone_branch_i
;
7618 goto do_addone_branch_i
;
7625 if (imm_expr
.X_op
!= O_constant
)
7626 as_bad (_("Unsupported large constant"));
7627 ++imm_expr
.X_add_number
;
7630 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7635 expr1
.X_add_number
= 0;
7636 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7638 move_register (&icnt
, xreg
, yreg
);
7639 expr1
.X_add_number
= 2;
7640 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7642 "neg", "x,w", xreg
, xreg
);
7646 /* For consistency checking, verify that all bits are specified either
7647 by the match/mask part of the instruction definition, or by the
7650 validate_mips_insn (opc
)
7651 const struct mips_opcode
*opc
;
7653 const char *p
= opc
->args
;
7655 unsigned long used_bits
= opc
->mask
;
7657 if ((used_bits
& opc
->match
) != opc
->match
)
7659 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7660 opc
->name
, opc
->args
);
7663 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7670 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7671 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7673 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7674 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7675 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7676 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7678 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7679 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7681 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7683 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7684 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7685 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7686 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7687 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7688 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7689 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7690 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7691 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7692 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7693 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7694 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7695 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7696 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7697 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7698 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7699 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7701 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7702 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7703 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7704 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7706 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7707 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7708 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7709 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7710 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7711 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7712 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7713 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7714 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7717 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7718 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7719 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7721 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7722 c
, opc
->name
, opc
->args
);
7726 if (used_bits
!= 0xffffffff)
7728 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7729 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7735 /* This routine assembles an instruction into its binary format. As a
7736 side effect, it sets one of the global variables imm_reloc or
7737 offset_reloc to the type of relocation to do if one of the operands
7738 is an address expression. */
7743 struct mips_cl_insn
*ip
;
7748 struct mips_opcode
*insn
;
7751 unsigned int lastregno
= 0;
7757 /* If the instruction contains a '.', we first try to match an instruction
7758 including the '.'. Then we try again without the '.'. */
7760 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7763 /* If we stopped on whitespace, then replace the whitespace with null for
7764 the call to hash_find. Save the character we replaced just in case we
7765 have to re-parse the instruction. */
7772 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7774 /* If we didn't find the instruction in the opcode table, try again, but
7775 this time with just the instruction up to, but not including the
7779 /* Restore the character we overwrite above (if any). */
7783 /* Scan up to the first '.' or whitespace. */
7785 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7789 /* If we did not find a '.', then we can quit now. */
7792 insn_error
= "unrecognized opcode";
7796 /* Lookup the instruction in the hash table. */
7798 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7800 insn_error
= "unrecognized opcode";
7810 assert (strcmp (insn
->name
, str
) == 0);
7812 if (OPCODE_IS_MEMBER (insn
,
7814 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
7815 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7816 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7822 if (insn
->pinfo
!= INSN_MACRO
)
7824 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7830 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7831 && strcmp (insn
->name
, insn
[1].name
) == 0)
7840 static char buf
[100];
7841 if (mips_arch_info
->is_isa
)
7843 _("opcode not supported at this ISA level (%s)"),
7844 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7847 _("opcode not supported on this processor: %s (%s)"),
7848 mips_arch_info
->name
,
7849 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7859 ip
->insn_opcode
= insn
->match
;
7861 for (args
= insn
->args
;; ++args
)
7865 s
+= strspn (s
, " \t");
7869 case '\0': /* end of args */
7882 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7886 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7890 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7894 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7900 /* Handle optional base register.
7901 Either the base register is omitted or
7902 we must have a left paren. */
7903 /* This is dependent on the next operand specifier
7904 is a base register specification. */
7905 assert (args
[1] == 'b' || args
[1] == '5'
7906 || args
[1] == '-' || args
[1] == '4');
7910 case ')': /* these must match exactly */
7915 case '<': /* must be at least one digit */
7917 * According to the manual, if the shift amount is greater
7918 * than 31 or less than 0, then the shift amount should be
7919 * mod 32. In reality the mips assembler issues an error.
7920 * We issue a warning and mask out all but the low 5 bits.
7922 my_getExpression (&imm_expr
, s
);
7923 check_absolute_expr (ip
, &imm_expr
);
7924 if ((unsigned long) imm_expr
.X_add_number
> 31)
7926 as_warn (_("Improper shift amount (%lu)"),
7927 (unsigned long) imm_expr
.X_add_number
);
7928 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7930 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7931 imm_expr
.X_op
= O_absent
;
7935 case '>': /* shift amount minus 32 */
7936 my_getExpression (&imm_expr
, s
);
7937 check_absolute_expr (ip
, &imm_expr
);
7938 if ((unsigned long) imm_expr
.X_add_number
< 32
7939 || (unsigned long) imm_expr
.X_add_number
> 63)
7941 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7942 imm_expr
.X_op
= O_absent
;
7946 case 'k': /* cache code */
7947 case 'h': /* prefx code */
7948 my_getExpression (&imm_expr
, s
);
7949 check_absolute_expr (ip
, &imm_expr
);
7950 if ((unsigned long) imm_expr
.X_add_number
> 31)
7952 as_warn (_("Invalid value for `%s' (%lu)"),
7954 (unsigned long) imm_expr
.X_add_number
);
7955 imm_expr
.X_add_number
&= 0x1f;
7958 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7960 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7961 imm_expr
.X_op
= O_absent
;
7965 case 'c': /* break code */
7966 my_getExpression (&imm_expr
, s
);
7967 check_absolute_expr (ip
, &imm_expr
);
7968 if ((unsigned long) imm_expr
.X_add_number
> 1023)
7970 as_warn (_("Illegal break code (%lu)"),
7971 (unsigned long) imm_expr
.X_add_number
);
7972 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7974 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7975 imm_expr
.X_op
= O_absent
;
7979 case 'q': /* lower break code */
7980 my_getExpression (&imm_expr
, s
);
7981 check_absolute_expr (ip
, &imm_expr
);
7982 if ((unsigned long) imm_expr
.X_add_number
> 1023)
7984 as_warn (_("Illegal lower break code (%lu)"),
7985 (unsigned long) imm_expr
.X_add_number
);
7986 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7988 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7989 imm_expr
.X_op
= O_absent
;
7993 case 'B': /* 20-bit syscall/break code. */
7994 my_getExpression (&imm_expr
, s
);
7995 check_absolute_expr (ip
, &imm_expr
);
7996 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7997 as_warn (_("Illegal 20-bit code (%lu)"),
7998 (unsigned long) imm_expr
.X_add_number
);
7999 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8000 imm_expr
.X_op
= O_absent
;
8004 case 'C': /* Coprocessor code */
8005 my_getExpression (&imm_expr
, s
);
8006 check_absolute_expr (ip
, &imm_expr
);
8007 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8009 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8010 (unsigned long) imm_expr
.X_add_number
);
8011 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8013 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8014 imm_expr
.X_op
= O_absent
;
8018 case 'J': /* 19-bit wait code. */
8019 my_getExpression (&imm_expr
, s
);
8020 check_absolute_expr (ip
, &imm_expr
);
8021 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8022 as_warn (_("Illegal 19-bit code (%lu)"),
8023 (unsigned long) imm_expr
.X_add_number
);
8024 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8025 imm_expr
.X_op
= O_absent
;
8029 case 'P': /* Performance register */
8030 my_getExpression (&imm_expr
, s
);
8031 check_absolute_expr (ip
, &imm_expr
);
8032 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8034 as_warn (_("Invalid performance register (%lu)"),
8035 (unsigned long) imm_expr
.X_add_number
);
8036 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8038 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8039 imm_expr
.X_op
= O_absent
;
8043 case 'b': /* base register */
8044 case 'd': /* destination register */
8045 case 's': /* source register */
8046 case 't': /* target register */
8047 case 'r': /* both target and source */
8048 case 'v': /* both dest and source */
8049 case 'w': /* both dest and target */
8050 case 'E': /* coprocessor target register */
8051 case 'G': /* coprocessor destination register */
8052 case 'x': /* ignore register name */
8053 case 'z': /* must be zero register */
8054 case 'U': /* destination register (clo/clz). */
8069 while (ISDIGIT (*s
));
8071 as_bad (_("Invalid register number (%d)"), regno
);
8073 else if (*args
== 'E' || *args
== 'G')
8077 if (s
[1] == 'r' && s
[2] == 'a')
8082 else if (s
[1] == 'f' && s
[2] == 'p')
8087 else if (s
[1] == 's' && s
[2] == 'p')
8092 else if (s
[1] == 'g' && s
[2] == 'p')
8097 else if (s
[1] == 'a' && s
[2] == 't')
8102 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8107 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8112 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8117 else if (itbl_have_entries
)
8122 p
= s
+ 1; /* advance past '$' */
8123 n
= itbl_get_field (&p
); /* n is name */
8125 /* See if this is a register defined in an
8127 if (itbl_get_reg_val (n
, &r
))
8129 /* Get_field advances to the start of
8130 the next field, so we need to back
8131 rack to the end of the last field. */
8135 s
= strchr (s
, '\0');
8148 as_warn (_("Used $at without \".set noat\""));
8154 if (c
== 'r' || c
== 'v' || c
== 'w')
8161 /* 'z' only matches $0. */
8162 if (c
== 'z' && regno
!= 0)
8165 /* Now that we have assembled one operand, we use the args string
8166 * to figure out where it goes in the instruction. */
8173 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8177 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8180 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8181 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8186 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8189 /* This case exists because on the r3000 trunc
8190 expands into a macro which requires a gp
8191 register. On the r6000 or r4000 it is
8192 assembled into a single instruction which
8193 ignores the register. Thus the insn version
8194 is MIPS_ISA2 and uses 'x', and the macro
8195 version is MIPS_ISA1 and uses 't'. */
8198 /* This case is for the div instruction, which
8199 acts differently if the destination argument
8200 is $0. This only matches $0, and is checked
8201 outside the switch. */
8204 /* Itbl operand; not yet implemented. FIXME ?? */
8206 /* What about all other operands like 'i', which
8207 can be specified in the opcode table? */
8217 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8220 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8225 case 'O': /* MDMX alignment immediate constant. */
8226 my_getExpression (&imm_expr
, s
);
8227 check_absolute_expr (ip
, &imm_expr
);
8228 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8230 as_warn ("Improper align amount (%ld), using low bits",
8231 (long) imm_expr
.X_add_number
);
8232 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8234 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8235 imm_expr
.X_op
= O_absent
;
8239 case 'Q': /* MDMX vector, element sel, or const. */
8242 /* MDMX Immediate. */
8243 my_getExpression (&imm_expr
, s
);
8244 check_absolute_expr (ip
, &imm_expr
);
8245 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8247 as_warn (_("Invalid MDMX Immediate (%ld)"),
8248 (long) imm_expr
.X_add_number
);
8249 imm_expr
.X_add_number
&= OP_MASK_FT
;
8251 imm_expr
.X_add_number
&= OP_MASK_FT
;
8252 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8253 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8255 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8256 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8257 imm_expr
.X_op
= O_absent
;
8261 /* Not MDMX Immediate. Fall through. */
8262 case 'X': /* MDMX destination register. */
8263 case 'Y': /* MDMX source register. */
8264 case 'Z': /* MDMX target register. */
8266 case 'D': /* floating point destination register */
8267 case 'S': /* floating point source register */
8268 case 'T': /* floating point target register */
8269 case 'R': /* floating point source register */
8273 /* Accept $fN for FP and MDMX register numbers, and in
8274 addition accept $vN for MDMX register numbers. */
8275 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8276 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8287 while (ISDIGIT (*s
));
8290 as_bad (_("Invalid float register number (%d)"), regno
);
8292 if ((regno
& 1) != 0
8294 && ! (strcmp (str
, "mtc1") == 0
8295 || strcmp (str
, "mfc1") == 0
8296 || strcmp (str
, "lwc1") == 0
8297 || strcmp (str
, "swc1") == 0
8298 || strcmp (str
, "l.s") == 0
8299 || strcmp (str
, "s.s") == 0))
8300 as_warn (_("Float register should be even, was %d"),
8308 if (c
== 'V' || c
== 'W')
8319 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8324 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8327 /* This is like 'Z', but also needs to fix the MDMX
8328 vector/scalar select bits. Note that the
8329 scalar immediate case is handled above. */
8332 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8333 int max_el
= (is_qh
? 3 : 7);
8335 my_getExpression(&imm_expr
, s
);
8336 check_absolute_expr (ip
, &imm_expr
);
8338 if (imm_expr
.X_add_number
> max_el
)
8339 as_bad(_("Bad element selector %ld"),
8340 (long) imm_expr
.X_add_number
);
8341 imm_expr
.X_add_number
&= max_el
;
8342 ip
->insn_opcode
|= (imm_expr
.X_add_number
8346 as_warn(_("Expecting ']' found '%s'"), s
);
8352 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8353 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8356 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8363 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8366 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8376 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8379 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8385 my_getExpression (&imm_expr
, s
);
8386 if (imm_expr
.X_op
!= O_big
8387 && imm_expr
.X_op
!= O_constant
)
8388 insn_error
= _("absolute expression required");
8393 my_getExpression (&offset_expr
, s
);
8394 *imm_reloc
= BFD_RELOC_32
;
8407 unsigned char temp
[8];
8409 unsigned int length
;
8414 /* These only appear as the last operand in an
8415 instruction, and every instruction that accepts
8416 them in any variant accepts them in all variants.
8417 This means we don't have to worry about backing out
8418 any changes if the instruction does not match.
8420 The difference between them is the size of the
8421 floating point constant and where it goes. For 'F'
8422 and 'L' the constant is 64 bits; for 'f' and 'l' it
8423 is 32 bits. Where the constant is placed is based
8424 on how the MIPS assembler does things:
8427 f -- immediate value
8430 The .lit4 and .lit8 sections are only used if
8431 permitted by the -G argument.
8433 When generating embedded PIC code, we use the
8434 .lit8 section but not the .lit4 section (we can do
8435 .lit4 inline easily; we need to put .lit8
8436 somewhere in the data segment, and using .lit8
8437 permits the linker to eventually combine identical
8440 The code below needs to know whether the target register
8441 is 32 or 64 bits wide. It relies on the fact 'f' and
8442 'F' are used with GPR-based instructions and 'l' and
8443 'L' are used with FPR-based instructions. */
8445 f64
= *args
== 'F' || *args
== 'L';
8446 using_gprs
= *args
== 'F' || *args
== 'f';
8448 save_in
= input_line_pointer
;
8449 input_line_pointer
= s
;
8450 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8452 s
= input_line_pointer
;
8453 input_line_pointer
= save_in
;
8454 if (err
!= NULL
&& *err
!= '\0')
8456 as_bad (_("Bad floating point constant: %s"), err
);
8457 memset (temp
, '\0', sizeof temp
);
8458 length
= f64
? 8 : 4;
8461 assert (length
== (unsigned) (f64
? 8 : 4));
8465 && (! USE_GLOBAL_POINTER_OPT
8466 || mips_pic
== EMBEDDED_PIC
8467 || g_switch_value
< 4
8468 || (temp
[0] == 0 && temp
[1] == 0)
8469 || (temp
[2] == 0 && temp
[3] == 0))))
8471 imm_expr
.X_op
= O_constant
;
8472 if (! target_big_endian
)
8473 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8475 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8478 && ! mips_disable_float_construction
8479 /* Constants can only be constructed in GPRs and
8480 copied to FPRs if the GPRs are at least as wide
8481 as the FPRs. Force the constant into memory if
8482 we are using 64-bit FPRs but the GPRs are only
8485 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8486 && ((temp
[0] == 0 && temp
[1] == 0)
8487 || (temp
[2] == 0 && temp
[3] == 0))
8488 && ((temp
[4] == 0 && temp
[5] == 0)
8489 || (temp
[6] == 0 && temp
[7] == 0)))
8491 /* The value is simple enough to load with a couple of
8492 instructions. If using 32-bit registers, set
8493 imm_expr to the high order 32 bits and offset_expr to
8494 the low order 32 bits. Otherwise, set imm_expr to
8495 the entire 64 bit constant. */
8496 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8498 imm_expr
.X_op
= O_constant
;
8499 offset_expr
.X_op
= O_constant
;
8500 if (! target_big_endian
)
8502 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8503 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8507 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8508 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8510 if (offset_expr
.X_add_number
== 0)
8511 offset_expr
.X_op
= O_absent
;
8513 else if (sizeof (imm_expr
.X_add_number
) > 4)
8515 imm_expr
.X_op
= O_constant
;
8516 if (! target_big_endian
)
8517 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8519 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8523 imm_expr
.X_op
= O_big
;
8524 imm_expr
.X_add_number
= 4;
8525 if (! target_big_endian
)
8527 generic_bignum
[0] = bfd_getl16 (temp
);
8528 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8529 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8530 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8534 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8535 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8536 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8537 generic_bignum
[3] = bfd_getb16 (temp
);
8543 const char *newname
;
8546 /* Switch to the right section. */
8548 subseg
= now_subseg
;
8551 default: /* unused default case avoids warnings. */
8553 newname
= RDATA_SECTION_NAME
;
8554 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8555 || mips_pic
== EMBEDDED_PIC
)
8559 if (mips_pic
== EMBEDDED_PIC
)
8562 newname
= RDATA_SECTION_NAME
;
8565 assert (!USE_GLOBAL_POINTER_OPT
8566 || g_switch_value
>= 4);
8570 new_seg
= subseg_new (newname
, (subsegT
) 0);
8571 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8572 bfd_set_section_flags (stdoutput
, new_seg
,
8577 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8578 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8579 && strcmp (TARGET_OS
, "elf") != 0)
8580 record_alignment (new_seg
, 4);
8582 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8584 as_bad (_("Can't use floating point insn in this section"));
8586 /* Set the argument to the current address in the
8588 offset_expr
.X_op
= O_symbol
;
8589 offset_expr
.X_add_symbol
=
8590 symbol_new ("L0\001", now_seg
,
8591 (valueT
) frag_now_fix (), frag_now
);
8592 offset_expr
.X_add_number
= 0;
8594 /* Put the floating point number into the section. */
8595 p
= frag_more ((int) length
);
8596 memcpy (p
, temp
, length
);
8598 /* Switch back to the original section. */
8599 subseg_set (seg
, subseg
);
8604 case 'i': /* 16 bit unsigned immediate */
8605 case 'j': /* 16 bit signed immediate */
8606 *imm_reloc
= BFD_RELOC_LO16
;
8607 c
= my_getSmallExpression (&imm_expr
, s
);
8614 *imm_reloc
= BFD_RELOC_HI16_S
;
8615 imm_unmatched_hi
= true;
8618 else if (c
== S_EX_HIGHEST
)
8619 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8620 else if (c
== S_EX_HIGHER
)
8621 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8622 else if (c
== S_EX_GP_REL
)
8624 /* This occurs in NewABI only. */
8625 c
= my_getSmallExpression (&imm_expr
, s
);
8627 as_bad (_("bad composition of relocations"));
8630 c
= my_getSmallExpression (&imm_expr
, s
);
8632 as_bad (_("bad composition of relocations"));
8635 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8636 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8637 imm_reloc
[2] = BFD_RELOC_LO16
;
8643 *imm_reloc
= BFD_RELOC_HI16
;
8645 else if (imm_expr
.X_op
== O_constant
)
8646 imm_expr
.X_add_number
&= 0xffff;
8650 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8651 || ((imm_expr
.X_add_number
< 0
8652 || imm_expr
.X_add_number
>= 0x10000)
8653 && imm_expr
.X_op
== O_constant
))
8655 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8656 !strcmp (insn
->name
, insn
[1].name
))
8658 if (imm_expr
.X_op
== O_constant
8659 || imm_expr
.X_op
== O_big
)
8660 as_bad (_("16 bit expression not in range 0..65535"));
8668 /* The upper bound should be 0x8000, but
8669 unfortunately the MIPS assembler accepts numbers
8670 from 0x8000 to 0xffff and sign extends them, and
8671 we want to be compatible. We only permit this
8672 extended range for an instruction which does not
8673 provide any further alternates, since those
8674 alternates may handle other cases. People should
8675 use the numbers they mean, rather than relying on
8676 a mysterious sign extension. */
8677 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8678 strcmp (insn
->name
, insn
[1].name
) == 0);
8683 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8684 || ((imm_expr
.X_add_number
< -0x8000
8685 || imm_expr
.X_add_number
>= max
)
8686 && imm_expr
.X_op
== O_constant
)
8688 && imm_expr
.X_add_number
< 0
8690 && imm_expr
.X_unsigned
8691 && sizeof (imm_expr
.X_add_number
) <= 4))
8695 if (imm_expr
.X_op
== O_constant
8696 || imm_expr
.X_op
== O_big
)
8697 as_bad (_("16 bit expression not in range -32768..32767"));
8703 case 'o': /* 16 bit offset */
8704 c
= my_getSmallExpression (&offset_expr
, s
);
8706 /* If this value won't fit into a 16 bit offset, then go
8707 find a macro that will generate the 32 bit offset
8710 && (offset_expr
.X_op
!= O_constant
8711 || offset_expr
.X_add_number
>= 0x8000
8712 || offset_expr
.X_add_number
< -0x8000))
8717 if (offset_expr
.X_op
!= O_constant
)
8719 offset_expr
.X_add_number
=
8720 (offset_expr
.X_add_number
>> 16) & 0xffff;
8722 *offset_reloc
= BFD_RELOC_LO16
;
8726 case 'p': /* pc relative offset */
8727 if (mips_pic
== EMBEDDED_PIC
)
8728 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8730 *offset_reloc
= BFD_RELOC_16_PCREL
;
8731 my_getExpression (&offset_expr
, s
);
8735 case 'u': /* upper 16 bits */
8736 c
= my_getSmallExpression (&imm_expr
, s
);
8737 *imm_reloc
= BFD_RELOC_LO16
;
8744 *imm_reloc
= BFD_RELOC_HI16_S
;
8745 imm_unmatched_hi
= true;
8748 else if (c
== S_EX_HIGHEST
)
8749 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8750 else if (c
== S_EX_GP_REL
)
8752 /* This occurs in NewABI only. */
8753 c
= my_getSmallExpression (&imm_expr
, s
);
8755 as_bad (_("bad composition of relocations"));
8758 c
= my_getSmallExpression (&imm_expr
, s
);
8760 as_bad (_("bad composition of relocations"));
8763 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8764 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8765 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8771 *imm_reloc
= BFD_RELOC_HI16
;
8773 else if (imm_expr
.X_op
== O_constant
)
8774 imm_expr
.X_add_number
&= 0xffff;
8776 else if (imm_expr
.X_op
== O_constant
8777 && (imm_expr
.X_add_number
< 0
8778 || imm_expr
.X_add_number
>= 0x10000))
8779 as_bad (_("lui expression not in range 0..65535"));
8783 case 'a': /* 26 bit address */
8784 my_getExpression (&offset_expr
, s
);
8786 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8789 case 'N': /* 3 bit branch condition code */
8790 case 'M': /* 3 bit compare condition code */
8791 if (strncmp (s
, "$fcc", 4) != 0)
8801 while (ISDIGIT (*s
));
8803 as_bad (_("invalid condition code register $fcc%d"), regno
);
8805 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8807 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8811 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8822 while (ISDIGIT (*s
));
8825 c
= 8; /* Invalid sel value. */
8828 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8829 ip
->insn_opcode
|= c
;
8833 as_bad (_("bad char = '%c'\n"), *args
);
8838 /* Args don't match. */
8839 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8840 !strcmp (insn
->name
, insn
[1].name
))
8844 insn_error
= _("illegal operands");
8849 insn_error
= _("illegal operands");
8854 /* This routine assembles an instruction into its binary format when
8855 assembling for the mips16. As a side effect, it sets one of the
8856 global variables imm_reloc or offset_reloc to the type of
8857 relocation to do if one of the operands is an address expression.
8858 It also sets mips16_small and mips16_ext if the user explicitly
8859 requested a small or extended instruction. */
8864 struct mips_cl_insn
*ip
;
8868 struct mips_opcode
*insn
;
8871 unsigned int lastregno
= 0;
8876 mips16_small
= false;
8879 for (s
= str
; ISLOWER (*s
); ++s
)
8891 if (s
[1] == 't' && s
[2] == ' ')
8894 mips16_small
= true;
8898 else if (s
[1] == 'e' && s
[2] == ' ')
8907 insn_error
= _("unknown opcode");
8911 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8912 mips16_small
= true;
8914 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8916 insn_error
= _("unrecognized opcode");
8923 assert (strcmp (insn
->name
, str
) == 0);
8926 ip
->insn_opcode
= insn
->match
;
8927 ip
->use_extend
= false;
8928 imm_expr
.X_op
= O_absent
;
8929 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8930 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8931 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8932 offset_expr
.X_op
= O_absent
;
8933 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8934 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8935 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8936 for (args
= insn
->args
; 1; ++args
)
8943 /* In this switch statement we call break if we did not find
8944 a match, continue if we did find a match, or return if we
8953 /* Stuff the immediate value in now, if we can. */
8954 if (imm_expr
.X_op
== O_constant
8955 && *imm_reloc
> BFD_RELOC_UNUSED
8956 && insn
->pinfo
!= INSN_MACRO
)
8958 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8959 imm_expr
.X_add_number
, true, mips16_small
,
8960 mips16_ext
, &ip
->insn_opcode
,
8961 &ip
->use_extend
, &ip
->extend
);
8962 imm_expr
.X_op
= O_absent
;
8963 *imm_reloc
= BFD_RELOC_UNUSED
;
8977 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8980 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8996 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8998 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9025 while (ISDIGIT (*s
));
9028 as_bad (_("invalid register number (%d)"), regno
);
9034 if (s
[1] == 'r' && s
[2] == 'a')
9039 else if (s
[1] == 'f' && s
[2] == 'p')
9044 else if (s
[1] == 's' && s
[2] == 'p')
9049 else if (s
[1] == 'g' && s
[2] == 'p')
9054 else if (s
[1] == 'a' && s
[2] == 't')
9059 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9064 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9069 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9082 if (c
== 'v' || c
== 'w')
9084 regno
= mips16_to_32_reg_map
[lastregno
];
9098 regno
= mips32_to_16_reg_map
[regno
];
9103 regno
= ILLEGAL_REG
;
9108 regno
= ILLEGAL_REG
;
9113 regno
= ILLEGAL_REG
;
9118 if (regno
== AT
&& ! mips_opts
.noat
)
9119 as_warn (_("used $at without \".set noat\""));
9126 if (regno
== ILLEGAL_REG
)
9133 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9137 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9140 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9143 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9149 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9152 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9153 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9163 if (strncmp (s
, "$pc", 3) == 0)
9187 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9189 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9190 and generate the appropriate reloc. If the text
9191 inside %gprel is not a symbol name with an
9192 optional offset, then we generate a normal reloc
9193 and will probably fail later. */
9194 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9195 if (imm_expr
.X_op
== O_symbol
)
9198 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9200 ip
->use_extend
= true;
9207 /* Just pick up a normal expression. */
9208 my_getExpression (&imm_expr
, s
);
9211 if (imm_expr
.X_op
== O_register
)
9213 /* What we thought was an expression turned out to
9216 if (s
[0] == '(' && args
[1] == '(')
9218 /* It looks like the expression was omitted
9219 before a register indirection, which means
9220 that the expression is implicitly zero. We
9221 still set up imm_expr, so that we handle
9222 explicit extensions correctly. */
9223 imm_expr
.X_op
= O_constant
;
9224 imm_expr
.X_add_number
= 0;
9225 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9232 /* We need to relax this instruction. */
9233 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9242 /* We use offset_reloc rather than imm_reloc for the PC
9243 relative operands. This lets macros with both
9244 immediate and address operands work correctly. */
9245 my_getExpression (&offset_expr
, s
);
9247 if (offset_expr
.X_op
== O_register
)
9250 /* We need to relax this instruction. */
9251 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9255 case '6': /* break code */
9256 my_getExpression (&imm_expr
, s
);
9257 check_absolute_expr (ip
, &imm_expr
);
9258 if ((unsigned long) imm_expr
.X_add_number
> 63)
9260 as_warn (_("Invalid value for `%s' (%lu)"),
9262 (unsigned long) imm_expr
.X_add_number
);
9263 imm_expr
.X_add_number
&= 0x3f;
9265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9266 imm_expr
.X_op
= O_absent
;
9270 case 'a': /* 26 bit address */
9271 my_getExpression (&offset_expr
, s
);
9273 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9274 ip
->insn_opcode
<<= 16;
9277 case 'l': /* register list for entry macro */
9278 case 'L': /* register list for exit macro */
9288 int freg
, reg1
, reg2
;
9290 while (*s
== ' ' || *s
== ',')
9294 as_bad (_("can't parse register list"));
9306 while (ISDIGIT (*s
))
9328 as_bad (_("invalid register list"));
9333 while (ISDIGIT (*s
))
9340 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9345 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9350 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9351 mask
|= (reg2
- 3) << 3;
9352 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9353 mask
|= (reg2
- 15) << 1;
9354 else if (reg1
== RA
&& reg2
== RA
)
9358 as_bad (_("invalid register list"));
9362 /* The mask is filled in in the opcode table for the
9363 benefit of the disassembler. We remove it before
9364 applying the actual mask. */
9365 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9366 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9370 case 'e': /* extend code */
9371 my_getExpression (&imm_expr
, s
);
9372 check_absolute_expr (ip
, &imm_expr
);
9373 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9375 as_warn (_("Invalid value for `%s' (%lu)"),
9377 (unsigned long) imm_expr
.X_add_number
);
9378 imm_expr
.X_add_number
&= 0x7ff;
9380 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9381 imm_expr
.X_op
= O_absent
;
9391 /* Args don't match. */
9392 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9393 strcmp (insn
->name
, insn
[1].name
) == 0)
9400 insn_error
= _("illegal operands");
9406 /* This structure holds information we know about a mips16 immediate
9409 struct mips16_immed_operand
9411 /* The type code used in the argument string in the opcode table. */
9413 /* The number of bits in the short form of the opcode. */
9415 /* The number of bits in the extended form of the opcode. */
9417 /* The amount by which the short form is shifted when it is used;
9418 for example, the sw instruction has a shift count of 2. */
9420 /* The amount by which the short form is shifted when it is stored
9421 into the instruction code. */
9423 /* Non-zero if the short form is unsigned. */
9425 /* Non-zero if the extended form is unsigned. */
9427 /* Non-zero if the value is PC relative. */
9431 /* The mips16 immediate operand types. */
9433 static const struct mips16_immed_operand mips16_immed_operands
[] =
9435 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9436 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9437 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9438 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9439 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9440 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9441 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9442 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9443 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9444 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9445 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9446 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9447 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9448 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9449 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9450 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9451 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9452 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9453 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9454 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9455 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9458 #define MIPS16_NUM_IMMED \
9459 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9461 /* Handle a mips16 instruction with an immediate value. This or's the
9462 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9463 whether an extended value is needed; if one is needed, it sets
9464 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9465 If SMALL is true, an unextended opcode was explicitly requested.
9466 If EXT is true, an extended opcode was explicitly requested. If
9467 WARN is true, warn if EXT does not match reality. */
9470 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9479 unsigned long *insn
;
9480 boolean
*use_extend
;
9481 unsigned short *extend
;
9483 register const struct mips16_immed_operand
*op
;
9484 int mintiny
, maxtiny
;
9487 op
= mips16_immed_operands
;
9488 while (op
->type
!= type
)
9491 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9496 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9499 maxtiny
= 1 << op
->nbits
;
9504 maxtiny
= (1 << op
->nbits
) - 1;
9509 mintiny
= - (1 << (op
->nbits
- 1));
9510 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9513 /* Branch offsets have an implicit 0 in the lowest bit. */
9514 if (type
== 'p' || type
== 'q')
9517 if ((val
& ((1 << op
->shift
) - 1)) != 0
9518 || val
< (mintiny
<< op
->shift
)
9519 || val
> (maxtiny
<< op
->shift
))
9524 if (warn
&& ext
&& ! needext
)
9525 as_warn_where (file
, line
,
9526 _("extended operand requested but not required"));
9527 if (small
&& needext
)
9528 as_bad_where (file
, line
, _("invalid unextended operand value"));
9530 if (small
|| (! ext
&& ! needext
))
9534 *use_extend
= false;
9535 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9536 insnval
<<= op
->op_shift
;
9541 long minext
, maxext
;
9547 maxext
= (1 << op
->extbits
) - 1;
9551 minext
= - (1 << (op
->extbits
- 1));
9552 maxext
= (1 << (op
->extbits
- 1)) - 1;
9554 if (val
< minext
|| val
> maxext
)
9555 as_bad_where (file
, line
,
9556 _("operand value out of range for instruction"));
9559 if (op
->extbits
== 16)
9561 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9564 else if (op
->extbits
== 15)
9566 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9571 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9575 *extend
= (unsigned short) extval
;
9580 static struct percent_op_match
9583 const enum small_ex_type type
;
9588 {"%call_hi", S_EX_CALL_HI
},
9589 {"%call_lo", S_EX_CALL_LO
},
9590 {"%call16", S_EX_CALL16
},
9591 {"%got_disp", S_EX_GOT_DISP
},
9592 {"%got_page", S_EX_GOT_PAGE
},
9593 {"%got_ofst", S_EX_GOT_OFST
},
9594 {"%got_hi", S_EX_GOT_HI
},
9595 {"%got_lo", S_EX_GOT_LO
},
9597 {"%gp_rel", S_EX_GP_REL
},
9598 {"%half", S_EX_HALF
},
9599 {"%highest", S_EX_HIGHEST
},
9600 {"%higher", S_EX_HIGHER
},
9606 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9607 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9608 can be nested, this is handled by blanking the innermost, parsing the
9609 rest by subsequent calls. */
9612 my_getSmallParser (str
, len
, nestlevel
)
9618 *str
+= strspn (*str
, " \t");
9619 /* Check for expression in parentheses. */
9622 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9625 /* Check for base register. */
9629 && (e
= b
+ strcspn (b
, ") \t"))
9630 && e
- b
> 1 && e
- b
< 4)
9633 && ((b
[1] == 'f' && b
[2] == 'p')
9634 || (b
[1] == 's' && b
[2] == 'p')
9635 || (b
[1] == 'g' && b
[2] == 'p')
9636 || (b
[1] == 'a' && b
[2] == 't')
9638 && ISDIGIT (b
[2]))))
9639 || (ISDIGIT (b
[1])))
9641 *len
= strcspn (*str
, ")") + 1;
9642 return S_EX_REGISTER
;
9646 /* Check for percent_op (in parentheses). */
9647 else if (b
[0] == '%')
9650 return my_getPercentOp (str
, len
, nestlevel
);
9653 /* Some other expression in the parentheses, which can contain
9654 parentheses itself. Attempt to find the matching one. */
9660 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9669 /* Check for percent_op (outside of parentheses). */
9670 else if (*str
[0] == '%')
9671 return my_getPercentOp (str
, len
, nestlevel
);
9673 /* Any other expression. */
9678 my_getPercentOp (str
, len
, nestlevel
)
9683 char *tmp
= *str
+ 1;
9686 while (ISALPHA (*tmp
) || *tmp
== '_')
9688 *tmp
= TOLOWER (*tmp
);
9691 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9693 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9697 int type
= percent_op
[i
].type
;
9699 /* Only %hi and %lo are allowed for OldABI. */
9700 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9703 *len
= strlen (percent_op
[i
].str
);
9712 my_getSmallExpression (ep
, str
)
9716 static char *oldstr
= NULL
;
9722 /* Don't update oldstr if the last call had nested percent_op's. We need
9723 it to parse the outer ones later. */
9730 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9731 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9734 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9738 /* A percent_op was encountered. Don't try to get an expression if
9739 it is already blanked out. */
9740 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9744 /* Let my_getExpression() stop at the closing parenthesis. */
9745 save
= *(str
+ len
);
9746 *(str
+ len
) = '\0';
9747 my_getExpression (ep
, str
);
9748 *(str
+ len
) = save
;
9752 /* Blank out including the % sign and the proper matching
9755 char *s
= strrchr (oldstr
, '%');
9758 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9762 else if (*end
== ')')
9766 memset (s
, ' ', end
- s
);
9770 expr_end
= str
+ len
;
9774 else if (c
== S_EX_NONE
)
9776 my_getExpression (ep
, str
);
9778 else if (c
== S_EX_REGISTER
)
9780 ep
->X_op
= O_constant
;
9782 ep
->X_add_symbol
= NULL
;
9783 ep
->X_op_symbol
= NULL
;
9784 ep
->X_add_number
= 0;
9788 as_fatal (_("internal error"));
9792 /* All percent_op's have been handled. */
9799 my_getExpression (ep
, str
)
9806 save_in
= input_line_pointer
;
9807 input_line_pointer
= str
;
9809 expr_end
= input_line_pointer
;
9810 input_line_pointer
= save_in
;
9812 /* If we are in mips16 mode, and this is an expression based on `.',
9813 then we bump the value of the symbol by 1 since that is how other
9814 text symbols are handled. We don't bother to handle complex
9815 expressions, just `.' plus or minus a constant. */
9816 if (mips_opts
.mips16
9817 && ep
->X_op
== O_symbol
9818 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9819 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9820 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9821 && symbol_constant_p (ep
->X_add_symbol
)
9822 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9823 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9826 /* Turn a string in input_line_pointer into a floating point constant
9827 of type TYPE, and store the appropriate bytes in *LITP. The number
9828 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9829 returned, or NULL on OK. */
9832 md_atof (type
, litP
, sizeP
)
9838 LITTLENUM_TYPE words
[4];
9854 return _("bad call to md_atof");
9857 t
= atof_ieee (input_line_pointer
, type
, words
);
9859 input_line_pointer
= t
;
9863 if (! target_big_endian
)
9865 for (i
= prec
- 1; i
>= 0; i
--)
9867 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9873 for (i
= 0; i
< prec
; i
++)
9875 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9884 md_number_to_chars (buf
, val
, n
)
9889 if (target_big_endian
)
9890 number_to_chars_bigendian (buf
, val
, n
);
9892 number_to_chars_littleendian (buf
, val
, n
);
9896 static int support_64bit_objects(void)
9898 const char **list
, **l
;
9900 list
= bfd_target_list ();
9901 for (l
= list
; *l
!= NULL
; l
++)
9903 /* This is traditional mips */
9904 if (strcmp (*l
, "elf64-tradbigmips") == 0
9905 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9907 if (strcmp (*l
, "elf64-bigmips") == 0
9908 || strcmp (*l
, "elf64-littlemips") == 0)
9912 return (*l
!= NULL
);
9914 #endif /* OBJ_ELF */
9916 const char *md_shortopts
= "nO::g::G:";
9918 struct option md_longopts
[] =
9920 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9921 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9922 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9923 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9924 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9925 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9926 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9927 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9928 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9929 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9930 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9931 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9932 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9933 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9934 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9935 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9936 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9937 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9938 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9939 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9940 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9941 {"break", no_argument
, NULL
, OPTION_BREAK
},
9942 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9943 #define OPTION_EB (OPTION_MD_BASE + 11)
9944 {"EB", no_argument
, NULL
, OPTION_EB
},
9945 #define OPTION_EL (OPTION_MD_BASE + 12)
9946 {"EL", no_argument
, NULL
, OPTION_EL
},
9947 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9948 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9949 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9950 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9951 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9952 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9953 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9954 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9955 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9956 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9957 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9958 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9959 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9960 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9961 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9962 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9963 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9964 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9965 {"march", required_argument
, NULL
, OPTION_MARCH
},
9966 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9967 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9968 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9969 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
9970 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9971 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9972 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9973 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9974 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9975 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9976 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9977 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9978 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9979 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9980 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9981 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9982 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9983 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9984 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9985 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9986 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9987 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9988 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9989 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9990 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9991 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9992 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9993 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9994 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9995 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9997 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9998 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9999 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10000 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10001 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10002 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10003 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10004 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10005 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10006 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10007 #define OPTION_32 (OPTION_ELF_BASE + 4)
10008 {"32", no_argument
, NULL
, OPTION_32
},
10009 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10010 {"n32", no_argument
, NULL
, OPTION_N32
},
10011 #define OPTION_64 (OPTION_ELF_BASE + 6)
10012 {"64", no_argument
, NULL
, OPTION_64
},
10013 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10014 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10015 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10016 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10017 #endif /* OBJ_ELF */
10018 {NULL
, no_argument
, NULL
, 0}
10020 size_t md_longopts_size
= sizeof (md_longopts
);
10022 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10023 NEW_VALUE. Warn if another value was already specified. Note:
10024 we have to defer parsing the -march and -mtune arguments in order
10025 to handle 'from-abi' correctly, since the ABI might be specified
10026 in a later argument. */
10029 mips_set_option_string (string_ptr
, new_value
)
10030 const char **string_ptr
, *new_value
;
10032 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10033 as_warn (_("A different %s was already specified, is now %s"),
10034 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10037 *string_ptr
= new_value
;
10041 md_parse_option (c
, arg
)
10047 case OPTION_CONSTRUCT_FLOATS
:
10048 mips_disable_float_construction
= 0;
10051 case OPTION_NO_CONSTRUCT_FLOATS
:
10052 mips_disable_float_construction
= 1;
10064 target_big_endian
= 1;
10068 target_big_endian
= 0;
10076 if (arg
&& arg
[1] == '0')
10086 mips_debug
= atoi (arg
);
10087 /* When the MIPS assembler sees -g or -g2, it does not do
10088 optimizations which limit full symbolic debugging. We take
10089 that to be equivalent to -O0. */
10090 if (mips_debug
== 2)
10095 file_mips_isa
= ISA_MIPS1
;
10099 file_mips_isa
= ISA_MIPS2
;
10103 file_mips_isa
= ISA_MIPS3
;
10107 file_mips_isa
= ISA_MIPS4
;
10111 file_mips_isa
= ISA_MIPS5
;
10114 case OPTION_MIPS32
:
10115 file_mips_isa
= ISA_MIPS32
;
10118 case OPTION_MIPS64
:
10119 file_mips_isa
= ISA_MIPS64
;
10123 mips_set_option_string (&mips_tune_string
, arg
);
10127 mips_set_option_string (&mips_arch_string
, arg
);
10131 mips_set_option_string (&mips_arch_string
, "4650");
10132 mips_set_option_string (&mips_tune_string
, "4650");
10135 case OPTION_NO_M4650
:
10139 mips_set_option_string (&mips_arch_string
, "4010");
10140 mips_set_option_string (&mips_tune_string
, "4010");
10143 case OPTION_NO_M4010
:
10147 mips_set_option_string (&mips_arch_string
, "4100");
10148 mips_set_option_string (&mips_tune_string
, "4100");
10151 case OPTION_NO_M4100
:
10155 mips_set_option_string (&mips_arch_string
, "3900");
10156 mips_set_option_string (&mips_tune_string
, "3900");
10159 case OPTION_NO_M3900
:
10163 mips_opts
.ase_mdmx
= 1;
10166 case OPTION_NO_MDMX
:
10167 mips_opts
.ase_mdmx
= 0;
10170 case OPTION_MIPS16
:
10171 mips_opts
.mips16
= 1;
10172 mips_no_prev_insn (false);
10175 case OPTION_NO_MIPS16
:
10176 mips_opts
.mips16
= 0;
10177 mips_no_prev_insn (false);
10180 case OPTION_MIPS3D
:
10181 mips_opts
.ase_mips3d
= 1;
10184 case OPTION_NO_MIPS3D
:
10185 mips_opts
.ase_mips3d
= 0;
10188 case OPTION_MEMBEDDED_PIC
:
10189 mips_pic
= EMBEDDED_PIC
;
10190 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10192 as_bad (_("-G may not be used with embedded PIC code"));
10195 g_switch_value
= 0x7fffffff;
10199 /* When generating ELF code, we permit -KPIC and -call_shared to
10200 select SVR4_PIC, and -non_shared to select no PIC. This is
10201 intended to be compatible with Irix 5. */
10202 case OPTION_CALL_SHARED
:
10203 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10205 as_bad (_("-call_shared is supported only for ELF format"));
10208 mips_pic
= SVR4_PIC
;
10209 if (g_switch_seen
&& g_switch_value
!= 0)
10211 as_bad (_("-G may not be used with SVR4 PIC code"));
10214 g_switch_value
= 0;
10217 case OPTION_NON_SHARED
:
10218 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10220 as_bad (_("-non_shared is supported only for ELF format"));
10226 /* The -xgot option tells the assembler to use 32 offsets when
10227 accessing the got in SVR4_PIC mode. It is for Irix
10232 #endif /* OBJ_ELF */
10235 if (! USE_GLOBAL_POINTER_OPT
)
10237 as_bad (_("-G is not supported for this configuration"));
10240 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10242 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10246 g_switch_value
= atoi (arg
);
10251 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10254 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10256 as_bad (_("-32 is supported for ELF format only"));
10259 mips_abi
= O32_ABI
;
10263 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10265 as_bad (_("-n32 is supported for ELF format only"));
10268 mips_abi
= N32_ABI
;
10272 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10274 as_bad (_("-64 is supported for ELF format only"));
10277 mips_abi
= N64_ABI
;
10278 if (! support_64bit_objects())
10279 as_fatal (_("No compiled in support for 64 bit object file format"));
10281 #endif /* OBJ_ELF */
10284 file_mips_gp32
= 1;
10288 file_mips_gp32
= 0;
10292 file_mips_fp32
= 1;
10296 file_mips_fp32
= 0;
10301 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10303 as_bad (_("-mabi is supported for ELF format only"));
10306 if (strcmp (arg
, "32") == 0)
10307 mips_abi
= O32_ABI
;
10308 else if (strcmp (arg
, "o64") == 0)
10309 mips_abi
= O64_ABI
;
10310 else if (strcmp (arg
, "n32") == 0)
10311 mips_abi
= N32_ABI
;
10312 else if (strcmp (arg
, "64") == 0)
10314 mips_abi
= N64_ABI
;
10315 if (! support_64bit_objects())
10316 as_fatal (_("No compiled in support for 64 bit object file "
10319 else if (strcmp (arg
, "eabi") == 0)
10320 mips_abi
= EABI_ABI
;
10323 as_fatal (_("invalid abi -mabi=%s"), arg
);
10327 #endif /* OBJ_ELF */
10329 case OPTION_M7000_HILO_FIX
:
10330 mips_7000_hilo_fix
= true;
10333 case OPTION_MNO_7000_HILO_FIX
:
10334 mips_7000_hilo_fix
= false;
10338 case OPTION_MDEBUG
:
10339 mips_flag_mdebug
= true;
10342 case OPTION_NO_MDEBUG
:
10343 mips_flag_mdebug
= false;
10345 #endif /* OBJ_ELF */
10354 /* Set up globals to generate code for the ISA or processor
10355 described by INFO. */
10358 mips_set_architecture (info
)
10359 const struct mips_cpu_info
*info
;
10363 mips_arch_info
= info
;
10364 mips_arch
= info
->cpu
;
10365 mips_opts
.isa
= info
->isa
;
10370 /* Likewise for tuning. */
10373 mips_set_tune (info
)
10374 const struct mips_cpu_info
*info
;
10378 mips_tune_info
= info
;
10379 mips_tune
= info
->cpu
;
10385 mips_after_parse_args ()
10387 /* GP relative stuff not working for PE */
10388 if (strncmp (TARGET_OS
, "pe", 2) == 0
10389 && g_switch_value
!= 0)
10392 as_bad (_("-G not supported in this configuration."));
10393 g_switch_value
= 0;
10396 /* The following code determines the architecture and register size.
10397 Similar code was added to GCC 3.3 (see override_options() in
10398 config/mips/mips.c). The GAS and GCC code should be kept in sync
10399 as much as possible. */
10401 if (mips_arch_string
!= 0)
10402 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10404 if (mips_tune_string
!= 0)
10405 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10407 if (file_mips_isa
!= ISA_UNKNOWN
)
10409 /* Handle -mipsN. At this point, file_mips_isa contains the
10410 ISA level specified by -mipsN, while mips_opts.isa contains
10411 the -march selection (if any). */
10412 if (mips_arch_info
!= 0)
10414 /* -march takes precedence over -mipsN, since it is more descriptive.
10415 There's no harm in specifying both as long as the ISA levels
10417 if (file_mips_isa
!= mips_opts
.isa
)
10418 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10419 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10420 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10423 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10426 if (mips_arch_info
== 0)
10427 mips_set_architecture (mips_parse_cpu ("default CPU",
10428 MIPS_CPU_STRING_DEFAULT
));
10430 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10431 as_bad ("-march=%s is not compatible with the selected ABI",
10432 mips_arch_info
->name
);
10434 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10435 if (mips_tune_info
== 0)
10436 mips_set_tune (mips_arch_info
);
10438 if (file_mips_gp32
>= 0)
10440 /* The user specified the size of the integer registers. Make sure
10441 it agrees with the ABI and ISA. */
10442 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10443 as_bad (_("-mgp64 used with a 32-bit processor"));
10444 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10445 as_bad (_("-mgp32 used with a 64-bit ABI"));
10446 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10447 as_bad (_("-mgp64 used with a 32-bit ABI"));
10451 /* Infer the integer register size from the ABI and processor.
10452 Restrict ourselves to 32-bit registers if that's all the
10453 processor has, or if the ABI cannot handle 64-bit registers. */
10454 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10455 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10458 /* ??? GAS treats single-float processors as though they had 64-bit
10459 float registers (although it complains when double-precision
10460 instructions are used). As things stand, saying they have 32-bit
10461 registers would lead to spurious "register must be even" messages.
10462 So here we assume float registers are always the same size as
10463 integer ones, unless the user says otherwise. */
10464 if (file_mips_fp32
< 0)
10465 file_mips_fp32
= file_mips_gp32
;
10467 /* End of GCC-shared inference code. */
10469 /* ??? When do we want this flag to be set? Who uses it? */
10470 if (file_mips_gp32
== 1
10471 && mips_abi
== NO_ABI
10472 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10473 mips_32bitmode
= 1;
10475 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10476 as_bad (_("trap exception not supported at ISA 1"));
10478 /* If the selected architecture includes support for ASEs, enable
10479 generation of code for them. */
10480 if (mips_opts
.mips16
== -1)
10481 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10482 if (mips_opts
.ase_mips3d
== -1)
10483 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10484 if (mips_opts
.ase_mdmx
== -1)
10485 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10487 file_mips_isa
= mips_opts
.isa
;
10488 file_ase_mips16
= mips_opts
.mips16
;
10489 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10490 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10491 mips_opts
.gp32
= file_mips_gp32
;
10492 mips_opts
.fp32
= file_mips_fp32
;
10494 if (mips_flag_mdebug
< 0)
10496 #ifdef OBJ_MAYBE_ECOFF
10497 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10498 mips_flag_mdebug
= 1;
10500 #endif /* OBJ_MAYBE_ECOFF */
10501 mips_flag_mdebug
= 0;
10506 mips_init_after_args ()
10508 /* initialize opcodes */
10509 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10510 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10514 md_pcrel_from (fixP
)
10517 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10518 && fixP
->fx_addsy
!= (symbolS
*) NULL
10519 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10521 /* This makes a branch to an undefined symbol be a branch to the
10522 current location. */
10523 if (mips_pic
== EMBEDDED_PIC
)
10529 /* Return the address of the delay slot. */
10530 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10533 /* This is called before the symbol table is processed. In order to
10534 work with gcc when using mips-tfile, we must keep all local labels.
10535 However, in other cases, we want to discard them. If we were
10536 called with -g, but we didn't see any debugging information, it may
10537 mean that gcc is smuggling debugging information through to
10538 mips-tfile, in which case we must generate all local labels. */
10541 mips_frob_file_before_adjust ()
10543 #ifndef NO_ECOFF_DEBUGGING
10544 if (ECOFF_DEBUGGING
10546 && ! ecoff_debugging_seen
)
10547 flag_keep_locals
= 1;
10551 /* Sort any unmatched HI16_S relocs so that they immediately precede
10552 the corresponding LO reloc. This is called before md_apply_fix3 and
10553 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10554 explicit use of the %hi modifier. */
10559 struct mips_hi_fixup
*l
;
10561 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10563 segment_info_type
*seginfo
;
10566 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10568 /* Check quickly whether the next fixup happens to be a matching
10570 if (l
->fixp
->fx_next
!= NULL
10571 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10572 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10573 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10576 /* Look through the fixups for this segment for a matching %lo.
10577 When we find one, move the %hi just in front of it. We do
10578 this in two passes. In the first pass, we try to find a
10579 unique %lo. In the second pass, we permit multiple %hi
10580 relocs for a single %lo (this is a GNU extension). */
10581 seginfo
= seg_info (l
->seg
);
10582 for (pass
= 0; pass
< 2; pass
++)
10587 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10589 /* Check whether this is a %lo fixup which matches l->fixp. */
10590 if (f
->fx_r_type
== BFD_RELOC_LO16
10591 && f
->fx_addsy
== l
->fixp
->fx_addsy
10592 && f
->fx_offset
== l
->fixp
->fx_offset
10595 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10596 || prev
->fx_addsy
!= f
->fx_addsy
10597 || prev
->fx_offset
!= f
->fx_offset
))
10601 /* Move l->fixp before f. */
10602 for (pf
= &seginfo
->fix_root
;
10604 pf
= &(*pf
)->fx_next
)
10605 assert (*pf
!= NULL
);
10607 *pf
= l
->fixp
->fx_next
;
10609 l
->fixp
->fx_next
= f
;
10611 seginfo
->fix_root
= l
->fixp
;
10613 prev
->fx_next
= l
->fixp
;
10624 #if 0 /* GCC code motion plus incomplete dead code elimination
10625 can leave a %hi without a %lo. */
10627 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10628 _("Unmatched %%hi reloc"));
10634 /* When generating embedded PIC code we need to use a special
10635 relocation to represent the difference of two symbols in the .text
10636 section (switch tables use a difference of this sort). See
10637 include/coff/mips.h for details. This macro checks whether this
10638 fixup requires the special reloc. */
10639 #define SWITCH_TABLE(fixp) \
10640 ((fixp)->fx_r_type == BFD_RELOC_32 \
10641 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10642 && (fixp)->fx_addsy != NULL \
10643 && (fixp)->fx_subsy != NULL \
10644 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10645 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10647 /* When generating embedded PIC code we must keep all PC relative
10648 relocations, in case the linker has to relax a call. We also need
10649 to keep relocations for switch table entries.
10651 We may have combined relocations without symbols in the N32/N64 ABI.
10652 We have to prevent gas from dropping them. */
10655 mips_force_relocation (fixp
)
10658 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10659 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10660 || S_FORCE_RELOC (fixp
->fx_addsy
))
10664 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10665 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10666 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10667 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10670 return (mips_pic
== EMBEDDED_PIC
10672 || SWITCH_TABLE (fixp
)
10673 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10674 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10679 mips_need_elf_addend_fixup (fixP
)
10682 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10684 if (mips_pic
== EMBEDDED_PIC
10685 && S_IS_WEAK (fixP
->fx_addsy
))
10687 if (mips_pic
!= EMBEDDED_PIC
10688 && (S_IS_WEAK (fixP
->fx_addsy
)
10689 || S_IS_EXTERNAL (fixP
->fx_addsy
))
10690 && !S_IS_COMMON (fixP
->fx_addsy
))
10692 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10693 && (((bfd_get_section_flags (stdoutput
,
10694 S_GET_SEGMENT (fixP
->fx_addsy
))
10695 & SEC_LINK_ONCE
) != 0)
10696 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10698 sizeof (".gnu.linkonce") - 1)))
10704 /* Apply a fixup to the object file. */
10707 md_apply_fix3 (fixP
, valP
, seg
)
10710 segT seg ATTRIBUTE_UNUSED
;
10715 static int previous_fx_r_type
= 0;
10717 /* FIXME: Maybe just return for all reloc types not listed below?
10718 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10719 if (fixP
->fx_r_type
== BFD_RELOC_8
)
10722 assert (fixP
->fx_size
== 4
10723 || fixP
->fx_r_type
== BFD_RELOC_16
10724 || fixP
->fx_r_type
== BFD_RELOC_32
10725 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10726 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10727 || fixP
->fx_r_type
== BFD_RELOC_LO16
10728 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10729 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10730 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10731 || fixP
->fx_r_type
== BFD_RELOC_64
10732 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10733 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10734 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10735 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10736 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10737 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10738 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10739 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10740 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10741 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
10745 /* If we aren't adjusting this fixup to be against the section
10746 symbol, we need to adjust the value. */
10748 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10750 if (mips_need_elf_addend_fixup (fixP
))
10752 reloc_howto_type
*howto
;
10753 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10757 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10758 if (value
!= 0 && howto
->partial_inplace
&& ! fixP
->fx_pcrel
)
10760 /* In this case, the bfd_install_relocation routine will
10761 incorrectly add the symbol value back in. We just want
10762 the addend to appear in the object file. */
10765 /* Make sure the addend is still non-zero. If it became zero
10766 after the last operation, set it to a spurious value and
10767 subtract the same value from the object file's contents. */
10772 /* The in-place addends for LO16 relocations are signed;
10773 leave the matching HI16 in-place addends as zero. */
10774 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10776 bfd_vma contents
, mask
, field
;
10778 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10781 target_big_endian
);
10783 /* MASK has bits set where the relocation should go.
10784 FIELD is -value, shifted into the appropriate place
10785 for this relocation. */
10786 mask
= 1 << (howto
->bitsize
- 1);
10787 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10788 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10790 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10791 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10793 target_big_endian
);
10799 /* This code was generated using trial and error and so is
10800 fragile and not trustworthy. If you change it, you should
10801 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10802 they still pass. */
10803 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10805 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10807 /* BFD's REL handling, for MIPS, is _very_ weird.
10808 This gives the right results, but it can't possibly
10809 be the way things are supposed to work. */
10810 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10811 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10812 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10813 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10818 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10820 /* We are not done if this is a composite relocation to set up gp. */
10821 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
10822 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10823 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
10824 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
10825 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
10827 previous_fx_r_type
= fixP
->fx_r_type
;
10829 switch (fixP
->fx_r_type
)
10831 case BFD_RELOC_MIPS_JMP
:
10832 case BFD_RELOC_MIPS_SHIFT5
:
10833 case BFD_RELOC_MIPS_SHIFT6
:
10834 case BFD_RELOC_MIPS_GOT_DISP
:
10835 case BFD_RELOC_MIPS_GOT_PAGE
:
10836 case BFD_RELOC_MIPS_GOT_OFST
:
10837 case BFD_RELOC_MIPS_SUB
:
10838 case BFD_RELOC_MIPS_INSERT_A
:
10839 case BFD_RELOC_MIPS_INSERT_B
:
10840 case BFD_RELOC_MIPS_DELETE
:
10841 case BFD_RELOC_MIPS_HIGHEST
:
10842 case BFD_RELOC_MIPS_HIGHER
:
10843 case BFD_RELOC_MIPS_SCN_DISP
:
10844 case BFD_RELOC_MIPS_REL16
:
10845 case BFD_RELOC_MIPS_RELGOT
:
10846 case BFD_RELOC_MIPS_JALR
:
10847 case BFD_RELOC_HI16
:
10848 case BFD_RELOC_HI16_S
:
10849 case BFD_RELOC_GPREL16
:
10850 case BFD_RELOC_MIPS_LITERAL
:
10851 case BFD_RELOC_MIPS_CALL16
:
10852 case BFD_RELOC_MIPS_GOT16
:
10853 case BFD_RELOC_GPREL32
:
10854 case BFD_RELOC_MIPS_GOT_HI16
:
10855 case BFD_RELOC_MIPS_GOT_LO16
:
10856 case BFD_RELOC_MIPS_CALL_HI16
:
10857 case BFD_RELOC_MIPS_CALL_LO16
:
10858 case BFD_RELOC_MIPS16_GPREL
:
10859 if (fixP
->fx_pcrel
)
10860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10861 _("Invalid PC relative reloc"));
10862 /* Nothing needed to do. The value comes from the reloc entry */
10865 case BFD_RELOC_MIPS16_JMP
:
10866 /* We currently always generate a reloc against a symbol, which
10867 means that we don't want an addend even if the symbol is
10869 fixP
->fx_addnumber
= 0;
10872 case BFD_RELOC_PCREL_HI16_S
:
10873 /* The addend for this is tricky if it is internal, so we just
10874 do everything here rather than in bfd_install_relocation. */
10875 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10880 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10882 /* For an external symbol adjust by the address to make it
10883 pcrel_offset. We use the address of the RELLO reloc
10884 which follows this one. */
10885 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10886 + fixP
->fx_next
->fx_where
);
10888 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10889 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10890 if (target_big_endian
)
10892 md_number_to_chars ((char *) buf
, value
, 2);
10895 case BFD_RELOC_PCREL_LO16
:
10896 /* The addend for this is tricky if it is internal, so we just
10897 do everything here rather than in bfd_install_relocation. */
10898 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10903 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10904 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10905 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10906 if (target_big_endian
)
10908 md_number_to_chars ((char *) buf
, value
, 2);
10912 /* This is handled like BFD_RELOC_32, but we output a sign
10913 extended value if we are only 32 bits. */
10915 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10917 if (8 <= sizeof (valueT
))
10918 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10925 w1
= w2
= fixP
->fx_where
;
10926 if (target_big_endian
)
10930 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10931 if ((value
& 0x80000000) != 0)
10935 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10940 case BFD_RELOC_RVA
:
10942 /* If we are deleting this reloc entry, we must fill in the
10943 value now. This can happen if we have a .word which is not
10944 resolved when it appears but is later defined. We also need
10945 to fill in the value if this is an embedded PIC switch table
10948 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10949 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10954 /* If we are deleting this reloc entry, we must fill in the
10956 assert (fixP
->fx_size
== 2);
10958 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10962 case BFD_RELOC_LO16
:
10963 /* When handling an embedded PIC switch statement, we can wind
10964 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10967 if (value
+ 0x8000 > 0xffff)
10968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10969 _("relocation overflow"));
10970 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10971 if (target_big_endian
)
10973 md_number_to_chars ((char *) buf
, value
, 2);
10977 case BFD_RELOC_16_PCREL_S2
:
10978 if ((value
& 0x3) != 0)
10979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10980 _("Branch to odd address (%lx)"), (long) value
);
10982 /* Fall through. */
10984 case BFD_RELOC_16_PCREL
:
10986 * We need to save the bits in the instruction since fixup_segment()
10987 * might be deleting the relocation entry (i.e., a branch within
10988 * the current segment).
10990 if (!fixP
->fx_done
&& value
!= 0)
10992 /* If 'value' is zero, the remaining reloc code won't actually
10993 do the store, so it must be done here. This is probably
10994 a bug somewhere. */
10996 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
10997 || fixP
->fx_addsy
== NULL
/* ??? */
10998 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
10999 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11001 value
= (offsetT
) value
>> 2;
11003 /* update old instruction data */
11004 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11005 if (target_big_endian
)
11006 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11008 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11010 if (value
+ 0x8000 <= 0xffff)
11011 insn
|= value
& 0xffff;
11014 /* The branch offset is too large. If this is an
11015 unconditional branch, and we are not generating PIC code,
11016 we can convert it to an absolute jump instruction. */
11017 if (mips_pic
== NO_PIC
11019 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11020 && (fixP
->fx_frag
->fr_address
11021 < text_section
->vma
+ text_section
->_raw_size
)
11022 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11023 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11024 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11026 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11027 insn
= 0x0c000000; /* jal */
11029 insn
= 0x08000000; /* j */
11030 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11032 fixP
->fx_addsy
= section_symbol (text_section
);
11033 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11037 /* FIXME. It would be possible in principle to handle
11038 conditional branches which overflow. They could be
11039 transformed into a branch around a jump. This would
11040 require setting up variant frags for each different
11041 branch type. The native MIPS assembler attempts to
11042 handle these cases, but it appears to do it
11044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11045 _("Branch out of range"));
11049 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11052 case BFD_RELOC_VTABLE_INHERIT
:
11055 && !S_IS_DEFINED (fixP
->fx_addsy
)
11056 && !S_IS_WEAK (fixP
->fx_addsy
))
11057 S_SET_WEAK (fixP
->fx_addsy
);
11060 case BFD_RELOC_VTABLE_ENTRY
:
11074 const struct mips_opcode
*p
;
11075 int treg
, sreg
, dreg
, shamt
;
11080 for (i
= 0; i
< NUMOPCODES
; ++i
)
11082 p
= &mips_opcodes
[i
];
11083 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11085 printf ("%08lx %s\t", oc
, p
->name
);
11086 treg
= (oc
>> 16) & 0x1f;
11087 sreg
= (oc
>> 21) & 0x1f;
11088 dreg
= (oc
>> 11) & 0x1f;
11089 shamt
= (oc
>> 6) & 0x1f;
11091 for (args
= p
->args
;; ++args
)
11102 printf ("%c", *args
);
11106 assert (treg
== sreg
);
11107 printf ("$%d,$%d", treg
, sreg
);
11112 printf ("$%d", dreg
);
11117 printf ("$%d", treg
);
11121 printf ("0x%x", treg
);
11126 printf ("$%d", sreg
);
11130 printf ("0x%08lx", oc
& 0x1ffffff);
11137 printf ("%d", imm
);
11142 printf ("$%d", shamt
);
11153 printf (_("%08lx UNDEFINED\n"), oc
);
11164 name
= input_line_pointer
;
11165 c
= get_symbol_end ();
11166 p
= (symbolS
*) symbol_find_or_make (name
);
11167 *input_line_pointer
= c
;
11171 /* Align the current frag to a given power of two. The MIPS assembler
11172 also automatically adjusts any preceding label. */
11175 mips_align (to
, fill
, label
)
11180 mips_emit_delays (false);
11181 frag_align (to
, fill
, 0);
11182 record_alignment (now_seg
, to
);
11185 assert (S_GET_SEGMENT (label
) == now_seg
);
11186 symbol_set_frag (label
, frag_now
);
11187 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11191 /* Align to a given power of two. .align 0 turns off the automatic
11192 alignment used by the data creating pseudo-ops. */
11196 int x ATTRIBUTE_UNUSED
;
11199 register long temp_fill
;
11200 long max_alignment
= 15;
11204 o Note that the assembler pulls down any immediately preceeding label
11205 to the aligned address.
11206 o It's not documented but auto alignment is reinstated by
11207 a .align pseudo instruction.
11208 o Note also that after auto alignment is turned off the mips assembler
11209 issues an error on attempt to assemble an improperly aligned data item.
11214 temp
= get_absolute_expression ();
11215 if (temp
> max_alignment
)
11216 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11219 as_warn (_("Alignment negative: 0 assumed."));
11222 if (*input_line_pointer
== ',')
11224 ++input_line_pointer
;
11225 temp_fill
= get_absolute_expression ();
11232 mips_align (temp
, (int) temp_fill
,
11233 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11240 demand_empty_rest_of_line ();
11244 mips_flush_pending_output ()
11246 mips_emit_delays (false);
11247 mips_clear_insn_labels ();
11256 /* When generating embedded PIC code, we only use the .text, .lit8,
11257 .sdata and .sbss sections. We change the .data and .rdata
11258 pseudo-ops to use .sdata. */
11259 if (mips_pic
== EMBEDDED_PIC
11260 && (sec
== 'd' || sec
== 'r'))
11264 /* The ELF backend needs to know that we are changing sections, so
11265 that .previous works correctly. We could do something like check
11266 for an obj_section_change_hook macro, but that might be confusing
11267 as it would not be appropriate to use it in the section changing
11268 functions in read.c, since obj-elf.c intercepts those. FIXME:
11269 This should be cleaner, somehow. */
11270 obj_elf_section_change_hook ();
11273 mips_emit_delays (false);
11283 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11284 demand_empty_rest_of_line ();
11288 if (USE_GLOBAL_POINTER_OPT
)
11290 seg
= subseg_new (RDATA_SECTION_NAME
,
11291 (subsegT
) get_absolute_expression ());
11292 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11294 bfd_set_section_flags (stdoutput
, seg
,
11300 if (strcmp (TARGET_OS
, "elf") != 0)
11301 record_alignment (seg
, 4);
11303 demand_empty_rest_of_line ();
11307 as_bad (_("No read only data section in this object file format"));
11308 demand_empty_rest_of_line ();
11314 if (USE_GLOBAL_POINTER_OPT
)
11316 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11317 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11319 bfd_set_section_flags (stdoutput
, seg
,
11320 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11322 if (strcmp (TARGET_OS
, "elf") != 0)
11323 record_alignment (seg
, 4);
11325 demand_empty_rest_of_line ();
11330 as_bad (_("Global pointers not supported; recompile -G 0"));
11331 demand_empty_rest_of_line ();
11340 s_change_section (ignore
)
11341 int ignore ATTRIBUTE_UNUSED
;
11344 char *section_name
;
11349 int section_entry_size
;
11350 int section_alignment
;
11352 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11355 section_name
= input_line_pointer
;
11356 c
= get_symbol_end ();
11357 next_c
= *(input_line_pointer
+ 1);
11359 /* Do we have .section Name<,"flags">? */
11360 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11362 /* just after name is now '\0'. */
11363 *input_line_pointer
= c
;
11364 input_line_pointer
= section_name
;
11365 obj_elf_section (ignore
);
11368 input_line_pointer
++;
11370 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11372 section_type
= get_absolute_expression ();
11375 if (*input_line_pointer
++ == ',')
11376 section_flag
= get_absolute_expression ();
11379 if (*input_line_pointer
++ == ',')
11380 section_entry_size
= get_absolute_expression ();
11382 section_entry_size
= 0;
11383 if (*input_line_pointer
++ == ',')
11384 section_alignment
= get_absolute_expression ();
11386 section_alignment
= 0;
11388 obj_elf_change_section (section_name
, section_type
, section_flag
,
11389 section_entry_size
, 0, 0, 0);
11390 #endif /* OBJ_ELF */
11394 mips_enable_auto_align ()
11405 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11406 mips_emit_delays (false);
11407 if (log_size
> 0 && auto_align
)
11408 mips_align (log_size
, 0, label
);
11409 mips_clear_insn_labels ();
11410 cons (1 << log_size
);
11414 s_float_cons (type
)
11419 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11421 mips_emit_delays (false);
11426 mips_align (3, 0, label
);
11428 mips_align (2, 0, label
);
11431 mips_clear_insn_labels ();
11436 /* Handle .globl. We need to override it because on Irix 5 you are
11439 where foo is an undefined symbol, to mean that foo should be
11440 considered to be the address of a function. */
11444 int x ATTRIBUTE_UNUSED
;
11451 name
= input_line_pointer
;
11452 c
= get_symbol_end ();
11453 symbolP
= symbol_find_or_make (name
);
11454 *input_line_pointer
= c
;
11455 SKIP_WHITESPACE ();
11457 /* On Irix 5, every global symbol that is not explicitly labelled as
11458 being a function is apparently labelled as being an object. */
11461 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11466 secname
= input_line_pointer
;
11467 c
= get_symbol_end ();
11468 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11470 as_bad (_("%s: no such section"), secname
);
11471 *input_line_pointer
= c
;
11473 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11474 flag
= BSF_FUNCTION
;
11477 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11479 S_SET_EXTERNAL (symbolP
);
11480 demand_empty_rest_of_line ();
11485 int x ATTRIBUTE_UNUSED
;
11490 opt
= input_line_pointer
;
11491 c
= get_symbol_end ();
11495 /* FIXME: What does this mean? */
11497 else if (strncmp (opt
, "pic", 3) == 0)
11501 i
= atoi (opt
+ 3);
11505 mips_pic
= SVR4_PIC
;
11507 as_bad (_(".option pic%d not supported"), i
);
11509 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11511 if (g_switch_seen
&& g_switch_value
!= 0)
11512 as_warn (_("-G may not be used with SVR4 PIC code"));
11513 g_switch_value
= 0;
11514 bfd_set_gp_size (stdoutput
, 0);
11518 as_warn (_("Unrecognized option \"%s\""), opt
);
11520 *input_line_pointer
= c
;
11521 demand_empty_rest_of_line ();
11524 /* This structure is used to hold a stack of .set values. */
11526 struct mips_option_stack
11528 struct mips_option_stack
*next
;
11529 struct mips_set_options options
;
11532 static struct mips_option_stack
*mips_opts_stack
;
11534 /* Handle the .set pseudo-op. */
11538 int x ATTRIBUTE_UNUSED
;
11540 char *name
= input_line_pointer
, ch
;
11542 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11543 ++input_line_pointer
;
11544 ch
= *input_line_pointer
;
11545 *input_line_pointer
= '\0';
11547 if (strcmp (name
, "reorder") == 0)
11549 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11551 /* If we still have pending nops, we can discard them. The
11552 usual nop handling will insert any that are still
11554 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11555 * (mips_opts
.mips16
? 2 : 4));
11556 prev_nop_frag
= NULL
;
11558 mips_opts
.noreorder
= 0;
11560 else if (strcmp (name
, "noreorder") == 0)
11562 mips_emit_delays (true);
11563 mips_opts
.noreorder
= 1;
11564 mips_any_noreorder
= 1;
11566 else if (strcmp (name
, "at") == 0)
11568 mips_opts
.noat
= 0;
11570 else if (strcmp (name
, "noat") == 0)
11572 mips_opts
.noat
= 1;
11574 else if (strcmp (name
, "macro") == 0)
11576 mips_opts
.warn_about_macros
= 0;
11578 else if (strcmp (name
, "nomacro") == 0)
11580 if (mips_opts
.noreorder
== 0)
11581 as_bad (_("`noreorder' must be set before `nomacro'"));
11582 mips_opts
.warn_about_macros
= 1;
11584 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11586 mips_opts
.nomove
= 0;
11588 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11590 mips_opts
.nomove
= 1;
11592 else if (strcmp (name
, "bopt") == 0)
11594 mips_opts
.nobopt
= 0;
11596 else if (strcmp (name
, "nobopt") == 0)
11598 mips_opts
.nobopt
= 1;
11600 else if (strcmp (name
, "mips16") == 0
11601 || strcmp (name
, "MIPS-16") == 0)
11602 mips_opts
.mips16
= 1;
11603 else if (strcmp (name
, "nomips16") == 0
11604 || strcmp (name
, "noMIPS-16") == 0)
11605 mips_opts
.mips16
= 0;
11606 else if (strcmp (name
, "mips3d") == 0)
11607 mips_opts
.ase_mips3d
= 1;
11608 else if (strcmp (name
, "nomips3d") == 0)
11609 mips_opts
.ase_mips3d
= 0;
11610 else if (strcmp (name
, "mdmx") == 0)
11611 mips_opts
.ase_mdmx
= 1;
11612 else if (strcmp (name
, "nomdmx") == 0)
11613 mips_opts
.ase_mdmx
= 0;
11614 else if (strncmp (name
, "mips", 4) == 0)
11618 /* Permit the user to change the ISA on the fly. Needless to
11619 say, misuse can cause serious problems. */
11620 isa
= atoi (name
+ 4);
11624 mips_opts
.gp32
= file_mips_gp32
;
11625 mips_opts
.fp32
= file_mips_fp32
;
11630 mips_opts
.gp32
= 1;
11631 mips_opts
.fp32
= 1;
11637 mips_opts
.gp32
= 0;
11638 mips_opts
.fp32
= 0;
11641 as_bad (_("unknown ISA level %s"), name
+ 4);
11647 case 0: mips_opts
.isa
= file_mips_isa
; break;
11648 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11649 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11650 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11651 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11652 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11653 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11654 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11655 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11658 else if (strcmp (name
, "autoextend") == 0)
11659 mips_opts
.noautoextend
= 0;
11660 else if (strcmp (name
, "noautoextend") == 0)
11661 mips_opts
.noautoextend
= 1;
11662 else if (strcmp (name
, "push") == 0)
11664 struct mips_option_stack
*s
;
11666 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11667 s
->next
= mips_opts_stack
;
11668 s
->options
= mips_opts
;
11669 mips_opts_stack
= s
;
11671 else if (strcmp (name
, "pop") == 0)
11673 struct mips_option_stack
*s
;
11675 s
= mips_opts_stack
;
11677 as_bad (_(".set pop with no .set push"));
11680 /* If we're changing the reorder mode we need to handle
11681 delay slots correctly. */
11682 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11683 mips_emit_delays (true);
11684 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11686 if (prev_nop_frag
!= NULL
)
11688 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11689 * (mips_opts
.mips16
? 2 : 4));
11690 prev_nop_frag
= NULL
;
11694 mips_opts
= s
->options
;
11695 mips_opts_stack
= s
->next
;
11701 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11703 *input_line_pointer
= ch
;
11704 demand_empty_rest_of_line ();
11707 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11708 .option pic2. It means to generate SVR4 PIC calls. */
11711 s_abicalls (ignore
)
11712 int ignore ATTRIBUTE_UNUSED
;
11714 mips_pic
= SVR4_PIC
;
11715 if (USE_GLOBAL_POINTER_OPT
)
11717 if (g_switch_seen
&& g_switch_value
!= 0)
11718 as_warn (_("-G may not be used with SVR4 PIC code"));
11719 g_switch_value
= 0;
11721 bfd_set_gp_size (stdoutput
, 0);
11722 demand_empty_rest_of_line ();
11725 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11726 PIC code. It sets the $gp register for the function based on the
11727 function address, which is in the register named in the argument.
11728 This uses a relocation against _gp_disp, which is handled specially
11729 by the linker. The result is:
11730 lui $gp,%hi(_gp_disp)
11731 addiu $gp,$gp,%lo(_gp_disp)
11732 addu $gp,$gp,.cpload argument
11733 The .cpload argument is normally $25 == $t9. */
11737 int ignore ATTRIBUTE_UNUSED
;
11742 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11743 .cpload is ignored. */
11744 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11750 /* .cpload should be in a .set noreorder section. */
11751 if (mips_opts
.noreorder
== 0)
11752 as_warn (_(".cpload not in noreorder section"));
11754 ex
.X_op
= O_symbol
;
11755 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11756 ex
.X_op_symbol
= NULL
;
11757 ex
.X_add_number
= 0;
11759 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11760 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11762 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
11763 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
11764 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
11766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11767 mips_gp_register
, mips_gp_register
, tc_get_register (0));
11769 demand_empty_rest_of_line ();
11772 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11773 .cpsetup $reg1, offset|$reg2, label
11775 If offset is given, this results in:
11776 sd $gp, offset($sp)
11777 lui $gp, %hi(%neg(%gp_rel(label)))
11778 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11779 daddu $gp, $gp, $reg1
11781 If $reg2 is given, this results in:
11782 daddu $reg2, $gp, $0
11783 lui $gp, %hi(%neg(%gp_rel(label)))
11784 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11785 daddu $gp, $gp, $reg1
11786 $reg1 is normally $25 == $t9. */
11789 int ignore ATTRIBUTE_UNUSED
;
11791 expressionS ex_off
;
11792 expressionS ex_sym
;
11797 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11798 We also need NewABI support. */
11799 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11805 reg1
= tc_get_register (0);
11806 SKIP_WHITESPACE ();
11807 if (*input_line_pointer
!= ',')
11809 as_bad (_("missing argument separator ',' for .cpsetup"));
11813 ++input_line_pointer
;
11814 SKIP_WHITESPACE ();
11815 if (*input_line_pointer
== '$')
11817 mips_cpreturn_register
= tc_get_register (0);
11818 mips_cpreturn_offset
= -1;
11822 mips_cpreturn_offset
= get_absolute_expression ();
11823 mips_cpreturn_register
= -1;
11825 SKIP_WHITESPACE ();
11826 if (*input_line_pointer
!= ',')
11828 as_bad (_("missing argument separator ',' for .cpsetup"));
11832 ++input_line_pointer
;
11833 SKIP_WHITESPACE ();
11834 expression (&ex_sym
);
11836 if (mips_cpreturn_register
== -1)
11838 ex_off
.X_op
= O_constant
;
11839 ex_off
.X_add_symbol
= NULL
;
11840 ex_off
.X_op_symbol
= NULL
;
11841 ex_off
.X_add_number
= mips_cpreturn_offset
;
11843 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11844 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11847 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11848 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11850 /* Ensure there's room for the next two instructions, so that `f'
11851 doesn't end up with an address in the wrong frag. */
11854 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11855 (int) BFD_RELOC_GPREL16
);
11856 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11857 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11858 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11859 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11862 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11863 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11864 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11865 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11866 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11867 0, NULL
, 0, 0, BFD_RELOC_LO16
);
11869 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11870 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
11871 mips_gp_register
, mips_gp_register
, reg1
);
11873 demand_empty_rest_of_line ();
11878 int ignore ATTRIBUTE_UNUSED
;
11880 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11881 .cplocal is ignored. */
11882 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11888 mips_gp_register
= tc_get_register (0);
11889 demand_empty_rest_of_line ();
11892 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11893 offset from $sp. The offset is remembered, and after making a PIC
11894 call $gp is restored from that location. */
11897 s_cprestore (ignore
)
11898 int ignore ATTRIBUTE_UNUSED
;
11903 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11904 .cprestore is ignored. */
11905 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11911 mips_cprestore_offset
= get_absolute_expression ();
11912 mips_cprestore_valid
= 1;
11914 ex
.X_op
= O_constant
;
11915 ex
.X_add_symbol
= NULL
;
11916 ex
.X_op_symbol
= NULL
;
11917 ex
.X_add_number
= mips_cprestore_offset
;
11919 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
11920 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11921 mips_gp_register
, SP
);
11923 demand_empty_rest_of_line ();
11926 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11927 was given in the preceeding .gpsetup, it results in:
11928 ld $gp, offset($sp)
11930 If a register $reg2 was given there, it results in:
11931 daddiu $gp, $gp, $reg2
11934 s_cpreturn (ignore
)
11935 int ignore ATTRIBUTE_UNUSED
;
11940 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11941 We also need NewABI support. */
11942 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11948 if (mips_cpreturn_register
== -1)
11950 ex
.X_op
= O_constant
;
11951 ex
.X_add_symbol
= NULL
;
11952 ex
.X_op_symbol
= NULL
;
11953 ex
.X_add_number
= mips_cpreturn_offset
;
11955 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11956 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11959 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11960 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11962 demand_empty_rest_of_line ();
11965 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11966 code. It sets the offset to use in gp_rel relocations. */
11970 int ignore ATTRIBUTE_UNUSED
;
11972 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11973 We also need NewABI support. */
11974 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11980 mips_gprel_offset
= get_absolute_expression ();
11982 demand_empty_rest_of_line ();
11985 /* Handle the .gpword pseudo-op. This is used when generating PIC
11986 code. It generates a 32 bit GP relative reloc. */
11990 int ignore ATTRIBUTE_UNUSED
;
11996 /* When not generating PIC code, this is treated as .word. */
11997 if (mips_pic
!= SVR4_PIC
)
12003 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12004 mips_emit_delays (true);
12006 mips_align (2, 0, label
);
12007 mips_clear_insn_labels ();
12011 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12013 as_bad (_("Unsupported use of .gpword"));
12014 ignore_rest_of_line ();
12018 md_number_to_chars (p
, (valueT
) 0, 4);
12019 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
12020 BFD_RELOC_GPREL32
);
12022 demand_empty_rest_of_line ();
12025 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12026 tables in SVR4 PIC code. */
12030 int ignore ATTRIBUTE_UNUSED
;
12035 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12037 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12043 /* Add $gp to the register named as an argument. */
12044 reg
= tc_get_register (0);
12045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12046 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12047 "d,v,t", reg
, reg
, mips_gp_register
);
12049 demand_empty_rest_of_line ();
12052 /* Handle the .insn pseudo-op. This marks instruction labels in
12053 mips16 mode. This permits the linker to handle them specially,
12054 such as generating jalx instructions when needed. We also make
12055 them odd for the duration of the assembly, in order to generate the
12056 right sort of code. We will make them even in the adjust_symtab
12057 routine, while leaving them marked. This is convenient for the
12058 debugger and the disassembler. The linker knows to make them odd
12063 int ignore ATTRIBUTE_UNUSED
;
12065 mips16_mark_labels ();
12067 demand_empty_rest_of_line ();
12070 /* Handle a .stabn directive. We need these in order to mark a label
12071 as being a mips16 text label correctly. Sometimes the compiler
12072 will emit a label, followed by a .stabn, and then switch sections.
12073 If the label and .stabn are in mips16 mode, then the label is
12074 really a mips16 text label. */
12081 mips16_mark_labels ();
12086 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12090 s_mips_weakext (ignore
)
12091 int ignore ATTRIBUTE_UNUSED
;
12098 name
= input_line_pointer
;
12099 c
= get_symbol_end ();
12100 symbolP
= symbol_find_or_make (name
);
12101 S_SET_WEAK (symbolP
);
12102 *input_line_pointer
= c
;
12104 SKIP_WHITESPACE ();
12106 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12108 if (S_IS_DEFINED (symbolP
))
12110 as_bad ("ignoring attempt to redefine symbol %s",
12111 S_GET_NAME (symbolP
));
12112 ignore_rest_of_line ();
12116 if (*input_line_pointer
== ',')
12118 ++input_line_pointer
;
12119 SKIP_WHITESPACE ();
12123 if (exp
.X_op
!= O_symbol
)
12125 as_bad ("bad .weakext directive");
12126 ignore_rest_of_line ();
12129 symbol_set_value_expression (symbolP
, &exp
);
12132 demand_empty_rest_of_line ();
12135 /* Parse a register string into a number. Called from the ECOFF code
12136 to parse .frame. The argument is non-zero if this is the frame
12137 register, so that we can record it in mips_frame_reg. */
12140 tc_get_register (frame
)
12145 SKIP_WHITESPACE ();
12146 if (*input_line_pointer
++ != '$')
12148 as_warn (_("expected `$'"));
12151 else if (ISDIGIT (*input_line_pointer
))
12153 reg
= get_absolute_expression ();
12154 if (reg
< 0 || reg
>= 32)
12156 as_warn (_("Bad register number"));
12162 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12165 input_line_pointer
+= 2;
12167 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12170 input_line_pointer
+= 2;
12172 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12175 input_line_pointer
+= 2;
12177 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12180 input_line_pointer
+= 2;
12182 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12185 input_line_pointer
+= 2;
12187 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12190 input_line_pointer
+= 3;
12192 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12195 input_line_pointer
+= 3;
12197 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12200 input_line_pointer
+= 4;
12204 as_warn (_("Unrecognized register name"));
12206 while (ISALNUM(*input_line_pointer
))
12207 input_line_pointer
++;
12212 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12213 mips_frame_reg_valid
= 1;
12214 mips_cprestore_valid
= 0;
12220 md_section_align (seg
, addr
)
12224 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12227 /* We don't need to align ELF sections to the full alignment.
12228 However, Irix 5 may prefer that we align them at least to a 16
12229 byte boundary. We don't bother to align the sections if we are
12230 targeted for an embedded system. */
12231 if (strcmp (TARGET_OS
, "elf") == 0)
12237 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12240 /* Utility routine, called from above as well. If called while the
12241 input file is still being read, it's only an approximation. (For
12242 example, a symbol may later become defined which appeared to be
12243 undefined earlier.) */
12246 nopic_need_relax (sym
, before_relaxing
)
12248 int before_relaxing
;
12253 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12255 const char *symname
;
12258 /* Find out whether this symbol can be referenced off the $gp
12259 register. It can be if it is smaller than the -G size or if
12260 it is in the .sdata or .sbss section. Certain symbols can
12261 not be referenced off the $gp, although it appears as though
12263 symname
= S_GET_NAME (sym
);
12264 if (symname
!= (const char *) NULL
12265 && (strcmp (symname
, "eprol") == 0
12266 || strcmp (symname
, "etext") == 0
12267 || strcmp (symname
, "_gp") == 0
12268 || strcmp (symname
, "edata") == 0
12269 || strcmp (symname
, "_fbss") == 0
12270 || strcmp (symname
, "_fdata") == 0
12271 || strcmp (symname
, "_ftext") == 0
12272 || strcmp (symname
, "end") == 0
12273 || strcmp (symname
, "_gp_disp") == 0))
12275 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12277 #ifndef NO_ECOFF_DEBUGGING
12278 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12279 && (symbol_get_obj (sym
)->ecoff_extern_size
12280 <= g_switch_value
))
12282 /* We must defer this decision until after the whole
12283 file has been read, since there might be a .extern
12284 after the first use of this symbol. */
12285 || (before_relaxing
12286 #ifndef NO_ECOFF_DEBUGGING
12287 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12289 && S_GET_VALUE (sym
) == 0)
12290 || (S_GET_VALUE (sym
) != 0
12291 && S_GET_VALUE (sym
) <= g_switch_value
)))
12295 const char *segname
;
12297 segname
= segment_name (S_GET_SEGMENT (sym
));
12298 assert (strcmp (segname
, ".lit8") != 0
12299 && strcmp (segname
, ".lit4") != 0);
12300 change
= (strcmp (segname
, ".sdata") != 0
12301 && strcmp (segname
, ".sbss") != 0
12302 && strncmp (segname
, ".sdata.", 7) != 0
12303 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12308 /* We are not optimizing for the $gp register. */
12312 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12313 extended opcode. SEC is the section the frag is in. */
12316 mips16_extended_frag (fragp
, sec
, stretch
)
12322 register const struct mips16_immed_operand
*op
;
12324 int mintiny
, maxtiny
;
12328 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12330 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12333 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12334 op
= mips16_immed_operands
;
12335 while (op
->type
!= type
)
12338 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12343 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12346 maxtiny
= 1 << op
->nbits
;
12351 maxtiny
= (1 << op
->nbits
) - 1;
12356 mintiny
= - (1 << (op
->nbits
- 1));
12357 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12360 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12361 val
= S_GET_VALUE (fragp
->fr_symbol
);
12362 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12368 /* We won't have the section when we are called from
12369 mips_relax_frag. However, we will always have been called
12370 from md_estimate_size_before_relax first. If this is a
12371 branch to a different section, we mark it as such. If SEC is
12372 NULL, and the frag is not marked, then it must be a branch to
12373 the same section. */
12376 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12381 /* Must have been called from md_estimate_size_before_relax. */
12384 fragp
->fr_subtype
=
12385 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12387 /* FIXME: We should support this, and let the linker
12388 catch branches and loads that are out of range. */
12389 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12390 _("unsupported PC relative reference to different section"));
12394 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12395 /* Assume non-extended on the first relaxation pass.
12396 The address we have calculated will be bogus if this is
12397 a forward branch to another frag, as the forward frag
12398 will have fr_address == 0. */
12402 /* In this case, we know for sure that the symbol fragment is in
12403 the same section. If the relax_marker of the symbol fragment
12404 differs from the relax_marker of this fragment, we have not
12405 yet adjusted the symbol fragment fr_address. We want to add
12406 in STRETCH in order to get a better estimate of the address.
12407 This particularly matters because of the shift bits. */
12409 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12413 /* Adjust stretch for any alignment frag. Note that if have
12414 been expanding the earlier code, the symbol may be
12415 defined in what appears to be an earlier frag. FIXME:
12416 This doesn't handle the fr_subtype field, which specifies
12417 a maximum number of bytes to skip when doing an
12419 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12421 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12424 stretch
= - ((- stretch
)
12425 & ~ ((1 << (int) f
->fr_offset
) - 1));
12427 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12436 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12438 /* The base address rules are complicated. The base address of
12439 a branch is the following instruction. The base address of a
12440 PC relative load or add is the instruction itself, but if it
12441 is in a delay slot (in which case it can not be extended) use
12442 the address of the instruction whose delay slot it is in. */
12443 if (type
== 'p' || type
== 'q')
12447 /* If we are currently assuming that this frag should be
12448 extended, then, the current address is two bytes
12450 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12453 /* Ignore the low bit in the target, since it will be set
12454 for a text label. */
12455 if ((val
& 1) != 0)
12458 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12460 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12463 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12465 /* Branch offsets have an implicit 0 in the lowest bit. */
12466 if (type
== 'p' || type
== 'q')
12469 /* If any of the shifted bits are set, we must use an extended
12470 opcode. If the address depends on the size of this
12471 instruction, this can lead to a loop, so we arrange to always
12472 use an extended opcode. We only check this when we are in
12473 the main relaxation loop, when SEC is NULL. */
12474 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12476 fragp
->fr_subtype
=
12477 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12481 /* If we are about to mark a frag as extended because the value
12482 is precisely maxtiny + 1, then there is a chance of an
12483 infinite loop as in the following code:
12488 In this case when the la is extended, foo is 0x3fc bytes
12489 away, so the la can be shrunk, but then foo is 0x400 away, so
12490 the la must be extended. To avoid this loop, we mark the
12491 frag as extended if it was small, and is about to become
12492 extended with a value of maxtiny + 1. */
12493 if (val
== ((maxtiny
+ 1) << op
->shift
)
12494 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12497 fragp
->fr_subtype
=
12498 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12502 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12503 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12505 if ((val
& ((1 << op
->shift
) - 1)) != 0
12506 || val
< (mintiny
<< op
->shift
)
12507 || val
> (maxtiny
<< op
->shift
))
12513 /* Estimate the size of a frag before relaxing. Unless this is the
12514 mips16, we are not really relaxing here, and the final size is
12515 encoded in the subtype information. For the mips16, we have to
12516 decide whether we are using an extended opcode or not. */
12519 md_estimate_size_before_relax (fragp
, segtype
)
12524 boolean linkonce
= false;
12526 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12527 /* We don't want to modify the EXTENDED bit here; it might get us
12528 into infinite loops. We change it only in mips_relax_frag(). */
12529 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12531 if (mips_pic
== NO_PIC
)
12533 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12535 else if (mips_pic
== SVR4_PIC
)
12540 sym
= fragp
->fr_symbol
;
12542 /* Handle the case of a symbol equated to another symbol. */
12543 while (symbol_equated_reloc_p (sym
))
12547 /* It's possible to get a loop here in a badly written
12549 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12555 symsec
= S_GET_SEGMENT (sym
);
12557 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12558 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12560 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12564 /* The GNU toolchain uses an extension for ELF: a section
12565 beginning with the magic string .gnu.linkonce is a linkonce
12567 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12568 sizeof ".gnu.linkonce" - 1) == 0)
12572 /* This must duplicate the test in adjust_reloc_syms. */
12573 change
= (symsec
!= &bfd_und_section
12574 && symsec
!= &bfd_abs_section
12575 && ! bfd_is_com_section (symsec
)
12578 /* A global or weak symbol is treated as external. */
12579 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12580 || (! S_IS_WEAK (sym
)
12581 && (! S_IS_EXTERNAL (sym
)
12582 || mips_pic
== EMBEDDED_PIC
)))
12591 /* Record the offset to the first reloc in the fr_opcode field.
12592 This lets md_convert_frag and tc_gen_reloc know that the code
12593 must be expanded. */
12594 fragp
->fr_opcode
= (fragp
->fr_literal
12596 - RELAX_OLD (fragp
->fr_subtype
)
12597 + RELAX_RELOC1 (fragp
->fr_subtype
));
12598 /* FIXME: This really needs as_warn_where. */
12599 if (RELAX_WARN (fragp
->fr_subtype
))
12600 as_warn (_("AT used after \".set noat\" or macro used after "
12601 "\".set nomacro\""));
12603 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12609 /* This is called to see whether a reloc against a defined symbol
12610 should be converted into a reloc against a section. Don't adjust
12611 MIPS16 jump relocations, so we don't have to worry about the format
12612 of the offset in the .o file. Don't adjust relocations against
12613 mips16 symbols, so that the linker can find them if it needs to set
12617 mips_fix_adjustable (fixp
)
12620 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12623 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12624 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12627 if (fixp
->fx_addsy
== NULL
)
12631 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12632 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12633 && fixp
->fx_subsy
== NULL
)
12640 /* Translate internal representation of relocation info to BFD target
12644 tc_gen_reloc (section
, fixp
)
12645 asection
*section ATTRIBUTE_UNUSED
;
12648 static arelent
*retval
[4];
12650 bfd_reloc_code_real_type code
;
12652 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12655 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12656 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12657 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12659 if (mips_pic
== EMBEDDED_PIC
12660 && SWITCH_TABLE (fixp
))
12662 /* For a switch table entry we use a special reloc. The addend
12663 is actually the difference between the reloc address and the
12665 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12666 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12667 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12668 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12670 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12672 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12673 reloc
->addend
= fixp
->fx_addnumber
;
12676 /* We use a special addend for an internal RELLO reloc. */
12677 if (symbol_section_p (fixp
->fx_addsy
))
12678 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12680 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12683 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12685 assert (fixp
->fx_next
!= NULL
12686 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12688 /* The reloc is relative to the RELLO; adjust the addend
12690 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12691 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12694 /* We use a special addend for an internal RELHI reloc. */
12695 if (symbol_section_p (fixp
->fx_addsy
))
12696 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12697 + fixp
->fx_next
->fx_where
12698 - S_GET_VALUE (fixp
->fx_subsy
));
12700 reloc
->addend
= (fixp
->fx_addnumber
12701 + fixp
->fx_next
->fx_frag
->fr_address
12702 + fixp
->fx_next
->fx_where
);
12705 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12706 reloc
->addend
= fixp
->fx_addnumber
;
12709 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12710 /* A gruesome hack which is a result of the gruesome gas reloc
12712 reloc
->addend
= reloc
->address
;
12714 reloc
->addend
= -reloc
->address
;
12717 /* If this is a variant frag, we may need to adjust the existing
12718 reloc and generate a new one. */
12719 if (fixp
->fx_frag
->fr_opcode
!= NULL
12720 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12722 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12723 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12724 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12725 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12726 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12727 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12732 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12734 /* If this is not the last reloc in this frag, then we have two
12735 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12736 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12737 the second one handle all of them. */
12738 if (fixp
->fx_next
!= NULL
12739 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12741 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12742 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12743 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12744 && (fixp
->fx_next
->fx_r_type
12745 == BFD_RELOC_MIPS_GOT_LO16
))
12746 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12747 && (fixp
->fx_next
->fx_r_type
12748 == BFD_RELOC_MIPS_CALL_LO16
)));
12753 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12754 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12755 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12757 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12758 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12759 reloc2
->address
= (reloc
->address
12760 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12761 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12762 reloc2
->addend
= fixp
->fx_addnumber
;
12763 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12764 assert (reloc2
->howto
!= NULL
);
12766 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12770 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12773 reloc3
->address
+= 4;
12776 if (mips_pic
== NO_PIC
)
12778 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12779 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12781 else if (mips_pic
== SVR4_PIC
)
12783 switch (fixp
->fx_r_type
)
12787 case BFD_RELOC_MIPS_GOT16
:
12789 case BFD_RELOC_MIPS_GOT_LO16
:
12790 case BFD_RELOC_MIPS_CALL_LO16
:
12791 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12793 case BFD_RELOC_MIPS_CALL16
:
12796 /* BFD_RELOC_MIPS_GOT16;*/
12797 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
12798 reloc2
->howto
= bfd_reloc_type_lookup
12799 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
12802 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12809 /* newabi uses R_MIPS_GOT_DISP for local symbols */
12810 if (HAVE_NEWABI
&& BFD_RELOC_MIPS_GOT_LO16
)
12812 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
12817 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12818 entry to be used in the relocation's section offset. */
12819 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12821 reloc
->address
= reloc
->addend
;
12825 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12826 fixup_segment converted a non-PC relative reloc into a PC
12827 relative reloc. In such a case, we need to convert the reloc
12829 code
= fixp
->fx_r_type
;
12830 if (fixp
->fx_pcrel
)
12835 code
= BFD_RELOC_8_PCREL
;
12838 code
= BFD_RELOC_16_PCREL
;
12841 code
= BFD_RELOC_32_PCREL
;
12844 code
= BFD_RELOC_64_PCREL
;
12846 case BFD_RELOC_8_PCREL
:
12847 case BFD_RELOC_16_PCREL
:
12848 case BFD_RELOC_32_PCREL
:
12849 case BFD_RELOC_64_PCREL
:
12850 case BFD_RELOC_16_PCREL_S2
:
12851 case BFD_RELOC_PCREL_HI16_S
:
12852 case BFD_RELOC_PCREL_LO16
:
12855 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12856 _("Cannot make %s relocation PC relative"),
12857 bfd_get_reloc_code_name (code
));
12862 /* md_apply_fix3 has a double-subtraction hack to get
12863 bfd_install_relocation to behave nicely. GPREL relocations are
12864 handled correctly without this hack, so undo it here. We can't
12865 stop md_apply_fix3 from subtracting twice in the first place since
12866 the fake addend is required for variant frags above. */
12867 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12868 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
12869 && reloc
->addend
!= 0
12870 && mips_need_elf_addend_fixup (fixp
))
12871 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12874 /* To support a PC relative reloc when generating embedded PIC code
12875 for ECOFF, we use a Cygnus extension. We check for that here to
12876 make sure that we don't let such a reloc escape normally. */
12877 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12878 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12879 && code
== BFD_RELOC_16_PCREL_S2
12880 && mips_pic
!= EMBEDDED_PIC
)
12881 reloc
->howto
= NULL
;
12883 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12885 if (reloc
->howto
== NULL
)
12887 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12888 _("Can not represent %s relocation in this object file format"),
12889 bfd_get_reloc_code_name (code
));
12896 /* Relax a machine dependent frag. This returns the amount by which
12897 the current size of the frag should change. */
12900 mips_relax_frag (fragp
, stretch
)
12904 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12907 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12909 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12911 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12916 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12918 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12925 /* Convert a machine dependent frag. */
12928 md_convert_frag (abfd
, asec
, fragp
)
12929 bfd
*abfd ATTRIBUTE_UNUSED
;
12936 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12939 register const struct mips16_immed_operand
*op
;
12940 boolean small
, ext
;
12943 unsigned long insn
;
12944 boolean use_extend
;
12945 unsigned short extend
;
12947 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12948 op
= mips16_immed_operands
;
12949 while (op
->type
!= type
)
12952 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12963 resolve_symbol_value (fragp
->fr_symbol
);
12964 val
= S_GET_VALUE (fragp
->fr_symbol
);
12969 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12971 /* The rules for the base address of a PC relative reloc are
12972 complicated; see mips16_extended_frag. */
12973 if (type
== 'p' || type
== 'q')
12978 /* Ignore the low bit in the target, since it will be
12979 set for a text label. */
12980 if ((val
& 1) != 0)
12983 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12985 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12988 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12991 /* Make sure the section winds up with the alignment we have
12994 record_alignment (asec
, op
->shift
);
12998 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12999 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13000 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13001 _("extended instruction in delay slot"));
13003 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13005 if (target_big_endian
)
13006 insn
= bfd_getb16 (buf
);
13008 insn
= bfd_getl16 (buf
);
13010 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13011 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13012 small
, ext
, &insn
, &use_extend
, &extend
);
13016 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13017 fragp
->fr_fix
+= 2;
13021 md_number_to_chars ((char *) buf
, insn
, 2);
13022 fragp
->fr_fix
+= 2;
13027 if (fragp
->fr_opcode
== NULL
)
13030 old
= RELAX_OLD (fragp
->fr_subtype
);
13031 new = RELAX_NEW (fragp
->fr_subtype
);
13032 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13035 memcpy (fixptr
- old
, fixptr
, new);
13037 fragp
->fr_fix
+= new - old
;
13043 /* This function is called after the relocs have been generated.
13044 We've been storing mips16 text labels as odd. Here we convert them
13045 back to even for the convenience of the debugger. */
13048 mips_frob_file_after_relocs ()
13051 unsigned int count
, i
;
13053 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13056 syms
= bfd_get_outsymbols (stdoutput
);
13057 count
= bfd_get_symcount (stdoutput
);
13058 for (i
= 0; i
< count
; i
++, syms
++)
13060 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13061 && ((*syms
)->value
& 1) != 0)
13063 (*syms
)->value
&= ~1;
13064 /* If the symbol has an odd size, it was probably computed
13065 incorrectly, so adjust that as well. */
13066 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13067 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13074 /* This function is called whenever a label is defined. It is used
13075 when handling branch delays; if a branch has a label, we assume we
13076 can not move it. */
13079 mips_define_label (sym
)
13082 struct insn_label_list
*l
;
13084 if (free_insn_labels
== NULL
)
13085 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13088 l
= free_insn_labels
;
13089 free_insn_labels
= l
->next
;
13093 l
->next
= insn_labels
;
13097 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13099 /* Some special processing for a MIPS ELF file. */
13102 mips_elf_final_processing ()
13104 /* Write out the register information. */
13105 if (mips_abi
!= N64_ABI
)
13109 s
.ri_gprmask
= mips_gprmask
;
13110 s
.ri_cprmask
[0] = mips_cprmask
[0];
13111 s
.ri_cprmask
[1] = mips_cprmask
[1];
13112 s
.ri_cprmask
[2] = mips_cprmask
[2];
13113 s
.ri_cprmask
[3] = mips_cprmask
[3];
13114 /* The gp_value field is set by the MIPS ELF backend. */
13116 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13117 ((Elf32_External_RegInfo
*)
13118 mips_regmask_frag
));
13122 Elf64_Internal_RegInfo s
;
13124 s
.ri_gprmask
= mips_gprmask
;
13126 s
.ri_cprmask
[0] = mips_cprmask
[0];
13127 s
.ri_cprmask
[1] = mips_cprmask
[1];
13128 s
.ri_cprmask
[2] = mips_cprmask
[2];
13129 s
.ri_cprmask
[3] = mips_cprmask
[3];
13130 /* The gp_value field is set by the MIPS ELF backend. */
13132 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13133 ((Elf64_External_RegInfo
*)
13134 mips_regmask_frag
));
13137 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13138 sort of BFD interface for this. */
13139 if (mips_any_noreorder
)
13140 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13141 if (mips_pic
!= NO_PIC
)
13142 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13144 /* Set MIPS ELF flags for ASEs. */
13145 if (file_ase_mips16
)
13146 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13147 #if 0 /* XXX FIXME */
13148 if (file_ase_mips3d
)
13149 elf_elfheader (stdoutput
)->e_flags
|= ???;
13152 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13154 /* Set the MIPS ELF ABI flags. */
13155 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13156 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13157 else if (mips_abi
== O64_ABI
)
13158 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13159 else if (mips_abi
== EABI_ABI
)
13161 if (!file_mips_gp32
)
13162 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13164 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13166 else if (mips_abi
== N32_ABI
)
13167 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13169 /* Nothing to do for N64_ABI. */
13171 if (mips_32bitmode
)
13172 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13175 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13177 typedef struct proc
{
13179 unsigned long reg_mask
;
13180 unsigned long reg_offset
;
13181 unsigned long fpreg_mask
;
13182 unsigned long fpreg_offset
;
13183 unsigned long frame_offset
;
13184 unsigned long frame_reg
;
13185 unsigned long pc_reg
;
13188 static procS cur_proc
;
13189 static procS
*cur_proc_ptr
;
13190 static int numprocs
;
13192 /* Fill in an rs_align_code fragment. */
13195 mips_handle_align (fragp
)
13198 if (fragp
->fr_type
!= rs_align_code
)
13201 if (mips_opts
.mips16
)
13203 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13204 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13209 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13210 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13218 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13222 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13233 /* check for premature end, nesting errors, etc */
13235 as_warn (_("missing .end at end of assembly"));
13244 if (*input_line_pointer
== '-')
13246 ++input_line_pointer
;
13249 if (!ISDIGIT (*input_line_pointer
))
13250 as_bad (_("expected simple number"));
13251 if (input_line_pointer
[0] == '0')
13253 if (input_line_pointer
[1] == 'x')
13255 input_line_pointer
+= 2;
13256 while (ISXDIGIT (*input_line_pointer
))
13259 val
|= hex_value (*input_line_pointer
++);
13261 return negative
? -val
: val
;
13265 ++input_line_pointer
;
13266 while (ISDIGIT (*input_line_pointer
))
13269 val
|= *input_line_pointer
++ - '0';
13271 return negative
? -val
: val
;
13274 if (!ISDIGIT (*input_line_pointer
))
13276 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13277 *input_line_pointer
, *input_line_pointer
);
13278 as_warn (_("invalid number"));
13281 while (ISDIGIT (*input_line_pointer
))
13284 val
+= *input_line_pointer
++ - '0';
13286 return negative
? -val
: val
;
13289 /* The .file directive; just like the usual .file directive, but there
13290 is an initial number which is the ECOFF file index. In the non-ECOFF
13291 case .file implies DWARF-2. */
13295 int x ATTRIBUTE_UNUSED
;
13297 static int first_file_directive
= 0;
13299 if (ECOFF_DEBUGGING
)
13308 filename
= dwarf2_directive_file (0);
13310 /* Versions of GCC up to 3.1 start files with a ".file"
13311 directive even for stabs output. Make sure that this
13312 ".file" is handled. Note that you need a version of GCC
13313 after 3.1 in order to support DWARF-2 on MIPS. */
13314 if (filename
!= NULL
&& ! first_file_directive
)
13316 (void) new_logical_line (filename
, -1);
13317 s_app_file_string (filename
);
13319 first_file_directive
= 1;
13323 /* The .loc directive, implying DWARF-2. */
13327 int x ATTRIBUTE_UNUSED
;
13329 if (!ECOFF_DEBUGGING
)
13330 dwarf2_directive_loc (0);
13333 /* The .end directive. */
13337 int x ATTRIBUTE_UNUSED
;
13342 /* Following functions need their own .frame and .cprestore directives. */
13343 mips_frame_reg_valid
= 0;
13344 mips_cprestore_valid
= 0;
13346 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13349 demand_empty_rest_of_line ();
13354 #ifdef BFD_ASSEMBLER
13355 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13360 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13367 as_warn (_(".end not in text section"));
13371 as_warn (_(".end directive without a preceding .ent directive."));
13372 demand_empty_rest_of_line ();
13378 assert (S_GET_NAME (p
));
13379 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13380 as_warn (_(".end symbol does not match .ent symbol."));
13382 if (debug_type
== DEBUG_STABS
)
13383 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13387 as_warn (_(".end directive missing or unknown symbol"));
13390 /* Generate a .pdr section. */
13391 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13393 segT saved_seg
= now_seg
;
13394 subsegT saved_subseg
= now_subseg
;
13399 dot
= frag_now_fix ();
13401 #ifdef md_flush_pending_output
13402 md_flush_pending_output ();
13406 subseg_set (pdr_seg
, 0);
13408 /* Write the symbol. */
13409 exp
.X_op
= O_symbol
;
13410 exp
.X_add_symbol
= p
;
13411 exp
.X_add_number
= 0;
13412 emit_expr (&exp
, 4);
13414 fragp
= frag_more (7 * 4);
13416 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13417 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13418 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13419 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13420 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13421 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13422 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13424 subseg_set (saved_seg
, saved_subseg
);
13426 #endif /* OBJ_ELF */
13428 cur_proc_ptr
= NULL
;
13431 /* The .aent and .ent directives. */
13440 symbolP
= get_symbol ();
13441 if (*input_line_pointer
== ',')
13442 ++input_line_pointer
;
13443 SKIP_WHITESPACE ();
13444 if (ISDIGIT (*input_line_pointer
)
13445 || *input_line_pointer
== '-')
13448 #ifdef BFD_ASSEMBLER
13449 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13454 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13461 as_warn (_(".ent or .aent not in text section."));
13463 if (!aent
&& cur_proc_ptr
)
13464 as_warn (_("missing .end"));
13468 /* This function needs its own .frame and .cprestore directives. */
13469 mips_frame_reg_valid
= 0;
13470 mips_cprestore_valid
= 0;
13472 cur_proc_ptr
= &cur_proc
;
13473 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13475 cur_proc_ptr
->isym
= symbolP
;
13477 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13481 if (debug_type
== DEBUG_STABS
)
13482 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13483 S_GET_NAME (symbolP
));
13486 demand_empty_rest_of_line ();
13489 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13490 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13491 s_mips_frame is used so that we can set the PDR information correctly.
13492 We can't use the ecoff routines because they make reference to the ecoff
13493 symbol table (in the mdebug section). */
13496 s_mips_frame (ignore
)
13497 int ignore ATTRIBUTE_UNUSED
;
13500 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13504 if (cur_proc_ptr
== (procS
*) NULL
)
13506 as_warn (_(".frame outside of .ent"));
13507 demand_empty_rest_of_line ();
13511 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13513 SKIP_WHITESPACE ();
13514 if (*input_line_pointer
++ != ','
13515 || get_absolute_expression_and_terminator (&val
) != ',')
13517 as_warn (_("Bad .frame directive"));
13518 --input_line_pointer
;
13519 demand_empty_rest_of_line ();
13523 cur_proc_ptr
->frame_offset
= val
;
13524 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13526 demand_empty_rest_of_line ();
13529 #endif /* OBJ_ELF */
13533 /* The .fmask and .mask directives. If the mdebug section is present
13534 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13535 embedded targets, s_mips_mask is used so that we can set the PDR
13536 information correctly. We can't use the ecoff routines because they
13537 make reference to the ecoff symbol table (in the mdebug section). */
13540 s_mips_mask (reg_type
)
13544 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13548 if (cur_proc_ptr
== (procS
*) NULL
)
13550 as_warn (_(".mask/.fmask outside of .ent"));
13551 demand_empty_rest_of_line ();
13555 if (get_absolute_expression_and_terminator (&mask
) != ',')
13557 as_warn (_("Bad .mask/.fmask directive"));
13558 --input_line_pointer
;
13559 demand_empty_rest_of_line ();
13563 off
= get_absolute_expression ();
13565 if (reg_type
== 'F')
13567 cur_proc_ptr
->fpreg_mask
= mask
;
13568 cur_proc_ptr
->fpreg_offset
= off
;
13572 cur_proc_ptr
->reg_mask
= mask
;
13573 cur_proc_ptr
->reg_offset
= off
;
13576 demand_empty_rest_of_line ();
13579 #endif /* OBJ_ELF */
13580 s_ignore (reg_type
);
13583 /* The .loc directive. */
13594 assert (now_seg
== text_section
);
13596 lineno
= get_number ();
13597 addroff
= frag_now_fix ();
13599 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13600 S_SET_TYPE (symbolP
, N_SLINE
);
13601 S_SET_OTHER (symbolP
, 0);
13602 S_SET_DESC (symbolP
, lineno
);
13603 symbolP
->sy_segment
= now_seg
;
13607 /* A table describing all the processors gas knows about. Names are
13608 matched in the order listed.
13610 To ease comparison, please keep this table in the same order as
13611 gcc's mips_cpu_info_table[]. */
13612 static const struct mips_cpu_info mips_cpu_info_table
[] =
13614 /* Entries for generic ISAs */
13615 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13616 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13617 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13618 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13619 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13620 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13621 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13624 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13625 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13626 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13629 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13632 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13633 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13634 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13635 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13636 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13637 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13638 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13639 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13640 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13643 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13644 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13645 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13646 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13647 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13648 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13649 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13650 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13651 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13652 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
13655 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13656 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13657 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13660 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13661 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13663 /* Broadcom SB-1 CPU core */
13664 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13671 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13672 with a final "000" replaced by "k". Ignore case.
13674 Note: this function is shared between GCC and GAS. */
13677 mips_strict_matching_cpu_name_p (canonical
, given
)
13678 const char *canonical
, *given
;
13680 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13681 given
++, canonical
++;
13683 return ((*given
== 0 && *canonical
== 0)
13684 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13688 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13689 CPU name. We've traditionally allowed a lot of variation here.
13691 Note: this function is shared between GCC and GAS. */
13694 mips_matching_cpu_name_p (canonical
, given
)
13695 const char *canonical
, *given
;
13697 /* First see if the name matches exactly, or with a final "000"
13698 turned into "k". */
13699 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13702 /* If not, try comparing based on numerical designation alone.
13703 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13704 if (TOLOWER (*given
) == 'r')
13706 if (!ISDIGIT (*given
))
13709 /* Skip over some well-known prefixes in the canonical name,
13710 hoping to find a number there too. */
13711 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13713 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13715 else if (TOLOWER (canonical
[0]) == 'r')
13718 return mips_strict_matching_cpu_name_p (canonical
, given
);
13722 /* Parse an option that takes the name of a processor as its argument.
13723 OPTION is the name of the option and CPU_STRING is the argument.
13724 Return the corresponding processor enumeration if the CPU_STRING is
13725 recognized, otherwise report an error and return null.
13727 A similar function exists in GCC. */
13729 static const struct mips_cpu_info
*
13730 mips_parse_cpu (option
, cpu_string
)
13731 const char *option
, *cpu_string
;
13733 const struct mips_cpu_info
*p
;
13735 /* 'from-abi' selects the most compatible architecture for the given
13736 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13737 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13738 version. Look first at the -mgp options, if given, otherwise base
13739 the choice on MIPS_DEFAULT_64BIT.
13741 Treat NO_ABI like the EABIs. One reason to do this is that the
13742 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13743 architecture. This code picks MIPS I for 'mips' and MIPS III for
13744 'mips64', just as we did in the days before 'from-abi'. */
13745 if (strcasecmp (cpu_string
, "from-abi") == 0)
13747 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13748 return mips_cpu_info_from_isa (ISA_MIPS1
);
13750 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13751 return mips_cpu_info_from_isa (ISA_MIPS3
);
13753 if (file_mips_gp32
>= 0)
13754 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13756 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13761 /* 'default' has traditionally been a no-op. Probably not very useful. */
13762 if (strcasecmp (cpu_string
, "default") == 0)
13765 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13766 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13769 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13773 /* Return the canonical processor information for ISA (a member of the
13774 ISA_MIPS* enumeration). */
13776 static const struct mips_cpu_info
*
13777 mips_cpu_info_from_isa (isa
)
13782 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13783 if (mips_cpu_info_table
[i
].is_isa
13784 && isa
== mips_cpu_info_table
[i
].isa
)
13785 return (&mips_cpu_info_table
[i
]);
13791 show (stream
, string
, col_p
, first_p
)
13793 const char *string
;
13799 fprintf (stream
, "%24s", "");
13804 fprintf (stream
, ", ");
13808 if (*col_p
+ strlen (string
) > 72)
13810 fprintf (stream
, "\n%24s", "");
13814 fprintf (stream
, "%s", string
);
13815 *col_p
+= strlen (string
);
13821 md_show_usage (stream
)
13827 fprintf (stream
, _("\
13829 -membedded-pic generate embedded position independent code\n\
13830 -EB generate big endian output\n\
13831 -EL generate little endian output\n\
13832 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13833 -G NUM allow referencing objects up to NUM bytes\n\
13834 implicitly with the gp register [default 8]\n"));
13835 fprintf (stream
, _("\
13836 -mips1 generate MIPS ISA I instructions\n\
13837 -mips2 generate MIPS ISA II instructions\n\
13838 -mips3 generate MIPS ISA III instructions\n\
13839 -mips4 generate MIPS ISA IV instructions\n\
13840 -mips5 generate MIPS ISA V instructions\n\
13841 -mips32 generate MIPS32 ISA instructions\n\
13842 -mips64 generate MIPS64 ISA instructions\n\
13843 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13847 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13848 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13849 show (stream
, "from-abi", &column
, &first
);
13850 fputc ('\n', stream
);
13852 fprintf (stream
, _("\
13853 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13854 -no-mCPU don't generate code specific to CPU.\n\
13855 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13859 show (stream
, "3900", &column
, &first
);
13860 show (stream
, "4010", &column
, &first
);
13861 show (stream
, "4100", &column
, &first
);
13862 show (stream
, "4650", &column
, &first
);
13863 fputc ('\n', stream
);
13865 fprintf (stream
, _("\
13866 -mips16 generate mips16 instructions\n\
13867 -no-mips16 do not generate mips16 instructions\n"));
13868 fprintf (stream
, _("\
13869 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13870 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13871 -O0 remove unneeded NOPs, do not swap branches\n\
13872 -O remove unneeded NOPs and swap branches\n\
13873 -n warn about NOPs generated from macros\n\
13874 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13875 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13876 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13878 fprintf (stream
, _("\
13879 -KPIC, -call_shared generate SVR4 position independent code\n\
13880 -non_shared do not generate position independent code\n\
13881 -xgot assume a 32 bit GOT\n\
13882 -mabi=ABI create ABI conformant object file for:\n"));
13886 show (stream
, "32", &column
, &first
);
13887 show (stream
, "o64", &column
, &first
);
13888 show (stream
, "n32", &column
, &first
);
13889 show (stream
, "64", &column
, &first
);
13890 show (stream
, "eabi", &column
, &first
);
13892 fputc ('\n', stream
);
13894 fprintf (stream
, _("\
13895 -32 create o32 ABI object file (default)\n\
13896 -n32 create n32 ABI object file\n\
13897 -64 create 64 ABI object file\n"));