1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_elf_flavour
:
122 return (target_big_endian
123 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
124 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
131 /* The name of the readonly data section. */
132 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
134 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
136 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
140 /* This is the set of options which may be modified by the .set
141 pseudo-op. We use a struct so that .set push and .set pop are more
144 struct mips_set_options
146 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
147 if it has not been initialized. Changed by `.set mipsN', and the
148 -mipsN command line option, and the default CPU. */
150 /* Whether we are assembling for the mips16 processor. 0 if we are
151 not, 1 if we are, and -1 if the value has not been initialized.
152 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
153 -nomips16 command line options, and the default CPU. */
155 /* Non-zero if we should not reorder instructions. Changed by `.set
156 reorder' and `.set noreorder'. */
158 /* Non-zero if we should not permit the $at ($1) register to be used
159 in instructions. Changed by `.set at' and `.set noat'. */
161 /* Non-zero if we should warn when a macro instruction expands into
162 more than one machine instruction. Changed by `.set nomacro' and
164 int warn_about_macros
;
165 /* Non-zero if we should not move instructions. Changed by `.set
166 move', `.set volatile', `.set nomove', and `.set novolatile'. */
168 /* Non-zero if we should not optimize branches by moving the target
169 of the branch into the delay slot. Actually, we don't perform
170 this optimization anyhow. Changed by `.set bopt' and `.set
173 /* Non-zero if we should not autoextend mips16 instructions.
174 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* This is the struct we use to hold the current set of options. Note
179 that we must set the isa and mips16 fields to -1 to indicate that
180 they have not been initialized. */
182 static struct mips_set_options mips_opts
= { -1, -1 };
184 /* These variables are filled in with the masks of registers used.
185 The object format code reads them and puts them in the appropriate
187 unsigned long mips_gprmask
;
188 unsigned long mips_cprmask
[4];
190 /* MIPS ISA we are using for this output file. */
191 static int file_mips_isa
;
193 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
194 static int mips_cpu
= -1;
196 /* The argument of the -mabi= flag. */
197 static char* mips_abi_string
= 0;
199 /* Wether we should mark the file EABI64 or EABI32. */
200 static int mips_eabi64
= 0;
202 /* If they asked for mips1 or mips2 and a cpu that is
203 mips3 or greater, then mark the object file 32BITMODE. */
204 static int mips_32bitmode
= 0;
206 /* Some ISA's have delay slots for instructions which read or write
207 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
208 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
209 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
210 delay slot in this ISA. The uses of this macro assume that any
211 ISA that has delay slots for one of these, has them for all. They
212 also assume that ISAs which don't have delays for these insns, don't
213 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
214 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
220 /* Return true if ISA supports 64 bit gp register instructions. */
221 #define ISA_HAS_64BIT_REGS(ISA) ( \
226 /* Whether the processor uses hardware interlocks to protect
227 reads from the HI and LO registers, and thus does not
228 require nops to be inserted.
230 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
231 -mcpu=FOO schedules for FOO, but still produces code that meets the
232 requirements of MIPS ISA I. For example, it won't generate any
233 FOO-specific instructions, and it will still assume that any
234 scheduling hazards described in MIPS ISA I are there, even if FOO
235 has interlocks. -mFOO gives GCC permission to generate code that
236 will only run on a FOO; it will generate FOO-specific instructions,
237 and assume interlocks provided by a FOO.
239 However, GAS currently doesn't make this distinction; before Jan 28
240 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
241 assumptions. The GCC driver passes these flags through to GAS, so
242 if GAS actually does anything that doesn't meet MIPS ISA I with
243 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
245 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
246 which seems senseless --- why generate code which will only run on
247 a FOO, but schedule for something else?
249 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
251 -- Jim Blandy <jimb@cygnus.com> */
253 #define hilo_interlocks (mips_cpu == 4010 \
256 /* Whether the processor uses hardware interlocks to protect reads
257 from the GPRs, and thus does not require nops to be inserted. */
258 #define gpr_interlocks \
259 (mips_opts.isa != 1 \
262 /* As with other "interlocks" this is used by hardware that has FP
263 (co-processor) interlocks. */
264 /* Itbl support may require additional care here. */
265 #define cop_interlocks (mips_cpu == 4300 \
268 /* MIPS PIC level. */
272 /* Do not generate PIC code. */
275 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
276 not sure what it is supposed to do. */
279 /* Generate PIC code as in the SVR4 MIPS ABI. */
282 /* Generate PIC code without using a global offset table: the data
283 segment has a maximum size of 64K, all data references are off
284 the $gp register, and all text references are PC relative. This
285 is used on some embedded systems. */
289 static enum mips_pic_level mips_pic
;
291 /* 1 if we should generate 32 bit offsets from the GP register in
292 SVR4_PIC mode. Currently has no meaning in other modes. */
293 static int mips_big_got
;
295 /* 1 if trap instructions should used for overflow rather than break
297 static int mips_trap
;
299 /* Non-zero if any .set noreorder directives were used. */
301 static int mips_any_noreorder
;
303 /* The size of the small data section. */
304 static int g_switch_value
= 8;
305 /* Whether the -G option was used. */
306 static int g_switch_seen
= 0;
311 /* If we can determine in advance that GP optimization won't be
312 possible, we can skip the relaxation stuff that tries to produce
313 GP-relative references. This makes delay slot optimization work
316 This function can only provide a guess, but it seems to work for
317 gcc output. It needs to guess right for gcc, otherwise gcc
318 will put what it thinks is a GP-relative instruction in a branch
321 I don't know if a fix is needed for the SVR4_PIC mode. I've only
322 fixed it for the non-PIC mode. KR 95/04/07 */
323 static int nopic_need_relax
PARAMS ((symbolS
*, int));
325 /* handle of the OPCODE hash table */
326 static struct hash_control
*op_hash
= NULL
;
328 /* The opcode hash table we use for the mips16. */
329 static struct hash_control
*mips16_op_hash
= NULL
;
331 /* This array holds the chars that always start a comment. If the
332 pre-processor is disabled, these aren't very useful */
333 const char comment_chars
[] = "#";
335 /* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
337 .line and .file directives will appear in the pre-processed output */
338 /* Note that input_file.c hand checks for '#' at the beginning of the
339 first line of the input file. This is because the compiler outputs
340 #NO_APP at the beginning of its output. */
341 /* Also note that C style comments are always supported. */
342 const char line_comment_chars
[] = "#";
344 /* This array holds machine specific line separator characters. */
345 const char line_separator_chars
[] = "";
347 /* Chars that can be used to separate mant from exp in floating point nums */
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant */
353 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
355 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
356 changed in read.c . Ideally it shouldn't have to know about it at all,
357 but nothing is ideal around here.
360 static char *insn_error
;
362 static int auto_align
= 1;
364 /* When outputting SVR4 PIC code, the assembler needs to know the
365 offset in the stack frame from which to restore the $gp register.
366 This is set by the .cprestore pseudo-op, and saved in this
368 static offsetT mips_cprestore_offset
= -1;
370 /* This is the register which holds the stack frame, as set by the
371 .frame pseudo-op. This is needed to implement .cprestore. */
372 static int mips_frame_reg
= SP
;
374 /* To output NOP instructions correctly, we need to keep information
375 about the previous two instructions. */
377 /* Whether we are optimizing. The default value of 2 means to remove
378 unneeded NOPs and swap branch instructions when possible. A value
379 of 1 means to not swap branches. A value of 0 means to always
381 static int mips_optimize
= 2;
383 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
384 equivalent to seeing no -g option at all. */
385 static int mips_debug
= 0;
387 /* The previous instruction. */
388 static struct mips_cl_insn prev_insn
;
390 /* The instruction before prev_insn. */
391 static struct mips_cl_insn prev_prev_insn
;
393 /* If we don't want information for prev_insn or prev_prev_insn, we
394 point the insn_mo field at this dummy integer. */
395 static const struct mips_opcode dummy_opcode
= { 0 };
397 /* Non-zero if prev_insn is valid. */
398 static int prev_insn_valid
;
400 /* The frag for the previous instruction. */
401 static struct frag
*prev_insn_frag
;
403 /* The offset into prev_insn_frag for the previous instruction. */
404 static long prev_insn_where
;
406 /* The reloc type for the previous instruction, if any. */
407 static bfd_reloc_code_real_type prev_insn_reloc_type
;
409 /* The reloc for the previous instruction, if any. */
410 static fixS
*prev_insn_fixp
;
412 /* Non-zero if the previous instruction was in a delay slot. */
413 static int prev_insn_is_delay_slot
;
415 /* Non-zero if the previous instruction was in a .set noreorder. */
416 static int prev_insn_unreordered
;
418 /* Non-zero if the previous instruction uses an extend opcode (if
420 static int prev_insn_extended
;
422 /* Non-zero if the previous previous instruction was in a .set
424 static int prev_prev_insn_unreordered
;
426 /* If this is set, it points to a frag holding nop instructions which
427 were inserted before the start of a noreorder section. If those
428 nops turn out to be unnecessary, the size of the frag can be
430 static fragS
*prev_nop_frag
;
432 /* The number of nop instructions we created in prev_nop_frag. */
433 static int prev_nop_frag_holds
;
435 /* The number of nop instructions that we know we need in
437 static int prev_nop_frag_required
;
439 /* The number of instructions we've seen since prev_nop_frag. */
440 static int prev_nop_frag_since
;
442 /* For ECOFF and ELF, relocations against symbols are done in two
443 parts, with a HI relocation and a LO relocation. Each relocation
444 has only 16 bits of space to store an addend. This means that in
445 order for the linker to handle carries correctly, it must be able
446 to locate both the HI and the LO relocation. This means that the
447 relocations must appear in order in the relocation table.
449 In order to implement this, we keep track of each unmatched HI
450 relocation. We then sort them so that they immediately precede the
451 corresponding LO relocation. */
456 struct mips_hi_fixup
*next
;
459 /* The section this fixup is in. */
463 /* The list of unmatched HI relocs. */
465 static struct mips_hi_fixup
*mips_hi_fixup_list
;
467 /* Map normal MIPS register numbers to mips16 register numbers. */
469 #define X ILLEGAL_REG
470 static const int mips32_to_16_reg_map
[] =
472 X
, X
, 2, 3, 4, 5, 6, 7,
473 X
, X
, X
, X
, X
, X
, X
, X
,
474 0, 1, X
, X
, X
, X
, X
, X
,
475 X
, X
, X
, X
, X
, X
, X
, X
479 /* Map mips16 register numbers to normal MIPS register numbers. */
481 static const int mips16_to_32_reg_map
[] =
483 16, 17, 2, 3, 4, 5, 6, 7
486 /* Since the MIPS does not have multiple forms of PC relative
487 instructions, we do not have to do relaxing as is done on other
488 platforms. However, we do have to handle GP relative addressing
489 correctly, which turns out to be a similar problem.
491 Every macro that refers to a symbol can occur in (at least) two
492 forms, one with GP relative addressing and one without. For
493 example, loading a global variable into a register generally uses
494 a macro instruction like this:
496 If i can be addressed off the GP register (this is true if it is in
497 the .sbss or .sdata section, or if it is known to be smaller than
498 the -G argument) this will generate the following instruction:
500 This instruction will use a GPREL reloc. If i can not be addressed
501 off the GP register, the following instruction sequence will be used:
504 In this case the first instruction will have a HI16 reloc, and the
505 second reloc will have a LO16 reloc. Both relocs will be against
508 The issue here is that we may not know whether i is GP addressable
509 until after we see the instruction that uses it. Therefore, we
510 want to be able to choose the final instruction sequence only at
511 the end of the assembly. This is similar to the way other
512 platforms choose the size of a PC relative instruction only at the
515 When generating position independent code we do not use GP
516 addressing in quite the same way, but the issue still arises as
517 external symbols and local symbols must be handled differently.
519 We handle these issues by actually generating both possible
520 instruction sequences. The longer one is put in a frag_var with
521 type rs_machine_dependent. We encode what to do with the frag in
522 the subtype field. We encode (1) the number of existing bytes to
523 replace, (2) the number of new bytes to use, (3) the offset from
524 the start of the existing bytes to the first reloc we must generate
525 (that is, the offset is applied from the start of the existing
526 bytes after they are replaced by the new bytes, if any), (4) the
527 offset from the start of the existing bytes to the second reloc,
528 (5) whether a third reloc is needed (the third reloc is always four
529 bytes after the second reloc), and (6) whether to warn if this
530 variant is used (this is sometimes needed if .set nomacro or .set
531 noat is in effect). All these numbers are reasonably small.
533 Generating two instruction sequences must be handled carefully to
534 ensure that delay slots are handled correctly. Fortunately, there
535 are a limited number of cases. When the second instruction
536 sequence is generated, append_insn is directed to maintain the
537 existing delay slot information, so it continues to apply to any
538 code after the second instruction sequence. This means that the
539 second instruction sequence must not impose any requirements not
540 required by the first instruction sequence.
542 These variant frags are then handled in functions called by the
543 machine independent code. md_estimate_size_before_relax returns
544 the final size of the frag. md_convert_frag sets up the final form
545 of the frag. tc_gen_reloc adjust the first reloc and adds a second
547 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
551 | (((reloc1) + 64) << 9) \
552 | (((reloc2) + 64) << 2) \
553 | ((reloc3) ? (1 << 1) : 0) \
555 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
556 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
557 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
558 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
559 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
560 #define RELAX_WARN(i) ((i) & 1)
562 /* For mips16 code, we use an entirely different form of relaxation.
563 mips16 supports two versions of most instructions which take
564 immediate values: a small one which takes some small value, and a
565 larger one which takes a 16 bit value. Since branches also follow
566 this pattern, relaxing these values is required.
568 We can assemble both mips16 and normal MIPS code in a single
569 object. Therefore, we need to support this type of relaxation at
570 the same time that we support the relaxation described above. We
571 use the high bit of the subtype field to distinguish these cases.
573 The information we store for this type of relaxation is the
574 argument code found in the opcode file for this relocation, whether
575 the user explicitly requested a small or extended form, and whether
576 the relocation is in a jump or jal delay slot. That tells us the
577 size of the value, and how it should be stored. We also store
578 whether the fragment is considered to be extended or not. We also
579 store whether this is known to be a branch to a different section,
580 whether we have tried to relax this frag yet, and whether we have
581 ever extended a PC relative fragment because of a shift count. */
582 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
585 | ((small) ? 0x100 : 0) \
586 | ((ext) ? 0x200 : 0) \
587 | ((dslot) ? 0x400 : 0) \
588 | ((jal_dslot) ? 0x800 : 0))
589 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
590 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
591 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
592 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
593 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
594 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
595 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
596 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
597 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
598 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
599 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
600 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
602 /* Prototypes for static functions. */
605 #define internalError() \
606 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
608 #define internalError() as_fatal (_("MIPS internal Error"));
611 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
613 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
614 unsigned int reg
, enum mips_regclass
class));
615 static int reg_needs_delay
PARAMS ((int));
616 static void mips16_mark_labels
PARAMS ((void));
617 static void append_insn
PARAMS ((char *place
,
618 struct mips_cl_insn
* ip
,
620 bfd_reloc_code_real_type r
,
622 static void mips_no_prev_insn
PARAMS ((int));
623 static void mips_emit_delays
PARAMS ((boolean
));
625 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
626 const char *name
, const char *fmt
,
629 static void macro_build ();
631 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
632 const char *, const char *,
634 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
635 expressionS
* ep
, int regnum
));
636 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
637 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
639 static void load_register
PARAMS ((int *, int, expressionS
*, int));
640 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
641 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
642 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
643 #ifdef LOSING_COMPILER
644 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
646 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
647 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
648 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
649 boolean
, boolean
, unsigned long *,
650 boolean
*, unsigned short *));
651 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
652 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
653 static symbolS
*get_symbol
PARAMS ((void));
654 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
655 static void s_align
PARAMS ((int));
656 static void s_change_sec
PARAMS ((int));
657 static void s_cons
PARAMS ((int));
658 static void s_float_cons
PARAMS ((int));
659 static void s_mips_globl
PARAMS ((int));
660 static void s_option
PARAMS ((int));
661 static void s_mipsset
PARAMS ((int));
662 static void s_abicalls
PARAMS ((int));
663 static void s_cpload
PARAMS ((int));
664 static void s_cprestore
PARAMS ((int));
665 static void s_gpword
PARAMS ((int));
666 static void s_cpadd
PARAMS ((int));
667 static void s_insn
PARAMS ((int));
668 static void md_obj_begin
PARAMS ((void));
669 static void md_obj_end
PARAMS ((void));
670 static long get_number
PARAMS ((void));
671 static void s_mips_ent
PARAMS ((int));
672 static void s_mips_end
PARAMS ((int));
673 static void s_mips_frame
PARAMS ((int));
674 static void s_mips_mask
PARAMS ((int));
675 static void s_mips_stab
PARAMS ((int));
676 static void s_mips_weakext
PARAMS ((int));
677 static void s_file
PARAMS ((int));
678 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
681 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
685 The following pseudo-ops from the Kane and Heinrich MIPS book
686 should be defined here, but are currently unsupported: .alias,
687 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
689 The following pseudo-ops from the Kane and Heinrich MIPS book are
690 specific to the type of debugging information being generated, and
691 should be defined by the object format: .aent, .begin, .bend,
692 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
695 The following pseudo-ops from the Kane and Heinrich MIPS book are
696 not MIPS CPU specific, but are also not specific to the object file
697 format. This file is probably the best place to define them, but
698 they are not currently supported: .asm0, .endr, .lab, .repeat,
701 static const pseudo_typeS mips_pseudo_table
[] =
703 /* MIPS specific pseudo-ops. */
704 {"option", s_option
, 0},
705 {"set", s_mipsset
, 0},
706 {"rdata", s_change_sec
, 'r'},
707 {"sdata", s_change_sec
, 's'},
708 {"livereg", s_ignore
, 0},
709 {"abicalls", s_abicalls
, 0},
710 {"cpload", s_cpload
, 0},
711 {"cprestore", s_cprestore
, 0},
712 {"gpword", s_gpword
, 0},
713 {"cpadd", s_cpadd
, 0},
716 /* Relatively generic pseudo-ops that happen to be used on MIPS
718 {"asciiz", stringer
, 1},
719 {"bss", s_change_sec
, 'b'},
722 {"dword", s_cons
, 3},
723 {"weakext", s_mips_weakext
, 0},
725 /* These pseudo-ops are defined in read.c, but must be overridden
726 here for one reason or another. */
727 {"align", s_align
, 0},
729 {"data", s_change_sec
, 'd'},
730 {"double", s_float_cons
, 'd'},
731 {"float", s_float_cons
, 'f'},
732 {"globl", s_mips_globl
, 0},
733 {"global", s_mips_globl
, 0},
734 {"hword", s_cons
, 1},
739 {"short", s_cons
, 1},
740 {"single", s_float_cons
, 'f'},
741 {"stabn", s_mips_stab
, 'n'},
742 {"text", s_change_sec
, 't'},
747 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
748 /* These pseudo-ops should be defined by the object file format.
749 However, a.out doesn't support them, so we have versions here. */
750 {"aent", s_mips_ent
, 1},
751 {"bgnb", s_ignore
, 0},
752 {"end", s_mips_end
, 0},
753 {"endb", s_ignore
, 0},
754 {"ent", s_mips_ent
, 0},
756 {"fmask", s_mips_mask
, 'F'},
757 {"frame", s_mips_frame
, 0},
758 {"loc", s_ignore
, 0},
759 {"mask", s_mips_mask
, 'R'},
760 {"verstamp", s_ignore
, 0},
764 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
769 pop_insert (mips_pseudo_table
);
770 if (! ECOFF_DEBUGGING
)
771 pop_insert (mips_nonecoff_pseudo_table
);
774 /* Symbols labelling the current insn. */
776 struct insn_label_list
778 struct insn_label_list
*next
;
782 static struct insn_label_list
*insn_labels
;
783 static struct insn_label_list
*free_insn_labels
;
785 static void mips_clear_insn_labels
PARAMS ((void));
788 mips_clear_insn_labels ()
790 register struct insn_label_list
**pl
;
792 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
798 static char *expr_end
;
800 /* Expressions which appear in instructions. These are set by
803 static expressionS imm_expr
;
804 static expressionS offset_expr
;
806 /* Relocs associated with imm_expr and offset_expr. */
808 static bfd_reloc_code_real_type imm_reloc
;
809 static bfd_reloc_code_real_type offset_reloc
;
811 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
813 static boolean imm_unmatched_hi
;
815 /* These are set by mips16_ip if an explicit extension is used. */
817 static boolean mips16_small
, mips16_ext
;
819 #ifdef MIPS_STABS_ELF
820 /* The pdr segment for per procedure frame/regmask info */
826 * This function is called once, at assembler startup time. It should
827 * set up all the tables, etc. that the MD part of the assembler will need.
833 register const char *retval
= NULL
;
834 register unsigned int i
= 0;
838 int mips_isa_from_cpu
;
841 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
843 a
= xmalloc (sizeof TARGET_CPU
);
844 strcpy (a
, TARGET_CPU
);
845 a
[(sizeof TARGET_CPU
) - 3] = '\0';
851 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
852 just the generic 'mips', in which case set mips_cpu based
853 on the given ISA, if any. */
855 if (strcmp (cpu
, "mips") == 0)
857 if (mips_opts
.isa
< 0)
860 else if (mips_opts
.isa
== 2)
863 else if (mips_opts
.isa
== 3)
866 else if (mips_opts
.isa
== 4)
873 else if (strcmp (cpu
, "r3900") == 0
874 || strcmp (cpu
, "mipstx39") == 0
878 else if (strcmp (cpu
, "r6000") == 0
879 || strcmp (cpu
, "mips2") == 0)
882 else if (strcmp (cpu
, "mips64") == 0
883 || strcmp (cpu
, "r4000") == 0
884 || strcmp (cpu
, "mips3") == 0)
887 else if (strcmp (cpu
, "r4400") == 0)
890 else if (strcmp (cpu
, "mips64orion") == 0
891 || strcmp (cpu
, "r4600") == 0)
894 else if (strcmp (cpu
, "r4650") == 0)
897 else if (strcmp (cpu
, "mips64vr4300") == 0)
900 else if (strcmp (cpu
, "mips64vr4111") == 0)
903 else if (strcmp (cpu
, "mips64vr4100") == 0)
906 else if (strcmp (cpu
, "r4010") == 0)
910 else if (strcmp (cpu
, "r5000") == 0
911 || strcmp (cpu
, "mips64vr5000") == 0)
916 else if (strcmp (cpu
, "r8000") == 0
917 || strcmp (cpu
, "mips4") == 0)
920 else if (strcmp (cpu
, "r10000") == 0)
923 else if (strcmp (cpu
, "mips16") == 0)
924 mips_cpu
= 0; /* FIXME */
932 mips_isa_from_cpu
= 1;
934 else if (mips_cpu
== 6000
936 mips_isa_from_cpu
= 2;
938 else if (mips_cpu
== 4000
945 mips_isa_from_cpu
= 3;
947 else if (mips_cpu
== 5000
949 || mips_cpu
== 10000)
950 mips_isa_from_cpu
= 4;
953 mips_isa_from_cpu
= -1;
955 if (mips_opts
.isa
== -1)
957 if (mips_isa_from_cpu
!= -1)
958 mips_opts
.isa
= mips_isa_from_cpu
;
963 if (mips_opts
.mips16
< 0)
965 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
966 mips_opts
.mips16
= 1;
968 mips_opts
.mips16
= 0;
971 /* End of TARGET_CPU processing, get rid of malloced memory
980 if (mips_opts
.isa
== 1 && mips_trap
)
981 as_bad (_("trap exception not supported at ISA 1"));
983 /* Set the EABI kind based on the ISA before the user gets
984 to change the ISA with directives. This isn't really
985 the best, but then neither is basing the abi on the isa. */
986 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
988 && 0 == strcmp (mips_abi_string
,"eabi"))
991 if (mips_cpu
!= 0 && mips_cpu
!= -1)
993 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
995 /* If they asked for mips1 or mips2 and a cpu that is
996 mips3 or greater, then mark the object file 32BITMODE. */
997 if (mips_isa_from_cpu
!= -1
998 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
999 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1004 switch (mips_opts
.isa
)
1007 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1010 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1013 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1016 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1022 as_warn (_("Could not set architecture and machine"));
1024 file_mips_isa
= mips_opts
.isa
;
1026 op_hash
= hash_new ();
1028 for (i
= 0; i
< NUMOPCODES
;)
1030 const char *name
= mips_opcodes
[i
].name
;
1032 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1035 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1036 mips_opcodes
[i
].name
, retval
);
1037 /* Probably a memory allocation problem? Give up now. */
1038 as_fatal (_("Broken assembler. No assembly attempted."));
1042 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1044 if (!validate_mips_insn (&mips_opcodes
[i
]))
1049 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1052 mips16_op_hash
= hash_new ();
1055 while (i
< bfd_mips16_num_opcodes
)
1057 const char *name
= mips16_opcodes
[i
].name
;
1059 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1061 as_fatal (_("internal: can't hash `%s': %s"),
1062 mips16_opcodes
[i
].name
, retval
);
1065 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1066 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1067 != mips16_opcodes
[i
].match
))
1069 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1070 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1075 while (i
< bfd_mips16_num_opcodes
1076 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1080 as_fatal (_("Broken assembler. No assembly attempted."));
1082 /* We add all the general register names to the symbol table. This
1083 helps us detect invalid uses of them. */
1084 for (i
= 0; i
< 32; i
++)
1088 sprintf (buf
, "$%d", i
);
1089 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1090 &zero_address_frag
));
1092 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1093 &zero_address_frag
));
1094 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1095 &zero_address_frag
));
1096 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1097 &zero_address_frag
));
1098 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1099 &zero_address_frag
));
1100 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1101 &zero_address_frag
));
1102 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1103 &zero_address_frag
));
1104 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1105 &zero_address_frag
));
1107 mips_no_prev_insn (false);
1110 mips_cprmask
[0] = 0;
1111 mips_cprmask
[1] = 0;
1112 mips_cprmask
[2] = 0;
1113 mips_cprmask
[3] = 0;
1115 /* set the default alignment for the text section (2**2) */
1116 record_alignment (text_section
, 2);
1118 if (USE_GLOBAL_POINTER_OPT
)
1119 bfd_set_gp_size (stdoutput
, g_switch_value
);
1121 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1123 /* On a native system, sections must be aligned to 16 byte
1124 boundaries. When configured for an embedded ELF target, we
1126 if (strcmp (TARGET_OS
, "elf") != 0)
1128 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1129 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1130 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1133 /* Create a .reginfo section for register masks and a .mdebug
1134 section for debugging information. */
1142 subseg
= now_subseg
;
1144 /* The ABI says this section should be loaded so that the
1145 running program can access it. However, we don't load it
1146 if we are configured for an embedded target */
1147 flags
= SEC_READONLY
| SEC_DATA
;
1148 if (strcmp (TARGET_OS
, "elf") != 0)
1149 flags
|= SEC_ALLOC
| SEC_LOAD
;
1153 sec
= subseg_new (".reginfo", (subsegT
) 0);
1156 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1157 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1160 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1165 /* The 64-bit ABI uses a .MIPS.options section rather than
1166 .reginfo section. */
1167 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1168 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1169 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1172 /* Set up the option header. */
1174 Elf_Internal_Options opthdr
;
1177 opthdr
.kind
= ODK_REGINFO
;
1178 opthdr
.size
= (sizeof (Elf_External_Options
)
1179 + sizeof (Elf64_External_RegInfo
));
1182 f
= frag_more (sizeof (Elf_External_Options
));
1183 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1184 (Elf_External_Options
*) f
);
1186 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1191 if (ECOFF_DEBUGGING
)
1193 sec
= subseg_new (".mdebug", (subsegT
) 0);
1194 (void) bfd_set_section_flags (stdoutput
, sec
,
1195 SEC_HAS_CONTENTS
| SEC_READONLY
);
1196 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1199 #ifdef MIPS_STABS_ELF
1200 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1201 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1202 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1203 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1206 subseg_set (seg
, subseg
);
1210 if (! ECOFF_DEBUGGING
)
1217 if (! ECOFF_DEBUGGING
)
1225 struct mips_cl_insn insn
;
1227 imm_expr
.X_op
= O_absent
;
1228 imm_reloc
= BFD_RELOC_UNUSED
;
1229 imm_unmatched_hi
= false;
1230 offset_expr
.X_op
= O_absent
;
1231 offset_reloc
= BFD_RELOC_UNUSED
;
1233 if (mips_opts
.mips16
)
1234 mips16_ip (str
, &insn
);
1237 mips_ip (str
, &insn
);
1238 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1239 str
, insn
.insn_opcode
));
1244 as_bad ("%s `%s'", insn_error
, str
);
1248 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1250 if (mips_opts
.mips16
)
1251 mips16_macro (&insn
);
1257 if (imm_expr
.X_op
!= O_absent
)
1258 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1260 else if (offset_expr
.X_op
!= O_absent
)
1261 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1263 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1267 /* See whether instruction IP reads register REG. CLASS is the type
1271 insn_uses_reg (ip
, reg
, class)
1272 struct mips_cl_insn
*ip
;
1274 enum mips_regclass
class;
1276 if (class == MIPS16_REG
)
1278 assert (mips_opts
.mips16
);
1279 reg
= mips16_to_32_reg_map
[reg
];
1280 class = MIPS_GR_REG
;
1283 /* Don't report on general register 0, since it never changes. */
1284 if (class == MIPS_GR_REG
&& reg
== 0)
1287 if (class == MIPS_FP_REG
)
1289 assert (! mips_opts
.mips16
);
1290 /* If we are called with either $f0 or $f1, we must check $f0.
1291 This is not optimal, because it will introduce an unnecessary
1292 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1293 need to distinguish reading both $f0 and $f1 or just one of
1294 them. Note that we don't have to check the other way,
1295 because there is no instruction that sets both $f0 and $f1
1296 and requires a delay. */
1297 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1298 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1299 == (reg
&~ (unsigned) 1)))
1301 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1302 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1303 == (reg
&~ (unsigned) 1)))
1306 else if (! mips_opts
.mips16
)
1308 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1309 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1311 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1312 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1317 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1318 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1319 & MIPS16OP_MASK_RX
)]
1322 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1323 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1324 & MIPS16OP_MASK_RY
)]
1327 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1328 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1329 & MIPS16OP_MASK_MOVE32Z
)]
1332 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1334 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1336 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1338 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1339 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1340 & MIPS16OP_MASK_REGR32
) == reg
)
1347 /* This function returns true if modifying a register requires a
1351 reg_needs_delay (reg
)
1354 unsigned long prev_pinfo
;
1356 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1357 if (! mips_opts
.noreorder
1358 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1359 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1360 || (! gpr_interlocks
1361 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1363 /* A load from a coprocessor or from memory. All load
1364 delays delay the use of general register rt for one
1365 instruction on the r3000. The r6000 and r4000 use
1367 /* Itbl support may require additional care here. */
1368 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1369 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1376 /* Mark instruction labels in mips16 mode. This permits the linker to
1377 handle them specially, such as generating jalx instructions when
1378 needed. We also make them odd for the duration of the assembly, in
1379 order to generate the right sort of code. We will make them even
1380 in the adjust_symtab routine, while leaving them marked. This is
1381 convenient for the debugger and the disassembler. The linker knows
1382 to make them odd again. */
1385 mips16_mark_labels ()
1387 if (mips_opts
.mips16
)
1389 struct insn_label_list
*l
;
1391 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1394 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1395 S_SET_OTHER (l
->label
, STO_MIPS16
);
1397 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1398 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1403 /* Output an instruction. PLACE is where to put the instruction; if
1404 it is NULL, this uses frag_more to get room. IP is the instruction
1405 information. ADDRESS_EXPR is an operand of the instruction to be
1406 used with RELOC_TYPE. */
1409 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1411 struct mips_cl_insn
*ip
;
1412 expressionS
*address_expr
;
1413 bfd_reloc_code_real_type reloc_type
;
1414 boolean unmatched_hi
;
1416 register unsigned long prev_pinfo
, pinfo
;
1421 /* Mark instruction labels in mips16 mode. */
1422 if (mips_opts
.mips16
)
1423 mips16_mark_labels ();
1425 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1426 pinfo
= ip
->insn_mo
->pinfo
;
1428 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1432 /* If the previous insn required any delay slots, see if we need
1433 to insert a NOP or two. There are eight kinds of possible
1434 hazards, of which an instruction can have at most one type.
1435 (1) a load from memory delay
1436 (2) a load from a coprocessor delay
1437 (3) an unconditional branch delay
1438 (4) a conditional branch delay
1439 (5) a move to coprocessor register delay
1440 (6) a load coprocessor register from memory delay
1441 (7) a coprocessor condition code delay
1442 (8) a HI/LO special register delay
1444 There are a lot of optimizations we could do that we don't.
1445 In particular, we do not, in general, reorder instructions.
1446 If you use gcc with optimization, it will reorder
1447 instructions and generally do much more optimization then we
1448 do here; repeating all that work in the assembler would only
1449 benefit hand written assembly code, and does not seem worth
1452 /* This is how a NOP is emitted. */
1453 #define emit_nop() \
1455 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1456 : md_number_to_chars (frag_more (4), 0, 4))
1458 /* The previous insn might require a delay slot, depending upon
1459 the contents of the current insn. */
1460 if (! mips_opts
.mips16
1461 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1462 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1463 && ! cop_interlocks
)
1464 || (! gpr_interlocks
1465 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1467 /* A load from a coprocessor or from memory. All load
1468 delays delay the use of general register rt for one
1469 instruction on the r3000. The r6000 and r4000 use
1471 /* Itbl support may require additional care here. */
1472 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1473 if (mips_optimize
== 0
1474 || insn_uses_reg (ip
,
1475 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1480 else if (! mips_opts
.mips16
1481 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1482 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1483 && ! cop_interlocks
)
1484 || (mips_opts
.isa
== 1
1485 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1487 /* A generic coprocessor delay. The previous instruction
1488 modified a coprocessor general or control register. If
1489 it modified a control register, we need to avoid any
1490 coprocessor instruction (this is probably not always
1491 required, but it sometimes is). If it modified a general
1492 register, we avoid using that register.
1494 On the r6000 and r4000 loading a coprocessor register
1495 from memory is interlocked, and does not require a delay.
1497 This case is not handled very well. There is no special
1498 knowledge of CP0 handling, and the coprocessors other
1499 than the floating point unit are not distinguished at
1501 /* Itbl support may require additional care here. FIXME!
1502 Need to modify this to include knowledge about
1503 user specified delays! */
1504 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1506 if (mips_optimize
== 0
1507 || insn_uses_reg (ip
,
1508 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1513 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1515 if (mips_optimize
== 0
1516 || insn_uses_reg (ip
,
1517 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1524 /* We don't know exactly what the previous instruction
1525 does. If the current instruction uses a coprocessor
1526 register, we must insert a NOP. If previous
1527 instruction may set the condition codes, and the
1528 current instruction uses them, we must insert two
1530 /* Itbl support may require additional care here. */
1531 if (mips_optimize
== 0
1532 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1533 && (pinfo
& INSN_READ_COND_CODE
)))
1535 else if (pinfo
& INSN_COP
)
1539 else if (! mips_opts
.mips16
1540 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1541 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1542 && ! cop_interlocks
)
1544 /* The previous instruction sets the coprocessor condition
1545 codes, but does not require a general coprocessor delay
1546 (this means it is a floating point comparison
1547 instruction). If this instruction uses the condition
1548 codes, we need to insert a single NOP. */
1549 /* Itbl support may require additional care here. */
1550 if (mips_optimize
== 0
1551 || (pinfo
& INSN_READ_COND_CODE
))
1554 else if (prev_pinfo
& INSN_READ_LO
)
1556 /* The previous instruction reads the LO register; if the
1557 current instruction writes to the LO register, we must
1558 insert two NOPS. Some newer processors have interlocks.
1559 Also the tx39's multiply instructions can be exectuted
1560 immediatly after a read from HI/LO (without the delay),
1561 though the tx39's divide insns still do require the
1563 if (! (hilo_interlocks
1564 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1565 && (mips_optimize
== 0
1566 || (pinfo
& INSN_WRITE_LO
)))
1568 /* Most mips16 branch insns don't have a delay slot.
1569 If a read from LO is immediately followed by a branch
1570 to a write to LO we have a read followed by a write
1571 less than 2 insns away. We assume the target of
1572 a branch might be a write to LO, and insert a nop
1573 between a read and an immediately following branch. */
1574 else if (mips_opts
.mips16
1575 && (mips_optimize
== 0
1576 || (pinfo
& MIPS16_INSN_BRANCH
)))
1579 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1581 /* The previous instruction reads the HI register; if the
1582 current instruction writes to the HI register, we must
1583 insert a NOP. Some newer processors have interlocks.
1584 Also the note tx39's multiply above. */
1585 if (! (hilo_interlocks
1586 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1587 && (mips_optimize
== 0
1588 || (pinfo
& INSN_WRITE_HI
)))
1590 /* Most mips16 branch insns don't have a delay slot.
1591 If a read from HI is immediately followed by a branch
1592 to a write to HI we have a read followed by a write
1593 less than 2 insns away. We assume the target of
1594 a branch might be a write to HI, and insert a nop
1595 between a read and an immediately following branch. */
1596 else if (mips_opts
.mips16
1597 && (mips_optimize
== 0
1598 || (pinfo
& MIPS16_INSN_BRANCH
)))
1602 /* If the previous instruction was in a noreorder section, then
1603 we don't want to insert the nop after all. */
1604 /* Itbl support may require additional care here. */
1605 if (prev_insn_unreordered
)
1608 /* There are two cases which require two intervening
1609 instructions: 1) setting the condition codes using a move to
1610 coprocessor instruction which requires a general coprocessor
1611 delay and then reading the condition codes 2) reading the HI
1612 or LO register and then writing to it (except on processors
1613 which have interlocks). If we are not already emitting a NOP
1614 instruction, we must check for these cases compared to the
1615 instruction previous to the previous instruction. */
1616 if ((! mips_opts
.mips16
1617 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1618 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1619 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1620 && (pinfo
& INSN_READ_COND_CODE
)
1621 && ! cop_interlocks
)
1622 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1623 && (pinfo
& INSN_WRITE_LO
)
1624 && ! (hilo_interlocks
1625 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1626 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1627 && (pinfo
& INSN_WRITE_HI
)
1628 && ! (hilo_interlocks
1629 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1634 if (prev_prev_insn_unreordered
)
1637 if (prev_prev_nop
&& nops
== 0)
1640 /* If we are being given a nop instruction, don't bother with
1641 one of the nops we would otherwise output. This will only
1642 happen when a nop instruction is used with mips_optimize set
1645 && ! mips_opts
.noreorder
1646 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1649 /* Now emit the right number of NOP instructions. */
1650 if (nops
> 0 && ! mips_opts
.noreorder
)
1653 unsigned long old_frag_offset
;
1655 struct insn_label_list
*l
;
1657 old_frag
= frag_now
;
1658 old_frag_offset
= frag_now_fix ();
1660 for (i
= 0; i
< nops
; i
++)
1665 listing_prev_line ();
1666 /* We may be at the start of a variant frag. In case we
1667 are, make sure there is enough space for the frag
1668 after the frags created by listing_prev_line. The
1669 argument to frag_grow here must be at least as large
1670 as the argument to all other calls to frag_grow in
1671 this file. We don't have to worry about being in the
1672 middle of a variant frag, because the variants insert
1673 all needed nop instructions themselves. */
1677 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1679 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1680 symbol_set_frag (l
->label
, frag_now
);
1681 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1682 /* mips16 text labels are stored as odd. */
1683 if (mips_opts
.mips16
)
1684 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1687 #ifndef NO_ECOFF_DEBUGGING
1688 if (ECOFF_DEBUGGING
)
1689 ecoff_fix_loc (old_frag
, old_frag_offset
);
1692 else if (prev_nop_frag
!= NULL
)
1694 /* We have a frag holding nops we may be able to remove. If
1695 we don't need any nops, we can decrease the size of
1696 prev_nop_frag by the size of one instruction. If we do
1697 need some nops, we count them in prev_nops_required. */
1698 if (prev_nop_frag_since
== 0)
1702 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1703 --prev_nop_frag_holds
;
1706 prev_nop_frag_required
+= nops
;
1710 if (prev_prev_nop
== 0)
1712 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1713 --prev_nop_frag_holds
;
1716 ++prev_nop_frag_required
;
1719 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1720 prev_nop_frag
= NULL
;
1722 ++prev_nop_frag_since
;
1724 /* Sanity check: by the time we reach the second instruction
1725 after prev_nop_frag, we should have used up all the nops
1726 one way or another. */
1727 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1731 if (reloc_type
> BFD_RELOC_UNUSED
)
1733 /* We need to set up a variant frag. */
1734 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1735 f
= frag_var (rs_machine_dependent
, 4, 0,
1736 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1737 mips16_small
, mips16_ext
,
1739 & INSN_UNCOND_BRANCH_DELAY
),
1740 (prev_insn_reloc_type
1741 == BFD_RELOC_MIPS16_JMP
)),
1742 make_expr_symbol (address_expr
), (offsetT
) 0,
1745 else if (place
!= NULL
)
1747 else if (mips_opts
.mips16
1749 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1751 /* Make sure there is enough room to swap this instruction with
1752 a following jump instruction. */
1758 if (mips_opts
.mips16
1759 && mips_opts
.noreorder
1760 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1761 as_warn (_("extended instruction in delay slot"));
1767 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1769 if (address_expr
->X_op
== O_constant
)
1774 ip
->insn_opcode
|= address_expr
->X_add_number
;
1777 case BFD_RELOC_LO16
:
1778 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1781 case BFD_RELOC_MIPS_JMP
:
1782 if ((address_expr
->X_add_number
& 3) != 0)
1783 as_bad (_("jump to misaligned address (0x%lx)"),
1784 (unsigned long) address_expr
->X_add_number
);
1785 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1788 case BFD_RELOC_MIPS16_JMP
:
1789 if ((address_expr
->X_add_number
& 3) != 0)
1790 as_bad (_("jump to misaligned address (0x%lx)"),
1791 (unsigned long) address_expr
->X_add_number
);
1793 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1794 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1795 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1799 case BFD_RELOC_16_PCREL_S2
:
1809 /* Don't generate a reloc if we are writing into a variant
1813 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1815 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1819 struct mips_hi_fixup
*hi_fixup
;
1821 assert (reloc_type
== BFD_RELOC_HI16_S
);
1822 hi_fixup
= ((struct mips_hi_fixup
*)
1823 xmalloc (sizeof (struct mips_hi_fixup
)));
1824 hi_fixup
->fixp
= fixp
;
1825 hi_fixup
->seg
= now_seg
;
1826 hi_fixup
->next
= mips_hi_fixup_list
;
1827 mips_hi_fixup_list
= hi_fixup
;
1833 if (! mips_opts
.mips16
)
1834 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1835 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1837 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1838 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1844 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1847 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1850 /* Update the register mask information. */
1851 if (! mips_opts
.mips16
)
1853 if (pinfo
& INSN_WRITE_GPR_D
)
1854 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1855 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1856 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1857 if (pinfo
& INSN_READ_GPR_S
)
1858 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1859 if (pinfo
& INSN_WRITE_GPR_31
)
1860 mips_gprmask
|= 1 << 31;
1861 if (pinfo
& INSN_WRITE_FPR_D
)
1862 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1863 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1864 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1865 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1866 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1867 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1868 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1869 if (pinfo
& INSN_COP
)
1871 /* We don't keep enough information to sort these cases out.
1872 The itbl support does keep this information however, although
1873 we currently don't support itbl fprmats as part of the cop
1874 instruction. May want to add this support in the future. */
1876 /* Never set the bit for $0, which is always zero. */
1877 mips_gprmask
&=~ 1 << 0;
1881 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1882 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1883 & MIPS16OP_MASK_RX
);
1884 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1885 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1886 & MIPS16OP_MASK_RY
);
1887 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1888 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1889 & MIPS16OP_MASK_RZ
);
1890 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1891 mips_gprmask
|= 1 << TREG
;
1892 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1893 mips_gprmask
|= 1 << SP
;
1894 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1895 mips_gprmask
|= 1 << RA
;
1896 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1897 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1898 if (pinfo
& MIPS16_INSN_READ_Z
)
1899 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1900 & MIPS16OP_MASK_MOVE32Z
);
1901 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1902 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1903 & MIPS16OP_MASK_REGR32
);
1906 if (place
== NULL
&& ! mips_opts
.noreorder
)
1908 /* Filling the branch delay slot is more complex. We try to
1909 switch the branch with the previous instruction, which we can
1910 do if the previous instruction does not set up a condition
1911 that the branch tests and if the branch is not itself the
1912 target of any branch. */
1913 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1914 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1916 if (mips_optimize
< 2
1917 /* If we have seen .set volatile or .set nomove, don't
1919 || mips_opts
.nomove
!= 0
1920 /* If we had to emit any NOP instructions, then we
1921 already know we can not swap. */
1923 /* If we don't even know the previous insn, we can not
1925 || ! prev_insn_valid
1926 /* If the previous insn is already in a branch delay
1927 slot, then we can not swap. */
1928 || prev_insn_is_delay_slot
1929 /* If the previous previous insn was in a .set
1930 noreorder, we can't swap. Actually, the MIPS
1931 assembler will swap in this situation. However, gcc
1932 configured -with-gnu-as will generate code like
1938 in which we can not swap the bne and INSN. If gcc is
1939 not configured -with-gnu-as, it does not output the
1940 .set pseudo-ops. We don't have to check
1941 prev_insn_unreordered, because prev_insn_valid will
1942 be 0 in that case. We don't want to use
1943 prev_prev_insn_valid, because we do want to be able
1944 to swap at the start of a function. */
1945 || prev_prev_insn_unreordered
1946 /* If the branch is itself the target of a branch, we
1947 can not swap. We cheat on this; all we check for is
1948 whether there is a label on this instruction. If
1949 there are any branches to anything other than a
1950 label, users must use .set noreorder. */
1951 || insn_labels
!= NULL
1952 /* If the previous instruction is in a variant frag, we
1953 can not do the swap. This does not apply to the
1954 mips16, which uses variant frags for different
1956 || (! mips_opts
.mips16
1957 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1958 /* If the branch reads the condition codes, we don't
1959 even try to swap, because in the sequence
1964 we can not swap, and I don't feel like handling that
1966 || (! mips_opts
.mips16
1967 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1968 && (pinfo
& INSN_READ_COND_CODE
))
1969 /* We can not swap with an instruction that requires a
1970 delay slot, becase the target of the branch might
1971 interfere with that instruction. */
1972 || (! mips_opts
.mips16
1973 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1975 /* Itbl support may require additional care here. */
1976 & (INSN_LOAD_COPROC_DELAY
1977 | INSN_COPROC_MOVE_DELAY
1978 | INSN_WRITE_COND_CODE
)))
1979 || (! (hilo_interlocks
1980 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1984 || (! mips_opts
.mips16
1986 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1987 || (! mips_opts
.mips16
1988 && mips_opts
.isa
== 1
1989 /* Itbl support may require additional care here. */
1990 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1991 /* We can not swap with a branch instruction. */
1993 & (INSN_UNCOND_BRANCH_DELAY
1994 | INSN_COND_BRANCH_DELAY
1995 | INSN_COND_BRANCH_LIKELY
))
1996 /* We do not swap with a trap instruction, since it
1997 complicates trap handlers to have the trap
1998 instruction be in a delay slot. */
1999 || (prev_pinfo
& INSN_TRAP
)
2000 /* If the branch reads a register that the previous
2001 instruction sets, we can not swap. */
2002 || (! mips_opts
.mips16
2003 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2004 && insn_uses_reg (ip
,
2005 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2008 || (! mips_opts
.mips16
2009 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2010 && insn_uses_reg (ip
,
2011 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2014 || (mips_opts
.mips16
2015 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2016 && insn_uses_reg (ip
,
2017 ((prev_insn
.insn_opcode
2019 & MIPS16OP_MASK_RX
),
2021 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2022 && insn_uses_reg (ip
,
2023 ((prev_insn
.insn_opcode
2025 & MIPS16OP_MASK_RY
),
2027 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2028 && insn_uses_reg (ip
,
2029 ((prev_insn
.insn_opcode
2031 & MIPS16OP_MASK_RZ
),
2033 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2034 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2035 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2036 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2037 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2038 && insn_uses_reg (ip
,
2039 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2042 /* If the branch writes a register that the previous
2043 instruction sets, we can not swap (we know that
2044 branches write only to RD or to $31). */
2045 || (! mips_opts
.mips16
2046 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2047 && (((pinfo
& INSN_WRITE_GPR_D
)
2048 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2049 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2050 || ((pinfo
& INSN_WRITE_GPR_31
)
2051 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2054 || (! mips_opts
.mips16
2055 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2056 && (((pinfo
& INSN_WRITE_GPR_D
)
2057 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2058 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2059 || ((pinfo
& INSN_WRITE_GPR_31
)
2060 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2063 || (mips_opts
.mips16
2064 && (pinfo
& MIPS16_INSN_WRITE_31
)
2065 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2066 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2067 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2069 /* If the branch writes a register that the previous
2070 instruction reads, we can not swap (we know that
2071 branches only write to RD or to $31). */
2072 || (! mips_opts
.mips16
2073 && (pinfo
& INSN_WRITE_GPR_D
)
2074 && insn_uses_reg (&prev_insn
,
2075 ((ip
->insn_opcode
>> OP_SH_RD
)
2078 || (! mips_opts
.mips16
2079 && (pinfo
& INSN_WRITE_GPR_31
)
2080 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2081 || (mips_opts
.mips16
2082 && (pinfo
& MIPS16_INSN_WRITE_31
)
2083 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2084 /* If we are generating embedded PIC code, the branch
2085 might be expanded into a sequence which uses $at, so
2086 we can't swap with an instruction which reads it. */
2087 || (mips_pic
== EMBEDDED_PIC
2088 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2089 /* If the previous previous instruction has a load
2090 delay, and sets a register that the branch reads, we
2092 || (! mips_opts
.mips16
2093 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2094 /* Itbl support may require additional care here. */
2095 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2096 || (! gpr_interlocks
2097 && (prev_prev_insn
.insn_mo
->pinfo
2098 & INSN_LOAD_MEMORY_DELAY
)))
2099 && insn_uses_reg (ip
,
2100 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2103 /* If one instruction sets a condition code and the
2104 other one uses a condition code, we can not swap. */
2105 || ((pinfo
& INSN_READ_COND_CODE
)
2106 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2107 || ((pinfo
& INSN_WRITE_COND_CODE
)
2108 && (prev_pinfo
& INSN_READ_COND_CODE
))
2109 /* If the previous instruction uses the PC, we can not
2111 || (mips_opts
.mips16
2112 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2113 /* If the previous instruction was extended, we can not
2115 || (mips_opts
.mips16
&& prev_insn_extended
)
2116 /* If the previous instruction had a fixup in mips16
2117 mode, we can not swap. This normally means that the
2118 previous instruction was a 4 byte branch anyhow. */
2119 || (mips_opts
.mips16
&& prev_insn_fixp
)
2120 /* If the previous instruction is a sync, sync.l, or
2121 sync.p, we can not swap. */
2122 || (prev_pinfo
& INSN_SYNC
))
2124 /* We could do even better for unconditional branches to
2125 portions of this object file; we could pick up the
2126 instruction at the destination, put it in the delay
2127 slot, and bump the destination address. */
2129 /* Update the previous insn information. */
2130 prev_prev_insn
= *ip
;
2131 prev_insn
.insn_mo
= &dummy_opcode
;
2135 /* It looks like we can actually do the swap. */
2136 if (! mips_opts
.mips16
)
2141 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2142 memcpy (temp
, prev_f
, 4);
2143 memcpy (prev_f
, f
, 4);
2144 memcpy (f
, temp
, 4);
2147 prev_insn_fixp
->fx_frag
= frag_now
;
2148 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2152 fixp
->fx_frag
= prev_insn_frag
;
2153 fixp
->fx_where
= prev_insn_where
;
2161 assert (prev_insn_fixp
== NULL
);
2162 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2163 memcpy (temp
, prev_f
, 2);
2164 memcpy (prev_f
, f
, 2);
2165 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2167 assert (reloc_type
== BFD_RELOC_UNUSED
);
2168 memcpy (f
, temp
, 2);
2172 memcpy (f
, f
+ 2, 2);
2173 memcpy (f
+ 2, temp
, 2);
2177 fixp
->fx_frag
= prev_insn_frag
;
2178 fixp
->fx_where
= prev_insn_where
;
2182 /* Update the previous insn information; leave prev_insn
2184 prev_prev_insn
= *ip
;
2186 prev_insn_is_delay_slot
= 1;
2188 /* If that was an unconditional branch, forget the previous
2189 insn information. */
2190 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2192 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2193 prev_insn
.insn_mo
= &dummy_opcode
;
2196 prev_insn_fixp
= NULL
;
2197 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2198 prev_insn_extended
= 0;
2200 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2202 /* We don't yet optimize a branch likely. What we should do
2203 is look at the target, copy the instruction found there
2204 into the delay slot, and increment the branch to jump to
2205 the next instruction. */
2207 /* Update the previous insn information. */
2208 prev_prev_insn
= *ip
;
2209 prev_insn
.insn_mo
= &dummy_opcode
;
2210 prev_insn_fixp
= NULL
;
2211 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2212 prev_insn_extended
= 0;
2216 /* Update the previous insn information. */
2218 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2220 prev_prev_insn
= prev_insn
;
2223 /* Any time we see a branch, we always fill the delay slot
2224 immediately; since this insn is not a branch, we know it
2225 is not in a delay slot. */
2226 prev_insn_is_delay_slot
= 0;
2228 prev_insn_fixp
= fixp
;
2229 prev_insn_reloc_type
= reloc_type
;
2230 if (mips_opts
.mips16
)
2231 prev_insn_extended
= (ip
->use_extend
2232 || reloc_type
> BFD_RELOC_UNUSED
);
2235 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2236 prev_insn_unreordered
= 0;
2237 prev_insn_frag
= frag_now
;
2238 prev_insn_where
= f
- frag_now
->fr_literal
;
2239 prev_insn_valid
= 1;
2241 else if (place
== NULL
)
2243 /* We need to record a bit of information even when we are not
2244 reordering, in order to determine the base address for mips16
2245 PC relative relocs. */
2246 prev_prev_insn
= prev_insn
;
2248 prev_insn_reloc_type
= reloc_type
;
2249 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2250 prev_insn_unreordered
= 1;
2253 /* We just output an insn, so the next one doesn't have a label. */
2254 mips_clear_insn_labels ();
2256 /* We must ensure that a fixup associated with an unmatched %hi
2257 reloc does not become a variant frag. Otherwise, the
2258 rearrangement of %hi relocs in frob_file may confuse
2262 frag_wane (frag_now
);
2267 /* This function forgets that there was any previous instruction or
2268 label. If PRESERVE is non-zero, it remembers enough information to
2269 know whether nops are needed before a noreorder section. */
2272 mips_no_prev_insn (preserve
)
2277 prev_insn
.insn_mo
= &dummy_opcode
;
2278 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2279 prev_nop_frag
= NULL
;
2280 prev_nop_frag_holds
= 0;
2281 prev_nop_frag_required
= 0;
2282 prev_nop_frag_since
= 0;
2284 prev_insn_valid
= 0;
2285 prev_insn_is_delay_slot
= 0;
2286 prev_insn_unreordered
= 0;
2287 prev_insn_extended
= 0;
2288 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2289 prev_prev_insn_unreordered
= 0;
2290 mips_clear_insn_labels ();
2293 /* This function must be called whenever we turn on noreorder or emit
2294 something other than instructions. It inserts any NOPS which might
2295 be needed by the previous instruction, and clears the information
2296 kept for the previous instructions. The INSNS parameter is true if
2297 instructions are to follow. */
2300 mips_emit_delays (insns
)
2303 if (! mips_opts
.noreorder
)
2308 if ((! mips_opts
.mips16
2309 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2310 && (! cop_interlocks
2311 && (prev_insn
.insn_mo
->pinfo
2312 & (INSN_LOAD_COPROC_DELAY
2313 | INSN_COPROC_MOVE_DELAY
2314 | INSN_WRITE_COND_CODE
))))
2315 || (! hilo_interlocks
2316 && (prev_insn
.insn_mo
->pinfo
2319 || (! mips_opts
.mips16
2321 && (prev_insn
.insn_mo
->pinfo
2322 & INSN_LOAD_MEMORY_DELAY
))
2323 || (! mips_opts
.mips16
2324 && mips_opts
.isa
== 1
2325 && (prev_insn
.insn_mo
->pinfo
2326 & INSN_COPROC_MEMORY_DELAY
)))
2328 /* Itbl support may require additional care here. */
2330 if ((! mips_opts
.mips16
2331 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2332 && (! cop_interlocks
2333 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2334 || (! hilo_interlocks
2335 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2336 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2339 if (prev_insn_unreordered
)
2342 else if ((! mips_opts
.mips16
2343 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2344 && (! cop_interlocks
2345 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2346 || (! hilo_interlocks
2347 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2348 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2350 /* Itbl support may require additional care here. */
2351 if (! prev_prev_insn_unreordered
)
2357 struct insn_label_list
*l
;
2361 /* Record the frag which holds the nop instructions, so
2362 that we can remove them if we don't need them. */
2363 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2364 prev_nop_frag
= frag_now
;
2365 prev_nop_frag_holds
= nops
;
2366 prev_nop_frag_required
= 0;
2367 prev_nop_frag_since
= 0;
2370 for (; nops
> 0; --nops
)
2375 /* Move on to a new frag, so that it is safe to simply
2376 decrease the size of prev_nop_frag. */
2377 frag_wane (frag_now
);
2381 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2383 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2384 symbol_set_frag (l
->label
, frag_now
);
2385 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2386 /* mips16 text labels are stored as odd. */
2387 if (mips_opts
.mips16
)
2388 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2393 /* Mark instruction labels in mips16 mode. */
2394 if (mips_opts
.mips16
&& insns
)
2395 mips16_mark_labels ();
2397 mips_no_prev_insn (insns
);
2400 /* Build an instruction created by a macro expansion. This is passed
2401 a pointer to the count of instructions created so far, an
2402 expression, the name of the instruction to build, an operand format
2403 string, and corresponding arguments. */
2407 macro_build (char *place
,
2415 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2424 struct mips_cl_insn insn
;
2425 bfd_reloc_code_real_type r
;
2429 va_start (args
, fmt
);
2435 * If the macro is about to expand into a second instruction,
2436 * print a warning if needed. We need to pass ip as a parameter
2437 * to generate a better warning message here...
2439 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2440 as_warn (_("Macro instruction expanded into multiple instructions"));
2443 *counter
+= 1; /* bump instruction counter */
2445 if (mips_opts
.mips16
)
2447 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2452 r
= BFD_RELOC_UNUSED
;
2453 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2454 assert (insn
.insn_mo
);
2455 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2457 /* Search until we get a match for NAME. */
2460 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2461 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2462 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
)
2463 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2467 assert (insn
.insn_mo
->name
);
2468 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2471 insn
.insn_opcode
= insn
.insn_mo
->match
;
2487 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2493 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2498 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2503 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2510 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2514 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2518 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2522 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2529 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2535 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2536 assert (r
== BFD_RELOC_MIPS_GPREL
2537 || r
== BFD_RELOC_MIPS_LITERAL
2538 || r
== BFD_RELOC_LO16
2539 || r
== BFD_RELOC_MIPS_GOT16
2540 || r
== BFD_RELOC_MIPS_CALL16
2541 || r
== BFD_RELOC_MIPS_GOT_LO16
2542 || r
== BFD_RELOC_MIPS_CALL_LO16
2543 || (ep
->X_op
== O_subtract
2544 && now_seg
== text_section
2545 && r
== BFD_RELOC_PCREL_LO16
));
2549 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2551 && (ep
->X_op
== O_constant
2552 || (ep
->X_op
== O_symbol
2553 && (r
== BFD_RELOC_HI16_S
2554 || r
== BFD_RELOC_HI16
2555 || r
== BFD_RELOC_MIPS_GOT_HI16
2556 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2557 || (ep
->X_op
== O_subtract
2558 && now_seg
== text_section
2559 && r
== BFD_RELOC_PCREL_HI16_S
)));
2560 if (ep
->X_op
== O_constant
)
2562 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2564 r
= BFD_RELOC_UNUSED
;
2569 assert (ep
!= NULL
);
2571 * This allows macro() to pass an immediate expression for
2572 * creating short branches without creating a symbol.
2573 * Note that the expression still might come from the assembly
2574 * input, in which case the value is not checked for range nor
2575 * is a relocation entry generated (yuck).
2577 if (ep
->X_op
== O_constant
)
2579 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2583 r
= BFD_RELOC_16_PCREL_S2
;
2587 assert (ep
!= NULL
);
2588 r
= BFD_RELOC_MIPS_JMP
;
2592 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2601 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2603 append_insn (place
, &insn
, ep
, r
, false);
2607 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2615 struct mips_cl_insn insn
;
2616 bfd_reloc_code_real_type r
;
2618 r
= BFD_RELOC_UNUSED
;
2619 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2620 assert (insn
.insn_mo
);
2621 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2623 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2624 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2627 assert (insn
.insn_mo
->name
);
2628 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2631 insn
.insn_opcode
= insn
.insn_mo
->match
;
2632 insn
.use_extend
= false;
2651 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2656 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2660 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2664 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2674 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2681 regno
= va_arg (args
, int);
2682 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2683 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2704 assert (ep
!= NULL
);
2706 if (ep
->X_op
!= O_constant
)
2707 r
= BFD_RELOC_UNUSED
+ c
;
2710 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2711 false, false, &insn
.insn_opcode
,
2712 &insn
.use_extend
, &insn
.extend
);
2714 r
= BFD_RELOC_UNUSED
;
2720 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2727 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2729 append_insn (place
, &insn
, ep
, r
, false);
2733 * Generate a "lui" instruction.
2736 macro_build_lui (place
, counter
, ep
, regnum
)
2742 expressionS high_expr
;
2743 struct mips_cl_insn insn
;
2744 bfd_reloc_code_real_type r
;
2745 CONST
char *name
= "lui";
2746 CONST
char *fmt
= "t,u";
2748 assert (! mips_opts
.mips16
);
2754 high_expr
.X_op
= O_constant
;
2755 high_expr
.X_add_number
= ep
->X_add_number
;
2758 if (high_expr
.X_op
== O_constant
)
2760 /* we can compute the instruction now without a relocation entry */
2761 if (high_expr
.X_add_number
& 0x8000)
2762 high_expr
.X_add_number
+= 0x10000;
2763 high_expr
.X_add_number
=
2764 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2765 r
= BFD_RELOC_UNUSED
;
2769 assert (ep
->X_op
== O_symbol
);
2770 /* _gp_disp is a special case, used from s_cpload. */
2771 assert (mips_pic
== NO_PIC
2772 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2773 r
= BFD_RELOC_HI16_S
;
2777 * If the macro is about to expand into a second instruction,
2778 * print a warning if needed. We need to pass ip as a parameter
2779 * to generate a better warning message here...
2781 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2782 as_warn (_("Macro instruction expanded into multiple instructions"));
2785 *counter
+= 1; /* bump instruction counter */
2787 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2788 assert (insn
.insn_mo
);
2789 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2790 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2792 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2793 if (r
== BFD_RELOC_UNUSED
)
2795 insn
.insn_opcode
|= high_expr
.X_add_number
;
2796 append_insn (place
, &insn
, NULL
, r
, false);
2799 append_insn (place
, &insn
, &high_expr
, r
, false);
2803 * Generates code to set the $at register to true (one)
2804 * if reg is less than the immediate expression.
2807 set_at (counter
, reg
, unsignedp
)
2812 if (imm_expr
.X_op
== O_constant
2813 && imm_expr
.X_add_number
>= -0x8000
2814 && imm_expr
.X_add_number
< 0x8000)
2815 macro_build ((char *) NULL
, counter
, &imm_expr
,
2816 unsignedp
? "sltiu" : "slti",
2817 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2820 load_register (counter
, AT
, &imm_expr
, 0);
2821 macro_build ((char *) NULL
, counter
, NULL
,
2822 unsignedp
? "sltu" : "slt",
2823 "d,v,t", AT
, reg
, AT
);
2827 /* Warn if an expression is not a constant. */
2830 check_absolute_expr (ip
, ex
)
2831 struct mips_cl_insn
*ip
;
2834 if (ex
->X_op
== O_big
)
2835 as_bad (_("unsupported large constant"));
2836 else if (ex
->X_op
!= O_constant
)
2837 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2840 /* Count the leading zeroes by performing a binary chop. This is a
2841 bulky bit of source, but performance is a LOT better for the
2842 majority of values than a simple loop to count the bits:
2843 for (lcnt = 0; (lcnt < 32); lcnt++)
2844 if ((v) & (1 << (31 - lcnt)))
2846 However it is not code size friendly, and the gain will drop a bit
2847 on certain cached systems.
2849 #define COUNT_TOP_ZEROES(v) \
2850 (((v) & ~0xffff) == 0 \
2851 ? ((v) & ~0xff) == 0 \
2852 ? ((v) & ~0xf) == 0 \
2853 ? ((v) & ~0x3) == 0 \
2854 ? ((v) & ~0x1) == 0 \
2859 : ((v) & ~0x7) == 0 \
2862 : ((v) & ~0x3f) == 0 \
2863 ? ((v) & ~0x1f) == 0 \
2866 : ((v) & ~0x7f) == 0 \
2869 : ((v) & ~0xfff) == 0 \
2870 ? ((v) & ~0x3ff) == 0 \
2871 ? ((v) & ~0x1ff) == 0 \
2874 : ((v) & ~0x7ff) == 0 \
2877 : ((v) & ~0x3fff) == 0 \
2878 ? ((v) & ~0x1fff) == 0 \
2881 : ((v) & ~0x7fff) == 0 \
2884 : ((v) & ~0xffffff) == 0 \
2885 ? ((v) & ~0xfffff) == 0 \
2886 ? ((v) & ~0x3ffff) == 0 \
2887 ? ((v) & ~0x1ffff) == 0 \
2890 : ((v) & ~0x7ffff) == 0 \
2893 : ((v) & ~0x3fffff) == 0 \
2894 ? ((v) & ~0x1fffff) == 0 \
2897 : ((v) & ~0x7fffff) == 0 \
2900 : ((v) & ~0xfffffff) == 0 \
2901 ? ((v) & ~0x3ffffff) == 0 \
2902 ? ((v) & ~0x1ffffff) == 0 \
2905 : ((v) & ~0x7ffffff) == 0 \
2908 : ((v) & ~0x3fffffff) == 0 \
2909 ? ((v) & ~0x1fffffff) == 0 \
2912 : ((v) & ~0x7fffffff) == 0 \
2917 * This routine generates the least number of instructions neccessary to load
2918 * an absolute expression value into a register.
2921 load_register (counter
, reg
, ep
, dbl
)
2928 expressionS hi32
, lo32
;
2930 if (ep
->X_op
!= O_big
)
2932 assert (ep
->X_op
== O_constant
);
2933 if (ep
->X_add_number
< 0x8000
2934 && (ep
->X_add_number
>= 0
2935 || (ep
->X_add_number
>= -0x8000
2938 || sizeof (ep
->X_add_number
) > 4))))
2940 /* We can handle 16 bit signed values with an addiu to
2941 $zero. No need to ever use daddiu here, since $zero and
2942 the result are always correct in 32 bit mode. */
2943 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2944 (int) BFD_RELOC_LO16
);
2947 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2949 /* We can handle 16 bit unsigned values with an ori to
2951 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2952 (int) BFD_RELOC_LO16
);
2955 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2956 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2957 == ~ (offsetT
) 0x7fffffff))
2960 || sizeof (ep
->X_add_number
) > 4
2961 || (ep
->X_add_number
& 0x80000000) == 0))
2962 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
2963 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2964 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
2966 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2967 == ~ (offsetT
) 0xffffffff)))
2969 /* 32 bit values require an lui. */
2970 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2971 (int) BFD_RELOC_HI16
);
2972 if ((ep
->X_add_number
& 0xffff) != 0)
2973 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2974 (int) BFD_RELOC_LO16
);
2979 /* The value is larger than 32 bits. */
2981 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2983 as_bad (_("Number larger than 32 bits"));
2984 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2985 (int) BFD_RELOC_LO16
);
2989 if (ep
->X_op
!= O_big
)
2992 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2993 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2994 hi32
.X_add_number
&= 0xffffffff;
2996 lo32
.X_add_number
&= 0xffffffff;
3000 assert (ep
->X_add_number
> 2);
3001 if (ep
->X_add_number
== 3)
3002 generic_bignum
[3] = 0;
3003 else if (ep
->X_add_number
> 4)
3004 as_bad (_("Number larger than 64 bits"));
3005 lo32
.X_op
= O_constant
;
3006 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3007 hi32
.X_op
= O_constant
;
3008 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3011 if (hi32
.X_add_number
== 0)
3016 unsigned long hi
, lo
;
3018 if (hi32
.X_add_number
== 0xffffffff)
3020 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3022 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3023 reg
, 0, (int) BFD_RELOC_LO16
);
3026 if (lo32
.X_add_number
& 0x80000000)
3028 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3029 (int) BFD_RELOC_HI16
);
3030 if (lo32
.X_add_number
& 0xffff)
3031 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3032 reg
, reg
, (int) BFD_RELOC_LO16
);
3037 /* Check for 16bit shifted constant. We know that hi32 is
3038 non-zero, so start the mask on the first bit of the hi32
3043 unsigned long himask
, lomask
;
3047 himask
= 0xffff >> (32 - shift
);
3048 lomask
= (0xffff << shift
) & 0xffffffff;
3052 himask
= 0xffff << (shift
- 32);
3055 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3056 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3060 tmp
.X_op
= O_constant
;
3062 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3063 | (lo32
.X_add_number
>> shift
));
3065 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3066 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3067 (int) BFD_RELOC_LO16
);
3068 macro_build ((char *) NULL
, counter
, NULL
,
3069 (shift
>= 32) ? "dsll32" : "dsll",
3071 (shift
>= 32) ? shift
- 32 : shift
);
3075 } while (shift
<= (64 - 16));
3077 /* Find the bit number of the lowest one bit, and store the
3078 shifted value in hi/lo. */
3079 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3080 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3084 while ((lo
& 1) == 0)
3089 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3095 while ((hi
& 1) == 0)
3104 /* Optimize if the shifted value is a (power of 2) - 1. */
3105 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3106 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3108 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3113 /* This instruction will set the register to be all
3115 tmp
.X_op
= O_constant
;
3116 tmp
.X_add_number
= (offsetT
) -1;
3117 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3118 reg
, 0, (int) BFD_RELOC_LO16
);
3122 macro_build ((char *) NULL
, counter
, NULL
,
3123 (bit
>= 32) ? "dsll32" : "dsll",
3125 (bit
>= 32) ? bit
- 32 : bit
);
3127 macro_build ((char *) NULL
, counter
, NULL
,
3128 (shift
>= 32) ? "dsrl32" : "dsrl",
3130 (shift
>= 32) ? shift
- 32 : shift
);
3135 /* Sign extend hi32 before calling load_register, because we can
3136 generally get better code when we load a sign extended value. */
3137 if ((hi32
.X_add_number
& 0x80000000) != 0)
3138 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3139 load_register (counter
, reg
, &hi32
, 0);
3142 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3146 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3155 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3157 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3158 (int) BFD_RELOC_HI16
);
3159 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3166 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3171 mid16
.X_add_number
>>= 16;
3172 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3173 freg
, (int) BFD_RELOC_LO16
);
3174 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3178 if ((lo32
.X_add_number
& 0xffff) != 0)
3179 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3180 (int) BFD_RELOC_LO16
);
3183 /* Load an address into a register. */
3186 load_address (counter
, reg
, ep
)
3193 if (ep
->X_op
!= O_constant
3194 && ep
->X_op
!= O_symbol
)
3196 as_bad (_("expression too complex"));
3197 ep
->X_op
= O_constant
;
3200 if (ep
->X_op
== O_constant
)
3202 load_register (counter
, reg
, ep
, 0);
3206 if (mips_pic
== NO_PIC
)
3208 /* If this is a reference to a GP relative symbol, we want
3209 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3211 lui $reg,<sym> (BFD_RELOC_HI16_S)
3212 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3213 If we have an addend, we always use the latter form. */
3214 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3215 || nopic_need_relax (ep
->X_add_symbol
, 1))
3220 macro_build ((char *) NULL
, counter
, ep
,
3221 ((bfd_arch_bits_per_address (stdoutput
) == 32
3222 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3223 ? "addiu" : "daddiu"),
3224 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3225 p
= frag_var (rs_machine_dependent
, 8, 0,
3226 RELAX_ENCODE (4, 8, 0, 4, 0,
3227 mips_opts
.warn_about_macros
),
3228 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3230 macro_build_lui (p
, counter
, ep
, reg
);
3233 macro_build (p
, counter
, ep
,
3234 ((bfd_arch_bits_per_address (stdoutput
) == 32
3235 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3236 ? "addiu" : "daddiu"),
3237 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3239 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3243 /* If this is a reference to an external symbol, we want
3244 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3246 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3248 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3249 If there is a constant, it must be added in after. */
3250 ex
.X_add_number
= ep
->X_add_number
;
3251 ep
->X_add_number
= 0;
3253 macro_build ((char *) NULL
, counter
, ep
,
3254 ((bfd_arch_bits_per_address (stdoutput
) == 32
3255 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3257 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3258 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3259 p
= frag_var (rs_machine_dependent
, 4, 0,
3260 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3261 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3262 macro_build (p
, counter
, ep
,
3263 ((bfd_arch_bits_per_address (stdoutput
) == 32
3264 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3265 ? "addiu" : "daddiu"),
3266 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3267 if (ex
.X_add_number
!= 0)
3269 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3270 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3271 ex
.X_op
= O_constant
;
3272 macro_build ((char *) NULL
, counter
, &ex
,
3273 ((bfd_arch_bits_per_address (stdoutput
) == 32
3274 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3275 ? "addiu" : "daddiu"),
3276 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3279 else if (mips_pic
== SVR4_PIC
)
3284 /* This is the large GOT case. If this is a reference to an
3285 external symbol, we want
3286 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3288 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3289 Otherwise, for a reference to a local symbol, we want
3290 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3292 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3293 If there is a constant, it must be added in after. */
3294 ex
.X_add_number
= ep
->X_add_number
;
3295 ep
->X_add_number
= 0;
3296 if (reg_needs_delay (GP
))
3301 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3302 (int) BFD_RELOC_MIPS_GOT_HI16
);
3303 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3304 ((bfd_arch_bits_per_address (stdoutput
) == 32
3305 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3306 ? "addu" : "daddu"),
3307 "d,v,t", reg
, reg
, GP
);
3308 macro_build ((char *) NULL
, counter
, ep
,
3309 ((bfd_arch_bits_per_address (stdoutput
) == 32
3310 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3312 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3313 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3314 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3315 mips_opts
.warn_about_macros
),
3316 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3319 /* We need a nop before loading from $gp. This special
3320 check is required because the lui which starts the main
3321 instruction stream does not refer to $gp, and so will not
3322 insert the nop which may be required. */
3323 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3326 macro_build (p
, counter
, ep
,
3327 ((bfd_arch_bits_per_address (stdoutput
) == 32
3328 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3330 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3332 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3334 macro_build (p
, counter
, ep
,
3335 ((bfd_arch_bits_per_address (stdoutput
) == 32
3336 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3337 ? "addiu" : "daddiu"),
3338 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3339 if (ex
.X_add_number
!= 0)
3341 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3342 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3343 ex
.X_op
= O_constant
;
3344 macro_build ((char *) NULL
, counter
, &ex
,
3345 ((bfd_arch_bits_per_address (stdoutput
) == 32
3346 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3347 ? "addiu" : "daddiu"),
3348 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3351 else if (mips_pic
== EMBEDDED_PIC
)
3354 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3356 macro_build ((char *) NULL
, counter
, ep
,
3357 ((bfd_arch_bits_per_address (stdoutput
) == 32
3358 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3359 ? "addiu" : "daddiu"),
3360 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3368 * This routine implements the seemingly endless macro or synthesized
3369 * instructions and addressing modes in the mips assembly language. Many
3370 * of these macros are simple and are similar to each other. These could
3371 * probably be handled by some kind of table or grammer aproach instead of
3372 * this verbose method. Others are not simple macros but are more like
3373 * optimizing code generation.
3374 * One interesting optimization is when several store macros appear
3375 * consecutivly that would load AT with the upper half of the same address.
3376 * The ensuing load upper instructions are ommited. This implies some kind
3377 * of global optimization. We currently only optimize within a single macro.
3378 * For many of the load and store macros if the address is specified as a
3379 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3380 * first load register 'at' with zero and use it as the base register. The
3381 * mips assembler simply uses register $zero. Just one tiny optimization
3386 struct mips_cl_insn
*ip
;
3388 register int treg
, sreg
, dreg
, breg
;
3404 bfd_reloc_code_real_type r
;
3406 int hold_mips_optimize
;
3408 assert (! mips_opts
.mips16
);
3410 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3411 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3412 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3413 mask
= ip
->insn_mo
->mask
;
3415 expr1
.X_op
= O_constant
;
3416 expr1
.X_op_symbol
= NULL
;
3417 expr1
.X_add_symbol
= NULL
;
3418 expr1
.X_add_number
= 1;
3430 mips_emit_delays (true);
3431 ++mips_opts
.noreorder
;
3432 mips_any_noreorder
= 1;
3434 expr1
.X_add_number
= 8;
3435 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3437 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3439 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3440 macro_build ((char *) NULL
, &icnt
, NULL
,
3441 dbl
? "dsub" : "sub",
3442 "d,v,t", dreg
, 0, sreg
);
3444 --mips_opts
.noreorder
;
3465 if (imm_expr
.X_op
== O_constant
3466 && imm_expr
.X_add_number
>= -0x8000
3467 && imm_expr
.X_add_number
< 0x8000)
3469 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3470 (int) BFD_RELOC_LO16
);
3473 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3493 if (imm_expr
.X_op
== O_constant
3494 && imm_expr
.X_add_number
>= 0
3495 && imm_expr
.X_add_number
< 0x10000)
3497 if (mask
!= M_NOR_I
)
3498 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3499 sreg
, (int) BFD_RELOC_LO16
);
3502 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3503 treg
, sreg
, (int) BFD_RELOC_LO16
);
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3510 load_register (&icnt
, AT
, &imm_expr
, 0);
3511 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3528 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3534 load_register (&icnt
, AT
, &imm_expr
, 0);
3535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3544 likely
? "bgezl" : "bgez",
3550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3551 likely
? "blezl" : "blez",
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3557 likely
? "beql" : "beq",
3564 /* check for > max integer */
3565 maxnum
= 0x7fffffff;
3566 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3573 if (imm_expr
.X_op
== O_constant
3574 && imm_expr
.X_add_number
>= maxnum
3575 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3578 /* result is always false */
3581 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3582 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3586 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3592 if (imm_expr
.X_op
!= O_constant
)
3593 as_bad (_("Unsupported large constant"));
3594 imm_expr
.X_add_number
++;
3598 if (mask
== M_BGEL_I
)
3600 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3603 likely
? "bgezl" : "bgez",
3607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3609 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3610 likely
? "bgtzl" : "bgtz",
3614 maxnum
= 0x7fffffff;
3615 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3622 maxnum
= - maxnum
- 1;
3623 if (imm_expr
.X_op
== O_constant
3624 && imm_expr
.X_add_number
<= maxnum
3625 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3628 /* result is always true */
3629 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3633 set_at (&icnt
, sreg
, 0);
3634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3635 likely
? "beql" : "beq",
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "beql" : "beq",
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3654 likely
? "beql" : "beq",
3662 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3663 && imm_expr
.X_op
== O_constant
3664 && imm_expr
.X_add_number
== 0xffffffff))
3666 if (imm_expr
.X_op
!= O_constant
)
3667 as_bad (_("Unsupported large constant"));
3668 imm_expr
.X_add_number
++;
3672 if (mask
== M_BGEUL_I
)
3674 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3676 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3679 likely
? "bnel" : "bne",
3683 set_at (&icnt
, sreg
, 1);
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3685 likely
? "beql" : "beq",
3694 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3695 likely
? "bgtzl" : "bgtz",
3701 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3702 likely
? "bltzl" : "bltz",
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3707 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3708 likely
? "bnel" : "bne",
3717 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3718 likely
? "bnel" : "bne",
3724 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3727 likely
? "bnel" : "bne",
3736 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3737 likely
? "blezl" : "blez",
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3744 likely
? "bgezl" : "bgez",
3748 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3749 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3750 likely
? "beql" : "beq",
3757 maxnum
= 0x7fffffff;
3758 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3765 if (imm_expr
.X_op
== O_constant
3766 && imm_expr
.X_add_number
>= maxnum
3767 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3769 if (imm_expr
.X_op
!= O_constant
)
3770 as_bad (_("Unsupported large constant"));
3771 imm_expr
.X_add_number
++;
3775 if (mask
== M_BLTL_I
)
3777 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3779 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3780 likely
? "bltzl" : "bltz",
3784 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3787 likely
? "blezl" : "blez",
3791 set_at (&icnt
, sreg
, 0);
3792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3793 likely
? "bnel" : "bne",
3802 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3803 likely
? "beql" : "beq",
3809 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "beql" : "beq",
3820 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3821 && imm_expr
.X_op
== O_constant
3822 && imm_expr
.X_add_number
== 0xffffffff))
3824 if (imm_expr
.X_op
!= O_constant
)
3825 as_bad (_("Unsupported large constant"));
3826 imm_expr
.X_add_number
++;
3830 if (mask
== M_BLTUL_I
)
3832 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3834 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3837 likely
? "beql" : "beq",
3841 set_at (&icnt
, sreg
, 1);
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "bnel" : "bne",
3852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3853 likely
? "bltzl" : "bltz",
3859 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3860 likely
? "bgtzl" : "bgtz",
3864 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3866 likely
? "bnel" : "bne",
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 likely
? "bnel" : "bne",
3882 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3885 likely
? "bnel" : "bne",
3901 as_warn (_("Divide by zero."));
3903 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3905 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3909 mips_emit_delays (true);
3910 ++mips_opts
.noreorder
;
3911 mips_any_noreorder
= 1;
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3915 macro_build ((char *) NULL
, &icnt
, NULL
,
3916 dbl
? "ddiv" : "div",
3917 "z,s,t", sreg
, treg
);
3921 expr1
.X_add_number
= 8;
3922 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3923 macro_build ((char *) NULL
, &icnt
, NULL
,
3924 dbl
? "ddiv" : "div",
3925 "z,s,t", sreg
, treg
);
3926 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3928 expr1
.X_add_number
= -1;
3929 macro_build ((char *) NULL
, &icnt
, &expr1
,
3930 dbl
? "daddiu" : "addiu",
3931 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3932 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3933 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3936 expr1
.X_add_number
= 1;
3937 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3938 (int) BFD_RELOC_LO16
);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3944 expr1
.X_add_number
= 0x80000000;
3945 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3946 (int) BFD_RELOC_HI16
);
3950 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3951 /* We want to close the noreorder block as soon as possible, so
3952 that later insns are available for delay slot filling. */
3953 --mips_opts
.noreorder
;
3957 expr1
.X_add_number
= 8;
3958 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3961 /* We want to close the noreorder block as soon as possible, so
3962 that later insns are available for delay slot filling. */
3963 --mips_opts
.noreorder
;
3965 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3967 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4006 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4008 as_warn (_("Divide by zero."));
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4012 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4015 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4017 if (strcmp (s2
, "mflo") == 0)
4018 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4021 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4024 if (imm_expr
.X_op
== O_constant
4025 && imm_expr
.X_add_number
== -1
4026 && s
[strlen (s
) - 1] != 'u')
4028 if (strcmp (s2
, "mflo") == 0)
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4034 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4038 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4042 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4043 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4044 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4063 mips_emit_delays (true);
4064 ++mips_opts
.noreorder
;
4065 mips_any_noreorder
= 1;
4068 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4070 /* We want to close the noreorder block as soon as possible, so
4071 that later insns are available for delay slot filling. */
4072 --mips_opts
.noreorder
;
4076 expr1
.X_add_number
= 8;
4077 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4080 /* We want to close the noreorder block as soon as possible, so
4081 that later insns are available for delay slot filling. */
4082 --mips_opts
.noreorder
;
4083 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4085 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4091 /* Load the address of a symbol into a register. If breg is not
4092 zero, we then add a base register to it. */
4094 /* When generating embedded PIC code, we permit expressions of
4097 where bar is an address in the .text section. These are used
4098 when getting the addresses of functions. We don't permit
4099 X_add_number to be non-zero, because if the symbol is
4100 external the relaxing code needs to know that any addend is
4101 purely the offset to X_op_symbol. */
4102 if (mips_pic
== EMBEDDED_PIC
4103 && offset_expr
.X_op
== O_subtract
4104 && now_seg
== text_section
4105 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4106 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4107 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4109 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4113 && offset_expr
.X_add_number
== 0)
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4116 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4118 ((bfd_arch_bits_per_address (stdoutput
) == 32
4119 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4120 ? "addiu" : "daddiu"),
4121 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4125 if (offset_expr
.X_op
!= O_symbol
4126 && offset_expr
.X_op
!= O_constant
)
4128 as_bad (_("expression too complex"));
4129 offset_expr
.X_op
= O_constant
;
4143 if (offset_expr
.X_op
== O_constant
)
4144 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4145 else if (mips_pic
== NO_PIC
)
4147 /* If this is a reference to an GP relative symbol, we want
4148 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4150 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4151 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4152 If we have a constant, we need two instructions anyhow,
4153 so we may as well always use the latter form. */
4154 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4155 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 ((bfd_arch_bits_per_address (stdoutput
) == 32
4162 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4163 ? "addiu" : "daddiu"),
4164 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4165 p
= frag_var (rs_machine_dependent
, 8, 0,
4166 RELAX_ENCODE (4, 8, 0, 4, 0,
4167 mips_opts
.warn_about_macros
),
4168 offset_expr
.X_add_symbol
, (offsetT
) 0,
4171 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4174 macro_build (p
, &icnt
, &offset_expr
,
4175 ((bfd_arch_bits_per_address (stdoutput
) == 32
4176 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4177 ? "addiu" : "daddiu"),
4178 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4180 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4182 /* If this is a reference to an external symbol, and there
4183 is no constant, we want
4184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4185 For a local symbol, we want
4186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4190 If we have a small constant, and this is a reference to
4191 an external symbol, we want
4192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4194 addiu $tempreg,$tempreg,<constant>
4195 For a local symbol, we want the same instruction
4196 sequence, but we output a BFD_RELOC_LO16 reloc on the
4199 If we have a large constant, and this is a reference to
4200 an external symbol, we want
4201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4202 lui $at,<hiconstant>
4203 addiu $at,$at,<loconstant>
4204 addu $tempreg,$tempreg,$at
4205 For a local symbol, we want the same instruction
4206 sequence, but we output a BFD_RELOC_LO16 reloc on the
4207 addiu instruction. */
4208 expr1
.X_add_number
= offset_expr
.X_add_number
;
4209 offset_expr
.X_add_number
= 0;
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4213 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4214 if (expr1
.X_add_number
== 0)
4222 /* We're going to put in an addu instruction using
4223 tempreg, so we may as well insert the nop right
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4229 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4230 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4232 ? mips_opts
.warn_about_macros
4234 offset_expr
.X_add_symbol
, (offsetT
) 0,
4238 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4241 macro_build (p
, &icnt
, &expr1
,
4242 ((bfd_arch_bits_per_address (stdoutput
) == 32
4243 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4244 ? "addiu" : "daddiu"),
4245 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4246 /* FIXME: If breg == 0, and the next instruction uses
4247 $tempreg, then if this variant case is used an extra
4248 nop will be generated. */
4250 else if (expr1
.X_add_number
>= -0x8000
4251 && expr1
.X_add_number
< 0x8000)
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4255 macro_build ((char *) NULL
, &icnt
, &expr1
,
4256 ((bfd_arch_bits_per_address (stdoutput
) == 32
4257 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4258 ? "addiu" : "daddiu"),
4259 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4260 (void) frag_var (rs_machine_dependent
, 0, 0,
4261 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4262 offset_expr
.X_add_symbol
, (offsetT
) 0,
4269 /* If we are going to add in a base register, and the
4270 target register and the base register are the same,
4271 then we are using AT as a temporary register. Since
4272 we want to load the constant into AT, we add our
4273 current AT (from the global offset table) and the
4274 register into the register now, and pretend we were
4275 not using a base register. */
4280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4283 ((bfd_arch_bits_per_address (stdoutput
) == 32
4284 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4285 ? "addu" : "daddu"),
4286 "d,v,t", treg
, AT
, breg
);
4292 /* Set mips_optimize around the lui instruction to avoid
4293 inserting an unnecessary nop after the lw. */
4294 hold_mips_optimize
= mips_optimize
;
4296 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4297 mips_optimize
= hold_mips_optimize
;
4299 macro_build ((char *) NULL
, &icnt
, &expr1
,
4300 ((bfd_arch_bits_per_address (stdoutput
) == 32
4301 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4302 ? "addiu" : "daddiu"),
4303 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4305 ((bfd_arch_bits_per_address (stdoutput
) == 32
4306 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4307 ? "addu" : "daddu"),
4308 "d,v,t", tempreg
, tempreg
, AT
);
4309 (void) frag_var (rs_machine_dependent
, 0, 0,
4310 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4311 offset_expr
.X_add_symbol
, (offsetT
) 0,
4316 else if (mips_pic
== SVR4_PIC
)
4320 /* This is the large GOT case. If this is a reference to an
4321 external symbol, and there is no constant, we want
4322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4323 addu $tempreg,$tempreg,$gp
4324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4325 For a local symbol, we want
4326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4328 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4330 If we have a small constant, and this is a reference to
4331 an external symbol, we want
4332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4333 addu $tempreg,$tempreg,$gp
4334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4336 addiu $tempreg,$tempreg,<constant>
4337 For a local symbol, we want
4338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4340 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4342 If we have a large constant, and this is a reference to
4343 an external symbol, we want
4344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4345 addu $tempreg,$tempreg,$gp
4346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4347 lui $at,<hiconstant>
4348 addiu $at,$at,<loconstant>
4349 addu $tempreg,$tempreg,$at
4350 For a local symbol, we want
4351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4352 lui $at,<hiconstant>
4353 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4354 addu $tempreg,$tempreg,$at
4356 expr1
.X_add_number
= offset_expr
.X_add_number
;
4357 offset_expr
.X_add_number
= 0;
4359 if (reg_needs_delay (GP
))
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4364 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4366 ((bfd_arch_bits_per_address (stdoutput
) == 32
4367 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4368 ? "addu" : "daddu"),
4369 "d,v,t", tempreg
, tempreg
, GP
);
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4372 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4374 if (expr1
.X_add_number
== 0)
4382 /* We're going to put in an addu instruction using
4383 tempreg, so we may as well insert the nop right
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4390 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4391 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4394 ? mips_opts
.warn_about_macros
4396 offset_expr
.X_add_symbol
, (offsetT
) 0,
4399 else if (expr1
.X_add_number
>= -0x8000
4400 && expr1
.X_add_number
< 0x8000)
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4404 macro_build ((char *) NULL
, &icnt
, &expr1
,
4405 ((bfd_arch_bits_per_address (stdoutput
) == 32
4406 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4407 ? "addiu" : "daddiu"),
4408 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4410 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4411 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4413 ? mips_opts
.warn_about_macros
4415 offset_expr
.X_add_symbol
, (offsetT
) 0,
4422 /* If we are going to add in a base register, and the
4423 target register and the base register are the same,
4424 then we are using AT as a temporary register. Since
4425 we want to load the constant into AT, we add our
4426 current AT (from the global offset table) and the
4427 register into the register now, and pretend we were
4428 not using a base register. */
4436 assert (tempreg
== AT
);
4437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4440 ((bfd_arch_bits_per_address (stdoutput
) == 32
4441 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4442 ? "addu" : "daddu"),
4443 "d,v,t", treg
, AT
, breg
);
4448 /* Set mips_optimize around the lui instruction to avoid
4449 inserting an unnecessary nop after the lw. */
4450 hold_mips_optimize
= mips_optimize
;
4452 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4453 mips_optimize
= hold_mips_optimize
;
4455 macro_build ((char *) NULL
, &icnt
, &expr1
,
4456 ((bfd_arch_bits_per_address (stdoutput
) == 32
4457 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4458 ? "addiu" : "daddiu"),
4459 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 ((bfd_arch_bits_per_address (stdoutput
) == 32
4462 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4463 ? "addu" : "daddu"),
4464 "d,v,t", dreg
, dreg
, AT
);
4466 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4467 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4470 ? mips_opts
.warn_about_macros
4472 offset_expr
.X_add_symbol
, (offsetT
) 0,
4480 /* This is needed because this instruction uses $gp, but
4481 the first instruction on the main stream does not. */
4482 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4485 macro_build (p
, &icnt
, &offset_expr
,
4487 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4489 if (expr1
.X_add_number
>= -0x8000
4490 && expr1
.X_add_number
< 0x8000)
4492 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4494 macro_build (p
, &icnt
, &expr1
,
4495 ((bfd_arch_bits_per_address (stdoutput
) == 32
4496 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4497 ? "addiu" : "daddiu"),
4498 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4499 /* FIXME: If add_number is 0, and there was no base
4500 register, the external symbol case ended with a load,
4501 so if the symbol turns out to not be external, and
4502 the next instruction uses tempreg, an unnecessary nop
4503 will be inserted. */
4509 /* We must add in the base register now, as in the
4510 external symbol case. */
4511 assert (tempreg
== AT
);
4512 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4514 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4515 ((bfd_arch_bits_per_address (stdoutput
) == 32
4516 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4517 ? "addu" : "daddu"),
4518 "d,v,t", treg
, AT
, breg
);
4521 /* We set breg to 0 because we have arranged to add
4522 it in in both cases. */
4526 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4528 macro_build (p
, &icnt
, &expr1
,
4529 ((bfd_arch_bits_per_address (stdoutput
) == 32
4530 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4531 ? "addiu" : "daddiu"),
4532 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4534 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4535 ((bfd_arch_bits_per_address (stdoutput
) == 32
4536 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4537 ? "addu" : "daddu"),
4538 "d,v,t", tempreg
, tempreg
, AT
);
4542 else if (mips_pic
== EMBEDDED_PIC
)
4545 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4548 ((bfd_arch_bits_per_address (stdoutput
) == 32
4549 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4550 ? "addiu" : "daddiu"),
4551 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4558 ((bfd_arch_bits_per_address (stdoutput
) == 32
4559 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4560 ? "addu" : "daddu"),
4561 "d,v,t", treg
, tempreg
, breg
);
4569 /* The j instruction may not be used in PIC code, since it
4570 requires an absolute address. We convert it to a b
4572 if (mips_pic
== NO_PIC
)
4573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4578 /* The jal instructions must be handled as macros because when
4579 generating PIC code they expand to multi-instruction
4580 sequences. Normally they are simple instructions. */
4585 if (mips_pic
== NO_PIC
4586 || mips_pic
== EMBEDDED_PIC
)
4587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4589 else if (mips_pic
== SVR4_PIC
)
4591 if (sreg
!= PIC_CALL_REG
)
4592 as_warn (_("MIPS PIC call to register other than $25"));
4594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4596 if (mips_cprestore_offset
< 0)
4597 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4600 expr1
.X_add_number
= mips_cprestore_offset
;
4601 macro_build ((char *) NULL
, &icnt
, &expr1
,
4602 ((bfd_arch_bits_per_address (stdoutput
) == 32
4603 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4605 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4614 if (mips_pic
== NO_PIC
)
4615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4616 else if (mips_pic
== SVR4_PIC
)
4618 /* If this is a reference to an external symbol, and we are
4619 using a small GOT, we want
4620 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4624 lw $gp,cprestore($sp)
4625 The cprestore value is set using the .cprestore
4626 pseudo-op. If we are using a big GOT, we want
4627 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4629 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4633 lw $gp,cprestore($sp)
4634 If the symbol is not external, we want
4635 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4637 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4640 lw $gp,cprestore($sp) */
4644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4645 ((bfd_arch_bits_per_address (stdoutput
) == 32
4646 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4648 "t,o(b)", PIC_CALL_REG
,
4649 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4652 p
= frag_var (rs_machine_dependent
, 4, 0,
4653 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4654 offset_expr
.X_add_symbol
, (offsetT
) 0,
4661 if (reg_needs_delay (GP
))
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4666 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4668 ((bfd_arch_bits_per_address (stdoutput
) == 32
4669 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4670 ? "addu" : "daddu"),
4671 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4673 ((bfd_arch_bits_per_address (stdoutput
) == 32
4674 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4676 "t,o(b)", PIC_CALL_REG
,
4677 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4680 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4681 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4683 offset_expr
.X_add_symbol
, (offsetT
) 0,
4687 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4690 macro_build (p
, &icnt
, &offset_expr
,
4691 ((bfd_arch_bits_per_address (stdoutput
) == 32
4692 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4694 "t,o(b)", PIC_CALL_REG
,
4695 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4697 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4700 macro_build (p
, &icnt
, &offset_expr
,
4701 ((bfd_arch_bits_per_address (stdoutput
) == 32
4702 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4703 ? "addiu" : "daddiu"),
4704 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4705 (int) BFD_RELOC_LO16
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4707 "jalr", "s", PIC_CALL_REG
);
4708 if (mips_cprestore_offset
< 0)
4709 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4712 if (mips_opts
.noreorder
)
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4715 expr1
.X_add_number
= mips_cprestore_offset
;
4716 macro_build ((char *) NULL
, &icnt
, &expr1
,
4717 ((bfd_arch_bits_per_address (stdoutput
) == 32
4718 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4720 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4724 else if (mips_pic
== EMBEDDED_PIC
)
4726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4727 /* The linker may expand the call to a longer sequence which
4728 uses $at, so we must break rather than return. */
4753 /* Itbl support may require additional care here. */
4758 /* Itbl support may require additional care here. */
4763 /* Itbl support may require additional care here. */
4768 /* Itbl support may require additional care here. */
4780 if (mips_cpu
== 4650)
4782 as_bad (_("opcode not supported on this processor"));
4786 /* Itbl support may require additional care here. */
4791 /* Itbl support may require additional care here. */
4796 /* Itbl support may require additional care here. */
4816 if (breg
== treg
|| coproc
|| lr
)
4838 /* Itbl support may require additional care here. */
4843 /* Itbl support may require additional care here. */
4848 /* Itbl support may require additional care here. */
4853 /* Itbl support may require additional care here. */
4869 if (mips_cpu
== 4650)
4871 as_bad (_("opcode not supported on this processor"));
4876 /* Itbl support may require additional care here. */
4880 /* Itbl support may require additional care here. */
4885 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4898 if (mask
== M_LWC1_AB
4899 || mask
== M_SWC1_AB
4900 || mask
== M_LDC1_AB
4901 || mask
== M_SDC1_AB
4910 if (offset_expr
.X_op
!= O_constant
4911 && offset_expr
.X_op
!= O_symbol
)
4913 as_bad (_("expression too complex"));
4914 offset_expr
.X_op
= O_constant
;
4917 /* A constant expression in PIC code can be handled just as it
4918 is in non PIC code. */
4919 if (mips_pic
== NO_PIC
4920 || offset_expr
.X_op
== O_constant
)
4922 /* If this is a reference to a GP relative symbol, and there
4923 is no base register, we want
4924 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4925 Otherwise, if there is no base register, we want
4926 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4927 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4928 If we have a constant, we need two instructions anyhow,
4929 so we always use the latter form.
4931 If we have a base register, and this is a reference to a
4932 GP relative symbol, we want
4933 addu $tempreg,$breg,$gp
4934 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4937 addu $tempreg,$tempreg,$breg
4938 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4939 With a constant we always use the latter case. */
4942 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4943 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4949 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4950 p
= frag_var (rs_machine_dependent
, 8, 0,
4951 RELAX_ENCODE (4, 8, 0, 4, 0,
4952 (mips_opts
.warn_about_macros
4954 && mips_opts
.noat
))),
4955 offset_expr
.X_add_symbol
, (offsetT
) 0,
4959 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4962 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4963 (int) BFD_RELOC_LO16
, tempreg
);
4967 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4968 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4974 ((bfd_arch_bits_per_address (stdoutput
) == 32
4975 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4976 ? "addu" : "daddu"),
4977 "d,v,t", tempreg
, breg
, GP
);
4978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4979 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4980 p
= frag_var (rs_machine_dependent
, 12, 0,
4981 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4982 offset_expr
.X_add_symbol
, (offsetT
) 0,
4985 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4988 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4989 ((bfd_arch_bits_per_address (stdoutput
) == 32
4990 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4991 ? "addu" : "daddu"),
4992 "d,v,t", tempreg
, tempreg
, breg
);
4995 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4996 (int) BFD_RELOC_LO16
, tempreg
);
4999 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5001 /* If this is a reference to an external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 <op> $treg,0($tempreg)
5006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5008 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5009 <op> $treg,0($tempreg)
5010 If there is a base register, we add it to $tempreg before
5011 the <op>. If there is a constant, we stick it in the
5012 <op> instruction. We don't handle constants larger than
5013 16 bits, because we have no way to load the upper 16 bits
5014 (actually, we could handle them for the subset of cases
5015 in which we are not using $at). */
5016 assert (offset_expr
.X_op
== O_symbol
);
5017 expr1
.X_add_number
= offset_expr
.X_add_number
;
5018 offset_expr
.X_add_number
= 0;
5019 if (expr1
.X_add_number
< -0x8000
5020 || expr1
.X_add_number
>= 0x8000)
5021 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5024 ((bfd_arch_bits_per_address (stdoutput
) == 32
5025 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5027 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5029 p
= frag_var (rs_machine_dependent
, 4, 0,
5030 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5031 offset_expr
.X_add_symbol
, (offsetT
) 0,
5033 macro_build (p
, &icnt
, &offset_expr
,
5034 ((bfd_arch_bits_per_address (stdoutput
) == 32
5035 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5036 ? "addiu" : "daddiu"),
5037 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5040 ((bfd_arch_bits_per_address (stdoutput
) == 32
5041 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5042 ? "addu" : "daddu"),
5043 "d,v,t", tempreg
, tempreg
, breg
);
5044 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5045 (int) BFD_RELOC_LO16
, tempreg
);
5047 else if (mips_pic
== SVR4_PIC
)
5051 /* If this is a reference to an external symbol, we want
5052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5053 addu $tempreg,$tempreg,$gp
5054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5055 <op> $treg,0($tempreg)
5057 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5059 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5060 <op> $treg,0($tempreg)
5061 If there is a base register, we add it to $tempreg before
5062 the <op>. If there is a constant, we stick it in the
5063 <op> instruction. We don't handle constants larger than
5064 16 bits, because we have no way to load the upper 16 bits
5065 (actually, we could handle them for the subset of cases
5066 in which we are not using $at). */
5067 assert (offset_expr
.X_op
== O_symbol
);
5068 expr1
.X_add_number
= offset_expr
.X_add_number
;
5069 offset_expr
.X_add_number
= 0;
5070 if (expr1
.X_add_number
< -0x8000
5071 || expr1
.X_add_number
>= 0x8000)
5072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5073 if (reg_needs_delay (GP
))
5078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5079 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5081 ((bfd_arch_bits_per_address (stdoutput
) == 32
5082 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5083 ? "addu" : "daddu"),
5084 "d,v,t", tempreg
, tempreg
, GP
);
5085 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5086 ((bfd_arch_bits_per_address (stdoutput
) == 32
5087 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5089 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5091 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5092 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5093 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5096 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5099 macro_build (p
, &icnt
, &offset_expr
,
5100 ((bfd_arch_bits_per_address (stdoutput
) == 32
5101 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5103 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5105 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5107 macro_build (p
, &icnt
, &offset_expr
,
5108 ((bfd_arch_bits_per_address (stdoutput
) == 32
5109 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5110 ? "addiu" : "daddiu"),
5111 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5114 ((bfd_arch_bits_per_address (stdoutput
) == 32
5115 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5116 ? "addu" : "daddu"),
5117 "d,v,t", tempreg
, tempreg
, breg
);
5118 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5119 (int) BFD_RELOC_LO16
, tempreg
);
5121 else if (mips_pic
== EMBEDDED_PIC
)
5123 /* If there is no base register, we want
5124 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5125 If there is a base register, we want
5126 addu $tempreg,$breg,$gp
5127 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5129 assert (offset_expr
.X_op
== O_symbol
);
5132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5133 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5141 ? "addu" : "daddu"),
5142 "d,v,t", tempreg
, breg
, GP
);
5143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5144 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5157 load_register (&icnt
, treg
, &imm_expr
, 0);
5161 load_register (&icnt
, treg
, &imm_expr
, 1);
5165 if (imm_expr
.X_op
== O_constant
)
5167 load_register (&icnt
, AT
, &imm_expr
, 0);
5168 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5169 "mtc1", "t,G", AT
, treg
);
5174 assert (offset_expr
.X_op
== O_symbol
5175 && strcmp (segment_name (S_GET_SEGMENT
5176 (offset_expr
.X_add_symbol
)),
5178 && offset_expr
.X_add_number
== 0);
5179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5180 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5185 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5186 the entire value, and in mips1 mode it is the high order 32
5187 bits of the value and the low order 32 bits are either zero
5188 or in offset_expr. */
5189 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5191 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5192 load_register (&icnt
, treg
, &imm_expr
, 1);
5197 if (target_big_endian
)
5209 load_register (&icnt
, hreg
, &imm_expr
, 0);
5212 if (offset_expr
.X_op
== O_absent
)
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5217 assert (offset_expr
.X_op
== O_constant
);
5218 load_register (&icnt
, lreg
, &offset_expr
, 0);
5225 /* We know that sym is in the .rdata section. First we get the
5226 upper 16 bits of the address. */
5227 if (mips_pic
== NO_PIC
)
5229 /* FIXME: This won't work for a 64 bit address. */
5230 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5232 else if (mips_pic
== SVR4_PIC
)
5234 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5235 ((bfd_arch_bits_per_address (stdoutput
) == 32
5236 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5238 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5240 else if (mips_pic
== EMBEDDED_PIC
)
5242 /* For embedded PIC we pick up the entire address off $gp in
5243 a single instruction. */
5244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5245 ((bfd_arch_bits_per_address (stdoutput
) == 32
5246 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5247 ? "addiu" : "daddiu"),
5248 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5249 offset_expr
.X_op
= O_constant
;
5250 offset_expr
.X_add_number
= 0;
5255 /* Now we load the register(s). */
5256 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5257 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5258 treg
, (int) BFD_RELOC_LO16
, AT
);
5261 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5262 treg
, (int) BFD_RELOC_LO16
, AT
);
5265 /* FIXME: How in the world do we deal with the possible
5267 offset_expr
.X_add_number
+= 4;
5268 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5269 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5273 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5274 does not become a variant frag. */
5275 frag_wane (frag_now
);
5281 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5282 the entire value, and in mips1 mode it is the high order 32
5283 bits of the value and the low order 32 bits are either zero
5284 or in offset_expr. */
5285 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5287 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5288 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5290 "dmtc1", "t,S", AT
, treg
);
5293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5294 "mtc1", "t,G", AT
, treg
+ 1);
5295 if (offset_expr
.X_op
== O_absent
)
5296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5297 "mtc1", "t,G", 0, treg
);
5300 assert (offset_expr
.X_op
== O_constant
);
5301 load_register (&icnt
, AT
, &offset_expr
, 0);
5302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5303 "mtc1", "t,G", AT
, treg
);
5309 assert (offset_expr
.X_op
== O_symbol
5310 && offset_expr
.X_add_number
== 0);
5311 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5312 if (strcmp (s
, ".lit8") == 0)
5314 if (mips_opts
.isa
!= 1)
5316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5317 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5321 r
= BFD_RELOC_MIPS_LITERAL
;
5326 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5327 if (mips_pic
== SVR4_PIC
)
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5329 ((bfd_arch_bits_per_address (stdoutput
) == 32
5330 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5332 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5335 /* FIXME: This won't work for a 64 bit address. */
5336 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5339 if (mips_opts
.isa
!= 1)
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5342 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5344 /* To avoid confusion in tc_gen_reloc, we must ensure
5345 that this does not become a variant frag. */
5346 frag_wane (frag_now
);
5357 if (mips_cpu
== 4650)
5359 as_bad (_("opcode not supported on this processor"));
5362 /* Even on a big endian machine $fn comes before $fn+1. We have
5363 to adjust when loading from memory. */
5366 assert (mips_opts
.isa
== 1);
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5368 target_big_endian
? treg
+ 1 : treg
,
5370 /* FIXME: A possible overflow which I don't know how to deal
5372 offset_expr
.X_add_number
+= 4;
5373 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5374 target_big_endian
? treg
: treg
+ 1,
5377 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5378 does not become a variant frag. */
5379 frag_wane (frag_now
);
5388 * The MIPS assembler seems to check for X_add_number not
5389 * being double aligned and generating:
5392 * addiu at,at,%lo(foo+1)
5395 * But, the resulting address is the same after relocation so why
5396 * generate the extra instruction?
5398 if (mips_cpu
== 4650)
5400 as_bad (_("opcode not supported on this processor"));
5403 /* Itbl support may require additional care here. */
5405 if (mips_opts
.isa
!= 1)
5416 if (mips_cpu
== 4650)
5418 as_bad (_("opcode not supported on this processor"));
5422 if (mips_opts
.isa
!= 1)
5430 /* Itbl support may require additional care here. */
5435 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5446 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5456 if (offset_expr
.X_op
!= O_symbol
5457 && offset_expr
.X_op
!= O_constant
)
5459 as_bad (_("expression too complex"));
5460 offset_expr
.X_op
= O_constant
;
5463 /* Even on a big endian machine $fn comes before $fn+1. We have
5464 to adjust when loading from memory. We set coproc if we must
5465 load $fn+1 first. */
5466 /* Itbl support may require additional care here. */
5467 if (! target_big_endian
)
5470 if (mips_pic
== NO_PIC
5471 || offset_expr
.X_op
== O_constant
)
5473 /* If this is a reference to a GP relative symbol, we want
5474 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5475 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5476 If we have a base register, we use this
5478 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5479 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5480 If this is not a GP relative symbol, we want
5481 lui $at,<sym> (BFD_RELOC_HI16_S)
5482 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5483 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5484 If there is a base register, we add it to $at after the
5485 lui instruction. If there is a constant, we always use
5487 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5488 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5508 ((bfd_arch_bits_per_address (stdoutput
) == 32
5509 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5510 ? "addu" : "daddu"),
5511 "d,v,t", AT
, breg
, GP
);
5517 /* Itbl support may require additional care here. */
5518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5519 coproc
? treg
+ 1 : treg
,
5520 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5521 offset_expr
.X_add_number
+= 4;
5523 /* Set mips_optimize to 2 to avoid inserting an
5525 hold_mips_optimize
= mips_optimize
;
5527 /* Itbl support may require additional care here. */
5528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5529 coproc
? treg
: treg
+ 1,
5530 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5531 mips_optimize
= hold_mips_optimize
;
5533 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5534 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5535 used_at
&& mips_opts
.noat
),
5536 offset_expr
.X_add_symbol
, (offsetT
) 0,
5539 /* We just generated two relocs. When tc_gen_reloc
5540 handles this case, it will skip the first reloc and
5541 handle the second. The second reloc already has an
5542 extra addend of 4, which we added above. We must
5543 subtract it out, and then subtract another 4 to make
5544 the first reloc come out right. The second reloc
5545 will come out right because we are going to add 4 to
5546 offset_expr when we build its instruction below.
5548 If we have a symbol, then we don't want to include
5549 the offset, because it will wind up being included
5550 when we generate the reloc. */
5552 if (offset_expr
.X_op
== O_constant
)
5553 offset_expr
.X_add_number
-= 8;
5556 offset_expr
.X_add_number
= -4;
5557 offset_expr
.X_op
= O_constant
;
5560 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5565 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5566 ((bfd_arch_bits_per_address (stdoutput
) == 32
5567 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5568 ? "addu" : "daddu"),
5569 "d,v,t", AT
, breg
, AT
);
5573 /* Itbl support may require additional care here. */
5574 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5575 coproc
? treg
+ 1 : treg
,
5576 (int) BFD_RELOC_LO16
, AT
);
5579 /* FIXME: How do we handle overflow here? */
5580 offset_expr
.X_add_number
+= 4;
5581 /* Itbl support may require additional care here. */
5582 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5583 coproc
? treg
: treg
+ 1,
5584 (int) BFD_RELOC_LO16
, AT
);
5586 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5590 /* If this is a reference to an external symbol, we want
5591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5598 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5599 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5600 If there is a base register we add it to $at before the
5601 lwc1 instructions. If there is a constant we include it
5602 in the lwc1 instructions. */
5604 expr1
.X_add_number
= offset_expr
.X_add_number
;
5605 offset_expr
.X_add_number
= 0;
5606 if (expr1
.X_add_number
< -0x8000
5607 || expr1
.X_add_number
>= 0x8000 - 4)
5608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5613 frag_grow (24 + off
);
5614 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5615 ((bfd_arch_bits_per_address (stdoutput
) == 32
5616 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5618 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5622 ((bfd_arch_bits_per_address (stdoutput
) == 32
5623 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5624 ? "addu" : "daddu"),
5625 "d,v,t", AT
, breg
, AT
);
5626 /* Itbl support may require additional care here. */
5627 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5628 coproc
? treg
+ 1 : treg
,
5629 (int) BFD_RELOC_LO16
, AT
);
5630 expr1
.X_add_number
+= 4;
5632 /* Set mips_optimize to 2 to avoid inserting an undesired
5634 hold_mips_optimize
= mips_optimize
;
5636 /* Itbl support may require additional care here. */
5637 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5638 coproc
? treg
: treg
+ 1,
5639 (int) BFD_RELOC_LO16
, AT
);
5640 mips_optimize
= hold_mips_optimize
;
5642 (void) frag_var (rs_machine_dependent
, 0, 0,
5643 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5644 offset_expr
.X_add_symbol
, (offsetT
) 0,
5647 else if (mips_pic
== SVR4_PIC
)
5651 /* If this is a reference to an external symbol, we want
5652 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5654 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5661 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5662 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5663 If there is a base register we add it to $at before the
5664 lwc1 instructions. If there is a constant we include it
5665 in the lwc1 instructions. */
5667 expr1
.X_add_number
= offset_expr
.X_add_number
;
5668 offset_expr
.X_add_number
= 0;
5669 if (expr1
.X_add_number
< -0x8000
5670 || expr1
.X_add_number
>= 0x8000 - 4)
5671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5672 if (reg_needs_delay (GP
))
5681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5682 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5684 ((bfd_arch_bits_per_address (stdoutput
) == 32
5685 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5686 ? "addu" : "daddu"),
5687 "d,v,t", AT
, AT
, GP
);
5688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5689 ((bfd_arch_bits_per_address (stdoutput
) == 32
5690 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5692 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5696 ((bfd_arch_bits_per_address (stdoutput
) == 32
5697 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5698 ? "addu" : "daddu"),
5699 "d,v,t", AT
, breg
, AT
);
5700 /* Itbl support may require additional care here. */
5701 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5702 coproc
? treg
+ 1 : treg
,
5703 (int) BFD_RELOC_LO16
, AT
);
5704 expr1
.X_add_number
+= 4;
5706 /* Set mips_optimize to 2 to avoid inserting an undesired
5708 hold_mips_optimize
= mips_optimize
;
5710 /* Itbl support may require additional care here. */
5711 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5712 coproc
? treg
: treg
+ 1,
5713 (int) BFD_RELOC_LO16
, AT
);
5714 mips_optimize
= hold_mips_optimize
;
5715 expr1
.X_add_number
-= 4;
5717 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5718 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5719 8 + gpdel
+ off
, 1, 0),
5720 offset_expr
.X_add_symbol
, (offsetT
) 0,
5724 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5727 macro_build (p
, &icnt
, &offset_expr
,
5728 ((bfd_arch_bits_per_address (stdoutput
) == 32
5729 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5731 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5733 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5738 ((bfd_arch_bits_per_address (stdoutput
) == 32
5739 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5740 ? "addu" : "daddu"),
5741 "d,v,t", AT
, breg
, AT
);
5744 /* Itbl support may require additional care here. */
5745 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5746 coproc
? treg
+ 1 : treg
,
5747 (int) BFD_RELOC_LO16
, AT
);
5749 expr1
.X_add_number
+= 4;
5751 /* Set mips_optimize to 2 to avoid inserting an undesired
5753 hold_mips_optimize
= mips_optimize
;
5755 /* Itbl support may require additional care here. */
5756 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5757 coproc
? treg
: treg
+ 1,
5758 (int) BFD_RELOC_LO16
, AT
);
5759 mips_optimize
= hold_mips_optimize
;
5761 else if (mips_pic
== EMBEDDED_PIC
)
5763 /* If there is no base register, we use
5764 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5765 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5766 If we have a base register, we use
5768 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5769 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5779 ((bfd_arch_bits_per_address (stdoutput
) == 32
5780 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5781 ? "addu" : "daddu"),
5782 "d,v,t", AT
, breg
, GP
);
5787 /* Itbl support may require additional care here. */
5788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5789 coproc
? treg
+ 1 : treg
,
5790 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5791 offset_expr
.X_add_number
+= 4;
5792 /* Itbl support may require additional care here. */
5793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5794 coproc
? treg
: treg
+ 1,
5795 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5811 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5812 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5814 (int) BFD_RELOC_LO16
, breg
);
5815 offset_expr
.X_add_number
+= 4;
5816 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5817 (int) BFD_RELOC_LO16
, breg
);
5820 /* New code added to support COPZ instructions.
5821 This code builds table entries out of the macros in mip_opcodes.
5822 R4000 uses interlocks to handle coproc delays.
5823 Other chips (like the R3000) require nops to be inserted for delays.
5825 FIXME: Currently, we require that the user handle delays.
5826 In order to fill delay slots for non-interlocked chips,
5827 we must have a way to specify delays based on the coprocessor.
5828 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5829 What are the side-effects of the cop instruction?
5830 What cache support might we have and what are its effects?
5831 Both coprocessor & memory require delays. how long???
5832 What registers are read/set/modified?
5834 If an itbl is provided to interpret cop instructions,
5835 this knowledge can be encoded in the itbl spec. */
5849 /* For now we just do C (same as Cz). The parameter will be
5850 stored in insn_opcode by mips_ip. */
5851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5855 #ifdef LOSING_COMPILER
5857 /* Try and see if this is a new itbl instruction.
5858 This code builds table entries out of the macros in mip_opcodes.
5859 FIXME: For now we just assemble the expression and pass it's
5860 value along as a 32-bit immediate.
5861 We may want to have the assembler assemble this value,
5862 so that we gain the assembler's knowledge of delay slots,
5864 Would it be more efficient to use mask (id) here? */
5865 if (itbl_have_entries
5866 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5868 s
= ip
->insn_mo
->name
;
5870 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5871 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5878 as_warn (_("Macro used $at after \".set noat\""));
5883 struct mips_cl_insn
*ip
;
5885 register int treg
, sreg
, dreg
, breg
;
5901 bfd_reloc_code_real_type r
;
5904 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5905 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5906 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5907 mask
= ip
->insn_mo
->mask
;
5909 expr1
.X_op
= O_constant
;
5910 expr1
.X_op_symbol
= NULL
;
5911 expr1
.X_add_symbol
= NULL
;
5912 expr1
.X_add_number
= 1;
5916 #endif /* LOSING_COMPILER */
5921 macro_build ((char *) NULL
, &icnt
, NULL
,
5922 dbl
? "dmultu" : "multu",
5924 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5930 /* The MIPS assembler some times generates shifts and adds. I'm
5931 not trying to be that fancy. GCC should do this for us
5933 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5934 macro_build ((char *) NULL
, &icnt
, NULL
,
5935 dbl
? "dmult" : "mult",
5937 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5950 mips_emit_delays (true);
5951 ++mips_opts
.noreorder
;
5952 mips_any_noreorder
= 1;
5954 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5955 macro_build ((char *) NULL
, &icnt
, NULL
,
5956 dbl
? "dmult" : "mult",
5957 "s,t", sreg
, imm
? AT
: treg
);
5958 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5959 macro_build ((char *) NULL
, &icnt
, NULL
,
5960 dbl
? "dsra32" : "sra",
5961 "d,w,<", dreg
, dreg
, 31);
5962 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5964 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5967 expr1
.X_add_number
= 8;
5968 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5970 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5972 --mips_opts
.noreorder
;
5973 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5986 mips_emit_delays (true);
5987 ++mips_opts
.noreorder
;
5988 mips_any_noreorder
= 1;
5990 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5991 macro_build ((char *) NULL
, &icnt
, NULL
,
5992 dbl
? "dmultu" : "multu",
5993 "s,t", sreg
, imm
? AT
: treg
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5997 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6000 expr1
.X_add_number
= 8;
6001 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6002 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6003 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6005 --mips_opts
.noreorder
;
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6010 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6011 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6013 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6017 if (imm_expr
.X_op
!= O_constant
)
6018 as_bad (_("rotate count too large"));
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6020 (int) (imm_expr
.X_add_number
& 0x1f));
6021 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6022 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6031 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6035 if (imm_expr
.X_op
!= O_constant
)
6036 as_bad (_("rotate count too large"));
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6038 (int) (imm_expr
.X_add_number
& 0x1f));
6039 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6040 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6041 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6045 if (mips_cpu
== 4650)
6047 as_bad (_("opcode not supported on this processor"));
6050 assert (mips_opts
.isa
== 1);
6051 /* Even on a big endian machine $fn comes before $fn+1. We have
6052 to adjust when storing to memory. */
6053 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6054 target_big_endian
? treg
+ 1 : treg
,
6055 (int) BFD_RELOC_LO16
, breg
);
6056 offset_expr
.X_add_number
+= 4;
6057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6058 target_big_endian
? treg
: treg
+ 1,
6059 (int) BFD_RELOC_LO16
, breg
);
6064 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6065 treg
, (int) BFD_RELOC_LO16
);
6067 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6068 sreg
, (int) BFD_RELOC_LO16
);
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6073 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6074 dreg
, (int) BFD_RELOC_LO16
);
6079 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6081 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6082 sreg
, (int) BFD_RELOC_LO16
);
6087 as_warn (_("Instruction %s: result is always false"),
6089 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6092 if (imm_expr
.X_op
== O_constant
6093 && imm_expr
.X_add_number
>= 0
6094 && imm_expr
.X_add_number
< 0x10000)
6096 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6097 sreg
, (int) BFD_RELOC_LO16
);
6100 else if (imm_expr
.X_op
== O_constant
6101 && imm_expr
.X_add_number
> -0x8000
6102 && imm_expr
.X_add_number
< 0)
6104 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6105 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6106 ((bfd_arch_bits_per_address (stdoutput
) == 32
6107 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6108 ? "addiu" : "daddiu"),
6109 "t,r,j", dreg
, sreg
,
6110 (int) BFD_RELOC_LO16
);
6115 load_register (&icnt
, AT
, &imm_expr
, 0);
6116 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6120 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6121 (int) BFD_RELOC_LO16
);
6126 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6132 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6133 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6134 (int) BFD_RELOC_LO16
);
6137 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6139 if (imm_expr
.X_op
== O_constant
6140 && imm_expr
.X_add_number
>= -0x8000
6141 && imm_expr
.X_add_number
< 0x8000)
6143 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6144 mask
== M_SGE_I
? "slti" : "sltiu",
6145 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6150 load_register (&icnt
, AT
, &imm_expr
, 0);
6151 macro_build ((char *) NULL
, &icnt
, NULL
,
6152 mask
== M_SGE_I
? "slt" : "sltu",
6153 "d,v,t", dreg
, sreg
, AT
);
6156 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6157 (int) BFD_RELOC_LO16
);
6162 case M_SGT
: /* sreg > treg <==> treg < sreg */
6168 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6171 case M_SGT_I
: /* sreg > I <==> I < sreg */
6177 load_register (&icnt
, AT
, &imm_expr
, 0);
6178 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6181 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6187 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6188 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6189 (int) BFD_RELOC_LO16
);
6192 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6198 load_register (&icnt
, AT
, &imm_expr
, 0);
6199 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6200 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6201 (int) BFD_RELOC_LO16
);
6205 if (imm_expr
.X_op
== O_constant
6206 && imm_expr
.X_add_number
>= -0x8000
6207 && imm_expr
.X_add_number
< 0x8000)
6209 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6210 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6213 load_register (&icnt
, AT
, &imm_expr
, 0);
6214 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6218 if (imm_expr
.X_op
== O_constant
6219 && imm_expr
.X_add_number
>= -0x8000
6220 && imm_expr
.X_add_number
< 0x8000)
6222 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6223 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6226 load_register (&icnt
, AT
, &imm_expr
, 0);
6227 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6233 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6236 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6240 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6242 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6248 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6250 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6256 as_warn (_("Instruction %s: result is always true"),
6258 macro_build ((char *) NULL
, &icnt
, &expr1
,
6259 ((bfd_arch_bits_per_address (stdoutput
) == 32
6260 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6261 ? "addiu" : "daddiu"),
6262 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6265 if (imm_expr
.X_op
== O_constant
6266 && imm_expr
.X_add_number
>= 0
6267 && imm_expr
.X_add_number
< 0x10000)
6269 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6270 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6273 else if (imm_expr
.X_op
== O_constant
6274 && imm_expr
.X_add_number
> -0x8000
6275 && imm_expr
.X_add_number
< 0)
6277 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6278 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6279 ((bfd_arch_bits_per_address (stdoutput
) == 32
6280 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6281 ? "addiu" : "daddiu"),
6282 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6287 load_register (&icnt
, AT
, &imm_expr
, 0);
6288 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6292 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6300 if (imm_expr
.X_op
== O_constant
6301 && imm_expr
.X_add_number
> -0x8000
6302 && imm_expr
.X_add_number
<= 0x8000)
6304 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6305 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6306 dbl
? "daddi" : "addi",
6307 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6310 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6311 macro_build ((char *) NULL
, &icnt
, NULL
,
6312 dbl
? "dsub" : "sub",
6313 "d,v,t", dreg
, sreg
, AT
);
6319 if (imm_expr
.X_op
== O_constant
6320 && imm_expr
.X_add_number
> -0x8000
6321 && imm_expr
.X_add_number
<= 0x8000)
6323 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6324 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6325 dbl
? "daddiu" : "addiu",
6326 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6329 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6330 macro_build ((char *) NULL
, &icnt
, NULL
,
6331 dbl
? "dsubu" : "subu",
6332 "d,v,t", dreg
, sreg
, AT
);
6353 load_register (&icnt
, AT
, &imm_expr
, 0);
6354 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6359 assert (mips_opts
.isa
== 1);
6360 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6361 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6364 * Is the double cfc1 instruction a bug in the mips assembler;
6365 * or is there a reason for it?
6367 mips_emit_delays (true);
6368 ++mips_opts
.noreorder
;
6369 mips_any_noreorder
= 1;
6370 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6372 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6373 expr1
.X_add_number
= 3;
6374 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6375 (int) BFD_RELOC_LO16
);
6376 expr1
.X_add_number
= 2;
6377 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6378 (int) BFD_RELOC_LO16
);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6380 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6381 macro_build ((char *) NULL
, &icnt
, NULL
,
6382 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6383 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6384 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6385 --mips_opts
.noreorder
;
6394 if (offset_expr
.X_add_number
>= 0x7fff)
6395 as_bad (_("operand overflow"));
6396 /* avoid load delay */
6397 if (! target_big_endian
)
6398 offset_expr
.X_add_number
+= 1;
6399 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6400 (int) BFD_RELOC_LO16
, breg
);
6401 if (! target_big_endian
)
6402 offset_expr
.X_add_number
-= 1;
6404 offset_expr
.X_add_number
+= 1;
6405 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6406 (int) BFD_RELOC_LO16
, breg
);
6407 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6408 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6421 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6422 as_bad (_("operand overflow"));
6423 if (! target_big_endian
)
6424 offset_expr
.X_add_number
+= off
;
6425 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6426 (int) BFD_RELOC_LO16
, breg
);
6427 if (! target_big_endian
)
6428 offset_expr
.X_add_number
-= off
;
6430 offset_expr
.X_add_number
+= off
;
6431 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6432 (int) BFD_RELOC_LO16
, breg
);
6445 load_address (&icnt
, AT
, &offset_expr
);
6447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6448 ((bfd_arch_bits_per_address (stdoutput
) == 32
6449 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6450 ? "addu" : "daddu"),
6451 "d,v,t", AT
, AT
, breg
);
6452 if (! target_big_endian
)
6453 expr1
.X_add_number
= off
;
6455 expr1
.X_add_number
= 0;
6456 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6457 (int) BFD_RELOC_LO16
, AT
);
6458 if (! target_big_endian
)
6459 expr1
.X_add_number
= 0;
6461 expr1
.X_add_number
= off
;
6462 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6463 (int) BFD_RELOC_LO16
, AT
);
6468 load_address (&icnt
, AT
, &offset_expr
);
6470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6471 ((bfd_arch_bits_per_address (stdoutput
) == 32
6472 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6473 ? "addu" : "daddu"),
6474 "d,v,t", AT
, AT
, breg
);
6475 if (target_big_endian
)
6476 expr1
.X_add_number
= 0;
6477 macro_build ((char *) NULL
, &icnt
, &expr1
,
6478 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6479 (int) BFD_RELOC_LO16
, AT
);
6480 if (target_big_endian
)
6481 expr1
.X_add_number
= 1;
6483 expr1
.X_add_number
= 0;
6484 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6485 (int) BFD_RELOC_LO16
, AT
);
6486 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6488 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6493 if (offset_expr
.X_add_number
>= 0x7fff)
6494 as_bad (_("operand overflow"));
6495 if (target_big_endian
)
6496 offset_expr
.X_add_number
+= 1;
6497 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6498 (int) BFD_RELOC_LO16
, breg
);
6499 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6500 if (target_big_endian
)
6501 offset_expr
.X_add_number
-= 1;
6503 offset_expr
.X_add_number
+= 1;
6504 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6505 (int) BFD_RELOC_LO16
, breg
);
6518 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6519 as_bad (_("operand overflow"));
6520 if (! target_big_endian
)
6521 offset_expr
.X_add_number
+= off
;
6522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6523 (int) BFD_RELOC_LO16
, breg
);
6524 if (! target_big_endian
)
6525 offset_expr
.X_add_number
-= off
;
6527 offset_expr
.X_add_number
+= off
;
6528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6529 (int) BFD_RELOC_LO16
, breg
);
6542 load_address (&icnt
, AT
, &offset_expr
);
6544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6545 ((bfd_arch_bits_per_address (stdoutput
) == 32
6546 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6547 ? "addu" : "daddu"),
6548 "d,v,t", AT
, AT
, breg
);
6549 if (! target_big_endian
)
6550 expr1
.X_add_number
= off
;
6552 expr1
.X_add_number
= 0;
6553 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, AT
);
6555 if (! target_big_endian
)
6556 expr1
.X_add_number
= 0;
6558 expr1
.X_add_number
= off
;
6559 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6560 (int) BFD_RELOC_LO16
, AT
);
6564 load_address (&icnt
, AT
, &offset_expr
);
6566 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6567 ((bfd_arch_bits_per_address (stdoutput
) == 32
6568 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6569 ? "addu" : "daddu"),
6570 "d,v,t", AT
, AT
, breg
);
6571 if (! target_big_endian
)
6572 expr1
.X_add_number
= 0;
6573 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6574 (int) BFD_RELOC_LO16
, AT
);
6575 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6577 if (! target_big_endian
)
6578 expr1
.X_add_number
= 1;
6580 expr1
.X_add_number
= 0;
6581 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6582 (int) BFD_RELOC_LO16
, AT
);
6583 if (! target_big_endian
)
6584 expr1
.X_add_number
= 0;
6586 expr1
.X_add_number
= 1;
6587 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6588 (int) BFD_RELOC_LO16
, AT
);
6589 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6591 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6596 /* FIXME: Check if this is one of the itbl macros, since they
6597 are added dynamically. */
6598 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6602 as_warn (_("Macro used $at after \".set noat\""));
6605 /* Implement macros in mips16 mode. */
6609 struct mips_cl_insn
*ip
;
6612 int xreg
, yreg
, zreg
, tmp
;
6616 const char *s
, *s2
, *s3
;
6618 mask
= ip
->insn_mo
->mask
;
6620 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6621 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6622 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6626 expr1
.X_op
= O_constant
;
6627 expr1
.X_op_symbol
= NULL
;
6628 expr1
.X_add_symbol
= NULL
;
6629 expr1
.X_add_number
= 1;
6648 mips_emit_delays (true);
6649 ++mips_opts
.noreorder
;
6650 mips_any_noreorder
= 1;
6651 macro_build ((char *) NULL
, &icnt
, NULL
,
6652 dbl
? "ddiv" : "div",
6653 "0,x,y", xreg
, yreg
);
6654 expr1
.X_add_number
= 2;
6655 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6656 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6658 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6659 since that causes an overflow. We should do that as well,
6660 but I don't see how to do the comparisons without a temporary
6662 --mips_opts
.noreorder
;
6663 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6682 mips_emit_delays (true);
6683 ++mips_opts
.noreorder
;
6684 mips_any_noreorder
= 1;
6685 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6686 expr1
.X_add_number
= 2;
6687 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6688 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6689 --mips_opts
.noreorder
;
6690 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6696 macro_build ((char *) NULL
, &icnt
, NULL
,
6697 dbl
? "dmultu" : "multu",
6699 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6707 if (imm_expr
.X_op
!= O_constant
)
6708 as_bad (_("Unsupported large constant"));
6709 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6710 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6711 dbl
? "daddiu" : "addiu",
6712 "y,x,4", yreg
, xreg
);
6716 if (imm_expr
.X_op
!= O_constant
)
6717 as_bad (_("Unsupported large constant"));
6718 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6719 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6724 if (imm_expr
.X_op
!= O_constant
)
6725 as_bad (_("Unsupported large constant"));
6726 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6727 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6750 goto do_reverse_branch
;
6754 goto do_reverse_branch
;
6766 goto do_reverse_branch
;
6777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6779 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6806 goto do_addone_branch_i
;
6811 goto do_addone_branch_i
;
6826 goto do_addone_branch_i
;
6833 if (imm_expr
.X_op
!= O_constant
)
6834 as_bad (_("Unsupported large constant"));
6835 ++imm_expr
.X_add_number
;
6838 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6843 expr1
.X_add_number
= 0;
6844 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6847 "move", "y,X", xreg
, yreg
);
6848 expr1
.X_add_number
= 2;
6849 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6851 "neg", "x,w", xreg
, xreg
);
6855 /* For consistency checking, verify that all bits are specified either
6856 by the match/mask part of the instruction definition, or by the
6859 validate_mips_insn (opc
)
6860 const struct mips_opcode
*opc
;
6862 const char *p
= opc
->args
;
6864 unsigned long used_bits
= opc
->mask
;
6866 if ((used_bits
& opc
->match
) != opc
->match
)
6868 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6869 opc
->name
, opc
->args
);
6872 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6879 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6880 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6882 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6883 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6884 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6885 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6887 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6890 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6891 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6892 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6893 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6894 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6895 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6896 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6897 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6898 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6899 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6900 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6902 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6903 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6904 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6905 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6907 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6908 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6909 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6910 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6911 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6912 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6913 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6914 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6915 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6918 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6920 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6921 c
, opc
->name
, opc
->args
);
6925 if (used_bits
!= 0xffffffff)
6927 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6928 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6934 /* This routine assembles an instruction into its binary format. As a
6935 side effect, it sets one of the global variables imm_reloc or
6936 offset_reloc to the type of relocation to do if one of the operands
6937 is an address expression. */
6942 struct mips_cl_insn
*ip
;
6947 struct mips_opcode
*insn
;
6950 unsigned int lastregno
= 0;
6953 int full_opcode_match
= 1;
6957 /* If the instruction contains a '.', we first try to match an instruction
6958 including the '.'. Then we try again without the '.'. */
6960 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6963 /* If we stopped on whitespace, then replace the whitespace with null for
6964 the call to hash_find. Save the character we replaced just in case we
6965 have to re-parse the instruction. */
6966 if (isspace ((unsigned char) *s
))
6972 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6974 /* If we didn't find the instruction in the opcode table, try again, but
6975 this time with just the instruction up to, but not including the
6979 /* Restore the character we overwrite above (if any). */
6983 /* Scan up to the first '.' or whitespace. */
6984 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
6987 /* If we did not find a '.', then we can quit now. */
6990 insn_error
= "unrecognized opcode";
6994 /* Lookup the instruction in the hash table. */
6996 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6998 insn_error
= "unrecognized opcode";
7002 full_opcode_match
= 0;
7010 assert (strcmp (insn
->name
, str
) == 0);
7012 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
))
7017 if (insn
->pinfo
!= INSN_MACRO
)
7019 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7025 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7026 && strcmp (insn
->name
, insn
[1].name
) == 0)
7033 static char buf
[100];
7035 _("opcode not supported on this processor: %d (MIPS%d)"),
7036 mips_cpu
, mips_opts
.isa
);
7044 ip
->insn_opcode
= insn
->match
;
7045 for (args
= insn
->args
;; ++args
)
7051 case '\0': /* end of args */
7064 ip
->insn_opcode
|= lastregno
<< 21;
7069 ip
->insn_opcode
|= lastregno
<< 16;
7073 ip
->insn_opcode
|= lastregno
<< 11;
7079 /* Handle optional base register.
7080 Either the base register is omitted or
7081 we must have a left paren. */
7082 /* This is dependent on the next operand specifier
7083 is a base register specification. */
7084 assert (args
[1] == 'b' || args
[1] == '5'
7085 || args
[1] == '-' || args
[1] == '4');
7089 case ')': /* these must match exactly */
7094 case '<': /* must be at least one digit */
7096 * According to the manual, if the shift amount is greater
7097 * than 31 or less than 0 the the shift amount should be
7098 * mod 32. In reality the mips assembler issues an error.
7099 * We issue a warning and mask out all but the low 5 bits.
7101 my_getExpression (&imm_expr
, s
);
7102 check_absolute_expr (ip
, &imm_expr
);
7103 if ((unsigned long) imm_expr
.X_add_number
> 31)
7105 as_warn (_("Improper shift amount (%ld)"),
7106 (long) imm_expr
.X_add_number
);
7107 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7109 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7110 imm_expr
.X_op
= O_absent
;
7114 case '>': /* shift amount minus 32 */
7115 my_getExpression (&imm_expr
, s
);
7116 check_absolute_expr (ip
, &imm_expr
);
7117 if ((unsigned long) imm_expr
.X_add_number
< 32
7118 || (unsigned long) imm_expr
.X_add_number
> 63)
7120 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7121 imm_expr
.X_op
= O_absent
;
7126 case 'k': /* cache code */
7127 case 'h': /* prefx code */
7128 my_getExpression (&imm_expr
, s
);
7129 check_absolute_expr (ip
, &imm_expr
);
7130 if ((unsigned long) imm_expr
.X_add_number
> 31)
7132 as_warn (_("Invalid value for `%s' (%lu)"),
7134 (unsigned long) imm_expr
.X_add_number
);
7135 imm_expr
.X_add_number
&= 0x1f;
7138 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7140 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7141 imm_expr
.X_op
= O_absent
;
7145 case 'c': /* break code */
7146 my_getExpression (&imm_expr
, s
);
7147 check_absolute_expr (ip
, &imm_expr
);
7148 if ((unsigned) imm_expr
.X_add_number
> 1023)
7150 as_warn (_("Illegal break code (%ld)"),
7151 (long) imm_expr
.X_add_number
);
7152 imm_expr
.X_add_number
&= 0x3ff;
7154 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7155 imm_expr
.X_op
= O_absent
;
7159 case 'q': /* lower break code */
7160 my_getExpression (&imm_expr
, s
);
7161 check_absolute_expr (ip
, &imm_expr
);
7162 if ((unsigned) imm_expr
.X_add_number
> 1023)
7164 as_warn (_("Illegal lower break code (%ld)"),
7165 (long) imm_expr
.X_add_number
);
7166 imm_expr
.X_add_number
&= 0x3ff;
7168 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7169 imm_expr
.X_op
= O_absent
;
7173 case 'B': /* syscall code */
7174 my_getExpression (&imm_expr
, s
);
7175 check_absolute_expr (ip
, &imm_expr
);
7176 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7177 as_warn (_("Illegal syscall code (%ld)"),
7178 (long) imm_expr
.X_add_number
);
7179 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7180 imm_expr
.X_op
= O_absent
;
7184 case 'C': /* Coprocessor code */
7185 my_getExpression (&imm_expr
, s
);
7186 check_absolute_expr (ip
, &imm_expr
);
7187 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7189 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7190 (long) imm_expr
.X_add_number
);
7191 imm_expr
.X_add_number
&= ((1<<25) - 1);
7193 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7194 imm_expr
.X_op
= O_absent
;
7198 case 'P': /* Performance register */
7199 my_getExpression (&imm_expr
, s
);
7200 check_absolute_expr (ip
, &imm_expr
);
7201 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7203 as_warn (_("Invalidate performance regster (%ld)"),
7204 (long) imm_expr
.X_add_number
);
7205 imm_expr
.X_add_number
&= 1;
7207 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7208 imm_expr
.X_op
= O_absent
;
7212 case 'b': /* base register */
7213 case 'd': /* destination register */
7214 case 's': /* source register */
7215 case 't': /* target register */
7216 case 'r': /* both target and source */
7217 case 'v': /* both dest and source */
7218 case 'w': /* both dest and target */
7219 case 'E': /* coprocessor target register */
7220 case 'G': /* coprocessor destination register */
7221 case 'x': /* ignore register name */
7222 case 'z': /* must be zero register */
7227 if (isdigit ((unsigned char) s
[1]))
7237 while (isdigit ((unsigned char) *s
));
7239 as_bad (_("Invalid register number (%d)"), regno
);
7241 else if (*args
== 'E' || *args
== 'G')
7245 if (s
[1] == 'f' && s
[2] == 'p')
7250 else if (s
[1] == 's' && s
[2] == 'p')
7255 else if (s
[1] == 'g' && s
[2] == 'p')
7260 else if (s
[1] == 'a' && s
[2] == 't')
7265 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7270 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7275 else if (itbl_have_entries
)
7280 p
= s
+ 1; /* advance past '$' */
7281 n
= itbl_get_field (&p
); /* n is name */
7283 /* See if this is a register defined in an
7285 if (itbl_get_reg_val (n
, &r
))
7287 /* Get_field advances to the start of
7288 the next field, so we need to back
7289 rack to the end of the last field. */
7293 s
= strchr (s
, '\0');
7306 as_warn (_("Used $at without \".set noat\""));
7312 if (c
== 'r' || c
== 'v' || c
== 'w')
7319 /* 'z' only matches $0. */
7320 if (c
== 'z' && regno
!= 0)
7323 /* Now that we have assembled one operand, we use the args string
7324 * to figure out where it goes in the instruction. */
7331 ip
->insn_opcode
|= regno
<< 21;
7335 ip
->insn_opcode
|= regno
<< 11;
7340 ip
->insn_opcode
|= regno
<< 16;
7343 /* This case exists because on the r3000 trunc
7344 expands into a macro which requires a gp
7345 register. On the r6000 or r4000 it is
7346 assembled into a single instruction which
7347 ignores the register. Thus the insn version
7348 is MIPS_ISA2 and uses 'x', and the macro
7349 version is MIPS_ISA1 and uses 't'. */
7352 /* This case is for the div instruction, which
7353 acts differently if the destination argument
7354 is $0. This only matches $0, and is checked
7355 outside the switch. */
7358 /* Itbl operand; not yet implemented. FIXME ?? */
7360 /* What about all other operands like 'i', which
7361 can be specified in the opcode table? */
7371 ip
->insn_opcode
|= lastregno
<< 21;
7374 ip
->insn_opcode
|= lastregno
<< 16;
7379 case 'D': /* floating point destination register */
7380 case 'S': /* floating point source register */
7381 case 'T': /* floating point target register */
7382 case 'R': /* floating point source register */
7386 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7396 while (isdigit ((unsigned char) *s
));
7399 as_bad (_("Invalid float register number (%d)"), regno
);
7401 if ((regno
& 1) != 0
7402 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7403 && ! (strcmp (str
, "mtc1") == 0
7404 || strcmp (str
, "mfc1") == 0
7405 || strcmp (str
, "lwc1") == 0
7406 || strcmp (str
, "swc1") == 0
7407 || strcmp (str
, "l.s") == 0
7408 || strcmp (str
, "s.s") == 0))
7409 as_warn (_("Float register should be even, was %d"),
7417 if (c
== 'V' || c
== 'W')
7427 ip
->insn_opcode
|= regno
<< 6;
7431 ip
->insn_opcode
|= regno
<< 11;
7435 ip
->insn_opcode
|= regno
<< 16;
7438 ip
->insn_opcode
|= regno
<< 21;
7449 ip
->insn_opcode
|= lastregno
<< 11;
7452 ip
->insn_opcode
|= lastregno
<< 16;
7458 my_getExpression (&imm_expr
, s
);
7459 if (imm_expr
.X_op
!= O_big
7460 && imm_expr
.X_op
!= O_constant
)
7461 insn_error
= _("absolute expression required");
7466 my_getExpression (&offset_expr
, s
);
7467 imm_reloc
= BFD_RELOC_32
;
7479 unsigned char temp
[8];
7481 unsigned int length
;
7486 /* These only appear as the last operand in an
7487 instruction, and every instruction that accepts
7488 them in any variant accepts them in all variants.
7489 This means we don't have to worry about backing out
7490 any changes if the instruction does not match.
7492 The difference between them is the size of the
7493 floating point constant and where it goes. For 'F'
7494 and 'L' the constant is 64 bits; for 'f' and 'l' it
7495 is 32 bits. Where the constant is placed is based
7496 on how the MIPS assembler does things:
7499 f -- immediate value
7502 The .lit4 and .lit8 sections are only used if
7503 permitted by the -G argument.
7505 When generating embedded PIC code, we use the
7506 .lit8 section but not the .lit4 section (we can do
7507 .lit4 inline easily; we need to put .lit8
7508 somewhere in the data segment, and using .lit8
7509 permits the linker to eventually combine identical
7512 f64
= *args
== 'F' || *args
== 'L';
7514 save_in
= input_line_pointer
;
7515 input_line_pointer
= s
;
7516 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7518 s
= input_line_pointer
;
7519 input_line_pointer
= save_in
;
7520 if (err
!= NULL
&& *err
!= '\0')
7522 as_bad (_("Bad floating point constant: %s"), err
);
7523 memset (temp
, '\0', sizeof temp
);
7524 length
= f64
? 8 : 4;
7527 assert (length
== (f64
? 8 : 4));
7531 && (! USE_GLOBAL_POINTER_OPT
7532 || mips_pic
== EMBEDDED_PIC
7533 || g_switch_value
< 4
7534 || (temp
[0] == 0 && temp
[1] == 0)
7535 || (temp
[2] == 0 && temp
[3] == 0))))
7537 imm_expr
.X_op
= O_constant
;
7538 if (! target_big_endian
)
7539 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7541 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7544 && ((temp
[0] == 0 && temp
[1] == 0)
7545 || (temp
[2] == 0 && temp
[3] == 0))
7546 && ((temp
[4] == 0 && temp
[5] == 0)
7547 || (temp
[6] == 0 && temp
[7] == 0)))
7549 /* The value is simple enough to load with a
7550 couple of instructions. In mips1 mode, set
7551 imm_expr to the high order 32 bits and
7552 offset_expr to the low order 32 bits.
7553 Otherwise, set imm_expr to the entire 64 bit
7555 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7557 imm_expr
.X_op
= O_constant
;
7558 offset_expr
.X_op
= O_constant
;
7559 if (! target_big_endian
)
7561 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7562 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7566 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7567 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7569 if (offset_expr
.X_add_number
== 0)
7570 offset_expr
.X_op
= O_absent
;
7572 else if (sizeof (imm_expr
.X_add_number
) > 4)
7574 imm_expr
.X_op
= O_constant
;
7575 if (! target_big_endian
)
7576 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7578 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7582 imm_expr
.X_op
= O_big
;
7583 imm_expr
.X_add_number
= 4;
7584 if (! target_big_endian
)
7586 generic_bignum
[0] = bfd_getl16 (temp
);
7587 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7588 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7589 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7593 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7594 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7595 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7596 generic_bignum
[3] = bfd_getb16 (temp
);
7602 const char *newname
;
7605 /* Switch to the right section. */
7607 subseg
= now_subseg
;
7610 default: /* unused default case avoids warnings. */
7612 newname
= RDATA_SECTION_NAME
;
7613 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7617 newname
= RDATA_SECTION_NAME
;
7620 assert (!USE_GLOBAL_POINTER_OPT
7621 || g_switch_value
>= 4);
7625 new_seg
= subseg_new (newname
, (subsegT
) 0);
7626 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7627 bfd_set_section_flags (stdoutput
, new_seg
,
7632 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7633 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7634 && strcmp (TARGET_OS
, "elf") != 0)
7635 record_alignment (new_seg
, 4);
7637 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7639 as_bad (_("Can't use floating point insn in this section"));
7641 /* Set the argument to the current address in the
7643 offset_expr
.X_op
= O_symbol
;
7644 offset_expr
.X_add_symbol
=
7645 symbol_new ("L0\001", now_seg
,
7646 (valueT
) frag_now_fix (), frag_now
);
7647 offset_expr
.X_add_number
= 0;
7649 /* Put the floating point number into the section. */
7650 p
= frag_more ((int) length
);
7651 memcpy (p
, temp
, length
);
7653 /* Switch back to the original section. */
7654 subseg_set (seg
, subseg
);
7659 case 'i': /* 16 bit unsigned immediate */
7660 case 'j': /* 16 bit signed immediate */
7661 imm_reloc
= BFD_RELOC_LO16
;
7662 c
= my_getSmallExpression (&imm_expr
, s
);
7667 if (imm_expr
.X_op
== O_constant
)
7668 imm_expr
.X_add_number
=
7669 (imm_expr
.X_add_number
>> 16) & 0xffff;
7672 imm_reloc
= BFD_RELOC_HI16_S
;
7673 imm_unmatched_hi
= true;
7676 imm_reloc
= BFD_RELOC_HI16
;
7678 else if (imm_expr
.X_op
== O_constant
)
7679 imm_expr
.X_add_number
&= 0xffff;
7683 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7684 || ((imm_expr
.X_add_number
< 0
7685 || imm_expr
.X_add_number
>= 0x10000)
7686 && imm_expr
.X_op
== O_constant
))
7688 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7689 !strcmp (insn
->name
, insn
[1].name
))
7691 if (imm_expr
.X_op
!= O_constant
7692 && imm_expr
.X_op
!= O_big
)
7693 insn_error
= _("absolute expression required");
7695 as_bad (_("16 bit expression not in range 0..65535"));
7703 /* The upper bound should be 0x8000, but
7704 unfortunately the MIPS assembler accepts numbers
7705 from 0x8000 to 0xffff and sign extends them, and
7706 we want to be compatible. We only permit this
7707 extended range for an instruction which does not
7708 provide any further alternates, since those
7709 alternates may handle other cases. People should
7710 use the numbers they mean, rather than relying on
7711 a mysterious sign extension. */
7712 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7713 strcmp (insn
->name
, insn
[1].name
) == 0);
7718 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7719 || ((imm_expr
.X_add_number
< -0x8000
7720 || imm_expr
.X_add_number
>= max
)
7721 && imm_expr
.X_op
== O_constant
)
7723 && imm_expr
.X_add_number
< 0
7724 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7725 && imm_expr
.X_unsigned
7726 && sizeof (imm_expr
.X_add_number
) <= 4))
7730 if (imm_expr
.X_op
!= O_constant
7731 && imm_expr
.X_op
!= O_big
)
7732 insn_error
= _("absolute expression required");
7734 as_bad (_("16 bit expression not in range -32768..32767"));
7740 case 'o': /* 16 bit offset */
7741 c
= my_getSmallExpression (&offset_expr
, s
);
7743 /* If this value won't fit into a 16 bit offset, then go
7744 find a macro that will generate the 32 bit offset
7745 code pattern. As a special hack, we accept the
7746 difference of two local symbols as a constant. This
7747 is required to suppose embedded PIC switches, which
7748 use an instruction which looks like
7749 lw $4,$L12-$LS12($4)
7750 The problem with handling this in a more general
7751 fashion is that the macro function doesn't expect to
7752 see anything which can be handled in a single
7753 constant instruction. */
7755 && (offset_expr
.X_op
!= O_constant
7756 || offset_expr
.X_add_number
>= 0x8000
7757 || offset_expr
.X_add_number
< -0x8000)
7758 && (mips_pic
!= EMBEDDED_PIC
7759 || offset_expr
.X_op
!= O_subtract
7760 || now_seg
!= text_section
7761 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7765 if (c
== 'h' || c
== 'H')
7767 if (offset_expr
.X_op
!= O_constant
)
7769 offset_expr
.X_add_number
=
7770 (offset_expr
.X_add_number
>> 16) & 0xffff;
7772 offset_reloc
= BFD_RELOC_LO16
;
7776 case 'p': /* pc relative offset */
7777 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7778 my_getExpression (&offset_expr
, s
);
7782 case 'u': /* upper 16 bits */
7783 c
= my_getSmallExpression (&imm_expr
, s
);
7784 imm_reloc
= BFD_RELOC_LO16
;
7789 if (imm_expr
.X_op
== O_constant
)
7790 imm_expr
.X_add_number
=
7791 (imm_expr
.X_add_number
>> 16) & 0xffff;
7794 imm_reloc
= BFD_RELOC_HI16_S
;
7795 imm_unmatched_hi
= true;
7798 imm_reloc
= BFD_RELOC_HI16
;
7800 else if (imm_expr
.X_op
== O_constant
)
7801 imm_expr
.X_add_number
&= 0xffff;
7803 if (imm_expr
.X_op
== O_constant
7804 && (imm_expr
.X_add_number
< 0
7805 || imm_expr
.X_add_number
>= 0x10000))
7806 as_bad (_("lui expression not in range 0..65535"));
7810 case 'a': /* 26 bit address */
7811 my_getExpression (&offset_expr
, s
);
7813 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7816 case 'N': /* 3 bit branch condition code */
7817 case 'M': /* 3 bit compare condition code */
7818 if (strncmp (s
, "$fcc", 4) != 0)
7828 while (isdigit ((unsigned char) *s
));
7830 as_bad (_("invalid condition code register $fcc%d"), regno
);
7832 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7834 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7838 as_bad (_("bad char = '%c'\n"), *args
);
7843 /* Args don't match. */
7844 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7845 !strcmp (insn
->name
, insn
[1].name
))
7851 insn_error
= _("illegal operands");
7856 /* This routine assembles an instruction into its binary format when
7857 assembling for the mips16. As a side effect, it sets one of the
7858 global variables imm_reloc or offset_reloc to the type of
7859 relocation to do if one of the operands is an address expression.
7860 It also sets mips16_small and mips16_ext if the user explicitly
7861 requested a small or extended instruction. */
7866 struct mips_cl_insn
*ip
;
7870 struct mips_opcode
*insn
;
7873 unsigned int lastregno
= 0;
7878 mips16_small
= false;
7881 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7893 if (s
[1] == 't' && s
[2] == ' ')
7896 mips16_small
= true;
7900 else if (s
[1] == 'e' && s
[2] == ' ')
7909 insn_error
= _("unknown opcode");
7913 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7914 mips16_small
= true;
7916 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7918 insn_error
= _("unrecognized opcode");
7925 assert (strcmp (insn
->name
, str
) == 0);
7928 ip
->insn_opcode
= insn
->match
;
7929 ip
->use_extend
= false;
7930 imm_expr
.X_op
= O_absent
;
7931 imm_reloc
= BFD_RELOC_UNUSED
;
7932 offset_expr
.X_op
= O_absent
;
7933 offset_reloc
= BFD_RELOC_UNUSED
;
7934 for (args
= insn
->args
; 1; ++args
)
7941 /* In this switch statement we call break if we did not find
7942 a match, continue if we did find a match, or return if we
7951 /* Stuff the immediate value in now, if we can. */
7952 if (imm_expr
.X_op
== O_constant
7953 && imm_reloc
> BFD_RELOC_UNUSED
7954 && insn
->pinfo
!= INSN_MACRO
)
7956 mips16_immed ((char *) NULL
, 0,
7957 imm_reloc
- BFD_RELOC_UNUSED
,
7958 imm_expr
.X_add_number
, true, mips16_small
,
7959 mips16_ext
, &ip
->insn_opcode
,
7960 &ip
->use_extend
, &ip
->extend
);
7961 imm_expr
.X_op
= O_absent
;
7962 imm_reloc
= BFD_RELOC_UNUSED
;
7976 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7979 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7995 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7997 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8014 if (isdigit ((unsigned char) s
[1]))
8024 while (isdigit ((unsigned char) *s
));
8027 as_bad (_("invalid register number (%d)"), regno
);
8033 if (s
[1] == 'f' && s
[2] == 'p')
8038 else if (s
[1] == 's' && s
[2] == 'p')
8043 else if (s
[1] == 'g' && s
[2] == 'p')
8048 else if (s
[1] == 'a' && s
[2] == 't')
8053 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8058 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8071 if (c
== 'v' || c
== 'w')
8073 regno
= mips16_to_32_reg_map
[lastregno
];
8087 regno
= mips32_to_16_reg_map
[regno
];
8092 regno
= ILLEGAL_REG
;
8097 regno
= ILLEGAL_REG
;
8102 regno
= ILLEGAL_REG
;
8107 if (regno
== AT
&& ! mips_opts
.noat
)
8108 as_warn (_("used $at without \".set noat\""));
8115 if (regno
== ILLEGAL_REG
)
8122 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8126 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8129 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8132 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8138 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8141 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8142 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8152 if (strncmp (s
, "$pc", 3) == 0)
8176 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8178 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8179 and generate the appropriate reloc. If the text
8180 inside %gprel is not a symbol name with an
8181 optional offset, then we generate a normal reloc
8182 and will probably fail later. */
8183 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8184 if (imm_expr
.X_op
== O_symbol
)
8187 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8189 ip
->use_extend
= true;
8196 /* Just pick up a normal expression. */
8197 my_getExpression (&imm_expr
, s
);
8200 if (imm_expr
.X_op
== O_register
)
8202 /* What we thought was an expression turned out to
8205 if (s
[0] == '(' && args
[1] == '(')
8207 /* It looks like the expression was omitted
8208 before a register indirection, which means
8209 that the expression is implicitly zero. We
8210 still set up imm_expr, so that we handle
8211 explicit extensions correctly. */
8212 imm_expr
.X_op
= O_constant
;
8213 imm_expr
.X_add_number
= 0;
8214 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8221 /* We need to relax this instruction. */
8222 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8231 /* We use offset_reloc rather than imm_reloc for the PC
8232 relative operands. This lets macros with both
8233 immediate and address operands work correctly. */
8234 my_getExpression (&offset_expr
, s
);
8236 if (offset_expr
.X_op
== O_register
)
8239 /* We need to relax this instruction. */
8240 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8244 case '6': /* break code */
8245 my_getExpression (&imm_expr
, s
);
8246 check_absolute_expr (ip
, &imm_expr
);
8247 if ((unsigned long) imm_expr
.X_add_number
> 63)
8249 as_warn (_("Invalid value for `%s' (%lu)"),
8251 (unsigned long) imm_expr
.X_add_number
);
8252 imm_expr
.X_add_number
&= 0x3f;
8254 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8255 imm_expr
.X_op
= O_absent
;
8259 case 'a': /* 26 bit address */
8260 my_getExpression (&offset_expr
, s
);
8262 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8263 ip
->insn_opcode
<<= 16;
8266 case 'l': /* register list for entry macro */
8267 case 'L': /* register list for exit macro */
8277 int freg
, reg1
, reg2
;
8279 while (*s
== ' ' || *s
== ',')
8283 as_bad (_("can't parse register list"));
8295 while (isdigit ((unsigned char) *s
))
8317 as_bad (_("invalid register list"));
8322 while (isdigit ((unsigned char) *s
))
8329 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8334 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8339 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8340 mask
|= (reg2
- 3) << 3;
8341 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8342 mask
|= (reg2
- 15) << 1;
8343 else if (reg1
== 31 && reg2
== 31)
8347 as_bad (_("invalid register list"));
8351 /* The mask is filled in in the opcode table for the
8352 benefit of the disassembler. We remove it before
8353 applying the actual mask. */
8354 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8355 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8359 case 'e': /* extend code */
8360 my_getExpression (&imm_expr
, s
);
8361 check_absolute_expr (ip
, &imm_expr
);
8362 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8364 as_warn (_("Invalid value for `%s' (%lu)"),
8366 (unsigned long) imm_expr
.X_add_number
);
8367 imm_expr
.X_add_number
&= 0x7ff;
8369 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8370 imm_expr
.X_op
= O_absent
;
8380 /* Args don't match. */
8381 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8382 strcmp (insn
->name
, insn
[1].name
) == 0)
8389 insn_error
= _("illegal operands");
8395 /* This structure holds information we know about a mips16 immediate
8398 struct mips16_immed_operand
8400 /* The type code used in the argument string in the opcode table. */
8402 /* The number of bits in the short form of the opcode. */
8404 /* The number of bits in the extended form of the opcode. */
8406 /* The amount by which the short form is shifted when it is used;
8407 for example, the sw instruction has a shift count of 2. */
8409 /* The amount by which the short form is shifted when it is stored
8410 into the instruction code. */
8412 /* Non-zero if the short form is unsigned. */
8414 /* Non-zero if the extended form is unsigned. */
8416 /* Non-zero if the value is PC relative. */
8420 /* The mips16 immediate operand types. */
8422 static const struct mips16_immed_operand mips16_immed_operands
[] =
8424 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8425 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8426 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8427 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8428 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8429 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8430 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8431 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8432 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8433 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8434 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8435 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8436 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8437 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8438 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8439 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8440 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8441 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8442 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8443 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8444 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8447 #define MIPS16_NUM_IMMED \
8448 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8450 /* Handle a mips16 instruction with an immediate value. This or's the
8451 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8452 whether an extended value is needed; if one is needed, it sets
8453 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8454 If SMALL is true, an unextended opcode was explicitly requested.
8455 If EXT is true, an extended opcode was explicitly requested. If
8456 WARN is true, warn if EXT does not match reality. */
8459 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8468 unsigned long *insn
;
8469 boolean
*use_extend
;
8470 unsigned short *extend
;
8472 register const struct mips16_immed_operand
*op
;
8473 int mintiny
, maxtiny
;
8476 op
= mips16_immed_operands
;
8477 while (op
->type
!= type
)
8480 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8485 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8488 maxtiny
= 1 << op
->nbits
;
8493 maxtiny
= (1 << op
->nbits
) - 1;
8498 mintiny
= - (1 << (op
->nbits
- 1));
8499 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8502 /* Branch offsets have an implicit 0 in the lowest bit. */
8503 if (type
== 'p' || type
== 'q')
8506 if ((val
& ((1 << op
->shift
) - 1)) != 0
8507 || val
< (mintiny
<< op
->shift
)
8508 || val
> (maxtiny
<< op
->shift
))
8513 if (warn
&& ext
&& ! needext
)
8514 as_warn_where (file
, line
, _("extended operand requested but not required"));
8515 if (small
&& needext
)
8516 as_bad_where (file
, line
, _("invalid unextended operand value"));
8518 if (small
|| (! ext
&& ! needext
))
8522 *use_extend
= false;
8523 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8524 insnval
<<= op
->op_shift
;
8529 long minext
, maxext
;
8535 maxext
= (1 << op
->extbits
) - 1;
8539 minext
= - (1 << (op
->extbits
- 1));
8540 maxext
= (1 << (op
->extbits
- 1)) - 1;
8542 if (val
< minext
|| val
> maxext
)
8543 as_bad_where (file
, line
,
8544 _("operand value out of range for instruction"));
8547 if (op
->extbits
== 16)
8549 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8552 else if (op
->extbits
== 15)
8554 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8559 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8563 *extend
= (unsigned short) extval
;
8572 my_getSmallExpression (ep
, str
)
8583 ((str
[1] == 'h' && str
[2] == 'i')
8584 || (str
[1] == 'H' && str
[2] == 'I')
8585 || (str
[1] == 'l' && str
[2] == 'o'))
8597 * A small expression may be followed by a base register.
8598 * Scan to the end of this operand, and then back over a possible
8599 * base register. Then scan the small expression up to that
8600 * point. (Based on code in sparc.c...)
8602 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8604 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8606 if (isdigit ((unsigned char) sp
[-2]))
8608 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8610 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8616 else if (sp
- 5 >= str
8619 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8620 || (sp
[-3] == 's' && sp
[-2] == 'p')
8621 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8622 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8628 /* no expression means zero offset */
8631 /* %xx(reg) is an error */
8632 ep
->X_op
= O_absent
;
8637 ep
->X_op
= O_constant
;
8640 ep
->X_add_symbol
= NULL
;
8641 ep
->X_op_symbol
= NULL
;
8642 ep
->X_add_number
= 0;
8647 my_getExpression (ep
, str
);
8654 my_getExpression (ep
, str
);
8655 return c
; /* => %hi or %lo encountered */
8659 my_getExpression (ep
, str
)
8665 save_in
= input_line_pointer
;
8666 input_line_pointer
= str
;
8668 expr_end
= input_line_pointer
;
8669 input_line_pointer
= save_in
;
8671 /* If we are in mips16 mode, and this is an expression based on `.',
8672 then we bump the value of the symbol by 1 since that is how other
8673 text symbols are handled. We don't bother to handle complex
8674 expressions, just `.' plus or minus a constant. */
8675 if (mips_opts
.mips16
8676 && ep
->X_op
== O_symbol
8677 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8678 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8679 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8680 && symbol_constant_p (ep
->X_add_symbol
)
8681 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8682 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8685 /* Turn a string in input_line_pointer into a floating point constant
8686 of type type, and store the appropriate bytes in *litP. The number
8687 of LITTLENUMS emitted is stored in *sizeP . An error message is
8688 returned, or NULL on OK. */
8691 md_atof (type
, litP
, sizeP
)
8697 LITTLENUM_TYPE words
[4];
8713 return _("bad call to md_atof");
8716 t
= atof_ieee (input_line_pointer
, type
, words
);
8718 input_line_pointer
= t
;
8722 if (! target_big_endian
)
8724 for (i
= prec
- 1; i
>= 0; i
--)
8726 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8732 for (i
= 0; i
< prec
; i
++)
8734 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8743 md_number_to_chars (buf
, val
, n
)
8748 if (target_big_endian
)
8749 number_to_chars_bigendian (buf
, val
, n
);
8751 number_to_chars_littleendian (buf
, val
, n
);
8754 CONST
char *md_shortopts
= "O::g::G:";
8756 struct option md_longopts
[] = {
8757 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8758 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8759 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8760 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8761 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8762 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8763 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8764 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8765 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8766 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8767 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8768 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8769 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8770 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8771 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8772 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8773 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8774 {"break", no_argument
, NULL
, OPTION_BREAK
},
8775 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8776 #define OPTION_EB (OPTION_MD_BASE + 11)
8777 {"EB", no_argument
, NULL
, OPTION_EB
},
8778 #define OPTION_EL (OPTION_MD_BASE + 12)
8779 {"EL", no_argument
, NULL
, OPTION_EL
},
8780 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8781 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8782 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8783 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8784 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8785 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8786 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8787 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8788 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8789 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8790 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8791 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8792 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8793 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8794 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8795 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8796 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8797 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8798 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8799 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8802 #define OPTION_MABI (OPTION_MD_BASE + 38)
8803 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8805 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8806 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8807 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8808 #define OPTION_32 (OPTION_MD_BASE + 20)
8809 #define OPTION_64 (OPTION_MD_BASE + 21)
8811 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8812 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8813 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8814 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8815 {"32", no_argument
, NULL
, OPTION_32
},
8816 {"64", no_argument
, NULL
, OPTION_64
},
8819 {NULL
, no_argument
, NULL
, 0}
8821 size_t md_longopts_size
= sizeof(md_longopts
);
8824 md_parse_option (c
, arg
)
8839 target_big_endian
= 1;
8843 target_big_endian
= 0;
8847 if (arg
&& arg
[1] == '0')
8857 mips_debug
= atoi (arg
);
8858 /* When the MIPS assembler sees -g or -g2, it does not do
8859 optimizations which limit full symbolic debugging. We take
8860 that to be equivalent to -O0. */
8861 if (mips_debug
== 2)
8885 /* Identify the processor type */
8887 if (strcmp (p
, "default") == 0
8888 || strcmp (p
, "DEFAULT") == 0)
8894 /* We need to cope with the various "vr" prefixes for the 4300
8896 if (*p
== 'v' || *p
== 'V')
8902 if (*p
== 'r' || *p
== 'R')
8909 if (strcmp (p
, "10000") == 0
8910 || strcmp (p
, "10k") == 0
8911 || strcmp (p
, "10K") == 0)
8916 if (strcmp (p
, "2000") == 0
8917 || strcmp (p
, "2k") == 0
8918 || strcmp (p
, "2K") == 0)
8923 if (strcmp (p
, "3000") == 0
8924 || strcmp (p
, "3k") == 0
8925 || strcmp (p
, "3K") == 0)
8927 else if (strcmp (p
, "3900") == 0)
8932 if (strcmp (p
, "4000") == 0
8933 || strcmp (p
, "4k") == 0
8934 || strcmp (p
, "4K") == 0)
8936 else if (strcmp (p
, "4100") == 0)
8938 else if (strcmp (p
, "4111") == 0)
8940 else if (strcmp (p
, "4300") == 0)
8942 else if (strcmp (p
, "4400") == 0)
8944 else if (strcmp (p
, "4600") == 0)
8946 else if (strcmp (p
, "4650") == 0)
8948 else if (strcmp (p
, "4010") == 0)
8953 if (strcmp (p
, "5000") == 0
8954 || strcmp (p
, "5k") == 0
8955 || strcmp (p
, "5K") == 0)
8960 if (strcmp (p
, "6000") == 0
8961 || strcmp (p
, "6k") == 0
8962 || strcmp (p
, "6K") == 0)
8967 if (strcmp (p
, "8000") == 0
8968 || strcmp (p
, "8k") == 0
8969 || strcmp (p
, "8K") == 0)
8974 if (strcmp (p
, "orion") == 0)
8980 && (mips_cpu
!= 4300
8983 && mips_cpu
!= 5000))
8985 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
8991 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9002 case OPTION_NO_M4650
:
9009 case OPTION_NO_M4010
:
9016 case OPTION_NO_M4100
:
9024 case OPTION_NO_M3900
:
9028 mips_opts
.mips16
= 1;
9029 mips_no_prev_insn (false);
9032 case OPTION_NO_MIPS16
:
9033 mips_opts
.mips16
= 0;
9034 mips_no_prev_insn (false);
9037 case OPTION_MEMBEDDED_PIC
:
9038 mips_pic
= EMBEDDED_PIC
;
9039 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9041 as_bad (_("-G may not be used with embedded PIC code"));
9044 g_switch_value
= 0x7fffffff;
9047 /* When generating ELF code, we permit -KPIC and -call_shared to
9048 select SVR4_PIC, and -non_shared to select no PIC. This is
9049 intended to be compatible with Irix 5. */
9050 case OPTION_CALL_SHARED
:
9051 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9053 as_bad (_("-call_shared is supported only for ELF format"));
9056 mips_pic
= SVR4_PIC
;
9057 if (g_switch_seen
&& g_switch_value
!= 0)
9059 as_bad (_("-G may not be used with SVR4 PIC code"));
9065 case OPTION_NON_SHARED
:
9066 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9068 as_bad (_("-non_shared is supported only for ELF format"));
9074 /* The -xgot option tells the assembler to use 32 offsets when
9075 accessing the got in SVR4_PIC mode. It is for Irix
9082 if (! USE_GLOBAL_POINTER_OPT
)
9084 as_bad (_("-G is not supported for this configuration"));
9087 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9089 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9093 g_switch_value
= atoi (arg
);
9097 /* The -32 and -64 options tell the assembler to output the 32
9098 bit or the 64 bit MIPS ELF format. */
9105 const char **list
, **l
;
9107 list
= bfd_target_list ();
9108 for (l
= list
; *l
!= NULL
; l
++)
9109 if (strcmp (*l
, "elf64-bigmips") == 0
9110 || strcmp (*l
, "elf64-littlemips") == 0)
9113 as_fatal (_("No compiled in support for 64 bit object file format"));
9121 if (strcmp (arg
,"32") == 0
9122 || strcmp (arg
,"n32") == 0
9123 || strcmp (arg
,"64") == 0
9124 || strcmp (arg
,"o64") == 0
9125 || strcmp (arg
,"eabi") == 0)
9126 mips_abi_string
= arg
;
9138 show (stream
, string
, col_p
, first_p
)
9146 fprintf (stream
, "%24s", "");
9151 fprintf (stream
, ", ");
9155 if (*col_p
+ strlen (string
) > 72)
9157 fprintf (stream
, "\n%24s", "");
9161 fprintf (stream
, "%s", string
);
9162 *col_p
+= strlen (string
);
9169 md_show_usage (stream
)
9174 fprintf(stream
, _("\
9176 -membedded-pic generate embedded position independent code\n\
9177 -EB generate big endian output\n\
9178 -EL generate little endian output\n\
9179 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9180 -G NUM allow referencing objects up to NUM bytes\n\
9181 implicitly with the gp register [default 8]\n"));
9182 fprintf(stream
, _("\
9183 -mips1 generate MIPS ISA I instructions\n\
9184 -mips2 generate MIPS ISA II instructions\n\
9185 -mips3 generate MIPS ISA III instructions\n\
9186 -mips4 generate MIPS ISA IV instructions\n\
9187 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9191 show (stream
, "2000", &column
, &first
);
9192 show (stream
, "3000", &column
, &first
);
9193 show (stream
, "3900", &column
, &first
);
9194 show (stream
, "4000", &column
, &first
);
9195 show (stream
, "4010", &column
, &first
);
9196 show (stream
, "4100", &column
, &first
);
9197 show (stream
, "4111", &column
, &first
);
9198 show (stream
, "4300", &column
, &first
);
9199 show (stream
, "4400", &column
, &first
);
9200 show (stream
, "4600", &column
, &first
);
9201 show (stream
, "4650", &column
, &first
);
9202 show (stream
, "5000", &column
, &first
);
9203 show (stream
, "6000", &column
, &first
);
9204 show (stream
, "8000", &column
, &first
);
9205 show (stream
, "10000", &column
, &first
);
9206 fputc ('\n', stream
);
9208 fprintf (stream
, _("\
9209 -mCPU equivalent to -mcpu=CPU.\n\
9210 -no-mCPU don't generate code specific to CPU.\n\
9211 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9215 show (stream
, "3900", &column
, &first
);
9216 show (stream
, "4010", &column
, &first
);
9217 show (stream
, "4100", &column
, &first
);
9218 show (stream
, "4650", &column
, &first
);
9219 fputc ('\n', stream
);
9221 fprintf(stream
, _("\
9222 -mips16 generate mips16 instructions\n\
9223 -no-mips16 do not generate mips16 instructions\n"));
9224 fprintf(stream
, _("\
9225 -O0 remove unneeded NOPs, do not swap branches\n\
9226 -O remove unneeded NOPs and swap branches\n\
9227 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9228 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9230 fprintf(stream
, _("\
9231 -KPIC, -call_shared generate SVR4 position independent code\n\
9232 -non_shared do not generate position independent code\n\
9233 -xgot assume a 32 bit GOT\n\
9234 -32 create 32 bit object file (default)\n\
9235 -64 create 64 bit object file\n"));
9240 mips_init_after_args ()
9242 /* initialize opcodes */
9243 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9244 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9248 md_pcrel_from (fixP
)
9251 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9252 && fixP
->fx_addsy
!= (symbolS
*) NULL
9253 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9255 /* This makes a branch to an undefined symbol be a branch to the
9256 current location. */
9260 /* return the address of the delay slot */
9261 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9264 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9265 reloc for a cons. We could use the definition there, except that
9266 we want to handle 64 bit relocs specially. */
9269 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9272 unsigned int nbytes
;
9276 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9278 if (nbytes
== 8 && ! mips_64
)
9280 if (target_big_endian
)
9286 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9287 as_bad (_("Unsupported reloc size %d"), nbytes
);
9289 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9292 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9295 /* This is called before the symbol table is processed. In order to
9296 work with gcc when using mips-tfile, we must keep all local labels.
9297 However, in other cases, we want to discard them. If we were
9298 called with -g, but we didn't see any debugging information, it may
9299 mean that gcc is smuggling debugging information through to
9300 mips-tfile, in which case we must generate all local labels. */
9303 mips_frob_file_before_adjust ()
9305 #ifndef NO_ECOFF_DEBUGGING
9308 && ! ecoff_debugging_seen
)
9309 flag_keep_locals
= 1;
9313 /* Sort any unmatched HI16_S relocs so that they immediately precede
9314 the corresponding LO reloc. This is called before md_apply_fix and
9315 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9316 explicit use of the %hi modifier. */
9321 struct mips_hi_fixup
*l
;
9323 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9325 segment_info_type
*seginfo
;
9328 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9330 /* Check quickly whether the next fixup happens to be a matching
9332 if (l
->fixp
->fx_next
!= NULL
9333 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9334 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9335 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9338 /* Look through the fixups for this segment for a matching %lo.
9339 When we find one, move the %hi just in front of it. We do
9340 this in two passes. In the first pass, we try to find a
9341 unique %lo. In the second pass, we permit multiple %hi
9342 relocs for a single %lo (this is a GNU extension). */
9343 seginfo
= seg_info (l
->seg
);
9344 for (pass
= 0; pass
< 2; pass
++)
9349 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9351 /* Check whether this is a %lo fixup which matches l->fixp. */
9352 if (f
->fx_r_type
== BFD_RELOC_LO16
9353 && f
->fx_addsy
== l
->fixp
->fx_addsy
9354 && f
->fx_offset
== l
->fixp
->fx_offset
9357 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9358 || prev
->fx_addsy
!= f
->fx_addsy
9359 || prev
->fx_offset
!= f
->fx_offset
))
9363 /* Move l->fixp before f. */
9364 for (pf
= &seginfo
->fix_root
;
9366 pf
= &(*pf
)->fx_next
)
9367 assert (*pf
!= NULL
);
9369 *pf
= l
->fixp
->fx_next
;
9371 l
->fixp
->fx_next
= f
;
9373 seginfo
->fix_root
= l
->fixp
;
9375 prev
->fx_next
= l
->fixp
;
9386 #if 0 /* GCC code motion plus incomplete dead code elimination
9387 can leave a %hi without a %lo. */
9389 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9390 _("Unmatched %%hi reloc"));
9396 /* When generating embedded PIC code we need to use a special
9397 relocation to represent the difference of two symbols in the .text
9398 section (switch tables use a difference of this sort). See
9399 include/coff/mips.h for details. This macro checks whether this
9400 fixup requires the special reloc. */
9401 #define SWITCH_TABLE(fixp) \
9402 ((fixp)->fx_r_type == BFD_RELOC_32 \
9403 && (fixp)->fx_addsy != NULL \
9404 && (fixp)->fx_subsy != NULL \
9405 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9406 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9408 /* When generating embedded PIC code we must keep all PC relative
9409 relocations, in case the linker has to relax a call. We also need
9410 to keep relocations for switch table entries. */
9414 mips_force_relocation (fixp
)
9417 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9418 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9421 return (mips_pic
== EMBEDDED_PIC
9423 || SWITCH_TABLE (fixp
)
9424 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9425 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9428 /* Apply a fixup to the object file. */
9431 md_apply_fix (fixP
, valueP
)
9438 assert (fixP
->fx_size
== 4
9439 || fixP
->fx_r_type
== BFD_RELOC_16
9440 || fixP
->fx_r_type
== BFD_RELOC_64
9441 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9442 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9446 /* If we aren't adjusting this fixup to be against the section
9447 symbol, we need to adjust the value. */
9449 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9450 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9451 || S_IS_WEAK (fixP
->fx_addsy
)
9452 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9453 && (((bfd_get_section_flags (stdoutput
,
9454 S_GET_SEGMENT (fixP
->fx_addsy
))
9455 & SEC_LINK_ONCE
) != 0)
9456 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9458 sizeof (".gnu.linkonce") - 1))))
9461 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9462 if (value
!= 0 && ! fixP
->fx_pcrel
)
9464 /* In this case, the bfd_install_relocation routine will
9465 incorrectly add the symbol value back in. We just want
9466 the addend to appear in the object file. */
9467 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9473 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9475 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9478 switch (fixP
->fx_r_type
)
9480 case BFD_RELOC_MIPS_JMP
:
9481 case BFD_RELOC_HI16
:
9482 case BFD_RELOC_HI16_S
:
9483 case BFD_RELOC_MIPS_GPREL
:
9484 case BFD_RELOC_MIPS_LITERAL
:
9485 case BFD_RELOC_MIPS_CALL16
:
9486 case BFD_RELOC_MIPS_GOT16
:
9487 case BFD_RELOC_MIPS_GPREL32
:
9488 case BFD_RELOC_MIPS_GOT_HI16
:
9489 case BFD_RELOC_MIPS_GOT_LO16
:
9490 case BFD_RELOC_MIPS_CALL_HI16
:
9491 case BFD_RELOC_MIPS_CALL_LO16
:
9492 case BFD_RELOC_MIPS16_GPREL
:
9494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9495 _("Invalid PC relative reloc"));
9496 /* Nothing needed to do. The value comes from the reloc entry */
9499 case BFD_RELOC_MIPS16_JMP
:
9500 /* We currently always generate a reloc against a symbol, which
9501 means that we don't want an addend even if the symbol is
9503 fixP
->fx_addnumber
= 0;
9506 case BFD_RELOC_PCREL_HI16_S
:
9507 /* The addend for this is tricky if it is internal, so we just
9508 do everything here rather than in bfd_install_relocation. */
9509 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9511 /* For an external symbol adjust by the address to make it
9512 pcrel_offset. We use the address of the RELLO reloc
9513 which follows this one. */
9514 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9515 + fixP
->fx_next
->fx_where
);
9520 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9521 if (target_big_endian
)
9523 md_number_to_chars (buf
, value
, 2);
9526 case BFD_RELOC_PCREL_LO16
:
9527 /* The addend for this is tricky if it is internal, so we just
9528 do everything here rather than in bfd_install_relocation. */
9529 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9530 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9531 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9532 if (target_big_endian
)
9534 md_number_to_chars (buf
, value
, 2);
9538 /* This is handled like BFD_RELOC_32, but we output a sign
9539 extended value if we are only 32 bits. */
9541 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9543 if (8 <= sizeof (valueT
))
9544 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9551 w1
= w2
= fixP
->fx_where
;
9552 if (target_big_endian
)
9556 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9557 if ((value
& 0x80000000) != 0)
9561 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9567 /* If we are deleting this reloc entry, we must fill in the
9568 value now. This can happen if we have a .word which is not
9569 resolved when it appears but is later defined. We also need
9570 to fill in the value if this is an embedded PIC switch table
9573 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9574 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9579 /* If we are deleting this reloc entry, we must fill in the
9581 assert (fixP
->fx_size
== 2);
9583 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9587 case BFD_RELOC_LO16
:
9588 /* When handling an embedded PIC switch statement, we can wind
9589 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9592 if (value
< -0x8000 || value
> 0x7fff)
9593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9594 _("relocation overflow"));
9595 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9596 if (target_big_endian
)
9598 md_number_to_chars (buf
, value
, 2);
9602 case BFD_RELOC_16_PCREL_S2
:
9604 * We need to save the bits in the instruction since fixup_segment()
9605 * might be deleting the relocation entry (i.e., a branch within
9606 * the current segment).
9608 if ((value
& 0x3) != 0)
9609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9610 _("Branch to odd address (%lx)"), value
);
9613 /* update old instruction data */
9614 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9615 if (target_big_endian
)
9616 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9618 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9620 if (value
>= -0x8000 && value
< 0x8000)
9621 insn
|= value
& 0xffff;
9624 /* The branch offset is too large. If this is an
9625 unconditional branch, and we are not generating PIC code,
9626 we can convert it to an absolute jump instruction. */
9627 if (mips_pic
== NO_PIC
9629 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9630 && (fixP
->fx_frag
->fr_address
9631 < text_section
->vma
+ text_section
->_raw_size
)
9632 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9633 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9634 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9636 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9637 insn
= 0x0c000000; /* jal */
9639 insn
= 0x08000000; /* j */
9640 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9642 fixP
->fx_addsy
= section_symbol (text_section
);
9643 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9647 /* FIXME. It would be possible in principle to handle
9648 conditional branches which overflow. They could be
9649 transformed into a branch around a jump. This would
9650 require setting up variant frags for each different
9651 branch type. The native MIPS assembler attempts to
9652 handle these cases, but it appears to do it
9654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9655 _("Branch out of range"));
9659 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9662 case BFD_RELOC_VTABLE_INHERIT
:
9665 && !S_IS_DEFINED (fixP
->fx_addsy
)
9666 && !S_IS_WEAK (fixP
->fx_addsy
))
9667 S_SET_WEAK (fixP
->fx_addsy
);
9670 case BFD_RELOC_VTABLE_ENTRY
:
9686 const struct mips_opcode
*p
;
9687 int treg
, sreg
, dreg
, shamt
;
9692 for (i
= 0; i
< NUMOPCODES
; ++i
)
9694 p
= &mips_opcodes
[i
];
9695 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9697 printf ("%08lx %s\t", oc
, p
->name
);
9698 treg
= (oc
>> 16) & 0x1f;
9699 sreg
= (oc
>> 21) & 0x1f;
9700 dreg
= (oc
>> 11) & 0x1f;
9701 shamt
= (oc
>> 6) & 0x1f;
9703 for (args
= p
->args
;; ++args
)
9714 printf ("%c", *args
);
9718 assert (treg
== sreg
);
9719 printf ("$%d,$%d", treg
, sreg
);
9724 printf ("$%d", dreg
);
9729 printf ("$%d", treg
);
9733 printf ("0x%x", treg
);
9738 printf ("$%d", sreg
);
9742 printf ("0x%08lx", oc
& 0x1ffffff);
9754 printf ("$%d", shamt
);
9765 printf (_("%08lx UNDEFINED\n"), oc
);
9776 name
= input_line_pointer
;
9777 c
= get_symbol_end ();
9778 p
= (symbolS
*) symbol_find_or_make (name
);
9779 *input_line_pointer
= c
;
9783 /* Align the current frag to a given power of two. The MIPS assembler
9784 also automatically adjusts any preceding label. */
9787 mips_align (to
, fill
, label
)
9792 mips_emit_delays (false);
9793 frag_align (to
, fill
, 0);
9794 record_alignment (now_seg
, to
);
9797 assert (S_GET_SEGMENT (label
) == now_seg
);
9798 symbol_set_frag (label
, frag_now
);
9799 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9803 /* Align to a given power of two. .align 0 turns off the automatic
9804 alignment used by the data creating pseudo-ops. */
9811 register long temp_fill
;
9812 long max_alignment
= 15;
9816 o Note that the assembler pulls down any immediately preceeding label
9817 to the aligned address.
9818 o It's not documented but auto alignment is reinstated by
9819 a .align pseudo instruction.
9820 o Note also that after auto alignment is turned off the mips assembler
9821 issues an error on attempt to assemble an improperly aligned data item.
9826 temp
= get_absolute_expression ();
9827 if (temp
> max_alignment
)
9828 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9831 as_warn (_("Alignment negative: 0 assumed."));
9834 if (*input_line_pointer
== ',')
9836 input_line_pointer
++;
9837 temp_fill
= get_absolute_expression ();
9844 mips_align (temp
, (int) temp_fill
,
9845 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9852 demand_empty_rest_of_line ();
9856 mips_flush_pending_output ()
9858 mips_emit_delays (false);
9859 mips_clear_insn_labels ();
9868 /* When generating embedded PIC code, we only use the .text, .lit8,
9869 .sdata and .sbss sections. We change the .data and .rdata
9870 pseudo-ops to use .sdata. */
9871 if (mips_pic
== EMBEDDED_PIC
9872 && (sec
== 'd' || sec
== 'r'))
9876 /* The ELF backend needs to know that we are changing sections, so
9877 that .previous works correctly. We could do something like check
9878 for a obj_section_change_hook macro, but that might be confusing
9879 as it would not be appropriate to use it in the section changing
9880 functions in read.c, since obj-elf.c intercepts those. FIXME:
9881 This should be cleaner, somehow. */
9882 obj_elf_section_change_hook ();
9885 mips_emit_delays (false);
9895 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9896 demand_empty_rest_of_line ();
9900 if (USE_GLOBAL_POINTER_OPT
)
9902 seg
= subseg_new (RDATA_SECTION_NAME
,
9903 (subsegT
) get_absolute_expression ());
9904 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9906 bfd_set_section_flags (stdoutput
, seg
,
9912 if (strcmp (TARGET_OS
, "elf") != 0)
9913 bfd_set_section_alignment (stdoutput
, seg
, 4);
9915 demand_empty_rest_of_line ();
9919 as_bad (_("No read only data section in this object file format"));
9920 demand_empty_rest_of_line ();
9926 if (USE_GLOBAL_POINTER_OPT
)
9928 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9929 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9931 bfd_set_section_flags (stdoutput
, seg
,
9932 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9934 if (strcmp (TARGET_OS
, "elf") != 0)
9935 bfd_set_section_alignment (stdoutput
, seg
, 4);
9937 demand_empty_rest_of_line ();
9942 as_bad (_("Global pointers not supported; recompile -G 0"));
9943 demand_empty_rest_of_line ();
9952 mips_enable_auto_align ()
9963 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9964 mips_emit_delays (false);
9965 if (log_size
> 0 && auto_align
)
9966 mips_align (log_size
, 0, label
);
9967 mips_clear_insn_labels ();
9968 cons (1 << log_size
);
9977 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9979 mips_emit_delays (false);
9984 mips_align (3, 0, label
);
9986 mips_align (2, 0, label
);
9989 mips_clear_insn_labels ();
9994 /* Handle .globl. We need to override it because on Irix 5 you are
9997 where foo is an undefined symbol, to mean that foo should be
9998 considered to be the address of a function. */
10009 name
= input_line_pointer
;
10010 c
= get_symbol_end ();
10011 symbolP
= symbol_find_or_make (name
);
10012 *input_line_pointer
= c
;
10013 SKIP_WHITESPACE ();
10015 /* On Irix 5, every global symbol that is not explicitly labelled as
10016 being a function is apparently labelled as being an object. */
10019 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10024 secname
= input_line_pointer
;
10025 c
= get_symbol_end ();
10026 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10028 as_bad (_("%s: no such section"), secname
);
10029 *input_line_pointer
= c
;
10031 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10032 flag
= BSF_FUNCTION
;
10035 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10037 S_SET_EXTERNAL (symbolP
);
10038 demand_empty_rest_of_line ();
10048 opt
= input_line_pointer
;
10049 c
= get_symbol_end ();
10053 /* FIXME: What does this mean? */
10055 else if (strncmp (opt
, "pic", 3) == 0)
10059 i
= atoi (opt
+ 3);
10063 mips_pic
= SVR4_PIC
;
10065 as_bad (_(".option pic%d not supported"), i
);
10067 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10069 if (g_switch_seen
&& g_switch_value
!= 0)
10070 as_warn (_("-G may not be used with SVR4 PIC code"));
10071 g_switch_value
= 0;
10072 bfd_set_gp_size (stdoutput
, 0);
10076 as_warn (_("Unrecognized option \"%s\""), opt
);
10078 *input_line_pointer
= c
;
10079 demand_empty_rest_of_line ();
10082 /* This structure is used to hold a stack of .set values. */
10084 struct mips_option_stack
10086 struct mips_option_stack
*next
;
10087 struct mips_set_options options
;
10090 static struct mips_option_stack
*mips_opts_stack
;
10092 /* Handle the .set pseudo-op. */
10098 char *name
= input_line_pointer
, ch
;
10100 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10101 input_line_pointer
++;
10102 ch
= *input_line_pointer
;
10103 *input_line_pointer
= '\0';
10105 if (strcmp (name
, "reorder") == 0)
10107 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10109 /* If we still have pending nops, we can discard them. The
10110 usual nop handling will insert any that are still
10112 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10113 * (mips_opts
.mips16
? 2 : 4));
10114 prev_nop_frag
= NULL
;
10116 mips_opts
.noreorder
= 0;
10118 else if (strcmp (name
, "noreorder") == 0)
10120 mips_emit_delays (true);
10121 mips_opts
.noreorder
= 1;
10122 mips_any_noreorder
= 1;
10124 else if (strcmp (name
, "at") == 0)
10126 mips_opts
.noat
= 0;
10128 else if (strcmp (name
, "noat") == 0)
10130 mips_opts
.noat
= 1;
10132 else if (strcmp (name
, "macro") == 0)
10134 mips_opts
.warn_about_macros
= 0;
10136 else if (strcmp (name
, "nomacro") == 0)
10138 if (mips_opts
.noreorder
== 0)
10139 as_bad (_("`noreorder' must be set before `nomacro'"));
10140 mips_opts
.warn_about_macros
= 1;
10142 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10144 mips_opts
.nomove
= 0;
10146 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10148 mips_opts
.nomove
= 1;
10150 else if (strcmp (name
, "bopt") == 0)
10152 mips_opts
.nobopt
= 0;
10154 else if (strcmp (name
, "nobopt") == 0)
10156 mips_opts
.nobopt
= 1;
10158 else if (strcmp (name
, "mips16") == 0
10159 || strcmp (name
, "MIPS-16") == 0)
10160 mips_opts
.mips16
= 1;
10161 else if (strcmp (name
, "nomips16") == 0
10162 || strcmp (name
, "noMIPS-16") == 0)
10163 mips_opts
.mips16
= 0;
10164 else if (strncmp (name
, "mips", 4) == 0)
10168 /* Permit the user to change the ISA on the fly. Needless to
10169 say, misuse can cause serious problems. */
10170 isa
= atoi (name
+ 4);
10172 mips_opts
.isa
= file_mips_isa
;
10173 else if (isa
< 1 || isa
> 4)
10174 as_bad (_("unknown ISA level"));
10176 mips_opts
.isa
= isa
;
10178 else if (strcmp (name
, "autoextend") == 0)
10179 mips_opts
.noautoextend
= 0;
10180 else if (strcmp (name
, "noautoextend") == 0)
10181 mips_opts
.noautoextend
= 1;
10182 else if (strcmp (name
, "push") == 0)
10184 struct mips_option_stack
*s
;
10186 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10187 s
->next
= mips_opts_stack
;
10188 s
->options
= mips_opts
;
10189 mips_opts_stack
= s
;
10191 else if (strcmp (name
, "pop") == 0)
10193 struct mips_option_stack
*s
;
10195 s
= mips_opts_stack
;
10197 as_bad (_(".set pop with no .set push"));
10200 /* If we're changing the reorder mode we need to handle
10201 delay slots correctly. */
10202 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10203 mips_emit_delays (true);
10204 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10206 if (prev_nop_frag
!= NULL
)
10208 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10209 * (mips_opts
.mips16
? 2 : 4));
10210 prev_nop_frag
= NULL
;
10214 mips_opts
= s
->options
;
10215 mips_opts_stack
= s
->next
;
10221 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10223 *input_line_pointer
= ch
;
10224 demand_empty_rest_of_line ();
10227 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10228 .option pic2. It means to generate SVR4 PIC calls. */
10231 s_abicalls (ignore
)
10234 mips_pic
= SVR4_PIC
;
10235 if (USE_GLOBAL_POINTER_OPT
)
10237 if (g_switch_seen
&& g_switch_value
!= 0)
10238 as_warn (_("-G may not be used with SVR4 PIC code"));
10239 g_switch_value
= 0;
10241 bfd_set_gp_size (stdoutput
, 0);
10242 demand_empty_rest_of_line ();
10245 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10246 PIC code. It sets the $gp register for the function based on the
10247 function address, which is in the register named in the argument.
10248 This uses a relocation against _gp_disp, which is handled specially
10249 by the linker. The result is:
10250 lui $gp,%hi(_gp_disp)
10251 addiu $gp,$gp,%lo(_gp_disp)
10252 addu $gp,$gp,.cpload argument
10253 The .cpload argument is normally $25 == $t9. */
10262 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10263 if (mips_pic
!= SVR4_PIC
)
10269 /* .cpload should be a in .set noreorder section. */
10270 if (mips_opts
.noreorder
== 0)
10271 as_warn (_(".cpload not in noreorder section"));
10273 ex
.X_op
= O_symbol
;
10274 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10275 ex
.X_op_symbol
= NULL
;
10276 ex
.X_add_number
= 0;
10278 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10279 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10281 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10282 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10283 (int) BFD_RELOC_LO16
);
10285 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10286 GP
, GP
, tc_get_register (0));
10288 demand_empty_rest_of_line ();
10291 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10292 offset from $sp. The offset is remembered, and after making a PIC
10293 call $gp is restored from that location. */
10296 s_cprestore (ignore
)
10302 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10303 if (mips_pic
!= SVR4_PIC
)
10309 mips_cprestore_offset
= get_absolute_expression ();
10311 ex
.X_op
= O_constant
;
10312 ex
.X_add_symbol
= NULL
;
10313 ex
.X_op_symbol
= NULL
;
10314 ex
.X_add_number
= mips_cprestore_offset
;
10316 macro_build ((char *) NULL
, &icnt
, &ex
,
10317 ((bfd_arch_bits_per_address (stdoutput
) == 32
10318 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10320 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10322 demand_empty_rest_of_line ();
10325 /* Handle the .gpword pseudo-op. This is used when generating PIC
10326 code. It generates a 32 bit GP relative reloc. */
10336 /* When not generating PIC code, this is treated as .word. */
10337 if (mips_pic
!= SVR4_PIC
)
10343 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10344 mips_emit_delays (true);
10346 mips_align (2, 0, label
);
10347 mips_clear_insn_labels ();
10351 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10353 as_bad (_("Unsupported use of .gpword"));
10354 ignore_rest_of_line ();
10358 md_number_to_chars (p
, (valueT
) 0, 4);
10359 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10360 BFD_RELOC_MIPS_GPREL32
);
10362 demand_empty_rest_of_line ();
10365 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10366 tables in SVR4 PIC code. */
10375 /* This is ignored when not generating SVR4 PIC code. */
10376 if (mips_pic
!= SVR4_PIC
)
10382 /* Add $gp to the register named as an argument. */
10383 reg
= tc_get_register (0);
10384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10385 ((bfd_arch_bits_per_address (stdoutput
) == 32
10386 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10387 ? "addu" : "daddu"),
10388 "d,v,t", reg
, reg
, GP
);
10390 demand_empty_rest_of_line ();
10393 /* Handle the .insn pseudo-op. This marks instruction labels in
10394 mips16 mode. This permits the linker to handle them specially,
10395 such as generating jalx instructions when needed. We also make
10396 them odd for the duration of the assembly, in order to generate the
10397 right sort of code. We will make them even in the adjust_symtab
10398 routine, while leaving them marked. This is convenient for the
10399 debugger and the disassembler. The linker knows to make them odd
10406 if (mips_opts
.mips16
)
10407 mips16_mark_labels ();
10409 demand_empty_rest_of_line ();
10412 /* Handle a .stabn directive. We need these in order to mark a label
10413 as being a mips16 text label correctly. Sometimes the compiler
10414 will emit a label, followed by a .stabn, and then switch sections.
10415 If the label and .stabn are in mips16 mode, then the label is
10416 really a mips16 text label. */
10422 if (type
== 'n' && mips_opts
.mips16
)
10423 mips16_mark_labels ();
10428 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10432 s_mips_weakext (ignore
)
10440 name
= input_line_pointer
;
10441 c
= get_symbol_end ();
10442 symbolP
= symbol_find_or_make (name
);
10443 S_SET_WEAK (symbolP
);
10444 *input_line_pointer
= c
;
10446 SKIP_WHITESPACE ();
10448 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10450 if (S_IS_DEFINED (symbolP
))
10452 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10453 S_GET_NAME (symbolP
));
10454 ignore_rest_of_line ();
10458 if (*input_line_pointer
== ',')
10460 ++input_line_pointer
;
10461 SKIP_WHITESPACE ();
10465 if (exp
.X_op
!= O_symbol
)
10467 as_bad ("bad .weakext directive");
10468 ignore_rest_of_line();
10471 symbol_set_value_expression (symbolP
, &exp
);
10474 demand_empty_rest_of_line ();
10477 /* Parse a register string into a number. Called from the ECOFF code
10478 to parse .frame. The argument is non-zero if this is the frame
10479 register, so that we can record it in mips_frame_reg. */
10482 tc_get_register (frame
)
10487 SKIP_WHITESPACE ();
10488 if (*input_line_pointer
++ != '$')
10490 as_warn (_("expected `$'"));
10493 else if (isdigit ((unsigned char) *input_line_pointer
))
10495 reg
= get_absolute_expression ();
10496 if (reg
< 0 || reg
>= 32)
10498 as_warn (_("Bad register number"));
10504 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10506 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10508 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10510 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10514 as_warn (_("Unrecognized register name"));
10517 input_line_pointer
+= 2;
10520 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10525 md_section_align (seg
, addr
)
10529 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10532 /* We don't need to align ELF sections to the full alignment.
10533 However, Irix 5 may prefer that we align them at least to a 16
10534 byte boundary. We don't bother to align the sections if we are
10535 targeted for an embedded system. */
10536 if (strcmp (TARGET_OS
, "elf") == 0)
10542 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10545 /* Utility routine, called from above as well. If called while the
10546 input file is still being read, it's only an approximation. (For
10547 example, a symbol may later become defined which appeared to be
10548 undefined earlier.) */
10551 nopic_need_relax (sym
, before_relaxing
)
10553 int before_relaxing
;
10558 if (USE_GLOBAL_POINTER_OPT
)
10560 const char *symname
;
10563 /* Find out whether this symbol can be referenced off the GP
10564 register. It can be if it is smaller than the -G size or if
10565 it is in the .sdata or .sbss section. Certain symbols can
10566 not be referenced off the GP, although it appears as though
10568 symname
= S_GET_NAME (sym
);
10569 if (symname
!= (const char *) NULL
10570 && (strcmp (symname
, "eprol") == 0
10571 || strcmp (symname
, "etext") == 0
10572 || strcmp (symname
, "_gp") == 0
10573 || strcmp (symname
, "edata") == 0
10574 || strcmp (symname
, "_fbss") == 0
10575 || strcmp (symname
, "_fdata") == 0
10576 || strcmp (symname
, "_ftext") == 0
10577 || strcmp (symname
, "end") == 0
10578 || strcmp (symname
, "_gp_disp") == 0))
10580 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10582 #ifndef NO_ECOFF_DEBUGGING
10583 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10584 && (symbol_get_obj (sym
)->ecoff_extern_size
10585 <= g_switch_value
))
10587 /* We must defer this decision until after the whole
10588 file has been read, since there might be a .extern
10589 after the first use of this symbol. */
10590 || (before_relaxing
10591 #ifndef NO_ECOFF_DEBUGGING
10592 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10594 && S_GET_VALUE (sym
) == 0)
10595 || (S_GET_VALUE (sym
) != 0
10596 && S_GET_VALUE (sym
) <= g_switch_value
)))
10600 const char *segname
;
10602 segname
= segment_name (S_GET_SEGMENT (sym
));
10603 assert (strcmp (segname
, ".lit8") != 0
10604 && strcmp (segname
, ".lit4") != 0);
10605 change
= (strcmp (segname
, ".sdata") != 0
10606 && strcmp (segname
, ".sbss") != 0
10607 && strncmp (segname
, ".sdata.", 7) != 0
10608 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10613 /* We are not optimizing for the GP register. */
10617 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10618 extended opcode. SEC is the section the frag is in. */
10621 mips16_extended_frag (fragp
, sec
, stretch
)
10627 register const struct mips16_immed_operand
*op
;
10629 int mintiny
, maxtiny
;
10632 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10634 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10637 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10638 op
= mips16_immed_operands
;
10639 while (op
->type
!= type
)
10642 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10647 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10650 maxtiny
= 1 << op
->nbits
;
10655 maxtiny
= (1 << op
->nbits
) - 1;
10660 mintiny
= - (1 << (op
->nbits
- 1));
10661 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10664 /* We can't always call S_GET_VALUE here, because we don't want to
10665 lock in a particular frag address. */
10666 if (symbol_constant_p (fragp
->fr_symbol
))
10668 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10669 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10670 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10672 else if (symbol_equated_p (fragp
->fr_symbol
)
10673 && (symbol_constant_p
10674 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10678 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10679 val
= (S_GET_VALUE (eqsym
)
10680 + symbol_get_frag (eqsym
)->fr_address
10681 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10682 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10683 symsec
= S_GET_SEGMENT (eqsym
);
10692 /* We won't have the section when we are called from
10693 mips_relax_frag. However, we will always have been called
10694 from md_estimate_size_before_relax first. If this is a
10695 branch to a different section, we mark it as such. If SEC is
10696 NULL, and the frag is not marked, then it must be a branch to
10697 the same section. */
10700 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10707 fragp
->fr_subtype
=
10708 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10710 /* FIXME: We should support this, and let the linker
10711 catch branches and loads that are out of range. */
10712 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10713 _("unsupported PC relative reference to different section"));
10719 /* In this case, we know for sure that the symbol fragment is in
10720 the same section. If the fr_address of the symbol fragment
10721 is greater then the address of this fragment we want to add
10722 in STRETCH in order to get a better estimate of the address.
10723 This particularly matters because of the shift bits. */
10725 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10726 >= fragp
->fr_address
))
10730 /* Adjust stretch for any alignment frag. Note that if have
10731 been expanding the earlier code, the symbol may be
10732 defined in what appears to be an earlier frag. FIXME:
10733 This doesn't handle the fr_subtype field, which specifies
10734 a maximum number of bytes to skip when doing an
10737 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10740 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10743 stretch
= - ((- stretch
)
10744 & ~ ((1 << (int) f
->fr_offset
) - 1));
10746 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10755 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10757 /* The base address rules are complicated. The base address of
10758 a branch is the following instruction. The base address of a
10759 PC relative load or add is the instruction itself, but if it
10760 is in a delay slot (in which case it can not be extended) use
10761 the address of the instruction whose delay slot it is in. */
10762 if (type
== 'p' || type
== 'q')
10766 /* If we are currently assuming that this frag should be
10767 extended, then, the current address is two bytes
10769 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10772 /* Ignore the low bit in the target, since it will be set
10773 for a text label. */
10774 if ((val
& 1) != 0)
10777 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10779 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10782 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10784 /* Branch offsets have an implicit 0 in the lowest bit. */
10785 if (type
== 'p' || type
== 'q')
10788 /* If any of the shifted bits are set, we must use an extended
10789 opcode. If the address depends on the size of this
10790 instruction, this can lead to a loop, so we arrange to always
10791 use an extended opcode. We only check this when we are in
10792 the main relaxation loop, when SEC is NULL. */
10793 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10795 fragp
->fr_subtype
=
10796 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10800 /* If we are about to mark a frag as extended because the value
10801 is precisely maxtiny + 1, then there is a chance of an
10802 infinite loop as in the following code:
10807 In this case when the la is extended, foo is 0x3fc bytes
10808 away, so the la can be shrunk, but then foo is 0x400 away, so
10809 the la must be extended. To avoid this loop, we mark the
10810 frag as extended if it was small, and is about to become
10811 extended with a value of maxtiny + 1. */
10812 if (val
== ((maxtiny
+ 1) << op
->shift
)
10813 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10816 fragp
->fr_subtype
=
10817 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10821 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10822 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10824 if ((val
& ((1 << op
->shift
) - 1)) != 0
10825 || val
< (mintiny
<< op
->shift
)
10826 || val
> (maxtiny
<< op
->shift
))
10832 /* Estimate the size of a frag before relaxing. Unless this is the
10833 mips16, we are not really relaxing here, and the final size is
10834 encoded in the subtype information. For the mips16, we have to
10835 decide whether we are using an extended opcode or not. */
10839 md_estimate_size_before_relax (fragp
, segtype
)
10845 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10847 if (mips16_extended_frag (fragp
, segtype
, 0))
10849 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10854 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10859 if (mips_pic
== NO_PIC
)
10861 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10863 else if (mips_pic
== SVR4_PIC
)
10868 sym
= fragp
->fr_symbol
;
10870 /* Handle the case of a symbol equated to another symbol. */
10871 while (symbol_equated_p (sym
)
10872 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10876 /* It's possible to get a loop here in a badly written
10878 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10884 symsec
= S_GET_SEGMENT (sym
);
10886 /* This must duplicate the test in adjust_reloc_syms. */
10887 change
= (symsec
!= &bfd_und_section
10888 && symsec
!= &bfd_abs_section
10889 && ! bfd_is_com_section (symsec
));
10896 /* Record the offset to the first reloc in the fr_opcode field.
10897 This lets md_convert_frag and tc_gen_reloc know that the code
10898 must be expanded. */
10899 fragp
->fr_opcode
= (fragp
->fr_literal
10901 - RELAX_OLD (fragp
->fr_subtype
)
10902 + RELAX_RELOC1 (fragp
->fr_subtype
));
10903 /* FIXME: This really needs as_warn_where. */
10904 if (RELAX_WARN (fragp
->fr_subtype
))
10905 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
10911 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10914 /* This is called to see whether a reloc against a defined symbol
10915 should be converted into a reloc against a section. Don't adjust
10916 MIPS16 jump relocations, so we don't have to worry about the format
10917 of the offset in the .o file. Don't adjust relocations against
10918 mips16 symbols, so that the linker can find them if it needs to set
10922 mips_fix_adjustable (fixp
)
10925 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10927 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10928 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10930 if (fixp
->fx_addsy
== NULL
)
10933 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10934 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10935 && fixp
->fx_subsy
== NULL
)
10941 /* Translate internal representation of relocation info to BFD target
10945 tc_gen_reloc (section
, fixp
)
10949 static arelent
*retval
[4];
10951 bfd_reloc_code_real_type code
;
10953 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10956 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10957 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10958 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10960 if (mips_pic
== EMBEDDED_PIC
10961 && SWITCH_TABLE (fixp
))
10963 /* For a switch table entry we use a special reloc. The addend
10964 is actually the difference between the reloc address and the
10966 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10967 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10968 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
10969 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10971 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10973 /* We use a special addend for an internal RELLO reloc. */
10974 if (symbol_section_p (fixp
->fx_addsy
))
10975 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10977 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10979 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10981 assert (fixp
->fx_next
!= NULL
10982 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10983 /* We use a special addend for an internal RELHI reloc. The
10984 reloc is relative to the RELLO; adjust the addend
10986 if (symbol_section_p (fixp
->fx_addsy
))
10987 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10988 + fixp
->fx_next
->fx_where
10989 - S_GET_VALUE (fixp
->fx_subsy
));
10991 reloc
->addend
= (fixp
->fx_addnumber
10992 + fixp
->fx_next
->fx_frag
->fr_address
10993 + fixp
->fx_next
->fx_where
);
10995 else if (fixp
->fx_pcrel
== 0)
10996 reloc
->addend
= fixp
->fx_addnumber
;
10999 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11000 /* A gruesome hack which is a result of the gruesome gas reloc
11002 reloc
->addend
= reloc
->address
;
11004 reloc
->addend
= -reloc
->address
;
11007 /* If this is a variant frag, we may need to adjust the existing
11008 reloc and generate a new one. */
11009 if (fixp
->fx_frag
->fr_opcode
!= NULL
11010 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11011 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11012 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11013 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11014 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11015 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11016 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11020 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11022 /* If this is not the last reloc in this frag, then we have two
11023 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11024 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11025 the second one handle all of them. */
11026 if (fixp
->fx_next
!= NULL
11027 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11029 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11030 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11031 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11032 && (fixp
->fx_next
->fx_r_type
11033 == BFD_RELOC_MIPS_GOT_LO16
))
11034 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11035 && (fixp
->fx_next
->fx_r_type
11036 == BFD_RELOC_MIPS_CALL_LO16
)));
11041 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11042 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11043 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11045 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11046 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11047 reloc2
->address
= (reloc
->address
11048 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11049 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11050 reloc2
->addend
= fixp
->fx_addnumber
;
11051 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11052 assert (reloc2
->howto
!= NULL
);
11054 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11058 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11061 reloc3
->address
+= 4;
11064 if (mips_pic
== NO_PIC
)
11066 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11067 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11069 else if (mips_pic
== SVR4_PIC
)
11071 switch (fixp
->fx_r_type
)
11075 case BFD_RELOC_MIPS_GOT16
:
11077 case BFD_RELOC_MIPS_CALL16
:
11078 case BFD_RELOC_MIPS_GOT_LO16
:
11079 case BFD_RELOC_MIPS_CALL_LO16
:
11080 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11088 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11089 to be used in the relocation's section offset. */
11090 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11092 reloc
->address
= reloc
->addend
;
11096 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11097 fixup_segment converted a non-PC relative reloc into a PC
11098 relative reloc. In such a case, we need to convert the reloc
11100 code
= fixp
->fx_r_type
;
11101 if (fixp
->fx_pcrel
)
11106 code
= BFD_RELOC_8_PCREL
;
11109 code
= BFD_RELOC_16_PCREL
;
11112 code
= BFD_RELOC_32_PCREL
;
11115 code
= BFD_RELOC_64_PCREL
;
11117 case BFD_RELOC_8_PCREL
:
11118 case BFD_RELOC_16_PCREL
:
11119 case BFD_RELOC_32_PCREL
:
11120 case BFD_RELOC_64_PCREL
:
11121 case BFD_RELOC_16_PCREL_S2
:
11122 case BFD_RELOC_PCREL_HI16_S
:
11123 case BFD_RELOC_PCREL_LO16
:
11126 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11127 _("Cannot make %s relocation PC relative"),
11128 bfd_get_reloc_code_name (code
));
11132 /* To support a PC relative reloc when generating embedded PIC code
11133 for ECOFF, we use a Cygnus extension. We check for that here to
11134 make sure that we don't let such a reloc escape normally. */
11135 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11136 && code
== BFD_RELOC_16_PCREL_S2
11137 && mips_pic
!= EMBEDDED_PIC
)
11138 reloc
->howto
= NULL
;
11140 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11142 if (reloc
->howto
== NULL
)
11144 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11145 _("Can not represent %s relocation in this object file format"),
11146 bfd_get_reloc_code_name (code
));
11153 /* Relax a machine dependent frag. This returns the amount by which
11154 the current size of the frag should change. */
11157 mips_relax_frag (fragp
, stretch
)
11161 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11164 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11166 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11168 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11173 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11175 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11182 /* Convert a machine dependent frag. */
11185 md_convert_frag (abfd
, asec
, fragp
)
11193 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11196 register const struct mips16_immed_operand
*op
;
11197 boolean small
, ext
;
11200 unsigned long insn
;
11201 boolean use_extend
;
11202 unsigned short extend
;
11204 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11205 op
= mips16_immed_operands
;
11206 while (op
->type
!= type
)
11209 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11220 resolve_symbol_value (fragp
->fr_symbol
, 1);
11221 val
= S_GET_VALUE (fragp
->fr_symbol
);
11226 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11228 /* The rules for the base address of a PC relative reloc are
11229 complicated; see mips16_extended_frag. */
11230 if (type
== 'p' || type
== 'q')
11235 /* Ignore the low bit in the target, since it will be
11236 set for a text label. */
11237 if ((val
& 1) != 0)
11240 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11242 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11245 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11248 /* Make sure the section winds up with the alignment we have
11251 record_alignment (asec
, op
->shift
);
11255 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11256 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11257 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11258 _("extended instruction in delay slot"));
11260 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11262 if (target_big_endian
)
11263 insn
= bfd_getb16 (buf
);
11265 insn
= bfd_getl16 (buf
);
11267 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11268 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11269 small
, ext
, &insn
, &use_extend
, &extend
);
11273 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11274 fragp
->fr_fix
+= 2;
11278 md_number_to_chars (buf
, insn
, 2);
11279 fragp
->fr_fix
+= 2;
11284 if (fragp
->fr_opcode
== NULL
)
11287 old
= RELAX_OLD (fragp
->fr_subtype
);
11288 new = RELAX_NEW (fragp
->fr_subtype
);
11289 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11292 memcpy (fixptr
- old
, fixptr
, new);
11294 fragp
->fr_fix
+= new - old
;
11300 /* This function is called after the relocs have been generated.
11301 We've been storing mips16 text labels as odd. Here we convert them
11302 back to even for the convenience of the debugger. */
11305 mips_frob_file_after_relocs ()
11308 unsigned int count
, i
;
11310 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11313 syms
= bfd_get_outsymbols (stdoutput
);
11314 count
= bfd_get_symcount (stdoutput
);
11315 for (i
= 0; i
< count
; i
++, syms
++)
11317 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11318 && ((*syms
)->value
& 1) != 0)
11320 (*syms
)->value
&= ~1;
11321 /* If the symbol has an odd size, it was probably computed
11322 incorrectly, so adjust that as well. */
11323 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11324 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11331 /* This function is called whenever a label is defined. It is used
11332 when handling branch delays; if a branch has a label, we assume we
11333 can not move it. */
11336 mips_define_label (sym
)
11339 struct insn_label_list
*l
;
11341 if (free_insn_labels
== NULL
)
11342 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11345 l
= free_insn_labels
;
11346 free_insn_labels
= l
->next
;
11350 l
->next
= insn_labels
;
11354 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11356 /* Some special processing for a MIPS ELF file. */
11359 mips_elf_final_processing ()
11361 /* Write out the register information. */
11366 s
.ri_gprmask
= mips_gprmask
;
11367 s
.ri_cprmask
[0] = mips_cprmask
[0];
11368 s
.ri_cprmask
[1] = mips_cprmask
[1];
11369 s
.ri_cprmask
[2] = mips_cprmask
[2];
11370 s
.ri_cprmask
[3] = mips_cprmask
[3];
11371 /* The gp_value field is set by the MIPS ELF backend. */
11373 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11374 ((Elf32_External_RegInfo
*)
11375 mips_regmask_frag
));
11379 Elf64_Internal_RegInfo s
;
11381 s
.ri_gprmask
= mips_gprmask
;
11383 s
.ri_cprmask
[0] = mips_cprmask
[0];
11384 s
.ri_cprmask
[1] = mips_cprmask
[1];
11385 s
.ri_cprmask
[2] = mips_cprmask
[2];
11386 s
.ri_cprmask
[3] = mips_cprmask
[3];
11387 /* The gp_value field is set by the MIPS ELF backend. */
11389 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11390 ((Elf64_External_RegInfo
*)
11391 mips_regmask_frag
));
11394 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11395 sort of BFD interface for this. */
11396 if (mips_any_noreorder
)
11397 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11398 if (mips_pic
!= NO_PIC
)
11399 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11401 /* Set the MIPS ELF ABI flags. */
11402 if (mips_abi_string
== 0)
11404 else if (strcmp (mips_abi_string
,"32") == 0)
11405 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11406 else if (strcmp (mips_abi_string
,"o64") == 0)
11407 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11408 else if (strcmp (mips_abi_string
,"eabi") == 0)
11411 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11413 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11416 if (mips_32bitmode
)
11417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11420 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11422 typedef struct proc
11425 unsigned long reg_mask
;
11426 unsigned long reg_offset
;
11427 unsigned long fpreg_mask
;
11428 unsigned long fpreg_offset
;
11429 unsigned long frame_offset
;
11430 unsigned long frame_reg
;
11431 unsigned long pc_reg
;
11435 static procS cur_proc
;
11436 static procS
*cur_proc_ptr
;
11437 static int numprocs
;
11447 /* check for premature end, nesting errors, etc */
11449 as_warn (_("missing `.end' at end of assembly"));
11458 if (*input_line_pointer
== '-')
11460 ++input_line_pointer
;
11463 if (!isdigit ((unsigned char) *input_line_pointer
))
11464 as_bad (_("Expected simple number."));
11465 if (input_line_pointer
[0] == '0')
11467 if (input_line_pointer
[1] == 'x')
11469 input_line_pointer
+= 2;
11470 while (isxdigit ((unsigned char) *input_line_pointer
))
11473 val
|= hex_value (*input_line_pointer
++);
11475 return negative
? -val
: val
;
11479 ++input_line_pointer
;
11480 while (isdigit ((unsigned char) *input_line_pointer
))
11483 val
|= *input_line_pointer
++ - '0';
11485 return negative
? -val
: val
;
11488 if (!isdigit ((unsigned char) *input_line_pointer
))
11490 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11491 *input_line_pointer
, *input_line_pointer
);
11492 as_warn (_("Invalid number"));
11495 while (isdigit ((unsigned char) *input_line_pointer
))
11498 val
+= *input_line_pointer
++ - '0';
11500 return negative
? -val
: val
;
11503 /* The .file directive; just like the usual .file directive, but there
11504 is an initial number which is the ECOFF file index. */
11512 line
= get_number ();
11517 /* The .end directive. */
11526 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11529 demand_empty_rest_of_line ();
11534 #ifdef BFD_ASSEMBLER
11535 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11540 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11547 as_warn (_(".end not in text section"));
11551 as_warn (_(".end directive without a preceding .ent directive."));
11552 demand_empty_rest_of_line ();
11558 assert (S_GET_NAME (p
));
11559 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11560 as_warn (_(".end symbol does not match .ent symbol."));
11563 as_warn (_(".end directive missing or unknown symbol"));
11565 #ifdef MIPS_STABS_ELF
11567 segT saved_seg
= now_seg
;
11568 subsegT saved_subseg
= now_subseg
;
11569 fragS
*saved_frag
= frag_now
;
11575 dot
= frag_now_fix ();
11577 #ifdef md_flush_pending_output
11578 md_flush_pending_output ();
11582 subseg_set (pdr_seg
, 0);
11584 /* Write the symbol */
11585 exp
.X_op
= O_symbol
;
11586 exp
.X_add_symbol
= p
;
11587 exp
.X_add_number
= 0;
11588 emit_expr (&exp
, 4);
11590 fragp
= frag_more (7*4);
11592 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11593 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11594 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11595 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11596 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11597 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11598 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11600 subseg_set (saved_seg
, saved_subseg
);
11604 cur_proc_ptr
= NULL
;
11607 /* The .aent and .ent directives. */
11617 symbolP
= get_symbol ();
11618 if (*input_line_pointer
== ',')
11619 input_line_pointer
++;
11620 SKIP_WHITESPACE ();
11621 if (isdigit ((unsigned char) *input_line_pointer
)
11622 || *input_line_pointer
== '-')
11623 number
= get_number ();
11625 #ifdef BFD_ASSEMBLER
11626 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11631 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11638 as_warn (_(".ent or .aent not in text section."));
11640 if (!aent
&& cur_proc_ptr
)
11641 as_warn (_("missing `.end'"));
11645 cur_proc_ptr
= &cur_proc
;
11646 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11648 cur_proc_ptr
->isym
= symbolP
;
11650 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11655 demand_empty_rest_of_line ();
11658 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11659 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11660 s_mips_frame is used so that we can set the PDR information correctly.
11661 We can't use the ecoff routines because they make reference to the ecoff
11662 symbol table (in the mdebug section). */
11665 s_mips_frame (ignore
)
11668 #ifdef MIPS_STABS_ELF
11672 if (cur_proc_ptr
== (procS
*) NULL
)
11674 as_warn (_(".frame outside of .ent"));
11675 demand_empty_rest_of_line ();
11679 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11681 SKIP_WHITESPACE ();
11682 if (*input_line_pointer
++ != ','
11683 || get_absolute_expression_and_terminator (&val
) != ',')
11685 as_warn (_("Bad .frame directive"));
11686 --input_line_pointer
;
11687 demand_empty_rest_of_line ();
11691 cur_proc_ptr
->frame_offset
= val
;
11692 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11694 demand_empty_rest_of_line ();
11697 #endif /* MIPS_STABS_ELF */
11700 /* The .fmask and .mask directives. If the mdebug section is present
11701 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11702 embedded targets, s_mips_mask is used so that we can set the PDR
11703 information correctly. We can't use the ecoff routines because they
11704 make reference to the ecoff symbol table (in the mdebug section). */
11707 s_mips_mask (reg_type
)
11710 #ifdef MIPS_STABS_ELF
11713 if (cur_proc_ptr
== (procS
*) NULL
)
11715 as_warn (_(".mask/.fmask outside of .ent"));
11716 demand_empty_rest_of_line ();
11720 if (get_absolute_expression_and_terminator (&mask
) != ',')
11722 as_warn (_("Bad .mask/.fmask directive"));
11723 --input_line_pointer
;
11724 demand_empty_rest_of_line ();
11728 off
= get_absolute_expression ();
11730 if (reg_type
== 'F')
11732 cur_proc_ptr
->fpreg_mask
= mask
;
11733 cur_proc_ptr
->fpreg_offset
= off
;
11737 cur_proc_ptr
->reg_mask
= mask
;
11738 cur_proc_ptr
->reg_offset
= off
;
11741 demand_empty_rest_of_line ();
11743 s_ignore (reg_type
);
11744 #endif /* MIPS_STABS_ELF */
11747 /* The .loc directive. */
11758 assert (now_seg
== text_section
);
11760 lineno
= get_number ();
11761 addroff
= frag_now_fix ();
11763 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11764 S_SET_TYPE (symbolP
, N_SLINE
);
11765 S_SET_OTHER (symbolP
, 0);
11766 S_SET_DESC (symbolP
, lineno
);
11767 symbolP
->sy_segment
= now_seg
;