1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF. */
109 /* The default target format to use. */
111 mips_target_format ()
113 switch (OUTPUT_FLAVOR
)
115 case bfd_target_aout_flavour
:
116 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
117 case bfd_target_ecoff_flavour
:
118 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
119 case bfd_target_elf_flavour
:
120 return (target_big_endian
121 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
122 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
128 /* The name of the readonly data section. */
129 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
131 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
133 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Whether we are assembling for the mips16 processor. 0 if we are
148 not, 1 if we are, and -1 if the value has not been initialized.
149 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
150 -nomips16 command line options, and the default CPU. */
152 /* Non-zero if we should not reorder instructions. Changed by `.set
153 reorder' and `.set noreorder'. */
155 /* Non-zero if we should not permit the $at ($1) register to be used
156 in instructions. Changed by `.set at' and `.set noat'. */
158 /* Non-zero if we should warn when a macro instruction expands into
159 more than one machine instruction. Changed by `.set nomacro' and
161 int warn_about_macros
;
162 /* Non-zero if we should not move instructions. Changed by `.set
163 move', `.set volatile', `.set nomove', and `.set novolatile'. */
165 /* Non-zero if we should not optimize branches by moving the target
166 of the branch into the delay slot. Actually, we don't perform
167 this optimization anyhow. Changed by `.set bopt' and `.set
170 /* Non-zero if we should not autoextend mips16 instructions.
171 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* This is the struct we use to hold the current set of options. Note
176 that we must set the isa and mips16 fields to -1 to indicate that
177 they have not been initialized. */
179 static struct mips_set_options mips_opts
= { -1, -1 };
181 /* These variables are filled in with the masks of registers used.
182 The object format code reads them and puts them in the appropriate
184 unsigned long mips_gprmask
;
185 unsigned long mips_cprmask
[4];
187 /* MIPS ISA we are using for this output file. */
188 static int file_mips_isa
;
190 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
191 static int mips_cpu
= -1;
193 /* Whether the 4650 instructions (mad/madu) are permitted. */
194 static int mips_4650
= -1;
196 /* Whether the 4010 instructions are permitted. */
197 static int mips_4010
= -1;
199 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
200 static int mips_4100
= -1;
202 /* start-sanitize-r5900 */
203 /* Whether Toshiba r5900 instructions are permitted. */
204 static int mips_5900
= -1;
205 /* end-sanitize-r5900 */
207 /* Whether the processor uses hardware interlocks, and thus does not
208 require nops to be inserted. */
209 static int interlocks
= -1;
211 /* As with "interlocks" this is used by hardware that has FP
212 (co-processor) interlocks. */
213 /* Itbl support may require additional care here. */
214 static int cop_interlocks
= -1;
216 /* MIPS PIC level. */
220 /* Do not generate PIC code. */
223 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
224 not sure what it is supposed to do. */
227 /* Generate PIC code as in the SVR4 MIPS ABI. */
230 /* Generate PIC code without using a global offset table: the data
231 segment has a maximum size of 64K, all data references are off
232 the $gp register, and all text references are PC relative. This
233 is used on some embedded systems. */
237 static enum mips_pic_level mips_pic
;
239 /* 1 if we should generate 32 bit offsets from the GP register in
240 SVR4_PIC mode. Currently has no meaning in other modes. */
241 static int mips_big_got
;
243 /* 1 if trap instructions should used for overflow rather than break
245 static int mips_trap
;
247 /* Non-zero if any .set noreorder directives were used. */
249 static int mips_any_noreorder
;
251 /* The size of the small data section. */
252 static int g_switch_value
= 8;
253 /* Whether the -G option was used. */
254 static int g_switch_seen
= 0;
259 /* If we can determine in advance that GP optimization won't be
260 possible, we can skip the relaxation stuff that tries to produce
261 GP-relative references. This makes delay slot optimization work
264 This function can only provide a guess, but it seems to work for
265 gcc output. If it guesses wrong, the only loss should be in
266 efficiency; it shouldn't introduce any bugs.
268 I don't know if a fix is needed for the SVR4_PIC mode. I've only
269 fixed it for the non-PIC mode. KR 95/04/07 */
270 static int nopic_need_relax
PARAMS ((symbolS
*));
272 /* handle of the OPCODE hash table */
273 static struct hash_control
*op_hash
= NULL
;
275 /* The opcode hash table we use for the mips16. */
276 static struct hash_control
*mips16_op_hash
= NULL
;
278 /* This array holds the chars that always start a comment. If the
279 pre-processor is disabled, these aren't very useful */
280 const char comment_chars
[] = "#";
282 /* This array holds the chars that only start a comment at the beginning of
283 a line. If the line seems to have the form '# 123 filename'
284 .line and .file directives will appear in the pre-processed output */
285 /* Note that input_file.c hand checks for '#' at the beginning of the
286 first line of the input file. This is because the compiler outputs
287 #NO_APP at the beginning of its output. */
288 /* Also note that C style comments are always supported. */
289 const char line_comment_chars
[] = "#";
291 /* This array holds machine specific line separator characters. */
292 const char line_separator_chars
[] = "";
294 /* Chars that can be used to separate mant from exp in floating point nums */
295 const char EXP_CHARS
[] = "eE";
297 /* Chars that mean this number is a floating point constant */
300 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
302 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
303 changed in read.c . Ideally it shouldn't have to know about it at all,
304 but nothing is ideal around here.
307 static char *insn_error
;
309 static int auto_align
= 1;
311 /* When outputting SVR4 PIC code, the assembler needs to know the
312 offset in the stack frame from which to restore the $gp register.
313 This is set by the .cprestore pseudo-op, and saved in this
315 static offsetT mips_cprestore_offset
= -1;
317 /* This is the register which holds the stack frame, as set by the
318 .frame pseudo-op. This is needed to implement .cprestore. */
319 static int mips_frame_reg
= SP
;
321 /* To output NOP instructions correctly, we need to keep information
322 about the previous two instructions. */
324 /* Whether we are optimizing. The default value of 2 means to remove
325 unneeded NOPs and swap branch instructions when possible. A value
326 of 1 means to not swap branches. A value of 0 means to always
328 static int mips_optimize
= 2;
330 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
331 equivalent to seeing no -g option at all. */
332 static int mips_debug
= 0;
334 /* The previous instruction. */
335 static struct mips_cl_insn prev_insn
;
337 /* The instruction before prev_insn. */
338 static struct mips_cl_insn prev_prev_insn
;
340 /* If we don't want information for prev_insn or prev_prev_insn, we
341 point the insn_mo field at this dummy integer. */
342 static const struct mips_opcode dummy_opcode
= { 0 };
344 /* Non-zero if prev_insn is valid. */
345 static int prev_insn_valid
;
347 /* The frag for the previous instruction. */
348 static struct frag
*prev_insn_frag
;
350 /* The offset into prev_insn_frag for the previous instruction. */
351 static long prev_insn_where
;
353 /* The reloc type for the previous instruction, if any. */
354 static bfd_reloc_code_real_type prev_insn_reloc_type
;
356 /* The reloc for the previous instruction, if any. */
357 static fixS
*prev_insn_fixp
;
359 /* Non-zero if the previous instruction was in a delay slot. */
360 static int prev_insn_is_delay_slot
;
362 /* Non-zero if the previous instruction was in a .set noreorder. */
363 static int prev_insn_unreordered
;
365 /* Non-zero if the previous instruction uses an extend opcode (if
367 static int prev_insn_extended
;
369 /* Non-zero if the previous previous instruction was in a .set
371 static int prev_prev_insn_unreordered
;
373 /* If this is set, it points to a frag holding nop instructions which
374 were inserted before the start of a noreorder section. If those
375 nops turn out to be unnecessary, the size of the frag can be
377 static fragS
*prev_nop_frag
;
379 /* The number of nop instructions we created in prev_nop_frag. */
380 static int prev_nop_frag_holds
;
382 /* The number of nop instructions that we know we need in
384 static int prev_nop_frag_required
;
386 /* The number of instructions we've seen since prev_nop_frag. */
387 static int prev_nop_frag_since
;
389 /* For ECOFF and ELF, relocations against symbols are done in two
390 parts, with a HI relocation and a LO relocation. Each relocation
391 has only 16 bits of space to store an addend. This means that in
392 order for the linker to handle carries correctly, it must be able
393 to locate both the HI and the LO relocation. This means that the
394 relocations must appear in order in the relocation table.
396 In order to implement this, we keep track of each unmatched HI
397 relocation. We then sort them so that they immediately precede the
398 corresponding LO relocation. */
403 struct mips_hi_fixup
*next
;
406 /* The section this fixup is in. */
410 /* The list of unmatched HI relocs. */
412 static struct mips_hi_fixup
*mips_hi_fixup_list
;
414 /* Map normal MIPS register numbers to mips16 register numbers. */
416 #define X ILLEGAL_REG
417 static const int mips32_to_16_reg_map
[] =
419 X
, X
, 2, 3, 4, 5, 6, 7,
420 X
, X
, X
, X
, X
, X
, X
, X
,
421 0, 1, X
, X
, X
, X
, X
, X
,
422 X
, X
, X
, X
, X
, X
, X
, X
426 /* Map mips16 register numbers to normal MIPS register numbers. */
428 static const int mips16_to_32_reg_map
[] =
430 16, 17, 2, 3, 4, 5, 6, 7
433 /* Since the MIPS does not have multiple forms of PC relative
434 instructions, we do not have to do relaxing as is done on other
435 platforms. However, we do have to handle GP relative addressing
436 correctly, which turns out to be a similar problem.
438 Every macro that refers to a symbol can occur in (at least) two
439 forms, one with GP relative addressing and one without. For
440 example, loading a global variable into a register generally uses
441 a macro instruction like this:
443 If i can be addressed off the GP register (this is true if it is in
444 the .sbss or .sdata section, or if it is known to be smaller than
445 the -G argument) this will generate the following instruction:
447 This instruction will use a GPREL reloc. If i can not be addressed
448 off the GP register, the following instruction sequence will be used:
451 In this case the first instruction will have a HI16 reloc, and the
452 second reloc will have a LO16 reloc. Both relocs will be against
455 The issue here is that we may not know whether i is GP addressable
456 until after we see the instruction that uses it. Therefore, we
457 want to be able to choose the final instruction sequence only at
458 the end of the assembly. This is similar to the way other
459 platforms choose the size of a PC relative instruction only at the
462 When generating position independent code we do not use GP
463 addressing in quite the same way, but the issue still arises as
464 external symbols and local symbols must be handled differently.
466 We handle these issues by actually generating both possible
467 instruction sequences. The longer one is put in a frag_var with
468 type rs_machine_dependent. We encode what to do with the frag in
469 the subtype field. We encode (1) the number of existing bytes to
470 replace, (2) the number of new bytes to use, (3) the offset from
471 the start of the existing bytes to the first reloc we must generate
472 (that is, the offset is applied from the start of the existing
473 bytes after they are replaced by the new bytes, if any), (4) the
474 offset from the start of the existing bytes to the second reloc,
475 (5) whether a third reloc is needed (the third reloc is always four
476 bytes after the second reloc), and (6) whether to warn if this
477 variant is used (this is sometimes needed if .set nomacro or .set
478 noat is in effect). All these numbers are reasonably small.
480 Generating two instruction sequences must be handled carefully to
481 ensure that delay slots are handled correctly. Fortunately, there
482 are a limited number of cases. When the second instruction
483 sequence is generated, append_insn is directed to maintain the
484 existing delay slot information, so it continues to apply to any
485 code after the second instruction sequence. This means that the
486 second instruction sequence must not impose any requirements not
487 required by the first instruction sequence.
489 These variant frags are then handled in functions called by the
490 machine independent code. md_estimate_size_before_relax returns
491 the final size of the frag. md_convert_frag sets up the final form
492 of the frag. tc_gen_reloc adjust the first reloc and adds a second
494 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
498 | (((reloc1) + 64) << 9) \
499 | (((reloc2) + 64) << 2) \
500 | ((reloc3) ? (1 << 1) : 0) \
502 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
503 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
504 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
505 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
506 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
507 #define RELAX_WARN(i) ((i) & 1)
509 /* For mips16 code, we use an entirely different form of relaxation.
510 mips16 supports two versions of most instructions which take
511 immediate values: a small one which takes some small value, and a
512 larger one which takes a 16 bit value. Since branches also follow
513 this pattern, relaxing these values is required.
515 We can assemble both mips16 and normal MIPS code in a single
516 object. Therefore, we need to support this type of relaxation at
517 the same time that we support the relaxation described above. We
518 use the high bit of the subtype field to distinguish these cases.
520 The information we store for this type of relaxation is the
521 argument code found in the opcode file for this relocation, whether
522 the user explicitly requested a small or extended form, and whether
523 the relocation is in a jump or jal delay slot. That tells us the
524 size of the value, and how it should be stored. We also store
525 whether the fragment is considered to be extended or not. We also
526 store whether this is known to be a branch to a different section,
527 whether we have tried to relax this frag yet, and whether we have
528 ever extended a PC relative fragment because of a shift count. */
529 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
532 | ((small) ? 0x100 : 0) \
533 | ((ext) ? 0x200 : 0) \
534 | ((dslot) ? 0x400 : 0) \
535 | ((jal_dslot) ? 0x800 : 0))
536 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
537 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
538 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
539 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
540 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
541 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
542 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
543 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
544 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
545 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
546 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
547 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
549 /* Prototypes for static functions. */
552 #define internalError() \
553 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
555 #define internalError() as_fatal ("MIPS internal Error");
558 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
560 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
561 unsigned int reg
, enum mips_regclass
class));
562 static int reg_needs_delay
PARAMS ((int));
563 static void mips16_mark_labels
PARAMS ((void));
564 static void append_insn
PARAMS ((char *place
,
565 struct mips_cl_insn
* ip
,
567 bfd_reloc_code_real_type r
,
569 static void mips_no_prev_insn
PARAMS ((int));
570 static void mips_emit_delays
PARAMS ((boolean
));
572 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
573 const char *name
, const char *fmt
,
576 static void macro_build ();
578 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
579 const char *, const char *,
581 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
582 expressionS
* ep
, int regnum
));
583 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
584 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
586 static void load_register
PARAMS ((int *, int, expressionS
*, int));
587 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
588 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
589 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
590 #ifdef LOSING_COMPILER
591 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
593 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
594 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
595 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
596 boolean
, boolean
, unsigned long *,
597 boolean
*, unsigned short *));
598 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
599 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
600 static symbolS
*get_symbol
PARAMS ((void));
601 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
602 static void s_align
PARAMS ((int));
603 static void s_change_sec
PARAMS ((int));
604 static void s_cons
PARAMS ((int));
605 static void s_float_cons
PARAMS ((int));
606 static void s_mips_globl
PARAMS ((int));
607 static void s_option
PARAMS ((int));
608 static void s_mipsset
PARAMS ((int));
609 static void s_abicalls
PARAMS ((int));
610 static void s_cpload
PARAMS ((int));
611 static void s_cprestore
PARAMS ((int));
612 static void s_gpword
PARAMS ((int));
613 static void s_cpadd
PARAMS ((int));
614 static void s_insn
PARAMS ((int));
615 static void md_obj_begin
PARAMS ((void));
616 static void md_obj_end
PARAMS ((void));
617 static long get_number
PARAMS ((void));
618 static void s_ent
PARAMS ((int));
619 static void s_mipsend
PARAMS ((int));
620 static void s_file
PARAMS ((int));
621 static void s_mips_stab
PARAMS ((int));
622 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
626 The following pseudo-ops from the Kane and Heinrich MIPS book
627 should be defined here, but are currently unsupported: .alias,
628 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
630 The following pseudo-ops from the Kane and Heinrich MIPS book are
631 specific to the type of debugging information being generated, and
632 should be defined by the object format: .aent, .begin, .bend,
633 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
636 The following pseudo-ops from the Kane and Heinrich MIPS book are
637 not MIPS CPU specific, but are also not specific to the object file
638 format. This file is probably the best place to define them, but
639 they are not currently supported: .asm0, .endr, .lab, .repeat,
640 .struct, .weakext. */
642 static const pseudo_typeS mips_pseudo_table
[] =
644 /* MIPS specific pseudo-ops. */
645 {"option", s_option
, 0},
646 {"set", s_mipsset
, 0},
647 {"rdata", s_change_sec
, 'r'},
648 {"sdata", s_change_sec
, 's'},
649 {"livereg", s_ignore
, 0},
650 {"abicalls", s_abicalls
, 0},
651 {"cpload", s_cpload
, 0},
652 {"cprestore", s_cprestore
, 0},
653 {"gpword", s_gpword
, 0},
654 {"cpadd", s_cpadd
, 0},
657 /* Relatively generic pseudo-ops that happen to be used on MIPS
659 {"asciiz", stringer
, 1},
660 {"bss", s_change_sec
, 'b'},
663 {"dword", s_cons
, 3},
665 /* These pseudo-ops are defined in read.c, but must be overridden
666 here for one reason or another. */
667 {"align", s_align
, 0},
669 {"data", s_change_sec
, 'd'},
670 {"double", s_float_cons
, 'd'},
671 {"float", s_float_cons
, 'f'},
672 {"globl", s_mips_globl
, 0},
673 {"global", s_mips_globl
, 0},
674 {"hword", s_cons
, 1},
679 {"short", s_cons
, 1},
680 {"single", s_float_cons
, 'f'},
681 {"stabn", s_mips_stab
, 'n'},
682 {"text", s_change_sec
, 't'},
687 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
688 /* These pseudo-ops should be defined by the object file format.
689 However, a.out doesn't support them, so we have versions here. */
691 {"bgnb", s_ignore
, 0},
692 {"end", s_mipsend
, 0},
693 {"endb", s_ignore
, 0},
696 {"fmask", s_ignore
, 'F'},
697 {"frame", s_ignore
, 0},
698 {"loc", s_ignore
, 0},
699 {"mask", s_ignore
, 'R'},
700 {"verstamp", s_ignore
, 0},
704 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
709 pop_insert (mips_pseudo_table
);
710 if (! ECOFF_DEBUGGING
)
711 pop_insert (mips_nonecoff_pseudo_table
);
714 /* Symbols labelling the current insn. */
716 struct insn_label_list
718 struct insn_label_list
*next
;
722 static struct insn_label_list
*insn_labels
;
723 static struct insn_label_list
*free_insn_labels
;
725 static void mips_clear_insn_labels
PARAMS ((void));
728 mips_clear_insn_labels ()
730 register struct insn_label_list
**pl
;
732 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
738 static char *expr_end
;
740 /* Expressions which appear in instructions. These are set by
743 static expressionS imm_expr
;
744 static expressionS offset_expr
;
746 /* Relocs associated with imm_expr and offset_expr. */
748 static bfd_reloc_code_real_type imm_reloc
;
749 static bfd_reloc_code_real_type offset_reloc
;
751 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
753 static boolean imm_unmatched_hi
;
755 /* These are set by mips16_ip if an explicit extension is used. */
757 static boolean mips16_small
, mips16_ext
;
760 * This function is called once, at assembler startup time. It should
761 * set up all the tables, etc. that the MD part of the assembler will need.
767 register const char *retval
= NULL
;
768 register unsigned int i
= 0;
770 if (mips_opts
.isa
== -1)
776 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
778 a
= xmalloc (sizeof TARGET_CPU
);
779 strcpy (a
, TARGET_CPU
);
780 a
[(sizeof TARGET_CPU
) - 3] = '\0';
784 if (strcmp (cpu
, "mips") == 0)
790 else if (strcmp (cpu
, "r6000") == 0
791 || strcmp (cpu
, "mips2") == 0)
797 else if (strcmp (cpu
, "mips64") == 0
798 || strcmp (cpu
, "r4000") == 0
799 || strcmp (cpu
, "mips3") == 0)
805 else if (strcmp (cpu
, "r4400") == 0)
811 else if (strcmp (cpu
, "mips64orion") == 0
812 || strcmp (cpu
, "r4600") == 0)
818 else if (strcmp (cpu
, "r4650") == 0)
826 else if (strcmp (cpu
, "mips64vr4300") == 0)
832 else if (strcmp (cpu
, "mips64vr4100") == 0)
840 else if (strcmp (cpu
, "r4010") == 0)
848 else if (strcmp (cpu
, "r5000") == 0
849 || strcmp (cpu
, "mips64vr5000") == 0)
855 /* start-sanitize-r5900 */
856 else if (strcmp (cpu
, "r5900") == 0
857 || strcmp (cpu
, "mips64vr5900") == 0
858 || strcmp (cpu
, "mips64vr5900el") == 0)
866 /* end-sanitize-r5900 */
867 else if (strcmp (cpu
, "r8000") == 0
868 || strcmp (cpu
, "mips4") == 0)
874 else if (strcmp (cpu
, "r10000") == 0)
880 else if (strcmp (cpu
, "mips16") == 0)
884 mips_cpu
= 0; /* FIXME */
897 if (mips_opts
.mips16
< 0)
899 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
900 mips_opts
.mips16
= 1;
902 mips_opts
.mips16
= 0;
914 /* start-sanitize-r5900 */
917 /* end-sanitize-r5900 */
919 if (mips_4010
|| mips_cpu
== 4300)
924 /* Itbl support may require additional care here. */
925 if (mips_cpu
== 4300)
930 if (mips_opts
.isa
< 2 && mips_trap
)
931 as_bad ("trap exception not supported at ISA 1");
933 switch (mips_opts
.isa
)
936 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
939 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
942 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
945 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
949 as_warn ("Could not set architecture and machine");
951 file_mips_isa
= mips_opts
.isa
;
953 op_hash
= hash_new ();
955 for (i
= 0; i
< NUMOPCODES
;)
957 const char *name
= mips_opcodes
[i
].name
;
959 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
962 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
963 mips_opcodes
[i
].name
, retval
);
964 as_fatal ("Broken assembler. No assembly attempted.");
968 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
969 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
970 != mips_opcodes
[i
].match
))
972 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
973 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
974 as_fatal ("Broken assembler. No assembly attempted.");
978 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
981 mips16_op_hash
= hash_new ();
984 while (i
< bfd_mips16_num_opcodes
)
986 const char *name
= mips16_opcodes
[i
].name
;
988 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
990 as_fatal ("internal error: can't hash `%s': %s\n",
991 mips16_opcodes
[i
].name
, retval
);
994 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
995 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
996 != mips16_opcodes
[i
].match
))
997 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
998 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1001 while (i
< bfd_mips16_num_opcodes
1002 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1005 /* We add all the general register names to the symbol table. This
1006 helps us detect invalid uses of them. */
1007 for (i
= 0; i
< 32; i
++)
1011 sprintf (buf
, "$%d", i
);
1012 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1013 &zero_address_frag
));
1015 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1016 &zero_address_frag
));
1017 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1018 &zero_address_frag
));
1019 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1020 &zero_address_frag
));
1021 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1022 &zero_address_frag
));
1023 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1024 &zero_address_frag
));
1025 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1026 &zero_address_frag
));
1027 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1028 &zero_address_frag
));
1030 mips_no_prev_insn (false);
1033 mips_cprmask
[0] = 0;
1034 mips_cprmask
[1] = 0;
1035 mips_cprmask
[2] = 0;
1036 mips_cprmask
[3] = 0;
1038 /* set the default alignment for the text section (2**2) */
1039 record_alignment (text_section
, 2);
1041 if (USE_GLOBAL_POINTER_OPT
)
1042 bfd_set_gp_size (stdoutput
, g_switch_value
);
1044 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1046 /* On a native system, sections must be aligned to 16 byte
1047 boundaries. When configured for an embedded ELF target, we
1049 if (strcmp (TARGET_OS
, "elf") != 0)
1051 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1052 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1053 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1056 /* Create a .reginfo section for register masks and a .mdebug
1057 section for debugging information. */
1065 subseg
= now_subseg
;
1067 /* The ABI says this section should be loaded so that the
1068 running program can access it. However, we don't load it
1069 if we are configured for an embedded target */
1070 flags
= SEC_READONLY
| SEC_DATA
;
1071 if (strcmp (TARGET_OS
, "elf") != 0)
1072 flags
|= SEC_ALLOC
| SEC_LOAD
;
1076 sec
= subseg_new (".reginfo", (subsegT
) 0);
1079 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1080 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1083 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1088 /* The 64-bit ABI uses a .MIPS.options section rather than
1089 .reginfo section. */
1090 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1091 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1092 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1095 /* Set up the option header. */
1097 Elf_Internal_Options opthdr
;
1100 opthdr
.kind
= ODK_REGINFO
;
1101 opthdr
.size
= (sizeof (Elf_External_Options
)
1102 + sizeof (Elf64_External_RegInfo
));
1105 f
= frag_more (sizeof (Elf_External_Options
));
1106 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1107 (Elf_External_Options
*) f
);
1109 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1114 if (ECOFF_DEBUGGING
)
1116 sec
= subseg_new (".mdebug", (subsegT
) 0);
1117 (void) bfd_set_section_flags (stdoutput
, sec
,
1118 SEC_HAS_CONTENTS
| SEC_READONLY
);
1119 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1122 subseg_set (seg
, subseg
);
1126 if (! ECOFF_DEBUGGING
)
1133 if (! ECOFF_DEBUGGING
)
1141 struct mips_cl_insn insn
;
1143 imm_expr
.X_op
= O_absent
;
1144 imm_reloc
= BFD_RELOC_UNUSED
;
1145 imm_unmatched_hi
= false;
1146 offset_expr
.X_op
= O_absent
;
1147 offset_reloc
= BFD_RELOC_UNUSED
;
1149 if (mips_opts
.mips16
)
1150 mips16_ip (str
, &insn
);
1153 mips_ip (str
, &insn
);
1154 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1155 str
, insn
.insn_opcode
));
1160 as_bad ("%s `%s'", insn_error
, str
);
1164 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1166 if (mips_opts
.mips16
)
1167 mips16_macro (&insn
);
1173 if (imm_expr
.X_op
!= O_absent
)
1174 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1176 else if (offset_expr
.X_op
!= O_absent
)
1177 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1179 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1183 /* See whether instruction IP reads register REG. CLASS is the type
1187 insn_uses_reg (ip
, reg
, class)
1188 struct mips_cl_insn
*ip
;
1190 enum mips_regclass
class;
1192 if (class == MIPS16_REG
)
1194 assert (mips_opts
.mips16
);
1195 reg
= mips16_to_32_reg_map
[reg
];
1196 class = MIPS_GR_REG
;
1199 /* Don't report on general register 0, since it never changes. */
1200 if (class == MIPS_GR_REG
&& reg
== 0)
1203 if (class == MIPS_FP_REG
)
1205 assert (! mips_opts
.mips16
);
1206 /* If we are called with either $f0 or $f1, we must check $f0.
1207 This is not optimal, because it will introduce an unnecessary
1208 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1209 need to distinguish reading both $f0 and $f1 or just one of
1210 them. Note that we don't have to check the other way,
1211 because there is no instruction that sets both $f0 and $f1
1212 and requires a delay. */
1213 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1214 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1215 == (reg
&~ (unsigned) 1)))
1217 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1218 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1219 == (reg
&~ (unsigned) 1)))
1222 else if (! mips_opts
.mips16
)
1224 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1225 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1227 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1228 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1233 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1234 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1235 & MIPS16OP_MASK_RX
)]
1238 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1239 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1240 & MIPS16OP_MASK_RY
)]
1243 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1244 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1245 & MIPS16OP_MASK_MOVE32Z
)]
1248 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1250 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1252 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1254 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1255 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1256 & MIPS16OP_MASK_REGR32
) == reg
)
1263 /* This function returns true if modifying a register requires a
1267 reg_needs_delay (reg
)
1270 unsigned long prev_pinfo
;
1272 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1273 if (! mips_opts
.noreorder
1274 && mips_opts
.isa
< 4
1275 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1276 || (mips_opts
.isa
< 2
1277 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1279 /* A load from a coprocessor or from memory. All load
1280 delays delay the use of general register rt for one
1281 instruction on the r3000. The r6000 and r4000 use
1283 /* Itbl support may require additional care here. */
1284 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1285 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1292 /* Mark instruction labels in mips16 mode. This permits the linker to
1293 handle them specially, such as generating jalx instructions when
1294 needed. We also make them odd for the duration of the assembly, in
1295 order to generate the right sort of code. We will make them even
1296 in the adjust_symtab routine, while leaving them marked. This is
1297 convenient for the debugger and the disassembler. The linker knows
1298 to make them odd again. */
1301 mips16_mark_labels ()
1303 if (mips_opts
.mips16
)
1305 struct insn_label_list
*l
;
1307 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1310 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1311 S_SET_OTHER (l
->label
, STO_MIPS16
);
1313 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1314 ++l
->label
->sy_value
.X_add_number
;
1319 /* Output an instruction. PLACE is where to put the instruction; if
1320 it is NULL, this uses frag_more to get room. IP is the instruction
1321 information. ADDRESS_EXPR is an operand of the instruction to be
1322 used with RELOC_TYPE. */
1325 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1327 struct mips_cl_insn
*ip
;
1328 expressionS
*address_expr
;
1329 bfd_reloc_code_real_type reloc_type
;
1330 boolean unmatched_hi
;
1332 register unsigned long prev_pinfo
, pinfo
;
1337 /* Mark instruction labels in mips16 mode. */
1338 if (mips_opts
.mips16
)
1339 mips16_mark_labels ();
1341 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1342 pinfo
= ip
->insn_mo
->pinfo
;
1344 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1348 /* If the previous insn required any delay slots, see if we need
1349 to insert a NOP or two. There are eight kinds of possible
1350 hazards, of which an instruction can have at most one type.
1351 (1) a load from memory delay
1352 (2) a load from a coprocessor delay
1353 (3) an unconditional branch delay
1354 (4) a conditional branch delay
1355 (5) a move to coprocessor register delay
1356 (6) a load coprocessor register from memory delay
1357 (7) a coprocessor condition code delay
1358 (8) a HI/LO special register delay
1360 There are a lot of optimizations we could do that we don't.
1361 In particular, we do not, in general, reorder instructions.
1362 If you use gcc with optimization, it will reorder
1363 instructions and generally do much more optimization then we
1364 do here; repeating all that work in the assembler would only
1365 benefit hand written assembly code, and does not seem worth
1368 /* This is how a NOP is emitted. */
1369 #define emit_nop() \
1371 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1372 : md_number_to_chars (frag_more (4), 0, 4))
1374 /* The previous insn might require a delay slot, depending upon
1375 the contents of the current insn. */
1376 if (! mips_opts
.mips16
1377 && mips_opts
.isa
< 4
1378 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1379 && ! cop_interlocks
)
1380 || (mips_opts
.isa
< 2
1381 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1383 /* A load from a coprocessor or from memory. All load
1384 delays delay the use of general register rt for one
1385 instruction on the r3000. The r6000 and r4000 use
1387 /* Itbl support may require additional care here. */
1388 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1389 if (mips_optimize
== 0
1390 || insn_uses_reg (ip
,
1391 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1396 else if (! mips_opts
.mips16
1397 && mips_opts
.isa
< 4
1398 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1399 && ! cop_interlocks
)
1400 || (mips_opts
.isa
< 2
1401 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1403 /* A generic coprocessor delay. The previous instruction
1404 modified a coprocessor general or control register. If
1405 it modified a control register, we need to avoid any
1406 coprocessor instruction (this is probably not always
1407 required, but it sometimes is). If it modified a general
1408 register, we avoid using that register.
1410 On the r6000 and r4000 loading a coprocessor register
1411 from memory is interlocked, and does not require a delay.
1413 This case is not handled very well. There is no special
1414 knowledge of CP0 handling, and the coprocessors other
1415 than the floating point unit are not distinguished at
1417 /* Itbl support may require additional care here. FIXME!
1418 Need to modify this to include knowledge about
1419 user specified delays! */
1420 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1422 if (mips_optimize
== 0
1423 || insn_uses_reg (ip
,
1424 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1429 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1431 if (mips_optimize
== 0
1432 || insn_uses_reg (ip
,
1433 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1440 /* We don't know exactly what the previous instruction
1441 does. If the current instruction uses a coprocessor
1442 register, we must insert a NOP. If previous
1443 instruction may set the condition codes, and the
1444 current instruction uses them, we must insert two
1446 /* Itbl support may require additional care here. */
1447 if (mips_optimize
== 0
1448 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1449 && (pinfo
& INSN_READ_COND_CODE
)))
1451 else if (pinfo
& INSN_COP
)
1455 else if (! mips_opts
.mips16
1456 && mips_opts
.isa
< 4
1457 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1458 && ! cop_interlocks
)
1460 /* The previous instruction sets the coprocessor condition
1461 codes, but does not require a general coprocessor delay
1462 (this means it is a floating point comparison
1463 instruction). If this instruction uses the condition
1464 codes, we need to insert a single NOP. */
1465 /* Itbl support may require additional care here. */
1466 if (mips_optimize
== 0
1467 || (pinfo
& INSN_READ_COND_CODE
))
1470 else if (prev_pinfo
& INSN_READ_LO
)
1472 /* The previous instruction reads the LO register; if the
1473 current instruction writes to the LO register, we must
1474 insert two NOPS. Some newer processors have interlocks. */
1476 && (mips_optimize
== 0
1477 || (pinfo
& INSN_WRITE_LO
)))
1480 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1482 /* The previous instruction reads the HI register; if the
1483 current instruction writes to the HI register, we must
1484 insert a NOP. Some newer processors have interlocks. */
1486 && (mips_optimize
== 0
1487 || (pinfo
& INSN_WRITE_HI
)))
1491 /* If the previous instruction was in a noreorder section, then
1492 we don't want to insert the nop after all. */
1493 /* Itbl support may require additional care here. */
1494 if (prev_insn_unreordered
)
1497 /* There are two cases which require two intervening
1498 instructions: 1) setting the condition codes using a move to
1499 coprocessor instruction which requires a general coprocessor
1500 delay and then reading the condition codes 2) reading the HI
1501 or LO register and then writing to it (except on processors
1502 which have interlocks). If we are not already emitting a NOP
1503 instruction, we must check for these cases compared to the
1504 instruction previous to the previous instruction. */
1505 if ((! mips_opts
.mips16
1506 && mips_opts
.isa
< 4
1507 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1508 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1509 && (pinfo
& INSN_READ_COND_CODE
)
1510 && ! cop_interlocks
)
1511 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1512 && (pinfo
& INSN_WRITE_LO
)
1514 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1515 && (pinfo
& INSN_WRITE_HI
)
1521 if (prev_prev_insn_unreordered
)
1524 if (prev_prev_nop
&& nops
== 0)
1527 /* If we are being given a nop instruction, don't bother with
1528 one of the nops we would otherwise output. This will only
1529 happen when a nop instruction is used with mips_optimize set
1532 && ! mips_opts
.noreorder
1533 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1536 /* Now emit the right number of NOP instructions. */
1537 if (nops
> 0 && ! mips_opts
.noreorder
)
1540 unsigned long old_frag_offset
;
1542 struct insn_label_list
*l
;
1544 old_frag
= frag_now
;
1545 old_frag_offset
= frag_now_fix ();
1547 for (i
= 0; i
< nops
; i
++)
1552 listing_prev_line ();
1553 /* We may be at the start of a variant frag. In case we
1554 are, make sure there is enough space for the frag
1555 after the frags created by listing_prev_line. The
1556 argument to frag_grow here must be at least as large
1557 as the argument to all other calls to frag_grow in
1558 this file. We don't have to worry about being in the
1559 middle of a variant frag, because the variants insert
1560 all needed nop instructions themselves. */
1564 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1566 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1567 l
->label
->sy_frag
= frag_now
;
1568 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1569 /* mips16 text labels are stored as odd. */
1570 if (mips_opts
.mips16
)
1571 ++l
->label
->sy_value
.X_add_number
;
1574 #ifndef NO_ECOFF_DEBUGGING
1575 if (ECOFF_DEBUGGING
)
1576 ecoff_fix_loc (old_frag
, old_frag_offset
);
1579 else if (prev_nop_frag
!= NULL
)
1581 /* We have a frag holding nops we may be able to remove. If
1582 we don't need any nops, we can decrease the size of
1583 prev_nop_frag by the size of one instruction. If we do
1584 need some nops, we count them in prev_nops_required. */
1585 if (prev_nop_frag_since
== 0)
1589 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1590 --prev_nop_frag_holds
;
1593 prev_nop_frag_required
+= nops
;
1597 if (prev_prev_nop
== 0)
1599 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1600 --prev_nop_frag_holds
;
1603 ++prev_nop_frag_required
;
1606 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1607 prev_nop_frag
= NULL
;
1609 ++prev_nop_frag_since
;
1611 /* Sanity check: by the time we reach the second instruction
1612 after prev_nop_frag, we should have used up all the nops
1613 one way or another. */
1614 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1618 if (reloc_type
> BFD_RELOC_UNUSED
)
1620 /* We need to set up a variant frag. */
1621 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1622 f
= frag_var (rs_machine_dependent
, 4, 0,
1623 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1624 mips16_small
, mips16_ext
,
1626 & INSN_UNCOND_BRANCH_DELAY
),
1627 (prev_insn_reloc_type
1628 == BFD_RELOC_MIPS16_JMP
)),
1629 make_expr_symbol (address_expr
), (offsetT
) 0,
1632 else if (place
!= NULL
)
1634 else if (mips_opts
.mips16
1636 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1638 /* Make sure there is enough room to swap this instruction with
1639 a following jump instruction. */
1645 if (mips_opts
.mips16
1646 && mips_opts
.noreorder
1647 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1648 as_warn ("extended instruction in delay slot");
1654 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1656 if (address_expr
->X_op
== O_constant
)
1661 ip
->insn_opcode
|= address_expr
->X_add_number
;
1664 case BFD_RELOC_LO16
:
1665 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1668 case BFD_RELOC_MIPS_JMP
:
1669 if ((address_expr
->X_add_number
& 3) != 0)
1670 as_bad ("jump to misaligned address (0x%lx)",
1671 (unsigned long) address_expr
->X_add_number
);
1672 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1675 case BFD_RELOC_MIPS16_JMP
:
1676 if ((address_expr
->X_add_number
& 3) != 0)
1677 as_bad ("jump to misaligned address (0x%lx)",
1678 (unsigned long) address_expr
->X_add_number
);
1680 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1681 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1682 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1685 case BFD_RELOC_16_PCREL_S2
:
1695 /* Don't generate a reloc if we are writing into a variant
1699 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1701 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1705 struct mips_hi_fixup
*hi_fixup
;
1707 assert (reloc_type
== BFD_RELOC_HI16_S
);
1708 hi_fixup
= ((struct mips_hi_fixup
*)
1709 xmalloc (sizeof (struct mips_hi_fixup
)));
1710 hi_fixup
->fixp
= fixp
;
1711 hi_fixup
->seg
= now_seg
;
1712 hi_fixup
->next
= mips_hi_fixup_list
;
1713 mips_hi_fixup_list
= hi_fixup
;
1719 if (! mips_opts
.mips16
)
1720 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1721 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1723 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1724 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1730 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1733 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1736 /* Update the register mask information. */
1737 if (! mips_opts
.mips16
)
1739 if (pinfo
& INSN_WRITE_GPR_D
)
1740 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1741 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1742 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1743 if (pinfo
& INSN_READ_GPR_S
)
1744 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1745 if (pinfo
& INSN_WRITE_GPR_31
)
1746 mips_gprmask
|= 1 << 31;
1747 if (pinfo
& INSN_WRITE_FPR_D
)
1748 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1749 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1750 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1751 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1752 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1753 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1754 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1755 if (pinfo
& INSN_COP
)
1757 /* We don't keep enough information to sort these cases out.
1758 The itbl support does keep this information however, although
1759 we currently don't support itbl fprmats as part of the cop
1760 instruction. May want to add this support in the future. */
1762 /* Never set the bit for $0, which is always zero. */
1763 mips_gprmask
&=~ 1 << 0;
1767 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1768 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1769 & MIPS16OP_MASK_RX
);
1770 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1771 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1772 & MIPS16OP_MASK_RY
);
1773 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1774 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1775 & MIPS16OP_MASK_RZ
);
1776 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1777 mips_gprmask
|= 1 << TREG
;
1778 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1779 mips_gprmask
|= 1 << SP
;
1780 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1781 mips_gprmask
|= 1 << RA
;
1782 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1783 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1784 if (pinfo
& MIPS16_INSN_READ_Z
)
1785 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1786 & MIPS16OP_MASK_MOVE32Z
);
1787 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1788 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1789 & MIPS16OP_MASK_REGR32
);
1792 if (place
== NULL
&& ! mips_opts
.noreorder
)
1794 /* Filling the branch delay slot is more complex. We try to
1795 switch the branch with the previous instruction, which we can
1796 do if the previous instruction does not set up a condition
1797 that the branch tests and if the branch is not itself the
1798 target of any branch. */
1799 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1800 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1802 if (mips_optimize
< 2
1803 /* If we have seen .set volatile or .set nomove, don't
1805 || mips_opts
.nomove
!= 0
1806 /* If we had to emit any NOP instructions, then we
1807 already know we can not swap. */
1809 /* If we don't even know the previous insn, we can not
1811 || ! prev_insn_valid
1812 /* If the previous insn is already in a branch delay
1813 slot, then we can not swap. */
1814 || prev_insn_is_delay_slot
1815 /* If the previous previous insn was in a .set
1816 noreorder, we can't swap. Actually, the MIPS
1817 assembler will swap in this situation. However, gcc
1818 configured -with-gnu-as will generate code like
1824 in which we can not swap the bne and INSN. If gcc is
1825 not configured -with-gnu-as, it does not output the
1826 .set pseudo-ops. We don't have to check
1827 prev_insn_unreordered, because prev_insn_valid will
1828 be 0 in that case. We don't want to use
1829 prev_prev_insn_valid, because we do want to be able
1830 to swap at the start of a function. */
1831 || prev_prev_insn_unreordered
1832 /* If the branch is itself the target of a branch, we
1833 can not swap. We cheat on this; all we check for is
1834 whether there is a label on this instruction. If
1835 there are any branches to anything other than a
1836 label, users must use .set noreorder. */
1837 || insn_labels
!= NULL
1838 /* If the previous instruction is in a variant frag, we
1839 can not do the swap. This does not apply to the
1840 mips16, which uses variant frags for different
1842 || (! mips_opts
.mips16
1843 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1844 /* If the branch reads the condition codes, we don't
1845 even try to swap, because in the sequence
1850 we can not swap, and I don't feel like handling that
1852 || (! mips_opts
.mips16
1853 && mips_opts
.isa
< 4
1854 && (pinfo
& INSN_READ_COND_CODE
))
1855 /* We can not swap with an instruction that requires a
1856 delay slot, becase the target of the branch might
1857 interfere with that instruction. */
1858 || (! mips_opts
.mips16
1859 && mips_opts
.isa
< 4
1861 /* Itbl support may require additional care here. */
1862 & (INSN_LOAD_COPROC_DELAY
1863 | INSN_COPROC_MOVE_DELAY
1864 | INSN_WRITE_COND_CODE
)))
1869 || (! mips_opts
.mips16
1870 && mips_opts
.isa
< 2
1872 & (INSN_LOAD_MEMORY_DELAY
1873 /* Itbl support may require additional care here. */
1874 | INSN_COPROC_MEMORY_DELAY
)))
1875 /* We can not swap with a branch instruction. */
1877 & (INSN_UNCOND_BRANCH_DELAY
1878 | INSN_COND_BRANCH_DELAY
1879 | INSN_COND_BRANCH_LIKELY
))
1880 /* We do not swap with a trap instruction, since it
1881 complicates trap handlers to have the trap
1882 instruction be in a delay slot. */
1883 || (prev_pinfo
& INSN_TRAP
)
1884 /* If the branch reads a register that the previous
1885 instruction sets, we can not swap. */
1886 || (! mips_opts
.mips16
1887 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1888 && insn_uses_reg (ip
,
1889 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1892 || (! mips_opts
.mips16
1893 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1894 && insn_uses_reg (ip
,
1895 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1898 || (mips_opts
.mips16
1899 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1900 && insn_uses_reg (ip
,
1901 ((prev_insn
.insn_opcode
1903 & MIPS16OP_MASK_RX
),
1905 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1906 && insn_uses_reg (ip
,
1907 ((prev_insn
.insn_opcode
1909 & MIPS16OP_MASK_RY
),
1911 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1912 && insn_uses_reg (ip
,
1913 ((prev_insn
.insn_opcode
1915 & MIPS16OP_MASK_RZ
),
1917 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1918 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1919 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1920 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1921 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1922 && insn_uses_reg (ip
,
1923 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1926 /* If the branch writes a register that the previous
1927 instruction sets, we can not swap (we know that
1928 branches write only to RD or to $31). */
1929 || (! mips_opts
.mips16
1930 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1931 && (((pinfo
& INSN_WRITE_GPR_D
)
1932 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1933 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1934 || ((pinfo
& INSN_WRITE_GPR_31
)
1935 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1938 || (! mips_opts
.mips16
1939 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1940 && (((pinfo
& INSN_WRITE_GPR_D
)
1941 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1942 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1943 || ((pinfo
& INSN_WRITE_GPR_31
)
1944 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1947 || (mips_opts
.mips16
1948 && (pinfo
& MIPS16_INSN_WRITE_31
)
1949 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1950 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1951 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1953 /* If the branch writes a register that the previous
1954 instruction reads, we can not swap (we know that
1955 branches only write to RD or to $31). */
1956 || (! mips_opts
.mips16
1957 && (pinfo
& INSN_WRITE_GPR_D
)
1958 && insn_uses_reg (&prev_insn
,
1959 ((ip
->insn_opcode
>> OP_SH_RD
)
1962 || (! mips_opts
.mips16
1963 && (pinfo
& INSN_WRITE_GPR_31
)
1964 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1965 || (mips_opts
.mips16
1966 && (pinfo
& MIPS16_INSN_WRITE_31
)
1967 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1968 /* If we are generating embedded PIC code, the branch
1969 might be expanded into a sequence which uses $at, so
1970 we can't swap with an instruction which reads it. */
1971 || (mips_pic
== EMBEDDED_PIC
1972 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1973 /* If the previous previous instruction has a load
1974 delay, and sets a register that the branch reads, we
1976 || (! mips_opts
.mips16
1977 && mips_opts
.isa
< 4
1978 /* Itbl support may require additional care here. */
1979 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1980 || (mips_opts
.isa
< 2
1981 && (prev_prev_insn
.insn_mo
->pinfo
1982 & INSN_LOAD_MEMORY_DELAY
)))
1983 && insn_uses_reg (ip
,
1984 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1987 /* If one instruction sets a condition code and the
1988 other one uses a condition code, we can not swap. */
1989 || ((pinfo
& INSN_READ_COND_CODE
)
1990 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1991 || ((pinfo
& INSN_WRITE_COND_CODE
)
1992 && (prev_pinfo
& INSN_READ_COND_CODE
))
1993 /* If the previous instruction uses the PC, we can not
1995 || (mips_opts
.mips16
1996 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1997 /* If the previous instruction was extended, we can not
1999 || (mips_opts
.mips16
&& prev_insn_extended
)
2000 /* If the previous instruction had a fixup in mips16
2001 mode, we can not swap. This normally means that the
2002 previous instruction was a 4 byte branch anyhow. */
2003 || (mips_opts
.mips16
&& prev_insn_fixp
))
2005 /* We could do even better for unconditional branches to
2006 portions of this object file; we could pick up the
2007 instruction at the destination, put it in the delay
2008 slot, and bump the destination address. */
2010 /* Update the previous insn information. */
2011 prev_prev_insn
= *ip
;
2012 prev_insn
.insn_mo
= &dummy_opcode
;
2016 /* It looks like we can actually do the swap. */
2017 if (! mips_opts
.mips16
)
2022 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2023 memcpy (temp
, prev_f
, 4);
2024 memcpy (prev_f
, f
, 4);
2025 memcpy (f
, temp
, 4);
2028 prev_insn_fixp
->fx_frag
= frag_now
;
2029 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2033 fixp
->fx_frag
= prev_insn_frag
;
2034 fixp
->fx_where
= prev_insn_where
;
2042 assert (prev_insn_fixp
== NULL
);
2043 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2044 memcpy (temp
, prev_f
, 2);
2045 memcpy (prev_f
, f
, 2);
2046 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2048 assert (reloc_type
== BFD_RELOC_UNUSED
);
2049 memcpy (f
, temp
, 2);
2053 memcpy (f
, f
+ 2, 2);
2054 memcpy (f
+ 2, temp
, 2);
2058 fixp
->fx_frag
= prev_insn_frag
;
2059 fixp
->fx_where
= prev_insn_where
;
2063 /* Update the previous insn information; leave prev_insn
2065 prev_prev_insn
= *ip
;
2067 prev_insn_is_delay_slot
= 1;
2069 /* If that was an unconditional branch, forget the previous
2070 insn information. */
2071 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2073 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2074 prev_insn
.insn_mo
= &dummy_opcode
;
2077 prev_insn_fixp
= NULL
;
2078 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2079 prev_insn_extended
= 0;
2081 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2083 /* We don't yet optimize a branch likely. What we should do
2084 is look at the target, copy the instruction found there
2085 into the delay slot, and increment the branch to jump to
2086 the next instruction. */
2088 /* Update the previous insn information. */
2089 prev_prev_insn
= *ip
;
2090 prev_insn
.insn_mo
= &dummy_opcode
;
2091 prev_insn_fixp
= NULL
;
2092 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2093 prev_insn_extended
= 0;
2097 /* Update the previous insn information. */
2099 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2101 prev_prev_insn
= prev_insn
;
2104 /* Any time we see a branch, we always fill the delay slot
2105 immediately; since this insn is not a branch, we know it
2106 is not in a delay slot. */
2107 prev_insn_is_delay_slot
= 0;
2109 prev_insn_fixp
= fixp
;
2110 prev_insn_reloc_type
= reloc_type
;
2111 if (mips_opts
.mips16
)
2112 prev_insn_extended
= (ip
->use_extend
2113 || reloc_type
> BFD_RELOC_UNUSED
);
2116 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2117 prev_insn_unreordered
= 0;
2118 prev_insn_frag
= frag_now
;
2119 prev_insn_where
= f
- frag_now
->fr_literal
;
2120 prev_insn_valid
= 1;
2122 else if (place
== NULL
)
2124 /* We need to record a bit of information even when we are not
2125 reordering, in order to determine the base address for mips16
2126 PC relative relocs. */
2127 prev_prev_insn
= prev_insn
;
2129 prev_insn_reloc_type
= reloc_type
;
2130 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2131 prev_insn_unreordered
= 1;
2134 /* We just output an insn, so the next one doesn't have a label. */
2135 mips_clear_insn_labels ();
2138 /* This function forgets that there was any previous instruction or
2139 label. If PRESERVE is non-zero, it remembers enough information to
2140 know whether nops are needed before a noreorder section. */
2143 mips_no_prev_insn (preserve
)
2148 prev_insn
.insn_mo
= &dummy_opcode
;
2149 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2150 prev_nop_frag
= NULL
;
2151 prev_nop_frag_holds
= 0;
2152 prev_nop_frag_required
= 0;
2153 prev_nop_frag_since
= 0;
2155 prev_insn_valid
= 0;
2156 prev_insn_is_delay_slot
= 0;
2157 prev_insn_unreordered
= 0;
2158 prev_insn_extended
= 0;
2159 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2160 prev_prev_insn_unreordered
= 0;
2161 mips_clear_insn_labels ();
2164 /* This function must be called whenever we turn on noreorder or emit
2165 something other than instructions. It inserts any NOPS which might
2166 be needed by the previous instruction, and clears the information
2167 kept for the previous instructions. The INSNS parameter is true if
2168 instructions are to follow. */
2171 mips_emit_delays (insns
)
2174 if (! mips_opts
.noreorder
)
2179 if ((! mips_opts
.mips16
2180 && mips_opts
.isa
< 4
2181 && (! cop_interlocks
2182 && (prev_insn
.insn_mo
->pinfo
2183 & (INSN_LOAD_COPROC_DELAY
2184 | INSN_COPROC_MOVE_DELAY
2185 | INSN_WRITE_COND_CODE
))))
2187 && (prev_insn
.insn_mo
->pinfo
2190 || (! mips_opts
.mips16
2191 && mips_opts
.isa
< 2
2192 && (prev_insn
.insn_mo
->pinfo
2193 & (INSN_LOAD_MEMORY_DELAY
2194 | INSN_COPROC_MEMORY_DELAY
))))
2196 /* Itbl support may require additional care here. */
2198 if ((! mips_opts
.mips16
2199 && mips_opts
.isa
< 4
2200 && (! cop_interlocks
2201 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2203 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2204 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2207 if (prev_insn_unreordered
)
2210 else if ((! mips_opts
.mips16
2211 && mips_opts
.isa
< 4
2212 && (! cop_interlocks
2213 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2215 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2216 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2218 /* Itbl support may require additional care here. */
2219 if (! prev_prev_insn_unreordered
)
2225 struct insn_label_list
*l
;
2229 /* Record the frag which holds the nop instructions, so
2230 that we can remove them if we don't need them. */
2231 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2232 prev_nop_frag
= frag_now
;
2233 prev_nop_frag_holds
= nops
;
2234 prev_nop_frag_required
= 0;
2235 prev_nop_frag_since
= 0;
2238 for (; nops
> 0; --nops
)
2243 /* Move on to a new frag, so that it is safe to simply
2244 decrease the size of prev_nop_frag. */
2245 frag_wane (frag_now
);
2249 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2251 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2252 l
->label
->sy_frag
= frag_now
;
2253 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2254 /* mips16 text labels are stored as odd. */
2255 if (mips_opts
.mips16
)
2256 ++l
->label
->sy_value
.X_add_number
;
2261 /* Mark instruction labels in mips16 mode. */
2262 if (mips_opts
.mips16
&& insns
)
2263 mips16_mark_labels ();
2265 mips_no_prev_insn (insns
);
2268 /* Build an instruction created by a macro expansion. This is passed
2269 a pointer to the count of instructions created so far, an
2270 expression, the name of the instruction to build, an operand format
2271 string, and corresponding arguments. */
2275 macro_build (char *place
,
2283 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2292 struct mips_cl_insn insn
;
2293 bfd_reloc_code_real_type r
;
2297 va_start (args
, fmt
);
2303 * If the macro is about to expand into a second instruction,
2304 * print a warning if needed. We need to pass ip as a parameter
2305 * to generate a better warning message here...
2307 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2308 as_warn ("Macro instruction expanded into multiple instructions");
2311 *counter
+= 1; /* bump instruction counter */
2313 if (mips_opts
.mips16
)
2315 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2320 r
= BFD_RELOC_UNUSED
;
2321 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2322 assert (insn
.insn_mo
);
2323 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2325 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2326 || insn
.insn_mo
->pinfo
== INSN_MACRO
2327 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2328 && mips_opts
.isa
< 2)
2329 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2330 && mips_opts
.isa
< 3)
2331 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2332 && mips_opts
.isa
< 4)
2333 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2335 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2337 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2339 /* start-sanitize-r5900 */
2340 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2342 /* end-sanitize-r5900 */
2346 assert (insn
.insn_mo
->name
);
2347 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2349 insn
.insn_opcode
= insn
.insn_mo
->match
;
2365 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2371 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2376 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2381 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2388 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2392 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2396 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2403 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2409 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2410 assert (r
== BFD_RELOC_MIPS_GPREL
2411 || r
== BFD_RELOC_MIPS_LITERAL
2412 || r
== BFD_RELOC_LO16
2413 || r
== BFD_RELOC_MIPS_GOT16
2414 || r
== BFD_RELOC_MIPS_CALL16
2415 || r
== BFD_RELOC_MIPS_GOT_LO16
2416 || r
== BFD_RELOC_MIPS_CALL_LO16
2417 || (ep
->X_op
== O_subtract
2418 && now_seg
== text_section
2419 && r
== BFD_RELOC_PCREL_LO16
));
2423 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2425 && (ep
->X_op
== O_constant
2426 || (ep
->X_op
== O_symbol
2427 && (r
== BFD_RELOC_HI16_S
2428 || r
== BFD_RELOC_HI16
2429 || r
== BFD_RELOC_MIPS_GOT_HI16
2430 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2431 || (ep
->X_op
== O_subtract
2432 && now_seg
== text_section
2433 && r
== BFD_RELOC_PCREL_HI16_S
)));
2434 if (ep
->X_op
== O_constant
)
2436 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2438 r
= BFD_RELOC_UNUSED
;
2443 assert (ep
!= NULL
);
2445 * This allows macro() to pass an immediate expression for
2446 * creating short branches without creating a symbol.
2447 * Note that the expression still might come from the assembly
2448 * input, in which case the value is not checked for range nor
2449 * is a relocation entry generated (yuck).
2451 if (ep
->X_op
== O_constant
)
2453 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2457 r
= BFD_RELOC_16_PCREL_S2
;
2461 assert (ep
!= NULL
);
2462 r
= BFD_RELOC_MIPS_JMP
;
2471 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2473 append_insn (place
, &insn
, ep
, r
, false);
2477 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2485 struct mips_cl_insn insn
;
2486 bfd_reloc_code_real_type r
;
2488 r
= BFD_RELOC_UNUSED
;
2489 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2490 assert (insn
.insn_mo
);
2491 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2493 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2494 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2497 assert (insn
.insn_mo
->name
);
2498 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2501 insn
.insn_opcode
= insn
.insn_mo
->match
;
2502 insn
.use_extend
= false;
2521 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2526 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2530 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2534 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2544 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2551 regno
= va_arg (args
, int);
2552 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2553 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2574 assert (ep
!= NULL
);
2576 if (ep
->X_op
!= O_constant
)
2577 r
= BFD_RELOC_UNUSED
+ c
;
2580 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2581 false, false, &insn
.insn_opcode
,
2582 &insn
.use_extend
, &insn
.extend
);
2584 r
= BFD_RELOC_UNUSED
;
2590 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2597 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2599 append_insn (place
, &insn
, ep
, r
, false);
2603 * Generate a "lui" instruction.
2606 macro_build_lui (place
, counter
, ep
, regnum
)
2612 expressionS high_expr
;
2613 struct mips_cl_insn insn
;
2614 bfd_reloc_code_real_type r
;
2615 CONST
char *name
= "lui";
2616 CONST
char *fmt
= "t,u";
2618 assert (! mips_opts
.mips16
);
2624 high_expr
.X_op
= O_constant
;
2625 high_expr
.X_add_number
= ep
->X_add_number
;
2628 if (high_expr
.X_op
== O_constant
)
2630 /* we can compute the instruction now without a relocation entry */
2631 if (high_expr
.X_add_number
& 0x8000)
2632 high_expr
.X_add_number
+= 0x10000;
2633 high_expr
.X_add_number
=
2634 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2635 r
= BFD_RELOC_UNUSED
;
2639 assert (ep
->X_op
== O_symbol
);
2640 /* _gp_disp is a special case, used from s_cpload. */
2641 assert (mips_pic
== NO_PIC
2642 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2643 r
= BFD_RELOC_HI16_S
;
2647 * If the macro is about to expand into a second instruction,
2648 * print a warning if needed. We need to pass ip as a parameter
2649 * to generate a better warning message here...
2651 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2652 as_warn ("Macro instruction expanded into multiple instructions");
2655 *counter
+= 1; /* bump instruction counter */
2657 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2658 assert (insn
.insn_mo
);
2659 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2660 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2662 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2663 if (r
== BFD_RELOC_UNUSED
)
2665 insn
.insn_opcode
|= high_expr
.X_add_number
;
2666 append_insn (place
, &insn
, NULL
, r
, false);
2669 append_insn (place
, &insn
, &high_expr
, r
, false);
2673 * Generates code to set the $at register to true (one)
2674 * if reg is less than the immediate expression.
2677 set_at (counter
, reg
, unsignedp
)
2682 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2683 macro_build ((char *) NULL
, counter
, &imm_expr
,
2684 unsignedp
? "sltiu" : "slti",
2685 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2688 load_register (counter
, AT
, &imm_expr
, 0);
2689 macro_build ((char *) NULL
, counter
, NULL
,
2690 unsignedp
? "sltu" : "slt",
2691 "d,v,t", AT
, reg
, AT
);
2695 /* Warn if an expression is not a constant. */
2698 check_absolute_expr (ip
, ex
)
2699 struct mips_cl_insn
*ip
;
2702 if (ex
->X_op
!= O_constant
)
2703 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2706 /* Count the leading zeroes by performing a binary chop. This is a
2707 bulky bit of source, but performance is a LOT better for the
2708 majority of values than a simple loop to count the bits:
2709 for (lcnt = 0; (lcnt < 32); lcnt++)
2710 if ((v) & (1 << (31 - lcnt)))
2712 However it is not code size friendly, and the gain will drop a bit
2713 on certain cached systems.
2715 #define COUNT_TOP_ZEROES(v) \
2716 (((v) & ~0xffff) == 0 \
2717 ? ((v) & ~0xff) == 0 \
2718 ? ((v) & ~0xf) == 0 \
2719 ? ((v) & ~0x3) == 0 \
2720 ? ((v) & ~0x1) == 0 \
2725 : ((v) & ~0x7) == 0 \
2728 : ((v) & ~0x3f) == 0 \
2729 ? ((v) & ~0x1f) == 0 \
2732 : ((v) & ~0x7f) == 0 \
2735 : ((v) & ~0xfff) == 0 \
2736 ? ((v) & ~0x3ff) == 0 \
2737 ? ((v) & ~0x1ff) == 0 \
2740 : ((v) & ~0x7ff) == 0 \
2743 : ((v) & ~0x3fff) == 0 \
2744 ? ((v) & ~0x1fff) == 0 \
2747 : ((v) & ~0x7fff) == 0 \
2750 : ((v) & ~0xffffff) == 0 \
2751 ? ((v) & ~0xfffff) == 0 \
2752 ? ((v) & ~0x3ffff) == 0 \
2753 ? ((v) & ~0x1ffff) == 0 \
2756 : ((v) & ~0x7ffff) == 0 \
2759 : ((v) & ~0x3fffff) == 0 \
2760 ? ((v) & ~0x1fffff) == 0 \
2763 : ((v) & ~0x7fffff) == 0 \
2766 : ((v) & ~0xfffffff) == 0 \
2767 ? ((v) & ~0x3ffffff) == 0 \
2768 ? ((v) & ~0x1ffffff) == 0 \
2771 : ((v) & ~0x7ffffff) == 0 \
2774 : ((v) & ~0x3fffffff) == 0 \
2775 ? ((v) & ~0x1fffffff) == 0 \
2778 : ((v) & ~0x7fffffff) == 0 \
2783 * This routine generates the least number of instructions neccessary to load
2784 * an absolute expression value into a register.
2787 load_register (counter
, reg
, ep
, dbl
)
2794 expressionS hi32
, lo32
;
2796 if (ep
->X_op
!= O_big
)
2798 assert (ep
->X_op
== O_constant
);
2799 if (ep
->X_add_number
< 0x8000
2800 && (ep
->X_add_number
>= 0
2801 || (ep
->X_add_number
>= -0x8000
2804 || sizeof (ep
->X_add_number
) > 4))))
2806 /* We can handle 16 bit signed values with an addiu to
2807 $zero. No need to ever use daddiu here, since $zero and
2808 the result are always correct in 32 bit mode. */
2809 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2810 (int) BFD_RELOC_LO16
);
2813 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2815 /* We can handle 16 bit unsigned values with an ori to
2817 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2818 (int) BFD_RELOC_LO16
);
2821 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2822 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2823 == ~ (offsetT
) 0x7fffffff))
2826 || sizeof (ep
->X_add_number
) > 4
2827 || (ep
->X_add_number
& 0x80000000) == 0))
2828 || ((mips_opts
.isa
< 3 || ! dbl
)
2829 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2830 || (mips_opts
.isa
< 3
2832 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2833 == ~ (offsetT
) 0xffffffff)))
2835 /* 32 bit values require an lui. */
2836 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2837 (int) BFD_RELOC_HI16
);
2838 if ((ep
->X_add_number
& 0xffff) != 0)
2839 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2840 (int) BFD_RELOC_LO16
);
2845 /* The value is larger than 32 bits. */
2847 if (mips_opts
.isa
< 3)
2849 as_bad ("Number larger than 32 bits");
2850 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2851 (int) BFD_RELOC_LO16
);
2855 if (ep
->X_op
!= O_big
)
2858 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2859 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2860 hi32
.X_add_number
&= 0xffffffff;
2862 lo32
.X_add_number
&= 0xffffffff;
2866 assert (ep
->X_add_number
> 2);
2867 if (ep
->X_add_number
== 3)
2868 generic_bignum
[3] = 0;
2869 else if (ep
->X_add_number
> 4)
2870 as_bad ("Number larger than 64 bits");
2871 lo32
.X_op
= O_constant
;
2872 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2873 hi32
.X_op
= O_constant
;
2874 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2877 if (hi32
.X_add_number
== 0)
2882 unsigned long hi
, lo
;
2884 if (hi32
.X_add_number
== 0xffffffff)
2886 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2888 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2889 reg
, 0, (int) BFD_RELOC_LO16
);
2892 if (lo32
.X_add_number
& 0x80000000)
2894 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2895 (int) BFD_RELOC_HI16
);
2896 if (lo32
.X_add_number
& 0xffff)
2897 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2898 reg
, reg
, (int) BFD_RELOC_LO16
);
2903 /* Check for 16bit shifted constant. We know that hi32 is
2904 non-zero, so start the mask on the first bit of the hi32
2909 unsigned long himask
, lomask
;
2913 himask
= 0xffff >> (32 - shift
);
2914 lomask
= (0xffff << shift
) & 0xffffffff;
2918 himask
= 0xffff << (shift
- 32);
2921 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2922 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2926 tmp
.X_op
= O_constant
;
2928 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2929 | (lo32
.X_add_number
>> shift
));
2931 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2932 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2933 (int) BFD_RELOC_LO16
);
2934 macro_build ((char *) NULL
, counter
, NULL
,
2935 (shift
>= 32) ? "dsll32" : "dsll",
2937 (shift
>= 32) ? shift
- 32 : shift
);
2941 } while (shift
<= (64 - 16));
2943 /* Find the bit number of the lowest one bit, and store the
2944 shifted value in hi/lo. */
2945 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2946 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2950 while ((lo
& 1) == 0)
2955 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2961 while ((hi
& 1) == 0)
2970 /* Optimize if the shifted value is a (power of 2) - 1. */
2971 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2972 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2974 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2979 /* This instruction will set the register to be all
2981 tmp
.X_op
= O_constant
;
2982 tmp
.X_add_number
= (offsetT
) -1;
2983 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2984 reg
, 0, (int) BFD_RELOC_LO16
);
2988 macro_build ((char *) NULL
, counter
, NULL
,
2989 (bit
>= 32) ? "dsll32" : "dsll",
2991 (bit
>= 32) ? bit
- 32 : bit
);
2993 macro_build ((char *) NULL
, counter
, NULL
,
2994 (shift
>= 32) ? "dsrl32" : "dsrl",
2996 (shift
>= 32) ? shift
- 32 : shift
);
3001 /* Sign extend hi32 before calling load_register, because we can
3002 generally get better code when we load a sign extended value. */
3003 if ((hi32
.X_add_number
& 0x80000000) != 0)
3004 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3005 load_register (counter
, reg
, &hi32
, 0);
3008 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3012 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3021 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3023 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3024 (int) BFD_RELOC_HI16
);
3025 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3032 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3037 mid16
.X_add_number
>>= 16;
3038 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3039 freg
, (int) BFD_RELOC_LO16
);
3040 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3044 if ((lo32
.X_add_number
& 0xffff) != 0)
3045 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3046 (int) BFD_RELOC_LO16
);
3049 /* Load an address into a register. */
3052 load_address (counter
, reg
, ep
)
3059 if (ep
->X_op
!= O_constant
3060 && ep
->X_op
!= O_symbol
)
3062 as_bad ("expression too complex");
3063 ep
->X_op
= O_constant
;
3066 if (ep
->X_op
== O_constant
)
3068 load_register (counter
, reg
, ep
, 0);
3072 if (mips_pic
== NO_PIC
)
3074 /* If this is a reference to a GP relative symbol, we want
3075 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3077 lui $reg,<sym> (BFD_RELOC_HI16_S)
3078 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3079 If we have an addend, we always use the latter form. */
3080 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3081 || nopic_need_relax (ep
->X_add_symbol
))
3086 macro_build ((char *) NULL
, counter
, ep
,
3087 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3088 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3089 p
= frag_var (rs_machine_dependent
, 8, 0,
3090 RELAX_ENCODE (4, 8, 0, 4, 0,
3091 mips_opts
.warn_about_macros
),
3092 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3094 macro_build_lui (p
, counter
, ep
, reg
);
3097 macro_build (p
, counter
, ep
,
3098 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3099 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3101 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3105 /* If this is a reference to an external symbol, we want
3106 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3108 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3110 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3111 If there is a constant, it must be added in after. */
3112 ex
.X_add_number
= ep
->X_add_number
;
3113 ep
->X_add_number
= 0;
3115 macro_build ((char *) NULL
, counter
, ep
,
3116 mips_opts
.isa
< 3 ? "lw" : "ld",
3117 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3118 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3119 p
= frag_var (rs_machine_dependent
, 4, 0,
3120 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3121 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3122 macro_build (p
, counter
, ep
,
3123 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3124 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3125 if (ex
.X_add_number
!= 0)
3127 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3128 as_bad ("PIC code offset overflow (max 16 signed bits)");
3129 ex
.X_op
= O_constant
;
3130 macro_build ((char *) NULL
, counter
, &ex
,
3131 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3132 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3135 else if (mips_pic
== SVR4_PIC
)
3140 /* This is the large GOT case. If this is a reference to an
3141 external symbol, we want
3142 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3144 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3145 Otherwise, for a reference to a local symbol, we want
3146 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3148 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3149 If there is a constant, it must be added in after. */
3150 ex
.X_add_number
= ep
->X_add_number
;
3151 ep
->X_add_number
= 0;
3152 if (reg_needs_delay (GP
))
3157 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3158 (int) BFD_RELOC_MIPS_GOT_HI16
);
3159 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3160 mips_opts
.isa
< 3 ? "addu" : "daddu",
3161 "d,v,t", reg
, reg
, GP
);
3162 macro_build ((char *) NULL
, counter
, ep
,
3163 mips_opts
.isa
< 3 ? "lw" : "ld",
3164 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3165 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3166 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3167 mips_opts
.warn_about_macros
),
3168 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3171 /* We need a nop before loading from $gp. This special
3172 check is required because the lui which starts the main
3173 instruction stream does not refer to $gp, and so will not
3174 insert the nop which may be required. */
3175 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3178 macro_build (p
, counter
, ep
,
3179 mips_opts
.isa
< 3 ? "lw" : "ld",
3180 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3182 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3184 macro_build (p
, counter
, ep
,
3185 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3186 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3187 if (ex
.X_add_number
!= 0)
3189 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3190 as_bad ("PIC code offset overflow (max 16 signed bits)");
3191 ex
.X_op
= O_constant
;
3192 macro_build ((char *) NULL
, counter
, &ex
,
3193 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3194 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3197 else if (mips_pic
== EMBEDDED_PIC
)
3200 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3202 macro_build ((char *) NULL
, counter
, ep
,
3203 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3204 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3212 * This routine implements the seemingly endless macro or synthesized
3213 * instructions and addressing modes in the mips assembly language. Many
3214 * of these macros are simple and are similar to each other. These could
3215 * probably be handled by some kind of table or grammer aproach instead of
3216 * this verbose method. Others are not simple macros but are more like
3217 * optimizing code generation.
3218 * One interesting optimization is when several store macros appear
3219 * consecutivly that would load AT with the upper half of the same address.
3220 * The ensuing load upper instructions are ommited. This implies some kind
3221 * of global optimization. We currently only optimize within a single macro.
3222 * For many of the load and store macros if the address is specified as a
3223 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3224 * first load register 'at' with zero and use it as the base register. The
3225 * mips assembler simply uses register $zero. Just one tiny optimization
3230 struct mips_cl_insn
*ip
;
3232 register int treg
, sreg
, dreg
, breg
;
3247 bfd_reloc_code_real_type r
;
3249 int hold_mips_optimize
;
3251 assert (! mips_opts
.mips16
);
3253 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3254 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3255 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3256 mask
= ip
->insn_mo
->mask
;
3258 expr1
.X_op
= O_constant
;
3259 expr1
.X_op_symbol
= NULL
;
3260 expr1
.X_add_symbol
= NULL
;
3261 expr1
.X_add_number
= 1;
3273 mips_emit_delays (true);
3274 ++mips_opts
.noreorder
;
3275 mips_any_noreorder
= 1;
3277 expr1
.X_add_number
= 8;
3278 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3280 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3282 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3283 macro_build ((char *) NULL
, &icnt
, NULL
,
3284 dbl
? "dsub" : "sub",
3285 "d,v,t", dreg
, 0, sreg
);
3287 --mips_opts
.noreorder
;
3308 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3310 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3311 (int) BFD_RELOC_LO16
);
3314 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3315 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3334 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3336 if (mask
!= M_NOR_I
)
3337 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3338 sreg
, (int) BFD_RELOC_LO16
);
3341 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3342 treg
, sreg
, (int) BFD_RELOC_LO16
);
3343 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3349 load_register (&icnt
, AT
, &imm_expr
, 0);
3350 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3367 if (imm_expr
.X_add_number
== 0)
3369 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3373 load_register (&icnt
, AT
, &imm_expr
, 0);
3374 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3383 likely
? "bgezl" : "bgez",
3389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3390 likely
? "blezl" : "blez",
3394 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3396 likely
? "beql" : "beq",
3403 /* check for > max integer */
3404 maxnum
= 0x7fffffff;
3405 if (mips_opts
.isa
>= 3)
3412 if (imm_expr
.X_add_number
>= maxnum
3413 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3416 /* result is always false */
3419 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3420 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3424 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3425 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3430 imm_expr
.X_add_number
++;
3434 if (mask
== M_BGEL_I
)
3436 if (imm_expr
.X_add_number
== 0)
3438 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3439 likely
? "bgezl" : "bgez",
3443 if (imm_expr
.X_add_number
== 1)
3445 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3446 likely
? "bgtzl" : "bgtz",
3450 maxnum
= 0x7fffffff;
3451 if (mips_opts
.isa
>= 3)
3458 maxnum
= - maxnum
- 1;
3459 if (imm_expr
.X_add_number
<= maxnum
3460 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3463 /* result is always true */
3464 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3465 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3468 set_at (&icnt
, sreg
, 0);
3469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3470 likely
? "beql" : "beq",
3481 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3482 likely
? "beql" : "beq",
3486 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3488 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3489 likely
? "beql" : "beq",
3496 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3498 imm_expr
.X_add_number
++;
3502 if (mask
== M_BGEUL_I
)
3504 if (imm_expr
.X_add_number
== 0)
3506 if (imm_expr
.X_add_number
== 1)
3508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3509 likely
? "bnel" : "bne",
3513 set_at (&icnt
, sreg
, 1);
3514 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3515 likely
? "beql" : "beq",
3524 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3525 likely
? "bgtzl" : "bgtz",
3531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3532 likely
? "bltzl" : "bltz",
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3538 likely
? "bnel" : "bne",
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3548 likely
? "bnel" : "bne",
3554 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3557 likely
? "bnel" : "bne",
3566 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3567 likely
? "blezl" : "blez",
3573 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3574 likely
? "bgezl" : "bgez",
3578 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3579 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3580 likely
? "beql" : "beq",
3587 maxnum
= 0x7fffffff;
3588 if (mips_opts
.isa
>= 3)
3595 if (imm_expr
.X_add_number
>= maxnum
3596 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3598 imm_expr
.X_add_number
++;
3602 if (mask
== M_BLTL_I
)
3604 if (imm_expr
.X_add_number
== 0)
3606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3607 likely
? "bltzl" : "bltz",
3611 if (imm_expr
.X_add_number
== 1)
3613 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3614 likely
? "blezl" : "blez",
3618 set_at (&icnt
, sreg
, 0);
3619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3620 likely
? "bnel" : "bne",
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3630 likely
? "beql" : "beq",
3636 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3638 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3639 likely
? "beql" : "beq",
3646 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3648 imm_expr
.X_add_number
++;
3652 if (mask
== M_BLTUL_I
)
3654 if (imm_expr
.X_add_number
== 0)
3656 if (imm_expr
.X_add_number
== 1)
3658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3659 likely
? "beql" : "beq",
3663 set_at (&icnt
, sreg
, 1);
3664 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3665 likely
? "bnel" : "bne",
3674 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3675 likely
? "bltzl" : "bltz",
3681 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3682 likely
? "bgtzl" : "bgtz",
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3688 likely
? "bnel" : "bne",
3699 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3700 likely
? "bnel" : "bne",
3704 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3707 likely
? "bnel" : "bne",
3723 as_warn ("Divide by zero.");
3725 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3727 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3731 mips_emit_delays (true);
3732 ++mips_opts
.noreorder
;
3733 mips_any_noreorder
= 1;
3734 macro_build ((char *) NULL
, &icnt
, NULL
,
3735 dbl
? "ddiv" : "div",
3736 "z,s,t", sreg
, treg
);
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3741 expr1
.X_add_number
= 8;
3742 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3743 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3744 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3746 expr1
.X_add_number
= -1;
3747 macro_build ((char *) NULL
, &icnt
, &expr1
,
3748 dbl
? "daddiu" : "addiu",
3749 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3750 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3751 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3754 expr1
.X_add_number
= 1;
3755 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3756 (int) BFD_RELOC_LO16
);
3757 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3762 expr1
.X_add_number
= 0x80000000;
3763 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3764 (int) BFD_RELOC_HI16
);
3767 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3770 expr1
.X_add_number
= 8;
3771 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3772 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3773 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3775 --mips_opts
.noreorder
;
3776 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3815 if (imm_expr
.X_add_number
== 0)
3817 as_warn ("Divide by zero.");
3819 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3821 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3824 if (imm_expr
.X_add_number
== 1)
3826 if (strcmp (s2
, "mflo") == 0)
3827 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3830 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3833 if (imm_expr
.X_add_number
== -1
3834 && s
[strlen (s
) - 1] != 'u')
3836 if (strcmp (s2
, "mflo") == 0)
3839 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3842 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3846 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3850 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3851 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3852 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3871 mips_emit_delays (true);
3872 ++mips_opts
.noreorder
;
3873 mips_any_noreorder
= 1;
3874 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3876 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3879 expr1
.X_add_number
= 8;
3880 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3881 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3882 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3884 --mips_opts
.noreorder
;
3885 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3891 /* Load the address of a symbol into a register. If breg is not
3892 zero, we then add a base register to it. */
3894 /* When generating embedded PIC code, we permit expressions of
3897 where bar is an address in the .text section. These are used
3898 when getting the addresses of functions. We don't permit
3899 X_add_number to be non-zero, because if the symbol is
3900 external the relaxing code needs to know that any addend is
3901 purely the offset to X_op_symbol. */
3902 if (mips_pic
== EMBEDDED_PIC
3903 && offset_expr
.X_op
== O_subtract
3904 && now_seg
== text_section
3905 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3906 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3907 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3908 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3909 ->sy_value
.X_add_symbol
)
3912 && offset_expr
.X_add_number
== 0)
3914 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3915 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3917 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3918 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3922 if (offset_expr
.X_op
!= O_symbol
3923 && offset_expr
.X_op
!= O_constant
)
3925 as_bad ("expression too complex");
3926 offset_expr
.X_op
= O_constant
;
3940 if (offset_expr
.X_op
== O_constant
)
3941 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3942 else if (mips_pic
== NO_PIC
)
3944 /* If this is a reference to an GP relative symbol, we want
3945 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3947 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3948 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3949 If we have a constant, we need two instructions anyhow,
3950 so we may as well always use the latter form. */
3951 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3952 || nopic_need_relax (offset_expr
.X_add_symbol
))
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3958 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3959 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3960 p
= frag_var (rs_machine_dependent
, 8, 0,
3961 RELAX_ENCODE (4, 8, 0, 4, 0,
3962 mips_opts
.warn_about_macros
),
3963 offset_expr
.X_add_symbol
, (offsetT
) 0,
3966 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3969 macro_build (p
, &icnt
, &offset_expr
,
3970 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3971 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3973 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3975 /* If this is a reference to an external symbol, and there
3976 is no constant, we want
3977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3978 For a local symbol, we want
3979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3981 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3983 If we have a small constant, and this is a reference to
3984 an external symbol, we want
3985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3987 addiu $tempreg,$tempreg,<constant>
3988 For a local symbol, we want the same instruction
3989 sequence, but we output a BFD_RELOC_LO16 reloc on the
3992 If we have a large constant, and this is a reference to
3993 an external symbol, we want
3994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3995 lui $at,<hiconstant>
3996 addiu $at,$at,<loconstant>
3997 addu $tempreg,$tempreg,$at
3998 For a local symbol, we want the same instruction
3999 sequence, but we output a BFD_RELOC_LO16 reloc on the
4000 addiu instruction. */
4001 expr1
.X_add_number
= offset_expr
.X_add_number
;
4002 offset_expr
.X_add_number
= 0;
4004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4006 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4007 if (expr1
.X_add_number
== 0)
4015 /* We're going to put in an addu instruction using
4016 tempreg, so we may as well insert the nop right
4018 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4022 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4023 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4025 ? mips_opts
.warn_about_macros
4027 offset_expr
.X_add_symbol
, (offsetT
) 0,
4031 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4034 macro_build (p
, &icnt
, &expr1
,
4035 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4036 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4037 /* FIXME: If breg == 0, and the next instruction uses
4038 $tempreg, then if this variant case is used an extra
4039 nop will be generated. */
4041 else if (expr1
.X_add_number
>= -0x8000
4042 && expr1
.X_add_number
< 0x8000)
4044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4046 macro_build ((char *) NULL
, &icnt
, &expr1
,
4047 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4048 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4049 (void) frag_var (rs_machine_dependent
, 0, 0,
4050 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4051 offset_expr
.X_add_symbol
, (offsetT
) 0,
4058 /* If we are going to add in a base register, and the
4059 target register and the base register are the same,
4060 then we are using AT as a temporary register. Since
4061 we want to load the constant into AT, we add our
4062 current AT (from the global offset table) and the
4063 register into the register now, and pretend we were
4064 not using a base register. */
4069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4072 mips_opts
.isa
< 3 ? "addu" : "daddu",
4073 "d,v,t", treg
, AT
, breg
);
4079 /* Set mips_optimize around the lui instruction to avoid
4080 inserting an unnecessary nop after the lw. */
4081 hold_mips_optimize
= mips_optimize
;
4083 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4084 mips_optimize
= hold_mips_optimize
;
4086 macro_build ((char *) NULL
, &icnt
, &expr1
,
4087 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4088 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4089 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4090 mips_opts
.isa
< 3 ? "addu" : "daddu",
4091 "d,v,t", tempreg
, tempreg
, AT
);
4092 (void) frag_var (rs_machine_dependent
, 0, 0,
4093 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4094 offset_expr
.X_add_symbol
, (offsetT
) 0,
4099 else if (mips_pic
== SVR4_PIC
)
4103 /* This is the large GOT case. If this is a reference to an
4104 external symbol, and there is no constant, we want
4105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4106 addu $tempreg,$tempreg,$gp
4107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4108 For a local symbol, we want
4109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4111 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4113 If we have a small constant, and this is a reference to
4114 an external symbol, we want
4115 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4116 addu $tempreg,$tempreg,$gp
4117 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4119 addiu $tempreg,$tempreg,<constant>
4120 For a local symbol, we want
4121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4123 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4125 If we have a large constant, and this is a reference to
4126 an external symbol, we want
4127 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4128 addu $tempreg,$tempreg,$gp
4129 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4130 lui $at,<hiconstant>
4131 addiu $at,$at,<loconstant>
4132 addu $tempreg,$tempreg,$at
4133 For a local symbol, we want
4134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4135 lui $at,<hiconstant>
4136 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4137 addu $tempreg,$tempreg,$at
4139 expr1
.X_add_number
= offset_expr
.X_add_number
;
4140 offset_expr
.X_add_number
= 0;
4142 if (reg_needs_delay (GP
))
4146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4147 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4148 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4149 mips_opts
.isa
< 3 ? "addu" : "daddu",
4150 "d,v,t", tempreg
, tempreg
, GP
);
4151 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4153 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4155 if (expr1
.X_add_number
== 0)
4163 /* We're going to put in an addu instruction using
4164 tempreg, so we may as well insert the nop right
4166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4171 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4172 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4175 ? mips_opts
.warn_about_macros
4177 offset_expr
.X_add_symbol
, (offsetT
) 0,
4180 else if (expr1
.X_add_number
>= -0x8000
4181 && expr1
.X_add_number
< 0x8000)
4183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4185 macro_build ((char *) NULL
, &icnt
, &expr1
,
4186 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4187 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4189 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4190 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4192 ? mips_opts
.warn_about_macros
4194 offset_expr
.X_add_symbol
, (offsetT
) 0,
4201 /* If we are going to add in a base register, and the
4202 target register and the base register are the same,
4203 then we are using AT as a temporary register. Since
4204 we want to load the constant into AT, we add our
4205 current AT (from the global offset table) and the
4206 register into the register now, and pretend we were
4207 not using a base register. */
4215 assert (tempreg
== AT
);
4216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4218 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4219 mips_opts
.isa
< 3 ? "addu" : "daddu",
4220 "d,v,t", treg
, AT
, breg
);
4225 /* Set mips_optimize around the lui instruction to avoid
4226 inserting an unnecessary nop after the lw. */
4227 hold_mips_optimize
= mips_optimize
;
4229 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4230 mips_optimize
= hold_mips_optimize
;
4232 macro_build ((char *) NULL
, &icnt
, &expr1
,
4233 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4234 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4235 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4236 mips_opts
.isa
< 3 ? "addu" : "daddu",
4237 "d,v,t", dreg
, dreg
, AT
);
4239 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4240 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4243 ? mips_opts
.warn_about_macros
4245 offset_expr
.X_add_symbol
, (offsetT
) 0,
4253 /* This is needed because this instruction uses $gp, but
4254 the first instruction on the main stream does not. */
4255 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4258 macro_build (p
, &icnt
, &offset_expr
,
4260 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4262 if (expr1
.X_add_number
>= -0x8000
4263 && expr1
.X_add_number
< 0x8000)
4265 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4267 macro_build (p
, &icnt
, &expr1
,
4268 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4269 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4270 /* FIXME: If add_number is 0, and there was no base
4271 register, the external symbol case ended with a load,
4272 so if the symbol turns out to not be external, and
4273 the next instruction uses tempreg, an unnecessary nop
4274 will be inserted. */
4280 /* We must add in the base register now, as in the
4281 external symbol case. */
4282 assert (tempreg
== AT
);
4283 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4285 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4286 mips_opts
.isa
< 3 ? "addu" : "daddu",
4287 "d,v,t", treg
, AT
, breg
);
4290 /* We set breg to 0 because we have arranged to add
4291 it in in both cases. */
4295 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4297 macro_build (p
, &icnt
, &expr1
,
4298 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4299 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4301 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4302 mips_opts
.isa
< 3 ? "addu" : "daddu",
4303 "d,v,t", tempreg
, tempreg
, AT
);
4307 else if (mips_pic
== EMBEDDED_PIC
)
4310 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4312 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4313 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4314 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4321 mips_opts
.isa
< 3 ? "addu" : "daddu",
4322 "d,v,t", treg
, tempreg
, breg
);
4330 /* The j instruction may not be used in PIC code, since it
4331 requires an absolute address. We convert it to a b
4333 if (mips_pic
== NO_PIC
)
4334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4336 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4339 /* The jal instructions must be handled as macros because when
4340 generating PIC code they expand to multi-instruction
4341 sequences. Normally they are simple instructions. */
4346 if (mips_pic
== NO_PIC
4347 || mips_pic
== EMBEDDED_PIC
)
4348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4350 else if (mips_pic
== SVR4_PIC
)
4352 if (sreg
!= PIC_CALL_REG
)
4353 as_warn ("MIPS PIC call to register other than $25");
4355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4357 if (mips_cprestore_offset
< 0)
4358 as_warn ("No .cprestore pseudo-op used in PIC code");
4361 expr1
.X_add_number
= mips_cprestore_offset
;
4362 macro_build ((char *) NULL
, &icnt
, &expr1
,
4363 mips_opts
.isa
< 3 ? "lw" : "ld",
4364 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4373 if (mips_pic
== NO_PIC
)
4374 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4375 else if (mips_pic
== SVR4_PIC
)
4377 /* If this is a reference to an external symbol, and we are
4378 using a small GOT, we want
4379 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4383 lw $gp,cprestore($sp)
4384 The cprestore value is set using the .cprestore
4385 pseudo-op. If we are using a big GOT, we want
4386 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4388 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4392 lw $gp,cprestore($sp)
4393 If the symbol is not external, we want
4394 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4396 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4399 lw $gp,cprestore($sp) */
4403 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4404 mips_opts
.isa
< 3 ? "lw" : "ld",
4405 "t,o(b)", PIC_CALL_REG
,
4406 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4407 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4409 p
= frag_var (rs_machine_dependent
, 4, 0,
4410 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4411 offset_expr
.X_add_symbol
, (offsetT
) 0,
4418 if (reg_needs_delay (GP
))
4422 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4423 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4425 mips_opts
.isa
< 3 ? "addu" : "daddu",
4426 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4428 mips_opts
.isa
< 3 ? "lw" : "ld",
4429 "t,o(b)", PIC_CALL_REG
,
4430 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4431 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4433 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4434 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4436 offset_expr
.X_add_symbol
, (offsetT
) 0,
4440 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4443 macro_build (p
, &icnt
, &offset_expr
,
4444 mips_opts
.isa
< 3 ? "lw" : "ld",
4445 "t,o(b)", PIC_CALL_REG
,
4446 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4448 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4451 macro_build (p
, &icnt
, &offset_expr
,
4452 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4453 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4454 (int) BFD_RELOC_LO16
);
4455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4456 "jalr", "s", PIC_CALL_REG
);
4457 if (mips_cprestore_offset
< 0)
4458 as_warn ("No .cprestore pseudo-op used in PIC code");
4461 if (mips_opts
.noreorder
)
4462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4464 expr1
.X_add_number
= mips_cprestore_offset
;
4465 macro_build ((char *) NULL
, &icnt
, &expr1
,
4466 mips_opts
.isa
< 3 ? "lw" : "ld",
4467 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4471 else if (mips_pic
== EMBEDDED_PIC
)
4473 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4474 /* The linker may expand the call to a longer sequence which
4475 uses $at, so we must break rather than return. */
4500 /* Itbl support may require additional care here. */
4505 /* Itbl support may require additional care here. */
4510 /* Itbl support may require additional care here. */
4515 /* Itbl support may require additional care here. */
4528 /* Itbl support may require additional care here. */
4533 /* Itbl support may require additional care here. */
4538 /* Itbl support may require additional care here. */
4558 if (breg
== treg
|| coproc
|| lr
)
4580 /* Itbl support may require additional care here. */
4585 /* Itbl support may require additional care here. */
4590 /* Itbl support may require additional care here. */
4595 /* Itbl support may require additional care here. */
4613 /* Itbl support may require additional care here. */
4617 /* Itbl support may require additional care here. */
4622 /* Itbl support may require additional care here. */
4634 /* Itbl support may require additional care here. */
4635 if (mask
== M_LWC1_AB
4636 || mask
== M_SWC1_AB
4637 || mask
== M_LDC1_AB
4638 || mask
== M_SDC1_AB
4647 if (offset_expr
.X_op
!= O_constant
4648 && offset_expr
.X_op
!= O_symbol
)
4650 as_bad ("expression too complex");
4651 offset_expr
.X_op
= O_constant
;
4654 /* A constant expression in PIC code can be handled just as it
4655 is in non PIC code. */
4656 if (mips_pic
== NO_PIC
4657 || offset_expr
.X_op
== O_constant
)
4659 /* If this is a reference to a GP relative symbol, and there
4660 is no base register, we want
4661 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4662 Otherwise, if there is no base register, we want
4663 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4664 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4665 If we have a constant, we need two instructions anyhow,
4666 so we always use the latter form.
4668 If we have a base register, and this is a reference to a
4669 GP relative symbol, we want
4670 addu $tempreg,$breg,$gp
4671 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4673 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4674 addu $tempreg,$tempreg,$breg
4675 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4676 With a constant we always use the latter case. */
4679 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4680 || nopic_need_relax (offset_expr
.X_add_symbol
))
4685 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4686 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4687 p
= frag_var (rs_machine_dependent
, 8, 0,
4688 RELAX_ENCODE (4, 8, 0, 4, 0,
4689 (mips_opts
.warn_about_macros
4691 && mips_opts
.noat
))),
4692 offset_expr
.X_add_symbol
, (offsetT
) 0,
4696 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4699 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4700 (int) BFD_RELOC_LO16
, tempreg
);
4704 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4705 || nopic_need_relax (offset_expr
.X_add_symbol
))
4710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4711 mips_opts
.isa
< 3 ? "addu" : "daddu",
4712 "d,v,t", tempreg
, breg
, GP
);
4713 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4714 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4715 p
= frag_var (rs_machine_dependent
, 12, 0,
4716 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4717 offset_expr
.X_add_symbol
, (offsetT
) 0,
4720 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4723 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4724 mips_opts
.isa
< 3 ? "addu" : "daddu",
4725 "d,v,t", tempreg
, tempreg
, breg
);
4728 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4729 (int) BFD_RELOC_LO16
, tempreg
);
4732 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4734 /* If this is a reference to an external symbol, we want
4735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4737 <op> $treg,0($tempreg)
4739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4742 <op> $treg,0($tempreg)
4743 If there is a base register, we add it to $tempreg before
4744 the <op>. If there is a constant, we stick it in the
4745 <op> instruction. We don't handle constants larger than
4746 16 bits, because we have no way to load the upper 16 bits
4747 (actually, we could handle them for the subset of cases
4748 in which we are not using $at). */
4749 assert (offset_expr
.X_op
== O_symbol
);
4750 expr1
.X_add_number
= offset_expr
.X_add_number
;
4751 offset_expr
.X_add_number
= 0;
4752 if (expr1
.X_add_number
< -0x8000
4753 || expr1
.X_add_number
>= 0x8000)
4754 as_bad ("PIC code offset overflow (max 16 signed bits)");
4756 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4757 mips_opts
.isa
< 3 ? "lw" : "ld",
4758 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4760 p
= frag_var (rs_machine_dependent
, 4, 0,
4761 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4762 offset_expr
.X_add_symbol
, (offsetT
) 0,
4764 macro_build (p
, &icnt
, &offset_expr
,
4765 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4766 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4769 mips_opts
.isa
< 3 ? "addu" : "daddu",
4770 "d,v,t", tempreg
, tempreg
, breg
);
4771 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4772 (int) BFD_RELOC_LO16
, tempreg
);
4774 else if (mips_pic
== SVR4_PIC
)
4778 /* If this is a reference to an external symbol, we want
4779 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4780 addu $tempreg,$tempreg,$gp
4781 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4782 <op> $treg,0($tempreg)
4784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4786 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4787 <op> $treg,0($tempreg)
4788 If there is a base register, we add it to $tempreg before
4789 the <op>. If there is a constant, we stick it in the
4790 <op> instruction. We don't handle constants larger than
4791 16 bits, because we have no way to load the upper 16 bits
4792 (actually, we could handle them for the subset of cases
4793 in which we are not using $at). */
4794 assert (offset_expr
.X_op
== O_symbol
);
4795 expr1
.X_add_number
= offset_expr
.X_add_number
;
4796 offset_expr
.X_add_number
= 0;
4797 if (expr1
.X_add_number
< -0x8000
4798 || expr1
.X_add_number
>= 0x8000)
4799 as_bad ("PIC code offset overflow (max 16 signed bits)");
4800 if (reg_needs_delay (GP
))
4805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4806 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4808 mips_opts
.isa
< 3 ? "addu" : "daddu",
4809 "d,v,t", tempreg
, tempreg
, GP
);
4810 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4811 mips_opts
.isa
< 3 ? "lw" : "ld",
4812 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4814 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4815 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4816 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4819 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4822 macro_build (p
, &icnt
, &offset_expr
,
4823 mips_opts
.isa
< 3 ? "lw" : "ld",
4824 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4826 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4828 macro_build (p
, &icnt
, &offset_expr
,
4829 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4830 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4833 mips_opts
.isa
< 3 ? "addu" : "daddu",
4834 "d,v,t", tempreg
, tempreg
, breg
);
4835 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4836 (int) BFD_RELOC_LO16
, tempreg
);
4838 else if (mips_pic
== EMBEDDED_PIC
)
4840 /* If there is no base register, we want
4841 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4842 If there is a base register, we want
4843 addu $tempreg,$breg,$gp
4844 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4846 assert (offset_expr
.X_op
== O_symbol
);
4849 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4850 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4856 mips_opts
.isa
< 3 ? "addu" : "daddu",
4857 "d,v,t", tempreg
, breg
, GP
);
4858 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4859 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4872 load_register (&icnt
, treg
, &imm_expr
, 0);
4876 load_register (&icnt
, treg
, &imm_expr
, 1);
4880 if (imm_expr
.X_op
== O_constant
)
4882 load_register (&icnt
, AT
, &imm_expr
, 0);
4883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4884 "mtc1", "t,G", AT
, treg
);
4889 assert (offset_expr
.X_op
== O_symbol
4890 && strcmp (segment_name (S_GET_SEGMENT
4891 (offset_expr
.X_add_symbol
)),
4893 && offset_expr
.X_add_number
== 0);
4894 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4895 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4900 /* We know that sym is in the .rdata section. First we get the
4901 upper 16 bits of the address. */
4902 if (mips_pic
== NO_PIC
)
4904 /* FIXME: This won't work for a 64 bit address. */
4905 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4907 else if (mips_pic
== SVR4_PIC
)
4909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4910 mips_opts
.isa
< 3 ? "lw" : "ld",
4911 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4913 else if (mips_pic
== EMBEDDED_PIC
)
4915 /* For embedded PIC we pick up the entire address off $gp in
4916 a single instruction. */
4917 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4918 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4919 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4920 offset_expr
.X_op
= O_constant
;
4921 offset_expr
.X_add_number
= 0;
4926 /* Now we load the register(s). */
4927 if (mips_opts
.isa
>= 3)
4928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4929 treg
, (int) BFD_RELOC_LO16
, AT
);
4932 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4933 treg
, (int) BFD_RELOC_LO16
, AT
);
4936 /* FIXME: How in the world do we deal with the possible
4938 offset_expr
.X_add_number
+= 4;
4939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4940 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4944 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4945 does not become a variant frag. */
4946 frag_wane (frag_now
);
4952 assert (offset_expr
.X_op
== O_symbol
4953 && offset_expr
.X_add_number
== 0);
4954 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4955 if (strcmp (s
, ".lit8") == 0)
4957 if (mips_opts
.isa
>= 2)
4959 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4960 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4964 r
= BFD_RELOC_MIPS_LITERAL
;
4969 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4970 if (mips_pic
== SVR4_PIC
)
4971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4972 mips_opts
.isa
< 3 ? "lw" : "ld",
4973 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4976 /* FIXME: This won't work for a 64 bit address. */
4977 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4980 if (mips_opts
.isa
>= 2)
4982 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4983 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4985 /* To avoid confusion in tc_gen_reloc, we must ensure
4986 that this does not become a variant frag. */
4987 frag_wane (frag_now
);
4998 /* Even on a big endian machine $fn comes before $fn+1. We have
4999 to adjust when loading from memory. */
5002 assert (mips_opts
.isa
< 2);
5003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5004 target_big_endian
? treg
+ 1 : treg
,
5006 /* FIXME: A possible overflow which I don't know how to deal
5008 offset_expr
.X_add_number
+= 4;
5009 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5010 target_big_endian
? treg
: treg
+ 1,
5013 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5014 does not become a variant frag. */
5015 frag_wane (frag_now
);
5024 * The MIPS assembler seems to check for X_add_number not
5025 * being double aligned and generating:
5028 * addiu at,at,%lo(foo+1)
5031 * But, the resulting address is the same after relocation so why
5032 * generate the extra instruction?
5034 /* Itbl support may require additional care here. */
5036 if (mips_opts
.isa
>= 2)
5047 if (mips_opts
.isa
>= 2)
5055 /* Itbl support may require additional care here. */
5060 if (mips_opts
.isa
>= 3)
5071 if (mips_opts
.isa
>= 3)
5081 if (offset_expr
.X_op
!= O_symbol
5082 && offset_expr
.X_op
!= O_constant
)
5084 as_bad ("expression too complex");
5085 offset_expr
.X_op
= O_constant
;
5088 /* Even on a big endian machine $fn comes before $fn+1. We have
5089 to adjust when loading from memory. We set coproc if we must
5090 load $fn+1 first. */
5091 /* Itbl support may require additional care here. */
5092 if (! target_big_endian
)
5095 if (mips_pic
== NO_PIC
5096 || offset_expr
.X_op
== O_constant
)
5098 /* If this is a reference to a GP relative symbol, we want
5099 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5100 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5101 If we have a base register, we use this
5103 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5104 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5105 If this is not a GP relative symbol, we want
5106 lui $at,<sym> (BFD_RELOC_HI16_S)
5107 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5108 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5109 If there is a base register, we add it to $at after the
5110 lui instruction. If there is a constant, we always use
5112 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5113 || nopic_need_relax (offset_expr
.X_add_symbol
))
5132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5133 mips_opts
.isa
< 3 ? "addu" : "daddu",
5134 "d,v,t", AT
, breg
, GP
);
5140 /* Itbl support may require additional care here. */
5141 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5142 coproc
? treg
+ 1 : treg
,
5143 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5144 offset_expr
.X_add_number
+= 4;
5146 /* Set mips_optimize to 2 to avoid inserting an
5148 hold_mips_optimize
= mips_optimize
;
5150 /* Itbl support may require additional care here. */
5151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5152 coproc
? treg
: treg
+ 1,
5153 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5154 mips_optimize
= hold_mips_optimize
;
5156 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5157 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5158 used_at
&& mips_opts
.noat
),
5159 offset_expr
.X_add_symbol
, (offsetT
) 0,
5162 /* We just generated two relocs. When tc_gen_reloc
5163 handles this case, it will skip the first reloc and
5164 handle the second. The second reloc already has an
5165 extra addend of 4, which we added above. We must
5166 subtract it out, and then subtract another 4 to make
5167 the first reloc come out right. The second reloc
5168 will come out right because we are going to add 4 to
5169 offset_expr when we build its instruction below. */
5170 offset_expr
.X_add_number
-= 8;
5171 offset_expr
.X_op
= O_constant
;
5173 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5178 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5179 mips_opts
.isa
< 3 ? "addu" : "daddu",
5180 "d,v,t", AT
, breg
, AT
);
5184 /* Itbl support may require additional care here. */
5185 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5186 coproc
? treg
+ 1 : treg
,
5187 (int) BFD_RELOC_LO16
, AT
);
5190 /* FIXME: How do we handle overflow here? */
5191 offset_expr
.X_add_number
+= 4;
5192 /* Itbl support may require additional care here. */
5193 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5194 coproc
? treg
: treg
+ 1,
5195 (int) BFD_RELOC_LO16
, AT
);
5197 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5201 /* If this is a reference to an external symbol, we want
5202 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5207 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5209 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5210 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5211 If there is a base register we add it to $at before the
5212 lwc1 instructions. If there is a constant we include it
5213 in the lwc1 instructions. */
5215 expr1
.X_add_number
= offset_expr
.X_add_number
;
5216 offset_expr
.X_add_number
= 0;
5217 if (expr1
.X_add_number
< -0x8000
5218 || expr1
.X_add_number
>= 0x8000 - 4)
5219 as_bad ("PIC code offset overflow (max 16 signed bits)");
5224 frag_grow (24 + off
);
5225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5226 mips_opts
.isa
< 3 ? "lw" : "ld",
5227 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5230 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5231 mips_opts
.isa
< 3 ? "addu" : "daddu",
5232 "d,v,t", AT
, breg
, AT
);
5233 /* Itbl support may require additional care here. */
5234 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5235 coproc
? treg
+ 1 : treg
,
5236 (int) BFD_RELOC_LO16
, AT
);
5237 expr1
.X_add_number
+= 4;
5239 /* Set mips_optimize to 2 to avoid inserting an undesired
5241 hold_mips_optimize
= mips_optimize
;
5243 /* Itbl support may require additional care here. */
5244 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5245 coproc
? treg
: treg
+ 1,
5246 (int) BFD_RELOC_LO16
, AT
);
5247 mips_optimize
= hold_mips_optimize
;
5249 (void) frag_var (rs_machine_dependent
, 0, 0,
5250 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5251 offset_expr
.X_add_symbol
, (offsetT
) 0,
5254 else if (mips_pic
== SVR4_PIC
)
5258 /* If this is a reference to an external symbol, we want
5259 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5261 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5266 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5268 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5269 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5270 If there is a base register we add it to $at before the
5271 lwc1 instructions. If there is a constant we include it
5272 in the lwc1 instructions. */
5274 expr1
.X_add_number
= offset_expr
.X_add_number
;
5275 offset_expr
.X_add_number
= 0;
5276 if (expr1
.X_add_number
< -0x8000
5277 || expr1
.X_add_number
>= 0x8000 - 4)
5278 as_bad ("PIC code offset overflow (max 16 signed bits)");
5279 if (reg_needs_delay (GP
))
5288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5289 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5291 mips_opts
.isa
< 3 ? "addu" : "daddu",
5292 "d,v,t", AT
, AT
, GP
);
5293 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5294 mips_opts
.isa
< 3 ? "lw" : "ld",
5295 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5299 mips_opts
.isa
< 3 ? "addu" : "daddu",
5300 "d,v,t", AT
, breg
, AT
);
5301 /* Itbl support may require additional care here. */
5302 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5303 coproc
? treg
+ 1 : treg
,
5304 (int) BFD_RELOC_LO16
, AT
);
5305 expr1
.X_add_number
+= 4;
5307 /* Set mips_optimize to 2 to avoid inserting an undesired
5309 hold_mips_optimize
= mips_optimize
;
5311 /* Itbl support may require additional care here. */
5312 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5313 coproc
? treg
: treg
+ 1,
5314 (int) BFD_RELOC_LO16
, AT
);
5315 mips_optimize
= hold_mips_optimize
;
5316 expr1
.X_add_number
-= 4;
5318 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5319 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5320 8 + gpdel
+ off
, 1, 0),
5321 offset_expr
.X_add_symbol
, (offsetT
) 0,
5325 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5328 macro_build (p
, &icnt
, &offset_expr
,
5329 mips_opts
.isa
< 3 ? "lw" : "ld",
5330 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5332 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5336 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5337 mips_opts
.isa
< 3 ? "addu" : "daddu",
5338 "d,v,t", AT
, breg
, AT
);
5341 /* Itbl support may require additional care here. */
5342 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5343 coproc
? treg
+ 1 : treg
,
5344 (int) BFD_RELOC_LO16
, AT
);
5346 expr1
.X_add_number
+= 4;
5348 /* Set mips_optimize to 2 to avoid inserting an undesired
5350 hold_mips_optimize
= mips_optimize
;
5352 /* Itbl support may require additional care here. */
5353 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5354 coproc
? treg
: treg
+ 1,
5355 (int) BFD_RELOC_LO16
, AT
);
5356 mips_optimize
= hold_mips_optimize
;
5358 else if (mips_pic
== EMBEDDED_PIC
)
5360 /* If there is no base register, we use
5361 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5362 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5363 If we have a base register, we use
5365 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5366 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5376 mips_opts
.isa
< 3 ? "addu" : "daddu",
5377 "d,v,t", AT
, breg
, GP
);
5382 /* Itbl support may require additional care here. */
5383 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5384 coproc
? treg
+ 1 : treg
,
5385 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5386 offset_expr
.X_add_number
+= 4;
5387 /* Itbl support may require additional care here. */
5388 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5389 coproc
? treg
: treg
+ 1,
5390 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5406 assert (mips_opts
.isa
< 3);
5407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5408 (int) BFD_RELOC_LO16
, breg
);
5409 offset_expr
.X_add_number
+= 4;
5410 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5411 (int) BFD_RELOC_LO16
, breg
);
5414 /* New code added to support COPZ instructions.
5415 This code builds table entries out of the macros in mip_opcodes.
5416 R4000 uses interlocks to handle coproc delays.
5417 Other chips (like the R3000) require nops to be inserted for delays.
5419 FIXME: Currently, we require that the user handle delays.
5420 In order to fill delay slots for non-interlocked chips,
5421 we must have a way to specify delays based on the coprocessor.
5422 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5423 What are the side-effects of the cop instruction?
5424 What cache support might we have and what are its effects?
5425 Both coprocessor & memory require delays. how long???
5426 What registers are read/set/modified?
5428 If an itbl is provided to interpret cop instructions,
5429 this knowledge can be encoded in the itbl spec. */
5443 /* For now we just do C (same as Cz). */
5444 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5447 #ifdef LOSING_COMPILER
5449 /* Try and see if this is a new itbl instruction.
5450 This code builds table entries out of the macros in mip_opcodes.
5451 FIXME: For now we just assemble the expression and pass it's
5452 value along as a 32-bit immediate.
5453 We may want to have the assembler assemble this value,
5454 so that we gain the assembler's knowledge of delay slots,
5456 Would it be more efficient to use mask (id) here? */
5457 if (itbl_have_entries
5458 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5460 s
= ip
->insn_mo
->name
;
5462 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5463 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5470 as_warn ("Macro used $at after \".set noat\"");
5475 struct mips_cl_insn
*ip
;
5477 register int treg
, sreg
, dreg
, breg
;
5492 bfd_reloc_code_real_type r
;
5495 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5496 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5497 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5498 mask
= ip
->insn_mo
->mask
;
5500 expr1
.X_op
= O_constant
;
5501 expr1
.X_op_symbol
= NULL
;
5502 expr1
.X_add_symbol
= NULL
;
5503 expr1
.X_add_number
= 1;
5507 #endif /* LOSING_COMPILER */
5512 macro_build ((char *) NULL
, &icnt
, NULL
,
5513 dbl
? "dmultu" : "multu",
5515 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5521 /* The MIPS assembler some times generates shifts and adds. I'm
5522 not trying to be that fancy. GCC should do this for us
5524 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5525 macro_build ((char *) NULL
, &icnt
, NULL
,
5526 dbl
? "dmult" : "mult",
5528 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5534 mips_emit_delays (true);
5535 ++mips_opts
.noreorder
;
5536 mips_any_noreorder
= 1;
5537 macro_build ((char *) NULL
, &icnt
, NULL
,
5538 dbl
? "dmult" : "mult",
5540 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5541 macro_build ((char *) NULL
, &icnt
, NULL
,
5542 dbl
? "dsra32" : "sra",
5543 "d,w,<", dreg
, dreg
, 31);
5544 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5546 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5549 expr1
.X_add_number
= 8;
5550 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5551 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5554 --mips_opts
.noreorder
;
5555 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5561 mips_emit_delays (true);
5562 ++mips_opts
.noreorder
;
5563 mips_any_noreorder
= 1;
5564 macro_build ((char *) NULL
, &icnt
, NULL
,
5565 dbl
? "dmultu" : "multu",
5567 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5568 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5570 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5573 expr1
.X_add_number
= 8;
5574 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5575 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5576 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5578 --mips_opts
.noreorder
;
5582 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5583 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5584 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5586 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5590 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5591 (int) (imm_expr
.X_add_number
& 0x1f));
5592 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5593 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5594 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5598 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5599 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5600 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5602 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5606 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5607 (int) (imm_expr
.X_add_number
& 0x1f));
5608 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5609 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5610 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5614 assert (mips_opts
.isa
< 2);
5615 /* Even on a big endian machine $fn comes before $fn+1. We have
5616 to adjust when storing to memory. */
5617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5618 target_big_endian
? treg
+ 1 : treg
,
5619 (int) BFD_RELOC_LO16
, breg
);
5620 offset_expr
.X_add_number
+= 4;
5621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5622 target_big_endian
? treg
: treg
+ 1,
5623 (int) BFD_RELOC_LO16
, breg
);
5628 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5629 treg
, (int) BFD_RELOC_LO16
);
5631 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5632 sreg
, (int) BFD_RELOC_LO16
);
5635 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5637 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5638 dreg
, (int) BFD_RELOC_LO16
);
5643 if (imm_expr
.X_add_number
== 0)
5645 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5646 sreg
, (int) BFD_RELOC_LO16
);
5651 as_warn ("Instruction %s: result is always false",
5653 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5656 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5658 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5659 sreg
, (int) BFD_RELOC_LO16
);
5662 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5664 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5665 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5666 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5667 "t,r,j", dreg
, sreg
,
5668 (int) BFD_RELOC_LO16
);
5673 load_register (&icnt
, AT
, &imm_expr
, 0);
5674 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5678 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5679 (int) BFD_RELOC_LO16
);
5684 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5690 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5691 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5692 (int) BFD_RELOC_LO16
);
5695 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5697 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5699 macro_build ((char *) NULL
, &icnt
, &expr1
,
5700 mask
== M_SGE_I
? "slti" : "sltiu",
5701 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5706 load_register (&icnt
, AT
, &imm_expr
, 0);
5707 macro_build ((char *) NULL
, &icnt
, NULL
,
5708 mask
== M_SGE_I
? "slt" : "sltu",
5709 "d,v,t", dreg
, sreg
, AT
);
5712 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5713 (int) BFD_RELOC_LO16
);
5718 case M_SGT
: /* sreg > treg <==> treg < sreg */
5724 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5727 case M_SGT_I
: /* sreg > I <==> I < sreg */
5733 load_register (&icnt
, AT
, &imm_expr
, 0);
5734 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5737 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5743 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5744 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5745 (int) BFD_RELOC_LO16
);
5748 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5754 load_register (&icnt
, AT
, &imm_expr
, 0);
5755 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5756 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5757 (int) BFD_RELOC_LO16
);
5761 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5763 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5764 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5767 load_register (&icnt
, AT
, &imm_expr
, 0);
5768 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5772 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5774 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5775 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5778 load_register (&icnt
, AT
, &imm_expr
, 0);
5779 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5785 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5788 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5792 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5794 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5800 if (imm_expr
.X_add_number
== 0)
5802 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5808 as_warn ("Instruction %s: result is always true",
5810 macro_build ((char *) NULL
, &icnt
, &expr1
,
5811 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5812 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5815 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5817 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5818 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5821 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5823 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5824 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5825 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5826 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5831 load_register (&icnt
, AT
, &imm_expr
, 0);
5832 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5836 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5844 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5846 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5847 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5848 dbl
? "daddi" : "addi",
5849 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5852 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5853 macro_build ((char *) NULL
, &icnt
, NULL
,
5854 dbl
? "dsub" : "sub",
5855 "d,v,t", dreg
, sreg
, AT
);
5861 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5863 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5864 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5865 dbl
? "daddiu" : "addiu",
5866 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5869 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5870 macro_build ((char *) NULL
, &icnt
, NULL
,
5871 dbl
? "dsubu" : "subu",
5872 "d,v,t", dreg
, sreg
, AT
);
5893 load_register (&icnt
, AT
, &imm_expr
, 0);
5894 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5899 assert (mips_opts
.isa
< 2);
5900 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5901 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5904 * Is the double cfc1 instruction a bug in the mips assembler;
5905 * or is there a reason for it?
5907 mips_emit_delays (true);
5908 ++mips_opts
.noreorder
;
5909 mips_any_noreorder
= 1;
5910 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5911 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5912 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5913 expr1
.X_add_number
= 3;
5914 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5915 (int) BFD_RELOC_LO16
);
5916 expr1
.X_add_number
= 2;
5917 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5918 (int) BFD_RELOC_LO16
);
5919 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5920 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5921 macro_build ((char *) NULL
, &icnt
, NULL
,
5922 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5923 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5924 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5925 --mips_opts
.noreorder
;
5934 if (offset_expr
.X_add_number
>= 0x7fff)
5935 as_bad ("operand overflow");
5936 /* avoid load delay */
5937 if (! target_big_endian
)
5938 offset_expr
.X_add_number
+= 1;
5939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5940 (int) BFD_RELOC_LO16
, breg
);
5941 if (! target_big_endian
)
5942 offset_expr
.X_add_number
-= 1;
5944 offset_expr
.X_add_number
+= 1;
5945 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5946 (int) BFD_RELOC_LO16
, breg
);
5947 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5948 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5961 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5962 as_bad ("operand overflow");
5963 if (! target_big_endian
)
5964 offset_expr
.X_add_number
+= off
;
5965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5966 (int) BFD_RELOC_LO16
, breg
);
5967 if (! target_big_endian
)
5968 offset_expr
.X_add_number
-= off
;
5970 offset_expr
.X_add_number
+= off
;
5971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5972 (int) BFD_RELOC_LO16
, breg
);
5985 load_address (&icnt
, AT
, &offset_expr
);
5987 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5988 mips_opts
.isa
< 3 ? "addu" : "daddu",
5989 "d,v,t", AT
, AT
, breg
);
5990 if (! target_big_endian
)
5991 expr1
.X_add_number
= off
;
5993 expr1
.X_add_number
= 0;
5994 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5995 (int) BFD_RELOC_LO16
, AT
);
5996 if (! target_big_endian
)
5997 expr1
.X_add_number
= 0;
5999 expr1
.X_add_number
= off
;
6000 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6001 (int) BFD_RELOC_LO16
, AT
);
6006 load_address (&icnt
, AT
, &offset_expr
);
6008 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6009 mips_opts
.isa
< 3 ? "addu" : "daddu",
6010 "d,v,t", AT
, AT
, breg
);
6011 if (target_big_endian
)
6012 expr1
.X_add_number
= 0;
6013 macro_build ((char *) NULL
, &icnt
, &expr1
,
6014 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6015 (int) BFD_RELOC_LO16
, AT
);
6016 if (target_big_endian
)
6017 expr1
.X_add_number
= 1;
6019 expr1
.X_add_number
= 0;
6020 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6021 (int) BFD_RELOC_LO16
, AT
);
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6029 if (offset_expr
.X_add_number
>= 0x7fff)
6030 as_bad ("operand overflow");
6031 if (target_big_endian
)
6032 offset_expr
.X_add_number
+= 1;
6033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6034 (int) BFD_RELOC_LO16
, breg
);
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6036 if (target_big_endian
)
6037 offset_expr
.X_add_number
-= 1;
6039 offset_expr
.X_add_number
+= 1;
6040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6041 (int) BFD_RELOC_LO16
, breg
);
6054 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6055 as_bad ("operand overflow");
6056 if (! target_big_endian
)
6057 offset_expr
.X_add_number
+= off
;
6058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6059 (int) BFD_RELOC_LO16
, breg
);
6060 if (! target_big_endian
)
6061 offset_expr
.X_add_number
-= off
;
6063 offset_expr
.X_add_number
+= off
;
6064 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6065 (int) BFD_RELOC_LO16
, breg
);
6078 load_address (&icnt
, AT
, &offset_expr
);
6080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6081 mips_opts
.isa
< 3 ? "addu" : "daddu",
6082 "d,v,t", AT
, AT
, breg
);
6083 if (! target_big_endian
)
6084 expr1
.X_add_number
= off
;
6086 expr1
.X_add_number
= 0;
6087 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6088 (int) BFD_RELOC_LO16
, AT
);
6089 if (! target_big_endian
)
6090 expr1
.X_add_number
= 0;
6092 expr1
.X_add_number
= off
;
6093 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6094 (int) BFD_RELOC_LO16
, AT
);
6098 load_address (&icnt
, AT
, &offset_expr
);
6100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6101 mips_opts
.isa
< 3 ? "addu" : "daddu",
6102 "d,v,t", AT
, AT
, breg
);
6103 if (! target_big_endian
)
6104 expr1
.X_add_number
= 0;
6105 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6106 (int) BFD_RELOC_LO16
, AT
);
6107 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6109 if (! target_big_endian
)
6110 expr1
.X_add_number
= 1;
6112 expr1
.X_add_number
= 0;
6113 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6114 (int) BFD_RELOC_LO16
, AT
);
6115 if (! target_big_endian
)
6116 expr1
.X_add_number
= 0;
6118 expr1
.X_add_number
= 1;
6119 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6120 (int) BFD_RELOC_LO16
, AT
);
6121 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6123 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6128 /* FIXME: Check if this is one of the itbl macros, since they
6129 are added dynamically. */
6130 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6134 as_warn ("Macro used $at after \".set noat\"");
6137 /* Implement macros in mips16 mode. */
6141 struct mips_cl_insn
*ip
;
6144 int xreg
, yreg
, zreg
, tmp
;
6148 const char *s
, *s2
, *s3
;
6150 mask
= ip
->insn_mo
->mask
;
6152 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6153 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6154 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6158 expr1
.X_op
= O_constant
;
6159 expr1
.X_op_symbol
= NULL
;
6160 expr1
.X_add_symbol
= NULL
;
6161 expr1
.X_add_number
= 1;
6180 mips_emit_delays (true);
6181 ++mips_opts
.noreorder
;
6182 mips_any_noreorder
= 1;
6183 macro_build ((char *) NULL
, &icnt
, NULL
,
6184 dbl
? "ddiv" : "div",
6185 "0,x,y", xreg
, yreg
);
6186 expr1
.X_add_number
= 2;
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6188 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6189 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6190 since that causes an overflow. We should do that as well,
6191 but I don't see how to do the comparisons without a temporary
6193 --mips_opts
.noreorder
;
6194 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6213 mips_emit_delays (true);
6214 ++mips_opts
.noreorder
;
6215 mips_any_noreorder
= 1;
6216 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6217 expr1
.X_add_number
= 2;
6218 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6219 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6220 --mips_opts
.noreorder
;
6221 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6229 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6230 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6231 dbl
? "daddiu" : "addiu",
6232 "y,x,4", yreg
, xreg
);
6236 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6237 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6242 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6243 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6266 goto do_reverse_branch
;
6270 goto do_reverse_branch
;
6282 goto do_reverse_branch
;
6293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6322 goto do_addone_branch_i
;
6327 goto do_addone_branch_i
;
6342 goto do_addone_branch_i
;
6349 ++imm_expr
.X_add_number
;
6352 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6357 expr1
.X_add_number
= 0;
6358 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6360 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6361 "move", "y,X", xreg
, yreg
);
6362 expr1
.X_add_number
= 2;
6363 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6365 "neg", "x,w", xreg
, xreg
);
6369 /* This routine assembles an instruction into its binary format. As a
6370 side effect, it sets one of the global variables imm_reloc or
6371 offset_reloc to the type of relocation to do if one of the operands
6372 is an address expression. */
6377 struct mips_cl_insn
*ip
;
6382 struct mips_opcode
*insn
;
6385 unsigned int lastregno
= 0;
6390 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6395 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6397 insn_error
= "unrecognized opcode";
6405 assert (strcmp (insn
->name
, str
) == 0);
6407 if (insn
->pinfo
== INSN_MACRO
)
6408 insn_isa
= insn
->match
;
6409 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6411 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6413 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6418 if (insn_isa
> mips_opts
.isa
6419 || (insn
->pinfo
!= INSN_MACRO
6420 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6422 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6424 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6426 /* start-sanitize-r5900 */
6427 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6429 /* end-sanitize-r5900 */
6432 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6433 && strcmp (insn
->name
, insn
[1].name
) == 0)
6438 if (insn_isa
<= mips_opts
.isa
)
6439 insn_error
= "opcode not supported on this processor";
6442 static char buf
[100];
6444 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6451 ip
->insn_opcode
= insn
->match
;
6452 for (args
= insn
->args
;; ++args
)
6458 case '\0': /* end of args */
6471 ip
->insn_opcode
|= lastregno
<< 21;
6476 ip
->insn_opcode
|= lastregno
<< 16;
6480 ip
->insn_opcode
|= lastregno
<< 11;
6486 /* handle optional base register.
6487 Either the base register is omitted or
6488 we must have a left paren. */
6489 /* this is dependent on the next operand specifier
6490 is a 'b' for base register */
6491 assert (args
[1] == 'b');
6495 case ')': /* these must match exactly */
6500 case '<': /* must be at least one digit */
6502 * According to the manual, if the shift amount is greater
6503 * than 31 or less than 0 the the shift amount should be
6504 * mod 32. In reality the mips assembler issues an error.
6505 * We issue a warning and mask out all but the low 5 bits.
6507 my_getExpression (&imm_expr
, s
);
6508 check_absolute_expr (ip
, &imm_expr
);
6509 if ((unsigned long) imm_expr
.X_add_number
> 31)
6511 as_warn ("Improper shift amount (%ld)",
6512 (long) imm_expr
.X_add_number
);
6513 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6515 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6516 imm_expr
.X_op
= O_absent
;
6520 case '>': /* shift amount minus 32 */
6521 my_getExpression (&imm_expr
, s
);
6522 check_absolute_expr (ip
, &imm_expr
);
6523 if ((unsigned long) imm_expr
.X_add_number
< 32
6524 || (unsigned long) imm_expr
.X_add_number
> 63)
6526 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6527 imm_expr
.X_op
= O_absent
;
6531 case 'k': /* cache code */
6532 case 'h': /* prefx code */
6533 my_getExpression (&imm_expr
, s
);
6534 check_absolute_expr (ip
, &imm_expr
);
6535 if ((unsigned long) imm_expr
.X_add_number
> 31)
6537 as_warn ("Invalid value for `%s' (%lu)",
6539 (unsigned long) imm_expr
.X_add_number
);
6540 imm_expr
.X_add_number
&= 0x1f;
6543 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6545 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6546 imm_expr
.X_op
= O_absent
;
6550 case 'c': /* break code */
6551 my_getExpression (&imm_expr
, s
);
6552 check_absolute_expr (ip
, &imm_expr
);
6553 if ((unsigned) imm_expr
.X_add_number
> 1023)
6554 as_warn ("Illegal break code (%ld)",
6555 (long) imm_expr
.X_add_number
);
6556 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6557 imm_expr
.X_op
= O_absent
;
6561 case 'B': /* syscall code */
6562 my_getExpression (&imm_expr
, s
);
6563 check_absolute_expr (ip
, &imm_expr
);
6564 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6565 as_warn ("Illegal syscall code (%ld)",
6566 (long) imm_expr
.X_add_number
);
6567 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6568 imm_expr
.X_op
= O_absent
;
6572 case 'C': /* Coprocessor code */
6573 my_getExpression (&imm_expr
, s
);
6574 check_absolute_expr (ip
, &imm_expr
);
6575 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6577 as_warn ("Coproccesor code > 25 bits (%ld)",
6578 (long) imm_expr
.X_add_number
);
6579 imm_expr
.X_add_number
&= ((1<<25) - 1);
6581 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6582 imm_expr
.X_op
= O_absent
;
6586 case 'b': /* base register */
6587 case 'd': /* destination register */
6588 case 's': /* source register */
6589 case 't': /* target register */
6590 case 'r': /* both target and source */
6591 case 'v': /* both dest and source */
6592 case 'w': /* both dest and target */
6593 case 'E': /* coprocessor target register */
6594 case 'G': /* coprocessor destination register */
6595 case 'x': /* ignore register name */
6596 case 'z': /* must be zero register */
6610 while (isdigit (*s
));
6612 as_bad ("Invalid register number (%d)", regno
);
6614 else if (*args
== 'E' || *args
== 'G')
6618 if (s
[1] == 'f' && s
[2] == 'p')
6623 else if (s
[1] == 's' && s
[2] == 'p')
6628 else if (s
[1] == 'g' && s
[2] == 'p')
6633 else if (s
[1] == 'a' && s
[2] == 't')
6638 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6643 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6648 else if (itbl_have_entries
)
6653 p
= s
+1; /* advance past '$' */
6654 n
= itbl_get_field (&p
); /* n is name */
6656 /* See if this is a register defined in an
6658 r
= itbl_get_reg_val (n
);
6661 /* Get_field advances to the start of
6662 the next field, so we need to back
6663 rack to the end of the last field. */
6667 s
= strchr (s
,'\0');
6680 as_warn ("Used $at without \".set noat\"");
6686 if (c
== 'r' || c
== 'v' || c
== 'w')
6693 /* 'z' only matches $0. */
6694 if (c
== 'z' && regno
!= 0)
6697 /* Now that we have assembled one operand, we use the args string
6698 * to figure out where it goes in the instruction. */
6705 ip
->insn_opcode
|= regno
<< 21;
6709 ip
->insn_opcode
|= regno
<< 11;
6714 ip
->insn_opcode
|= regno
<< 16;
6717 /* This case exists because on the r3000 trunc
6718 expands into a macro which requires a gp
6719 register. On the r6000 or r4000 it is
6720 assembled into a single instruction which
6721 ignores the register. Thus the insn version
6722 is MIPS_ISA2 and uses 'x', and the macro
6723 version is MIPS_ISA1 and uses 't'. */
6726 /* This case is for the div instruction, which
6727 acts differently if the destination argument
6728 is $0. This only matches $0, and is checked
6729 outside the switch. */
6732 /* Itbl operand; not yet implemented. FIXME ?? */
6734 /* What about all other operands like 'i', which
6735 can be specified in the opcode table? */
6745 ip
->insn_opcode
|= lastregno
<< 21;
6748 ip
->insn_opcode
|= lastregno
<< 16;
6753 case 'D': /* floating point destination register */
6754 case 'S': /* floating point source register */
6755 case 'T': /* floating point target register */
6756 case 'R': /* floating point source register */
6760 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6770 while (isdigit (*s
));
6773 as_bad ("Invalid float register number (%d)", regno
);
6775 if ((regno
& 1) != 0
6776 && mips_opts
.isa
< 3
6777 && ! (strcmp (str
, "mtc1") == 0
6778 || strcmp (str
, "mfc1") == 0
6779 || strcmp (str
, "lwc1") == 0
6780 || strcmp (str
, "swc1") == 0
6781 || strcmp (str
, "l.s") == 0
6782 || strcmp (str
, "s.s") == 0))
6783 as_warn ("Float register should be even, was %d",
6791 if (c
== 'V' || c
== 'W')
6801 ip
->insn_opcode
|= regno
<< 6;
6805 ip
->insn_opcode
|= regno
<< 11;
6809 ip
->insn_opcode
|= regno
<< 16;
6812 ip
->insn_opcode
|= regno
<< 21;
6821 ip
->insn_opcode
|= lastregno
<< 11;
6824 ip
->insn_opcode
|= lastregno
<< 16;
6830 my_getExpression (&imm_expr
, s
);
6831 if (imm_expr
.X_op
!= O_big
6832 && imm_expr
.X_op
!= O_constant
)
6833 insn_error
= "absolute expression required";
6838 my_getExpression (&offset_expr
, s
);
6839 imm_reloc
= BFD_RELOC_32
;
6851 unsigned char temp
[8];
6853 unsigned int length
;
6858 /* These only appear as the last operand in an
6859 instruction, and every instruction that accepts
6860 them in any variant accepts them in all variants.
6861 This means we don't have to worry about backing out
6862 any changes if the instruction does not match.
6864 The difference between them is the size of the
6865 floating point constant and where it goes. For 'F'
6866 and 'L' the constant is 64 bits; for 'f' and 'l' it
6867 is 32 bits. Where the constant is placed is based
6868 on how the MIPS assembler does things:
6871 f -- immediate value
6874 The .lit4 and .lit8 sections are only used if
6875 permitted by the -G argument.
6877 When generating embedded PIC code, we use the
6878 .lit8 section but not the .lit4 section (we can do
6879 .lit4 inline easily; we need to put .lit8
6880 somewhere in the data segment, and using .lit8
6881 permits the linker to eventually combine identical
6884 f64
= *args
== 'F' || *args
== 'L';
6886 save_in
= input_line_pointer
;
6887 input_line_pointer
= s
;
6888 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6890 s
= input_line_pointer
;
6891 input_line_pointer
= save_in
;
6892 if (err
!= NULL
&& *err
!= '\0')
6894 as_bad ("Bad floating point constant: %s", err
);
6895 memset (temp
, '\0', sizeof temp
);
6896 length
= f64
? 8 : 4;
6899 assert (length
== (f64
? 8 : 4));
6903 && (! USE_GLOBAL_POINTER_OPT
6904 || mips_pic
== EMBEDDED_PIC
6905 || g_switch_value
< 4)
6908 imm_expr
.X_op
= O_constant
;
6909 if (! target_big_endian
)
6910 imm_expr
.X_add_number
=
6911 (((((((int) temp
[3] << 8)
6916 imm_expr
.X_add_number
=
6917 (((((((int) temp
[0] << 8)
6924 const char *newname
;
6927 /* Switch to the right section. */
6929 subseg
= now_subseg
;
6932 default: /* unused default case avoids warnings. */
6934 newname
= RDATA_SECTION_NAME
;
6935 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6939 newname
= RDATA_SECTION_NAME
;
6942 assert (!USE_GLOBAL_POINTER_OPT
6943 || g_switch_value
>= 4);
6947 new_seg
= subseg_new (newname
, (subsegT
) 0);
6948 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6949 bfd_set_section_flags (stdoutput
, new_seg
,
6954 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
6955 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
6956 && strcmp (TARGET_OS
, "elf") != 0)
6957 record_alignment (new_seg
, 4);
6959 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6961 as_bad ("Can't use floating point insn in this section");
6963 /* Set the argument to the current address in the
6965 offset_expr
.X_op
= O_symbol
;
6966 offset_expr
.X_add_symbol
=
6967 symbol_new ("L0\001", now_seg
,
6968 (valueT
) frag_now_fix (), frag_now
);
6969 offset_expr
.X_add_number
= 0;
6971 /* Put the floating point number into the section. */
6972 p
= frag_more ((int) length
);
6973 memcpy (p
, temp
, length
);
6975 /* Switch back to the original section. */
6976 subseg_set (seg
, subseg
);
6981 case 'i': /* 16 bit unsigned immediate */
6982 case 'j': /* 16 bit signed immediate */
6983 imm_reloc
= BFD_RELOC_LO16
;
6984 c
= my_getSmallExpression (&imm_expr
, s
);
6989 if (imm_expr
.X_op
== O_constant
)
6990 imm_expr
.X_add_number
=
6991 (imm_expr
.X_add_number
>> 16) & 0xffff;
6994 imm_reloc
= BFD_RELOC_HI16_S
;
6995 imm_unmatched_hi
= true;
6998 imm_reloc
= BFD_RELOC_HI16
;
7003 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7004 || ((imm_expr
.X_add_number
< 0
7005 || imm_expr
.X_add_number
>= 0x10000)
7006 && imm_expr
.X_op
== O_constant
))
7008 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7009 !strcmp (insn
->name
, insn
[1].name
))
7011 if (imm_expr
.X_op
!= O_constant
7012 && imm_expr
.X_op
!= O_big
)
7013 insn_error
= "absolute expression required";
7015 as_bad ("16 bit expression not in range 0..65535");
7023 /* The upper bound should be 0x8000, but
7024 unfortunately the MIPS assembler accepts numbers
7025 from 0x8000 to 0xffff and sign extends them, and
7026 we want to be compatible. We only permit this
7027 extended range for an instruction which does not
7028 provide any further alternates, since those
7029 alternates may handle other cases. People should
7030 use the numbers they mean, rather than relying on
7031 a mysterious sign extension. */
7032 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7033 strcmp (insn
->name
, insn
[1].name
) == 0);
7038 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7039 || ((imm_expr
.X_add_number
< -0x8000
7040 || imm_expr
.X_add_number
>= max
)
7041 && imm_expr
.X_op
== O_constant
)
7043 && imm_expr
.X_add_number
< 0
7044 && mips_opts
.isa
>= 3
7045 && imm_expr
.X_unsigned
7046 && sizeof (imm_expr
.X_add_number
) <= 4))
7050 if (imm_expr
.X_op
!= O_constant
7051 && imm_expr
.X_op
!= O_big
)
7052 insn_error
= "absolute expression required";
7054 as_bad ("16 bit expression not in range -32768..32767");
7060 case 'o': /* 16 bit offset */
7061 c
= my_getSmallExpression (&offset_expr
, s
);
7063 /* If this value won't fit into a 16 bit offset, then go
7064 find a macro that will generate the 32 bit offset
7065 code pattern. As a special hack, we accept the
7066 difference of two local symbols as a constant. This
7067 is required to suppose embedded PIC switches, which
7068 use an instruction which looks like
7069 lw $4,$L12-$LS12($4)
7070 The problem with handling this in a more general
7071 fashion is that the macro function doesn't expect to
7072 see anything which can be handled in a single
7073 constant instruction. */
7075 && (offset_expr
.X_op
!= O_constant
7076 || offset_expr
.X_add_number
>= 0x8000
7077 || offset_expr
.X_add_number
< -0x8000)
7078 && (mips_pic
!= EMBEDDED_PIC
7079 || offset_expr
.X_op
!= O_subtract
7080 || now_seg
!= text_section
7081 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7085 offset_reloc
= BFD_RELOC_LO16
;
7086 if (c
== 'h' || c
== 'H')
7088 assert (offset_expr
.X_op
== O_constant
);
7089 offset_expr
.X_add_number
=
7090 (offset_expr
.X_add_number
>> 16) & 0xffff;
7095 case 'p': /* pc relative offset */
7096 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7097 my_getExpression (&offset_expr
, s
);
7101 case 'u': /* upper 16 bits */
7102 c
= my_getSmallExpression (&imm_expr
, s
);
7103 if (imm_expr
.X_op
== O_constant
7104 && (imm_expr
.X_add_number
< 0
7105 || imm_expr
.X_add_number
>= 0x10000))
7106 as_bad ("lui expression not in range 0..65535");
7107 imm_reloc
= BFD_RELOC_LO16
;
7112 if (imm_expr
.X_op
== O_constant
)
7113 imm_expr
.X_add_number
=
7114 (imm_expr
.X_add_number
>> 16) & 0xffff;
7117 imm_reloc
= BFD_RELOC_HI16_S
;
7118 imm_unmatched_hi
= true;
7121 imm_reloc
= BFD_RELOC_HI16
;
7127 case 'a': /* 26 bit address */
7128 my_getExpression (&offset_expr
, s
);
7130 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7133 case 'N': /* 3 bit branch condition code */
7134 case 'M': /* 3 bit compare condition code */
7135 if (strncmp (s
, "$fcc", 4) != 0)
7145 while (isdigit (*s
));
7147 as_bad ("invalid condition code register $fcc%d", regno
);
7149 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7151 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7155 fprintf (stderr
, "bad char = '%c'\n", *args
);
7160 /* Args don't match. */
7161 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7162 !strcmp (insn
->name
, insn
[1].name
))
7168 insn_error
= "illegal operands";
7173 /* This routine assembles an instruction into its binary format when
7174 assembling for the mips16. As a side effect, it sets one of the
7175 global variables imm_reloc or offset_reloc to the type of
7176 relocation to do if one of the operands is an address expression.
7177 It also sets mips16_small and mips16_ext if the user explicitly
7178 requested a small or extended instruction. */
7183 struct mips_cl_insn
*ip
;
7187 struct mips_opcode
*insn
;
7190 unsigned int lastregno
= 0;
7195 mips16_small
= false;
7198 for (s
= str
; islower (*s
); ++s
)
7210 if (s
[1] == 't' && s
[2] == ' ')
7213 mips16_small
= true;
7217 else if (s
[1] == 'e' && s
[2] == ' ')
7226 insn_error
= "unknown opcode";
7230 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7231 mips16_small
= true;
7233 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7235 insn_error
= "unrecognized opcode";
7242 assert (strcmp (insn
->name
, str
) == 0);
7245 ip
->insn_opcode
= insn
->match
;
7246 ip
->use_extend
= false;
7247 imm_expr
.X_op
= O_absent
;
7248 imm_reloc
= BFD_RELOC_UNUSED
;
7249 offset_expr
.X_op
= O_absent
;
7250 offset_reloc
= BFD_RELOC_UNUSED
;
7251 for (args
= insn
->args
; 1; ++args
)
7258 /* In this switch statement we call break if we did not find
7259 a match, continue if we did find a match, or return if we
7268 /* Stuff the immediate value in now, if we can. */
7269 if (imm_expr
.X_op
== O_constant
7270 && imm_reloc
> BFD_RELOC_UNUSED
7271 && insn
->pinfo
!= INSN_MACRO
)
7273 mips16_immed ((char *) NULL
, 0,
7274 imm_reloc
- BFD_RELOC_UNUSED
,
7275 imm_expr
.X_add_number
, true, mips16_small
,
7276 mips16_ext
, &ip
->insn_opcode
,
7277 &ip
->use_extend
, &ip
->extend
);
7278 imm_expr
.X_op
= O_absent
;
7279 imm_reloc
= BFD_RELOC_UNUSED
;
7293 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7296 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7312 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7314 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7341 while (isdigit (*s
));
7344 as_bad ("invalid register number (%d)", regno
);
7350 if (s
[1] == 'f' && s
[2] == 'p')
7355 else if (s
[1] == 's' && s
[2] == 'p')
7360 else if (s
[1] == 'g' && s
[2] == 'p')
7365 else if (s
[1] == 'a' && s
[2] == 't')
7370 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7375 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7388 if (c
== 'v' || c
== 'w')
7390 regno
= mips16_to_32_reg_map
[lastregno
];
7404 regno
= mips32_to_16_reg_map
[regno
];
7409 regno
= ILLEGAL_REG
;
7414 regno
= ILLEGAL_REG
;
7419 regno
= ILLEGAL_REG
;
7424 if (regno
== AT
&& ! mips_opts
.noat
)
7425 as_warn ("used $at without \".set noat\"");
7432 if (regno
== ILLEGAL_REG
)
7439 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7443 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7446 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7449 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7455 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7458 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7459 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7469 if (strncmp (s
, "$pc", 3) == 0)
7493 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7495 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7496 and generate the appropriate reloc. If the text
7497 inside %gprel is not a symbol name with an
7498 optional offset, then we generate a normal reloc
7499 and will probably fail later. */
7500 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7501 if (imm_expr
.X_op
== O_symbol
)
7504 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7506 ip
->use_extend
= true;
7513 /* Just pick up a normal expression. */
7514 my_getExpression (&imm_expr
, s
);
7517 if (imm_expr
.X_op
== O_register
)
7519 /* What we thought was an expression turned out to
7522 if (s
[0] == '(' && args
[1] == '(')
7524 /* It looks like the expression was omitted
7525 before a register indirection, which means
7526 that the expression is implicitly zero. We
7527 still set up imm_expr, so that we handle
7528 explicit extensions correctly. */
7529 imm_expr
.X_op
= O_constant
;
7530 imm_expr
.X_add_number
= 0;
7531 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7538 /* We need to relax this instruction. */
7539 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7548 /* We use offset_reloc rather than imm_reloc for the PC
7549 relative operands. This lets macros with both
7550 immediate and address operands work correctly. */
7551 my_getExpression (&offset_expr
, s
);
7553 if (offset_expr
.X_op
== O_register
)
7556 /* We need to relax this instruction. */
7557 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7561 case '6': /* break code */
7562 my_getExpression (&imm_expr
, s
);
7563 check_absolute_expr (ip
, &imm_expr
);
7564 if ((unsigned long) imm_expr
.X_add_number
> 63)
7566 as_warn ("Invalid value for `%s' (%lu)",
7568 (unsigned long) imm_expr
.X_add_number
);
7569 imm_expr
.X_add_number
&= 0x3f;
7571 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7572 imm_expr
.X_op
= O_absent
;
7576 case 'a': /* 26 bit address */
7577 my_getExpression (&offset_expr
, s
);
7579 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7580 ip
->insn_opcode
<<= 16;
7583 case 'l': /* register list for entry macro */
7584 case 'L': /* register list for exit macro */
7594 int freg
, reg1
, reg2
;
7596 while (*s
== ' ' || *s
== ',')
7600 as_bad ("can't parse register list");
7612 while (isdigit (*s
))
7634 as_bad ("invalid register list");
7639 while (isdigit (*s
))
7646 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7651 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7656 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7657 mask
|= (reg2
- 3) << 3;
7658 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7659 mask
|= (reg2
- 15) << 1;
7660 else if (reg1
== 31 && reg2
== 31)
7664 as_bad ("invalid register list");
7668 /* The mask is filled in in the opcode table for the
7669 benefit of the disassembler. We remove it before
7670 applying the actual mask. */
7671 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7672 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7676 case 'e': /* extend code */
7677 my_getExpression (&imm_expr
, s
);
7678 check_absolute_expr (ip
, &imm_expr
);
7679 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7681 as_warn ("Invalid value for `%s' (%lu)",
7683 (unsigned long) imm_expr
.X_add_number
);
7684 imm_expr
.X_add_number
&= 0x7ff;
7686 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7687 imm_expr
.X_op
= O_absent
;
7697 /* Args don't match. */
7698 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7699 strcmp (insn
->name
, insn
[1].name
) == 0)
7706 insn_error
= "illegal operands";
7712 /* This structure holds information we know about a mips16 immediate
7715 struct mips16_immed_operand
7717 /* The type code used in the argument string in the opcode table. */
7719 /* The number of bits in the short form of the opcode. */
7721 /* The number of bits in the extended form of the opcode. */
7723 /* The amount by which the short form is shifted when it is used;
7724 for example, the sw instruction has a shift count of 2. */
7726 /* The amount by which the short form is shifted when it is stored
7727 into the instruction code. */
7729 /* Non-zero if the short form is unsigned. */
7731 /* Non-zero if the extended form is unsigned. */
7733 /* Non-zero if the value is PC relative. */
7737 /* The mips16 immediate operand types. */
7739 static const struct mips16_immed_operand mips16_immed_operands
[] =
7741 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7742 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7743 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7744 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7745 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7746 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7747 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7748 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7749 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7750 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7751 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7752 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7753 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7754 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7755 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7756 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7757 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7758 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7759 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7760 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7761 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7764 #define MIPS16_NUM_IMMED \
7765 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7767 /* Handle a mips16 instruction with an immediate value. This or's the
7768 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7769 whether an extended value is needed; if one is needed, it sets
7770 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7771 If SMALL is true, an unextended opcode was explicitly requested.
7772 If EXT is true, an extended opcode was explicitly requested. If
7773 WARN is true, warn if EXT does not match reality. */
7776 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7785 unsigned long *insn
;
7786 boolean
*use_extend
;
7787 unsigned short *extend
;
7789 register const struct mips16_immed_operand
*op
;
7790 int mintiny
, maxtiny
;
7793 op
= mips16_immed_operands
;
7794 while (op
->type
!= type
)
7797 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7802 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7805 maxtiny
= 1 << op
->nbits
;
7810 maxtiny
= (1 << op
->nbits
) - 1;
7815 mintiny
= - (1 << (op
->nbits
- 1));
7816 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7819 /* Branch offsets have an implicit 0 in the lowest bit. */
7820 if (type
== 'p' || type
== 'q')
7823 if ((val
& ((1 << op
->shift
) - 1)) != 0
7824 || val
< (mintiny
<< op
->shift
)
7825 || val
> (maxtiny
<< op
->shift
))
7830 if (warn
&& ext
&& ! needext
)
7831 as_warn_where (file
, line
, "extended operand requested but not required");
7832 if (small
&& needext
)
7833 as_bad_where (file
, line
, "invalid unextended operand value");
7835 if (small
|| (! ext
&& ! needext
))
7839 *use_extend
= false;
7840 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7841 insnval
<<= op
->op_shift
;
7846 long minext
, maxext
;
7852 maxext
= (1 << op
->extbits
) - 1;
7856 minext
= - (1 << (op
->extbits
- 1));
7857 maxext
= (1 << (op
->extbits
- 1)) - 1;
7859 if (val
< minext
|| val
> maxext
)
7860 as_bad_where (file
, line
,
7861 "operand value out of range for instruction");
7864 if (op
->extbits
== 16)
7866 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7869 else if (op
->extbits
== 15)
7871 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7876 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7880 *extend
= (unsigned short) extval
;
7889 my_getSmallExpression (ep
, str
)
7900 ((str
[1] == 'h' && str
[2] == 'i')
7901 || (str
[1] == 'H' && str
[2] == 'I')
7902 || (str
[1] == 'l' && str
[2] == 'o'))
7914 * A small expression may be followed by a base register.
7915 * Scan to the end of this operand, and then back over a possible
7916 * base register. Then scan the small expression up to that
7917 * point. (Based on code in sparc.c...)
7919 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7921 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7923 if (isdigit (sp
[-2]))
7925 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7927 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7933 else if (sp
- 5 >= str
7936 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7937 || (sp
[-3] == 's' && sp
[-2] == 'p')
7938 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7939 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7945 /* no expression means zero offset */
7948 /* %xx(reg) is an error */
7949 ep
->X_op
= O_absent
;
7954 ep
->X_op
= O_constant
;
7957 ep
->X_add_symbol
= NULL
;
7958 ep
->X_op_symbol
= NULL
;
7959 ep
->X_add_number
= 0;
7964 my_getExpression (ep
, str
);
7971 my_getExpression (ep
, str
);
7972 return c
; /* => %hi or %lo encountered */
7976 my_getExpression (ep
, str
)
7982 save_in
= input_line_pointer
;
7983 input_line_pointer
= str
;
7985 expr_end
= input_line_pointer
;
7986 input_line_pointer
= save_in
;
7988 /* If we are in mips16 mode, and this is an expression based on `.',
7989 then we bump the value of the symbol by 1 since that is how other
7990 text symbols are handled. We don't bother to handle complex
7991 expressions, just `.' plus or minus a constant. */
7992 if (mips_opts
.mips16
7993 && ep
->X_op
== O_symbol
7994 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7995 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7996 && ep
->X_add_symbol
->sy_frag
== frag_now
7997 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7998 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7999 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8002 /* Turn a string in input_line_pointer into a floating point constant
8003 of type type, and store the appropriate bytes in *litP. The number
8004 of LITTLENUMS emitted is stored in *sizeP . An error message is
8005 returned, or NULL on OK. */
8008 md_atof (type
, litP
, sizeP
)
8014 LITTLENUM_TYPE words
[4];
8030 return "bad call to md_atof";
8033 t
= atof_ieee (input_line_pointer
, type
, words
);
8035 input_line_pointer
= t
;
8039 if (! target_big_endian
)
8041 for (i
= prec
- 1; i
>= 0; i
--)
8043 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8049 for (i
= 0; i
< prec
; i
++)
8051 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8060 md_number_to_chars (buf
, val
, n
)
8065 if (target_big_endian
)
8066 number_to_chars_bigendian (buf
, val
, n
);
8068 number_to_chars_littleendian (buf
, val
, n
);
8071 CONST
char *md_shortopts
= "O::g::G:";
8073 struct option md_longopts
[] = {
8074 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8075 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8076 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8077 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8078 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8079 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8080 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8081 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8082 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8083 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8084 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8085 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8086 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8087 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8088 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8089 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8090 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8091 {"break", no_argument
, NULL
, OPTION_BREAK
},
8092 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8093 #define OPTION_EB (OPTION_MD_BASE + 11)
8094 {"EB", no_argument
, NULL
, OPTION_EB
},
8095 #define OPTION_EL (OPTION_MD_BASE + 12)
8096 {"EL", no_argument
, NULL
, OPTION_EL
},
8097 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8098 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8099 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8100 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8101 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8102 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8103 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8104 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8105 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8106 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8107 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8108 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8109 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8110 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8111 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8112 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8113 /* start-sanitize-r5900 */
8114 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8115 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8116 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8117 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8118 /* end-sanitize-r5900 */
8120 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8121 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8122 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8123 #define OPTION_32 (OPTION_MD_BASE + 20)
8124 #define OPTION_64 (OPTION_MD_BASE + 21)
8126 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8127 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8128 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8129 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8130 {"32", no_argument
, NULL
, OPTION_32
},
8131 {"64", no_argument
, NULL
, OPTION_64
},
8134 {NULL
, no_argument
, NULL
, 0}
8136 size_t md_longopts_size
= sizeof(md_longopts
);
8139 md_parse_option (c
, arg
)
8154 target_big_endian
= 1;
8158 target_big_endian
= 0;
8162 if (arg
&& arg
[1] == '0')
8172 mips_debug
= atoi (arg
);
8173 /* When the MIPS assembler sees -g or -g2, it does not do
8174 optimizations which limit full symbolic debugging. We take
8175 that to be equivalent to -O0. */
8176 if (mips_debug
== 2)
8208 /* Identify the processor type */
8210 if (strcmp (p
, "default") == 0
8211 || strcmp (p
, "DEFAULT") == 0)
8217 /* We need to cope with the various "vr" prefixes for the 4300
8219 if (*p
== 'v' || *p
== 'V')
8225 if (*p
== 'r' || *p
== 'R')
8232 if (strcmp (p
, "10000") == 0
8233 || strcmp (p
, "10k") == 0
8234 || strcmp (p
, "10K") == 0)
8239 if (strcmp (p
, "2000") == 0
8240 || strcmp (p
, "2k") == 0
8241 || strcmp (p
, "2K") == 0)
8246 if (strcmp (p
, "3000") == 0
8247 || strcmp (p
, "3k") == 0
8248 || strcmp (p
, "3K") == 0)
8253 if (strcmp (p
, "4000") == 0
8254 || strcmp (p
, "4k") == 0
8255 || strcmp (p
, "4K") == 0)
8257 else if (strcmp (p
, "4100") == 0)
8263 else if (strcmp (p
, "4300") == 0)
8265 else if (strcmp (p
, "4400") == 0)
8267 else if (strcmp (p
, "4600") == 0)
8269 else if (strcmp (p
, "4650") == 0)
8275 else if (strcmp (p
, "4010") == 0)
8284 if (strcmp (p
, "5000") == 0
8285 || strcmp (p
, "5k") == 0
8286 || strcmp (p
, "5K") == 0)
8288 /* start-sanitize-r5900 */
8289 else if (strcmp (p
, "5900") == 0)
8291 /* end-sanitize-r5900 */
8295 if (strcmp (p
, "6000") == 0
8296 || strcmp (p
, "6k") == 0
8297 || strcmp (p
, "6K") == 0)
8302 if (strcmp (p
, "8000") == 0
8303 || strcmp (p
, "8k") == 0
8304 || strcmp (p
, "8K") == 0)
8309 if (strcmp (p
, "orion") == 0)
8314 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8316 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8322 as_bad ("invalid architecture -mcpu=%s", arg
);
8333 case OPTION_NO_M4650
:
8341 case OPTION_NO_M4010
:
8349 case OPTION_NO_M4100
:
8353 /* start-sanitize-r5900 */
8358 case OPTION_NO_M5900
:
8361 /* end-sanitize-r5900 */
8364 mips_opts
.mips16
= 1;
8365 mips_no_prev_insn (false);
8368 case OPTION_NO_MIPS16
:
8369 mips_opts
.mips16
= 0;
8370 mips_no_prev_insn (false);
8373 case OPTION_MEMBEDDED_PIC
:
8374 mips_pic
= EMBEDDED_PIC
;
8375 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8377 as_bad ("-G may not be used with embedded PIC code");
8380 g_switch_value
= 0x7fffffff;
8383 /* When generating ELF code, we permit -KPIC and -call_shared to
8384 select SVR4_PIC, and -non_shared to select no PIC. This is
8385 intended to be compatible with Irix 5. */
8386 case OPTION_CALL_SHARED
:
8387 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8389 as_bad ("-call_shared is supported only for ELF format");
8392 mips_pic
= SVR4_PIC
;
8393 if (g_switch_seen
&& g_switch_value
!= 0)
8395 as_bad ("-G may not be used with SVR4 PIC code");
8401 case OPTION_NON_SHARED
:
8402 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8404 as_bad ("-non_shared is supported only for ELF format");
8410 /* The -xgot option tells the assembler to use 32 offsets when
8411 accessing the got in SVR4_PIC mode. It is for Irix
8418 if (! USE_GLOBAL_POINTER_OPT
)
8420 as_bad ("-G is not supported for this configuration");
8423 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8425 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8429 g_switch_value
= atoi (arg
);
8433 /* The -32 and -64 options tell the assembler to output the 32
8434 bit or the 64 bit MIPS ELF format. */
8441 const char **list
, **l
;
8443 list
= bfd_target_list ();
8444 for (l
= list
; *l
!= NULL
; l
++)
8445 if (strcmp (*l
, "elf64-bigmips") == 0
8446 || strcmp (*l
, "elf64-littlemips") == 0)
8449 as_fatal ("No compiled in support for 64 bit object file format");
8463 md_show_usage (stream
)
8468 -membedded-pic generate embedded position independent code\n\
8469 -EB generate big endian output\n\
8470 -EL generate little endian output\n\
8471 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8472 -G NUM allow referencing objects up to NUM bytes\n\
8473 implicitly with the gp register [default 8]\n");
8475 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8476 -mips2, -mcpu=r6000 generate code for r6000\n\
8477 -mips3, -mcpu=r4000 generate code for r4000\n\
8478 -mips4, -mcpu=r8000 generate code for r8000\n\
8479 -mcpu=vr4300 generate code for vr4300\n\
8480 -mcpu=vr4100 generate code for vr4100\n\
8481 -m4650 permit R4650 instructions\n\
8482 -no-m4650 do not permit R4650 instructions\n\
8483 -m4010 permit R4010 instructions\n\
8484 -no-m4010 do not permit R4010 instructions\n\
8485 -m4100 permit VR4100 instructions\n\
8486 -no-m4100 do not permit VR4100 instructions\n");
8488 -mips16 generate mips16 instructions\n\
8489 -no-mips16 do not generate mips16 instructions\n");
8491 -O0 remove unneeded NOPs, do not swap branches\n\
8492 -O remove unneeded NOPs and swap branches\n\
8493 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8494 --break, --no-trap break exception on div by 0 and mult overflow\n");
8497 -KPIC, -call_shared generate SVR4 position independent code\n\
8498 -non_shared do not generate position independent code\n\
8499 -xgot assume a 32 bit GOT\n\
8500 -32 create 32 bit object file (default)\n\
8501 -64 create 64 bit object file\n");
8506 mips_init_after_args ()
8508 /* initialize opcodes */
8509 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8510 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8514 md_pcrel_from (fixP
)
8517 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8518 && fixP
->fx_addsy
!= (symbolS
*) NULL
8519 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8521 /* This makes a branch to an undefined symbol be a branch to the
8522 current location. */
8526 /* return the address of the delay slot */
8527 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8530 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8531 reloc for a cons. We could use the definition there, except that
8532 we want to handle 64 bit relocs specially. */
8535 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8538 unsigned int nbytes
;
8542 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8544 if (nbytes
== 8 && ! mips_64
)
8546 if (target_big_endian
)
8552 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8553 as_bad ("Unsupported reloc size %d", nbytes
);
8555 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8558 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8561 /* This is called before the symbol table is processed. In order to
8562 work with gcc when using mips-tfile, we must keep all local labels.
8563 However, in other cases, we want to discard them. If we were
8564 called with -g, but we didn't see any debugging information, it may
8565 mean that gcc is smuggling debugging information through to
8566 mips-tfile, in which case we must generate all local labels. */
8569 mips_frob_file_before_adjust ()
8571 #ifndef NO_ECOFF_DEBUGGING
8574 && ! ecoff_debugging_seen
)
8575 flag_keep_locals
= 1;
8579 /* Sort any unmatched HI16_S relocs so that they immediately precede
8580 the corresponding LO reloc. This is called before md_apply_fix and
8581 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8582 explicit use of the %hi modifier. */
8587 struct mips_hi_fixup
*l
;
8589 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8591 segment_info_type
*seginfo
;
8594 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8596 /* Check quickly whether the next fixup happens to be a matching
8598 if (l
->fixp
->fx_next
!= NULL
8599 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8600 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8601 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8604 /* Look through the fixups for this segment for a matching %lo.
8605 When we find one, move the %hi just in front of it. We do
8606 this in two passes. In the first pass, we try to find a
8607 unique %lo. In the second pass, we permit multiple %hi
8608 relocs for a single %lo (this is a GNU extension). */
8609 seginfo
= seg_info (l
->seg
);
8610 for (pass
= 0; pass
< 2; pass
++)
8615 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8617 /* Check whether this is a %lo fixup which matches l->fixp. */
8618 if (f
->fx_r_type
== BFD_RELOC_LO16
8619 && f
->fx_addsy
== l
->fixp
->fx_addsy
8620 && f
->fx_offset
== l
->fixp
->fx_offset
8623 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8624 || prev
->fx_addsy
!= f
->fx_addsy
8625 || prev
->fx_offset
!= f
->fx_offset
))
8629 /* Move l->fixp before f. */
8630 for (pf
= &seginfo
->fix_root
;
8632 pf
= &(*pf
)->fx_next
)
8633 assert (*pf
!= NULL
);
8635 *pf
= l
->fixp
->fx_next
;
8637 l
->fixp
->fx_next
= f
;
8639 seginfo
->fix_root
= l
->fixp
;
8641 prev
->fx_next
= l
->fixp
;
8653 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8654 "Unmatched %%hi reloc");
8659 /* When generating embedded PIC code we need to use a special
8660 relocation to represent the difference of two symbols in the .text
8661 section (switch tables use a difference of this sort). See
8662 include/coff/mips.h for details. This macro checks whether this
8663 fixup requires the special reloc. */
8664 #define SWITCH_TABLE(fixp) \
8665 ((fixp)->fx_r_type == BFD_RELOC_32 \
8666 && (fixp)->fx_addsy != NULL \
8667 && (fixp)->fx_subsy != NULL \
8668 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8669 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8671 /* When generating embedded PIC code we must keep all PC relative
8672 relocations, in case the linker has to relax a call. We also need
8673 to keep relocations for switch table entries. */
8677 mips_force_relocation (fixp
)
8680 return (mips_pic
== EMBEDDED_PIC
8682 || SWITCH_TABLE (fixp
)
8683 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8684 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8687 /* Apply a fixup to the object file. */
8690 md_apply_fix (fixP
, valueP
)
8697 assert (fixP
->fx_size
== 4
8698 || fixP
->fx_r_type
== BFD_RELOC_16
8699 || fixP
->fx_r_type
== BFD_RELOC_64
);
8703 /* If we aren't adjusting this fixup to be against the section
8704 symbol, we need to adjust the value. */
8706 if (fixP
->fx_addsy
!= NULL
8707 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8708 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8710 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8711 if (value
!= 0 && ! fixP
->fx_pcrel
)
8713 /* In this case, the bfd_install_relocation routine will
8714 incorrectly add the symbol value back in. We just want
8715 the addend to appear in the object file. */
8716 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8721 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8723 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8726 switch (fixP
->fx_r_type
)
8728 case BFD_RELOC_MIPS_JMP
:
8729 case BFD_RELOC_HI16
:
8730 case BFD_RELOC_HI16_S
:
8731 case BFD_RELOC_MIPS_GPREL
:
8732 case BFD_RELOC_MIPS_LITERAL
:
8733 case BFD_RELOC_MIPS_CALL16
:
8734 case BFD_RELOC_MIPS_GOT16
:
8735 case BFD_RELOC_MIPS_GPREL32
:
8736 case BFD_RELOC_MIPS_GOT_HI16
:
8737 case BFD_RELOC_MIPS_GOT_LO16
:
8738 case BFD_RELOC_MIPS_CALL_HI16
:
8739 case BFD_RELOC_MIPS_CALL_LO16
:
8740 case BFD_RELOC_MIPS16_GPREL
:
8742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8743 "Invalid PC relative reloc");
8744 /* Nothing needed to do. The value comes from the reloc entry */
8747 case BFD_RELOC_MIPS16_JMP
:
8748 /* We currently always generate a reloc against a symbol, which
8749 means that we don't want an addend even if the symbol is
8751 fixP
->fx_addnumber
= 0;
8754 case BFD_RELOC_PCREL_HI16_S
:
8755 /* The addend for this is tricky if it is internal, so we just
8756 do everything here rather than in bfd_install_relocation. */
8757 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8759 /* For an external symbol adjust by the address to make it
8760 pcrel_offset. We use the address of the RELLO reloc
8761 which follows this one. */
8762 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8763 + fixP
->fx_next
->fx_where
);
8768 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8769 if (target_big_endian
)
8771 md_number_to_chars (buf
, value
, 2);
8774 case BFD_RELOC_PCREL_LO16
:
8775 /* The addend for this is tricky if it is internal, so we just
8776 do everything here rather than in bfd_install_relocation. */
8777 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8778 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8779 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8780 if (target_big_endian
)
8782 md_number_to_chars (buf
, value
, 2);
8786 /* This is handled like BFD_RELOC_32, but we output a sign
8787 extended value if we are only 32 bits. */
8789 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8791 if (8 <= sizeof (valueT
))
8792 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8799 w1
= w2
= fixP
->fx_where
;
8800 if (target_big_endian
)
8804 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8805 if ((value
& 0x80000000) != 0)
8809 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8815 /* If we are deleting this reloc entry, we must fill in the
8816 value now. This can happen if we have a .word which is not
8817 resolved when it appears but is later defined. We also need
8818 to fill in the value if this is an embedded PIC switch table
8821 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8822 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8827 /* If we are deleting this reloc entry, we must fill in the
8829 assert (fixP
->fx_size
== 2);
8831 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8835 case BFD_RELOC_LO16
:
8836 /* When handling an embedded PIC switch statement, we can wind
8837 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8840 if (value
< -0x8000 || value
> 0x7fff)
8841 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8842 "relocation overflow");
8843 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8844 if (target_big_endian
)
8846 md_number_to_chars (buf
, value
, 2);
8850 case BFD_RELOC_16_PCREL_S2
:
8852 * We need to save the bits in the instruction since fixup_segment()
8853 * might be deleting the relocation entry (i.e., a branch within
8854 * the current segment).
8856 if ((value
& 0x3) != 0)
8857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8858 "Branch to odd address (%lx)", value
);
8861 /* update old instruction data */
8862 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8863 if (target_big_endian
)
8864 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8866 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8868 if (value
>= -0x8000 && value
< 0x8000)
8869 insn
|= value
& 0xffff;
8872 /* The branch offset is too large. If this is an
8873 unconditional branch, and we are not generating PIC code,
8874 we can convert it to an absolute jump instruction. */
8875 if (mips_pic
== NO_PIC
8877 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8878 && (fixP
->fx_frag
->fr_address
8879 < text_section
->vma
+ text_section
->_raw_size
)
8880 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8881 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8882 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8884 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8885 insn
= 0x0c000000; /* jal */
8887 insn
= 0x08000000; /* j */
8888 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8890 fixP
->fx_addsy
= section_symbol (text_section
);
8891 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8895 /* FIXME. It would be possible in principle to handle
8896 conditional branches which overflow. They could be
8897 transformed into a branch around a jump. This would
8898 require setting up variant frags for each different
8899 branch type. The native MIPS assembler attempts to
8900 handle these cases, but it appears to do it
8902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8903 "Branch out of range");
8907 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8922 const struct mips_opcode
*p
;
8923 int treg
, sreg
, dreg
, shamt
;
8928 for (i
= 0; i
< NUMOPCODES
; ++i
)
8930 p
= &mips_opcodes
[i
];
8931 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8933 printf ("%08lx %s\t", oc
, p
->name
);
8934 treg
= (oc
>> 16) & 0x1f;
8935 sreg
= (oc
>> 21) & 0x1f;
8936 dreg
= (oc
>> 11) & 0x1f;
8937 shamt
= (oc
>> 6) & 0x1f;
8939 for (args
= p
->args
;; ++args
)
8950 printf ("%c", *args
);
8954 assert (treg
== sreg
);
8955 printf ("$%d,$%d", treg
, sreg
);
8960 printf ("$%d", dreg
);
8965 printf ("$%d", treg
);
8969 printf ("0x%x", treg
);
8974 printf ("$%d", sreg
);
8978 printf ("0x%08lx", oc
& 0x1ffffff);
8990 printf ("$%d", shamt
);
9001 printf ("%08lx UNDEFINED\n", oc
);
9012 name
= input_line_pointer
;
9013 c
= get_symbol_end ();
9014 p
= (symbolS
*) symbol_find_or_make (name
);
9015 *input_line_pointer
= c
;
9019 /* Align the current frag to a given power of two. The MIPS assembler
9020 also automatically adjusts any preceding label. */
9023 mips_align (to
, fill
, label
)
9028 mips_emit_delays (false);
9029 frag_align (to
, fill
, 0);
9030 record_alignment (now_seg
, to
);
9033 assert (S_GET_SEGMENT (label
) == now_seg
);
9034 label
->sy_frag
= frag_now
;
9035 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9039 /* Align to a given power of two. .align 0 turns off the automatic
9040 alignment used by the data creating pseudo-ops. */
9047 register long temp_fill
;
9048 long max_alignment
= 15;
9052 o Note that the assembler pulls down any immediately preceeding label
9053 to the aligned address.
9054 o It's not documented but auto alignment is reinstated by
9055 a .align pseudo instruction.
9056 o Note also that after auto alignment is turned off the mips assembler
9057 issues an error on attempt to assemble an improperly aligned data item.
9062 temp
= get_absolute_expression ();
9063 if (temp
> max_alignment
)
9064 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9067 as_warn ("Alignment negative: 0 assumed.");
9070 if (*input_line_pointer
== ',')
9072 input_line_pointer
++;
9073 temp_fill
= get_absolute_expression ();
9080 mips_align (temp
, (int) temp_fill
,
9081 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9088 demand_empty_rest_of_line ();
9092 mips_flush_pending_output ()
9094 mips_emit_delays (false);
9095 mips_clear_insn_labels ();
9104 /* When generating embedded PIC code, we only use the .text, .lit8,
9105 .sdata and .sbss sections. We change the .data and .rdata
9106 pseudo-ops to use .sdata. */
9107 if (mips_pic
== EMBEDDED_PIC
9108 && (sec
== 'd' || sec
== 'r'))
9112 /* The ELF backend needs to know that we are changing sections, so
9113 that .previous works correctly. We could do something like check
9114 for a obj_section_change_hook macro, but that might be confusing
9115 as it would not be appropriate to use it in the section changing
9116 functions in read.c, since obj-elf.c intercepts those. FIXME:
9117 This should be cleaner, somehow. */
9118 obj_elf_section_change_hook ();
9121 mips_emit_delays (false);
9131 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9132 demand_empty_rest_of_line ();
9136 if (USE_GLOBAL_POINTER_OPT
)
9138 seg
= subseg_new (RDATA_SECTION_NAME
,
9139 (subsegT
) get_absolute_expression ());
9140 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9142 bfd_set_section_flags (stdoutput
, seg
,
9148 if (strcmp (TARGET_OS
, "elf") != 0)
9149 bfd_set_section_alignment (stdoutput
, seg
, 4);
9151 demand_empty_rest_of_line ();
9155 as_bad ("No read only data section in this object file format");
9156 demand_empty_rest_of_line ();
9162 if (USE_GLOBAL_POINTER_OPT
)
9164 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9165 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9167 bfd_set_section_flags (stdoutput
, seg
,
9168 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9170 if (strcmp (TARGET_OS
, "elf") != 0)
9171 bfd_set_section_alignment (stdoutput
, seg
, 4);
9173 demand_empty_rest_of_line ();
9178 as_bad ("Global pointers not supported; recompile -G 0");
9179 demand_empty_rest_of_line ();
9188 mips_enable_auto_align ()
9199 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9200 mips_emit_delays (false);
9201 if (log_size
> 0 && auto_align
)
9202 mips_align (log_size
, 0, label
);
9203 mips_clear_insn_labels ();
9204 cons (1 << log_size
);
9213 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9215 mips_emit_delays (false);
9219 mips_align (3, 0, label
);
9221 mips_align (2, 0, label
);
9223 mips_clear_insn_labels ();
9228 /* Handle .globl. We need to override it because on Irix 5 you are
9231 where foo is an undefined symbol, to mean that foo should be
9232 considered to be the address of a function. */
9243 name
= input_line_pointer
;
9244 c
= get_symbol_end ();
9245 symbolP
= symbol_find_or_make (name
);
9246 *input_line_pointer
= c
;
9249 /* On Irix 5, every global symbol that is not explicitly labelled as
9250 being a function is apparently labelled as being an object. */
9253 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9258 secname
= input_line_pointer
;
9259 c
= get_symbol_end ();
9260 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9262 as_bad ("%s: no such section", secname
);
9263 *input_line_pointer
= c
;
9265 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9266 flag
= BSF_FUNCTION
;
9269 symbolP
->bsym
->flags
|= flag
;
9271 S_SET_EXTERNAL (symbolP
);
9272 demand_empty_rest_of_line ();
9282 opt
= input_line_pointer
;
9283 c
= get_symbol_end ();
9287 /* FIXME: What does this mean? */
9289 else if (strncmp (opt
, "pic", 3) == 0)
9297 mips_pic
= SVR4_PIC
;
9299 as_bad (".option pic%d not supported", i
);
9301 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9303 if (g_switch_seen
&& g_switch_value
!= 0)
9304 as_warn ("-G may not be used with SVR4 PIC code");
9306 bfd_set_gp_size (stdoutput
, 0);
9310 as_warn ("Unrecognized option \"%s\"", opt
);
9312 *input_line_pointer
= c
;
9313 demand_empty_rest_of_line ();
9316 /* This structure is used to hold a stack of .set values. */
9318 struct mips_option_stack
9320 struct mips_option_stack
*next
;
9321 struct mips_set_options options
;
9324 static struct mips_option_stack
*mips_opts_stack
;
9326 /* Handle the .set pseudo-op. */
9332 char *name
= input_line_pointer
, ch
;
9334 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9335 input_line_pointer
++;
9336 ch
= *input_line_pointer
;
9337 *input_line_pointer
= '\0';
9339 if (strcmp (name
, "reorder") == 0)
9341 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9343 /* If we still have pending nops, we can discard them. The
9344 usual nop handling will insert any that are still
9346 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9347 * (mips_opts
.mips16
? 2 : 4));
9348 prev_nop_frag
= NULL
;
9350 mips_opts
.noreorder
= 0;
9352 else if (strcmp (name
, "noreorder") == 0)
9354 mips_emit_delays (true);
9355 mips_opts
.noreorder
= 1;
9356 mips_any_noreorder
= 1;
9358 else if (strcmp (name
, "at") == 0)
9362 else if (strcmp (name
, "noat") == 0)
9366 else if (strcmp (name
, "macro") == 0)
9368 mips_opts
.warn_about_macros
= 0;
9370 else if (strcmp (name
, "nomacro") == 0)
9372 if (mips_opts
.noreorder
== 0)
9373 as_bad ("`noreorder' must be set before `nomacro'");
9374 mips_opts
.warn_about_macros
= 1;
9376 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9378 mips_opts
.nomove
= 0;
9380 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9382 mips_opts
.nomove
= 1;
9384 else if (strcmp (name
, "bopt") == 0)
9386 mips_opts
.nobopt
= 0;
9388 else if (strcmp (name
, "nobopt") == 0)
9390 mips_opts
.nobopt
= 1;
9392 else if (strcmp (name
, "mips16") == 0
9393 || strcmp (name
, "MIPS-16") == 0)
9394 mips_opts
.mips16
= 1;
9395 else if (strcmp (name
, "nomips16") == 0
9396 || strcmp (name
, "noMIPS-16") == 0)
9397 mips_opts
.mips16
= 0;
9398 else if (strncmp (name
, "mips", 4) == 0)
9402 /* Permit the user to change the ISA on the fly. Needless to
9403 say, misuse can cause serious problems. */
9404 isa
= atoi (name
+ 4);
9406 mips_opts
.isa
= file_mips_isa
;
9407 else if (isa
< 1 || isa
> 4)
9408 as_bad ("unknown ISA level");
9410 mips_opts
.isa
= isa
;
9412 else if (strcmp (name
, "autoextend") == 0)
9413 mips_opts
.noautoextend
= 0;
9414 else if (strcmp (name
, "noautoextend") == 0)
9415 mips_opts
.noautoextend
= 1;
9416 else if (strcmp (name
, "push") == 0)
9418 struct mips_option_stack
*s
;
9420 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9421 s
->next
= mips_opts_stack
;
9422 s
->options
= mips_opts
;
9423 mips_opts_stack
= s
;
9425 else if (strcmp (name
, "pop") == 0)
9427 struct mips_option_stack
*s
;
9429 s
= mips_opts_stack
;
9431 as_bad (".set pop with no .set push");
9434 /* If we're changing the reorder mode we need to handle
9435 delay slots correctly. */
9436 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9437 mips_emit_delays (true);
9438 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9440 if (prev_nop_frag
!= NULL
)
9442 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9443 * (mips_opts
.mips16
? 2 : 4));
9444 prev_nop_frag
= NULL
;
9448 mips_opts
= s
->options
;
9449 mips_opts_stack
= s
->next
;
9455 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9457 *input_line_pointer
= ch
;
9458 demand_empty_rest_of_line ();
9461 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9462 .option pic2. It means to generate SVR4 PIC calls. */
9468 mips_pic
= SVR4_PIC
;
9469 if (USE_GLOBAL_POINTER_OPT
)
9471 if (g_switch_seen
&& g_switch_value
!= 0)
9472 as_warn ("-G may not be used with SVR4 PIC code");
9475 bfd_set_gp_size (stdoutput
, 0);
9476 demand_empty_rest_of_line ();
9479 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9480 PIC code. It sets the $gp register for the function based on the
9481 function address, which is in the register named in the argument.
9482 This uses a relocation against _gp_disp, which is handled specially
9483 by the linker. The result is:
9484 lui $gp,%hi(_gp_disp)
9485 addiu $gp,$gp,%lo(_gp_disp)
9486 addu $gp,$gp,.cpload argument
9487 The .cpload argument is normally $25 == $t9. */
9496 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9497 if (mips_pic
!= SVR4_PIC
)
9503 /* .cpload should be a in .set noreorder section. */
9504 if (mips_opts
.noreorder
== 0)
9505 as_warn (".cpload not in noreorder section");
9508 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9509 ex
.X_op_symbol
= NULL
;
9510 ex
.X_add_number
= 0;
9512 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9513 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9515 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9516 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9517 (int) BFD_RELOC_LO16
);
9519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9520 GP
, GP
, tc_get_register (0));
9522 demand_empty_rest_of_line ();
9525 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9526 offset from $sp. The offset is remembered, and after making a PIC
9527 call $gp is restored from that location. */
9530 s_cprestore (ignore
)
9536 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9537 if (mips_pic
!= SVR4_PIC
)
9543 mips_cprestore_offset
= get_absolute_expression ();
9545 ex
.X_op
= O_constant
;
9546 ex
.X_add_symbol
= NULL
;
9547 ex
.X_op_symbol
= NULL
;
9548 ex
.X_add_number
= mips_cprestore_offset
;
9550 macro_build ((char *) NULL
, &icnt
, &ex
,
9551 mips_opts
.isa
< 3 ? "sw" : "sd",
9552 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9554 demand_empty_rest_of_line ();
9557 /* Handle the .gpword pseudo-op. This is used when generating PIC
9558 code. It generates a 32 bit GP relative reloc. */
9568 /* When not generating PIC code, this is treated as .word. */
9569 if (mips_pic
!= SVR4_PIC
)
9575 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9576 mips_emit_delays (true);
9578 mips_align (2, 0, label
);
9579 mips_clear_insn_labels ();
9583 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9585 as_bad ("Unsupported use of .gpword");
9586 ignore_rest_of_line ();
9590 md_number_to_chars (p
, (valueT
) 0, 4);
9591 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9592 BFD_RELOC_MIPS_GPREL32
);
9594 demand_empty_rest_of_line ();
9597 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9598 tables in SVR4 PIC code. */
9607 /* This is ignored when not generating SVR4 PIC code. */
9608 if (mips_pic
!= SVR4_PIC
)
9614 /* Add $gp to the register named as an argument. */
9615 reg
= tc_get_register (0);
9616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9617 mips_opts
.isa
< 3 ? "addu" : "daddu",
9618 "d,v,t", reg
, reg
, GP
);
9620 demand_empty_rest_of_line ();
9623 /* Handle the .insn pseudo-op. This marks instruction labels in
9624 mips16 mode. This permits the linker to handle them specially,
9625 such as generating jalx instructions when needed. We also make
9626 them odd for the duration of the assembly, in order to generate the
9627 right sort of code. We will make them even in the adjust_symtab
9628 routine, while leaving them marked. This is convenient for the
9629 debugger and the disassembler. The linker knows to make them odd
9636 if (mips_opts
.mips16
)
9637 mips16_mark_labels ();
9639 demand_empty_rest_of_line ();
9642 /* Handle a .stabn directive. We need these in order to mark a label
9643 as being a mips16 text label correctly. Sometimes the compiler
9644 will emit a label, followed by a .stabn, and then switch sections.
9645 If the label and .stabn are in mips16 mode, then the label is
9646 really a mips16 text label. */
9652 if (type
== 'n' && mips_opts
.mips16
)
9653 mips16_mark_labels ();
9658 /* Parse a register string into a number. Called from the ECOFF code
9659 to parse .frame. The argument is non-zero if this is the frame
9660 register, so that we can record it in mips_frame_reg. */
9663 tc_get_register (frame
)
9669 if (*input_line_pointer
++ != '$')
9671 as_warn ("expected `$'");
9674 else if (isdigit ((unsigned char) *input_line_pointer
))
9676 reg
= get_absolute_expression ();
9677 if (reg
< 0 || reg
>= 32)
9679 as_warn ("Bad register number");
9685 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9687 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9689 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9691 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9695 as_warn ("Unrecognized register name");
9698 input_line_pointer
+= 2;
9701 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9706 md_section_align (seg
, addr
)
9710 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9713 /* We don't need to align ELF sections to the full alignment.
9714 However, Irix 5 may prefer that we align them at least to a 16
9715 byte boundary. We don't bother to align the sections if we are
9716 targeted for an embedded system. */
9717 if (strcmp (TARGET_OS
, "elf") == 0)
9723 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9726 /* Utility routine, called from above as well. If called while the
9727 input file is still being read, it's only an approximation. (For
9728 example, a symbol may later become defined which appeared to be
9729 undefined earlier.) */
9732 nopic_need_relax (sym
)
9738 if (USE_GLOBAL_POINTER_OPT
)
9740 const char *symname
;
9743 /* Find out whether this symbol can be referenced off the GP
9744 register. It can be if it is smaller than the -G size or if
9745 it is in the .sdata or .sbss section. Certain symbols can
9746 not be referenced off the GP, although it appears as though
9748 symname
= S_GET_NAME (sym
);
9749 if (symname
!= (const char *) NULL
9750 && (strcmp (symname
, "eprol") == 0
9751 || strcmp (symname
, "etext") == 0
9752 || strcmp (symname
, "_gp") == 0
9753 || strcmp (symname
, "edata") == 0
9754 || strcmp (symname
, "_fbss") == 0
9755 || strcmp (symname
, "_fdata") == 0
9756 || strcmp (symname
, "_ftext") == 0
9757 || strcmp (symname
, "end") == 0
9758 || strcmp (symname
, "_gp_disp") == 0))
9760 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
9762 #ifndef NO_ECOFF_DEBUGGING
9763 || (sym
->ecoff_extern_size
!= 0
9764 && sym
->ecoff_extern_size
<= g_switch_value
)
9766 || (S_GET_VALUE (sym
) != 0
9767 && S_GET_VALUE (sym
) <= g_switch_value
)))
9771 const char *segname
;
9773 segname
= segment_name (S_GET_SEGMENT (sym
));
9774 assert (strcmp (segname
, ".lit8") != 0
9775 && strcmp (segname
, ".lit4") != 0);
9776 change
= (strcmp (segname
, ".sdata") != 0
9777 && strcmp (segname
, ".sbss") != 0);
9782 /* We are not optimizing for the GP register. */
9786 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9787 extended opcode. SEC is the section the frag is in. */
9790 mips16_extended_frag (fragp
, sec
, stretch
)
9796 register const struct mips16_immed_operand
*op
;
9798 int mintiny
, maxtiny
;
9801 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9803 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9806 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9807 op
= mips16_immed_operands
;
9808 while (op
->type
!= type
)
9811 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9816 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9819 maxtiny
= 1 << op
->nbits
;
9824 maxtiny
= (1 << op
->nbits
) - 1;
9829 mintiny
= - (1 << (op
->nbits
- 1));
9830 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9833 /* We can't call S_GET_VALUE here, because we don't want to lock in
9834 a particular frag address. */
9835 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9837 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9838 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9839 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9841 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9842 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9845 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9846 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9847 + fragp
->fr_symbol
->sy_value
.X_add_number
9848 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9849 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9858 /* We won't have the section when we are called from
9859 mips_relax_frag. However, we will always have been called
9860 from md_estimate_size_before_relax first. If this is a
9861 branch to a different section, we mark it as such. If SEC is
9862 NULL, and the frag is not marked, then it must be a branch to
9863 the same section. */
9866 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9874 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9876 /* FIXME: We should support this, and let the linker
9877 catch branches and loads that are out of range. */
9878 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9879 "unsupported PC relative reference to different section");
9885 /* In this case, we know for sure that the symbol fragment is in
9886 the same section. If the fr_address of the symbol fragment
9887 is greater then the address of this fragment we want to add
9888 in STRETCH in order to get a better estimate of the address.
9889 This particularly matters because of the shift bits. */
9891 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9895 /* Adjust stretch for any alignment frag. Note that if have
9896 been expanding the earlier code, the symbol may be
9897 defined in what appears to be an earlier frag. FIXME:
9898 This doesn't handle the fr_subtype field, which specifies
9899 a maximum number of bytes to skip when doing an
9902 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
9905 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9908 stretch
= - ((- stretch
)
9909 & ~ ((1 << (int) f
->fr_offset
) - 1));
9911 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9920 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9922 /* The base address rules are complicated. The base address of
9923 a branch is the following instruction. The base address of a
9924 PC relative load or add is the instruction itself, but if it
9925 is in a delay slot (in which case it can not be extended) use
9926 the address of the instruction whose delay slot it is in. */
9927 if (type
== 'p' || type
== 'q')
9931 /* If we are currently assuming that this frag should be
9932 extended, then, the current address is two bytes
9934 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9937 /* Ignore the low bit in the target, since it will be set
9938 for a text label. */
9942 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9944 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9947 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9949 /* Branch offsets have an implicit 0 in the lowest bit. */
9950 if (type
== 'p' || type
== 'q')
9953 /* If any of the shifted bits are set, we must use an extended
9954 opcode. If the address depends on the size of this
9955 instruction, this can lead to a loop, so we arrange to always
9956 use an extended opcode. We only check this when we are in
9957 the main relaxation loop, when SEC is NULL. */
9958 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9961 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9965 /* If we are about to mark a frag as extended because the value
9966 is precisely maxtiny + 1, then there is a chance of an
9967 infinite loop as in the following code:
9972 In this case when the la is extended, foo is 0x3fc bytes
9973 away, so the la can be shrunk, but then foo is 0x400 away, so
9974 the la must be extended. To avoid this loop, we mark the
9975 frag as extended if it was small, and is about to become
9976 extended with a value of maxtiny + 1. */
9977 if (val
== ((maxtiny
+ 1) << op
->shift
)
9978 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9982 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9986 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9987 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9989 if ((val
& ((1 << op
->shift
) - 1)) != 0
9990 || val
< (mintiny
<< op
->shift
)
9991 || val
> (maxtiny
<< op
->shift
))
9997 /* Estimate the size of a frag before relaxing. Unless this is the
9998 mips16, we are not really relaxing here, and the final size is
9999 encoded in the subtype information. For the mips16, we have to
10000 decide whether we are using an extended opcode or not. */
10004 md_estimate_size_before_relax (fragp
, segtype
)
10010 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10012 if (mips16_extended_frag (fragp
, segtype
, 0))
10014 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10019 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10024 if (mips_pic
== NO_PIC
)
10026 change
= nopic_need_relax (fragp
->fr_symbol
);
10028 else if (mips_pic
== SVR4_PIC
)
10033 sym
= fragp
->fr_symbol
;
10035 /* Handle the case of a symbol equated to another symbol. */
10036 while (sym
->sy_value
.X_op
== O_symbol
10037 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10041 /* It's possible to get a loop here in a badly written
10043 n
= sym
->sy_value
.X_add_symbol
;
10049 symsec
= S_GET_SEGMENT (sym
);
10051 /* This must duplicate the test in adjust_reloc_syms. */
10052 change
= (symsec
!= &bfd_und_section
10053 && symsec
!= &bfd_abs_section
10054 && ! bfd_is_com_section (symsec
));
10061 /* Record the offset to the first reloc in the fr_opcode field.
10062 This lets md_convert_frag and tc_gen_reloc know that the code
10063 must be expanded. */
10064 fragp
->fr_opcode
= (fragp
->fr_literal
10066 - RELAX_OLD (fragp
->fr_subtype
)
10067 + RELAX_RELOC1 (fragp
->fr_subtype
));
10068 /* FIXME: This really needs as_warn_where. */
10069 if (RELAX_WARN (fragp
->fr_subtype
))
10070 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10076 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10079 /* This is called to see whether a reloc against a defined symbol
10080 should be converted into a reloc against a section. Don't adjust
10081 MIPS16 jump relocations, so we don't have to worry about the format
10082 of the offset in the .o file. Don't adjust relocations against
10083 mips16 symbols, so that the linker can find them if it needs to set
10087 mips_fix_adjustable (fixp
)
10090 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10092 if (fixp
->fx_addsy
== NULL
)
10095 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10096 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10097 && fixp
->fx_subsy
== NULL
)
10103 /* Translate internal representation of relocation info to BFD target
10107 tc_gen_reloc (section
, fixp
)
10111 static arelent
*retval
[4];
10113 bfd_reloc_code_real_type code
;
10115 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10118 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10119 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10121 if (mips_pic
== EMBEDDED_PIC
10122 && SWITCH_TABLE (fixp
))
10124 /* For a switch table entry we use a special reloc. The addend
10125 is actually the difference between the reloc address and the
10127 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10128 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10129 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10130 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10132 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10134 /* We use a special addend for an internal RELLO reloc. */
10135 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10136 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10138 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10140 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10142 assert (fixp
->fx_next
!= NULL
10143 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10144 /* We use a special addend for an internal RELHI reloc. The
10145 reloc is relative to the RELLO; adjust the addend
10147 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10148 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10149 + fixp
->fx_next
->fx_where
10150 - S_GET_VALUE (fixp
->fx_subsy
));
10152 reloc
->addend
= (fixp
->fx_addnumber
10153 + fixp
->fx_next
->fx_frag
->fr_address
10154 + fixp
->fx_next
->fx_where
);
10156 else if (fixp
->fx_pcrel
== 0)
10157 reloc
->addend
= fixp
->fx_addnumber
;
10160 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10161 /* A gruesome hack which is a result of the gruesome gas reloc
10163 reloc
->addend
= reloc
->address
;
10165 reloc
->addend
= -reloc
->address
;
10168 /* If this is a variant frag, we may need to adjust the existing
10169 reloc and generate a new one. */
10170 if (fixp
->fx_frag
->fr_opcode
!= NULL
10171 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10172 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10173 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10174 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10175 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10176 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10177 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10181 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10183 /* If this is not the last reloc in this frag, then we have two
10184 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10185 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10186 the second one handle all of them. */
10187 if (fixp
->fx_next
!= NULL
10188 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10190 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10191 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10192 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10193 && (fixp
->fx_next
->fx_r_type
10194 == BFD_RELOC_MIPS_GOT_LO16
))
10195 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10196 && (fixp
->fx_next
->fx_r_type
10197 == BFD_RELOC_MIPS_CALL_LO16
)));
10202 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10203 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10204 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10206 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10207 reloc2
->address
= (reloc
->address
10208 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10209 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10210 reloc2
->addend
= fixp
->fx_addnumber
;
10211 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10212 assert (reloc2
->howto
!= NULL
);
10214 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10218 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10221 reloc3
->address
+= 4;
10224 if (mips_pic
== NO_PIC
)
10226 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10227 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10229 else if (mips_pic
== SVR4_PIC
)
10231 switch (fixp
->fx_r_type
)
10235 case BFD_RELOC_MIPS_GOT16
:
10237 case BFD_RELOC_MIPS_CALL16
:
10238 case BFD_RELOC_MIPS_GOT_LO16
:
10239 case BFD_RELOC_MIPS_CALL_LO16
:
10240 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10248 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10249 fixup_segment converted a non-PC relative reloc into a PC
10250 relative reloc. In such a case, we need to convert the reloc
10252 code
= fixp
->fx_r_type
;
10253 if (fixp
->fx_pcrel
)
10258 code
= BFD_RELOC_8_PCREL
;
10261 code
= BFD_RELOC_16_PCREL
;
10264 code
= BFD_RELOC_32_PCREL
;
10267 code
= BFD_RELOC_64_PCREL
;
10269 case BFD_RELOC_8_PCREL
:
10270 case BFD_RELOC_16_PCREL
:
10271 case BFD_RELOC_32_PCREL
:
10272 case BFD_RELOC_64_PCREL
:
10273 case BFD_RELOC_16_PCREL_S2
:
10274 case BFD_RELOC_PCREL_HI16_S
:
10275 case BFD_RELOC_PCREL_LO16
:
10278 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10279 "Cannot make %s relocation PC relative",
10280 bfd_get_reloc_code_name (code
));
10284 /* To support a PC relative reloc when generating embedded PIC code
10285 for ECOFF, we use a Cygnus extension. We check for that here to
10286 make sure that we don't let such a reloc escape normally. */
10287 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10288 && code
== BFD_RELOC_16_PCREL_S2
10289 && mips_pic
!= EMBEDDED_PIC
)
10290 reloc
->howto
= NULL
;
10292 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10294 if (reloc
->howto
== NULL
)
10296 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10297 "Can not represent %s relocation in this object file format",
10298 bfd_get_reloc_code_name (code
));
10305 /* Relax a machine dependent frag. This returns the amount by which
10306 the current size of the frag should change. */
10309 mips_relax_frag (fragp
, stretch
)
10313 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10316 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10318 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10320 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10325 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10327 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10334 /* Convert a machine dependent frag. */
10337 md_convert_frag (abfd
, asec
, fragp
)
10345 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10348 register const struct mips16_immed_operand
*op
;
10349 boolean small
, ext
;
10352 unsigned long insn
;
10353 boolean use_extend
;
10354 unsigned short extend
;
10356 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10357 op
= mips16_immed_operands
;
10358 while (op
->type
!= type
)
10361 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10372 resolve_symbol_value (fragp
->fr_symbol
);
10373 val
= S_GET_VALUE (fragp
->fr_symbol
);
10378 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10380 /* The rules for the base address of a PC relative reloc are
10381 complicated; see mips16_extended_frag. */
10382 if (type
== 'p' || type
== 'q')
10387 /* Ignore the low bit in the target, since it will be
10388 set for a text label. */
10389 if ((val
& 1) != 0)
10392 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10394 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10397 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10400 /* Make sure the section winds up with the alignment we have
10403 record_alignment (asec
, op
->shift
);
10407 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10408 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10409 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10410 "extended instruction in delay slot");
10412 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10414 if (target_big_endian
)
10415 insn
= bfd_getb16 (buf
);
10417 insn
= bfd_getl16 (buf
);
10419 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10420 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10421 small
, ext
, &insn
, &use_extend
, &extend
);
10425 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10426 fragp
->fr_fix
+= 2;
10430 md_number_to_chars (buf
, insn
, 2);
10431 fragp
->fr_fix
+= 2;
10436 if (fragp
->fr_opcode
== NULL
)
10439 old
= RELAX_OLD (fragp
->fr_subtype
);
10440 new = RELAX_NEW (fragp
->fr_subtype
);
10441 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10444 memcpy (fixptr
- old
, fixptr
, new);
10446 fragp
->fr_fix
+= new - old
;
10452 /* This function is called after the relocs have been generated.
10453 We've been storing mips16 text labels as odd. Here we convert them
10454 back to even for the convenience of the debugger. */
10457 mips_frob_file_after_relocs ()
10460 unsigned int count
, i
;
10462 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10465 syms
= bfd_get_outsymbols (stdoutput
);
10466 count
= bfd_get_symcount (stdoutput
);
10467 for (i
= 0; i
< count
; i
++, syms
++)
10469 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10470 && ((*syms
)->value
& 1) != 0)
10472 (*syms
)->value
&= ~1;
10473 /* If the symbol has an odd size, it was probably computed
10474 incorrectly, so adjust that as well. */
10475 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10476 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10483 /* This function is called whenever a label is defined. It is used
10484 when handling branch delays; if a branch has a label, we assume we
10485 can not move it. */
10488 mips_define_label (sym
)
10491 struct insn_label_list
*l
;
10493 if (free_insn_labels
== NULL
)
10494 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10497 l
= free_insn_labels
;
10498 free_insn_labels
= l
->next
;
10502 l
->next
= insn_labels
;
10506 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10508 /* Some special processing for a MIPS ELF file. */
10511 mips_elf_final_processing ()
10513 /* Write out the register information. */
10518 s
.ri_gprmask
= mips_gprmask
;
10519 s
.ri_cprmask
[0] = mips_cprmask
[0];
10520 s
.ri_cprmask
[1] = mips_cprmask
[1];
10521 s
.ri_cprmask
[2] = mips_cprmask
[2];
10522 s
.ri_cprmask
[3] = mips_cprmask
[3];
10523 /* The gp_value field is set by the MIPS ELF backend. */
10525 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10526 ((Elf32_External_RegInfo
*)
10527 mips_regmask_frag
));
10531 Elf64_Internal_RegInfo s
;
10533 s
.ri_gprmask
= mips_gprmask
;
10535 s
.ri_cprmask
[0] = mips_cprmask
[0];
10536 s
.ri_cprmask
[1] = mips_cprmask
[1];
10537 s
.ri_cprmask
[2] = mips_cprmask
[2];
10538 s
.ri_cprmask
[3] = mips_cprmask
[3];
10539 /* The gp_value field is set by the MIPS ELF backend. */
10541 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10542 ((Elf64_External_RegInfo
*)
10543 mips_regmask_frag
));
10546 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10547 sort of BFD interface for this. */
10548 if (mips_any_noreorder
)
10549 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10550 if (mips_pic
!= NO_PIC
)
10551 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10554 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10556 /* These functions should really be defined by the object file format,
10557 since they are related to debugging information. However, this
10558 code has to work for the a.out format, which does not define them,
10559 so we provide simple versions here. These don't actually generate
10560 any debugging information, but they do simple checking and someday
10561 somebody may make them useful. */
10565 struct loc
*loc_next
;
10566 unsigned long loc_fileno
;
10567 unsigned long loc_lineno
;
10568 unsigned long loc_offset
;
10569 unsigned short loc_delta
;
10570 unsigned short loc_count
;
10577 typedef struct proc
10579 struct proc
*proc_next
;
10580 struct symbol
*proc_isym
;
10581 struct symbol
*proc_end
;
10582 unsigned long proc_reg_mask
;
10583 unsigned long proc_reg_offset
;
10584 unsigned long proc_fpreg_mask
;
10585 unsigned long proc_fpreg_offset
;
10586 unsigned long proc_frameoffset
;
10587 unsigned long proc_framereg
;
10588 unsigned long proc_pcreg
;
10590 struct file
*proc_file
;
10595 typedef struct file
10597 struct file
*file_next
;
10598 unsigned long file_fileno
;
10599 struct symbol
*file_symbol
;
10600 struct symbol
*file_end
;
10601 struct proc
*file_proc
;
10606 static struct obstack proc_frags
;
10607 static procS
*proc_lastP
;
10608 static procS
*proc_rootP
;
10609 static int numprocs
;
10614 obstack_begin (&proc_frags
, 0x2000);
10620 /* check for premature end, nesting errors, etc */
10621 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10622 as_warn ("missing `.end' at end of assembly");
10631 if (*input_line_pointer
== '-')
10633 ++input_line_pointer
;
10636 if (!isdigit (*input_line_pointer
))
10637 as_bad ("Expected simple number.");
10638 if (input_line_pointer
[0] == '0')
10640 if (input_line_pointer
[1] == 'x')
10642 input_line_pointer
+= 2;
10643 while (isxdigit (*input_line_pointer
))
10646 val
|= hex_value (*input_line_pointer
++);
10648 return negative
? -val
: val
;
10652 ++input_line_pointer
;
10653 while (isdigit (*input_line_pointer
))
10656 val
|= *input_line_pointer
++ - '0';
10658 return negative
? -val
: val
;
10661 if (!isdigit (*input_line_pointer
))
10663 printf (" *input_line_pointer == '%c' 0x%02x\n",
10664 *input_line_pointer
, *input_line_pointer
);
10665 as_warn ("Invalid number");
10668 while (isdigit (*input_line_pointer
))
10671 val
+= *input_line_pointer
++ - '0';
10673 return negative
? -val
: val
;
10676 /* The .file directive; just like the usual .file directive, but there
10677 is an initial number which is the ECOFF file index. */
10685 line
= get_number ();
10690 /* The .end directive. */
10698 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10701 demand_empty_rest_of_line ();
10705 if (now_seg
!= text_section
)
10706 as_warn (".end not in text section");
10709 as_warn (".end and no .ent seen yet.");
10715 assert (S_GET_NAME (p
));
10716 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10717 as_warn (".end symbol does not match .ent symbol.");
10720 proc_lastP
->proc_end
= (symbolS
*) 1;
10723 /* The .aent and .ent directives. */
10733 symbolP
= get_symbol ();
10734 if (*input_line_pointer
== ',')
10735 input_line_pointer
++;
10736 SKIP_WHITESPACE ();
10737 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10738 number
= get_number ();
10739 if (now_seg
!= text_section
)
10740 as_warn (".ent or .aent not in text section.");
10742 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10743 as_warn ("missing `.end'");
10747 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10748 procP
->proc_isym
= symbolP
;
10749 procP
->proc_reg_mask
= 0;
10750 procP
->proc_reg_offset
= 0;
10751 procP
->proc_fpreg_mask
= 0;
10752 procP
->proc_fpreg_offset
= 0;
10753 procP
->proc_frameoffset
= 0;
10754 procP
->proc_framereg
= 0;
10755 procP
->proc_pcreg
= 0;
10756 procP
->proc_end
= NULL
;
10757 procP
->proc_next
= NULL
;
10759 proc_lastP
->proc_next
= procP
;
10761 proc_rootP
= procP
;
10762 proc_lastP
= procP
;
10765 demand_empty_rest_of_line ();
10768 /* The .frame directive. */
10781 frame_reg
= tc_get_register (1);
10782 if (*input_line_pointer
== ',')
10783 input_line_pointer
++;
10784 frame_off
= get_absolute_expression ();
10785 if (*input_line_pointer
== ',')
10786 input_line_pointer
++;
10787 pcreg
= tc_get_register (0);
10789 /* bob third eye */
10790 assert (proc_rootP
);
10791 proc_rootP
->proc_framereg
= frame_reg
;
10792 proc_rootP
->proc_frameoffset
= frame_off
;
10793 proc_rootP
->proc_pcreg
= pcreg
;
10794 /* bob macho .frame */
10796 /* We don't have to write out a frame stab for unoptimized code. */
10797 if (!(frame_reg
== FP
&& frame_off
== 0))
10800 as_warn ("No .ent for .frame to use.");
10801 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10802 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10803 S_SET_TYPE (symP
, N_RMASK
);
10804 S_SET_OTHER (symP
, 0);
10805 S_SET_DESC (symP
, 0);
10806 symP
->sy_forward
= proc_lastP
->proc_isym
;
10807 /* bob perhaps I should have used pseudo set */
10809 demand_empty_rest_of_line ();
10813 /* The .fmask and .mask directives. */
10820 char str
[100], *strP
;
10826 mask
= get_number ();
10827 if (*input_line_pointer
== ',')
10828 input_line_pointer
++;
10829 off
= get_absolute_expression ();
10831 /* bob only for coff */
10832 assert (proc_rootP
);
10833 if (reg_type
== 'F')
10835 proc_rootP
->proc_fpreg_mask
= mask
;
10836 proc_rootP
->proc_fpreg_offset
= off
;
10840 proc_rootP
->proc_reg_mask
= mask
;
10841 proc_rootP
->proc_reg_offset
= off
;
10844 /* bob macho .mask + .fmask */
10846 /* We don't have to write out a mask stab if no saved regs. */
10850 as_warn ("No .ent for .mask to use.");
10852 for (i
= 0; i
< 32; i
++)
10856 sprintf (strP
, "%c%d,", reg_type
, i
);
10857 strP
+= strlen (strP
);
10861 sprintf (strP
, ";%d,", off
);
10862 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10863 S_SET_TYPE (symP
, N_RMASK
);
10864 S_SET_OTHER (symP
, 0);
10865 S_SET_DESC (symP
, 0);
10866 symP
->sy_forward
= proc_lastP
->proc_isym
;
10867 /* bob perhaps I should have used pseudo set */
10872 /* The .loc directive. */
10883 assert (now_seg
== text_section
);
10885 lineno
= get_number ();
10886 addroff
= frag_now_fix ();
10888 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10889 S_SET_TYPE (symbolP
, N_SLINE
);
10890 S_SET_OTHER (symbolP
, 0);
10891 S_SET_DESC (symbolP
, lineno
);
10892 symbolP
->sy_segment
= now_seg
;