1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_coff_flavour
:
123 case bfd_target_elf_flavour
:
125 /* This is traditional mips */
126 return (target_big_endian
127 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
129 return (target_big_endian
130 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
131 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
139 /* The name of the readonly data section. */
140 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
142 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
144 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
150 /* This is the set of options which may be modified by the .set
151 pseudo-op. We use a struct so that .set push and .set pop are more
154 struct mips_set_options
156 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
157 if it has not been initialized. Changed by `.set mipsN', and the
158 -mipsN command line option, and the default CPU. */
160 /* Whether we are assembling for the mips16 processor. 0 if we are
161 not, 1 if we are, and -1 if the value has not been initialized.
162 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
163 -nomips16 command line options, and the default CPU. */
165 /* Non-zero if we should not reorder instructions. Changed by `.set
166 reorder' and `.set noreorder'. */
168 /* Non-zero if we should not permit the $at ($1) register to be used
169 in instructions. Changed by `.set at' and `.set noat'. */
171 /* Non-zero if we should warn when a macro instruction expands into
172 more than one machine instruction. Changed by `.set nomacro' and
174 int warn_about_macros
;
175 /* Non-zero if we should not move instructions. Changed by `.set
176 move', `.set volatile', `.set nomove', and `.set novolatile'. */
178 /* Non-zero if we should not optimize branches by moving the target
179 of the branch into the delay slot. Actually, we don't perform
180 this optimization anyhow. Changed by `.set bopt' and `.set
183 /* Non-zero if we should not autoextend mips16 instructions.
184 Changed by `.set autoextend' and `.set noautoextend'. */
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa and mips16 fields to -1 to indicate that
190 they have not been initialized. */
192 static struct mips_set_options mips_opts
= { -1, -1, 0, 0, 0, 0, 0, 0 };
194 /* These variables are filled in with the masks of registers used.
195 The object format code reads them and puts them in the appropriate
197 unsigned long mips_gprmask
;
198 unsigned long mips_cprmask
[4];
200 /* MIPS ISA we are using for this output file. */
201 static int file_mips_isa
;
203 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
204 static int mips_cpu
= -1;
206 /* The argument of the -mabi= flag. */
207 static char* mips_abi_string
= 0;
209 /* Wether we should mark the file EABI64 or EABI32. */
210 static int mips_eabi64
= 0;
212 /* If they asked for mips1 or mips2 and a cpu that is
213 mips3 or greater, then mark the object file 32BITMODE. */
214 static int mips_32bitmode
= 0;
216 /* True if -mgp32 was passed. */
217 static int mips_gp32
= 0;
219 /* Some ISA's have delay slots for instructions which read or write
220 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
221 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
222 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
223 delay slot in this ISA. The uses of this macro assume that any
224 ISA that has delay slots for one of these, has them for all. They
225 also assume that ISAs which don't have delays for these insns, don't
226 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
227 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
233 /* Return true if ISA supports 64 bit gp register instructions. */
234 #define ISA_HAS_64BIT_REGS(ISA) ( \
239 /* Whether the processor uses hardware interlocks to protect
240 reads from the HI and LO registers, and thus does not
241 require nops to be inserted.
243 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
244 -mcpu=FOO schedules for FOO, but still produces code that meets the
245 requirements of MIPS ISA I. For example, it won't generate any
246 FOO-specific instructions, and it will still assume that any
247 scheduling hazards described in MIPS ISA I are there, even if FOO
248 has interlocks. -mFOO gives GCC permission to generate code that
249 will only run on a FOO; it will generate FOO-specific instructions,
250 and assume interlocks provided by a FOO.
252 However, GAS currently doesn't make this distinction; before Jan 28
253 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
254 assumptions. The GCC driver passes these flags through to GAS, so
255 if GAS actually does anything that doesn't meet MIPS ISA I with
256 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
258 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
259 which seems senseless --- why generate code which will only run on
260 a FOO, but schedule for something else?
262 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
264 -- Jim Blandy <jimb@cygnus.com> */
266 #define hilo_interlocks (mips_cpu == 4010 \
269 /* Whether the processor uses hardware interlocks to protect reads
270 from the GPRs, and thus does not require nops to be inserted. */
271 #define gpr_interlocks \
272 (mips_opts.isa != 1 \
275 /* As with other "interlocks" this is used by hardware that has FP
276 (co-processor) interlocks. */
277 /* Itbl support may require additional care here. */
278 #define cop_interlocks (mips_cpu == 4300 \
281 /* Is this a mfhi or mflo instruction? */
282 #define MF_HILO_INSN(PINFO) \
283 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
285 /* MIPS PIC level. */
289 /* Do not generate PIC code. */
292 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
293 not sure what it is supposed to do. */
296 /* Generate PIC code as in the SVR4 MIPS ABI. */
299 /* Generate PIC code without using a global offset table: the data
300 segment has a maximum size of 64K, all data references are off
301 the $gp register, and all text references are PC relative. This
302 is used on some embedded systems. */
306 static enum mips_pic_level mips_pic
;
308 /* 1 if we should generate 32 bit offsets from the GP register in
309 SVR4_PIC mode. Currently has no meaning in other modes. */
310 static int mips_big_got
;
312 /* 1 if trap instructions should used for overflow rather than break
314 static int mips_trap
;
316 /* Non-zero if any .set noreorder directives were used. */
318 static int mips_any_noreorder
;
320 /* Non-zero if nops should be inserted when the register referenced in
321 an mfhi/mflo instruction is read in the next two instructions. */
322 static int mips_7000_hilo_fix
;
324 /* The size of the small data section. */
325 static int g_switch_value
= 8;
326 /* Whether the -G option was used. */
327 static int g_switch_seen
= 0;
332 /* If we can determine in advance that GP optimization won't be
333 possible, we can skip the relaxation stuff that tries to produce
334 GP-relative references. This makes delay slot optimization work
337 This function can only provide a guess, but it seems to work for
338 gcc output. It needs to guess right for gcc, otherwise gcc
339 will put what it thinks is a GP-relative instruction in a branch
342 I don't know if a fix is needed for the SVR4_PIC mode. I've only
343 fixed it for the non-PIC mode. KR 95/04/07 */
344 static int nopic_need_relax
PARAMS ((symbolS
*, int));
346 /* handle of the OPCODE hash table */
347 static struct hash_control
*op_hash
= NULL
;
349 /* The opcode hash table we use for the mips16. */
350 static struct hash_control
*mips16_op_hash
= NULL
;
352 /* This array holds the chars that always start a comment. If the
353 pre-processor is disabled, these aren't very useful */
354 const char comment_chars
[] = "#";
356 /* This array holds the chars that only start a comment at the beginning of
357 a line. If the line seems to have the form '# 123 filename'
358 .line and .file directives will appear in the pre-processed output */
359 /* Note that input_file.c hand checks for '#' at the beginning of the
360 first line of the input file. This is because the compiler outputs
361 #NO_APP at the beginning of its output. */
362 /* Also note that C style comments are always supported. */
363 const char line_comment_chars
[] = "#";
365 /* This array holds machine specific line separator characters. */
366 const char line_separator_chars
[] = ";";
368 /* Chars that can be used to separate mant from exp in floating point nums */
369 const char EXP_CHARS
[] = "eE";
371 /* Chars that mean this number is a floating point constant */
374 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
376 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
377 changed in read.c . Ideally it shouldn't have to know about it at all,
378 but nothing is ideal around here.
381 static char *insn_error
;
383 static int auto_align
= 1;
385 /* When outputting SVR4 PIC code, the assembler needs to know the
386 offset in the stack frame from which to restore the $gp register.
387 This is set by the .cprestore pseudo-op, and saved in this
389 static offsetT mips_cprestore_offset
= -1;
391 /* This is the register which holds the stack frame, as set by the
392 .frame pseudo-op. This is needed to implement .cprestore. */
393 static int mips_frame_reg
= SP
;
395 /* To output NOP instructions correctly, we need to keep information
396 about the previous two instructions. */
398 /* Whether we are optimizing. The default value of 2 means to remove
399 unneeded NOPs and swap branch instructions when possible. A value
400 of 1 means to not swap branches. A value of 0 means to always
402 static int mips_optimize
= 2;
404 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
405 equivalent to seeing no -g option at all. */
406 static int mips_debug
= 0;
408 /* The previous instruction. */
409 static struct mips_cl_insn prev_insn
;
411 /* The instruction before prev_insn. */
412 static struct mips_cl_insn prev_prev_insn
;
414 /* If we don't want information for prev_insn or prev_prev_insn, we
415 point the insn_mo field at this dummy integer. */
416 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
418 /* Non-zero if prev_insn is valid. */
419 static int prev_insn_valid
;
421 /* The frag for the previous instruction. */
422 static struct frag
*prev_insn_frag
;
424 /* The offset into prev_insn_frag for the previous instruction. */
425 static long prev_insn_where
;
427 /* The reloc type for the previous instruction, if any. */
428 static bfd_reloc_code_real_type prev_insn_reloc_type
;
430 /* The reloc for the previous instruction, if any. */
431 static fixS
*prev_insn_fixp
;
433 /* Non-zero if the previous instruction was in a delay slot. */
434 static int prev_insn_is_delay_slot
;
436 /* Non-zero if the previous instruction was in a .set noreorder. */
437 static int prev_insn_unreordered
;
439 /* Non-zero if the previous instruction uses an extend opcode (if
441 static int prev_insn_extended
;
443 /* Non-zero if the previous previous instruction was in a .set
445 static int prev_prev_insn_unreordered
;
447 /* If this is set, it points to a frag holding nop instructions which
448 were inserted before the start of a noreorder section. If those
449 nops turn out to be unnecessary, the size of the frag can be
451 static fragS
*prev_nop_frag
;
453 /* The number of nop instructions we created in prev_nop_frag. */
454 static int prev_nop_frag_holds
;
456 /* The number of nop instructions that we know we need in
458 static int prev_nop_frag_required
;
460 /* The number of instructions we've seen since prev_nop_frag. */
461 static int prev_nop_frag_since
;
463 /* For ECOFF and ELF, relocations against symbols are done in two
464 parts, with a HI relocation and a LO relocation. Each relocation
465 has only 16 bits of space to store an addend. This means that in
466 order for the linker to handle carries correctly, it must be able
467 to locate both the HI and the LO relocation. This means that the
468 relocations must appear in order in the relocation table.
470 In order to implement this, we keep track of each unmatched HI
471 relocation. We then sort them so that they immediately precede the
472 corresponding LO relocation. */
477 struct mips_hi_fixup
*next
;
480 /* The section this fixup is in. */
484 /* The list of unmatched HI relocs. */
486 static struct mips_hi_fixup
*mips_hi_fixup_list
;
488 /* Map normal MIPS register numbers to mips16 register numbers. */
490 #define X ILLEGAL_REG
491 static const int mips32_to_16_reg_map
[] =
493 X
, X
, 2, 3, 4, 5, 6, 7,
494 X
, X
, X
, X
, X
, X
, X
, X
,
495 0, 1, X
, X
, X
, X
, X
, X
,
496 X
, X
, X
, X
, X
, X
, X
, X
500 /* Map mips16 register numbers to normal MIPS register numbers. */
502 static const int mips16_to_32_reg_map
[] =
504 16, 17, 2, 3, 4, 5, 6, 7
507 /* Since the MIPS does not have multiple forms of PC relative
508 instructions, we do not have to do relaxing as is done on other
509 platforms. However, we do have to handle GP relative addressing
510 correctly, which turns out to be a similar problem.
512 Every macro that refers to a symbol can occur in (at least) two
513 forms, one with GP relative addressing and one without. For
514 example, loading a global variable into a register generally uses
515 a macro instruction like this:
517 If i can be addressed off the GP register (this is true if it is in
518 the .sbss or .sdata section, or if it is known to be smaller than
519 the -G argument) this will generate the following instruction:
521 This instruction will use a GPREL reloc. If i can not be addressed
522 off the GP register, the following instruction sequence will be used:
525 In this case the first instruction will have a HI16 reloc, and the
526 second reloc will have a LO16 reloc. Both relocs will be against
529 The issue here is that we may not know whether i is GP addressable
530 until after we see the instruction that uses it. Therefore, we
531 want to be able to choose the final instruction sequence only at
532 the end of the assembly. This is similar to the way other
533 platforms choose the size of a PC relative instruction only at the
536 When generating position independent code we do not use GP
537 addressing in quite the same way, but the issue still arises as
538 external symbols and local symbols must be handled differently.
540 We handle these issues by actually generating both possible
541 instruction sequences. The longer one is put in a frag_var with
542 type rs_machine_dependent. We encode what to do with the frag in
543 the subtype field. We encode (1) the number of existing bytes to
544 replace, (2) the number of new bytes to use, (3) the offset from
545 the start of the existing bytes to the first reloc we must generate
546 (that is, the offset is applied from the start of the existing
547 bytes after they are replaced by the new bytes, if any), (4) the
548 offset from the start of the existing bytes to the second reloc,
549 (5) whether a third reloc is needed (the third reloc is always four
550 bytes after the second reloc), and (6) whether to warn if this
551 variant is used (this is sometimes needed if .set nomacro or .set
552 noat is in effect). All these numbers are reasonably small.
554 Generating two instruction sequences must be handled carefully to
555 ensure that delay slots are handled correctly. Fortunately, there
556 are a limited number of cases. When the second instruction
557 sequence is generated, append_insn is directed to maintain the
558 existing delay slot information, so it continues to apply to any
559 code after the second instruction sequence. This means that the
560 second instruction sequence must not impose any requirements not
561 required by the first instruction sequence.
563 These variant frags are then handled in functions called by the
564 machine independent code. md_estimate_size_before_relax returns
565 the final size of the frag. md_convert_frag sets up the final form
566 of the frag. tc_gen_reloc adjust the first reloc and adds a second
568 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
572 | (((reloc1) + 64) << 9) \
573 | (((reloc2) + 64) << 2) \
574 | ((reloc3) ? (1 << 1) : 0) \
576 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
577 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
578 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
579 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
580 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
581 #define RELAX_WARN(i) ((i) & 1)
583 /* For mips16 code, we use an entirely different form of relaxation.
584 mips16 supports two versions of most instructions which take
585 immediate values: a small one which takes some small value, and a
586 larger one which takes a 16 bit value. Since branches also follow
587 this pattern, relaxing these values is required.
589 We can assemble both mips16 and normal MIPS code in a single
590 object. Therefore, we need to support this type of relaxation at
591 the same time that we support the relaxation described above. We
592 use the high bit of the subtype field to distinguish these cases.
594 The information we store for this type of relaxation is the
595 argument code found in the opcode file for this relocation, whether
596 the user explicitly requested a small or extended form, and whether
597 the relocation is in a jump or jal delay slot. That tells us the
598 size of the value, and how it should be stored. We also store
599 whether the fragment is considered to be extended or not. We also
600 store whether this is known to be a branch to a different section,
601 whether we have tried to relax this frag yet, and whether we have
602 ever extended a PC relative fragment because of a shift count. */
603 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
606 | ((small) ? 0x100 : 0) \
607 | ((ext) ? 0x200 : 0) \
608 | ((dslot) ? 0x400 : 0) \
609 | ((jal_dslot) ? 0x800 : 0))
610 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
611 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
612 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
613 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
614 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
615 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
616 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
617 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
618 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
619 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
620 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
621 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
623 /* Prototypes for static functions. */
626 #define internalError() \
627 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
629 #define internalError() as_fatal (_("MIPS internal Error"));
632 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
634 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
635 unsigned int reg
, enum mips_regclass
class));
636 static int reg_needs_delay
PARAMS ((int));
637 static void mips16_mark_labels
PARAMS ((void));
638 static void append_insn
PARAMS ((char *place
,
639 struct mips_cl_insn
* ip
,
641 bfd_reloc_code_real_type r
,
643 static void mips_no_prev_insn
PARAMS ((int));
644 static void mips_emit_delays
PARAMS ((boolean
));
646 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
647 const char *name
, const char *fmt
,
650 static void macro_build ();
652 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
653 const char *, const char *,
655 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
656 expressionS
* ep
, int regnum
));
657 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
658 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
660 static void load_register
PARAMS ((int *, int, expressionS
*, int));
661 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
662 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
663 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
664 #ifdef LOSING_COMPILER
665 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
667 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
668 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
669 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
670 boolean
, boolean
, unsigned long *,
671 boolean
*, unsigned short *));
672 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
673 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
674 static symbolS
*get_symbol
PARAMS ((void));
675 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
676 static void s_align
PARAMS ((int));
677 static void s_change_sec
PARAMS ((int));
678 static void s_cons
PARAMS ((int));
679 static void s_float_cons
PARAMS ((int));
680 static void s_mips_globl
PARAMS ((int));
681 static void s_option
PARAMS ((int));
682 static void s_mipsset
PARAMS ((int));
683 static void s_abicalls
PARAMS ((int));
684 static void s_cpload
PARAMS ((int));
685 static void s_cprestore
PARAMS ((int));
686 static void s_gpword
PARAMS ((int));
687 static void s_cpadd
PARAMS ((int));
688 static void s_insn
PARAMS ((int));
689 static void md_obj_begin
PARAMS ((void));
690 static void md_obj_end
PARAMS ((void));
691 static long get_number
PARAMS ((void));
692 static void s_mips_ent
PARAMS ((int));
693 static void s_mips_end
PARAMS ((int));
694 static void s_mips_frame
PARAMS ((int));
695 static void s_mips_mask
PARAMS ((int));
696 static void s_mips_stab
PARAMS ((int));
697 static void s_mips_weakext
PARAMS ((int));
698 static void s_file
PARAMS ((int));
699 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
702 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
706 The following pseudo-ops from the Kane and Heinrich MIPS book
707 should be defined here, but are currently unsupported: .alias,
708 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
710 The following pseudo-ops from the Kane and Heinrich MIPS book are
711 specific to the type of debugging information being generated, and
712 should be defined by the object format: .aent, .begin, .bend,
713 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
716 The following pseudo-ops from the Kane and Heinrich MIPS book are
717 not MIPS CPU specific, but are also not specific to the object file
718 format. This file is probably the best place to define them, but
719 they are not currently supported: .asm0, .endr, .lab, .repeat,
722 static const pseudo_typeS mips_pseudo_table
[] =
724 /* MIPS specific pseudo-ops. */
725 {"option", s_option
, 0},
726 {"set", s_mipsset
, 0},
727 {"rdata", s_change_sec
, 'r'},
728 {"sdata", s_change_sec
, 's'},
729 {"livereg", s_ignore
, 0},
730 {"abicalls", s_abicalls
, 0},
731 {"cpload", s_cpload
, 0},
732 {"cprestore", s_cprestore
, 0},
733 {"gpword", s_gpword
, 0},
734 {"cpadd", s_cpadd
, 0},
737 /* Relatively generic pseudo-ops that happen to be used on MIPS
739 {"asciiz", stringer
, 1},
740 {"bss", s_change_sec
, 'b'},
743 {"dword", s_cons
, 3},
744 {"weakext", s_mips_weakext
, 0},
746 /* These pseudo-ops are defined in read.c, but must be overridden
747 here for one reason or another. */
748 {"align", s_align
, 0},
750 {"data", s_change_sec
, 'd'},
751 {"double", s_float_cons
, 'd'},
752 {"float", s_float_cons
, 'f'},
753 {"globl", s_mips_globl
, 0},
754 {"global", s_mips_globl
, 0},
755 {"hword", s_cons
, 1},
760 {"short", s_cons
, 1},
761 {"single", s_float_cons
, 'f'},
762 {"stabn", s_mips_stab
, 'n'},
763 {"text", s_change_sec
, 't'},
768 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
769 /* These pseudo-ops should be defined by the object file format.
770 However, a.out doesn't support them, so we have versions here. */
771 {"aent", s_mips_ent
, 1},
772 {"bgnb", s_ignore
, 0},
773 {"end", s_mips_end
, 0},
774 {"endb", s_ignore
, 0},
775 {"ent", s_mips_ent
, 0},
777 {"fmask", s_mips_mask
, 'F'},
778 {"frame", s_mips_frame
, 0},
779 {"loc", s_ignore
, 0},
780 {"mask", s_mips_mask
, 'R'},
781 {"verstamp", s_ignore
, 0},
785 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
790 pop_insert (mips_pseudo_table
);
791 if (! ECOFF_DEBUGGING
)
792 pop_insert (mips_nonecoff_pseudo_table
);
795 /* Symbols labelling the current insn. */
797 struct insn_label_list
799 struct insn_label_list
*next
;
803 static struct insn_label_list
*insn_labels
;
804 static struct insn_label_list
*free_insn_labels
;
806 static void mips_clear_insn_labels
PARAMS ((void));
809 mips_clear_insn_labels ()
811 register struct insn_label_list
**pl
;
813 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
819 static char *expr_end
;
821 /* Expressions which appear in instructions. These are set by
824 static expressionS imm_expr
;
825 static expressionS offset_expr
;
827 /* Relocs associated with imm_expr and offset_expr. */
829 static bfd_reloc_code_real_type imm_reloc
;
830 static bfd_reloc_code_real_type offset_reloc
;
832 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
834 static boolean imm_unmatched_hi
;
836 /* These are set by mips16_ip if an explicit extension is used. */
838 static boolean mips16_small
, mips16_ext
;
840 #ifdef MIPS_STABS_ELF
841 /* The pdr segment for per procedure frame/regmask info */
847 * This function is called once, at assembler startup time. It should
848 * set up all the tables, etc. that the MD part of the assembler will need.
854 register const char *retval
= NULL
;
855 register unsigned int i
= 0;
859 int mips_isa_from_cpu
;
861 /* GP relative stuff not working for PE */
862 if (strncmp (TARGET_OS
, "pe", 2) == 0
863 && g_switch_value
!= 0)
866 as_bad (_("-G not supported in this configuration."));
871 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
873 a
= xmalloc (sizeof TARGET_CPU
);
874 strcpy (a
, TARGET_CPU
);
875 a
[(sizeof TARGET_CPU
) - 3] = '\0';
881 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
882 just the generic 'mips', in which case set mips_cpu based
883 on the given ISA, if any. */
885 if (strcmp (cpu
, "mips") == 0)
887 if (mips_opts
.isa
< 0)
890 else if (mips_opts
.isa
== 2)
893 else if (mips_opts
.isa
== 3)
896 else if (mips_opts
.isa
== 4)
903 else if (strcmp (cpu
, "r3900") == 0
904 || strcmp (cpu
, "mipstx39") == 0
908 else if (strcmp (cpu
, "r6000") == 0
909 || strcmp (cpu
, "mips2") == 0)
912 else if (strcmp (cpu
, "mips64") == 0
913 || strcmp (cpu
, "r4000") == 0
914 || strcmp (cpu
, "mips3") == 0)
917 else if (strcmp (cpu
, "r4400") == 0)
920 else if (strcmp (cpu
, "mips64orion") == 0
921 || strcmp (cpu
, "r4600") == 0)
924 else if (strcmp (cpu
, "r4650") == 0)
927 else if (strcmp (cpu
, "mips64vr4300") == 0)
930 else if (strcmp (cpu
, "mips64vr4111") == 0)
933 else if (strcmp (cpu
, "mips64vr4100") == 0)
936 else if (strcmp (cpu
, "r4010") == 0)
940 else if (strcmp (cpu
, "r5000") == 0
941 || strcmp (cpu
, "mips64vr5000") == 0)
946 else if (strcmp (cpu
, "r8000") == 0
947 || strcmp (cpu
, "mips4") == 0)
950 else if (strcmp (cpu
, "r10000") == 0)
953 else if (strcmp (cpu
, "mips16") == 0)
954 mips_cpu
= 0; /* FIXME */
962 mips_isa_from_cpu
= 1;
964 else if (mips_cpu
== 6000
966 mips_isa_from_cpu
= 2;
968 else if (mips_cpu
== 4000
975 mips_isa_from_cpu
= 3;
977 else if (mips_cpu
== 5000
979 || mips_cpu
== 10000)
980 mips_isa_from_cpu
= 4;
983 mips_isa_from_cpu
= -1;
985 if (mips_opts
.isa
== -1)
987 if (mips_isa_from_cpu
!= -1)
988 mips_opts
.isa
= mips_isa_from_cpu
;
993 if (mips_opts
.mips16
< 0)
995 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
996 mips_opts
.mips16
= 1;
998 mips_opts
.mips16
= 0;
1001 /* End of TARGET_CPU processing, get rid of malloced memory
1010 if (mips_opts
.isa
== 1 && mips_trap
)
1011 as_bad (_("trap exception not supported at ISA 1"));
1013 /* Set the EABI kind based on the ISA before the user gets
1014 to change the ISA with directives. This isn't really
1015 the best, but then neither is basing the abi on the isa. */
1016 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1018 && 0 == strcmp (mips_abi_string
,"eabi"))
1021 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1023 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1025 /* If they asked for mips1 or mips2 and a cpu that is
1026 mips3 or greater, then mark the object file 32BITMODE. */
1027 if (mips_isa_from_cpu
!= -1
1028 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1029 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1034 switch (mips_opts
.isa
)
1037 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1040 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1043 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1046 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1052 as_warn (_("Could not set architecture and machine"));
1054 file_mips_isa
= mips_opts
.isa
;
1056 op_hash
= hash_new ();
1058 for (i
= 0; i
< NUMOPCODES
;)
1060 const char *name
= mips_opcodes
[i
].name
;
1062 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1065 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1066 mips_opcodes
[i
].name
, retval
);
1067 /* Probably a memory allocation problem? Give up now. */
1068 as_fatal (_("Broken assembler. No assembly attempted."));
1072 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1074 if (!validate_mips_insn (&mips_opcodes
[i
]))
1079 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1082 mips16_op_hash
= hash_new ();
1085 while (i
< bfd_mips16_num_opcodes
)
1087 const char *name
= mips16_opcodes
[i
].name
;
1089 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1091 as_fatal (_("internal: can't hash `%s': %s"),
1092 mips16_opcodes
[i
].name
, retval
);
1095 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1096 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1097 != mips16_opcodes
[i
].match
))
1099 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1100 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1105 while (i
< bfd_mips16_num_opcodes
1106 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1110 as_fatal (_("Broken assembler. No assembly attempted."));
1112 /* We add all the general register names to the symbol table. This
1113 helps us detect invalid uses of them. */
1114 for (i
= 0; i
< 32; i
++)
1118 sprintf (buf
, "$%d", i
);
1119 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1120 &zero_address_frag
));
1122 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1123 &zero_address_frag
));
1124 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1125 &zero_address_frag
));
1126 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1127 &zero_address_frag
));
1128 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1129 &zero_address_frag
));
1130 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1131 &zero_address_frag
));
1132 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1133 &zero_address_frag
));
1134 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1135 &zero_address_frag
));
1137 mips_no_prev_insn (false);
1140 mips_cprmask
[0] = 0;
1141 mips_cprmask
[1] = 0;
1142 mips_cprmask
[2] = 0;
1143 mips_cprmask
[3] = 0;
1145 /* set the default alignment for the text section (2**2) */
1146 record_alignment (text_section
, 2);
1148 if (USE_GLOBAL_POINTER_OPT
)
1149 bfd_set_gp_size (stdoutput
, g_switch_value
);
1151 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1153 /* On a native system, sections must be aligned to 16 byte
1154 boundaries. When configured for an embedded ELF target, we
1156 if (strcmp (TARGET_OS
, "elf") != 0)
1158 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1159 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1160 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1163 /* Create a .reginfo section for register masks and a .mdebug
1164 section for debugging information. */
1172 subseg
= now_subseg
;
1174 /* The ABI says this section should be loaded so that the
1175 running program can access it. However, we don't load it
1176 if we are configured for an embedded target */
1177 flags
= SEC_READONLY
| SEC_DATA
;
1178 if (strcmp (TARGET_OS
, "elf") != 0)
1179 flags
|= SEC_ALLOC
| SEC_LOAD
;
1183 sec
= subseg_new (".reginfo", (subsegT
) 0);
1186 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1187 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1190 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1195 /* The 64-bit ABI uses a .MIPS.options section rather than
1196 .reginfo section. */
1197 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1198 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1199 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1202 /* Set up the option header. */
1204 Elf_Internal_Options opthdr
;
1207 opthdr
.kind
= ODK_REGINFO
;
1208 opthdr
.size
= (sizeof (Elf_External_Options
)
1209 + sizeof (Elf64_External_RegInfo
));
1212 f
= frag_more (sizeof (Elf_External_Options
));
1213 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1214 (Elf_External_Options
*) f
);
1216 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1221 if (ECOFF_DEBUGGING
)
1223 sec
= subseg_new (".mdebug", (subsegT
) 0);
1224 (void) bfd_set_section_flags (stdoutput
, sec
,
1225 SEC_HAS_CONTENTS
| SEC_READONLY
);
1226 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1229 #ifdef MIPS_STABS_ELF
1230 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1231 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1232 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1233 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1236 subseg_set (seg
, subseg
);
1240 if (! ECOFF_DEBUGGING
)
1247 if (! ECOFF_DEBUGGING
)
1255 struct mips_cl_insn insn
;
1257 imm_expr
.X_op
= O_absent
;
1258 imm_reloc
= BFD_RELOC_UNUSED
;
1259 imm_unmatched_hi
= false;
1260 offset_expr
.X_op
= O_absent
;
1261 offset_reloc
= BFD_RELOC_UNUSED
;
1263 if (mips_opts
.mips16
)
1264 mips16_ip (str
, &insn
);
1267 mips_ip (str
, &insn
);
1268 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1269 str
, insn
.insn_opcode
));
1274 as_bad ("%s `%s'", insn_error
, str
);
1278 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1280 if (mips_opts
.mips16
)
1281 mips16_macro (&insn
);
1287 if (imm_expr
.X_op
!= O_absent
)
1288 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1290 else if (offset_expr
.X_op
!= O_absent
)
1291 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1293 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1297 /* See whether instruction IP reads register REG. CLASS is the type
1301 insn_uses_reg (ip
, reg
, class)
1302 struct mips_cl_insn
*ip
;
1304 enum mips_regclass
class;
1306 if (class == MIPS16_REG
)
1308 assert (mips_opts
.mips16
);
1309 reg
= mips16_to_32_reg_map
[reg
];
1310 class = MIPS_GR_REG
;
1313 /* Don't report on general register 0, since it never changes. */
1314 if (class == MIPS_GR_REG
&& reg
== 0)
1317 if (class == MIPS_FP_REG
)
1319 assert (! mips_opts
.mips16
);
1320 /* If we are called with either $f0 or $f1, we must check $f0.
1321 This is not optimal, because it will introduce an unnecessary
1322 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1323 need to distinguish reading both $f0 and $f1 or just one of
1324 them. Note that we don't have to check the other way,
1325 because there is no instruction that sets both $f0 and $f1
1326 and requires a delay. */
1327 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1328 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1329 == (reg
&~ (unsigned) 1)))
1331 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1332 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1333 == (reg
&~ (unsigned) 1)))
1336 else if (! mips_opts
.mips16
)
1338 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1339 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1341 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1342 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1347 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1348 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1349 & MIPS16OP_MASK_RX
)]
1352 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1353 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1354 & MIPS16OP_MASK_RY
)]
1357 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1358 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1359 & MIPS16OP_MASK_MOVE32Z
)]
1362 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1364 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1366 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1368 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1369 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1370 & MIPS16OP_MASK_REGR32
) == reg
)
1377 /* This function returns true if modifying a register requires a
1381 reg_needs_delay (reg
)
1384 unsigned long prev_pinfo
;
1386 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1387 if (! mips_opts
.noreorder
1388 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1389 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1390 || (! gpr_interlocks
1391 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1393 /* A load from a coprocessor or from memory. All load
1394 delays delay the use of general register rt for one
1395 instruction on the r3000. The r6000 and r4000 use
1397 /* Itbl support may require additional care here. */
1398 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1399 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1406 /* Mark instruction labels in mips16 mode. This permits the linker to
1407 handle them specially, such as generating jalx instructions when
1408 needed. We also make them odd for the duration of the assembly, in
1409 order to generate the right sort of code. We will make them even
1410 in the adjust_symtab routine, while leaving them marked. This is
1411 convenient for the debugger and the disassembler. The linker knows
1412 to make them odd again. */
1415 mips16_mark_labels ()
1417 if (mips_opts
.mips16
)
1419 struct insn_label_list
*l
;
1421 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1424 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1425 S_SET_OTHER (l
->label
, STO_MIPS16
);
1427 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1428 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1433 /* Output an instruction. PLACE is where to put the instruction; if
1434 it is NULL, this uses frag_more to get room. IP is the instruction
1435 information. ADDRESS_EXPR is an operand of the instruction to be
1436 used with RELOC_TYPE. */
1439 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1441 struct mips_cl_insn
*ip
;
1442 expressionS
*address_expr
;
1443 bfd_reloc_code_real_type reloc_type
;
1444 boolean unmatched_hi
;
1446 register unsigned long prev_pinfo
, pinfo
;
1451 /* Mark instruction labels in mips16 mode. */
1452 if (mips_opts
.mips16
)
1453 mips16_mark_labels ();
1455 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1456 pinfo
= ip
->insn_mo
->pinfo
;
1458 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1462 /* If the previous insn required any delay slots, see if we need
1463 to insert a NOP or two. There are eight kinds of possible
1464 hazards, of which an instruction can have at most one type.
1465 (1) a load from memory delay
1466 (2) a load from a coprocessor delay
1467 (3) an unconditional branch delay
1468 (4) a conditional branch delay
1469 (5) a move to coprocessor register delay
1470 (6) a load coprocessor register from memory delay
1471 (7) a coprocessor condition code delay
1472 (8) a HI/LO special register delay
1474 There are a lot of optimizations we could do that we don't.
1475 In particular, we do not, in general, reorder instructions.
1476 If you use gcc with optimization, it will reorder
1477 instructions and generally do much more optimization then we
1478 do here; repeating all that work in the assembler would only
1479 benefit hand written assembly code, and does not seem worth
1482 /* This is how a NOP is emitted. */
1483 #define emit_nop() \
1485 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1486 : md_number_to_chars (frag_more (4), 0, 4))
1488 /* The previous insn might require a delay slot, depending upon
1489 the contents of the current insn. */
1490 if (! mips_opts
.mips16
1491 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1492 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1493 && ! cop_interlocks
)
1494 || (! gpr_interlocks
1495 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1497 /* A load from a coprocessor or from memory. All load
1498 delays delay the use of general register rt for one
1499 instruction on the r3000. The r6000 and r4000 use
1501 /* Itbl support may require additional care here. */
1502 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1503 if (mips_optimize
== 0
1504 || insn_uses_reg (ip
,
1505 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1510 else if (! mips_opts
.mips16
1511 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1512 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1513 && ! cop_interlocks
)
1514 || (mips_opts
.isa
== 1
1515 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1517 /* A generic coprocessor delay. The previous instruction
1518 modified a coprocessor general or control register. If
1519 it modified a control register, we need to avoid any
1520 coprocessor instruction (this is probably not always
1521 required, but it sometimes is). If it modified a general
1522 register, we avoid using that register.
1524 On the r6000 and r4000 loading a coprocessor register
1525 from memory is interlocked, and does not require a delay.
1527 This case is not handled very well. There is no special
1528 knowledge of CP0 handling, and the coprocessors other
1529 than the floating point unit are not distinguished at
1531 /* Itbl support may require additional care here. FIXME!
1532 Need to modify this to include knowledge about
1533 user specified delays! */
1534 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1536 if (mips_optimize
== 0
1537 || insn_uses_reg (ip
,
1538 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1543 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1545 if (mips_optimize
== 0
1546 || insn_uses_reg (ip
,
1547 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1554 /* We don't know exactly what the previous instruction
1555 does. If the current instruction uses a coprocessor
1556 register, we must insert a NOP. If previous
1557 instruction may set the condition codes, and the
1558 current instruction uses them, we must insert two
1560 /* Itbl support may require additional care here. */
1561 if (mips_optimize
== 0
1562 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1563 && (pinfo
& INSN_READ_COND_CODE
)))
1565 else if (pinfo
& INSN_COP
)
1569 else if (! mips_opts
.mips16
1570 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1571 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1572 && ! cop_interlocks
)
1574 /* The previous instruction sets the coprocessor condition
1575 codes, but does not require a general coprocessor delay
1576 (this means it is a floating point comparison
1577 instruction). If this instruction uses the condition
1578 codes, we need to insert a single NOP. */
1579 /* Itbl support may require additional care here. */
1580 if (mips_optimize
== 0
1581 || (pinfo
& INSN_READ_COND_CODE
))
1585 /* If we're fixing up mfhi/mflo for the r7000 and the
1586 previous insn was an mfhi/mflo and the current insn
1587 reads the register that the mfhi/mflo wrote to, then
1590 else if (mips_7000_hilo_fix
1591 && MF_HILO_INSN (prev_pinfo
)
1592 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1600 /* If we're fixing up mfhi/mflo for the r7000 and the
1601 2nd previous insn was an mfhi/mflo and the current insn
1602 reads the register that the mfhi/mflo wrote to, then
1605 else if (mips_7000_hilo_fix
1606 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1607 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1615 else if (prev_pinfo
& INSN_READ_LO
)
1617 /* The previous instruction reads the LO register; if the
1618 current instruction writes to the LO register, we must
1619 insert two NOPS. Some newer processors have interlocks.
1620 Also the tx39's multiply instructions can be exectuted
1621 immediatly after a read from HI/LO (without the delay),
1622 though the tx39's divide insns still do require the
1624 if (! (hilo_interlocks
1625 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1626 && (mips_optimize
== 0
1627 || (pinfo
& INSN_WRITE_LO
)))
1629 /* Most mips16 branch insns don't have a delay slot.
1630 If a read from LO is immediately followed by a branch
1631 to a write to LO we have a read followed by a write
1632 less than 2 insns away. We assume the target of
1633 a branch might be a write to LO, and insert a nop
1634 between a read and an immediately following branch. */
1635 else if (mips_opts
.mips16
1636 && (mips_optimize
== 0
1637 || (pinfo
& MIPS16_INSN_BRANCH
)))
1640 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1642 /* The previous instruction reads the HI register; if the
1643 current instruction writes to the HI register, we must
1644 insert a NOP. Some newer processors have interlocks.
1645 Also the note tx39's multiply above. */
1646 if (! (hilo_interlocks
1647 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1648 && (mips_optimize
== 0
1649 || (pinfo
& INSN_WRITE_HI
)))
1651 /* Most mips16 branch insns don't have a delay slot.
1652 If a read from HI is immediately followed by a branch
1653 to a write to HI we have a read followed by a write
1654 less than 2 insns away. We assume the target of
1655 a branch might be a write to HI, and insert a nop
1656 between a read and an immediately following branch. */
1657 else if (mips_opts
.mips16
1658 && (mips_optimize
== 0
1659 || (pinfo
& MIPS16_INSN_BRANCH
)))
1663 /* If the previous instruction was in a noreorder section, then
1664 we don't want to insert the nop after all. */
1665 /* Itbl support may require additional care here. */
1666 if (prev_insn_unreordered
)
1669 /* There are two cases which require two intervening
1670 instructions: 1) setting the condition codes using a move to
1671 coprocessor instruction which requires a general coprocessor
1672 delay and then reading the condition codes 2) reading the HI
1673 or LO register and then writing to it (except on processors
1674 which have interlocks). If we are not already emitting a NOP
1675 instruction, we must check for these cases compared to the
1676 instruction previous to the previous instruction. */
1677 if ((! mips_opts
.mips16
1678 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1679 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1680 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1681 && (pinfo
& INSN_READ_COND_CODE
)
1682 && ! cop_interlocks
)
1683 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1684 && (pinfo
& INSN_WRITE_LO
)
1685 && ! (hilo_interlocks
1686 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1687 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1688 && (pinfo
& INSN_WRITE_HI
)
1689 && ! (hilo_interlocks
1690 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1695 if (prev_prev_insn_unreordered
)
1698 if (prev_prev_nop
&& nops
== 0)
1701 /* If we are being given a nop instruction, don't bother with
1702 one of the nops we would otherwise output. This will only
1703 happen when a nop instruction is used with mips_optimize set
1706 && ! mips_opts
.noreorder
1707 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1710 /* Now emit the right number of NOP instructions. */
1711 if (nops
> 0 && ! mips_opts
.noreorder
)
1714 unsigned long old_frag_offset
;
1716 struct insn_label_list
*l
;
1718 old_frag
= frag_now
;
1719 old_frag_offset
= frag_now_fix ();
1721 for (i
= 0; i
< nops
; i
++)
1726 listing_prev_line ();
1727 /* We may be at the start of a variant frag. In case we
1728 are, make sure there is enough space for the frag
1729 after the frags created by listing_prev_line. The
1730 argument to frag_grow here must be at least as large
1731 as the argument to all other calls to frag_grow in
1732 this file. We don't have to worry about being in the
1733 middle of a variant frag, because the variants insert
1734 all needed nop instructions themselves. */
1738 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1740 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1741 symbol_set_frag (l
->label
, frag_now
);
1742 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1743 /* mips16 text labels are stored as odd. */
1744 if (mips_opts
.mips16
)
1745 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1748 #ifndef NO_ECOFF_DEBUGGING
1749 if (ECOFF_DEBUGGING
)
1750 ecoff_fix_loc (old_frag
, old_frag_offset
);
1753 else if (prev_nop_frag
!= NULL
)
1755 /* We have a frag holding nops we may be able to remove. If
1756 we don't need any nops, we can decrease the size of
1757 prev_nop_frag by the size of one instruction. If we do
1758 need some nops, we count them in prev_nops_required. */
1759 if (prev_nop_frag_since
== 0)
1763 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1764 --prev_nop_frag_holds
;
1767 prev_nop_frag_required
+= nops
;
1771 if (prev_prev_nop
== 0)
1773 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1774 --prev_nop_frag_holds
;
1777 ++prev_nop_frag_required
;
1780 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1781 prev_nop_frag
= NULL
;
1783 ++prev_nop_frag_since
;
1785 /* Sanity check: by the time we reach the second instruction
1786 after prev_nop_frag, we should have used up all the nops
1787 one way or another. */
1788 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1792 if (reloc_type
> BFD_RELOC_UNUSED
)
1794 /* We need to set up a variant frag. */
1795 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1796 f
= frag_var (rs_machine_dependent
, 4, 0,
1797 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1798 mips16_small
, mips16_ext
,
1800 & INSN_UNCOND_BRANCH_DELAY
),
1801 (prev_insn_reloc_type
1802 == BFD_RELOC_MIPS16_JMP
)),
1803 make_expr_symbol (address_expr
), (offsetT
) 0,
1806 else if (place
!= NULL
)
1808 else if (mips_opts
.mips16
1810 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1812 /* Make sure there is enough room to swap this instruction with
1813 a following jump instruction. */
1819 if (mips_opts
.mips16
1820 && mips_opts
.noreorder
1821 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1822 as_warn (_("extended instruction in delay slot"));
1828 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1830 if (address_expr
->X_op
== O_constant
)
1835 ip
->insn_opcode
|= address_expr
->X_add_number
;
1838 case BFD_RELOC_LO16
:
1839 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1842 case BFD_RELOC_MIPS_JMP
:
1843 if ((address_expr
->X_add_number
& 3) != 0)
1844 as_bad (_("jump to misaligned address (0x%lx)"),
1845 (unsigned long) address_expr
->X_add_number
);
1846 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1849 case BFD_RELOC_MIPS16_JMP
:
1850 if ((address_expr
->X_add_number
& 3) != 0)
1851 as_bad (_("jump to misaligned address (0x%lx)"),
1852 (unsigned long) address_expr
->X_add_number
);
1854 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1855 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1856 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1860 case BFD_RELOC_16_PCREL_S2
:
1870 /* Don't generate a reloc if we are writing into a variant
1874 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1876 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1880 struct mips_hi_fixup
*hi_fixup
;
1882 assert (reloc_type
== BFD_RELOC_HI16_S
);
1883 hi_fixup
= ((struct mips_hi_fixup
*)
1884 xmalloc (sizeof (struct mips_hi_fixup
)));
1885 hi_fixup
->fixp
= fixp
;
1886 hi_fixup
->seg
= now_seg
;
1887 hi_fixup
->next
= mips_hi_fixup_list
;
1888 mips_hi_fixup_list
= hi_fixup
;
1894 if (! mips_opts
.mips16
)
1895 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1896 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1898 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1899 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1905 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1908 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1911 /* Update the register mask information. */
1912 if (! mips_opts
.mips16
)
1914 if (pinfo
& INSN_WRITE_GPR_D
)
1915 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1916 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1917 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1918 if (pinfo
& INSN_READ_GPR_S
)
1919 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1920 if (pinfo
& INSN_WRITE_GPR_31
)
1921 mips_gprmask
|= 1 << 31;
1922 if (pinfo
& INSN_WRITE_FPR_D
)
1923 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1924 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1925 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1926 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1927 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1928 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1929 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1930 if (pinfo
& INSN_COP
)
1932 /* We don't keep enough information to sort these cases out.
1933 The itbl support does keep this information however, although
1934 we currently don't support itbl fprmats as part of the cop
1935 instruction. May want to add this support in the future. */
1937 /* Never set the bit for $0, which is always zero. */
1938 mips_gprmask
&=~ 1 << 0;
1942 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1943 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1944 & MIPS16OP_MASK_RX
);
1945 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1946 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1947 & MIPS16OP_MASK_RY
);
1948 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1949 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1950 & MIPS16OP_MASK_RZ
);
1951 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1952 mips_gprmask
|= 1 << TREG
;
1953 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1954 mips_gprmask
|= 1 << SP
;
1955 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1956 mips_gprmask
|= 1 << RA
;
1957 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1958 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1959 if (pinfo
& MIPS16_INSN_READ_Z
)
1960 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1961 & MIPS16OP_MASK_MOVE32Z
);
1962 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1963 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1964 & MIPS16OP_MASK_REGR32
);
1967 if (place
== NULL
&& ! mips_opts
.noreorder
)
1969 /* Filling the branch delay slot is more complex. We try to
1970 switch the branch with the previous instruction, which we can
1971 do if the previous instruction does not set up a condition
1972 that the branch tests and if the branch is not itself the
1973 target of any branch. */
1974 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1975 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1977 if (mips_optimize
< 2
1978 /* If we have seen .set volatile or .set nomove, don't
1980 || mips_opts
.nomove
!= 0
1981 /* If we had to emit any NOP instructions, then we
1982 already know we can not swap. */
1984 /* If we don't even know the previous insn, we can not
1986 || ! prev_insn_valid
1987 /* If the previous insn is already in a branch delay
1988 slot, then we can not swap. */
1989 || prev_insn_is_delay_slot
1990 /* If the previous previous insn was in a .set
1991 noreorder, we can't swap. Actually, the MIPS
1992 assembler will swap in this situation. However, gcc
1993 configured -with-gnu-as will generate code like
1999 in which we can not swap the bne and INSN. If gcc is
2000 not configured -with-gnu-as, it does not output the
2001 .set pseudo-ops. We don't have to check
2002 prev_insn_unreordered, because prev_insn_valid will
2003 be 0 in that case. We don't want to use
2004 prev_prev_insn_valid, because we do want to be able
2005 to swap at the start of a function. */
2006 || prev_prev_insn_unreordered
2007 /* If the branch is itself the target of a branch, we
2008 can not swap. We cheat on this; all we check for is
2009 whether there is a label on this instruction. If
2010 there are any branches to anything other than a
2011 label, users must use .set noreorder. */
2012 || insn_labels
!= NULL
2013 /* If the previous instruction is in a variant frag, we
2014 can not do the swap. This does not apply to the
2015 mips16, which uses variant frags for different
2017 || (! mips_opts
.mips16
2018 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2019 /* If the branch reads the condition codes, we don't
2020 even try to swap, because in the sequence
2025 we can not swap, and I don't feel like handling that
2027 || (! mips_opts
.mips16
2028 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2029 && (pinfo
& INSN_READ_COND_CODE
))
2030 /* We can not swap with an instruction that requires a
2031 delay slot, becase the target of the branch might
2032 interfere with that instruction. */
2033 || (! mips_opts
.mips16
2034 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2036 /* Itbl support may require additional care here. */
2037 & (INSN_LOAD_COPROC_DELAY
2038 | INSN_COPROC_MOVE_DELAY
2039 | INSN_WRITE_COND_CODE
)))
2040 || (! (hilo_interlocks
2041 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2045 || (! mips_opts
.mips16
2047 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2048 || (! mips_opts
.mips16
2049 && mips_opts
.isa
== 1
2050 /* Itbl support may require additional care here. */
2051 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2052 /* We can not swap with a branch instruction. */
2054 & (INSN_UNCOND_BRANCH_DELAY
2055 | INSN_COND_BRANCH_DELAY
2056 | INSN_COND_BRANCH_LIKELY
))
2057 /* We do not swap with a trap instruction, since it
2058 complicates trap handlers to have the trap
2059 instruction be in a delay slot. */
2060 || (prev_pinfo
& INSN_TRAP
)
2061 /* If the branch reads a register that the previous
2062 instruction sets, we can not swap. */
2063 || (! mips_opts
.mips16
2064 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2065 && insn_uses_reg (ip
,
2066 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2069 || (! mips_opts
.mips16
2070 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2071 && insn_uses_reg (ip
,
2072 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2075 || (mips_opts
.mips16
2076 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2077 && insn_uses_reg (ip
,
2078 ((prev_insn
.insn_opcode
2080 & MIPS16OP_MASK_RX
),
2082 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2083 && insn_uses_reg (ip
,
2084 ((prev_insn
.insn_opcode
2086 & MIPS16OP_MASK_RY
),
2088 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2089 && insn_uses_reg (ip
,
2090 ((prev_insn
.insn_opcode
2092 & MIPS16OP_MASK_RZ
),
2094 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2095 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2096 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2097 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2098 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2099 && insn_uses_reg (ip
,
2100 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2103 /* If the branch writes a register that the previous
2104 instruction sets, we can not swap (we know that
2105 branches write only to RD or to $31). */
2106 || (! mips_opts
.mips16
2107 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2108 && (((pinfo
& INSN_WRITE_GPR_D
)
2109 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2110 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2111 || ((pinfo
& INSN_WRITE_GPR_31
)
2112 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2115 || (! mips_opts
.mips16
2116 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2117 && (((pinfo
& INSN_WRITE_GPR_D
)
2118 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2119 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2120 || ((pinfo
& INSN_WRITE_GPR_31
)
2121 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2124 || (mips_opts
.mips16
2125 && (pinfo
& MIPS16_INSN_WRITE_31
)
2126 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2127 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2128 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2130 /* If the branch writes a register that the previous
2131 instruction reads, we can not swap (we know that
2132 branches only write to RD or to $31). */
2133 || (! mips_opts
.mips16
2134 && (pinfo
& INSN_WRITE_GPR_D
)
2135 && insn_uses_reg (&prev_insn
,
2136 ((ip
->insn_opcode
>> OP_SH_RD
)
2139 || (! mips_opts
.mips16
2140 && (pinfo
& INSN_WRITE_GPR_31
)
2141 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2142 || (mips_opts
.mips16
2143 && (pinfo
& MIPS16_INSN_WRITE_31
)
2144 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2145 /* If we are generating embedded PIC code, the branch
2146 might be expanded into a sequence which uses $at, so
2147 we can't swap with an instruction which reads it. */
2148 || (mips_pic
== EMBEDDED_PIC
2149 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2150 /* If the previous previous instruction has a load
2151 delay, and sets a register that the branch reads, we
2153 || (! mips_opts
.mips16
2154 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2155 /* Itbl support may require additional care here. */
2156 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2157 || (! gpr_interlocks
2158 && (prev_prev_insn
.insn_mo
->pinfo
2159 & INSN_LOAD_MEMORY_DELAY
)))
2160 && insn_uses_reg (ip
,
2161 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2164 /* If one instruction sets a condition code and the
2165 other one uses a condition code, we can not swap. */
2166 || ((pinfo
& INSN_READ_COND_CODE
)
2167 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2168 || ((pinfo
& INSN_WRITE_COND_CODE
)
2169 && (prev_pinfo
& INSN_READ_COND_CODE
))
2170 /* If the previous instruction uses the PC, we can not
2172 || (mips_opts
.mips16
2173 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2174 /* If the previous instruction was extended, we can not
2176 || (mips_opts
.mips16
&& prev_insn_extended
)
2177 /* If the previous instruction had a fixup in mips16
2178 mode, we can not swap. This normally means that the
2179 previous instruction was a 4 byte branch anyhow. */
2180 || (mips_opts
.mips16
&& prev_insn_fixp
)
2181 /* If the previous instruction is a sync, sync.l, or
2182 sync.p, we can not swap. */
2183 || (prev_pinfo
& INSN_SYNC
))
2185 /* We could do even better for unconditional branches to
2186 portions of this object file; we could pick up the
2187 instruction at the destination, put it in the delay
2188 slot, and bump the destination address. */
2190 /* Update the previous insn information. */
2191 prev_prev_insn
= *ip
;
2192 prev_insn
.insn_mo
= &dummy_opcode
;
2196 /* It looks like we can actually do the swap. */
2197 if (! mips_opts
.mips16
)
2202 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2203 memcpy (temp
, prev_f
, 4);
2204 memcpy (prev_f
, f
, 4);
2205 memcpy (f
, temp
, 4);
2208 prev_insn_fixp
->fx_frag
= frag_now
;
2209 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2213 fixp
->fx_frag
= prev_insn_frag
;
2214 fixp
->fx_where
= prev_insn_where
;
2222 assert (prev_insn_fixp
== NULL
);
2223 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2224 memcpy (temp
, prev_f
, 2);
2225 memcpy (prev_f
, f
, 2);
2226 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2228 assert (reloc_type
== BFD_RELOC_UNUSED
);
2229 memcpy (f
, temp
, 2);
2233 memcpy (f
, f
+ 2, 2);
2234 memcpy (f
+ 2, temp
, 2);
2238 fixp
->fx_frag
= prev_insn_frag
;
2239 fixp
->fx_where
= prev_insn_where
;
2243 /* Update the previous insn information; leave prev_insn
2245 prev_prev_insn
= *ip
;
2247 prev_insn_is_delay_slot
= 1;
2249 /* If that was an unconditional branch, forget the previous
2250 insn information. */
2251 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2253 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2254 prev_insn
.insn_mo
= &dummy_opcode
;
2257 prev_insn_fixp
= NULL
;
2258 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2259 prev_insn_extended
= 0;
2261 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2263 /* We don't yet optimize a branch likely. What we should do
2264 is look at the target, copy the instruction found there
2265 into the delay slot, and increment the branch to jump to
2266 the next instruction. */
2268 /* Update the previous insn information. */
2269 prev_prev_insn
= *ip
;
2270 prev_insn
.insn_mo
= &dummy_opcode
;
2271 prev_insn_fixp
= NULL
;
2272 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2273 prev_insn_extended
= 0;
2277 /* Update the previous insn information. */
2279 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2281 prev_prev_insn
= prev_insn
;
2284 /* Any time we see a branch, we always fill the delay slot
2285 immediately; since this insn is not a branch, we know it
2286 is not in a delay slot. */
2287 prev_insn_is_delay_slot
= 0;
2289 prev_insn_fixp
= fixp
;
2290 prev_insn_reloc_type
= reloc_type
;
2291 if (mips_opts
.mips16
)
2292 prev_insn_extended
= (ip
->use_extend
2293 || reloc_type
> BFD_RELOC_UNUSED
);
2296 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2297 prev_insn_unreordered
= 0;
2298 prev_insn_frag
= frag_now
;
2299 prev_insn_where
= f
- frag_now
->fr_literal
;
2300 prev_insn_valid
= 1;
2302 else if (place
== NULL
)
2304 /* We need to record a bit of information even when we are not
2305 reordering, in order to determine the base address for mips16
2306 PC relative relocs. */
2307 prev_prev_insn
= prev_insn
;
2309 prev_insn_reloc_type
= reloc_type
;
2310 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2311 prev_insn_unreordered
= 1;
2314 /* We just output an insn, so the next one doesn't have a label. */
2315 mips_clear_insn_labels ();
2317 /* We must ensure that a fixup associated with an unmatched %hi
2318 reloc does not become a variant frag. Otherwise, the
2319 rearrangement of %hi relocs in frob_file may confuse
2323 frag_wane (frag_now
);
2328 /* This function forgets that there was any previous instruction or
2329 label. If PRESERVE is non-zero, it remembers enough information to
2330 know whether nops are needed before a noreorder section. */
2333 mips_no_prev_insn (preserve
)
2338 prev_insn
.insn_mo
= &dummy_opcode
;
2339 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2340 prev_nop_frag
= NULL
;
2341 prev_nop_frag_holds
= 0;
2342 prev_nop_frag_required
= 0;
2343 prev_nop_frag_since
= 0;
2345 prev_insn_valid
= 0;
2346 prev_insn_is_delay_slot
= 0;
2347 prev_insn_unreordered
= 0;
2348 prev_insn_extended
= 0;
2349 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2350 prev_prev_insn_unreordered
= 0;
2351 mips_clear_insn_labels ();
2354 /* This function must be called whenever we turn on noreorder or emit
2355 something other than instructions. It inserts any NOPS which might
2356 be needed by the previous instruction, and clears the information
2357 kept for the previous instructions. The INSNS parameter is true if
2358 instructions are to follow. */
2361 mips_emit_delays (insns
)
2364 if (! mips_opts
.noreorder
)
2369 if ((! mips_opts
.mips16
2370 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2371 && (! cop_interlocks
2372 && (prev_insn
.insn_mo
->pinfo
2373 & (INSN_LOAD_COPROC_DELAY
2374 | INSN_COPROC_MOVE_DELAY
2375 | INSN_WRITE_COND_CODE
))))
2376 || (! hilo_interlocks
2377 && (prev_insn
.insn_mo
->pinfo
2380 || (! mips_opts
.mips16
2382 && (prev_insn
.insn_mo
->pinfo
2383 & INSN_LOAD_MEMORY_DELAY
))
2384 || (! mips_opts
.mips16
2385 && mips_opts
.isa
== 1
2386 && (prev_insn
.insn_mo
->pinfo
2387 & INSN_COPROC_MEMORY_DELAY
)))
2389 /* Itbl support may require additional care here. */
2391 if ((! mips_opts
.mips16
2392 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2393 && (! cop_interlocks
2394 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2395 || (! hilo_interlocks
2396 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2397 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2400 if (prev_insn_unreordered
)
2403 else if ((! mips_opts
.mips16
2404 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2405 && (! cop_interlocks
2406 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2407 || (! hilo_interlocks
2408 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2409 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2411 /* Itbl support may require additional care here. */
2412 if (! prev_prev_insn_unreordered
)
2418 struct insn_label_list
*l
;
2422 /* Record the frag which holds the nop instructions, so
2423 that we can remove them if we don't need them. */
2424 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2425 prev_nop_frag
= frag_now
;
2426 prev_nop_frag_holds
= nops
;
2427 prev_nop_frag_required
= 0;
2428 prev_nop_frag_since
= 0;
2431 for (; nops
> 0; --nops
)
2436 /* Move on to a new frag, so that it is safe to simply
2437 decrease the size of prev_nop_frag. */
2438 frag_wane (frag_now
);
2442 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2444 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2445 symbol_set_frag (l
->label
, frag_now
);
2446 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2447 /* mips16 text labels are stored as odd. */
2448 if (mips_opts
.mips16
)
2449 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2454 /* Mark instruction labels in mips16 mode. */
2455 if (mips_opts
.mips16
&& insns
)
2456 mips16_mark_labels ();
2458 mips_no_prev_insn (insns
);
2461 /* Build an instruction created by a macro expansion. This is passed
2462 a pointer to the count of instructions created so far, an
2463 expression, the name of the instruction to build, an operand format
2464 string, and corresponding arguments. */
2468 macro_build (char *place
,
2476 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2485 struct mips_cl_insn insn
;
2486 bfd_reloc_code_real_type r
;
2490 va_start (args
, fmt
);
2496 * If the macro is about to expand into a second instruction,
2497 * print a warning if needed. We need to pass ip as a parameter
2498 * to generate a better warning message here...
2500 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2501 as_warn (_("Macro instruction expanded into multiple instructions"));
2504 *counter
+= 1; /* bump instruction counter */
2506 if (mips_opts
.mips16
)
2508 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2513 r
= BFD_RELOC_UNUSED
;
2514 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2515 assert (insn
.insn_mo
);
2516 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2518 /* Search until we get a match for NAME. */
2521 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2522 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2523 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2525 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2529 assert (insn
.insn_mo
->name
);
2530 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2533 insn
.insn_opcode
= insn
.insn_mo
->match
;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2555 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2560 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2565 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2572 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2576 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2580 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2584 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2591 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2597 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2598 assert (r
== BFD_RELOC_MIPS_GPREL
2599 || r
== BFD_RELOC_MIPS_LITERAL
2600 || r
== BFD_RELOC_LO16
2601 || r
== BFD_RELOC_MIPS_GOT16
2602 || r
== BFD_RELOC_MIPS_CALL16
2603 || r
== BFD_RELOC_MIPS_GOT_LO16
2604 || r
== BFD_RELOC_MIPS_CALL_LO16
2605 || (ep
->X_op
== O_subtract
2606 && r
== BFD_RELOC_PCREL_LO16
));
2610 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2612 && (ep
->X_op
== O_constant
2613 || (ep
->X_op
== O_symbol
2614 && (r
== BFD_RELOC_HI16_S
2615 || r
== BFD_RELOC_HI16
2616 || r
== BFD_RELOC_MIPS_GOT_HI16
2617 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2618 || (ep
->X_op
== O_subtract
2619 && r
== BFD_RELOC_PCREL_HI16_S
)));
2620 if (ep
->X_op
== O_constant
)
2622 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2624 r
= BFD_RELOC_UNUSED
;
2629 assert (ep
!= NULL
);
2631 * This allows macro() to pass an immediate expression for
2632 * creating short branches without creating a symbol.
2633 * Note that the expression still might come from the assembly
2634 * input, in which case the value is not checked for range nor
2635 * is a relocation entry generated (yuck).
2637 if (ep
->X_op
== O_constant
)
2639 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2643 r
= BFD_RELOC_16_PCREL_S2
;
2647 assert (ep
!= NULL
);
2648 r
= BFD_RELOC_MIPS_JMP
;
2652 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2661 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2663 append_insn (place
, &insn
, ep
, r
, false);
2667 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2669 int *counter ATTRIBUTE_UNUSED
;
2675 struct mips_cl_insn insn
;
2676 bfd_reloc_code_real_type r
;
2678 r
= BFD_RELOC_UNUSED
;
2679 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2680 assert (insn
.insn_mo
);
2681 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2683 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2684 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2687 assert (insn
.insn_mo
->name
);
2688 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2691 insn
.insn_opcode
= insn
.insn_mo
->match
;
2692 insn
.use_extend
= false;
2711 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2716 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2720 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2724 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2734 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2741 regno
= va_arg (args
, int);
2742 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2743 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2764 assert (ep
!= NULL
);
2766 if (ep
->X_op
!= O_constant
)
2767 r
= BFD_RELOC_UNUSED
+ c
;
2770 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2771 false, false, &insn
.insn_opcode
,
2772 &insn
.use_extend
, &insn
.extend
);
2774 r
= BFD_RELOC_UNUSED
;
2780 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2787 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2789 append_insn (place
, &insn
, ep
, r
, false);
2793 * Generate a "lui" instruction.
2796 macro_build_lui (place
, counter
, ep
, regnum
)
2802 expressionS high_expr
;
2803 struct mips_cl_insn insn
;
2804 bfd_reloc_code_real_type r
;
2805 CONST
char *name
= "lui";
2806 CONST
char *fmt
= "t,u";
2808 assert (! mips_opts
.mips16
);
2814 high_expr
.X_op
= O_constant
;
2815 high_expr
.X_add_number
= ep
->X_add_number
;
2818 if (high_expr
.X_op
== O_constant
)
2820 /* we can compute the instruction now without a relocation entry */
2821 if (high_expr
.X_add_number
& 0x8000)
2822 high_expr
.X_add_number
+= 0x10000;
2823 high_expr
.X_add_number
=
2824 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2825 r
= BFD_RELOC_UNUSED
;
2829 assert (ep
->X_op
== O_symbol
);
2830 /* _gp_disp is a special case, used from s_cpload. */
2831 assert (mips_pic
== NO_PIC
2832 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2833 r
= BFD_RELOC_HI16_S
;
2837 * If the macro is about to expand into a second instruction,
2838 * print a warning if needed. We need to pass ip as a parameter
2839 * to generate a better warning message here...
2841 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2842 as_warn (_("Macro instruction expanded into multiple instructions"));
2845 *counter
+= 1; /* bump instruction counter */
2847 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2848 assert (insn
.insn_mo
);
2849 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2850 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2852 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2853 if (r
== BFD_RELOC_UNUSED
)
2855 insn
.insn_opcode
|= high_expr
.X_add_number
;
2856 append_insn (place
, &insn
, NULL
, r
, false);
2859 append_insn (place
, &insn
, &high_expr
, r
, false);
2863 * Generates code to set the $at register to true (one)
2864 * if reg is less than the immediate expression.
2867 set_at (counter
, reg
, unsignedp
)
2872 if (imm_expr
.X_op
== O_constant
2873 && imm_expr
.X_add_number
>= -0x8000
2874 && imm_expr
.X_add_number
< 0x8000)
2875 macro_build ((char *) NULL
, counter
, &imm_expr
,
2876 unsignedp
? "sltiu" : "slti",
2877 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2880 load_register (counter
, AT
, &imm_expr
, 0);
2881 macro_build ((char *) NULL
, counter
, NULL
,
2882 unsignedp
? "sltu" : "slt",
2883 "d,v,t", AT
, reg
, AT
);
2887 /* Warn if an expression is not a constant. */
2890 check_absolute_expr (ip
, ex
)
2891 struct mips_cl_insn
*ip
;
2894 if (ex
->X_op
== O_big
)
2895 as_bad (_("unsupported large constant"));
2896 else if (ex
->X_op
!= O_constant
)
2897 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2900 /* Count the leading zeroes by performing a binary chop. This is a
2901 bulky bit of source, but performance is a LOT better for the
2902 majority of values than a simple loop to count the bits:
2903 for (lcnt = 0; (lcnt < 32); lcnt++)
2904 if ((v) & (1 << (31 - lcnt)))
2906 However it is not code size friendly, and the gain will drop a bit
2907 on certain cached systems.
2909 #define COUNT_TOP_ZEROES(v) \
2910 (((v) & ~0xffff) == 0 \
2911 ? ((v) & ~0xff) == 0 \
2912 ? ((v) & ~0xf) == 0 \
2913 ? ((v) & ~0x3) == 0 \
2914 ? ((v) & ~0x1) == 0 \
2919 : ((v) & ~0x7) == 0 \
2922 : ((v) & ~0x3f) == 0 \
2923 ? ((v) & ~0x1f) == 0 \
2926 : ((v) & ~0x7f) == 0 \
2929 : ((v) & ~0xfff) == 0 \
2930 ? ((v) & ~0x3ff) == 0 \
2931 ? ((v) & ~0x1ff) == 0 \
2934 : ((v) & ~0x7ff) == 0 \
2937 : ((v) & ~0x3fff) == 0 \
2938 ? ((v) & ~0x1fff) == 0 \
2941 : ((v) & ~0x7fff) == 0 \
2944 : ((v) & ~0xffffff) == 0 \
2945 ? ((v) & ~0xfffff) == 0 \
2946 ? ((v) & ~0x3ffff) == 0 \
2947 ? ((v) & ~0x1ffff) == 0 \
2950 : ((v) & ~0x7ffff) == 0 \
2953 : ((v) & ~0x3fffff) == 0 \
2954 ? ((v) & ~0x1fffff) == 0 \
2957 : ((v) & ~0x7fffff) == 0 \
2960 : ((v) & ~0xfffffff) == 0 \
2961 ? ((v) & ~0x3ffffff) == 0 \
2962 ? ((v) & ~0x1ffffff) == 0 \
2965 : ((v) & ~0x7ffffff) == 0 \
2968 : ((v) & ~0x3fffffff) == 0 \
2969 ? ((v) & ~0x1fffffff) == 0 \
2972 : ((v) & ~0x7fffffff) == 0 \
2977 * This routine generates the least number of instructions neccessary to load
2978 * an absolute expression value into a register.
2981 load_register (counter
, reg
, ep
, dbl
)
2988 expressionS hi32
, lo32
;
2990 if (ep
->X_op
!= O_big
)
2992 assert (ep
->X_op
== O_constant
);
2993 if (ep
->X_add_number
< 0x8000
2994 && (ep
->X_add_number
>= 0
2995 || (ep
->X_add_number
>= -0x8000
2998 || sizeof (ep
->X_add_number
) > 4))))
3000 /* We can handle 16 bit signed values with an addiu to
3001 $zero. No need to ever use daddiu here, since $zero and
3002 the result are always correct in 32 bit mode. */
3003 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3004 (int) BFD_RELOC_LO16
);
3007 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3009 /* We can handle 16 bit unsigned values with an ori to
3011 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3012 (int) BFD_RELOC_LO16
);
3015 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3016 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3017 == ~ (offsetT
) 0x7fffffff))
3020 || sizeof (ep
->X_add_number
) > 4
3021 || (ep
->X_add_number
& 0x80000000) == 0))
3022 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3023 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3024 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3026 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3027 == ~ (offsetT
) 0xffffffff)))
3029 /* 32 bit values require an lui. */
3030 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3031 (int) BFD_RELOC_HI16
);
3032 if ((ep
->X_add_number
& 0xffff) != 0)
3033 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3034 (int) BFD_RELOC_LO16
);
3039 /* The value is larger than 32 bits. */
3041 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3043 as_bad (_("Number larger than 32 bits"));
3044 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3045 (int) BFD_RELOC_LO16
);
3049 if (ep
->X_op
!= O_big
)
3052 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3053 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3054 hi32
.X_add_number
&= 0xffffffff;
3056 lo32
.X_add_number
&= 0xffffffff;
3060 assert (ep
->X_add_number
> 2);
3061 if (ep
->X_add_number
== 3)
3062 generic_bignum
[3] = 0;
3063 else if (ep
->X_add_number
> 4)
3064 as_bad (_("Number larger than 64 bits"));
3065 lo32
.X_op
= O_constant
;
3066 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3067 hi32
.X_op
= O_constant
;
3068 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3071 if (hi32
.X_add_number
== 0)
3076 unsigned long hi
, lo
;
3078 if (hi32
.X_add_number
== 0xffffffff)
3080 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3082 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3083 reg
, 0, (int) BFD_RELOC_LO16
);
3086 if (lo32
.X_add_number
& 0x80000000)
3088 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3089 (int) BFD_RELOC_HI16
);
3090 if (lo32
.X_add_number
& 0xffff)
3091 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3092 reg
, reg
, (int) BFD_RELOC_LO16
);
3097 /* Check for 16bit shifted constant. We know that hi32 is
3098 non-zero, so start the mask on the first bit of the hi32
3103 unsigned long himask
, lomask
;
3107 himask
= 0xffff >> (32 - shift
);
3108 lomask
= (0xffff << shift
) & 0xffffffff;
3112 himask
= 0xffff << (shift
- 32);
3115 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3116 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3120 tmp
.X_op
= O_constant
;
3122 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3123 | (lo32
.X_add_number
>> shift
));
3125 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3126 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3127 (int) BFD_RELOC_LO16
);
3128 macro_build ((char *) NULL
, counter
, NULL
,
3129 (shift
>= 32) ? "dsll32" : "dsll",
3131 (shift
>= 32) ? shift
- 32 : shift
);
3135 } while (shift
<= (64 - 16));
3137 /* Find the bit number of the lowest one bit, and store the
3138 shifted value in hi/lo. */
3139 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3140 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3144 while ((lo
& 1) == 0)
3149 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3155 while ((hi
& 1) == 0)
3164 /* Optimize if the shifted value is a (power of 2) - 1. */
3165 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3166 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3168 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3173 /* This instruction will set the register to be all
3175 tmp
.X_op
= O_constant
;
3176 tmp
.X_add_number
= (offsetT
) -1;
3177 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3178 reg
, 0, (int) BFD_RELOC_LO16
);
3182 macro_build ((char *) NULL
, counter
, NULL
,
3183 (bit
>= 32) ? "dsll32" : "dsll",
3185 (bit
>= 32) ? bit
- 32 : bit
);
3187 macro_build ((char *) NULL
, counter
, NULL
,
3188 (shift
>= 32) ? "dsrl32" : "dsrl",
3190 (shift
>= 32) ? shift
- 32 : shift
);
3195 /* Sign extend hi32 before calling load_register, because we can
3196 generally get better code when we load a sign extended value. */
3197 if ((hi32
.X_add_number
& 0x80000000) != 0)
3198 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3199 load_register (counter
, reg
, &hi32
, 0);
3202 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3206 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3215 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3217 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3218 (int) BFD_RELOC_HI16
);
3219 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3226 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3231 mid16
.X_add_number
>>= 16;
3232 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3233 freg
, (int) BFD_RELOC_LO16
);
3234 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3238 if ((lo32
.X_add_number
& 0xffff) != 0)
3239 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3240 (int) BFD_RELOC_LO16
);
3243 /* Load an address into a register. */
3246 load_address (counter
, reg
, ep
)
3253 if (ep
->X_op
!= O_constant
3254 && ep
->X_op
!= O_symbol
)
3256 as_bad (_("expression too complex"));
3257 ep
->X_op
= O_constant
;
3260 if (ep
->X_op
== O_constant
)
3262 load_register (counter
, reg
, ep
, 0);
3266 if (mips_pic
== NO_PIC
)
3268 /* If this is a reference to a GP relative symbol, we want
3269 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3271 lui $reg,<sym> (BFD_RELOC_HI16_S)
3272 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3273 If we have an addend, we always use the latter form. */
3274 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3275 || nopic_need_relax (ep
->X_add_symbol
, 1))
3280 macro_build ((char *) NULL
, counter
, ep
,
3281 ((bfd_arch_bits_per_address (stdoutput
) == 32
3282 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3283 ? "addiu" : "daddiu"),
3284 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3285 p
= frag_var (rs_machine_dependent
, 8, 0,
3286 RELAX_ENCODE (4, 8, 0, 4, 0,
3287 mips_opts
.warn_about_macros
),
3288 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3290 macro_build_lui (p
, counter
, ep
, reg
);
3293 macro_build (p
, counter
, ep
,
3294 ((bfd_arch_bits_per_address (stdoutput
) == 32
3295 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3296 ? "addiu" : "daddiu"),
3297 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3299 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3303 /* If this is a reference to an external symbol, we want
3304 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3306 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3308 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3309 If there is a constant, it must be added in after. */
3310 ex
.X_add_number
= ep
->X_add_number
;
3311 ep
->X_add_number
= 0;
3313 macro_build ((char *) NULL
, counter
, ep
,
3314 ((bfd_arch_bits_per_address (stdoutput
) == 32
3315 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3317 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3318 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3319 p
= frag_var (rs_machine_dependent
, 4, 0,
3320 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3321 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3322 macro_build (p
, counter
, ep
,
3323 ((bfd_arch_bits_per_address (stdoutput
) == 32
3324 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3325 ? "addiu" : "daddiu"),
3326 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3327 if (ex
.X_add_number
!= 0)
3329 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3330 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3331 ex
.X_op
= O_constant
;
3332 macro_build ((char *) NULL
, counter
, &ex
,
3333 ((bfd_arch_bits_per_address (stdoutput
) == 32
3334 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3335 ? "addiu" : "daddiu"),
3336 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3339 else if (mips_pic
== SVR4_PIC
)
3344 /* This is the large GOT case. If this is a reference to an
3345 external symbol, we want
3346 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3348 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3349 Otherwise, for a reference to a local symbol, we want
3350 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3352 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3353 If there is a constant, it must be added in after. */
3354 ex
.X_add_number
= ep
->X_add_number
;
3355 ep
->X_add_number
= 0;
3356 if (reg_needs_delay (GP
))
3361 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3362 (int) BFD_RELOC_MIPS_GOT_HI16
);
3363 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3364 ((bfd_arch_bits_per_address (stdoutput
) == 32
3365 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3366 ? "addu" : "daddu"),
3367 "d,v,t", reg
, reg
, GP
);
3368 macro_build ((char *) NULL
, counter
, ep
,
3369 ((bfd_arch_bits_per_address (stdoutput
) == 32
3370 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3372 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3373 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3374 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3375 mips_opts
.warn_about_macros
),
3376 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3379 /* We need a nop before loading from $gp. This special
3380 check is required because the lui which starts the main
3381 instruction stream does not refer to $gp, and so will not
3382 insert the nop which may be required. */
3383 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3386 macro_build (p
, counter
, ep
,
3387 ((bfd_arch_bits_per_address (stdoutput
) == 32
3388 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3390 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3392 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3394 macro_build (p
, counter
, ep
,
3395 ((bfd_arch_bits_per_address (stdoutput
) == 32
3396 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3397 ? "addiu" : "daddiu"),
3398 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3399 if (ex
.X_add_number
!= 0)
3401 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3402 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3403 ex
.X_op
= O_constant
;
3404 macro_build ((char *) NULL
, counter
, &ex
,
3405 ((bfd_arch_bits_per_address (stdoutput
) == 32
3406 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3407 ? "addiu" : "daddiu"),
3408 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3411 else if (mips_pic
== EMBEDDED_PIC
)
3414 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3416 macro_build ((char *) NULL
, counter
, ep
,
3417 ((bfd_arch_bits_per_address (stdoutput
) == 32
3418 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3419 ? "addiu" : "daddiu"),
3420 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3428 * This routine implements the seemingly endless macro or synthesized
3429 * instructions and addressing modes in the mips assembly language. Many
3430 * of these macros are simple and are similar to each other. These could
3431 * probably be handled by some kind of table or grammer aproach instead of
3432 * this verbose method. Others are not simple macros but are more like
3433 * optimizing code generation.
3434 * One interesting optimization is when several store macros appear
3435 * consecutivly that would load AT with the upper half of the same address.
3436 * The ensuing load upper instructions are ommited. This implies some kind
3437 * of global optimization. We currently only optimize within a single macro.
3438 * For many of the load and store macros if the address is specified as a
3439 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3440 * first load register 'at' with zero and use it as the base register. The
3441 * mips assembler simply uses register $zero. Just one tiny optimization
3446 struct mips_cl_insn
*ip
;
3448 register int treg
, sreg
, dreg
, breg
;
3464 bfd_reloc_code_real_type r
;
3466 int hold_mips_optimize
;
3468 assert (! mips_opts
.mips16
);
3470 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3471 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3472 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3473 mask
= ip
->insn_mo
->mask
;
3475 expr1
.X_op
= O_constant
;
3476 expr1
.X_op_symbol
= NULL
;
3477 expr1
.X_add_symbol
= NULL
;
3478 expr1
.X_add_number
= 1;
3490 mips_emit_delays (true);
3491 ++mips_opts
.noreorder
;
3492 mips_any_noreorder
= 1;
3494 expr1
.X_add_number
= 8;
3495 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3497 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3499 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3500 macro_build ((char *) NULL
, &icnt
, NULL
,
3501 dbl
? "dsub" : "sub",
3502 "d,v,t", dreg
, 0, sreg
);
3504 --mips_opts
.noreorder
;
3525 if (imm_expr
.X_op
== O_constant
3526 && imm_expr
.X_add_number
>= -0x8000
3527 && imm_expr
.X_add_number
< 0x8000)
3529 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3530 (int) BFD_RELOC_LO16
);
3533 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3534 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3553 if (imm_expr
.X_op
== O_constant
3554 && imm_expr
.X_add_number
>= 0
3555 && imm_expr
.X_add_number
< 0x10000)
3557 if (mask
!= M_NOR_I
)
3558 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3559 sreg
, (int) BFD_RELOC_LO16
);
3562 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3563 treg
, sreg
, (int) BFD_RELOC_LO16
);
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3570 load_register (&icnt
, AT
, &imm_expr
, 0);
3571 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3588 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3594 load_register (&icnt
, AT
, &imm_expr
, 0);
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3603 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3604 likely
? "bgezl" : "bgez",
3610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3611 likely
? "blezl" : "blez",
3615 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3616 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3617 likely
? "beql" : "beq",
3624 /* check for > max integer */
3625 maxnum
= 0x7fffffff;
3626 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3633 if (imm_expr
.X_op
== O_constant
3634 && imm_expr
.X_add_number
>= maxnum
3635 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3638 /* result is always false */
3641 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3646 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3652 if (imm_expr
.X_op
!= O_constant
)
3653 as_bad (_("Unsupported large constant"));
3654 imm_expr
.X_add_number
++;
3658 if (mask
== M_BGEL_I
)
3660 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3662 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3663 likely
? "bgezl" : "bgez",
3667 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3669 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3670 likely
? "bgtzl" : "bgtz",
3674 maxnum
= 0x7fffffff;
3675 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3682 maxnum
= - maxnum
- 1;
3683 if (imm_expr
.X_op
== O_constant
3684 && imm_expr
.X_add_number
<= maxnum
3685 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3688 /* result is always true */
3689 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3690 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3693 set_at (&icnt
, sreg
, 0);
3694 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3695 likely
? "beql" : "beq",
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3707 likely
? "beql" : "beq",
3711 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3713 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3714 likely
? "beql" : "beq",
3722 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3723 && imm_expr
.X_op
== O_constant
3724 && imm_expr
.X_add_number
== 0xffffffff))
3726 if (imm_expr
.X_op
!= O_constant
)
3727 as_bad (_("Unsupported large constant"));
3728 imm_expr
.X_add_number
++;
3732 if (mask
== M_BGEUL_I
)
3734 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3736 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3739 likely
? "bnel" : "bne",
3743 set_at (&icnt
, sreg
, 1);
3744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3745 likely
? "beql" : "beq",
3754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3755 likely
? "bgtzl" : "bgtz",
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3762 likely
? "bltzl" : "bltz",
3766 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3767 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3768 likely
? "bnel" : "bne",
3777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3778 likely
? "bnel" : "bne",
3784 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3787 likely
? "bnel" : "bne",
3796 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3797 likely
? "blezl" : "blez",
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 likely
? "bgezl" : "bgez",
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3809 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3810 likely
? "beql" : "beq",
3817 maxnum
= 0x7fffffff;
3818 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3825 if (imm_expr
.X_op
== O_constant
3826 && imm_expr
.X_add_number
>= maxnum
3827 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3829 if (imm_expr
.X_op
!= O_constant
)
3830 as_bad (_("Unsupported large constant"));
3831 imm_expr
.X_add_number
++;
3835 if (mask
== M_BLTL_I
)
3837 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 likely
? "bltzl" : "bltz",
3844 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3847 likely
? "blezl" : "blez",
3851 set_at (&icnt
, sreg
, 0);
3852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3853 likely
? "bnel" : "bne",
3862 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3863 likely
? "beql" : "beq",
3869 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3871 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3872 likely
? "beql" : "beq",
3880 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3881 && imm_expr
.X_op
== O_constant
3882 && imm_expr
.X_add_number
== 0xffffffff))
3884 if (imm_expr
.X_op
!= O_constant
)
3885 as_bad (_("Unsupported large constant"));
3886 imm_expr
.X_add_number
++;
3890 if (mask
== M_BLTUL_I
)
3892 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3894 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "beql" : "beq",
3901 set_at (&icnt
, sreg
, 1);
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "bnel" : "bne",
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3913 likely
? "bltzl" : "bltz",
3919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3920 likely
? "bgtzl" : "bgtz",
3924 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3926 likely
? "bnel" : "bne",
3937 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3938 likely
? "bnel" : "bne",
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3944 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3945 likely
? "bnel" : "bne",
3961 as_warn (_("Divide by zero."));
3963 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3965 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3969 mips_emit_delays (true);
3970 ++mips_opts
.noreorder
;
3971 mips_any_noreorder
= 1;
3974 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3975 macro_build ((char *) NULL
, &icnt
, NULL
,
3976 dbl
? "ddiv" : "div",
3977 "z,s,t", sreg
, treg
);
3981 expr1
.X_add_number
= 8;
3982 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3983 macro_build ((char *) NULL
, &icnt
, NULL
,
3984 dbl
? "ddiv" : "div",
3985 "z,s,t", sreg
, treg
);
3986 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3988 expr1
.X_add_number
= -1;
3989 macro_build ((char *) NULL
, &icnt
, &expr1
,
3990 dbl
? "daddiu" : "addiu",
3991 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3992 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3993 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3996 expr1
.X_add_number
= 1;
3997 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3998 (int) BFD_RELOC_LO16
);
3999 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4004 expr1
.X_add_number
= 0x80000000;
4005 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4006 (int) BFD_RELOC_HI16
);
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4011 /* We want to close the noreorder block as soon as possible, so
4012 that later insns are available for delay slot filling. */
4013 --mips_opts
.noreorder
;
4017 expr1
.X_add_number
= 8;
4018 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4019 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4021 /* We want to close the noreorder block as soon as possible, so
4022 that later insns are available for delay slot filling. */
4023 --mips_opts
.noreorder
;
4025 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4027 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4066 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4068 as_warn (_("Divide by zero."));
4070 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4072 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4075 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4077 if (strcmp (s2
, "mflo") == 0)
4078 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4081 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4084 if (imm_expr
.X_op
== O_constant
4085 && imm_expr
.X_add_number
== -1
4086 && s
[strlen (s
) - 1] != 'u')
4088 if (strcmp (s2
, "mflo") == 0)
4091 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4094 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4098 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4102 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4104 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4123 mips_emit_delays (true);
4124 ++mips_opts
.noreorder
;
4125 mips_any_noreorder
= 1;
4128 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4129 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4130 /* We want to close the noreorder block as soon as possible, so
4131 that later insns are available for delay slot filling. */
4132 --mips_opts
.noreorder
;
4136 expr1
.X_add_number
= 8;
4137 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4138 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4140 /* We want to close the noreorder block as soon as possible, so
4141 that later insns are available for delay slot filling. */
4142 --mips_opts
.noreorder
;
4143 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4145 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4151 /* Load the address of a symbol into a register. If breg is not
4152 zero, we then add a base register to it. */
4154 /* When generating embedded PIC code, we permit expressions of
4157 where bar is an address in the current section. These are used
4158 when getting the addresses of functions. We don't permit
4159 X_add_number to be non-zero, because if the symbol is
4160 external the relaxing code needs to know that any addend is
4161 purely the offset to X_op_symbol. */
4162 if (mips_pic
== EMBEDDED_PIC
4163 && offset_expr
.X_op
== O_subtract
4164 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4165 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4166 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4168 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4172 && (offset_expr
.X_add_number
== 0
4173 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4175 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4176 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4178 ((bfd_arch_bits_per_address (stdoutput
) == 32
4179 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4180 ? "addiu" : "daddiu"),
4181 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4185 if (offset_expr
.X_op
!= O_symbol
4186 && offset_expr
.X_op
!= O_constant
)
4188 as_bad (_("expression too complex"));
4189 offset_expr
.X_op
= O_constant
;
4203 if (offset_expr
.X_op
== O_constant
)
4204 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4205 else if (mips_pic
== NO_PIC
)
4207 /* If this is a reference to an GP relative symbol, we want
4208 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4210 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4211 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4212 If we have a constant, we need two instructions anyhow,
4213 so we may as well always use the latter form. */
4214 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4215 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4220 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4221 ((bfd_arch_bits_per_address (stdoutput
) == 32
4222 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4223 ? "addiu" : "daddiu"),
4224 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4225 p
= frag_var (rs_machine_dependent
, 8, 0,
4226 RELAX_ENCODE (4, 8, 0, 4, 0,
4227 mips_opts
.warn_about_macros
),
4228 offset_expr
.X_add_symbol
, (offsetT
) 0,
4231 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4234 macro_build (p
, &icnt
, &offset_expr
,
4235 ((bfd_arch_bits_per_address (stdoutput
) == 32
4236 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4237 ? "addiu" : "daddiu"),
4238 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4240 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4242 /* If this is a reference to an external symbol, and there
4243 is no constant, we want
4244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4245 For a local symbol, we want
4246 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4248 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4250 If we have a small constant, and this is a reference to
4251 an external symbol, we want
4252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4254 addiu $tempreg,$tempreg,<constant>
4255 For a local symbol, we want the same instruction
4256 sequence, but we output a BFD_RELOC_LO16 reloc on the
4259 If we have a large constant, and this is a reference to
4260 an external symbol, we want
4261 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4262 lui $at,<hiconstant>
4263 addiu $at,$at,<loconstant>
4264 addu $tempreg,$tempreg,$at
4265 For a local symbol, we want the same instruction
4266 sequence, but we output a BFD_RELOC_LO16 reloc on the
4267 addiu instruction. */
4268 expr1
.X_add_number
= offset_expr
.X_add_number
;
4269 offset_expr
.X_add_number
= 0;
4271 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4273 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4274 if (expr1
.X_add_number
== 0)
4282 /* We're going to put in an addu instruction using
4283 tempreg, so we may as well insert the nop right
4285 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4289 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4290 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4292 ? mips_opts
.warn_about_macros
4294 offset_expr
.X_add_symbol
, (offsetT
) 0,
4298 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4301 macro_build (p
, &icnt
, &expr1
,
4302 ((bfd_arch_bits_per_address (stdoutput
) == 32
4303 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4304 ? "addiu" : "daddiu"),
4305 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4306 /* FIXME: If breg == 0, and the next instruction uses
4307 $tempreg, then if this variant case is used an extra
4308 nop will be generated. */
4310 else if (expr1
.X_add_number
>= -0x8000
4311 && expr1
.X_add_number
< 0x8000)
4313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4315 macro_build ((char *) NULL
, &icnt
, &expr1
,
4316 ((bfd_arch_bits_per_address (stdoutput
) == 32
4317 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4318 ? "addiu" : "daddiu"),
4319 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4320 (void) frag_var (rs_machine_dependent
, 0, 0,
4321 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4322 offset_expr
.X_add_symbol
, (offsetT
) 0,
4329 /* If we are going to add in a base register, and the
4330 target register and the base register are the same,
4331 then we are using AT as a temporary register. Since
4332 we want to load the constant into AT, we add our
4333 current AT (from the global offset table) and the
4334 register into the register now, and pretend we were
4335 not using a base register. */
4340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4343 ((bfd_arch_bits_per_address (stdoutput
) == 32
4344 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4345 ? "addu" : "daddu"),
4346 "d,v,t", treg
, AT
, breg
);
4352 /* Set mips_optimize around the lui instruction to avoid
4353 inserting an unnecessary nop after the lw. */
4354 hold_mips_optimize
= mips_optimize
;
4356 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4357 mips_optimize
= hold_mips_optimize
;
4359 macro_build ((char *) NULL
, &icnt
, &expr1
,
4360 ((bfd_arch_bits_per_address (stdoutput
) == 32
4361 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4362 ? "addiu" : "daddiu"),
4363 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4365 ((bfd_arch_bits_per_address (stdoutput
) == 32
4366 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4367 ? "addu" : "daddu"),
4368 "d,v,t", tempreg
, tempreg
, AT
);
4369 (void) frag_var (rs_machine_dependent
, 0, 0,
4370 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4371 offset_expr
.X_add_symbol
, (offsetT
) 0,
4376 else if (mips_pic
== SVR4_PIC
)
4380 /* This is the large GOT case. If this is a reference to an
4381 external symbol, and there is no constant, we want
4382 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4383 addu $tempreg,$tempreg,$gp
4384 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4385 For a local symbol, we want
4386 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4388 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4390 If we have a small constant, and this is a reference to
4391 an external symbol, we want
4392 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4393 addu $tempreg,$tempreg,$gp
4394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4396 addiu $tempreg,$tempreg,<constant>
4397 For a local symbol, we want
4398 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4400 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4402 If we have a large constant, and this is a reference to
4403 an external symbol, we want
4404 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4405 addu $tempreg,$tempreg,$gp
4406 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4407 lui $at,<hiconstant>
4408 addiu $at,$at,<loconstant>
4409 addu $tempreg,$tempreg,$at
4410 For a local symbol, we want
4411 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4412 lui $at,<hiconstant>
4413 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4414 addu $tempreg,$tempreg,$at
4416 expr1
.X_add_number
= offset_expr
.X_add_number
;
4417 offset_expr
.X_add_number
= 0;
4419 if (reg_needs_delay (GP
))
4423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4424 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4426 ((bfd_arch_bits_per_address (stdoutput
) == 32
4427 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4428 ? "addu" : "daddu"),
4429 "d,v,t", tempreg
, tempreg
, GP
);
4430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4432 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4434 if (expr1
.X_add_number
== 0)
4442 /* We're going to put in an addu instruction using
4443 tempreg, so we may as well insert the nop right
4445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4450 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4451 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4454 ? mips_opts
.warn_about_macros
4456 offset_expr
.X_add_symbol
, (offsetT
) 0,
4459 else if (expr1
.X_add_number
>= -0x8000
4460 && expr1
.X_add_number
< 0x8000)
4462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4464 macro_build ((char *) NULL
, &icnt
, &expr1
,
4465 ((bfd_arch_bits_per_address (stdoutput
) == 32
4466 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4467 ? "addiu" : "daddiu"),
4468 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4470 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4471 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4473 ? mips_opts
.warn_about_macros
4475 offset_expr
.X_add_symbol
, (offsetT
) 0,
4482 /* If we are going to add in a base register, and the
4483 target register and the base register are the same,
4484 then we are using AT as a temporary register. Since
4485 we want to load the constant into AT, we add our
4486 current AT (from the global offset table) and the
4487 register into the register now, and pretend we were
4488 not using a base register. */
4496 assert (tempreg
== AT
);
4497 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4499 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4500 ((bfd_arch_bits_per_address (stdoutput
) == 32
4501 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4502 ? "addu" : "daddu"),
4503 "d,v,t", treg
, AT
, breg
);
4508 /* Set mips_optimize around the lui instruction to avoid
4509 inserting an unnecessary nop after the lw. */
4510 hold_mips_optimize
= mips_optimize
;
4512 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4513 mips_optimize
= hold_mips_optimize
;
4515 macro_build ((char *) NULL
, &icnt
, &expr1
,
4516 ((bfd_arch_bits_per_address (stdoutput
) == 32
4517 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4518 ? "addiu" : "daddiu"),
4519 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4521 ((bfd_arch_bits_per_address (stdoutput
) == 32
4522 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4523 ? "addu" : "daddu"),
4524 "d,v,t", dreg
, dreg
, AT
);
4526 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4527 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4530 ? mips_opts
.warn_about_macros
4532 offset_expr
.X_add_symbol
, (offsetT
) 0,
4540 /* This is needed because this instruction uses $gp, but
4541 the first instruction on the main stream does not. */
4542 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4545 macro_build (p
, &icnt
, &offset_expr
,
4547 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4549 if (expr1
.X_add_number
>= -0x8000
4550 && expr1
.X_add_number
< 0x8000)
4552 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4554 macro_build (p
, &icnt
, &expr1
,
4555 ((bfd_arch_bits_per_address (stdoutput
) == 32
4556 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4557 ? "addiu" : "daddiu"),
4558 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4559 /* FIXME: If add_number is 0, and there was no base
4560 register, the external symbol case ended with a load,
4561 so if the symbol turns out to not be external, and
4562 the next instruction uses tempreg, an unnecessary nop
4563 will be inserted. */
4569 /* We must add in the base register now, as in the
4570 external symbol case. */
4571 assert (tempreg
== AT
);
4572 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4574 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4575 ((bfd_arch_bits_per_address (stdoutput
) == 32
4576 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4577 ? "addu" : "daddu"),
4578 "d,v,t", treg
, AT
, breg
);
4581 /* We set breg to 0 because we have arranged to add
4582 it in in both cases. */
4586 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4588 macro_build (p
, &icnt
, &expr1
,
4589 ((bfd_arch_bits_per_address (stdoutput
) == 32
4590 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4591 ? "addiu" : "daddiu"),
4592 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4594 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4595 ((bfd_arch_bits_per_address (stdoutput
) == 32
4596 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4597 ? "addu" : "daddu"),
4598 "d,v,t", tempreg
, tempreg
, AT
);
4602 else if (mips_pic
== EMBEDDED_PIC
)
4605 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4607 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4608 ((bfd_arch_bits_per_address (stdoutput
) == 32
4609 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4610 ? "addiu" : "daddiu"),
4611 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4618 ((bfd_arch_bits_per_address (stdoutput
) == 32
4619 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4620 ? "addu" : "daddu"),
4621 "d,v,t", treg
, tempreg
, breg
);
4629 /* The j instruction may not be used in PIC code, since it
4630 requires an absolute address. We convert it to a b
4632 if (mips_pic
== NO_PIC
)
4633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4635 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4638 /* The jal instructions must be handled as macros because when
4639 generating PIC code they expand to multi-instruction
4640 sequences. Normally they are simple instructions. */
4645 if (mips_pic
== NO_PIC
4646 || mips_pic
== EMBEDDED_PIC
)
4647 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4649 else if (mips_pic
== SVR4_PIC
)
4651 if (sreg
!= PIC_CALL_REG
)
4652 as_warn (_("MIPS PIC call to register other than $25"));
4654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4656 if (mips_cprestore_offset
< 0)
4657 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4660 expr1
.X_add_number
= mips_cprestore_offset
;
4661 macro_build ((char *) NULL
, &icnt
, &expr1
,
4662 ((bfd_arch_bits_per_address (stdoutput
) == 32
4663 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4665 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4674 if (mips_pic
== NO_PIC
)
4675 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4676 else if (mips_pic
== SVR4_PIC
)
4678 /* If this is a reference to an external symbol, and we are
4679 using a small GOT, we want
4680 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4684 lw $gp,cprestore($sp)
4685 The cprestore value is set using the .cprestore
4686 pseudo-op. If we are using a big GOT, we want
4687 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4689 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4693 lw $gp,cprestore($sp)
4694 If the symbol is not external, we want
4695 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4697 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4700 lw $gp,cprestore($sp) */
4704 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4705 ((bfd_arch_bits_per_address (stdoutput
) == 32
4706 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4708 "t,o(b)", PIC_CALL_REG
,
4709 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4712 p
= frag_var (rs_machine_dependent
, 4, 0,
4713 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4714 offset_expr
.X_add_symbol
, (offsetT
) 0,
4721 if (reg_needs_delay (GP
))
4725 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4726 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4728 ((bfd_arch_bits_per_address (stdoutput
) == 32
4729 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4730 ? "addu" : "daddu"),
4731 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4733 ((bfd_arch_bits_per_address (stdoutput
) == 32
4734 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4736 "t,o(b)", PIC_CALL_REG
,
4737 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4738 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4740 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4741 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4743 offset_expr
.X_add_symbol
, (offsetT
) 0,
4747 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4750 macro_build (p
, &icnt
, &offset_expr
,
4751 ((bfd_arch_bits_per_address (stdoutput
) == 32
4752 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4754 "t,o(b)", PIC_CALL_REG
,
4755 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4757 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4760 macro_build (p
, &icnt
, &offset_expr
,
4761 ((bfd_arch_bits_per_address (stdoutput
) == 32
4762 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4763 ? "addiu" : "daddiu"),
4764 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4765 (int) BFD_RELOC_LO16
);
4766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4767 "jalr", "s", PIC_CALL_REG
);
4768 if (mips_cprestore_offset
< 0)
4769 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4772 if (mips_opts
.noreorder
)
4773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4775 expr1
.X_add_number
= mips_cprestore_offset
;
4776 macro_build ((char *) NULL
, &icnt
, &expr1
,
4777 ((bfd_arch_bits_per_address (stdoutput
) == 32
4778 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4780 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4784 else if (mips_pic
== EMBEDDED_PIC
)
4786 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4787 /* The linker may expand the call to a longer sequence which
4788 uses $at, so we must break rather than return. */
4813 /* Itbl support may require additional care here. */
4818 /* Itbl support may require additional care here. */
4823 /* Itbl support may require additional care here. */
4828 /* Itbl support may require additional care here. */
4840 if (mips_cpu
== 4650)
4842 as_bad (_("opcode not supported on this processor"));
4846 /* Itbl support may require additional care here. */
4851 /* Itbl support may require additional care here. */
4856 /* Itbl support may require additional care here. */
4876 if (breg
== treg
|| coproc
|| lr
)
4898 /* Itbl support may require additional care here. */
4903 /* Itbl support may require additional care here. */
4908 /* Itbl support may require additional care here. */
4913 /* Itbl support may require additional care here. */
4929 if (mips_cpu
== 4650)
4931 as_bad (_("opcode not supported on this processor"));
4936 /* Itbl support may require additional care here. */
4940 /* Itbl support may require additional care here. */
4945 /* Itbl support may require additional care here. */
4957 /* Itbl support may require additional care here. */
4958 if (mask
== M_LWC1_AB
4959 || mask
== M_SWC1_AB
4960 || mask
== M_LDC1_AB
4961 || mask
== M_SDC1_AB
4970 if (offset_expr
.X_op
!= O_constant
4971 && offset_expr
.X_op
!= O_symbol
)
4973 as_bad (_("expression too complex"));
4974 offset_expr
.X_op
= O_constant
;
4977 /* A constant expression in PIC code can be handled just as it
4978 is in non PIC code. */
4979 if (mips_pic
== NO_PIC
4980 || offset_expr
.X_op
== O_constant
)
4982 /* If this is a reference to a GP relative symbol, and there
4983 is no base register, we want
4984 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4985 Otherwise, if there is no base register, we want
4986 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4987 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4988 If we have a constant, we need two instructions anyhow,
4989 so we always use the latter form.
4991 If we have a base register, and this is a reference to a
4992 GP relative symbol, we want
4993 addu $tempreg,$breg,$gp
4994 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4996 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4997 addu $tempreg,$tempreg,$breg
4998 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4999 With a constant we always use the latter case. */
5002 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5003 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5009 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5010 p
= frag_var (rs_machine_dependent
, 8, 0,
5011 RELAX_ENCODE (4, 8, 0, 4, 0,
5012 (mips_opts
.warn_about_macros
5014 && mips_opts
.noat
))),
5015 offset_expr
.X_add_symbol
, (offsetT
) 0,
5019 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5022 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5023 (int) BFD_RELOC_LO16
, tempreg
);
5027 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5028 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5034 ((bfd_arch_bits_per_address (stdoutput
) == 32
5035 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5036 ? "addu" : "daddu"),
5037 "d,v,t", tempreg
, breg
, GP
);
5038 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5039 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5040 p
= frag_var (rs_machine_dependent
, 12, 0,
5041 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5042 offset_expr
.X_add_symbol
, (offsetT
) 0,
5045 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5048 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5049 ((bfd_arch_bits_per_address (stdoutput
) == 32
5050 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5051 ? "addu" : "daddu"),
5052 "d,v,t", tempreg
, tempreg
, breg
);
5055 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5056 (int) BFD_RELOC_LO16
, tempreg
);
5059 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5061 /* If this is a reference to an external symbol, we want
5062 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5064 <op> $treg,0($tempreg)
5066 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5068 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5069 <op> $treg,0($tempreg)
5070 If there is a base register, we add it to $tempreg before
5071 the <op>. If there is a constant, we stick it in the
5072 <op> instruction. We don't handle constants larger than
5073 16 bits, because we have no way to load the upper 16 bits
5074 (actually, we could handle them for the subset of cases
5075 in which we are not using $at). */
5076 assert (offset_expr
.X_op
== O_symbol
);
5077 expr1
.X_add_number
= offset_expr
.X_add_number
;
5078 offset_expr
.X_add_number
= 0;
5079 if (expr1
.X_add_number
< -0x8000
5080 || expr1
.X_add_number
>= 0x8000)
5081 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5083 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5084 ((bfd_arch_bits_per_address (stdoutput
) == 32
5085 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5087 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5088 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5089 p
= frag_var (rs_machine_dependent
, 4, 0,
5090 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5091 offset_expr
.X_add_symbol
, (offsetT
) 0,
5093 macro_build (p
, &icnt
, &offset_expr
,
5094 ((bfd_arch_bits_per_address (stdoutput
) == 32
5095 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5096 ? "addiu" : "daddiu"),
5097 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5099 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5100 ((bfd_arch_bits_per_address (stdoutput
) == 32
5101 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5102 ? "addu" : "daddu"),
5103 "d,v,t", tempreg
, tempreg
, breg
);
5104 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5105 (int) BFD_RELOC_LO16
, tempreg
);
5107 else if (mips_pic
== SVR4_PIC
)
5111 /* If this is a reference to an external symbol, we want
5112 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5113 addu $tempreg,$tempreg,$gp
5114 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5115 <op> $treg,0($tempreg)
5117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5119 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5120 <op> $treg,0($tempreg)
5121 If there is a base register, we add it to $tempreg before
5122 the <op>. If there is a constant, we stick it in the
5123 <op> instruction. We don't handle constants larger than
5124 16 bits, because we have no way to load the upper 16 bits
5125 (actually, we could handle them for the subset of cases
5126 in which we are not using $at). */
5127 assert (offset_expr
.X_op
== O_symbol
);
5128 expr1
.X_add_number
= offset_expr
.X_add_number
;
5129 offset_expr
.X_add_number
= 0;
5130 if (expr1
.X_add_number
< -0x8000
5131 || expr1
.X_add_number
>= 0x8000)
5132 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5133 if (reg_needs_delay (GP
))
5138 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5139 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5140 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5141 ((bfd_arch_bits_per_address (stdoutput
) == 32
5142 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5143 ? "addu" : "daddu"),
5144 "d,v,t", tempreg
, tempreg
, GP
);
5145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5146 ((bfd_arch_bits_per_address (stdoutput
) == 32
5147 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5149 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5151 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5152 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5153 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5156 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5159 macro_build (p
, &icnt
, &offset_expr
,
5160 ((bfd_arch_bits_per_address (stdoutput
) == 32
5161 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5163 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5165 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5167 macro_build (p
, &icnt
, &offset_expr
,
5168 ((bfd_arch_bits_per_address (stdoutput
) == 32
5169 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5170 ? "addiu" : "daddiu"),
5171 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5174 ((bfd_arch_bits_per_address (stdoutput
) == 32
5175 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5176 ? "addu" : "daddu"),
5177 "d,v,t", tempreg
, tempreg
, breg
);
5178 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5179 (int) BFD_RELOC_LO16
, tempreg
);
5181 else if (mips_pic
== EMBEDDED_PIC
)
5183 /* If there is no base register, we want
5184 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5185 If there is a base register, we want
5186 addu $tempreg,$breg,$gp
5187 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5189 assert (offset_expr
.X_op
== O_symbol
);
5192 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5193 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5198 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5199 ((bfd_arch_bits_per_address (stdoutput
) == 32
5200 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5201 ? "addu" : "daddu"),
5202 "d,v,t", tempreg
, breg
, GP
);
5203 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5204 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5217 load_register (&icnt
, treg
, &imm_expr
, 0);
5221 load_register (&icnt
, treg
, &imm_expr
, 1);
5225 if (imm_expr
.X_op
== O_constant
)
5227 load_register (&icnt
, AT
, &imm_expr
, 0);
5228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5229 "mtc1", "t,G", AT
, treg
);
5234 assert (offset_expr
.X_op
== O_symbol
5235 && strcmp (segment_name (S_GET_SEGMENT
5236 (offset_expr
.X_add_symbol
)),
5238 && offset_expr
.X_add_number
== 0);
5239 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5240 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5245 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5246 the entire value, and in mips1 mode it is the high order 32
5247 bits of the value and the low order 32 bits are either zero
5248 or in offset_expr. */
5249 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5251 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5252 load_register (&icnt
, treg
, &imm_expr
, 1);
5257 if (target_big_endian
)
5269 load_register (&icnt
, hreg
, &imm_expr
, 0);
5272 if (offset_expr
.X_op
== O_absent
)
5273 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5277 assert (offset_expr
.X_op
== O_constant
);
5278 load_register (&icnt
, lreg
, &offset_expr
, 0);
5285 /* We know that sym is in the .rdata section. First we get the
5286 upper 16 bits of the address. */
5287 if (mips_pic
== NO_PIC
)
5289 /* FIXME: This won't work for a 64 bit address. */
5290 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5292 else if (mips_pic
== SVR4_PIC
)
5294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5295 ((bfd_arch_bits_per_address (stdoutput
) == 32
5296 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5298 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5300 else if (mips_pic
== EMBEDDED_PIC
)
5302 /* For embedded PIC we pick up the entire address off $gp in
5303 a single instruction. */
5304 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5305 ((bfd_arch_bits_per_address (stdoutput
) == 32
5306 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5307 ? "addiu" : "daddiu"),
5308 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5309 offset_expr
.X_op
= O_constant
;
5310 offset_expr
.X_add_number
= 0;
5315 /* Now we load the register(s). */
5316 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5317 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5318 treg
, (int) BFD_RELOC_LO16
, AT
);
5321 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5322 treg
, (int) BFD_RELOC_LO16
, AT
);
5325 /* FIXME: How in the world do we deal with the possible
5327 offset_expr
.X_add_number
+= 4;
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5329 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5333 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5334 does not become a variant frag. */
5335 frag_wane (frag_now
);
5341 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5342 the entire value, and in mips1 mode it is the high order 32
5343 bits of the value and the low order 32 bits are either zero
5344 or in offset_expr. */
5345 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5347 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5348 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5350 "dmtc1", "t,S", AT
, treg
);
5353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5354 "mtc1", "t,G", AT
, treg
+ 1);
5355 if (offset_expr
.X_op
== O_absent
)
5356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5357 "mtc1", "t,G", 0, treg
);
5360 assert (offset_expr
.X_op
== O_constant
);
5361 load_register (&icnt
, AT
, &offset_expr
, 0);
5362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5363 "mtc1", "t,G", AT
, treg
);
5369 assert (offset_expr
.X_op
== O_symbol
5370 && offset_expr
.X_add_number
== 0);
5371 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5372 if (strcmp (s
, ".lit8") == 0)
5374 if (mips_opts
.isa
!= 1)
5376 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5377 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5381 r
= BFD_RELOC_MIPS_LITERAL
;
5386 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5387 if (mips_pic
== SVR4_PIC
)
5388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5389 ((bfd_arch_bits_per_address (stdoutput
) == 32
5390 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5392 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5395 /* FIXME: This won't work for a 64 bit address. */
5396 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5399 if (mips_opts
.isa
!= 1)
5401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5402 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5404 /* To avoid confusion in tc_gen_reloc, we must ensure
5405 that this does not become a variant frag. */
5406 frag_wane (frag_now
);
5417 if (mips_cpu
== 4650)
5419 as_bad (_("opcode not supported on this processor"));
5422 /* Even on a big endian machine $fn comes before $fn+1. We have
5423 to adjust when loading from memory. */
5426 assert (mips_opts
.isa
== 1);
5427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5428 target_big_endian
? treg
+ 1 : treg
,
5430 /* FIXME: A possible overflow which I don't know how to deal
5432 offset_expr
.X_add_number
+= 4;
5433 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5434 target_big_endian
? treg
: treg
+ 1,
5437 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5438 does not become a variant frag. */
5439 frag_wane (frag_now
);
5448 * The MIPS assembler seems to check for X_add_number not
5449 * being double aligned and generating:
5452 * addiu at,at,%lo(foo+1)
5455 * But, the resulting address is the same after relocation so why
5456 * generate the extra instruction?
5458 if (mips_cpu
== 4650)
5460 as_bad (_("opcode not supported on this processor"));
5463 /* Itbl support may require additional care here. */
5465 if (mips_opts
.isa
!= 1)
5476 if (mips_cpu
== 4650)
5478 as_bad (_("opcode not supported on this processor"));
5482 if (mips_opts
.isa
!= 1)
5490 /* Itbl support may require additional care here. */
5495 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5506 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5516 if (offset_expr
.X_op
!= O_symbol
5517 && offset_expr
.X_op
!= O_constant
)
5519 as_bad (_("expression too complex"));
5520 offset_expr
.X_op
= O_constant
;
5523 /* Even on a big endian machine $fn comes before $fn+1. We have
5524 to adjust when loading from memory. We set coproc if we must
5525 load $fn+1 first. */
5526 /* Itbl support may require additional care here. */
5527 if (! target_big_endian
)
5530 if (mips_pic
== NO_PIC
5531 || offset_expr
.X_op
== O_constant
)
5533 /* If this is a reference to a GP relative symbol, we want
5534 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5535 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5536 If we have a base register, we use this
5538 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5539 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5540 If this is not a GP relative symbol, we want
5541 lui $at,<sym> (BFD_RELOC_HI16_S)
5542 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5543 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5544 If there is a base register, we add it to $at after the
5545 lui instruction. If there is a constant, we always use
5547 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5548 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5568 ((bfd_arch_bits_per_address (stdoutput
) == 32
5569 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5570 ? "addu" : "daddu"),
5571 "d,v,t", AT
, breg
, GP
);
5577 /* Itbl support may require additional care here. */
5578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5579 coproc
? treg
+ 1 : treg
,
5580 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5581 offset_expr
.X_add_number
+= 4;
5583 /* Set mips_optimize to 2 to avoid inserting an
5585 hold_mips_optimize
= mips_optimize
;
5587 /* Itbl support may require additional care here. */
5588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5589 coproc
? treg
: treg
+ 1,
5590 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5591 mips_optimize
= hold_mips_optimize
;
5593 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5594 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5595 used_at
&& mips_opts
.noat
),
5596 offset_expr
.X_add_symbol
, (offsetT
) 0,
5599 /* We just generated two relocs. When tc_gen_reloc
5600 handles this case, it will skip the first reloc and
5601 handle the second. The second reloc already has an
5602 extra addend of 4, which we added above. We must
5603 subtract it out, and then subtract another 4 to make
5604 the first reloc come out right. The second reloc
5605 will come out right because we are going to add 4 to
5606 offset_expr when we build its instruction below.
5608 If we have a symbol, then we don't want to include
5609 the offset, because it will wind up being included
5610 when we generate the reloc. */
5612 if (offset_expr
.X_op
== O_constant
)
5613 offset_expr
.X_add_number
-= 8;
5616 offset_expr
.X_add_number
= -4;
5617 offset_expr
.X_op
= O_constant
;
5620 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5625 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5626 ((bfd_arch_bits_per_address (stdoutput
) == 32
5627 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5628 ? "addu" : "daddu"),
5629 "d,v,t", AT
, breg
, AT
);
5633 /* Itbl support may require additional care here. */
5634 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5635 coproc
? treg
+ 1 : treg
,
5636 (int) BFD_RELOC_LO16
, AT
);
5639 /* FIXME: How do we handle overflow here? */
5640 offset_expr
.X_add_number
+= 4;
5641 /* Itbl support may require additional care here. */
5642 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5643 coproc
? treg
: treg
+ 1,
5644 (int) BFD_RELOC_LO16
, AT
);
5646 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5650 /* If this is a reference to an external symbol, we want
5651 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5656 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5658 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5659 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5660 If there is a base register we add it to $at before the
5661 lwc1 instructions. If there is a constant we include it
5662 in the lwc1 instructions. */
5664 expr1
.X_add_number
= offset_expr
.X_add_number
;
5665 offset_expr
.X_add_number
= 0;
5666 if (expr1
.X_add_number
< -0x8000
5667 || expr1
.X_add_number
>= 0x8000 - 4)
5668 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5673 frag_grow (24 + off
);
5674 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5675 ((bfd_arch_bits_per_address (stdoutput
) == 32
5676 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5678 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5682 ((bfd_arch_bits_per_address (stdoutput
) == 32
5683 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5684 ? "addu" : "daddu"),
5685 "d,v,t", AT
, breg
, AT
);
5686 /* Itbl support may require additional care here. */
5687 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5688 coproc
? treg
+ 1 : treg
,
5689 (int) BFD_RELOC_LO16
, AT
);
5690 expr1
.X_add_number
+= 4;
5692 /* Set mips_optimize to 2 to avoid inserting an undesired
5694 hold_mips_optimize
= mips_optimize
;
5696 /* Itbl support may require additional care here. */
5697 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5698 coproc
? treg
: treg
+ 1,
5699 (int) BFD_RELOC_LO16
, AT
);
5700 mips_optimize
= hold_mips_optimize
;
5702 (void) frag_var (rs_machine_dependent
, 0, 0,
5703 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5704 offset_expr
.X_add_symbol
, (offsetT
) 0,
5707 else if (mips_pic
== SVR4_PIC
)
5711 /* If this is a reference to an external symbol, we want
5712 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5714 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5719 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5721 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5722 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5723 If there is a base register we add it to $at before the
5724 lwc1 instructions. If there is a constant we include it
5725 in the lwc1 instructions. */
5727 expr1
.X_add_number
= offset_expr
.X_add_number
;
5728 offset_expr
.X_add_number
= 0;
5729 if (expr1
.X_add_number
< -0x8000
5730 || expr1
.X_add_number
>= 0x8000 - 4)
5731 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5732 if (reg_needs_delay (GP
))
5741 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5742 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5744 ((bfd_arch_bits_per_address (stdoutput
) == 32
5745 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5746 ? "addu" : "daddu"),
5747 "d,v,t", AT
, AT
, GP
);
5748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5749 ((bfd_arch_bits_per_address (stdoutput
) == 32
5750 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5752 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5756 ((bfd_arch_bits_per_address (stdoutput
) == 32
5757 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5758 ? "addu" : "daddu"),
5759 "d,v,t", AT
, breg
, AT
);
5760 /* Itbl support may require additional care here. */
5761 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5762 coproc
? treg
+ 1 : treg
,
5763 (int) BFD_RELOC_LO16
, AT
);
5764 expr1
.X_add_number
+= 4;
5766 /* Set mips_optimize to 2 to avoid inserting an undesired
5768 hold_mips_optimize
= mips_optimize
;
5770 /* Itbl support may require additional care here. */
5771 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5772 coproc
? treg
: treg
+ 1,
5773 (int) BFD_RELOC_LO16
, AT
);
5774 mips_optimize
= hold_mips_optimize
;
5775 expr1
.X_add_number
-= 4;
5777 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5778 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5779 8 + gpdel
+ off
, 1, 0),
5780 offset_expr
.X_add_symbol
, (offsetT
) 0,
5784 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5787 macro_build (p
, &icnt
, &offset_expr
,
5788 ((bfd_arch_bits_per_address (stdoutput
) == 32
5789 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5791 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5793 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5797 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5798 ((bfd_arch_bits_per_address (stdoutput
) == 32
5799 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5800 ? "addu" : "daddu"),
5801 "d,v,t", AT
, breg
, AT
);
5804 /* Itbl support may require additional care here. */
5805 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5806 coproc
? treg
+ 1 : treg
,
5807 (int) BFD_RELOC_LO16
, AT
);
5809 expr1
.X_add_number
+= 4;
5811 /* Set mips_optimize to 2 to avoid inserting an undesired
5813 hold_mips_optimize
= mips_optimize
;
5815 /* Itbl support may require additional care here. */
5816 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5817 coproc
? treg
: treg
+ 1,
5818 (int) BFD_RELOC_LO16
, AT
);
5819 mips_optimize
= hold_mips_optimize
;
5821 else if (mips_pic
== EMBEDDED_PIC
)
5823 /* If there is no base register, we use
5824 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5825 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5826 If we have a base register, we use
5828 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5829 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5839 ((bfd_arch_bits_per_address (stdoutput
) == 32
5840 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5841 ? "addu" : "daddu"),
5842 "d,v,t", AT
, breg
, GP
);
5847 /* Itbl support may require additional care here. */
5848 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5849 coproc
? treg
+ 1 : treg
,
5850 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5851 offset_expr
.X_add_number
+= 4;
5852 /* Itbl support may require additional care here. */
5853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5854 coproc
? treg
: treg
+ 1,
5855 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5871 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5872 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5873 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5874 (int) BFD_RELOC_LO16
, breg
);
5875 offset_expr
.X_add_number
+= 4;
5876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5877 (int) BFD_RELOC_LO16
, breg
);
5880 /* New code added to support COPZ instructions.
5881 This code builds table entries out of the macros in mip_opcodes.
5882 R4000 uses interlocks to handle coproc delays.
5883 Other chips (like the R3000) require nops to be inserted for delays.
5885 FIXME: Currently, we require that the user handle delays.
5886 In order to fill delay slots for non-interlocked chips,
5887 we must have a way to specify delays based on the coprocessor.
5888 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5889 What are the side-effects of the cop instruction?
5890 What cache support might we have and what are its effects?
5891 Both coprocessor & memory require delays. how long???
5892 What registers are read/set/modified?
5894 If an itbl is provided to interpret cop instructions,
5895 this knowledge can be encoded in the itbl spec. */
5909 /* For now we just do C (same as Cz). The parameter will be
5910 stored in insn_opcode by mips_ip. */
5911 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5915 #ifdef LOSING_COMPILER
5917 /* Try and see if this is a new itbl instruction.
5918 This code builds table entries out of the macros in mip_opcodes.
5919 FIXME: For now we just assemble the expression and pass it's
5920 value along as a 32-bit immediate.
5921 We may want to have the assembler assemble this value,
5922 so that we gain the assembler's knowledge of delay slots,
5924 Would it be more efficient to use mask (id) here? */
5925 if (itbl_have_entries
5926 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5928 s
= ip
->insn_mo
->name
;
5930 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5931 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5938 as_warn (_("Macro used $at after \".set noat\""));
5943 struct mips_cl_insn
*ip
;
5945 register int treg
, sreg
, dreg
, breg
;
5961 bfd_reloc_code_real_type r
;
5964 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5965 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5966 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5967 mask
= ip
->insn_mo
->mask
;
5969 expr1
.X_op
= O_constant
;
5970 expr1
.X_op_symbol
= NULL
;
5971 expr1
.X_add_symbol
= NULL
;
5972 expr1
.X_add_number
= 1;
5976 #endif /* LOSING_COMPILER */
5981 macro_build ((char *) NULL
, &icnt
, NULL
,
5982 dbl
? "dmultu" : "multu",
5984 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5990 /* The MIPS assembler some times generates shifts and adds. I'm
5991 not trying to be that fancy. GCC should do this for us
5993 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
,
5995 dbl
? "dmult" : "mult",
5997 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6010 mips_emit_delays (true);
6011 ++mips_opts
.noreorder
;
6012 mips_any_noreorder
= 1;
6014 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6015 macro_build ((char *) NULL
, &icnt
, NULL
,
6016 dbl
? "dmult" : "mult",
6017 "s,t", sreg
, imm
? AT
: treg
);
6018 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6019 macro_build ((char *) NULL
, &icnt
, NULL
,
6020 dbl
? "dsra32" : "sra",
6021 "d,w,<", dreg
, dreg
, 31);
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6027 expr1
.X_add_number
= 8;
6028 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6030 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6032 --mips_opts
.noreorder
;
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6046 mips_emit_delays (true);
6047 ++mips_opts
.noreorder
;
6048 mips_any_noreorder
= 1;
6050 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6051 macro_build ((char *) NULL
, &icnt
, NULL
,
6052 dbl
? "dmultu" : "multu",
6053 "s,t", sreg
, imm
? AT
: treg
);
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6055 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6057 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6060 expr1
.X_add_number
= 8;
6061 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6065 --mips_opts
.noreorder
;
6069 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6077 if (imm_expr
.X_op
!= O_constant
)
6078 as_bad (_("rotate count too large"));
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6080 (int) (imm_expr
.X_add_number
& 0x1f));
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6082 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6083 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6087 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6088 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6089 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6095 if (imm_expr
.X_op
!= O_constant
)
6096 as_bad (_("rotate count too large"));
6097 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6098 (int) (imm_expr
.X_add_number
& 0x1f));
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6100 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6101 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6105 if (mips_cpu
== 4650)
6107 as_bad (_("opcode not supported on this processor"));
6110 assert (mips_opts
.isa
== 1);
6111 /* Even on a big endian machine $fn comes before $fn+1. We have
6112 to adjust when storing to memory. */
6113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6114 target_big_endian
? treg
+ 1 : treg
,
6115 (int) BFD_RELOC_LO16
, breg
);
6116 offset_expr
.X_add_number
+= 4;
6117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6118 target_big_endian
? treg
: treg
+ 1,
6119 (int) BFD_RELOC_LO16
, breg
);
6124 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6125 treg
, (int) BFD_RELOC_LO16
);
6127 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6128 sreg
, (int) BFD_RELOC_LO16
);
6131 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6133 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6134 dreg
, (int) BFD_RELOC_LO16
);
6139 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6141 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6142 sreg
, (int) BFD_RELOC_LO16
);
6147 as_warn (_("Instruction %s: result is always false"),
6149 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6152 if (imm_expr
.X_op
== O_constant
6153 && imm_expr
.X_add_number
>= 0
6154 && imm_expr
.X_add_number
< 0x10000)
6156 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6157 sreg
, (int) BFD_RELOC_LO16
);
6160 else if (imm_expr
.X_op
== O_constant
6161 && imm_expr
.X_add_number
> -0x8000
6162 && imm_expr
.X_add_number
< 0)
6164 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6165 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6166 ((bfd_arch_bits_per_address (stdoutput
) == 32
6167 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6168 ? "addiu" : "daddiu"),
6169 "t,r,j", dreg
, sreg
,
6170 (int) BFD_RELOC_LO16
);
6175 load_register (&icnt
, AT
, &imm_expr
, 0);
6176 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6180 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6181 (int) BFD_RELOC_LO16
);
6186 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6192 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6193 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6194 (int) BFD_RELOC_LO16
);
6197 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6199 if (imm_expr
.X_op
== O_constant
6200 && imm_expr
.X_add_number
>= -0x8000
6201 && imm_expr
.X_add_number
< 0x8000)
6203 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6204 mask
== M_SGE_I
? "slti" : "sltiu",
6205 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6210 load_register (&icnt
, AT
, &imm_expr
, 0);
6211 macro_build ((char *) NULL
, &icnt
, NULL
,
6212 mask
== M_SGE_I
? "slt" : "sltu",
6213 "d,v,t", dreg
, sreg
, AT
);
6216 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6217 (int) BFD_RELOC_LO16
);
6222 case M_SGT
: /* sreg > treg <==> treg < sreg */
6228 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6231 case M_SGT_I
: /* sreg > I <==> I < sreg */
6237 load_register (&icnt
, AT
, &imm_expr
, 0);
6238 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6241 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6247 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6248 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6249 (int) BFD_RELOC_LO16
);
6252 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6258 load_register (&icnt
, AT
, &imm_expr
, 0);
6259 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6260 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6261 (int) BFD_RELOC_LO16
);
6265 if (imm_expr
.X_op
== O_constant
6266 && imm_expr
.X_add_number
>= -0x8000
6267 && imm_expr
.X_add_number
< 0x8000)
6269 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6270 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6273 load_register (&icnt
, AT
, &imm_expr
, 0);
6274 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6278 if (imm_expr
.X_op
== O_constant
6279 && imm_expr
.X_add_number
>= -0x8000
6280 && imm_expr
.X_add_number
< 0x8000)
6282 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6283 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6286 load_register (&icnt
, AT
, &imm_expr
, 0);
6287 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6293 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6296 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6300 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6302 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6310 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6316 as_warn (_("Instruction %s: result is always true"),
6318 macro_build ((char *) NULL
, &icnt
, &expr1
,
6319 ((bfd_arch_bits_per_address (stdoutput
) == 32
6320 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6321 ? "addiu" : "daddiu"),
6322 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6325 if (imm_expr
.X_op
== O_constant
6326 && imm_expr
.X_add_number
>= 0
6327 && imm_expr
.X_add_number
< 0x10000)
6329 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6330 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6333 else if (imm_expr
.X_op
== O_constant
6334 && imm_expr
.X_add_number
> -0x8000
6335 && imm_expr
.X_add_number
< 0)
6337 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6338 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6339 ((bfd_arch_bits_per_address (stdoutput
) == 32
6340 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6341 ? "addiu" : "daddiu"),
6342 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6347 load_register (&icnt
, AT
, &imm_expr
, 0);
6348 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6352 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6360 if (imm_expr
.X_op
== O_constant
6361 && imm_expr
.X_add_number
> -0x8000
6362 && imm_expr
.X_add_number
<= 0x8000)
6364 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6365 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6366 dbl
? "daddi" : "addi",
6367 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6370 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6371 macro_build ((char *) NULL
, &icnt
, NULL
,
6372 dbl
? "dsub" : "sub",
6373 "d,v,t", dreg
, sreg
, AT
);
6379 if (imm_expr
.X_op
== O_constant
6380 && imm_expr
.X_add_number
> -0x8000
6381 && imm_expr
.X_add_number
<= 0x8000)
6383 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6384 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6385 dbl
? "daddiu" : "addiu",
6386 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6389 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6390 macro_build ((char *) NULL
, &icnt
, NULL
,
6391 dbl
? "dsubu" : "subu",
6392 "d,v,t", dreg
, sreg
, AT
);
6413 load_register (&icnt
, AT
, &imm_expr
, 0);
6414 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6419 assert (mips_opts
.isa
== 1);
6420 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6421 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6424 * Is the double cfc1 instruction a bug in the mips assembler;
6425 * or is there a reason for it?
6427 mips_emit_delays (true);
6428 ++mips_opts
.noreorder
;
6429 mips_any_noreorder
= 1;
6430 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6431 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6432 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6433 expr1
.X_add_number
= 3;
6434 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6435 (int) BFD_RELOC_LO16
);
6436 expr1
.X_add_number
= 2;
6437 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6438 (int) BFD_RELOC_LO16
);
6439 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6440 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6441 macro_build ((char *) NULL
, &icnt
, NULL
,
6442 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6443 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6444 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6445 --mips_opts
.noreorder
;
6454 if (offset_expr
.X_add_number
>= 0x7fff)
6455 as_bad (_("operand overflow"));
6456 /* avoid load delay */
6457 if (! target_big_endian
)
6458 offset_expr
.X_add_number
+= 1;
6459 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6460 (int) BFD_RELOC_LO16
, breg
);
6461 if (! target_big_endian
)
6462 offset_expr
.X_add_number
-= 1;
6464 offset_expr
.X_add_number
+= 1;
6465 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6466 (int) BFD_RELOC_LO16
, breg
);
6467 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6468 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6481 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6482 as_bad (_("operand overflow"));
6483 if (! target_big_endian
)
6484 offset_expr
.X_add_number
+= off
;
6485 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6486 (int) BFD_RELOC_LO16
, breg
);
6487 if (! target_big_endian
)
6488 offset_expr
.X_add_number
-= off
;
6490 offset_expr
.X_add_number
+= off
;
6491 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6492 (int) BFD_RELOC_LO16
, breg
);
6505 load_address (&icnt
, AT
, &offset_expr
);
6507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6508 ((bfd_arch_bits_per_address (stdoutput
) == 32
6509 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6510 ? "addu" : "daddu"),
6511 "d,v,t", AT
, AT
, breg
);
6512 if (! target_big_endian
)
6513 expr1
.X_add_number
= off
;
6515 expr1
.X_add_number
= 0;
6516 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6517 (int) BFD_RELOC_LO16
, AT
);
6518 if (! target_big_endian
)
6519 expr1
.X_add_number
= 0;
6521 expr1
.X_add_number
= off
;
6522 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6523 (int) BFD_RELOC_LO16
, AT
);
6528 load_address (&icnt
, AT
, &offset_expr
);
6530 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6531 ((bfd_arch_bits_per_address (stdoutput
) == 32
6532 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6533 ? "addu" : "daddu"),
6534 "d,v,t", AT
, AT
, breg
);
6535 if (target_big_endian
)
6536 expr1
.X_add_number
= 0;
6537 macro_build ((char *) NULL
, &icnt
, &expr1
,
6538 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6539 (int) BFD_RELOC_LO16
, AT
);
6540 if (target_big_endian
)
6541 expr1
.X_add_number
= 1;
6543 expr1
.X_add_number
= 0;
6544 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6545 (int) BFD_RELOC_LO16
, AT
);
6546 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6548 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6553 if (offset_expr
.X_add_number
>= 0x7fff)
6554 as_bad (_("operand overflow"));
6555 if (target_big_endian
)
6556 offset_expr
.X_add_number
+= 1;
6557 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6558 (int) BFD_RELOC_LO16
, breg
);
6559 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6560 if (target_big_endian
)
6561 offset_expr
.X_add_number
-= 1;
6563 offset_expr
.X_add_number
+= 1;
6564 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6565 (int) BFD_RELOC_LO16
, breg
);
6578 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6579 as_bad (_("operand overflow"));
6580 if (! target_big_endian
)
6581 offset_expr
.X_add_number
+= off
;
6582 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6583 (int) BFD_RELOC_LO16
, breg
);
6584 if (! target_big_endian
)
6585 offset_expr
.X_add_number
-= off
;
6587 offset_expr
.X_add_number
+= off
;
6588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6589 (int) BFD_RELOC_LO16
, breg
);
6602 load_address (&icnt
, AT
, &offset_expr
);
6604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6605 ((bfd_arch_bits_per_address (stdoutput
) == 32
6606 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6607 ? "addu" : "daddu"),
6608 "d,v,t", AT
, AT
, breg
);
6609 if (! target_big_endian
)
6610 expr1
.X_add_number
= off
;
6612 expr1
.X_add_number
= 0;
6613 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6614 (int) BFD_RELOC_LO16
, AT
);
6615 if (! target_big_endian
)
6616 expr1
.X_add_number
= 0;
6618 expr1
.X_add_number
= off
;
6619 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6620 (int) BFD_RELOC_LO16
, AT
);
6624 load_address (&icnt
, AT
, &offset_expr
);
6626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6627 ((bfd_arch_bits_per_address (stdoutput
) == 32
6628 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6629 ? "addu" : "daddu"),
6630 "d,v,t", AT
, AT
, breg
);
6631 if (! target_big_endian
)
6632 expr1
.X_add_number
= 0;
6633 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6634 (int) BFD_RELOC_LO16
, AT
);
6635 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6637 if (! target_big_endian
)
6638 expr1
.X_add_number
= 1;
6640 expr1
.X_add_number
= 0;
6641 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6642 (int) BFD_RELOC_LO16
, AT
);
6643 if (! target_big_endian
)
6644 expr1
.X_add_number
= 0;
6646 expr1
.X_add_number
= 1;
6647 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6648 (int) BFD_RELOC_LO16
, AT
);
6649 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6651 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6656 /* FIXME: Check if this is one of the itbl macros, since they
6657 are added dynamically. */
6658 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6662 as_warn (_("Macro used $at after \".set noat\""));
6665 /* Implement macros in mips16 mode. */
6669 struct mips_cl_insn
*ip
;
6672 int xreg
, yreg
, zreg
, tmp
;
6676 const char *s
, *s2
, *s3
;
6678 mask
= ip
->insn_mo
->mask
;
6680 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6681 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6682 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6686 expr1
.X_op
= O_constant
;
6687 expr1
.X_op_symbol
= NULL
;
6688 expr1
.X_add_symbol
= NULL
;
6689 expr1
.X_add_number
= 1;
6708 mips_emit_delays (true);
6709 ++mips_opts
.noreorder
;
6710 mips_any_noreorder
= 1;
6711 macro_build ((char *) NULL
, &icnt
, NULL
,
6712 dbl
? "ddiv" : "div",
6713 "0,x,y", xreg
, yreg
);
6714 expr1
.X_add_number
= 2;
6715 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6716 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6718 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6719 since that causes an overflow. We should do that as well,
6720 but I don't see how to do the comparisons without a temporary
6722 --mips_opts
.noreorder
;
6723 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6742 mips_emit_delays (true);
6743 ++mips_opts
.noreorder
;
6744 mips_any_noreorder
= 1;
6745 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6746 expr1
.X_add_number
= 2;
6747 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6748 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6749 --mips_opts
.noreorder
;
6750 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6756 macro_build ((char *) NULL
, &icnt
, NULL
,
6757 dbl
? "dmultu" : "multu",
6759 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6767 if (imm_expr
.X_op
!= O_constant
)
6768 as_bad (_("Unsupported large constant"));
6769 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6770 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6771 dbl
? "daddiu" : "addiu",
6772 "y,x,4", yreg
, xreg
);
6776 if (imm_expr
.X_op
!= O_constant
)
6777 as_bad (_("Unsupported large constant"));
6778 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6779 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6784 if (imm_expr
.X_op
!= O_constant
)
6785 as_bad (_("Unsupported large constant"));
6786 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6787 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6810 goto do_reverse_branch
;
6814 goto do_reverse_branch
;
6826 goto do_reverse_branch
;
6837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6866 goto do_addone_branch_i
;
6871 goto do_addone_branch_i
;
6886 goto do_addone_branch_i
;
6893 if (imm_expr
.X_op
!= O_constant
)
6894 as_bad (_("Unsupported large constant"));
6895 ++imm_expr
.X_add_number
;
6898 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6899 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6903 expr1
.X_add_number
= 0;
6904 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6907 "move", "y,X", xreg
, yreg
);
6908 expr1
.X_add_number
= 2;
6909 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6911 "neg", "x,w", xreg
, xreg
);
6915 /* For consistency checking, verify that all bits are specified either
6916 by the match/mask part of the instruction definition, or by the
6919 validate_mips_insn (opc
)
6920 const struct mips_opcode
*opc
;
6922 const char *p
= opc
->args
;
6924 unsigned long used_bits
= opc
->mask
;
6926 if ((used_bits
& opc
->match
) != opc
->match
)
6928 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6929 opc
->name
, opc
->args
);
6932 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6939 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6940 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6942 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6943 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6944 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6945 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6947 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6950 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6951 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6952 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6953 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6954 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6955 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6956 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6957 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6958 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6959 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6960 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6962 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6963 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6964 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6965 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6967 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6968 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6969 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6970 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6971 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6972 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6973 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6974 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6975 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6978 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6980 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6981 c
, opc
->name
, opc
->args
);
6985 if (used_bits
!= 0xffffffff)
6987 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6988 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6994 /* This routine assembles an instruction into its binary format. As a
6995 side effect, it sets one of the global variables imm_reloc or
6996 offset_reloc to the type of relocation to do if one of the operands
6997 is an address expression. */
7002 struct mips_cl_insn
*ip
;
7007 struct mips_opcode
*insn
;
7010 unsigned int lastregno
= 0;
7013 int full_opcode_match
= 1;
7017 /* If the instruction contains a '.', we first try to match an instruction
7018 including the '.'. Then we try again without the '.'. */
7020 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7023 /* If we stopped on whitespace, then replace the whitespace with null for
7024 the call to hash_find. Save the character we replaced just in case we
7025 have to re-parse the instruction. */
7026 if (isspace ((unsigned char) *s
))
7032 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7034 /* If we didn't find the instruction in the opcode table, try again, but
7035 this time with just the instruction up to, but not including the
7039 /* Restore the character we overwrite above (if any). */
7043 /* Scan up to the first '.' or whitespace. */
7044 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7047 /* If we did not find a '.', then we can quit now. */
7050 insn_error
= "unrecognized opcode";
7054 /* Lookup the instruction in the hash table. */
7056 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7058 insn_error
= "unrecognized opcode";
7062 full_opcode_match
= 0;
7070 assert (strcmp (insn
->name
, str
) == 0);
7072 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7077 if (insn
->pinfo
!= INSN_MACRO
)
7079 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7085 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7086 && strcmp (insn
->name
, insn
[1].name
) == 0)
7093 static char buf
[100];
7095 _("opcode not supported on this processor: %d (MIPS%d)"),
7096 mips_cpu
, mips_opts
.isa
);
7104 ip
->insn_opcode
= insn
->match
;
7105 for (args
= insn
->args
;; ++args
)
7111 case '\0': /* end of args */
7124 ip
->insn_opcode
|= lastregno
<< 21;
7129 ip
->insn_opcode
|= lastregno
<< 16;
7133 ip
->insn_opcode
|= lastregno
<< 11;
7139 /* Handle optional base register.
7140 Either the base register is omitted or
7141 we must have a left paren. */
7142 /* This is dependent on the next operand specifier
7143 is a base register specification. */
7144 assert (args
[1] == 'b' || args
[1] == '5'
7145 || args
[1] == '-' || args
[1] == '4');
7149 case ')': /* these must match exactly */
7154 case '<': /* must be at least one digit */
7156 * According to the manual, if the shift amount is greater
7157 * than 31 or less than 0 the the shift amount should be
7158 * mod 32. In reality the mips assembler issues an error.
7159 * We issue a warning and mask out all but the low 5 bits.
7161 my_getExpression (&imm_expr
, s
);
7162 check_absolute_expr (ip
, &imm_expr
);
7163 if ((unsigned long) imm_expr
.X_add_number
> 31)
7165 as_warn (_("Improper shift amount (%ld)"),
7166 (long) imm_expr
.X_add_number
);
7167 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7169 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7170 imm_expr
.X_op
= O_absent
;
7174 case '>': /* shift amount minus 32 */
7175 my_getExpression (&imm_expr
, s
);
7176 check_absolute_expr (ip
, &imm_expr
);
7177 if ((unsigned long) imm_expr
.X_add_number
< 32
7178 || (unsigned long) imm_expr
.X_add_number
> 63)
7180 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7181 imm_expr
.X_op
= O_absent
;
7186 case 'k': /* cache code */
7187 case 'h': /* prefx code */
7188 my_getExpression (&imm_expr
, s
);
7189 check_absolute_expr (ip
, &imm_expr
);
7190 if ((unsigned long) imm_expr
.X_add_number
> 31)
7192 as_warn (_("Invalid value for `%s' (%lu)"),
7194 (unsigned long) imm_expr
.X_add_number
);
7195 imm_expr
.X_add_number
&= 0x1f;
7198 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7200 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7201 imm_expr
.X_op
= O_absent
;
7205 case 'c': /* break code */
7206 my_getExpression (&imm_expr
, s
);
7207 check_absolute_expr (ip
, &imm_expr
);
7208 if ((unsigned) imm_expr
.X_add_number
> 1023)
7210 as_warn (_("Illegal break code (%ld)"),
7211 (long) imm_expr
.X_add_number
);
7212 imm_expr
.X_add_number
&= 0x3ff;
7214 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7215 imm_expr
.X_op
= O_absent
;
7219 case 'q': /* lower break code */
7220 my_getExpression (&imm_expr
, s
);
7221 check_absolute_expr (ip
, &imm_expr
);
7222 if ((unsigned) imm_expr
.X_add_number
> 1023)
7224 as_warn (_("Illegal lower break code (%ld)"),
7225 (long) imm_expr
.X_add_number
);
7226 imm_expr
.X_add_number
&= 0x3ff;
7228 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7229 imm_expr
.X_op
= O_absent
;
7233 case 'B': /* syscall code */
7234 my_getExpression (&imm_expr
, s
);
7235 check_absolute_expr (ip
, &imm_expr
);
7236 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7237 as_warn (_("Illegal syscall code (%ld)"),
7238 (long) imm_expr
.X_add_number
);
7239 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7240 imm_expr
.X_op
= O_absent
;
7244 case 'C': /* Coprocessor code */
7245 my_getExpression (&imm_expr
, s
);
7246 check_absolute_expr (ip
, &imm_expr
);
7247 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7249 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7250 (long) imm_expr
.X_add_number
);
7251 imm_expr
.X_add_number
&= ((1<<25) - 1);
7253 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7254 imm_expr
.X_op
= O_absent
;
7258 case 'P': /* Performance register */
7259 my_getExpression (&imm_expr
, s
);
7260 check_absolute_expr (ip
, &imm_expr
);
7261 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7263 as_warn (_("Invalidate performance regster (%ld)"),
7264 (long) imm_expr
.X_add_number
);
7265 imm_expr
.X_add_number
&= 1;
7267 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7268 imm_expr
.X_op
= O_absent
;
7272 case 'b': /* base register */
7273 case 'd': /* destination register */
7274 case 's': /* source register */
7275 case 't': /* target register */
7276 case 'r': /* both target and source */
7277 case 'v': /* both dest and source */
7278 case 'w': /* both dest and target */
7279 case 'E': /* coprocessor target register */
7280 case 'G': /* coprocessor destination register */
7281 case 'x': /* ignore register name */
7282 case 'z': /* must be zero register */
7287 if (isdigit ((unsigned char) s
[1]))
7297 while (isdigit ((unsigned char) *s
));
7299 as_bad (_("Invalid register number (%d)"), regno
);
7301 else if (*args
== 'E' || *args
== 'G')
7305 if (s
[1] == 'f' && s
[2] == 'p')
7310 else if (s
[1] == 's' && s
[2] == 'p')
7315 else if (s
[1] == 'g' && s
[2] == 'p')
7320 else if (s
[1] == 'a' && s
[2] == 't')
7325 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7330 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7335 else if (itbl_have_entries
)
7340 p
= s
+ 1; /* advance past '$' */
7341 n
= itbl_get_field (&p
); /* n is name */
7343 /* See if this is a register defined in an
7345 if (itbl_get_reg_val (n
, &r
))
7347 /* Get_field advances to the start of
7348 the next field, so we need to back
7349 rack to the end of the last field. */
7353 s
= strchr (s
, '\0');
7366 as_warn (_("Used $at without \".set noat\""));
7372 if (c
== 'r' || c
== 'v' || c
== 'w')
7379 /* 'z' only matches $0. */
7380 if (c
== 'z' && regno
!= 0)
7383 /* Now that we have assembled one operand, we use the args string
7384 * to figure out where it goes in the instruction. */
7391 ip
->insn_opcode
|= regno
<< 21;
7395 ip
->insn_opcode
|= regno
<< 11;
7400 ip
->insn_opcode
|= regno
<< 16;
7403 /* This case exists because on the r3000 trunc
7404 expands into a macro which requires a gp
7405 register. On the r6000 or r4000 it is
7406 assembled into a single instruction which
7407 ignores the register. Thus the insn version
7408 is MIPS_ISA2 and uses 'x', and the macro
7409 version is MIPS_ISA1 and uses 't'. */
7412 /* This case is for the div instruction, which
7413 acts differently if the destination argument
7414 is $0. This only matches $0, and is checked
7415 outside the switch. */
7418 /* Itbl operand; not yet implemented. FIXME ?? */
7420 /* What about all other operands like 'i', which
7421 can be specified in the opcode table? */
7431 ip
->insn_opcode
|= lastregno
<< 21;
7434 ip
->insn_opcode
|= lastregno
<< 16;
7439 case 'D': /* floating point destination register */
7440 case 'S': /* floating point source register */
7441 case 'T': /* floating point target register */
7442 case 'R': /* floating point source register */
7446 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7456 while (isdigit ((unsigned char) *s
));
7459 as_bad (_("Invalid float register number (%d)"), regno
);
7461 if ((regno
& 1) != 0
7462 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7463 && ! (strcmp (str
, "mtc1") == 0
7464 || strcmp (str
, "mfc1") == 0
7465 || strcmp (str
, "lwc1") == 0
7466 || strcmp (str
, "swc1") == 0
7467 || strcmp (str
, "l.s") == 0
7468 || strcmp (str
, "s.s") == 0))
7469 as_warn (_("Float register should be even, was %d"),
7477 if (c
== 'V' || c
== 'W')
7487 ip
->insn_opcode
|= regno
<< 6;
7491 ip
->insn_opcode
|= regno
<< 11;
7495 ip
->insn_opcode
|= regno
<< 16;
7498 ip
->insn_opcode
|= regno
<< 21;
7509 ip
->insn_opcode
|= lastregno
<< 11;
7512 ip
->insn_opcode
|= lastregno
<< 16;
7518 my_getExpression (&imm_expr
, s
);
7519 if (imm_expr
.X_op
!= O_big
7520 && imm_expr
.X_op
!= O_constant
)
7521 insn_error
= _("absolute expression required");
7526 my_getExpression (&offset_expr
, s
);
7527 imm_reloc
= BFD_RELOC_32
;
7539 unsigned char temp
[8];
7541 unsigned int length
;
7546 /* These only appear as the last operand in an
7547 instruction, and every instruction that accepts
7548 them in any variant accepts them in all variants.
7549 This means we don't have to worry about backing out
7550 any changes if the instruction does not match.
7552 The difference between them is the size of the
7553 floating point constant and where it goes. For 'F'
7554 and 'L' the constant is 64 bits; for 'f' and 'l' it
7555 is 32 bits. Where the constant is placed is based
7556 on how the MIPS assembler does things:
7559 f -- immediate value
7562 The .lit4 and .lit8 sections are only used if
7563 permitted by the -G argument.
7565 When generating embedded PIC code, we use the
7566 .lit8 section but not the .lit4 section (we can do
7567 .lit4 inline easily; we need to put .lit8
7568 somewhere in the data segment, and using .lit8
7569 permits the linker to eventually combine identical
7572 f64
= *args
== 'F' || *args
== 'L';
7574 save_in
= input_line_pointer
;
7575 input_line_pointer
= s
;
7576 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7578 s
= input_line_pointer
;
7579 input_line_pointer
= save_in
;
7580 if (err
!= NULL
&& *err
!= '\0')
7582 as_bad (_("Bad floating point constant: %s"), err
);
7583 memset (temp
, '\0', sizeof temp
);
7584 length
= f64
? 8 : 4;
7587 assert (length
== (f64
? 8 : 4));
7591 && (! USE_GLOBAL_POINTER_OPT
7592 || mips_pic
== EMBEDDED_PIC
7593 || g_switch_value
< 4
7594 || (temp
[0] == 0 && temp
[1] == 0)
7595 || (temp
[2] == 0 && temp
[3] == 0))))
7597 imm_expr
.X_op
= O_constant
;
7598 if (! target_big_endian
)
7599 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7601 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7604 && ((temp
[0] == 0 && temp
[1] == 0)
7605 || (temp
[2] == 0 && temp
[3] == 0))
7606 && ((temp
[4] == 0 && temp
[5] == 0)
7607 || (temp
[6] == 0 && temp
[7] == 0)))
7609 /* The value is simple enough to load with a
7610 couple of instructions. In mips1 mode, set
7611 imm_expr to the high order 32 bits and
7612 offset_expr to the low order 32 bits.
7613 Otherwise, set imm_expr to the entire 64 bit
7615 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7617 imm_expr
.X_op
= O_constant
;
7618 offset_expr
.X_op
= O_constant
;
7619 if (! target_big_endian
)
7621 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7622 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7626 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7627 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7629 if (offset_expr
.X_add_number
== 0)
7630 offset_expr
.X_op
= O_absent
;
7632 else if (sizeof (imm_expr
.X_add_number
) > 4)
7634 imm_expr
.X_op
= O_constant
;
7635 if (! target_big_endian
)
7636 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7638 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7642 imm_expr
.X_op
= O_big
;
7643 imm_expr
.X_add_number
= 4;
7644 if (! target_big_endian
)
7646 generic_bignum
[0] = bfd_getl16 (temp
);
7647 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7648 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7649 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7653 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7654 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7655 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7656 generic_bignum
[3] = bfd_getb16 (temp
);
7662 const char *newname
;
7665 /* Switch to the right section. */
7667 subseg
= now_subseg
;
7670 default: /* unused default case avoids warnings. */
7672 newname
= RDATA_SECTION_NAME
;
7673 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7674 || mips_pic
== EMBEDDED_PIC
)
7678 if (mips_pic
== EMBEDDED_PIC
)
7681 newname
= RDATA_SECTION_NAME
;
7684 assert (!USE_GLOBAL_POINTER_OPT
7685 || g_switch_value
>= 4);
7689 new_seg
= subseg_new (newname
, (subsegT
) 0);
7690 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7691 bfd_set_section_flags (stdoutput
, new_seg
,
7696 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7697 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7698 && strcmp (TARGET_OS
, "elf") != 0)
7699 record_alignment (new_seg
, 4);
7701 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7703 as_bad (_("Can't use floating point insn in this section"));
7705 /* Set the argument to the current address in the
7707 offset_expr
.X_op
= O_symbol
;
7708 offset_expr
.X_add_symbol
=
7709 symbol_new ("L0\001", now_seg
,
7710 (valueT
) frag_now_fix (), frag_now
);
7711 offset_expr
.X_add_number
= 0;
7713 /* Put the floating point number into the section. */
7714 p
= frag_more ((int) length
);
7715 memcpy (p
, temp
, length
);
7717 /* Switch back to the original section. */
7718 subseg_set (seg
, subseg
);
7723 case 'i': /* 16 bit unsigned immediate */
7724 case 'j': /* 16 bit signed immediate */
7725 imm_reloc
= BFD_RELOC_LO16
;
7726 c
= my_getSmallExpression (&imm_expr
, s
);
7731 if (imm_expr
.X_op
== O_constant
)
7732 imm_expr
.X_add_number
=
7733 (imm_expr
.X_add_number
>> 16) & 0xffff;
7736 imm_reloc
= BFD_RELOC_HI16_S
;
7737 imm_unmatched_hi
= true;
7740 imm_reloc
= BFD_RELOC_HI16
;
7742 else if (imm_expr
.X_op
== O_constant
)
7743 imm_expr
.X_add_number
&= 0xffff;
7747 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7748 || ((imm_expr
.X_add_number
< 0
7749 || imm_expr
.X_add_number
>= 0x10000)
7750 && imm_expr
.X_op
== O_constant
))
7752 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7753 !strcmp (insn
->name
, insn
[1].name
))
7755 if (imm_expr
.X_op
== O_constant
7756 || imm_expr
.X_op
== O_big
)
7757 as_bad (_("16 bit expression not in range 0..65535"));
7765 /* The upper bound should be 0x8000, but
7766 unfortunately the MIPS assembler accepts numbers
7767 from 0x8000 to 0xffff and sign extends them, and
7768 we want to be compatible. We only permit this
7769 extended range for an instruction which does not
7770 provide any further alternates, since those
7771 alternates may handle other cases. People should
7772 use the numbers they mean, rather than relying on
7773 a mysterious sign extension. */
7774 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7775 strcmp (insn
->name
, insn
[1].name
) == 0);
7780 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7781 || ((imm_expr
.X_add_number
< -0x8000
7782 || imm_expr
.X_add_number
>= max
)
7783 && imm_expr
.X_op
== O_constant
)
7785 && imm_expr
.X_add_number
< 0
7786 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7787 && imm_expr
.X_unsigned
7788 && sizeof (imm_expr
.X_add_number
) <= 4))
7792 if (imm_expr
.X_op
== O_constant
7793 || imm_expr
.X_op
== O_big
)
7794 as_bad (_("16 bit expression not in range -32768..32767"));
7800 case 'o': /* 16 bit offset */
7801 c
= my_getSmallExpression (&offset_expr
, s
);
7803 /* If this value won't fit into a 16 bit offset, then go
7804 find a macro that will generate the 32 bit offset
7805 code pattern. As a special hack, we accept the
7806 difference of two local symbols as a constant. This
7807 is required to suppose embedded PIC switches, which
7808 use an instruction which looks like
7809 lw $4,$L12-$LS12($4)
7810 The problem with handling this in a more general
7811 fashion is that the macro function doesn't expect to
7812 see anything which can be handled in a single
7813 constant instruction. */
7815 && (offset_expr
.X_op
!= O_constant
7816 || offset_expr
.X_add_number
>= 0x8000
7817 || offset_expr
.X_add_number
< -0x8000)
7818 && (mips_pic
!= EMBEDDED_PIC
7819 || offset_expr
.X_op
!= O_subtract
7820 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7824 if (c
== 'h' || c
== 'H')
7826 if (offset_expr
.X_op
!= O_constant
)
7828 offset_expr
.X_add_number
=
7829 (offset_expr
.X_add_number
>> 16) & 0xffff;
7831 offset_reloc
= BFD_RELOC_LO16
;
7835 case 'p': /* pc relative offset */
7836 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7837 my_getExpression (&offset_expr
, s
);
7841 case 'u': /* upper 16 bits */
7842 c
= my_getSmallExpression (&imm_expr
, s
);
7843 imm_reloc
= BFD_RELOC_LO16
;
7848 if (imm_expr
.X_op
== O_constant
)
7849 imm_expr
.X_add_number
=
7850 (imm_expr
.X_add_number
>> 16) & 0xffff;
7853 imm_reloc
= BFD_RELOC_HI16_S
;
7854 imm_unmatched_hi
= true;
7857 imm_reloc
= BFD_RELOC_HI16
;
7859 else if (imm_expr
.X_op
== O_constant
)
7860 imm_expr
.X_add_number
&= 0xffff;
7862 if (imm_expr
.X_op
== O_constant
7863 && (imm_expr
.X_add_number
< 0
7864 || imm_expr
.X_add_number
>= 0x10000))
7865 as_bad (_("lui expression not in range 0..65535"));
7869 case 'a': /* 26 bit address */
7870 my_getExpression (&offset_expr
, s
);
7872 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7875 case 'N': /* 3 bit branch condition code */
7876 case 'M': /* 3 bit compare condition code */
7877 if (strncmp (s
, "$fcc", 4) != 0)
7887 while (isdigit ((unsigned char) *s
));
7889 as_bad (_("invalid condition code register $fcc%d"), regno
);
7891 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7893 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7897 as_bad (_("bad char = '%c'\n"), *args
);
7902 /* Args don't match. */
7903 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7904 !strcmp (insn
->name
, insn
[1].name
))
7910 insn_error
= _("illegal operands");
7915 /* This routine assembles an instruction into its binary format when
7916 assembling for the mips16. As a side effect, it sets one of the
7917 global variables imm_reloc or offset_reloc to the type of
7918 relocation to do if one of the operands is an address expression.
7919 It also sets mips16_small and mips16_ext if the user explicitly
7920 requested a small or extended instruction. */
7925 struct mips_cl_insn
*ip
;
7929 struct mips_opcode
*insn
;
7932 unsigned int lastregno
= 0;
7937 mips16_small
= false;
7940 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7952 if (s
[1] == 't' && s
[2] == ' ')
7955 mips16_small
= true;
7959 else if (s
[1] == 'e' && s
[2] == ' ')
7968 insn_error
= _("unknown opcode");
7972 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7973 mips16_small
= true;
7975 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7977 insn_error
= _("unrecognized opcode");
7984 assert (strcmp (insn
->name
, str
) == 0);
7987 ip
->insn_opcode
= insn
->match
;
7988 ip
->use_extend
= false;
7989 imm_expr
.X_op
= O_absent
;
7990 imm_reloc
= BFD_RELOC_UNUSED
;
7991 offset_expr
.X_op
= O_absent
;
7992 offset_reloc
= BFD_RELOC_UNUSED
;
7993 for (args
= insn
->args
; 1; ++args
)
8000 /* In this switch statement we call break if we did not find
8001 a match, continue if we did find a match, or return if we
8010 /* Stuff the immediate value in now, if we can. */
8011 if (imm_expr
.X_op
== O_constant
8012 && imm_reloc
> BFD_RELOC_UNUSED
8013 && insn
->pinfo
!= INSN_MACRO
)
8015 mips16_immed ((char *) NULL
, 0,
8016 imm_reloc
- BFD_RELOC_UNUSED
,
8017 imm_expr
.X_add_number
, true, mips16_small
,
8018 mips16_ext
, &ip
->insn_opcode
,
8019 &ip
->use_extend
, &ip
->extend
);
8020 imm_expr
.X_op
= O_absent
;
8021 imm_reloc
= BFD_RELOC_UNUSED
;
8035 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8038 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8054 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8056 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8073 if (isdigit ((unsigned char) s
[1]))
8083 while (isdigit ((unsigned char) *s
));
8086 as_bad (_("invalid register number (%d)"), regno
);
8092 if (s
[1] == 'f' && s
[2] == 'p')
8097 else if (s
[1] == 's' && s
[2] == 'p')
8102 else if (s
[1] == 'g' && s
[2] == 'p')
8107 else if (s
[1] == 'a' && s
[2] == 't')
8112 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8117 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8130 if (c
== 'v' || c
== 'w')
8132 regno
= mips16_to_32_reg_map
[lastregno
];
8146 regno
= mips32_to_16_reg_map
[regno
];
8151 regno
= ILLEGAL_REG
;
8156 regno
= ILLEGAL_REG
;
8161 regno
= ILLEGAL_REG
;
8166 if (regno
== AT
&& ! mips_opts
.noat
)
8167 as_warn (_("used $at without \".set noat\""));
8174 if (regno
== ILLEGAL_REG
)
8181 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8185 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8188 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8191 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8197 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8200 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8201 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8211 if (strncmp (s
, "$pc", 3) == 0)
8235 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8237 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8238 and generate the appropriate reloc. If the text
8239 inside %gprel is not a symbol name with an
8240 optional offset, then we generate a normal reloc
8241 and will probably fail later. */
8242 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8243 if (imm_expr
.X_op
== O_symbol
)
8246 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8248 ip
->use_extend
= true;
8255 /* Just pick up a normal expression. */
8256 my_getExpression (&imm_expr
, s
);
8259 if (imm_expr
.X_op
== O_register
)
8261 /* What we thought was an expression turned out to
8264 if (s
[0] == '(' && args
[1] == '(')
8266 /* It looks like the expression was omitted
8267 before a register indirection, which means
8268 that the expression is implicitly zero. We
8269 still set up imm_expr, so that we handle
8270 explicit extensions correctly. */
8271 imm_expr
.X_op
= O_constant
;
8272 imm_expr
.X_add_number
= 0;
8273 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8280 /* We need to relax this instruction. */
8281 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8290 /* We use offset_reloc rather than imm_reloc for the PC
8291 relative operands. This lets macros with both
8292 immediate and address operands work correctly. */
8293 my_getExpression (&offset_expr
, s
);
8295 if (offset_expr
.X_op
== O_register
)
8298 /* We need to relax this instruction. */
8299 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8303 case '6': /* break code */
8304 my_getExpression (&imm_expr
, s
);
8305 check_absolute_expr (ip
, &imm_expr
);
8306 if ((unsigned long) imm_expr
.X_add_number
> 63)
8308 as_warn (_("Invalid value for `%s' (%lu)"),
8310 (unsigned long) imm_expr
.X_add_number
);
8311 imm_expr
.X_add_number
&= 0x3f;
8313 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8314 imm_expr
.X_op
= O_absent
;
8318 case 'a': /* 26 bit address */
8319 my_getExpression (&offset_expr
, s
);
8321 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8322 ip
->insn_opcode
<<= 16;
8325 case 'l': /* register list for entry macro */
8326 case 'L': /* register list for exit macro */
8336 int freg
, reg1
, reg2
;
8338 while (*s
== ' ' || *s
== ',')
8342 as_bad (_("can't parse register list"));
8354 while (isdigit ((unsigned char) *s
))
8376 as_bad (_("invalid register list"));
8381 while (isdigit ((unsigned char) *s
))
8388 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8393 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8398 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8399 mask
|= (reg2
- 3) << 3;
8400 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8401 mask
|= (reg2
- 15) << 1;
8402 else if (reg1
== 31 && reg2
== 31)
8406 as_bad (_("invalid register list"));
8410 /* The mask is filled in in the opcode table for the
8411 benefit of the disassembler. We remove it before
8412 applying the actual mask. */
8413 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8414 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8418 case 'e': /* extend code */
8419 my_getExpression (&imm_expr
, s
);
8420 check_absolute_expr (ip
, &imm_expr
);
8421 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8423 as_warn (_("Invalid value for `%s' (%lu)"),
8425 (unsigned long) imm_expr
.X_add_number
);
8426 imm_expr
.X_add_number
&= 0x7ff;
8428 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8429 imm_expr
.X_op
= O_absent
;
8439 /* Args don't match. */
8440 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8441 strcmp (insn
->name
, insn
[1].name
) == 0)
8448 insn_error
= _("illegal operands");
8454 /* This structure holds information we know about a mips16 immediate
8457 struct mips16_immed_operand
8459 /* The type code used in the argument string in the opcode table. */
8461 /* The number of bits in the short form of the opcode. */
8463 /* The number of bits in the extended form of the opcode. */
8465 /* The amount by which the short form is shifted when it is used;
8466 for example, the sw instruction has a shift count of 2. */
8468 /* The amount by which the short form is shifted when it is stored
8469 into the instruction code. */
8471 /* Non-zero if the short form is unsigned. */
8473 /* Non-zero if the extended form is unsigned. */
8475 /* Non-zero if the value is PC relative. */
8479 /* The mips16 immediate operand types. */
8481 static const struct mips16_immed_operand mips16_immed_operands
[] =
8483 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8484 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8485 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8486 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8487 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8488 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8489 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8490 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8491 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8492 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8493 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8494 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8495 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8496 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8497 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8498 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8499 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8500 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8501 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8502 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8503 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8506 #define MIPS16_NUM_IMMED \
8507 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8509 /* Handle a mips16 instruction with an immediate value. This or's the
8510 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8511 whether an extended value is needed; if one is needed, it sets
8512 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8513 If SMALL is true, an unextended opcode was explicitly requested.
8514 If EXT is true, an extended opcode was explicitly requested. If
8515 WARN is true, warn if EXT does not match reality. */
8518 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8527 unsigned long *insn
;
8528 boolean
*use_extend
;
8529 unsigned short *extend
;
8531 register const struct mips16_immed_operand
*op
;
8532 int mintiny
, maxtiny
;
8535 op
= mips16_immed_operands
;
8536 while (op
->type
!= type
)
8539 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8544 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8547 maxtiny
= 1 << op
->nbits
;
8552 maxtiny
= (1 << op
->nbits
) - 1;
8557 mintiny
= - (1 << (op
->nbits
- 1));
8558 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8561 /* Branch offsets have an implicit 0 in the lowest bit. */
8562 if (type
== 'p' || type
== 'q')
8565 if ((val
& ((1 << op
->shift
) - 1)) != 0
8566 || val
< (mintiny
<< op
->shift
)
8567 || val
> (maxtiny
<< op
->shift
))
8572 if (warn
&& ext
&& ! needext
)
8573 as_warn_where (file
, line
, _("extended operand requested but not required"));
8574 if (small
&& needext
)
8575 as_bad_where (file
, line
, _("invalid unextended operand value"));
8577 if (small
|| (! ext
&& ! needext
))
8581 *use_extend
= false;
8582 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8583 insnval
<<= op
->op_shift
;
8588 long minext
, maxext
;
8594 maxext
= (1 << op
->extbits
) - 1;
8598 minext
= - (1 << (op
->extbits
- 1));
8599 maxext
= (1 << (op
->extbits
- 1)) - 1;
8601 if (val
< minext
|| val
> maxext
)
8602 as_bad_where (file
, line
,
8603 _("operand value out of range for instruction"));
8606 if (op
->extbits
== 16)
8608 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8611 else if (op
->extbits
== 15)
8613 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8618 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8622 *extend
= (unsigned short) extval
;
8631 my_getSmallExpression (ep
, str
)
8642 ((str
[1] == 'h' && str
[2] == 'i')
8643 || (str
[1] == 'H' && str
[2] == 'I')
8644 || (str
[1] == 'l' && str
[2] == 'o'))
8656 * A small expression may be followed by a base register.
8657 * Scan to the end of this operand, and then back over a possible
8658 * base register. Then scan the small expression up to that
8659 * point. (Based on code in sparc.c...)
8661 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8663 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8665 if (isdigit ((unsigned char) sp
[-2]))
8667 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8669 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8675 else if (sp
- 5 >= str
8678 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8679 || (sp
[-3] == 's' && sp
[-2] == 'p')
8680 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8681 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8687 /* no expression means zero offset */
8690 /* %xx(reg) is an error */
8691 ep
->X_op
= O_absent
;
8696 ep
->X_op
= O_constant
;
8699 ep
->X_add_symbol
= NULL
;
8700 ep
->X_op_symbol
= NULL
;
8701 ep
->X_add_number
= 0;
8706 my_getExpression (ep
, str
);
8713 my_getExpression (ep
, str
);
8714 return c
; /* => %hi or %lo encountered */
8718 my_getExpression (ep
, str
)
8724 save_in
= input_line_pointer
;
8725 input_line_pointer
= str
;
8727 expr_end
= input_line_pointer
;
8728 input_line_pointer
= save_in
;
8730 /* If we are in mips16 mode, and this is an expression based on `.',
8731 then we bump the value of the symbol by 1 since that is how other
8732 text symbols are handled. We don't bother to handle complex
8733 expressions, just `.' plus or minus a constant. */
8734 if (mips_opts
.mips16
8735 && ep
->X_op
== O_symbol
8736 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8737 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8738 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8739 && symbol_constant_p (ep
->X_add_symbol
)
8740 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8741 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8744 /* Turn a string in input_line_pointer into a floating point constant
8745 of type type, and store the appropriate bytes in *litP. The number
8746 of LITTLENUMS emitted is stored in *sizeP . An error message is
8747 returned, or NULL on OK. */
8750 md_atof (type
, litP
, sizeP
)
8756 LITTLENUM_TYPE words
[4];
8772 return _("bad call to md_atof");
8775 t
= atof_ieee (input_line_pointer
, type
, words
);
8777 input_line_pointer
= t
;
8781 if (! target_big_endian
)
8783 for (i
= prec
- 1; i
>= 0; i
--)
8785 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8791 for (i
= 0; i
< prec
; i
++)
8793 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8802 md_number_to_chars (buf
, val
, n
)
8807 if (target_big_endian
)
8808 number_to_chars_bigendian (buf
, val
, n
);
8810 number_to_chars_littleendian (buf
, val
, n
);
8813 CONST
char *md_shortopts
= "O::g::G:";
8815 struct option md_longopts
[] = {
8816 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8817 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8818 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8819 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8820 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8821 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8822 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8823 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8824 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8825 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8826 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8827 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8828 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8829 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8830 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8831 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8832 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8833 {"break", no_argument
, NULL
, OPTION_BREAK
},
8834 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8835 #define OPTION_EB (OPTION_MD_BASE + 11)
8836 {"EB", no_argument
, NULL
, OPTION_EB
},
8837 #define OPTION_EL (OPTION_MD_BASE + 12)
8838 {"EL", no_argument
, NULL
, OPTION_EL
},
8839 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8840 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8841 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8842 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8843 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8844 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8845 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8846 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8847 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8848 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8849 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8850 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8851 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8852 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8853 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8854 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8855 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8856 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8857 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8858 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8861 #define OPTION_MABI (OPTION_MD_BASE + 38)
8862 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8864 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8865 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8866 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8867 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8869 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8870 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8871 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8872 #define OPTION_32 (OPTION_MD_BASE + 20)
8873 #define OPTION_64 (OPTION_MD_BASE + 21)
8875 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8876 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8877 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8878 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8879 {"32", no_argument
, NULL
, OPTION_32
},
8880 {"64", no_argument
, NULL
, OPTION_64
},
8883 #define OPTION_GP32 (OPTION_MD_BASE + 41)
8884 #define OPTION_GP64 (OPTION_MD_BASE + 42)
8885 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8886 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8888 {NULL
, no_argument
, NULL
, 0}
8890 size_t md_longopts_size
= sizeof(md_longopts
);
8893 md_parse_option (c
, arg
)
8908 target_big_endian
= 1;
8912 target_big_endian
= 0;
8916 if (arg
&& arg
[1] == '0')
8926 mips_debug
= atoi (arg
);
8927 /* When the MIPS assembler sees -g or -g2, it does not do
8928 optimizations which limit full symbolic debugging. We take
8929 that to be equivalent to -O0. */
8930 if (mips_debug
== 2)
8954 /* Identify the processor type */
8956 if (strcmp (p
, "default") == 0
8957 || strcmp (p
, "DEFAULT") == 0)
8963 /* We need to cope with the various "vr" prefixes for the 4300
8965 if (*p
== 'v' || *p
== 'V')
8971 if (*p
== 'r' || *p
== 'R')
8978 if (strcmp (p
, "10000") == 0
8979 || strcmp (p
, "10k") == 0
8980 || strcmp (p
, "10K") == 0)
8985 if (strcmp (p
, "2000") == 0
8986 || strcmp (p
, "2k") == 0
8987 || strcmp (p
, "2K") == 0)
8992 if (strcmp (p
, "3000") == 0
8993 || strcmp (p
, "3k") == 0
8994 || strcmp (p
, "3K") == 0)
8996 else if (strcmp (p
, "3900") == 0)
9001 if (strcmp (p
, "4000") == 0
9002 || strcmp (p
, "4k") == 0
9003 || strcmp (p
, "4K") == 0)
9005 else if (strcmp (p
, "4100") == 0)
9007 else if (strcmp (p
, "4111") == 0)
9009 else if (strcmp (p
, "4300") == 0)
9011 else if (strcmp (p
, "4400") == 0)
9013 else if (strcmp (p
, "4600") == 0)
9015 else if (strcmp (p
, "4650") == 0)
9017 else if (strcmp (p
, "4010") == 0)
9022 if (strcmp (p
, "5000") == 0
9023 || strcmp (p
, "5k") == 0
9024 || strcmp (p
, "5K") == 0)
9029 if (strcmp (p
, "6000") == 0
9030 || strcmp (p
, "6k") == 0
9031 || strcmp (p
, "6K") == 0)
9036 if (strcmp (p
, "8000") == 0
9037 || strcmp (p
, "8k") == 0
9038 || strcmp (p
, "8K") == 0)
9043 if (strcmp (p
, "orion") == 0)
9049 switch (atoi (p
+ 1))
9065 && (mips_cpu
!= 4300
9068 && mips_cpu
!= 5000))
9070 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9076 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9087 case OPTION_NO_M4650
:
9094 case OPTION_NO_M4010
:
9101 case OPTION_NO_M4100
:
9109 case OPTION_NO_M3900
:
9113 mips_opts
.mips16
= 1;
9114 mips_no_prev_insn (false);
9117 case OPTION_NO_MIPS16
:
9118 mips_opts
.mips16
= 0;
9119 mips_no_prev_insn (false);
9122 case OPTION_MEMBEDDED_PIC
:
9123 mips_pic
= EMBEDDED_PIC
;
9124 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9126 as_bad (_("-G may not be used with embedded PIC code"));
9129 g_switch_value
= 0x7fffffff;
9132 /* When generating ELF code, we permit -KPIC and -call_shared to
9133 select SVR4_PIC, and -non_shared to select no PIC. This is
9134 intended to be compatible with Irix 5. */
9135 case OPTION_CALL_SHARED
:
9136 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9138 as_bad (_("-call_shared is supported only for ELF format"));
9141 mips_pic
= SVR4_PIC
;
9142 if (g_switch_seen
&& g_switch_value
!= 0)
9144 as_bad (_("-G may not be used with SVR4 PIC code"));
9150 case OPTION_NON_SHARED
:
9151 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9153 as_bad (_("-non_shared is supported only for ELF format"));
9159 /* The -xgot option tells the assembler to use 32 offsets when
9160 accessing the got in SVR4_PIC mode. It is for Irix
9167 if (! USE_GLOBAL_POINTER_OPT
)
9169 as_bad (_("-G is not supported for this configuration"));
9172 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9174 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9178 g_switch_value
= atoi (arg
);
9182 /* The -32 and -64 options tell the assembler to output the 32
9183 bit or the 64 bit MIPS ELF format. */
9190 const char **list
, **l
;
9192 list
= bfd_target_list ();
9193 for (l
= list
; *l
!= NULL
; l
++)
9194 if (strcmp (*l
, "elf64-bigmips") == 0
9195 || strcmp (*l
, "elf64-littlemips") == 0)
9198 as_fatal (_("No compiled in support for 64 bit object file format"));
9208 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9209 flag in object files because to do so would make it
9210 impossible to link with libraries compiled without "-gp32".
9211 This is unnecessarily restrictive.
9213 We could solve this problem by adding "-gp32" multilibs to
9214 gcc, but to set this flag before gcc is built with such
9215 multilibs will break too many systems. */
9217 /* mips_32bitmode = 1; */
9223 /* mips_32bitmode = 0; */
9227 if (strcmp (arg
,"32") == 0
9228 || strcmp (arg
,"n32") == 0
9229 || strcmp (arg
,"64") == 0
9230 || strcmp (arg
,"o64") == 0
9231 || strcmp (arg
,"eabi") == 0)
9232 mips_abi_string
= arg
;
9235 case OPTION_M7000_HILO_FIX
:
9236 mips_7000_hilo_fix
= true;
9239 case OPTION_NO_M7000_HILO_FIX
:
9240 mips_7000_hilo_fix
= false;
9252 show (stream
, string
, col_p
, first_p
)
9260 fprintf (stream
, "%24s", "");
9265 fprintf (stream
, ", ");
9269 if (*col_p
+ strlen (string
) > 72)
9271 fprintf (stream
, "\n%24s", "");
9275 fprintf (stream
, "%s", string
);
9276 *col_p
+= strlen (string
);
9283 md_show_usage (stream
)
9288 fprintf(stream
, _("\
9290 -membedded-pic generate embedded position independent code\n\
9291 -EB generate big endian output\n\
9292 -EL generate little endian output\n\
9293 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9294 -G NUM allow referencing objects up to NUM bytes\n\
9295 implicitly with the gp register [default 8]\n"));
9296 fprintf(stream
, _("\
9297 -mips1 generate MIPS ISA I instructions\n\
9298 -mips2 generate MIPS ISA II instructions\n\
9299 -mips3 generate MIPS ISA III instructions\n\
9300 -mips4 generate MIPS ISA IV instructions\n\
9301 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9305 show (stream
, "2000", &column
, &first
);
9306 show (stream
, "3000", &column
, &first
);
9307 show (stream
, "3900", &column
, &first
);
9308 show (stream
, "4000", &column
, &first
);
9309 show (stream
, "4010", &column
, &first
);
9310 show (stream
, "4100", &column
, &first
);
9311 show (stream
, "4111", &column
, &first
);
9312 show (stream
, "4300", &column
, &first
);
9313 show (stream
, "4400", &column
, &first
);
9314 show (stream
, "4600", &column
, &first
);
9315 show (stream
, "4650", &column
, &first
);
9316 show (stream
, "5000", &column
, &first
);
9317 show (stream
, "6000", &column
, &first
);
9318 show (stream
, "8000", &column
, &first
);
9319 show (stream
, "10000", &column
, &first
);
9320 fputc ('\n', stream
);
9322 fprintf (stream
, _("\
9323 -mCPU equivalent to -mcpu=CPU.\n\
9324 -no-mCPU don't generate code specific to CPU.\n\
9325 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9329 show (stream
, "3900", &column
, &first
);
9330 show (stream
, "4010", &column
, &first
);
9331 show (stream
, "4100", &column
, &first
);
9332 show (stream
, "4650", &column
, &first
);
9333 fputc ('\n', stream
);
9335 fprintf(stream
, _("\
9336 -mips16 generate mips16 instructions\n\
9337 -no-mips16 do not generate mips16 instructions\n"));
9338 fprintf(stream
, _("\
9339 -O0 remove unneeded NOPs, do not swap branches\n\
9340 -O remove unneeded NOPs and swap branches\n\
9341 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9342 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9344 fprintf(stream
, _("\
9345 -KPIC, -call_shared generate SVR4 position independent code\n\
9346 -non_shared do not generate position independent code\n\
9347 -xgot assume a 32 bit GOT\n\
9348 -32 create 32 bit object file (default)\n\
9349 -64 create 64 bit object file\n"));
9354 mips_init_after_args ()
9356 /* initialize opcodes */
9357 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9358 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9362 md_pcrel_from (fixP
)
9365 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9366 && fixP
->fx_addsy
!= (symbolS
*) NULL
9367 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9369 /* This makes a branch to an undefined symbol be a branch to the
9370 current location. */
9374 /* return the address of the delay slot */
9375 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9378 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9379 reloc for a cons. We could use the definition there, except that
9380 we want to handle 64 bit relocs specially. */
9383 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9384 fragS
*frag ATTRIBUTE_UNUSED
;
9386 unsigned int nbytes
;
9390 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9392 if (nbytes
== 8 && ! mips_64
)
9394 if (target_big_endian
)
9400 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9401 as_bad (_("Unsupported reloc size %d"), nbytes
);
9403 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9406 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9409 /* This is called before the symbol table is processed. In order to
9410 work with gcc when using mips-tfile, we must keep all local labels.
9411 However, in other cases, we want to discard them. If we were
9412 called with -g, but we didn't see any debugging information, it may
9413 mean that gcc is smuggling debugging information through to
9414 mips-tfile, in which case we must generate all local labels. */
9417 mips_frob_file_before_adjust ()
9419 #ifndef NO_ECOFF_DEBUGGING
9422 && ! ecoff_debugging_seen
)
9423 flag_keep_locals
= 1;
9427 /* Sort any unmatched HI16_S relocs so that they immediately precede
9428 the corresponding LO reloc. This is called before md_apply_fix and
9429 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9430 explicit use of the %hi modifier. */
9435 struct mips_hi_fixup
*l
;
9437 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9439 segment_info_type
*seginfo
;
9442 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9444 /* Check quickly whether the next fixup happens to be a matching
9446 if (l
->fixp
->fx_next
!= NULL
9447 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9448 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9449 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9452 /* Look through the fixups for this segment for a matching %lo.
9453 When we find one, move the %hi just in front of it. We do
9454 this in two passes. In the first pass, we try to find a
9455 unique %lo. In the second pass, we permit multiple %hi
9456 relocs for a single %lo (this is a GNU extension). */
9457 seginfo
= seg_info (l
->seg
);
9458 for (pass
= 0; pass
< 2; pass
++)
9463 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9465 /* Check whether this is a %lo fixup which matches l->fixp. */
9466 if (f
->fx_r_type
== BFD_RELOC_LO16
9467 && f
->fx_addsy
== l
->fixp
->fx_addsy
9468 && f
->fx_offset
== l
->fixp
->fx_offset
9471 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9472 || prev
->fx_addsy
!= f
->fx_addsy
9473 || prev
->fx_offset
!= f
->fx_offset
))
9477 /* Move l->fixp before f. */
9478 for (pf
= &seginfo
->fix_root
;
9480 pf
= &(*pf
)->fx_next
)
9481 assert (*pf
!= NULL
);
9483 *pf
= l
->fixp
->fx_next
;
9485 l
->fixp
->fx_next
= f
;
9487 seginfo
->fix_root
= l
->fixp
;
9489 prev
->fx_next
= l
->fixp
;
9500 #if 0 /* GCC code motion plus incomplete dead code elimination
9501 can leave a %hi without a %lo. */
9503 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9504 _("Unmatched %%hi reloc"));
9510 /* When generating embedded PIC code we need to use a special
9511 relocation to represent the difference of two symbols in the .text
9512 section (switch tables use a difference of this sort). See
9513 include/coff/mips.h for details. This macro checks whether this
9514 fixup requires the special reloc. */
9515 #define SWITCH_TABLE(fixp) \
9516 ((fixp)->fx_r_type == BFD_RELOC_32 \
9517 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9518 && (fixp)->fx_addsy != NULL \
9519 && (fixp)->fx_subsy != NULL \
9520 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9521 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9523 /* When generating embedded PIC code we must keep all PC relative
9524 relocations, in case the linker has to relax a call. We also need
9525 to keep relocations for switch table entries. */
9529 mips_force_relocation (fixp
)
9532 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9533 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9536 return (mips_pic
== EMBEDDED_PIC
9538 || SWITCH_TABLE (fixp
)
9539 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9540 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9543 /* Apply a fixup to the object file. */
9546 md_apply_fix (fixP
, valueP
)
9553 assert (fixP
->fx_size
== 4
9554 || fixP
->fx_r_type
== BFD_RELOC_16
9555 || fixP
->fx_r_type
== BFD_RELOC_64
9556 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9557 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9561 /* If we aren't adjusting this fixup to be against the section
9562 symbol, we need to adjust the value. */
9564 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9566 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9567 || S_IS_WEAK (fixP
->fx_addsy
)
9568 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9569 && (((bfd_get_section_flags (stdoutput
,
9570 S_GET_SEGMENT (fixP
->fx_addsy
))
9571 & SEC_LINK_ONCE
) != 0)
9572 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9574 sizeof (".gnu.linkonce") - 1))))
9577 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9578 if (value
!= 0 && ! fixP
->fx_pcrel
)
9580 /* In this case, the bfd_install_relocation routine will
9581 incorrectly add the symbol value back in. We just want
9582 the addend to appear in the object file.
9583 FIXME: If this makes VALUE zero, we're toast. */
9584 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9588 /* This code was generated using trial and error and so is
9589 fragile and not trustworthy. If you change it, you should
9590 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9592 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9594 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9596 /* BFD's REL handling, for MIPS, is _very_ weird.
9597 This gives the right results, but it can't possibly
9598 be the way things are supposed to work. */
9599 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9600 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9601 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9606 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9608 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9611 switch (fixP
->fx_r_type
)
9613 case BFD_RELOC_MIPS_JMP
:
9614 case BFD_RELOC_HI16
:
9615 case BFD_RELOC_HI16_S
:
9616 case BFD_RELOC_MIPS_GPREL
:
9617 case BFD_RELOC_MIPS_LITERAL
:
9618 case BFD_RELOC_MIPS_CALL16
:
9619 case BFD_RELOC_MIPS_GOT16
:
9620 case BFD_RELOC_MIPS_GPREL32
:
9621 case BFD_RELOC_MIPS_GOT_HI16
:
9622 case BFD_RELOC_MIPS_GOT_LO16
:
9623 case BFD_RELOC_MIPS_CALL_HI16
:
9624 case BFD_RELOC_MIPS_CALL_LO16
:
9625 case BFD_RELOC_MIPS16_GPREL
:
9627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9628 _("Invalid PC relative reloc"));
9629 /* Nothing needed to do. The value comes from the reloc entry */
9632 case BFD_RELOC_MIPS16_JMP
:
9633 /* We currently always generate a reloc against a symbol, which
9634 means that we don't want an addend even if the symbol is
9636 fixP
->fx_addnumber
= 0;
9639 case BFD_RELOC_PCREL_HI16_S
:
9640 /* The addend for this is tricky if it is internal, so we just
9641 do everything here rather than in bfd_install_relocation. */
9642 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9647 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9649 /* For an external symbol adjust by the address to make it
9650 pcrel_offset. We use the address of the RELLO reloc
9651 which follows this one. */
9652 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9653 + fixP
->fx_next
->fx_where
);
9658 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9659 if (target_big_endian
)
9661 md_number_to_chars (buf
, value
, 2);
9664 case BFD_RELOC_PCREL_LO16
:
9665 /* The addend for this is tricky if it is internal, so we just
9666 do everything here rather than in bfd_install_relocation. */
9667 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9672 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9673 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9674 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9675 if (target_big_endian
)
9677 md_number_to_chars (buf
, value
, 2);
9681 /* This is handled like BFD_RELOC_32, but we output a sign
9682 extended value if we are only 32 bits. */
9684 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9686 if (8 <= sizeof (valueT
))
9687 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9694 w1
= w2
= fixP
->fx_where
;
9695 if (target_big_endian
)
9699 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9700 if ((value
& 0x80000000) != 0)
9704 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9711 /* If we are deleting this reloc entry, we must fill in the
9712 value now. This can happen if we have a .word which is not
9713 resolved when it appears but is later defined. We also need
9714 to fill in the value if this is an embedded PIC switch table
9717 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9718 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9723 /* If we are deleting this reloc entry, we must fill in the
9725 assert (fixP
->fx_size
== 2);
9727 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9731 case BFD_RELOC_LO16
:
9732 /* When handling an embedded PIC switch statement, we can wind
9733 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9736 if (value
< -0x8000 || value
> 0x7fff)
9737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9738 _("relocation overflow"));
9739 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9740 if (target_big_endian
)
9742 md_number_to_chars (buf
, value
, 2);
9746 case BFD_RELOC_16_PCREL_S2
:
9748 * We need to save the bits in the instruction since fixup_segment()
9749 * might be deleting the relocation entry (i.e., a branch within
9750 * the current segment).
9752 if ((value
& 0x3) != 0)
9753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9754 _("Branch to odd address (%lx)"), value
);
9756 if (!fixP
->fx_done
&& value
!= 0)
9758 /* If 'value' is zero, the remaining reloc code won't actually
9759 do the store, so it must be done here. This is probably
9762 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9766 /* update old instruction data */
9767 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9768 if (target_big_endian
)
9769 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9771 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9773 if (value
>= -0x8000 && value
< 0x8000)
9774 insn
|= value
& 0xffff;
9777 /* The branch offset is too large. If this is an
9778 unconditional branch, and we are not generating PIC code,
9779 we can convert it to an absolute jump instruction. */
9780 if (mips_pic
== NO_PIC
9782 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9783 && (fixP
->fx_frag
->fr_address
9784 < text_section
->vma
+ text_section
->_raw_size
)
9785 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9786 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9787 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9789 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9790 insn
= 0x0c000000; /* jal */
9792 insn
= 0x08000000; /* j */
9793 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9795 fixP
->fx_addsy
= section_symbol (text_section
);
9796 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9800 /* FIXME. It would be possible in principle to handle
9801 conditional branches which overflow. They could be
9802 transformed into a branch around a jump. This would
9803 require setting up variant frags for each different
9804 branch type. The native MIPS assembler attempts to
9805 handle these cases, but it appears to do it
9807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9808 _("Branch out of range"));
9812 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9815 case BFD_RELOC_VTABLE_INHERIT
:
9818 && !S_IS_DEFINED (fixP
->fx_addsy
)
9819 && !S_IS_WEAK (fixP
->fx_addsy
))
9820 S_SET_WEAK (fixP
->fx_addsy
);
9823 case BFD_RELOC_VTABLE_ENTRY
:
9839 const struct mips_opcode
*p
;
9840 int treg
, sreg
, dreg
, shamt
;
9845 for (i
= 0; i
< NUMOPCODES
; ++i
)
9847 p
= &mips_opcodes
[i
];
9848 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9850 printf ("%08lx %s\t", oc
, p
->name
);
9851 treg
= (oc
>> 16) & 0x1f;
9852 sreg
= (oc
>> 21) & 0x1f;
9853 dreg
= (oc
>> 11) & 0x1f;
9854 shamt
= (oc
>> 6) & 0x1f;
9856 for (args
= p
->args
;; ++args
)
9867 printf ("%c", *args
);
9871 assert (treg
== sreg
);
9872 printf ("$%d,$%d", treg
, sreg
);
9877 printf ("$%d", dreg
);
9882 printf ("$%d", treg
);
9886 printf ("0x%x", treg
);
9891 printf ("$%d", sreg
);
9895 printf ("0x%08lx", oc
& 0x1ffffff);
9907 printf ("$%d", shamt
);
9918 printf (_("%08lx UNDEFINED\n"), oc
);
9929 name
= input_line_pointer
;
9930 c
= get_symbol_end ();
9931 p
= (symbolS
*) symbol_find_or_make (name
);
9932 *input_line_pointer
= c
;
9936 /* Align the current frag to a given power of two. The MIPS assembler
9937 also automatically adjusts any preceding label. */
9940 mips_align (to
, fill
, label
)
9945 mips_emit_delays (false);
9946 frag_align (to
, fill
, 0);
9947 record_alignment (now_seg
, to
);
9950 assert (S_GET_SEGMENT (label
) == now_seg
);
9951 symbol_set_frag (label
, frag_now
);
9952 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9956 /* Align to a given power of two. .align 0 turns off the automatic
9957 alignment used by the data creating pseudo-ops. */
9961 int x ATTRIBUTE_UNUSED
;
9964 register long temp_fill
;
9965 long max_alignment
= 15;
9969 o Note that the assembler pulls down any immediately preceeding label
9970 to the aligned address.
9971 o It's not documented but auto alignment is reinstated by
9972 a .align pseudo instruction.
9973 o Note also that after auto alignment is turned off the mips assembler
9974 issues an error on attempt to assemble an improperly aligned data item.
9979 temp
= get_absolute_expression ();
9980 if (temp
> max_alignment
)
9981 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9984 as_warn (_("Alignment negative: 0 assumed."));
9987 if (*input_line_pointer
== ',')
9989 input_line_pointer
++;
9990 temp_fill
= get_absolute_expression ();
9997 mips_align (temp
, (int) temp_fill
,
9998 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10005 demand_empty_rest_of_line ();
10009 mips_flush_pending_output ()
10011 mips_emit_delays (false);
10012 mips_clear_insn_labels ();
10021 /* When generating embedded PIC code, we only use the .text, .lit8,
10022 .sdata and .sbss sections. We change the .data and .rdata
10023 pseudo-ops to use .sdata. */
10024 if (mips_pic
== EMBEDDED_PIC
10025 && (sec
== 'd' || sec
== 'r'))
10029 /* The ELF backend needs to know that we are changing sections, so
10030 that .previous works correctly. We could do something like check
10031 for a obj_section_change_hook macro, but that might be confusing
10032 as it would not be appropriate to use it in the section changing
10033 functions in read.c, since obj-elf.c intercepts those. FIXME:
10034 This should be cleaner, somehow. */
10035 obj_elf_section_change_hook ();
10038 mips_emit_delays (false);
10048 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10049 demand_empty_rest_of_line ();
10053 if (USE_GLOBAL_POINTER_OPT
)
10055 seg
= subseg_new (RDATA_SECTION_NAME
,
10056 (subsegT
) get_absolute_expression ());
10057 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10059 bfd_set_section_flags (stdoutput
, seg
,
10065 if (strcmp (TARGET_OS
, "elf") != 0)
10066 record_alignment (seg
, 4);
10068 demand_empty_rest_of_line ();
10072 as_bad (_("No read only data section in this object file format"));
10073 demand_empty_rest_of_line ();
10079 if (USE_GLOBAL_POINTER_OPT
)
10081 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10082 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10084 bfd_set_section_flags (stdoutput
, seg
,
10085 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10087 if (strcmp (TARGET_OS
, "elf") != 0)
10088 record_alignment (seg
, 4);
10090 demand_empty_rest_of_line ();
10095 as_bad (_("Global pointers not supported; recompile -G 0"));
10096 demand_empty_rest_of_line ();
10105 mips_enable_auto_align ()
10116 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10117 mips_emit_delays (false);
10118 if (log_size
> 0 && auto_align
)
10119 mips_align (log_size
, 0, label
);
10120 mips_clear_insn_labels ();
10121 cons (1 << log_size
);
10125 s_float_cons (type
)
10130 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10132 mips_emit_delays (false);
10137 mips_align (3, 0, label
);
10139 mips_align (2, 0, label
);
10142 mips_clear_insn_labels ();
10147 /* Handle .globl. We need to override it because on Irix 5 you are
10150 where foo is an undefined symbol, to mean that foo should be
10151 considered to be the address of a function. */
10155 int x ATTRIBUTE_UNUSED
;
10162 name
= input_line_pointer
;
10163 c
= get_symbol_end ();
10164 symbolP
= symbol_find_or_make (name
);
10165 *input_line_pointer
= c
;
10166 SKIP_WHITESPACE ();
10168 /* On Irix 5, every global symbol that is not explicitly labelled as
10169 being a function is apparently labelled as being an object. */
10172 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10177 secname
= input_line_pointer
;
10178 c
= get_symbol_end ();
10179 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10181 as_bad (_("%s: no such section"), secname
);
10182 *input_line_pointer
= c
;
10184 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10185 flag
= BSF_FUNCTION
;
10188 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10190 S_SET_EXTERNAL (symbolP
);
10191 demand_empty_rest_of_line ();
10196 int x ATTRIBUTE_UNUSED
;
10201 opt
= input_line_pointer
;
10202 c
= get_symbol_end ();
10206 /* FIXME: What does this mean? */
10208 else if (strncmp (opt
, "pic", 3) == 0)
10212 i
= atoi (opt
+ 3);
10216 mips_pic
= SVR4_PIC
;
10218 as_bad (_(".option pic%d not supported"), i
);
10220 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10222 if (g_switch_seen
&& g_switch_value
!= 0)
10223 as_warn (_("-G may not be used with SVR4 PIC code"));
10224 g_switch_value
= 0;
10225 bfd_set_gp_size (stdoutput
, 0);
10229 as_warn (_("Unrecognized option \"%s\""), opt
);
10231 *input_line_pointer
= c
;
10232 demand_empty_rest_of_line ();
10235 /* This structure is used to hold a stack of .set values. */
10237 struct mips_option_stack
10239 struct mips_option_stack
*next
;
10240 struct mips_set_options options
;
10243 static struct mips_option_stack
*mips_opts_stack
;
10245 /* Handle the .set pseudo-op. */
10249 int x ATTRIBUTE_UNUSED
;
10251 char *name
= input_line_pointer
, ch
;
10253 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10254 input_line_pointer
++;
10255 ch
= *input_line_pointer
;
10256 *input_line_pointer
= '\0';
10258 if (strcmp (name
, "reorder") == 0)
10260 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10262 /* If we still have pending nops, we can discard them. The
10263 usual nop handling will insert any that are still
10265 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10266 * (mips_opts
.mips16
? 2 : 4));
10267 prev_nop_frag
= NULL
;
10269 mips_opts
.noreorder
= 0;
10271 else if (strcmp (name
, "noreorder") == 0)
10273 mips_emit_delays (true);
10274 mips_opts
.noreorder
= 1;
10275 mips_any_noreorder
= 1;
10277 else if (strcmp (name
, "at") == 0)
10279 mips_opts
.noat
= 0;
10281 else if (strcmp (name
, "noat") == 0)
10283 mips_opts
.noat
= 1;
10285 else if (strcmp (name
, "macro") == 0)
10287 mips_opts
.warn_about_macros
= 0;
10289 else if (strcmp (name
, "nomacro") == 0)
10291 if (mips_opts
.noreorder
== 0)
10292 as_bad (_("`noreorder' must be set before `nomacro'"));
10293 mips_opts
.warn_about_macros
= 1;
10295 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10297 mips_opts
.nomove
= 0;
10299 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10301 mips_opts
.nomove
= 1;
10303 else if (strcmp (name
, "bopt") == 0)
10305 mips_opts
.nobopt
= 0;
10307 else if (strcmp (name
, "nobopt") == 0)
10309 mips_opts
.nobopt
= 1;
10311 else if (strcmp (name
, "mips16") == 0
10312 || strcmp (name
, "MIPS-16") == 0)
10313 mips_opts
.mips16
= 1;
10314 else if (strcmp (name
, "nomips16") == 0
10315 || strcmp (name
, "noMIPS-16") == 0)
10316 mips_opts
.mips16
= 0;
10317 else if (strncmp (name
, "mips", 4) == 0)
10321 /* Permit the user to change the ISA on the fly. Needless to
10322 say, misuse can cause serious problems. */
10323 isa
= atoi (name
+ 4);
10325 mips_opts
.isa
= file_mips_isa
;
10326 else if (isa
< 1 || isa
> 4)
10327 as_bad (_("unknown ISA level"));
10329 mips_opts
.isa
= isa
;
10331 else if (strcmp (name
, "autoextend") == 0)
10332 mips_opts
.noautoextend
= 0;
10333 else if (strcmp (name
, "noautoextend") == 0)
10334 mips_opts
.noautoextend
= 1;
10335 else if (strcmp (name
, "push") == 0)
10337 struct mips_option_stack
*s
;
10339 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10340 s
->next
= mips_opts_stack
;
10341 s
->options
= mips_opts
;
10342 mips_opts_stack
= s
;
10344 else if (strcmp (name
, "pop") == 0)
10346 struct mips_option_stack
*s
;
10348 s
= mips_opts_stack
;
10350 as_bad (_(".set pop with no .set push"));
10353 /* If we're changing the reorder mode we need to handle
10354 delay slots correctly. */
10355 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10356 mips_emit_delays (true);
10357 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10359 if (prev_nop_frag
!= NULL
)
10361 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10362 * (mips_opts
.mips16
? 2 : 4));
10363 prev_nop_frag
= NULL
;
10367 mips_opts
= s
->options
;
10368 mips_opts_stack
= s
->next
;
10374 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10376 *input_line_pointer
= ch
;
10377 demand_empty_rest_of_line ();
10380 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10381 .option pic2. It means to generate SVR4 PIC calls. */
10384 s_abicalls (ignore
)
10385 int ignore ATTRIBUTE_UNUSED
;
10387 mips_pic
= SVR4_PIC
;
10388 if (USE_GLOBAL_POINTER_OPT
)
10390 if (g_switch_seen
&& g_switch_value
!= 0)
10391 as_warn (_("-G may not be used with SVR4 PIC code"));
10392 g_switch_value
= 0;
10394 bfd_set_gp_size (stdoutput
, 0);
10395 demand_empty_rest_of_line ();
10398 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10399 PIC code. It sets the $gp register for the function based on the
10400 function address, which is in the register named in the argument.
10401 This uses a relocation against _gp_disp, which is handled specially
10402 by the linker. The result is:
10403 lui $gp,%hi(_gp_disp)
10404 addiu $gp,$gp,%lo(_gp_disp)
10405 addu $gp,$gp,.cpload argument
10406 The .cpload argument is normally $25 == $t9. */
10410 int ignore ATTRIBUTE_UNUSED
;
10415 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10416 if (mips_pic
!= SVR4_PIC
)
10422 /* .cpload should be a in .set noreorder section. */
10423 if (mips_opts
.noreorder
== 0)
10424 as_warn (_(".cpload not in noreorder section"));
10426 ex
.X_op
= O_symbol
;
10427 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10428 ex
.X_op_symbol
= NULL
;
10429 ex
.X_add_number
= 0;
10431 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10432 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10434 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10435 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10436 (int) BFD_RELOC_LO16
);
10438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10439 GP
, GP
, tc_get_register (0));
10441 demand_empty_rest_of_line ();
10444 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10445 offset from $sp. The offset is remembered, and after making a PIC
10446 call $gp is restored from that location. */
10449 s_cprestore (ignore
)
10450 int ignore ATTRIBUTE_UNUSED
;
10455 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10456 if (mips_pic
!= SVR4_PIC
)
10462 mips_cprestore_offset
= get_absolute_expression ();
10464 ex
.X_op
= O_constant
;
10465 ex
.X_add_symbol
= NULL
;
10466 ex
.X_op_symbol
= NULL
;
10467 ex
.X_add_number
= mips_cprestore_offset
;
10469 macro_build ((char *) NULL
, &icnt
, &ex
,
10470 ((bfd_arch_bits_per_address (stdoutput
) == 32
10471 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10473 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10475 demand_empty_rest_of_line ();
10478 /* Handle the .gpword pseudo-op. This is used when generating PIC
10479 code. It generates a 32 bit GP relative reloc. */
10483 int ignore ATTRIBUTE_UNUSED
;
10489 /* When not generating PIC code, this is treated as .word. */
10490 if (mips_pic
!= SVR4_PIC
)
10496 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10497 mips_emit_delays (true);
10499 mips_align (2, 0, label
);
10500 mips_clear_insn_labels ();
10504 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10506 as_bad (_("Unsupported use of .gpword"));
10507 ignore_rest_of_line ();
10511 md_number_to_chars (p
, (valueT
) 0, 4);
10512 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10513 BFD_RELOC_MIPS_GPREL32
);
10515 demand_empty_rest_of_line ();
10518 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10519 tables in SVR4 PIC code. */
10523 int ignore ATTRIBUTE_UNUSED
;
10528 /* This is ignored when not generating SVR4 PIC code. */
10529 if (mips_pic
!= SVR4_PIC
)
10535 /* Add $gp to the register named as an argument. */
10536 reg
= tc_get_register (0);
10537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10538 ((bfd_arch_bits_per_address (stdoutput
) == 32
10539 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10540 ? "addu" : "daddu"),
10541 "d,v,t", reg
, reg
, GP
);
10543 demand_empty_rest_of_line ();
10546 /* Handle the .insn pseudo-op. This marks instruction labels in
10547 mips16 mode. This permits the linker to handle them specially,
10548 such as generating jalx instructions when needed. We also make
10549 them odd for the duration of the assembly, in order to generate the
10550 right sort of code. We will make them even in the adjust_symtab
10551 routine, while leaving them marked. This is convenient for the
10552 debugger and the disassembler. The linker knows to make them odd
10557 int ignore ATTRIBUTE_UNUSED
;
10559 if (mips_opts
.mips16
)
10560 mips16_mark_labels ();
10562 demand_empty_rest_of_line ();
10565 /* Handle a .stabn directive. We need these in order to mark a label
10566 as being a mips16 text label correctly. Sometimes the compiler
10567 will emit a label, followed by a .stabn, and then switch sections.
10568 If the label and .stabn are in mips16 mode, then the label is
10569 really a mips16 text label. */
10575 if (type
== 'n' && mips_opts
.mips16
)
10576 mips16_mark_labels ();
10581 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10585 s_mips_weakext (ignore
)
10586 int ignore ATTRIBUTE_UNUSED
;
10593 name
= input_line_pointer
;
10594 c
= get_symbol_end ();
10595 symbolP
= symbol_find_or_make (name
);
10596 S_SET_WEAK (symbolP
);
10597 *input_line_pointer
= c
;
10599 SKIP_WHITESPACE ();
10601 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10603 if (S_IS_DEFINED (symbolP
))
10605 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10606 S_GET_NAME (symbolP
));
10607 ignore_rest_of_line ();
10611 if (*input_line_pointer
== ',')
10613 ++input_line_pointer
;
10614 SKIP_WHITESPACE ();
10618 if (exp
.X_op
!= O_symbol
)
10620 as_bad ("bad .weakext directive");
10621 ignore_rest_of_line();
10624 symbol_set_value_expression (symbolP
, &exp
);
10627 demand_empty_rest_of_line ();
10630 /* Parse a register string into a number. Called from the ECOFF code
10631 to parse .frame. The argument is non-zero if this is the frame
10632 register, so that we can record it in mips_frame_reg. */
10635 tc_get_register (frame
)
10640 SKIP_WHITESPACE ();
10641 if (*input_line_pointer
++ != '$')
10643 as_warn (_("expected `$'"));
10646 else if (isdigit ((unsigned char) *input_line_pointer
))
10648 reg
= get_absolute_expression ();
10649 if (reg
< 0 || reg
>= 32)
10651 as_warn (_("Bad register number"));
10657 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10659 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10661 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10663 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10667 as_warn (_("Unrecognized register name"));
10670 input_line_pointer
+= 2;
10673 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10678 md_section_align (seg
, addr
)
10682 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10685 /* We don't need to align ELF sections to the full alignment.
10686 However, Irix 5 may prefer that we align them at least to a 16
10687 byte boundary. We don't bother to align the sections if we are
10688 targeted for an embedded system. */
10689 if (strcmp (TARGET_OS
, "elf") == 0)
10695 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10698 /* Utility routine, called from above as well. If called while the
10699 input file is still being read, it's only an approximation. (For
10700 example, a symbol may later become defined which appeared to be
10701 undefined earlier.) */
10704 nopic_need_relax (sym
, before_relaxing
)
10706 int before_relaxing
;
10711 if (USE_GLOBAL_POINTER_OPT
)
10713 const char *symname
;
10716 /* Find out whether this symbol can be referenced off the GP
10717 register. It can be if it is smaller than the -G size or if
10718 it is in the .sdata or .sbss section. Certain symbols can
10719 not be referenced off the GP, although it appears as though
10721 symname
= S_GET_NAME (sym
);
10722 if (symname
!= (const char *) NULL
10723 && (strcmp (symname
, "eprol") == 0
10724 || strcmp (symname
, "etext") == 0
10725 || strcmp (symname
, "_gp") == 0
10726 || strcmp (symname
, "edata") == 0
10727 || strcmp (symname
, "_fbss") == 0
10728 || strcmp (symname
, "_fdata") == 0
10729 || strcmp (symname
, "_ftext") == 0
10730 || strcmp (symname
, "end") == 0
10731 || strcmp (symname
, "_gp_disp") == 0))
10733 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10735 #ifndef NO_ECOFF_DEBUGGING
10736 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10737 && (symbol_get_obj (sym
)->ecoff_extern_size
10738 <= g_switch_value
))
10740 /* We must defer this decision until after the whole
10741 file has been read, since there might be a .extern
10742 after the first use of this symbol. */
10743 || (before_relaxing
10744 #ifndef NO_ECOFF_DEBUGGING
10745 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10747 && S_GET_VALUE (sym
) == 0)
10748 || (S_GET_VALUE (sym
) != 0
10749 && S_GET_VALUE (sym
) <= g_switch_value
)))
10753 const char *segname
;
10755 segname
= segment_name (S_GET_SEGMENT (sym
));
10756 assert (strcmp (segname
, ".lit8") != 0
10757 && strcmp (segname
, ".lit4") != 0);
10758 change
= (strcmp (segname
, ".sdata") != 0
10759 && strcmp (segname
, ".sbss") != 0
10760 && strncmp (segname
, ".sdata.", 7) != 0
10761 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10766 /* We are not optimizing for the GP register. */
10770 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10771 extended opcode. SEC is the section the frag is in. */
10774 mips16_extended_frag (fragp
, sec
, stretch
)
10780 register const struct mips16_immed_operand
*op
;
10782 int mintiny
, maxtiny
;
10785 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10787 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10790 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10791 op
= mips16_immed_operands
;
10792 while (op
->type
!= type
)
10795 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10800 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10803 maxtiny
= 1 << op
->nbits
;
10808 maxtiny
= (1 << op
->nbits
) - 1;
10813 mintiny
= - (1 << (op
->nbits
- 1));
10814 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10817 /* We can't always call S_GET_VALUE here, because we don't want to
10818 lock in a particular frag address. */
10819 if (symbol_constant_p (fragp
->fr_symbol
))
10821 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10822 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10823 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10825 else if (symbol_equated_p (fragp
->fr_symbol
)
10826 && (symbol_constant_p
10827 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10831 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10832 val
= (S_GET_VALUE (eqsym
)
10833 + symbol_get_frag (eqsym
)->fr_address
10834 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10835 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10836 symsec
= S_GET_SEGMENT (eqsym
);
10845 /* We won't have the section when we are called from
10846 mips_relax_frag. However, we will always have been called
10847 from md_estimate_size_before_relax first. If this is a
10848 branch to a different section, we mark it as such. If SEC is
10849 NULL, and the frag is not marked, then it must be a branch to
10850 the same section. */
10853 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10860 fragp
->fr_subtype
=
10861 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10863 /* FIXME: We should support this, and let the linker
10864 catch branches and loads that are out of range. */
10865 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10866 _("unsupported PC relative reference to different section"));
10872 /* In this case, we know for sure that the symbol fragment is in
10873 the same section. If the fr_address of the symbol fragment
10874 is greater then the address of this fragment we want to add
10875 in STRETCH in order to get a better estimate of the address.
10876 This particularly matters because of the shift bits. */
10878 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10879 >= fragp
->fr_address
))
10883 /* Adjust stretch for any alignment frag. Note that if have
10884 been expanding the earlier code, the symbol may be
10885 defined in what appears to be an earlier frag. FIXME:
10886 This doesn't handle the fr_subtype field, which specifies
10887 a maximum number of bytes to skip when doing an
10890 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10893 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10896 stretch
= - ((- stretch
)
10897 & ~ ((1 << (int) f
->fr_offset
) - 1));
10899 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10908 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10910 /* The base address rules are complicated. The base address of
10911 a branch is the following instruction. The base address of a
10912 PC relative load or add is the instruction itself, but if it
10913 is in a delay slot (in which case it can not be extended) use
10914 the address of the instruction whose delay slot it is in. */
10915 if (type
== 'p' || type
== 'q')
10919 /* If we are currently assuming that this frag should be
10920 extended, then, the current address is two bytes
10922 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10925 /* Ignore the low bit in the target, since it will be set
10926 for a text label. */
10927 if ((val
& 1) != 0)
10930 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10932 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10935 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10937 /* Branch offsets have an implicit 0 in the lowest bit. */
10938 if (type
== 'p' || type
== 'q')
10941 /* If any of the shifted bits are set, we must use an extended
10942 opcode. If the address depends on the size of this
10943 instruction, this can lead to a loop, so we arrange to always
10944 use an extended opcode. We only check this when we are in
10945 the main relaxation loop, when SEC is NULL. */
10946 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10948 fragp
->fr_subtype
=
10949 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10953 /* If we are about to mark a frag as extended because the value
10954 is precisely maxtiny + 1, then there is a chance of an
10955 infinite loop as in the following code:
10960 In this case when the la is extended, foo is 0x3fc bytes
10961 away, so the la can be shrunk, but then foo is 0x400 away, so
10962 the la must be extended. To avoid this loop, we mark the
10963 frag as extended if it was small, and is about to become
10964 extended with a value of maxtiny + 1. */
10965 if (val
== ((maxtiny
+ 1) << op
->shift
)
10966 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10969 fragp
->fr_subtype
=
10970 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10974 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10975 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10977 if ((val
& ((1 << op
->shift
) - 1)) != 0
10978 || val
< (mintiny
<< op
->shift
)
10979 || val
> (maxtiny
<< op
->shift
))
10985 /* Estimate the size of a frag before relaxing. Unless this is the
10986 mips16, we are not really relaxing here, and the final size is
10987 encoded in the subtype information. For the mips16, we have to
10988 decide whether we are using an extended opcode or not. */
10992 md_estimate_size_before_relax (fragp
, segtype
)
10997 boolean linkonce
= false;
10999 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11001 if (mips16_extended_frag (fragp
, segtype
, 0))
11003 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11008 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11013 if (mips_pic
== NO_PIC
)
11015 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11017 else if (mips_pic
== SVR4_PIC
)
11022 sym
= fragp
->fr_symbol
;
11024 /* Handle the case of a symbol equated to another symbol. */
11025 while (symbol_equated_p (sym
)
11026 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11030 /* It's possible to get a loop here in a badly written
11032 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11038 symsec
= S_GET_SEGMENT (sym
);
11040 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11041 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11043 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11047 /* The GNU toolchain uses an extension for ELF: a section
11048 beginning with the magic string .gnu.linkonce is a linkonce
11050 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11051 sizeof ".gnu.linkonce" - 1) == 0)
11055 /* This must duplicate the test in adjust_reloc_syms. */
11056 change
= (symsec
!= &bfd_und_section
11057 && symsec
!= &bfd_abs_section
11058 && ! bfd_is_com_section (symsec
)
11061 /* A weak symbol is treated as external. */
11062 && ! S_IS_WEAK (sym
)
11071 /* Record the offset to the first reloc in the fr_opcode field.
11072 This lets md_convert_frag and tc_gen_reloc know that the code
11073 must be expanded. */
11074 fragp
->fr_opcode
= (fragp
->fr_literal
11076 - RELAX_OLD (fragp
->fr_subtype
)
11077 + RELAX_RELOC1 (fragp
->fr_subtype
));
11078 /* FIXME: This really needs as_warn_where. */
11079 if (RELAX_WARN (fragp
->fr_subtype
))
11080 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11086 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11089 /* This is called to see whether a reloc against a defined symbol
11090 should be converted into a reloc against a section. Don't adjust
11091 MIPS16 jump relocations, so we don't have to worry about the format
11092 of the offset in the .o file. Don't adjust relocations against
11093 mips16 symbols, so that the linker can find them if it needs to set
11097 mips_fix_adjustable (fixp
)
11100 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11102 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11103 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11105 if (fixp
->fx_addsy
== NULL
)
11108 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11109 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11110 && fixp
->fx_subsy
== NULL
)
11116 /* Translate internal representation of relocation info to BFD target
11120 tc_gen_reloc (section
, fixp
)
11121 asection
*section ATTRIBUTE_UNUSED
;
11124 static arelent
*retval
[4];
11126 bfd_reloc_code_real_type code
;
11128 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11131 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11132 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11133 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11135 if (mips_pic
== EMBEDDED_PIC
11136 && SWITCH_TABLE (fixp
))
11138 /* For a switch table entry we use a special reloc. The addend
11139 is actually the difference between the reloc address and the
11141 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11142 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11143 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11144 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11146 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11147 reloc
->addend
= fixp
->fx_addnumber
;
11148 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11150 /* We use a special addend for an internal RELLO reloc. */
11151 if (symbol_section_p (fixp
->fx_addsy
))
11152 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11154 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11156 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11158 assert (fixp
->fx_next
!= NULL
11159 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11160 /* We use a special addend for an internal RELHI reloc. The
11161 reloc is relative to the RELLO; adjust the addend
11163 if (symbol_section_p (fixp
->fx_addsy
))
11164 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11165 + fixp
->fx_next
->fx_where
11166 - S_GET_VALUE (fixp
->fx_subsy
));
11168 reloc
->addend
= (fixp
->fx_addnumber
11169 + fixp
->fx_next
->fx_frag
->fr_address
11170 + fixp
->fx_next
->fx_where
);
11174 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11175 /* A gruesome hack which is a result of the gruesome gas reloc
11177 reloc
->addend
= reloc
->address
;
11179 reloc
->addend
= -reloc
->address
;
11182 /* If this is a variant frag, we may need to adjust the existing
11183 reloc and generate a new one. */
11184 if (fixp
->fx_frag
->fr_opcode
!= NULL
11185 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11186 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11187 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11188 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11189 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11190 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11191 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11195 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11197 /* If this is not the last reloc in this frag, then we have two
11198 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11199 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11200 the second one handle all of them. */
11201 if (fixp
->fx_next
!= NULL
11202 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11204 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11205 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11206 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11207 && (fixp
->fx_next
->fx_r_type
11208 == BFD_RELOC_MIPS_GOT_LO16
))
11209 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11210 && (fixp
->fx_next
->fx_r_type
11211 == BFD_RELOC_MIPS_CALL_LO16
)));
11216 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11217 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11218 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11220 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11221 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11222 reloc2
->address
= (reloc
->address
11223 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11224 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11225 reloc2
->addend
= fixp
->fx_addnumber
;
11226 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11227 assert (reloc2
->howto
!= NULL
);
11229 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11233 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11236 reloc3
->address
+= 4;
11239 if (mips_pic
== NO_PIC
)
11241 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11242 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11244 else if (mips_pic
== SVR4_PIC
)
11246 switch (fixp
->fx_r_type
)
11250 case BFD_RELOC_MIPS_GOT16
:
11252 case BFD_RELOC_MIPS_CALL16
:
11253 case BFD_RELOC_MIPS_GOT_LO16
:
11254 case BFD_RELOC_MIPS_CALL_LO16
:
11255 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11263 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11264 to be used in the relocation's section offset. */
11265 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11267 reloc
->address
= reloc
->addend
;
11271 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11272 fixup_segment converted a non-PC relative reloc into a PC
11273 relative reloc. In such a case, we need to convert the reloc
11275 code
= fixp
->fx_r_type
;
11276 if (fixp
->fx_pcrel
)
11281 code
= BFD_RELOC_8_PCREL
;
11284 code
= BFD_RELOC_16_PCREL
;
11287 code
= BFD_RELOC_32_PCREL
;
11290 code
= BFD_RELOC_64_PCREL
;
11292 case BFD_RELOC_8_PCREL
:
11293 case BFD_RELOC_16_PCREL
:
11294 case BFD_RELOC_32_PCREL
:
11295 case BFD_RELOC_64_PCREL
:
11296 case BFD_RELOC_16_PCREL_S2
:
11297 case BFD_RELOC_PCREL_HI16_S
:
11298 case BFD_RELOC_PCREL_LO16
:
11301 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11302 _("Cannot make %s relocation PC relative"),
11303 bfd_get_reloc_code_name (code
));
11307 /* To support a PC relative reloc when generating embedded PIC code
11308 for ECOFF, we use a Cygnus extension. We check for that here to
11309 make sure that we don't let such a reloc escape normally. */
11310 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11311 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11312 && code
== BFD_RELOC_16_PCREL_S2
11313 && mips_pic
!= EMBEDDED_PIC
)
11314 reloc
->howto
= NULL
;
11316 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11318 if (reloc
->howto
== NULL
)
11320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11321 _("Can not represent %s relocation in this object file format"),
11322 bfd_get_reloc_code_name (code
));
11329 /* Relax a machine dependent frag. This returns the amount by which
11330 the current size of the frag should change. */
11333 mips_relax_frag (fragp
, stretch
)
11337 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11340 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11342 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11344 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11349 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11351 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11358 /* Convert a machine dependent frag. */
11361 md_convert_frag (abfd
, asec
, fragp
)
11362 bfd
*abfd ATTRIBUTE_UNUSED
;
11369 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11372 register const struct mips16_immed_operand
*op
;
11373 boolean small
, ext
;
11376 unsigned long insn
;
11377 boolean use_extend
;
11378 unsigned short extend
;
11380 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11381 op
= mips16_immed_operands
;
11382 while (op
->type
!= type
)
11385 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11396 resolve_symbol_value (fragp
->fr_symbol
, 1);
11397 val
= S_GET_VALUE (fragp
->fr_symbol
);
11402 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11404 /* The rules for the base address of a PC relative reloc are
11405 complicated; see mips16_extended_frag. */
11406 if (type
== 'p' || type
== 'q')
11411 /* Ignore the low bit in the target, since it will be
11412 set for a text label. */
11413 if ((val
& 1) != 0)
11416 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11418 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11421 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11424 /* Make sure the section winds up with the alignment we have
11427 record_alignment (asec
, op
->shift
);
11431 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11432 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11433 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11434 _("extended instruction in delay slot"));
11436 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11438 if (target_big_endian
)
11439 insn
= bfd_getb16 (buf
);
11441 insn
= bfd_getl16 (buf
);
11443 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11444 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11445 small
, ext
, &insn
, &use_extend
, &extend
);
11449 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11450 fragp
->fr_fix
+= 2;
11454 md_number_to_chars (buf
, insn
, 2);
11455 fragp
->fr_fix
+= 2;
11460 if (fragp
->fr_opcode
== NULL
)
11463 old
= RELAX_OLD (fragp
->fr_subtype
);
11464 new = RELAX_NEW (fragp
->fr_subtype
);
11465 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11468 memcpy (fixptr
- old
, fixptr
, new);
11470 fragp
->fr_fix
+= new - old
;
11476 /* This function is called after the relocs have been generated.
11477 We've been storing mips16 text labels as odd. Here we convert them
11478 back to even for the convenience of the debugger. */
11481 mips_frob_file_after_relocs ()
11484 unsigned int count
, i
;
11486 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11489 syms
= bfd_get_outsymbols (stdoutput
);
11490 count
= bfd_get_symcount (stdoutput
);
11491 for (i
= 0; i
< count
; i
++, syms
++)
11493 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11494 && ((*syms
)->value
& 1) != 0)
11496 (*syms
)->value
&= ~1;
11497 /* If the symbol has an odd size, it was probably computed
11498 incorrectly, so adjust that as well. */
11499 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11500 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11507 /* This function is called whenever a label is defined. It is used
11508 when handling branch delays; if a branch has a label, we assume we
11509 can not move it. */
11512 mips_define_label (sym
)
11515 struct insn_label_list
*l
;
11517 if (free_insn_labels
== NULL
)
11518 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11521 l
= free_insn_labels
;
11522 free_insn_labels
= l
->next
;
11526 l
->next
= insn_labels
;
11530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11532 /* Some special processing for a MIPS ELF file. */
11535 mips_elf_final_processing ()
11537 /* Write out the register information. */
11542 s
.ri_gprmask
= mips_gprmask
;
11543 s
.ri_cprmask
[0] = mips_cprmask
[0];
11544 s
.ri_cprmask
[1] = mips_cprmask
[1];
11545 s
.ri_cprmask
[2] = mips_cprmask
[2];
11546 s
.ri_cprmask
[3] = mips_cprmask
[3];
11547 /* The gp_value field is set by the MIPS ELF backend. */
11549 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11550 ((Elf32_External_RegInfo
*)
11551 mips_regmask_frag
));
11555 Elf64_Internal_RegInfo s
;
11557 s
.ri_gprmask
= mips_gprmask
;
11559 s
.ri_cprmask
[0] = mips_cprmask
[0];
11560 s
.ri_cprmask
[1] = mips_cprmask
[1];
11561 s
.ri_cprmask
[2] = mips_cprmask
[2];
11562 s
.ri_cprmask
[3] = mips_cprmask
[3];
11563 /* The gp_value field is set by the MIPS ELF backend. */
11565 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11566 ((Elf64_External_RegInfo
*)
11567 mips_regmask_frag
));
11570 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11571 sort of BFD interface for this. */
11572 if (mips_any_noreorder
)
11573 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11574 if (mips_pic
!= NO_PIC
)
11575 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11577 /* Set the MIPS ELF ABI flags. */
11578 if (mips_abi_string
== 0)
11580 else if (strcmp (mips_abi_string
,"32") == 0)
11581 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11582 else if (strcmp (mips_abi_string
,"o64") == 0)
11583 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11584 else if (strcmp (mips_abi_string
,"eabi") == 0)
11587 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11589 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11592 if (mips_32bitmode
)
11593 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11596 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11598 typedef struct proc
11601 unsigned long reg_mask
;
11602 unsigned long reg_offset
;
11603 unsigned long fpreg_mask
;
11604 unsigned long fpreg_offset
;
11605 unsigned long frame_offset
;
11606 unsigned long frame_reg
;
11607 unsigned long pc_reg
;
11611 static procS cur_proc
;
11612 static procS
*cur_proc_ptr
;
11613 static int numprocs
;
11615 /* When we align code in the .text section of mips16, use the correct two
11616 byte nop pattern of 0x6500 (move $0,$0) */
11619 mips_do_align (n
, fill
, len
, max
)
11622 int len ATTRIBUTE_UNUSED
;
11626 && subseg_text_p (now_seg
)
11628 && mips_opts
.mips16
)
11630 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11631 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11633 frag_align (1, 0, 0);
11635 if (target_big_endian
)
11636 frag_align_pattern (n
, be_nop
, 2, max
);
11638 frag_align_pattern (n
, le_nop
, 2, max
);
11653 /* check for premature end, nesting errors, etc */
11655 as_warn (_("missing `.end' at end of assembly"));
11664 if (*input_line_pointer
== '-')
11666 ++input_line_pointer
;
11669 if (!isdigit ((unsigned char) *input_line_pointer
))
11670 as_bad (_("Expected simple number."));
11671 if (input_line_pointer
[0] == '0')
11673 if (input_line_pointer
[1] == 'x')
11675 input_line_pointer
+= 2;
11676 while (isxdigit ((unsigned char) *input_line_pointer
))
11679 val
|= hex_value (*input_line_pointer
++);
11681 return negative
? -val
: val
;
11685 ++input_line_pointer
;
11686 while (isdigit ((unsigned char) *input_line_pointer
))
11689 val
|= *input_line_pointer
++ - '0';
11691 return negative
? -val
: val
;
11694 if (!isdigit ((unsigned char) *input_line_pointer
))
11696 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11697 *input_line_pointer
, *input_line_pointer
);
11698 as_warn (_("Invalid number"));
11701 while (isdigit ((unsigned char) *input_line_pointer
))
11704 val
+= *input_line_pointer
++ - '0';
11706 return negative
? -val
: val
;
11709 /* The .file directive; just like the usual .file directive, but there
11710 is an initial number which is the ECOFF file index. */
11714 int x ATTRIBUTE_UNUSED
;
11718 line
= get_number ();
11723 /* The .end directive. */
11727 int x ATTRIBUTE_UNUSED
;
11732 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11735 demand_empty_rest_of_line ();
11740 #ifdef BFD_ASSEMBLER
11741 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11746 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11753 as_warn (_(".end not in text section"));
11757 as_warn (_(".end directive without a preceding .ent directive."));
11758 demand_empty_rest_of_line ();
11764 assert (S_GET_NAME (p
));
11765 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11766 as_warn (_(".end symbol does not match .ent symbol."));
11769 as_warn (_(".end directive missing or unknown symbol"));
11771 #ifdef MIPS_STABS_ELF
11773 segT saved_seg
= now_seg
;
11774 subsegT saved_subseg
= now_subseg
;
11775 fragS
*saved_frag
= frag_now
;
11781 dot
= frag_now_fix ();
11783 #ifdef md_flush_pending_output
11784 md_flush_pending_output ();
11788 subseg_set (pdr_seg
, 0);
11790 /* Write the symbol */
11791 exp
.X_op
= O_symbol
;
11792 exp
.X_add_symbol
= p
;
11793 exp
.X_add_number
= 0;
11794 emit_expr (&exp
, 4);
11796 fragp
= frag_more (7*4);
11798 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11799 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11800 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11801 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11802 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11803 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11804 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11806 subseg_set (saved_seg
, saved_subseg
);
11810 cur_proc_ptr
= NULL
;
11813 /* The .aent and .ent directives. */
11823 symbolP
= get_symbol ();
11824 if (*input_line_pointer
== ',')
11825 input_line_pointer
++;
11826 SKIP_WHITESPACE ();
11827 if (isdigit ((unsigned char) *input_line_pointer
)
11828 || *input_line_pointer
== '-')
11829 number
= get_number ();
11831 #ifdef BFD_ASSEMBLER
11832 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11837 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11844 as_warn (_(".ent or .aent not in text section."));
11846 if (!aent
&& cur_proc_ptr
)
11847 as_warn (_("missing `.end'"));
11851 cur_proc_ptr
= &cur_proc
;
11852 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11854 cur_proc_ptr
->isym
= symbolP
;
11856 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11861 demand_empty_rest_of_line ();
11864 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11865 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11866 s_mips_frame is used so that we can set the PDR information correctly.
11867 We can't use the ecoff routines because they make reference to the ecoff
11868 symbol table (in the mdebug section). */
11871 s_mips_frame (ignore
)
11874 #ifdef MIPS_STABS_ELF
11878 if (cur_proc_ptr
== (procS
*) NULL
)
11880 as_warn (_(".frame outside of .ent"));
11881 demand_empty_rest_of_line ();
11885 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11887 SKIP_WHITESPACE ();
11888 if (*input_line_pointer
++ != ','
11889 || get_absolute_expression_and_terminator (&val
) != ',')
11891 as_warn (_("Bad .frame directive"));
11892 --input_line_pointer
;
11893 demand_empty_rest_of_line ();
11897 cur_proc_ptr
->frame_offset
= val
;
11898 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11900 demand_empty_rest_of_line ();
11903 #endif /* MIPS_STABS_ELF */
11906 /* The .fmask and .mask directives. If the mdebug section is present
11907 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11908 embedded targets, s_mips_mask is used so that we can set the PDR
11909 information correctly. We can't use the ecoff routines because they
11910 make reference to the ecoff symbol table (in the mdebug section). */
11913 s_mips_mask (reg_type
)
11916 #ifdef MIPS_STABS_ELF
11919 if (cur_proc_ptr
== (procS
*) NULL
)
11921 as_warn (_(".mask/.fmask outside of .ent"));
11922 demand_empty_rest_of_line ();
11926 if (get_absolute_expression_and_terminator (&mask
) != ',')
11928 as_warn (_("Bad .mask/.fmask directive"));
11929 --input_line_pointer
;
11930 demand_empty_rest_of_line ();
11934 off
= get_absolute_expression ();
11936 if (reg_type
== 'F')
11938 cur_proc_ptr
->fpreg_mask
= mask
;
11939 cur_proc_ptr
->fpreg_offset
= off
;
11943 cur_proc_ptr
->reg_mask
= mask
;
11944 cur_proc_ptr
->reg_offset
= off
;
11947 demand_empty_rest_of_line ();
11949 s_ignore (reg_type
);
11950 #endif /* MIPS_STABS_ELF */
11953 /* The .loc directive. */
11964 assert (now_seg
== text_section
);
11966 lineno
= get_number ();
11967 addroff
= frag_now_fix ();
11969 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11970 S_SET_TYPE (symbolP
, N_SLINE
);
11971 S_SET_OTHER (symbolP
, 0);
11972 S_SET_DESC (symbolP
, lineno
);
11973 symbolP
->sy_segment
= now_seg
;