1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occured in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
198 /* Whether we are assembling for the mips16 processor. 0 if we are
199 not, 1 if we are, and -1 if the value has not been initialized.
200 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
201 -nomips16 command line options, and the default CPU. */
203 /* Non-zero if we should not reorder instructions. Changed by `.set
204 reorder' and `.set noreorder'. */
206 /* Non-zero if we should not permit the $at ($1) register to be used
207 in instructions. Changed by `.set at' and `.set noat'. */
209 /* Non-zero if we should warn when a macro instruction expands into
210 more than one machine instruction. Changed by `.set nomacro' and
212 int warn_about_macros
;
213 /* Non-zero if we should not move instructions. Changed by `.set
214 move', `.set volatile', `.set nomove', and `.set novolatile'. */
216 /* Non-zero if we should not optimize branches by moving the target
217 of the branch into the delay slot. Actually, we don't perform
218 this optimization anyhow. Changed by `.set bopt' and `.set
221 /* Non-zero if we should not autoextend mips16 instructions.
222 Changed by `.set autoextend' and `.set noautoextend'. */
224 /* Restrict general purpose registers and floating point registers
225 to 32 bit. This is initially determined when -mgp32 or -mfp32
226 is passed but can changed if the assembler code uses .set mipsN. */
229 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
230 command line option, and the default CPU. */
232 /* True if ".set sym32" is in effect. */
236 /* True if -mgp32 was passed. */
237 static int file_mips_gp32
= -1;
239 /* True if -mfp32 was passed. */
240 static int file_mips_fp32
= -1;
242 /* This is the struct we use to hold the current set of options. Note
243 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
244 -1 to indicate that they have not been initialized. */
246 static struct mips_set_options mips_opts
=
248 ISA_UNKNOWN
, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
251 /* These variables are filled in with the masks of registers used.
252 The object format code reads them and puts them in the appropriate
254 unsigned long mips_gprmask
;
255 unsigned long mips_cprmask
[4];
257 /* MIPS ISA we are using for this output file. */
258 static int file_mips_isa
= ISA_UNKNOWN
;
260 /* True if -mips16 was passed or implied by arguments passed on the
261 command line (e.g., by -march). */
262 static int file_ase_mips16
;
264 /* True if -mips3d was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips3d
;
268 /* True if -mdmx was passed or implied by arguments passed on the
269 command line (e.g., by -march). */
270 static int file_ase_mdmx
;
272 /* True if -mdsp was passed or implied by arguments passed on the
273 command line (e.g., by -march). */
274 static int file_ase_dsp
;
276 /* True if -mmt was passed or implied by arguments passed on the
277 command line (e.g., by -march). */
278 static int file_ase_mt
;
280 /* The argument of the -march= flag. The architecture we are assembling. */
281 static int file_mips_arch
= CPU_UNKNOWN
;
282 static const char *mips_arch_string
;
284 /* The argument of the -mtune= flag. The architecture for which we
286 static int mips_tune
= CPU_UNKNOWN
;
287 static const char *mips_tune_string
;
289 /* True when generating 32-bit code for a 64-bit processor. */
290 static int mips_32bitmode
= 0;
292 /* True if the given ABI requires 32-bit registers. */
293 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
295 /* Likewise 64-bit registers. */
296 #define ABI_NEEDS_64BIT_REGS(ABI) \
298 || (ABI) == N64_ABI \
301 /* Return true if ISA supports 64 bit gp register instructions. */
302 #define ISA_HAS_64BIT_REGS(ISA) ( \
304 || (ISA) == ISA_MIPS4 \
305 || (ISA) == ISA_MIPS5 \
306 || (ISA) == ISA_MIPS64 \
307 || (ISA) == ISA_MIPS64R2 \
310 /* Return true if ISA supports 64-bit right rotate (dror et al.)
312 #define ISA_HAS_DROR(ISA) ( \
313 (ISA) == ISA_MIPS64R2 \
316 /* Return true if ISA supports 32-bit right rotate (ror et al.)
318 #define ISA_HAS_ROR(ISA) ( \
319 (ISA) == ISA_MIPS32R2 \
320 || (ISA) == ISA_MIPS64R2 \
323 #define HAVE_32BIT_GPRS \
324 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
326 #define HAVE_32BIT_FPRS \
327 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
329 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
330 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
332 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
334 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
336 /* True if relocations are stored in-place. */
337 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
339 /* The ABI-derived address size. */
340 #define HAVE_64BIT_ADDRESSES \
341 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
342 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
344 /* The size of symbolic constants (i.e., expressions of the form
345 "SYMBOL" or "SYMBOL + OFFSET"). */
346 #define HAVE_32BIT_SYMBOLS \
347 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
348 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
350 /* Addresses are loaded in different ways, depending on the address size
351 in use. The n32 ABI Documentation also mandates the use of additions
352 with overflow checking, but existing implementations don't follow it. */
353 #define ADDRESS_ADD_INSN \
354 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
356 #define ADDRESS_ADDI_INSN \
357 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
359 #define ADDRESS_LOAD_INSN \
360 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
362 #define ADDRESS_STORE_INSN \
363 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
365 /* Return true if the given CPU supports the MIPS16 ASE. */
366 #define CPU_HAS_MIPS16(cpu) \
367 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
368 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
370 /* Return true if the given CPU supports the MIPS3D ASE. */
371 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
374 /* Return true if the given CPU supports the MDMX ASE. */
375 #define CPU_HAS_MDMX(cpu) (FALSE \
378 /* Return true if the given CPU supports the DSP ASE. */
379 #define CPU_HAS_DSP(cpu) (FALSE \
382 /* Return true if the given CPU supports the MT ASE. */
383 #define CPU_HAS_MT(cpu) (FALSE \
386 /* True if CPU has a dror instruction. */
387 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
389 /* True if CPU has a ror instruction. */
390 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
392 /* True if mflo and mfhi can be immediately followed by instructions
393 which write to the HI and LO registers.
395 According to MIPS specifications, MIPS ISAs I, II, and III need
396 (at least) two instructions between the reads of HI/LO and
397 instructions which write them, and later ISAs do not. Contradicting
398 the MIPS specifications, some MIPS IV processor user manuals (e.g.
399 the UM for the NEC Vr5000) document needing the instructions between
400 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
401 MIPS64 and later ISAs to have the interlocks, plus any specific
402 earlier-ISA CPUs for which CPU documentation declares that the
403 instructions are really interlocked. */
404 #define hilo_interlocks \
405 (mips_opts.isa == ISA_MIPS32 \
406 || mips_opts.isa == ISA_MIPS32R2 \
407 || mips_opts.isa == ISA_MIPS64 \
408 || mips_opts.isa == ISA_MIPS64R2 \
409 || mips_opts.arch == CPU_R4010 \
410 || mips_opts.arch == CPU_R10000 \
411 || mips_opts.arch == CPU_R12000 \
412 || mips_opts.arch == CPU_RM7000 \
413 || mips_opts.arch == CPU_VR5500 \
416 /* Whether the processor uses hardware interlocks to protect reads
417 from the GPRs after they are loaded from memory, and thus does not
418 require nops to be inserted. This applies to instructions marked
419 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
421 #define gpr_interlocks \
422 (mips_opts.isa != ISA_MIPS1 \
423 || mips_opts.arch == CPU_R3900)
425 /* Whether the processor uses hardware interlocks to avoid delays
426 required by coprocessor instructions, and thus does not require
427 nops to be inserted. This applies to instructions marked
428 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
429 between instructions marked INSN_WRITE_COND_CODE and ones marked
430 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
431 levels I, II, and III. */
432 /* Itbl support may require additional care here. */
433 #define cop_interlocks \
434 ((mips_opts.isa != ISA_MIPS1 \
435 && mips_opts.isa != ISA_MIPS2 \
436 && mips_opts.isa != ISA_MIPS3) \
437 || mips_opts.arch == CPU_R4300 \
440 /* Whether the processor uses hardware interlocks to protect reads
441 from coprocessor registers after they are loaded from memory, and
442 thus does not require nops to be inserted. This applies to
443 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
444 requires at MIPS ISA level I. */
445 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
447 /* Is this a mfhi or mflo instruction? */
448 #define MF_HILO_INSN(PINFO) \
449 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
451 /* MIPS PIC level. */
453 enum mips_pic_level mips_pic
;
455 /* 1 if we should generate 32 bit offsets from the $gp register in
456 SVR4_PIC mode. Currently has no meaning in other modes. */
457 static int mips_big_got
= 0;
459 /* 1 if trap instructions should used for overflow rather than break
461 static int mips_trap
= 0;
463 /* 1 if double width floating point constants should not be constructed
464 by assembling two single width halves into two single width floating
465 point registers which just happen to alias the double width destination
466 register. On some architectures this aliasing can be disabled by a bit
467 in the status register, and the setting of this bit cannot be determined
468 automatically at assemble time. */
469 static int mips_disable_float_construction
;
471 /* Non-zero if any .set noreorder directives were used. */
473 static int mips_any_noreorder
;
475 /* Non-zero if nops should be inserted when the register referenced in
476 an mfhi/mflo instruction is read in the next two instructions. */
477 static int mips_7000_hilo_fix
;
479 /* The size of the small data section. */
480 static unsigned int g_switch_value
= 8;
481 /* Whether the -G option was used. */
482 static int g_switch_seen
= 0;
487 /* If we can determine in advance that GP optimization won't be
488 possible, we can skip the relaxation stuff that tries to produce
489 GP-relative references. This makes delay slot optimization work
492 This function can only provide a guess, but it seems to work for
493 gcc output. It needs to guess right for gcc, otherwise gcc
494 will put what it thinks is a GP-relative instruction in a branch
497 I don't know if a fix is needed for the SVR4_PIC mode. I've only
498 fixed it for the non-PIC mode. KR 95/04/07 */
499 static int nopic_need_relax (symbolS
*, int);
501 /* handle of the OPCODE hash table */
502 static struct hash_control
*op_hash
= NULL
;
504 /* The opcode hash table we use for the mips16. */
505 static struct hash_control
*mips16_op_hash
= NULL
;
507 /* This array holds the chars that always start a comment. If the
508 pre-processor is disabled, these aren't very useful */
509 const char comment_chars
[] = "#";
511 /* This array holds the chars that only start a comment at the beginning of
512 a line. If the line seems to have the form '# 123 filename'
513 .line and .file directives will appear in the pre-processed output */
514 /* Note that input_file.c hand checks for '#' at the beginning of the
515 first line of the input file. This is because the compiler outputs
516 #NO_APP at the beginning of its output. */
517 /* Also note that C style comments are always supported. */
518 const char line_comment_chars
[] = "#";
520 /* This array holds machine specific line separator characters. */
521 const char line_separator_chars
[] = ";";
523 /* Chars that can be used to separate mant from exp in floating point nums */
524 const char EXP_CHARS
[] = "eE";
526 /* Chars that mean this number is a floating point constant */
529 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
531 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
532 changed in read.c . Ideally it shouldn't have to know about it at all,
533 but nothing is ideal around here.
536 static char *insn_error
;
538 static int auto_align
= 1;
540 /* When outputting SVR4 PIC code, the assembler needs to know the
541 offset in the stack frame from which to restore the $gp register.
542 This is set by the .cprestore pseudo-op, and saved in this
544 static offsetT mips_cprestore_offset
= -1;
546 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
547 more optimizations, it can use a register value instead of a memory-saved
548 offset and even an other register than $gp as global pointer. */
549 static offsetT mips_cpreturn_offset
= -1;
550 static int mips_cpreturn_register
= -1;
551 static int mips_gp_register
= GP
;
552 static int mips_gprel_offset
= 0;
554 /* Whether mips_cprestore_offset has been set in the current function
555 (or whether it has already been warned about, if not). */
556 static int mips_cprestore_valid
= 0;
558 /* This is the register which holds the stack frame, as set by the
559 .frame pseudo-op. This is needed to implement .cprestore. */
560 static int mips_frame_reg
= SP
;
562 /* Whether mips_frame_reg has been set in the current function
563 (or whether it has already been warned about, if not). */
564 static int mips_frame_reg_valid
= 0;
566 /* To output NOP instructions correctly, we need to keep information
567 about the previous two instructions. */
569 /* Whether we are optimizing. The default value of 2 means to remove
570 unneeded NOPs and swap branch instructions when possible. A value
571 of 1 means to not swap branches. A value of 0 means to always
573 static int mips_optimize
= 2;
575 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
576 equivalent to seeing no -g option at all. */
577 static int mips_debug
= 0;
579 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
580 #define MAX_VR4130_NOPS 4
582 /* The maximum number of NOPs needed to fill delay slots. */
583 #define MAX_DELAY_NOPS 2
585 /* The maximum number of NOPs needed for any purpose. */
588 /* A list of previous instructions, with index 0 being the most recent.
589 We need to look back MAX_NOPS instructions when filling delay slots
590 or working around processor errata. We need to look back one
591 instruction further if we're thinking about using history[0] to
592 fill a branch delay slot. */
593 static struct mips_cl_insn history
[1 + MAX_NOPS
];
595 /* Nop instructions used by emit_nop. */
596 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
598 /* The appropriate nop for the current mode. */
599 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
601 /* If this is set, it points to a frag holding nop instructions which
602 were inserted before the start of a noreorder section. If those
603 nops turn out to be unnecessary, the size of the frag can be
605 static fragS
*prev_nop_frag
;
607 /* The number of nop instructions we created in prev_nop_frag. */
608 static int prev_nop_frag_holds
;
610 /* The number of nop instructions that we know we need in
612 static int prev_nop_frag_required
;
614 /* The number of instructions we've seen since prev_nop_frag. */
615 static int prev_nop_frag_since
;
617 /* For ECOFF and ELF, relocations against symbols are done in two
618 parts, with a HI relocation and a LO relocation. Each relocation
619 has only 16 bits of space to store an addend. This means that in
620 order for the linker to handle carries correctly, it must be able
621 to locate both the HI and the LO relocation. This means that the
622 relocations must appear in order in the relocation table.
624 In order to implement this, we keep track of each unmatched HI
625 relocation. We then sort them so that they immediately precede the
626 corresponding LO relocation. */
631 struct mips_hi_fixup
*next
;
634 /* The section this fixup is in. */
638 /* The list of unmatched HI relocs. */
640 static struct mips_hi_fixup
*mips_hi_fixup_list
;
642 /* The frag containing the last explicit relocation operator.
643 Null if explicit relocations have not been used. */
645 static fragS
*prev_reloc_op_frag
;
647 /* Map normal MIPS register numbers to mips16 register numbers. */
649 #define X ILLEGAL_REG
650 static const int mips32_to_16_reg_map
[] =
652 X
, X
, 2, 3, 4, 5, 6, 7,
653 X
, X
, X
, X
, X
, X
, X
, X
,
654 0, 1, X
, X
, X
, X
, X
, X
,
655 X
, X
, X
, X
, X
, X
, X
, X
659 /* Map mips16 register numbers to normal MIPS register numbers. */
661 static const unsigned int mips16_to_32_reg_map
[] =
663 16, 17, 2, 3, 4, 5, 6, 7
666 /* Classifies the kind of instructions we're interested in when
667 implementing -mfix-vr4120. */
668 enum fix_vr4120_class
{
675 NUM_FIX_VR4120_CLASSES
678 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
679 there must be at least one other instruction between an instruction
680 of type X and an instruction of type Y. */
681 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
683 /* True if -mfix-vr4120 is in force. */
684 static int mips_fix_vr4120
;
686 /* ...likewise -mfix-vr4130. */
687 static int mips_fix_vr4130
;
689 /* We don't relax branches by default, since this causes us to expand
690 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
691 fail to compute the offset before expanding the macro to the most
692 efficient expansion. */
694 static int mips_relax_branch
;
696 /* The expansion of many macros depends on the type of symbol that
697 they refer to. For example, when generating position-dependent code,
698 a macro that refers to a symbol may have two different expansions,
699 one which uses GP-relative addresses and one which uses absolute
700 addresses. When generating SVR4-style PIC, a macro may have
701 different expansions for local and global symbols.
703 We handle these situations by generating both sequences and putting
704 them in variant frags. In position-dependent code, the first sequence
705 will be the GP-relative one and the second sequence will be the
706 absolute one. In SVR4 PIC, the first sequence will be for global
707 symbols and the second will be for local symbols.
709 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
710 SECOND are the lengths of the two sequences in bytes. These fields
711 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
712 the subtype has the following flags:
715 Set if it has been decided that we should use the second
716 sequence instead of the first.
719 Set in the first variant frag if the macro's second implementation
720 is longer than its first. This refers to the macro as a whole,
721 not an individual relaxation.
724 Set in the first variant frag if the macro appeared in a .set nomacro
725 block and if one alternative requires a warning but the other does not.
728 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
731 The frag's "opcode" points to the first fixup for relaxable code.
733 Relaxable macros are generated using a sequence such as:
735 relax_start (SYMBOL);
736 ... generate first expansion ...
738 ... generate second expansion ...
741 The code and fixups for the unwanted alternative are discarded
742 by md_convert_frag. */
743 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
745 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
746 #define RELAX_SECOND(X) ((X) & 0xff)
747 #define RELAX_USE_SECOND 0x10000
748 #define RELAX_SECOND_LONGER 0x20000
749 #define RELAX_NOMACRO 0x40000
750 #define RELAX_DELAY_SLOT 0x80000
752 /* Branch without likely bit. If label is out of range, we turn:
754 beq reg1, reg2, label
764 with the following opcode replacements:
771 bltzal <-> bgezal (with jal label instead of j label)
773 Even though keeping the delay slot instruction in the delay slot of
774 the branch would be more efficient, it would be very tricky to do
775 correctly, because we'd have to introduce a variable frag *after*
776 the delay slot instruction, and expand that instead. Let's do it
777 the easy way for now, even if the branch-not-taken case now costs
778 one additional instruction. Out-of-range branches are not supposed
779 to be common, anyway.
781 Branch likely. If label is out of range, we turn:
783 beql reg1, reg2, label
784 delay slot (annulled if branch not taken)
793 delay slot (executed only if branch taken)
796 It would be possible to generate a shorter sequence by losing the
797 likely bit, generating something like:
802 delay slot (executed only if branch taken)
814 bltzall -> bgezal (with jal label instead of j label)
815 bgezall -> bltzal (ditto)
818 but it's not clear that it would actually improve performance. */
819 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
822 | ((toofar) ? 1 : 0) \
824 | ((likely) ? 4 : 0) \
825 | ((uncond) ? 8 : 0)))
826 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
827 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
828 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
829 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
830 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
832 /* For mips16 code, we use an entirely different form of relaxation.
833 mips16 supports two versions of most instructions which take
834 immediate values: a small one which takes some small value, and a
835 larger one which takes a 16 bit value. Since branches also follow
836 this pattern, relaxing these values is required.
838 We can assemble both mips16 and normal MIPS code in a single
839 object. Therefore, we need to support this type of relaxation at
840 the same time that we support the relaxation described above. We
841 use the high bit of the subtype field to distinguish these cases.
843 The information we store for this type of relaxation is the
844 argument code found in the opcode file for this relocation, whether
845 the user explicitly requested a small or extended form, and whether
846 the relocation is in a jump or jal delay slot. That tells us the
847 size of the value, and how it should be stored. We also store
848 whether the fragment is considered to be extended or not. We also
849 store whether this is known to be a branch to a different section,
850 whether we have tried to relax this frag yet, and whether we have
851 ever extended a PC relative fragment because of a shift count. */
852 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
855 | ((small) ? 0x100 : 0) \
856 | ((ext) ? 0x200 : 0) \
857 | ((dslot) ? 0x400 : 0) \
858 | ((jal_dslot) ? 0x800 : 0))
859 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
860 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
861 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
862 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
863 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
864 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
865 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
866 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
867 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
868 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
869 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
870 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
872 /* Is the given value a sign-extended 32-bit value? */
873 #define IS_SEXT_32BIT_NUM(x) \
874 (((x) &~ (offsetT) 0x7fffffff) == 0 \
875 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
877 /* Is the given value a sign-extended 16-bit value? */
878 #define IS_SEXT_16BIT_NUM(x) \
879 (((x) &~ (offsetT) 0x7fff) == 0 \
880 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
882 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
883 #define IS_ZEXT_32BIT_NUM(x) \
884 (((x) &~ (offsetT) 0xffffffff) == 0 \
885 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
887 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
888 VALUE << SHIFT. VALUE is evaluated exactly once. */
889 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
890 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
891 | (((VALUE) & (MASK)) << (SHIFT)))
893 /* Extract bits MASK << SHIFT from STRUCT and shift them right
895 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
896 (((STRUCT) >> (SHIFT)) & (MASK))
898 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
899 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
901 include/opcode/mips.h specifies operand fields using the macros
902 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
903 with "MIPS16OP" instead of "OP". */
904 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
905 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
906 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
907 INSERT_BITS ((INSN).insn_opcode, VALUE, \
908 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
910 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
911 #define EXTRACT_OPERAND(FIELD, INSN) \
912 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
913 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
914 EXTRACT_BITS ((INSN).insn_opcode, \
915 MIPS16OP_MASK_##FIELD, \
918 /* Global variables used when generating relaxable macros. See the
919 comment above RELAX_ENCODE for more details about how relaxation
922 /* 0 if we're not emitting a relaxable macro.
923 1 if we're emitting the first of the two relaxation alternatives.
924 2 if we're emitting the second alternative. */
927 /* The first relaxable fixup in the current frag. (In other words,
928 the first fixup that refers to relaxable code.) */
931 /* sizes[0] says how many bytes of the first alternative are stored in
932 the current frag. Likewise sizes[1] for the second alternative. */
933 unsigned int sizes
[2];
935 /* The symbol on which the choice of sequence depends. */
939 /* Global variables used to decide whether a macro needs a warning. */
941 /* True if the macro is in a branch delay slot. */
942 bfd_boolean delay_slot_p
;
944 /* For relaxable macros, sizes[0] is the length of the first alternative
945 in bytes and sizes[1] is the length of the second alternative.
946 For non-relaxable macros, both elements give the length of the
948 unsigned int sizes
[2];
950 /* The first variant frag for this macro. */
952 } mips_macro_warning
;
954 /* Prototypes for static functions. */
956 #define internalError() \
957 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
959 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
961 static void append_insn
962 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
963 static void mips_no_prev_insn (void);
964 static void mips16_macro_build
965 (expressionS
*, const char *, const char *, va_list);
966 static void load_register (int, expressionS
*, int);
967 static void macro_start (void);
968 static void macro_end (void);
969 static void macro (struct mips_cl_insn
* ip
);
970 static void mips16_macro (struct mips_cl_insn
* ip
);
971 #ifdef LOSING_COMPILER
972 static void macro2 (struct mips_cl_insn
* ip
);
974 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
975 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
976 static void mips16_immed
977 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
978 unsigned long *, bfd_boolean
*, unsigned short *);
979 static size_t my_getSmallExpression
980 (expressionS
*, bfd_reloc_code_real_type
*, char *);
981 static void my_getExpression (expressionS
*, char *);
982 static void s_align (int);
983 static void s_change_sec (int);
984 static void s_change_section (int);
985 static void s_cons (int);
986 static void s_float_cons (int);
987 static void s_mips_globl (int);
988 static void s_option (int);
989 static void s_mipsset (int);
990 static void s_abicalls (int);
991 static void s_cpload (int);
992 static void s_cpsetup (int);
993 static void s_cplocal (int);
994 static void s_cprestore (int);
995 static void s_cpreturn (int);
996 static void s_gpvalue (int);
997 static void s_gpword (int);
998 static void s_gpdword (int);
999 static void s_cpadd (int);
1000 static void s_insn (int);
1001 static void md_obj_begin (void);
1002 static void md_obj_end (void);
1003 static void s_mips_ent (int);
1004 static void s_mips_end (int);
1005 static void s_mips_frame (int);
1006 static void s_mips_mask (int reg_type
);
1007 static void s_mips_stab (int);
1008 static void s_mips_weakext (int);
1009 static void s_mips_file (int);
1010 static void s_mips_loc (int);
1011 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1012 static int relaxed_branch_length (fragS
*, asection
*, int);
1013 static int validate_mips_insn (const struct mips_opcode
*);
1015 /* Table and functions used to map between CPU/ISA names, and
1016 ISA levels, and CPU numbers. */
1018 struct mips_cpu_info
1020 const char *name
; /* CPU or ISA name. */
1021 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1022 int isa
; /* ISA level. */
1023 int cpu
; /* CPU number (default CPU if ISA). */
1026 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1027 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1028 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1032 The following pseudo-ops from the Kane and Heinrich MIPS book
1033 should be defined here, but are currently unsupported: .alias,
1034 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1036 The following pseudo-ops from the Kane and Heinrich MIPS book are
1037 specific to the type of debugging information being generated, and
1038 should be defined by the object format: .aent, .begin, .bend,
1039 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1042 The following pseudo-ops from the Kane and Heinrich MIPS book are
1043 not MIPS CPU specific, but are also not specific to the object file
1044 format. This file is probably the best place to define them, but
1045 they are not currently supported: .asm0, .endr, .lab, .repeat,
1048 static const pseudo_typeS mips_pseudo_table
[] =
1050 /* MIPS specific pseudo-ops. */
1051 {"option", s_option
, 0},
1052 {"set", s_mipsset
, 0},
1053 {"rdata", s_change_sec
, 'r'},
1054 {"sdata", s_change_sec
, 's'},
1055 {"livereg", s_ignore
, 0},
1056 {"abicalls", s_abicalls
, 0},
1057 {"cpload", s_cpload
, 0},
1058 {"cpsetup", s_cpsetup
, 0},
1059 {"cplocal", s_cplocal
, 0},
1060 {"cprestore", s_cprestore
, 0},
1061 {"cpreturn", s_cpreturn
, 0},
1062 {"gpvalue", s_gpvalue
, 0},
1063 {"gpword", s_gpword
, 0},
1064 {"gpdword", s_gpdword
, 0},
1065 {"cpadd", s_cpadd
, 0},
1066 {"insn", s_insn
, 0},
1068 /* Relatively generic pseudo-ops that happen to be used on MIPS
1070 {"asciiz", stringer
, 1},
1071 {"bss", s_change_sec
, 'b'},
1073 {"half", s_cons
, 1},
1074 {"dword", s_cons
, 3},
1075 {"weakext", s_mips_weakext
, 0},
1077 /* These pseudo-ops are defined in read.c, but must be overridden
1078 here for one reason or another. */
1079 {"align", s_align
, 0},
1080 {"byte", s_cons
, 0},
1081 {"data", s_change_sec
, 'd'},
1082 {"double", s_float_cons
, 'd'},
1083 {"float", s_float_cons
, 'f'},
1084 {"globl", s_mips_globl
, 0},
1085 {"global", s_mips_globl
, 0},
1086 {"hword", s_cons
, 1},
1088 {"long", s_cons
, 2},
1089 {"octa", s_cons
, 4},
1090 {"quad", s_cons
, 3},
1091 {"section", s_change_section
, 0},
1092 {"short", s_cons
, 1},
1093 {"single", s_float_cons
, 'f'},
1094 {"stabn", s_mips_stab
, 'n'},
1095 {"text", s_change_sec
, 't'},
1096 {"word", s_cons
, 2},
1098 { "extern", ecoff_directive_extern
, 0},
1103 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1105 /* These pseudo-ops should be defined by the object file format.
1106 However, a.out doesn't support them, so we have versions here. */
1107 {"aent", s_mips_ent
, 1},
1108 {"bgnb", s_ignore
, 0},
1109 {"end", s_mips_end
, 0},
1110 {"endb", s_ignore
, 0},
1111 {"ent", s_mips_ent
, 0},
1112 {"file", s_mips_file
, 0},
1113 {"fmask", s_mips_mask
, 'F'},
1114 {"frame", s_mips_frame
, 0},
1115 {"loc", s_mips_loc
, 0},
1116 {"mask", s_mips_mask
, 'R'},
1117 {"verstamp", s_ignore
, 0},
1121 extern void pop_insert (const pseudo_typeS
*);
1124 mips_pop_insert (void)
1126 pop_insert (mips_pseudo_table
);
1127 if (! ECOFF_DEBUGGING
)
1128 pop_insert (mips_nonecoff_pseudo_table
);
1131 /* Symbols labelling the current insn. */
1133 struct insn_label_list
1135 struct insn_label_list
*next
;
1139 static struct insn_label_list
*insn_labels
;
1140 static struct insn_label_list
*free_insn_labels
;
1142 static void mips_clear_insn_labels (void);
1145 mips_clear_insn_labels (void)
1147 register struct insn_label_list
**pl
;
1149 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1155 static char *expr_end
;
1157 /* Expressions which appear in instructions. These are set by
1160 static expressionS imm_expr
;
1161 static expressionS imm2_expr
;
1162 static expressionS offset_expr
;
1164 /* Relocs associated with imm_expr and offset_expr. */
1166 static bfd_reloc_code_real_type imm_reloc
[3]
1167 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1168 static bfd_reloc_code_real_type offset_reloc
[3]
1169 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1171 /* These are set by mips16_ip if an explicit extension is used. */
1173 static bfd_boolean mips16_small
, mips16_ext
;
1176 /* The pdr segment for per procedure frame/regmask info. Not used for
1179 static segT pdr_seg
;
1182 /* The default target format to use. */
1185 mips_target_format (void)
1187 switch (OUTPUT_FLAVOR
)
1189 case bfd_target_ecoff_flavour
:
1190 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1191 case bfd_target_coff_flavour
:
1193 case bfd_target_elf_flavour
:
1195 /* This is traditional mips. */
1196 return (target_big_endian
1197 ? (HAVE_64BIT_OBJECTS
1198 ? "elf64-tradbigmips"
1200 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1201 : (HAVE_64BIT_OBJECTS
1202 ? "elf64-tradlittlemips"
1204 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1206 return (target_big_endian
1207 ? (HAVE_64BIT_OBJECTS
1210 ? "elf32-nbigmips" : "elf32-bigmips"))
1211 : (HAVE_64BIT_OBJECTS
1212 ? "elf64-littlemips"
1214 ? "elf32-nlittlemips" : "elf32-littlemips")));
1222 /* Return the length of instruction INSN. */
1224 static inline unsigned int
1225 insn_length (const struct mips_cl_insn
*insn
)
1227 if (!mips_opts
.mips16
)
1229 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1232 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1235 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1240 insn
->use_extend
= FALSE
;
1242 insn
->insn_opcode
= mo
->match
;
1245 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1246 insn
->fixp
[i
] = NULL
;
1247 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1248 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1249 insn
->mips16_absolute_jump_p
= 0;
1252 /* Install INSN at the location specified by its "frag" and "where" fields. */
1255 install_insn (const struct mips_cl_insn
*insn
)
1257 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1258 if (!mips_opts
.mips16
)
1259 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1260 else if (insn
->mips16_absolute_jump_p
)
1262 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1263 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1267 if (insn
->use_extend
)
1269 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1272 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1276 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1277 and install the opcode in the new location. */
1280 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1285 insn
->where
= where
;
1286 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1287 if (insn
->fixp
[i
] != NULL
)
1289 insn
->fixp
[i
]->fx_frag
= frag
;
1290 insn
->fixp
[i
]->fx_where
= where
;
1292 install_insn (insn
);
1295 /* Add INSN to the end of the output. */
1298 add_fixed_insn (struct mips_cl_insn
*insn
)
1300 char *f
= frag_more (insn_length (insn
));
1301 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1304 /* Start a variant frag and move INSN to the start of the variant part,
1305 marking it as fixed. The other arguments are as for frag_var. */
1308 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1309 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1311 frag_grow (max_chars
);
1312 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1314 frag_var (rs_machine_dependent
, max_chars
, var
,
1315 subtype
, symbol
, offset
, NULL
);
1318 /* Insert N copies of INSN into the history buffer, starting at
1319 position FIRST. Neither FIRST nor N need to be clipped. */
1322 insert_into_history (unsigned int first
, unsigned int n
,
1323 const struct mips_cl_insn
*insn
)
1325 if (mips_relax
.sequence
!= 2)
1329 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1331 history
[i
] = history
[i
- n
];
1337 /* Emit a nop instruction, recording it in the history buffer. */
1342 add_fixed_insn (NOP_INSN
);
1343 insert_into_history (0, 1, NOP_INSN
);
1346 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1347 the idea is to make it obvious at a glance that each errata is
1351 init_vr4120_conflicts (void)
1353 #define CONFLICT(FIRST, SECOND) \
1354 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1356 /* Errata 21 - [D]DIV[U] after [D]MACC */
1357 CONFLICT (MACC
, DIV
);
1358 CONFLICT (DMACC
, DIV
);
1360 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1361 CONFLICT (DMULT
, DMULT
);
1362 CONFLICT (DMULT
, DMACC
);
1363 CONFLICT (DMACC
, DMULT
);
1364 CONFLICT (DMACC
, DMACC
);
1366 /* Errata 24 - MT{LO,HI} after [D]MACC */
1367 CONFLICT (MACC
, MTHILO
);
1368 CONFLICT (DMACC
, MTHILO
);
1370 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1371 instruction is executed immediately after a MACC or DMACC
1372 instruction, the result of [either instruction] is incorrect." */
1373 CONFLICT (MACC
, MULT
);
1374 CONFLICT (MACC
, DMULT
);
1375 CONFLICT (DMACC
, MULT
);
1376 CONFLICT (DMACC
, DMULT
);
1378 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1379 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1380 DDIV or DDIVU instruction, the result of the MACC or
1381 DMACC instruction is incorrect.". */
1382 CONFLICT (DMULT
, MACC
);
1383 CONFLICT (DMULT
, DMACC
);
1384 CONFLICT (DIV
, MACC
);
1385 CONFLICT (DIV
, DMACC
);
1390 /* This function is called once, at assembler startup time. It should
1391 set up all the tables, etc. that the MD part of the assembler will need. */
1396 register const char *retval
= NULL
;
1400 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1401 as_warn (_("Could not set architecture and machine"));
1403 op_hash
= hash_new ();
1405 for (i
= 0; i
< NUMOPCODES
;)
1407 const char *name
= mips_opcodes
[i
].name
;
1409 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1412 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1413 mips_opcodes
[i
].name
, retval
);
1414 /* Probably a memory allocation problem? Give up now. */
1415 as_fatal (_("Broken assembler. No assembly attempted."));
1419 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1421 if (!validate_mips_insn (&mips_opcodes
[i
]))
1423 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1425 create_insn (&nop_insn
, mips_opcodes
+ i
);
1426 nop_insn
.fixed_p
= 1;
1431 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1434 mips16_op_hash
= hash_new ();
1437 while (i
< bfd_mips16_num_opcodes
)
1439 const char *name
= mips16_opcodes
[i
].name
;
1441 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1443 as_fatal (_("internal: can't hash `%s': %s"),
1444 mips16_opcodes
[i
].name
, retval
);
1447 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1448 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1449 != mips16_opcodes
[i
].match
))
1451 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1452 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1455 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1457 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1458 mips16_nop_insn
.fixed_p
= 1;
1462 while (i
< bfd_mips16_num_opcodes
1463 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1467 as_fatal (_("Broken assembler. No assembly attempted."));
1469 /* We add all the general register names to the symbol table. This
1470 helps us detect invalid uses of them. */
1471 for (i
= 0; i
< 32; i
++)
1475 sprintf (buf
, "$%d", i
);
1476 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1477 &zero_address_frag
));
1479 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1480 &zero_address_frag
));
1481 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1482 &zero_address_frag
));
1483 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1484 &zero_address_frag
));
1485 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1486 &zero_address_frag
));
1487 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1488 &zero_address_frag
));
1489 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1490 &zero_address_frag
));
1491 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1492 &zero_address_frag
));
1493 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1494 &zero_address_frag
));
1495 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1496 &zero_address_frag
));
1498 /* If we don't add these register names to the symbol table, they
1499 may end up being added as regular symbols by operand(), and then
1500 make it to the object file as undefined in case they're not
1501 regarded as local symbols. They're local in o32, since `$' is a
1502 local symbol prefix, but not in n32 or n64. */
1503 for (i
= 0; i
< 8; i
++)
1507 sprintf (buf
, "$fcc%i", i
);
1508 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1509 &zero_address_frag
));
1512 mips_no_prev_insn ();
1515 mips_cprmask
[0] = 0;
1516 mips_cprmask
[1] = 0;
1517 mips_cprmask
[2] = 0;
1518 mips_cprmask
[3] = 0;
1520 /* set the default alignment for the text section (2**2) */
1521 record_alignment (text_section
, 2);
1523 bfd_set_gp_size (stdoutput
, g_switch_value
);
1525 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1527 /* On a native system, sections must be aligned to 16 byte
1528 boundaries. When configured for an embedded ELF target, we
1530 if (strcmp (TARGET_OS
, "elf") != 0)
1532 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1533 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1534 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1537 /* Create a .reginfo section for register masks and a .mdebug
1538 section for debugging information. */
1546 subseg
= now_subseg
;
1548 /* The ABI says this section should be loaded so that the
1549 running program can access it. However, we don't load it
1550 if we are configured for an embedded target */
1551 flags
= SEC_READONLY
| SEC_DATA
;
1552 if (strcmp (TARGET_OS
, "elf") != 0)
1553 flags
|= SEC_ALLOC
| SEC_LOAD
;
1555 if (mips_abi
!= N64_ABI
)
1557 sec
= subseg_new (".reginfo", (subsegT
) 0);
1559 bfd_set_section_flags (stdoutput
, sec
, flags
);
1560 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1563 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1568 /* The 64-bit ABI uses a .MIPS.options section rather than
1569 .reginfo section. */
1570 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1571 bfd_set_section_flags (stdoutput
, sec
, flags
);
1572 bfd_set_section_alignment (stdoutput
, sec
, 3);
1575 /* Set up the option header. */
1577 Elf_Internal_Options opthdr
;
1580 opthdr
.kind
= ODK_REGINFO
;
1581 opthdr
.size
= (sizeof (Elf_External_Options
)
1582 + sizeof (Elf64_External_RegInfo
));
1585 f
= frag_more (sizeof (Elf_External_Options
));
1586 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1587 (Elf_External_Options
*) f
);
1589 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1594 if (ECOFF_DEBUGGING
)
1596 sec
= subseg_new (".mdebug", (subsegT
) 0);
1597 (void) bfd_set_section_flags (stdoutput
, sec
,
1598 SEC_HAS_CONTENTS
| SEC_READONLY
);
1599 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1602 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1604 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1605 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1606 SEC_READONLY
| SEC_RELOC
1608 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1612 subseg_set (seg
, subseg
);
1616 if (! ECOFF_DEBUGGING
)
1619 if (mips_fix_vr4120
)
1620 init_vr4120_conflicts ();
1626 if (! ECOFF_DEBUGGING
)
1631 md_assemble (char *str
)
1633 struct mips_cl_insn insn
;
1634 bfd_reloc_code_real_type unused_reloc
[3]
1635 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1637 imm_expr
.X_op
= O_absent
;
1638 imm2_expr
.X_op
= O_absent
;
1639 offset_expr
.X_op
= O_absent
;
1640 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1641 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1642 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1643 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1644 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1645 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1647 if (mips_opts
.mips16
)
1648 mips16_ip (str
, &insn
);
1651 mips_ip (str
, &insn
);
1652 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1653 str
, insn
.insn_opcode
));
1658 as_bad ("%s `%s'", insn_error
, str
);
1662 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1665 if (mips_opts
.mips16
)
1666 mips16_macro (&insn
);
1673 if (imm_expr
.X_op
!= O_absent
)
1674 append_insn (&insn
, &imm_expr
, imm_reloc
);
1675 else if (offset_expr
.X_op
!= O_absent
)
1676 append_insn (&insn
, &offset_expr
, offset_reloc
);
1678 append_insn (&insn
, NULL
, unused_reloc
);
1682 /* Return true if the given relocation might need a matching %lo().
1683 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1684 applied to local symbols. */
1686 static inline bfd_boolean
1687 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1689 return (HAVE_IN_PLACE_ADDENDS
1690 && (reloc
== BFD_RELOC_HI16_S
1691 || reloc
== BFD_RELOC_MIPS_GOT16
1692 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1695 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1698 static inline bfd_boolean
1699 fixup_has_matching_lo_p (fixS
*fixp
)
1701 return (fixp
->fx_next
!= NULL
1702 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1703 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1704 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1705 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1708 /* See whether instruction IP reads register REG. CLASS is the type
1712 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1713 enum mips_regclass
class)
1715 if (class == MIPS16_REG
)
1717 assert (mips_opts
.mips16
);
1718 reg
= mips16_to_32_reg_map
[reg
];
1719 class = MIPS_GR_REG
;
1722 /* Don't report on general register ZERO, since it never changes. */
1723 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1726 if (class == MIPS_FP_REG
)
1728 assert (! mips_opts
.mips16
);
1729 /* If we are called with either $f0 or $f1, we must check $f0.
1730 This is not optimal, because it will introduce an unnecessary
1731 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1732 need to distinguish reading both $f0 and $f1 or just one of
1733 them. Note that we don't have to check the other way,
1734 because there is no instruction that sets both $f0 and $f1
1735 and requires a delay. */
1736 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1737 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1738 == (reg
&~ (unsigned) 1)))
1740 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1741 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1742 == (reg
&~ (unsigned) 1)))
1745 else if (! mips_opts
.mips16
)
1747 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1748 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1750 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1751 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1756 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1757 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1759 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1760 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1762 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1763 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1766 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1768 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1770 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1772 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1773 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1780 /* This function returns true if modifying a register requires a
1784 reg_needs_delay (unsigned int reg
)
1786 unsigned long prev_pinfo
;
1788 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1789 if (! mips_opts
.noreorder
1790 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1791 && ! gpr_interlocks
)
1792 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1793 && ! cop_interlocks
)))
1795 /* A load from a coprocessor or from memory. All load delays
1796 delay the use of general register rt for one instruction. */
1797 /* Itbl support may require additional care here. */
1798 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1799 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1806 /* Move all labels in insn_labels to the current insertion point. */
1809 mips_move_labels (void)
1811 struct insn_label_list
*l
;
1814 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1816 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1817 symbol_set_frag (l
->label
, frag_now
);
1818 val
= (valueT
) frag_now_fix ();
1819 /* mips16 text labels are stored as odd. */
1820 if (mips_opts
.mips16
)
1822 S_SET_VALUE (l
->label
, val
);
1826 /* Mark instruction labels in mips16 mode. This permits the linker to
1827 handle them specially, such as generating jalx instructions when
1828 needed. We also make them odd for the duration of the assembly, in
1829 order to generate the right sort of code. We will make them even
1830 in the adjust_symtab routine, while leaving them marked. This is
1831 convenient for the debugger and the disassembler. The linker knows
1832 to make them odd again. */
1835 mips16_mark_labels (void)
1837 if (mips_opts
.mips16
)
1839 struct insn_label_list
*l
;
1842 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1845 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1846 S_SET_OTHER (l
->label
, STO_MIPS16
);
1848 val
= S_GET_VALUE (l
->label
);
1850 S_SET_VALUE (l
->label
, val
+ 1);
1855 /* End the current frag. Make it a variant frag and record the
1859 relax_close_frag (void)
1861 mips_macro_warning
.first_frag
= frag_now
;
1862 frag_var (rs_machine_dependent
, 0, 0,
1863 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1864 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1866 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1867 mips_relax
.first_fixup
= 0;
1870 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1871 See the comment above RELAX_ENCODE for more details. */
1874 relax_start (symbolS
*symbol
)
1876 assert (mips_relax
.sequence
== 0);
1877 mips_relax
.sequence
= 1;
1878 mips_relax
.symbol
= symbol
;
1881 /* Start generating the second version of a relaxable sequence.
1882 See the comment above RELAX_ENCODE for more details. */
1887 assert (mips_relax
.sequence
== 1);
1888 mips_relax
.sequence
= 2;
1891 /* End the current relaxable sequence. */
1896 assert (mips_relax
.sequence
== 2);
1897 relax_close_frag ();
1898 mips_relax
.sequence
= 0;
1901 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1902 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1903 by VR4120 errata. */
1906 classify_vr4120_insn (const char *name
)
1908 if (strncmp (name
, "macc", 4) == 0)
1909 return FIX_VR4120_MACC
;
1910 if (strncmp (name
, "dmacc", 5) == 0)
1911 return FIX_VR4120_DMACC
;
1912 if (strncmp (name
, "mult", 4) == 0)
1913 return FIX_VR4120_MULT
;
1914 if (strncmp (name
, "dmult", 5) == 0)
1915 return FIX_VR4120_DMULT
;
1916 if (strstr (name
, "div"))
1917 return FIX_VR4120_DIV
;
1918 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1919 return FIX_VR4120_MTHILO
;
1920 return NUM_FIX_VR4120_CLASSES
;
1923 /* Return the number of instructions that must separate INSN1 and INSN2,
1924 where INSN1 is the earlier instruction. Return the worst-case value
1925 for any INSN2 if INSN2 is null. */
1928 insns_between (const struct mips_cl_insn
*insn1
,
1929 const struct mips_cl_insn
*insn2
)
1931 unsigned long pinfo1
, pinfo2
;
1933 /* This function needs to know which pinfo flags are set for INSN2
1934 and which registers INSN2 uses. The former is stored in PINFO2 and
1935 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1936 will have every flag set and INSN2_USES_REG will always return true. */
1937 pinfo1
= insn1
->insn_mo
->pinfo
;
1938 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1940 #define INSN2_USES_REG(REG, CLASS) \
1941 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1943 /* For most targets, write-after-read dependencies on the HI and LO
1944 registers must be separated by at least two instructions. */
1945 if (!hilo_interlocks
)
1947 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1949 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1953 /* If we're working around r7000 errata, there must be two instructions
1954 between an mfhi or mflo and any instruction that uses the result. */
1955 if (mips_7000_hilo_fix
1956 && MF_HILO_INSN (pinfo1
)
1957 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1960 /* If working around VR4120 errata, check for combinations that need
1961 a single intervening instruction. */
1962 if (mips_fix_vr4120
)
1964 unsigned int class1
, class2
;
1966 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1967 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1971 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1972 if (vr4120_conflicts
[class1
] & (1 << class2
))
1977 if (!mips_opts
.mips16
)
1979 /* Check for GPR or coprocessor load delays. All such delays
1980 are on the RT register. */
1981 /* Itbl support may require additional care here. */
1982 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1983 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1985 know (pinfo1
& INSN_WRITE_GPR_T
);
1986 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1990 /* Check for generic coprocessor hazards.
1992 This case is not handled very well. There is no special
1993 knowledge of CP0 handling, and the coprocessors other than
1994 the floating point unit are not distinguished at all. */
1995 /* Itbl support may require additional care here. FIXME!
1996 Need to modify this to include knowledge about
1997 user specified delays! */
1998 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1999 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2001 /* Handle cases where INSN1 writes to a known general coprocessor
2002 register. There must be a one instruction delay before INSN2
2003 if INSN2 reads that register, otherwise no delay is needed. */
2004 if (pinfo1
& INSN_WRITE_FPR_T
)
2006 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2009 else if (pinfo1
& INSN_WRITE_FPR_S
)
2011 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2016 /* Read-after-write dependencies on the control registers
2017 require a two-instruction gap. */
2018 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2019 && (pinfo2
& INSN_READ_COND_CODE
))
2022 /* We don't know exactly what INSN1 does. If INSN2 is
2023 also a coprocessor instruction, assume there must be
2024 a one instruction gap. */
2025 if (pinfo2
& INSN_COP
)
2030 /* Check for read-after-write dependencies on the coprocessor
2031 control registers in cases where INSN1 does not need a general
2032 coprocessor delay. This means that INSN1 is a floating point
2033 comparison instruction. */
2034 /* Itbl support may require additional care here. */
2035 else if (!cop_interlocks
2036 && (pinfo1
& INSN_WRITE_COND_CODE
)
2037 && (pinfo2
& INSN_READ_COND_CODE
))
2041 #undef INSN2_USES_REG
2046 /* Return the number of nops that would be needed to work around the
2047 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2048 the MAX_VR4130_NOPS instructions described by HISTORY. */
2051 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2052 const struct mips_cl_insn
*insn
)
2056 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2057 are not affected by the errata. */
2059 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2060 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2061 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2064 /* Search for the first MFLO or MFHI. */
2065 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2066 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2068 /* Extract the destination register. */
2069 if (mips_opts
.mips16
)
2070 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2072 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2074 /* No nops are needed if INSN reads that register. */
2075 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2078 /* ...or if any of the intervening instructions do. */
2079 for (j
= 0; j
< i
; j
++)
2080 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2083 return MAX_VR4130_NOPS
- i
;
2088 /* Return the number of nops that would be needed if instruction INSN
2089 immediately followed the MAX_NOPS instructions given by HISTORY,
2090 where HISTORY[0] is the most recent instruction. If INSN is null,
2091 return the worse-case number of nops for any instruction. */
2094 nops_for_insn (const struct mips_cl_insn
*history
,
2095 const struct mips_cl_insn
*insn
)
2097 int i
, nops
, tmp_nops
;
2100 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2101 if (!history
[i
].noreorder_p
)
2103 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2104 if (tmp_nops
> nops
)
2108 if (mips_fix_vr4130
)
2110 tmp_nops
= nops_for_vr4130 (history
, insn
);
2111 if (tmp_nops
> nops
)
2118 /* The variable arguments provide NUM_INSNS extra instructions that
2119 might be added to HISTORY. Return the largest number of nops that
2120 would be needed after the extended sequence. */
2123 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2126 struct mips_cl_insn buffer
[MAX_NOPS
];
2127 struct mips_cl_insn
*cursor
;
2130 va_start (args
, history
);
2131 cursor
= buffer
+ num_insns
;
2132 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2133 while (cursor
> buffer
)
2134 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2136 nops
= nops_for_insn (buffer
, NULL
);
2141 /* Like nops_for_insn, but if INSN is a branch, take into account the
2142 worst-case delay for the branch target. */
2145 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2146 const struct mips_cl_insn
*insn
)
2150 nops
= nops_for_insn (history
, insn
);
2151 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2152 | INSN_COND_BRANCH_DELAY
2153 | INSN_COND_BRANCH_LIKELY
))
2155 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2156 if (tmp_nops
> nops
)
2159 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2161 tmp_nops
= nops_for_sequence (1, history
, insn
);
2162 if (tmp_nops
> nops
)
2168 /* Output an instruction. IP is the instruction information.
2169 ADDRESS_EXPR is an operand of the instruction to be used with
2173 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2174 bfd_reloc_code_real_type
*reloc_type
)
2176 register unsigned long prev_pinfo
, pinfo
;
2177 relax_stateT prev_insn_frag_type
= 0;
2178 bfd_boolean relaxed_branch
= FALSE
;
2180 /* Mark instruction labels in mips16 mode. */
2181 mips16_mark_labels ();
2183 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2184 pinfo
= ip
->insn_mo
->pinfo
;
2186 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2188 /* There are a lot of optimizations we could do that we don't.
2189 In particular, we do not, in general, reorder instructions.
2190 If you use gcc with optimization, it will reorder
2191 instructions and generally do much more optimization then we
2192 do here; repeating all that work in the assembler would only
2193 benefit hand written assembly code, and does not seem worth
2195 int nops
= (mips_optimize
== 0
2196 ? nops_for_insn (history
, NULL
)
2197 : nops_for_insn_or_target (history
, ip
));
2201 unsigned long old_frag_offset
;
2204 old_frag
= frag_now
;
2205 old_frag_offset
= frag_now_fix ();
2207 for (i
= 0; i
< nops
; i
++)
2212 listing_prev_line ();
2213 /* We may be at the start of a variant frag. In case we
2214 are, make sure there is enough space for the frag
2215 after the frags created by listing_prev_line. The
2216 argument to frag_grow here must be at least as large
2217 as the argument to all other calls to frag_grow in
2218 this file. We don't have to worry about being in the
2219 middle of a variant frag, because the variants insert
2220 all needed nop instructions themselves. */
2224 mips_move_labels ();
2226 #ifndef NO_ECOFF_DEBUGGING
2227 if (ECOFF_DEBUGGING
)
2228 ecoff_fix_loc (old_frag
, old_frag_offset
);
2232 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2234 /* Work out how many nops in prev_nop_frag are needed by IP. */
2235 int nops
= nops_for_insn_or_target (history
, ip
);
2236 assert (nops
<= prev_nop_frag_holds
);
2238 /* Enforce NOPS as a minimum. */
2239 if (nops
> prev_nop_frag_required
)
2240 prev_nop_frag_required
= nops
;
2242 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2244 /* Settle for the current number of nops. Update the history
2245 accordingly (for the benefit of any future .set reorder code). */
2246 prev_nop_frag
= NULL
;
2247 insert_into_history (prev_nop_frag_since
,
2248 prev_nop_frag_holds
, NOP_INSN
);
2252 /* Allow this instruction to replace one of the nops that was
2253 tentatively added to prev_nop_frag. */
2254 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2255 prev_nop_frag_holds
--;
2256 prev_nop_frag_since
++;
2261 /* The value passed to dwarf2_emit_insn is the distance between
2262 the beginning of the current instruction and the address that
2263 should be recorded in the debug tables. For MIPS16 debug info
2264 we want to use ISA-encoded addresses, so we pass -1 for an
2265 address higher by one than the current. */
2266 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2269 /* Record the frag type before frag_var. */
2270 if (history
[0].frag
)
2271 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2274 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2275 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2276 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2277 && mips_relax_branch
2278 /* Don't try branch relaxation within .set nomacro, or within
2279 .set noat if we use $at for PIC computations. If it turns
2280 out that the branch was out-of-range, we'll get an error. */
2281 && !mips_opts
.warn_about_macros
2282 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2283 && !mips_opts
.mips16
)
2285 relaxed_branch
= TRUE
;
2286 add_relaxed_insn (ip
, (relaxed_branch_length
2288 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2289 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2292 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2293 pinfo
& INSN_COND_BRANCH_LIKELY
,
2294 pinfo
& INSN_WRITE_GPR_31
,
2296 address_expr
->X_add_symbol
,
2297 address_expr
->X_add_number
);
2298 *reloc_type
= BFD_RELOC_UNUSED
;
2300 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2302 /* We need to set up a variant frag. */
2303 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2304 add_relaxed_insn (ip
, 4, 0,
2306 (*reloc_type
- BFD_RELOC_UNUSED
,
2307 mips16_small
, mips16_ext
,
2308 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2309 history
[0].mips16_absolute_jump_p
),
2310 make_expr_symbol (address_expr
), 0);
2312 else if (mips_opts
.mips16
2314 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2316 /* Make sure there is enough room to swap this instruction with
2317 a following jump instruction. */
2319 add_fixed_insn (ip
);
2323 if (mips_opts
.mips16
2324 && mips_opts
.noreorder
2325 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2326 as_warn (_("extended instruction in delay slot"));
2328 if (mips_relax
.sequence
)
2330 /* If we've reached the end of this frag, turn it into a variant
2331 frag and record the information for the instructions we've
2333 if (frag_room () < 4)
2334 relax_close_frag ();
2335 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2338 if (mips_relax
.sequence
!= 2)
2339 mips_macro_warning
.sizes
[0] += 4;
2340 if (mips_relax
.sequence
!= 1)
2341 mips_macro_warning
.sizes
[1] += 4;
2343 if (mips_opts
.mips16
)
2346 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2348 add_fixed_insn (ip
);
2351 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2353 if (address_expr
->X_op
== O_constant
)
2357 switch (*reloc_type
)
2360 ip
->insn_opcode
|= address_expr
->X_add_number
;
2363 case BFD_RELOC_MIPS_HIGHEST
:
2364 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2365 ip
->insn_opcode
|= tmp
& 0xffff;
2368 case BFD_RELOC_MIPS_HIGHER
:
2369 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2370 ip
->insn_opcode
|= tmp
& 0xffff;
2373 case BFD_RELOC_HI16_S
:
2374 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2375 ip
->insn_opcode
|= tmp
& 0xffff;
2378 case BFD_RELOC_HI16
:
2379 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2382 case BFD_RELOC_UNUSED
:
2383 case BFD_RELOC_LO16
:
2384 case BFD_RELOC_MIPS_GOT_DISP
:
2385 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2388 case BFD_RELOC_MIPS_JMP
:
2389 if ((address_expr
->X_add_number
& 3) != 0)
2390 as_bad (_("jump to misaligned address (0x%lx)"),
2391 (unsigned long) address_expr
->X_add_number
);
2392 if (address_expr
->X_add_number
& ~0xfffffff)
2393 as_bad (_("jump address range overflow (0x%lx)"),
2394 (unsigned long) address_expr
->X_add_number
);
2395 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2398 case BFD_RELOC_MIPS16_JMP
:
2399 if ((address_expr
->X_add_number
& 3) != 0)
2400 as_bad (_("jump to misaligned address (0x%lx)"),
2401 (unsigned long) address_expr
->X_add_number
);
2402 if (address_expr
->X_add_number
& ~0xfffffff)
2403 as_bad (_("jump address range overflow (0x%lx)"),
2404 (unsigned long) address_expr
->X_add_number
);
2406 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2407 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2408 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2411 case BFD_RELOC_16_PCREL_S2
:
2418 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2421 reloc_howto_type
*howto
;
2424 /* In a compound relocation, it is the final (outermost)
2425 operator that determines the relocated field. */
2426 for (i
= 1; i
< 3; i
++)
2427 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2430 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2431 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2432 bfd_get_reloc_size (howto
),
2434 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2437 /* These relocations can have an addend that won't fit in
2438 4 octets for 64bit assembly. */
2440 && ! howto
->partial_inplace
2441 && (reloc_type
[0] == BFD_RELOC_16
2442 || reloc_type
[0] == BFD_RELOC_32
2443 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2444 || reloc_type
[0] == BFD_RELOC_HI16_S
2445 || reloc_type
[0] == BFD_RELOC_LO16
2446 || reloc_type
[0] == BFD_RELOC_GPREL16
2447 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2448 || reloc_type
[0] == BFD_RELOC_GPREL32
2449 || reloc_type
[0] == BFD_RELOC_64
2450 || reloc_type
[0] == BFD_RELOC_CTOR
2451 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2452 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2453 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2454 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2455 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2456 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2457 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2458 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2459 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2460 ip
->fixp
[0]->fx_no_overflow
= 1;
2462 if (mips_relax
.sequence
)
2464 if (mips_relax
.first_fixup
== 0)
2465 mips_relax
.first_fixup
= ip
->fixp
[0];
2467 else if (reloc_needs_lo_p (*reloc_type
))
2469 struct mips_hi_fixup
*hi_fixup
;
2471 /* Reuse the last entry if it already has a matching %lo. */
2472 hi_fixup
= mips_hi_fixup_list
;
2474 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2476 hi_fixup
= ((struct mips_hi_fixup
*)
2477 xmalloc (sizeof (struct mips_hi_fixup
)));
2478 hi_fixup
->next
= mips_hi_fixup_list
;
2479 mips_hi_fixup_list
= hi_fixup
;
2481 hi_fixup
->fixp
= ip
->fixp
[0];
2482 hi_fixup
->seg
= now_seg
;
2485 /* Add fixups for the second and third relocations, if given.
2486 Note that the ABI allows the second relocation to be
2487 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2488 moment we only use RSS_UNDEF, but we could add support
2489 for the others if it ever becomes necessary. */
2490 for (i
= 1; i
< 3; i
++)
2491 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2493 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2494 ip
->fixp
[0]->fx_size
, NULL
, 0,
2495 FALSE
, reloc_type
[i
]);
2497 /* Use fx_tcbit to mark compound relocs. */
2498 ip
->fixp
[0]->fx_tcbit
= 1;
2499 ip
->fixp
[i
]->fx_tcbit
= 1;
2505 /* Update the register mask information. */
2506 if (! mips_opts
.mips16
)
2508 if (pinfo
& INSN_WRITE_GPR_D
)
2509 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2510 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2511 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2512 if (pinfo
& INSN_READ_GPR_S
)
2513 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2514 if (pinfo
& INSN_WRITE_GPR_31
)
2515 mips_gprmask
|= 1 << RA
;
2516 if (pinfo
& INSN_WRITE_FPR_D
)
2517 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2518 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2519 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2520 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2521 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2522 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2523 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2524 if (pinfo
& INSN_COP
)
2526 /* We don't keep enough information to sort these cases out.
2527 The itbl support does keep this information however, although
2528 we currently don't support itbl fprmats as part of the cop
2529 instruction. May want to add this support in the future. */
2531 /* Never set the bit for $0, which is always zero. */
2532 mips_gprmask
&= ~1 << 0;
2536 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2537 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2538 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2539 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2540 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2541 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2542 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2543 mips_gprmask
|= 1 << TREG
;
2544 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2545 mips_gprmask
|= 1 << SP
;
2546 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2547 mips_gprmask
|= 1 << RA
;
2548 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2549 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2550 if (pinfo
& MIPS16_INSN_READ_Z
)
2551 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2552 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2553 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2556 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2558 /* Filling the branch delay slot is more complex. We try to
2559 switch the branch with the previous instruction, which we can
2560 do if the previous instruction does not set up a condition
2561 that the branch tests and if the branch is not itself the
2562 target of any branch. */
2563 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2564 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2566 if (mips_optimize
< 2
2567 /* If we have seen .set volatile or .set nomove, don't
2569 || mips_opts
.nomove
!= 0
2570 /* We can't swap if the previous instruction's position
2572 || history
[0].fixed_p
2573 /* If the previous previous insn was in a .set
2574 noreorder, we can't swap. Actually, the MIPS
2575 assembler will swap in this situation. However, gcc
2576 configured -with-gnu-as will generate code like
2582 in which we can not swap the bne and INSN. If gcc is
2583 not configured -with-gnu-as, it does not output the
2585 || history
[1].noreorder_p
2586 /* If the branch is itself the target of a branch, we
2587 can not swap. We cheat on this; all we check for is
2588 whether there is a label on this instruction. If
2589 there are any branches to anything other than a
2590 label, users must use .set noreorder. */
2591 || insn_labels
!= NULL
2592 /* If the previous instruction is in a variant frag
2593 other than this branch's one, we cannot do the swap.
2594 This does not apply to the mips16, which uses variant
2595 frags for different purposes. */
2596 || (! mips_opts
.mips16
2597 && prev_insn_frag_type
== rs_machine_dependent
)
2598 /* Check for conflicts between the branch and the instructions
2599 before the candidate delay slot. */
2600 || nops_for_insn (history
+ 1, ip
) > 0
2601 /* Check for conflicts between the swapped sequence and the
2602 target of the branch. */
2603 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2604 /* We do not swap with a trap instruction, since it
2605 complicates trap handlers to have the trap
2606 instruction be in a delay slot. */
2607 || (prev_pinfo
& INSN_TRAP
)
2608 /* If the branch reads a register that the previous
2609 instruction sets, we can not swap. */
2610 || (! mips_opts
.mips16
2611 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2612 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2614 || (! mips_opts
.mips16
2615 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2616 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2618 || (mips_opts
.mips16
2619 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2621 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2623 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2625 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2627 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2629 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2631 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2632 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2633 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2634 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2635 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2636 && insn_uses_reg (ip
,
2637 MIPS16OP_EXTRACT_REG32R
2638 (history
[0].insn_opcode
),
2640 /* If the branch writes a register that the previous
2641 instruction sets, we can not swap (we know that
2642 branches write only to RD or to $31). */
2643 || (! mips_opts
.mips16
2644 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2645 && (((pinfo
& INSN_WRITE_GPR_D
)
2646 && (EXTRACT_OPERAND (RT
, history
[0])
2647 == EXTRACT_OPERAND (RD
, *ip
)))
2648 || ((pinfo
& INSN_WRITE_GPR_31
)
2649 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2650 || (! mips_opts
.mips16
2651 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2652 && (((pinfo
& INSN_WRITE_GPR_D
)
2653 && (EXTRACT_OPERAND (RD
, history
[0])
2654 == EXTRACT_OPERAND (RD
, *ip
)))
2655 || ((pinfo
& INSN_WRITE_GPR_31
)
2656 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2657 || (mips_opts
.mips16
2658 && (pinfo
& MIPS16_INSN_WRITE_31
)
2659 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2660 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2661 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2663 /* If the branch writes a register that the previous
2664 instruction reads, we can not swap (we know that
2665 branches only write to RD or to $31). */
2666 || (! mips_opts
.mips16
2667 && (pinfo
& INSN_WRITE_GPR_D
)
2668 && insn_uses_reg (&history
[0],
2669 EXTRACT_OPERAND (RD
, *ip
),
2671 || (! mips_opts
.mips16
2672 && (pinfo
& INSN_WRITE_GPR_31
)
2673 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2674 || (mips_opts
.mips16
2675 && (pinfo
& MIPS16_INSN_WRITE_31
)
2676 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2677 /* If one instruction sets a condition code and the
2678 other one uses a condition code, we can not swap. */
2679 || ((pinfo
& INSN_READ_COND_CODE
)
2680 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2681 || ((pinfo
& INSN_WRITE_COND_CODE
)
2682 && (prev_pinfo
& INSN_READ_COND_CODE
))
2683 /* If the previous instruction uses the PC, we can not
2685 || (mips_opts
.mips16
2686 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2687 /* If the previous instruction had a fixup in mips16
2688 mode, we can not swap. This normally means that the
2689 previous instruction was a 4 byte branch anyhow. */
2690 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2691 /* If the previous instruction is a sync, sync.l, or
2692 sync.p, we can not swap. */
2693 || (prev_pinfo
& INSN_SYNC
))
2695 /* We could do even better for unconditional branches to
2696 portions of this object file; we could pick up the
2697 instruction at the destination, put it in the delay
2698 slot, and bump the destination address. */
2699 insert_into_history (0, 1, ip
);
2701 if (mips_relax
.sequence
)
2702 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2706 /* It looks like we can actually do the swap. */
2707 struct mips_cl_insn delay
= history
[0];
2708 if (mips_opts
.mips16
)
2710 if (delay
.frag
== ip
->frag
)
2712 move_insn (ip
, delay
.frag
, delay
.where
);
2713 move_insn (&delay
, ip
->frag
, delay
.where
2714 + insn_length (ip
));
2716 else if (insn_length (ip
) == insn_length (&delay
))
2718 move_insn (&delay
, ip
->frag
, ip
->where
);
2719 move_insn (ip
, history
[0].frag
, history
[0].where
);
2723 add_fixed_insn (NOP_INSN
);
2727 else if (relaxed_branch
)
2729 /* Add the delay slot instruction to the end of the
2730 current frag and shrink the fixed part of the
2731 original frag. If the branch occupies the tail of
2732 the latter, move it backwards to cover the gap. */
2733 delay
.frag
->fr_fix
-= 4;
2734 if (delay
.frag
== ip
->frag
)
2735 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2736 add_fixed_insn (&delay
);
2740 move_insn (&delay
, ip
->frag
, ip
->where
);
2741 move_insn (ip
, history
[0].frag
, history
[0].where
);
2745 insert_into_history (0, 1, &delay
);
2748 /* If that was an unconditional branch, forget the previous
2749 insn information. */
2750 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2751 mips_no_prev_insn ();
2753 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2755 /* We don't yet optimize a branch likely. What we should do
2756 is look at the target, copy the instruction found there
2757 into the delay slot, and increment the branch to jump to
2758 the next instruction. */
2759 insert_into_history (0, 1, ip
);
2763 insert_into_history (0, 1, ip
);
2766 insert_into_history (0, 1, ip
);
2768 /* We just output an insn, so the next one doesn't have a label. */
2769 mips_clear_insn_labels ();
2772 /* Forget that there was any previous instruction or label. */
2775 mips_no_prev_insn (void)
2777 prev_nop_frag
= NULL
;
2778 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2779 mips_clear_insn_labels ();
2782 /* This function must be called before we emit something other than
2783 instructions. It is like mips_no_prev_insn except that it inserts
2784 any NOPS that might be needed by previous instructions. */
2787 mips_emit_delays (void)
2789 if (! mips_opts
.noreorder
)
2791 int nops
= nops_for_insn (history
, NULL
);
2795 add_fixed_insn (NOP_INSN
);
2796 mips_move_labels ();
2799 mips_no_prev_insn ();
2802 /* Start a (possibly nested) noreorder block. */
2805 start_noreorder (void)
2807 if (mips_opts
.noreorder
== 0)
2812 /* None of the instructions before the .set noreorder can be moved. */
2813 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2814 history
[i
].fixed_p
= 1;
2816 /* Insert any nops that might be needed between the .set noreorder
2817 block and the previous instructions. We will later remove any
2818 nops that turn out not to be needed. */
2819 nops
= nops_for_insn (history
, NULL
);
2822 if (mips_optimize
!= 0)
2824 /* Record the frag which holds the nop instructions, so
2825 that we can remove them if we don't need them. */
2826 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2827 prev_nop_frag
= frag_now
;
2828 prev_nop_frag_holds
= nops
;
2829 prev_nop_frag_required
= 0;
2830 prev_nop_frag_since
= 0;
2833 for (; nops
> 0; --nops
)
2834 add_fixed_insn (NOP_INSN
);
2836 /* Move on to a new frag, so that it is safe to simply
2837 decrease the size of prev_nop_frag. */
2838 frag_wane (frag_now
);
2840 mips_move_labels ();
2842 mips16_mark_labels ();
2843 mips_clear_insn_labels ();
2845 mips_opts
.noreorder
++;
2846 mips_any_noreorder
= 1;
2849 /* End a nested noreorder block. */
2852 end_noreorder (void)
2854 mips_opts
.noreorder
--;
2855 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2857 /* Commit to inserting prev_nop_frag_required nops and go back to
2858 handling nop insertion the .set reorder way. */
2859 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2860 * (mips_opts
.mips16
? 2 : 4));
2861 insert_into_history (prev_nop_frag_since
,
2862 prev_nop_frag_required
, NOP_INSN
);
2863 prev_nop_frag
= NULL
;
2867 /* Set up global variables for the start of a new macro. */
2872 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2873 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2874 && (history
[0].insn_mo
->pinfo
2875 & (INSN_UNCOND_BRANCH_DELAY
2876 | INSN_COND_BRANCH_DELAY
2877 | INSN_COND_BRANCH_LIKELY
)) != 0);
2880 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2881 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2882 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2885 macro_warning (relax_substateT subtype
)
2887 if (subtype
& RELAX_DELAY_SLOT
)
2888 return _("Macro instruction expanded into multiple instructions"
2889 " in a branch delay slot");
2890 else if (subtype
& RELAX_NOMACRO
)
2891 return _("Macro instruction expanded into multiple instructions");
2896 /* Finish up a macro. Emit warnings as appropriate. */
2901 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2903 relax_substateT subtype
;
2905 /* Set up the relaxation warning flags. */
2907 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2908 subtype
|= RELAX_SECOND_LONGER
;
2909 if (mips_opts
.warn_about_macros
)
2910 subtype
|= RELAX_NOMACRO
;
2911 if (mips_macro_warning
.delay_slot_p
)
2912 subtype
|= RELAX_DELAY_SLOT
;
2914 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2916 /* Either the macro has a single implementation or both
2917 implementations are longer than 4 bytes. Emit the
2919 const char *msg
= macro_warning (subtype
);
2925 /* One implementation might need a warning but the other
2926 definitely doesn't. */
2927 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2932 /* Read a macro's relocation codes from *ARGS and store them in *R.
2933 The first argument in *ARGS will be either the code for a single
2934 relocation or -1 followed by the three codes that make up a
2935 composite relocation. */
2938 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2942 next
= va_arg (*args
, int);
2944 r
[0] = (bfd_reloc_code_real_type
) next
;
2946 for (i
= 0; i
< 3; i
++)
2947 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2950 /* Build an instruction created by a macro expansion. This is passed
2951 a pointer to the count of instructions created so far, an
2952 expression, the name of the instruction to build, an operand format
2953 string, and corresponding arguments. */
2956 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2958 const struct mips_opcode
*mo
;
2959 struct mips_cl_insn insn
;
2960 bfd_reloc_code_real_type r
[3];
2963 va_start (args
, fmt
);
2965 if (mips_opts
.mips16
)
2967 mips16_macro_build (ep
, name
, fmt
, args
);
2972 r
[0] = BFD_RELOC_UNUSED
;
2973 r
[1] = BFD_RELOC_UNUSED
;
2974 r
[2] = BFD_RELOC_UNUSED
;
2975 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2977 assert (strcmp (name
, mo
->name
) == 0);
2979 /* Search until we get a match for NAME. It is assumed here that
2980 macros will never generate MDMX or MIPS-3D instructions. */
2981 while (strcmp (fmt
, mo
->args
) != 0
2982 || mo
->pinfo
== INSN_MACRO
2983 || !OPCODE_IS_MEMBER (mo
,
2985 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2987 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2991 assert (strcmp (name
, mo
->name
) == 0);
2994 create_insn (&insn
, mo
);
3012 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3017 /* Note that in the macro case, these arguments are already
3018 in MSB form. (When handling the instruction in the
3019 non-macro case, these arguments are sizes from which
3020 MSB values must be calculated.) */
3021 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3027 /* Note that in the macro case, these arguments are already
3028 in MSBD form. (When handling the instruction in the
3029 non-macro case, these arguments are sizes from which
3030 MSBD values must be calculated.) */
3031 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3042 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3046 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3051 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3057 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3062 int tmp
= va_arg (args
, int);
3064 INSERT_OPERAND (RT
, insn
, tmp
);
3065 INSERT_OPERAND (RD
, insn
, tmp
);
3071 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3078 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3082 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3086 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3090 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3094 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3101 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3107 macro_read_relocs (&args
, r
);
3108 assert (*r
== BFD_RELOC_GPREL16
3109 || *r
== BFD_RELOC_MIPS_LITERAL
3110 || *r
== BFD_RELOC_MIPS_HIGHER
3111 || *r
== BFD_RELOC_HI16_S
3112 || *r
== BFD_RELOC_LO16
3113 || *r
== BFD_RELOC_MIPS_GOT16
3114 || *r
== BFD_RELOC_MIPS_CALL16
3115 || *r
== BFD_RELOC_MIPS_GOT_DISP
3116 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3117 || *r
== BFD_RELOC_MIPS_GOT_OFST
3118 || *r
== BFD_RELOC_MIPS_GOT_LO16
3119 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3123 macro_read_relocs (&args
, r
);
3125 && (ep
->X_op
== O_constant
3126 || (ep
->X_op
== O_symbol
3127 && (*r
== BFD_RELOC_MIPS_HIGHEST
3128 || *r
== BFD_RELOC_HI16_S
3129 || *r
== BFD_RELOC_HI16
3130 || *r
== BFD_RELOC_GPREL16
3131 || *r
== BFD_RELOC_MIPS_GOT_HI16
3132 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3136 assert (ep
!= NULL
);
3138 * This allows macro() to pass an immediate expression for
3139 * creating short branches without creating a symbol.
3140 * Note that the expression still might come from the assembly
3141 * input, in which case the value is not checked for range nor
3142 * is a relocation entry generated (yuck).
3144 if (ep
->X_op
== O_constant
)
3146 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3150 *r
= BFD_RELOC_16_PCREL_S2
;
3154 assert (ep
!= NULL
);
3155 *r
= BFD_RELOC_MIPS_JMP
;
3159 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3168 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3170 append_insn (&insn
, ep
, r
);
3174 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3177 struct mips_opcode
*mo
;
3178 struct mips_cl_insn insn
;
3179 bfd_reloc_code_real_type r
[3]
3180 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3182 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3184 assert (strcmp (name
, mo
->name
) == 0);
3186 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3190 assert (strcmp (name
, mo
->name
) == 0);
3193 create_insn (&insn
, mo
);
3211 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3216 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3220 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3224 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3234 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3241 regno
= va_arg (args
, int);
3242 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3243 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3264 assert (ep
!= NULL
);
3266 if (ep
->X_op
!= O_constant
)
3267 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3270 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3271 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3274 *r
= BFD_RELOC_UNUSED
;
3280 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3287 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3289 append_insn (&insn
, ep
, r
);
3293 * Sign-extend 32-bit mode constants that have bit 31 set and all
3294 * higher bits unset.
3297 normalize_constant_expr (expressionS
*ex
)
3299 if (ex
->X_op
== O_constant
3300 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3301 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3306 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3307 * all higher bits unset.
3310 normalize_address_expr (expressionS
*ex
)
3312 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3313 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3314 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3315 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3320 * Generate a "jalr" instruction with a relocation hint to the called
3321 * function. This occurs in NewABI PIC code.
3324 macro_build_jalr (expressionS
*ep
)
3333 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3335 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3336 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3340 * Generate a "lui" instruction.
3343 macro_build_lui (expressionS
*ep
, int regnum
)
3345 expressionS high_expr
;
3346 const struct mips_opcode
*mo
;
3347 struct mips_cl_insn insn
;
3348 bfd_reloc_code_real_type r
[3]
3349 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3350 const char *name
= "lui";
3351 const char *fmt
= "t,u";
3353 assert (! mips_opts
.mips16
);
3357 if (high_expr
.X_op
== O_constant
)
3359 /* we can compute the instruction now without a relocation entry */
3360 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3362 *r
= BFD_RELOC_UNUSED
;
3366 assert (ep
->X_op
== O_symbol
);
3367 /* _gp_disp is a special case, used from s_cpload.
3368 __gnu_local_gp is used if mips_no_shared. */
3369 assert (mips_pic
== NO_PIC
3371 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3372 || (! mips_in_shared
3373 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3374 "__gnu_local_gp") == 0));
3375 *r
= BFD_RELOC_HI16_S
;
3378 mo
= hash_find (op_hash
, name
);
3379 assert (strcmp (name
, mo
->name
) == 0);
3380 assert (strcmp (fmt
, mo
->args
) == 0);
3381 create_insn (&insn
, mo
);
3383 insn
.insn_opcode
= insn
.insn_mo
->match
;
3384 INSERT_OPERAND (RT
, insn
, regnum
);
3385 if (*r
== BFD_RELOC_UNUSED
)
3387 insn
.insn_opcode
|= high_expr
.X_add_number
;
3388 append_insn (&insn
, NULL
, r
);
3391 append_insn (&insn
, &high_expr
, r
);
3394 /* Generate a sequence of instructions to do a load or store from a constant
3395 offset off of a base register (breg) into/from a target register (treg),
3396 using AT if necessary. */
3398 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3399 int treg
, int breg
, int dbl
)
3401 assert (ep
->X_op
== O_constant
);
3403 /* Sign-extending 32-bit constants makes their handling easier. */
3405 normalize_constant_expr (ep
);
3407 /* Right now, this routine can only handle signed 32-bit constants. */
3408 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3409 as_warn (_("operand overflow"));
3411 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3413 /* Signed 16-bit offset will fit in the op. Easy! */
3414 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3418 /* 32-bit offset, need multiple instructions and AT, like:
3419 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3420 addu $tempreg,$tempreg,$breg
3421 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3422 to handle the complete offset. */
3423 macro_build_lui (ep
, AT
);
3424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3425 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3428 as_bad (_("Macro used $at after \".set noat\""));
3433 * Generates code to set the $at register to true (one)
3434 * if reg is less than the immediate expression.
3437 set_at (int reg
, int unsignedp
)
3439 if (imm_expr
.X_op
== O_constant
3440 && imm_expr
.X_add_number
>= -0x8000
3441 && imm_expr
.X_add_number
< 0x8000)
3442 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3443 AT
, reg
, BFD_RELOC_LO16
);
3446 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3447 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3451 /* Warn if an expression is not a constant. */
3454 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3456 if (ex
->X_op
== O_big
)
3457 as_bad (_("unsupported large constant"));
3458 else if (ex
->X_op
!= O_constant
)
3459 as_bad (_("Instruction %s requires absolute expression"),
3462 if (HAVE_32BIT_GPRS
)
3463 normalize_constant_expr (ex
);
3466 /* Count the leading zeroes by performing a binary chop. This is a
3467 bulky bit of source, but performance is a LOT better for the
3468 majority of values than a simple loop to count the bits:
3469 for (lcnt = 0; (lcnt < 32); lcnt++)
3470 if ((v) & (1 << (31 - lcnt)))
3472 However it is not code size friendly, and the gain will drop a bit
3473 on certain cached systems.
3475 #define COUNT_TOP_ZEROES(v) \
3476 (((v) & ~0xffff) == 0 \
3477 ? ((v) & ~0xff) == 0 \
3478 ? ((v) & ~0xf) == 0 \
3479 ? ((v) & ~0x3) == 0 \
3480 ? ((v) & ~0x1) == 0 \
3485 : ((v) & ~0x7) == 0 \
3488 : ((v) & ~0x3f) == 0 \
3489 ? ((v) & ~0x1f) == 0 \
3492 : ((v) & ~0x7f) == 0 \
3495 : ((v) & ~0xfff) == 0 \
3496 ? ((v) & ~0x3ff) == 0 \
3497 ? ((v) & ~0x1ff) == 0 \
3500 : ((v) & ~0x7ff) == 0 \
3503 : ((v) & ~0x3fff) == 0 \
3504 ? ((v) & ~0x1fff) == 0 \
3507 : ((v) & ~0x7fff) == 0 \
3510 : ((v) & ~0xffffff) == 0 \
3511 ? ((v) & ~0xfffff) == 0 \
3512 ? ((v) & ~0x3ffff) == 0 \
3513 ? ((v) & ~0x1ffff) == 0 \
3516 : ((v) & ~0x7ffff) == 0 \
3519 : ((v) & ~0x3fffff) == 0 \
3520 ? ((v) & ~0x1fffff) == 0 \
3523 : ((v) & ~0x7fffff) == 0 \
3526 : ((v) & ~0xfffffff) == 0 \
3527 ? ((v) & ~0x3ffffff) == 0 \
3528 ? ((v) & ~0x1ffffff) == 0 \
3531 : ((v) & ~0x7ffffff) == 0 \
3534 : ((v) & ~0x3fffffff) == 0 \
3535 ? ((v) & ~0x1fffffff) == 0 \
3538 : ((v) & ~0x7fffffff) == 0 \
3543 * This routine generates the least number of instructions necessary to load
3544 * an absolute expression value into a register.
3547 load_register (int reg
, expressionS
*ep
, int dbl
)
3550 expressionS hi32
, lo32
;
3552 if (ep
->X_op
!= O_big
)
3554 assert (ep
->X_op
== O_constant
);
3556 /* Sign-extending 32-bit constants makes their handling easier. */
3558 normalize_constant_expr (ep
);
3560 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3562 /* We can handle 16 bit signed values with an addiu to
3563 $zero. No need to ever use daddiu here, since $zero and
3564 the result are always correct in 32 bit mode. */
3565 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3568 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3570 /* We can handle 16 bit unsigned values with an ori to
3572 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3575 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3577 /* 32 bit values require an lui. */
3578 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3579 if ((ep
->X_add_number
& 0xffff) != 0)
3580 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3585 /* The value is larger than 32 bits. */
3587 if (!dbl
|| HAVE_32BIT_GPRS
)
3591 sprintf_vma (value
, ep
->X_add_number
);
3592 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3593 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3597 if (ep
->X_op
!= O_big
)
3600 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3601 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3602 hi32
.X_add_number
&= 0xffffffff;
3604 lo32
.X_add_number
&= 0xffffffff;
3608 assert (ep
->X_add_number
> 2);
3609 if (ep
->X_add_number
== 3)
3610 generic_bignum
[3] = 0;
3611 else if (ep
->X_add_number
> 4)
3612 as_bad (_("Number larger than 64 bits"));
3613 lo32
.X_op
= O_constant
;
3614 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3615 hi32
.X_op
= O_constant
;
3616 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3619 if (hi32
.X_add_number
== 0)
3624 unsigned long hi
, lo
;
3626 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3628 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3630 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3633 if (lo32
.X_add_number
& 0x80000000)
3635 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3636 if (lo32
.X_add_number
& 0xffff)
3637 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3642 /* Check for 16bit shifted constant. We know that hi32 is
3643 non-zero, so start the mask on the first bit of the hi32
3648 unsigned long himask
, lomask
;
3652 himask
= 0xffff >> (32 - shift
);
3653 lomask
= (0xffff << shift
) & 0xffffffff;
3657 himask
= 0xffff << (shift
- 32);
3660 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3661 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3665 tmp
.X_op
= O_constant
;
3667 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3668 | (lo32
.X_add_number
>> shift
));
3670 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3671 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3672 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3673 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3678 while (shift
<= (64 - 16));
3680 /* Find the bit number of the lowest one bit, and store the
3681 shifted value in hi/lo. */
3682 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3683 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3687 while ((lo
& 1) == 0)
3692 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3698 while ((hi
& 1) == 0)
3707 /* Optimize if the shifted value is a (power of 2) - 1. */
3708 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3709 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3711 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3716 /* This instruction will set the register to be all
3718 tmp
.X_op
= O_constant
;
3719 tmp
.X_add_number
= (offsetT
) -1;
3720 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3724 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3725 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3727 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3728 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3733 /* Sign extend hi32 before calling load_register, because we can
3734 generally get better code when we load a sign extended value. */
3735 if ((hi32
.X_add_number
& 0x80000000) != 0)
3736 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3737 load_register (reg
, &hi32
, 0);
3740 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3744 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3752 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3754 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3755 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3761 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3765 mid16
.X_add_number
>>= 16;
3766 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3767 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3770 if ((lo32
.X_add_number
& 0xffff) != 0)
3771 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3775 load_delay_nop (void)
3777 if (!gpr_interlocks
)
3778 macro_build (NULL
, "nop", "");
3781 /* Load an address into a register. */
3784 load_address (int reg
, expressionS
*ep
, int *used_at
)
3786 if (ep
->X_op
!= O_constant
3787 && ep
->X_op
!= O_symbol
)
3789 as_bad (_("expression too complex"));
3790 ep
->X_op
= O_constant
;
3793 if (ep
->X_op
== O_constant
)
3795 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3799 if (mips_pic
== NO_PIC
)
3801 /* If this is a reference to a GP relative symbol, we want
3802 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3804 lui $reg,<sym> (BFD_RELOC_HI16_S)
3805 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3806 If we have an addend, we always use the latter form.
3808 With 64bit address space and a usable $at we want
3809 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3810 lui $at,<sym> (BFD_RELOC_HI16_S)
3811 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3812 daddiu $at,<sym> (BFD_RELOC_LO16)
3816 If $at is already in use, we use a path which is suboptimal
3817 on superscalar processors.
3818 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3819 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3821 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3823 daddiu $reg,<sym> (BFD_RELOC_LO16)
3825 For GP relative symbols in 64bit address space we can use
3826 the same sequence as in 32bit address space. */
3827 if (HAVE_64BIT_SYMBOLS
)
3829 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3830 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3832 relax_start (ep
->X_add_symbol
);
3833 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3834 mips_gp_register
, BFD_RELOC_GPREL16
);
3838 if (*used_at
== 0 && !mips_opts
.noat
)
3840 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3841 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3842 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3843 BFD_RELOC_MIPS_HIGHER
);
3844 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3845 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3846 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3851 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3852 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3853 BFD_RELOC_MIPS_HIGHER
);
3854 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3855 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3856 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3857 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3860 if (mips_relax
.sequence
)
3865 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3866 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3868 relax_start (ep
->X_add_symbol
);
3869 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3870 mips_gp_register
, BFD_RELOC_GPREL16
);
3873 macro_build_lui (ep
, reg
);
3874 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3875 reg
, reg
, BFD_RELOC_LO16
);
3876 if (mips_relax
.sequence
)
3880 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3884 /* If this is a reference to an external symbol, we want
3885 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3887 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3889 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3890 If there is a constant, it must be added in after.
3892 If we have NewABI, we want
3893 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3894 unless we're referencing a global symbol with a non-zero
3895 offset, in which case cst must be added separately. */
3898 if (ep
->X_add_number
)
3900 ex
.X_add_number
= ep
->X_add_number
;
3901 ep
->X_add_number
= 0;
3902 relax_start (ep
->X_add_symbol
);
3903 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3904 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3905 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3907 ex
.X_op
= O_constant
;
3908 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3909 reg
, reg
, BFD_RELOC_LO16
);
3910 ep
->X_add_number
= ex
.X_add_number
;
3913 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3914 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3915 if (mips_relax
.sequence
)
3920 ex
.X_add_number
= ep
->X_add_number
;
3921 ep
->X_add_number
= 0;
3922 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3923 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3925 relax_start (ep
->X_add_symbol
);
3927 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3931 if (ex
.X_add_number
!= 0)
3933 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3934 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3935 ex
.X_op
= O_constant
;
3936 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3937 reg
, reg
, BFD_RELOC_LO16
);
3941 else if (mips_pic
== SVR4_PIC
)
3945 /* This is the large GOT case. If this is a reference to an
3946 external symbol, we want
3947 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3949 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3951 Otherwise, for a reference to a local symbol in old ABI, we want
3952 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3954 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3955 If there is a constant, it must be added in after.
3957 In the NewABI, for local symbols, with or without offsets, we want:
3958 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3959 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3963 ex
.X_add_number
= ep
->X_add_number
;
3964 ep
->X_add_number
= 0;
3965 relax_start (ep
->X_add_symbol
);
3966 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3967 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3968 reg
, reg
, mips_gp_register
);
3969 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3970 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3971 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3972 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3973 else if (ex
.X_add_number
)
3975 ex
.X_op
= O_constant
;
3976 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3980 ep
->X_add_number
= ex
.X_add_number
;
3982 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3983 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3984 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3985 BFD_RELOC_MIPS_GOT_OFST
);
3990 ex
.X_add_number
= ep
->X_add_number
;
3991 ep
->X_add_number
= 0;
3992 relax_start (ep
->X_add_symbol
);
3993 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3995 reg
, reg
, mips_gp_register
);
3996 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3997 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3999 if (reg_needs_delay (mips_gp_register
))
4001 /* We need a nop before loading from $gp. This special
4002 check is required because the lui which starts the main
4003 instruction stream does not refer to $gp, and so will not
4004 insert the nop which may be required. */
4005 macro_build (NULL
, "nop", "");
4007 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4008 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4010 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4014 if (ex
.X_add_number
!= 0)
4016 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4017 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4018 ex
.X_op
= O_constant
;
4019 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4027 if (mips_opts
.noat
&& *used_at
== 1)
4028 as_bad (_("Macro used $at after \".set noat\""));
4031 /* Move the contents of register SOURCE into register DEST. */
4034 move_register (int dest
, int source
)
4036 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4040 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4041 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4042 The two alternatives are:
4044 Global symbol Local sybmol
4045 ------------- ------------
4046 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4048 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4050 load_got_offset emits the first instruction and add_got_offset
4051 emits the second for a 16-bit offset or add_got_offset_hilo emits
4052 a sequence to add a 32-bit offset using a scratch register. */
4055 load_got_offset (int dest
, expressionS
*local
)
4060 global
.X_add_number
= 0;
4062 relax_start (local
->X_add_symbol
);
4063 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4064 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4066 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4067 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4072 add_got_offset (int dest
, expressionS
*local
)
4076 global
.X_op
= O_constant
;
4077 global
.X_op_symbol
= NULL
;
4078 global
.X_add_symbol
= NULL
;
4079 global
.X_add_number
= local
->X_add_number
;
4081 relax_start (local
->X_add_symbol
);
4082 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4083 dest
, dest
, BFD_RELOC_LO16
);
4085 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4090 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4093 int hold_mips_optimize
;
4095 global
.X_op
= O_constant
;
4096 global
.X_op_symbol
= NULL
;
4097 global
.X_add_symbol
= NULL
;
4098 global
.X_add_number
= local
->X_add_number
;
4100 relax_start (local
->X_add_symbol
);
4101 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4103 /* Set mips_optimize around the lui instruction to avoid
4104 inserting an unnecessary nop after the lw. */
4105 hold_mips_optimize
= mips_optimize
;
4107 macro_build_lui (&global
, tmp
);
4108 mips_optimize
= hold_mips_optimize
;
4109 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4117 * This routine implements the seemingly endless macro or synthesized
4118 * instructions and addressing modes in the mips assembly language. Many
4119 * of these macros are simple and are similar to each other. These could
4120 * probably be handled by some kind of table or grammar approach instead of
4121 * this verbose method. Others are not simple macros but are more like
4122 * optimizing code generation.
4123 * One interesting optimization is when several store macros appear
4124 * consecutively that would load AT with the upper half of the same address.
4125 * The ensuing load upper instructions are ommited. This implies some kind
4126 * of global optimization. We currently only optimize within a single macro.
4127 * For many of the load and store macros if the address is specified as a
4128 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4129 * first load register 'at' with zero and use it as the base register. The
4130 * mips assembler simply uses register $zero. Just one tiny optimization
4134 macro (struct mips_cl_insn
*ip
)
4136 register int treg
, sreg
, dreg
, breg
;
4152 bfd_reloc_code_real_type r
;
4153 int hold_mips_optimize
;
4155 assert (! mips_opts
.mips16
);
4157 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4158 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4159 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4160 mask
= ip
->insn_mo
->mask
;
4162 expr1
.X_op
= O_constant
;
4163 expr1
.X_op_symbol
= NULL
;
4164 expr1
.X_add_symbol
= NULL
;
4165 expr1
.X_add_number
= 1;
4179 expr1
.X_add_number
= 8;
4180 macro_build (&expr1
, "bgez", "s,p", sreg
);
4182 macro_build (NULL
, "nop", "", 0);
4184 move_register (dreg
, sreg
);
4185 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4208 if (imm_expr
.X_op
== O_constant
4209 && imm_expr
.X_add_number
>= -0x8000
4210 && imm_expr
.X_add_number
< 0x8000)
4212 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4216 load_register (AT
, &imm_expr
, dbl
);
4217 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4236 if (imm_expr
.X_op
== O_constant
4237 && imm_expr
.X_add_number
>= 0
4238 && imm_expr
.X_add_number
< 0x10000)
4240 if (mask
!= M_NOR_I
)
4241 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4244 macro_build (&imm_expr
, "ori", "t,r,i",
4245 treg
, sreg
, BFD_RELOC_LO16
);
4246 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4252 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4253 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4270 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4272 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4276 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4277 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4285 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4290 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4294 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4295 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4301 /* check for > max integer */
4302 maxnum
= 0x7fffffff;
4303 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4310 if (imm_expr
.X_op
== O_constant
4311 && imm_expr
.X_add_number
>= maxnum
4312 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4315 /* result is always false */
4317 macro_build (NULL
, "nop", "", 0);
4319 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4322 if (imm_expr
.X_op
!= O_constant
)
4323 as_bad (_("Unsupported large constant"));
4324 ++imm_expr
.X_add_number
;
4328 if (mask
== M_BGEL_I
)
4330 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4332 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4335 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4337 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4340 maxnum
= 0x7fffffff;
4341 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4348 maxnum
= - maxnum
- 1;
4349 if (imm_expr
.X_op
== O_constant
4350 && imm_expr
.X_add_number
<= maxnum
4351 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4354 /* result is always true */
4355 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4356 macro_build (&offset_expr
, "b", "p");
4361 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4371 macro_build (&offset_expr
, likely
? "beql" : "beq",
4376 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4377 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4385 && imm_expr
.X_op
== O_constant
4386 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4388 if (imm_expr
.X_op
!= O_constant
)
4389 as_bad (_("Unsupported large constant"));
4390 ++imm_expr
.X_add_number
;
4394 if (mask
== M_BGEUL_I
)
4396 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4398 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4400 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4406 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4414 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4419 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4423 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4424 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4432 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4439 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4440 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4448 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4453 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4457 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4458 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4464 maxnum
= 0x7fffffff;
4465 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4472 if (imm_expr
.X_op
== O_constant
4473 && imm_expr
.X_add_number
>= maxnum
4474 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4476 if (imm_expr
.X_op
!= O_constant
)
4477 as_bad (_("Unsupported large constant"));
4478 ++imm_expr
.X_add_number
;
4482 if (mask
== M_BLTL_I
)
4484 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4486 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4489 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4491 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4496 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4504 macro_build (&offset_expr
, likely
? "beql" : "beq",
4511 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4512 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4520 && imm_expr
.X_op
== O_constant
4521 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4523 if (imm_expr
.X_op
!= O_constant
)
4524 as_bad (_("Unsupported large constant"));
4525 ++imm_expr
.X_add_number
;
4529 if (mask
== M_BLTUL_I
)
4531 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4533 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4535 macro_build (&offset_expr
, likely
? "beql" : "beq",
4541 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4549 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4554 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4558 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4559 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4569 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4574 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4575 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4583 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4585 as_bad (_("Unsupported large constant"));
4590 pos
= (unsigned long) imm_expr
.X_add_number
;
4591 size
= (unsigned long) imm2_expr
.X_add_number
;
4596 as_bad (_("Improper position (%lu)"), pos
);
4599 if (size
== 0 || size
> 64
4600 || (pos
+ size
- 1) > 63)
4602 as_bad (_("Improper extract size (%lu, position %lu)"),
4607 if (size
<= 32 && pos
< 32)
4612 else if (size
<= 32)
4622 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4631 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4633 as_bad (_("Unsupported large constant"));
4638 pos
= (unsigned long) imm_expr
.X_add_number
;
4639 size
= (unsigned long) imm2_expr
.X_add_number
;
4644 as_bad (_("Improper position (%lu)"), pos
);
4647 if (size
== 0 || size
> 64
4648 || (pos
+ size
- 1) > 63)
4650 as_bad (_("Improper insert size (%lu, position %lu)"),
4655 if (pos
< 32 && (pos
+ size
- 1) < 32)
4670 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4687 as_warn (_("Divide by zero."));
4689 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4691 macro_build (NULL
, "break", "c", 7);
4698 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4699 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4703 expr1
.X_add_number
= 8;
4704 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4705 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4706 macro_build (NULL
, "break", "c", 7);
4708 expr1
.X_add_number
= -1;
4710 load_register (AT
, &expr1
, dbl
);
4711 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4712 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4715 expr1
.X_add_number
= 1;
4716 load_register (AT
, &expr1
, dbl
);
4717 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4721 expr1
.X_add_number
= 0x80000000;
4722 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4726 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4727 /* We want to close the noreorder block as soon as possible, so
4728 that later insns are available for delay slot filling. */
4733 expr1
.X_add_number
= 8;
4734 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4735 macro_build (NULL
, "nop", "", 0);
4737 /* We want to close the noreorder block as soon as possible, so
4738 that later insns are available for delay slot filling. */
4741 macro_build (NULL
, "break", "c", 6);
4743 macro_build (NULL
, s
, "d", dreg
);
4782 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4784 as_warn (_("Divide by zero."));
4786 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4788 macro_build (NULL
, "break", "c", 7);
4791 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4793 if (strcmp (s2
, "mflo") == 0)
4794 move_register (dreg
, sreg
);
4796 move_register (dreg
, 0);
4799 if (imm_expr
.X_op
== O_constant
4800 && imm_expr
.X_add_number
== -1
4801 && s
[strlen (s
) - 1] != 'u')
4803 if (strcmp (s2
, "mflo") == 0)
4805 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4808 move_register (dreg
, 0);
4813 load_register (AT
, &imm_expr
, dbl
);
4814 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4815 macro_build (NULL
, s2
, "d", dreg
);
4837 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4838 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4839 /* We want to close the noreorder block as soon as possible, so
4840 that later insns are available for delay slot filling. */
4845 expr1
.X_add_number
= 8;
4846 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4847 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4849 /* We want to close the noreorder block as soon as possible, so
4850 that later insns are available for delay slot filling. */
4852 macro_build (NULL
, "break", "c", 7);
4854 macro_build (NULL
, s2
, "d", dreg
);
4866 /* Load the address of a symbol into a register. If breg is not
4867 zero, we then add a base register to it. */
4869 if (dbl
&& HAVE_32BIT_GPRS
)
4870 as_warn (_("dla used to load 32-bit register"));
4872 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4873 as_warn (_("la used to load 64-bit address"));
4875 if (offset_expr
.X_op
== O_constant
4876 && offset_expr
.X_add_number
>= -0x8000
4877 && offset_expr
.X_add_number
< 0x8000)
4879 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4880 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4884 if (!mips_opts
.noat
&& (treg
== breg
))
4894 if (offset_expr
.X_op
!= O_symbol
4895 && offset_expr
.X_op
!= O_constant
)
4897 as_bad (_("expression too complex"));
4898 offset_expr
.X_op
= O_constant
;
4901 if (offset_expr
.X_op
== O_constant
)
4902 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4903 else if (mips_pic
== NO_PIC
)
4905 /* If this is a reference to a GP relative symbol, we want
4906 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4908 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4909 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4910 If we have a constant, we need two instructions anyhow,
4911 so we may as well always use the latter form.
4913 With 64bit address space and a usable $at we want
4914 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4915 lui $at,<sym> (BFD_RELOC_HI16_S)
4916 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4917 daddiu $at,<sym> (BFD_RELOC_LO16)
4919 daddu $tempreg,$tempreg,$at
4921 If $at is already in use, we use a path which is suboptimal
4922 on superscalar processors.
4923 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4924 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4926 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4928 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4930 For GP relative symbols in 64bit address space we can use
4931 the same sequence as in 32bit address space. */
4932 if (HAVE_64BIT_SYMBOLS
)
4934 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4935 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4937 relax_start (offset_expr
.X_add_symbol
);
4938 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4939 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4943 if (used_at
== 0 && !mips_opts
.noat
)
4945 macro_build (&offset_expr
, "lui", "t,u",
4946 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4947 macro_build (&offset_expr
, "lui", "t,u",
4948 AT
, BFD_RELOC_HI16_S
);
4949 macro_build (&offset_expr
, "daddiu", "t,r,j",
4950 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4951 macro_build (&offset_expr
, "daddiu", "t,r,j",
4952 AT
, AT
, BFD_RELOC_LO16
);
4953 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4954 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4959 macro_build (&offset_expr
, "lui", "t,u",
4960 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4961 macro_build (&offset_expr
, "daddiu", "t,r,j",
4962 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4963 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4964 macro_build (&offset_expr
, "daddiu", "t,r,j",
4965 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4966 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4967 macro_build (&offset_expr
, "daddiu", "t,r,j",
4968 tempreg
, tempreg
, BFD_RELOC_LO16
);
4971 if (mips_relax
.sequence
)
4976 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4977 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4979 relax_start (offset_expr
.X_add_symbol
);
4980 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4981 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4984 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4985 as_bad (_("offset too large"));
4986 macro_build_lui (&offset_expr
, tempreg
);
4987 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4988 tempreg
, tempreg
, BFD_RELOC_LO16
);
4989 if (mips_relax
.sequence
)
4993 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4995 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4997 /* If this is a reference to an external symbol, and there
4998 is no constant, we want
4999 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5000 or for lca or if tempreg is PIC_CALL_REG
5001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5002 For a local symbol, we want
5003 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5005 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5007 If we have a small constant, and this is a reference to
5008 an external symbol, we want
5009 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5011 addiu $tempreg,$tempreg,<constant>
5012 For a local symbol, we want the same instruction
5013 sequence, but we output a BFD_RELOC_LO16 reloc on the
5016 If we have a large constant, and this is a reference to
5017 an external symbol, we want
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5019 lui $at,<hiconstant>
5020 addiu $at,$at,<loconstant>
5021 addu $tempreg,$tempreg,$at
5022 For a local symbol, we want the same instruction
5023 sequence, but we output a BFD_RELOC_LO16 reloc on the
5027 if (offset_expr
.X_add_number
== 0)
5029 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5030 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5032 relax_start (offset_expr
.X_add_symbol
);
5033 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5034 lw_reloc_type
, mips_gp_register
);
5037 /* We're going to put in an addu instruction using
5038 tempreg, so we may as well insert the nop right
5043 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5044 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5046 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5047 tempreg
, tempreg
, BFD_RELOC_LO16
);
5049 /* FIXME: If breg == 0, and the next instruction uses
5050 $tempreg, then if this variant case is used an extra
5051 nop will be generated. */
5053 else if (offset_expr
.X_add_number
>= -0x8000
5054 && offset_expr
.X_add_number
< 0x8000)
5056 load_got_offset (tempreg
, &offset_expr
);
5058 add_got_offset (tempreg
, &offset_expr
);
5062 expr1
.X_add_number
= offset_expr
.X_add_number
;
5063 offset_expr
.X_add_number
=
5064 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5065 load_got_offset (tempreg
, &offset_expr
);
5066 offset_expr
.X_add_number
= expr1
.X_add_number
;
5067 /* If we are going to add in a base register, and the
5068 target register and the base register are the same,
5069 then we are using AT as a temporary register. Since
5070 we want to load the constant into AT, we add our
5071 current AT (from the global offset table) and the
5072 register into the register now, and pretend we were
5073 not using a base register. */
5077 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5082 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5086 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5088 int add_breg_early
= 0;
5090 /* If this is a reference to an external, and there is no
5091 constant, or local symbol (*), with or without a
5093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5094 or for lca or if tempreg is PIC_CALL_REG
5095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5097 If we have a small constant, and this is a reference to
5098 an external symbol, we want
5099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5100 addiu $tempreg,$tempreg,<constant>
5102 If we have a large constant, and this is a reference to
5103 an external symbol, we want
5104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5105 lui $at,<hiconstant>
5106 addiu $at,$at,<loconstant>
5107 addu $tempreg,$tempreg,$at
5109 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5110 local symbols, even though it introduces an additional
5113 if (offset_expr
.X_add_number
)
5115 expr1
.X_add_number
= offset_expr
.X_add_number
;
5116 offset_expr
.X_add_number
= 0;
5118 relax_start (offset_expr
.X_add_symbol
);
5119 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5120 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5122 if (expr1
.X_add_number
>= -0x8000
5123 && expr1
.X_add_number
< 0x8000)
5125 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5126 tempreg
, tempreg
, BFD_RELOC_LO16
);
5128 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5132 /* If we are going to add in a base register, and the
5133 target register and the base register are the same,
5134 then we are using AT as a temporary register. Since
5135 we want to load the constant into AT, we add our
5136 current AT (from the global offset table) and the
5137 register into the register now, and pretend we were
5138 not using a base register. */
5143 assert (tempreg
== AT
);
5144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5150 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5151 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5157 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5160 offset_expr
.X_add_number
= expr1
.X_add_number
;
5162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5163 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5167 treg
, tempreg
, breg
);
5173 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5175 relax_start (offset_expr
.X_add_symbol
);
5176 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5177 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5179 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5180 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5185 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5186 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5189 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5192 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5193 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5194 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5196 /* This is the large GOT case. If this is a reference to an
5197 external symbol, and there is no constant, we want
5198 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5199 addu $tempreg,$tempreg,$gp
5200 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5201 or for lca or if tempreg is PIC_CALL_REG
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5205 For a local symbol, we want
5206 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5208 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5210 If we have a small constant, and this is a reference to
5211 an external symbol, we want
5212 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5213 addu $tempreg,$tempreg,$gp
5214 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5216 addiu $tempreg,$tempreg,<constant>
5217 For a local symbol, we want
5218 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5220 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5222 If we have a large constant, and this is a reference to
5223 an external symbol, we want
5224 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5225 addu $tempreg,$tempreg,$gp
5226 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5227 lui $at,<hiconstant>
5228 addiu $at,$at,<loconstant>
5229 addu $tempreg,$tempreg,$at
5230 For a local symbol, we want
5231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5232 lui $at,<hiconstant>
5233 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5234 addu $tempreg,$tempreg,$at
5237 expr1
.X_add_number
= offset_expr
.X_add_number
;
5238 offset_expr
.X_add_number
= 0;
5239 relax_start (offset_expr
.X_add_symbol
);
5240 gpdelay
= reg_needs_delay (mips_gp_register
);
5241 if (expr1
.X_add_number
== 0 && breg
== 0
5242 && (call
|| tempreg
== PIC_CALL_REG
))
5244 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5245 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5247 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5248 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5249 tempreg
, tempreg
, mips_gp_register
);
5250 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5251 tempreg
, lw_reloc_type
, tempreg
);
5252 if (expr1
.X_add_number
== 0)
5256 /* We're going to put in an addu instruction using
5257 tempreg, so we may as well insert the nop right
5262 else if (expr1
.X_add_number
>= -0x8000
5263 && expr1
.X_add_number
< 0x8000)
5266 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5267 tempreg
, tempreg
, BFD_RELOC_LO16
);
5273 /* If we are going to add in a base register, and the
5274 target register and the base register are the same,
5275 then we are using AT as a temporary register. Since
5276 we want to load the constant into AT, we add our
5277 current AT (from the global offset table) and the
5278 register into the register now, and pretend we were
5279 not using a base register. */
5284 assert (tempreg
== AT
);
5286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5291 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5292 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5296 offset_expr
.X_add_number
=
5297 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5302 /* This is needed because this instruction uses $gp, but
5303 the first instruction on the main stream does not. */
5304 macro_build (NULL
, "nop", "");
5307 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5308 local_reloc_type
, mips_gp_register
);
5309 if (expr1
.X_add_number
>= -0x8000
5310 && expr1
.X_add_number
< 0x8000)
5313 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5314 tempreg
, tempreg
, BFD_RELOC_LO16
);
5315 /* FIXME: If add_number is 0, and there was no base
5316 register, the external symbol case ended with a load,
5317 so if the symbol turns out to not be external, and
5318 the next instruction uses tempreg, an unnecessary nop
5319 will be inserted. */
5325 /* We must add in the base register now, as in the
5326 external symbol case. */
5327 assert (tempreg
== AT
);
5329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5332 /* We set breg to 0 because we have arranged to add
5333 it in in both cases. */
5337 macro_build_lui (&expr1
, AT
);
5338 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5339 AT
, AT
, BFD_RELOC_LO16
);
5340 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5341 tempreg
, tempreg
, AT
);
5346 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5348 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5349 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5350 int add_breg_early
= 0;
5352 /* This is the large GOT case. If this is a reference to an
5353 external symbol, and there is no constant, we want
5354 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5355 add $tempreg,$tempreg,$gp
5356 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5357 or for lca or if tempreg is PIC_CALL_REG
5358 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5359 add $tempreg,$tempreg,$gp
5360 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5362 If we have a small constant, and this is a reference to
5363 an external symbol, we want
5364 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5365 add $tempreg,$tempreg,$gp
5366 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5367 addi $tempreg,$tempreg,<constant>
5369 If we have a large constant, and this is a reference to
5370 an external symbol, we want
5371 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5372 addu $tempreg,$tempreg,$gp
5373 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5374 lui $at,<hiconstant>
5375 addi $at,$at,<loconstant>
5376 add $tempreg,$tempreg,$at
5378 If we have NewABI, and we know it's a local symbol, we want
5379 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5380 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5381 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5383 relax_start (offset_expr
.X_add_symbol
);
5385 expr1
.X_add_number
= offset_expr
.X_add_number
;
5386 offset_expr
.X_add_number
= 0;
5388 if (expr1
.X_add_number
== 0 && breg
== 0
5389 && (call
|| tempreg
== PIC_CALL_REG
))
5391 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5392 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5394 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5395 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5396 tempreg
, tempreg
, mips_gp_register
);
5397 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5398 tempreg
, lw_reloc_type
, tempreg
);
5400 if (expr1
.X_add_number
== 0)
5402 else if (expr1
.X_add_number
>= -0x8000
5403 && expr1
.X_add_number
< 0x8000)
5405 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5406 tempreg
, tempreg
, BFD_RELOC_LO16
);
5408 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5412 /* If we are going to add in a base register, and the
5413 target register and the base register are the same,
5414 then we are using AT as a temporary register. Since
5415 we want to load the constant into AT, we add our
5416 current AT (from the global offset table) and the
5417 register into the register now, and pretend we were
5418 not using a base register. */
5423 assert (tempreg
== AT
);
5424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5430 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5431 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5436 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5439 offset_expr
.X_add_number
= expr1
.X_add_number
;
5440 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5441 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5442 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5443 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5447 treg
, tempreg
, breg
);
5457 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5461 /* The j instruction may not be used in PIC code, since it
5462 requires an absolute address. We convert it to a b
5464 if (mips_pic
== NO_PIC
)
5465 macro_build (&offset_expr
, "j", "a");
5467 macro_build (&offset_expr
, "b", "p");
5470 /* The jal instructions must be handled as macros because when
5471 generating PIC code they expand to multi-instruction
5472 sequences. Normally they are simple instructions. */
5477 if (mips_pic
== NO_PIC
)
5478 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5479 else if (mips_pic
== SVR4_PIC
)
5481 if (sreg
!= PIC_CALL_REG
)
5482 as_warn (_("MIPS PIC call to register other than $25"));
5484 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5487 if (mips_cprestore_offset
< 0)
5488 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5491 if (! mips_frame_reg_valid
)
5493 as_warn (_("No .frame pseudo-op used in PIC code"));
5494 /* Quiet this warning. */
5495 mips_frame_reg_valid
= 1;
5497 if (! mips_cprestore_valid
)
5499 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5500 /* Quiet this warning. */
5501 mips_cprestore_valid
= 1;
5503 expr1
.X_add_number
= mips_cprestore_offset
;
5504 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5507 HAVE_64BIT_ADDRESSES
);
5517 if (mips_pic
== NO_PIC
)
5518 macro_build (&offset_expr
, "jal", "a");
5519 else if (mips_pic
== SVR4_PIC
)
5521 /* If this is a reference to an external symbol, and we are
5522 using a small GOT, we want
5523 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5527 lw $gp,cprestore($sp)
5528 The cprestore value is set using the .cprestore
5529 pseudo-op. If we are using a big GOT, we want
5530 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5532 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5536 lw $gp,cprestore($sp)
5537 If the symbol is not external, we want
5538 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5540 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5543 lw $gp,cprestore($sp)
5545 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5546 sequences above, minus nops, unless the symbol is local,
5547 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5553 relax_start (offset_expr
.X_add_symbol
);
5554 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5555 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5558 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5559 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5565 relax_start (offset_expr
.X_add_symbol
);
5566 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5567 BFD_RELOC_MIPS_CALL_HI16
);
5568 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5569 PIC_CALL_REG
, mips_gp_register
);
5570 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5571 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5575 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5577 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5578 PIC_CALL_REG
, PIC_CALL_REG
,
5579 BFD_RELOC_MIPS_GOT_OFST
);
5583 macro_build_jalr (&offset_expr
);
5587 relax_start (offset_expr
.X_add_symbol
);
5590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5591 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5600 gpdelay
= reg_needs_delay (mips_gp_register
);
5601 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5602 BFD_RELOC_MIPS_CALL_HI16
);
5603 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5604 PIC_CALL_REG
, mips_gp_register
);
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5611 macro_build (NULL
, "nop", "");
5613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5614 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5617 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5618 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5620 macro_build_jalr (&offset_expr
);
5622 if (mips_cprestore_offset
< 0)
5623 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5626 if (! mips_frame_reg_valid
)
5628 as_warn (_("No .frame pseudo-op used in PIC code"));
5629 /* Quiet this warning. */
5630 mips_frame_reg_valid
= 1;
5632 if (! mips_cprestore_valid
)
5634 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5635 /* Quiet this warning. */
5636 mips_cprestore_valid
= 1;
5638 if (mips_opts
.noreorder
)
5639 macro_build (NULL
, "nop", "");
5640 expr1
.X_add_number
= mips_cprestore_offset
;
5641 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5644 HAVE_64BIT_ADDRESSES
);
5670 /* Itbl support may require additional care here. */
5675 /* Itbl support may require additional care here. */
5680 /* Itbl support may require additional care here. */
5685 /* Itbl support may require additional care here. */
5697 if (mips_opts
.arch
== CPU_R4650
)
5699 as_bad (_("opcode not supported on this processor"));
5703 /* Itbl support may require additional care here. */
5708 /* Itbl support may require additional care here. */
5713 /* Itbl support may require additional care here. */
5733 if (breg
== treg
|| coproc
|| lr
)
5754 /* Itbl support may require additional care here. */
5759 /* Itbl support may require additional care here. */
5764 /* Itbl support may require additional care here. */
5769 /* Itbl support may require additional care here. */
5785 if (mips_opts
.arch
== CPU_R4650
)
5787 as_bad (_("opcode not supported on this processor"));
5792 /* Itbl support may require additional care here. */
5796 /* Itbl support may require additional care here. */
5801 /* Itbl support may require additional care here. */
5813 /* Itbl support may require additional care here. */
5814 if (mask
== M_LWC1_AB
5815 || mask
== M_SWC1_AB
5816 || mask
== M_LDC1_AB
5817 || mask
== M_SDC1_AB
5826 if (offset_expr
.X_op
!= O_constant
5827 && offset_expr
.X_op
!= O_symbol
)
5829 as_bad (_("expression too complex"));
5830 offset_expr
.X_op
= O_constant
;
5833 if (HAVE_32BIT_ADDRESSES
5834 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5838 sprintf_vma (value
, offset_expr
.X_add_number
);
5839 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5842 /* A constant expression in PIC code can be handled just as it
5843 is in non PIC code. */
5844 if (offset_expr
.X_op
== O_constant
)
5846 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5847 & ~(bfd_vma
) 0xffff);
5848 normalize_address_expr (&expr1
);
5849 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5851 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5852 tempreg
, tempreg
, breg
);
5853 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5855 else if (mips_pic
== NO_PIC
)
5857 /* If this is a reference to a GP relative symbol, and there
5858 is no base register, we want
5859 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5860 Otherwise, if there is no base register, we want
5861 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5862 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5863 If we have a constant, we need two instructions anyhow,
5864 so we always use the latter form.
5866 If we have a base register, and this is a reference to a
5867 GP relative symbol, we want
5868 addu $tempreg,$breg,$gp
5869 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5871 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5872 addu $tempreg,$tempreg,$breg
5873 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5874 With a constant we always use the latter case.
5876 With 64bit address space and no base register and $at usable,
5878 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5879 lui $at,<sym> (BFD_RELOC_HI16_S)
5880 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5884 If we have a base register, we want
5885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5886 lui $at,<sym> (BFD_RELOC_HI16_S)
5887 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5891 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5893 Without $at we can't generate the optimal path for superscalar
5894 processors here since this would require two temporary registers.
5895 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5896 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5898 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5900 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5901 If we have a base register, we want
5902 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5903 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5905 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5907 daddu $tempreg,$tempreg,$breg
5908 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5910 For GP relative symbols in 64bit address space we can use
5911 the same sequence as in 32bit address space. */
5912 if (HAVE_64BIT_SYMBOLS
)
5914 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5915 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5917 relax_start (offset_expr
.X_add_symbol
);
5920 macro_build (&offset_expr
, s
, fmt
, treg
,
5921 BFD_RELOC_GPREL16
, mips_gp_register
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5926 tempreg
, breg
, mips_gp_register
);
5927 macro_build (&offset_expr
, s
, fmt
, treg
,
5928 BFD_RELOC_GPREL16
, tempreg
);
5933 if (used_at
== 0 && !mips_opts
.noat
)
5935 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5936 BFD_RELOC_MIPS_HIGHEST
);
5937 macro_build (&offset_expr
, "lui", "t,u", AT
,
5939 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5940 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5942 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5943 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5944 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5945 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5951 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5952 BFD_RELOC_MIPS_HIGHEST
);
5953 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5954 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5955 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5956 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5957 tempreg
, BFD_RELOC_HI16_S
);
5958 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5960 macro_build (NULL
, "daddu", "d,v,t",
5961 tempreg
, tempreg
, breg
);
5962 macro_build (&offset_expr
, s
, fmt
, treg
,
5963 BFD_RELOC_LO16
, tempreg
);
5966 if (mips_relax
.sequence
)
5973 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5974 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5976 relax_start (offset_expr
.X_add_symbol
);
5977 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5981 macro_build_lui (&offset_expr
, tempreg
);
5982 macro_build (&offset_expr
, s
, fmt
, treg
,
5983 BFD_RELOC_LO16
, tempreg
);
5984 if (mips_relax
.sequence
)
5989 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5990 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5992 relax_start (offset_expr
.X_add_symbol
);
5993 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5994 tempreg
, breg
, mips_gp_register
);
5995 macro_build (&offset_expr
, s
, fmt
, treg
,
5996 BFD_RELOC_GPREL16
, tempreg
);
5999 macro_build_lui (&offset_expr
, tempreg
);
6000 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6001 tempreg
, tempreg
, breg
);
6002 macro_build (&offset_expr
, s
, fmt
, treg
,
6003 BFD_RELOC_LO16
, tempreg
);
6004 if (mips_relax
.sequence
)
6008 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6010 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6012 /* If this is a reference to an external symbol, we want
6013 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6015 <op> $treg,0($tempreg)
6017 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6019 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6020 <op> $treg,0($tempreg)
6023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6024 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6026 If there is a base register, we add it to $tempreg before
6027 the <op>. If there is a constant, we stick it in the
6028 <op> instruction. We don't handle constants larger than
6029 16 bits, because we have no way to load the upper 16 bits
6030 (actually, we could handle them for the subset of cases
6031 in which we are not using $at). */
6032 assert (offset_expr
.X_op
== O_symbol
);
6035 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6036 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6039 tempreg
, tempreg
, breg
);
6040 macro_build (&offset_expr
, s
, fmt
, treg
,
6041 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6044 expr1
.X_add_number
= offset_expr
.X_add_number
;
6045 offset_expr
.X_add_number
= 0;
6046 if (expr1
.X_add_number
< -0x8000
6047 || expr1
.X_add_number
>= 0x8000)
6048 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6049 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6050 lw_reloc_type
, mips_gp_register
);
6052 relax_start (offset_expr
.X_add_symbol
);
6054 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6055 tempreg
, BFD_RELOC_LO16
);
6058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6059 tempreg
, tempreg
, breg
);
6060 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6062 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6066 /* If this is a reference to an external symbol, we want
6067 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6068 addu $tempreg,$tempreg,$gp
6069 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6070 <op> $treg,0($tempreg)
6072 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6074 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6075 <op> $treg,0($tempreg)
6076 If there is a base register, we add it to $tempreg before
6077 the <op>. If there is a constant, we stick it in the
6078 <op> instruction. We don't handle constants larger than
6079 16 bits, because we have no way to load the upper 16 bits
6080 (actually, we could handle them for the subset of cases
6081 in which we are not using $at). */
6082 assert (offset_expr
.X_op
== O_symbol
);
6083 expr1
.X_add_number
= offset_expr
.X_add_number
;
6084 offset_expr
.X_add_number
= 0;
6085 if (expr1
.X_add_number
< -0x8000
6086 || expr1
.X_add_number
>= 0x8000)
6087 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6088 gpdelay
= reg_needs_delay (mips_gp_register
);
6089 relax_start (offset_expr
.X_add_symbol
);
6090 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6091 BFD_RELOC_MIPS_GOT_HI16
);
6092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6095 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6098 macro_build (NULL
, "nop", "");
6099 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6100 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6102 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6103 tempreg
, BFD_RELOC_LO16
);
6107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6108 tempreg
, tempreg
, breg
);
6109 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6111 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6113 /* If this is a reference to an external symbol, we want
6114 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6115 add $tempreg,$tempreg,$gp
6116 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6117 <op> $treg,<ofst>($tempreg)
6118 Otherwise, for local symbols, we want:
6119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6120 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6121 assert (offset_expr
.X_op
== O_symbol
);
6122 expr1
.X_add_number
= offset_expr
.X_add_number
;
6123 offset_expr
.X_add_number
= 0;
6124 if (expr1
.X_add_number
< -0x8000
6125 || expr1
.X_add_number
>= 0x8000)
6126 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6127 relax_start (offset_expr
.X_add_symbol
);
6128 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6129 BFD_RELOC_MIPS_GOT_HI16
);
6130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6132 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6133 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6135 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6136 tempreg
, tempreg
, breg
);
6137 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6140 offset_expr
.X_add_number
= expr1
.X_add_number
;
6141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6142 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6145 tempreg
, tempreg
, breg
);
6146 macro_build (&offset_expr
, s
, fmt
, treg
,
6147 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6157 load_register (treg
, &imm_expr
, 0);
6161 load_register (treg
, &imm_expr
, 1);
6165 if (imm_expr
.X_op
== O_constant
)
6168 load_register (AT
, &imm_expr
, 0);
6169 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6174 assert (offset_expr
.X_op
== O_symbol
6175 && strcmp (segment_name (S_GET_SEGMENT
6176 (offset_expr
.X_add_symbol
)),
6178 && offset_expr
.X_add_number
== 0);
6179 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6180 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6185 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6186 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6187 order 32 bits of the value and the low order 32 bits are either
6188 zero or in OFFSET_EXPR. */
6189 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6191 if (HAVE_64BIT_GPRS
)
6192 load_register (treg
, &imm_expr
, 1);
6197 if (target_big_endian
)
6209 load_register (hreg
, &imm_expr
, 0);
6212 if (offset_expr
.X_op
== O_absent
)
6213 move_register (lreg
, 0);
6216 assert (offset_expr
.X_op
== O_constant
);
6217 load_register (lreg
, &offset_expr
, 0);
6224 /* We know that sym is in the .rdata section. First we get the
6225 upper 16 bits of the address. */
6226 if (mips_pic
== NO_PIC
)
6228 macro_build_lui (&offset_expr
, AT
);
6231 else if (mips_pic
== SVR4_PIC
)
6233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6234 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6240 /* Now we load the register(s). */
6241 if (HAVE_64BIT_GPRS
)
6244 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6249 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6252 /* FIXME: How in the world do we deal with the possible
6254 offset_expr
.X_add_number
+= 4;
6255 macro_build (&offset_expr
, "lw", "t,o(b)",
6256 treg
+ 1, BFD_RELOC_LO16
, AT
);
6262 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6263 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6264 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6265 the value and the low order 32 bits are either zero or in
6267 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6270 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6271 if (HAVE_64BIT_FPRS
)
6273 assert (HAVE_64BIT_GPRS
);
6274 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6278 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6279 if (offset_expr
.X_op
== O_absent
)
6280 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6283 assert (offset_expr
.X_op
== O_constant
);
6284 load_register (AT
, &offset_expr
, 0);
6285 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6291 assert (offset_expr
.X_op
== O_symbol
6292 && offset_expr
.X_add_number
== 0);
6293 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6294 if (strcmp (s
, ".lit8") == 0)
6296 if (mips_opts
.isa
!= ISA_MIPS1
)
6298 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6299 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6302 breg
= mips_gp_register
;
6303 r
= BFD_RELOC_MIPS_LITERAL
;
6308 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6310 if (mips_pic
== SVR4_PIC
)
6311 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6312 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6315 /* FIXME: This won't work for a 64 bit address. */
6316 macro_build_lui (&offset_expr
, AT
);
6319 if (mips_opts
.isa
!= ISA_MIPS1
)
6321 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6322 treg
, BFD_RELOC_LO16
, AT
);
6331 if (mips_opts
.arch
== CPU_R4650
)
6333 as_bad (_("opcode not supported on this processor"));
6336 /* Even on a big endian machine $fn comes before $fn+1. We have
6337 to adjust when loading from memory. */
6340 assert (mips_opts
.isa
== ISA_MIPS1
);
6341 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6342 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6343 /* FIXME: A possible overflow which I don't know how to deal
6345 offset_expr
.X_add_number
+= 4;
6346 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6347 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6352 * The MIPS assembler seems to check for X_add_number not
6353 * being double aligned and generating:
6356 * addiu at,at,%lo(foo+1)
6359 * But, the resulting address is the same after relocation so why
6360 * generate the extra instruction?
6362 if (mips_opts
.arch
== CPU_R4650
)
6364 as_bad (_("opcode not supported on this processor"));
6367 /* Itbl support may require additional care here. */
6369 if (mips_opts
.isa
!= ISA_MIPS1
)
6380 if (mips_opts
.arch
== CPU_R4650
)
6382 as_bad (_("opcode not supported on this processor"));
6386 if (mips_opts
.isa
!= ISA_MIPS1
)
6394 /* Itbl support may require additional care here. */
6399 if (HAVE_64BIT_GPRS
)
6410 if (HAVE_64BIT_GPRS
)
6420 if (offset_expr
.X_op
!= O_symbol
6421 && offset_expr
.X_op
!= O_constant
)
6423 as_bad (_("expression too complex"));
6424 offset_expr
.X_op
= O_constant
;
6427 if (HAVE_32BIT_ADDRESSES
6428 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6432 sprintf_vma (value
, offset_expr
.X_add_number
);
6433 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6436 /* Even on a big endian machine $fn comes before $fn+1. We have
6437 to adjust when loading from memory. We set coproc if we must
6438 load $fn+1 first. */
6439 /* Itbl support may require additional care here. */
6440 if (! target_big_endian
)
6443 if (mips_pic
== NO_PIC
6444 || offset_expr
.X_op
== O_constant
)
6446 /* If this is a reference to a GP relative symbol, we want
6447 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6448 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6449 If we have a base register, we use this
6451 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6452 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6453 If this is not a GP relative symbol, we want
6454 lui $at,<sym> (BFD_RELOC_HI16_S)
6455 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6456 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6457 If there is a base register, we add it to $at after the
6458 lui instruction. If there is a constant, we always use
6460 if (offset_expr
.X_op
== O_symbol
6461 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6462 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6464 relax_start (offset_expr
.X_add_symbol
);
6467 tempreg
= mips_gp_register
;
6471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6472 AT
, breg
, mips_gp_register
);
6477 /* Itbl support may require additional care here. */
6478 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6479 BFD_RELOC_GPREL16
, tempreg
);
6480 offset_expr
.X_add_number
+= 4;
6482 /* Set mips_optimize to 2 to avoid inserting an
6484 hold_mips_optimize
= mips_optimize
;
6486 /* Itbl support may require additional care here. */
6487 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6488 BFD_RELOC_GPREL16
, tempreg
);
6489 mips_optimize
= hold_mips_optimize
;
6493 /* We just generated two relocs. When tc_gen_reloc
6494 handles this case, it will skip the first reloc and
6495 handle the second. The second reloc already has an
6496 extra addend of 4, which we added above. We must
6497 subtract it out, and then subtract another 4 to make
6498 the first reloc come out right. The second reloc
6499 will come out right because we are going to add 4 to
6500 offset_expr when we build its instruction below.
6502 If we have a symbol, then we don't want to include
6503 the offset, because it will wind up being included
6504 when we generate the reloc. */
6506 if (offset_expr
.X_op
== O_constant
)
6507 offset_expr
.X_add_number
-= 8;
6510 offset_expr
.X_add_number
= -4;
6511 offset_expr
.X_op
= O_constant
;
6515 macro_build_lui (&offset_expr
, AT
);
6517 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6518 /* Itbl support may require additional care here. */
6519 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6520 BFD_RELOC_LO16
, AT
);
6521 /* FIXME: How do we handle overflow here? */
6522 offset_expr
.X_add_number
+= 4;
6523 /* Itbl support may require additional care here. */
6524 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6525 BFD_RELOC_LO16
, AT
);
6526 if (mips_relax
.sequence
)
6529 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6531 /* If this is a reference to an external symbol, we want
6532 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6537 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6539 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6540 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6541 If there is a base register we add it to $at before the
6542 lwc1 instructions. If there is a constant we include it
6543 in the lwc1 instructions. */
6545 expr1
.X_add_number
= offset_expr
.X_add_number
;
6546 if (expr1
.X_add_number
< -0x8000
6547 || expr1
.X_add_number
>= 0x8000 - 4)
6548 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6549 load_got_offset (AT
, &offset_expr
);
6552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6554 /* Set mips_optimize to 2 to avoid inserting an undesired
6556 hold_mips_optimize
= mips_optimize
;
6559 /* Itbl support may require additional care here. */
6560 relax_start (offset_expr
.X_add_symbol
);
6561 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6562 BFD_RELOC_LO16
, AT
);
6563 expr1
.X_add_number
+= 4;
6564 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6565 BFD_RELOC_LO16
, AT
);
6567 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6568 BFD_RELOC_LO16
, AT
);
6569 offset_expr
.X_add_number
+= 4;
6570 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6571 BFD_RELOC_LO16
, AT
);
6574 mips_optimize
= hold_mips_optimize
;
6576 else if (mips_pic
== SVR4_PIC
)
6580 /* If this is a reference to an external symbol, we want
6581 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6583 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6588 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6590 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6591 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6592 If there is a base register we add it to $at before the
6593 lwc1 instructions. If there is a constant we include it
6594 in the lwc1 instructions. */
6596 expr1
.X_add_number
= offset_expr
.X_add_number
;
6597 offset_expr
.X_add_number
= 0;
6598 if (expr1
.X_add_number
< -0x8000
6599 || expr1
.X_add_number
>= 0x8000 - 4)
6600 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6601 gpdelay
= reg_needs_delay (mips_gp_register
);
6602 relax_start (offset_expr
.X_add_symbol
);
6603 macro_build (&offset_expr
, "lui", "t,u",
6604 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6606 AT
, AT
, mips_gp_register
);
6607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6608 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6611 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6612 /* Itbl support may require additional care here. */
6613 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6614 BFD_RELOC_LO16
, AT
);
6615 expr1
.X_add_number
+= 4;
6617 /* Set mips_optimize to 2 to avoid inserting an undesired
6619 hold_mips_optimize
= mips_optimize
;
6621 /* Itbl support may require additional care here. */
6622 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6623 BFD_RELOC_LO16
, AT
);
6624 mips_optimize
= hold_mips_optimize
;
6625 expr1
.X_add_number
-= 4;
6628 offset_expr
.X_add_number
= expr1
.X_add_number
;
6630 macro_build (NULL
, "nop", "");
6631 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6632 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6635 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6636 /* Itbl support may require additional care here. */
6637 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6638 BFD_RELOC_LO16
, AT
);
6639 offset_expr
.X_add_number
+= 4;
6641 /* Set mips_optimize to 2 to avoid inserting an undesired
6643 hold_mips_optimize
= mips_optimize
;
6645 /* Itbl support may require additional care here. */
6646 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6647 BFD_RELOC_LO16
, AT
);
6648 mips_optimize
= hold_mips_optimize
;
6662 assert (HAVE_32BIT_ADDRESSES
);
6663 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6664 offset_expr
.X_add_number
+= 4;
6665 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6668 /* New code added to support COPZ instructions.
6669 This code builds table entries out of the macros in mip_opcodes.
6670 R4000 uses interlocks to handle coproc delays.
6671 Other chips (like the R3000) require nops to be inserted for delays.
6673 FIXME: Currently, we require that the user handle delays.
6674 In order to fill delay slots for non-interlocked chips,
6675 we must have a way to specify delays based on the coprocessor.
6676 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6677 What are the side-effects of the cop instruction?
6678 What cache support might we have and what are its effects?
6679 Both coprocessor & memory require delays. how long???
6680 What registers are read/set/modified?
6682 If an itbl is provided to interpret cop instructions,
6683 this knowledge can be encoded in the itbl spec. */
6697 /* For now we just do C (same as Cz). The parameter will be
6698 stored in insn_opcode by mips_ip. */
6699 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6703 move_register (dreg
, sreg
);
6706 #ifdef LOSING_COMPILER
6708 /* Try and see if this is a new itbl instruction.
6709 This code builds table entries out of the macros in mip_opcodes.
6710 FIXME: For now we just assemble the expression and pass it's
6711 value along as a 32-bit immediate.
6712 We may want to have the assembler assemble this value,
6713 so that we gain the assembler's knowledge of delay slots,
6715 Would it be more efficient to use mask (id) here? */
6716 if (itbl_have_entries
6717 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6719 s
= ip
->insn_mo
->name
;
6721 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6722 macro_build (&immed_expr
, s
, "C");
6728 if (mips_opts
.noat
&& used_at
)
6729 as_bad (_("Macro used $at after \".set noat\""));
6733 macro2 (struct mips_cl_insn
*ip
)
6735 register int treg
, sreg
, dreg
, breg
;
6750 bfd_reloc_code_real_type r
;
6752 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6753 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6754 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6755 mask
= ip
->insn_mo
->mask
;
6757 expr1
.X_op
= O_constant
;
6758 expr1
.X_op_symbol
= NULL
;
6759 expr1
.X_add_symbol
= NULL
;
6760 expr1
.X_add_number
= 1;
6764 #endif /* LOSING_COMPILER */
6769 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6770 macro_build (NULL
, "mflo", "d", dreg
);
6776 /* The MIPS assembler some times generates shifts and adds. I'm
6777 not trying to be that fancy. GCC should do this for us
6780 load_register (AT
, &imm_expr
, dbl
);
6781 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6782 macro_build (NULL
, "mflo", "d", dreg
);
6798 load_register (AT
, &imm_expr
, dbl
);
6799 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6800 macro_build (NULL
, "mflo", "d", dreg
);
6801 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6802 macro_build (NULL
, "mfhi", "d", AT
);
6804 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6807 expr1
.X_add_number
= 8;
6808 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6809 macro_build (NULL
, "nop", "", 0);
6810 macro_build (NULL
, "break", "c", 6);
6813 macro_build (NULL
, "mflo", "d", dreg
);
6829 load_register (AT
, &imm_expr
, dbl
);
6830 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6831 sreg
, imm
? AT
: treg
);
6832 macro_build (NULL
, "mfhi", "d", AT
);
6833 macro_build (NULL
, "mflo", "d", dreg
);
6835 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6838 expr1
.X_add_number
= 8;
6839 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6840 macro_build (NULL
, "nop", "", 0);
6841 macro_build (NULL
, "break", "c", 6);
6847 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6858 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6859 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6863 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6864 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6865 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6866 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6870 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6881 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6882 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6886 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6887 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6888 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6889 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6897 if (imm_expr
.X_op
!= O_constant
)
6898 as_bad (_("Improper rotate count"));
6899 rot
= imm_expr
.X_add_number
& 0x3f;
6900 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6902 rot
= (64 - rot
) & 0x3f;
6904 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6906 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6911 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6914 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6915 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6918 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6919 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6920 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6928 if (imm_expr
.X_op
!= O_constant
)
6929 as_bad (_("Improper rotate count"));
6930 rot
= imm_expr
.X_add_number
& 0x1f;
6931 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6933 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6938 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6942 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6943 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6944 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6949 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6951 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6955 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6956 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6957 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6958 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6962 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6964 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6968 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6969 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6970 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6971 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6979 if (imm_expr
.X_op
!= O_constant
)
6980 as_bad (_("Improper rotate count"));
6981 rot
= imm_expr
.X_add_number
& 0x3f;
6982 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6985 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6987 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6992 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6995 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6996 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6999 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7000 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7001 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7009 if (imm_expr
.X_op
!= O_constant
)
7010 as_bad (_("Improper rotate count"));
7011 rot
= imm_expr
.X_add_number
& 0x1f;
7012 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7014 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7019 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7023 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7024 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7025 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7030 if (mips_opts
.arch
== CPU_R4650
)
7032 as_bad (_("opcode not supported on this processor"));
7035 assert (mips_opts
.isa
== ISA_MIPS1
);
7036 /* Even on a big endian machine $fn comes before $fn+1. We have
7037 to adjust when storing to memory. */
7038 macro_build (&offset_expr
, "swc1", "T,o(b)",
7039 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7040 offset_expr
.X_add_number
+= 4;
7041 macro_build (&offset_expr
, "swc1", "T,o(b)",
7042 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7047 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7049 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7052 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7053 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7058 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7060 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7065 as_warn (_("Instruction %s: result is always false"),
7067 move_register (dreg
, 0);
7070 if (imm_expr
.X_op
== O_constant
7071 && imm_expr
.X_add_number
>= 0
7072 && imm_expr
.X_add_number
< 0x10000)
7074 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7076 else if (imm_expr
.X_op
== O_constant
7077 && imm_expr
.X_add_number
> -0x8000
7078 && imm_expr
.X_add_number
< 0)
7080 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7081 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7082 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7086 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7087 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7090 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7093 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7099 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7100 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7103 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7105 if (imm_expr
.X_op
== O_constant
7106 && imm_expr
.X_add_number
>= -0x8000
7107 && imm_expr
.X_add_number
< 0x8000)
7109 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7110 dreg
, sreg
, BFD_RELOC_LO16
);
7114 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7115 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7119 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7122 case M_SGT
: /* sreg > treg <==> treg < sreg */
7128 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7131 case M_SGT_I
: /* sreg > I <==> I < sreg */
7138 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7139 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7142 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7148 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7149 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7152 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7159 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7160 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7161 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7165 if (imm_expr
.X_op
== O_constant
7166 && imm_expr
.X_add_number
>= -0x8000
7167 && imm_expr
.X_add_number
< 0x8000)
7169 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7173 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7174 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7178 if (imm_expr
.X_op
== O_constant
7179 && imm_expr
.X_add_number
>= -0x8000
7180 && imm_expr
.X_add_number
< 0x8000)
7182 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7187 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7188 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7193 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7195 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7198 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7199 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7204 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7206 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7211 as_warn (_("Instruction %s: result is always true"),
7213 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7214 dreg
, 0, BFD_RELOC_LO16
);
7217 if (imm_expr
.X_op
== O_constant
7218 && imm_expr
.X_add_number
>= 0
7219 && imm_expr
.X_add_number
< 0x10000)
7221 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7223 else if (imm_expr
.X_op
== O_constant
7224 && imm_expr
.X_add_number
> -0x8000
7225 && imm_expr
.X_add_number
< 0)
7227 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7228 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7229 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7233 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7234 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7237 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7243 if (imm_expr
.X_op
== O_constant
7244 && imm_expr
.X_add_number
> -0x8000
7245 && imm_expr
.X_add_number
<= 0x8000)
7247 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7248 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7249 dreg
, sreg
, BFD_RELOC_LO16
);
7253 load_register (AT
, &imm_expr
, dbl
);
7254 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7260 if (imm_expr
.X_op
== O_constant
7261 && imm_expr
.X_add_number
> -0x8000
7262 && imm_expr
.X_add_number
<= 0x8000)
7264 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7265 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7266 dreg
, sreg
, BFD_RELOC_LO16
);
7270 load_register (AT
, &imm_expr
, dbl
);
7271 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7293 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7294 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7299 assert (mips_opts
.isa
== ISA_MIPS1
);
7301 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7302 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7305 * Is the double cfc1 instruction a bug in the mips assembler;
7306 * or is there a reason for it?
7309 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7310 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7311 macro_build (NULL
, "nop", "");
7312 expr1
.X_add_number
= 3;
7313 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7314 expr1
.X_add_number
= 2;
7315 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7316 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7317 macro_build (NULL
, "nop", "");
7318 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7320 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7321 macro_build (NULL
, "nop", "");
7332 if (offset_expr
.X_add_number
>= 0x7fff)
7333 as_bad (_("operand overflow"));
7334 if (! target_big_endian
)
7335 ++offset_expr
.X_add_number
;
7336 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7337 if (! target_big_endian
)
7338 --offset_expr
.X_add_number
;
7340 ++offset_expr
.X_add_number
;
7341 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7342 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7343 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7356 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7357 as_bad (_("operand overflow"));
7365 if (! target_big_endian
)
7366 offset_expr
.X_add_number
+= off
;
7367 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7368 if (! target_big_endian
)
7369 offset_expr
.X_add_number
-= off
;
7371 offset_expr
.X_add_number
+= off
;
7372 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7374 /* If necessary, move the result in tempreg the final destination. */
7375 if (treg
== tempreg
)
7377 /* Protect second load's delay slot. */
7379 move_register (treg
, tempreg
);
7393 load_address (AT
, &offset_expr
, &used_at
);
7395 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7396 if (! target_big_endian
)
7397 expr1
.X_add_number
= off
;
7399 expr1
.X_add_number
= 0;
7400 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7401 if (! target_big_endian
)
7402 expr1
.X_add_number
= 0;
7404 expr1
.X_add_number
= off
;
7405 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7411 load_address (AT
, &offset_expr
, &used_at
);
7413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7414 if (target_big_endian
)
7415 expr1
.X_add_number
= 0;
7416 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7417 treg
, BFD_RELOC_LO16
, AT
);
7418 if (target_big_endian
)
7419 expr1
.X_add_number
= 1;
7421 expr1
.X_add_number
= 0;
7422 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7423 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7424 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7429 if (offset_expr
.X_add_number
>= 0x7fff)
7430 as_bad (_("operand overflow"));
7431 if (target_big_endian
)
7432 ++offset_expr
.X_add_number
;
7433 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7434 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7435 if (target_big_endian
)
7436 --offset_expr
.X_add_number
;
7438 ++offset_expr
.X_add_number
;
7439 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7452 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7453 as_bad (_("operand overflow"));
7454 if (! target_big_endian
)
7455 offset_expr
.X_add_number
+= off
;
7456 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7457 if (! target_big_endian
)
7458 offset_expr
.X_add_number
-= off
;
7460 offset_expr
.X_add_number
+= off
;
7461 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7475 load_address (AT
, &offset_expr
, &used_at
);
7477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7478 if (! target_big_endian
)
7479 expr1
.X_add_number
= off
;
7481 expr1
.X_add_number
= 0;
7482 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7483 if (! target_big_endian
)
7484 expr1
.X_add_number
= 0;
7486 expr1
.X_add_number
= off
;
7487 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7492 load_address (AT
, &offset_expr
, &used_at
);
7494 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7495 if (! target_big_endian
)
7496 expr1
.X_add_number
= 0;
7497 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7498 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7499 if (! target_big_endian
)
7500 expr1
.X_add_number
= 1;
7502 expr1
.X_add_number
= 0;
7503 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7504 if (! target_big_endian
)
7505 expr1
.X_add_number
= 0;
7507 expr1
.X_add_number
= 1;
7508 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7509 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7510 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7514 /* FIXME: Check if this is one of the itbl macros, since they
7515 are added dynamically. */
7516 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7519 if (mips_opts
.noat
&& used_at
)
7520 as_bad (_("Macro used $at after \".set noat\""));
7523 /* Implement macros in mips16 mode. */
7526 mips16_macro (struct mips_cl_insn
*ip
)
7529 int xreg
, yreg
, zreg
, tmp
;
7532 const char *s
, *s2
, *s3
;
7534 mask
= ip
->insn_mo
->mask
;
7536 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7537 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7538 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7540 expr1
.X_op
= O_constant
;
7541 expr1
.X_op_symbol
= NULL
;
7542 expr1
.X_add_symbol
= NULL
;
7543 expr1
.X_add_number
= 1;
7563 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7564 expr1
.X_add_number
= 2;
7565 macro_build (&expr1
, "bnez", "x,p", yreg
);
7566 macro_build (NULL
, "break", "6", 7);
7568 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7569 since that causes an overflow. We should do that as well,
7570 but I don't see how to do the comparisons without a temporary
7573 macro_build (NULL
, s
, "x", zreg
);
7593 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7594 expr1
.X_add_number
= 2;
7595 macro_build (&expr1
, "bnez", "x,p", yreg
);
7596 macro_build (NULL
, "break", "6", 7);
7598 macro_build (NULL
, s2
, "x", zreg
);
7604 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7605 macro_build (NULL
, "mflo", "x", zreg
);
7613 if (imm_expr
.X_op
!= O_constant
)
7614 as_bad (_("Unsupported large constant"));
7615 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7616 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7620 if (imm_expr
.X_op
!= O_constant
)
7621 as_bad (_("Unsupported large constant"));
7622 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7623 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7627 if (imm_expr
.X_op
!= O_constant
)
7628 as_bad (_("Unsupported large constant"));
7629 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7630 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7652 goto do_reverse_branch
;
7656 goto do_reverse_branch
;
7668 goto do_reverse_branch
;
7679 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7680 macro_build (&offset_expr
, s2
, "p");
7707 goto do_addone_branch_i
;
7712 goto do_addone_branch_i
;
7727 goto do_addone_branch_i
;
7734 if (imm_expr
.X_op
!= O_constant
)
7735 as_bad (_("Unsupported large constant"));
7736 ++imm_expr
.X_add_number
;
7739 macro_build (&imm_expr
, s
, s3
, xreg
);
7740 macro_build (&offset_expr
, s2
, "p");
7744 expr1
.X_add_number
= 0;
7745 macro_build (&expr1
, "slti", "x,8", yreg
);
7747 move_register (xreg
, yreg
);
7748 expr1
.X_add_number
= 2;
7749 macro_build (&expr1
, "bteqz", "p");
7750 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7754 /* For consistency checking, verify that all bits are specified either
7755 by the match/mask part of the instruction definition, or by the
7758 validate_mips_insn (const struct mips_opcode
*opc
)
7760 const char *p
= opc
->args
;
7762 unsigned long used_bits
= opc
->mask
;
7764 if ((used_bits
& opc
->match
) != opc
->match
)
7766 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7767 opc
->name
, opc
->args
);
7770 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7780 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7781 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7782 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7783 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7784 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7785 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7786 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7787 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7788 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7790 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7791 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
7792 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7794 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7795 c
, opc
->name
, opc
->args
);
7799 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7800 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7802 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7803 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7804 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7805 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7807 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7808 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7810 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7811 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7813 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7814 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7815 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7816 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7817 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7818 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7819 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7820 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7821 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7822 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7823 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7824 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7825 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7826 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7827 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7828 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7829 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7831 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7832 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7833 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7834 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7836 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7837 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7838 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7839 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7840 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7841 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7842 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7843 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7844 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7847 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7848 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7849 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7850 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7851 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7854 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
7855 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
7856 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
7857 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7858 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
7859 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
7860 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
7861 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
7862 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
7863 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
7864 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
7865 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
7866 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
7867 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
7868 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
7869 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7871 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7872 c
, opc
->name
, opc
->args
);
7876 if (used_bits
!= 0xffffffff)
7878 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7879 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7885 /* This routine assembles an instruction into its binary format. As a
7886 side effect, it sets one of the global variables imm_reloc or
7887 offset_reloc to the type of relocation to do if one of the operands
7888 is an address expression. */
7891 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7896 struct mips_opcode
*insn
;
7899 unsigned int lastregno
= 0;
7900 unsigned int lastpos
= 0;
7901 unsigned int limlo
, limhi
;
7904 offsetT min_range
, max_range
;
7908 /* If the instruction contains a '.', we first try to match an instruction
7909 including the '.'. Then we try again without the '.'. */
7911 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7914 /* If we stopped on whitespace, then replace the whitespace with null for
7915 the call to hash_find. Save the character we replaced just in case we
7916 have to re-parse the instruction. */
7923 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7925 /* If we didn't find the instruction in the opcode table, try again, but
7926 this time with just the instruction up to, but not including the
7930 /* Restore the character we overwrite above (if any). */
7934 /* Scan up to the first '.' or whitespace. */
7936 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7940 /* If we did not find a '.', then we can quit now. */
7943 insn_error
= "unrecognized opcode";
7947 /* Lookup the instruction in the hash table. */
7949 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7951 insn_error
= "unrecognized opcode";
7961 assert (strcmp (insn
->name
, str
) == 0);
7963 if (OPCODE_IS_MEMBER (insn
,
7965 | (file_ase_mips16
? INSN_MIPS16
: 0)
7966 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7967 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
7968 | (mips_opts
.ase_mt
? INSN_MT
: 0)
7969 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7975 if (insn
->pinfo
!= INSN_MACRO
)
7977 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7983 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7984 && strcmp (insn
->name
, insn
[1].name
) == 0)
7993 static char buf
[100];
7995 _("opcode not supported on this processor: %s (%s)"),
7996 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7997 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8006 create_insn (ip
, insn
);
8008 for (args
= insn
->args
;; ++args
)
8012 s
+= strspn (s
, " \t");
8016 case '\0': /* end of args */
8021 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8022 my_getExpression (&imm_expr
, s
);
8023 check_absolute_expr (ip
, &imm_expr
);
8024 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8026 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8027 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8028 imm_expr
.X_add_number
&= OP_MASK_SA3
;
8030 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA3
;
8031 imm_expr
.X_op
= O_absent
;
8035 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8036 my_getExpression (&imm_expr
, s
);
8037 check_absolute_expr (ip
, &imm_expr
);
8038 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8040 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8041 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8042 imm_expr
.X_add_number
&= OP_MASK_SA4
;
8044 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA4
;
8045 imm_expr
.X_op
= O_absent
;
8049 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8050 my_getExpression (&imm_expr
, s
);
8051 check_absolute_expr (ip
, &imm_expr
);
8052 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8054 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8055 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8056 imm_expr
.X_add_number
&= OP_MASK_IMM8
;
8058 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_IMM8
;
8059 imm_expr
.X_op
= O_absent
;
8063 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8064 my_getExpression (&imm_expr
, s
);
8065 check_absolute_expr (ip
, &imm_expr
);
8066 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8068 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8069 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8070 imm_expr
.X_add_number
&= OP_MASK_RS
;
8072 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RS
;
8073 imm_expr
.X_op
= O_absent
;
8077 case '7': /* four dsp accumulators in bits 11,12 */
8078 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8079 s
[3] >= '0' && s
[3] <= '3')
8083 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC
;
8087 as_bad (_("Invalid dsp acc register"));
8090 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8091 my_getExpression (&imm_expr
, s
);
8092 check_absolute_expr (ip
, &imm_expr
);
8093 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8095 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8097 (unsigned long) imm_expr
.X_add_number
);
8098 imm_expr
.X_add_number
&= OP_MASK_WRDSP
;
8100 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_WRDSP
;
8101 imm_expr
.X_op
= O_absent
;
8105 case '9': /* four dsp accumulators in bits 21,22 */
8106 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8107 s
[3] >= '0' && s
[3] <= '3')
8111 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC_S
;
8115 as_bad (_("Invalid dsp acc register"));
8118 case '0': /* dsp 6-bit signed immediate in bit 20 */
8119 my_getExpression (&imm_expr
, s
);
8120 check_absolute_expr (ip
, &imm_expr
);
8121 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8122 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8123 if (imm_expr
.X_add_number
< min_range
||
8124 imm_expr
.X_add_number
> max_range
)
8126 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8127 (long) min_range
, (long) max_range
,
8128 (long) imm_expr
.X_add_number
);
8130 imm_expr
.X_add_number
&= OP_MASK_DSPSFT
;
8131 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8133 imm_expr
.X_op
= O_absent
;
8137 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8138 my_getExpression (&imm_expr
, s
);
8139 check_absolute_expr (ip
, &imm_expr
);
8140 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8142 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8144 (unsigned long) imm_expr
.X_add_number
);
8145 imm_expr
.X_add_number
&= OP_MASK_RDDSP
;
8147 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RDDSP
;
8148 imm_expr
.X_op
= O_absent
;
8152 case ':': /* dsp 7-bit signed immediate in bit 19 */
8153 my_getExpression (&imm_expr
, s
);
8154 check_absolute_expr (ip
, &imm_expr
);
8155 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8156 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8157 if (imm_expr
.X_add_number
< min_range
||
8158 imm_expr
.X_add_number
> max_range
)
8160 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8161 (long) min_range
, (long) max_range
,
8162 (long) imm_expr
.X_add_number
);
8164 imm_expr
.X_add_number
&= OP_MASK_DSPSFT_7
;
8165 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8167 imm_expr
.X_op
= O_absent
;
8171 case '@': /* dsp 10-bit signed immediate in bit 16 */
8172 my_getExpression (&imm_expr
, s
);
8173 check_absolute_expr (ip
, &imm_expr
);
8174 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8175 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8176 if (imm_expr
.X_add_number
< min_range
||
8177 imm_expr
.X_add_number
> max_range
)
8179 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8180 (long) min_range
, (long) max_range
,
8181 (long) imm_expr
.X_add_number
);
8183 imm_expr
.X_add_number
&= OP_MASK_IMM10
;
8184 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8186 imm_expr
.X_op
= O_absent
;
8190 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8191 my_getExpression (&imm_expr
, s
);
8192 check_absolute_expr (ip
, &imm_expr
);
8193 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8195 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8196 OP_MASK_MT_U
, (unsigned long) imm_expr
.X_add_number
);
8197 imm_expr
.X_add_number
&= OP_MASK_MT_U
;
8199 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_U
;
8200 imm_expr
.X_op
= O_absent
;
8204 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8205 my_getExpression (&imm_expr
, s
);
8206 check_absolute_expr (ip
, &imm_expr
);
8207 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8209 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8210 OP_MASK_MT_H
, (unsigned long) imm_expr
.X_add_number
);
8211 imm_expr
.X_add_number
&= OP_MASK_MT_H
;
8213 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_H
;
8214 imm_expr
.X_op
= O_absent
;
8218 case '*': /* four dsp accumulators in bits 18,19 */
8219 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8220 s
[3] >= '0' && s
[3] <= '3')
8224 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_T
;
8228 as_bad (_("Invalid dsp/smartmips acc register"));
8231 case '&': /* four dsp accumulators in bits 13,14 */
8232 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8233 s
[3] >= '0' && s
[3] <= '3')
8237 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_D
;
8241 as_bad (_("Invalid dsp/smartmips acc register"));
8252 INSERT_OPERAND (RS
, *ip
, lastregno
);
8256 INSERT_OPERAND (RT
, *ip
, lastregno
);
8260 INSERT_OPERAND (FT
, *ip
, lastregno
);
8264 INSERT_OPERAND (FS
, *ip
, lastregno
);
8270 /* Handle optional base register.
8271 Either the base register is omitted or
8272 we must have a left paren. */
8273 /* This is dependent on the next operand specifier
8274 is a base register specification. */
8275 assert (args
[1] == 'b' || args
[1] == '5'
8276 || args
[1] == '-' || args
[1] == '4');
8280 case ')': /* these must match exactly */
8287 case '+': /* Opcode extension character. */
8290 case 'A': /* ins/ext position, becomes LSB. */
8299 my_getExpression (&imm_expr
, s
);
8300 check_absolute_expr (ip
, &imm_expr
);
8301 if ((unsigned long) imm_expr
.X_add_number
< limlo
8302 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8304 as_bad (_("Improper position (%lu)"),
8305 (unsigned long) imm_expr
.X_add_number
);
8306 imm_expr
.X_add_number
= limlo
;
8308 lastpos
= imm_expr
.X_add_number
;
8309 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8310 imm_expr
.X_op
= O_absent
;
8314 case 'B': /* ins size, becomes MSB. */
8323 my_getExpression (&imm_expr
, s
);
8324 check_absolute_expr (ip
, &imm_expr
);
8325 /* Check for negative input so that small negative numbers
8326 will not succeed incorrectly. The checks against
8327 (pos+size) transitively check "size" itself,
8328 assuming that "pos" is reasonable. */
8329 if ((long) imm_expr
.X_add_number
< 0
8330 || ((unsigned long) imm_expr
.X_add_number
8332 || ((unsigned long) imm_expr
.X_add_number
8335 as_bad (_("Improper insert size (%lu, position %lu)"),
8336 (unsigned long) imm_expr
.X_add_number
,
8337 (unsigned long) lastpos
);
8338 imm_expr
.X_add_number
= limlo
- lastpos
;
8340 INSERT_OPERAND (INSMSB
, *ip
,
8341 lastpos
+ imm_expr
.X_add_number
- 1);
8342 imm_expr
.X_op
= O_absent
;
8346 case 'C': /* ext size, becomes MSBD. */
8359 my_getExpression (&imm_expr
, s
);
8360 check_absolute_expr (ip
, &imm_expr
);
8361 /* Check for negative input so that small negative numbers
8362 will not succeed incorrectly. The checks against
8363 (pos+size) transitively check "size" itself,
8364 assuming that "pos" is reasonable. */
8365 if ((long) imm_expr
.X_add_number
< 0
8366 || ((unsigned long) imm_expr
.X_add_number
8368 || ((unsigned long) imm_expr
.X_add_number
8371 as_bad (_("Improper extract size (%lu, position %lu)"),
8372 (unsigned long) imm_expr
.X_add_number
,
8373 (unsigned long) lastpos
);
8374 imm_expr
.X_add_number
= limlo
- lastpos
;
8376 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8377 imm_expr
.X_op
= O_absent
;
8382 /* +D is for disassembly only; never match. */
8386 /* "+I" is like "I", except that imm2_expr is used. */
8387 my_getExpression (&imm2_expr
, s
);
8388 if (imm2_expr
.X_op
!= O_big
8389 && imm2_expr
.X_op
!= O_constant
)
8390 insn_error
= _("absolute expression required");
8391 if (HAVE_32BIT_GPRS
)
8392 normalize_constant_expr (&imm2_expr
);
8396 case 'T': /* Coprocessor register */
8397 /* +T is for disassembly only; never match. */
8400 case 't': /* Coprocessor register number */
8401 if (s
[0] == '$' && ISDIGIT (s
[1]))
8411 while (ISDIGIT (*s
));
8413 as_bad (_("Invalid register number (%d)"), regno
);
8416 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8421 as_bad (_("Invalid coprocessor 0 register number"));
8425 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8426 *args
, insn
->name
, insn
->args
);
8427 /* Further processing is fruitless. */
8432 case '<': /* must be at least one digit */
8434 * According to the manual, if the shift amount is greater
8435 * than 31 or less than 0, then the shift amount should be
8436 * mod 32. In reality the mips assembler issues an error.
8437 * We issue a warning and mask out all but the low 5 bits.
8439 my_getExpression (&imm_expr
, s
);
8440 check_absolute_expr (ip
, &imm_expr
);
8441 if ((unsigned long) imm_expr
.X_add_number
> 31)
8442 as_warn (_("Improper shift amount (%lu)"),
8443 (unsigned long) imm_expr
.X_add_number
);
8444 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8445 imm_expr
.X_op
= O_absent
;
8449 case '>': /* shift amount minus 32 */
8450 my_getExpression (&imm_expr
, s
);
8451 check_absolute_expr (ip
, &imm_expr
);
8452 if ((unsigned long) imm_expr
.X_add_number
< 32
8453 || (unsigned long) imm_expr
.X_add_number
> 63)
8455 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8456 imm_expr
.X_op
= O_absent
;
8460 case 'k': /* cache code */
8461 case 'h': /* prefx code */
8462 my_getExpression (&imm_expr
, s
);
8463 check_absolute_expr (ip
, &imm_expr
);
8464 if ((unsigned long) imm_expr
.X_add_number
> 31)
8465 as_warn (_("Invalid value for `%s' (%lu)"),
8467 (unsigned long) imm_expr
.X_add_number
);
8469 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8471 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8472 imm_expr
.X_op
= O_absent
;
8476 case 'c': /* break code */
8477 my_getExpression (&imm_expr
, s
);
8478 check_absolute_expr (ip
, &imm_expr
);
8479 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8480 as_warn (_("Illegal break code (%lu)"),
8481 (unsigned long) imm_expr
.X_add_number
);
8482 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8483 imm_expr
.X_op
= O_absent
;
8487 case 'q': /* lower break code */
8488 my_getExpression (&imm_expr
, s
);
8489 check_absolute_expr (ip
, &imm_expr
);
8490 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8491 as_warn (_("Illegal lower break code (%lu)"),
8492 (unsigned long) imm_expr
.X_add_number
);
8493 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8494 imm_expr
.X_op
= O_absent
;
8498 case 'B': /* 20-bit syscall/break code. */
8499 my_getExpression (&imm_expr
, s
);
8500 check_absolute_expr (ip
, &imm_expr
);
8501 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8502 as_warn (_("Illegal 20-bit code (%lu)"),
8503 (unsigned long) imm_expr
.X_add_number
);
8504 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8505 imm_expr
.X_op
= O_absent
;
8509 case 'C': /* Coprocessor code */
8510 my_getExpression (&imm_expr
, s
);
8511 check_absolute_expr (ip
, &imm_expr
);
8512 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8514 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8515 (unsigned long) imm_expr
.X_add_number
);
8516 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8518 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8519 imm_expr
.X_op
= O_absent
;
8523 case 'J': /* 19-bit wait code. */
8524 my_getExpression (&imm_expr
, s
);
8525 check_absolute_expr (ip
, &imm_expr
);
8526 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8527 as_warn (_("Illegal 19-bit code (%lu)"),
8528 (unsigned long) imm_expr
.X_add_number
);
8529 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8530 imm_expr
.X_op
= O_absent
;
8534 case 'P': /* Performance register */
8535 my_getExpression (&imm_expr
, s
);
8536 check_absolute_expr (ip
, &imm_expr
);
8537 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8538 as_warn (_("Invalid performance register (%lu)"),
8539 (unsigned long) imm_expr
.X_add_number
);
8540 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8541 imm_expr
.X_op
= O_absent
;
8545 case 'b': /* base register */
8546 case 'd': /* destination register */
8547 case 's': /* source register */
8548 case 't': /* target register */
8549 case 'r': /* both target and source */
8550 case 'v': /* both dest and source */
8551 case 'w': /* both dest and target */
8552 case 'E': /* coprocessor target register */
8553 case 'G': /* coprocessor destination register */
8554 case 'K': /* 'rdhwr' destination register */
8555 case 'x': /* ignore register name */
8556 case 'z': /* must be zero register */
8557 case 'U': /* destination register (clo/clz). */
8558 case 'g': /* coprocessor destination register */
8573 while (ISDIGIT (*s
));
8575 as_bad (_("Invalid register number (%d)"), regno
);
8577 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8581 if (s
[1] == 'r' && s
[2] == 'a')
8586 else if (s
[1] == 'f' && s
[2] == 'p')
8591 else if (s
[1] == 's' && s
[2] == 'p')
8596 else if (s
[1] == 'g' && s
[2] == 'p')
8601 else if (s
[1] == 'a' && s
[2] == 't')
8606 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8611 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8616 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8621 else if (itbl_have_entries
)
8626 p
= s
+ 1; /* advance past '$' */
8627 n
= itbl_get_field (&p
); /* n is name */
8629 /* See if this is a register defined in an
8631 if (itbl_get_reg_val (n
, &r
))
8633 /* Get_field advances to the start of
8634 the next field, so we need to back
8635 rack to the end of the last field. */
8639 s
= strchr (s
, '\0');
8653 as_warn (_("Used $at without \".set noat\""));
8659 if (c
== 'r' || c
== 'v' || c
== 'w')
8666 /* 'z' only matches $0. */
8667 if (c
== 'z' && regno
!= 0)
8670 /* Now that we have assembled one operand, we use the args string
8671 * to figure out where it goes in the instruction. */
8678 INSERT_OPERAND (RS
, *ip
, regno
);
8684 INSERT_OPERAND (RD
, *ip
, regno
);
8687 INSERT_OPERAND (RD
, *ip
, regno
);
8688 INSERT_OPERAND (RT
, *ip
, regno
);
8693 INSERT_OPERAND (RT
, *ip
, regno
);
8696 /* This case exists because on the r3000 trunc
8697 expands into a macro which requires a gp
8698 register. On the r6000 or r4000 it is
8699 assembled into a single instruction which
8700 ignores the register. Thus the insn version
8701 is MIPS_ISA2 and uses 'x', and the macro
8702 version is MIPS_ISA1 and uses 't'. */
8705 /* This case is for the div instruction, which
8706 acts differently if the destination argument
8707 is $0. This only matches $0, and is checked
8708 outside the switch. */
8711 /* Itbl operand; not yet implemented. FIXME ?? */
8713 /* What about all other operands like 'i', which
8714 can be specified in the opcode table? */
8724 INSERT_OPERAND (RS
, *ip
, lastregno
);
8727 INSERT_OPERAND (RT
, *ip
, lastregno
);
8732 case 'O': /* MDMX alignment immediate constant. */
8733 my_getExpression (&imm_expr
, s
);
8734 check_absolute_expr (ip
, &imm_expr
);
8735 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8736 as_warn ("Improper align amount (%ld), using low bits",
8737 (long) imm_expr
.X_add_number
);
8738 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8739 imm_expr
.X_op
= O_absent
;
8743 case 'Q': /* MDMX vector, element sel, or const. */
8746 /* MDMX Immediate. */
8747 my_getExpression (&imm_expr
, s
);
8748 check_absolute_expr (ip
, &imm_expr
);
8749 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8750 as_warn (_("Invalid MDMX Immediate (%ld)"),
8751 (long) imm_expr
.X_add_number
);
8752 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8753 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8754 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8756 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8757 imm_expr
.X_op
= O_absent
;
8761 /* Not MDMX Immediate. Fall through. */
8762 case 'X': /* MDMX destination register. */
8763 case 'Y': /* MDMX source register. */
8764 case 'Z': /* MDMX target register. */
8766 case 'D': /* floating point destination register */
8767 case 'S': /* floating point source register */
8768 case 'T': /* floating point target register */
8769 case 'R': /* floating point source register */
8773 /* Accept $fN for FP and MDMX register numbers, and in
8774 addition accept $vN for MDMX register numbers. */
8775 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8776 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8787 while (ISDIGIT (*s
));
8790 as_bad (_("Invalid float register number (%d)"), regno
);
8792 if ((regno
& 1) != 0
8794 && ! (strcmp (str
, "mtc1") == 0
8795 || strcmp (str
, "mfc1") == 0
8796 || strcmp (str
, "lwc1") == 0
8797 || strcmp (str
, "swc1") == 0
8798 || strcmp (str
, "l.s") == 0
8799 || strcmp (str
, "s.s") == 0
8800 || strcmp (str
, "mftc1") == 0
8801 || strcmp (str
, "mfthc1") == 0
8802 || strcmp (str
, "cftc1") == 0
8803 || strcmp (str
, "mttc1") == 0
8804 || strcmp (str
, "mtthc1") == 0
8805 || strcmp (str
, "cttc1") == 0))
8806 as_warn (_("Float register should be even, was %d"),
8814 if (c
== 'V' || c
== 'W')
8825 INSERT_OPERAND (FD
, *ip
, regno
);
8830 INSERT_OPERAND (FS
, *ip
, regno
);
8833 /* This is like 'Z', but also needs to fix the MDMX
8834 vector/scalar select bits. Note that the
8835 scalar immediate case is handled above. */
8838 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8839 int max_el
= (is_qh
? 3 : 7);
8841 my_getExpression(&imm_expr
, s
);
8842 check_absolute_expr (ip
, &imm_expr
);
8844 if (imm_expr
.X_add_number
> max_el
)
8845 as_bad(_("Bad element selector %ld"),
8846 (long) imm_expr
.X_add_number
);
8847 imm_expr
.X_add_number
&= max_el
;
8848 ip
->insn_opcode
|= (imm_expr
.X_add_number
8851 imm_expr
.X_op
= O_absent
;
8853 as_warn(_("Expecting ']' found '%s'"), s
);
8859 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8860 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8863 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8870 INSERT_OPERAND (FT
, *ip
, regno
);
8873 INSERT_OPERAND (FR
, *ip
, regno
);
8883 INSERT_OPERAND (FS
, *ip
, lastregno
);
8886 INSERT_OPERAND (FT
, *ip
, lastregno
);
8892 my_getExpression (&imm_expr
, s
);
8893 if (imm_expr
.X_op
!= O_big
8894 && imm_expr
.X_op
!= O_constant
)
8895 insn_error
= _("absolute expression required");
8896 if (HAVE_32BIT_GPRS
)
8897 normalize_constant_expr (&imm_expr
);
8902 my_getExpression (&offset_expr
, s
);
8903 normalize_address_expr (&offset_expr
);
8904 *imm_reloc
= BFD_RELOC_32
;
8917 unsigned char temp
[8];
8919 unsigned int length
;
8924 /* These only appear as the last operand in an
8925 instruction, and every instruction that accepts
8926 them in any variant accepts them in all variants.
8927 This means we don't have to worry about backing out
8928 any changes if the instruction does not match.
8930 The difference between them is the size of the
8931 floating point constant and where it goes. For 'F'
8932 and 'L' the constant is 64 bits; for 'f' and 'l' it
8933 is 32 bits. Where the constant is placed is based
8934 on how the MIPS assembler does things:
8937 f -- immediate value
8940 The .lit4 and .lit8 sections are only used if
8941 permitted by the -G argument.
8943 The code below needs to know whether the target register
8944 is 32 or 64 bits wide. It relies on the fact 'f' and
8945 'F' are used with GPR-based instructions and 'l' and
8946 'L' are used with FPR-based instructions. */
8948 f64
= *args
== 'F' || *args
== 'L';
8949 using_gprs
= *args
== 'F' || *args
== 'f';
8951 save_in
= input_line_pointer
;
8952 input_line_pointer
= s
;
8953 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8955 s
= input_line_pointer
;
8956 input_line_pointer
= save_in
;
8957 if (err
!= NULL
&& *err
!= '\0')
8959 as_bad (_("Bad floating point constant: %s"), err
);
8960 memset (temp
, '\0', sizeof temp
);
8961 length
= f64
? 8 : 4;
8964 assert (length
== (unsigned) (f64
? 8 : 4));
8968 && (g_switch_value
< 4
8969 || (temp
[0] == 0 && temp
[1] == 0)
8970 || (temp
[2] == 0 && temp
[3] == 0))))
8972 imm_expr
.X_op
= O_constant
;
8973 if (! target_big_endian
)
8974 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8976 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8979 && ! mips_disable_float_construction
8980 /* Constants can only be constructed in GPRs and
8981 copied to FPRs if the GPRs are at least as wide
8982 as the FPRs. Force the constant into memory if
8983 we are using 64-bit FPRs but the GPRs are only
8986 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8987 && ((temp
[0] == 0 && temp
[1] == 0)
8988 || (temp
[2] == 0 && temp
[3] == 0))
8989 && ((temp
[4] == 0 && temp
[5] == 0)
8990 || (temp
[6] == 0 && temp
[7] == 0)))
8992 /* The value is simple enough to load with a couple of
8993 instructions. If using 32-bit registers, set
8994 imm_expr to the high order 32 bits and offset_expr to
8995 the low order 32 bits. Otherwise, set imm_expr to
8996 the entire 64 bit constant. */
8997 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8999 imm_expr
.X_op
= O_constant
;
9000 offset_expr
.X_op
= O_constant
;
9001 if (! target_big_endian
)
9003 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9004 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9008 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9009 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9011 if (offset_expr
.X_add_number
== 0)
9012 offset_expr
.X_op
= O_absent
;
9014 else if (sizeof (imm_expr
.X_add_number
) > 4)
9016 imm_expr
.X_op
= O_constant
;
9017 if (! target_big_endian
)
9018 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9020 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9024 imm_expr
.X_op
= O_big
;
9025 imm_expr
.X_add_number
= 4;
9026 if (! target_big_endian
)
9028 generic_bignum
[0] = bfd_getl16 (temp
);
9029 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9030 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9031 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9035 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9036 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9037 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9038 generic_bignum
[3] = bfd_getb16 (temp
);
9044 const char *newname
;
9047 /* Switch to the right section. */
9049 subseg
= now_subseg
;
9052 default: /* unused default case avoids warnings. */
9054 newname
= RDATA_SECTION_NAME
;
9055 if (g_switch_value
>= 8)
9059 newname
= RDATA_SECTION_NAME
;
9062 assert (g_switch_value
>= 4);
9066 new_seg
= subseg_new (newname
, (subsegT
) 0);
9067 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9068 bfd_set_section_flags (stdoutput
, new_seg
,
9073 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9074 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9075 && strcmp (TARGET_OS
, "elf") != 0)
9076 record_alignment (new_seg
, 4);
9078 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9080 as_bad (_("Can't use floating point insn in this section"));
9082 /* Set the argument to the current address in the
9084 offset_expr
.X_op
= O_symbol
;
9085 offset_expr
.X_add_symbol
=
9086 symbol_new ("L0\001", now_seg
,
9087 (valueT
) frag_now_fix (), frag_now
);
9088 offset_expr
.X_add_number
= 0;
9090 /* Put the floating point number into the section. */
9091 p
= frag_more ((int) length
);
9092 memcpy (p
, temp
, length
);
9094 /* Switch back to the original section. */
9095 subseg_set (seg
, subseg
);
9100 case 'i': /* 16 bit unsigned immediate */
9101 case 'j': /* 16 bit signed immediate */
9102 *imm_reloc
= BFD_RELOC_LO16
;
9103 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9106 offsetT minval
, maxval
;
9108 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9109 && strcmp (insn
->name
, insn
[1].name
) == 0);
9111 /* If the expression was written as an unsigned number,
9112 only treat it as signed if there are no more
9116 && sizeof (imm_expr
.X_add_number
) <= 4
9117 && imm_expr
.X_op
== O_constant
9118 && imm_expr
.X_add_number
< 0
9119 && imm_expr
.X_unsigned
9123 /* For compatibility with older assemblers, we accept
9124 0x8000-0xffff as signed 16-bit numbers when only
9125 signed numbers are allowed. */
9127 minval
= 0, maxval
= 0xffff;
9129 minval
= -0x8000, maxval
= 0x7fff;
9131 minval
= -0x8000, maxval
= 0xffff;
9133 if (imm_expr
.X_op
!= O_constant
9134 || imm_expr
.X_add_number
< minval
9135 || imm_expr
.X_add_number
> maxval
)
9139 if (imm_expr
.X_op
== O_constant
9140 || imm_expr
.X_op
== O_big
)
9141 as_bad (_("expression out of range"));
9147 case 'o': /* 16 bit offset */
9148 /* Check whether there is only a single bracketed expression
9149 left. If so, it must be the base register and the
9150 constant must be zero. */
9151 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9153 offset_expr
.X_op
= O_constant
;
9154 offset_expr
.X_add_number
= 0;
9158 /* If this value won't fit into a 16 bit offset, then go
9159 find a macro that will generate the 32 bit offset
9161 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9162 && (offset_expr
.X_op
!= O_constant
9163 || offset_expr
.X_add_number
>= 0x8000
9164 || offset_expr
.X_add_number
< -0x8000))
9170 case 'p': /* pc relative offset */
9171 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9172 my_getExpression (&offset_expr
, s
);
9176 case 'u': /* upper 16 bits */
9177 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9178 && imm_expr
.X_op
== O_constant
9179 && (imm_expr
.X_add_number
< 0
9180 || imm_expr
.X_add_number
>= 0x10000))
9181 as_bad (_("lui expression not in range 0..65535"));
9185 case 'a': /* 26 bit address */
9186 my_getExpression (&offset_expr
, s
);
9188 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9191 case 'N': /* 3 bit branch condition code */
9192 case 'M': /* 3 bit compare condition code */
9193 if (strncmp (s
, "$fcc", 4) != 0)
9203 while (ISDIGIT (*s
));
9205 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9206 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9207 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9208 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9209 && (regno
& 1) != 0)
9210 as_warn(_("Condition code register should be even for %s, was %d"),
9212 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9213 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9214 && (regno
& 3) != 0)
9215 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9218 INSERT_OPERAND (BCC
, *ip
, regno
);
9220 INSERT_OPERAND (CCC
, *ip
, regno
);
9224 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9235 while (ISDIGIT (*s
));
9238 c
= 8; /* Invalid sel value. */
9241 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9242 ip
->insn_opcode
|= c
;
9246 /* Must be at least one digit. */
9247 my_getExpression (&imm_expr
, s
);
9248 check_absolute_expr (ip
, &imm_expr
);
9250 if ((unsigned long) imm_expr
.X_add_number
9251 > (unsigned long) OP_MASK_VECBYTE
)
9253 as_bad (_("bad byte vector index (%ld)"),
9254 (long) imm_expr
.X_add_number
);
9255 imm_expr
.X_add_number
= 0;
9258 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9259 imm_expr
.X_op
= O_absent
;
9264 my_getExpression (&imm_expr
, s
);
9265 check_absolute_expr (ip
, &imm_expr
);
9267 if ((unsigned long) imm_expr
.X_add_number
9268 > (unsigned long) OP_MASK_VECALIGN
)
9270 as_bad (_("bad byte vector index (%ld)"),
9271 (long) imm_expr
.X_add_number
);
9272 imm_expr
.X_add_number
= 0;
9275 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9276 imm_expr
.X_op
= O_absent
;
9281 as_bad (_("bad char = '%c'\n"), *args
);
9286 /* Args don't match. */
9287 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9288 !strcmp (insn
->name
, insn
[1].name
))
9292 insn_error
= _("illegal operands");
9297 insn_error
= _("illegal operands");
9302 /* This routine assembles an instruction into its binary format when
9303 assembling for the mips16. As a side effect, it sets one of the
9304 global variables imm_reloc or offset_reloc to the type of
9305 relocation to do if one of the operands is an address expression.
9306 It also sets mips16_small and mips16_ext if the user explicitly
9307 requested a small or extended instruction. */
9310 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9314 struct mips_opcode
*insn
;
9317 unsigned int lastregno
= 0;
9323 mips16_small
= FALSE
;
9326 for (s
= str
; ISLOWER (*s
); ++s
)
9338 if (s
[1] == 't' && s
[2] == ' ')
9341 mips16_small
= TRUE
;
9345 else if (s
[1] == 'e' && s
[2] == ' ')
9354 insn_error
= _("unknown opcode");
9358 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9359 mips16_small
= TRUE
;
9361 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9363 insn_error
= _("unrecognized opcode");
9370 assert (strcmp (insn
->name
, str
) == 0);
9372 create_insn (ip
, insn
);
9373 imm_expr
.X_op
= O_absent
;
9374 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9375 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9376 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9377 imm2_expr
.X_op
= O_absent
;
9378 offset_expr
.X_op
= O_absent
;
9379 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9380 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9381 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9382 for (args
= insn
->args
; 1; ++args
)
9389 /* In this switch statement we call break if we did not find
9390 a match, continue if we did find a match, or return if we
9399 /* Stuff the immediate value in now, if we can. */
9400 if (imm_expr
.X_op
== O_constant
9401 && *imm_reloc
> BFD_RELOC_UNUSED
9402 && insn
->pinfo
!= INSN_MACRO
)
9406 switch (*offset_reloc
)
9408 case BFD_RELOC_MIPS16_HI16_S
:
9409 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9412 case BFD_RELOC_MIPS16_HI16
:
9413 tmp
= imm_expr
.X_add_number
>> 16;
9416 case BFD_RELOC_MIPS16_LO16
:
9417 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9421 case BFD_RELOC_UNUSED
:
9422 tmp
= imm_expr
.X_add_number
;
9428 *offset_reloc
= BFD_RELOC_UNUSED
;
9430 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9431 tmp
, TRUE
, mips16_small
,
9432 mips16_ext
, &ip
->insn_opcode
,
9433 &ip
->use_extend
, &ip
->extend
);
9434 imm_expr
.X_op
= O_absent
;
9435 *imm_reloc
= BFD_RELOC_UNUSED
;
9449 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9452 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9468 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9470 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9497 while (ISDIGIT (*s
));
9500 as_bad (_("invalid register number (%d)"), regno
);
9506 if (s
[1] == 'r' && s
[2] == 'a')
9511 else if (s
[1] == 'f' && s
[2] == 'p')
9516 else if (s
[1] == 's' && s
[2] == 'p')
9521 else if (s
[1] == 'g' && s
[2] == 'p')
9526 else if (s
[1] == 'a' && s
[2] == 't')
9531 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9536 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9541 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9554 if (c
== 'v' || c
== 'w')
9556 regno
= mips16_to_32_reg_map
[lastregno
];
9570 regno
= mips32_to_16_reg_map
[regno
];
9575 regno
= ILLEGAL_REG
;
9580 regno
= ILLEGAL_REG
;
9585 regno
= ILLEGAL_REG
;
9590 if (regno
== AT
&& ! mips_opts
.noat
)
9591 as_warn (_("used $at without \".set noat\""));
9598 if (regno
== ILLEGAL_REG
)
9605 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9609 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9612 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9615 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9621 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9624 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9625 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9635 if (strncmp (s
, "$pc", 3) == 0)
9652 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9655 if (imm_expr
.X_op
!= O_constant
)
9658 ip
->use_extend
= TRUE
;
9663 /* We need to relax this instruction. */
9664 *offset_reloc
= *imm_reloc
;
9665 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9670 *imm_reloc
= BFD_RELOC_UNUSED
;
9678 my_getExpression (&imm_expr
, s
);
9679 if (imm_expr
.X_op
== O_register
)
9681 /* What we thought was an expression turned out to
9684 if (s
[0] == '(' && args
[1] == '(')
9686 /* It looks like the expression was omitted
9687 before a register indirection, which means
9688 that the expression is implicitly zero. We
9689 still set up imm_expr, so that we handle
9690 explicit extensions correctly. */
9691 imm_expr
.X_op
= O_constant
;
9692 imm_expr
.X_add_number
= 0;
9693 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9700 /* We need to relax this instruction. */
9701 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9710 /* We use offset_reloc rather than imm_reloc for the PC
9711 relative operands. This lets macros with both
9712 immediate and address operands work correctly. */
9713 my_getExpression (&offset_expr
, s
);
9715 if (offset_expr
.X_op
== O_register
)
9718 /* We need to relax this instruction. */
9719 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9723 case '6': /* break code */
9724 my_getExpression (&imm_expr
, s
);
9725 check_absolute_expr (ip
, &imm_expr
);
9726 if ((unsigned long) imm_expr
.X_add_number
> 63)
9727 as_warn (_("Invalid value for `%s' (%lu)"),
9729 (unsigned long) imm_expr
.X_add_number
);
9730 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9731 imm_expr
.X_op
= O_absent
;
9735 case 'a': /* 26 bit address */
9736 my_getExpression (&offset_expr
, s
);
9738 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9739 ip
->insn_opcode
<<= 16;
9742 case 'l': /* register list for entry macro */
9743 case 'L': /* register list for exit macro */
9753 int freg
, reg1
, reg2
;
9755 while (*s
== ' ' || *s
== ',')
9759 as_bad (_("can't parse register list"));
9771 while (ISDIGIT (*s
))
9793 as_bad (_("invalid register list"));
9798 while (ISDIGIT (*s
))
9805 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9810 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9815 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9816 mask
|= (reg2
- 3) << 3;
9817 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9818 mask
|= (reg2
- 15) << 1;
9819 else if (reg1
== RA
&& reg2
== RA
)
9823 as_bad (_("invalid register list"));
9827 /* The mask is filled in in the opcode table for the
9828 benefit of the disassembler. We remove it before
9829 applying the actual mask. */
9830 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9831 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9835 case 'e': /* extend code */
9836 my_getExpression (&imm_expr
, s
);
9837 check_absolute_expr (ip
, &imm_expr
);
9838 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9840 as_warn (_("Invalid value for `%s' (%lu)"),
9842 (unsigned long) imm_expr
.X_add_number
);
9843 imm_expr
.X_add_number
&= 0x7ff;
9845 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9846 imm_expr
.X_op
= O_absent
;
9856 /* Args don't match. */
9857 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9858 strcmp (insn
->name
, insn
[1].name
) == 0)
9865 insn_error
= _("illegal operands");
9871 /* This structure holds information we know about a mips16 immediate
9874 struct mips16_immed_operand
9876 /* The type code used in the argument string in the opcode table. */
9878 /* The number of bits in the short form of the opcode. */
9880 /* The number of bits in the extended form of the opcode. */
9882 /* The amount by which the short form is shifted when it is used;
9883 for example, the sw instruction has a shift count of 2. */
9885 /* The amount by which the short form is shifted when it is stored
9886 into the instruction code. */
9888 /* Non-zero if the short form is unsigned. */
9890 /* Non-zero if the extended form is unsigned. */
9892 /* Non-zero if the value is PC relative. */
9896 /* The mips16 immediate operand types. */
9898 static const struct mips16_immed_operand mips16_immed_operands
[] =
9900 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9901 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9902 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9903 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9904 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9905 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9906 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9907 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9908 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9909 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9910 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9911 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9912 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9913 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9914 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9915 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9916 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9917 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9918 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9919 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9920 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9923 #define MIPS16_NUM_IMMED \
9924 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9926 /* Handle a mips16 instruction with an immediate value. This or's the
9927 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9928 whether an extended value is needed; if one is needed, it sets
9929 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9930 If SMALL is true, an unextended opcode was explicitly requested.
9931 If EXT is true, an extended opcode was explicitly requested. If
9932 WARN is true, warn if EXT does not match reality. */
9935 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9936 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9937 unsigned long *insn
, bfd_boolean
*use_extend
,
9938 unsigned short *extend
)
9940 register const struct mips16_immed_operand
*op
;
9941 int mintiny
, maxtiny
;
9942 bfd_boolean needext
;
9944 op
= mips16_immed_operands
;
9945 while (op
->type
!= type
)
9948 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9953 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9956 maxtiny
= 1 << op
->nbits
;
9961 maxtiny
= (1 << op
->nbits
) - 1;
9966 mintiny
= - (1 << (op
->nbits
- 1));
9967 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9970 /* Branch offsets have an implicit 0 in the lowest bit. */
9971 if (type
== 'p' || type
== 'q')
9974 if ((val
& ((1 << op
->shift
) - 1)) != 0
9975 || val
< (mintiny
<< op
->shift
)
9976 || val
> (maxtiny
<< op
->shift
))
9981 if (warn
&& ext
&& ! needext
)
9982 as_warn_where (file
, line
,
9983 _("extended operand requested but not required"));
9984 if (small
&& needext
)
9985 as_bad_where (file
, line
, _("invalid unextended operand value"));
9987 if (small
|| (! ext
&& ! needext
))
9991 *use_extend
= FALSE
;
9992 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9993 insnval
<<= op
->op_shift
;
9998 long minext
, maxext
;
10004 maxext
= (1 << op
->extbits
) - 1;
10008 minext
= - (1 << (op
->extbits
- 1));
10009 maxext
= (1 << (op
->extbits
- 1)) - 1;
10011 if (val
< minext
|| val
> maxext
)
10012 as_bad_where (file
, line
,
10013 _("operand value out of range for instruction"));
10015 *use_extend
= TRUE
;
10016 if (op
->extbits
== 16)
10018 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10021 else if (op
->extbits
== 15)
10023 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10028 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10032 *extend
= (unsigned short) extval
;
10037 struct percent_op_match
10040 bfd_reloc_code_real_type reloc
;
10043 static const struct percent_op_match mips_percent_op
[] =
10045 {"%lo", BFD_RELOC_LO16
},
10047 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10048 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10049 {"%call16", BFD_RELOC_MIPS_CALL16
},
10050 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10051 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10052 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10053 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10054 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10055 {"%got", BFD_RELOC_MIPS_GOT16
},
10056 {"%gp_rel", BFD_RELOC_GPREL16
},
10057 {"%half", BFD_RELOC_16
},
10058 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10059 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10060 {"%neg", BFD_RELOC_MIPS_SUB
},
10061 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10062 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10063 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10064 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10065 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10066 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10067 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10069 {"%hi", BFD_RELOC_HI16_S
}
10072 static const struct percent_op_match mips16_percent_op
[] =
10074 {"%lo", BFD_RELOC_MIPS16_LO16
},
10075 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10076 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10080 /* Return true if *STR points to a relocation operator. When returning true,
10081 move *STR over the operator and store its relocation code in *RELOC.
10082 Leave both *STR and *RELOC alone when returning false. */
10085 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10087 const struct percent_op_match
*percent_op
;
10090 if (mips_opts
.mips16
)
10092 percent_op
= mips16_percent_op
;
10093 limit
= ARRAY_SIZE (mips16_percent_op
);
10097 percent_op
= mips_percent_op
;
10098 limit
= ARRAY_SIZE (mips_percent_op
);
10101 for (i
= 0; i
< limit
; i
++)
10102 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10104 int len
= strlen (percent_op
[i
].str
);
10106 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10109 *str
+= strlen (percent_op
[i
].str
);
10110 *reloc
= percent_op
[i
].reloc
;
10112 /* Check whether the output BFD supports this relocation.
10113 If not, issue an error and fall back on something safe. */
10114 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10116 as_bad ("relocation %s isn't supported by the current ABI",
10117 percent_op
[i
].str
);
10118 *reloc
= BFD_RELOC_UNUSED
;
10126 /* Parse string STR as a 16-bit relocatable operand. Store the
10127 expression in *EP and the relocations in the array starting
10128 at RELOC. Return the number of relocation operators used.
10130 On exit, EXPR_END points to the first character after the expression. */
10133 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10136 bfd_reloc_code_real_type reversed_reloc
[3];
10137 size_t reloc_index
, i
;
10138 int crux_depth
, str_depth
;
10141 /* Search for the start of the main expression, recoding relocations
10142 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10143 of the main expression and with CRUX_DEPTH containing the number
10144 of open brackets at that point. */
10151 crux_depth
= str_depth
;
10153 /* Skip over whitespace and brackets, keeping count of the number
10155 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10160 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10161 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10163 my_getExpression (ep
, crux
);
10166 /* Match every open bracket. */
10167 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10171 if (crux_depth
> 0)
10172 as_bad ("unclosed '('");
10176 if (reloc_index
!= 0)
10178 prev_reloc_op_frag
= frag_now
;
10179 for (i
= 0; i
< reloc_index
; i
++)
10180 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10183 return reloc_index
;
10187 my_getExpression (expressionS
*ep
, char *str
)
10192 save_in
= input_line_pointer
;
10193 input_line_pointer
= str
;
10195 expr_end
= input_line_pointer
;
10196 input_line_pointer
= save_in
;
10198 /* If we are in mips16 mode, and this is an expression based on `.',
10199 then we bump the value of the symbol by 1 since that is how other
10200 text symbols are handled. We don't bother to handle complex
10201 expressions, just `.' plus or minus a constant. */
10202 if (mips_opts
.mips16
10203 && ep
->X_op
== O_symbol
10204 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10205 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10206 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10207 && symbol_constant_p (ep
->X_add_symbol
)
10208 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10209 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10212 /* Turn a string in input_line_pointer into a floating point constant
10213 of type TYPE, and store the appropriate bytes in *LITP. The number
10214 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10215 returned, or NULL on OK. */
10218 md_atof (int type
, char *litP
, int *sizeP
)
10221 LITTLENUM_TYPE words
[4];
10237 return _("bad call to md_atof");
10240 t
= atof_ieee (input_line_pointer
, type
, words
);
10242 input_line_pointer
= t
;
10246 if (! target_big_endian
)
10248 for (i
= prec
- 1; i
>= 0; i
--)
10250 md_number_to_chars (litP
, words
[i
], 2);
10256 for (i
= 0; i
< prec
; i
++)
10258 md_number_to_chars (litP
, words
[i
], 2);
10267 md_number_to_chars (char *buf
, valueT val
, int n
)
10269 if (target_big_endian
)
10270 number_to_chars_bigendian (buf
, val
, n
);
10272 number_to_chars_littleendian (buf
, val
, n
);
10276 static int support_64bit_objects(void)
10278 const char **list
, **l
;
10281 list
= bfd_target_list ();
10282 for (l
= list
; *l
!= NULL
; l
++)
10284 /* This is traditional mips */
10285 if (strcmp (*l
, "elf64-tradbigmips") == 0
10286 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10288 if (strcmp (*l
, "elf64-bigmips") == 0
10289 || strcmp (*l
, "elf64-littlemips") == 0)
10292 yes
= (*l
!= NULL
);
10296 #endif /* OBJ_ELF */
10298 const char *md_shortopts
= "O::g::G:";
10300 struct option md_longopts
[] =
10302 /* Options which specify architecture. */
10303 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10304 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10305 {"march", required_argument
, NULL
, OPTION_MARCH
},
10306 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10307 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10308 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10309 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10310 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10311 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10312 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10313 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10314 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10315 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10316 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10317 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10318 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10319 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10320 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10321 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10322 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10323 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10324 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10325 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10326 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10328 /* Options which specify Application Specific Extensions (ASEs). */
10329 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10330 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10331 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10332 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10333 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10334 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10335 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10336 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10337 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10338 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10339 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10340 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10341 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10342 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10343 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10344 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10345 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10346 #define OPTION_MT (OPTION_ASE_BASE + 8)
10347 {"mmt", no_argument
, NULL
, OPTION_MT
},
10348 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10349 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10351 /* Old-style architecture options. Don't add more of these. */
10352 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
10353 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10354 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10355 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10356 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10357 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10358 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10359 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10360 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10361 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10362 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10363 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10364 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10365 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10366 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10367 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10368 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10370 /* Options which enable bug fixes. */
10371 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10372 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10373 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10374 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10375 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10376 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10377 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10378 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10379 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10380 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10381 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10382 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10383 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10384 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10386 /* Miscellaneous options. */
10387 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10388 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10389 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10390 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10391 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10392 {"break", no_argument
, NULL
, OPTION_BREAK
},
10393 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10394 #define OPTION_EB (OPTION_MISC_BASE + 2)
10395 {"EB", no_argument
, NULL
, OPTION_EB
},
10396 #define OPTION_EL (OPTION_MISC_BASE + 3)
10397 {"EL", no_argument
, NULL
, OPTION_EL
},
10398 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10399 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10400 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10401 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10402 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10403 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10404 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10405 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10406 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10407 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10408 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10409 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10410 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10411 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10412 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10413 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10414 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10415 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10416 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10417 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10418 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10419 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10420 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10421 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10423 /* ELF-specific options. */
10425 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10426 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10427 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10428 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10429 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10430 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10431 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10432 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10433 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10434 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10435 #define OPTION_32 (OPTION_ELF_BASE + 4)
10436 {"32", no_argument
, NULL
, OPTION_32
},
10437 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10438 {"n32", no_argument
, NULL
, OPTION_N32
},
10439 #define OPTION_64 (OPTION_ELF_BASE + 6)
10440 {"64", no_argument
, NULL
, OPTION_64
},
10441 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10442 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10443 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10444 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10445 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10446 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10447 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10448 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10449 #endif /* OBJ_ELF */
10451 {NULL
, no_argument
, NULL
, 0}
10453 size_t md_longopts_size
= sizeof (md_longopts
);
10455 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10456 NEW_VALUE. Warn if another value was already specified. Note:
10457 we have to defer parsing the -march and -mtune arguments in order
10458 to handle 'from-abi' correctly, since the ABI might be specified
10459 in a later argument. */
10462 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10464 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10465 as_warn (_("A different %s was already specified, is now %s"),
10466 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10469 *string_ptr
= new_value
;
10473 md_parse_option (int c
, char *arg
)
10477 case OPTION_CONSTRUCT_FLOATS
:
10478 mips_disable_float_construction
= 0;
10481 case OPTION_NO_CONSTRUCT_FLOATS
:
10482 mips_disable_float_construction
= 1;
10494 target_big_endian
= 1;
10498 target_big_endian
= 0;
10502 if (arg
&& arg
[1] == '0')
10512 mips_debug
= atoi (arg
);
10513 /* When the MIPS assembler sees -g or -g2, it does not do
10514 optimizations which limit full symbolic debugging. We take
10515 that to be equivalent to -O0. */
10516 if (mips_debug
== 2)
10521 file_mips_isa
= ISA_MIPS1
;
10525 file_mips_isa
= ISA_MIPS2
;
10529 file_mips_isa
= ISA_MIPS3
;
10533 file_mips_isa
= ISA_MIPS4
;
10537 file_mips_isa
= ISA_MIPS5
;
10540 case OPTION_MIPS32
:
10541 file_mips_isa
= ISA_MIPS32
;
10544 case OPTION_MIPS32R2
:
10545 file_mips_isa
= ISA_MIPS32R2
;
10548 case OPTION_MIPS64R2
:
10549 file_mips_isa
= ISA_MIPS64R2
;
10552 case OPTION_MIPS64
:
10553 file_mips_isa
= ISA_MIPS64
;
10557 mips_set_option_string (&mips_tune_string
, arg
);
10561 mips_set_option_string (&mips_arch_string
, arg
);
10565 mips_set_option_string (&mips_arch_string
, "4650");
10566 mips_set_option_string (&mips_tune_string
, "4650");
10569 case OPTION_NO_M4650
:
10573 mips_set_option_string (&mips_arch_string
, "4010");
10574 mips_set_option_string (&mips_tune_string
, "4010");
10577 case OPTION_NO_M4010
:
10581 mips_set_option_string (&mips_arch_string
, "4100");
10582 mips_set_option_string (&mips_tune_string
, "4100");
10585 case OPTION_NO_M4100
:
10589 mips_set_option_string (&mips_arch_string
, "3900");
10590 mips_set_option_string (&mips_tune_string
, "3900");
10593 case OPTION_NO_M3900
:
10597 mips_opts
.ase_mdmx
= 1;
10600 case OPTION_NO_MDMX
:
10601 mips_opts
.ase_mdmx
= 0;
10605 mips_opts
.ase_dsp
= 1;
10608 case OPTION_NO_DSP
:
10609 mips_opts
.ase_dsp
= 0;
10613 mips_opts
.ase_mt
= 1;
10617 mips_opts
.ase_mt
= 0;
10620 case OPTION_MIPS16
:
10621 mips_opts
.mips16
= 1;
10622 mips_no_prev_insn ();
10625 case OPTION_NO_MIPS16
:
10626 mips_opts
.mips16
= 0;
10627 mips_no_prev_insn ();
10630 case OPTION_MIPS3D
:
10631 mips_opts
.ase_mips3d
= 1;
10634 case OPTION_NO_MIPS3D
:
10635 mips_opts
.ase_mips3d
= 0;
10638 case OPTION_FIX_VR4120
:
10639 mips_fix_vr4120
= 1;
10642 case OPTION_NO_FIX_VR4120
:
10643 mips_fix_vr4120
= 0;
10646 case OPTION_FIX_VR4130
:
10647 mips_fix_vr4130
= 1;
10650 case OPTION_NO_FIX_VR4130
:
10651 mips_fix_vr4130
= 0;
10654 case OPTION_RELAX_BRANCH
:
10655 mips_relax_branch
= 1;
10658 case OPTION_NO_RELAX_BRANCH
:
10659 mips_relax_branch
= 0;
10662 case OPTION_MSHARED
:
10663 mips_in_shared
= TRUE
;
10666 case OPTION_MNO_SHARED
:
10667 mips_in_shared
= FALSE
;
10670 case OPTION_MSYM32
:
10671 mips_opts
.sym32
= TRUE
;
10674 case OPTION_MNO_SYM32
:
10675 mips_opts
.sym32
= FALSE
;
10679 /* When generating ELF code, we permit -KPIC and -call_shared to
10680 select SVR4_PIC, and -non_shared to select no PIC. This is
10681 intended to be compatible with Irix 5. */
10682 case OPTION_CALL_SHARED
:
10683 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10685 as_bad (_("-call_shared is supported only for ELF format"));
10688 mips_pic
= SVR4_PIC
;
10689 mips_abicalls
= TRUE
;
10690 if (g_switch_seen
&& g_switch_value
!= 0)
10692 as_bad (_("-G may not be used with SVR4 PIC code"));
10695 g_switch_value
= 0;
10698 case OPTION_NON_SHARED
:
10699 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10701 as_bad (_("-non_shared is supported only for ELF format"));
10705 mips_abicalls
= FALSE
;
10708 /* The -xgot option tells the assembler to use 32 offsets when
10709 accessing the got in SVR4_PIC mode. It is for Irix
10714 #endif /* OBJ_ELF */
10717 g_switch_value
= atoi (arg
);
10719 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10721 as_bad (_("-G may not be used with SVR4 PIC code"));
10727 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10730 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10732 as_bad (_("-32 is supported for ELF format only"));
10735 mips_abi
= O32_ABI
;
10739 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10741 as_bad (_("-n32 is supported for ELF format only"));
10744 mips_abi
= N32_ABI
;
10748 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10750 as_bad (_("-64 is supported for ELF format only"));
10753 mips_abi
= N64_ABI
;
10754 if (! support_64bit_objects())
10755 as_fatal (_("No compiled in support for 64 bit object file format"));
10757 #endif /* OBJ_ELF */
10760 file_mips_gp32
= 1;
10764 file_mips_gp32
= 0;
10768 file_mips_fp32
= 1;
10772 file_mips_fp32
= 0;
10777 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10779 as_bad (_("-mabi is supported for ELF format only"));
10782 if (strcmp (arg
, "32") == 0)
10783 mips_abi
= O32_ABI
;
10784 else if (strcmp (arg
, "o64") == 0)
10785 mips_abi
= O64_ABI
;
10786 else if (strcmp (arg
, "n32") == 0)
10787 mips_abi
= N32_ABI
;
10788 else if (strcmp (arg
, "64") == 0)
10790 mips_abi
= N64_ABI
;
10791 if (! support_64bit_objects())
10792 as_fatal (_("No compiled in support for 64 bit object file "
10795 else if (strcmp (arg
, "eabi") == 0)
10796 mips_abi
= EABI_ABI
;
10799 as_fatal (_("invalid abi -mabi=%s"), arg
);
10803 #endif /* OBJ_ELF */
10805 case OPTION_M7000_HILO_FIX
:
10806 mips_7000_hilo_fix
= TRUE
;
10809 case OPTION_MNO_7000_HILO_FIX
:
10810 mips_7000_hilo_fix
= FALSE
;
10814 case OPTION_MDEBUG
:
10815 mips_flag_mdebug
= TRUE
;
10818 case OPTION_NO_MDEBUG
:
10819 mips_flag_mdebug
= FALSE
;
10823 mips_flag_pdr
= TRUE
;
10826 case OPTION_NO_PDR
:
10827 mips_flag_pdr
= FALSE
;
10829 #endif /* OBJ_ELF */
10838 /* Set up globals to generate code for the ISA or processor
10839 described by INFO. */
10842 mips_set_architecture (const struct mips_cpu_info
*info
)
10846 file_mips_arch
= info
->cpu
;
10847 mips_opts
.arch
= info
->cpu
;
10848 mips_opts
.isa
= info
->isa
;
10853 /* Likewise for tuning. */
10856 mips_set_tune (const struct mips_cpu_info
*info
)
10859 mips_tune
= info
->cpu
;
10864 mips_after_parse_args (void)
10866 const struct mips_cpu_info
*arch_info
= 0;
10867 const struct mips_cpu_info
*tune_info
= 0;
10869 /* GP relative stuff not working for PE */
10870 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10872 if (g_switch_seen
&& g_switch_value
!= 0)
10873 as_bad (_("-G not supported in this configuration."));
10874 g_switch_value
= 0;
10877 if (mips_abi
== NO_ABI
)
10878 mips_abi
= MIPS_DEFAULT_ABI
;
10880 /* The following code determines the architecture and register size.
10881 Similar code was added to GCC 3.3 (see override_options() in
10882 config/mips/mips.c). The GAS and GCC code should be kept in sync
10883 as much as possible. */
10885 if (mips_arch_string
!= 0)
10886 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10888 if (file_mips_isa
!= ISA_UNKNOWN
)
10890 /* Handle -mipsN. At this point, file_mips_isa contains the
10891 ISA level specified by -mipsN, while arch_info->isa contains
10892 the -march selection (if any). */
10893 if (arch_info
!= 0)
10895 /* -march takes precedence over -mipsN, since it is more descriptive.
10896 There's no harm in specifying both as long as the ISA levels
10898 if (file_mips_isa
!= arch_info
->isa
)
10899 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10900 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10901 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10904 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10907 if (arch_info
== 0)
10908 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10910 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10911 as_bad ("-march=%s is not compatible with the selected ABI",
10914 mips_set_architecture (arch_info
);
10916 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10917 if (mips_tune_string
!= 0)
10918 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10920 if (tune_info
== 0)
10921 mips_set_tune (arch_info
);
10923 mips_set_tune (tune_info
);
10925 if (file_mips_gp32
>= 0)
10927 /* The user specified the size of the integer registers. Make sure
10928 it agrees with the ABI and ISA. */
10929 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10930 as_bad (_("-mgp64 used with a 32-bit processor"));
10931 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10932 as_bad (_("-mgp32 used with a 64-bit ABI"));
10933 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10934 as_bad (_("-mgp64 used with a 32-bit ABI"));
10938 /* Infer the integer register size from the ABI and processor.
10939 Restrict ourselves to 32-bit registers if that's all the
10940 processor has, or if the ABI cannot handle 64-bit registers. */
10941 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10942 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10945 /* ??? GAS treats single-float processors as though they had 64-bit
10946 float registers (although it complains when double-precision
10947 instructions are used). As things stand, saying they have 32-bit
10948 registers would lead to spurious "register must be even" messages.
10949 So here we assume float registers are always the same size as
10950 integer ones, unless the user says otherwise. */
10951 if (file_mips_fp32
< 0)
10952 file_mips_fp32
= file_mips_gp32
;
10954 /* End of GCC-shared inference code. */
10956 /* This flag is set when we have a 64-bit capable CPU but use only
10957 32-bit wide registers. Note that EABI does not use it. */
10958 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10959 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10960 || mips_abi
== O32_ABI
))
10961 mips_32bitmode
= 1;
10963 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10964 as_bad (_("trap exception not supported at ISA 1"));
10966 /* If the selected architecture includes support for ASEs, enable
10967 generation of code for them. */
10968 if (mips_opts
.mips16
== -1)
10969 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10970 if (mips_opts
.ase_mips3d
== -1)
10971 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10972 if (mips_opts
.ase_mdmx
== -1)
10973 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10974 if (mips_opts
.ase_dsp
== -1)
10975 mips_opts
.ase_dsp
= (CPU_HAS_DSP (file_mips_arch
)) ? 1 : 0;
10976 if (mips_opts
.ase_mt
== -1)
10977 mips_opts
.ase_mt
= (CPU_HAS_MT (file_mips_arch
)) ? 1 : 0;
10979 file_mips_isa
= mips_opts
.isa
;
10980 file_ase_mips16
= mips_opts
.mips16
;
10981 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10982 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10983 file_ase_dsp
= mips_opts
.ase_dsp
;
10984 file_ase_mt
= mips_opts
.ase_mt
;
10985 mips_opts
.gp32
= file_mips_gp32
;
10986 mips_opts
.fp32
= file_mips_fp32
;
10988 if (mips_flag_mdebug
< 0)
10990 #ifdef OBJ_MAYBE_ECOFF
10991 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10992 mips_flag_mdebug
= 1;
10994 #endif /* OBJ_MAYBE_ECOFF */
10995 mips_flag_mdebug
= 0;
11000 mips_init_after_args (void)
11002 /* initialize opcodes */
11003 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11004 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11008 md_pcrel_from (fixS
*fixP
)
11010 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11011 switch (fixP
->fx_r_type
)
11013 case BFD_RELOC_16_PCREL_S2
:
11014 case BFD_RELOC_MIPS_JMP
:
11015 /* Return the address of the delay slot. */
11022 /* This is called before the symbol table is processed. In order to
11023 work with gcc when using mips-tfile, we must keep all local labels.
11024 However, in other cases, we want to discard them. If we were
11025 called with -g, but we didn't see any debugging information, it may
11026 mean that gcc is smuggling debugging information through to
11027 mips-tfile, in which case we must generate all local labels. */
11030 mips_frob_file_before_adjust (void)
11032 #ifndef NO_ECOFF_DEBUGGING
11033 if (ECOFF_DEBUGGING
11035 && ! ecoff_debugging_seen
)
11036 flag_keep_locals
= 1;
11040 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11041 the corresponding LO16 reloc. This is called before md_apply_fix and
11042 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11043 relocation operators.
11045 For our purposes, a %lo() expression matches a %got() or %hi()
11048 (a) it refers to the same symbol; and
11049 (b) the offset applied in the %lo() expression is no lower than
11050 the offset applied in the %got() or %hi().
11052 (b) allows us to cope with code like:
11055 lh $4,%lo(foo+2)($4)
11057 ...which is legal on RELA targets, and has a well-defined behaviour
11058 if the user knows that adding 2 to "foo" will not induce a carry to
11061 When several %lo()s match a particular %got() or %hi(), we use the
11062 following rules to distinguish them:
11064 (1) %lo()s with smaller offsets are a better match than %lo()s with
11067 (2) %lo()s with no matching %got() or %hi() are better than those
11068 that already have a matching %got() or %hi().
11070 (3) later %lo()s are better than earlier %lo()s.
11072 These rules are applied in order.
11074 (1) means, among other things, that %lo()s with identical offsets are
11075 chosen if they exist.
11077 (2) means that we won't associate several high-part relocations with
11078 the same low-part relocation unless there's no alternative. Having
11079 several high parts for the same low part is a GNU extension; this rule
11080 allows careful users to avoid it.
11082 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11083 with the last high-part relocation being at the front of the list.
11084 It therefore makes sense to choose the last matching low-part
11085 relocation, all other things being equal. It's also easier
11086 to code that way. */
11089 mips_frob_file (void)
11091 struct mips_hi_fixup
*l
;
11093 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11095 segment_info_type
*seginfo
;
11096 bfd_boolean matched_lo_p
;
11097 fixS
**hi_pos
, **lo_pos
, **pos
;
11099 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11101 /* If a GOT16 relocation turns out to be against a global symbol,
11102 there isn't supposed to be a matching LO. */
11103 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11104 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11107 /* Check quickly whether the next fixup happens to be a matching %lo. */
11108 if (fixup_has_matching_lo_p (l
->fixp
))
11111 seginfo
= seg_info (l
->seg
);
11113 /* Set HI_POS to the position of this relocation in the chain.
11114 Set LO_POS to the position of the chosen low-part relocation.
11115 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11116 relocation that matches an immediately-preceding high-part
11120 matched_lo_p
= FALSE
;
11121 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11123 if (*pos
== l
->fixp
)
11126 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11127 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11128 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11129 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11131 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11133 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11136 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11137 && fixup_has_matching_lo_p (*pos
));
11140 /* If we found a match, remove the high-part relocation from its
11141 current position and insert it before the low-part relocation.
11142 Make the offsets match so that fixup_has_matching_lo_p()
11145 We don't warn about unmatched high-part relocations since some
11146 versions of gcc have been known to emit dead "lui ...%hi(...)"
11148 if (lo_pos
!= NULL
)
11150 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11151 if (l
->fixp
->fx_next
!= *lo_pos
)
11153 *hi_pos
= l
->fixp
->fx_next
;
11154 l
->fixp
->fx_next
= *lo_pos
;
11161 /* We may have combined relocations without symbols in the N32/N64 ABI.
11162 We have to prevent gas from dropping them. */
11165 mips_force_relocation (fixS
*fixp
)
11167 if (generic_force_reloc (fixp
))
11171 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11172 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11173 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11174 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11180 /* This hook is called before a fix is simplified. We don't really
11181 decide whether to skip a fix here. Rather, we turn global symbols
11182 used as branch targets into local symbols, such that they undergo
11183 simplification. We can only do this if the symbol is defined and
11184 it is in the same section as the branch. If this doesn't hold, we
11185 emit a better error message than just saying the relocation is not
11186 valid for the selected object format.
11188 FIXP is the fix-up we're going to try to simplify, SEG is the
11189 segment in which the fix up occurs. The return value should be
11190 non-zero to indicate the fix-up is valid for further
11191 simplifications. */
11194 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
11196 /* There's a lot of discussion on whether it should be possible to
11197 use R_MIPS_PC16 to represent branch relocations. The outcome
11198 seems to be that it can, but gas/bfd are very broken in creating
11199 RELA relocations for this, so for now we only accept branches to
11200 symbols in the same section. Anything else is of dubious value,
11201 since there's no guarantee that at link time the symbol would be
11202 in range. Even for branches to local symbols this is arguably
11203 wrong, since it we assume the symbol is not going to be
11204 overridden, which should be possible per ELF library semantics,
11205 but then, there isn't a dynamic relocation that could be used to
11206 this effect, and the target would likely be out of range as well.
11208 Unfortunately, it seems that there is too much code out there
11209 that relies on branches to symbols that are global to be resolved
11210 as if they were local, like the IRIX tools do, so we do it as
11211 well, but with a warning so that people are reminded to fix their
11212 code. If we ever get back to using R_MIPS_PC16 for branch
11213 targets, this entire block should go away (and probably the
11214 whole function). */
11216 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11217 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11218 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11219 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11222 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11225 _("Cannot branch to undefined symbol."));
11226 /* Avoid any further errors about this fixup. */
11229 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11232 _("Cannot branch to symbol in another section."));
11235 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11237 symbolS
*sym
= fixP
->fx_addsy
;
11239 if (mips_pic
== SVR4_PIC
)
11240 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11241 _("Pretending global symbol used as branch target is local."));
11243 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11244 S_GET_SEGMENT (sym
),
11246 symbol_get_frag (sym
));
11247 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11248 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11249 assert (symbol_resolved_p (sym
));
11250 symbol_mark_resolved (fixP
->fx_addsy
);
11257 /* Apply a fixup to the object file. */
11260 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11264 reloc_howto_type
*howto
;
11266 /* We ignore generic BFD relocations we don't know about. */
11267 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11271 assert (fixP
->fx_size
== 4
11272 || fixP
->fx_r_type
== BFD_RELOC_16
11273 || fixP
->fx_r_type
== BFD_RELOC_64
11274 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11275 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11276 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11277 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11279 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11281 assert (! fixP
->fx_pcrel
);
11283 /* Don't treat parts of a composite relocation as done. There are two
11286 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11287 should nevertheless be emitted if the first part is.
11289 (2) In normal usage, composite relocations are never assembly-time
11290 constants. The easiest way of dealing with the pathological
11291 exceptions is to generate a relocation against STN_UNDEF and
11292 leave everything up to the linker. */
11293 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11296 switch (fixP
->fx_r_type
)
11298 case BFD_RELOC_MIPS_TLS_GD
:
11299 case BFD_RELOC_MIPS_TLS_LDM
:
11300 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11301 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11302 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11303 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11304 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11305 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11308 case BFD_RELOC_MIPS_JMP
:
11309 case BFD_RELOC_MIPS_SHIFT5
:
11310 case BFD_RELOC_MIPS_SHIFT6
:
11311 case BFD_RELOC_MIPS_GOT_DISP
:
11312 case BFD_RELOC_MIPS_GOT_PAGE
:
11313 case BFD_RELOC_MIPS_GOT_OFST
:
11314 case BFD_RELOC_MIPS_SUB
:
11315 case BFD_RELOC_MIPS_INSERT_A
:
11316 case BFD_RELOC_MIPS_INSERT_B
:
11317 case BFD_RELOC_MIPS_DELETE
:
11318 case BFD_RELOC_MIPS_HIGHEST
:
11319 case BFD_RELOC_MIPS_HIGHER
:
11320 case BFD_RELOC_MIPS_SCN_DISP
:
11321 case BFD_RELOC_MIPS_REL16
:
11322 case BFD_RELOC_MIPS_RELGOT
:
11323 case BFD_RELOC_MIPS_JALR
:
11324 case BFD_RELOC_HI16
:
11325 case BFD_RELOC_HI16_S
:
11326 case BFD_RELOC_GPREL16
:
11327 case BFD_RELOC_MIPS_LITERAL
:
11328 case BFD_RELOC_MIPS_CALL16
:
11329 case BFD_RELOC_MIPS_GOT16
:
11330 case BFD_RELOC_GPREL32
:
11331 case BFD_RELOC_MIPS_GOT_HI16
:
11332 case BFD_RELOC_MIPS_GOT_LO16
:
11333 case BFD_RELOC_MIPS_CALL_HI16
:
11334 case BFD_RELOC_MIPS_CALL_LO16
:
11335 case BFD_RELOC_MIPS16_GPREL
:
11336 case BFD_RELOC_MIPS16_HI16
:
11337 case BFD_RELOC_MIPS16_HI16_S
:
11338 assert (! fixP
->fx_pcrel
);
11339 /* Nothing needed to do. The value comes from the reloc entry */
11342 case BFD_RELOC_MIPS16_JMP
:
11343 /* We currently always generate a reloc against a symbol, which
11344 means that we don't want an addend even if the symbol is
11350 /* This is handled like BFD_RELOC_32, but we output a sign
11351 extended value if we are only 32 bits. */
11354 if (8 <= sizeof (valueT
))
11355 md_number_to_chars ((char *) buf
, *valP
, 8);
11360 if ((*valP
& 0x80000000) != 0)
11364 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11366 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11372 case BFD_RELOC_RVA
:
11374 /* If we are deleting this reloc entry, we must fill in the
11375 value now. This can happen if we have a .word which is not
11376 resolved when it appears but is later defined. */
11378 md_number_to_chars ((char *) buf
, *valP
, 4);
11382 /* If we are deleting this reloc entry, we must fill in the
11385 md_number_to_chars ((char *) buf
, *valP
, 2);
11388 case BFD_RELOC_LO16
:
11389 case BFD_RELOC_MIPS16_LO16
:
11390 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11391 may be safe to remove, but if so it's not obvious. */
11392 /* When handling an embedded PIC switch statement, we can wind
11393 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11396 if (*valP
+ 0x8000 > 0xffff)
11397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11398 _("relocation overflow"));
11399 if (target_big_endian
)
11401 md_number_to_chars ((char *) buf
, *valP
, 2);
11405 case BFD_RELOC_16_PCREL_S2
:
11406 if ((*valP
& 0x3) != 0)
11407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11408 _("Branch to odd address (%lx)"), (long) *valP
);
11411 * We need to save the bits in the instruction since fixup_segment()
11412 * might be deleting the relocation entry (i.e., a branch within
11413 * the current segment).
11415 if (! fixP
->fx_done
)
11418 /* update old instruction data */
11419 if (target_big_endian
)
11420 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11422 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11424 if (*valP
+ 0x20000 <= 0x3ffff)
11426 insn
|= (*valP
>> 2) & 0xffff;
11427 md_number_to_chars ((char *) buf
, insn
, 4);
11429 else if (mips_pic
== NO_PIC
11431 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11432 && (fixP
->fx_frag
->fr_address
11433 < text_section
->vma
+ bfd_get_section_size (text_section
))
11434 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11435 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11436 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11438 /* The branch offset is too large. If this is an
11439 unconditional branch, and we are not generating PIC code,
11440 we can convert it to an absolute jump instruction. */
11441 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11442 insn
= 0x0c000000; /* jal */
11444 insn
= 0x08000000; /* j */
11445 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11447 fixP
->fx_addsy
= section_symbol (text_section
);
11448 *valP
+= md_pcrel_from (fixP
);
11449 md_number_to_chars ((char *) buf
, insn
, 4);
11453 /* If we got here, we have branch-relaxation disabled,
11454 and there's nothing we can do to fix this instruction
11455 without turning it into a longer sequence. */
11456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11457 _("Branch out of range"));
11461 case BFD_RELOC_VTABLE_INHERIT
:
11464 && !S_IS_DEFINED (fixP
->fx_addsy
)
11465 && !S_IS_WEAK (fixP
->fx_addsy
))
11466 S_SET_WEAK (fixP
->fx_addsy
);
11469 case BFD_RELOC_VTABLE_ENTRY
:
11477 /* Remember value for tc_gen_reloc. */
11478 fixP
->fx_addnumber
= *valP
;
11488 name
= input_line_pointer
;
11489 c
= get_symbol_end ();
11490 p
= (symbolS
*) symbol_find_or_make (name
);
11491 *input_line_pointer
= c
;
11495 /* Align the current frag to a given power of two. The MIPS assembler
11496 also automatically adjusts any preceding label. */
11499 mips_align (int to
, int fill
, symbolS
*label
)
11501 mips_emit_delays ();
11502 frag_align (to
, fill
, 0);
11503 record_alignment (now_seg
, to
);
11506 assert (S_GET_SEGMENT (label
) == now_seg
);
11507 symbol_set_frag (label
, frag_now
);
11508 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11512 /* Align to a given power of two. .align 0 turns off the automatic
11513 alignment used by the data creating pseudo-ops. */
11516 s_align (int x ATTRIBUTE_UNUSED
)
11519 register long temp_fill
;
11520 long max_alignment
= 15;
11524 o Note that the assembler pulls down any immediately preceding label
11525 to the aligned address.
11526 o It's not documented but auto alignment is reinstated by
11527 a .align pseudo instruction.
11528 o Note also that after auto alignment is turned off the mips assembler
11529 issues an error on attempt to assemble an improperly aligned data item.
11534 temp
= get_absolute_expression ();
11535 if (temp
> max_alignment
)
11536 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11539 as_warn (_("Alignment negative: 0 assumed."));
11542 if (*input_line_pointer
== ',')
11544 ++input_line_pointer
;
11545 temp_fill
= get_absolute_expression ();
11552 mips_align (temp
, (int) temp_fill
,
11553 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11560 demand_empty_rest_of_line ();
11564 s_change_sec (int sec
)
11569 /* The ELF backend needs to know that we are changing sections, so
11570 that .previous works correctly. We could do something like check
11571 for an obj_section_change_hook macro, but that might be confusing
11572 as it would not be appropriate to use it in the section changing
11573 functions in read.c, since obj-elf.c intercepts those. FIXME:
11574 This should be cleaner, somehow. */
11575 obj_elf_section_change_hook ();
11578 mips_emit_delays ();
11588 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11589 demand_empty_rest_of_line ();
11593 seg
= subseg_new (RDATA_SECTION_NAME
,
11594 (subsegT
) get_absolute_expression ());
11595 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11597 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11598 | SEC_READONLY
| SEC_RELOC
11600 if (strcmp (TARGET_OS
, "elf") != 0)
11601 record_alignment (seg
, 4);
11603 demand_empty_rest_of_line ();
11607 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11608 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11610 bfd_set_section_flags (stdoutput
, seg
,
11611 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11612 if (strcmp (TARGET_OS
, "elf") != 0)
11613 record_alignment (seg
, 4);
11615 demand_empty_rest_of_line ();
11623 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11626 char *section_name
;
11631 int section_entry_size
;
11632 int section_alignment
;
11634 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11637 section_name
= input_line_pointer
;
11638 c
= get_symbol_end ();
11640 next_c
= *(input_line_pointer
+ 1);
11642 /* Do we have .section Name<,"flags">? */
11643 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11645 /* just after name is now '\0'. */
11646 *input_line_pointer
= c
;
11647 input_line_pointer
= section_name
;
11648 obj_elf_section (ignore
);
11651 input_line_pointer
++;
11653 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11655 section_type
= get_absolute_expression ();
11658 if (*input_line_pointer
++ == ',')
11659 section_flag
= get_absolute_expression ();
11662 if (*input_line_pointer
++ == ',')
11663 section_entry_size
= get_absolute_expression ();
11665 section_entry_size
= 0;
11666 if (*input_line_pointer
++ == ',')
11667 section_alignment
= get_absolute_expression ();
11669 section_alignment
= 0;
11671 section_name
= xstrdup (section_name
);
11673 /* When using the generic form of .section (as implemented by obj-elf.c),
11674 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11675 traditionally had to fall back on the more common @progbits instead.
11677 There's nothing really harmful in this, since bfd will correct
11678 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11679 means that, for backwards compatibiltiy, the special_section entries
11680 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11682 Even so, we shouldn't force users of the MIPS .section syntax to
11683 incorrectly label the sections as SHT_PROGBITS. The best compromise
11684 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11685 generic type-checking code. */
11686 if (section_type
== SHT_MIPS_DWARF
)
11687 section_type
= SHT_PROGBITS
;
11689 obj_elf_change_section (section_name
, section_type
, section_flag
,
11690 section_entry_size
, 0, 0, 0);
11692 if (now_seg
->name
!= section_name
)
11693 free (section_name
);
11694 #endif /* OBJ_ELF */
11698 mips_enable_auto_align (void)
11704 s_cons (int log_size
)
11708 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11709 mips_emit_delays ();
11710 if (log_size
> 0 && auto_align
)
11711 mips_align (log_size
, 0, label
);
11712 mips_clear_insn_labels ();
11713 cons (1 << log_size
);
11717 s_float_cons (int type
)
11721 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11723 mips_emit_delays ();
11728 mips_align (3, 0, label
);
11730 mips_align (2, 0, label
);
11733 mips_clear_insn_labels ();
11738 /* Handle .globl. We need to override it because on Irix 5 you are
11741 where foo is an undefined symbol, to mean that foo should be
11742 considered to be the address of a function. */
11745 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11754 name
= input_line_pointer
;
11755 c
= get_symbol_end ();
11756 symbolP
= symbol_find_or_make (name
);
11757 S_SET_EXTERNAL (symbolP
);
11759 *input_line_pointer
= c
;
11760 SKIP_WHITESPACE ();
11762 /* On Irix 5, every global symbol that is not explicitly labelled as
11763 being a function is apparently labelled as being an object. */
11766 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
11767 && (*input_line_pointer
!= ','))
11772 secname
= input_line_pointer
;
11773 c
= get_symbol_end ();
11774 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11776 as_bad (_("%s: no such section"), secname
);
11777 *input_line_pointer
= c
;
11779 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11780 flag
= BSF_FUNCTION
;
11783 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11785 c
= *input_line_pointer
;
11788 input_line_pointer
++;
11789 SKIP_WHITESPACE ();
11790 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
11796 demand_empty_rest_of_line ();
11800 s_option (int x ATTRIBUTE_UNUSED
)
11805 opt
= input_line_pointer
;
11806 c
= get_symbol_end ();
11810 /* FIXME: What does this mean? */
11812 else if (strncmp (opt
, "pic", 3) == 0)
11816 i
= atoi (opt
+ 3);
11821 mips_pic
= SVR4_PIC
;
11822 mips_abicalls
= TRUE
;
11825 as_bad (_(".option pic%d not supported"), i
);
11827 if (mips_pic
== SVR4_PIC
)
11829 if (g_switch_seen
&& g_switch_value
!= 0)
11830 as_warn (_("-G may not be used with SVR4 PIC code"));
11831 g_switch_value
= 0;
11832 bfd_set_gp_size (stdoutput
, 0);
11836 as_warn (_("Unrecognized option \"%s\""), opt
);
11838 *input_line_pointer
= c
;
11839 demand_empty_rest_of_line ();
11842 /* This structure is used to hold a stack of .set values. */
11844 struct mips_option_stack
11846 struct mips_option_stack
*next
;
11847 struct mips_set_options options
;
11850 static struct mips_option_stack
*mips_opts_stack
;
11852 /* Handle the .set pseudo-op. */
11855 s_mipsset (int x ATTRIBUTE_UNUSED
)
11857 char *name
= input_line_pointer
, ch
;
11859 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11860 ++input_line_pointer
;
11861 ch
= *input_line_pointer
;
11862 *input_line_pointer
= '\0';
11864 if (strcmp (name
, "reorder") == 0)
11866 if (mips_opts
.noreorder
)
11869 else if (strcmp (name
, "noreorder") == 0)
11871 if (!mips_opts
.noreorder
)
11872 start_noreorder ();
11874 else if (strcmp (name
, "at") == 0)
11876 mips_opts
.noat
= 0;
11878 else if (strcmp (name
, "noat") == 0)
11880 mips_opts
.noat
= 1;
11882 else if (strcmp (name
, "macro") == 0)
11884 mips_opts
.warn_about_macros
= 0;
11886 else if (strcmp (name
, "nomacro") == 0)
11888 if (mips_opts
.noreorder
== 0)
11889 as_bad (_("`noreorder' must be set before `nomacro'"));
11890 mips_opts
.warn_about_macros
= 1;
11892 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11894 mips_opts
.nomove
= 0;
11896 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11898 mips_opts
.nomove
= 1;
11900 else if (strcmp (name
, "bopt") == 0)
11902 mips_opts
.nobopt
= 0;
11904 else if (strcmp (name
, "nobopt") == 0)
11906 mips_opts
.nobopt
= 1;
11908 else if (strcmp (name
, "mips16") == 0
11909 || strcmp (name
, "MIPS-16") == 0)
11910 mips_opts
.mips16
= 1;
11911 else if (strcmp (name
, "nomips16") == 0
11912 || strcmp (name
, "noMIPS-16") == 0)
11913 mips_opts
.mips16
= 0;
11914 else if (strcmp (name
, "mips3d") == 0)
11915 mips_opts
.ase_mips3d
= 1;
11916 else if (strcmp (name
, "nomips3d") == 0)
11917 mips_opts
.ase_mips3d
= 0;
11918 else if (strcmp (name
, "mdmx") == 0)
11919 mips_opts
.ase_mdmx
= 1;
11920 else if (strcmp (name
, "nomdmx") == 0)
11921 mips_opts
.ase_mdmx
= 0;
11922 else if (strcmp (name
, "dsp") == 0)
11923 mips_opts
.ase_dsp
= 1;
11924 else if (strcmp (name
, "nodsp") == 0)
11925 mips_opts
.ase_dsp
= 0;
11926 else if (strcmp (name
, "mt") == 0)
11927 mips_opts
.ase_mt
= 1;
11928 else if (strcmp (name
, "nomt") == 0)
11929 mips_opts
.ase_mt
= 0;
11930 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11934 /* Permit the user to change the ISA and architecture on the fly.
11935 Needless to say, misuse can cause serious problems. */
11936 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11939 mips_opts
.isa
= file_mips_isa
;
11940 mips_opts
.arch
= file_mips_arch
;
11942 else if (strncmp (name
, "arch=", 5) == 0)
11944 const struct mips_cpu_info
*p
;
11946 p
= mips_parse_cpu("internal use", name
+ 5);
11948 as_bad (_("unknown architecture %s"), name
+ 5);
11951 mips_opts
.arch
= p
->cpu
;
11952 mips_opts
.isa
= p
->isa
;
11955 else if (strncmp (name
, "mips", 4) == 0)
11957 const struct mips_cpu_info
*p
;
11959 p
= mips_parse_cpu("internal use", name
);
11961 as_bad (_("unknown ISA level %s"), name
+ 4);
11964 mips_opts
.arch
= p
->cpu
;
11965 mips_opts
.isa
= p
->isa
;
11969 as_bad (_("unknown ISA or architecture %s"), name
);
11971 switch (mips_opts
.isa
)
11979 mips_opts
.gp32
= 1;
11980 mips_opts
.fp32
= 1;
11987 mips_opts
.gp32
= 0;
11988 mips_opts
.fp32
= 0;
11991 as_bad (_("unknown ISA level %s"), name
+ 4);
11996 mips_opts
.gp32
= file_mips_gp32
;
11997 mips_opts
.fp32
= file_mips_fp32
;
12000 else if (strcmp (name
, "autoextend") == 0)
12001 mips_opts
.noautoextend
= 0;
12002 else if (strcmp (name
, "noautoextend") == 0)
12003 mips_opts
.noautoextend
= 1;
12004 else if (strcmp (name
, "push") == 0)
12006 struct mips_option_stack
*s
;
12008 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12009 s
->next
= mips_opts_stack
;
12010 s
->options
= mips_opts
;
12011 mips_opts_stack
= s
;
12013 else if (strcmp (name
, "pop") == 0)
12015 struct mips_option_stack
*s
;
12017 s
= mips_opts_stack
;
12019 as_bad (_(".set pop with no .set push"));
12022 /* If we're changing the reorder mode we need to handle
12023 delay slots correctly. */
12024 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12025 start_noreorder ();
12026 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12029 mips_opts
= s
->options
;
12030 mips_opts_stack
= s
->next
;
12034 else if (strcmp (name
, "sym32") == 0)
12035 mips_opts
.sym32
= TRUE
;
12036 else if (strcmp (name
, "nosym32") == 0)
12037 mips_opts
.sym32
= FALSE
;
12040 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12042 *input_line_pointer
= ch
;
12043 demand_empty_rest_of_line ();
12046 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12047 .option pic2. It means to generate SVR4 PIC calls. */
12050 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12052 mips_pic
= SVR4_PIC
;
12053 mips_abicalls
= TRUE
;
12055 if (g_switch_seen
&& g_switch_value
!= 0)
12056 as_warn (_("-G may not be used with SVR4 PIC code"));
12057 g_switch_value
= 0;
12059 bfd_set_gp_size (stdoutput
, 0);
12060 demand_empty_rest_of_line ();
12063 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12064 PIC code. It sets the $gp register for the function based on the
12065 function address, which is in the register named in the argument.
12066 This uses a relocation against _gp_disp, which is handled specially
12067 by the linker. The result is:
12068 lui $gp,%hi(_gp_disp)
12069 addiu $gp,$gp,%lo(_gp_disp)
12070 addu $gp,$gp,.cpload argument
12071 The .cpload argument is normally $25 == $t9.
12073 The -mno-shared option changes this to:
12074 lui $gp,%hi(__gnu_local_gp)
12075 addiu $gp,$gp,%lo(__gnu_local_gp)
12076 and the argument is ignored. This saves an instruction, but the
12077 resulting code is not position independent; it uses an absolute
12078 address for __gnu_local_gp. Thus code assembled with -mno-shared
12079 can go into an ordinary executable, but not into a shared library. */
12082 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12088 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12089 .cpload is ignored. */
12090 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12096 /* .cpload should be in a .set noreorder section. */
12097 if (mips_opts
.noreorder
== 0)
12098 as_warn (_(".cpload not in noreorder section"));
12100 reg
= tc_get_register (0);
12102 /* If we need to produce a 64-bit address, we are better off using
12103 the default instruction sequence. */
12104 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12106 ex
.X_op
= O_symbol
;
12107 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12109 ex
.X_op_symbol
= NULL
;
12110 ex
.X_add_number
= 0;
12112 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12113 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12116 macro_build_lui (&ex
, mips_gp_register
);
12117 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12118 mips_gp_register
, BFD_RELOC_LO16
);
12120 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12121 mips_gp_register
, reg
);
12124 demand_empty_rest_of_line ();
12127 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12128 .cpsetup $reg1, offset|$reg2, label
12130 If offset is given, this results in:
12131 sd $gp, offset($sp)
12132 lui $gp, %hi(%neg(%gp_rel(label)))
12133 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12134 daddu $gp, $gp, $reg1
12136 If $reg2 is given, this results in:
12137 daddu $reg2, $gp, $0
12138 lui $gp, %hi(%neg(%gp_rel(label)))
12139 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12140 daddu $gp, $gp, $reg1
12141 $reg1 is normally $25 == $t9.
12143 The -mno-shared option replaces the last three instructions with
12145 addiu $gp,$gp,%lo(_gp)
12149 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12151 expressionS ex_off
;
12152 expressionS ex_sym
;
12155 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12156 We also need NewABI support. */
12157 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12163 reg1
= tc_get_register (0);
12164 SKIP_WHITESPACE ();
12165 if (*input_line_pointer
!= ',')
12167 as_bad (_("missing argument separator ',' for .cpsetup"));
12171 ++input_line_pointer
;
12172 SKIP_WHITESPACE ();
12173 if (*input_line_pointer
== '$')
12175 mips_cpreturn_register
= tc_get_register (0);
12176 mips_cpreturn_offset
= -1;
12180 mips_cpreturn_offset
= get_absolute_expression ();
12181 mips_cpreturn_register
= -1;
12183 SKIP_WHITESPACE ();
12184 if (*input_line_pointer
!= ',')
12186 as_bad (_("missing argument separator ',' for .cpsetup"));
12190 ++input_line_pointer
;
12191 SKIP_WHITESPACE ();
12192 expression (&ex_sym
);
12195 if (mips_cpreturn_register
== -1)
12197 ex_off
.X_op
= O_constant
;
12198 ex_off
.X_add_symbol
= NULL
;
12199 ex_off
.X_op_symbol
= NULL
;
12200 ex_off
.X_add_number
= mips_cpreturn_offset
;
12202 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12203 BFD_RELOC_LO16
, SP
);
12206 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12207 mips_gp_register
, 0);
12209 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12211 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12212 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12215 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12216 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12217 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12220 mips_gp_register
, reg1
);
12226 ex
.X_op
= O_symbol
;
12227 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12228 ex
.X_op_symbol
= NULL
;
12229 ex
.X_add_number
= 0;
12231 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12232 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12234 macro_build_lui (&ex
, mips_gp_register
);
12235 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12236 mips_gp_register
, BFD_RELOC_LO16
);
12241 demand_empty_rest_of_line ();
12245 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12247 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12248 .cplocal is ignored. */
12249 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12255 mips_gp_register
= tc_get_register (0);
12256 demand_empty_rest_of_line ();
12259 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12260 offset from $sp. The offset is remembered, and after making a PIC
12261 call $gp is restored from that location. */
12264 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12268 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12269 .cprestore is ignored. */
12270 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12276 mips_cprestore_offset
= get_absolute_expression ();
12277 mips_cprestore_valid
= 1;
12279 ex
.X_op
= O_constant
;
12280 ex
.X_add_symbol
= NULL
;
12281 ex
.X_op_symbol
= NULL
;
12282 ex
.X_add_number
= mips_cprestore_offset
;
12285 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12286 SP
, HAVE_64BIT_ADDRESSES
);
12289 demand_empty_rest_of_line ();
12292 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12293 was given in the preceding .cpsetup, it results in:
12294 ld $gp, offset($sp)
12296 If a register $reg2 was given there, it results in:
12297 daddu $gp, $reg2, $0
12300 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12304 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12305 We also need NewABI support. */
12306 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12313 if (mips_cpreturn_register
== -1)
12315 ex
.X_op
= O_constant
;
12316 ex
.X_add_symbol
= NULL
;
12317 ex
.X_op_symbol
= NULL
;
12318 ex
.X_add_number
= mips_cpreturn_offset
;
12320 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12323 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12324 mips_cpreturn_register
, 0);
12327 demand_empty_rest_of_line ();
12330 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12331 code. It sets the offset to use in gp_rel relocations. */
12334 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12336 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12337 We also need NewABI support. */
12338 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12344 mips_gprel_offset
= get_absolute_expression ();
12346 demand_empty_rest_of_line ();
12349 /* Handle the .gpword pseudo-op. This is used when generating PIC
12350 code. It generates a 32 bit GP relative reloc. */
12353 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12359 /* When not generating PIC code, this is treated as .word. */
12360 if (mips_pic
!= SVR4_PIC
)
12366 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12367 mips_emit_delays ();
12369 mips_align (2, 0, label
);
12370 mips_clear_insn_labels ();
12374 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12376 as_bad (_("Unsupported use of .gpword"));
12377 ignore_rest_of_line ();
12381 md_number_to_chars (p
, 0, 4);
12382 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12383 BFD_RELOC_GPREL32
);
12385 demand_empty_rest_of_line ();
12389 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12395 /* When not generating PIC code, this is treated as .dword. */
12396 if (mips_pic
!= SVR4_PIC
)
12402 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12403 mips_emit_delays ();
12405 mips_align (3, 0, label
);
12406 mips_clear_insn_labels ();
12410 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12412 as_bad (_("Unsupported use of .gpdword"));
12413 ignore_rest_of_line ();
12417 md_number_to_chars (p
, 0, 8);
12418 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12419 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12421 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12422 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12423 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12425 demand_empty_rest_of_line ();
12428 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12429 tables in SVR4 PIC code. */
12432 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12436 /* This is ignored when not generating SVR4 PIC code. */
12437 if (mips_pic
!= SVR4_PIC
)
12443 /* Add $gp to the register named as an argument. */
12445 reg
= tc_get_register (0);
12446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12449 demand_empty_rest_of_line ();
12452 /* Handle the .insn pseudo-op. This marks instruction labels in
12453 mips16 mode. This permits the linker to handle them specially,
12454 such as generating jalx instructions when needed. We also make
12455 them odd for the duration of the assembly, in order to generate the
12456 right sort of code. We will make them even in the adjust_symtab
12457 routine, while leaving them marked. This is convenient for the
12458 debugger and the disassembler. The linker knows to make them odd
12462 s_insn (int ignore ATTRIBUTE_UNUSED
)
12464 mips16_mark_labels ();
12466 demand_empty_rest_of_line ();
12469 /* Handle a .stabn directive. We need these in order to mark a label
12470 as being a mips16 text label correctly. Sometimes the compiler
12471 will emit a label, followed by a .stabn, and then switch sections.
12472 If the label and .stabn are in mips16 mode, then the label is
12473 really a mips16 text label. */
12476 s_mips_stab (int type
)
12479 mips16_mark_labels ();
12484 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12488 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12495 name
= input_line_pointer
;
12496 c
= get_symbol_end ();
12497 symbolP
= symbol_find_or_make (name
);
12498 S_SET_WEAK (symbolP
);
12499 *input_line_pointer
= c
;
12501 SKIP_WHITESPACE ();
12503 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12505 if (S_IS_DEFINED (symbolP
))
12507 as_bad ("ignoring attempt to redefine symbol %s",
12508 S_GET_NAME (symbolP
));
12509 ignore_rest_of_line ();
12513 if (*input_line_pointer
== ',')
12515 ++input_line_pointer
;
12516 SKIP_WHITESPACE ();
12520 if (exp
.X_op
!= O_symbol
)
12522 as_bad ("bad .weakext directive");
12523 ignore_rest_of_line ();
12526 symbol_set_value_expression (symbolP
, &exp
);
12529 demand_empty_rest_of_line ();
12532 /* Parse a register string into a number. Called from the ECOFF code
12533 to parse .frame. The argument is non-zero if this is the frame
12534 register, so that we can record it in mips_frame_reg. */
12537 tc_get_register (int frame
)
12541 SKIP_WHITESPACE ();
12542 if (*input_line_pointer
++ != '$')
12544 as_warn (_("expected `$'"));
12547 else if (ISDIGIT (*input_line_pointer
))
12549 reg
= get_absolute_expression ();
12550 if (reg
< 0 || reg
>= 32)
12552 as_warn (_("Bad register number"));
12558 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12561 input_line_pointer
+= 2;
12563 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12566 input_line_pointer
+= 2;
12568 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12571 input_line_pointer
+= 2;
12573 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12576 input_line_pointer
+= 2;
12578 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12581 input_line_pointer
+= 2;
12583 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12586 input_line_pointer
+= 3;
12588 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12591 input_line_pointer
+= 3;
12593 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12596 input_line_pointer
+= 4;
12600 as_warn (_("Unrecognized register name"));
12602 while (ISALNUM(*input_line_pointer
))
12603 input_line_pointer
++;
12608 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12609 mips_frame_reg_valid
= 1;
12610 mips_cprestore_valid
= 0;
12616 md_section_align (asection
*seg
, valueT addr
)
12618 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12621 /* We don't need to align ELF sections to the full alignment.
12622 However, Irix 5 may prefer that we align them at least to a 16
12623 byte boundary. We don't bother to align the sections if we are
12624 targeted for an embedded system. */
12625 if (strcmp (TARGET_OS
, "elf") == 0)
12631 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12634 /* Utility routine, called from above as well. If called while the
12635 input file is still being read, it's only an approximation. (For
12636 example, a symbol may later become defined which appeared to be
12637 undefined earlier.) */
12640 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12645 if (g_switch_value
> 0)
12647 const char *symname
;
12650 /* Find out whether this symbol can be referenced off the $gp
12651 register. It can be if it is smaller than the -G size or if
12652 it is in the .sdata or .sbss section. Certain symbols can
12653 not be referenced off the $gp, although it appears as though
12655 symname
= S_GET_NAME (sym
);
12656 if (symname
!= (const char *) NULL
12657 && (strcmp (symname
, "eprol") == 0
12658 || strcmp (symname
, "etext") == 0
12659 || strcmp (symname
, "_gp") == 0
12660 || strcmp (symname
, "edata") == 0
12661 || strcmp (symname
, "_fbss") == 0
12662 || strcmp (symname
, "_fdata") == 0
12663 || strcmp (symname
, "_ftext") == 0
12664 || strcmp (symname
, "end") == 0
12665 || strcmp (symname
, "_gp_disp") == 0))
12667 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12669 #ifndef NO_ECOFF_DEBUGGING
12670 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12671 && (symbol_get_obj (sym
)->ecoff_extern_size
12672 <= g_switch_value
))
12674 /* We must defer this decision until after the whole
12675 file has been read, since there might be a .extern
12676 after the first use of this symbol. */
12677 || (before_relaxing
12678 #ifndef NO_ECOFF_DEBUGGING
12679 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12681 && S_GET_VALUE (sym
) == 0)
12682 || (S_GET_VALUE (sym
) != 0
12683 && S_GET_VALUE (sym
) <= g_switch_value
)))
12687 const char *segname
;
12689 segname
= segment_name (S_GET_SEGMENT (sym
));
12690 assert (strcmp (segname
, ".lit8") != 0
12691 && strcmp (segname
, ".lit4") != 0);
12692 change
= (strcmp (segname
, ".sdata") != 0
12693 && strcmp (segname
, ".sbss") != 0
12694 && strncmp (segname
, ".sdata.", 7) != 0
12695 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12700 /* We are not optimizing for the $gp register. */
12705 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12708 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12711 bfd_boolean linkonce
;
12713 /* Handle the case of a symbol equated to another symbol. */
12714 while (symbol_equated_reloc_p (sym
))
12718 /* It's possible to get a loop here in a badly written
12720 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12726 symsec
= S_GET_SEGMENT (sym
);
12728 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12730 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12732 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12736 /* The GNU toolchain uses an extension for ELF: a section
12737 beginning with the magic string .gnu.linkonce is a linkonce
12739 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12740 sizeof ".gnu.linkonce" - 1) == 0)
12744 /* This must duplicate the test in adjust_reloc_syms. */
12745 return (symsec
!= &bfd_und_section
12746 && symsec
!= &bfd_abs_section
12747 && ! bfd_is_com_section (symsec
)
12750 /* A global or weak symbol is treated as external. */
12751 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12752 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12758 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12759 extended opcode. SEC is the section the frag is in. */
12762 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12765 register const struct mips16_immed_operand
*op
;
12767 int mintiny
, maxtiny
;
12771 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12773 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12776 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12777 op
= mips16_immed_operands
;
12778 while (op
->type
!= type
)
12781 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12786 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12789 maxtiny
= 1 << op
->nbits
;
12794 maxtiny
= (1 << op
->nbits
) - 1;
12799 mintiny
= - (1 << (op
->nbits
- 1));
12800 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12803 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12804 val
= S_GET_VALUE (fragp
->fr_symbol
);
12805 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12811 /* We won't have the section when we are called from
12812 mips_relax_frag. However, we will always have been called
12813 from md_estimate_size_before_relax first. If this is a
12814 branch to a different section, we mark it as such. If SEC is
12815 NULL, and the frag is not marked, then it must be a branch to
12816 the same section. */
12819 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12824 /* Must have been called from md_estimate_size_before_relax. */
12827 fragp
->fr_subtype
=
12828 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12830 /* FIXME: We should support this, and let the linker
12831 catch branches and loads that are out of range. */
12832 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12833 _("unsupported PC relative reference to different section"));
12837 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12838 /* Assume non-extended on the first relaxation pass.
12839 The address we have calculated will be bogus if this is
12840 a forward branch to another frag, as the forward frag
12841 will have fr_address == 0. */
12845 /* In this case, we know for sure that the symbol fragment is in
12846 the same section. If the relax_marker of the symbol fragment
12847 differs from the relax_marker of this fragment, we have not
12848 yet adjusted the symbol fragment fr_address. We want to add
12849 in STRETCH in order to get a better estimate of the address.
12850 This particularly matters because of the shift bits. */
12852 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12856 /* Adjust stretch for any alignment frag. Note that if have
12857 been expanding the earlier code, the symbol may be
12858 defined in what appears to be an earlier frag. FIXME:
12859 This doesn't handle the fr_subtype field, which specifies
12860 a maximum number of bytes to skip when doing an
12862 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12864 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12867 stretch
= - ((- stretch
)
12868 & ~ ((1 << (int) f
->fr_offset
) - 1));
12870 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12879 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12881 /* The base address rules are complicated. The base address of
12882 a branch is the following instruction. The base address of a
12883 PC relative load or add is the instruction itself, but if it
12884 is in a delay slot (in which case it can not be extended) use
12885 the address of the instruction whose delay slot it is in. */
12886 if (type
== 'p' || type
== 'q')
12890 /* If we are currently assuming that this frag should be
12891 extended, then, the current address is two bytes
12893 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12896 /* Ignore the low bit in the target, since it will be set
12897 for a text label. */
12898 if ((val
& 1) != 0)
12901 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12903 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12906 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12908 /* Branch offsets have an implicit 0 in the lowest bit. */
12909 if (type
== 'p' || type
== 'q')
12912 /* If any of the shifted bits are set, we must use an extended
12913 opcode. If the address depends on the size of this
12914 instruction, this can lead to a loop, so we arrange to always
12915 use an extended opcode. We only check this when we are in
12916 the main relaxation loop, when SEC is NULL. */
12917 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12919 fragp
->fr_subtype
=
12920 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12924 /* If we are about to mark a frag as extended because the value
12925 is precisely maxtiny + 1, then there is a chance of an
12926 infinite loop as in the following code:
12931 In this case when the la is extended, foo is 0x3fc bytes
12932 away, so the la can be shrunk, but then foo is 0x400 away, so
12933 the la must be extended. To avoid this loop, we mark the
12934 frag as extended if it was small, and is about to become
12935 extended with a value of maxtiny + 1. */
12936 if (val
== ((maxtiny
+ 1) << op
->shift
)
12937 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12940 fragp
->fr_subtype
=
12941 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12945 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12946 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12948 if ((val
& ((1 << op
->shift
) - 1)) != 0
12949 || val
< (mintiny
<< op
->shift
)
12950 || val
> (maxtiny
<< op
->shift
))
12956 /* Compute the length of a branch sequence, and adjust the
12957 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12958 worst-case length is computed, with UPDATE being used to indicate
12959 whether an unconditional (-1), branch-likely (+1) or regular (0)
12960 branch is to be computed. */
12962 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12964 bfd_boolean toofar
;
12968 && S_IS_DEFINED (fragp
->fr_symbol
)
12969 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12974 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12976 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12980 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12983 /* If the symbol is not defined or it's in a different segment,
12984 assume the user knows what's going on and emit a short
12990 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12992 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12993 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12994 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13000 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13003 if (mips_pic
!= NO_PIC
)
13005 /* Additional space for PIC loading of target address. */
13007 if (mips_opts
.isa
== ISA_MIPS1
)
13008 /* Additional space for $at-stabilizing nop. */
13012 /* If branch is conditional. */
13013 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13020 /* Estimate the size of a frag before relaxing. Unless this is the
13021 mips16, we are not really relaxing here, and the final size is
13022 encoded in the subtype information. For the mips16, we have to
13023 decide whether we are using an extended opcode or not. */
13026 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13030 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13033 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13035 return fragp
->fr_var
;
13038 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13039 /* We don't want to modify the EXTENDED bit here; it might get us
13040 into infinite loops. We change it only in mips_relax_frag(). */
13041 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13043 if (mips_pic
== NO_PIC
)
13044 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13045 else if (mips_pic
== SVR4_PIC
)
13046 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13052 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13053 return -RELAX_FIRST (fragp
->fr_subtype
);
13056 return -RELAX_SECOND (fragp
->fr_subtype
);
13059 /* This is called to see whether a reloc against a defined symbol
13060 should be converted into a reloc against a section. */
13063 mips_fix_adjustable (fixS
*fixp
)
13065 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13066 about the format of the offset in the .o file. */
13067 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13070 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13071 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13074 if (fixp
->fx_addsy
== NULL
)
13077 /* If symbol SYM is in a mergeable section, relocations of the form
13078 SYM + 0 can usually be made section-relative. The mergeable data
13079 is then identified by the section offset rather than by the symbol.
13081 However, if we're generating REL LO16 relocations, the offset is split
13082 between the LO16 and parterning high part relocation. The linker will
13083 need to recalculate the complete offset in order to correctly identify
13086 The linker has traditionally not looked for the parterning high part
13087 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13088 placed anywhere. Rather than break backwards compatibility by changing
13089 this, it seems better not to force the issue, and instead keep the
13090 original symbol. This will work with either linker behavior. */
13091 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13092 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13093 || reloc_needs_lo_p (fixp
->fx_r_type
))
13094 && HAVE_IN_PLACE_ADDENDS
13095 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13099 /* Don't adjust relocations against mips16 symbols, so that the linker
13100 can find them if it needs to set up a stub. */
13101 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13102 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13103 && fixp
->fx_subsy
== NULL
)
13110 /* Translate internal representation of relocation info to BFD target
13114 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13116 static arelent
*retval
[4];
13118 bfd_reloc_code_real_type code
;
13120 memset (retval
, 0, sizeof(retval
));
13121 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13122 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13123 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13124 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13126 assert (! fixp
->fx_pcrel
);
13127 reloc
->addend
= fixp
->fx_addnumber
;
13129 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13130 entry to be used in the relocation's section offset. */
13131 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13133 reloc
->address
= reloc
->addend
;
13137 code
= fixp
->fx_r_type
;
13139 /* To support a PC relative reloc, we used a Cygnus extension.
13140 We check for that here to make sure that we don't let such a
13141 reloc escape normally. (FIXME: This was formerly used by
13142 embedded-PIC support, but is now used by branch handling in
13143 general. That probably should be fixed.) */
13144 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13145 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13146 && code
== BFD_RELOC_16_PCREL_S2
)
13147 reloc
->howto
= NULL
;
13149 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13151 if (reloc
->howto
== NULL
)
13153 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13154 _("Can not represent %s relocation in this object file format"),
13155 bfd_get_reloc_code_name (code
));
13162 /* Relax a machine dependent frag. This returns the amount by which
13163 the current size of the frag should change. */
13166 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13168 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13170 offsetT old_var
= fragp
->fr_var
;
13172 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13174 return fragp
->fr_var
- old_var
;
13177 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13180 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13182 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13184 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13189 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13191 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13198 /* Convert a machine dependent frag. */
13201 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13203 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13206 unsigned long insn
;
13210 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13212 if (target_big_endian
)
13213 insn
= bfd_getb32 (buf
);
13215 insn
= bfd_getl32 (buf
);
13217 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13219 /* We generate a fixup instead of applying it right now
13220 because, if there are linker relaxations, we're going to
13221 need the relocations. */
13222 exp
.X_op
= O_symbol
;
13223 exp
.X_add_symbol
= fragp
->fr_symbol
;
13224 exp
.X_add_number
= fragp
->fr_offset
;
13226 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13228 BFD_RELOC_16_PCREL_S2
);
13229 fixp
->fx_file
= fragp
->fr_file
;
13230 fixp
->fx_line
= fragp
->fr_line
;
13232 md_number_to_chars ((char *) buf
, insn
, 4);
13239 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13240 _("relaxed out-of-range branch into a jump"));
13242 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13245 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13247 /* Reverse the branch. */
13248 switch ((insn
>> 28) & 0xf)
13251 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13252 have the condition reversed by tweaking a single
13253 bit, and their opcodes all have 0x4???????. */
13254 assert ((insn
& 0xf1000000) == 0x41000000);
13255 insn
^= 0x00010000;
13259 /* bltz 0x04000000 bgez 0x04010000
13260 bltzal 0x04100000 bgezal 0x04110000 */
13261 assert ((insn
& 0xfc0e0000) == 0x04000000);
13262 insn
^= 0x00010000;
13266 /* beq 0x10000000 bne 0x14000000
13267 blez 0x18000000 bgtz 0x1c000000 */
13268 insn
^= 0x04000000;
13276 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13278 /* Clear the and-link bit. */
13279 assert ((insn
& 0xfc1c0000) == 0x04100000);
13281 /* bltzal 0x04100000 bgezal 0x04110000
13282 bltzall 0x04120000 bgezall 0x04130000 */
13283 insn
&= ~0x00100000;
13286 /* Branch over the branch (if the branch was likely) or the
13287 full jump (not likely case). Compute the offset from the
13288 current instruction to branch to. */
13289 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13293 /* How many bytes in instructions we've already emitted? */
13294 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13295 /* How many bytes in instructions from here to the end? */
13296 i
= fragp
->fr_var
- i
;
13298 /* Convert to instruction count. */
13300 /* Branch counts from the next instruction. */
13303 /* Branch over the jump. */
13304 md_number_to_chars ((char *) buf
, insn
, 4);
13308 md_number_to_chars ((char *) buf
, 0, 4);
13311 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13313 /* beql $0, $0, 2f */
13315 /* Compute the PC offset from the current instruction to
13316 the end of the variable frag. */
13317 /* How many bytes in instructions we've already emitted? */
13318 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13319 /* How many bytes in instructions from here to the end? */
13320 i
= fragp
->fr_var
- i
;
13321 /* Convert to instruction count. */
13323 /* Don't decrement i, because we want to branch over the
13327 md_number_to_chars ((char *) buf
, insn
, 4);
13330 md_number_to_chars ((char *) buf
, 0, 4);
13335 if (mips_pic
== NO_PIC
)
13338 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13339 ? 0x0c000000 : 0x08000000);
13340 exp
.X_op
= O_symbol
;
13341 exp
.X_add_symbol
= fragp
->fr_symbol
;
13342 exp
.X_add_number
= fragp
->fr_offset
;
13344 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13345 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13346 fixp
->fx_file
= fragp
->fr_file
;
13347 fixp
->fx_line
= fragp
->fr_line
;
13349 md_number_to_chars ((char *) buf
, insn
, 4);
13354 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13355 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13356 exp
.X_op
= O_symbol
;
13357 exp
.X_add_symbol
= fragp
->fr_symbol
;
13358 exp
.X_add_number
= fragp
->fr_offset
;
13360 if (fragp
->fr_offset
)
13362 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13363 exp
.X_add_number
= 0;
13366 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13367 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13368 fixp
->fx_file
= fragp
->fr_file
;
13369 fixp
->fx_line
= fragp
->fr_line
;
13371 md_number_to_chars ((char *) buf
, insn
, 4);
13374 if (mips_opts
.isa
== ISA_MIPS1
)
13377 md_number_to_chars ((char *) buf
, 0, 4);
13381 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13382 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13384 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13385 4, &exp
, 0, BFD_RELOC_LO16
);
13386 fixp
->fx_file
= fragp
->fr_file
;
13387 fixp
->fx_line
= fragp
->fr_line
;
13389 md_number_to_chars ((char *) buf
, insn
, 4);
13393 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13398 md_number_to_chars ((char *) buf
, insn
, 4);
13403 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13404 + fragp
->fr_fix
+ fragp
->fr_var
);
13406 fragp
->fr_fix
+= fragp
->fr_var
;
13411 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13414 register const struct mips16_immed_operand
*op
;
13415 bfd_boolean small
, ext
;
13418 unsigned long insn
;
13419 bfd_boolean use_extend
;
13420 unsigned short extend
;
13422 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13423 op
= mips16_immed_operands
;
13424 while (op
->type
!= type
)
13427 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13438 resolve_symbol_value (fragp
->fr_symbol
);
13439 val
= S_GET_VALUE (fragp
->fr_symbol
);
13444 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13446 /* The rules for the base address of a PC relative reloc are
13447 complicated; see mips16_extended_frag. */
13448 if (type
== 'p' || type
== 'q')
13453 /* Ignore the low bit in the target, since it will be
13454 set for a text label. */
13455 if ((val
& 1) != 0)
13458 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13460 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13463 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13466 /* Make sure the section winds up with the alignment we have
13469 record_alignment (asec
, op
->shift
);
13473 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13474 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13475 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13476 _("extended instruction in delay slot"));
13478 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13480 if (target_big_endian
)
13481 insn
= bfd_getb16 (buf
);
13483 insn
= bfd_getl16 (buf
);
13485 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13486 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13487 small
, ext
, &insn
, &use_extend
, &extend
);
13491 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13492 fragp
->fr_fix
+= 2;
13496 md_number_to_chars ((char *) buf
, insn
, 2);
13497 fragp
->fr_fix
+= 2;
13505 first
= RELAX_FIRST (fragp
->fr_subtype
);
13506 second
= RELAX_SECOND (fragp
->fr_subtype
);
13507 fixp
= (fixS
*) fragp
->fr_opcode
;
13509 /* Possibly emit a warning if we've chosen the longer option. */
13510 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13511 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13513 const char *msg
= macro_warning (fragp
->fr_subtype
);
13515 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13518 /* Go through all the fixups for the first sequence. Disable them
13519 (by marking them as done) if we're going to use the second
13520 sequence instead. */
13522 && fixp
->fx_frag
== fragp
13523 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13525 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13527 fixp
= fixp
->fx_next
;
13530 /* Go through the fixups for the second sequence. Disable them if
13531 we're going to use the first sequence, otherwise adjust their
13532 addresses to account for the relaxation. */
13533 while (fixp
&& fixp
->fx_frag
== fragp
)
13535 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13536 fixp
->fx_where
-= first
;
13539 fixp
= fixp
->fx_next
;
13542 /* Now modify the frag contents. */
13543 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13547 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13548 memmove (start
, start
+ first
, second
);
13549 fragp
->fr_fix
-= first
;
13552 fragp
->fr_fix
-= second
;
13558 /* This function is called after the relocs have been generated.
13559 We've been storing mips16 text labels as odd. Here we convert them
13560 back to even for the convenience of the debugger. */
13563 mips_frob_file_after_relocs (void)
13566 unsigned int count
, i
;
13568 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13571 syms
= bfd_get_outsymbols (stdoutput
);
13572 count
= bfd_get_symcount (stdoutput
);
13573 for (i
= 0; i
< count
; i
++, syms
++)
13575 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13576 && ((*syms
)->value
& 1) != 0)
13578 (*syms
)->value
&= ~1;
13579 /* If the symbol has an odd size, it was probably computed
13580 incorrectly, so adjust that as well. */
13581 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13582 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13589 /* This function is called whenever a label is defined. It is used
13590 when handling branch delays; if a branch has a label, we assume we
13591 can not move it. */
13594 mips_define_label (symbolS
*sym
)
13596 struct insn_label_list
*l
;
13598 if (free_insn_labels
== NULL
)
13599 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13602 l
= free_insn_labels
;
13603 free_insn_labels
= l
->next
;
13607 l
->next
= insn_labels
;
13611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13613 /* Some special processing for a MIPS ELF file. */
13616 mips_elf_final_processing (void)
13618 /* Write out the register information. */
13619 if (mips_abi
!= N64_ABI
)
13623 s
.ri_gprmask
= mips_gprmask
;
13624 s
.ri_cprmask
[0] = mips_cprmask
[0];
13625 s
.ri_cprmask
[1] = mips_cprmask
[1];
13626 s
.ri_cprmask
[2] = mips_cprmask
[2];
13627 s
.ri_cprmask
[3] = mips_cprmask
[3];
13628 /* The gp_value field is set by the MIPS ELF backend. */
13630 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13631 ((Elf32_External_RegInfo
*)
13632 mips_regmask_frag
));
13636 Elf64_Internal_RegInfo s
;
13638 s
.ri_gprmask
= mips_gprmask
;
13640 s
.ri_cprmask
[0] = mips_cprmask
[0];
13641 s
.ri_cprmask
[1] = mips_cprmask
[1];
13642 s
.ri_cprmask
[2] = mips_cprmask
[2];
13643 s
.ri_cprmask
[3] = mips_cprmask
[3];
13644 /* The gp_value field is set by the MIPS ELF backend. */
13646 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13647 ((Elf64_External_RegInfo
*)
13648 mips_regmask_frag
));
13651 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13652 sort of BFD interface for this. */
13653 if (mips_any_noreorder
)
13654 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13655 if (mips_pic
!= NO_PIC
)
13657 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13658 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13661 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13663 /* Set MIPS ELF flags for ASEs. */
13664 /* We may need to define a new flag for DSP ASE, and set this flag when
13665 file_ase_dsp is true. */
13666 /* We may need to define a new flag for MT ASE, and set this flag when
13667 file_ase_mt is true. */
13668 if (file_ase_mips16
)
13669 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13670 #if 0 /* XXX FIXME */
13671 if (file_ase_mips3d
)
13672 elf_elfheader (stdoutput
)->e_flags
|= ???;
13675 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13677 /* Set the MIPS ELF ABI flags. */
13678 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13679 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13680 else if (mips_abi
== O64_ABI
)
13681 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13682 else if (mips_abi
== EABI_ABI
)
13684 if (!file_mips_gp32
)
13685 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13687 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13689 else if (mips_abi
== N32_ABI
)
13690 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13692 /* Nothing to do for N64_ABI. */
13694 if (mips_32bitmode
)
13695 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13698 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13700 typedef struct proc
{
13702 symbolS
*func_end_sym
;
13703 unsigned long reg_mask
;
13704 unsigned long reg_offset
;
13705 unsigned long fpreg_mask
;
13706 unsigned long fpreg_offset
;
13707 unsigned long frame_offset
;
13708 unsigned long frame_reg
;
13709 unsigned long pc_reg
;
13712 static procS cur_proc
;
13713 static procS
*cur_proc_ptr
;
13714 static int numprocs
;
13716 /* Fill in an rs_align_code fragment. */
13719 mips_handle_align (fragS
*fragp
)
13721 if (fragp
->fr_type
!= rs_align_code
)
13724 if (mips_opts
.mips16
)
13726 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13727 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13732 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13733 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13741 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13745 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13749 md_obj_begin (void)
13756 /* check for premature end, nesting errors, etc */
13758 as_warn (_("missing .end at end of assembly"));
13767 if (*input_line_pointer
== '-')
13769 ++input_line_pointer
;
13772 if (!ISDIGIT (*input_line_pointer
))
13773 as_bad (_("expected simple number"));
13774 if (input_line_pointer
[0] == '0')
13776 if (input_line_pointer
[1] == 'x')
13778 input_line_pointer
+= 2;
13779 while (ISXDIGIT (*input_line_pointer
))
13782 val
|= hex_value (*input_line_pointer
++);
13784 return negative
? -val
: val
;
13788 ++input_line_pointer
;
13789 while (ISDIGIT (*input_line_pointer
))
13792 val
|= *input_line_pointer
++ - '0';
13794 return negative
? -val
: val
;
13797 if (!ISDIGIT (*input_line_pointer
))
13799 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13800 *input_line_pointer
, *input_line_pointer
);
13801 as_warn (_("invalid number"));
13804 while (ISDIGIT (*input_line_pointer
))
13807 val
+= *input_line_pointer
++ - '0';
13809 return negative
? -val
: val
;
13812 /* The .file directive; just like the usual .file directive, but there
13813 is an initial number which is the ECOFF file index. In the non-ECOFF
13814 case .file implies DWARF-2. */
13817 s_mips_file (int x ATTRIBUTE_UNUSED
)
13819 static int first_file_directive
= 0;
13821 if (ECOFF_DEBUGGING
)
13830 filename
= dwarf2_directive_file (0);
13832 /* Versions of GCC up to 3.1 start files with a ".file"
13833 directive even for stabs output. Make sure that this
13834 ".file" is handled. Note that you need a version of GCC
13835 after 3.1 in order to support DWARF-2 on MIPS. */
13836 if (filename
!= NULL
&& ! first_file_directive
)
13838 (void) new_logical_line (filename
, -1);
13839 s_app_file_string (filename
, 0);
13841 first_file_directive
= 1;
13845 /* The .loc directive, implying DWARF-2. */
13848 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13850 if (!ECOFF_DEBUGGING
)
13851 dwarf2_directive_loc (0);
13854 /* The .end directive. */
13857 s_mips_end (int x ATTRIBUTE_UNUSED
)
13861 /* Following functions need their own .frame and .cprestore directives. */
13862 mips_frame_reg_valid
= 0;
13863 mips_cprestore_valid
= 0;
13865 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13868 demand_empty_rest_of_line ();
13873 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13874 as_warn (_(".end not in text section"));
13878 as_warn (_(".end directive without a preceding .ent directive."));
13879 demand_empty_rest_of_line ();
13885 assert (S_GET_NAME (p
));
13886 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13887 as_warn (_(".end symbol does not match .ent symbol."));
13889 if (debug_type
== DEBUG_STABS
)
13890 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13894 as_warn (_(".end directive missing or unknown symbol"));
13897 /* Create an expression to calculate the size of the function. */
13898 if (p
&& cur_proc_ptr
)
13900 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13901 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13904 exp
->X_op
= O_subtract
;
13905 exp
->X_add_symbol
= symbol_temp_new_now ();
13906 exp
->X_op_symbol
= p
;
13907 exp
->X_add_number
= 0;
13909 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13912 /* Generate a .pdr section. */
13913 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13916 segT saved_seg
= now_seg
;
13917 subsegT saved_subseg
= now_subseg
;
13922 dot
= frag_now_fix ();
13924 #ifdef md_flush_pending_output
13925 md_flush_pending_output ();
13929 subseg_set (pdr_seg
, 0);
13931 /* Write the symbol. */
13932 exp
.X_op
= O_symbol
;
13933 exp
.X_add_symbol
= p
;
13934 exp
.X_add_number
= 0;
13935 emit_expr (&exp
, 4);
13937 fragp
= frag_more (7 * 4);
13939 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13940 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13941 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13942 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13943 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13944 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13945 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13947 subseg_set (saved_seg
, saved_subseg
);
13949 #endif /* OBJ_ELF */
13951 cur_proc_ptr
= NULL
;
13954 /* The .aent and .ent directives. */
13957 s_mips_ent (int aent
)
13961 symbolP
= get_symbol ();
13962 if (*input_line_pointer
== ',')
13963 ++input_line_pointer
;
13964 SKIP_WHITESPACE ();
13965 if (ISDIGIT (*input_line_pointer
)
13966 || *input_line_pointer
== '-')
13969 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13970 as_warn (_(".ent or .aent not in text section."));
13972 if (!aent
&& cur_proc_ptr
)
13973 as_warn (_("missing .end"));
13977 /* This function needs its own .frame and .cprestore directives. */
13978 mips_frame_reg_valid
= 0;
13979 mips_cprestore_valid
= 0;
13981 cur_proc_ptr
= &cur_proc
;
13982 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13984 cur_proc_ptr
->func_sym
= symbolP
;
13986 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13990 if (debug_type
== DEBUG_STABS
)
13991 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13992 S_GET_NAME (symbolP
));
13995 demand_empty_rest_of_line ();
13998 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13999 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14000 s_mips_frame is used so that we can set the PDR information correctly.
14001 We can't use the ecoff routines because they make reference to the ecoff
14002 symbol table (in the mdebug section). */
14005 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14008 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14012 if (cur_proc_ptr
== (procS
*) NULL
)
14014 as_warn (_(".frame outside of .ent"));
14015 demand_empty_rest_of_line ();
14019 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14021 SKIP_WHITESPACE ();
14022 if (*input_line_pointer
++ != ','
14023 || get_absolute_expression_and_terminator (&val
) != ',')
14025 as_warn (_("Bad .frame directive"));
14026 --input_line_pointer
;
14027 demand_empty_rest_of_line ();
14031 cur_proc_ptr
->frame_offset
= val
;
14032 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14034 demand_empty_rest_of_line ();
14037 #endif /* OBJ_ELF */
14041 /* The .fmask and .mask directives. If the mdebug section is present
14042 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14043 embedded targets, s_mips_mask is used so that we can set the PDR
14044 information correctly. We can't use the ecoff routines because they
14045 make reference to the ecoff symbol table (in the mdebug section). */
14048 s_mips_mask (int reg_type
)
14051 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14055 if (cur_proc_ptr
== (procS
*) NULL
)
14057 as_warn (_(".mask/.fmask outside of .ent"));
14058 demand_empty_rest_of_line ();
14062 if (get_absolute_expression_and_terminator (&mask
) != ',')
14064 as_warn (_("Bad .mask/.fmask directive"));
14065 --input_line_pointer
;
14066 demand_empty_rest_of_line ();
14070 off
= get_absolute_expression ();
14072 if (reg_type
== 'F')
14074 cur_proc_ptr
->fpreg_mask
= mask
;
14075 cur_proc_ptr
->fpreg_offset
= off
;
14079 cur_proc_ptr
->reg_mask
= mask
;
14080 cur_proc_ptr
->reg_offset
= off
;
14083 demand_empty_rest_of_line ();
14086 #endif /* OBJ_ELF */
14087 s_ignore (reg_type
);
14090 /* A table describing all the processors gas knows about. Names are
14091 matched in the order listed.
14093 To ease comparison, please keep this table in the same order as
14094 gcc's mips_cpu_info_table[]. */
14095 static const struct mips_cpu_info mips_cpu_info_table
[] =
14097 /* Entries for generic ISAs */
14098 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14099 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14100 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14101 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14102 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14103 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14104 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14105 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14106 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14109 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14110 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14111 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14114 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14117 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14118 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14119 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14120 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14121 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14122 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14123 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14124 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14125 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14126 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14127 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14128 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14131 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14132 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14133 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14134 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14135 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14136 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14137 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14138 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14139 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14140 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14141 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14142 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14143 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14146 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14147 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14148 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14150 /* MIPS32 Release 2 */
14151 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14152 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14153 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14154 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14155 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14158 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14159 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14160 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14162 /* Broadcom SB-1 CPU core */
14163 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14170 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14171 with a final "000" replaced by "k". Ignore case.
14173 Note: this function is shared between GCC and GAS. */
14176 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14178 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14179 given
++, canonical
++;
14181 return ((*given
== 0 && *canonical
== 0)
14182 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14186 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14187 CPU name. We've traditionally allowed a lot of variation here.
14189 Note: this function is shared between GCC and GAS. */
14192 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14194 /* First see if the name matches exactly, or with a final "000"
14195 turned into "k". */
14196 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14199 /* If not, try comparing based on numerical designation alone.
14200 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14201 if (TOLOWER (*given
) == 'r')
14203 if (!ISDIGIT (*given
))
14206 /* Skip over some well-known prefixes in the canonical name,
14207 hoping to find a number there too. */
14208 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14210 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14212 else if (TOLOWER (canonical
[0]) == 'r')
14215 return mips_strict_matching_cpu_name_p (canonical
, given
);
14219 /* Parse an option that takes the name of a processor as its argument.
14220 OPTION is the name of the option and CPU_STRING is the argument.
14221 Return the corresponding processor enumeration if the CPU_STRING is
14222 recognized, otherwise report an error and return null.
14224 A similar function exists in GCC. */
14226 static const struct mips_cpu_info
*
14227 mips_parse_cpu (const char *option
, const char *cpu_string
)
14229 const struct mips_cpu_info
*p
;
14231 /* 'from-abi' selects the most compatible architecture for the given
14232 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14233 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14234 version. Look first at the -mgp options, if given, otherwise base
14235 the choice on MIPS_DEFAULT_64BIT.
14237 Treat NO_ABI like the EABIs. One reason to do this is that the
14238 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14239 architecture. This code picks MIPS I for 'mips' and MIPS III for
14240 'mips64', just as we did in the days before 'from-abi'. */
14241 if (strcasecmp (cpu_string
, "from-abi") == 0)
14243 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14244 return mips_cpu_info_from_isa (ISA_MIPS1
);
14246 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14247 return mips_cpu_info_from_isa (ISA_MIPS3
);
14249 if (file_mips_gp32
>= 0)
14250 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14252 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14257 /* 'default' has traditionally been a no-op. Probably not very useful. */
14258 if (strcasecmp (cpu_string
, "default") == 0)
14261 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14262 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14265 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14269 /* Return the canonical processor information for ISA (a member of the
14270 ISA_MIPS* enumeration). */
14272 static const struct mips_cpu_info
*
14273 mips_cpu_info_from_isa (int isa
)
14277 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14278 if (mips_cpu_info_table
[i
].is_isa
14279 && isa
== mips_cpu_info_table
[i
].isa
)
14280 return (&mips_cpu_info_table
[i
]);
14285 static const struct mips_cpu_info
*
14286 mips_cpu_info_from_arch (int arch
)
14290 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14291 if (arch
== mips_cpu_info_table
[i
].cpu
)
14292 return (&mips_cpu_info_table
[i
]);
14298 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14302 fprintf (stream
, "%24s", "");
14307 fprintf (stream
, ", ");
14311 if (*col_p
+ strlen (string
) > 72)
14313 fprintf (stream
, "\n%24s", "");
14317 fprintf (stream
, "%s", string
);
14318 *col_p
+= strlen (string
);
14324 md_show_usage (FILE *stream
)
14329 fprintf (stream
, _("\
14331 -EB generate big endian output\n\
14332 -EL generate little endian output\n\
14333 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14334 -G NUM allow referencing objects up to NUM bytes\n\
14335 implicitly with the gp register [default 8]\n"));
14336 fprintf (stream
, _("\
14337 -mips1 generate MIPS ISA I instructions\n\
14338 -mips2 generate MIPS ISA II instructions\n\
14339 -mips3 generate MIPS ISA III instructions\n\
14340 -mips4 generate MIPS ISA IV instructions\n\
14341 -mips5 generate MIPS ISA V instructions\n\
14342 -mips32 generate MIPS32 ISA instructions\n\
14343 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14344 -mips64 generate MIPS64 ISA instructions\n\
14345 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14346 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14350 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14351 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14352 show (stream
, "from-abi", &column
, &first
);
14353 fputc ('\n', stream
);
14355 fprintf (stream
, _("\
14356 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14357 -no-mCPU don't generate code specific to CPU.\n\
14358 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14362 show (stream
, "3900", &column
, &first
);
14363 show (stream
, "4010", &column
, &first
);
14364 show (stream
, "4100", &column
, &first
);
14365 show (stream
, "4650", &column
, &first
);
14366 fputc ('\n', stream
);
14368 fprintf (stream
, _("\
14369 -mips16 generate mips16 instructions\n\
14370 -no-mips16 do not generate mips16 instructions\n"));
14371 fprintf (stream
, _("\
14372 -mdsp generate DSP instructions\n\
14373 -mno-dsp do not generate DSP instructions\n"));
14374 fprintf (stream
, _("\
14375 -mmt generate MT instructions\n\
14376 -mno-mt do not generate MT instructions\n"));
14377 fprintf (stream
, _("\
14378 -mfix-vr4120 work around certain VR4120 errata\n\
14379 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14380 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14381 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14382 -mno-shared optimize output for executables\n\
14383 -msym32 assume all symbols have 32-bit values\n\
14384 -O0 remove unneeded NOPs, do not swap branches\n\
14385 -O remove unneeded NOPs and swap branches\n\
14386 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14387 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14388 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14390 fprintf (stream
, _("\
14391 -KPIC, -call_shared generate SVR4 position independent code\n\
14392 -non_shared do not generate position independent code\n\
14393 -xgot assume a 32 bit GOT\n\
14394 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14395 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14397 -mabi=ABI create ABI conformant object file for:\n"));
14401 show (stream
, "32", &column
, &first
);
14402 show (stream
, "o64", &column
, &first
);
14403 show (stream
, "n32", &column
, &first
);
14404 show (stream
, "64", &column
, &first
);
14405 show (stream
, "eabi", &column
, &first
);
14407 fputc ('\n', stream
);
14409 fprintf (stream
, _("\
14410 -32 create o32 ABI object file (default)\n\
14411 -n32 create n32 ABI object file\n\
14412 -64 create 64 ABI object file\n"));
14417 mips_dwarf2_format (void)
14419 if (mips_abi
== N64_ABI
)
14422 return dwarf2_format_64bit_irix
;
14424 return dwarf2_format_64bit
;
14428 return dwarf2_format_32bit
;
14432 mips_dwarf2_addr_size (void)
14434 if (mips_abi
== N64_ABI
)
14440 /* Standard calling conventions leave the CFA at SP on entry. */
14442 mips_cfi_frame_initial_instructions (void)
14444 cfi_add_CFA_def_cfa_register (SP
);