1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* MIPS ISA (Instruction Set Architecture) level. */
50 static int mips_isa
= -1;
52 static int mips_warn_about_macros
;
53 static int mips_noreorder
;
54 static int mips_nomove
;
56 static int mips_nobopt
;
59 /* The size of the small data section. */
60 static int g_switch_value
= 8;
66 /* handle of the OPCODE hash table */
67 static struct hash_control
*op_hash
= NULL
;
69 /* This array holds the chars that always start a comment. If the
70 pre-processor is disabled, these aren't very useful */
71 const char comment_chars
[] = "#";
73 /* This array holds the chars that only start a comment at the beginning of
74 a line. If the line seems to have the form '# 123 filename'
75 .line and .file directives will appear in the pre-processed output */
76 /* Note that input_file.c hand checks for '#' at the beginning of the
77 first line of the input file. This is because the compiler outputs
78 #NO_APP at the beginning of its output. */
79 /* Also note that C style comments are always supported. */
80 const char line_comment_chars
[] = "#";
82 /* This array holds machine specific line separator characters. */
83 const char line_separator_chars
[] = "";
85 /* Chars that can be used to separate mant from exp in floating point nums */
86 const char EXP_CHARS
[] = "eE";
88 /* Chars that mean this number is a floating point constant */
91 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
93 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
94 changed in read.c . Ideally it shouldn't have to know about it at all,
95 but nothing is ideal around here.
98 static char *insn_error
;
100 static int byte_order
= BYTE_ORDER
;
102 static int auto_align
= 1;
104 /* Symbol labelling the current insn. */
105 static symbolS
*insn_label
;
107 /* To output NOP instructions correctly, we need to keep information
108 about the previous two instructions. */
110 /* Whether we are optimizing. The default value of 2 means to remove
111 unneeded NOPs and swap branch instructions when possible. A value
112 of 1 means to not swap branches. A value of 0 means to always
114 static int mips_optimize
= 2;
116 /* The previous instruction. */
117 static struct mips_cl_insn prev_insn
;
119 /* The instruction before prev_insn. */
120 static struct mips_cl_insn prev_prev_insn
;
122 /* If we don't want information for prev_insn or prev_prev_insn, we
123 point the insn_mo field at this dummy integer. */
124 static const struct mips_opcode dummy_opcode
= { 0 };
126 /* Non-zero if prev_insn is valid. */
127 static int prev_insn_valid
;
129 /* The frag for the previous instruction. */
130 static struct frag
*prev_insn_frag
;
132 /* The offset into prev_insn_frag for the previous instruction. */
133 static long prev_insn_where
;
135 /* The reloc for the previous instruction, if any. */
136 static fixS
*prev_insn_fixp
;
138 /* Non-zero if the previous instruction was in a delay slot. */
139 static int prev_insn_is_delay_slot
;
141 /* Non-zero if the previous instruction was in a .set noreorder. */
142 static int prev_insn_unreordered
;
144 /* Non-zero if the previous previous instruction was in a .set
146 static int prev_prev_insn_unreordered
;
148 /* Prototypes for static functions. */
151 #define internalError() \
152 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
154 #define internalError() as_fatal ("MIPS internal Error");
157 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
159 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
161 bfd_reloc_code_real_type r
));
162 static void mips_no_prev_insn
PARAMS ((void));
163 static void mips_emit_delays
PARAMS ((void));
164 static int gp_reference
PARAMS ((expressionS
* ep
));
165 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
166 const char *name
, const char *fmt
,
168 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
170 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
171 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
173 static void load_register
PARAMS ((int *counter
,
174 int reg
, expressionS
* ep
));
175 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
176 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
177 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
178 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
179 static symbolS
*get_symbol
PARAMS ((void));
180 static void mips_align
PARAMS ((int to
, int fill
));
181 static void s_align
PARAMS ((int));
182 static void s_stringer
PARAMS ((int));
183 static void s_change_sec
PARAMS ((int));
184 static void s_cons
PARAMS ((int));
185 static void s_err
PARAMS ((int));
186 static void s_extern
PARAMS ((int));
187 static void s_float_cons
PARAMS ((int));
188 static void s_option
PARAMS ((int));
189 static void s_mipsset
PARAMS ((int));
190 static void s_mips_space
PARAMS ((int));
192 static void md_obj_begin
PARAMS ((void));
193 static void md_obj_end
PARAMS ((void));
194 static long get_number
PARAMS ((void));
195 static void s_ent
PARAMS ((int));
196 static void s_mipsend
PARAMS ((int));
197 static void s_file
PARAMS ((int));
198 static void s_frame
PARAMS ((int));
199 static void s_loc
PARAMS ((int));
200 static void s_mask
PARAMS ((char));
205 The following pseudo-ops from the Kane and Heinrich MIPS book
206 should be defined here, but are currently unsupported: .alias,
207 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
209 The following pseudo-ops from the Kane and Heinrich MIPS book are
210 specific to the type of debugging information being generated, and
211 should be defined by the object format: .aent, .begin, .bend,
212 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
215 The following pseudo-ops from the Kane and Heinrich MIPS book are
216 not MIPS CPU specific, but are also not specific to the object file
217 format. This file is probably the best place to define them, but
218 they are not currently supported: .asm0, .endr, .lab, .repeat,
219 .struct, .weakext. */
221 const pseudo_typeS md_pseudo_table
[] =
223 /* MIPS specific pseudo-ops. */
224 {"option", s_option
, 0},
225 {"set", s_mipsset
, 0},
226 {"rdata", s_change_sec
, 'r',},
227 {"sdata", s_change_sec
, 's',},
229 /* Relatively generic pseudo-ops that happen to be used on MIPS
231 {"asciiz", s_stringer
, 1},
232 {"bss", s_change_sec
, 'b'},
236 /* These pseudo-ops are defined in read.c, but must be overridden
237 here for one reason or another. */
238 {"align", s_align
, 0},
239 {"ascii", s_stringer
, 0},
240 {"asciz", s_stringer
, 1},
242 {"data", s_change_sec
, 'd'},
243 {"double", s_float_cons
, 'd'},
244 {"extern", s_extern
, 0},
245 {"float", s_float_cons
, 'f'},
246 {"space", s_mips_space
, 0},
247 {"text", s_change_sec
, 't'},
251 /* These pseudo-ops should be defined by the object file format.
252 However, ECOFF is the only format which currently defines them,
253 so we have versions here for a.out. */
255 {"end", s_mipsend
, 0},
258 {"fmask", s_ignore
, 'F'},
259 {"frame", s_ignore
, 0},
260 {"loc", s_ignore
, 0},
261 {"mask", s_ignore
, 'R'},
262 {"verstamp", s_ignore
, 0},
269 const relax_typeS md_relax_table
[] =
275 static char *expr_end
;
277 static expressionS imm_expr
;
278 static expressionS offset_expr
;
279 static bfd_reloc_code_real_type imm_reloc
;
280 static bfd_reloc_code_real_type offset_reloc
;
283 * This function is called once, at assembler startup time. It should
284 * set up all the tables, etc. that the MD part of the assembler will need.
289 register char *retval
= NULL
;
290 register unsigned int i
= 0;
294 if (strcmp (TARGET_CPU
, "mips") == 0)
296 else if (strcmp (TARGET_CPU
, "r6000") == 0
297 || strcmp (TARGET_CPU
, "mips2") == 0)
299 else if (strcmp (TARGET_CPU
, "mips64") == 0
300 || strcmp (TARGET_CPU
, "r4000") == 0
301 || strcmp (TARGET_CPU
, "mips3") == 0)
307 if ((op_hash
= hash_new ()) == NULL
)
309 as_fatal ("Virtual memory exhausted");
311 for (i
= 0; i
< NUMOPCODES
;)
313 const char *name
= mips_opcodes
[i
].name
;
315 retval
= hash_insert (op_hash
, name
, &mips_opcodes
[i
]);
316 if (retval
!= NULL
&& *retval
!= '\0')
318 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
319 mips_opcodes
[i
].name
, retval
);
320 as_fatal ("Broken assembler. No assembly attempted.");
324 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
325 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
326 != mips_opcodes
[i
].match
))
328 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
329 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
330 as_fatal ("Broken assembler. No assembly attempted.");
334 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
337 mips_no_prev_insn ();
339 /* set the default alignment for the text section (2**2) */
340 record_alignment (text_section
, 2);
343 bfd_set_gp_size (stdoutput
, g_switch_value
);
363 struct mips_cl_insn insn
;
365 imm_expr
.X_op
= O_absent
;
366 offset_expr
.X_op
= O_absent
;
368 mips_ip (str
, &insn
);
371 as_bad ("%s `%s'", insn_error
, str
);
374 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
380 if (imm_expr
.X_op
!= O_absent
)
381 append_insn (&insn
, &imm_expr
, imm_reloc
);
382 else if (offset_expr
.X_op
!= O_absent
)
383 append_insn (&insn
, &offset_expr
, offset_reloc
);
385 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
389 /* See whether instruction IP reads register REG. If FPR is non-zero,
390 REG is a floating point register. */
393 insn_uses_reg (ip
, reg
, fpr
)
394 struct mips_cl_insn
*ip
;
398 /* Don't report on general register 0, since it never changes. */
399 if (! fpr
&& reg
== 0)
404 /* If we are called with either $f0 or $f1, we must check $f0.
405 This is not optimal, because it will introduce an unnecessary
406 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
407 need to distinguish reading both $f0 and $f1 or just one of
408 them. Note that we don't have to check the other way,
409 because there is no instruction that sets both $f0 and $f1
410 and requires a delay. */
411 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
412 && ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) == (reg
&~ 1))
414 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
415 && ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) == (reg
&~ 1))
420 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
421 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
423 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
424 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
431 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
432 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
436 * Output an instruction.
439 append_insn (ip
, address_expr
, reloc_type
)
440 struct mips_cl_insn
*ip
;
441 expressionS
*address_expr
;
442 bfd_reloc_code_real_type reloc_type
;
448 if (! mips_noreorder
)
450 /* If the previous insn required any delay slots, see if we need
451 to insert a NOP or two. There are eight kinds of possible
452 hazards, of which an instruction can have at most one type.
453 (1) a load from memory delay
454 (2) a load from a coprocessor delay
455 (3) an unconditional branch delay
456 (4) a conditional branch delay
457 (5) a move to coprocessor register delay
458 (6) a load coprocessor register from memory delay
459 (7) a coprocessor condition code delay
460 (8) a HI/LO special register delay
462 There are a lot of optimizations we could do that we don't.
463 In particular, we do not, in general, reorder instructions.
464 If you use gcc with optimization, it will reorder
465 instructions and generally do much more optimization then we
466 do here; repeating all that work in the assembler would only
467 benefit hand written assembly code, and does not seem worth
470 /* This is how a NOP is emitted. */
471 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
473 /* The previous insn might require a delay slot, depending upon
474 the contents of the current insn. */
475 if ((prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
477 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)))
479 /* A load from a coprocessor or from memory. All load
480 delays delay the use of general register rt for one
481 instruction on the r3000. The r6000 and r4000 use
483 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
484 if (mips_optimize
== 0
485 || insn_uses_reg (ip
,
486 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
491 else if ((prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
493 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)))
495 /* A generic coprocessor delay. The previous instruction
496 modified a coprocessor general or control register. If
497 it modified a control register, we need to avoid any
498 coprocessor instruction (this is probably not always
499 required, but it sometimes is). If it modified a general
500 register, we avoid using that register.
502 On the r6000 and r4000 loading a coprocessor register
503 from memory is interlocked, and does not require a delay.
505 This case is not handled very well. There is no special
506 knowledge of CP0 handling, and the coprocessors other
507 than the floating point unit are not distinguished at
509 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
511 if (mips_optimize
== 0
512 || insn_uses_reg (ip
,
513 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
518 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_S
)
520 if (mips_optimize
== 0
521 || insn_uses_reg (ip
,
522 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
529 /* We don't know exactly what the previous instruction
530 does. If the current instruction uses a coprocessor
531 register, we must insert a NOP. If previous
532 instruction may set the condition codes, and the
533 current instruction uses them, we must insert two
535 if (mips_optimize
== 0
536 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
537 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)))
539 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
543 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
545 /* The previous instruction sets the coprocessor condition
546 codes, but does not require a general coprocessor delay
547 (this means it is a floating point comparison
548 instruction). If this instruction uses the condition
549 codes, we need to insert a single NOP. */
550 if (mips_optimize
== 0
551 || ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
554 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
556 /* The previous instruction reads the LO register; if the
557 current instruction writes to the LO register, we must
559 if (mips_optimize
== 0
560 || ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
563 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
565 /* The previous instruction reads the HI register; if the
566 current instruction writes to the HI register, we must
568 if (mips_optimize
== 0
569 || ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
573 /* There are two cases which require two intervening
574 instructions: 1) setting the condition codes using a move to
575 coprocessor instruction which requires a general coprocessor
576 delay and then reading the condition codes 2) reading the HI
577 or LO register and then writing to it. If we are not already
578 emitting a NOP instruction, we must check for these cases
579 compared to the instruction previous to the previous
582 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
583 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
584 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
585 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
586 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
587 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
588 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
591 /* Now emit the right number of NOP instructions. */
597 if (insn_label
!= NULL
)
599 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
600 insn_label
->sy_frag
= frag_now
;
601 S_SET_VALUE (insn_label
, frag_now_fix ());
608 /* This is testing the address of the frag, not the alignment of
609 the instruction in the current section. */
617 if (address_expr
!= NULL
)
619 if (address_expr
->X_op
== O_constant
)
624 ip
->insn_opcode
|= address_expr
->X_add_number
;
628 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
631 case BFD_RELOC_MIPS_JMP
:
632 case BFD_RELOC_16_PCREL_S2
:
641 assert (reloc_type
!= BFD_RELOC_UNUSED
);
643 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
645 reloc_type
== BFD_RELOC_16_PCREL_S2
,
650 md_number_to_chars (f
, ip
->insn_opcode
, 4);
652 if (! mips_noreorder
)
654 /* Filling the branch delay slot is more complex. We try to
655 switch the branch with the previous instruction, which we can
656 do if the previous instruction does not set up a condition
657 that the branch tests and if the branch is not itself the
658 target of any branch. */
659 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
660 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
662 if (mips_optimize
< 2
663 /* If we have seen .set nobopt, don't optimize. */
665 /* If we have seen .set volatile or .set nomove, don't
668 /* If we had to emit any NOP instructions, then we
669 already know we can not swap. */
671 /* If we don't even know the previous insn, we can not
674 /* If the previous insn is already in a branch delay
675 slot, then we can not swap. */
676 || prev_insn_is_delay_slot
677 /* If the previous previous insn was in a .set
678 noreorder, we can't swap. Actually, the MIPS
679 assembler will swap in this situation. However, gcc
680 configured -with-gnu-as will generate code like
686 in which we can not swap the bne and INSN. If gcc is
687 not configured -with-gnu-as, it does not output the
688 .set pseudo-ops. We don't have to check
689 prev_insn_unreordered, because prev_insn_valid will
690 be 0 in that case. We don't want to use
691 prev_prev_insn_valid, because we do want to be able
692 to swap at the start of a function. */
693 || prev_prev_insn_unreordered
694 /* If the branch is itself the target of a branch, we
695 can not swap. We cheat on this; all we check for is
696 whether there is a label on this instruction. If
697 there are any branches to anything other than a
698 label, users must use .set noreorder. */
699 || insn_label
!= NULL
700 /* If the branch reads the condition codes, we don't
701 even try to swap, because in the sequence
706 we can not swap, and I don't feel like handling that
708 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
709 /* We can not swap with an instruction that requires a
710 delay slot, becase the target of the branch might
711 interfere with that instruction. */
712 || (prev_insn
.insn_mo
->pinfo
713 & (INSN_LOAD_COPROC_DELAY
714 | INSN_COPROC_MOVE_DELAY
715 | INSN_WRITE_COND_CODE
719 && (prev_insn
.insn_mo
->pinfo
720 & (INSN_LOAD_MEMORY_DELAY
721 | INSN_COPROC_MEMORY_DELAY
)))
722 /* We can not swap with a branch instruction. */
723 || (prev_insn
.insn_mo
->pinfo
724 & (INSN_UNCOND_BRANCH_DELAY
725 | INSN_COND_BRANCH_DELAY
726 | INSN_COND_BRANCH_LIKELY
))
727 /* If the branch reads a register that the previous
728 instruction sets, we can not swap. */
729 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
730 && insn_uses_reg (ip
,
731 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
734 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
735 && insn_uses_reg (ip
,
736 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
739 /* If the branch writes a register that the previous
740 instruction reads, we can not swap (we know that
741 branches only write to RD or to $31). */
742 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
743 && insn_uses_reg (&prev_insn
,
744 ((ip
->insn_opcode
>> OP_SH_RD
)
747 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
748 && insn_uses_reg (&prev_insn
, 31, 0))
749 /* If the previous previous instruction has a load
750 delay, and sets a register that the branch reads, we
752 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
754 && (prev_prev_insn
.insn_mo
->pinfo
755 & INSN_LOAD_MEMORY_DELAY
)))
756 && insn_uses_reg (ip
,
757 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
761 /* We could do even better for unconditional branches to
762 portions of this object file; we could pick up the
763 instruction at the destination, put it in the delay
764 slot, and bump the destination address. */
766 /* Update the previous insn information. */
767 prev_prev_insn
= *ip
;
768 prev_insn
.insn_mo
= &dummy_opcode
;
775 /* It looks like we can actually do the swap. */
776 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
777 memcpy (temp
, prev_f
, 4);
778 memcpy (prev_f
, f
, 4);
782 prev_insn_fixp
->fx_frag
= frag_now
;
783 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
787 fixp
->fx_frag
= prev_insn_frag
;
788 fixp
->fx_where
= prev_insn_where
;
790 /* Update the previous insn information; leave prev_insn
792 prev_prev_insn
= *ip
;
794 prev_insn_is_delay_slot
= 1;
796 /* If that was an unconditional branch, forget the previous
798 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
800 prev_prev_insn
.insn_mo
= &dummy_opcode
;
801 prev_insn
.insn_mo
= &dummy_opcode
;
804 else if (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
)
806 /* We don't yet optimize a branch likely. What we should do
807 is look at the target, copy the instruction found there
808 into the delay slot, and increment the branch to jump to
809 the next instruction. */
811 /* Update the previous insn information. */
812 prev_prev_insn
= *ip
;
813 prev_insn
.insn_mo
= &dummy_opcode
;
817 /* Update the previous insn information. */
819 prev_prev_insn
.insn_mo
= &dummy_opcode
;
821 prev_prev_insn
= prev_insn
;
824 /* Any time we see a branch, we always fill the delay slot
825 immediately; since this insn is not a branch, we know it
826 is not in a delay slot. */
827 prev_insn_is_delay_slot
= 0;
830 prev_prev_insn_unreordered
= prev_insn_unreordered
;
831 prev_insn_unreordered
= 0;
832 prev_insn_frag
= frag_now
;
833 prev_insn_where
= f
- frag_now
->fr_literal
;
834 prev_insn_fixp
= fixp
;
838 /* We just output an insn, so the next one doesn't have a label. */
842 /* This function forgets that there was any previous instruction or
848 prev_insn
.insn_mo
= &dummy_opcode
;
849 prev_prev_insn
.insn_mo
= &dummy_opcode
;
851 prev_insn_is_delay_slot
= 0;
852 prev_insn_unreordered
= 0;
853 prev_prev_insn_unreordered
= 0;
857 /* This function must be called whenever we turn on noreorder or emit
858 something other than instructions. It inserts any NOPS which might
859 be needed by the previous instruction, and clears the information
860 kept for the previous instructions. */
865 if (! mips_noreorder
)
870 if ((prev_insn
.insn_mo
->pinfo
871 & (INSN_LOAD_COPROC_DELAY
872 | INSN_COPROC_MOVE_DELAY
873 | INSN_WRITE_COND_CODE
877 && (prev_insn
.insn_mo
->pinfo
878 & (INSN_LOAD_MEMORY_DELAY
879 | INSN_COPROC_MEMORY_DELAY
))))
882 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
883 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
884 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
887 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
888 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
889 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
894 if (insn_label
!= NULL
)
896 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
897 insn_label
->sy_frag
= frag_now
;
898 S_SET_VALUE (insn_label
, frag_now_fix ());
901 mips_no_prev_insn ();
905 /* Return 1 if an expression can be accessed via the GP register. */
916 sym
= ep
->X_add_symbol
;
917 if (sym
== (symbolS
*) NULL
918 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
921 /* Certain symbols can not be referenced off the GP, although it
922 appears as though they can. */
923 symname
= S_GET_NAME (sym
);
924 if (symname
!= (const char *) NULL
925 && (strcmp (symname
, "eprol") == 0
926 || strcmp (symname
, "etext") == 0
927 || strcmp (symname
, "_gp") == 0
928 || strcmp (symname
, "edata") == 0
929 || strcmp (symname
, "_fbss") == 0
930 || strcmp (symname
, "_fdata") == 0
931 || strcmp (symname
, "_ftext") == 0
932 || strcmp (symname
, "end") == 0))
934 if (! S_IS_DEFINED (sym
)
935 && S_GET_VALUE (sym
) != 0
936 && S_GET_VALUE (sym
) <= g_switch_value
)
938 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
939 return (strcmp (segname
, ".sdata") == 0
940 || strcmp (segname
, ".sbss") == 0
941 || strcmp (segname
, ".lit8") == 0
942 || strcmp (segname
, ".lit4") == 0);
943 #else /* ! defined (OBJ_ECOFF) */
944 /* The GP register is only used for ECOFF. */
946 #endif /* ! defined (OBJ_ECOFF) */
949 /* Build an instruction created by a macro expansion. This is passed
950 a pointer to the count of instructions created so far, an
951 expression, the name of the instruction to build, an operand format
952 string, and corresponding arguments. */
956 macro_build (int *counter
,
961 #else /* ! defined (NO_STDARG) */
963 macro_build (counter
, ep
, name
, fmt
, va_alist
)
969 #endif /* ! defined (NO_STDARG) */
971 struct mips_cl_insn insn
;
972 bfd_reloc_code_real_type r
;
976 va_start (args
, fmt
);
982 * If the macro is about to expand into a second instruction,
983 * print a warning if needed. We need to pass ip as a parameter
984 * to generate a better warning message here...
986 if (mips_warn_about_macros
&& *counter
== 1)
987 as_warn ("Macro instruction expanded into multiple instructions");
989 *counter
+= 1; /* bump instruction counter */
991 r
= BFD_RELOC_UNUSED
;
992 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
993 assert (insn
.insn_mo
);
994 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
996 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
999 assert (insn
.insn_mo
->name
);
1000 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1002 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1003 insn
.insn_opcode
= insn
.insn_mo
->match
;
1019 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1025 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1030 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1035 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1039 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1043 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1047 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1054 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1064 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1065 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1070 assert (ep
!= NULL
);
1072 * This allows macro() to pass an immediate expression for
1073 * creating short branches without creating a symbol.
1074 * Note that the expression still might come from the assembly
1075 * input, in which case the value is not checked for range nor
1076 * is a relocation entry generated (yuck).
1078 if (ep
->X_op
== O_constant
)
1080 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1084 r
= BFD_RELOC_16_PCREL_S2
;
1093 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1095 /* Use GP relative addressing if possible. */
1096 if (r
== BFD_RELOC_LO16
1097 && gp_reference (ep
))
1098 r
= BFD_RELOC_MIPS_GPREL
;
1100 append_insn (&insn
, ep
, r
);
1104 * Generate a "lui" instruction.
1107 macro_build_lui (counter
, ep
, regnum
)
1112 expressionS high_expr
;
1113 struct mips_cl_insn insn
;
1114 bfd_reloc_code_real_type r
;
1115 CONST
char *name
= "lui";
1116 CONST
char *fmt
= "t,u";
1120 if (high_expr
.X_op
== O_constant
)
1122 /* we can compute the instruction now without a relocation entry */
1123 if (high_expr
.X_add_number
& 0x8000)
1124 high_expr
.X_add_number
+= 0x10000;
1125 high_expr
.X_add_number
=
1126 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1127 r
= BFD_RELOC_UNUSED
;
1130 r
= BFD_RELOC_HI16_S
;
1133 * If the macro is about to expand into a second instruction,
1134 * print a warning if needed. We need to pass ip as a parameter
1135 * to generate a better warning message here...
1137 if (mips_warn_about_macros
&& *counter
== 1)
1138 as_warn ("Macro instruction expanded into multiple instructions");
1140 *counter
+= 1; /* bump instruction counter */
1142 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1143 assert (insn
.insn_mo
);
1144 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1145 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1147 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1148 if (r
== BFD_RELOC_UNUSED
)
1150 insn
.insn_opcode
|= high_expr
.X_add_number
;
1151 append_insn (&insn
, NULL
, r
);
1154 append_insn (&insn
, &high_expr
, r
);
1158 * Generates code to set the $at register to true (one)
1159 * if reg is less than the immediate expression.
1162 set_at (counter
, reg
, unsignedp
)
1167 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1168 macro_build (counter
, &imm_expr
,
1169 unsignedp
? "sltiu" : "slti",
1173 load_register (counter
, AT
, &imm_expr
);
1174 macro_build (counter
, NULL
,
1175 unsignedp
? "sltu" : "slt",
1176 "d,v,t", AT
, reg
, AT
);
1180 /* Warn if an expression is not a constant. */
1183 check_absolute_expr (ip
, ex
)
1184 struct mips_cl_insn
*ip
;
1187 if (ex
->X_op
!= O_constant
)
1188 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1192 * This routine generates the least number of instructions neccessary to load
1193 * an absolute expression value into a register.
1196 load_register (counter
, reg
, ep
)
1201 assert (ep
->X_op
== O_constant
);
1202 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1203 macro_build (counter
, ep
,
1204 mips_isa
< 3 ? "addiu" : "daddiu",
1206 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1207 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1208 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1209 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1210 == ~ (offsetT
) 0x7fffffff))
1212 macro_build (counter
, ep
, "lui", "t,u", reg
);
1213 if ((ep
->X_add_number
& 0xffff) != 0)
1214 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1216 else if (mips_isa
< 3)
1218 as_bad ("Number larger than 32 bits");
1219 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1224 expressionS hi32
, lo32
;
1228 hi32
.X_add_number
>>= shift
;
1229 hi32
.X_add_number
&= 0xffffffff;
1230 if ((hi32
.X_add_number
& 0x80000000) != 0)
1231 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1232 load_register (counter
, reg
, &hi32
);
1234 lo32
.X_add_number
&= 0xffffffff;
1235 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1236 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1241 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1243 mid16
.X_add_number
>>= 16;
1244 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1245 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1247 if ((lo32
.X_add_number
& 0xffff) != 0)
1248 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1254 * This routine implements the seemingly endless macro or synthesized
1255 * instructions and addressing modes in the mips assembly language. Many
1256 * of these macros are simple and are similar to each other. These could
1257 * probably be handled by some kind of table or grammer aproach instead of
1258 * this verbose method. Others are not simple macros but are more like
1259 * optimizing code generation.
1260 * One interesting optimization is when several store macros appear
1261 * consecutivly that would load AT with the upper half of the same address.
1262 * The ensuing load upper instructions are ommited. This implies some kind
1263 * of global optimization. We currently only optimize within a single macro.
1264 * For many of the load and store macros if the address is specified as a
1265 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1266 * first load register 'at' with zero and use it as the base register. The
1267 * mips assembler simply uses register $zero. Just one tiny optimization
1272 struct mips_cl_insn
*ip
;
1274 register int treg
, sreg
, dreg
, breg
;
1288 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1289 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1290 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1291 mask
= ip
->insn_mo
->mask
;
1293 expr1
.X_op
= O_constant
;
1294 expr1
.X_op_symbol
= NULL
;
1295 expr1
.X_add_symbol
= NULL
;
1296 expr1
.X_add_number
= 1;
1308 mips_emit_delays ();
1311 expr1
.X_add_number
= 8;
1312 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1314 macro_build (&icnt
, NULL
, "nop", "", 0);
1316 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1317 macro_build (&icnt
, NULL
,
1318 dbl
? "dsub" : "sub",
1319 "d,v,t", dreg
, 0, sreg
);
1342 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1344 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1347 load_register (&icnt
, AT
, &imm_expr
);
1348 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1367 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1369 if (mask
!= M_NOR_I
)
1370 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1373 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1374 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1379 load_register (&icnt
, AT
, &imm_expr
);
1380 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1397 if (imm_expr
.X_add_number
== 0)
1399 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1402 load_register (&icnt
, AT
, &imm_expr
);
1403 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1411 macro_build (&icnt
, &offset_expr
,
1412 likely
? "bgezl" : "bgez",
1418 macro_build (&icnt
, &offset_expr
,
1419 likely
? "blezl" : "blez",
1423 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1424 macro_build (&icnt
, &offset_expr
,
1425 likely
? "beql" : "beq",
1432 /* check for > max integer */
1433 maxnum
= 0x7fffffff;
1441 if (imm_expr
.X_add_number
>= maxnum
)
1444 /* result is always false */
1447 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1448 macro_build (&icnt
, NULL
, "nop", "", 0);
1452 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1453 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1457 imm_expr
.X_add_number
++;
1461 if (mask
== M_BGEL_I
)
1463 if (imm_expr
.X_add_number
== 0)
1465 macro_build (&icnt
, &offset_expr
,
1466 likely
? "bgezl" : "bgez",
1470 if (imm_expr
.X_add_number
== 1)
1472 macro_build (&icnt
, &offset_expr
,
1473 likely
? "bgtzl" : "bgtz",
1477 maxnum
= 0x7fffffff;
1485 maxnum
= - maxnum
- 1;
1486 if (imm_expr
.X_add_number
<= maxnum
)
1489 /* result is always true */
1490 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1491 macro_build (&icnt
, &offset_expr
, "b", "p");
1494 set_at (&icnt
, sreg
, 0);
1495 macro_build (&icnt
, &offset_expr
,
1496 likely
? "beql" : "beq",
1507 macro_build (&icnt
, &offset_expr
,
1508 likely
? "beql" : "beq",
1512 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1513 macro_build (&icnt
, &offset_expr
,
1514 likely
? "beql" : "beq",
1521 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1523 imm_expr
.X_add_number
++;
1527 if (mask
== M_BGEUL_I
)
1529 if (imm_expr
.X_add_number
== 0)
1531 if (imm_expr
.X_add_number
== 1)
1533 macro_build (&icnt
, &offset_expr
,
1534 likely
? "bnel" : "bne",
1538 set_at (&icnt
, sreg
, 1);
1539 macro_build (&icnt
, &offset_expr
,
1540 likely
? "beql" : "beq",
1549 macro_build (&icnt
, &offset_expr
,
1550 likely
? "bgtzl" : "bgtz",
1556 macro_build (&icnt
, &offset_expr
,
1557 likely
? "bltzl" : "bltz",
1561 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1562 macro_build (&icnt
, &offset_expr
,
1563 likely
? "bnel" : "bne",
1572 macro_build (&icnt
, &offset_expr
,
1573 likely
? "bnel" : "bne",
1579 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1580 macro_build (&icnt
, &offset_expr
,
1581 likely
? "bnel" : "bne",
1590 macro_build (&icnt
, &offset_expr
,
1591 likely
? "blezl" : "blez",
1597 macro_build (&icnt
, &offset_expr
,
1598 likely
? "bgezl" : "bgez",
1602 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1603 macro_build (&icnt
, &offset_expr
,
1604 likely
? "beql" : "beq",
1611 maxnum
= 0x7fffffff;
1619 if (imm_expr
.X_add_number
>= maxnum
)
1621 imm_expr
.X_add_number
++;
1625 if (mask
== M_BLTL_I
)
1627 if (imm_expr
.X_add_number
== 0)
1629 macro_build (&icnt
, &offset_expr
,
1630 likely
? "bltzl" : "bltz",
1634 if (imm_expr
.X_add_number
== 1)
1636 macro_build (&icnt
, &offset_expr
,
1637 likely
? "blezl" : "blez",
1641 set_at (&icnt
, sreg
, 0);
1642 macro_build (&icnt
, &offset_expr
,
1643 likely
? "bnel" : "bne",
1652 macro_build (&icnt
, &offset_expr
,
1653 likely
? "beql" : "beq",
1659 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1660 macro_build (&icnt
, &offset_expr
,
1661 likely
? "beql" : "beq",
1668 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1670 imm_expr
.X_add_number
++;
1674 if (mask
== M_BLTUL_I
)
1676 if (imm_expr
.X_add_number
== 0)
1678 if (imm_expr
.X_add_number
== 1)
1680 macro_build (&icnt
, &offset_expr
,
1681 likely
? "beql" : "beq",
1685 set_at (&icnt
, sreg
, 1);
1686 macro_build (&icnt
, &offset_expr
,
1687 likely
? "bnel" : "bne",
1696 macro_build (&icnt
, &offset_expr
,
1697 likely
? "bltzl" : "bltz",
1703 macro_build (&icnt
, &offset_expr
,
1704 likely
? "bgtzl" : "bgtz",
1708 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1709 macro_build (&icnt
, &offset_expr
,
1710 likely
? "bnel" : "bne",
1721 macro_build (&icnt
, &offset_expr
,
1722 likely
? "bnel" : "bne",
1726 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1727 macro_build (&icnt
, &offset_expr
,
1728 likely
? "bnel" : "bne",
1744 as_warn ("Divide by zero.");
1745 macro_build (&icnt
, NULL
, "break", "c", 7);
1749 mips_emit_delays ();
1751 macro_build (&icnt
, NULL
,
1752 dbl
? "ddiv" : "div",
1754 expr1
.X_add_number
= 8;
1755 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1756 macro_build (&icnt
, NULL
, "nop", "", 0);
1757 macro_build (&icnt
, NULL
, "break", "c", 7);
1758 expr1
.X_add_number
= -1;
1759 macro_build (&icnt
, &expr1
,
1760 dbl
? "daddiu" : "addiu",
1762 expr1
.X_add_number
= dbl
? 20 : 16;
1763 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1766 expr1
.X_add_number
= 1;
1767 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1768 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1772 expr1
.X_add_number
= 0x80000000;
1773 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1775 expr1
.X_add_number
= 8;
1776 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1777 macro_build (&icnt
, NULL
, "nop", "", 0);
1778 macro_build (&icnt
, NULL
, "break", "c", 6);
1780 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1819 if (imm_expr
.X_add_number
== 0)
1821 as_warn ("Divide by zero.");
1822 macro_build (&icnt
, NULL
, "break", "c", 7);
1825 if (imm_expr
.X_add_number
== 1)
1827 if (strcmp (s2
, "mflo") == 0)
1828 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1830 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1833 if (imm_expr
.X_add_number
== -1
1834 && s
[strlen (s
) - 1] != 'u')
1836 if (strcmp (s2
, "mflo") == 0)
1839 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1841 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1844 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1848 load_register (&icnt
, AT
, &imm_expr
);
1849 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
1850 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1869 mips_emit_delays ();
1871 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, treg
);
1872 expr1
.X_add_number
= 8;
1873 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1874 macro_build (&icnt
, NULL
, "nop", "", 0);
1875 macro_build (&icnt
, NULL
, "break", "c", 7);
1877 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1881 if (offset_expr
.X_op
== O_constant
)
1883 load_register (&icnt
, treg
, &offset_expr
);
1886 if (gp_reference (&offset_expr
))
1887 macro_build (&icnt
, &offset_expr
,
1888 mips_isa
< 3 ? "addiu" : "daddiu",
1892 /* FIXME: This won't work for a 64 bit address. */
1893 macro_build_lui (&icnt
, &offset_expr
, treg
);
1894 macro_build (&icnt
, &offset_expr
,
1895 mips_isa
< 3 ? "addiu" : "daddiu",
1896 "t,r,j", treg
, treg
);
1901 tempreg
= (breg
== treg
) ? AT
: treg
;
1902 if (offset_expr
.X_op
== O_constant
)
1903 load_register (&icnt
, tempreg
, &offset_expr
);
1904 else if (gp_reference (&offset_expr
))
1905 macro_build (&icnt
, &offset_expr
,
1906 mips_isa
< 3 ? "addiu" : "daddiu",
1907 "t,r,j", tempreg
, GP
);
1910 /* FIXME: This won't work for a 64 bit address. */
1911 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1912 macro_build (&icnt
, &offset_expr
,
1913 mips_isa
< 3 ? "addiu" : "daddiu",
1914 "t,r,j", tempreg
, tempreg
);
1917 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
1987 if (breg
== treg
|| coproc
)
2056 if (mask
== M_LWC1_AB
2057 || mask
== M_SWC1_AB
2059 || mask
== M_LDC1_AB
2060 || mask
== M_SDC1_AB
)
2066 if (gp_reference (&offset_expr
))
2070 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2073 macro_build (&icnt
, (expressionS
*) NULL
,
2074 mips_isa
< 3 ? "addu" : "daddu",
2075 "d,v,t", tempreg
, breg
, GP
);
2079 /* FIXME: This won't work for a 64 bit address. */
2080 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2082 macro_build (&icnt
, NULL
,
2083 mips_isa
< 3 ? "addu" : "daddu",
2084 "d,v,t", tempreg
, tempreg
, breg
);
2086 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2093 load_register (&icnt
, treg
, &imm_expr
);
2098 lw $v0,%lo(foo)($at)
2099 lw $v1,%lo(foo+4)($at)
2104 /* FIXME: This won't work for a 64 bit address. */
2105 macro_build_lui (&icnt
, &offset_expr
, AT
);
2107 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2110 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2111 offset_expr
.X_add_number
+= 4;
2112 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2117 /* Load a floating point number from the .lit8 section. */
2120 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2126 /* Even on a big endian machine $fn comes before $fn+1. We have
2127 to adjust when loading from memory. */
2128 assert (mips_isa
< 2);
2129 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2130 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2132 offset_expr
.X_add_number
+= 4;
2133 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2134 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2140 * The MIPS assembler seems to check for X_add_number not
2141 * being double aligned and generating:
2144 * addiu at,at,%lo(foo+1)
2147 * But, the resulting address is the same after relocation so why
2148 * generate the extra instruction?
2150 if (gp_reference (&offset_expr
))
2156 macro_build (&icnt
, &offset_expr
,
2157 mips_isa
< 3 ? "addu" : "daddu",
2158 "d,v,t", AT
, breg
, GP
);
2164 /* FIXME: This won't work for a 64 bit address. */
2165 macro_build_lui (&icnt
, &offset_expr
, AT
);
2167 macro_build (&icnt
, NULL
,
2168 mips_isa
< 3 ? "addu" : "daddu",
2169 "d,v,t", AT
, AT
, breg
);
2173 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2176 /* Even on a big endian machine $fn comes before $fn+1. We
2177 have to adjust when loading from memory. */
2178 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2179 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2181 offset_expr
.X_add_number
+= 4;
2182 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2183 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2196 assert (mips_isa
< 3);
2197 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2198 offset_expr
.X_add_number
+= 4;
2199 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2222 if (gp_reference (&offset_expr
))
2230 macro_build (&icnt
, (expressionS
*) NULL
,
2231 mips_isa
< 3 ? "addu" : "daddu",
2232 "d,v,t", tempreg
, breg
, GP
);
2236 /* FIXME: This won't work for a 64 bit address. */
2237 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2239 macro_build (&icnt
, NULL
,
2240 mips_isa
< 3 ? "addu" : "daddu",
2241 "d,v,t", tempreg
, tempreg
, breg
);
2244 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2247 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2248 offset_expr
.X_add_number
+= 4;
2249 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2258 macro_build (&icnt
, NULL
,
2259 dbl
? "dmultu" : "multu",
2261 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2267 /* The MIPS assembler some times generates shifts and adds. I'm
2268 not trying to be that fancy. GCC should do this for us
2270 load_register (&icnt
, AT
, &imm_expr
);
2271 macro_build (&icnt
, NULL
,
2272 dbl
? "dmult" : "mult",
2274 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2280 mips_emit_delays ();
2282 macro_build (&icnt
, NULL
,
2283 dbl
? "dmult" : "mult",
2285 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2286 macro_build (&icnt
, NULL
,
2287 dbl
? "dsra32" : "sra",
2288 "d,w,<", dreg
, dreg
, 31);
2289 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2290 expr1
.X_add_number
= 8;
2291 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2292 macro_build (&icnt
, NULL
, "nop", "", 0);
2293 macro_build (&icnt
, NULL
, "break", "c", 6);
2295 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2301 mips_emit_delays ();
2303 macro_build (&icnt
, NULL
,
2304 dbl
? "dmultu" : "multu",
2306 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2307 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2308 expr1
.X_add_number
= 8;
2309 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2310 macro_build (&icnt
, NULL
, "nop", "", 0);
2311 macro_build (&icnt
, NULL
, "break", "c", 6);
2316 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2317 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2318 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2319 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2323 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2324 imm_expr
.X_add_number
& 0x1f);
2325 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2326 (0 - imm_expr
.X_add_number
) & 0x1f);
2327 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2331 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2332 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2333 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2334 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2338 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2339 imm_expr
.X_add_number
& 0x1f);
2340 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2341 (0 - imm_expr
.X_add_number
) & 0x1f);
2342 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2346 assert (mips_isa
< 2);
2347 /* Even on a big endian machine $fn comes before $fn+1. We have
2348 to adjust when storing to memory. */
2349 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2350 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2352 offset_expr
.X_add_number
+= 4;
2353 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2354 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2359 if (gp_reference (&offset_expr
))
2365 macro_build (&icnt
, (expressionS
*) NULL
,
2366 mips_isa
< 3 ? "addu" : "daddu",
2367 "d,v,t", AT
, breg
, GP
);
2373 /* FIXME: This won't work for a 64 bit address. */
2374 macro_build_lui (&icnt
, &offset_expr
, AT
);
2376 macro_build (&icnt
, NULL
,
2377 mips_isa
< 3 ? "addu" : "daddu",
2378 "d,v,t", AT
, AT
, breg
);
2382 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2385 /* Even on a big endian machine $fn comes before $fn+1. We
2386 have to adjust when storing to memory. */
2387 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2388 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2390 offset_expr
.X_add_number
+= 4;
2391 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2392 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2401 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2403 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2406 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2407 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2412 if (imm_expr
.X_add_number
== 0)
2414 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2419 as_warn ("Instruction %s: result is always false",
2421 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2424 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2426 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2429 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2431 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2432 macro_build (&icnt
, &imm_expr
,
2433 mips_isa
< 3 ? "addiu" : "daddiu",
2434 "t,r,j", dreg
, sreg
);
2439 load_register (&icnt
, AT
, &imm_expr
);
2440 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2443 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2448 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2454 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2455 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2458 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2460 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2462 macro_build (&icnt
, &expr1
,
2463 mask
== M_SGE_I
? "slti" : "sltiu",
2464 "t,r,j", dreg
, sreg
);
2469 load_register (&icnt
, AT
, &imm_expr
);
2470 macro_build (&icnt
, NULL
,
2471 mask
== M_SGE_I
? "slt" : "sltu",
2472 "d,v,t", dreg
, sreg
, AT
);
2475 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2480 case M_SGT
: /* sreg > treg <==> treg < sreg */
2486 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2489 case M_SGT_I
: /* sreg > I <==> I < sreg */
2495 load_register (&icnt
, AT
, &imm_expr
);
2496 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2499 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2505 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2506 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2509 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2515 load_register (&icnt
, AT
, &imm_expr
);
2516 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2517 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2521 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2523 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2526 load_register (&icnt
, AT
, &imm_expr
);
2527 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2531 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2533 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2536 load_register (&icnt
, AT
, &imm_expr
);
2537 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2542 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2544 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2547 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2548 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2553 if (imm_expr
.X_add_number
== 0)
2555 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2560 as_warn ("Instruction %s: result is always true",
2562 macro_build (&icnt
, &expr1
,
2563 mips_isa
< 3 ? "addiu" : "daddiu",
2567 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2569 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2572 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2574 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2575 macro_build (&icnt
, &imm_expr
,
2576 mips_isa
< 3 ? "addiu" : "daddiu",
2577 "t,r,j", dreg
, sreg
);
2582 load_register (&icnt
, AT
, &imm_expr
);
2583 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2586 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2594 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2596 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2597 macro_build (&icnt
, &imm_expr
,
2598 dbl
? "daddi" : "addi",
2599 "t,r,j", dreg
, sreg
);
2602 load_register (&icnt
, AT
, &imm_expr
);
2603 macro_build (&icnt
, NULL
,
2604 dbl
? "dsub" : "sub",
2605 "d,v,t", dreg
, sreg
, AT
);
2611 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2613 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2614 macro_build (&icnt
, &imm_expr
,
2615 dbl
? "daddiu" : "addiu",
2616 "t,r,j", dreg
, sreg
);
2619 load_register (&icnt
, AT
, &imm_expr
);
2620 macro_build (&icnt
, NULL
,
2621 dbl
? "dsubu" : "subu",
2622 "d,v,t", dreg
, sreg
, AT
);
2643 load_register (&icnt
, AT
, &imm_expr
);
2644 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2649 assert (mips_isa
< 2);
2650 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2651 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2654 * Is the double cfc1 instruction a bug in the mips assembler;
2655 * or is there a reason for it?
2657 mips_emit_delays ();
2659 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2660 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2661 macro_build (&icnt
, NULL
, "nop", "");
2662 expr1
.X_add_number
= 3;
2663 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2664 expr1
.X_add_number
= 2;
2665 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2666 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2667 macro_build (&icnt
, NULL
, "nop", "");
2668 macro_build (&icnt
, NULL
,
2669 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2670 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2671 macro_build (&icnt
, NULL
, "nop", "");
2681 /* avoid load delay */
2682 offset_expr
.X_add_number
+= 1;
2683 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2684 offset_expr
.X_add_number
-= 1;
2685 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2686 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2687 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2691 /* does this work on a big endian machine? */
2692 offset_expr
.X_add_number
+= 3;
2693 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2694 offset_expr
.X_add_number
-= 3;
2695 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2701 if (offset_expr
.X_op
== O_constant
)
2702 load_register (&icnt
, AT
, &offset_expr
);
2703 else if (gp_reference (&offset_expr
))
2704 macro_build (&icnt
, &offset_expr
,
2705 mips_isa
< 3 ? "addiu" : "daddiu",
2709 /* FIXME: This won't work for a 64 bit address. */
2710 macro_build_lui (&icnt
, &offset_expr
, AT
);
2711 macro_build (&icnt
, &offset_expr
,
2712 mips_isa
< 3 ? "addiu" : "daddiu",
2715 if (mask
== M_ULW_A
)
2717 expr1
.X_add_number
= 3;
2718 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2719 imm_expr
.X_add_number
= 0;
2720 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2724 macro_build (&icnt
, &expr1
,
2725 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2726 imm_expr
.X_add_number
= 0;
2727 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2728 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2729 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2734 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2735 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2736 offset_expr
.X_add_number
+= 1;
2737 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2741 offset_expr
.X_add_number
+= 3;
2742 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2743 offset_expr
.X_add_number
-= 3;
2744 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2749 if (offset_expr
.X_op
== O_constant
)
2750 load_register (&icnt
, AT
, &offset_expr
);
2751 else if (gp_reference (&offset_expr
))
2752 macro_build (&icnt
, &offset_expr
,
2753 mips_isa
< 3 ? "addiu" : "daddiu",
2757 /* FIXME: This won't work for a 64 bit address. */
2758 macro_build_lui (&icnt
, &offset_expr
, AT
);
2759 macro_build (&icnt
, &offset_expr
,
2760 mips_isa
< 3 ? "addiu" : "daddiu",
2763 if (mask
== M_USW_A
)
2765 expr1
.X_add_number
= 3;
2766 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2767 expr1
.X_add_number
= 0;
2768 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2772 expr1
.X_add_number
= 0;
2773 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2774 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2775 expr1
.X_add_number
= 1;
2776 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2777 expr1
.X_add_number
= 0;
2778 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2779 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2780 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2785 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2789 as_warn ("Macro used $at after \".set noat\"");
2794 This routine assembles an instruction into its binary format. As a side
2795 effect it sets one of the global variables imm_reloc or offset_reloc to the
2796 type of relocation to do if one of the operands is an address expression.
2801 struct mips_cl_insn
*ip
;
2806 struct mips_opcode
*insn
;
2809 unsigned int lastregno
= 0;
2814 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2826 as_warn ("Unknown opcode: `%s'", str
);
2829 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2831 as_warn ("`%s' not in hash table.", str
);
2832 insn_error
= "ERROR: Unrecognized opcode";
2840 assert (strcmp (insn
->name
, str
) == 0);
2842 if (insn
->pinfo
== INSN_MACRO
)
2843 insn_isa
= insn
->match
;
2844 else if (insn
->pinfo
& INSN_ISA2
)
2846 else if (insn
->pinfo
& INSN_ISA3
)
2851 if (insn_isa
> mips_isa
)
2853 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2854 && strcmp (insn
->name
, insn
[1].name
) == 0)
2859 insn_error
= "ERROR: instruction not supported on this processor";
2864 ip
->insn_opcode
= insn
->match
;
2865 for (args
= insn
->args
;; ++args
)
2871 case '\0': /* end of args */
2884 ip
->insn_opcode
|= lastregno
<< 21;
2889 ip
->insn_opcode
|= lastregno
<< 16;
2893 ip
->insn_opcode
|= lastregno
<< 11;
2899 /* handle optional base register.
2900 Either the base register is omitted or
2901 we must have a left paren. */
2902 /* this is dependent on the next operand specifier
2903 is a 'b' for base register */
2904 assert (args
[1] == 'b');
2908 case ')': /* these must match exactly */
2913 case '<': /* must be at least one digit */
2915 * According to the manual, if the shift amount is greater
2916 * than 31 or less than 0 the the shift amount should be
2917 * mod 32. In reality the mips assembler issues an error.
2918 * We issue a warning and do the mod.
2920 my_getExpression (&imm_expr
, s
);
2921 check_absolute_expr (ip
, &imm_expr
);
2922 if ((unsigned long) imm_expr
.X_add_number
> 31)
2924 as_warn ("Improper shift amount (%d)",
2925 imm_expr
.X_add_number
);
2926 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2928 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2929 imm_expr
.X_op
= O_absent
;
2933 case 'c': /* break code */
2934 my_getExpression (&imm_expr
, s
);
2935 check_absolute_expr (ip
, &imm_expr
);
2936 if ((unsigned) imm_expr
.X_add_number
> 1023)
2937 as_warn ("Illegal break code (%d)", imm_expr
.X_add_number
);
2938 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2939 imm_expr
.X_op
= O_absent
;
2943 case 'B': /* syscall code */
2944 my_getExpression (&imm_expr
, s
);
2945 check_absolute_expr (ip
, &imm_expr
);
2946 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2947 as_warn ("Illegal syscall code (%d)", imm_expr
.X_add_number
);
2948 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2949 imm_expr
.X_op
= O_absent
;
2953 case 'C': /* Coprocessor code */
2954 my_getExpression (&imm_expr
, s
);
2955 check_absolute_expr (ip
, &imm_expr
);
2956 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
2958 as_warn ("Coproccesor code > 25 bits (%d)",
2959 imm_expr
.X_add_number
);
2960 imm_expr
.X_add_number
&= ((1<<25) - 1);
2962 ip
->insn_opcode
|= imm_expr
.X_add_number
;
2963 imm_expr
.X_op
= O_absent
;
2967 case 'b': /* base register */
2968 case 'd': /* destination register */
2969 case 's': /* source register */
2970 case 't': /* target register */
2971 case 'r': /* both target and source */
2972 case 'v': /* both dest and source */
2973 case 'w': /* both dest and target */
2974 case 'E': /* coprocessor target register */
2975 case 'G': /* coprocessor destination register */
2976 case 'x': /* ignore register name */
2990 while (isdigit (*s
));
2992 as_bad ("Invalid register number (%d)", regno
);
2994 else if (*args
!= 'E' && *args
!= 'G')
2996 if (s
[1] == 'f' && s
[2] == 'p')
3001 else if (s
[1] == 's' && s
[2] == 'p')
3006 else if (s
[1] == 'g' && s
[2] == 'p')
3011 else if (s
[1] == 'a' && s
[2] == 't')
3018 if (regno
== AT
&& ! mips_noat
)
3019 as_warn ("Used $at without \".set noat\"");
3026 if (c
== 'r' || c
== 'v' || c
== 'w')
3039 ip
->insn_opcode
|= regno
<< 21;
3043 ip
->insn_opcode
|= regno
<< 11;
3048 ip
->insn_opcode
|= regno
<< 16;
3051 /* This case exists because on the r3000 trunc
3052 expands into a macro which requires a gp
3053 register. On the r6000 or r4000 it is
3054 assembled into a single instruction which
3055 ignores the register. Thus the insn version
3056 is MIPS_ISA2 and uses 'x', and the macro
3057 version is MIPS_ISA1 and uses 't'. */
3068 ip
->insn_opcode
|= lastregno
<< 21;
3071 ip
->insn_opcode
|= lastregno
<< 16;
3076 case 'D': /* floating point destination register */
3077 case 'S': /* floating point source register */
3078 case 'T': /* floating point target register */
3082 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3092 while (isdigit (*s
));
3095 as_bad ("Invalid float register number (%d)", regno
);
3098 !(strcmp (str
, "mtc1") == 0 ||
3099 strcmp (str
, "mfc1") == 0 ||
3100 strcmp (str
, "lwc1") == 0 ||
3101 strcmp (str
, "swc1") == 0))
3102 as_warn ("Float register should be even, was %d",
3110 if (c
== 'V' || c
== 'W')
3120 ip
->insn_opcode
|= regno
<< 6;
3124 ip
->insn_opcode
|= regno
<< 11;
3128 ip
->insn_opcode
|= regno
<< 16;
3136 ip
->insn_opcode
|= lastregno
<< 11;
3139 ip
->insn_opcode
|= lastregno
<< 16;
3145 my_getExpression (&imm_expr
, s
);
3146 check_absolute_expr (ip
, &imm_expr
);
3151 my_getExpression (&offset_expr
, s
);
3152 imm_reloc
= BFD_RELOC_32
;
3164 unsigned char temp
[8];
3170 /* These only appear as the last operand in an
3171 instruction, and every instruction that accepts
3172 them in any variant accepts them in all variants.
3173 This means we don't have to worry about backing out
3174 any changes if the instruction does not match.
3176 The difference between them is the size of the
3177 floating point constant and where it goes. For 'F'
3178 and 'L' the constant is 64 bits; for 'f' and 'l' it
3179 is 32 bits. Where the constant is placed is based
3180 on how the MIPS assembler does things:
3183 f -- immediate value
3187 f64
= *args
== 'F' || *args
== 'L';
3189 save_in
= input_line_pointer
;
3190 input_line_pointer
= s
;
3191 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &length
);
3192 s
= input_line_pointer
;
3193 input_line_pointer
= save_in
;
3194 if (err
!= NULL
&& *err
!= '\0')
3196 as_bad ("Bad floating point constant: %s", err
);
3197 memset (temp
, '\0', sizeof temp
);
3198 length
= f64
? 8 : 4;
3201 assert (length
== (f64
? 8 : 4));
3205 imm_expr
.X_op
= O_constant
;
3206 if (byte_order
== LITTLE_ENDIAN
)
3207 imm_expr
.X_add_number
=
3208 (((((((int) temp
[3] << 8)
3213 imm_expr
.X_add_number
=
3214 (((((((int) temp
[0] << 8)
3221 /* Switch to the right section. */
3223 subseg
= now_subseg
;
3227 subseg_new (".rdata", (subsegT
) 0);
3230 subseg_new (".lit8", (subsegT
) 0);
3233 subseg_new (".lit4", (subsegT
) 0);
3237 as_bad ("Can't use floating point insn in this section");
3239 /* Set the argument to the current address in the
3241 offset_expr
.X_op
= O_symbol
;
3242 offset_expr
.X_add_symbol
=
3243 symbol_new ("L0\001", now_seg
,
3244 (valueT
) frag_now_fix (), frag_now
);
3245 offset_expr
.X_add_number
= 0;
3247 /* Put the floating point number into the section. */
3248 p
= frag_more (length
);
3249 memcpy (p
, temp
, length
);
3251 /* Switch back to the original section. */
3252 subseg_set (seg
, subseg
);
3257 case 'i': /* 16 bit unsigned immediate */
3258 case 'j': /* 16 bit signed immediate */
3259 imm_reloc
= BFD_RELOC_LO16
;
3260 c
= my_getSmallExpression (&imm_expr
, s
);
3265 if (imm_expr
.X_op
== O_constant
)
3266 imm_expr
.X_add_number
=
3267 (imm_expr
.X_add_number
>> 16) & 0xffff;
3269 imm_reloc
= BFD_RELOC_HI16_S
;
3271 imm_reloc
= BFD_RELOC_HI16
;
3275 check_absolute_expr (ip
, &imm_expr
);
3278 if (imm_expr
.X_add_number
< 0
3279 || imm_expr
.X_add_number
>= 0x10000)
3281 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3282 !strcmp (insn
->name
, insn
[1].name
))
3284 as_bad ("16 bit expression not in range 0..65535");
3289 if (imm_expr
.X_add_number
< -0x8000 ||
3290 imm_expr
.X_add_number
>= 0x8000)
3292 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3293 !strcmp (insn
->name
, insn
[1].name
))
3295 as_bad ("16 bit expression not in range -32768..32767");
3301 case 'o': /* 16 bit offset */
3302 c
= my_getSmallExpression (&offset_expr
, s
);
3304 * If this value won't fit into a 16 bit offset, then
3305 * go find a macro that will generate the 32 bit offset
3308 if (offset_expr
.X_op
!= O_constant
3309 || offset_expr
.X_add_number
>= 0x8000
3310 || offset_expr
.X_add_number
< -0x8000)
3313 offset_reloc
= BFD_RELOC_LO16
;
3314 if (c
== 'h' || c
== 'H')
3316 assert (offset_expr
.X_op
== O_constant
);
3317 offset_expr
.X_add_number
=
3318 (offset_expr
.X_add_number
>> 16) & 0xffff;
3323 case 'p': /* pc relative offset */
3324 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3325 my_getExpression (&offset_expr
, s
);
3329 case 'u': /* upper 16 bits */
3330 c
= my_getSmallExpression (&imm_expr
, s
);
3331 if (imm_expr
.X_op
!= O_constant
3332 || imm_expr
.X_add_number
< 0
3333 || imm_expr
.X_add_number
>= 0x10000)
3334 as_bad ("lui expression not in range 0..65535");
3335 imm_reloc
= BFD_RELOC_LO16
;
3340 if (imm_expr
.X_op
== O_constant
)
3341 imm_expr
.X_add_number
=
3342 (imm_expr
.X_add_number
>> 16) & 0xffff;
3344 imm_reloc
= BFD_RELOC_HI16_S
;
3346 imm_reloc
= BFD_RELOC_HI16
;
3352 case 'a': /* 26 bit address */
3353 my_getExpression (&offset_expr
, s
);
3355 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3359 fprintf (stderr
, "bad char = '%c'\n", *args
);
3364 /* Args don't match. */
3365 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3366 !strcmp (insn
->name
, insn
[1].name
))
3372 insn_error
= "ERROR: Illegal operands";
3381 my_getSmallExpression (ep
, str
)
3392 ((str
[1] == 'h' && str
[2] == 'i')
3393 || (str
[1] == 'H' && str
[2] == 'I')
3394 || (str
[1] == 'l' && str
[2] == 'o'))
3406 * A small expression may be followed by a base register.
3407 * Scan to the end of this operand, and then back over a possible
3408 * base register. Then scan the small expression up to that
3409 * point. (Based on code in sparc.c...)
3411 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3413 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3415 if (isdigit (sp
[-2]))
3417 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3419 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3425 else if (sp
- 5 >= str
3428 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3429 || (sp
[-3] == 's' && sp
[-2] == 'p')
3430 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3431 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3437 /* no expression means zero offset */
3440 /* %xx(reg) is an error */
3441 ep
->X_op
= O_absent
;
3446 ep
->X_op
= O_absent
;
3449 ep
->X_add_symbol
= NULL
;
3450 ep
->X_op_symbol
= NULL
;
3451 ep
->X_add_number
= 0;
3456 my_getExpression (ep
, str
);
3463 my_getExpression (ep
, str
);
3464 return c
; /* => %hi or %lo encountered */
3468 my_getExpression (ep
, str
)
3474 save_in
= input_line_pointer
;
3475 input_line_pointer
= str
;
3477 expr_end
= input_line_pointer
;
3478 input_line_pointer
= save_in
;
3481 /* Turn a string in input_line_pointer into a floating point constant
3482 of type type, and store the appropriate bytes in *litP. The number
3483 of LITTLENUMS emitted is stored in *sizeP . An error message is
3484 returned, or NULL on OK. */
3487 md_atof (type
, litP
, sizeP
)
3493 LITTLENUM_TYPE words
[4];
3509 return "bad call to md_atof";
3512 t
= atof_ieee (input_line_pointer
, type
, words
);
3514 input_line_pointer
= t
;
3518 if (byte_order
== LITTLE_ENDIAN
)
3520 for (i
= prec
- 1; i
>= 0; i
--)
3522 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3528 for (i
= 0; i
< prec
; i
++)
3530 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3539 md_number_to_chars (buf
, val
, n
)
3587 md_number_to_chars (buf
, hi
, 4);
3612 md_parse_option (argP
, cntP
, vecP
)
3617 /* Accept -nocpp but ignore it. */
3618 if (strcmp (*argP
, "nocpp") == 0)
3624 if (strcmp (*argP
, "EL") == 0
3625 || strcmp (*argP
, "EB") == 0)
3627 /* FIXME: This breaks -L -EL. */
3635 if ((*argP
)[1] == '0')
3644 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3649 if (strncmp (*argP
, "mips", 4) == 0)
3651 mips_isa
= atol (*argP
+ 4);
3654 else if (mips_isa
< 1 || mips_isa
> 3)
3656 as_bad ("-mips%d not supported", mips_isa
);
3663 if (strncmp (*argP
, "mcpu=", 5) == 0)
3667 /* Identify the processor type */
3669 if (strcmp (p
, "default") == 0
3670 || strcmp (p
, "DEFAULT") == 0)
3674 if (*p
== 'r' || *p
== 'R')
3681 if (strcmp (p
, "2000") == 0
3682 || strcmp (p
, "2k") == 0
3683 || strcmp (p
, "2K") == 0)
3688 if (strcmp (p
, "3000") == 0
3689 || strcmp (p
, "3k") == 0
3690 || strcmp (p
, "3K") == 0)
3695 if (strcmp (p
, "4000") == 0
3696 || strcmp (p
, "4k") == 0
3697 || strcmp (p
, "4K") == 0)
3702 if (strcmp (p
, "6000") == 0
3703 || strcmp (p
, "6k") == 0
3704 || strcmp (p
, "6K") == 0)
3711 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3724 if ((*argP
)[1] != '\0')
3725 g_switch_value
= atoi (*argP
+ 1);
3728 **vecP
= (char *) NULL
;
3731 g_switch_value
= atoi (**vecP
);
3734 as_warn ("Number expected after -G");
3740 return 1; /* pretend you parsed the character */
3744 md_pcrel_from (fixP
)
3747 /* return the address of the delay slot */
3748 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3752 md_apply_fix (fixP
, valueP
)
3759 assert (fixP
->fx_size
== 4);
3762 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3764 switch (fixP
->fx_r_type
)
3767 case BFD_RELOC_MIPS_JMP
:
3768 case BFD_RELOC_HI16
:
3769 case BFD_RELOC_HI16_S
:
3770 case BFD_RELOC_LO16
:
3771 case BFD_RELOC_MIPS_GPREL
:
3772 /* Nothing needed to do. The value comes from the reloc entry */
3775 case BFD_RELOC_16_PCREL_S2
:
3777 * We need to save the bits in the instruction since fixup_segment()
3778 * might be deleting the relocation entry (i.e., a branch within
3779 * the current segment).
3782 as_warn ("Branch to odd address (%x)", value
);
3784 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3785 as_bad ("Relocation overflow");
3787 /* update old instruction data */
3788 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3792 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3796 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3803 insn
|= value
& 0xFFFF;
3804 md_number_to_chars ((char *) buf
, insn
, 4);
3818 const struct mips_opcode
*p
;
3819 int treg
, sreg
, dreg
, shamt
;
3824 for (i
= 0; i
< NUMOPCODES
; ++i
)
3826 p
= &mips_opcodes
[i
];
3827 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3829 printf ("%08lx %s\t", oc
, p
->name
);
3830 treg
= (oc
>> 16) & 0x1f;
3831 sreg
= (oc
>> 21) & 0x1f;
3832 dreg
= (oc
>> 11) & 0x1f;
3833 shamt
= (oc
>> 6) & 0x1f;
3835 for (args
= p
->args
;; ++args
)
3846 printf ("%c", *args
);
3850 assert (treg
== sreg
);
3851 printf ("$%d,$%d", treg
, sreg
);
3856 printf ("$%d", dreg
);
3861 printf ("$%d", treg
);
3866 printf ("$%d", sreg
);
3870 printf ("0x%08lx", oc
& 0x1ffffff);
3881 printf ("$%d", shamt
);
3892 printf ("%08lx UNDEFINED\n", oc
);
3903 name
= input_line_pointer
;
3904 c
= get_symbol_end ();
3905 p
= (symbolS
*) symbol_find_or_make (name
);
3906 *input_line_pointer
= c
;
3910 /* Align the current frag to a given power of two. The MIPS assembler
3911 also automatically adjusts any preceding label. */
3914 mips_align (to
, fill
)
3918 mips_emit_delays ();
3919 frag_align (to
, fill
);
3920 record_alignment (now_seg
, to
);
3921 if (insn_label
!= NULL
)
3923 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3924 insn_label
->sy_frag
= frag_now
;
3925 S_SET_VALUE (insn_label
, frag_now_fix ());
3929 /* Align to a given power of two. .align 0 turns off the automatic
3930 alignment used by the data creating pseudo-ops. */
3937 register long temp_fill
;
3938 long max_alignment
= 15;
3942 o Note that the assembler pulls down any immediately preceeding label
3943 to the aligned address.
3944 o It's not documented but auto alignment is reinstated by
3945 a .align pseudo instruction.
3946 o Note also that after auto alignment is turned off the mips assembler
3947 issues an error on attempt to assemble an improperly aligned data item.
3952 temp
= get_absolute_expression ();
3953 if (temp
> max_alignment
)
3954 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
3957 as_warn ("Alignment negative: 0 assumed.");
3960 if (*input_line_pointer
== ',')
3962 input_line_pointer
++;
3963 temp_fill
= get_absolute_expression ();
3970 mips_align (temp
, (int) temp_fill
);
3977 demand_empty_rest_of_line ();
3980 /* Handle .ascii and .asciiz. This just calls stringer and forgets
3981 that there was a previous instruction. */
3984 s_stringer (append_zero
)
3987 mips_emit_delays ();
3988 stringer (append_zero
);
3997 mips_emit_delays ();
4006 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4007 demand_empty_rest_of_line ();
4016 #ifdef BFD_ASSEMBLER
4017 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4019 subseg_new (bss_section
, (subsegT
) get_absolute_expression ());
4021 demand_empty_rest_of_line ();
4025 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4026 demand_empty_rest_of_line ();
4029 as_bad ("Global pointers not supported; recompile -G 0");
4030 demand_empty_rest_of_line ();
4041 mips_emit_delays ();
4042 if (log_size
> 0 && auto_align
)
4043 mips_align (log_size
, 0);
4044 cons (1 << log_size
);
4051 as_fatal ("Encountered `.err', aborting assembly");
4061 symbolP
= get_symbol ();
4062 if (*input_line_pointer
== ',')
4063 input_line_pointer
++;
4064 size
= get_absolute_expression ();
4065 S_SET_VALUE (symbolP
, size
);
4066 S_SET_EXTERNAL (symbolP
);
4069 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4070 so we use an additional ECOFF specific field. */
4071 symbolP
->ecoff_undefined
= 1;
4079 mips_emit_delays ();
4094 if (strcmp (input_line_pointer
, "O1") != 0
4095 && strcmp (input_line_pointer
, "O2") != 0)
4096 as_warn ("Unrecognized option");
4097 demand_empty_rest_of_line ();
4104 char *name
= input_line_pointer
, ch
;
4106 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4107 input_line_pointer
++;
4108 ch
= *input_line_pointer
;
4109 *input_line_pointer
= '\0';
4111 if (strcmp (name
, "reorder") == 0)
4115 prev_insn_unreordered
= 1;
4116 prev_prev_insn_unreordered
= 1;
4120 else if (strcmp (name
, "noreorder") == 0)
4122 mips_emit_delays ();
4125 else if (strcmp (name
, "at") == 0)
4129 else if (strcmp (name
, "noat") == 0)
4133 else if (strcmp (name
, "macro") == 0)
4135 mips_warn_about_macros
= 0;
4137 else if (strcmp (name
, "nomacro") == 0)
4139 if (mips_noreorder
== 0)
4140 as_bad ("`noreorder' must be set before `nomacro'");
4141 mips_warn_about_macros
= 1;
4143 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4147 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4151 else if (strcmp (name
, "bopt") == 0)
4155 else if (strcmp (name
, "nobopt") == 0)
4161 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4163 *input_line_pointer
= ch
;
4164 demand_empty_rest_of_line ();
4167 /* The same as the usual .space directive, except that we have to
4168 forget about any previous instruction. */
4171 s_mips_space (param
)
4174 mips_emit_delays ();
4184 if (*input_line_pointer
++ != '$')
4186 as_warn ("expected `$'");
4189 if (isdigit ((unsigned char) *input_line_pointer
))
4191 reg
= get_absolute_expression ();
4192 if (reg
< 0 || reg
>= 32)
4194 as_warn ("Bad register number");
4200 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4202 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4204 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4206 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4210 as_warn ("Unrecognized register name");
4213 input_line_pointer
+= 2;
4219 * Translate internal representation of relocation info to BFD target format.
4222 tc_gen_reloc (section
, fixp
)
4228 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4229 assert (reloc
!= 0);
4231 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4232 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4233 if (fixp
->fx_pcrel
== 0)
4234 reloc
->addend
= fixp
->fx_addnumber
;
4239 reloc
->addend
= -reloc
->address
;
4241 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4242 assert (reloc
->howto
!= 0);
4247 /* should never be called */
4249 md_section_align (seg
, addr
)
4253 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4255 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4259 md_estimate_size_before_relax (fragP
, segtype
)
4263 as_fatal ("md_estimate_size_before_relax");
4265 } /* md_estimate_size_before_relax() */
4267 /* This function is called whenever a label is defined. It is used
4268 when handling branch delays; if a branch has a label, we assume we
4272 mips_define_label (sym
)
4280 /* These functions should really be defined by the object file format,
4281 since they are related to debugging information. However, this
4282 code has to work for the a.out format, which does not define them,
4283 so we provide simple versions here. These don't actually generate
4284 any debugging information, but they do simple checking and someday
4285 somebody may make them useful. */
4289 struct loc
*loc_next
;
4290 unsigned long loc_fileno
;
4291 unsigned long loc_lineno
;
4292 unsigned long loc_offset
;
4293 unsigned short loc_delta
;
4294 unsigned short loc_count
;
4303 struct proc
*proc_next
;
4304 struct symbol
*proc_isym
;
4305 struct symbol
*proc_end
;
4306 unsigned long proc_reg_mask
;
4307 unsigned long proc_reg_offset
;
4308 unsigned long proc_fpreg_mask
;
4309 unsigned long proc_fpreg_offset
;
4310 unsigned long proc_frameoffset
;
4311 unsigned long proc_framereg
;
4312 unsigned long proc_pcreg
;
4314 struct file
*proc_file
;
4321 struct file
*file_next
;
4322 unsigned long file_fileno
;
4323 struct symbol
*file_symbol
;
4324 struct symbol
*file_end
;
4325 struct proc
*file_proc
;
4330 static struct obstack proc_frags
;
4331 static procS
*proc_lastP
;
4332 static procS
*proc_rootP
;
4333 static int numprocs
;
4338 obstack_begin (&proc_frags
, 0x2000);
4344 /* check for premature end, nesting errors, etc */
4345 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4346 as_warn ("missing `.end' at end of assembly");
4349 extern char hex_value
[];
4357 if (*input_line_pointer
== '-')
4359 ++input_line_pointer
;
4362 if (!isdigit (*input_line_pointer
))
4363 as_bad ("Expected simple number.");
4364 if (input_line_pointer
[0] == '0')
4366 if (input_line_pointer
[1] == 'x')
4368 input_line_pointer
+= 2;
4369 while (isxdigit (*input_line_pointer
))
4372 val
|= hex_value
[(int) *input_line_pointer
++];
4374 return negative
? -val
: val
;
4378 ++input_line_pointer
;
4379 while (isdigit (*input_line_pointer
))
4382 val
|= *input_line_pointer
++ - '0';
4384 return negative
? -val
: val
;
4387 if (!isdigit (*input_line_pointer
))
4389 printf (" *input_line_pointer == '%c' 0x%02x\n",
4390 *input_line_pointer
, *input_line_pointer
);
4391 as_warn ("Invalid number");
4394 while (isdigit (*input_line_pointer
))
4397 val
+= *input_line_pointer
++ - '0';
4399 return negative
? -val
: val
;
4402 /* The .file directive; just like the usual .file directive, but there
4403 is an initial number which is the ECOFF file index. */
4411 line
= get_number ();
4416 /* The .end directive. */
4424 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4427 demand_empty_rest_of_line ();
4431 if (now_seg
!= text_section
)
4432 as_warn (".end not in text section");
4435 as_warn (".end and no .ent seen yet.");
4441 assert (S_GET_NAME (p
));
4442 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4443 as_warn (".end symbol does not match .ent symbol.");
4446 proc_lastP
->proc_end
= (symbolS
*) 1;
4449 /* The .aent and .ent directives. */
4459 symbolP
= get_symbol ();
4460 if (*input_line_pointer
== ',')
4461 input_line_pointer
++;
4462 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4463 number
= get_number ();
4464 if (now_seg
!= text_section
)
4465 as_warn (".ent or .aent not in text section.");
4467 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4468 as_warn ("missing `.end'");
4472 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4473 procP
->proc_isym
= symbolP
;
4474 procP
->proc_reg_mask
= 0;
4475 procP
->proc_reg_offset
= 0;
4476 procP
->proc_fpreg_mask
= 0;
4477 procP
->proc_fpreg_offset
= 0;
4478 procP
->proc_frameoffset
= 0;
4479 procP
->proc_framereg
= 0;
4480 procP
->proc_pcreg
= 0;
4481 procP
->proc_end
= NULL
;
4482 procP
->proc_next
= NULL
;
4484 proc_lastP
->proc_next
= procP
;
4490 demand_empty_rest_of_line ();
4493 /* The .frame directive. */
4506 frame_reg
= tc_get_register ();
4507 if (*input_line_pointer
== ',')
4508 input_line_pointer
++;
4509 frame_off
= get_absolute_expression ();
4510 if (*input_line_pointer
== ',')
4511 input_line_pointer
++;
4512 pcreg
= tc_get_register ();
4515 assert (proc_rootP
);
4516 proc_rootP
->proc_framereg
= frame_reg
;
4517 proc_rootP
->proc_frameoffset
= frame_off
;
4518 proc_rootP
->proc_pcreg
= pcreg
;
4519 /* bob macho .frame */
4521 /* We don't have to write out a frame stab for unoptimized code. */
4522 if (!(frame_reg
== 30 && frame_off
== 0))
4525 as_warn ("No .ent for .frame to use.");
4526 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4527 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4528 S_SET_TYPE (symP
, N_RMASK
);
4529 S_SET_OTHER (symP
, 0);
4530 S_SET_DESC (symP
, 0);
4531 symP
->sy_forward
= proc_lastP
->proc_isym
;
4532 /* bob perhaps I should have used pseudo set */
4534 demand_empty_rest_of_line ();
4538 /* The .fmask and .mask directives. */
4545 char str
[100], *strP
;
4551 mask
= get_number ();
4552 if (*input_line_pointer
== ',')
4553 input_line_pointer
++;
4554 off
= get_absolute_expression ();
4556 /* bob only for coff */
4557 assert (proc_rootP
);
4558 if (reg_type
== 'F')
4560 proc_rootP
->proc_fpreg_mask
= mask
;
4561 proc_rootP
->proc_fpreg_offset
= off
;
4565 proc_rootP
->proc_reg_mask
= mask
;
4566 proc_rootP
->proc_reg_offset
= off
;
4569 /* bob macho .mask + .fmask */
4571 /* We don't have to write out a mask stab if no saved regs. */
4575 as_warn ("No .ent for .mask to use.");
4577 for (i
= 0; i
< 32; i
++)
4581 sprintf (strP
, "%c%d,", reg_type
, i
);
4582 strP
+= strlen (strP
);
4586 sprintf (strP
, ";%d,", off
);
4587 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4588 S_SET_TYPE (symP
, N_RMASK
);
4589 S_SET_OTHER (symP
, 0);
4590 S_SET_DESC (symP
, 0);
4591 symP
->sy_forward
= proc_lastP
->proc_isym
;
4592 /* bob perhaps I should have used pseudo set */
4597 /* The .loc directive. */
4608 assert (now_seg
== text_section
);
4610 lineno
= get_number ();
4611 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4613 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4614 S_SET_TYPE (symbolP
, N_SLINE
);
4615 S_SET_OTHER (symbolP
, 0);
4616 S_SET_DESC (symbolP
, lineno
);
4617 symbolP
->sy_segment
= now_seg
;
4621 #endif /* ! defined (OBJ_ECOFF) */