1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros
;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float
;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float
;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32
= -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32
= -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float
= 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float
= 0;
287 static struct mips_set_options mips_opts
=
289 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
294 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d
;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx
;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips
;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp
;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2
;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt
;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch
= CPU_UNKNOWN
;
375 static const char *mips_arch_string
;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune
= CPU_UNKNOWN
;
380 static const char *mips_tune_string
;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode
= 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic
;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got
= 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap
= 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction
;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder
;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix
;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value
= 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen
= 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS
*, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control
*op_hash
= NULL
;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control
*mips16_op_hash
= NULL
;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control
*micromips_op_hash
= NULL
;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars
[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars
[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars
[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS
[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error
;
669 static int auto_align
= 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset
= -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset
= -1;
681 static int mips_cpreturn_register
= -1;
682 static int mips_gp_register
= GP
;
683 static int mips_gprel_offset
= 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid
= 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg
= SP
;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid
= 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize
= 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug
= 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history
[1 + MAX_NOPS
];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn
;
728 static struct mips_cl_insn mips16_nop_insn
;
729 static struct mips_cl_insn micromips_nop16_insn
;
730 static struct mips_cl_insn micromips_nop32_insn
;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS
*prev_nop_frag
;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds
;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required
;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since
;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup
*next
;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup
*mips_hi_fixup_list
;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS
*prev_reloc_op_frag
;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map
[] =
790 X
, X
, 2, 3, 4, 5, 6, 7,
791 X
, X
, X
, X
, X
, X
, X
, X
,
792 0, 1, X
, X
, X
, X
, X
, X
,
793 X
, X
, X
, X
, X
, X
, X
, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map
[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map
[] =
818 X
, X
, X
, X
, 4, 5, 6, X
,
819 X
, X
, X
, X
, X
, X
, X
, X
,
820 X
, X
, X
, X
, X
, X
, X
, X
,
821 X
, X
, X
, X
, X
, X
, X
, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map
[] =
827 0, X
, 2, 3, X
, X
, X
, X
,
828 X
, X
, X
, X
, X
, X
, X
, X
,
829 4, 1, 5, 6, 7, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map
[] =
836 0, X
, 2, 3, 4, 5, 6, 7,
837 X
, X
, X
, X
, X
, X
, X
, X
,
838 X
, 1, X
, X
, X
, X
, X
, X
,
839 X
, X
, X
, X
, X
, X
, X
, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map
[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map
[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map
[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map
[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map
[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map
[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump
;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop
;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f
;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120
;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130
;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k
;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1
;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch
;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Sign-extend 16-bit value X. */
1180 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1182 /* Is the given value a sign-extended 32-bit value? */
1183 #define IS_SEXT_32BIT_NUM(x) \
1184 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1185 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1187 /* Is the given value a sign-extended 16-bit value? */
1188 #define IS_SEXT_16BIT_NUM(x) \
1189 (((x) &~ (offsetT) 0x7fff) == 0 \
1190 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1192 /* Is the given value a sign-extended 12-bit value? */
1193 #define IS_SEXT_12BIT_NUM(x) \
1194 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1196 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1197 #define IS_ZEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0xffffffff) == 0 \
1199 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1201 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1202 VALUE << SHIFT. VALUE is evaluated exactly once. */
1203 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1204 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1205 | (((VALUE) & (MASK)) << (SHIFT)))
1207 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1209 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1210 (((STRUCT) >> (SHIFT)) & (MASK))
1212 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1213 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1215 include/opcode/mips.h specifies operand fields using the macros
1216 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1217 with "MIPS16OP" instead of "OP". */
1218 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 OP_MASK_##FIELD, OP_SH_##FIELD); \
1224 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1225 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1227 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1228 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1229 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1231 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1232 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1234 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1235 : EXTRACT_BITS ((INSN).insn_opcode, \
1236 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1237 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1238 EXTRACT_BITS ((INSN).insn_opcode, \
1239 MIPS16OP_MASK_##FIELD, \
1240 MIPS16OP_SH_##FIELD)
1242 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1243 #define MIPS16_EXTEND (0xf000U << 16)
1245 /* Whether or not we are emitting a branch-likely macro. */
1246 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1248 /* Global variables used when generating relaxable macros. See the
1249 comment above RELAX_ENCODE for more details about how relaxation
1252 /* 0 if we're not emitting a relaxable macro.
1253 1 if we're emitting the first of the two relaxation alternatives.
1254 2 if we're emitting the second alternative. */
1257 /* The first relaxable fixup in the current frag. (In other words,
1258 the first fixup that refers to relaxable code.) */
1261 /* sizes[0] says how many bytes of the first alternative are stored in
1262 the current frag. Likewise sizes[1] for the second alternative. */
1263 unsigned int sizes
[2];
1265 /* The symbol on which the choice of sequence depends. */
1269 /* Global variables used to decide whether a macro needs a warning. */
1271 /* True if the macro is in a branch delay slot. */
1272 bfd_boolean delay_slot_p
;
1274 /* Set to the length in bytes required if the macro is in a delay slot
1275 that requires a specific length of instruction, otherwise zero. */
1276 unsigned int delay_slot_length
;
1278 /* For relaxable macros, sizes[0] is the length of the first alternative
1279 in bytes and sizes[1] is the length of the second alternative.
1280 For non-relaxable macros, both elements give the length of the
1282 unsigned int sizes
[2];
1284 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1285 instruction of the first alternative in bytes and first_insn_sizes[1]
1286 is the length of the first instruction of the second alternative.
1287 For non-relaxable macros, both elements give the length of the first
1288 instruction in bytes.
1290 Set to zero if we haven't yet seen the first instruction. */
1291 unsigned int first_insn_sizes
[2];
1293 /* For relaxable macros, insns[0] is the number of instructions for the
1294 first alternative and insns[1] is the number of instructions for the
1297 For non-relaxable macros, both elements give the number of
1298 instructions for the macro. */
1299 unsigned int insns
[2];
1301 /* The first variant frag for this macro. */
1303 } mips_macro_warning
;
1305 /* Prototypes for static functions. */
1307 #define internalError() \
1308 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1310 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1312 static void append_insn
1313 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1314 bfd_boolean expansionp
);
1315 static void mips_no_prev_insn (void);
1316 static void macro_build (expressionS
*, const char *, const char *, ...);
1317 static void mips16_macro_build
1318 (expressionS
*, const char *, const char *, va_list *);
1319 static void load_register (int, expressionS
*, int);
1320 static void macro_start (void);
1321 static void macro_end (void);
1322 static void macro (struct mips_cl_insn
* ip
);
1323 static void mips16_macro (struct mips_cl_insn
* ip
);
1324 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1325 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1326 static void mips16_immed
1327 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1328 unsigned int, unsigned long *);
1329 static size_t my_getSmallExpression
1330 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1331 static void my_getExpression (expressionS
*, char *);
1332 static void s_align (int);
1333 static void s_change_sec (int);
1334 static void s_change_section (int);
1335 static void s_cons (int);
1336 static void s_float_cons (int);
1337 static void s_mips_globl (int);
1338 static void s_option (int);
1339 static void s_mipsset (int);
1340 static void s_abicalls (int);
1341 static void s_cpload (int);
1342 static void s_cpsetup (int);
1343 static void s_cplocal (int);
1344 static void s_cprestore (int);
1345 static void s_cpreturn (int);
1346 static void s_dtprelword (int);
1347 static void s_dtpreldword (int);
1348 static void s_tprelword (int);
1349 static void s_tpreldword (int);
1350 static void s_gpvalue (int);
1351 static void s_gpword (int);
1352 static void s_gpdword (int);
1353 static void s_cpadd (int);
1354 static void s_insn (int);
1355 static void md_obj_begin (void);
1356 static void md_obj_end (void);
1357 static void s_mips_ent (int);
1358 static void s_mips_end (int);
1359 static void s_mips_frame (int);
1360 static void s_mips_mask (int reg_type
);
1361 static void s_mips_stab (int);
1362 static void s_mips_weakext (int);
1363 static void s_mips_file (int);
1364 static void s_mips_loc (int);
1365 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1366 static int relaxed_branch_length (fragS
*, asection
*, int);
1367 static int validate_mips_insn (const struct mips_opcode
*);
1368 static int validate_micromips_insn (const struct mips_opcode
*);
1369 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1370 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1372 /* Table and functions used to map between CPU/ISA names, and
1373 ISA levels, and CPU numbers. */
1375 struct mips_cpu_info
1377 const char *name
; /* CPU or ISA name. */
1378 int flags
; /* ASEs available, or ISA flag. */
1379 int isa
; /* ISA level. */
1380 int cpu
; /* CPU number (default CPU if ISA). */
1383 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1384 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1385 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1386 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1387 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1388 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1389 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1390 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1392 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table
[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option
, 0},
1417 {"set", s_mipsset
, 0},
1418 {"rdata", s_change_sec
, 'r'},
1419 {"sdata", s_change_sec
, 's'},
1420 {"livereg", s_ignore
, 0},
1421 {"abicalls", s_abicalls
, 0},
1422 {"cpload", s_cpload
, 0},
1423 {"cpsetup", s_cpsetup
, 0},
1424 {"cplocal", s_cplocal
, 0},
1425 {"cprestore", s_cprestore
, 0},
1426 {"cpreturn", s_cpreturn
, 0},
1427 {"dtprelword", s_dtprelword
, 0},
1428 {"dtpreldword", s_dtpreldword
, 0},
1429 {"tprelword", s_tprelword
, 0},
1430 {"tpreldword", s_tpreldword
, 0},
1431 {"gpvalue", s_gpvalue
, 0},
1432 {"gpword", s_gpword
, 0},
1433 {"gpdword", s_gpdword
, 0},
1434 {"cpadd", s_cpadd
, 0},
1435 {"insn", s_insn
, 0},
1437 /* Relatively generic pseudo-ops that happen to be used on MIPS
1439 {"asciiz", stringer
, 8 + 1},
1440 {"bss", s_change_sec
, 'b'},
1442 {"half", s_cons
, 1},
1443 {"dword", s_cons
, 3},
1444 {"weakext", s_mips_weakext
, 0},
1445 {"origin", s_org
, 0},
1446 {"repeat", s_rept
, 0},
1448 /* For MIPS this is non-standard, but we define it for consistency. */
1449 {"sbss", s_change_sec
, 'B'},
1451 /* These pseudo-ops are defined in read.c, but must be overridden
1452 here for one reason or another. */
1453 {"align", s_align
, 0},
1454 {"byte", s_cons
, 0},
1455 {"data", s_change_sec
, 'd'},
1456 {"double", s_float_cons
, 'd'},
1457 {"float", s_float_cons
, 'f'},
1458 {"globl", s_mips_globl
, 0},
1459 {"global", s_mips_globl
, 0},
1460 {"hword", s_cons
, 1},
1462 {"long", s_cons
, 2},
1463 {"octa", s_cons
, 4},
1464 {"quad", s_cons
, 3},
1465 {"section", s_change_section
, 0},
1466 {"short", s_cons
, 1},
1467 {"single", s_float_cons
, 'f'},
1468 {"stabn", s_mips_stab
, 'n'},
1469 {"text", s_change_sec
, 't'},
1470 {"word", s_cons
, 2},
1472 { "extern", ecoff_directive_extern
, 0},
1477 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1479 /* These pseudo-ops should be defined by the object file format.
1480 However, a.out doesn't support them, so we have versions here. */
1481 {"aent", s_mips_ent
, 1},
1482 {"bgnb", s_ignore
, 0},
1483 {"end", s_mips_end
, 0},
1484 {"endb", s_ignore
, 0},
1485 {"ent", s_mips_ent
, 0},
1486 {"file", s_mips_file
, 0},
1487 {"fmask", s_mips_mask
, 'F'},
1488 {"frame", s_mips_frame
, 0},
1489 {"loc", s_mips_loc
, 0},
1490 {"mask", s_mips_mask
, 'R'},
1491 {"verstamp", s_ignore
, 0},
1495 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1496 purpose of the `.dc.a' internal pseudo-op. */
1499 mips_address_bytes (void)
1501 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1504 extern void pop_insert (const pseudo_typeS
*);
1507 mips_pop_insert (void)
1509 pop_insert (mips_pseudo_table
);
1510 if (! ECOFF_DEBUGGING
)
1511 pop_insert (mips_nonecoff_pseudo_table
);
1514 /* Symbols labelling the current insn. */
1516 struct insn_label_list
1518 struct insn_label_list
*next
;
1522 static struct insn_label_list
*free_insn_labels
;
1523 #define label_list tc_segment_info_data.labels
1525 static void mips_clear_insn_labels (void);
1526 static void mips_mark_labels (void);
1527 static void mips_compressed_mark_labels (void);
1530 mips_clear_insn_labels (void)
1532 register struct insn_label_list
**pl
;
1533 segment_info_type
*si
;
1537 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1540 si
= seg_info (now_seg
);
1541 *pl
= si
->label_list
;
1542 si
->label_list
= NULL
;
1546 /* Mark instruction labels in MIPS16/microMIPS mode. */
1549 mips_mark_labels (void)
1551 if (HAVE_CODE_COMPRESSION
)
1552 mips_compressed_mark_labels ();
1555 static char *expr_end
;
1557 /* Expressions which appear in instructions. These are set by
1560 static expressionS imm_expr
;
1561 static expressionS imm2_expr
;
1562 static expressionS offset_expr
;
1564 /* Relocs associated with imm_expr and offset_expr. */
1566 static bfd_reloc_code_real_type imm_reloc
[3]
1567 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1568 static bfd_reloc_code_real_type offset_reloc
[3]
1569 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1571 /* This is set to the resulting size of the instruction to be produced
1572 by mips16_ip if an explicit extension is used or by mips_ip if an
1573 explicit size is supplied. */
1575 static unsigned int forced_insn_length
;
1577 /* True if we are assembling an instruction. All dot symbols defined during
1578 this time should be treated as code labels. */
1580 static bfd_boolean mips_assembling_insn
;
1583 /* The pdr segment for per procedure frame/regmask info. Not used for
1586 static segT pdr_seg
;
1589 /* The default target format to use. */
1591 #if defined (TE_FreeBSD)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1593 #elif defined (TE_TMIPS)
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1596 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1600 mips_target_format (void)
1602 switch (OUTPUT_FLAVOR
)
1604 case bfd_target_ecoff_flavour
:
1605 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1606 case bfd_target_coff_flavour
:
1608 case bfd_target_elf_flavour
:
1610 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1611 return (target_big_endian
1612 ? "elf32-bigmips-vxworks"
1613 : "elf32-littlemips-vxworks");
1615 return (target_big_endian
1616 ? (HAVE_64BIT_OBJECTS
1617 ? ELF_TARGET ("elf64-", "big")
1619 ? ELF_TARGET ("elf32-n", "big")
1620 : ELF_TARGET ("elf32-", "big")))
1621 : (HAVE_64BIT_OBJECTS
1622 ? ELF_TARGET ("elf64-", "little")
1624 ? ELF_TARGET ("elf32-n", "little")
1625 : ELF_TARGET ("elf32-", "little"))));
1632 /* Return the length of a microMIPS instruction in bytes. If bits of
1633 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1634 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1635 major opcode) will require further modifications to the opcode
1638 static inline unsigned int
1639 micromips_insn_length (const struct mips_opcode
*mo
)
1641 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1644 /* Return the length of MIPS16 instruction OPCODE. */
1646 static inline unsigned int
1647 mips16_opcode_length (unsigned long opcode
)
1649 return (opcode
>> 16) == 0 ? 2 : 4;
1652 /* Return the length of instruction INSN. */
1654 static inline unsigned int
1655 insn_length (const struct mips_cl_insn
*insn
)
1657 if (mips_opts
.micromips
)
1658 return micromips_insn_length (insn
->insn_mo
);
1659 else if (mips_opts
.mips16
)
1660 return mips16_opcode_length (insn
->insn_opcode
);
1665 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1668 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1673 insn
->insn_opcode
= mo
->match
;
1676 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1677 insn
->fixp
[i
] = NULL
;
1678 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1679 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1680 insn
->mips16_absolute_jump_p
= 0;
1681 insn
->complete_p
= 0;
1684 /* Record the current MIPS16/microMIPS mode in now_seg. */
1687 mips_record_compressed_mode (void)
1689 segment_info_type
*si
;
1691 si
= seg_info (now_seg
);
1692 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1693 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1694 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1695 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1698 /* Read a standard MIPS instruction from BUF. */
1700 static unsigned long
1701 read_insn (char *buf
)
1703 if (target_big_endian
)
1704 return bfd_getb32 ((bfd_byte
*) buf
);
1706 return bfd_getl32 ((bfd_byte
*) buf
);
1709 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1713 write_insn (char *buf
, unsigned int insn
)
1715 md_number_to_chars (buf
, insn
, 4);
1719 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1720 has length LENGTH. */
1722 static unsigned long
1723 read_compressed_insn (char *buf
, unsigned int length
)
1729 for (i
= 0; i
< length
; i
+= 2)
1732 if (target_big_endian
)
1733 insn
|= bfd_getb16 ((char *) buf
);
1735 insn
|= bfd_getl16 ((char *) buf
);
1741 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1742 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1745 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1749 for (i
= 0; i
< length
; i
+= 2)
1750 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1751 return buf
+ length
;
1754 /* Install INSN at the location specified by its "frag" and "where" fields. */
1757 install_insn (const struct mips_cl_insn
*insn
)
1759 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1760 if (HAVE_CODE_COMPRESSION
)
1761 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1763 write_insn (f
, insn
->insn_opcode
);
1764 mips_record_compressed_mode ();
1767 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1768 and install the opcode in the new location. */
1771 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1776 insn
->where
= where
;
1777 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1778 if (insn
->fixp
[i
] != NULL
)
1780 insn
->fixp
[i
]->fx_frag
= frag
;
1781 insn
->fixp
[i
]->fx_where
= where
;
1783 install_insn (insn
);
1786 /* Add INSN to the end of the output. */
1789 add_fixed_insn (struct mips_cl_insn
*insn
)
1791 char *f
= frag_more (insn_length (insn
));
1792 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1795 /* Start a variant frag and move INSN to the start of the variant part,
1796 marking it as fixed. The other arguments are as for frag_var. */
1799 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1800 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1802 frag_grow (max_chars
);
1803 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1805 frag_var (rs_machine_dependent
, max_chars
, var
,
1806 subtype
, symbol
, offset
, NULL
);
1809 /* Insert N copies of INSN into the history buffer, starting at
1810 position FIRST. Neither FIRST nor N need to be clipped. */
1813 insert_into_history (unsigned int first
, unsigned int n
,
1814 const struct mips_cl_insn
*insn
)
1816 if (mips_relax
.sequence
!= 2)
1820 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1822 history
[i
] = history
[i
- n
];
1828 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1829 the idea is to make it obvious at a glance that each errata is
1833 init_vr4120_conflicts (void)
1835 #define CONFLICT(FIRST, SECOND) \
1836 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1838 /* Errata 21 - [D]DIV[U] after [D]MACC */
1839 CONFLICT (MACC
, DIV
);
1840 CONFLICT (DMACC
, DIV
);
1842 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1843 CONFLICT (DMULT
, DMULT
);
1844 CONFLICT (DMULT
, DMACC
);
1845 CONFLICT (DMACC
, DMULT
);
1846 CONFLICT (DMACC
, DMACC
);
1848 /* Errata 24 - MT{LO,HI} after [D]MACC */
1849 CONFLICT (MACC
, MTHILO
);
1850 CONFLICT (DMACC
, MTHILO
);
1852 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1853 instruction is executed immediately after a MACC or DMACC
1854 instruction, the result of [either instruction] is incorrect." */
1855 CONFLICT (MACC
, MULT
);
1856 CONFLICT (MACC
, DMULT
);
1857 CONFLICT (DMACC
, MULT
);
1858 CONFLICT (DMACC
, DMULT
);
1860 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1861 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1862 DDIV or DDIVU instruction, the result of the MACC or
1863 DMACC instruction is incorrect.". */
1864 CONFLICT (DMULT
, MACC
);
1865 CONFLICT (DMULT
, DMACC
);
1866 CONFLICT (DIV
, MACC
);
1867 CONFLICT (DIV
, DMACC
);
1877 #define RTYPE_MASK 0x1ff00
1878 #define RTYPE_NUM 0x00100
1879 #define RTYPE_FPU 0x00200
1880 #define RTYPE_FCC 0x00400
1881 #define RTYPE_VEC 0x00800
1882 #define RTYPE_GP 0x01000
1883 #define RTYPE_CP0 0x02000
1884 #define RTYPE_PC 0x04000
1885 #define RTYPE_ACC 0x08000
1886 #define RTYPE_CCC 0x10000
1887 #define RNUM_MASK 0x000ff
1888 #define RWARN 0x80000
1890 #define GENERIC_REGISTER_NUMBERS \
1891 {"$0", RTYPE_NUM | 0}, \
1892 {"$1", RTYPE_NUM | 1}, \
1893 {"$2", RTYPE_NUM | 2}, \
1894 {"$3", RTYPE_NUM | 3}, \
1895 {"$4", RTYPE_NUM | 4}, \
1896 {"$5", RTYPE_NUM | 5}, \
1897 {"$6", RTYPE_NUM | 6}, \
1898 {"$7", RTYPE_NUM | 7}, \
1899 {"$8", RTYPE_NUM | 8}, \
1900 {"$9", RTYPE_NUM | 9}, \
1901 {"$10", RTYPE_NUM | 10}, \
1902 {"$11", RTYPE_NUM | 11}, \
1903 {"$12", RTYPE_NUM | 12}, \
1904 {"$13", RTYPE_NUM | 13}, \
1905 {"$14", RTYPE_NUM | 14}, \
1906 {"$15", RTYPE_NUM | 15}, \
1907 {"$16", RTYPE_NUM | 16}, \
1908 {"$17", RTYPE_NUM | 17}, \
1909 {"$18", RTYPE_NUM | 18}, \
1910 {"$19", RTYPE_NUM | 19}, \
1911 {"$20", RTYPE_NUM | 20}, \
1912 {"$21", RTYPE_NUM | 21}, \
1913 {"$22", RTYPE_NUM | 22}, \
1914 {"$23", RTYPE_NUM | 23}, \
1915 {"$24", RTYPE_NUM | 24}, \
1916 {"$25", RTYPE_NUM | 25}, \
1917 {"$26", RTYPE_NUM | 26}, \
1918 {"$27", RTYPE_NUM | 27}, \
1919 {"$28", RTYPE_NUM | 28}, \
1920 {"$29", RTYPE_NUM | 29}, \
1921 {"$30", RTYPE_NUM | 30}, \
1922 {"$31", RTYPE_NUM | 31}
1924 #define FPU_REGISTER_NAMES \
1925 {"$f0", RTYPE_FPU | 0}, \
1926 {"$f1", RTYPE_FPU | 1}, \
1927 {"$f2", RTYPE_FPU | 2}, \
1928 {"$f3", RTYPE_FPU | 3}, \
1929 {"$f4", RTYPE_FPU | 4}, \
1930 {"$f5", RTYPE_FPU | 5}, \
1931 {"$f6", RTYPE_FPU | 6}, \
1932 {"$f7", RTYPE_FPU | 7}, \
1933 {"$f8", RTYPE_FPU | 8}, \
1934 {"$f9", RTYPE_FPU | 9}, \
1935 {"$f10", RTYPE_FPU | 10}, \
1936 {"$f11", RTYPE_FPU | 11}, \
1937 {"$f12", RTYPE_FPU | 12}, \
1938 {"$f13", RTYPE_FPU | 13}, \
1939 {"$f14", RTYPE_FPU | 14}, \
1940 {"$f15", RTYPE_FPU | 15}, \
1941 {"$f16", RTYPE_FPU | 16}, \
1942 {"$f17", RTYPE_FPU | 17}, \
1943 {"$f18", RTYPE_FPU | 18}, \
1944 {"$f19", RTYPE_FPU | 19}, \
1945 {"$f20", RTYPE_FPU | 20}, \
1946 {"$f21", RTYPE_FPU | 21}, \
1947 {"$f22", RTYPE_FPU | 22}, \
1948 {"$f23", RTYPE_FPU | 23}, \
1949 {"$f24", RTYPE_FPU | 24}, \
1950 {"$f25", RTYPE_FPU | 25}, \
1951 {"$f26", RTYPE_FPU | 26}, \
1952 {"$f27", RTYPE_FPU | 27}, \
1953 {"$f28", RTYPE_FPU | 28}, \
1954 {"$f29", RTYPE_FPU | 29}, \
1955 {"$f30", RTYPE_FPU | 30}, \
1956 {"$f31", RTYPE_FPU | 31}
1958 #define FPU_CONDITION_CODE_NAMES \
1959 {"$fcc0", RTYPE_FCC | 0}, \
1960 {"$fcc1", RTYPE_FCC | 1}, \
1961 {"$fcc2", RTYPE_FCC | 2}, \
1962 {"$fcc3", RTYPE_FCC | 3}, \
1963 {"$fcc4", RTYPE_FCC | 4}, \
1964 {"$fcc5", RTYPE_FCC | 5}, \
1965 {"$fcc6", RTYPE_FCC | 6}, \
1966 {"$fcc7", RTYPE_FCC | 7}
1968 #define COPROC_CONDITION_CODE_NAMES \
1969 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1970 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1971 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1972 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1973 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1974 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1975 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1976 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1978 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1979 {"$a4", RTYPE_GP | 8}, \
1980 {"$a5", RTYPE_GP | 9}, \
1981 {"$a6", RTYPE_GP | 10}, \
1982 {"$a7", RTYPE_GP | 11}, \
1983 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1984 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1985 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1986 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1987 {"$t0", RTYPE_GP | 12}, \
1988 {"$t1", RTYPE_GP | 13}, \
1989 {"$t2", RTYPE_GP | 14}, \
1990 {"$t3", RTYPE_GP | 15}
1992 #define O32_SYMBOLIC_REGISTER_NAMES \
1993 {"$t0", RTYPE_GP | 8}, \
1994 {"$t1", RTYPE_GP | 9}, \
1995 {"$t2", RTYPE_GP | 10}, \
1996 {"$t3", RTYPE_GP | 11}, \
1997 {"$t4", RTYPE_GP | 12}, \
1998 {"$t5", RTYPE_GP | 13}, \
1999 {"$t6", RTYPE_GP | 14}, \
2000 {"$t7", RTYPE_GP | 15}, \
2001 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2002 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2003 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2004 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2006 /* Remaining symbolic register names */
2007 #define SYMBOLIC_REGISTER_NAMES \
2008 {"$zero", RTYPE_GP | 0}, \
2009 {"$at", RTYPE_GP | 1}, \
2010 {"$AT", RTYPE_GP | 1}, \
2011 {"$v0", RTYPE_GP | 2}, \
2012 {"$v1", RTYPE_GP | 3}, \
2013 {"$a0", RTYPE_GP | 4}, \
2014 {"$a1", RTYPE_GP | 5}, \
2015 {"$a2", RTYPE_GP | 6}, \
2016 {"$a3", RTYPE_GP | 7}, \
2017 {"$s0", RTYPE_GP | 16}, \
2018 {"$s1", RTYPE_GP | 17}, \
2019 {"$s2", RTYPE_GP | 18}, \
2020 {"$s3", RTYPE_GP | 19}, \
2021 {"$s4", RTYPE_GP | 20}, \
2022 {"$s5", RTYPE_GP | 21}, \
2023 {"$s6", RTYPE_GP | 22}, \
2024 {"$s7", RTYPE_GP | 23}, \
2025 {"$t8", RTYPE_GP | 24}, \
2026 {"$t9", RTYPE_GP | 25}, \
2027 {"$k0", RTYPE_GP | 26}, \
2028 {"$kt0", RTYPE_GP | 26}, \
2029 {"$k1", RTYPE_GP | 27}, \
2030 {"$kt1", RTYPE_GP | 27}, \
2031 {"$gp", RTYPE_GP | 28}, \
2032 {"$sp", RTYPE_GP | 29}, \
2033 {"$s8", RTYPE_GP | 30}, \
2034 {"$fp", RTYPE_GP | 30}, \
2035 {"$ra", RTYPE_GP | 31}
2037 #define MIPS16_SPECIAL_REGISTER_NAMES \
2038 {"$pc", RTYPE_PC | 0}
2040 #define MDMX_VECTOR_REGISTER_NAMES \
2041 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2042 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2043 {"$v2", RTYPE_VEC | 2}, \
2044 {"$v3", RTYPE_VEC | 3}, \
2045 {"$v4", RTYPE_VEC | 4}, \
2046 {"$v5", RTYPE_VEC | 5}, \
2047 {"$v6", RTYPE_VEC | 6}, \
2048 {"$v7", RTYPE_VEC | 7}, \
2049 {"$v8", RTYPE_VEC | 8}, \
2050 {"$v9", RTYPE_VEC | 9}, \
2051 {"$v10", RTYPE_VEC | 10}, \
2052 {"$v11", RTYPE_VEC | 11}, \
2053 {"$v12", RTYPE_VEC | 12}, \
2054 {"$v13", RTYPE_VEC | 13}, \
2055 {"$v14", RTYPE_VEC | 14}, \
2056 {"$v15", RTYPE_VEC | 15}, \
2057 {"$v16", RTYPE_VEC | 16}, \
2058 {"$v17", RTYPE_VEC | 17}, \
2059 {"$v18", RTYPE_VEC | 18}, \
2060 {"$v19", RTYPE_VEC | 19}, \
2061 {"$v20", RTYPE_VEC | 20}, \
2062 {"$v21", RTYPE_VEC | 21}, \
2063 {"$v22", RTYPE_VEC | 22}, \
2064 {"$v23", RTYPE_VEC | 23}, \
2065 {"$v24", RTYPE_VEC | 24}, \
2066 {"$v25", RTYPE_VEC | 25}, \
2067 {"$v26", RTYPE_VEC | 26}, \
2068 {"$v27", RTYPE_VEC | 27}, \
2069 {"$v28", RTYPE_VEC | 28}, \
2070 {"$v29", RTYPE_VEC | 29}, \
2071 {"$v30", RTYPE_VEC | 30}, \
2072 {"$v31", RTYPE_VEC | 31}
2074 #define MIPS_DSP_ACCUMULATOR_NAMES \
2075 {"$ac0", RTYPE_ACC | 0}, \
2076 {"$ac1", RTYPE_ACC | 1}, \
2077 {"$ac2", RTYPE_ACC | 2}, \
2078 {"$ac3", RTYPE_ACC | 3}
2080 static const struct regname reg_names
[] = {
2081 GENERIC_REGISTER_NUMBERS
,
2083 FPU_CONDITION_CODE_NAMES
,
2084 COPROC_CONDITION_CODE_NAMES
,
2086 /* The $txx registers depends on the abi,
2087 these will be added later into the symbol table from
2088 one of the tables below once mips_abi is set after
2089 parsing of arguments from the command line. */
2090 SYMBOLIC_REGISTER_NAMES
,
2092 MIPS16_SPECIAL_REGISTER_NAMES
,
2093 MDMX_VECTOR_REGISTER_NAMES
,
2094 MIPS_DSP_ACCUMULATOR_NAMES
,
2098 static const struct regname reg_names_o32
[] = {
2099 O32_SYMBOLIC_REGISTER_NAMES
,
2103 static const struct regname reg_names_n32n64
[] = {
2104 N32N64_SYMBOLIC_REGISTER_NAMES
,
2108 /* Check if S points at a valid register specifier according to TYPES.
2109 If so, then return 1, advance S to consume the specifier and store
2110 the register's number in REGNOP, otherwise return 0. */
2113 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2120 /* Find end of name. */
2122 if (is_name_beginner (*e
))
2124 while (is_part_of_name (*e
))
2127 /* Terminate name. */
2131 /* Look for a register symbol. */
2132 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2134 int r
= S_GET_VALUE (symbolP
);
2136 reg
= r
& RNUM_MASK
;
2137 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2138 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2139 reg
= (r
& RNUM_MASK
) - 2;
2141 /* Else see if this is a register defined in an itbl entry. */
2142 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2149 if (itbl_get_reg_val (n
, &r
))
2150 reg
= r
& RNUM_MASK
;
2153 /* Advance to next token if a register was recognised. */
2156 else if (types
& RWARN
)
2157 as_warn (_("Unrecognized register name `%s'"), *s
);
2165 /* Check if S points at a valid register list according to TYPES.
2166 If so, then return 1, advance S to consume the list and store
2167 the registers present on the list as a bitmask of ones in REGLISTP,
2168 otherwise return 0. A valid list comprises a comma-separated
2169 enumeration of valid single registers and/or dash-separated
2170 contiguous register ranges as determined by their numbers.
2172 As a special exception if one of s0-s7 registers is specified as
2173 the range's lower delimiter and s8 (fp) is its upper one, then no
2174 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2175 are selected; they have to be listed separately if needed. */
2178 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2180 unsigned int reglist
= 0;
2181 unsigned int lastregno
;
2182 bfd_boolean ok
= TRUE
;
2183 unsigned int regmask
;
2184 char *s_endlist
= *s
;
2188 while (reg_lookup (s
, types
, ®no
))
2194 ok
= reg_lookup (s
, types
, &lastregno
);
2195 if (ok
&& lastregno
< regno
)
2201 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2206 regmask
= 1 << lastregno
;
2207 regmask
= (regmask
<< 1) - 1;
2208 regmask
^= (1 << regno
) - 1;
2222 *reglistp
= reglist
;
2223 return ok
&& reglist
!= 0;
2226 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2227 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2230 is_opcode_valid (const struct mips_opcode
*mo
)
2232 int isa
= mips_opts
.isa
;
2235 if (mips_opts
.ase_mdmx
)
2237 if (mips_opts
.ase_dsp
)
2239 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2241 if (mips_opts
.ase_dspr2
)
2243 if (mips_opts
.ase_mt
)
2245 if (mips_opts
.ase_mips3d
)
2247 if (mips_opts
.ase_smartmips
)
2248 isa
|= INSN_SMARTMIPS
;
2249 if (mips_opts
.ase_mcu
)
2252 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2255 /* Check whether the instruction or macro requires single-precision or
2256 double-precision floating-point support. Note that this information is
2257 stored differently in the opcode table for insns and macros. */
2258 if (mo
->pinfo
== INSN_MACRO
)
2260 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2261 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2265 fp_s
= mo
->pinfo
& FP_S
;
2266 fp_d
= mo
->pinfo
& FP_D
;
2269 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2272 if (fp_s
&& mips_opts
.soft_float
)
2278 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2279 selected ISA and architecture. */
2282 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2284 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2287 /* Return TRUE if the size of the microMIPS opcode MO matches one
2288 explicitly requested. Always TRUE in the standard MIPS mode. */
2291 is_size_valid (const struct mips_opcode
*mo
)
2293 if (!mips_opts
.micromips
)
2296 if (!forced_insn_length
)
2298 if (mo
->pinfo
== INSN_MACRO
)
2300 return forced_insn_length
== micromips_insn_length (mo
);
2303 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2304 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2307 is_delay_slot_valid (const struct mips_opcode
*mo
)
2309 if (!mips_opts
.micromips
)
2312 if (mo
->pinfo
== INSN_MACRO
)
2314 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2315 && micromips_insn_length (mo
) != 4)
2317 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2318 && micromips_insn_length (mo
) != 2)
2324 /* This function is called once, at assembler startup time. It should set up
2325 all the tables, etc. that the MD part of the assembler will need. */
2330 const char *retval
= NULL
;
2334 if (mips_pic
!= NO_PIC
)
2336 if (g_switch_seen
&& g_switch_value
!= 0)
2337 as_bad (_("-G may not be used in position-independent code"));
2341 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2342 as_warn (_("Could not set architecture and machine"));
2344 op_hash
= hash_new ();
2346 for (i
= 0; i
< NUMOPCODES
;)
2348 const char *name
= mips_opcodes
[i
].name
;
2350 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2353 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2354 mips_opcodes
[i
].name
, retval
);
2355 /* Probably a memory allocation problem? Give up now. */
2356 as_fatal (_("Broken assembler. No assembly attempted."));
2360 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2362 if (!validate_mips_insn (&mips_opcodes
[i
]))
2364 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2366 create_insn (&nop_insn
, mips_opcodes
+ i
);
2367 if (mips_fix_loongson2f_nop
)
2368 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2369 nop_insn
.fixed_p
= 1;
2374 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2377 mips16_op_hash
= hash_new ();
2380 while (i
< bfd_mips16_num_opcodes
)
2382 const char *name
= mips16_opcodes
[i
].name
;
2384 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2386 as_fatal (_("internal: can't hash `%s': %s"),
2387 mips16_opcodes
[i
].name
, retval
);
2390 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2391 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2392 != mips16_opcodes
[i
].match
))
2394 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2395 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2398 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2400 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2401 mips16_nop_insn
.fixed_p
= 1;
2405 while (i
< bfd_mips16_num_opcodes
2406 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2409 micromips_op_hash
= hash_new ();
2412 while (i
< bfd_micromips_num_opcodes
)
2414 const char *name
= micromips_opcodes
[i
].name
;
2416 retval
= hash_insert (micromips_op_hash
, name
,
2417 (void *) µmips_opcodes
[i
]);
2419 as_fatal (_("internal: can't hash `%s': %s"),
2420 micromips_opcodes
[i
].name
, retval
);
2422 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2424 struct mips_cl_insn
*micromips_nop_insn
;
2426 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2429 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2430 micromips_nop_insn
= µmips_nop16_insn
;
2431 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2432 micromips_nop_insn
= µmips_nop32_insn
;
2436 if (micromips_nop_insn
->insn_mo
== NULL
2437 && strcmp (name
, "nop") == 0)
2439 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2440 micromips_nop_insn
->fixed_p
= 1;
2443 while (++i
< bfd_micromips_num_opcodes
2444 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2448 as_fatal (_("Broken assembler. No assembly attempted."));
2450 /* We add all the general register names to the symbol table. This
2451 helps us detect invalid uses of them. */
2452 for (i
= 0; reg_names
[i
].name
; i
++)
2453 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2454 reg_names
[i
].num
, /* & RNUM_MASK, */
2455 &zero_address_frag
));
2457 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2458 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2459 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2460 &zero_address_frag
));
2462 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2463 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2464 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2465 &zero_address_frag
));
2467 mips_no_prev_insn ();
2470 mips_cprmask
[0] = 0;
2471 mips_cprmask
[1] = 0;
2472 mips_cprmask
[2] = 0;
2473 mips_cprmask
[3] = 0;
2475 /* set the default alignment for the text section (2**2) */
2476 record_alignment (text_section
, 2);
2478 bfd_set_gp_size (stdoutput
, g_switch_value
);
2483 /* On a native system other than VxWorks, sections must be aligned
2484 to 16 byte boundaries. When configured for an embedded ELF
2485 target, we don't bother. */
2486 if (strncmp (TARGET_OS
, "elf", 3) != 0
2487 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2489 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2490 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2491 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2494 /* Create a .reginfo section for register masks and a .mdebug
2495 section for debugging information. */
2503 subseg
= now_subseg
;
2505 /* The ABI says this section should be loaded so that the
2506 running program can access it. However, we don't load it
2507 if we are configured for an embedded target */
2508 flags
= SEC_READONLY
| SEC_DATA
;
2509 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2510 flags
|= SEC_ALLOC
| SEC_LOAD
;
2512 if (mips_abi
!= N64_ABI
)
2514 sec
= subseg_new (".reginfo", (subsegT
) 0);
2516 bfd_set_section_flags (stdoutput
, sec
, flags
);
2517 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2519 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2523 /* The 64-bit ABI uses a .MIPS.options section rather than
2524 .reginfo section. */
2525 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2526 bfd_set_section_flags (stdoutput
, sec
, flags
);
2527 bfd_set_section_alignment (stdoutput
, sec
, 3);
2529 /* Set up the option header. */
2531 Elf_Internal_Options opthdr
;
2534 opthdr
.kind
= ODK_REGINFO
;
2535 opthdr
.size
= (sizeof (Elf_External_Options
)
2536 + sizeof (Elf64_External_RegInfo
));
2539 f
= frag_more (sizeof (Elf_External_Options
));
2540 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2541 (Elf_External_Options
*) f
);
2543 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2547 if (ECOFF_DEBUGGING
)
2549 sec
= subseg_new (".mdebug", (subsegT
) 0);
2550 (void) bfd_set_section_flags (stdoutput
, sec
,
2551 SEC_HAS_CONTENTS
| SEC_READONLY
);
2552 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2554 else if (mips_flag_pdr
)
2556 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2557 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2558 SEC_READONLY
| SEC_RELOC
2560 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2563 subseg_set (seg
, subseg
);
2566 #endif /* OBJ_ELF */
2568 if (! ECOFF_DEBUGGING
)
2571 if (mips_fix_vr4120
)
2572 init_vr4120_conflicts ();
2578 mips_emit_delays ();
2579 if (! ECOFF_DEBUGGING
)
2584 md_assemble (char *str
)
2586 struct mips_cl_insn insn
;
2587 bfd_reloc_code_real_type unused_reloc
[3]
2588 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2590 imm_expr
.X_op
= O_absent
;
2591 imm2_expr
.X_op
= O_absent
;
2592 offset_expr
.X_op
= O_absent
;
2593 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2594 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2595 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2596 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2597 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2598 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2600 mips_mark_labels ();
2601 mips_assembling_insn
= TRUE
;
2603 if (mips_opts
.mips16
)
2604 mips16_ip (str
, &insn
);
2607 mips_ip (str
, &insn
);
2608 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2609 str
, insn
.insn_opcode
));
2613 as_bad ("%s `%s'", insn_error
, str
);
2614 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2617 if (mips_opts
.mips16
)
2618 mips16_macro (&insn
);
2625 if (imm_expr
.X_op
!= O_absent
)
2626 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2627 else if (offset_expr
.X_op
!= O_absent
)
2628 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2630 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2633 mips_assembling_insn
= FALSE
;
2636 /* Convenience functions for abstracting away the differences between
2637 MIPS16 and non-MIPS16 relocations. */
2639 static inline bfd_boolean
2640 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2644 case BFD_RELOC_MIPS16_JMP
:
2645 case BFD_RELOC_MIPS16_GPREL
:
2646 case BFD_RELOC_MIPS16_GOT16
:
2647 case BFD_RELOC_MIPS16_CALL16
:
2648 case BFD_RELOC_MIPS16_HI16_S
:
2649 case BFD_RELOC_MIPS16_HI16
:
2650 case BFD_RELOC_MIPS16_LO16
:
2658 static inline bfd_boolean
2659 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2663 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2664 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2665 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2666 case BFD_RELOC_MICROMIPS_GPREL16
:
2667 case BFD_RELOC_MICROMIPS_JMP
:
2668 case BFD_RELOC_MICROMIPS_HI16
:
2669 case BFD_RELOC_MICROMIPS_HI16_S
:
2670 case BFD_RELOC_MICROMIPS_LO16
:
2671 case BFD_RELOC_MICROMIPS_LITERAL
:
2672 case BFD_RELOC_MICROMIPS_GOT16
:
2673 case BFD_RELOC_MICROMIPS_CALL16
:
2674 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2675 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2676 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2677 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2678 case BFD_RELOC_MICROMIPS_SUB
:
2679 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2680 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2681 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2682 case BFD_RELOC_MICROMIPS_HIGHEST
:
2683 case BFD_RELOC_MICROMIPS_HIGHER
:
2684 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2685 case BFD_RELOC_MICROMIPS_JALR
:
2693 static inline bfd_boolean
2694 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2696 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2699 static inline bfd_boolean
2700 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2702 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2703 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2706 static inline bfd_boolean
2707 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2709 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2710 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2713 static inline bfd_boolean
2714 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2716 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2717 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2720 static inline bfd_boolean
2721 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2723 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2726 /* Return true if the given relocation might need a matching %lo().
2727 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2728 need a matching %lo() when applied to local symbols. */
2730 static inline bfd_boolean
2731 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2733 return (HAVE_IN_PLACE_ADDENDS
2734 && (hi16_reloc_p (reloc
)
2735 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2736 all GOT16 relocations evaluate to "G". */
2737 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2740 /* Return the type of %lo() reloc needed by RELOC, given that
2741 reloc_needs_lo_p. */
2743 static inline bfd_reloc_code_real_type
2744 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2746 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2747 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2751 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2754 static inline bfd_boolean
2755 fixup_has_matching_lo_p (fixS
*fixp
)
2757 return (fixp
->fx_next
!= NULL
2758 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2759 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2760 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2763 /* This function returns true if modifying a register requires a
2767 reg_needs_delay (unsigned int reg
)
2769 unsigned long prev_pinfo
;
2771 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2772 if (! mips_opts
.noreorder
2773 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2774 && ! gpr_interlocks
)
2775 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2776 && ! cop_interlocks
)))
2778 /* A load from a coprocessor or from memory. All load delays
2779 delay the use of general register rt for one instruction. */
2780 /* Itbl support may require additional care here. */
2781 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2782 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2789 /* Move all labels in LABELS to the current insertion point. TEXT_P
2790 says whether the labels refer to text or data. */
2793 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2795 struct insn_label_list
*l
;
2798 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2800 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2801 symbol_set_frag (l
->label
, frag_now
);
2802 val
= (valueT
) frag_now_fix ();
2803 /* MIPS16/microMIPS text labels are stored as odd. */
2804 if (text_p
&& HAVE_CODE_COMPRESSION
)
2806 S_SET_VALUE (l
->label
, val
);
2810 /* Move all labels in insn_labels to the current insertion point
2811 and treat them as text labels. */
2814 mips_move_text_labels (void)
2816 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2820 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2822 bfd_boolean linkonce
= FALSE
;
2823 segT symseg
= S_GET_SEGMENT (sym
);
2825 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2827 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2830 /* The GNU toolchain uses an extension for ELF: a section
2831 beginning with the magic string .gnu.linkonce is a
2832 linkonce section. */
2833 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2834 sizeof ".gnu.linkonce" - 1) == 0)
2841 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2842 linker to handle them specially, such as generating jalx instructions
2843 when needed. We also make them odd for the duration of the assembly,
2844 in order to generate the right sort of code. We will make them even
2845 in the adjust_symtab routine, while leaving them marked. This is
2846 convenient for the debugger and the disassembler. The linker knows
2847 to make them odd again. */
2850 mips_compressed_mark_label (symbolS
*label
)
2852 gas_assert (HAVE_CODE_COMPRESSION
);
2854 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2857 if (mips_opts
.mips16
)
2858 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2860 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2863 if ((S_GET_VALUE (label
) & 1) == 0
2864 /* Don't adjust the address if the label is global or weak, or
2865 in a link-once section, since we'll be emitting symbol reloc
2866 references to it which will be patched up by the linker, and
2867 the final value of the symbol may or may not be MIPS16/microMIPS. */
2868 && !S_IS_WEAK (label
)
2869 && !S_IS_EXTERNAL (label
)
2870 && !s_is_linkonce (label
, now_seg
))
2871 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2874 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2877 mips_compressed_mark_labels (void)
2879 struct insn_label_list
*l
;
2881 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2882 mips_compressed_mark_label (l
->label
);
2885 /* End the current frag. Make it a variant frag and record the
2889 relax_close_frag (void)
2891 mips_macro_warning
.first_frag
= frag_now
;
2892 frag_var (rs_machine_dependent
, 0, 0,
2893 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2894 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2896 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2897 mips_relax
.first_fixup
= 0;
2900 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2901 See the comment above RELAX_ENCODE for more details. */
2904 relax_start (symbolS
*symbol
)
2906 gas_assert (mips_relax
.sequence
== 0);
2907 mips_relax
.sequence
= 1;
2908 mips_relax
.symbol
= symbol
;
2911 /* Start generating the second version of a relaxable sequence.
2912 See the comment above RELAX_ENCODE for more details. */
2917 gas_assert (mips_relax
.sequence
== 1);
2918 mips_relax
.sequence
= 2;
2921 /* End the current relaxable sequence. */
2926 gas_assert (mips_relax
.sequence
== 2);
2927 relax_close_frag ();
2928 mips_relax
.sequence
= 0;
2931 /* Return true if IP is a delayed branch or jump. */
2933 static inline bfd_boolean
2934 delayed_branch_p (const struct mips_cl_insn
*ip
)
2936 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2937 | INSN_COND_BRANCH_DELAY
2938 | INSN_COND_BRANCH_LIKELY
)) != 0;
2941 /* Return true if IP is a compact branch or jump. */
2943 static inline bfd_boolean
2944 compact_branch_p (const struct mips_cl_insn
*ip
)
2946 if (mips_opts
.mips16
)
2947 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2948 | MIPS16_INSN_COND_BRANCH
)) != 0;
2950 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2951 | INSN2_COND_BRANCH
)) != 0;
2954 /* Return true if IP is an unconditional branch or jump. */
2956 static inline bfd_boolean
2957 uncond_branch_p (const struct mips_cl_insn
*ip
)
2959 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2960 || (mips_opts
.mips16
2961 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2962 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2965 /* Return true if IP is a branch-likely instruction. */
2967 static inline bfd_boolean
2968 branch_likely_p (const struct mips_cl_insn
*ip
)
2970 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2973 /* Return the type of nop that should be used to fill the delay slot
2974 of delayed branch IP. */
2976 static struct mips_cl_insn
*
2977 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2979 if (mips_opts
.micromips
2980 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2981 return µmips_nop32_insn
;
2985 /* Return the mask of core registers that IP reads or writes. */
2988 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2990 unsigned long pinfo2
;
2994 pinfo2
= ip
->insn_mo
->pinfo2
;
2995 if (mips_opts
.micromips
)
2997 if (pinfo2
& INSN2_MOD_GPR_MD
)
2998 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2999 if (pinfo2
& INSN2_MOD_GPR_MF
)
3000 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3001 if (pinfo2
& INSN2_MOD_SP
)
3007 /* Return the mask of core registers that IP reads. */
3010 gpr_read_mask (const struct mips_cl_insn
*ip
)
3012 unsigned long pinfo
, pinfo2
;
3015 mask
= gpr_mod_mask (ip
);
3016 pinfo
= ip
->insn_mo
->pinfo
;
3017 pinfo2
= ip
->insn_mo
->pinfo2
;
3018 if (mips_opts
.mips16
)
3020 if (pinfo
& MIPS16_INSN_READ_X
)
3021 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3022 if (pinfo
& MIPS16_INSN_READ_Y
)
3023 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3024 if (pinfo
& MIPS16_INSN_READ_T
)
3026 if (pinfo
& MIPS16_INSN_READ_SP
)
3028 if (pinfo
& MIPS16_INSN_READ_31
)
3030 if (pinfo
& MIPS16_INSN_READ_Z
)
3031 mask
|= 1 << (mips16_to_32_reg_map
3032 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3033 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3034 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3038 if (pinfo2
& INSN2_READ_GPR_D
)
3039 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3040 if (pinfo
& INSN_READ_GPR_T
)
3041 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3042 if (pinfo
& INSN_READ_GPR_S
)
3043 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3044 if (pinfo2
& INSN2_READ_GP
)
3046 if (pinfo2
& INSN2_READ_GPR_31
)
3048 if (pinfo2
& INSN2_READ_GPR_Z
)
3049 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3051 if (mips_opts
.micromips
)
3053 if (pinfo2
& INSN2_READ_GPR_MC
)
3054 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3055 if (pinfo2
& INSN2_READ_GPR_ME
)
3056 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3057 if (pinfo2
& INSN2_READ_GPR_MG
)
3058 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3059 if (pinfo2
& INSN2_READ_GPR_MJ
)
3060 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3061 if (pinfo2
& INSN2_READ_GPR_MMN
)
3063 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3064 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3066 if (pinfo2
& INSN2_READ_GPR_MP
)
3067 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3068 if (pinfo2
& INSN2_READ_GPR_MQ
)
3069 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3071 /* Don't include register 0. */
3075 /* Return the mask of core registers that IP writes. */
3078 gpr_write_mask (const struct mips_cl_insn
*ip
)
3080 unsigned long pinfo
, pinfo2
;
3083 mask
= gpr_mod_mask (ip
);
3084 pinfo
= ip
->insn_mo
->pinfo
;
3085 pinfo2
= ip
->insn_mo
->pinfo2
;
3086 if (mips_opts
.mips16
)
3088 if (pinfo
& MIPS16_INSN_WRITE_X
)
3089 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3090 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3091 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3092 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3093 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3094 if (pinfo
& MIPS16_INSN_WRITE_T
)
3096 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3098 if (pinfo
& MIPS16_INSN_WRITE_31
)
3100 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3101 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3105 if (pinfo
& INSN_WRITE_GPR_D
)
3106 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3107 if (pinfo
& INSN_WRITE_GPR_T
)
3108 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3109 if (pinfo
& INSN_WRITE_GPR_S
)
3110 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3111 if (pinfo
& INSN_WRITE_GPR_31
)
3113 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3114 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3116 if (mips_opts
.micromips
)
3118 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3119 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3120 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3122 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3123 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3125 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3126 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3127 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3128 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3130 /* Don't include register 0. */
3134 /* Return the mask of floating-point registers that IP reads. */
3137 fpr_read_mask (const struct mips_cl_insn
*ip
)
3139 unsigned long pinfo
, pinfo2
;
3143 pinfo
= ip
->insn_mo
->pinfo
;
3144 pinfo2
= ip
->insn_mo
->pinfo2
;
3145 if (!mips_opts
.mips16
)
3147 if (pinfo2
& INSN2_READ_FPR_D
)
3148 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3149 if (pinfo
& INSN_READ_FPR_S
)
3150 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3151 if (pinfo
& INSN_READ_FPR_T
)
3152 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3153 if (pinfo
& INSN_READ_FPR_R
)
3154 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3155 if (pinfo2
& INSN2_READ_FPR_Z
)
3156 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3158 /* Conservatively treat all operands to an FP_D instruction are doubles.
3159 (This is overly pessimistic for things like cvt.d.s.) */
3160 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3165 /* Return the mask of floating-point registers that IP writes. */
3168 fpr_write_mask (const struct mips_cl_insn
*ip
)
3170 unsigned long pinfo
, pinfo2
;
3174 pinfo
= ip
->insn_mo
->pinfo
;
3175 pinfo2
= ip
->insn_mo
->pinfo2
;
3176 if (!mips_opts
.mips16
)
3178 if (pinfo
& INSN_WRITE_FPR_D
)
3179 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3180 if (pinfo
& INSN_WRITE_FPR_S
)
3181 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3182 if (pinfo
& INSN_WRITE_FPR_T
)
3183 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3184 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3185 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3187 /* Conservatively treat all operands to an FP_D instruction are doubles.
3188 (This is overly pessimistic for things like cvt.s.d.) */
3189 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3194 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3195 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3196 by VR4120 errata. */
3199 classify_vr4120_insn (const char *name
)
3201 if (strncmp (name
, "macc", 4) == 0)
3202 return FIX_VR4120_MACC
;
3203 if (strncmp (name
, "dmacc", 5) == 0)
3204 return FIX_VR4120_DMACC
;
3205 if (strncmp (name
, "mult", 4) == 0)
3206 return FIX_VR4120_MULT
;
3207 if (strncmp (name
, "dmult", 5) == 0)
3208 return FIX_VR4120_DMULT
;
3209 if (strstr (name
, "div"))
3210 return FIX_VR4120_DIV
;
3211 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3212 return FIX_VR4120_MTHILO
;
3213 return NUM_FIX_VR4120_CLASSES
;
3216 #define INSN_ERET 0x42000018
3217 #define INSN_DERET 0x4200001f
3219 /* Return the number of instructions that must separate INSN1 and INSN2,
3220 where INSN1 is the earlier instruction. Return the worst-case value
3221 for any INSN2 if INSN2 is null. */
3224 insns_between (const struct mips_cl_insn
*insn1
,
3225 const struct mips_cl_insn
*insn2
)
3227 unsigned long pinfo1
, pinfo2
;
3230 /* This function needs to know which pinfo flags are set for INSN2
3231 and which registers INSN2 uses. The former is stored in PINFO2 and
3232 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3233 will have every flag set and INSN2_USES_GPR will always return true. */
3234 pinfo1
= insn1
->insn_mo
->pinfo
;
3235 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3237 #define INSN2_USES_GPR(REG) \
3238 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3240 /* For most targets, write-after-read dependencies on the HI and LO
3241 registers must be separated by at least two instructions. */
3242 if (!hilo_interlocks
)
3244 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3246 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3250 /* If we're working around r7000 errata, there must be two instructions
3251 between an mfhi or mflo and any instruction that uses the result. */
3252 if (mips_7000_hilo_fix
3253 && !mips_opts
.micromips
3254 && MF_HILO_INSN (pinfo1
)
3255 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3258 /* If we're working around 24K errata, one instruction is required
3259 if an ERET or DERET is followed by a branch instruction. */
3260 if (mips_fix_24k
&& !mips_opts
.micromips
)
3262 if (insn1
->insn_opcode
== INSN_ERET
3263 || insn1
->insn_opcode
== INSN_DERET
)
3266 || insn2
->insn_opcode
== INSN_ERET
3267 || insn2
->insn_opcode
== INSN_DERET
3268 || delayed_branch_p (insn2
))
3273 /* If working around VR4120 errata, check for combinations that need
3274 a single intervening instruction. */
3275 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3277 unsigned int class1
, class2
;
3279 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3280 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3284 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3285 if (vr4120_conflicts
[class1
] & (1 << class2
))
3290 if (!HAVE_CODE_COMPRESSION
)
3292 /* Check for GPR or coprocessor load delays. All such delays
3293 are on the RT register. */
3294 /* Itbl support may require additional care here. */
3295 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3296 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3298 know (pinfo1
& INSN_WRITE_GPR_T
);
3299 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3303 /* Check for generic coprocessor hazards.
3305 This case is not handled very well. There is no special
3306 knowledge of CP0 handling, and the coprocessors other than
3307 the floating point unit are not distinguished at all. */
3308 /* Itbl support may require additional care here. FIXME!
3309 Need to modify this to include knowledge about
3310 user specified delays! */
3311 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3312 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3314 /* Handle cases where INSN1 writes to a known general coprocessor
3315 register. There must be a one instruction delay before INSN2
3316 if INSN2 reads that register, otherwise no delay is needed. */
3317 mask
= fpr_write_mask (insn1
);
3320 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3325 /* Read-after-write dependencies on the control registers
3326 require a two-instruction gap. */
3327 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3328 && (pinfo2
& INSN_READ_COND_CODE
))
3331 /* We don't know exactly what INSN1 does. If INSN2 is
3332 also a coprocessor instruction, assume there must be
3333 a one instruction gap. */
3334 if (pinfo2
& INSN_COP
)
3339 /* Check for read-after-write dependencies on the coprocessor
3340 control registers in cases where INSN1 does not need a general
3341 coprocessor delay. This means that INSN1 is a floating point
3342 comparison instruction. */
3343 /* Itbl support may require additional care here. */
3344 else if (!cop_interlocks
3345 && (pinfo1
& INSN_WRITE_COND_CODE
)
3346 && (pinfo2
& INSN_READ_COND_CODE
))
3350 #undef INSN2_USES_GPR
3355 /* Return the number of nops that would be needed to work around the
3356 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3357 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3358 that are contained within the first IGNORE instructions of HIST. */
3361 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3362 const struct mips_cl_insn
*insn
)
3367 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3368 are not affected by the errata. */
3370 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3371 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3372 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3375 /* Search for the first MFLO or MFHI. */
3376 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3377 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3379 /* Extract the destination register. */
3380 mask
= gpr_write_mask (&hist
[i
]);
3382 /* No nops are needed if INSN reads that register. */
3383 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3386 /* ...or if any of the intervening instructions do. */
3387 for (j
= 0; j
< i
; j
++)
3388 if (gpr_read_mask (&hist
[j
]) & mask
)
3392 return MAX_VR4130_NOPS
- i
;
3397 #define BASE_REG_EQ(INSN1, INSN2) \
3398 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3399 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3401 /* Return the minimum alignment for this store instruction. */
3404 fix_24k_align_to (const struct mips_opcode
*mo
)
3406 if (strcmp (mo
->name
, "sh") == 0)
3409 if (strcmp (mo
->name
, "swc1") == 0
3410 || strcmp (mo
->name
, "swc2") == 0
3411 || strcmp (mo
->name
, "sw") == 0
3412 || strcmp (mo
->name
, "sc") == 0
3413 || strcmp (mo
->name
, "s.s") == 0)
3416 if (strcmp (mo
->name
, "sdc1") == 0
3417 || strcmp (mo
->name
, "sdc2") == 0
3418 || strcmp (mo
->name
, "s.d") == 0)
3425 struct fix_24k_store_info
3427 /* Immediate offset, if any, for this store instruction. */
3429 /* Alignment required by this store instruction. */
3431 /* True for register offsets. */
3432 int register_offset
;
3435 /* Comparison function used by qsort. */
3438 fix_24k_sort (const void *a
, const void *b
)
3440 const struct fix_24k_store_info
*pos1
= a
;
3441 const struct fix_24k_store_info
*pos2
= b
;
3443 return (pos1
->off
- pos2
->off
);
3446 /* INSN is a store instruction. Try to record the store information
3447 in STINFO. Return false if the information isn't known. */
3450 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3451 const struct mips_cl_insn
*insn
)
3453 /* The instruction must have a known offset. */
3454 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3457 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3458 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3462 /* Return the number of nops that would be needed to work around the 24k
3463 "lost data on stores during refill" errata if instruction INSN
3464 immediately followed the 2 instructions described by HIST.
3465 Ignore hazards that are contained within the first IGNORE
3466 instructions of HIST.
3468 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3469 for the data cache refills and store data. The following describes
3470 the scenario where the store data could be lost.
3472 * A data cache miss, due to either a load or a store, causing fill
3473 data to be supplied by the memory subsystem
3474 * The first three doublewords of fill data are returned and written
3476 * A sequence of four stores occurs in consecutive cycles around the
3477 final doubleword of the fill:
3481 * Zero, One or more instructions
3484 The four stores A-D must be to different doublewords of the line that
3485 is being filled. The fourth instruction in the sequence above permits
3486 the fill of the final doubleword to be transferred from the FSB into
3487 the cache. In the sequence above, the stores may be either integer
3488 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3489 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3490 different doublewords on the line. If the floating point unit is
3491 running in 1:2 mode, it is not possible to create the sequence above
3492 using only floating point store instructions.
3494 In this case, the cache line being filled is incorrectly marked
3495 invalid, thereby losing the data from any store to the line that
3496 occurs between the original miss and the completion of the five
3497 cycle sequence shown above.
3499 The workarounds are:
3501 * Run the data cache in write-through mode.
3502 * Insert a non-store instruction between
3503 Store A and Store B or Store B and Store C. */
3506 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3507 const struct mips_cl_insn
*insn
)
3509 struct fix_24k_store_info pos
[3];
3510 int align
, i
, base_offset
;
3515 /* If the previous instruction wasn't a store, there's nothing to
3517 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3520 /* If the instructions after the previous one are unknown, we have
3521 to assume the worst. */
3525 /* Check whether we are dealing with three consecutive stores. */
3526 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3527 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3530 /* If we don't know the relationship between the store addresses,
3531 assume the worst. */
3532 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3533 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3536 if (!fix_24k_record_store_info (&pos
[0], insn
)
3537 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3538 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3541 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3543 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3544 X bytes and such that the base register + X is known to be aligned
3547 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3551 align
= pos
[0].align_to
;
3552 base_offset
= pos
[0].off
;
3553 for (i
= 1; i
< 3; i
++)
3554 if (align
< pos
[i
].align_to
)
3556 align
= pos
[i
].align_to
;
3557 base_offset
= pos
[i
].off
;
3559 for (i
= 0; i
< 3; i
++)
3560 pos
[i
].off
-= base_offset
;
3563 pos
[0].off
&= ~align
+ 1;
3564 pos
[1].off
&= ~align
+ 1;
3565 pos
[2].off
&= ~align
+ 1;
3567 /* If any two stores write to the same chunk, they also write to the
3568 same doubleword. The offsets are still sorted at this point. */
3569 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3572 /* A range of at least 9 bytes is needed for the stores to be in
3573 non-overlapping doublewords. */
3574 if (pos
[2].off
- pos
[0].off
<= 8)
3577 if (pos
[2].off
- pos
[1].off
>= 24
3578 || pos
[1].off
- pos
[0].off
>= 24
3579 || pos
[2].off
- pos
[0].off
>= 32)
3585 /* Return the number of nops that would be needed if instruction INSN
3586 immediately followed the MAX_NOPS instructions given by HIST,
3587 where HIST[0] is the most recent instruction. Ignore hazards
3588 between INSN and the first IGNORE instructions in HIST.
3590 If INSN is null, return the worse-case number of nops for any
3594 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3595 const struct mips_cl_insn
*insn
)
3597 int i
, nops
, tmp_nops
;
3600 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3602 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3603 if (tmp_nops
> nops
)
3607 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3609 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3610 if (tmp_nops
> nops
)
3614 if (mips_fix_24k
&& !mips_opts
.micromips
)
3616 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3617 if (tmp_nops
> nops
)
3624 /* The variable arguments provide NUM_INSNS extra instructions that
3625 might be added to HIST. Return the largest number of nops that
3626 would be needed after the extended sequence, ignoring hazards
3627 in the first IGNORE instructions. */
3630 nops_for_sequence (int num_insns
, int ignore
,
3631 const struct mips_cl_insn
*hist
, ...)
3634 struct mips_cl_insn buffer
[MAX_NOPS
];
3635 struct mips_cl_insn
*cursor
;
3638 va_start (args
, hist
);
3639 cursor
= buffer
+ num_insns
;
3640 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3641 while (cursor
> buffer
)
3642 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3644 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3649 /* Like nops_for_insn, but if INSN is a branch, take into account the
3650 worst-case delay for the branch target. */
3653 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3654 const struct mips_cl_insn
*insn
)
3658 nops
= nops_for_insn (ignore
, hist
, insn
);
3659 if (delayed_branch_p (insn
))
3661 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3662 hist
, insn
, get_delay_slot_nop (insn
));
3663 if (tmp_nops
> nops
)
3666 else if (compact_branch_p (insn
))
3668 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3669 if (tmp_nops
> nops
)
3675 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3678 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3680 gas_assert (!HAVE_CODE_COMPRESSION
);
3681 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3682 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3685 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3686 jr target pc &= 'hffff_ffff_cfff_ffff. */
3689 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3691 gas_assert (!HAVE_CODE_COMPRESSION
);
3692 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3693 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3694 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3702 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3703 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3706 ep
.X_op
= O_constant
;
3707 ep
.X_add_number
= 0xcfff0000;
3708 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3709 ep
.X_add_number
= 0xffff;
3710 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3711 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3716 fix_loongson2f (struct mips_cl_insn
* ip
)
3718 if (mips_fix_loongson2f_nop
)
3719 fix_loongson2f_nop (ip
);
3721 if (mips_fix_loongson2f_jump
)
3722 fix_loongson2f_jump (ip
);
3725 /* IP is a branch that has a delay slot, and we need to fill it
3726 automatically. Return true if we can do that by swapping IP
3727 with the previous instruction. */
3730 can_swap_branch_p (struct mips_cl_insn
*ip
)
3732 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3733 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3735 /* -O2 and above is required for this optimization. */
3736 if (mips_optimize
< 2)
3739 /* If we have seen .set volatile or .set nomove, don't optimize. */
3740 if (mips_opts
.nomove
)
3743 /* We can't swap if the previous instruction's position is fixed. */
3744 if (history
[0].fixed_p
)
3747 /* If the previous previous insn was in a .set noreorder, we can't
3748 swap. Actually, the MIPS assembler will swap in this situation.
3749 However, gcc configured -with-gnu-as will generate code like
3757 in which we can not swap the bne and INSN. If gcc is not configured
3758 -with-gnu-as, it does not output the .set pseudo-ops. */
3759 if (history
[1].noreorder_p
)
3762 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3763 This means that the previous instruction was a 4-byte one anyhow. */
3764 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3767 /* If the branch is itself the target of a branch, we can not swap.
3768 We cheat on this; all we check for is whether there is a label on
3769 this instruction. If there are any branches to anything other than
3770 a label, users must use .set noreorder. */
3771 if (seg_info (now_seg
)->label_list
)
3774 /* If the previous instruction is in a variant frag other than this
3775 branch's one, we cannot do the swap. This does not apply to
3776 MIPS16 code, which uses variant frags for different purposes. */
3777 if (!mips_opts
.mips16
3779 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3782 /* We do not swap with instructions that cannot architecturally
3783 be placed in a branch delay slot, such as SYNC or ERET. We
3784 also refrain from swapping with a trap instruction, since it
3785 complicates trap handlers to have the trap instruction be in
3787 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3788 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3791 /* Check for conflicts between the branch and the instructions
3792 before the candidate delay slot. */
3793 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3796 /* Check for conflicts between the swapped sequence and the
3797 target of the branch. */
3798 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3801 /* If the branch reads a register that the previous
3802 instruction sets, we can not swap. */
3803 gpr_read
= gpr_read_mask (ip
);
3804 prev_gpr_write
= gpr_write_mask (&history
[0]);
3805 if (gpr_read
& prev_gpr_write
)
3808 /* If the branch writes a register that the previous
3809 instruction sets, we can not swap. */
3810 gpr_write
= gpr_write_mask (ip
);
3811 if (gpr_write
& prev_gpr_write
)
3814 /* If the branch writes a register that the previous
3815 instruction reads, we can not swap. */
3816 prev_gpr_read
= gpr_read_mask (&history
[0]);
3817 if (gpr_write
& prev_gpr_read
)
3820 /* If one instruction sets a condition code and the
3821 other one uses a condition code, we can not swap. */
3822 pinfo
= ip
->insn_mo
->pinfo
;
3823 if ((pinfo
& INSN_READ_COND_CODE
)
3824 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3826 if ((pinfo
& INSN_WRITE_COND_CODE
)
3827 && (prev_pinfo
& INSN_READ_COND_CODE
))
3830 /* If the previous instruction uses the PC, we can not swap. */
3831 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3832 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3834 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3837 /* If the previous instruction has an incorrect size for a fixed
3838 branch delay slot in microMIPS mode, we cannot swap. */
3839 pinfo2
= ip
->insn_mo
->pinfo2
;
3840 if (mips_opts
.micromips
3841 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3842 && insn_length (history
) != 2)
3844 if (mips_opts
.micromips
3845 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3846 && insn_length (history
) != 4)
3852 /* Decide how we should add IP to the instruction stream. */
3854 static enum append_method
3855 get_append_method (struct mips_cl_insn
*ip
)
3857 unsigned long pinfo
;
3859 /* The relaxed version of a macro sequence must be inherently
3861 if (mips_relax
.sequence
== 2)
3864 /* We must not dabble with instructions in a ".set norerorder" block. */
3865 if (mips_opts
.noreorder
)
3868 /* Otherwise, it's our responsibility to fill branch delay slots. */
3869 if (delayed_branch_p (ip
))
3871 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3874 pinfo
= ip
->insn_mo
->pinfo
;
3875 if (mips_opts
.mips16
3876 && ISA_SUPPORTS_MIPS16E
3877 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3878 return APPEND_ADD_COMPACT
;
3880 return APPEND_ADD_WITH_NOP
;
3886 /* IP is a MIPS16 instruction whose opcode we have just changed.
3887 Point IP->insn_mo to the new opcode's definition. */
3890 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3892 const struct mips_opcode
*mo
, *end
;
3894 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3895 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3896 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3904 /* For microMIPS macros, we need to generate a local number label
3905 as the target of branches. */
3906 #define MICROMIPS_LABEL_CHAR '\037'
3907 static unsigned long micromips_target_label
;
3908 static char micromips_target_name
[32];
3911 micromips_label_name (void)
3913 char *p
= micromips_target_name
;
3914 char symbol_name_temporary
[24];
3922 l
= micromips_target_label
;
3923 #ifdef LOCAL_LABEL_PREFIX
3924 *p
++ = LOCAL_LABEL_PREFIX
;
3927 *p
++ = MICROMIPS_LABEL_CHAR
;
3930 symbol_name_temporary
[i
++] = l
% 10 + '0';
3935 *p
++ = symbol_name_temporary
[--i
];
3938 return micromips_target_name
;
3942 micromips_label_expr (expressionS
*label_expr
)
3944 label_expr
->X_op
= O_symbol
;
3945 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3946 label_expr
->X_add_number
= 0;
3950 micromips_label_inc (void)
3952 micromips_target_label
++;
3953 *micromips_target_name
= '\0';
3957 micromips_add_label (void)
3961 s
= colon (micromips_label_name ());
3962 micromips_label_inc ();
3963 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3965 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3971 /* If assembling microMIPS code, then return the microMIPS reloc
3972 corresponding to the requested one if any. Otherwise return
3973 the reloc unchanged. */
3975 static bfd_reloc_code_real_type
3976 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3978 static const bfd_reloc_code_real_type relocs
[][2] =
3980 /* Keep sorted incrementally by the left-hand key. */
3981 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3982 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3983 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3984 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3985 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3986 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3987 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3988 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3989 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3990 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3991 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3992 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3993 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3994 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3995 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3996 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3997 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3998 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3999 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4000 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4001 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4002 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4003 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4004 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4005 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4006 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4007 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4009 bfd_reloc_code_real_type r
;
4012 if (!mips_opts
.micromips
)
4014 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4020 return relocs
[i
][1];
4025 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4026 Return true on success, storing the resolved value in RESULT. */
4029 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4034 case BFD_RELOC_MIPS_HIGHEST
:
4035 case BFD_RELOC_MICROMIPS_HIGHEST
:
4036 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4039 case BFD_RELOC_MIPS_HIGHER
:
4040 case BFD_RELOC_MICROMIPS_HIGHER
:
4041 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4044 case BFD_RELOC_HI16_S
:
4045 case BFD_RELOC_MICROMIPS_HI16_S
:
4046 case BFD_RELOC_MIPS16_HI16_S
:
4047 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4050 case BFD_RELOC_HI16
:
4051 case BFD_RELOC_MICROMIPS_HI16
:
4052 case BFD_RELOC_MIPS16_HI16
:
4053 *result
= (operand
>> 16) & 0xffff;
4056 case BFD_RELOC_LO16
:
4057 case BFD_RELOC_MICROMIPS_LO16
:
4058 case BFD_RELOC_MIPS16_LO16
:
4059 *result
= operand
& 0xffff;
4062 case BFD_RELOC_UNUSED
:
4071 /* Output an instruction. IP is the instruction information.
4072 ADDRESS_EXPR is an operand of the instruction to be used with
4073 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4074 a macro expansion. */
4077 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4078 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4080 unsigned long prev_pinfo2
, pinfo
;
4081 bfd_boolean relaxed_branch
= FALSE
;
4082 enum append_method method
;
4083 bfd_boolean relax32
;
4086 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4087 fix_loongson2f (ip
);
4089 file_ase_mips16
|= mips_opts
.mips16
;
4090 file_ase_micromips
|= mips_opts
.micromips
;
4092 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4093 pinfo
= ip
->insn_mo
->pinfo
;
4095 if (mips_opts
.micromips
4097 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4098 && micromips_insn_length (ip
->insn_mo
) != 2)
4099 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4100 && micromips_insn_length (ip
->insn_mo
) != 4)))
4101 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4102 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4104 if (address_expr
== NULL
)
4106 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4107 && reloc_type
[1] == BFD_RELOC_UNUSED
4108 && reloc_type
[2] == BFD_RELOC_UNUSED
4109 && address_expr
->X_op
== O_constant
)
4111 switch (*reloc_type
)
4113 case BFD_RELOC_MIPS_JMP
:
4117 shift
= mips_opts
.micromips
? 1 : 2;
4118 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4119 as_bad (_("jump to misaligned address (0x%lx)"),
4120 (unsigned long) address_expr
->X_add_number
);
4121 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4127 case BFD_RELOC_MIPS16_JMP
:
4128 if ((address_expr
->X_add_number
& 3) != 0)
4129 as_bad (_("jump to misaligned address (0x%lx)"),
4130 (unsigned long) address_expr
->X_add_number
);
4132 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4133 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4134 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4138 case BFD_RELOC_16_PCREL_S2
:
4142 shift
= mips_opts
.micromips
? 1 : 2;
4143 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4144 as_bad (_("branch to misaligned address (0x%lx)"),
4145 (unsigned long) address_expr
->X_add_number
);
4146 if (!mips_relax_branch
)
4148 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4149 & ~((1 << (shift
+ 16)) - 1))
4150 as_bad (_("branch address range overflow (0x%lx)"),
4151 (unsigned long) address_expr
->X_add_number
);
4152 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4162 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4165 ip
->insn_opcode
|= value
& 0xffff;
4173 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4175 /* There are a lot of optimizations we could do that we don't.
4176 In particular, we do not, in general, reorder instructions.
4177 If you use gcc with optimization, it will reorder
4178 instructions and generally do much more optimization then we
4179 do here; repeating all that work in the assembler would only
4180 benefit hand written assembly code, and does not seem worth
4182 int nops
= (mips_optimize
== 0
4183 ? nops_for_insn (0, history
, NULL
)
4184 : nops_for_insn_or_target (0, history
, ip
));
4188 unsigned long old_frag_offset
;
4191 old_frag
= frag_now
;
4192 old_frag_offset
= frag_now_fix ();
4194 for (i
= 0; i
< nops
; i
++)
4195 add_fixed_insn (NOP_INSN
);
4196 insert_into_history (0, nops
, NOP_INSN
);
4200 listing_prev_line ();
4201 /* We may be at the start of a variant frag. In case we
4202 are, make sure there is enough space for the frag
4203 after the frags created by listing_prev_line. The
4204 argument to frag_grow here must be at least as large
4205 as the argument to all other calls to frag_grow in
4206 this file. We don't have to worry about being in the
4207 middle of a variant frag, because the variants insert
4208 all needed nop instructions themselves. */
4212 mips_move_text_labels ();
4214 #ifndef NO_ECOFF_DEBUGGING
4215 if (ECOFF_DEBUGGING
)
4216 ecoff_fix_loc (old_frag
, old_frag_offset
);
4220 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4224 /* Work out how many nops in prev_nop_frag are needed by IP,
4225 ignoring hazards generated by the first prev_nop_frag_since
4227 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4228 gas_assert (nops
<= prev_nop_frag_holds
);
4230 /* Enforce NOPS as a minimum. */
4231 if (nops
> prev_nop_frag_required
)
4232 prev_nop_frag_required
= nops
;
4234 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4236 /* Settle for the current number of nops. Update the history
4237 accordingly (for the benefit of any future .set reorder code). */
4238 prev_nop_frag
= NULL
;
4239 insert_into_history (prev_nop_frag_since
,
4240 prev_nop_frag_holds
, NOP_INSN
);
4244 /* Allow this instruction to replace one of the nops that was
4245 tentatively added to prev_nop_frag. */
4246 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4247 prev_nop_frag_holds
--;
4248 prev_nop_frag_since
++;
4252 method
= get_append_method (ip
);
4253 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4256 /* The value passed to dwarf2_emit_insn is the distance between
4257 the beginning of the current instruction and the address that
4258 should be recorded in the debug tables. This is normally the
4261 For MIPS16/microMIPS debug info we want to use ISA-encoded
4262 addresses, so we use -1 for an address higher by one than the
4265 If the instruction produced is a branch that we will swap with
4266 the preceding instruction, then we add the displacement by which
4267 the branch will be moved backwards. This is more appropriate
4268 and for MIPS16/microMIPS code also prevents a debugger from
4269 placing a breakpoint in the middle of the branch (and corrupting
4270 code if software breakpoints are used). */
4271 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4274 relax32
= (mips_relax_branch
4275 /* Don't try branch relaxation within .set nomacro, or within
4276 .set noat if we use $at for PIC computations. If it turns
4277 out that the branch was out-of-range, we'll get an error. */
4278 && !mips_opts
.warn_about_macros
4279 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4280 /* Don't relax BPOSGE32/64 as they have no complementing
4282 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4284 if (!HAVE_CODE_COMPRESSION
4287 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4288 && delayed_branch_p (ip
))
4290 relaxed_branch
= TRUE
;
4291 add_relaxed_insn (ip
, (relaxed_branch_length
4293 uncond_branch_p (ip
) ? -1
4294 : branch_likely_p (ip
) ? 1
4298 uncond_branch_p (ip
),
4299 branch_likely_p (ip
),
4300 pinfo
& INSN_WRITE_GPR_31
,
4302 address_expr
->X_add_symbol
,
4303 address_expr
->X_add_number
);
4304 *reloc_type
= BFD_RELOC_UNUSED
;
4306 else if (mips_opts
.micromips
4308 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4309 || *reloc_type
> BFD_RELOC_UNUSED
)
4310 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4311 /* Don't try branch relaxation when users specify
4312 16-bit/32-bit instructions. */
4313 && !forced_insn_length
)
4315 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4316 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4317 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4318 int compact
= compact_branch_p (ip
);
4319 int al
= pinfo
& INSN_WRITE_GPR_31
;
4322 gas_assert (address_expr
!= NULL
);
4323 gas_assert (!mips_relax
.sequence
);
4325 relaxed_branch
= TRUE
;
4326 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4327 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4328 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4330 address_expr
->X_add_symbol
,
4331 address_expr
->X_add_number
);
4332 *reloc_type
= BFD_RELOC_UNUSED
;
4334 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4336 /* We need to set up a variant frag. */
4337 gas_assert (address_expr
!= NULL
);
4338 add_relaxed_insn (ip
, 4, 0,
4340 (*reloc_type
- BFD_RELOC_UNUSED
,
4341 forced_insn_length
== 2, forced_insn_length
== 4,
4342 delayed_branch_p (&history
[0]),
4343 history
[0].mips16_absolute_jump_p
),
4344 make_expr_symbol (address_expr
), 0);
4346 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4348 if (!delayed_branch_p (ip
))
4349 /* Make sure there is enough room to swap this instruction with
4350 a following jump instruction. */
4352 add_fixed_insn (ip
);
4356 if (mips_opts
.mips16
4357 && mips_opts
.noreorder
4358 && delayed_branch_p (&history
[0]))
4359 as_warn (_("extended instruction in delay slot"));
4361 if (mips_relax
.sequence
)
4363 /* If we've reached the end of this frag, turn it into a variant
4364 frag and record the information for the instructions we've
4366 if (frag_room () < 4)
4367 relax_close_frag ();
4368 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4371 if (mips_relax
.sequence
!= 2)
4373 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4374 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4375 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4376 mips_macro_warning
.insns
[0]++;
4378 if (mips_relax
.sequence
!= 1)
4380 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4381 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4382 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4383 mips_macro_warning
.insns
[1]++;
4386 if (mips_opts
.mips16
)
4389 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4391 add_fixed_insn (ip
);
4394 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4396 bfd_reloc_code_real_type final_type
[3];
4397 reloc_howto_type
*howto0
;
4398 reloc_howto_type
*howto
;
4401 /* Perform any necessary conversion to microMIPS relocations
4402 and find out how many relocations there actually are. */
4403 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4404 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4406 /* In a compound relocation, it is the final (outermost)
4407 operator that determines the relocated field. */
4408 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4412 /* To reproduce this failure try assembling gas/testsuites/
4413 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4415 as_bad (_("Unsupported MIPS relocation number %d"),
4417 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4421 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4422 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4423 bfd_get_reloc_size (howto
),
4425 howto0
&& howto0
->pc_relative
,
4428 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4429 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4430 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4432 /* These relocations can have an addend that won't fit in
4433 4 octets for 64bit assembly. */
4435 && ! howto
->partial_inplace
4436 && (reloc_type
[0] == BFD_RELOC_16
4437 || reloc_type
[0] == BFD_RELOC_32
4438 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4439 || reloc_type
[0] == BFD_RELOC_GPREL16
4440 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4441 || reloc_type
[0] == BFD_RELOC_GPREL32
4442 || reloc_type
[0] == BFD_RELOC_64
4443 || reloc_type
[0] == BFD_RELOC_CTOR
4444 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4445 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4446 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4447 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4448 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4449 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4450 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4451 || hi16_reloc_p (reloc_type
[0])
4452 || lo16_reloc_p (reloc_type
[0])))
4453 ip
->fixp
[0]->fx_no_overflow
= 1;
4455 if (mips_relax
.sequence
)
4457 if (mips_relax
.first_fixup
== 0)
4458 mips_relax
.first_fixup
= ip
->fixp
[0];
4460 else if (reloc_needs_lo_p (*reloc_type
))
4462 struct mips_hi_fixup
*hi_fixup
;
4464 /* Reuse the last entry if it already has a matching %lo. */
4465 hi_fixup
= mips_hi_fixup_list
;
4467 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4469 hi_fixup
= ((struct mips_hi_fixup
*)
4470 xmalloc (sizeof (struct mips_hi_fixup
)));
4471 hi_fixup
->next
= mips_hi_fixup_list
;
4472 mips_hi_fixup_list
= hi_fixup
;
4474 hi_fixup
->fixp
= ip
->fixp
[0];
4475 hi_fixup
->seg
= now_seg
;
4478 /* Add fixups for the second and third relocations, if given.
4479 Note that the ABI allows the second relocation to be
4480 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4481 moment we only use RSS_UNDEF, but we could add support
4482 for the others if it ever becomes necessary. */
4483 for (i
= 1; i
< 3; i
++)
4484 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4486 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4487 ip
->fixp
[0]->fx_size
, NULL
, 0,
4488 FALSE
, final_type
[i
]);
4490 /* Use fx_tcbit to mark compound relocs. */
4491 ip
->fixp
[0]->fx_tcbit
= 1;
4492 ip
->fixp
[i
]->fx_tcbit
= 1;
4497 /* Update the register mask information. */
4498 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4499 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4504 insert_into_history (0, 1, ip
);
4507 case APPEND_ADD_WITH_NOP
:
4509 struct mips_cl_insn
*nop
;
4511 insert_into_history (0, 1, ip
);
4512 nop
= get_delay_slot_nop (ip
);
4513 add_fixed_insn (nop
);
4514 insert_into_history (0, 1, nop
);
4515 if (mips_relax
.sequence
)
4516 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4520 case APPEND_ADD_COMPACT
:
4521 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4522 gas_assert (mips_opts
.mips16
);
4523 ip
->insn_opcode
|= 0x0080;
4524 find_altered_mips16_opcode (ip
);
4526 insert_into_history (0, 1, ip
);
4531 struct mips_cl_insn delay
= history
[0];
4532 if (mips_opts
.mips16
)
4534 know (delay
.frag
== ip
->frag
);
4535 move_insn (ip
, delay
.frag
, delay
.where
);
4536 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4538 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4540 /* Add the delay slot instruction to the end of the
4541 current frag and shrink the fixed part of the
4542 original frag. If the branch occupies the tail of
4543 the latter, move it backwards to cover the gap. */
4544 delay
.frag
->fr_fix
-= branch_disp
;
4545 if (delay
.frag
== ip
->frag
)
4546 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4547 add_fixed_insn (&delay
);
4551 move_insn (&delay
, ip
->frag
,
4552 ip
->where
- branch_disp
+ insn_length (ip
));
4553 move_insn (ip
, history
[0].frag
, history
[0].where
);
4557 insert_into_history (0, 1, &delay
);
4562 /* If we have just completed an unconditional branch, clear the history. */
4563 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4564 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4565 mips_no_prev_insn ();
4567 /* We need to emit a label at the end of branch-likely macros. */
4568 if (emit_branch_likely_macro
)
4570 emit_branch_likely_macro
= FALSE
;
4571 micromips_add_label ();
4574 /* We just output an insn, so the next one doesn't have a label. */
4575 mips_clear_insn_labels ();
4578 /* Forget that there was any previous instruction or label. */
4581 mips_no_prev_insn (void)
4583 prev_nop_frag
= NULL
;
4584 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4585 mips_clear_insn_labels ();
4588 /* This function must be called before we emit something other than
4589 instructions. It is like mips_no_prev_insn except that it inserts
4590 any NOPS that might be needed by previous instructions. */
4593 mips_emit_delays (void)
4595 if (! mips_opts
.noreorder
)
4597 int nops
= nops_for_insn (0, history
, NULL
);
4601 add_fixed_insn (NOP_INSN
);
4602 mips_move_text_labels ();
4605 mips_no_prev_insn ();
4608 /* Start a (possibly nested) noreorder block. */
4611 start_noreorder (void)
4613 if (mips_opts
.noreorder
== 0)
4618 /* None of the instructions before the .set noreorder can be moved. */
4619 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4620 history
[i
].fixed_p
= 1;
4622 /* Insert any nops that might be needed between the .set noreorder
4623 block and the previous instructions. We will later remove any
4624 nops that turn out not to be needed. */
4625 nops
= nops_for_insn (0, history
, NULL
);
4628 if (mips_optimize
!= 0)
4630 /* Record the frag which holds the nop instructions, so
4631 that we can remove them if we don't need them. */
4632 frag_grow (nops
* NOP_INSN_SIZE
);
4633 prev_nop_frag
= frag_now
;
4634 prev_nop_frag_holds
= nops
;
4635 prev_nop_frag_required
= 0;
4636 prev_nop_frag_since
= 0;
4639 for (; nops
> 0; --nops
)
4640 add_fixed_insn (NOP_INSN
);
4642 /* Move on to a new frag, so that it is safe to simply
4643 decrease the size of prev_nop_frag. */
4644 frag_wane (frag_now
);
4646 mips_move_text_labels ();
4648 mips_mark_labels ();
4649 mips_clear_insn_labels ();
4651 mips_opts
.noreorder
++;
4652 mips_any_noreorder
= 1;
4655 /* End a nested noreorder block. */
4658 end_noreorder (void)
4660 mips_opts
.noreorder
--;
4661 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4663 /* Commit to inserting prev_nop_frag_required nops and go back to
4664 handling nop insertion the .set reorder way. */
4665 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4667 insert_into_history (prev_nop_frag_since
,
4668 prev_nop_frag_required
, NOP_INSN
);
4669 prev_nop_frag
= NULL
;
4673 /* Set up global variables for the start of a new macro. */
4678 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4679 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4680 sizeof (mips_macro_warning
.first_insn_sizes
));
4681 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4682 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4683 && delayed_branch_p (&history
[0]));
4684 switch (history
[0].insn_mo
->pinfo2
4685 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4687 case INSN2_BRANCH_DELAY_32BIT
:
4688 mips_macro_warning
.delay_slot_length
= 4;
4690 case INSN2_BRANCH_DELAY_16BIT
:
4691 mips_macro_warning
.delay_slot_length
= 2;
4694 mips_macro_warning
.delay_slot_length
= 0;
4697 mips_macro_warning
.first_frag
= NULL
;
4700 /* Given that a macro is longer than one instruction or of the wrong size,
4701 return the appropriate warning for it. Return null if no warning is
4702 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4703 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4704 and RELAX_NOMACRO. */
4707 macro_warning (relax_substateT subtype
)
4709 if (subtype
& RELAX_DELAY_SLOT
)
4710 return _("Macro instruction expanded into multiple instructions"
4711 " in a branch delay slot");
4712 else if (subtype
& RELAX_NOMACRO
)
4713 return _("Macro instruction expanded into multiple instructions");
4714 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4715 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4716 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4717 ? _("Macro instruction expanded into a wrong size instruction"
4718 " in a 16-bit branch delay slot")
4719 : _("Macro instruction expanded into a wrong size instruction"
4720 " in a 32-bit branch delay slot"));
4725 /* Finish up a macro. Emit warnings as appropriate. */
4730 /* Relaxation warning flags. */
4731 relax_substateT subtype
= 0;
4733 /* Check delay slot size requirements. */
4734 if (mips_macro_warning
.delay_slot_length
== 2)
4735 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4736 if (mips_macro_warning
.delay_slot_length
!= 0)
4738 if (mips_macro_warning
.delay_slot_length
4739 != mips_macro_warning
.first_insn_sizes
[0])
4740 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4741 if (mips_macro_warning
.delay_slot_length
4742 != mips_macro_warning
.first_insn_sizes
[1])
4743 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4746 /* Check instruction count requirements. */
4747 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4749 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4750 subtype
|= RELAX_SECOND_LONGER
;
4751 if (mips_opts
.warn_about_macros
)
4752 subtype
|= RELAX_NOMACRO
;
4753 if (mips_macro_warning
.delay_slot_p
)
4754 subtype
|= RELAX_DELAY_SLOT
;
4757 /* If both alternatives fail to fill a delay slot correctly,
4758 emit the warning now. */
4759 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4760 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4765 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4766 | RELAX_DELAY_SLOT_SIZE_FIRST
4767 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4768 msg
= macro_warning (s
);
4770 as_warn ("%s", msg
);
4774 /* If both implementations are longer than 1 instruction, then emit the
4776 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4781 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4782 msg
= macro_warning (s
);
4784 as_warn ("%s", msg
);
4788 /* If any flags still set, then one implementation might need a warning
4789 and the other either will need one of a different kind or none at all.
4790 Pass any remaining flags over to relaxation. */
4791 if (mips_macro_warning
.first_frag
!= NULL
)
4792 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4795 /* Instruction operand formats used in macros that vary between
4796 standard MIPS and microMIPS code. */
4798 static const char * const brk_fmt
[2] = { "c", "mF" };
4799 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4800 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4801 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4802 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4803 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4804 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4805 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4807 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4808 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4809 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4810 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4811 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4812 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4813 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4814 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4816 /* Read a macro's relocation codes from *ARGS and store them in *R.
4817 The first argument in *ARGS will be either the code for a single
4818 relocation or -1 followed by the three codes that make up a
4819 composite relocation. */
4822 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4826 next
= va_arg (*args
, int);
4828 r
[0] = (bfd_reloc_code_real_type
) next
;
4830 for (i
= 0; i
< 3; i
++)
4831 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4834 /* Build an instruction created by a macro expansion. This is passed
4835 a pointer to the count of instructions created so far, an
4836 expression, the name of the instruction to build, an operand format
4837 string, and corresponding arguments. */
4840 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4842 const struct mips_opcode
*mo
= NULL
;
4843 bfd_reloc_code_real_type r
[3];
4844 const struct mips_opcode
*amo
;
4845 struct hash_control
*hash
;
4846 struct mips_cl_insn insn
;
4849 va_start (args
, fmt
);
4851 if (mips_opts
.mips16
)
4853 mips16_macro_build (ep
, name
, fmt
, &args
);
4858 r
[0] = BFD_RELOC_UNUSED
;
4859 r
[1] = BFD_RELOC_UNUSED
;
4860 r
[2] = BFD_RELOC_UNUSED
;
4861 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4862 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4864 gas_assert (strcmp (name
, amo
->name
) == 0);
4868 /* Search until we get a match for NAME. It is assumed here that
4869 macros will never generate MDMX, MIPS-3D, or MT instructions.
4870 We try to match an instruction that fulfils the branch delay
4871 slot instruction length requirement (if any) of the previous
4872 instruction. While doing this we record the first instruction
4873 seen that matches all the other conditions and use it anyway
4874 if the requirement cannot be met; we will issue an appropriate
4875 warning later on. */
4876 if (strcmp (fmt
, amo
->args
) == 0
4877 && amo
->pinfo
!= INSN_MACRO
4878 && is_opcode_valid (amo
)
4879 && is_size_valid (amo
))
4881 if (is_delay_slot_valid (amo
))
4891 gas_assert (amo
->name
);
4893 while (strcmp (name
, amo
->name
) == 0);
4896 create_insn (&insn
, mo
);
4914 INSERT_OPERAND (mips_opts
.micromips
,
4915 EXTLSB
, insn
, va_arg (args
, int));
4920 /* Note that in the macro case, these arguments are already
4921 in MSB form. (When handling the instruction in the
4922 non-macro case, these arguments are sizes from which
4923 MSB values must be calculated.) */
4924 INSERT_OPERAND (mips_opts
.micromips
,
4925 INSMSB
, insn
, va_arg (args
, int));
4931 /* Note that in the macro case, these arguments are already
4932 in MSBD form. (When handling the instruction in the
4933 non-macro case, these arguments are sizes from which
4934 MSBD values must be calculated.) */
4935 INSERT_OPERAND (mips_opts
.micromips
,
4936 EXTMSBD
, insn
, va_arg (args
, int));
4940 gas_assert (!mips_opts
.micromips
);
4941 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4950 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
4954 gas_assert (mips_opts
.micromips
);
4958 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4962 gas_assert (!mips_opts
.micromips
);
4963 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4967 gas_assert (!mips_opts
.micromips
);
4969 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4973 if (mips_opts
.micromips
)
4974 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4976 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4980 gas_assert (!mips_opts
.micromips
);
4982 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4986 gas_assert (!mips_opts
.micromips
);
4988 int tmp
= va_arg (args
, int);
4990 INSERT_OPERAND (0, RT
, insn
, tmp
);
4991 INSERT_OPERAND (0, RD
, insn
, tmp
);
4997 gas_assert (!mips_opts
.micromips
);
4998 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5005 INSERT_OPERAND (mips_opts
.micromips
,
5006 SHAMT
, insn
, va_arg (args
, int));
5010 gas_assert (!mips_opts
.micromips
);
5011 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5015 gas_assert (!mips_opts
.micromips
);
5016 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5020 gas_assert (!mips_opts
.micromips
);
5021 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5025 gas_assert (!mips_opts
.micromips
);
5026 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5033 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5038 macro_read_relocs (&args
, r
);
5039 gas_assert (*r
== BFD_RELOC_GPREL16
5040 || *r
== BFD_RELOC_MIPS_HIGHER
5041 || *r
== BFD_RELOC_HI16_S
5042 || *r
== BFD_RELOC_LO16
5043 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5047 macro_read_relocs (&args
, r
);
5051 macro_read_relocs (&args
, r
);
5052 gas_assert (ep
!= NULL
5053 && (ep
->X_op
== O_constant
5054 || (ep
->X_op
== O_symbol
5055 && (*r
== BFD_RELOC_MIPS_HIGHEST
5056 || *r
== BFD_RELOC_HI16_S
5057 || *r
== BFD_RELOC_HI16
5058 || *r
== BFD_RELOC_GPREL16
5059 || *r
== BFD_RELOC_MIPS_GOT_HI16
5060 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5064 gas_assert (ep
!= NULL
);
5067 * This allows macro() to pass an immediate expression for
5068 * creating short branches without creating a symbol.
5070 * We don't allow branch relaxation for these branches, as
5071 * they should only appear in ".set nomacro" anyway.
5073 if (ep
->X_op
== O_constant
)
5075 /* For microMIPS we always use relocations for branches.
5076 So we should not resolve immediate values. */
5077 gas_assert (!mips_opts
.micromips
);
5079 if ((ep
->X_add_number
& 3) != 0)
5080 as_bad (_("branch to misaligned address (0x%lx)"),
5081 (unsigned long) ep
->X_add_number
);
5082 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5083 as_bad (_("branch address range overflow (0x%lx)"),
5084 (unsigned long) ep
->X_add_number
);
5085 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5089 *r
= BFD_RELOC_16_PCREL_S2
;
5093 gas_assert (ep
!= NULL
);
5094 *r
= BFD_RELOC_MIPS_JMP
;
5098 gas_assert (!mips_opts
.micromips
);
5099 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5103 INSERT_OPERAND (mips_opts
.micromips
,
5104 CACHE
, insn
, va_arg (args
, unsigned long));
5108 gas_assert (mips_opts
.micromips
);
5109 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5113 gas_assert (mips_opts
.micromips
);
5114 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5118 INSERT_OPERAND (mips_opts
.micromips
,
5119 3BITPOS
, insn
, va_arg (args
, unsigned int));
5123 INSERT_OPERAND (mips_opts
.micromips
,
5124 OFFSET12
, insn
, va_arg (args
, unsigned long));
5128 gas_assert (mips_opts
.micromips
);
5129 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5132 case 'm': /* Opcode extension character. */
5133 gas_assert (mips_opts
.micromips
);
5137 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5141 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5145 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5159 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5161 append_insn (&insn
, ep
, r
, TRUE
);
5165 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5168 struct mips_opcode
*mo
;
5169 struct mips_cl_insn insn
;
5170 bfd_reloc_code_real_type r
[3]
5171 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5173 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5175 gas_assert (strcmp (name
, mo
->name
) == 0);
5177 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5180 gas_assert (mo
->name
);
5181 gas_assert (strcmp (name
, mo
->name
) == 0);
5184 create_insn (&insn
, mo
);
5202 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5207 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5211 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5215 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5225 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5232 regno
= va_arg (*args
, int);
5233 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5234 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5257 gas_assert (ep
!= NULL
);
5259 if (ep
->X_op
!= O_constant
)
5260 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5261 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5263 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5265 *r
= BFD_RELOC_UNUSED
;
5271 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5278 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5280 append_insn (&insn
, ep
, r
, TRUE
);
5284 * Sign-extend 32-bit mode constants that have bit 31 set and all
5285 * higher bits unset.
5288 normalize_constant_expr (expressionS
*ex
)
5290 if (ex
->X_op
== O_constant
5291 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5292 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5297 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5298 * all higher bits unset.
5301 normalize_address_expr (expressionS
*ex
)
5303 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5304 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5305 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5306 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5311 * Generate a "jalr" instruction with a relocation hint to the called
5312 * function. This occurs in NewABI PIC code.
5315 macro_build_jalr (expressionS
*ep
, int cprestore
)
5317 static const bfd_reloc_code_real_type jalr_relocs
[2]
5318 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5319 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5323 if (MIPS_JALR_HINT_P (ep
))
5328 if (mips_opts
.micromips
)
5330 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5331 if (MIPS_JALR_HINT_P (ep
))
5332 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5334 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5337 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5338 if (MIPS_JALR_HINT_P (ep
))
5339 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5343 * Generate a "lui" instruction.
5346 macro_build_lui (expressionS
*ep
, int regnum
)
5348 gas_assert (! mips_opts
.mips16
);
5350 if (ep
->X_op
!= O_constant
)
5352 gas_assert (ep
->X_op
== O_symbol
);
5353 /* _gp_disp is a special case, used from s_cpload.
5354 __gnu_local_gp is used if mips_no_shared. */
5355 gas_assert (mips_pic
== NO_PIC
5357 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5358 || (! mips_in_shared
5359 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5360 "__gnu_local_gp") == 0));
5363 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5366 /* Generate a sequence of instructions to do a load or store from a constant
5367 offset off of a base register (breg) into/from a target register (treg),
5368 using AT if necessary. */
5370 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5371 int treg
, int breg
, int dbl
)
5373 gas_assert (ep
->X_op
== O_constant
);
5375 /* Sign-extending 32-bit constants makes their handling easier. */
5377 normalize_constant_expr (ep
);
5379 /* Right now, this routine can only handle signed 32-bit constants. */
5380 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5381 as_warn (_("operand overflow"));
5383 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5385 /* Signed 16-bit offset will fit in the op. Easy! */
5386 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5390 /* 32-bit offset, need multiple instructions and AT, like:
5391 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5392 addu $tempreg,$tempreg,$breg
5393 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5394 to handle the complete offset. */
5395 macro_build_lui (ep
, AT
);
5396 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5397 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5400 as_bad (_("Macro used $at after \".set noat\""));
5405 * Generates code to set the $at register to true (one)
5406 * if reg is less than the immediate expression.
5409 set_at (int reg
, int unsignedp
)
5411 if (imm_expr
.X_op
== O_constant
5412 && imm_expr
.X_add_number
>= -0x8000
5413 && imm_expr
.X_add_number
< 0x8000)
5414 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5415 AT
, reg
, BFD_RELOC_LO16
);
5418 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5419 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5423 /* Warn if an expression is not a constant. */
5426 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5428 if (ex
->X_op
== O_big
)
5429 as_bad (_("unsupported large constant"));
5430 else if (ex
->X_op
!= O_constant
)
5431 as_bad (_("Instruction %s requires absolute expression"),
5434 if (HAVE_32BIT_GPRS
)
5435 normalize_constant_expr (ex
);
5438 /* Count the leading zeroes by performing a binary chop. This is a
5439 bulky bit of source, but performance is a LOT better for the
5440 majority of values than a simple loop to count the bits:
5441 for (lcnt = 0; (lcnt < 32); lcnt++)
5442 if ((v) & (1 << (31 - lcnt)))
5444 However it is not code size friendly, and the gain will drop a bit
5445 on certain cached systems.
5447 #define COUNT_TOP_ZEROES(v) \
5448 (((v) & ~0xffff) == 0 \
5449 ? ((v) & ~0xff) == 0 \
5450 ? ((v) & ~0xf) == 0 \
5451 ? ((v) & ~0x3) == 0 \
5452 ? ((v) & ~0x1) == 0 \
5457 : ((v) & ~0x7) == 0 \
5460 : ((v) & ~0x3f) == 0 \
5461 ? ((v) & ~0x1f) == 0 \
5464 : ((v) & ~0x7f) == 0 \
5467 : ((v) & ~0xfff) == 0 \
5468 ? ((v) & ~0x3ff) == 0 \
5469 ? ((v) & ~0x1ff) == 0 \
5472 : ((v) & ~0x7ff) == 0 \
5475 : ((v) & ~0x3fff) == 0 \
5476 ? ((v) & ~0x1fff) == 0 \
5479 : ((v) & ~0x7fff) == 0 \
5482 : ((v) & ~0xffffff) == 0 \
5483 ? ((v) & ~0xfffff) == 0 \
5484 ? ((v) & ~0x3ffff) == 0 \
5485 ? ((v) & ~0x1ffff) == 0 \
5488 : ((v) & ~0x7ffff) == 0 \
5491 : ((v) & ~0x3fffff) == 0 \
5492 ? ((v) & ~0x1fffff) == 0 \
5495 : ((v) & ~0x7fffff) == 0 \
5498 : ((v) & ~0xfffffff) == 0 \
5499 ? ((v) & ~0x3ffffff) == 0 \
5500 ? ((v) & ~0x1ffffff) == 0 \
5503 : ((v) & ~0x7ffffff) == 0 \
5506 : ((v) & ~0x3fffffff) == 0 \
5507 ? ((v) & ~0x1fffffff) == 0 \
5510 : ((v) & ~0x7fffffff) == 0 \
5515 * This routine generates the least number of instructions necessary to load
5516 * an absolute expression value into a register.
5519 load_register (int reg
, expressionS
*ep
, int dbl
)
5522 expressionS hi32
, lo32
;
5524 if (ep
->X_op
!= O_big
)
5526 gas_assert (ep
->X_op
== O_constant
);
5528 /* Sign-extending 32-bit constants makes their handling easier. */
5530 normalize_constant_expr (ep
);
5532 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5534 /* We can handle 16 bit signed values with an addiu to
5535 $zero. No need to ever use daddiu here, since $zero and
5536 the result are always correct in 32 bit mode. */
5537 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5540 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5542 /* We can handle 16 bit unsigned values with an ori to
5544 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5547 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5549 /* 32 bit values require an lui. */
5550 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5551 if ((ep
->X_add_number
& 0xffff) != 0)
5552 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5557 /* The value is larger than 32 bits. */
5559 if (!dbl
|| HAVE_32BIT_GPRS
)
5563 sprintf_vma (value
, ep
->X_add_number
);
5564 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5565 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5569 if (ep
->X_op
!= O_big
)
5572 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5573 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5574 hi32
.X_add_number
&= 0xffffffff;
5576 lo32
.X_add_number
&= 0xffffffff;
5580 gas_assert (ep
->X_add_number
> 2);
5581 if (ep
->X_add_number
== 3)
5582 generic_bignum
[3] = 0;
5583 else if (ep
->X_add_number
> 4)
5584 as_bad (_("Number larger than 64 bits"));
5585 lo32
.X_op
= O_constant
;
5586 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5587 hi32
.X_op
= O_constant
;
5588 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5591 if (hi32
.X_add_number
== 0)
5596 unsigned long hi
, lo
;
5598 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5600 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5602 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5605 if (lo32
.X_add_number
& 0x80000000)
5607 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5608 if (lo32
.X_add_number
& 0xffff)
5609 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5614 /* Check for 16bit shifted constant. We know that hi32 is
5615 non-zero, so start the mask on the first bit of the hi32
5620 unsigned long himask
, lomask
;
5624 himask
= 0xffff >> (32 - shift
);
5625 lomask
= (0xffff << shift
) & 0xffffffff;
5629 himask
= 0xffff << (shift
- 32);
5632 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5633 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5637 tmp
.X_op
= O_constant
;
5639 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5640 | (lo32
.X_add_number
>> shift
));
5642 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5643 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5644 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5645 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5650 while (shift
<= (64 - 16));
5652 /* Find the bit number of the lowest one bit, and store the
5653 shifted value in hi/lo. */
5654 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5655 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5659 while ((lo
& 1) == 0)
5664 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5670 while ((hi
& 1) == 0)
5679 /* Optimize if the shifted value is a (power of 2) - 1. */
5680 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5681 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5683 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5688 /* This instruction will set the register to be all
5690 tmp
.X_op
= O_constant
;
5691 tmp
.X_add_number
= (offsetT
) -1;
5692 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5696 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5697 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5699 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5700 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5705 /* Sign extend hi32 before calling load_register, because we can
5706 generally get better code when we load a sign extended value. */
5707 if ((hi32
.X_add_number
& 0x80000000) != 0)
5708 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5709 load_register (reg
, &hi32
, 0);
5712 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5716 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5724 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5726 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5727 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5733 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5737 mid16
.X_add_number
>>= 16;
5738 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5739 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5742 if ((lo32
.X_add_number
& 0xffff) != 0)
5743 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5747 load_delay_nop (void)
5749 if (!gpr_interlocks
)
5750 macro_build (NULL
, "nop", "");
5753 /* Load an address into a register. */
5756 load_address (int reg
, expressionS
*ep
, int *used_at
)
5758 if (ep
->X_op
!= O_constant
5759 && ep
->X_op
!= O_symbol
)
5761 as_bad (_("expression too complex"));
5762 ep
->X_op
= O_constant
;
5765 if (ep
->X_op
== O_constant
)
5767 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5771 if (mips_pic
== NO_PIC
)
5773 /* If this is a reference to a GP relative symbol, we want
5774 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5776 lui $reg,<sym> (BFD_RELOC_HI16_S)
5777 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5778 If we have an addend, we always use the latter form.
5780 With 64bit address space and a usable $at we want
5781 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5782 lui $at,<sym> (BFD_RELOC_HI16_S)
5783 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5784 daddiu $at,<sym> (BFD_RELOC_LO16)
5788 If $at is already in use, we use a path which is suboptimal
5789 on superscalar processors.
5790 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5791 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5793 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5795 daddiu $reg,<sym> (BFD_RELOC_LO16)
5797 For GP relative symbols in 64bit address space we can use
5798 the same sequence as in 32bit address space. */
5799 if (HAVE_64BIT_SYMBOLS
)
5801 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5802 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5804 relax_start (ep
->X_add_symbol
);
5805 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5806 mips_gp_register
, BFD_RELOC_GPREL16
);
5810 if (*used_at
== 0 && mips_opts
.at
)
5812 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5813 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5814 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5815 BFD_RELOC_MIPS_HIGHER
);
5816 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5817 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5818 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5823 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5824 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5825 BFD_RELOC_MIPS_HIGHER
);
5826 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5827 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5828 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5829 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5832 if (mips_relax
.sequence
)
5837 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5838 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5840 relax_start (ep
->X_add_symbol
);
5841 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5842 mips_gp_register
, BFD_RELOC_GPREL16
);
5845 macro_build_lui (ep
, reg
);
5846 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5847 reg
, reg
, BFD_RELOC_LO16
);
5848 if (mips_relax
.sequence
)
5852 else if (!mips_big_got
)
5856 /* If this is a reference to an external symbol, we want
5857 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5861 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5862 If there is a constant, it must be added in after.
5864 If we have NewABI, we want
5865 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5866 unless we're referencing a global symbol with a non-zero
5867 offset, in which case cst must be added separately. */
5870 if (ep
->X_add_number
)
5872 ex
.X_add_number
= ep
->X_add_number
;
5873 ep
->X_add_number
= 0;
5874 relax_start (ep
->X_add_symbol
);
5875 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5876 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5877 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5878 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5879 ex
.X_op
= O_constant
;
5880 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5881 reg
, reg
, BFD_RELOC_LO16
);
5882 ep
->X_add_number
= ex
.X_add_number
;
5885 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5886 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5887 if (mips_relax
.sequence
)
5892 ex
.X_add_number
= ep
->X_add_number
;
5893 ep
->X_add_number
= 0;
5894 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5895 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5897 relax_start (ep
->X_add_symbol
);
5899 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5903 if (ex
.X_add_number
!= 0)
5905 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5907 ex
.X_op
= O_constant
;
5908 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5909 reg
, reg
, BFD_RELOC_LO16
);
5913 else if (mips_big_got
)
5917 /* This is the large GOT case. If this is a reference to an
5918 external symbol, we want
5919 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5921 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5923 Otherwise, for a reference to a local symbol in old ABI, we want
5924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5926 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5927 If there is a constant, it must be added in after.
5929 In the NewABI, for local symbols, with or without offsets, we want:
5930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5931 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5935 ex
.X_add_number
= ep
->X_add_number
;
5936 ep
->X_add_number
= 0;
5937 relax_start (ep
->X_add_symbol
);
5938 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5940 reg
, reg
, mips_gp_register
);
5941 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5942 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5943 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5944 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5945 else if (ex
.X_add_number
)
5947 ex
.X_op
= O_constant
;
5948 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5952 ep
->X_add_number
= ex
.X_add_number
;
5954 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5955 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5956 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5957 BFD_RELOC_MIPS_GOT_OFST
);
5962 ex
.X_add_number
= ep
->X_add_number
;
5963 ep
->X_add_number
= 0;
5964 relax_start (ep
->X_add_symbol
);
5965 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5967 reg
, reg
, mips_gp_register
);
5968 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5969 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5971 if (reg_needs_delay (mips_gp_register
))
5973 /* We need a nop before loading from $gp. This special
5974 check is required because the lui which starts the main
5975 instruction stream does not refer to $gp, and so will not
5976 insert the nop which may be required. */
5977 macro_build (NULL
, "nop", "");
5979 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5980 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5982 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5986 if (ex
.X_add_number
!= 0)
5988 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5989 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5990 ex
.X_op
= O_constant
;
5991 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5999 if (!mips_opts
.at
&& *used_at
== 1)
6000 as_bad (_("Macro used $at after \".set noat\""));
6003 /* Move the contents of register SOURCE into register DEST. */
6006 move_register (int dest
, int source
)
6008 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6009 instruction specifically requires a 32-bit one. */
6010 if (mips_opts
.micromips
6011 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6012 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6014 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6018 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6019 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6020 The two alternatives are:
6022 Global symbol Local sybmol
6023 ------------- ------------
6024 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6026 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6028 load_got_offset emits the first instruction and add_got_offset
6029 emits the second for a 16-bit offset or add_got_offset_hilo emits
6030 a sequence to add a 32-bit offset using a scratch register. */
6033 load_got_offset (int dest
, expressionS
*local
)
6038 global
.X_add_number
= 0;
6040 relax_start (local
->X_add_symbol
);
6041 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6042 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6044 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6045 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6050 add_got_offset (int dest
, expressionS
*local
)
6054 global
.X_op
= O_constant
;
6055 global
.X_op_symbol
= NULL
;
6056 global
.X_add_symbol
= NULL
;
6057 global
.X_add_number
= local
->X_add_number
;
6059 relax_start (local
->X_add_symbol
);
6060 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6061 dest
, dest
, BFD_RELOC_LO16
);
6063 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6068 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6071 int hold_mips_optimize
;
6073 global
.X_op
= O_constant
;
6074 global
.X_op_symbol
= NULL
;
6075 global
.X_add_symbol
= NULL
;
6076 global
.X_add_number
= local
->X_add_number
;
6078 relax_start (local
->X_add_symbol
);
6079 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6081 /* Set mips_optimize around the lui instruction to avoid
6082 inserting an unnecessary nop after the lw. */
6083 hold_mips_optimize
= mips_optimize
;
6085 macro_build_lui (&global
, tmp
);
6086 mips_optimize
= hold_mips_optimize
;
6087 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6090 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6093 /* Emit a sequence of instructions to emulate a branch likely operation.
6094 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6095 is its complementing branch with the original condition negated.
6096 CALL is set if the original branch specified the link operation.
6097 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6099 Code like this is produced in the noreorder mode:
6104 delay slot (executed only if branch taken)
6112 delay slot (executed only if branch taken)
6115 In the reorder mode the delay slot would be filled with a nop anyway,
6116 so code produced is simply:
6121 This function is used when producing code for the microMIPS ASE that
6122 does not implement branch likely instructions in hardware. */
6125 macro_build_branch_likely (const char *br
, const char *brneg
,
6126 int call
, expressionS
*ep
, const char *fmt
,
6127 unsigned int sreg
, unsigned int treg
)
6129 int noreorder
= mips_opts
.noreorder
;
6132 gas_assert (mips_opts
.micromips
);
6136 micromips_label_expr (&expr1
);
6137 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6138 macro_build (NULL
, "nop", "");
6139 macro_build (ep
, call
? "bal" : "b", "p");
6141 /* Set to true so that append_insn adds a label. */
6142 emit_branch_likely_macro
= TRUE
;
6146 macro_build (ep
, br
, fmt
, sreg
, treg
);
6147 macro_build (NULL
, "nop", "");
6152 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6153 the condition code tested. EP specifies the branch target. */
6156 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6183 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6186 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6187 the register tested. EP specifies the branch target. */
6190 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6192 const char *brneg
= NULL
;
6202 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6206 gas_assert (mips_opts
.micromips
);
6215 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6222 br
= mips_opts
.micromips
? "blez" : "blezl";
6229 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6233 gas_assert (mips_opts
.micromips
);
6241 if (mips_opts
.micromips
&& brneg
)
6242 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6244 macro_build (ep
, br
, "s,p", sreg
);
6247 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6248 TREG as the registers tested. EP specifies the branch target. */
6251 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6252 unsigned int sreg
, unsigned int treg
)
6254 const char *brneg
= NULL
;
6266 br
= mips_opts
.micromips
? "beq" : "beql";
6275 br
= mips_opts
.micromips
? "bne" : "bnel";
6281 if (mips_opts
.micromips
&& brneg
)
6282 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6284 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6289 * This routine implements the seemingly endless macro or synthesized
6290 * instructions and addressing modes in the mips assembly language. Many
6291 * of these macros are simple and are similar to each other. These could
6292 * probably be handled by some kind of table or grammar approach instead of
6293 * this verbose method. Others are not simple macros but are more like
6294 * optimizing code generation.
6295 * One interesting optimization is when several store macros appear
6296 * consecutively that would load AT with the upper half of the same address.
6297 * The ensuing load upper instructions are ommited. This implies some kind
6298 * of global optimization. We currently only optimize within a single macro.
6299 * For many of the load and store macros if the address is specified as a
6300 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6301 * first load register 'at' with zero and use it as the base register. The
6302 * mips assembler simply uses register $zero. Just one tiny optimization
6306 macro (struct mips_cl_insn
*ip
)
6308 unsigned int treg
, sreg
, dreg
, breg
;
6309 unsigned int tempreg
;
6312 expressionS label_expr
;
6331 bfd_reloc_code_real_type r
;
6332 int hold_mips_optimize
;
6334 gas_assert (! mips_opts
.mips16
);
6336 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6337 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6338 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6339 mask
= ip
->insn_mo
->mask
;
6341 label_expr
.X_op
= O_constant
;
6342 label_expr
.X_op_symbol
= NULL
;
6343 label_expr
.X_add_symbol
= NULL
;
6344 label_expr
.X_add_number
= 0;
6346 expr1
.X_op
= O_constant
;
6347 expr1
.X_op_symbol
= NULL
;
6348 expr1
.X_add_symbol
= NULL
;
6349 expr1
.X_add_number
= 1;
6364 if (mips_opts
.micromips
)
6365 micromips_label_expr (&label_expr
);
6367 label_expr
.X_add_number
= 8;
6368 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6370 macro_build (NULL
, "nop", "");
6372 move_register (dreg
, sreg
);
6373 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6374 if (mips_opts
.micromips
)
6375 micromips_add_label ();
6392 if (!mips_opts
.micromips
)
6394 if (imm_expr
.X_op
== O_constant
6395 && imm_expr
.X_add_number
>= -0x200
6396 && imm_expr
.X_add_number
< 0x200)
6398 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6407 if (imm_expr
.X_op
== O_constant
6408 && imm_expr
.X_add_number
>= -0x8000
6409 && imm_expr
.X_add_number
< 0x8000)
6411 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6416 load_register (AT
, &imm_expr
, dbl
);
6417 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6436 if (imm_expr
.X_op
== O_constant
6437 && imm_expr
.X_add_number
>= 0
6438 && imm_expr
.X_add_number
< 0x10000)
6440 if (mask
!= M_NOR_I
)
6441 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6444 macro_build (&imm_expr
, "ori", "t,r,i",
6445 treg
, sreg
, BFD_RELOC_LO16
);
6446 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6452 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6453 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6457 switch (imm_expr
.X_add_number
)
6460 macro_build (NULL
, "nop", "");
6463 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6467 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6468 (int) imm_expr
.X_add_number
);
6471 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6472 (unsigned long) imm_expr
.X_add_number
);
6481 gas_assert (mips_opts
.micromips
);
6482 macro_build_branch_ccl (mask
, &offset_expr
,
6483 EXTRACT_OPERAND (1, BCC
, *ip
));
6490 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6496 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6501 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6508 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6510 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6514 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6515 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6516 &offset_expr
, AT
, ZERO
);
6526 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6532 /* Check for > max integer. */
6533 maxnum
= 0x7fffffff;
6534 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6541 if (imm_expr
.X_op
== O_constant
6542 && imm_expr
.X_add_number
>= maxnum
6543 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6546 /* Result is always false. */
6548 macro_build (NULL
, "nop", "");
6550 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6553 if (imm_expr
.X_op
!= O_constant
)
6554 as_bad (_("Unsupported large constant"));
6555 ++imm_expr
.X_add_number
;
6559 if (mask
== M_BGEL_I
)
6561 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6563 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6564 &offset_expr
, sreg
);
6567 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6569 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6570 &offset_expr
, sreg
);
6573 maxnum
= 0x7fffffff;
6574 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6581 maxnum
= - maxnum
- 1;
6582 if (imm_expr
.X_op
== O_constant
6583 && imm_expr
.X_add_number
<= maxnum
6584 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6587 /* result is always true */
6588 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6589 macro_build (&offset_expr
, "b", "p");
6594 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6595 &offset_expr
, AT
, ZERO
);
6604 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6605 &offset_expr
, ZERO
, treg
);
6609 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6610 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6611 &offset_expr
, AT
, ZERO
);
6620 && imm_expr
.X_op
== O_constant
6621 && imm_expr
.X_add_number
== -1))
6623 if (imm_expr
.X_op
!= O_constant
)
6624 as_bad (_("Unsupported large constant"));
6625 ++imm_expr
.X_add_number
;
6629 if (mask
== M_BGEUL_I
)
6631 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6633 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6634 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6635 &offset_expr
, sreg
, ZERO
);
6640 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6641 &offset_expr
, AT
, ZERO
);
6649 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6651 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6655 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6656 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6657 &offset_expr
, AT
, ZERO
);
6665 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6666 &offset_expr
, sreg
, ZERO
);
6672 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6673 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6674 &offset_expr
, AT
, ZERO
);
6682 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6684 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6688 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6689 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6690 &offset_expr
, AT
, ZERO
);
6697 maxnum
= 0x7fffffff;
6698 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6705 if (imm_expr
.X_op
== O_constant
6706 && imm_expr
.X_add_number
>= maxnum
6707 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6709 if (imm_expr
.X_op
!= O_constant
)
6710 as_bad (_("Unsupported large constant"));
6711 ++imm_expr
.X_add_number
;
6715 if (mask
== M_BLTL_I
)
6717 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6718 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6719 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6720 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6725 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6726 &offset_expr
, AT
, ZERO
);
6734 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6735 &offset_expr
, sreg
, ZERO
);
6741 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6742 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6743 &offset_expr
, AT
, ZERO
);
6752 && imm_expr
.X_op
== O_constant
6753 && imm_expr
.X_add_number
== -1))
6755 if (imm_expr
.X_op
!= O_constant
)
6756 as_bad (_("Unsupported large constant"));
6757 ++imm_expr
.X_add_number
;
6761 if (mask
== M_BLTUL_I
)
6763 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6765 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6766 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6767 &offset_expr
, sreg
, ZERO
);
6772 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6773 &offset_expr
, AT
, ZERO
);
6781 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6783 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6787 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6788 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6789 &offset_expr
, AT
, ZERO
);
6799 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6800 &offset_expr
, ZERO
, treg
);
6804 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6805 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6806 &offset_expr
, AT
, ZERO
);
6812 /* Use unsigned arithmetic. */
6816 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6818 as_bad (_("Unsupported large constant"));
6823 pos
= imm_expr
.X_add_number
;
6824 size
= imm2_expr
.X_add_number
;
6829 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6832 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6834 as_bad (_("Improper extract size (%lu, position %lu)"),
6835 (unsigned long) size
, (unsigned long) pos
);
6839 if (size
<= 32 && pos
< 32)
6844 else if (size
<= 32)
6854 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6861 /* Use unsigned arithmetic. */
6865 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6867 as_bad (_("Unsupported large constant"));
6872 pos
= imm_expr
.X_add_number
;
6873 size
= imm2_expr
.X_add_number
;
6878 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6881 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6883 as_bad (_("Improper insert size (%lu, position %lu)"),
6884 (unsigned long) size
, (unsigned long) pos
);
6888 if (pos
< 32 && (pos
+ size
- 1) < 32)
6903 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6904 (int) (pos
+ size
- 1));
6920 as_warn (_("Divide by zero."));
6922 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6924 macro_build (NULL
, "break", BRK_FMT
, 7);
6931 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6932 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6936 if (mips_opts
.micromips
)
6937 micromips_label_expr (&label_expr
);
6939 label_expr
.X_add_number
= 8;
6940 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6941 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6942 macro_build (NULL
, "break", BRK_FMT
, 7);
6943 if (mips_opts
.micromips
)
6944 micromips_add_label ();
6946 expr1
.X_add_number
= -1;
6948 load_register (AT
, &expr1
, dbl
);
6949 if (mips_opts
.micromips
)
6950 micromips_label_expr (&label_expr
);
6952 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6953 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6956 expr1
.X_add_number
= 1;
6957 load_register (AT
, &expr1
, dbl
);
6958 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6962 expr1
.X_add_number
= 0x80000000;
6963 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6967 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6968 /* We want to close the noreorder block as soon as possible, so
6969 that later insns are available for delay slot filling. */
6974 if (mips_opts
.micromips
)
6975 micromips_label_expr (&label_expr
);
6977 label_expr
.X_add_number
= 8;
6978 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6979 macro_build (NULL
, "nop", "");
6981 /* We want to close the noreorder block as soon as possible, so
6982 that later insns are available for delay slot filling. */
6985 macro_build (NULL
, "break", BRK_FMT
, 6);
6987 if (mips_opts
.micromips
)
6988 micromips_add_label ();
6989 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7028 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7030 as_warn (_("Divide by zero."));
7032 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7034 macro_build (NULL
, "break", BRK_FMT
, 7);
7037 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7039 if (strcmp (s2
, "mflo") == 0)
7040 move_register (dreg
, sreg
);
7042 move_register (dreg
, ZERO
);
7045 if (imm_expr
.X_op
== O_constant
7046 && imm_expr
.X_add_number
== -1
7047 && s
[strlen (s
) - 1] != 'u')
7049 if (strcmp (s2
, "mflo") == 0)
7051 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7054 move_register (dreg
, ZERO
);
7059 load_register (AT
, &imm_expr
, dbl
);
7060 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7061 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7083 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7084 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7085 /* We want to close the noreorder block as soon as possible, so
7086 that later insns are available for delay slot filling. */
7091 if (mips_opts
.micromips
)
7092 micromips_label_expr (&label_expr
);
7094 label_expr
.X_add_number
= 8;
7095 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7096 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7098 /* We want to close the noreorder block as soon as possible, so
7099 that later insns are available for delay slot filling. */
7101 macro_build (NULL
, "break", BRK_FMT
, 7);
7102 if (mips_opts
.micromips
)
7103 micromips_add_label ();
7105 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7117 /* Load the address of a symbol into a register. If breg is not
7118 zero, we then add a base register to it. */
7120 if (dbl
&& HAVE_32BIT_GPRS
)
7121 as_warn (_("dla used to load 32-bit register"));
7123 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7124 as_warn (_("la used to load 64-bit address"));
7126 if (offset_expr
.X_op
== O_constant
7127 && offset_expr
.X_add_number
>= -0x8000
7128 && offset_expr
.X_add_number
< 0x8000)
7130 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7131 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7135 if (mips_opts
.at
&& (treg
== breg
))
7145 if (offset_expr
.X_op
!= O_symbol
7146 && offset_expr
.X_op
!= O_constant
)
7148 as_bad (_("Expression too complex"));
7149 offset_expr
.X_op
= O_constant
;
7152 if (offset_expr
.X_op
== O_constant
)
7153 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7154 else if (mips_pic
== NO_PIC
)
7156 /* If this is a reference to a GP relative symbol, we want
7157 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7159 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7160 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7161 If we have a constant, we need two instructions anyhow,
7162 so we may as well always use the latter form.
7164 With 64bit address space and a usable $at we want
7165 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7166 lui $at,<sym> (BFD_RELOC_HI16_S)
7167 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7168 daddiu $at,<sym> (BFD_RELOC_LO16)
7170 daddu $tempreg,$tempreg,$at
7172 If $at is already in use, we use a path which is suboptimal
7173 on superscalar processors.
7174 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7175 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7177 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7179 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7181 For GP relative symbols in 64bit address space we can use
7182 the same sequence as in 32bit address space. */
7183 if (HAVE_64BIT_SYMBOLS
)
7185 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7186 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7188 relax_start (offset_expr
.X_add_symbol
);
7189 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7190 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7194 if (used_at
== 0 && mips_opts
.at
)
7196 macro_build (&offset_expr
, "lui", LUI_FMT
,
7197 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7198 macro_build (&offset_expr
, "lui", LUI_FMT
,
7199 AT
, BFD_RELOC_HI16_S
);
7200 macro_build (&offset_expr
, "daddiu", "t,r,j",
7201 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7202 macro_build (&offset_expr
, "daddiu", "t,r,j",
7203 AT
, AT
, BFD_RELOC_LO16
);
7204 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7205 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7210 macro_build (&offset_expr
, "lui", LUI_FMT
,
7211 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7212 macro_build (&offset_expr
, "daddiu", "t,r,j",
7213 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7214 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7215 macro_build (&offset_expr
, "daddiu", "t,r,j",
7216 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7217 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7218 macro_build (&offset_expr
, "daddiu", "t,r,j",
7219 tempreg
, tempreg
, BFD_RELOC_LO16
);
7222 if (mips_relax
.sequence
)
7227 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7228 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7230 relax_start (offset_expr
.X_add_symbol
);
7231 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7232 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7235 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7236 as_bad (_("Offset too large"));
7237 macro_build_lui (&offset_expr
, tempreg
);
7238 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7239 tempreg
, tempreg
, BFD_RELOC_LO16
);
7240 if (mips_relax
.sequence
)
7244 else if (!mips_big_got
&& !HAVE_NEWABI
)
7246 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7248 /* If this is a reference to an external symbol, and there
7249 is no constant, we want
7250 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7251 or for lca or if tempreg is PIC_CALL_REG
7252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7253 For a local symbol, we want
7254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7256 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7258 If we have a small constant, and this is a reference to
7259 an external symbol, we want
7260 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7262 addiu $tempreg,$tempreg,<constant>
7263 For a local symbol, we want the same instruction
7264 sequence, but we output a BFD_RELOC_LO16 reloc on the
7267 If we have a large constant, and this is a reference to
7268 an external symbol, we want
7269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7270 lui $at,<hiconstant>
7271 addiu $at,$at,<loconstant>
7272 addu $tempreg,$tempreg,$at
7273 For a local symbol, we want the same instruction
7274 sequence, but we output a BFD_RELOC_LO16 reloc on the
7278 if (offset_expr
.X_add_number
== 0)
7280 if (mips_pic
== SVR4_PIC
7282 && (call
|| tempreg
== PIC_CALL_REG
))
7283 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7285 relax_start (offset_expr
.X_add_symbol
);
7286 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7287 lw_reloc_type
, mips_gp_register
);
7290 /* We're going to put in an addu instruction using
7291 tempreg, so we may as well insert the nop right
7296 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7297 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7299 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7300 tempreg
, tempreg
, BFD_RELOC_LO16
);
7302 /* FIXME: If breg == 0, and the next instruction uses
7303 $tempreg, then if this variant case is used an extra
7304 nop will be generated. */
7306 else if (offset_expr
.X_add_number
>= -0x8000
7307 && offset_expr
.X_add_number
< 0x8000)
7309 load_got_offset (tempreg
, &offset_expr
);
7311 add_got_offset (tempreg
, &offset_expr
);
7315 expr1
.X_add_number
= offset_expr
.X_add_number
;
7316 offset_expr
.X_add_number
=
7317 SEXT_16BIT (offset_expr
.X_add_number
);
7318 load_got_offset (tempreg
, &offset_expr
);
7319 offset_expr
.X_add_number
= expr1
.X_add_number
;
7320 /* If we are going to add in a base register, and the
7321 target register and the base register are the same,
7322 then we are using AT as a temporary register. Since
7323 we want to load the constant into AT, we add our
7324 current AT (from the global offset table) and the
7325 register into the register now, and pretend we were
7326 not using a base register. */
7330 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7335 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7339 else if (!mips_big_got
&& HAVE_NEWABI
)
7341 int add_breg_early
= 0;
7343 /* If this is a reference to an external, and there is no
7344 constant, or local symbol (*), with or without a
7346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7347 or for lca or if tempreg is PIC_CALL_REG
7348 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7350 If we have a small constant, and this is a reference to
7351 an external symbol, we want
7352 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7353 addiu $tempreg,$tempreg,<constant>
7355 If we have a large constant, and this is a reference to
7356 an external symbol, we want
7357 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7358 lui $at,<hiconstant>
7359 addiu $at,$at,<loconstant>
7360 addu $tempreg,$tempreg,$at
7362 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7363 local symbols, even though it introduces an additional
7366 if (offset_expr
.X_add_number
)
7368 expr1
.X_add_number
= offset_expr
.X_add_number
;
7369 offset_expr
.X_add_number
= 0;
7371 relax_start (offset_expr
.X_add_symbol
);
7372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7373 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7375 if (expr1
.X_add_number
>= -0x8000
7376 && expr1
.X_add_number
< 0x8000)
7378 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7379 tempreg
, tempreg
, BFD_RELOC_LO16
);
7381 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7383 /* If we are going to add in a base register, and the
7384 target register and the base register are the same,
7385 then we are using AT as a temporary register. Since
7386 we want to load the constant into AT, we add our
7387 current AT (from the global offset table) and the
7388 register into the register now, and pretend we were
7389 not using a base register. */
7394 gas_assert (tempreg
== AT
);
7395 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7401 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7408 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7411 offset_expr
.X_add_number
= expr1
.X_add_number
;
7413 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7414 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7417 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7418 treg
, tempreg
, breg
);
7424 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7426 relax_start (offset_expr
.X_add_symbol
);
7427 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7428 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7430 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7431 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7436 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7437 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7440 else if (mips_big_got
&& !HAVE_NEWABI
)
7443 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7444 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7445 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7447 /* This is the large GOT case. If this is a reference to an
7448 external symbol, and there is no constant, we want
7449 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7450 addu $tempreg,$tempreg,$gp
7451 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7452 or for lca or if tempreg is PIC_CALL_REG
7453 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7454 addu $tempreg,$tempreg,$gp
7455 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7456 For a local symbol, we want
7457 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7459 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7461 If we have a small constant, and this is a reference to
7462 an external symbol, we want
7463 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7464 addu $tempreg,$tempreg,$gp
7465 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7467 addiu $tempreg,$tempreg,<constant>
7468 For a local symbol, we want
7469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7471 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7473 If we have a large constant, and this is a reference to
7474 an external symbol, we want
7475 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7476 addu $tempreg,$tempreg,$gp
7477 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7478 lui $at,<hiconstant>
7479 addiu $at,$at,<loconstant>
7480 addu $tempreg,$tempreg,$at
7481 For a local symbol, we want
7482 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7483 lui $at,<hiconstant>
7484 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7485 addu $tempreg,$tempreg,$at
7488 expr1
.X_add_number
= offset_expr
.X_add_number
;
7489 offset_expr
.X_add_number
= 0;
7490 relax_start (offset_expr
.X_add_symbol
);
7491 gpdelay
= reg_needs_delay (mips_gp_register
);
7492 if (expr1
.X_add_number
== 0 && breg
== 0
7493 && (call
|| tempreg
== PIC_CALL_REG
))
7495 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7496 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7498 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7500 tempreg
, tempreg
, mips_gp_register
);
7501 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7502 tempreg
, lw_reloc_type
, tempreg
);
7503 if (expr1
.X_add_number
== 0)
7507 /* We're going to put in an addu instruction using
7508 tempreg, so we may as well insert the nop right
7513 else if (expr1
.X_add_number
>= -0x8000
7514 && expr1
.X_add_number
< 0x8000)
7517 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7518 tempreg
, tempreg
, BFD_RELOC_LO16
);
7522 /* If we are going to add in a base register, and the
7523 target register and the base register are the same,
7524 then we are using AT as a temporary register. Since
7525 we want to load the constant into AT, we add our
7526 current AT (from the global offset table) and the
7527 register into the register now, and pretend we were
7528 not using a base register. */
7533 gas_assert (tempreg
== AT
);
7535 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7540 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7545 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7550 /* This is needed because this instruction uses $gp, but
7551 the first instruction on the main stream does not. */
7552 macro_build (NULL
, "nop", "");
7555 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7556 local_reloc_type
, mips_gp_register
);
7557 if (expr1
.X_add_number
>= -0x8000
7558 && expr1
.X_add_number
< 0x8000)
7561 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7562 tempreg
, tempreg
, BFD_RELOC_LO16
);
7563 /* FIXME: If add_number is 0, and there was no base
7564 register, the external symbol case ended with a load,
7565 so if the symbol turns out to not be external, and
7566 the next instruction uses tempreg, an unnecessary nop
7567 will be inserted. */
7573 /* We must add in the base register now, as in the
7574 external symbol case. */
7575 gas_assert (tempreg
== AT
);
7577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7580 /* We set breg to 0 because we have arranged to add
7581 it in in both cases. */
7585 macro_build_lui (&expr1
, AT
);
7586 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7587 AT
, AT
, BFD_RELOC_LO16
);
7588 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7589 tempreg
, tempreg
, AT
);
7594 else if (mips_big_got
&& HAVE_NEWABI
)
7596 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7597 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7598 int add_breg_early
= 0;
7600 /* This is the large GOT case. If this is a reference to an
7601 external symbol, and there is no constant, we want
7602 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7603 add $tempreg,$tempreg,$gp
7604 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7605 or for lca or if tempreg is PIC_CALL_REG
7606 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7607 add $tempreg,$tempreg,$gp
7608 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7610 If we have a small constant, and this is a reference to
7611 an external symbol, we want
7612 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7613 add $tempreg,$tempreg,$gp
7614 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7615 addi $tempreg,$tempreg,<constant>
7617 If we have a large constant, and this is a reference to
7618 an external symbol, we want
7619 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7620 addu $tempreg,$tempreg,$gp
7621 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7622 lui $at,<hiconstant>
7623 addi $at,$at,<loconstant>
7624 add $tempreg,$tempreg,$at
7626 If we have NewABI, and we know it's a local symbol, we want
7627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7628 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7629 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7631 relax_start (offset_expr
.X_add_symbol
);
7633 expr1
.X_add_number
= offset_expr
.X_add_number
;
7634 offset_expr
.X_add_number
= 0;
7636 if (expr1
.X_add_number
== 0 && breg
== 0
7637 && (call
|| tempreg
== PIC_CALL_REG
))
7639 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7640 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7642 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7643 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7644 tempreg
, tempreg
, mips_gp_register
);
7645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7646 tempreg
, lw_reloc_type
, tempreg
);
7648 if (expr1
.X_add_number
== 0)
7650 else if (expr1
.X_add_number
>= -0x8000
7651 && expr1
.X_add_number
< 0x8000)
7653 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7654 tempreg
, tempreg
, BFD_RELOC_LO16
);
7656 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7658 /* If we are going to add in a base register, and the
7659 target register and the base register are the same,
7660 then we are using AT as a temporary register. Since
7661 we want to load the constant into AT, we add our
7662 current AT (from the global offset table) and the
7663 register into the register now, and pretend we were
7664 not using a base register. */
7669 gas_assert (tempreg
== AT
);
7670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7676 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7677 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7682 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7685 offset_expr
.X_add_number
= expr1
.X_add_number
;
7686 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7687 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7688 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7689 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7692 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7693 treg
, tempreg
, breg
);
7703 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7707 gas_assert (!mips_opts
.micromips
);
7709 unsigned long temp
= (treg
<< 16) | (0x01);
7710 macro_build (NULL
, "c2", "C", temp
);
7715 gas_assert (!mips_opts
.micromips
);
7717 unsigned long temp
= (0x02);
7718 macro_build (NULL
, "c2", "C", temp
);
7723 gas_assert (!mips_opts
.micromips
);
7725 unsigned long temp
= (treg
<< 16) | (0x02);
7726 macro_build (NULL
, "c2", "C", temp
);
7731 gas_assert (!mips_opts
.micromips
);
7732 macro_build (NULL
, "c2", "C", 3);
7736 gas_assert (!mips_opts
.micromips
);
7738 unsigned long temp
= (treg
<< 16) | 0x03;
7739 macro_build (NULL
, "c2", "C", temp
);
7744 /* The j instruction may not be used in PIC code, since it
7745 requires an absolute address. We convert it to a b
7747 if (mips_pic
== NO_PIC
)
7748 macro_build (&offset_expr
, "j", "a");
7750 macro_build (&offset_expr
, "b", "p");
7753 /* The jal instructions must be handled as macros because when
7754 generating PIC code they expand to multi-instruction
7755 sequences. Normally they are simple instructions. */
7760 gas_assert (mips_opts
.micromips
);
7768 if (mips_pic
== NO_PIC
)
7770 s
= jals
? "jalrs" : "jalr";
7771 if (mips_opts
.micromips
&& dreg
== RA
)
7772 macro_build (NULL
, s
, "mj", sreg
);
7774 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7778 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7779 && mips_cprestore_offset
>= 0);
7781 if (sreg
!= PIC_CALL_REG
)
7782 as_warn (_("MIPS PIC call to register other than $25"));
7784 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7785 ? "jalrs" : "jalr");
7786 if (mips_opts
.micromips
&& dreg
== RA
)
7787 macro_build (NULL
, s
, "mj", sreg
);
7789 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7790 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7792 if (mips_cprestore_offset
< 0)
7793 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7796 if (!mips_frame_reg_valid
)
7798 as_warn (_("No .frame pseudo-op used in PIC code"));
7799 /* Quiet this warning. */
7800 mips_frame_reg_valid
= 1;
7802 if (!mips_cprestore_valid
)
7804 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7805 /* Quiet this warning. */
7806 mips_cprestore_valid
= 1;
7808 if (mips_opts
.noreorder
)
7809 macro_build (NULL
, "nop", "");
7810 expr1
.X_add_number
= mips_cprestore_offset
;
7811 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7814 HAVE_64BIT_ADDRESSES
);
7822 gas_assert (mips_opts
.micromips
);
7826 if (mips_pic
== NO_PIC
)
7827 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7828 else if (mips_pic
== SVR4_PIC
)
7830 /* If this is a reference to an external symbol, and we are
7831 using a small GOT, we want
7832 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7836 lw $gp,cprestore($sp)
7837 The cprestore value is set using the .cprestore
7838 pseudo-op. If we are using a big GOT, we want
7839 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7841 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7845 lw $gp,cprestore($sp)
7846 If the symbol is not external, we want
7847 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7849 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7852 lw $gp,cprestore($sp)
7854 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7855 sequences above, minus nops, unless the symbol is local,
7856 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7862 relax_start (offset_expr
.X_add_symbol
);
7863 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7864 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7867 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7868 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7874 relax_start (offset_expr
.X_add_symbol
);
7875 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7876 BFD_RELOC_MIPS_CALL_HI16
);
7877 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7878 PIC_CALL_REG
, mips_gp_register
);
7879 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7880 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7883 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7884 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7886 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7887 PIC_CALL_REG
, PIC_CALL_REG
,
7888 BFD_RELOC_MIPS_GOT_OFST
);
7892 macro_build_jalr (&offset_expr
, 0);
7896 relax_start (offset_expr
.X_add_symbol
);
7899 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7900 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7909 gpdelay
= reg_needs_delay (mips_gp_register
);
7910 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7911 BFD_RELOC_MIPS_CALL_HI16
);
7912 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7913 PIC_CALL_REG
, mips_gp_register
);
7914 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7915 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7920 macro_build (NULL
, "nop", "");
7922 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7923 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7926 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7927 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7929 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7931 if (mips_cprestore_offset
< 0)
7932 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7935 if (!mips_frame_reg_valid
)
7937 as_warn (_("No .frame pseudo-op used in PIC code"));
7938 /* Quiet this warning. */
7939 mips_frame_reg_valid
= 1;
7941 if (!mips_cprestore_valid
)
7943 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7944 /* Quiet this warning. */
7945 mips_cprestore_valid
= 1;
7947 if (mips_opts
.noreorder
)
7948 macro_build (NULL
, "nop", "");
7949 expr1
.X_add_number
= mips_cprestore_offset
;
7950 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7953 HAVE_64BIT_ADDRESSES
);
7957 else if (mips_pic
== VXWORKS_PIC
)
7958 as_bad (_("Non-PIC jump used in PIC library"));
7968 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7976 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8007 gas_assert (!mips_opts
.micromips
);
8010 /* Itbl support may require additional care here. */
8017 /* Itbl support may require additional care here. */
8025 off12
= mips_opts
.micromips
;
8026 /* Itbl support may require additional care here. */
8031 gas_assert (!mips_opts
.micromips
);
8034 /* Itbl support may require additional care here. */
8042 off12
= mips_opts
.micromips
;
8049 off12
= mips_opts
.micromips
;
8055 /* Itbl support may require additional care here. */
8063 off12
= mips_opts
.micromips
;
8064 /* Itbl support may require additional care here. */
8071 /* Itbl support may require additional care here. */
8079 off12
= mips_opts
.micromips
;
8086 off12
= mips_opts
.micromips
;
8093 off12
= mips_opts
.micromips
;
8100 off12
= mips_opts
.micromips
;
8107 off12
= mips_opts
.micromips
;
8112 gas_assert (mips_opts
.micromips
);
8121 gas_assert (mips_opts
.micromips
);
8130 gas_assert (mips_opts
.micromips
);
8138 gas_assert (mips_opts
.micromips
);
8145 if (breg
== treg
+ lp
)
8148 tempreg
= treg
+ lp
;
8168 gas_assert (!mips_opts
.micromips
);
8171 /* Itbl support may require additional care here. */
8178 /* Itbl support may require additional care here. */
8186 off12
= mips_opts
.micromips
;
8187 /* Itbl support may require additional care here. */
8192 gas_assert (!mips_opts
.micromips
);
8195 /* Itbl support may require additional care here. */
8203 off12
= mips_opts
.micromips
;
8210 off12
= mips_opts
.micromips
;
8217 off12
= mips_opts
.micromips
;
8224 off12
= mips_opts
.micromips
;
8230 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8231 off12
= mips_opts
.micromips
;
8237 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8238 off12
= mips_opts
.micromips
;
8245 /* Itbl support may require additional care here. */
8252 off12
= mips_opts
.micromips
;
8253 /* Itbl support may require additional care here. */
8258 gas_assert (!mips_opts
.micromips
);
8261 /* Itbl support may require additional care here. */
8269 off12
= mips_opts
.micromips
;
8276 off12
= mips_opts
.micromips
;
8281 gas_assert (mips_opts
.micromips
);
8289 gas_assert (mips_opts
.micromips
);
8297 gas_assert (mips_opts
.micromips
);
8305 gas_assert (mips_opts
.micromips
);
8314 if (offset_expr
.X_op
!= O_constant
8315 && offset_expr
.X_op
!= O_symbol
)
8317 as_bad (_("Expression too complex"));
8318 offset_expr
.X_op
= O_constant
;
8321 if (HAVE_32BIT_ADDRESSES
8322 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8326 sprintf_vma (value
, offset_expr
.X_add_number
);
8327 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8330 /* A constant expression in PIC code can be handled just as it
8331 is in non PIC code. */
8332 if (offset_expr
.X_op
== O_constant
)
8336 expr1
.X_add_number
= offset_expr
.X_add_number
;
8337 normalize_address_expr (&expr1
);
8338 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8340 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8341 & ~(bfd_vma
) 0xffff);
8344 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8346 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8347 & ~(bfd_vma
) 0xfff);
8352 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8355 tempreg
, tempreg
, breg
);
8360 if (offset_expr
.X_add_number
== 0)
8363 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8364 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8365 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8368 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8370 macro_build (NULL
, s
, fmt
,
8371 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8373 else if (off12
|| off0
)
8375 /* A 12-bit or 0-bit offset field is too narrow to be used
8376 for a low-part relocation, so load the whole address into
8377 the auxillary register. In the case of "A(b)" addresses,
8378 we first load absolute address "A" into the register and
8379 then add base register "b". In the case of "o(b)" addresses,
8380 we simply need to add 16-bit offset "o" to base register "b", and
8381 offset_reloc already contains the relocations associated
8385 load_address (tempreg
, &offset_expr
, &used_at
);
8387 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8388 tempreg
, tempreg
, breg
);
8391 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8393 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8394 expr1
.X_add_number
= 0;
8396 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8398 macro_build (NULL
, s
, fmt
,
8399 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8401 else if (mips_pic
== NO_PIC
)
8403 /* If this is a reference to a GP relative symbol, and there
8404 is no base register, we want
8405 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8406 Otherwise, if there is no base register, we want
8407 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8408 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8409 If we have a constant, we need two instructions anyhow,
8410 so we always use the latter form.
8412 If we have a base register, and this is a reference to a
8413 GP relative symbol, we want
8414 addu $tempreg,$breg,$gp
8415 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8417 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8418 addu $tempreg,$tempreg,$breg
8419 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8420 With a constant we always use the latter case.
8422 With 64bit address space and no base register and $at usable,
8424 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8425 lui $at,<sym> (BFD_RELOC_HI16_S)
8426 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8429 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8430 If we have a base register, we want
8431 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8432 lui $at,<sym> (BFD_RELOC_HI16_S)
8433 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8437 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8439 Without $at we can't generate the optimal path for superscalar
8440 processors here since this would require two temporary registers.
8441 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8442 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8444 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8446 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8447 If we have a base register, we want
8448 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8449 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8451 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8453 daddu $tempreg,$tempreg,$breg
8454 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8456 For GP relative symbols in 64bit address space we can use
8457 the same sequence as in 32bit address space. */
8458 if (HAVE_64BIT_SYMBOLS
)
8460 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8461 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8463 relax_start (offset_expr
.X_add_symbol
);
8466 macro_build (&offset_expr
, s
, fmt
, treg
,
8467 BFD_RELOC_GPREL16
, mips_gp_register
);
8471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8472 tempreg
, breg
, mips_gp_register
);
8473 macro_build (&offset_expr
, s
, fmt
, treg
,
8474 BFD_RELOC_GPREL16
, tempreg
);
8479 if (used_at
== 0 && mips_opts
.at
)
8481 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8482 BFD_RELOC_MIPS_HIGHEST
);
8483 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8485 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8486 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8488 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8489 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8490 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8491 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8497 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8498 BFD_RELOC_MIPS_HIGHEST
);
8499 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8500 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8501 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8502 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8503 tempreg
, BFD_RELOC_HI16_S
);
8504 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8506 macro_build (NULL
, "daddu", "d,v,t",
8507 tempreg
, tempreg
, breg
);
8508 macro_build (&offset_expr
, s
, fmt
, treg
,
8509 BFD_RELOC_LO16
, tempreg
);
8512 if (mips_relax
.sequence
)
8519 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8520 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8522 relax_start (offset_expr
.X_add_symbol
);
8523 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8527 macro_build_lui (&offset_expr
, tempreg
);
8528 macro_build (&offset_expr
, s
, fmt
, treg
,
8529 BFD_RELOC_LO16
, tempreg
);
8530 if (mips_relax
.sequence
)
8535 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8536 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8538 relax_start (offset_expr
.X_add_symbol
);
8539 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8540 tempreg
, breg
, mips_gp_register
);
8541 macro_build (&offset_expr
, s
, fmt
, treg
,
8542 BFD_RELOC_GPREL16
, tempreg
);
8545 macro_build_lui (&offset_expr
, tempreg
);
8546 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8547 tempreg
, tempreg
, breg
);
8548 macro_build (&offset_expr
, s
, fmt
, treg
,
8549 BFD_RELOC_LO16
, tempreg
);
8550 if (mips_relax
.sequence
)
8554 else if (!mips_big_got
)
8556 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8558 /* If this is a reference to an external symbol, we want
8559 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8561 <op> $treg,0($tempreg)
8563 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8565 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8566 <op> $treg,0($tempreg)
8569 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8570 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8572 If there is a base register, we add it to $tempreg before
8573 the <op>. If there is a constant, we stick it in the
8574 <op> instruction. We don't handle constants larger than
8575 16 bits, because we have no way to load the upper 16 bits
8576 (actually, we could handle them for the subset of cases
8577 in which we are not using $at). */
8578 gas_assert (offset_expr
.X_op
== O_symbol
);
8581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8582 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8584 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8585 tempreg
, tempreg
, breg
);
8586 macro_build (&offset_expr
, s
, fmt
, treg
,
8587 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8590 expr1
.X_add_number
= offset_expr
.X_add_number
;
8591 offset_expr
.X_add_number
= 0;
8592 if (expr1
.X_add_number
< -0x8000
8593 || expr1
.X_add_number
>= 0x8000)
8594 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8595 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8596 lw_reloc_type
, mips_gp_register
);
8598 relax_start (offset_expr
.X_add_symbol
);
8600 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8601 tempreg
, BFD_RELOC_LO16
);
8604 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8605 tempreg
, tempreg
, breg
);
8606 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8608 else if (mips_big_got
&& !HAVE_NEWABI
)
8612 /* If this is a reference to an external symbol, we want
8613 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8614 addu $tempreg,$tempreg,$gp
8615 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8616 <op> $treg,0($tempreg)
8618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8620 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8621 <op> $treg,0($tempreg)
8622 If there is a base register, we add it to $tempreg before
8623 the <op>. If there is a constant, we stick it in the
8624 <op> instruction. We don't handle constants larger than
8625 16 bits, because we have no way to load the upper 16 bits
8626 (actually, we could handle them for the subset of cases
8627 in which we are not using $at). */
8628 gas_assert (offset_expr
.X_op
== O_symbol
);
8629 expr1
.X_add_number
= offset_expr
.X_add_number
;
8630 offset_expr
.X_add_number
= 0;
8631 if (expr1
.X_add_number
< -0x8000
8632 || expr1
.X_add_number
>= 0x8000)
8633 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8634 gpdelay
= reg_needs_delay (mips_gp_register
);
8635 relax_start (offset_expr
.X_add_symbol
);
8636 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8637 BFD_RELOC_MIPS_GOT_HI16
);
8638 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8640 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8641 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8644 macro_build (NULL
, "nop", "");
8645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8646 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8648 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8649 tempreg
, BFD_RELOC_LO16
);
8653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8654 tempreg
, tempreg
, breg
);
8655 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8657 else if (mips_big_got
&& HAVE_NEWABI
)
8659 /* If this is a reference to an external symbol, we want
8660 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8661 add $tempreg,$tempreg,$gp
8662 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8663 <op> $treg,<ofst>($tempreg)
8664 Otherwise, for local symbols, we want:
8665 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8666 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8667 gas_assert (offset_expr
.X_op
== O_symbol
);
8668 expr1
.X_add_number
= offset_expr
.X_add_number
;
8669 offset_expr
.X_add_number
= 0;
8670 if (expr1
.X_add_number
< -0x8000
8671 || expr1
.X_add_number
>= 0x8000)
8672 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8673 relax_start (offset_expr
.X_add_symbol
);
8674 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8675 BFD_RELOC_MIPS_GOT_HI16
);
8676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8678 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8679 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8682 tempreg
, tempreg
, breg
);
8683 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8686 offset_expr
.X_add_number
= expr1
.X_add_number
;
8687 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8688 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8690 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8691 tempreg
, tempreg
, breg
);
8692 macro_build (&offset_expr
, s
, fmt
, treg
,
8693 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8703 load_register (treg
, &imm_expr
, 0);
8707 load_register (treg
, &imm_expr
, 1);
8711 if (imm_expr
.X_op
== O_constant
)
8714 load_register (AT
, &imm_expr
, 0);
8715 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8720 gas_assert (offset_expr
.X_op
== O_symbol
8721 && strcmp (segment_name (S_GET_SEGMENT
8722 (offset_expr
.X_add_symbol
)),
8724 && offset_expr
.X_add_number
== 0);
8725 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8726 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8731 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8732 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8733 order 32 bits of the value and the low order 32 bits are either
8734 zero or in OFFSET_EXPR. */
8735 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8737 if (HAVE_64BIT_GPRS
)
8738 load_register (treg
, &imm_expr
, 1);
8743 if (target_big_endian
)
8755 load_register (hreg
, &imm_expr
, 0);
8758 if (offset_expr
.X_op
== O_absent
)
8759 move_register (lreg
, 0);
8762 gas_assert (offset_expr
.X_op
== O_constant
);
8763 load_register (lreg
, &offset_expr
, 0);
8770 /* We know that sym is in the .rdata section. First we get the
8771 upper 16 bits of the address. */
8772 if (mips_pic
== NO_PIC
)
8774 macro_build_lui (&offset_expr
, AT
);
8779 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8780 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8784 /* Now we load the register(s). */
8785 if (HAVE_64BIT_GPRS
)
8788 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8793 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8796 /* FIXME: How in the world do we deal with the possible
8798 offset_expr
.X_add_number
+= 4;
8799 macro_build (&offset_expr
, "lw", "t,o(b)",
8800 treg
+ 1, BFD_RELOC_LO16
, AT
);
8806 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8807 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8808 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8809 the value and the low order 32 bits are either zero or in
8811 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8814 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8815 if (HAVE_64BIT_FPRS
)
8817 gas_assert (HAVE_64BIT_GPRS
);
8818 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8822 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8823 if (offset_expr
.X_op
== O_absent
)
8824 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8827 gas_assert (offset_expr
.X_op
== O_constant
);
8828 load_register (AT
, &offset_expr
, 0);
8829 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8835 gas_assert (offset_expr
.X_op
== O_symbol
8836 && offset_expr
.X_add_number
== 0);
8837 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8838 if (strcmp (s
, ".lit8") == 0)
8840 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8842 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8843 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8846 breg
= mips_gp_register
;
8847 r
= BFD_RELOC_MIPS_LITERAL
;
8852 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8854 if (mips_pic
!= NO_PIC
)
8855 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8856 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8859 /* FIXME: This won't work for a 64 bit address. */
8860 macro_build_lui (&offset_expr
, AT
);
8863 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8865 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8866 treg
, BFD_RELOC_LO16
, AT
);
8875 /* Even on a big endian machine $fn comes before $fn+1. We have
8876 to adjust when loading from memory. */
8879 gas_assert (!mips_opts
.micromips
);
8880 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8881 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8882 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8883 /* FIXME: A possible overflow which I don't know how to deal
8885 offset_expr
.X_add_number
+= 4;
8886 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8887 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8891 gas_assert (!mips_opts
.micromips
);
8892 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8893 /* Even on a big endian machine $fn comes before $fn+1. We have
8894 to adjust when storing to memory. */
8895 macro_build (&offset_expr
, "swc1", "T,o(b)",
8896 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8897 offset_expr
.X_add_number
+= 4;
8898 macro_build (&offset_expr
, "swc1", "T,o(b)",
8899 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8903 gas_assert (!mips_opts
.micromips
);
8905 * The MIPS assembler seems to check for X_add_number not
8906 * being double aligned and generating:
8909 * addiu at,at,%lo(foo+1)
8912 * But, the resulting address is the same after relocation so why
8913 * generate the extra instruction?
8915 /* Itbl support may require additional care here. */
8918 if (mips_opts
.isa
!= ISA_MIPS1
)
8927 gas_assert (!mips_opts
.micromips
);
8928 /* Itbl support may require additional care here. */
8931 if (mips_opts
.isa
!= ISA_MIPS1
)
8941 if (HAVE_64BIT_GPRS
)
8951 if (HAVE_64BIT_GPRS
)
8959 if (offset_expr
.X_op
!= O_symbol
8960 && offset_expr
.X_op
!= O_constant
)
8962 as_bad (_("Expression too complex"));
8963 offset_expr
.X_op
= O_constant
;
8966 if (HAVE_32BIT_ADDRESSES
8967 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8971 sprintf_vma (value
, offset_expr
.X_add_number
);
8972 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8975 /* Even on a big endian machine $fn comes before $fn+1. We have
8976 to adjust when loading from memory. We set coproc if we must
8977 load $fn+1 first. */
8978 /* Itbl support may require additional care here. */
8979 if (!target_big_endian
)
8982 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8984 /* If this is a reference to a GP relative symbol, we want
8985 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8986 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8987 If we have a base register, we use this
8989 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8990 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8991 If this is not a GP relative symbol, we want
8992 lui $at,<sym> (BFD_RELOC_HI16_S)
8993 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8994 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8995 If there is a base register, we add it to $at after the
8996 lui instruction. If there is a constant, we always use
8998 if (offset_expr
.X_op
== O_symbol
8999 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9000 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9002 relax_start (offset_expr
.X_add_symbol
);
9005 tempreg
= mips_gp_register
;
9009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9010 AT
, breg
, mips_gp_register
);
9015 /* Itbl support may require additional care here. */
9016 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9017 BFD_RELOC_GPREL16
, tempreg
);
9018 offset_expr
.X_add_number
+= 4;
9020 /* Set mips_optimize to 2 to avoid inserting an
9022 hold_mips_optimize
= mips_optimize
;
9024 /* Itbl support may require additional care here. */
9025 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9026 BFD_RELOC_GPREL16
, tempreg
);
9027 mips_optimize
= hold_mips_optimize
;
9031 offset_expr
.X_add_number
-= 4;
9034 macro_build_lui (&offset_expr
, AT
);
9036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9037 /* Itbl support may require additional care here. */
9038 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9039 BFD_RELOC_LO16
, AT
);
9040 /* FIXME: How do we handle overflow here? */
9041 offset_expr
.X_add_number
+= 4;
9042 /* Itbl support may require additional care here. */
9043 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9044 BFD_RELOC_LO16
, AT
);
9045 if (mips_relax
.sequence
)
9048 else if (!mips_big_got
)
9050 /* If this is a reference to an external symbol, we want
9051 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9056 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9058 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9059 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9060 If there is a base register we add it to $at before the
9061 lwc1 instructions. If there is a constant we include it
9062 in the lwc1 instructions. */
9064 expr1
.X_add_number
= offset_expr
.X_add_number
;
9065 if (expr1
.X_add_number
< -0x8000
9066 || expr1
.X_add_number
>= 0x8000 - 4)
9067 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9068 load_got_offset (AT
, &offset_expr
);
9071 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9073 /* Set mips_optimize to 2 to avoid inserting an undesired
9075 hold_mips_optimize
= mips_optimize
;
9078 /* Itbl support may require additional care here. */
9079 relax_start (offset_expr
.X_add_symbol
);
9080 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9081 BFD_RELOC_LO16
, AT
);
9082 expr1
.X_add_number
+= 4;
9083 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9084 BFD_RELOC_LO16
, AT
);
9086 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9087 BFD_RELOC_LO16
, AT
);
9088 offset_expr
.X_add_number
+= 4;
9089 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9090 BFD_RELOC_LO16
, AT
);
9093 mips_optimize
= hold_mips_optimize
;
9095 else if (mips_big_got
)
9099 /* If this is a reference to an external symbol, we want
9100 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9102 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9107 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9109 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9110 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9111 If there is a base register we add it to $at before the
9112 lwc1 instructions. If there is a constant we include it
9113 in the lwc1 instructions. */
9115 expr1
.X_add_number
= offset_expr
.X_add_number
;
9116 offset_expr
.X_add_number
= 0;
9117 if (expr1
.X_add_number
< -0x8000
9118 || expr1
.X_add_number
>= 0x8000 - 4)
9119 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9120 gpdelay
= reg_needs_delay (mips_gp_register
);
9121 relax_start (offset_expr
.X_add_symbol
);
9122 macro_build (&offset_expr
, "lui", LUI_FMT
,
9123 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9125 AT
, AT
, mips_gp_register
);
9126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9127 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9131 /* Itbl support may require additional care here. */
9132 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9133 BFD_RELOC_LO16
, AT
);
9134 expr1
.X_add_number
+= 4;
9136 /* Set mips_optimize to 2 to avoid inserting an undesired
9138 hold_mips_optimize
= mips_optimize
;
9140 /* Itbl support may require additional care here. */
9141 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9142 BFD_RELOC_LO16
, AT
);
9143 mips_optimize
= hold_mips_optimize
;
9144 expr1
.X_add_number
-= 4;
9147 offset_expr
.X_add_number
= expr1
.X_add_number
;
9149 macro_build (NULL
, "nop", "");
9150 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9151 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9155 /* Itbl support may require additional care here. */
9156 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9157 BFD_RELOC_LO16
, AT
);
9158 offset_expr
.X_add_number
+= 4;
9160 /* Set mips_optimize to 2 to avoid inserting an undesired
9162 hold_mips_optimize
= mips_optimize
;
9164 /* Itbl support may require additional care here. */
9165 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9166 BFD_RELOC_LO16
, AT
);
9167 mips_optimize
= hold_mips_optimize
;
9176 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9179 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9181 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9182 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9184 if (!HAVE_64BIT_GPRS
)
9186 offset_expr
.X_add_number
+= 4;
9187 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9188 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9209 /* New code added to support COPZ instructions.
9210 This code builds table entries out of the macros in mip_opcodes.
9211 R4000 uses interlocks to handle coproc delays.
9212 Other chips (like the R3000) require nops to be inserted for delays.
9214 FIXME: Currently, we require that the user handle delays.
9215 In order to fill delay slots for non-interlocked chips,
9216 we must have a way to specify delays based on the coprocessor.
9217 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9218 What are the side-effects of the cop instruction?
9219 What cache support might we have and what are its effects?
9220 Both coprocessor & memory require delays. how long???
9221 What registers are read/set/modified?
9223 If an itbl is provided to interpret cop instructions,
9224 this knowledge can be encoded in the itbl spec. */
9238 gas_assert (!mips_opts
.micromips
);
9239 /* For now we just do C (same as Cz). The parameter will be
9240 stored in insn_opcode by mips_ip. */
9241 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9245 move_register (dreg
, sreg
);
9251 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9252 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9258 /* The MIPS assembler some times generates shifts and adds. I'm
9259 not trying to be that fancy. GCC should do this for us
9262 load_register (AT
, &imm_expr
, dbl
);
9263 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9264 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9280 load_register (AT
, &imm_expr
, dbl
);
9281 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9282 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9283 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9284 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9286 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9289 if (mips_opts
.micromips
)
9290 micromips_label_expr (&label_expr
);
9292 label_expr
.X_add_number
= 8;
9293 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9294 macro_build (NULL
, "nop", "");
9295 macro_build (NULL
, "break", BRK_FMT
, 6);
9296 if (mips_opts
.micromips
)
9297 micromips_add_label ();
9300 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9316 load_register (AT
, &imm_expr
, dbl
);
9317 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9318 sreg
, imm
? AT
: treg
);
9319 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9320 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9322 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9325 if (mips_opts
.micromips
)
9326 micromips_label_expr (&label_expr
);
9328 label_expr
.X_add_number
= 8;
9329 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9330 macro_build (NULL
, "nop", "");
9331 macro_build (NULL
, "break", BRK_FMT
, 6);
9332 if (mips_opts
.micromips
)
9333 micromips_add_label ();
9339 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9350 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9351 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9355 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9356 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9357 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9358 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9362 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9373 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9374 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9378 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9379 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9380 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9381 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9390 if (imm_expr
.X_op
!= O_constant
)
9391 as_bad (_("Improper rotate count"));
9392 rot
= imm_expr
.X_add_number
& 0x3f;
9393 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9395 rot
= (64 - rot
) & 0x3f;
9397 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9399 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9404 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9407 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9408 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9411 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9412 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9413 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9421 if (imm_expr
.X_op
!= O_constant
)
9422 as_bad (_("Improper rotate count"));
9423 rot
= imm_expr
.X_add_number
& 0x1f;
9424 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9426 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9431 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9435 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9436 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9437 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9442 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9444 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9448 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9449 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9450 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9451 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9455 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9457 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9461 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9462 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9463 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9464 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9473 if (imm_expr
.X_op
!= O_constant
)
9474 as_bad (_("Improper rotate count"));
9475 rot
= imm_expr
.X_add_number
& 0x3f;
9476 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9479 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9481 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9486 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9489 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9490 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9493 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9494 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9495 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9503 if (imm_expr
.X_op
!= O_constant
)
9504 as_bad (_("Improper rotate count"));
9505 rot
= imm_expr
.X_add_number
& 0x1f;
9506 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9508 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9513 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9517 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9518 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9519 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9525 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9527 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9530 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9531 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9536 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9538 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9543 as_warn (_("Instruction %s: result is always false"),
9545 move_register (dreg
, 0);
9548 if (CPU_HAS_SEQ (mips_opts
.arch
)
9549 && -512 <= imm_expr
.X_add_number
9550 && imm_expr
.X_add_number
< 512)
9552 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9553 (int) imm_expr
.X_add_number
);
9556 if (imm_expr
.X_op
== O_constant
9557 && imm_expr
.X_add_number
>= 0
9558 && imm_expr
.X_add_number
< 0x10000)
9560 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9562 else if (imm_expr
.X_op
== O_constant
9563 && imm_expr
.X_add_number
> -0x8000
9564 && imm_expr
.X_add_number
< 0)
9566 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9567 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9568 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9570 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9573 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9574 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9579 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9580 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9583 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9586 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9592 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9593 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9596 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9598 if (imm_expr
.X_op
== O_constant
9599 && imm_expr
.X_add_number
>= -0x8000
9600 && imm_expr
.X_add_number
< 0x8000)
9602 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9603 dreg
, sreg
, BFD_RELOC_LO16
);
9607 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9608 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9612 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9615 case M_SGT
: /* sreg > treg <==> treg < sreg */
9621 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9624 case M_SGT_I
: /* sreg > I <==> I < sreg */
9631 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9632 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9635 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9641 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9642 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9645 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9652 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9653 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9654 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9658 if (imm_expr
.X_op
== O_constant
9659 && imm_expr
.X_add_number
>= -0x8000
9660 && imm_expr
.X_add_number
< 0x8000)
9662 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9666 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9667 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9671 if (imm_expr
.X_op
== O_constant
9672 && imm_expr
.X_add_number
>= -0x8000
9673 && imm_expr
.X_add_number
< 0x8000)
9675 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9680 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9681 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9686 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9688 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9691 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9692 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9697 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9699 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9704 as_warn (_("Instruction %s: result is always true"),
9706 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9707 dreg
, 0, BFD_RELOC_LO16
);
9710 if (CPU_HAS_SEQ (mips_opts
.arch
)
9711 && -512 <= imm_expr
.X_add_number
9712 && imm_expr
.X_add_number
< 512)
9714 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9715 (int) imm_expr
.X_add_number
);
9718 if (imm_expr
.X_op
== O_constant
9719 && imm_expr
.X_add_number
>= 0
9720 && imm_expr
.X_add_number
< 0x10000)
9722 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9724 else if (imm_expr
.X_op
== O_constant
9725 && imm_expr
.X_add_number
> -0x8000
9726 && imm_expr
.X_add_number
< 0)
9728 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9729 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9730 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9732 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9735 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9736 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9741 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9742 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9745 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9760 if (!mips_opts
.micromips
)
9762 if (imm_expr
.X_op
== O_constant
9763 && imm_expr
.X_add_number
> -0x200
9764 && imm_expr
.X_add_number
<= 0x200)
9766 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9775 if (imm_expr
.X_op
== O_constant
9776 && imm_expr
.X_add_number
> -0x8000
9777 && imm_expr
.X_add_number
<= 0x8000)
9779 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9780 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9785 load_register (AT
, &imm_expr
, dbl
);
9786 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9808 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9809 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9814 gas_assert (!mips_opts
.micromips
);
9815 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9817 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9818 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9821 * Is the double cfc1 instruction a bug in the mips assembler;
9822 * or is there a reason for it?
9825 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9826 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9827 macro_build (NULL
, "nop", "");
9828 expr1
.X_add_number
= 3;
9829 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9830 expr1
.X_add_number
= 2;
9831 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9832 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9833 macro_build (NULL
, "nop", "");
9834 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9836 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9837 macro_build (NULL
, "nop", "");
9860 off12
= mips_opts
.micromips
;
9868 off12
= mips_opts
.micromips
;
9884 off12
= mips_opts
.micromips
;
9893 off12
= mips_opts
.micromips
;
9898 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9899 as_bad (_("Operand overflow"));
9902 expr1
.X_add_number
= 0;
9907 load_address (tempreg
, ep
, &used_at
);
9909 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9910 tempreg
, tempreg
, breg
);
9916 && (offset_expr
.X_op
!= O_constant
9917 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9918 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9922 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9923 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9928 else if (!ust
&& treg
== breg
)
9939 if (!target_big_endian
)
9940 ep
->X_add_number
+= off
;
9942 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9944 macro_build (NULL
, s
, "t,~(b)",
9945 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9947 if (!target_big_endian
)
9948 ep
->X_add_number
-= off
;
9950 ep
->X_add_number
+= off
;
9952 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9954 macro_build (NULL
, s2
, "t,~(b)",
9955 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9957 /* If necessary, move the result in tempreg to the final destination. */
9958 if (!ust
&& treg
!= tempreg
)
9960 /* Protect second load's delay slot. */
9962 move_register (treg
, tempreg
);
9968 if (target_big_endian
== ust
)
9969 ep
->X_add_number
+= off
;
9970 tempreg
= ust
|| ab
? treg
: AT
;
9971 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9973 /* For halfword transfers we need a temporary register to shuffle
9974 bytes. Unfortunately for M_USH_A we have none available before
9975 the next store as AT holds the base address. We deal with this
9976 case by clobbering TREG and then restoring it as with ULH. */
9977 tempreg
= ust
== ab
? treg
: AT
;
9979 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9981 if (target_big_endian
== ust
)
9982 ep
->X_add_number
-= off
;
9984 ep
->X_add_number
+= off
;
9985 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9987 /* For M_USH_A re-retrieve the LSB. */
9990 if (target_big_endian
)
9991 ep
->X_add_number
+= off
;
9993 ep
->X_add_number
-= off
;
9994 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9996 /* For ULH and M_USH_A OR the LSB in. */
9999 tempreg
= !ab
? AT
: treg
;
10000 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10001 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10006 /* FIXME: Check if this is one of the itbl macros, since they
10007 are added dynamically. */
10008 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10011 if (!mips_opts
.at
&& used_at
)
10012 as_bad (_("Macro used $at after \".set noat\""));
10015 /* Implement macros in mips16 mode. */
10018 mips16_macro (struct mips_cl_insn
*ip
)
10021 int xreg
, yreg
, zreg
, tmp
;
10024 const char *s
, *s2
, *s3
;
10026 mask
= ip
->insn_mo
->mask
;
10028 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10029 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10030 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10032 expr1
.X_op
= O_constant
;
10033 expr1
.X_op_symbol
= NULL
;
10034 expr1
.X_add_symbol
= NULL
;
10035 expr1
.X_add_number
= 1;
10054 start_noreorder ();
10055 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10056 expr1
.X_add_number
= 2;
10057 macro_build (&expr1
, "bnez", "x,p", yreg
);
10058 macro_build (NULL
, "break", "6", 7);
10060 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10061 since that causes an overflow. We should do that as well,
10062 but I don't see how to do the comparisons without a temporary
10065 macro_build (NULL
, s
, "x", zreg
);
10084 start_noreorder ();
10085 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10086 expr1
.X_add_number
= 2;
10087 macro_build (&expr1
, "bnez", "x,p", yreg
);
10088 macro_build (NULL
, "break", "6", 7);
10090 macro_build (NULL
, s2
, "x", zreg
);
10096 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10097 macro_build (NULL
, "mflo", "x", zreg
);
10105 if (imm_expr
.X_op
!= O_constant
)
10106 as_bad (_("Unsupported large constant"));
10107 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10108 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10112 if (imm_expr
.X_op
!= O_constant
)
10113 as_bad (_("Unsupported large constant"));
10114 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10115 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10119 if (imm_expr
.X_op
!= O_constant
)
10120 as_bad (_("Unsupported large constant"));
10121 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10122 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10144 goto do_reverse_branch
;
10148 goto do_reverse_branch
;
10160 goto do_reverse_branch
;
10171 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10172 macro_build (&offset_expr
, s2
, "p");
10199 goto do_addone_branch_i
;
10204 goto do_addone_branch_i
;
10219 goto do_addone_branch_i
;
10225 do_addone_branch_i
:
10226 if (imm_expr
.X_op
!= O_constant
)
10227 as_bad (_("Unsupported large constant"));
10228 ++imm_expr
.X_add_number
;
10231 macro_build (&imm_expr
, s
, s3
, xreg
);
10232 macro_build (&offset_expr
, s2
, "p");
10236 expr1
.X_add_number
= 0;
10237 macro_build (&expr1
, "slti", "x,8", yreg
);
10239 move_register (xreg
, yreg
);
10240 expr1
.X_add_number
= 2;
10241 macro_build (&expr1
, "bteqz", "p");
10242 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10246 /* For consistency checking, verify that all bits are specified either
10247 by the match/mask part of the instruction definition, or by the
10250 validate_mips_insn (const struct mips_opcode
*opc
)
10252 const char *p
= opc
->args
;
10254 unsigned long used_bits
= opc
->mask
;
10256 if ((used_bits
& opc
->match
) != opc
->match
)
10258 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10259 opc
->name
, opc
->args
);
10262 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10272 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10273 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10274 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10275 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10276 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10277 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10278 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10279 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10280 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10281 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10282 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10283 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10284 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10286 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10287 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10288 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10289 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10290 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10291 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10292 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10293 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10294 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10295 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10296 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10297 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10298 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10299 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10300 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10303 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10304 c
, opc
->name
, opc
->args
);
10308 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10309 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10311 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10312 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10313 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10314 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10316 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10317 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10319 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10320 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10322 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10323 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10324 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10325 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10326 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10327 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10328 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10329 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10330 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10331 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10332 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10333 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10334 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10335 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10336 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10337 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10338 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10340 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10341 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10342 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10343 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10345 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10346 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10347 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10348 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10349 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10350 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10351 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10352 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10353 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10356 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10357 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10358 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10359 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10360 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10363 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10364 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10365 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10366 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10367 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10368 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10369 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10370 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10371 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10372 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10373 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10374 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10375 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10376 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10377 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10378 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10379 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10380 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10381 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10382 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10384 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10385 c
, opc
->name
, opc
->args
);
10389 if (used_bits
!= 0xffffffff)
10391 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10392 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10398 /* For consistency checking, verify that the length implied matches the
10399 major opcode and that all bits are specified either by the match/mask
10400 part of the instruction definition, or by the operand list. */
10403 validate_micromips_insn (const struct mips_opcode
*opc
)
10405 unsigned long match
= opc
->match
;
10406 unsigned long mask
= opc
->mask
;
10407 const char *p
= opc
->args
;
10408 unsigned long insn_bits
;
10409 unsigned long used_bits
;
10410 unsigned long major
;
10411 unsigned int length
;
10415 if ((mask
& match
) != match
)
10417 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10418 opc
->name
, opc
->args
);
10421 length
= micromips_insn_length (opc
);
10422 if (length
!= 2 && length
!= 4)
10424 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10425 "%s %s"), length
, opc
->name
, opc
->args
);
10428 major
= match
>> (10 + 8 * (length
- 2));
10429 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10430 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10432 as_bad (_("Internal error: bad microMIPS opcode "
10433 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10437 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10438 insn_bits
= 1 << 4 * length
;
10439 insn_bits
<<= 4 * length
;
10442 #define USE_BITS(field) \
10443 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10454 case 'A': USE_BITS (EXTLSB
); break;
10455 case 'B': USE_BITS (INSMSB
); break;
10456 case 'C': USE_BITS (EXTMSBD
); break;
10457 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10458 case 'E': USE_BITS (EXTLSB
); break;
10459 case 'F': USE_BITS (INSMSB
); break;
10460 case 'G': USE_BITS (EXTMSBD
); break;
10461 case 'H': USE_BITS (EXTMSBD
); break;
10463 as_bad (_("Internal error: bad mips opcode "
10464 "(unknown extension operand type `%c%c'): %s %s"),
10465 e
, c
, opc
->name
, opc
->args
);
10473 case 'A': USE_BITS (IMMA
); break;
10474 case 'B': USE_BITS (IMMB
); break;
10475 case 'C': USE_BITS (IMMC
); break;
10476 case 'D': USE_BITS (IMMD
); break;
10477 case 'E': USE_BITS (IMME
); break;
10478 case 'F': USE_BITS (IMMF
); break;
10479 case 'G': USE_BITS (IMMG
); break;
10480 case 'H': USE_BITS (IMMH
); break;
10481 case 'I': USE_BITS (IMMI
); break;
10482 case 'J': USE_BITS (IMMJ
); break;
10483 case 'L': USE_BITS (IMML
); break;
10484 case 'M': USE_BITS (IMMM
); break;
10485 case 'N': USE_BITS (IMMN
); break;
10486 case 'O': USE_BITS (IMMO
); break;
10487 case 'P': USE_BITS (IMMP
); break;
10488 case 'Q': USE_BITS (IMMQ
); break;
10489 case 'U': USE_BITS (IMMU
); break;
10490 case 'W': USE_BITS (IMMW
); break;
10491 case 'X': USE_BITS (IMMX
); break;
10492 case 'Y': USE_BITS (IMMY
); break;
10495 case 'b': USE_BITS (MB
); break;
10496 case 'c': USE_BITS (MC
); break;
10497 case 'd': USE_BITS (MD
); break;
10498 case 'e': USE_BITS (ME
); break;
10499 case 'f': USE_BITS (MF
); break;
10500 case 'g': USE_BITS (MG
); break;
10501 case 'h': USE_BITS (MH
); break;
10502 case 'i': USE_BITS (MI
); break;
10503 case 'j': USE_BITS (MJ
); break;
10504 case 'l': USE_BITS (ML
); break;
10505 case 'm': USE_BITS (MM
); break;
10506 case 'n': USE_BITS (MN
); break;
10507 case 'p': USE_BITS (MP
); break;
10508 case 'q': USE_BITS (MQ
); break;
10516 as_bad (_("Internal error: bad mips opcode "
10517 "(unknown extension operand type `%c%c'): %s %s"),
10518 e
, c
, opc
->name
, opc
->args
);
10522 case '.': USE_BITS (OFFSET10
); break;
10523 case '1': USE_BITS (STYPE
); break;
10524 case '2': USE_BITS (BP
); break;
10525 case '3': USE_BITS (SA3
); break;
10526 case '4': USE_BITS (SA4
); break;
10527 case '5': USE_BITS (IMM8
); break;
10528 case '6': USE_BITS (RS
); break;
10529 case '7': USE_BITS (DSPACC
); break;
10530 case '8': USE_BITS (WRDSP
); break;
10531 case '0': USE_BITS (DSPSFT
); break;
10532 case '<': USE_BITS (SHAMT
); break;
10533 case '>': USE_BITS (SHAMT
); break;
10534 case '@': USE_BITS (IMM10
); break;
10535 case 'B': USE_BITS (CODE10
); break;
10536 case 'C': USE_BITS (COPZ
); break;
10537 case 'D': USE_BITS (FD
); break;
10538 case 'E': USE_BITS (RT
); break;
10539 case 'G': USE_BITS (RS
); break;
10540 case 'H': USE_BITS (SEL
); break;
10541 case 'K': USE_BITS (RS
); break;
10542 case 'M': USE_BITS (CCC
); break;
10543 case 'N': USE_BITS (BCC
); break;
10544 case 'R': USE_BITS (FR
); break;
10545 case 'S': USE_BITS (FS
); break;
10546 case 'T': USE_BITS (FT
); break;
10547 case 'V': USE_BITS (FS
); break;
10548 case '\\': USE_BITS (3BITPOS
); break;
10549 case '^': USE_BITS (RD
); break;
10550 case 'a': USE_BITS (TARGET
); break;
10551 case 'b': USE_BITS (RS
); break;
10552 case 'c': USE_BITS (CODE
); break;
10553 case 'd': USE_BITS (RD
); break;
10554 case 'h': USE_BITS (PREFX
); break;
10555 case 'i': USE_BITS (IMMEDIATE
); break;
10556 case 'j': USE_BITS (DELTA
); break;
10557 case 'k': USE_BITS (CACHE
); break;
10558 case 'n': USE_BITS (RT
); break;
10559 case 'o': USE_BITS (DELTA
); break;
10560 case 'p': USE_BITS (DELTA
); break;
10561 case 'q': USE_BITS (CODE2
); break;
10562 case 'r': USE_BITS (RS
); break;
10563 case 's': USE_BITS (RS
); break;
10564 case 't': USE_BITS (RT
); break;
10565 case 'u': USE_BITS (IMMEDIATE
); break;
10566 case 'v': USE_BITS (RS
); break;
10567 case 'w': USE_BITS (RT
); break;
10568 case 'y': USE_BITS (RS3
); break;
10570 case '|': USE_BITS (TRAP
); break;
10571 case '~': USE_BITS (OFFSET12
); break;
10573 as_bad (_("Internal error: bad microMIPS opcode "
10574 "(unknown operand type `%c'): %s %s"),
10575 c
, opc
->name
, opc
->args
);
10579 if (used_bits
!= insn_bits
)
10581 if (~used_bits
& insn_bits
)
10582 as_bad (_("Internal error: bad microMIPS opcode "
10583 "(bits 0x%lx undefined): %s %s"),
10584 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10585 if (used_bits
& ~insn_bits
)
10586 as_bad (_("Internal error: bad microMIPS opcode "
10587 "(bits 0x%lx defined): %s %s"),
10588 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10594 /* UDI immediates. */
10595 struct mips_immed
{
10597 unsigned int shift
;
10598 unsigned long mask
;
10602 static const struct mips_immed mips_immed
[] = {
10603 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10604 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10605 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10606 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10610 /* Check whether an odd floating-point register is allowed. */
10612 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10614 const char *s
= insn
->name
;
10616 if (insn
->pinfo
== INSN_MACRO
)
10617 /* Let a macro pass, we'll catch it later when it is expanded. */
10620 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10622 /* Allow odd registers for single-precision ops. */
10623 switch (insn
->pinfo
& (FP_S
| FP_D
))
10627 return 1; /* both single precision - ok */
10629 return 0; /* both double precision - fail */
10634 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10635 s
= strchr (insn
->name
, '.');
10637 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10638 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10641 /* Single-precision coprocessor loads and moves are OK too. */
10642 if ((insn
->pinfo
& FP_S
)
10643 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10644 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10650 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10651 taking bits from BIT up. */
10653 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10655 return (ep
->X_op
== O_constant
10656 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10657 && ep
->X_add_number
>= min
<< bit
10658 && ep
->X_add_number
< max
<< bit
);
10661 /* This routine assembles an instruction into its binary format. As a
10662 side effect, it sets one of the global variables imm_reloc or
10663 offset_reloc to the type of relocation to do if one of the operands
10664 is an address expression. */
10667 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10669 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10670 bfd_boolean need_delay_slot_ok
= TRUE
;
10671 struct mips_opcode
*firstinsn
= NULL
;
10672 const struct mips_opcode
*past
;
10673 struct hash_control
*hash
;
10677 struct mips_opcode
*insn
;
10679 unsigned int regno
;
10680 unsigned int lastregno
;
10681 unsigned int destregno
= 0;
10682 unsigned int lastpos
= 0;
10683 unsigned int limlo
, limhi
;
10685 offsetT min_range
, max_range
;
10689 unsigned int rtype
;
10695 if (mips_opts
.micromips
)
10697 hash
= micromips_op_hash
;
10698 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10703 past
= &mips_opcodes
[NUMOPCODES
];
10705 forced_insn_length
= 0;
10708 /* We first try to match an instruction up to a space or to the end. */
10709 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10712 /* Make a copy of the instruction so that we can fiddle with it. */
10713 name
= alloca (end
+ 1);
10714 memcpy (name
, str
, end
);
10719 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10721 if (insn
!= NULL
|| !mips_opts
.micromips
)
10723 if (forced_insn_length
)
10726 /* See if there's an instruction size override suffix,
10727 either `16' or `32', at the end of the mnemonic proper,
10728 that defines the operation, i.e. before the first `.'
10729 character if any. Strip it and retry. */
10730 dot
= strchr (name
, '.');
10731 opend
= dot
!= NULL
? dot
- name
: end
;
10734 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10735 forced_insn_length
= 2;
10736 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10737 forced_insn_length
= 4;
10740 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10744 insn_error
= _("Unrecognized opcode");
10748 /* For microMIPS instructions placed in a fixed-length branch delay slot
10749 we make up to two passes over the relevant fragment of the opcode
10750 table. First we try instructions that meet the delay slot's length
10751 requirement. If none matched, then we retry with the remaining ones
10752 and if one matches, then we use it and then issue an appropriate
10753 warning later on. */
10754 argsStart
= s
= str
+ end
;
10757 bfd_boolean delay_slot_ok
;
10758 bfd_boolean size_ok
;
10761 gas_assert (strcmp (insn
->name
, name
) == 0);
10763 ok
= is_opcode_valid (insn
);
10764 size_ok
= is_size_valid (insn
);
10765 delay_slot_ok
= is_delay_slot_valid (insn
);
10766 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10769 wrong_delay_slot_insns
= TRUE
;
10771 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10773 static char buf
[256];
10775 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10780 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10782 gas_assert (firstinsn
);
10783 need_delay_slot_ok
= FALSE
;
10793 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10794 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10795 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10797 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10798 8 * forced_insn_length
);
10804 create_insn (ip
, insn
);
10807 lastregno
= 0xffffffff;
10808 for (args
= insn
->args
;; ++args
)
10812 s
+= strspn (s
, " \t");
10816 case '\0': /* end of args */
10822 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10823 code) or 14 (for microMIPS code). */
10824 my_getExpression (&imm_expr
, s
);
10825 check_absolute_expr (ip
, &imm_expr
);
10826 if ((unsigned long) imm_expr
.X_add_number
!= 1
10827 && (unsigned long) imm_expr
.X_add_number
!= 3)
10829 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10830 (unsigned long) imm_expr
.X_add_number
);
10832 INSERT_OPERAND (mips_opts
.micromips
,
10833 BP
, *ip
, imm_expr
.X_add_number
);
10834 imm_expr
.X_op
= O_absent
;
10839 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10840 code) or 21 (for microMIPS code). */
10842 unsigned long mask
= (mips_opts
.micromips
10843 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10845 my_getExpression (&imm_expr
, s
);
10846 check_absolute_expr (ip
, &imm_expr
);
10847 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10848 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10849 mask
, (unsigned long) imm_expr
.X_add_number
);
10850 INSERT_OPERAND (mips_opts
.micromips
,
10851 SA3
, *ip
, imm_expr
.X_add_number
);
10852 imm_expr
.X_op
= O_absent
;
10858 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10859 code) or 21 (for microMIPS code). */
10861 unsigned long mask
= (mips_opts
.micromips
10862 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10864 my_getExpression (&imm_expr
, s
);
10865 check_absolute_expr (ip
, &imm_expr
);
10866 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10867 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10868 mask
, (unsigned long) imm_expr
.X_add_number
);
10869 INSERT_OPERAND (mips_opts
.micromips
,
10870 SA4
, *ip
, imm_expr
.X_add_number
);
10871 imm_expr
.X_op
= O_absent
;
10877 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10878 code) or 16 (for microMIPS code). */
10880 unsigned long mask
= (mips_opts
.micromips
10881 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
10883 my_getExpression (&imm_expr
, s
);
10884 check_absolute_expr (ip
, &imm_expr
);
10885 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10886 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10887 mask
, (unsigned long) imm_expr
.X_add_number
);
10888 INSERT_OPERAND (mips_opts
.micromips
,
10889 IMM8
, *ip
, imm_expr
.X_add_number
);
10890 imm_expr
.X_op
= O_absent
;
10896 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10897 code) or 21 (for microMIPS code). */
10899 unsigned long mask
= (mips_opts
.micromips
10900 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
10902 my_getExpression (&imm_expr
, s
);
10903 check_absolute_expr (ip
, &imm_expr
);
10904 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10905 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10906 mask
, (unsigned long) imm_expr
.X_add_number
);
10907 INSERT_OPERAND (mips_opts
.micromips
,
10908 RS
, *ip
, imm_expr
.X_add_number
);
10909 imm_expr
.X_op
= O_absent
;
10914 case '7': /* Four DSP accumulators in bits 11,12. */
10915 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10916 && s
[3] >= '0' && s
[3] <= '3')
10918 regno
= s
[3] - '0';
10920 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
10924 as_bad (_("Invalid dsp acc register"));
10928 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10929 code) or 14 (for microMIPS code). */
10931 unsigned long mask
= (mips_opts
.micromips
10932 ? MICROMIPSOP_MASK_WRDSP
10935 my_getExpression (&imm_expr
, s
);
10936 check_absolute_expr (ip
, &imm_expr
);
10937 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10938 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10939 mask
, (unsigned long) imm_expr
.X_add_number
);
10940 INSERT_OPERAND (mips_opts
.micromips
,
10941 WRDSP
, *ip
, imm_expr
.X_add_number
);
10942 imm_expr
.X_op
= O_absent
;
10947 case '9': /* Four DSP accumulators in bits 21,22. */
10948 gas_assert (!mips_opts
.micromips
);
10949 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10950 && s
[3] >= '0' && s
[3] <= '3')
10952 regno
= s
[3] - '0';
10954 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10958 as_bad (_("Invalid dsp acc register"));
10962 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10963 code) or 20 (for microMIPS code). */
10965 long mask
= (mips_opts
.micromips
10966 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
10968 my_getExpression (&imm_expr
, s
);
10969 check_absolute_expr (ip
, &imm_expr
);
10970 min_range
= -((mask
+ 1) >> 1);
10971 max_range
= ((mask
+ 1) >> 1) - 1;
10972 if (imm_expr
.X_add_number
< min_range
10973 || imm_expr
.X_add_number
> max_range
)
10974 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10975 (long) min_range
, (long) max_range
,
10976 (long) imm_expr
.X_add_number
);
10977 INSERT_OPERAND (mips_opts
.micromips
,
10978 DSPSFT
, *ip
, imm_expr
.X_add_number
);
10979 imm_expr
.X_op
= O_absent
;
10984 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10985 gas_assert (!mips_opts
.micromips
);
10986 my_getExpression (&imm_expr
, s
);
10987 check_absolute_expr (ip
, &imm_expr
);
10988 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10990 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10992 (unsigned long) imm_expr
.X_add_number
);
10994 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10995 imm_expr
.X_op
= O_absent
;
10999 case ':': /* DSP 7-bit signed immediate in bit 19. */
11000 gas_assert (!mips_opts
.micromips
);
11001 my_getExpression (&imm_expr
, s
);
11002 check_absolute_expr (ip
, &imm_expr
);
11003 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11004 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11005 if (imm_expr
.X_add_number
< min_range
||
11006 imm_expr
.X_add_number
> max_range
)
11008 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11009 (long) min_range
, (long) max_range
,
11010 (long) imm_expr
.X_add_number
);
11012 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11013 imm_expr
.X_op
= O_absent
;
11017 case '@': /* DSP 10-bit signed immediate in bit 16. */
11019 long mask
= (mips_opts
.micromips
11020 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11022 my_getExpression (&imm_expr
, s
);
11023 check_absolute_expr (ip
, &imm_expr
);
11024 min_range
= -((mask
+ 1) >> 1);
11025 max_range
= ((mask
+ 1) >> 1) - 1;
11026 if (imm_expr
.X_add_number
< min_range
11027 || imm_expr
.X_add_number
> max_range
)
11028 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11029 (long) min_range
, (long) max_range
,
11030 (long) imm_expr
.X_add_number
);
11031 INSERT_OPERAND (mips_opts
.micromips
,
11032 IMM10
, *ip
, imm_expr
.X_add_number
);
11033 imm_expr
.X_op
= O_absent
;
11038 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11039 gas_assert (mips_opts
.micromips
);
11040 my_getExpression (&imm_expr
, s
);
11041 check_absolute_expr (ip
, &imm_expr
);
11042 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11043 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11044 MICROMIPSOP_MASK_RD
,
11045 (unsigned long) imm_expr
.X_add_number
);
11046 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11047 imm_expr
.X_op
= O_absent
;
11051 case '!': /* MT usermode flag bit. */
11052 gas_assert (!mips_opts
.micromips
);
11053 my_getExpression (&imm_expr
, s
);
11054 check_absolute_expr (ip
, &imm_expr
);
11055 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11056 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11057 (unsigned long) imm_expr
.X_add_number
);
11058 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11059 imm_expr
.X_op
= O_absent
;
11063 case '$': /* MT load high flag bit. */
11064 gas_assert (!mips_opts
.micromips
);
11065 my_getExpression (&imm_expr
, s
);
11066 check_absolute_expr (ip
, &imm_expr
);
11067 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11068 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11069 (unsigned long) imm_expr
.X_add_number
);
11070 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11071 imm_expr
.X_op
= O_absent
;
11075 case '*': /* Four DSP accumulators in bits 18,19. */
11076 gas_assert (!mips_opts
.micromips
);
11077 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11078 s
[3] >= '0' && s
[3] <= '3')
11080 regno
= s
[3] - '0';
11082 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11086 as_bad (_("Invalid dsp/smartmips acc register"));
11089 case '&': /* Four DSP accumulators in bits 13,14. */
11090 gas_assert (!mips_opts
.micromips
);
11091 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11092 s
[3] >= '0' && s
[3] <= '3')
11094 regno
= s
[3] - '0';
11096 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11100 as_bad (_("Invalid dsp/smartmips acc register"));
11103 case '\\': /* 3-bit bit position. */
11105 unsigned long mask
= (mips_opts
.micromips
11106 ? MICROMIPSOP_MASK_3BITPOS
11107 : OP_MASK_3BITPOS
);
11109 my_getExpression (&imm_expr
, s
);
11110 check_absolute_expr (ip
, &imm_expr
);
11111 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11112 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11114 mask
, (unsigned long) imm_expr
.X_add_number
);
11115 INSERT_OPERAND (mips_opts
.micromips
,
11116 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11117 imm_expr
.X_op
= O_absent
;
11131 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11135 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11139 gas_assert (!mips_opts
.micromips
);
11140 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11144 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11150 /* Handle optional base register.
11151 Either the base register is omitted or
11152 we must have a left paren. */
11153 /* This is dependent on the next operand specifier
11154 is a base register specification. */
11155 gas_assert (args
[1] == 'b'
11156 || (mips_opts
.micromips
11158 && (args
[2] == 'l' || args
[2] == 'n'
11159 || args
[2] == 's' || args
[2] == 'a')));
11160 if (*s
== '\0' && args
[1] == 'b')
11162 /* Fall through. */
11164 case ')': /* These must match exactly. */
11169 case '[': /* These must match exactly. */
11171 gas_assert (!mips_opts
.micromips
);
11176 case '+': /* Opcode extension character. */
11179 case '1': /* UDI immediates. */
11183 gas_assert (!mips_opts
.micromips
);
11185 const struct mips_immed
*imm
= mips_immed
;
11187 while (imm
->type
&& imm
->type
!= *args
)
11191 my_getExpression (&imm_expr
, s
);
11192 check_absolute_expr (ip
, &imm_expr
);
11193 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11195 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11196 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11197 (unsigned long) imm_expr
.X_add_number
,
11198 (unsigned long) imm_expr
.X_add_number
);
11199 imm_expr
.X_add_number
&= imm
->mask
;
11201 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11203 imm_expr
.X_op
= O_absent
;
11208 case 'A': /* ins/ext position, becomes LSB. */
11217 my_getExpression (&imm_expr
, s
);
11218 check_absolute_expr (ip
, &imm_expr
);
11219 if ((unsigned long) imm_expr
.X_add_number
< limlo
11220 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11222 as_bad (_("Improper position (%lu)"),
11223 (unsigned long) imm_expr
.X_add_number
);
11224 imm_expr
.X_add_number
= limlo
;
11226 lastpos
= imm_expr
.X_add_number
;
11227 INSERT_OPERAND (mips_opts
.micromips
,
11228 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11229 imm_expr
.X_op
= O_absent
;
11233 case 'B': /* ins size, becomes MSB. */
11242 my_getExpression (&imm_expr
, s
);
11243 check_absolute_expr (ip
, &imm_expr
);
11244 /* Check for negative input so that small negative numbers
11245 will not succeed incorrectly. The checks against
11246 (pos+size) transitively check "size" itself,
11247 assuming that "pos" is reasonable. */
11248 if ((long) imm_expr
.X_add_number
< 0
11249 || ((unsigned long) imm_expr
.X_add_number
11251 || ((unsigned long) imm_expr
.X_add_number
11252 + lastpos
) > limhi
)
11254 as_bad (_("Improper insert size (%lu, position %lu)"),
11255 (unsigned long) imm_expr
.X_add_number
,
11256 (unsigned long) lastpos
);
11257 imm_expr
.X_add_number
= limlo
- lastpos
;
11259 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11260 lastpos
+ imm_expr
.X_add_number
- 1);
11261 imm_expr
.X_op
= O_absent
;
11265 case 'C': /* ext size, becomes MSBD. */
11278 my_getExpression (&imm_expr
, s
);
11279 check_absolute_expr (ip
, &imm_expr
);
11280 /* Check for negative input so that small negative numbers
11281 will not succeed incorrectly. The checks against
11282 (pos+size) transitively check "size" itself,
11283 assuming that "pos" is reasonable. */
11284 if ((long) imm_expr
.X_add_number
< 0
11285 || ((unsigned long) imm_expr
.X_add_number
11287 || ((unsigned long) imm_expr
.X_add_number
11288 + lastpos
) > limhi
)
11290 as_bad (_("Improper extract size (%lu, position %lu)"),
11291 (unsigned long) imm_expr
.X_add_number
,
11292 (unsigned long) lastpos
);
11293 imm_expr
.X_add_number
= limlo
- lastpos
;
11295 INSERT_OPERAND (mips_opts
.micromips
,
11296 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11297 imm_expr
.X_op
= O_absent
;
11302 /* +D is for disassembly only; never match. */
11306 /* "+I" is like "I", except that imm2_expr is used. */
11307 my_getExpression (&imm2_expr
, s
);
11308 if (imm2_expr
.X_op
!= O_big
11309 && imm2_expr
.X_op
!= O_constant
)
11310 insn_error
= _("absolute expression required");
11311 if (HAVE_32BIT_GPRS
)
11312 normalize_constant_expr (&imm2_expr
);
11316 case 'T': /* Coprocessor register. */
11317 gas_assert (!mips_opts
.micromips
);
11318 /* +T is for disassembly only; never match. */
11321 case 't': /* Coprocessor register number. */
11322 gas_assert (!mips_opts
.micromips
);
11323 if (s
[0] == '$' && ISDIGIT (s
[1]))
11333 while (ISDIGIT (*s
));
11335 as_bad (_("Invalid register number (%d)"), regno
);
11338 INSERT_OPERAND (0, RT
, *ip
, regno
);
11343 as_bad (_("Invalid coprocessor 0 register number"));
11347 /* bbit[01] and bbit[01]32 bit index. Give error if index
11348 is not in the valid range. */
11349 gas_assert (!mips_opts
.micromips
);
11350 my_getExpression (&imm_expr
, s
);
11351 check_absolute_expr (ip
, &imm_expr
);
11352 if ((unsigned) imm_expr
.X_add_number
> 31)
11354 as_bad (_("Improper bit index (%lu)"),
11355 (unsigned long) imm_expr
.X_add_number
);
11356 imm_expr
.X_add_number
= 0;
11358 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11359 imm_expr
.X_op
= O_absent
;
11364 /* bbit[01] bit index when bbit is used but we generate
11365 bbit[01]32 because the index is over 32. Move to the
11366 next candidate if index is not in the valid range. */
11367 gas_assert (!mips_opts
.micromips
);
11368 my_getExpression (&imm_expr
, s
);
11369 check_absolute_expr (ip
, &imm_expr
);
11370 if ((unsigned) imm_expr
.X_add_number
< 32
11371 || (unsigned) imm_expr
.X_add_number
> 63)
11373 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11374 imm_expr
.X_op
= O_absent
;
11379 /* cins, cins32, exts and exts32 position field. Give error
11380 if it's not in the valid range. */
11381 gas_assert (!mips_opts
.micromips
);
11382 my_getExpression (&imm_expr
, s
);
11383 check_absolute_expr (ip
, &imm_expr
);
11384 if ((unsigned) imm_expr
.X_add_number
> 31)
11386 as_bad (_("Improper position (%lu)"),
11387 (unsigned long) imm_expr
.X_add_number
);
11388 imm_expr
.X_add_number
= 0;
11390 /* Make the pos explicit to simplify +S. */
11391 lastpos
= imm_expr
.X_add_number
+ 32;
11392 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11393 imm_expr
.X_op
= O_absent
;
11398 /* cins, cins32, exts and exts32 position field. Move to
11399 the next candidate if it's not in the valid range. */
11400 gas_assert (!mips_opts
.micromips
);
11401 my_getExpression (&imm_expr
, s
);
11402 check_absolute_expr (ip
, &imm_expr
);
11403 if ((unsigned) imm_expr
.X_add_number
< 32
11404 || (unsigned) imm_expr
.X_add_number
> 63)
11406 lastpos
= imm_expr
.X_add_number
;
11407 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11408 imm_expr
.X_op
= O_absent
;
11413 /* cins and exts length-minus-one field. */
11414 gas_assert (!mips_opts
.micromips
);
11415 my_getExpression (&imm_expr
, s
);
11416 check_absolute_expr (ip
, &imm_expr
);
11417 if ((unsigned long) imm_expr
.X_add_number
> 31)
11419 as_bad (_("Improper size (%lu)"),
11420 (unsigned long) imm_expr
.X_add_number
);
11421 imm_expr
.X_add_number
= 0;
11423 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11424 imm_expr
.X_op
= O_absent
;
11429 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11430 length-minus-one field. */
11431 gas_assert (!mips_opts
.micromips
);
11432 my_getExpression (&imm_expr
, s
);
11433 check_absolute_expr (ip
, &imm_expr
);
11434 if ((long) imm_expr
.X_add_number
< 0
11435 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11437 as_bad (_("Improper size (%lu)"),
11438 (unsigned long) imm_expr
.X_add_number
);
11439 imm_expr
.X_add_number
= 0;
11441 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11442 imm_expr
.X_op
= O_absent
;
11447 /* seqi/snei immediate field. */
11448 gas_assert (!mips_opts
.micromips
);
11449 my_getExpression (&imm_expr
, s
);
11450 check_absolute_expr (ip
, &imm_expr
);
11451 if ((long) imm_expr
.X_add_number
< -512
11452 || (long) imm_expr
.X_add_number
>= 512)
11454 as_bad (_("Improper immediate (%ld)"),
11455 (long) imm_expr
.X_add_number
);
11456 imm_expr
.X_add_number
= 0;
11458 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11459 imm_expr
.X_op
= O_absent
;
11463 case 'a': /* 8-bit signed offset in bit 6 */
11464 gas_assert (!mips_opts
.micromips
);
11465 my_getExpression (&imm_expr
, s
);
11466 check_absolute_expr (ip
, &imm_expr
);
11467 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11468 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11469 if (imm_expr
.X_add_number
< min_range
11470 || imm_expr
.X_add_number
> max_range
)
11472 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11473 (long) min_range
, (long) max_range
,
11474 (long) imm_expr
.X_add_number
);
11476 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11477 imm_expr
.X_op
= O_absent
;
11481 case 'b': /* 8-bit signed offset in bit 3 */
11482 gas_assert (!mips_opts
.micromips
);
11483 my_getExpression (&imm_expr
, s
);
11484 check_absolute_expr (ip
, &imm_expr
);
11485 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11486 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11487 if (imm_expr
.X_add_number
< min_range
11488 || imm_expr
.X_add_number
> max_range
)
11490 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11491 (long) min_range
, (long) max_range
,
11492 (long) imm_expr
.X_add_number
);
11494 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11495 imm_expr
.X_op
= O_absent
;
11499 case 'c': /* 9-bit signed offset in bit 6 */
11500 gas_assert (!mips_opts
.micromips
);
11501 my_getExpression (&imm_expr
, s
);
11502 check_absolute_expr (ip
, &imm_expr
);
11503 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11504 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11505 /* We check the offset range before adjusted. */
11508 if (imm_expr
.X_add_number
< min_range
11509 || imm_expr
.X_add_number
> max_range
)
11511 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11512 (long) min_range
, (long) max_range
,
11513 (long) imm_expr
.X_add_number
);
11515 if (imm_expr
.X_add_number
& 0xf)
11517 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11518 (long) imm_expr
.X_add_number
);
11520 /* Right shift 4 bits to adjust the offset operand. */
11521 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11522 imm_expr
.X_add_number
>> 4);
11523 imm_expr
.X_op
= O_absent
;
11528 gas_assert (!mips_opts
.micromips
);
11529 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11531 if (regno
== AT
&& mips_opts
.at
)
11533 if (mips_opts
.at
== ATREG
)
11534 as_warn (_("used $at without \".set noat\""));
11536 as_warn (_("used $%u with \".set at=$%u\""),
11537 regno
, mips_opts
.at
);
11539 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11543 gas_assert (!mips_opts
.micromips
);
11544 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11546 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11550 as_bad (_("Internal error: bad %s opcode "
11551 "(unknown extension operand type `+%c'): %s %s"),
11552 mips_opts
.micromips
? "microMIPS" : "MIPS",
11553 *args
, insn
->name
, insn
->args
);
11554 /* Further processing is fruitless. */
11559 case '.': /* 10-bit offset. */
11560 gas_assert (mips_opts
.micromips
);
11561 case '~': /* 12-bit offset. */
11563 int shift
= *args
== '.' ? 9 : 11;
11566 /* Check whether there is only a single bracketed expression
11567 left. If so, it must be the base register and the
11568 constant must be zero. */
11569 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11572 /* If this value won't fit into the offset, then go find
11573 a macro that will generate a 16- or 32-bit offset code
11575 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11576 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11577 || imm_expr
.X_add_number
>= 1 << shift
11578 || imm_expr
.X_add_number
< -1 << shift
))
11581 imm_expr
.X_op
= O_absent
;
11585 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11587 INSERT_OPERAND (mips_opts
.micromips
,
11588 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11589 imm_expr
.X_op
= O_absent
;
11594 case '<': /* must be at least one digit */
11596 * According to the manual, if the shift amount is greater
11597 * than 31 or less than 0, then the shift amount should be
11598 * mod 32. In reality the mips assembler issues an error.
11599 * We issue a warning and mask out all but the low 5 bits.
11601 my_getExpression (&imm_expr
, s
);
11602 check_absolute_expr (ip
, &imm_expr
);
11603 if ((unsigned long) imm_expr
.X_add_number
> 31)
11604 as_warn (_("Improper shift amount (%lu)"),
11605 (unsigned long) imm_expr
.X_add_number
);
11606 INSERT_OPERAND (mips_opts
.micromips
,
11607 SHAMT
, *ip
, imm_expr
.X_add_number
);
11608 imm_expr
.X_op
= O_absent
;
11612 case '>': /* shift amount minus 32 */
11613 my_getExpression (&imm_expr
, s
);
11614 check_absolute_expr (ip
, &imm_expr
);
11615 if ((unsigned long) imm_expr
.X_add_number
< 32
11616 || (unsigned long) imm_expr
.X_add_number
> 63)
11618 INSERT_OPERAND (mips_opts
.micromips
,
11619 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11620 imm_expr
.X_op
= O_absent
;
11624 case 'k': /* CACHE code. */
11625 case 'h': /* PREFX code. */
11626 case '1': /* SYNC type. */
11627 my_getExpression (&imm_expr
, s
);
11628 check_absolute_expr (ip
, &imm_expr
);
11629 if ((unsigned long) imm_expr
.X_add_number
> 31)
11630 as_warn (_("Invalid value for `%s' (%lu)"),
11632 (unsigned long) imm_expr
.X_add_number
);
11636 if (mips_fix_cn63xxp1
11637 && !mips_opts
.micromips
11638 && strcmp ("pref", insn
->name
) == 0)
11639 switch (imm_expr
.X_add_number
)
11648 case 31: /* These are ok. */
11651 default: /* The rest must be changed to 28. */
11652 imm_expr
.X_add_number
= 28;
11655 INSERT_OPERAND (mips_opts
.micromips
,
11656 CACHE
, *ip
, imm_expr
.X_add_number
);
11659 INSERT_OPERAND (mips_opts
.micromips
,
11660 PREFX
, *ip
, imm_expr
.X_add_number
);
11663 INSERT_OPERAND (mips_opts
.micromips
,
11664 STYPE
, *ip
, imm_expr
.X_add_number
);
11667 imm_expr
.X_op
= O_absent
;
11671 case 'c': /* BREAK code. */
11673 unsigned long mask
= (mips_opts
.micromips
11674 ? MICROMIPSOP_MASK_CODE
11677 my_getExpression (&imm_expr
, s
);
11678 check_absolute_expr (ip
, &imm_expr
);
11679 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11680 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11682 mask
, (unsigned long) imm_expr
.X_add_number
);
11683 INSERT_OPERAND (mips_opts
.micromips
,
11684 CODE
, *ip
, imm_expr
.X_add_number
);
11685 imm_expr
.X_op
= O_absent
;
11690 case 'q': /* Lower BREAK code. */
11692 unsigned long mask
= (mips_opts
.micromips
11693 ? MICROMIPSOP_MASK_CODE2
11696 my_getExpression (&imm_expr
, s
);
11697 check_absolute_expr (ip
, &imm_expr
);
11698 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11699 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11701 mask
, (unsigned long) imm_expr
.X_add_number
);
11702 INSERT_OPERAND (mips_opts
.micromips
,
11703 CODE2
, *ip
, imm_expr
.X_add_number
);
11704 imm_expr
.X_op
= O_absent
;
11709 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11711 unsigned long mask
= (mips_opts
.micromips
11712 ? MICROMIPSOP_MASK_CODE10
11715 my_getExpression (&imm_expr
, s
);
11716 check_absolute_expr (ip
, &imm_expr
);
11717 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11718 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11720 mask
, (unsigned long) imm_expr
.X_add_number
);
11721 if (mips_opts
.micromips
)
11722 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11724 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11725 imm_expr
.X_op
= O_absent
;
11730 case 'C': /* 25- or 23-bit coprocessor code. */
11732 unsigned long mask
= (mips_opts
.micromips
11733 ? MICROMIPSOP_MASK_COPZ
11736 my_getExpression (&imm_expr
, s
);
11737 check_absolute_expr (ip
, &imm_expr
);
11738 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11739 as_warn (_("Coproccesor code > %u bits (%lu)"),
11740 mips_opts
.micromips
? 23U : 25U,
11741 (unsigned long) imm_expr
.X_add_number
);
11742 INSERT_OPERAND (mips_opts
.micromips
,
11743 COPZ
, *ip
, imm_expr
.X_add_number
);
11744 imm_expr
.X_op
= O_absent
;
11749 case 'J': /* 19-bit WAIT code. */
11750 gas_assert (!mips_opts
.micromips
);
11751 my_getExpression (&imm_expr
, s
);
11752 check_absolute_expr (ip
, &imm_expr
);
11753 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11755 as_warn (_("Illegal 19-bit code (%lu)"),
11756 (unsigned long) imm_expr
.X_add_number
);
11757 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11759 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11760 imm_expr
.X_op
= O_absent
;
11764 case 'P': /* Performance register. */
11765 gas_assert (!mips_opts
.micromips
);
11766 my_getExpression (&imm_expr
, s
);
11767 check_absolute_expr (ip
, &imm_expr
);
11768 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11769 as_warn (_("Invalid performance register (%lu)"),
11770 (unsigned long) imm_expr
.X_add_number
);
11771 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11772 imm_expr
.X_op
= O_absent
;
11776 case 'G': /* Coprocessor destination register. */
11778 unsigned long opcode
= ip
->insn_opcode
;
11779 unsigned long mask
;
11780 unsigned int types
;
11783 if (mips_opts
.micromips
)
11785 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11786 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11787 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11791 case 0x000000fc: /* mfc0 */
11792 case 0x000002fc: /* mtc0 */
11793 case 0x580000fc: /* dmfc0 */
11794 case 0x580002fc: /* dmtc0 */
11804 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11805 cop0
= opcode
== OP_OP_COP0
;
11807 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11808 ok
= reg_lookup (&s
, types
, ®no
);
11809 if (mips_opts
.micromips
)
11810 INSERT_OPERAND (1, RS
, *ip
, regno
);
11812 INSERT_OPERAND (0, RD
, *ip
, regno
);
11821 case 'y': /* ALNV.PS source register. */
11822 gas_assert (mips_opts
.micromips
);
11824 case 'x': /* Ignore register name. */
11825 case 'U': /* Destination register (CLO/CLZ). */
11826 case 'g': /* Coprocessor destination register. */
11827 gas_assert (!mips_opts
.micromips
);
11828 case 'b': /* Base register. */
11829 case 'd': /* Destination register. */
11830 case 's': /* Source register. */
11831 case 't': /* Target register. */
11832 case 'r': /* Both target and source. */
11833 case 'v': /* Both dest and source. */
11834 case 'w': /* Both dest and target. */
11835 case 'E': /* Coprocessor target register. */
11836 case 'K': /* RDHWR destination register. */
11837 case 'z': /* Must be zero register. */
11840 if (*args
== 'E' || *args
== 'K')
11841 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11844 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11845 if (regno
== AT
&& mips_opts
.at
)
11847 if (mips_opts
.at
== ATREG
)
11848 as_warn (_("Used $at without \".set noat\""));
11850 as_warn (_("Used $%u with \".set at=$%u\""),
11851 regno
, mips_opts
.at
);
11861 if (c
== 'r' || c
== 'v' || c
== 'w')
11868 /* 'z' only matches $0. */
11869 if (c
== 'z' && regno
!= 0)
11872 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11874 if (regno
== lastregno
)
11877 = _("Source and destination must be different");
11880 if (regno
== 31 && lastregno
== 0xffffffff)
11883 = _("A destination register must be supplied");
11887 /* Now that we have assembled one operand, we use the args
11888 string to figure out where it goes in the instruction. */
11895 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11899 if (mips_opts
.micromips
)
11900 INSERT_OPERAND (1, RS
, *ip
, regno
);
11902 INSERT_OPERAND (0, RD
, *ip
, regno
);
11907 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11911 gas_assert (!mips_opts
.micromips
);
11912 INSERT_OPERAND (0, RD
, *ip
, regno
);
11913 INSERT_OPERAND (0, RT
, *ip
, regno
);
11919 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11923 gas_assert (mips_opts
.micromips
);
11924 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11928 /* This case exists because on the r3000 trunc
11929 expands into a macro which requires a gp
11930 register. On the r6000 or r4000 it is
11931 assembled into a single instruction which
11932 ignores the register. Thus the insn version
11933 is MIPS_ISA2 and uses 'x', and the macro
11934 version is MIPS_ISA1 and uses 't'. */
11938 /* This case is for the div instruction, which
11939 acts differently if the destination argument
11940 is $0. This only matches $0, and is checked
11941 outside the switch. */
11951 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11955 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11960 case 'O': /* MDMX alignment immediate constant. */
11961 gas_assert (!mips_opts
.micromips
);
11962 my_getExpression (&imm_expr
, s
);
11963 check_absolute_expr (ip
, &imm_expr
);
11964 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11965 as_warn (_("Improper align amount (%ld), using low bits"),
11966 (long) imm_expr
.X_add_number
);
11967 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11968 imm_expr
.X_op
= O_absent
;
11972 case 'Q': /* MDMX vector, element sel, or const. */
11975 /* MDMX Immediate. */
11976 gas_assert (!mips_opts
.micromips
);
11977 my_getExpression (&imm_expr
, s
);
11978 check_absolute_expr (ip
, &imm_expr
);
11979 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11980 as_warn (_("Invalid MDMX Immediate (%ld)"),
11981 (long) imm_expr
.X_add_number
);
11982 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11983 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11984 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11986 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11987 imm_expr
.X_op
= O_absent
;
11991 /* Not MDMX Immediate. Fall through. */
11992 case 'X': /* MDMX destination register. */
11993 case 'Y': /* MDMX source register. */
11994 case 'Z': /* MDMX target register. */
11997 gas_assert (!mips_opts
.micromips
);
11998 case 'D': /* Floating point destination register. */
11999 case 'S': /* Floating point source register. */
12000 case 'T': /* Floating point target register. */
12001 case 'R': /* Floating point source register. */
12005 || (mips_opts
.ase_mdmx
12006 && (ip
->insn_mo
->pinfo
& FP_D
)
12007 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12008 | INSN_COPROC_MEMORY_DELAY
12009 | INSN_LOAD_COPROC_DELAY
12010 | INSN_LOAD_MEMORY_DELAY
12011 | INSN_STORE_MEMORY
))))
12012 rtype
|= RTYPE_VEC
;
12014 if (reg_lookup (&s
, rtype
, ®no
))
12016 if ((regno
& 1) != 0
12018 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12019 as_warn (_("Float register should be even, was %d"),
12027 if (c
== 'V' || c
== 'W')
12038 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12044 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12048 /* This is like 'Z', but also needs to fix the MDMX
12049 vector/scalar select bits. Note that the
12050 scalar immediate case is handled above. */
12053 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12054 int max_el
= (is_qh
? 3 : 7);
12056 my_getExpression(&imm_expr
, s
);
12057 check_absolute_expr (ip
, &imm_expr
);
12059 if (imm_expr
.X_add_number
> max_el
)
12060 as_bad (_("Bad element selector %ld"),
12061 (long) imm_expr
.X_add_number
);
12062 imm_expr
.X_add_number
&= max_el
;
12063 ip
->insn_opcode
|= (imm_expr
.X_add_number
12066 imm_expr
.X_op
= O_absent
;
12068 as_warn (_("Expecting ']' found '%s'"), s
);
12074 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12075 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12078 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12081 /* Fall through. */
12085 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12089 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12099 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12103 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12109 my_getExpression (&imm_expr
, s
);
12110 if (imm_expr
.X_op
!= O_big
12111 && imm_expr
.X_op
!= O_constant
)
12112 insn_error
= _("absolute expression required");
12113 if (HAVE_32BIT_GPRS
)
12114 normalize_constant_expr (&imm_expr
);
12119 my_getExpression (&offset_expr
, s
);
12120 normalize_address_expr (&offset_expr
);
12121 *imm_reloc
= BFD_RELOC_32
;
12134 unsigned char temp
[8];
12136 unsigned int length
;
12141 /* These only appear as the last operand in an
12142 instruction, and every instruction that accepts
12143 them in any variant accepts them in all variants.
12144 This means we don't have to worry about backing out
12145 any changes if the instruction does not match.
12147 The difference between them is the size of the
12148 floating point constant and where it goes. For 'F'
12149 and 'L' the constant is 64 bits; for 'f' and 'l' it
12150 is 32 bits. Where the constant is placed is based
12151 on how the MIPS assembler does things:
12154 f -- immediate value
12157 The .lit4 and .lit8 sections are only used if
12158 permitted by the -G argument.
12160 The code below needs to know whether the target register
12161 is 32 or 64 bits wide. It relies on the fact 'f' and
12162 'F' are used with GPR-based instructions and 'l' and
12163 'L' are used with FPR-based instructions. */
12165 f64
= *args
== 'F' || *args
== 'L';
12166 using_gprs
= *args
== 'F' || *args
== 'f';
12168 save_in
= input_line_pointer
;
12169 input_line_pointer
= s
;
12170 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12172 s
= input_line_pointer
;
12173 input_line_pointer
= save_in
;
12174 if (err
!= NULL
&& *err
!= '\0')
12176 as_bad (_("Bad floating point constant: %s"), err
);
12177 memset (temp
, '\0', sizeof temp
);
12178 length
= f64
? 8 : 4;
12181 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12185 && (g_switch_value
< 4
12186 || (temp
[0] == 0 && temp
[1] == 0)
12187 || (temp
[2] == 0 && temp
[3] == 0))))
12189 imm_expr
.X_op
= O_constant
;
12190 if (!target_big_endian
)
12191 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12193 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12195 else if (length
> 4
12196 && !mips_disable_float_construction
12197 /* Constants can only be constructed in GPRs and
12198 copied to FPRs if the GPRs are at least as wide
12199 as the FPRs. Force the constant into memory if
12200 we are using 64-bit FPRs but the GPRs are only
12203 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12204 && ((temp
[0] == 0 && temp
[1] == 0)
12205 || (temp
[2] == 0 && temp
[3] == 0))
12206 && ((temp
[4] == 0 && temp
[5] == 0)
12207 || (temp
[6] == 0 && temp
[7] == 0)))
12209 /* The value is simple enough to load with a couple of
12210 instructions. If using 32-bit registers, set
12211 imm_expr to the high order 32 bits and offset_expr to
12212 the low order 32 bits. Otherwise, set imm_expr to
12213 the entire 64 bit constant. */
12214 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12216 imm_expr
.X_op
= O_constant
;
12217 offset_expr
.X_op
= O_constant
;
12218 if (!target_big_endian
)
12220 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12221 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12225 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12226 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12228 if (offset_expr
.X_add_number
== 0)
12229 offset_expr
.X_op
= O_absent
;
12231 else if (sizeof (imm_expr
.X_add_number
) > 4)
12233 imm_expr
.X_op
= O_constant
;
12234 if (!target_big_endian
)
12235 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12237 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12241 imm_expr
.X_op
= O_big
;
12242 imm_expr
.X_add_number
= 4;
12243 if (!target_big_endian
)
12245 generic_bignum
[0] = bfd_getl16 (temp
);
12246 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12247 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12248 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12252 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12253 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12254 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12255 generic_bignum
[3] = bfd_getb16 (temp
);
12261 const char *newname
;
12264 /* Switch to the right section. */
12266 subseg
= now_subseg
;
12269 default: /* unused default case avoids warnings. */
12271 newname
= RDATA_SECTION_NAME
;
12272 if (g_switch_value
>= 8)
12276 newname
= RDATA_SECTION_NAME
;
12279 gas_assert (g_switch_value
>= 4);
12283 new_seg
= subseg_new (newname
, (subsegT
) 0);
12285 bfd_set_section_flags (stdoutput
, new_seg
,
12290 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12291 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12292 record_alignment (new_seg
, 4);
12294 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12295 if (seg
== now_seg
)
12296 as_bad (_("Can't use floating point insn in this section"));
12298 /* Set the argument to the current address in the
12300 offset_expr
.X_op
= O_symbol
;
12301 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12302 offset_expr
.X_add_number
= 0;
12304 /* Put the floating point number into the section. */
12305 p
= frag_more ((int) length
);
12306 memcpy (p
, temp
, length
);
12308 /* Switch back to the original section. */
12309 subseg_set (seg
, subseg
);
12314 case 'i': /* 16-bit unsigned immediate. */
12315 case 'j': /* 16-bit signed immediate. */
12316 *imm_reloc
= BFD_RELOC_LO16
;
12317 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12320 offsetT minval
, maxval
;
12322 more
= (insn
+ 1 < past
12323 && strcmp (insn
->name
, insn
[1].name
) == 0);
12325 /* If the expression was written as an unsigned number,
12326 only treat it as signed if there are no more
12330 && sizeof (imm_expr
.X_add_number
) <= 4
12331 && imm_expr
.X_op
== O_constant
12332 && imm_expr
.X_add_number
< 0
12333 && imm_expr
.X_unsigned
12334 && HAVE_64BIT_GPRS
)
12337 /* For compatibility with older assemblers, we accept
12338 0x8000-0xffff as signed 16-bit numbers when only
12339 signed numbers are allowed. */
12341 minval
= 0, maxval
= 0xffff;
12343 minval
= -0x8000, maxval
= 0x7fff;
12345 minval
= -0x8000, maxval
= 0xffff;
12347 if (imm_expr
.X_op
!= O_constant
12348 || imm_expr
.X_add_number
< minval
12349 || imm_expr
.X_add_number
> maxval
)
12353 if (imm_expr
.X_op
== O_constant
12354 || imm_expr
.X_op
== O_big
)
12355 as_bad (_("Expression out of range"));
12361 case 'o': /* 16-bit offset. */
12362 offset_reloc
[0] = BFD_RELOC_LO16
;
12363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12366 /* Check whether there is only a single bracketed expression
12367 left. If so, it must be the base register and the
12368 constant must be zero. */
12369 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12371 offset_expr
.X_op
= O_constant
;
12372 offset_expr
.X_add_number
= 0;
12376 /* If this value won't fit into a 16 bit offset, then go
12377 find a macro that will generate the 32 bit offset
12379 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12380 && (offset_expr
.X_op
!= O_constant
12381 || offset_expr
.X_add_number
>= 0x8000
12382 || offset_expr
.X_add_number
< -0x8000))
12388 case 'p': /* PC-relative offset. */
12389 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12390 my_getExpression (&offset_expr
, s
);
12394 case 'u': /* Upper 16 bits. */
12395 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12396 && imm_expr
.X_op
== O_constant
12397 && (imm_expr
.X_add_number
< 0
12398 || imm_expr
.X_add_number
>= 0x10000))
12399 as_bad (_("lui expression (%lu) not in range 0..65535"),
12400 (unsigned long) imm_expr
.X_add_number
);
12404 case 'a': /* 26-bit address. */
12405 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12406 my_getExpression (&offset_expr
, s
);
12410 case 'N': /* 3-bit branch condition code. */
12411 case 'M': /* 3-bit compare condition code. */
12413 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12414 rtype
|= RTYPE_FCC
;
12415 if (!reg_lookup (&s
, rtype
, ®no
))
12417 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12418 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12419 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12420 && (regno
& 1) != 0)
12421 as_warn (_("Condition code register should be even for %s, "
12424 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12425 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12426 && (regno
& 3) != 0)
12427 as_warn (_("Condition code register should be 0 or 4 for %s, "
12431 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12433 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12437 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12448 while (ISDIGIT (*s
));
12451 c
= 8; /* Invalid sel value. */
12454 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12455 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12459 gas_assert (!mips_opts
.micromips
);
12460 /* Must be at least one digit. */
12461 my_getExpression (&imm_expr
, s
);
12462 check_absolute_expr (ip
, &imm_expr
);
12464 if ((unsigned long) imm_expr
.X_add_number
12465 > (unsigned long) OP_MASK_VECBYTE
)
12467 as_bad (_("bad byte vector index (%ld)"),
12468 (long) imm_expr
.X_add_number
);
12469 imm_expr
.X_add_number
= 0;
12472 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12473 imm_expr
.X_op
= O_absent
;
12478 gas_assert (!mips_opts
.micromips
);
12479 my_getExpression (&imm_expr
, s
);
12480 check_absolute_expr (ip
, &imm_expr
);
12482 if ((unsigned long) imm_expr
.X_add_number
12483 > (unsigned long) OP_MASK_VECALIGN
)
12485 as_bad (_("bad byte vector index (%ld)"),
12486 (long) imm_expr
.X_add_number
);
12487 imm_expr
.X_add_number
= 0;
12490 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12491 imm_expr
.X_op
= O_absent
;
12495 case 'm': /* Opcode extension character. */
12496 gas_assert (mips_opts
.micromips
);
12501 if (strncmp (s
, "$pc", 3) == 0)
12529 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12530 if (regno
== AT
&& mips_opts
.at
)
12532 if (mips_opts
.at
== ATREG
)
12533 as_warn (_("Used $at without \".set noat\""));
12535 as_warn (_("Used $%u with \".set at=$%u\""),
12536 regno
, mips_opts
.at
);
12542 gas_assert (args
[1] == ',');
12548 gas_assert (args
[1] == ',');
12550 continue; /* Nothing to do. */
12556 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12558 if (regno
== lastregno
)
12561 = _("Source and destination must be different");
12564 if (regno
== 31 && lastregno
== 0xffffffff)
12567 = _("A destination register must be supplied");
12578 gas_assert (args
[1] == ',');
12585 gas_assert (args
[1] == ',');
12588 continue; /* Nothing to do. */
12592 /* Make sure regno is the same as lastregno. */
12593 if (c
== 't' && regno
!= lastregno
)
12596 /* Make sure regno is the same as destregno. */
12597 if (c
== 'x' && regno
!= destregno
)
12600 /* We need to save regno, before regno maps to the
12601 microMIPS register encoding. */
12611 regno
= ILLEGAL_REG
;
12615 regno
= mips32_to_micromips_reg_b_map
[regno
];
12619 regno
= mips32_to_micromips_reg_c_map
[regno
];
12623 regno
= mips32_to_micromips_reg_d_map
[regno
];
12627 regno
= mips32_to_micromips_reg_e_map
[regno
];
12631 regno
= mips32_to_micromips_reg_f_map
[regno
];
12635 regno
= mips32_to_micromips_reg_g_map
[regno
];
12639 regno
= mips32_to_micromips_reg_h_map
[regno
];
12643 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12648 else if (regno
== 22)
12650 else if (regno
== 5)
12652 else if (regno
== 6)
12654 else if (regno
== 7)
12657 regno
= ILLEGAL_REG
;
12663 else if (regno
== 7)
12666 regno
= ILLEGAL_REG
;
12673 regno
= ILLEGAL_REG
;
12677 regno
= ILLEGAL_REG
;
12683 regno
= mips32_to_micromips_reg_l_map
[regno
];
12687 regno
= mips32_to_micromips_reg_m_map
[regno
];
12691 regno
= mips32_to_micromips_reg_n_map
[regno
];
12695 regno
= mips32_to_micromips_reg_q_map
[regno
];
12700 regno
= ILLEGAL_REG
;
12705 regno
= ILLEGAL_REG
;
12710 regno
= ILLEGAL_REG
;
12713 case 'j': /* Do nothing. */
12723 if (regno
== ILLEGAL_REG
)
12729 INSERT_OPERAND (1, MB
, *ip
, regno
);
12733 INSERT_OPERAND (1, MC
, *ip
, regno
);
12737 INSERT_OPERAND (1, MD
, *ip
, regno
);
12741 INSERT_OPERAND (1, ME
, *ip
, regno
);
12745 INSERT_OPERAND (1, MF
, *ip
, regno
);
12749 INSERT_OPERAND (1, MG
, *ip
, regno
);
12753 INSERT_OPERAND (1, MH
, *ip
, regno
);
12757 INSERT_OPERAND (1, MI
, *ip
, regno
);
12761 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12765 INSERT_OPERAND (1, ML
, *ip
, regno
);
12769 INSERT_OPERAND (1, MM
, *ip
, regno
);
12773 INSERT_OPERAND (1, MN
, *ip
, regno
);
12777 INSERT_OPERAND (1, MP
, *ip
, regno
);
12781 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12784 case 'a': /* Do nothing. */
12785 case 's': /* Do nothing. */
12786 case 't': /* Do nothing. */
12787 case 'x': /* Do nothing. */
12788 case 'y': /* Do nothing. */
12789 case 'z': /* Do nothing. */
12799 bfd_reloc_code_real_type r
[3];
12803 /* Check whether there is only a single bracketed
12804 expression left. If so, it must be the base register
12805 and the constant must be zero. */
12806 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12808 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12812 if (my_getSmallExpression (&ep
, r
, s
) > 0
12813 || !expr_const_in_range (&ep
, -64, 64, 2))
12816 imm
= ep
.X_add_number
>> 2;
12817 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12824 bfd_reloc_code_real_type r
[3];
12828 if (my_getSmallExpression (&ep
, r
, s
) > 0
12829 || ep
.X_op
!= O_constant
)
12832 for (imm
= 0; imm
< 8; imm
++)
12833 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12838 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12845 bfd_reloc_code_real_type r
[3];
12849 if (my_getSmallExpression (&ep
, r
, s
) > 0
12850 || ep
.X_op
!= O_constant
)
12853 for (imm
= 0; imm
< 16; imm
++)
12854 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12859 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12864 case 'D': /* pc relative offset */
12865 case 'E': /* pc relative offset */
12866 my_getExpression (&offset_expr
, s
);
12867 if (offset_expr
.X_op
== O_register
)
12870 if (!forced_insn_length
)
12871 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12873 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12875 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12881 bfd_reloc_code_real_type r
[3];
12885 if (my_getSmallExpression (&ep
, r
, s
) > 0
12886 || !expr_const_in_range (&ep
, 0, 16, 0))
12889 imm
= ep
.X_add_number
;
12890 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12897 bfd_reloc_code_real_type r
[3];
12901 /* Check whether there is only a single bracketed
12902 expression left. If so, it must be the base register
12903 and the constant must be zero. */
12904 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12906 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12910 if (my_getSmallExpression (&ep
, r
, s
) > 0
12911 || !expr_const_in_range (&ep
, -1, 15, 0))
12914 imm
= ep
.X_add_number
& 15;
12915 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12922 bfd_reloc_code_real_type r
[3];
12926 /* Check whether there is only a single bracketed
12927 expression left. If so, it must be the base register
12928 and the constant must be zero. */
12929 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12931 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12935 if (my_getSmallExpression (&ep
, r
, s
) > 0
12936 || !expr_const_in_range (&ep
, 0, 16, 1))
12939 imm
= ep
.X_add_number
>> 1;
12940 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12947 bfd_reloc_code_real_type r
[3];
12951 if (my_getSmallExpression (&ep
, r
, s
) > 0
12952 || !expr_const_in_range (&ep
, -1, 127, 0))
12955 imm
= ep
.X_add_number
& 127;
12956 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12963 bfd_reloc_code_real_type r
[3];
12967 /* Check whether there is only a single bracketed
12968 expression left. If so, it must be the base register
12969 and the constant must be zero. */
12970 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12972 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12976 if (my_getSmallExpression (&ep
, r
, s
) > 0
12977 || !expr_const_in_range (&ep
, 0, 16, 2))
12980 imm
= ep
.X_add_number
>> 2;
12981 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12988 bfd_reloc_code_real_type r
[3];
12992 /* Check whether there is only a single bracketed
12993 expression left. If so, it must be the base register
12994 and the constant must be zero. */
12995 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12997 INSERT_OPERAND (1, IMML
, *ip
, 0);
13001 if (my_getSmallExpression (&ep
, r
, s
) > 0
13002 || !expr_const_in_range (&ep
, 0, 16, 0))
13005 imm
= ep
.X_add_number
;
13006 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13013 bfd_reloc_code_real_type r
[3];
13017 if (my_getSmallExpression (&ep
, r
, s
) > 0
13018 || !expr_const_in_range (&ep
, 1, 9, 0))
13021 imm
= ep
.X_add_number
& 7;
13022 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13027 case 'N': /* Register list for lwm and swm. */
13029 /* A comma-separated list of registers and/or
13030 dash-separated contiguous ranges including
13031 both ra and a set of one or more registers
13032 starting at s0 up to s3 which have to be
13039 and any permutations of these. */
13040 unsigned int reglist
;
13043 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13046 if ((reglist
& 0xfff1ffff) != 0x80010000)
13049 reglist
= (reglist
>> 17) & 7;
13051 if ((reglist
& -reglist
) != reglist
)
13054 imm
= ffs (reglist
) - 1;
13055 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13059 case 'O': /* sdbbp 4-bit code. */
13061 bfd_reloc_code_real_type r
[3];
13065 if (my_getSmallExpression (&ep
, r
, s
) > 0
13066 || !expr_const_in_range (&ep
, 0, 16, 0))
13069 imm
= ep
.X_add_number
;
13070 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13077 bfd_reloc_code_real_type r
[3];
13081 if (my_getSmallExpression (&ep
, r
, s
) > 0
13082 || !expr_const_in_range (&ep
, 0, 32, 2))
13085 imm
= ep
.X_add_number
>> 2;
13086 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13093 bfd_reloc_code_real_type r
[3];
13097 if (my_getSmallExpression (&ep
, r
, s
) > 0
13098 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13101 imm
= ep
.X_add_number
>> 2;
13102 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13109 bfd_reloc_code_real_type r
[3];
13113 /* Check whether there is only a single bracketed
13114 expression left. If so, it must be the base register
13115 and the constant must be zero. */
13116 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13118 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13122 if (my_getSmallExpression (&ep
, r
, s
) > 0
13123 || !expr_const_in_range (&ep
, 0, 32, 2))
13126 imm
= ep
.X_add_number
>> 2;
13127 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13134 bfd_reloc_code_real_type r
[3];
13138 if (my_getSmallExpression (&ep
, r
, s
) > 0
13139 || !expr_const_in_range (&ep
, 0, 64, 2))
13142 imm
= ep
.X_add_number
>> 2;
13143 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13150 bfd_reloc_code_real_type r
[3];
13154 if (my_getSmallExpression (&ep
, r
, s
) > 0
13155 || !expr_const_in_range (&ep
, -8, 8, 0))
13158 imm
= ep
.X_add_number
;
13159 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13166 bfd_reloc_code_real_type r
[3];
13170 if (my_getSmallExpression (&ep
, r
, s
) > 0
13171 || expr_const_in_range (&ep
, -2, 2, 2)
13172 || !expr_const_in_range (&ep
, -258, 258, 2))
13175 imm
= ep
.X_add_number
>> 2;
13176 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13177 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13184 bfd_reloc_code_real_type r
[3];
13187 if (my_getSmallExpression (&ep
, r
, s
) > 0
13188 || !expr_const_in_range (&ep
, 0, 1, 0))
13195 as_bad (_("Internal error: bad microMIPS opcode "
13196 "(unknown extension operand type `m%c'): %s %s"),
13197 *args
, insn
->name
, insn
->args
);
13198 /* Further processing is fruitless. */
13203 case 'n': /* Register list for 32-bit lwm and swm. */
13204 gas_assert (mips_opts
.micromips
);
13206 /* A comma-separated list of registers and/or
13207 dash-separated contiguous ranges including
13208 at least one of ra and a set of one or more
13209 registers starting at s0 up to s7 and then
13210 s8 which have to be consecutive, e.g.:
13218 and any permutations of these. */
13219 unsigned int reglist
;
13223 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13226 if ((reglist
& 0x3f00ffff) != 0)
13229 ra
= (reglist
>> 27) & 0x10;
13230 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13232 if ((reglist
& -reglist
) != reglist
)
13235 imm
= (ffs (reglist
) - 1) | ra
;
13236 INSERT_OPERAND (1, RT
, *ip
, imm
);
13237 imm_expr
.X_op
= O_absent
;
13241 case '|': /* 4-bit trap code. */
13242 gas_assert (mips_opts
.micromips
);
13243 my_getExpression (&imm_expr
, s
);
13244 check_absolute_expr (ip
, &imm_expr
);
13245 if ((unsigned long) imm_expr
.X_add_number
13246 > MICROMIPSOP_MASK_TRAP
)
13247 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13248 (unsigned long) imm_expr
.X_add_number
,
13249 ip
->insn_mo
->name
);
13250 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13251 imm_expr
.X_op
= O_absent
;
13256 as_bad (_("Bad char = '%c'\n"), *args
);
13261 /* Args don't match. */
13263 insn_error
= _("Illegal operands");
13264 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13269 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13271 gas_assert (firstinsn
);
13272 need_delay_slot_ok
= FALSE
;
13281 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13283 /* This routine assembles an instruction into its binary format when
13284 assembling for the mips16. As a side effect, it sets one of the
13285 global variables imm_reloc or offset_reloc to the type of relocation
13286 to do if one of the operands is an address expression. It also sets
13287 forced_insn_length to the resulting instruction size in bytes if the
13288 user explicitly requested a small or extended instruction. */
13291 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13295 struct mips_opcode
*insn
;
13297 unsigned int regno
;
13298 unsigned int lastregno
= 0;
13304 forced_insn_length
= 0;
13306 for (s
= str
; ISLOWER (*s
); ++s
)
13318 if (s
[1] == 't' && s
[2] == ' ')
13321 forced_insn_length
= 2;
13325 else if (s
[1] == 'e' && s
[2] == ' ')
13328 forced_insn_length
= 4;
13332 /* Fall through. */
13334 insn_error
= _("unknown opcode");
13338 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13339 forced_insn_length
= 2;
13341 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13343 insn_error
= _("unrecognized opcode");
13352 gas_assert (strcmp (insn
->name
, str
) == 0);
13354 ok
= is_opcode_valid_16 (insn
);
13357 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13358 && strcmp (insn
->name
, insn
[1].name
) == 0)
13367 static char buf
[100];
13369 _("Opcode not supported on this processor: %s (%s)"),
13370 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13371 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13378 create_insn (ip
, insn
);
13379 imm_expr
.X_op
= O_absent
;
13380 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13381 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13382 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13383 imm2_expr
.X_op
= O_absent
;
13384 offset_expr
.X_op
= O_absent
;
13385 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13386 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13387 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13388 for (args
= insn
->args
; 1; ++args
)
13395 /* In this switch statement we call break if we did not find
13396 a match, continue if we did find a match, or return if we
13407 /* Stuff the immediate value in now, if we can. */
13408 if (imm_expr
.X_op
== O_constant
13409 && *imm_reloc
> BFD_RELOC_UNUSED
13410 && insn
->pinfo
!= INSN_MACRO
13411 && calculate_reloc (*offset_reloc
,
13412 imm_expr
.X_add_number
, &value
))
13414 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13415 *offset_reloc
, value
, forced_insn_length
,
13417 imm_expr
.X_op
= O_absent
;
13418 *imm_reloc
= BFD_RELOC_UNUSED
;
13419 *offset_reloc
= BFD_RELOC_UNUSED
;
13433 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13436 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13452 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13454 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13458 /* Fall through. */
13469 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13471 if (c
== 'v' || c
== 'w')
13474 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13476 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13487 if (c
== 'v' || c
== 'w')
13489 regno
= mips16_to_32_reg_map
[lastregno
];
13503 regno
= mips32_to_16_reg_map
[regno
];
13508 regno
= ILLEGAL_REG
;
13513 regno
= ILLEGAL_REG
;
13518 regno
= ILLEGAL_REG
;
13523 if (regno
== AT
&& mips_opts
.at
)
13525 if (mips_opts
.at
== ATREG
)
13526 as_warn (_("used $at without \".set noat\""));
13528 as_warn (_("used $%u with \".set at=$%u\""),
13529 regno
, mips_opts
.at
);
13537 if (regno
== ILLEGAL_REG
)
13544 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13548 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13551 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13554 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13560 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13563 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13564 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13574 if (strncmp (s
, "$pc", 3) == 0)
13591 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13594 if (imm_expr
.X_op
!= O_constant
)
13596 forced_insn_length
= 4;
13597 ip
->insn_opcode
|= MIPS16_EXTEND
;
13601 /* We need to relax this instruction. */
13602 *offset_reloc
= *imm_reloc
;
13603 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13608 *imm_reloc
= BFD_RELOC_UNUSED
;
13609 /* Fall through. */
13616 my_getExpression (&imm_expr
, s
);
13617 if (imm_expr
.X_op
== O_register
)
13619 /* What we thought was an expression turned out to
13622 if (s
[0] == '(' && args
[1] == '(')
13624 /* It looks like the expression was omitted
13625 before a register indirection, which means
13626 that the expression is implicitly zero. We
13627 still set up imm_expr, so that we handle
13628 explicit extensions correctly. */
13629 imm_expr
.X_op
= O_constant
;
13630 imm_expr
.X_add_number
= 0;
13631 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13638 /* We need to relax this instruction. */
13639 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13648 /* We use offset_reloc rather than imm_reloc for the PC
13649 relative operands. This lets macros with both
13650 immediate and address operands work correctly. */
13651 my_getExpression (&offset_expr
, s
);
13653 if (offset_expr
.X_op
== O_register
)
13656 /* We need to relax this instruction. */
13657 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13661 case '6': /* break code */
13662 my_getExpression (&imm_expr
, s
);
13663 check_absolute_expr (ip
, &imm_expr
);
13664 if ((unsigned long) imm_expr
.X_add_number
> 63)
13665 as_warn (_("Invalid value for `%s' (%lu)"),
13667 (unsigned long) imm_expr
.X_add_number
);
13668 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13669 imm_expr
.X_op
= O_absent
;
13673 case 'a': /* 26 bit address */
13674 my_getExpression (&offset_expr
, s
);
13676 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13677 ip
->insn_opcode
<<= 16;
13680 case 'l': /* register list for entry macro */
13681 case 'L': /* register list for exit macro */
13691 unsigned int freg
, reg1
, reg2
;
13693 while (*s
== ' ' || *s
== ',')
13695 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13697 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13701 as_bad (_("can't parse register list"));
13711 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13712 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13714 as_bad (_("invalid register list"));
13718 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13720 mask
&= ~ (7 << 3);
13723 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13725 mask
&= ~ (7 << 3);
13728 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13729 mask
|= (reg2
- 3) << 3;
13730 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13731 mask
|= (reg2
- 15) << 1;
13732 else if (reg1
== RA
&& reg2
== RA
)
13736 as_bad (_("invalid register list"));
13740 /* The mask is filled in in the opcode table for the
13741 benefit of the disassembler. We remove it before
13742 applying the actual mask. */
13743 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13744 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13748 case 'm': /* Register list for save insn. */
13749 case 'M': /* Register list for restore insn. */
13751 int opcode
= ip
->insn_opcode
;
13752 int framesz
= 0, seen_framesz
= 0;
13753 int nargs
= 0, statics
= 0, sregs
= 0;
13757 unsigned int reg1
, reg2
;
13759 SKIP_SPACE_TABS (s
);
13762 SKIP_SPACE_TABS (s
);
13764 my_getExpression (&imm_expr
, s
);
13765 if (imm_expr
.X_op
== O_constant
)
13767 /* Handle the frame size. */
13770 as_bad (_("more than one frame size in list"));
13774 framesz
= imm_expr
.X_add_number
;
13775 imm_expr
.X_op
= O_absent
;
13780 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13782 as_bad (_("can't parse register list"));
13794 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13797 as_bad (_("can't parse register list"));
13802 while (reg1
<= reg2
)
13804 if (reg1
>= 4 && reg1
<= 7)
13808 nargs
|= 1 << (reg1
- 4);
13810 /* statics $a0-$a3 */
13811 statics
|= 1 << (reg1
- 4);
13813 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13816 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13818 else if (reg1
== 31)
13820 /* Add $ra to insn. */
13825 as_bad (_("unexpected register in list"));
13833 /* Encode args/statics combination. */
13834 if (nargs
& statics
)
13835 as_bad (_("arg/static registers overlap"));
13836 else if (nargs
== 0xf)
13837 /* All $a0-$a3 are args. */
13838 opcode
|= MIPS16_ALL_ARGS
<< 16;
13839 else if (statics
== 0xf)
13840 /* All $a0-$a3 are statics. */
13841 opcode
|= MIPS16_ALL_STATICS
<< 16;
13844 int narg
= 0, nstat
= 0;
13846 /* Count arg registers. */
13847 while (nargs
& 0x1)
13853 as_bad (_("invalid arg register list"));
13855 /* Count static registers. */
13856 while (statics
& 0x8)
13858 statics
= (statics
<< 1) & 0xf;
13862 as_bad (_("invalid static register list"));
13864 /* Encode args/statics. */
13865 opcode
|= ((narg
<< 2) | nstat
) << 16;
13868 /* Encode $s0/$s1. */
13869 if (sregs
& (1 << 0)) /* $s0 */
13871 if (sregs
& (1 << 1)) /* $s1 */
13877 /* Count regs $s2-$s8. */
13885 as_bad (_("invalid static register list"));
13886 /* Encode $s2-$s8. */
13887 opcode
|= nsreg
<< 24;
13890 /* Encode frame size. */
13892 as_bad (_("missing frame size"));
13893 else if ((framesz
& 7) != 0 || framesz
< 0
13894 || framesz
> 0xff * 8)
13895 as_bad (_("invalid frame size"));
13896 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13899 opcode
|= (((framesz
& 0xf0) << 16)
13900 | (framesz
& 0x0f));
13903 /* Finally build the instruction. */
13904 if ((opcode
>> 16) != 0 || framesz
== 0)
13905 opcode
|= MIPS16_EXTEND
;
13906 ip
->insn_opcode
= opcode
;
13910 case 'e': /* extend code */
13911 my_getExpression (&imm_expr
, s
);
13912 check_absolute_expr (ip
, &imm_expr
);
13913 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13915 as_warn (_("Invalid value for `%s' (%lu)"),
13917 (unsigned long) imm_expr
.X_add_number
);
13918 imm_expr
.X_add_number
&= 0x7ff;
13920 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13921 imm_expr
.X_op
= O_absent
;
13931 /* Args don't match. */
13932 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13933 strcmp (insn
->name
, insn
[1].name
) == 0)
13940 insn_error
= _("illegal operands");
13946 /* This structure holds information we know about a mips16 immediate
13949 struct mips16_immed_operand
13951 /* The type code used in the argument string in the opcode table. */
13953 /* The number of bits in the short form of the opcode. */
13955 /* The number of bits in the extended form of the opcode. */
13957 /* The amount by which the short form is shifted when it is used;
13958 for example, the sw instruction has a shift count of 2. */
13960 /* The amount by which the short form is shifted when it is stored
13961 into the instruction code. */
13963 /* Non-zero if the short form is unsigned. */
13965 /* Non-zero if the extended form is unsigned. */
13967 /* Non-zero if the value is PC relative. */
13971 /* The mips16 immediate operand types. */
13973 static const struct mips16_immed_operand mips16_immed_operands
[] =
13975 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13976 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13977 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13978 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13979 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13980 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13981 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13982 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13983 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13984 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13985 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13986 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13987 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13988 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13989 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13990 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13991 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13992 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13993 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13994 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13995 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13998 #define MIPS16_NUM_IMMED \
13999 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14001 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14002 NBITS is the number of significant bits in VAL. */
14004 static unsigned long
14005 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14010 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14013 else if (nbits
== 15)
14015 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14020 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14023 return (extval
<< 16) | val
;
14026 /* Install immediate value VAL into MIPS16 instruction *INSN,
14027 extending it if necessary. The instruction in *INSN may
14028 already be extended.
14030 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14031 if none. In the former case, VAL is a 16-bit number with no
14032 defined signedness.
14034 TYPE is the type of the immediate field. USER_INSN_LENGTH
14035 is the length that the user requested, or 0 if none. */
14038 mips16_immed (char *file
, unsigned int line
, int type
,
14039 bfd_reloc_code_real_type reloc
, offsetT val
,
14040 unsigned int user_insn_length
, unsigned long *insn
)
14042 const struct mips16_immed_operand
*op
;
14043 int mintiny
, maxtiny
;
14045 op
= mips16_immed_operands
;
14046 while (op
->type
!= type
)
14049 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14054 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14057 maxtiny
= 1 << op
->nbits
;
14062 maxtiny
= (1 << op
->nbits
) - 1;
14064 if (reloc
!= BFD_RELOC_UNUSED
)
14069 mintiny
= - (1 << (op
->nbits
- 1));
14070 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14071 if (reloc
!= BFD_RELOC_UNUSED
)
14072 val
= SEXT_16BIT (val
);
14075 /* Branch offsets have an implicit 0 in the lowest bit. */
14076 if (type
== 'p' || type
== 'q')
14079 if ((val
& ((1 << op
->shift
) - 1)) != 0
14080 || val
< (mintiny
<< op
->shift
)
14081 || val
> (maxtiny
<< op
->shift
))
14083 /* We need an extended instruction. */
14084 if (user_insn_length
== 2)
14085 as_bad_where (file
, line
, _("invalid unextended operand value"));
14087 *insn
|= MIPS16_EXTEND
;
14089 else if (user_insn_length
== 4)
14091 /* The operand doesn't force an unextended instruction to be extended.
14092 Warn if the user wanted an extended instruction anyway. */
14093 *insn
|= MIPS16_EXTEND
;
14094 as_warn_where (file
, line
,
14095 _("extended operand requested but not required"));
14098 if (mips16_opcode_length (*insn
) == 2)
14102 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14103 insnval
<<= op
->op_shift
;
14108 long minext
, maxext
;
14110 if (reloc
== BFD_RELOC_UNUSED
)
14115 maxext
= (1 << op
->extbits
) - 1;
14119 minext
= - (1 << (op
->extbits
- 1));
14120 maxext
= (1 << (op
->extbits
- 1)) - 1;
14122 if (val
< minext
|| val
> maxext
)
14123 as_bad_where (file
, line
,
14124 _("operand value out of range for instruction"));
14127 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14131 struct percent_op_match
14134 bfd_reloc_code_real_type reloc
;
14137 static const struct percent_op_match mips_percent_op
[] =
14139 {"%lo", BFD_RELOC_LO16
},
14141 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14142 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14143 {"%call16", BFD_RELOC_MIPS_CALL16
},
14144 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14145 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14146 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14147 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14148 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14149 {"%got", BFD_RELOC_MIPS_GOT16
},
14150 {"%gp_rel", BFD_RELOC_GPREL16
},
14151 {"%half", BFD_RELOC_16
},
14152 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14153 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14154 {"%neg", BFD_RELOC_MIPS_SUB
},
14155 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14156 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14157 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14158 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14159 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14160 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14161 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14163 {"%hi", BFD_RELOC_HI16_S
}
14166 static const struct percent_op_match mips16_percent_op
[] =
14168 {"%lo", BFD_RELOC_MIPS16_LO16
},
14169 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14170 {"%got", BFD_RELOC_MIPS16_GOT16
},
14171 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14172 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14173 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14174 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14175 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14176 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14177 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14178 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14179 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14183 /* Return true if *STR points to a relocation operator. When returning true,
14184 move *STR over the operator and store its relocation code in *RELOC.
14185 Leave both *STR and *RELOC alone when returning false. */
14188 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14190 const struct percent_op_match
*percent_op
;
14193 if (mips_opts
.mips16
)
14195 percent_op
= mips16_percent_op
;
14196 limit
= ARRAY_SIZE (mips16_percent_op
);
14200 percent_op
= mips_percent_op
;
14201 limit
= ARRAY_SIZE (mips_percent_op
);
14204 for (i
= 0; i
< limit
; i
++)
14205 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14207 int len
= strlen (percent_op
[i
].str
);
14209 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14212 *str
+= strlen (percent_op
[i
].str
);
14213 *reloc
= percent_op
[i
].reloc
;
14215 /* Check whether the output BFD supports this relocation.
14216 If not, issue an error and fall back on something safe. */
14217 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14219 as_bad (_("relocation %s isn't supported by the current ABI"),
14220 percent_op
[i
].str
);
14221 *reloc
= BFD_RELOC_UNUSED
;
14229 /* Parse string STR as a 16-bit relocatable operand. Store the
14230 expression in *EP and the relocations in the array starting
14231 at RELOC. Return the number of relocation operators used.
14233 On exit, EXPR_END points to the first character after the expression. */
14236 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14239 bfd_reloc_code_real_type reversed_reloc
[3];
14240 size_t reloc_index
, i
;
14241 int crux_depth
, str_depth
;
14244 /* Search for the start of the main expression, recoding relocations
14245 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14246 of the main expression and with CRUX_DEPTH containing the number
14247 of open brackets at that point. */
14254 crux_depth
= str_depth
;
14256 /* Skip over whitespace and brackets, keeping count of the number
14258 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14263 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14264 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14266 my_getExpression (ep
, crux
);
14269 /* Match every open bracket. */
14270 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14274 if (crux_depth
> 0)
14275 as_bad (_("unclosed '('"));
14279 if (reloc_index
!= 0)
14281 prev_reloc_op_frag
= frag_now
;
14282 for (i
= 0; i
< reloc_index
; i
++)
14283 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14286 return reloc_index
;
14290 my_getExpression (expressionS
*ep
, char *str
)
14294 save_in
= input_line_pointer
;
14295 input_line_pointer
= str
;
14297 expr_end
= input_line_pointer
;
14298 input_line_pointer
= save_in
;
14302 md_atof (int type
, char *litP
, int *sizeP
)
14304 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14308 md_number_to_chars (char *buf
, valueT val
, int n
)
14310 if (target_big_endian
)
14311 number_to_chars_bigendian (buf
, val
, n
);
14313 number_to_chars_littleendian (buf
, val
, n
);
14317 static int support_64bit_objects(void)
14319 const char **list
, **l
;
14322 list
= bfd_target_list ();
14323 for (l
= list
; *l
!= NULL
; l
++)
14324 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14325 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14327 yes
= (*l
!= NULL
);
14331 #endif /* OBJ_ELF */
14333 const char *md_shortopts
= "O::g::G:";
14337 OPTION_MARCH
= OPTION_MD_BASE
,
14359 OPTION_NO_SMARTMIPS
,
14363 OPTION_NO_MICROMIPS
,
14366 OPTION_COMPAT_ARCH_BASE
,
14375 OPTION_M7000_HILO_FIX
,
14376 OPTION_MNO_7000_HILO_FIX
,
14379 OPTION_FIX_LOONGSON2F_JUMP
,
14380 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14381 OPTION_FIX_LOONGSON2F_NOP
,
14382 OPTION_NO_FIX_LOONGSON2F_NOP
,
14384 OPTION_NO_FIX_VR4120
,
14386 OPTION_NO_FIX_VR4130
,
14387 OPTION_FIX_CN63XXP1
,
14388 OPTION_NO_FIX_CN63XXP1
,
14395 OPTION_CONSTRUCT_FLOATS
,
14396 OPTION_NO_CONSTRUCT_FLOATS
,
14399 OPTION_RELAX_BRANCH
,
14400 OPTION_NO_RELAX_BRANCH
,
14407 OPTION_SINGLE_FLOAT
,
14408 OPTION_DOUBLE_FLOAT
,
14411 OPTION_CALL_SHARED
,
14412 OPTION_CALL_NONPIC
,
14422 OPTION_MVXWORKS_PIC
,
14423 #endif /* OBJ_ELF */
14427 struct option md_longopts
[] =
14429 /* Options which specify architecture. */
14430 {"march", required_argument
, NULL
, OPTION_MARCH
},
14431 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14432 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14433 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14434 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14435 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14436 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14437 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14438 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14439 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14440 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14441 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14443 /* Options which specify Application Specific Extensions (ASEs). */
14444 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14445 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14446 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14447 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14448 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14449 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14450 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14451 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14452 {"mmt", no_argument
, NULL
, OPTION_MT
},
14453 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14454 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14455 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14456 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14457 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14458 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14459 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14460 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14461 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14463 /* Old-style architecture options. Don't add more of these. */
14464 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14465 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14466 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14467 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14468 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14469 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14470 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14471 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14473 /* Options which enable bug fixes. */
14474 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14475 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14476 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14477 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14478 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14479 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14480 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14481 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14482 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14483 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14484 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14485 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14486 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14487 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14488 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14490 /* Miscellaneous options. */
14491 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14492 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14493 {"break", no_argument
, NULL
, OPTION_BREAK
},
14494 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14495 {"EB", no_argument
, NULL
, OPTION_EB
},
14496 {"EL", no_argument
, NULL
, OPTION_EL
},
14497 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14498 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14499 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14500 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14501 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14502 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14503 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14504 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14505 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14506 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14507 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14508 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14509 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14510 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14511 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14512 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14514 /* Strictly speaking this next option is ELF specific,
14515 but we allow it for other ports as well in order to
14516 make testing easier. */
14517 {"32", no_argument
, NULL
, OPTION_32
},
14519 /* ELF-specific options. */
14521 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14522 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14523 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14524 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14525 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14526 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14527 {"n32", no_argument
, NULL
, OPTION_N32
},
14528 {"64", no_argument
, NULL
, OPTION_64
},
14529 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14530 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14531 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14532 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14533 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14534 #endif /* OBJ_ELF */
14536 {NULL
, no_argument
, NULL
, 0}
14538 size_t md_longopts_size
= sizeof (md_longopts
);
14540 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14541 NEW_VALUE. Warn if another value was already specified. Note:
14542 we have to defer parsing the -march and -mtune arguments in order
14543 to handle 'from-abi' correctly, since the ABI might be specified
14544 in a later argument. */
14547 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14549 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14550 as_warn (_("A different %s was already specified, is now %s"),
14551 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14554 *string_ptr
= new_value
;
14558 md_parse_option (int c
, char *arg
)
14562 case OPTION_CONSTRUCT_FLOATS
:
14563 mips_disable_float_construction
= 0;
14566 case OPTION_NO_CONSTRUCT_FLOATS
:
14567 mips_disable_float_construction
= 1;
14579 target_big_endian
= 1;
14583 target_big_endian
= 0;
14589 else if (arg
[0] == '0')
14591 else if (arg
[0] == '1')
14601 mips_debug
= atoi (arg
);
14605 file_mips_isa
= ISA_MIPS1
;
14609 file_mips_isa
= ISA_MIPS2
;
14613 file_mips_isa
= ISA_MIPS3
;
14617 file_mips_isa
= ISA_MIPS4
;
14621 file_mips_isa
= ISA_MIPS5
;
14624 case OPTION_MIPS32
:
14625 file_mips_isa
= ISA_MIPS32
;
14628 case OPTION_MIPS32R2
:
14629 file_mips_isa
= ISA_MIPS32R2
;
14632 case OPTION_MIPS64R2
:
14633 file_mips_isa
= ISA_MIPS64R2
;
14636 case OPTION_MIPS64
:
14637 file_mips_isa
= ISA_MIPS64
;
14641 mips_set_option_string (&mips_tune_string
, arg
);
14645 mips_set_option_string (&mips_arch_string
, arg
);
14649 mips_set_option_string (&mips_arch_string
, "4650");
14650 mips_set_option_string (&mips_tune_string
, "4650");
14653 case OPTION_NO_M4650
:
14657 mips_set_option_string (&mips_arch_string
, "4010");
14658 mips_set_option_string (&mips_tune_string
, "4010");
14661 case OPTION_NO_M4010
:
14665 mips_set_option_string (&mips_arch_string
, "4100");
14666 mips_set_option_string (&mips_tune_string
, "4100");
14669 case OPTION_NO_M4100
:
14673 mips_set_option_string (&mips_arch_string
, "3900");
14674 mips_set_option_string (&mips_tune_string
, "3900");
14677 case OPTION_NO_M3900
:
14681 mips_opts
.ase_mdmx
= 1;
14684 case OPTION_NO_MDMX
:
14685 mips_opts
.ase_mdmx
= 0;
14689 mips_opts
.ase_dsp
= 1;
14690 mips_opts
.ase_dspr2
= 0;
14693 case OPTION_NO_DSP
:
14694 mips_opts
.ase_dsp
= 0;
14695 mips_opts
.ase_dspr2
= 0;
14699 mips_opts
.ase_dspr2
= 1;
14700 mips_opts
.ase_dsp
= 1;
14703 case OPTION_NO_DSPR2
:
14704 mips_opts
.ase_dspr2
= 0;
14705 mips_opts
.ase_dsp
= 0;
14709 mips_opts
.ase_mt
= 1;
14713 mips_opts
.ase_mt
= 0;
14717 mips_opts
.ase_mcu
= 1;
14720 case OPTION_NO_MCU
:
14721 mips_opts
.ase_mcu
= 0;
14724 case OPTION_MICROMIPS
:
14725 if (mips_opts
.mips16
== 1)
14727 as_bad (_("-mmicromips cannot be used with -mips16"));
14730 mips_opts
.micromips
= 1;
14731 mips_no_prev_insn ();
14734 case OPTION_NO_MICROMIPS
:
14735 mips_opts
.micromips
= 0;
14736 mips_no_prev_insn ();
14739 case OPTION_MIPS16
:
14740 if (mips_opts
.micromips
== 1)
14742 as_bad (_("-mips16 cannot be used with -micromips"));
14745 mips_opts
.mips16
= 1;
14746 mips_no_prev_insn ();
14749 case OPTION_NO_MIPS16
:
14750 mips_opts
.mips16
= 0;
14751 mips_no_prev_insn ();
14754 case OPTION_MIPS3D
:
14755 mips_opts
.ase_mips3d
= 1;
14758 case OPTION_NO_MIPS3D
:
14759 mips_opts
.ase_mips3d
= 0;
14762 case OPTION_SMARTMIPS
:
14763 mips_opts
.ase_smartmips
= 1;
14766 case OPTION_NO_SMARTMIPS
:
14767 mips_opts
.ase_smartmips
= 0;
14770 case OPTION_FIX_24K
:
14774 case OPTION_NO_FIX_24K
:
14778 case OPTION_FIX_LOONGSON2F_JUMP
:
14779 mips_fix_loongson2f_jump
= TRUE
;
14782 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14783 mips_fix_loongson2f_jump
= FALSE
;
14786 case OPTION_FIX_LOONGSON2F_NOP
:
14787 mips_fix_loongson2f_nop
= TRUE
;
14790 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14791 mips_fix_loongson2f_nop
= FALSE
;
14794 case OPTION_FIX_VR4120
:
14795 mips_fix_vr4120
= 1;
14798 case OPTION_NO_FIX_VR4120
:
14799 mips_fix_vr4120
= 0;
14802 case OPTION_FIX_VR4130
:
14803 mips_fix_vr4130
= 1;
14806 case OPTION_NO_FIX_VR4130
:
14807 mips_fix_vr4130
= 0;
14810 case OPTION_FIX_CN63XXP1
:
14811 mips_fix_cn63xxp1
= TRUE
;
14814 case OPTION_NO_FIX_CN63XXP1
:
14815 mips_fix_cn63xxp1
= FALSE
;
14818 case OPTION_RELAX_BRANCH
:
14819 mips_relax_branch
= 1;
14822 case OPTION_NO_RELAX_BRANCH
:
14823 mips_relax_branch
= 0;
14826 case OPTION_MSHARED
:
14827 mips_in_shared
= TRUE
;
14830 case OPTION_MNO_SHARED
:
14831 mips_in_shared
= FALSE
;
14834 case OPTION_MSYM32
:
14835 mips_opts
.sym32
= TRUE
;
14838 case OPTION_MNO_SYM32
:
14839 mips_opts
.sym32
= FALSE
;
14843 /* When generating ELF code, we permit -KPIC and -call_shared to
14844 select SVR4_PIC, and -non_shared to select no PIC. This is
14845 intended to be compatible with Irix 5. */
14846 case OPTION_CALL_SHARED
:
14849 as_bad (_("-call_shared is supported only for ELF format"));
14852 mips_pic
= SVR4_PIC
;
14853 mips_abicalls
= TRUE
;
14856 case OPTION_CALL_NONPIC
:
14859 as_bad (_("-call_nonpic is supported only for ELF format"));
14863 mips_abicalls
= TRUE
;
14866 case OPTION_NON_SHARED
:
14869 as_bad (_("-non_shared is supported only for ELF format"));
14873 mips_abicalls
= FALSE
;
14876 /* The -xgot option tells the assembler to use 32 bit offsets
14877 when accessing the got in SVR4_PIC mode. It is for Irix
14882 #endif /* OBJ_ELF */
14885 g_switch_value
= atoi (arg
);
14889 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14893 mips_abi
= O32_ABI
;
14894 /* We silently ignore -32 for non-ELF targets. This greatly
14895 simplifies the construction of the MIPS GAS test cases. */
14902 as_bad (_("-n32 is supported for ELF format only"));
14905 mips_abi
= N32_ABI
;
14911 as_bad (_("-64 is supported for ELF format only"));
14914 mips_abi
= N64_ABI
;
14915 if (!support_64bit_objects())
14916 as_fatal (_("No compiled in support for 64 bit object file format"));
14918 #endif /* OBJ_ELF */
14921 file_mips_gp32
= 1;
14925 file_mips_gp32
= 0;
14929 file_mips_fp32
= 1;
14933 file_mips_fp32
= 0;
14936 case OPTION_SINGLE_FLOAT
:
14937 file_mips_single_float
= 1;
14940 case OPTION_DOUBLE_FLOAT
:
14941 file_mips_single_float
= 0;
14944 case OPTION_SOFT_FLOAT
:
14945 file_mips_soft_float
= 1;
14948 case OPTION_HARD_FLOAT
:
14949 file_mips_soft_float
= 0;
14956 as_bad (_("-mabi is supported for ELF format only"));
14959 if (strcmp (arg
, "32") == 0)
14960 mips_abi
= O32_ABI
;
14961 else if (strcmp (arg
, "o64") == 0)
14962 mips_abi
= O64_ABI
;
14963 else if (strcmp (arg
, "n32") == 0)
14964 mips_abi
= N32_ABI
;
14965 else if (strcmp (arg
, "64") == 0)
14967 mips_abi
= N64_ABI
;
14968 if (! support_64bit_objects())
14969 as_fatal (_("No compiled in support for 64 bit object file "
14972 else if (strcmp (arg
, "eabi") == 0)
14973 mips_abi
= EABI_ABI
;
14976 as_fatal (_("invalid abi -mabi=%s"), arg
);
14980 #endif /* OBJ_ELF */
14982 case OPTION_M7000_HILO_FIX
:
14983 mips_7000_hilo_fix
= TRUE
;
14986 case OPTION_MNO_7000_HILO_FIX
:
14987 mips_7000_hilo_fix
= FALSE
;
14991 case OPTION_MDEBUG
:
14992 mips_flag_mdebug
= TRUE
;
14995 case OPTION_NO_MDEBUG
:
14996 mips_flag_mdebug
= FALSE
;
15000 mips_flag_pdr
= TRUE
;
15003 case OPTION_NO_PDR
:
15004 mips_flag_pdr
= FALSE
;
15007 case OPTION_MVXWORKS_PIC
:
15008 mips_pic
= VXWORKS_PIC
;
15010 #endif /* OBJ_ELF */
15016 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15021 /* Set up globals to generate code for the ISA or processor
15022 described by INFO. */
15025 mips_set_architecture (const struct mips_cpu_info
*info
)
15029 file_mips_arch
= info
->cpu
;
15030 mips_opts
.arch
= info
->cpu
;
15031 mips_opts
.isa
= info
->isa
;
15036 /* Likewise for tuning. */
15039 mips_set_tune (const struct mips_cpu_info
*info
)
15042 mips_tune
= info
->cpu
;
15047 mips_after_parse_args (void)
15049 const struct mips_cpu_info
*arch_info
= 0;
15050 const struct mips_cpu_info
*tune_info
= 0;
15052 /* GP relative stuff not working for PE */
15053 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15055 if (g_switch_seen
&& g_switch_value
!= 0)
15056 as_bad (_("-G not supported in this configuration."));
15057 g_switch_value
= 0;
15060 if (mips_abi
== NO_ABI
)
15061 mips_abi
= MIPS_DEFAULT_ABI
;
15063 /* The following code determines the architecture and register size.
15064 Similar code was added to GCC 3.3 (see override_options() in
15065 config/mips/mips.c). The GAS and GCC code should be kept in sync
15066 as much as possible. */
15068 if (mips_arch_string
!= 0)
15069 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15071 if (file_mips_isa
!= ISA_UNKNOWN
)
15073 /* Handle -mipsN. At this point, file_mips_isa contains the
15074 ISA level specified by -mipsN, while arch_info->isa contains
15075 the -march selection (if any). */
15076 if (arch_info
!= 0)
15078 /* -march takes precedence over -mipsN, since it is more descriptive.
15079 There's no harm in specifying both as long as the ISA levels
15081 if (file_mips_isa
!= arch_info
->isa
)
15082 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15083 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15084 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15087 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15090 if (arch_info
== 0)
15092 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15093 gas_assert (arch_info
);
15096 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15097 as_bad (_("-march=%s is not compatible with the selected ABI"),
15100 mips_set_architecture (arch_info
);
15102 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15103 if (mips_tune_string
!= 0)
15104 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15106 if (tune_info
== 0)
15107 mips_set_tune (arch_info
);
15109 mips_set_tune (tune_info
);
15111 if (file_mips_gp32
>= 0)
15113 /* The user specified the size of the integer registers. Make sure
15114 it agrees with the ABI and ISA. */
15115 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15116 as_bad (_("-mgp64 used with a 32-bit processor"));
15117 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15118 as_bad (_("-mgp32 used with a 64-bit ABI"));
15119 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15120 as_bad (_("-mgp64 used with a 32-bit ABI"));
15124 /* Infer the integer register size from the ABI and processor.
15125 Restrict ourselves to 32-bit registers if that's all the
15126 processor has, or if the ABI cannot handle 64-bit registers. */
15127 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15128 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15131 switch (file_mips_fp32
)
15135 /* No user specified float register size.
15136 ??? GAS treats single-float processors as though they had 64-bit
15137 float registers (although it complains when double-precision
15138 instructions are used). As things stand, saying they have 32-bit
15139 registers would lead to spurious "register must be even" messages.
15140 So here we assume float registers are never smaller than the
15142 if (file_mips_gp32
== 0)
15143 /* 64-bit integer registers implies 64-bit float registers. */
15144 file_mips_fp32
= 0;
15145 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15146 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15147 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15148 file_mips_fp32
= 0;
15150 /* 32-bit float registers. */
15151 file_mips_fp32
= 1;
15154 /* The user specified the size of the float registers. Check if it
15155 agrees with the ABI and ISA. */
15157 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15158 as_bad (_("-mfp64 used with a 32-bit fpu"));
15159 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15160 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15161 as_warn (_("-mfp64 used with a 32-bit ABI"));
15164 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15165 as_warn (_("-mfp32 used with a 64-bit ABI"));
15169 /* End of GCC-shared inference code. */
15171 /* This flag is set when we have a 64-bit capable CPU but use only
15172 32-bit wide registers. Note that EABI does not use it. */
15173 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15174 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15175 || mips_abi
== O32_ABI
))
15176 mips_32bitmode
= 1;
15178 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15179 as_bad (_("trap exception not supported at ISA 1"));
15181 /* If the selected architecture includes support for ASEs, enable
15182 generation of code for them. */
15183 if (mips_opts
.mips16
== -1)
15184 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15185 if (mips_opts
.micromips
== -1)
15186 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15187 if (mips_opts
.ase_mips3d
== -1)
15188 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15189 && file_mips_fp32
== 0) ? 1 : 0;
15190 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15191 as_bad (_("-mfp32 used with -mips3d"));
15193 if (mips_opts
.ase_mdmx
== -1)
15194 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15195 && file_mips_fp32
== 0) ? 1 : 0;
15196 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15197 as_bad (_("-mfp32 used with -mdmx"));
15199 if (mips_opts
.ase_smartmips
== -1)
15200 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15201 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15202 as_warn (_("%s ISA does not support SmartMIPS"),
15203 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15205 if (mips_opts
.ase_dsp
== -1)
15206 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15207 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15208 as_warn (_("%s ISA does not support DSP ASE"),
15209 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15211 if (mips_opts
.ase_dspr2
== -1)
15213 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15214 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15216 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15217 as_warn (_("%s ISA does not support DSP R2 ASE"),
15218 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15220 if (mips_opts
.ase_mt
== -1)
15221 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15222 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15223 as_warn (_("%s ISA does not support MT ASE"),
15224 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15226 if (mips_opts
.ase_mcu
== -1)
15227 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15228 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15229 as_warn (_("%s ISA does not support MCU ASE"),
15230 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15232 file_mips_isa
= mips_opts
.isa
;
15233 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15234 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15235 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15236 file_ase_dsp
= mips_opts
.ase_dsp
;
15237 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15238 file_ase_mt
= mips_opts
.ase_mt
;
15239 mips_opts
.gp32
= file_mips_gp32
;
15240 mips_opts
.fp32
= file_mips_fp32
;
15241 mips_opts
.soft_float
= file_mips_soft_float
;
15242 mips_opts
.single_float
= file_mips_single_float
;
15244 if (mips_flag_mdebug
< 0)
15246 #ifdef OBJ_MAYBE_ECOFF
15247 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15248 mips_flag_mdebug
= 1;
15250 #endif /* OBJ_MAYBE_ECOFF */
15251 mips_flag_mdebug
= 0;
15256 mips_init_after_args (void)
15258 /* initialize opcodes */
15259 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15260 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15264 md_pcrel_from (fixS
*fixP
)
15266 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15267 switch (fixP
->fx_r_type
)
15269 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15270 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15271 /* Return the address of the delay slot. */
15274 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15275 case BFD_RELOC_MICROMIPS_JMP
:
15276 case BFD_RELOC_16_PCREL_S2
:
15277 case BFD_RELOC_MIPS_JMP
:
15278 /* Return the address of the delay slot. */
15282 /* We have no relocation type for PC relative MIPS16 instructions. */
15283 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15285 _("PC relative MIPS16 instruction references a different section"));
15290 /* This is called before the symbol table is processed. In order to
15291 work with gcc when using mips-tfile, we must keep all local labels.
15292 However, in other cases, we want to discard them. If we were
15293 called with -g, but we didn't see any debugging information, it may
15294 mean that gcc is smuggling debugging information through to
15295 mips-tfile, in which case we must generate all local labels. */
15298 mips_frob_file_before_adjust (void)
15300 #ifndef NO_ECOFF_DEBUGGING
15301 if (ECOFF_DEBUGGING
15303 && ! ecoff_debugging_seen
)
15304 flag_keep_locals
= 1;
15308 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15309 the corresponding LO16 reloc. This is called before md_apply_fix and
15310 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15311 relocation operators.
15313 For our purposes, a %lo() expression matches a %got() or %hi()
15316 (a) it refers to the same symbol; and
15317 (b) the offset applied in the %lo() expression is no lower than
15318 the offset applied in the %got() or %hi().
15320 (b) allows us to cope with code like:
15323 lh $4,%lo(foo+2)($4)
15325 ...which is legal on RELA targets, and has a well-defined behaviour
15326 if the user knows that adding 2 to "foo" will not induce a carry to
15329 When several %lo()s match a particular %got() or %hi(), we use the
15330 following rules to distinguish them:
15332 (1) %lo()s with smaller offsets are a better match than %lo()s with
15335 (2) %lo()s with no matching %got() or %hi() are better than those
15336 that already have a matching %got() or %hi().
15338 (3) later %lo()s are better than earlier %lo()s.
15340 These rules are applied in order.
15342 (1) means, among other things, that %lo()s with identical offsets are
15343 chosen if they exist.
15345 (2) means that we won't associate several high-part relocations with
15346 the same low-part relocation unless there's no alternative. Having
15347 several high parts for the same low part is a GNU extension; this rule
15348 allows careful users to avoid it.
15350 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15351 with the last high-part relocation being at the front of the list.
15352 It therefore makes sense to choose the last matching low-part
15353 relocation, all other things being equal. It's also easier
15354 to code that way. */
15357 mips_frob_file (void)
15359 struct mips_hi_fixup
*l
;
15360 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15362 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15364 segment_info_type
*seginfo
;
15365 bfd_boolean matched_lo_p
;
15366 fixS
**hi_pos
, **lo_pos
, **pos
;
15368 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15370 /* If a GOT16 relocation turns out to be against a global symbol,
15371 there isn't supposed to be a matching LO. Ignore %gots against
15372 constants; we'll report an error for those later. */
15373 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15374 && !(l
->fixp
->fx_addsy
15375 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15378 /* Check quickly whether the next fixup happens to be a matching %lo. */
15379 if (fixup_has_matching_lo_p (l
->fixp
))
15382 seginfo
= seg_info (l
->seg
);
15384 /* Set HI_POS to the position of this relocation in the chain.
15385 Set LO_POS to the position of the chosen low-part relocation.
15386 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15387 relocation that matches an immediately-preceding high-part
15391 matched_lo_p
= FALSE
;
15392 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15394 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15396 if (*pos
== l
->fixp
)
15399 if ((*pos
)->fx_r_type
== looking_for_rtype
15400 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15401 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15403 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15405 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15408 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15409 && fixup_has_matching_lo_p (*pos
));
15412 /* If we found a match, remove the high-part relocation from its
15413 current position and insert it before the low-part relocation.
15414 Make the offsets match so that fixup_has_matching_lo_p()
15417 We don't warn about unmatched high-part relocations since some
15418 versions of gcc have been known to emit dead "lui ...%hi(...)"
15420 if (lo_pos
!= NULL
)
15422 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15423 if (l
->fixp
->fx_next
!= *lo_pos
)
15425 *hi_pos
= l
->fixp
->fx_next
;
15426 l
->fixp
->fx_next
= *lo_pos
;
15434 mips_force_relocation (fixS
*fixp
)
15436 if (generic_force_reloc (fixp
))
15439 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15440 so that the linker relaxation can update targets. */
15441 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15442 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15443 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15449 /* Read the instruction associated with RELOC from BUF. */
15451 static unsigned int
15452 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15454 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15455 return read_compressed_insn (buf
, 4);
15457 return read_insn (buf
);
15460 /* Write instruction INSN to BUF, given that it has been relocated
15464 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15465 unsigned long insn
)
15467 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15468 write_compressed_insn (buf
, insn
, 4);
15470 write_insn (buf
, insn
);
15473 /* Apply a fixup to the object file. */
15476 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15479 unsigned long insn
;
15480 reloc_howto_type
*howto
;
15482 /* We ignore generic BFD relocations we don't know about. */
15483 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15487 gas_assert (fixP
->fx_size
== 2
15488 || fixP
->fx_size
== 4
15489 || fixP
->fx_r_type
== BFD_RELOC_16
15490 || fixP
->fx_r_type
== BFD_RELOC_64
15491 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15492 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15493 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15495 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15496 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15498 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15500 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15501 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15502 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15503 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15505 /* Don't treat parts of a composite relocation as done. There are two
15508 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15509 should nevertheless be emitted if the first part is.
15511 (2) In normal usage, composite relocations are never assembly-time
15512 constants. The easiest way of dealing with the pathological
15513 exceptions is to generate a relocation against STN_UNDEF and
15514 leave everything up to the linker. */
15515 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15518 switch (fixP
->fx_r_type
)
15520 case BFD_RELOC_MIPS_TLS_GD
:
15521 case BFD_RELOC_MIPS_TLS_LDM
:
15522 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15523 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15524 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15525 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15526 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15527 case BFD_RELOC_MIPS_TLS_TPREL32
:
15528 case BFD_RELOC_MIPS_TLS_TPREL64
:
15529 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15530 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15531 case BFD_RELOC_MICROMIPS_TLS_GD
:
15532 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15533 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15534 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15535 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15536 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15537 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15538 case BFD_RELOC_MIPS16_TLS_GD
:
15539 case BFD_RELOC_MIPS16_TLS_LDM
:
15540 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15541 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15542 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15543 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15544 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15545 if (!fixP
->fx_addsy
)
15547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15548 _("TLS relocation against a constant"));
15551 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15554 case BFD_RELOC_MIPS_JMP
:
15555 case BFD_RELOC_MIPS_SHIFT5
:
15556 case BFD_RELOC_MIPS_SHIFT6
:
15557 case BFD_RELOC_MIPS_GOT_DISP
:
15558 case BFD_RELOC_MIPS_GOT_PAGE
:
15559 case BFD_RELOC_MIPS_GOT_OFST
:
15560 case BFD_RELOC_MIPS_SUB
:
15561 case BFD_RELOC_MIPS_INSERT_A
:
15562 case BFD_RELOC_MIPS_INSERT_B
:
15563 case BFD_RELOC_MIPS_DELETE
:
15564 case BFD_RELOC_MIPS_HIGHEST
:
15565 case BFD_RELOC_MIPS_HIGHER
:
15566 case BFD_RELOC_MIPS_SCN_DISP
:
15567 case BFD_RELOC_MIPS_REL16
:
15568 case BFD_RELOC_MIPS_RELGOT
:
15569 case BFD_RELOC_MIPS_JALR
:
15570 case BFD_RELOC_HI16
:
15571 case BFD_RELOC_HI16_S
:
15572 case BFD_RELOC_LO16
:
15573 case BFD_RELOC_GPREL16
:
15574 case BFD_RELOC_MIPS_LITERAL
:
15575 case BFD_RELOC_MIPS_CALL16
:
15576 case BFD_RELOC_MIPS_GOT16
:
15577 case BFD_RELOC_GPREL32
:
15578 case BFD_RELOC_MIPS_GOT_HI16
:
15579 case BFD_RELOC_MIPS_GOT_LO16
:
15580 case BFD_RELOC_MIPS_CALL_HI16
:
15581 case BFD_RELOC_MIPS_CALL_LO16
:
15582 case BFD_RELOC_MIPS16_GPREL
:
15583 case BFD_RELOC_MIPS16_GOT16
:
15584 case BFD_RELOC_MIPS16_CALL16
:
15585 case BFD_RELOC_MIPS16_HI16
:
15586 case BFD_RELOC_MIPS16_HI16_S
:
15587 case BFD_RELOC_MIPS16_LO16
:
15588 case BFD_RELOC_MIPS16_JMP
:
15589 case BFD_RELOC_MICROMIPS_JMP
:
15590 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15591 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15592 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15593 case BFD_RELOC_MICROMIPS_SUB
:
15594 case BFD_RELOC_MICROMIPS_HIGHEST
:
15595 case BFD_RELOC_MICROMIPS_HIGHER
:
15596 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15597 case BFD_RELOC_MICROMIPS_JALR
:
15598 case BFD_RELOC_MICROMIPS_HI16
:
15599 case BFD_RELOC_MICROMIPS_HI16_S
:
15600 case BFD_RELOC_MICROMIPS_LO16
:
15601 case BFD_RELOC_MICROMIPS_GPREL16
:
15602 case BFD_RELOC_MICROMIPS_LITERAL
:
15603 case BFD_RELOC_MICROMIPS_CALL16
:
15604 case BFD_RELOC_MICROMIPS_GOT16
:
15605 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15606 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15607 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15608 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15613 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15615 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15616 if (mips16_reloc_p (fixP
->fx_r_type
))
15617 insn
|= mips16_immed_extend (value
, 16);
15619 insn
|= (value
& 0xffff);
15620 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15624 _("Unsupported constant in relocation"));
15629 /* This is handled like BFD_RELOC_32, but we output a sign
15630 extended value if we are only 32 bits. */
15633 if (8 <= sizeof (valueT
))
15634 md_number_to_chars (buf
, *valP
, 8);
15639 if ((*valP
& 0x80000000) != 0)
15643 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15644 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15649 case BFD_RELOC_RVA
:
15652 /* If we are deleting this reloc entry, we must fill in the
15653 value now. This can happen if we have a .word which is not
15654 resolved when it appears but is later defined. */
15656 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15659 case BFD_RELOC_16_PCREL_S2
:
15660 if ((*valP
& 0x3) != 0)
15661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15662 _("Branch to misaligned address (%lx)"), (long) *valP
);
15664 /* We need to save the bits in the instruction since fixup_segment()
15665 might be deleting the relocation entry (i.e., a branch within
15666 the current segment). */
15667 if (! fixP
->fx_done
)
15670 /* Update old instruction data. */
15671 insn
= read_insn (buf
);
15673 if (*valP
+ 0x20000 <= 0x3ffff)
15675 insn
|= (*valP
>> 2) & 0xffff;
15676 write_insn (buf
, insn
);
15678 else if (mips_pic
== NO_PIC
15680 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15681 && (fixP
->fx_frag
->fr_address
15682 < text_section
->vma
+ bfd_get_section_size (text_section
))
15683 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15684 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15685 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15687 /* The branch offset is too large. If this is an
15688 unconditional branch, and we are not generating PIC code,
15689 we can convert it to an absolute jump instruction. */
15690 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15691 insn
= 0x0c000000; /* jal */
15693 insn
= 0x08000000; /* j */
15694 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15696 fixP
->fx_addsy
= section_symbol (text_section
);
15697 *valP
+= md_pcrel_from (fixP
);
15698 write_insn (buf
, insn
);
15702 /* If we got here, we have branch-relaxation disabled,
15703 and there's nothing we can do to fix this instruction
15704 without turning it into a longer sequence. */
15705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15706 _("Branch out of range"));
15710 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15711 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15712 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15713 /* We adjust the offset back to even. */
15714 if ((*valP
& 0x1) != 0)
15717 if (! fixP
->fx_done
)
15720 /* Should never visit here, because we keep the relocation. */
15724 case BFD_RELOC_VTABLE_INHERIT
:
15727 && !S_IS_DEFINED (fixP
->fx_addsy
)
15728 && !S_IS_WEAK (fixP
->fx_addsy
))
15729 S_SET_WEAK (fixP
->fx_addsy
);
15732 case BFD_RELOC_VTABLE_ENTRY
:
15740 /* Remember value for tc_gen_reloc. */
15741 fixP
->fx_addnumber
= *valP
;
15751 name
= input_line_pointer
;
15752 c
= get_symbol_end ();
15753 p
= (symbolS
*) symbol_find_or_make (name
);
15754 *input_line_pointer
= c
;
15758 /* Align the current frag to a given power of two. If a particular
15759 fill byte should be used, FILL points to an integer that contains
15760 that byte, otherwise FILL is null.
15762 This function used to have the comment:
15764 The MIPS assembler also automatically adjusts any preceding label.
15766 The implementation therefore applied the adjustment to a maximum of
15767 one label. However, other label adjustments are applied to batches
15768 of labels, and adjusting just one caused problems when new labels
15769 were added for the sake of debugging or unwind information.
15770 We therefore adjust all preceding labels (given as LABELS) instead. */
15773 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15775 mips_emit_delays ();
15776 mips_record_compressed_mode ();
15777 if (fill
== NULL
&& subseg_text_p (now_seg
))
15778 frag_align_code (to
, 0);
15780 frag_align (to
, fill
? *fill
: 0, 0);
15781 record_alignment (now_seg
, to
);
15782 mips_move_labels (labels
, FALSE
);
15785 /* Align to a given power of two. .align 0 turns off the automatic
15786 alignment used by the data creating pseudo-ops. */
15789 s_align (int x ATTRIBUTE_UNUSED
)
15791 int temp
, fill_value
, *fill_ptr
;
15792 long max_alignment
= 28;
15794 /* o Note that the assembler pulls down any immediately preceding label
15795 to the aligned address.
15796 o It's not documented but auto alignment is reinstated by
15797 a .align pseudo instruction.
15798 o Note also that after auto alignment is turned off the mips assembler
15799 issues an error on attempt to assemble an improperly aligned data item.
15802 temp
= get_absolute_expression ();
15803 if (temp
> max_alignment
)
15804 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15807 as_warn (_("Alignment negative: 0 assumed."));
15810 if (*input_line_pointer
== ',')
15812 ++input_line_pointer
;
15813 fill_value
= get_absolute_expression ();
15814 fill_ptr
= &fill_value
;
15820 segment_info_type
*si
= seg_info (now_seg
);
15821 struct insn_label_list
*l
= si
->label_list
;
15822 /* Auto alignment should be switched on by next section change. */
15824 mips_align (temp
, fill_ptr
, l
);
15831 demand_empty_rest_of_line ();
15835 s_change_sec (int sec
)
15840 /* The ELF backend needs to know that we are changing sections, so
15841 that .previous works correctly. We could do something like check
15842 for an obj_section_change_hook macro, but that might be confusing
15843 as it would not be appropriate to use it in the section changing
15844 functions in read.c, since obj-elf.c intercepts those. FIXME:
15845 This should be cleaner, somehow. */
15847 obj_elf_section_change_hook ();
15850 mips_emit_delays ();
15861 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15862 demand_empty_rest_of_line ();
15866 seg
= subseg_new (RDATA_SECTION_NAME
,
15867 (subsegT
) get_absolute_expression ());
15870 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15871 | SEC_READONLY
| SEC_RELOC
15873 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15874 record_alignment (seg
, 4);
15876 demand_empty_rest_of_line ();
15880 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15883 bfd_set_section_flags (stdoutput
, seg
,
15884 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15885 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15886 record_alignment (seg
, 4);
15888 demand_empty_rest_of_line ();
15892 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15895 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15896 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15897 record_alignment (seg
, 4);
15899 demand_empty_rest_of_line ();
15907 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15910 char *section_name
;
15915 int section_entry_size
;
15916 int section_alignment
;
15921 section_name
= input_line_pointer
;
15922 c
= get_symbol_end ();
15924 next_c
= *(input_line_pointer
+ 1);
15926 /* Do we have .section Name<,"flags">? */
15927 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15929 /* just after name is now '\0'. */
15930 *input_line_pointer
= c
;
15931 input_line_pointer
= section_name
;
15932 obj_elf_section (ignore
);
15935 input_line_pointer
++;
15937 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15939 section_type
= get_absolute_expression ();
15942 if (*input_line_pointer
++ == ',')
15943 section_flag
= get_absolute_expression ();
15946 if (*input_line_pointer
++ == ',')
15947 section_entry_size
= get_absolute_expression ();
15949 section_entry_size
= 0;
15950 if (*input_line_pointer
++ == ',')
15951 section_alignment
= get_absolute_expression ();
15953 section_alignment
= 0;
15954 /* FIXME: really ignore? */
15955 (void) section_alignment
;
15957 section_name
= xstrdup (section_name
);
15959 /* When using the generic form of .section (as implemented by obj-elf.c),
15960 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15961 traditionally had to fall back on the more common @progbits instead.
15963 There's nothing really harmful in this, since bfd will correct
15964 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15965 means that, for backwards compatibility, the special_section entries
15966 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15968 Even so, we shouldn't force users of the MIPS .section syntax to
15969 incorrectly label the sections as SHT_PROGBITS. The best compromise
15970 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15971 generic type-checking code. */
15972 if (section_type
== SHT_MIPS_DWARF
)
15973 section_type
= SHT_PROGBITS
;
15975 obj_elf_change_section (section_name
, section_type
, section_flag
,
15976 section_entry_size
, 0, 0, 0);
15978 if (now_seg
->name
!= section_name
)
15979 free (section_name
);
15980 #endif /* OBJ_ELF */
15984 mips_enable_auto_align (void)
15990 s_cons (int log_size
)
15992 segment_info_type
*si
= seg_info (now_seg
);
15993 struct insn_label_list
*l
= si
->label_list
;
15995 mips_emit_delays ();
15996 if (log_size
> 0 && auto_align
)
15997 mips_align (log_size
, 0, l
);
15998 cons (1 << log_size
);
15999 mips_clear_insn_labels ();
16003 s_float_cons (int type
)
16005 segment_info_type
*si
= seg_info (now_seg
);
16006 struct insn_label_list
*l
= si
->label_list
;
16008 mips_emit_delays ();
16013 mips_align (3, 0, l
);
16015 mips_align (2, 0, l
);
16019 mips_clear_insn_labels ();
16022 /* Handle .globl. We need to override it because on Irix 5 you are
16025 where foo is an undefined symbol, to mean that foo should be
16026 considered to be the address of a function. */
16029 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16038 name
= input_line_pointer
;
16039 c
= get_symbol_end ();
16040 symbolP
= symbol_find_or_make (name
);
16041 S_SET_EXTERNAL (symbolP
);
16043 *input_line_pointer
= c
;
16044 SKIP_WHITESPACE ();
16046 /* On Irix 5, every global symbol that is not explicitly labelled as
16047 being a function is apparently labelled as being an object. */
16050 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16051 && (*input_line_pointer
!= ','))
16056 secname
= input_line_pointer
;
16057 c
= get_symbol_end ();
16058 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16060 as_bad (_("%s: no such section"), secname
);
16061 *input_line_pointer
= c
;
16063 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16064 flag
= BSF_FUNCTION
;
16067 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16069 c
= *input_line_pointer
;
16072 input_line_pointer
++;
16073 SKIP_WHITESPACE ();
16074 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16080 demand_empty_rest_of_line ();
16084 s_option (int x ATTRIBUTE_UNUSED
)
16089 opt
= input_line_pointer
;
16090 c
= get_symbol_end ();
16094 /* FIXME: What does this mean? */
16096 else if (strncmp (opt
, "pic", 3) == 0)
16100 i
= atoi (opt
+ 3);
16105 mips_pic
= SVR4_PIC
;
16106 mips_abicalls
= TRUE
;
16109 as_bad (_(".option pic%d not supported"), i
);
16111 if (mips_pic
== SVR4_PIC
)
16113 if (g_switch_seen
&& g_switch_value
!= 0)
16114 as_warn (_("-G may not be used with SVR4 PIC code"));
16115 g_switch_value
= 0;
16116 bfd_set_gp_size (stdoutput
, 0);
16120 as_warn (_("Unrecognized option \"%s\""), opt
);
16122 *input_line_pointer
= c
;
16123 demand_empty_rest_of_line ();
16126 /* This structure is used to hold a stack of .set values. */
16128 struct mips_option_stack
16130 struct mips_option_stack
*next
;
16131 struct mips_set_options options
;
16134 static struct mips_option_stack
*mips_opts_stack
;
16136 /* Handle the .set pseudo-op. */
16139 s_mipsset (int x ATTRIBUTE_UNUSED
)
16141 char *name
= input_line_pointer
, ch
;
16143 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16144 ++input_line_pointer
;
16145 ch
= *input_line_pointer
;
16146 *input_line_pointer
= '\0';
16148 if (strcmp (name
, "reorder") == 0)
16150 if (mips_opts
.noreorder
)
16153 else if (strcmp (name
, "noreorder") == 0)
16155 if (!mips_opts
.noreorder
)
16156 start_noreorder ();
16158 else if (strncmp (name
, "at=", 3) == 0)
16160 char *s
= name
+ 3;
16162 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16163 as_bad (_("Unrecognized register name `%s'"), s
);
16165 else if (strcmp (name
, "at") == 0)
16167 mips_opts
.at
= ATREG
;
16169 else if (strcmp (name
, "noat") == 0)
16171 mips_opts
.at
= ZERO
;
16173 else if (strcmp (name
, "macro") == 0)
16175 mips_opts
.warn_about_macros
= 0;
16177 else if (strcmp (name
, "nomacro") == 0)
16179 if (mips_opts
.noreorder
== 0)
16180 as_bad (_("`noreorder' must be set before `nomacro'"));
16181 mips_opts
.warn_about_macros
= 1;
16183 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16185 mips_opts
.nomove
= 0;
16187 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16189 mips_opts
.nomove
= 1;
16191 else if (strcmp (name
, "bopt") == 0)
16193 mips_opts
.nobopt
= 0;
16195 else if (strcmp (name
, "nobopt") == 0)
16197 mips_opts
.nobopt
= 1;
16199 else if (strcmp (name
, "gp=default") == 0)
16200 mips_opts
.gp32
= file_mips_gp32
;
16201 else if (strcmp (name
, "gp=32") == 0)
16202 mips_opts
.gp32
= 1;
16203 else if (strcmp (name
, "gp=64") == 0)
16205 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16206 as_warn (_("%s isa does not support 64-bit registers"),
16207 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16208 mips_opts
.gp32
= 0;
16210 else if (strcmp (name
, "fp=default") == 0)
16211 mips_opts
.fp32
= file_mips_fp32
;
16212 else if (strcmp (name
, "fp=32") == 0)
16213 mips_opts
.fp32
= 1;
16214 else if (strcmp (name
, "fp=64") == 0)
16216 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16217 as_warn (_("%s isa does not support 64-bit floating point registers"),
16218 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16219 mips_opts
.fp32
= 0;
16221 else if (strcmp (name
, "softfloat") == 0)
16222 mips_opts
.soft_float
= 1;
16223 else if (strcmp (name
, "hardfloat") == 0)
16224 mips_opts
.soft_float
= 0;
16225 else if (strcmp (name
, "singlefloat") == 0)
16226 mips_opts
.single_float
= 1;
16227 else if (strcmp (name
, "doublefloat") == 0)
16228 mips_opts
.single_float
= 0;
16229 else if (strcmp (name
, "mips16") == 0
16230 || strcmp (name
, "MIPS-16") == 0)
16232 if (mips_opts
.micromips
== 1)
16233 as_fatal (_("`mips16' cannot be used with `micromips'"));
16234 mips_opts
.mips16
= 1;
16236 else if (strcmp (name
, "nomips16") == 0
16237 || strcmp (name
, "noMIPS-16") == 0)
16238 mips_opts
.mips16
= 0;
16239 else if (strcmp (name
, "micromips") == 0)
16241 if (mips_opts
.mips16
== 1)
16242 as_fatal (_("`micromips' cannot be used with `mips16'"));
16243 mips_opts
.micromips
= 1;
16245 else if (strcmp (name
, "nomicromips") == 0)
16246 mips_opts
.micromips
= 0;
16247 else if (strcmp (name
, "smartmips") == 0)
16249 if (!ISA_SUPPORTS_SMARTMIPS
)
16250 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16251 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16252 mips_opts
.ase_smartmips
= 1;
16254 else if (strcmp (name
, "nosmartmips") == 0)
16255 mips_opts
.ase_smartmips
= 0;
16256 else if (strcmp (name
, "mips3d") == 0)
16257 mips_opts
.ase_mips3d
= 1;
16258 else if (strcmp (name
, "nomips3d") == 0)
16259 mips_opts
.ase_mips3d
= 0;
16260 else if (strcmp (name
, "mdmx") == 0)
16261 mips_opts
.ase_mdmx
= 1;
16262 else if (strcmp (name
, "nomdmx") == 0)
16263 mips_opts
.ase_mdmx
= 0;
16264 else if (strcmp (name
, "dsp") == 0)
16266 if (!ISA_SUPPORTS_DSP_ASE
)
16267 as_warn (_("%s ISA does not support DSP ASE"),
16268 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16269 mips_opts
.ase_dsp
= 1;
16270 mips_opts
.ase_dspr2
= 0;
16272 else if (strcmp (name
, "nodsp") == 0)
16274 mips_opts
.ase_dsp
= 0;
16275 mips_opts
.ase_dspr2
= 0;
16277 else if (strcmp (name
, "dspr2") == 0)
16279 if (!ISA_SUPPORTS_DSPR2_ASE
)
16280 as_warn (_("%s ISA does not support DSP R2 ASE"),
16281 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16282 mips_opts
.ase_dspr2
= 1;
16283 mips_opts
.ase_dsp
= 1;
16285 else if (strcmp (name
, "nodspr2") == 0)
16287 mips_opts
.ase_dspr2
= 0;
16288 mips_opts
.ase_dsp
= 0;
16290 else if (strcmp (name
, "mt") == 0)
16292 if (!ISA_SUPPORTS_MT_ASE
)
16293 as_warn (_("%s ISA does not support MT ASE"),
16294 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16295 mips_opts
.ase_mt
= 1;
16297 else if (strcmp (name
, "nomt") == 0)
16298 mips_opts
.ase_mt
= 0;
16299 else if (strcmp (name
, "mcu") == 0)
16300 mips_opts
.ase_mcu
= 1;
16301 else if (strcmp (name
, "nomcu") == 0)
16302 mips_opts
.ase_mcu
= 0;
16303 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16307 /* Permit the user to change the ISA and architecture on the fly.
16308 Needless to say, misuse can cause serious problems. */
16309 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16312 mips_opts
.isa
= file_mips_isa
;
16313 mips_opts
.arch
= file_mips_arch
;
16315 else if (strncmp (name
, "arch=", 5) == 0)
16317 const struct mips_cpu_info
*p
;
16319 p
= mips_parse_cpu("internal use", name
+ 5);
16321 as_bad (_("unknown architecture %s"), name
+ 5);
16324 mips_opts
.arch
= p
->cpu
;
16325 mips_opts
.isa
= p
->isa
;
16328 else if (strncmp (name
, "mips", 4) == 0)
16330 const struct mips_cpu_info
*p
;
16332 p
= mips_parse_cpu("internal use", name
);
16334 as_bad (_("unknown ISA level %s"), name
+ 4);
16337 mips_opts
.arch
= p
->cpu
;
16338 mips_opts
.isa
= p
->isa
;
16342 as_bad (_("unknown ISA or architecture %s"), name
);
16344 switch (mips_opts
.isa
)
16352 mips_opts
.gp32
= 1;
16353 mips_opts
.fp32
= 1;
16360 mips_opts
.gp32
= 0;
16361 mips_opts
.fp32
= 0;
16364 as_bad (_("unknown ISA level %s"), name
+ 4);
16369 mips_opts
.gp32
= file_mips_gp32
;
16370 mips_opts
.fp32
= file_mips_fp32
;
16373 else if (strcmp (name
, "autoextend") == 0)
16374 mips_opts
.noautoextend
= 0;
16375 else if (strcmp (name
, "noautoextend") == 0)
16376 mips_opts
.noautoextend
= 1;
16377 else if (strcmp (name
, "push") == 0)
16379 struct mips_option_stack
*s
;
16381 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16382 s
->next
= mips_opts_stack
;
16383 s
->options
= mips_opts
;
16384 mips_opts_stack
= s
;
16386 else if (strcmp (name
, "pop") == 0)
16388 struct mips_option_stack
*s
;
16390 s
= mips_opts_stack
;
16392 as_bad (_(".set pop with no .set push"));
16395 /* If we're changing the reorder mode we need to handle
16396 delay slots correctly. */
16397 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16398 start_noreorder ();
16399 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16402 mips_opts
= s
->options
;
16403 mips_opts_stack
= s
->next
;
16407 else if (strcmp (name
, "sym32") == 0)
16408 mips_opts
.sym32
= TRUE
;
16409 else if (strcmp (name
, "nosym32") == 0)
16410 mips_opts
.sym32
= FALSE
;
16411 else if (strchr (name
, ','))
16413 /* Generic ".set" directive; use the generic handler. */
16414 *input_line_pointer
= ch
;
16415 input_line_pointer
= name
;
16421 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16423 *input_line_pointer
= ch
;
16424 demand_empty_rest_of_line ();
16427 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16428 .option pic2. It means to generate SVR4 PIC calls. */
16431 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16433 mips_pic
= SVR4_PIC
;
16434 mips_abicalls
= TRUE
;
16436 if (g_switch_seen
&& g_switch_value
!= 0)
16437 as_warn (_("-G may not be used with SVR4 PIC code"));
16438 g_switch_value
= 0;
16440 bfd_set_gp_size (stdoutput
, 0);
16441 demand_empty_rest_of_line ();
16444 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16445 PIC code. It sets the $gp register for the function based on the
16446 function address, which is in the register named in the argument.
16447 This uses a relocation against _gp_disp, which is handled specially
16448 by the linker. The result is:
16449 lui $gp,%hi(_gp_disp)
16450 addiu $gp,$gp,%lo(_gp_disp)
16451 addu $gp,$gp,.cpload argument
16452 The .cpload argument is normally $25 == $t9.
16454 The -mno-shared option changes this to:
16455 lui $gp,%hi(__gnu_local_gp)
16456 addiu $gp,$gp,%lo(__gnu_local_gp)
16457 and the argument is ignored. This saves an instruction, but the
16458 resulting code is not position independent; it uses an absolute
16459 address for __gnu_local_gp. Thus code assembled with -mno-shared
16460 can go into an ordinary executable, but not into a shared library. */
16463 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16469 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16470 .cpload is ignored. */
16471 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16477 if (mips_opts
.mips16
)
16479 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16480 ignore_rest_of_line ();
16484 /* .cpload should be in a .set noreorder section. */
16485 if (mips_opts
.noreorder
== 0)
16486 as_warn (_(".cpload not in noreorder section"));
16488 reg
= tc_get_register (0);
16490 /* If we need to produce a 64-bit address, we are better off using
16491 the default instruction sequence. */
16492 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16494 ex
.X_op
= O_symbol
;
16495 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16497 ex
.X_op_symbol
= NULL
;
16498 ex
.X_add_number
= 0;
16500 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16501 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16504 macro_build_lui (&ex
, mips_gp_register
);
16505 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16506 mips_gp_register
, BFD_RELOC_LO16
);
16508 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16509 mips_gp_register
, reg
);
16512 demand_empty_rest_of_line ();
16515 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16516 .cpsetup $reg1, offset|$reg2, label
16518 If offset is given, this results in:
16519 sd $gp, offset($sp)
16520 lui $gp, %hi(%neg(%gp_rel(label)))
16521 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16522 daddu $gp, $gp, $reg1
16524 If $reg2 is given, this results in:
16525 daddu $reg2, $gp, $0
16526 lui $gp, %hi(%neg(%gp_rel(label)))
16527 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16528 daddu $gp, $gp, $reg1
16529 $reg1 is normally $25 == $t9.
16531 The -mno-shared option replaces the last three instructions with
16533 addiu $gp,$gp,%lo(_gp) */
16536 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16538 expressionS ex_off
;
16539 expressionS ex_sym
;
16542 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16543 We also need NewABI support. */
16544 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16550 if (mips_opts
.mips16
)
16552 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16553 ignore_rest_of_line ();
16557 reg1
= tc_get_register (0);
16558 SKIP_WHITESPACE ();
16559 if (*input_line_pointer
!= ',')
16561 as_bad (_("missing argument separator ',' for .cpsetup"));
16565 ++input_line_pointer
;
16566 SKIP_WHITESPACE ();
16567 if (*input_line_pointer
== '$')
16569 mips_cpreturn_register
= tc_get_register (0);
16570 mips_cpreturn_offset
= -1;
16574 mips_cpreturn_offset
= get_absolute_expression ();
16575 mips_cpreturn_register
= -1;
16577 SKIP_WHITESPACE ();
16578 if (*input_line_pointer
!= ',')
16580 as_bad (_("missing argument separator ',' for .cpsetup"));
16584 ++input_line_pointer
;
16585 SKIP_WHITESPACE ();
16586 expression (&ex_sym
);
16589 if (mips_cpreturn_register
== -1)
16591 ex_off
.X_op
= O_constant
;
16592 ex_off
.X_add_symbol
= NULL
;
16593 ex_off
.X_op_symbol
= NULL
;
16594 ex_off
.X_add_number
= mips_cpreturn_offset
;
16596 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16597 BFD_RELOC_LO16
, SP
);
16600 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16601 mips_gp_register
, 0);
16603 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16605 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16606 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16609 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16610 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16611 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16613 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16614 mips_gp_register
, reg1
);
16620 ex
.X_op
= O_symbol
;
16621 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16622 ex
.X_op_symbol
= NULL
;
16623 ex
.X_add_number
= 0;
16625 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16626 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16628 macro_build_lui (&ex
, mips_gp_register
);
16629 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16630 mips_gp_register
, BFD_RELOC_LO16
);
16635 demand_empty_rest_of_line ();
16639 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16641 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16642 .cplocal is ignored. */
16643 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16649 if (mips_opts
.mips16
)
16651 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16652 ignore_rest_of_line ();
16656 mips_gp_register
= tc_get_register (0);
16657 demand_empty_rest_of_line ();
16660 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16661 offset from $sp. The offset is remembered, and after making a PIC
16662 call $gp is restored from that location. */
16665 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16669 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16670 .cprestore is ignored. */
16671 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16677 if (mips_opts
.mips16
)
16679 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16680 ignore_rest_of_line ();
16684 mips_cprestore_offset
= get_absolute_expression ();
16685 mips_cprestore_valid
= 1;
16687 ex
.X_op
= O_constant
;
16688 ex
.X_add_symbol
= NULL
;
16689 ex
.X_op_symbol
= NULL
;
16690 ex
.X_add_number
= mips_cprestore_offset
;
16693 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16694 SP
, HAVE_64BIT_ADDRESSES
);
16697 demand_empty_rest_of_line ();
16700 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16701 was given in the preceding .cpsetup, it results in:
16702 ld $gp, offset($sp)
16704 If a register $reg2 was given there, it results in:
16705 daddu $gp, $reg2, $0 */
16708 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16712 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16713 We also need NewABI support. */
16714 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16720 if (mips_opts
.mips16
)
16722 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16723 ignore_rest_of_line ();
16728 if (mips_cpreturn_register
== -1)
16730 ex
.X_op
= O_constant
;
16731 ex
.X_add_symbol
= NULL
;
16732 ex
.X_op_symbol
= NULL
;
16733 ex
.X_add_number
= mips_cpreturn_offset
;
16735 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16738 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16739 mips_cpreturn_register
, 0);
16742 demand_empty_rest_of_line ();
16745 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16746 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16747 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16748 debug information or MIPS16 TLS. */
16751 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16752 bfd_reloc_code_real_type rtype
)
16759 if (ex
.X_op
!= O_symbol
)
16761 as_bad (_("Unsupported use of %s"), dirstr
);
16762 ignore_rest_of_line ();
16765 p
= frag_more (bytes
);
16766 md_number_to_chars (p
, 0, bytes
);
16767 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16768 demand_empty_rest_of_line ();
16769 mips_clear_insn_labels ();
16772 /* Handle .dtprelword. */
16775 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16777 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16780 /* Handle .dtpreldword. */
16783 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16785 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16788 /* Handle .tprelword. */
16791 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16793 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16796 /* Handle .tpreldword. */
16799 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16801 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16804 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16805 code. It sets the offset to use in gp_rel relocations. */
16808 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16810 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16811 We also need NewABI support. */
16812 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16818 mips_gprel_offset
= get_absolute_expression ();
16820 demand_empty_rest_of_line ();
16823 /* Handle the .gpword pseudo-op. This is used when generating PIC
16824 code. It generates a 32 bit GP relative reloc. */
16827 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16829 segment_info_type
*si
;
16830 struct insn_label_list
*l
;
16834 /* When not generating PIC code, this is treated as .word. */
16835 if (mips_pic
!= SVR4_PIC
)
16841 si
= seg_info (now_seg
);
16842 l
= si
->label_list
;
16843 mips_emit_delays ();
16845 mips_align (2, 0, l
);
16848 mips_clear_insn_labels ();
16850 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16852 as_bad (_("Unsupported use of .gpword"));
16853 ignore_rest_of_line ();
16857 md_number_to_chars (p
, 0, 4);
16858 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16859 BFD_RELOC_GPREL32
);
16861 demand_empty_rest_of_line ();
16865 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16867 segment_info_type
*si
;
16868 struct insn_label_list
*l
;
16872 /* When not generating PIC code, this is treated as .dword. */
16873 if (mips_pic
!= SVR4_PIC
)
16879 si
= seg_info (now_seg
);
16880 l
= si
->label_list
;
16881 mips_emit_delays ();
16883 mips_align (3, 0, l
);
16886 mips_clear_insn_labels ();
16888 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16890 as_bad (_("Unsupported use of .gpdword"));
16891 ignore_rest_of_line ();
16895 md_number_to_chars (p
, 0, 8);
16896 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16897 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16899 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16900 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16901 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16903 demand_empty_rest_of_line ();
16906 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16907 tables in SVR4 PIC code. */
16910 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16914 /* This is ignored when not generating SVR4 PIC code. */
16915 if (mips_pic
!= SVR4_PIC
)
16921 /* Add $gp to the register named as an argument. */
16923 reg
= tc_get_register (0);
16924 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16927 demand_empty_rest_of_line ();
16930 /* Handle the .insn pseudo-op. This marks instruction labels in
16931 mips16/micromips mode. This permits the linker to handle them specially,
16932 such as generating jalx instructions when needed. We also make
16933 them odd for the duration of the assembly, in order to generate the
16934 right sort of code. We will make them even in the adjust_symtab
16935 routine, while leaving them marked. This is convenient for the
16936 debugger and the disassembler. The linker knows to make them odd
16940 s_insn (int ignore ATTRIBUTE_UNUSED
)
16942 mips_mark_labels ();
16944 demand_empty_rest_of_line ();
16947 /* Handle a .stabn directive. We need these in order to mark a label
16948 as being a mips16 text label correctly. Sometimes the compiler
16949 will emit a label, followed by a .stabn, and then switch sections.
16950 If the label and .stabn are in mips16 mode, then the label is
16951 really a mips16 text label. */
16954 s_mips_stab (int type
)
16957 mips_mark_labels ();
16962 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16965 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16972 name
= input_line_pointer
;
16973 c
= get_symbol_end ();
16974 symbolP
= symbol_find_or_make (name
);
16975 S_SET_WEAK (symbolP
);
16976 *input_line_pointer
= c
;
16978 SKIP_WHITESPACE ();
16980 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16982 if (S_IS_DEFINED (symbolP
))
16984 as_bad (_("ignoring attempt to redefine symbol %s"),
16985 S_GET_NAME (symbolP
));
16986 ignore_rest_of_line ();
16990 if (*input_line_pointer
== ',')
16992 ++input_line_pointer
;
16993 SKIP_WHITESPACE ();
16997 if (exp
.X_op
!= O_symbol
)
16999 as_bad (_("bad .weakext directive"));
17000 ignore_rest_of_line ();
17003 symbol_set_value_expression (symbolP
, &exp
);
17006 demand_empty_rest_of_line ();
17009 /* Parse a register string into a number. Called from the ECOFF code
17010 to parse .frame. The argument is non-zero if this is the frame
17011 register, so that we can record it in mips_frame_reg. */
17014 tc_get_register (int frame
)
17018 SKIP_WHITESPACE ();
17019 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17023 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17024 mips_frame_reg_valid
= 1;
17025 mips_cprestore_valid
= 0;
17031 md_section_align (asection
*seg
, valueT addr
)
17033 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17037 /* We don't need to align ELF sections to the full alignment.
17038 However, Irix 5 may prefer that we align them at least to a 16
17039 byte boundary. We don't bother to align the sections if we
17040 are targeted for an embedded system. */
17041 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17047 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17050 /* Utility routine, called from above as well. If called while the
17051 input file is still being read, it's only an approximation. (For
17052 example, a symbol may later become defined which appeared to be
17053 undefined earlier.) */
17056 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17061 if (g_switch_value
> 0)
17063 const char *symname
;
17066 /* Find out whether this symbol can be referenced off the $gp
17067 register. It can be if it is smaller than the -G size or if
17068 it is in the .sdata or .sbss section. Certain symbols can
17069 not be referenced off the $gp, although it appears as though
17071 symname
= S_GET_NAME (sym
);
17072 if (symname
!= (const char *) NULL
17073 && (strcmp (symname
, "eprol") == 0
17074 || strcmp (symname
, "etext") == 0
17075 || strcmp (symname
, "_gp") == 0
17076 || strcmp (symname
, "edata") == 0
17077 || strcmp (symname
, "_fbss") == 0
17078 || strcmp (symname
, "_fdata") == 0
17079 || strcmp (symname
, "_ftext") == 0
17080 || strcmp (symname
, "end") == 0
17081 || strcmp (symname
, "_gp_disp") == 0))
17083 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17085 #ifndef NO_ECOFF_DEBUGGING
17086 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17087 && (symbol_get_obj (sym
)->ecoff_extern_size
17088 <= g_switch_value
))
17090 /* We must defer this decision until after the whole
17091 file has been read, since there might be a .extern
17092 after the first use of this symbol. */
17093 || (before_relaxing
17094 #ifndef NO_ECOFF_DEBUGGING
17095 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17097 && S_GET_VALUE (sym
) == 0)
17098 || (S_GET_VALUE (sym
) != 0
17099 && S_GET_VALUE (sym
) <= g_switch_value
)))
17103 const char *segname
;
17105 segname
= segment_name (S_GET_SEGMENT (sym
));
17106 gas_assert (strcmp (segname
, ".lit8") != 0
17107 && strcmp (segname
, ".lit4") != 0);
17108 change
= (strcmp (segname
, ".sdata") != 0
17109 && strcmp (segname
, ".sbss") != 0
17110 && strncmp (segname
, ".sdata.", 7) != 0
17111 && strncmp (segname
, ".sbss.", 6) != 0
17112 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17113 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17118 /* We are not optimizing for the $gp register. */
17123 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17126 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17130 /* Handle the case of a symbol equated to another symbol. */
17131 while (symbol_equated_reloc_p (sym
))
17135 /* It's possible to get a loop here in a badly written program. */
17136 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17142 if (symbol_section_p (sym
))
17145 symsec
= S_GET_SEGMENT (sym
);
17147 /* This must duplicate the test in adjust_reloc_syms. */
17148 return (!bfd_is_und_section (symsec
)
17149 && !bfd_is_abs_section (symsec
)
17150 && !bfd_is_com_section (symsec
)
17151 && !s_is_linkonce (sym
, segtype
)
17153 /* A global or weak symbol is treated as external. */
17154 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17160 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17161 extended opcode. SEC is the section the frag is in. */
17164 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17167 const struct mips16_immed_operand
*op
;
17169 int mintiny
, maxtiny
;
17173 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17175 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17178 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17179 op
= mips16_immed_operands
;
17180 while (op
->type
!= type
)
17183 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17188 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17191 maxtiny
= 1 << op
->nbits
;
17196 maxtiny
= (1 << op
->nbits
) - 1;
17201 mintiny
= - (1 << (op
->nbits
- 1));
17202 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17205 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17206 val
= S_GET_VALUE (fragp
->fr_symbol
);
17207 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17213 /* We won't have the section when we are called from
17214 mips_relax_frag. However, we will always have been called
17215 from md_estimate_size_before_relax first. If this is a
17216 branch to a different section, we mark it as such. If SEC is
17217 NULL, and the frag is not marked, then it must be a branch to
17218 the same section. */
17221 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17226 /* Must have been called from md_estimate_size_before_relax. */
17229 fragp
->fr_subtype
=
17230 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17232 /* FIXME: We should support this, and let the linker
17233 catch branches and loads that are out of range. */
17234 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17235 _("unsupported PC relative reference to different section"));
17239 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17240 /* Assume non-extended on the first relaxation pass.
17241 The address we have calculated will be bogus if this is
17242 a forward branch to another frag, as the forward frag
17243 will have fr_address == 0. */
17247 /* In this case, we know for sure that the symbol fragment is in
17248 the same section. If the relax_marker of the symbol fragment
17249 differs from the relax_marker of this fragment, we have not
17250 yet adjusted the symbol fragment fr_address. We want to add
17251 in STRETCH in order to get a better estimate of the address.
17252 This particularly matters because of the shift bits. */
17254 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17258 /* Adjust stretch for any alignment frag. Note that if have
17259 been expanding the earlier code, the symbol may be
17260 defined in what appears to be an earlier frag. FIXME:
17261 This doesn't handle the fr_subtype field, which specifies
17262 a maximum number of bytes to skip when doing an
17264 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17266 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17269 stretch
= - ((- stretch
)
17270 & ~ ((1 << (int) f
->fr_offset
) - 1));
17272 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17281 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17283 /* The base address rules are complicated. The base address of
17284 a branch is the following instruction. The base address of a
17285 PC relative load or add is the instruction itself, but if it
17286 is in a delay slot (in which case it can not be extended) use
17287 the address of the instruction whose delay slot it is in. */
17288 if (type
== 'p' || type
== 'q')
17292 /* If we are currently assuming that this frag should be
17293 extended, then, the current address is two bytes
17295 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17298 /* Ignore the low bit in the target, since it will be set
17299 for a text label. */
17300 if ((val
& 1) != 0)
17303 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17305 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17308 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17310 /* Branch offsets have an implicit 0 in the lowest bit. */
17311 if (type
== 'p' || type
== 'q')
17314 /* If any of the shifted bits are set, we must use an extended
17315 opcode. If the address depends on the size of this
17316 instruction, this can lead to a loop, so we arrange to always
17317 use an extended opcode. We only check this when we are in
17318 the main relaxation loop, when SEC is NULL. */
17319 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17321 fragp
->fr_subtype
=
17322 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17326 /* If we are about to mark a frag as extended because the value
17327 is precisely maxtiny + 1, then there is a chance of an
17328 infinite loop as in the following code:
17333 In this case when the la is extended, foo is 0x3fc bytes
17334 away, so the la can be shrunk, but then foo is 0x400 away, so
17335 the la must be extended. To avoid this loop, we mark the
17336 frag as extended if it was small, and is about to become
17337 extended with a value of maxtiny + 1. */
17338 if (val
== ((maxtiny
+ 1) << op
->shift
)
17339 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17342 fragp
->fr_subtype
=
17343 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17347 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17348 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17350 if ((val
& ((1 << op
->shift
) - 1)) != 0
17351 || val
< (mintiny
<< op
->shift
)
17352 || val
> (maxtiny
<< op
->shift
))
17358 /* Compute the length of a branch sequence, and adjust the
17359 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17360 worst-case length is computed, with UPDATE being used to indicate
17361 whether an unconditional (-1), branch-likely (+1) or regular (0)
17362 branch is to be computed. */
17364 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17366 bfd_boolean toofar
;
17370 && S_IS_DEFINED (fragp
->fr_symbol
)
17371 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17376 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17378 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17382 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17385 /* If the symbol is not defined or it's in a different segment,
17386 assume the user knows what's going on and emit a short
17392 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17394 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17395 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17396 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17397 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17403 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17406 if (mips_pic
!= NO_PIC
)
17408 /* Additional space for PIC loading of target address. */
17410 if (mips_opts
.isa
== ISA_MIPS1
)
17411 /* Additional space for $at-stabilizing nop. */
17415 /* If branch is conditional. */
17416 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17423 /* Compute the length of a branch sequence, and adjust the
17424 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17425 worst-case length is computed, with UPDATE being used to indicate
17426 whether an unconditional (-1), or regular (0) branch is to be
17430 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17432 bfd_boolean toofar
;
17436 && S_IS_DEFINED (fragp
->fr_symbol
)
17437 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17442 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17443 /* Ignore the low bit in the target, since it will be set
17444 for a text label. */
17445 if ((val
& 1) != 0)
17448 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17452 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17455 /* If the symbol is not defined or it's in a different segment,
17456 assume the user knows what's going on and emit a short
17462 if (fragp
&& update
17463 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17464 fragp
->fr_subtype
= (toofar
17465 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17466 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17471 bfd_boolean compact_known
= fragp
!= NULL
;
17472 bfd_boolean compact
= FALSE
;
17473 bfd_boolean uncond
;
17476 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17478 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17480 uncond
= update
< 0;
17482 /* If label is out of range, we turn branch <br>:
17484 <br> label # 4 bytes
17490 nop # 2 bytes if compact && !PIC
17493 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17496 /* If assembling PIC code, we further turn:
17502 lw/ld at, %got(label)(gp) # 4 bytes
17503 d/addiu at, %lo(label) # 4 bytes
17506 if (mips_pic
!= NO_PIC
)
17509 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17511 <brneg> 0f # 4 bytes
17512 nop # 2 bytes if !compact
17515 length
+= (compact_known
&& compact
) ? 4 : 6;
17521 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17522 bit accordingly. */
17525 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17527 bfd_boolean toofar
;
17530 && S_IS_DEFINED (fragp
->fr_symbol
)
17531 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17537 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17538 /* Ignore the low bit in the target, since it will be set
17539 for a text label. */
17540 if ((val
& 1) != 0)
17543 /* Assume this is a 2-byte branch. */
17544 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17546 /* We try to avoid the infinite loop by not adding 2 more bytes for
17551 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17553 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17554 else if (type
== 'E')
17555 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17560 /* If the symbol is not defined or it's in a different segment,
17561 we emit a normal 32-bit branch. */
17564 if (fragp
&& update
17565 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17567 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17568 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17576 /* Estimate the size of a frag before relaxing. Unless this is the
17577 mips16, we are not really relaxing here, and the final size is
17578 encoded in the subtype information. For the mips16, we have to
17579 decide whether we are using an extended opcode or not. */
17582 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17586 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17589 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17591 return fragp
->fr_var
;
17594 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17595 /* We don't want to modify the EXTENDED bit here; it might get us
17596 into infinite loops. We change it only in mips_relax_frag(). */
17597 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17599 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17603 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17604 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17605 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17606 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17607 fragp
->fr_var
= length
;
17612 if (mips_pic
== NO_PIC
)
17613 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17614 else if (mips_pic
== SVR4_PIC
)
17615 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17616 else if (mips_pic
== VXWORKS_PIC
)
17617 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17624 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17625 return -RELAX_FIRST (fragp
->fr_subtype
);
17628 return -RELAX_SECOND (fragp
->fr_subtype
);
17631 /* This is called to see whether a reloc against a defined symbol
17632 should be converted into a reloc against a section. */
17635 mips_fix_adjustable (fixS
*fixp
)
17637 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17638 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17641 if (fixp
->fx_addsy
== NULL
)
17644 /* If symbol SYM is in a mergeable section, relocations of the form
17645 SYM + 0 can usually be made section-relative. The mergeable data
17646 is then identified by the section offset rather than by the symbol.
17648 However, if we're generating REL LO16 relocations, the offset is split
17649 between the LO16 and parterning high part relocation. The linker will
17650 need to recalculate the complete offset in order to correctly identify
17653 The linker has traditionally not looked for the parterning high part
17654 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17655 placed anywhere. Rather than break backwards compatibility by changing
17656 this, it seems better not to force the issue, and instead keep the
17657 original symbol. This will work with either linker behavior. */
17658 if ((lo16_reloc_p (fixp
->fx_r_type
)
17659 || reloc_needs_lo_p (fixp
->fx_r_type
))
17660 && HAVE_IN_PLACE_ADDENDS
17661 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17664 /* There is no place to store an in-place offset for JALR relocations.
17665 Likewise an in-range offset of PC-relative relocations may overflow
17666 the in-place relocatable field if recalculated against the start
17667 address of the symbol's containing section. */
17668 if (HAVE_IN_PLACE_ADDENDS
17669 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17673 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17674 to a floating-point stub. The same is true for non-R_MIPS16_26
17675 relocations against MIPS16 functions; in this case, the stub becomes
17676 the function's canonical address.
17678 Floating-point stubs are stored in unique .mips16.call.* or
17679 .mips16.fn.* sections. If a stub T for function F is in section S,
17680 the first relocation in section S must be against F; this is how the
17681 linker determines the target function. All relocations that might
17682 resolve to T must also be against F. We therefore have the following
17683 restrictions, which are given in an intentionally-redundant way:
17685 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17688 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17689 if that stub might be used.
17691 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17694 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17695 that stub might be used.
17697 There is a further restriction:
17699 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17700 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17701 targets with in-place addends; the relocation field cannot
17702 encode the low bit.
17704 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17705 against a MIPS16 symbol. We deal with (5) by by not reducing any
17706 such relocations on REL targets.
17708 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17709 relocation against some symbol R, no relocation against R may be
17710 reduced. (Note that this deals with (2) as well as (1) because
17711 relocations against global symbols will never be reduced on ELF
17712 targets.) This approach is a little simpler than trying to detect
17713 stub sections, and gives the "all or nothing" per-symbol consistency
17714 that we have for MIPS16 symbols. */
17716 && fixp
->fx_subsy
== NULL
17717 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17718 || *symbol_get_tc (fixp
->fx_addsy
)
17719 || (HAVE_IN_PLACE_ADDENDS
17720 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17721 && jmp_reloc_p (fixp
->fx_r_type
))))
17728 /* Translate internal representation of relocation info to BFD target
17732 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17734 static arelent
*retval
[4];
17736 bfd_reloc_code_real_type code
;
17738 memset (retval
, 0, sizeof(retval
));
17739 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17740 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17741 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17742 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17744 if (fixp
->fx_pcrel
)
17746 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17747 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17748 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17749 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17751 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17752 Relocations want only the symbol offset. */
17753 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17756 /* A gruesome hack which is a result of the gruesome gas
17757 reloc handling. What's worse, for COFF (as opposed to
17758 ECOFF), we might need yet another copy of reloc->address.
17759 See bfd_install_relocation. */
17760 reloc
->addend
+= reloc
->address
;
17764 reloc
->addend
= fixp
->fx_addnumber
;
17766 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17767 entry to be used in the relocation's section offset. */
17768 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17770 reloc
->address
= reloc
->addend
;
17774 code
= fixp
->fx_r_type
;
17776 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17777 if (reloc
->howto
== NULL
)
17779 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17780 _("Can not represent %s relocation in this object file format"),
17781 bfd_get_reloc_code_name (code
));
17788 /* Relax a machine dependent frag. This returns the amount by which
17789 the current size of the frag should change. */
17792 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17794 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17796 offsetT old_var
= fragp
->fr_var
;
17798 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17800 return fragp
->fr_var
- old_var
;
17803 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17805 offsetT old_var
= fragp
->fr_var
;
17806 offsetT new_var
= 4;
17808 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17809 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17810 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17811 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17812 fragp
->fr_var
= new_var
;
17814 return new_var
- old_var
;
17817 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17820 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17822 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17824 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17829 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17831 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17838 /* Convert a machine dependent frag. */
17841 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17843 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17846 unsigned long insn
;
17850 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17851 insn
= read_insn (buf
);
17853 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17855 /* We generate a fixup instead of applying it right now
17856 because, if there are linker relaxations, we're going to
17857 need the relocations. */
17858 exp
.X_op
= O_symbol
;
17859 exp
.X_add_symbol
= fragp
->fr_symbol
;
17860 exp
.X_add_number
= fragp
->fr_offset
;
17862 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17863 BFD_RELOC_16_PCREL_S2
);
17864 fixp
->fx_file
= fragp
->fr_file
;
17865 fixp
->fx_line
= fragp
->fr_line
;
17867 buf
= write_insn (buf
, insn
);
17873 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17874 _("Relaxed out-of-range branch into a jump"));
17876 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17879 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17881 /* Reverse the branch. */
17882 switch ((insn
>> 28) & 0xf)
17885 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17886 have the condition reversed by tweaking a single
17887 bit, and their opcodes all have 0x4???????. */
17888 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17889 insn
^= 0x00010000;
17893 /* bltz 0x04000000 bgez 0x04010000
17894 bltzal 0x04100000 bgezal 0x04110000 */
17895 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17896 insn
^= 0x00010000;
17900 /* beq 0x10000000 bne 0x14000000
17901 blez 0x18000000 bgtz 0x1c000000 */
17902 insn
^= 0x04000000;
17910 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17912 /* Clear the and-link bit. */
17913 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17915 /* bltzal 0x04100000 bgezal 0x04110000
17916 bltzall 0x04120000 bgezall 0x04130000 */
17917 insn
&= ~0x00100000;
17920 /* Branch over the branch (if the branch was likely) or the
17921 full jump (not likely case). Compute the offset from the
17922 current instruction to branch to. */
17923 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17927 /* How many bytes in instructions we've already emitted? */
17928 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17929 /* How many bytes in instructions from here to the end? */
17930 i
= fragp
->fr_var
- i
;
17932 /* Convert to instruction count. */
17934 /* Branch counts from the next instruction. */
17937 /* Branch over the jump. */
17938 buf
= write_insn (buf
, insn
);
17941 buf
= write_insn (buf
, 0);
17943 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17945 /* beql $0, $0, 2f */
17947 /* Compute the PC offset from the current instruction to
17948 the end of the variable frag. */
17949 /* How many bytes in instructions we've already emitted? */
17950 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17951 /* How many bytes in instructions from here to the end? */
17952 i
= fragp
->fr_var
- i
;
17953 /* Convert to instruction count. */
17955 /* Don't decrement i, because we want to branch over the
17959 buf
= write_insn (buf
, insn
);
17960 buf
= write_insn (buf
, 0);
17964 if (mips_pic
== NO_PIC
)
17967 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17968 ? 0x0c000000 : 0x08000000);
17969 exp
.X_op
= O_symbol
;
17970 exp
.X_add_symbol
= fragp
->fr_symbol
;
17971 exp
.X_add_number
= fragp
->fr_offset
;
17973 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17974 FALSE
, BFD_RELOC_MIPS_JMP
);
17975 fixp
->fx_file
= fragp
->fr_file
;
17976 fixp
->fx_line
= fragp
->fr_line
;
17978 buf
= write_insn (buf
, insn
);
17982 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17984 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17985 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17986 insn
|= at
<< OP_SH_RT
;
17987 exp
.X_op
= O_symbol
;
17988 exp
.X_add_symbol
= fragp
->fr_symbol
;
17989 exp
.X_add_number
= fragp
->fr_offset
;
17991 if (fragp
->fr_offset
)
17993 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17994 exp
.X_add_number
= 0;
17997 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17998 FALSE
, BFD_RELOC_MIPS_GOT16
);
17999 fixp
->fx_file
= fragp
->fr_file
;
18000 fixp
->fx_line
= fragp
->fr_line
;
18002 buf
= write_insn (buf
, insn
);
18004 if (mips_opts
.isa
== ISA_MIPS1
)
18006 buf
= write_insn (buf
, 0);
18008 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18009 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18010 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18012 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18013 FALSE
, BFD_RELOC_LO16
);
18014 fixp
->fx_file
= fragp
->fr_file
;
18015 fixp
->fx_line
= fragp
->fr_line
;
18017 buf
= write_insn (buf
, insn
);
18020 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18024 insn
|= at
<< OP_SH_RS
;
18026 buf
= write_insn (buf
, insn
);
18030 fragp
->fr_fix
+= fragp
->fr_var
;
18031 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18035 /* Relax microMIPS branches. */
18036 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18038 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18039 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18040 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18041 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18042 bfd_boolean short_ds
;
18043 unsigned long insn
;
18047 exp
.X_op
= O_symbol
;
18048 exp
.X_add_symbol
= fragp
->fr_symbol
;
18049 exp
.X_add_number
= fragp
->fr_offset
;
18051 fragp
->fr_fix
+= fragp
->fr_var
;
18053 /* Handle 16-bit branches that fit or are forced to fit. */
18054 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18056 /* We generate a fixup instead of applying it right now,
18057 because if there is linker relaxation, we're going to
18058 need the relocations. */
18060 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18061 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18062 else if (type
== 'E')
18063 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18064 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18068 fixp
->fx_file
= fragp
->fr_file
;
18069 fixp
->fx_line
= fragp
->fr_line
;
18071 /* These relocations can have an addend that won't fit in
18073 fixp
->fx_no_overflow
= 1;
18078 /* Handle 32-bit branches that fit or are forced to fit. */
18079 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18080 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18082 /* We generate a fixup instead of applying it right now,
18083 because if there is linker relaxation, we're going to
18084 need the relocations. */
18085 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18086 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18087 fixp
->fx_file
= fragp
->fr_file
;
18088 fixp
->fx_line
= fragp
->fr_line
;
18094 /* Relax 16-bit branches to 32-bit branches. */
18097 insn
= read_compressed_insn (buf
, 2);
18099 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18100 insn
= 0x94000000; /* beq */
18101 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18103 unsigned long regno
;
18105 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18106 regno
= micromips_to_32_reg_d_map
[regno
];
18107 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18108 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18113 /* Nothing else to do, just write it out. */
18114 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18115 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18117 buf
= write_compressed_insn (buf
, insn
, 4);
18118 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18123 insn
= read_compressed_insn (buf
, 4);
18125 /* Relax 32-bit branches to a sequence of instructions. */
18126 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18127 _("Relaxed out-of-range branch into a jump"));
18129 /* Set the short-delay-slot bit. */
18130 short_ds
= al
&& (insn
& 0x02000000) != 0;
18132 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18136 /* Reverse the branch. */
18137 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18138 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18139 insn
^= 0x20000000;
18140 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18141 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18142 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18143 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18144 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18145 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18146 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18147 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18148 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18149 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18150 insn
^= 0x00400000;
18151 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18152 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18153 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18154 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18155 insn
^= 0x00200000;
18161 /* Clear the and-link and short-delay-slot bits. */
18162 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18164 /* bltzal 0x40200000 bgezal 0x40600000 */
18165 /* bltzals 0x42200000 bgezals 0x42600000 */
18166 insn
&= ~0x02200000;
18169 /* Make a label at the end for use with the branch. */
18170 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18171 micromips_label_inc ();
18172 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18174 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18178 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18179 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18180 fixp
->fx_file
= fragp
->fr_file
;
18181 fixp
->fx_line
= fragp
->fr_line
;
18183 /* Branch over the jump. */
18184 buf
= write_compressed_insn (buf
, insn
, 4);
18187 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18190 if (mips_pic
== NO_PIC
)
18192 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18194 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18195 insn
= al
? jal
: 0xd4000000;
18197 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18198 BFD_RELOC_MICROMIPS_JMP
);
18199 fixp
->fx_file
= fragp
->fr_file
;
18200 fixp
->fx_line
= fragp
->fr_line
;
18202 buf
= write_compressed_insn (buf
, insn
, 4);
18205 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18209 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18210 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18211 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18213 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18214 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18215 insn
|= at
<< MICROMIPSOP_SH_RT
;
18217 if (exp
.X_add_number
)
18219 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18220 exp
.X_add_number
= 0;
18223 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18224 BFD_RELOC_MICROMIPS_GOT16
);
18225 fixp
->fx_file
= fragp
->fr_file
;
18226 fixp
->fx_line
= fragp
->fr_line
;
18228 buf
= write_compressed_insn (buf
, insn
, 4);
18230 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18231 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18232 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18234 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18235 BFD_RELOC_MICROMIPS_LO16
);
18236 fixp
->fx_file
= fragp
->fr_file
;
18237 fixp
->fx_line
= fragp
->fr_line
;
18239 buf
= write_compressed_insn (buf
, insn
, 4);
18241 /* jr/jrc/jalr/jalrs $at */
18242 insn
= al
? jalr
: jr
;
18243 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18245 buf
= write_compressed_insn (buf
, insn
, 2);
18248 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18252 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18255 const struct mips16_immed_operand
*op
;
18258 unsigned int user_length
, length
;
18259 unsigned long insn
;
18262 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18263 op
= mips16_immed_operands
;
18264 while (op
->type
!= type
)
18267 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18268 val
= resolve_symbol_value (fragp
->fr_symbol
);
18273 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18275 /* The rules for the base address of a PC relative reloc are
18276 complicated; see mips16_extended_frag. */
18277 if (type
== 'p' || type
== 'q')
18282 /* Ignore the low bit in the target, since it will be
18283 set for a text label. */
18284 if ((val
& 1) != 0)
18287 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18289 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18292 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18295 /* Make sure the section winds up with the alignment we have
18298 record_alignment (asec
, op
->shift
);
18302 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18303 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18304 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18305 _("extended instruction in delay slot"));
18307 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18309 insn
= read_compressed_insn (buf
, 2);
18311 insn
|= MIPS16_EXTEND
;
18313 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18315 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18320 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18321 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18323 length
= (ext
? 4 : 2);
18324 gas_assert (mips16_opcode_length (insn
) == length
);
18325 write_compressed_insn (buf
, insn
, length
);
18326 fragp
->fr_fix
+= length
;
18330 relax_substateT subtype
= fragp
->fr_subtype
;
18331 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18332 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18336 first
= RELAX_FIRST (subtype
);
18337 second
= RELAX_SECOND (subtype
);
18338 fixp
= (fixS
*) fragp
->fr_opcode
;
18340 /* If the delay slot chosen does not match the size of the instruction,
18341 then emit a warning. */
18342 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18343 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18348 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18349 | RELAX_DELAY_SLOT_SIZE_FIRST
18350 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18351 msg
= macro_warning (s
);
18353 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18357 /* Possibly emit a warning if we've chosen the longer option. */
18358 if (use_second
== second_longer
)
18364 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18365 msg
= macro_warning (s
);
18367 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18371 /* Go through all the fixups for the first sequence. Disable them
18372 (by marking them as done) if we're going to use the second
18373 sequence instead. */
18375 && fixp
->fx_frag
== fragp
18376 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18378 if (subtype
& RELAX_USE_SECOND
)
18380 fixp
= fixp
->fx_next
;
18383 /* Go through the fixups for the second sequence. Disable them if
18384 we're going to use the first sequence, otherwise adjust their
18385 addresses to account for the relaxation. */
18386 while (fixp
&& fixp
->fx_frag
== fragp
)
18388 if (subtype
& RELAX_USE_SECOND
)
18389 fixp
->fx_where
-= first
;
18392 fixp
= fixp
->fx_next
;
18395 /* Now modify the frag contents. */
18396 if (subtype
& RELAX_USE_SECOND
)
18400 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18401 memmove (start
, start
+ first
, second
);
18402 fragp
->fr_fix
-= first
;
18405 fragp
->fr_fix
-= second
;
18411 /* This function is called after the relocs have been generated.
18412 We've been storing mips16 text labels as odd. Here we convert them
18413 back to even for the convenience of the debugger. */
18416 mips_frob_file_after_relocs (void)
18419 unsigned int count
, i
;
18424 syms
= bfd_get_outsymbols (stdoutput
);
18425 count
= bfd_get_symcount (stdoutput
);
18426 for (i
= 0; i
< count
; i
++, syms
++)
18427 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18428 && ((*syms
)->value
& 1) != 0)
18430 (*syms
)->value
&= ~1;
18431 /* If the symbol has an odd size, it was probably computed
18432 incorrectly, so adjust that as well. */
18433 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18434 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18440 /* This function is called whenever a label is defined, including fake
18441 labels instantiated off the dot special symbol. It is used when
18442 handling branch delays; if a branch has a label, we assume we cannot
18443 move it. This also bumps the value of the symbol by 1 in compressed
18447 mips_record_label (symbolS
*sym
)
18449 segment_info_type
*si
= seg_info (now_seg
);
18450 struct insn_label_list
*l
;
18452 if (free_insn_labels
== NULL
)
18453 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18456 l
= free_insn_labels
;
18457 free_insn_labels
= l
->next
;
18461 l
->next
= si
->label_list
;
18462 si
->label_list
= l
;
18465 /* This function is called as tc_frob_label() whenever a label is defined
18466 and adds a DWARF-2 record we only want for true labels. */
18469 mips_define_label (symbolS
*sym
)
18471 mips_record_label (sym
);
18473 dwarf2_emit_label (sym
);
18477 /* This function is called by tc_new_dot_label whenever a new dot symbol
18481 mips_add_dot_label (symbolS
*sym
)
18483 mips_record_label (sym
);
18484 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18485 mips_compressed_mark_label (sym
);
18488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18490 /* Some special processing for a MIPS ELF file. */
18493 mips_elf_final_processing (void)
18495 /* Write out the register information. */
18496 if (mips_abi
!= N64_ABI
)
18500 s
.ri_gprmask
= mips_gprmask
;
18501 s
.ri_cprmask
[0] = mips_cprmask
[0];
18502 s
.ri_cprmask
[1] = mips_cprmask
[1];
18503 s
.ri_cprmask
[2] = mips_cprmask
[2];
18504 s
.ri_cprmask
[3] = mips_cprmask
[3];
18505 /* The gp_value field is set by the MIPS ELF backend. */
18507 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18508 ((Elf32_External_RegInfo
*)
18509 mips_regmask_frag
));
18513 Elf64_Internal_RegInfo s
;
18515 s
.ri_gprmask
= mips_gprmask
;
18517 s
.ri_cprmask
[0] = mips_cprmask
[0];
18518 s
.ri_cprmask
[1] = mips_cprmask
[1];
18519 s
.ri_cprmask
[2] = mips_cprmask
[2];
18520 s
.ri_cprmask
[3] = mips_cprmask
[3];
18521 /* The gp_value field is set by the MIPS ELF backend. */
18523 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18524 ((Elf64_External_RegInfo
*)
18525 mips_regmask_frag
));
18528 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18529 sort of BFD interface for this. */
18530 if (mips_any_noreorder
)
18531 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18532 if (mips_pic
!= NO_PIC
)
18534 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18535 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18538 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18540 /* Set MIPS ELF flags for ASEs. */
18541 /* We may need to define a new flag for DSP ASE, and set this flag when
18542 file_ase_dsp is true. */
18543 /* Same for DSP R2. */
18544 /* We may need to define a new flag for MT ASE, and set this flag when
18545 file_ase_mt is true. */
18546 if (file_ase_mips16
)
18547 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18548 if (file_ase_micromips
)
18549 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18550 #if 0 /* XXX FIXME */
18551 if (file_ase_mips3d
)
18552 elf_elfheader (stdoutput
)->e_flags
|= ???;
18555 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18557 /* Set the MIPS ELF ABI flags. */
18558 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18559 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18560 else if (mips_abi
== O64_ABI
)
18561 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18562 else if (mips_abi
== EABI_ABI
)
18564 if (!file_mips_gp32
)
18565 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18567 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18569 else if (mips_abi
== N32_ABI
)
18570 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18572 /* Nothing to do for N64_ABI. */
18574 if (mips_32bitmode
)
18575 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18577 #if 0 /* XXX FIXME */
18578 /* 32 bit code with 64 bit FP registers. */
18579 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18580 elf_elfheader (stdoutput
)->e_flags
|= ???;
18584 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18586 typedef struct proc
{
18588 symbolS
*func_end_sym
;
18589 unsigned long reg_mask
;
18590 unsigned long reg_offset
;
18591 unsigned long fpreg_mask
;
18592 unsigned long fpreg_offset
;
18593 unsigned long frame_offset
;
18594 unsigned long frame_reg
;
18595 unsigned long pc_reg
;
18598 static procS cur_proc
;
18599 static procS
*cur_proc_ptr
;
18600 static int numprocs
;
18602 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18603 as "2", and a normal nop as "0". */
18605 #define NOP_OPCODE_MIPS 0
18606 #define NOP_OPCODE_MIPS16 1
18607 #define NOP_OPCODE_MICROMIPS 2
18610 mips_nop_opcode (void)
18612 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18613 return NOP_OPCODE_MICROMIPS
;
18614 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18615 return NOP_OPCODE_MIPS16
;
18617 return NOP_OPCODE_MIPS
;
18620 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18621 32-bit microMIPS NOPs here (if applicable). */
18624 mips_handle_align (fragS
*fragp
)
18628 int bytes
, size
, excess
;
18631 if (fragp
->fr_type
!= rs_align_code
)
18634 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18636 switch (nop_opcode
)
18638 case NOP_OPCODE_MICROMIPS
:
18639 opcode
= micromips_nop32_insn
.insn_opcode
;
18642 case NOP_OPCODE_MIPS16
:
18643 opcode
= mips16_nop_insn
.insn_opcode
;
18646 case NOP_OPCODE_MIPS
:
18648 opcode
= nop_insn
.insn_opcode
;
18653 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18654 excess
= bytes
% size
;
18656 /* Handle the leading part if we're not inserting a whole number of
18657 instructions, and make it the end of the fixed part of the frag.
18658 Try to fit in a short microMIPS NOP if applicable and possible,
18659 and use zeroes otherwise. */
18660 gas_assert (excess
< 4);
18661 fragp
->fr_fix
+= excess
;
18666 /* Fall through. */
18668 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18670 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18674 /* Fall through. */
18677 /* Fall through. */
18682 md_number_to_chars (p
, opcode
, size
);
18683 fragp
->fr_var
= size
;
18687 md_obj_begin (void)
18694 /* Check for premature end, nesting errors, etc. */
18696 as_warn (_("missing .end at end of assembly"));
18705 if (*input_line_pointer
== '-')
18707 ++input_line_pointer
;
18710 if (!ISDIGIT (*input_line_pointer
))
18711 as_bad (_("expected simple number"));
18712 if (input_line_pointer
[0] == '0')
18714 if (input_line_pointer
[1] == 'x')
18716 input_line_pointer
+= 2;
18717 while (ISXDIGIT (*input_line_pointer
))
18720 val
|= hex_value (*input_line_pointer
++);
18722 return negative
? -val
: val
;
18726 ++input_line_pointer
;
18727 while (ISDIGIT (*input_line_pointer
))
18730 val
|= *input_line_pointer
++ - '0';
18732 return negative
? -val
: val
;
18735 if (!ISDIGIT (*input_line_pointer
))
18737 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18738 *input_line_pointer
, *input_line_pointer
);
18739 as_warn (_("invalid number"));
18742 while (ISDIGIT (*input_line_pointer
))
18745 val
+= *input_line_pointer
++ - '0';
18747 return negative
? -val
: val
;
18750 /* The .file directive; just like the usual .file directive, but there
18751 is an initial number which is the ECOFF file index. In the non-ECOFF
18752 case .file implies DWARF-2. */
18755 s_mips_file (int x ATTRIBUTE_UNUSED
)
18757 static int first_file_directive
= 0;
18759 if (ECOFF_DEBUGGING
)
18768 filename
= dwarf2_directive_file (0);
18770 /* Versions of GCC up to 3.1 start files with a ".file"
18771 directive even for stabs output. Make sure that this
18772 ".file" is handled. Note that you need a version of GCC
18773 after 3.1 in order to support DWARF-2 on MIPS. */
18774 if (filename
!= NULL
&& ! first_file_directive
)
18776 (void) new_logical_line (filename
, -1);
18777 s_app_file_string (filename
, 0);
18779 first_file_directive
= 1;
18783 /* The .loc directive, implying DWARF-2. */
18786 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18788 if (!ECOFF_DEBUGGING
)
18789 dwarf2_directive_loc (0);
18792 /* The .end directive. */
18795 s_mips_end (int x ATTRIBUTE_UNUSED
)
18799 /* Following functions need their own .frame and .cprestore directives. */
18800 mips_frame_reg_valid
= 0;
18801 mips_cprestore_valid
= 0;
18803 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18806 demand_empty_rest_of_line ();
18811 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18812 as_warn (_(".end not in text section"));
18816 as_warn (_(".end directive without a preceding .ent directive."));
18817 demand_empty_rest_of_line ();
18823 gas_assert (S_GET_NAME (p
));
18824 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18825 as_warn (_(".end symbol does not match .ent symbol."));
18827 if (debug_type
== DEBUG_STABS
)
18828 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18832 as_warn (_(".end directive missing or unknown symbol"));
18835 /* Create an expression to calculate the size of the function. */
18836 if (p
&& cur_proc_ptr
)
18838 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18839 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18842 exp
->X_op
= O_subtract
;
18843 exp
->X_add_symbol
= symbol_temp_new_now ();
18844 exp
->X_op_symbol
= p
;
18845 exp
->X_add_number
= 0;
18847 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18850 /* Generate a .pdr section. */
18851 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18853 segT saved_seg
= now_seg
;
18854 subsegT saved_subseg
= now_subseg
;
18858 #ifdef md_flush_pending_output
18859 md_flush_pending_output ();
18862 gas_assert (pdr_seg
);
18863 subseg_set (pdr_seg
, 0);
18865 /* Write the symbol. */
18866 exp
.X_op
= O_symbol
;
18867 exp
.X_add_symbol
= p
;
18868 exp
.X_add_number
= 0;
18869 emit_expr (&exp
, 4);
18871 fragp
= frag_more (7 * 4);
18873 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18874 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18875 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18876 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18877 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18878 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18879 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18881 subseg_set (saved_seg
, saved_subseg
);
18883 #endif /* OBJ_ELF */
18885 cur_proc_ptr
= NULL
;
18888 /* The .aent and .ent directives. */
18891 s_mips_ent (int aent
)
18895 symbolP
= get_symbol ();
18896 if (*input_line_pointer
== ',')
18897 ++input_line_pointer
;
18898 SKIP_WHITESPACE ();
18899 if (ISDIGIT (*input_line_pointer
)
18900 || *input_line_pointer
== '-')
18903 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18904 as_warn (_(".ent or .aent not in text section."));
18906 if (!aent
&& cur_proc_ptr
)
18907 as_warn (_("missing .end"));
18911 /* This function needs its own .frame and .cprestore directives. */
18912 mips_frame_reg_valid
= 0;
18913 mips_cprestore_valid
= 0;
18915 cur_proc_ptr
= &cur_proc
;
18916 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18918 cur_proc_ptr
->func_sym
= symbolP
;
18922 if (debug_type
== DEBUG_STABS
)
18923 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18924 S_GET_NAME (symbolP
));
18927 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18929 demand_empty_rest_of_line ();
18932 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18933 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18934 s_mips_frame is used so that we can set the PDR information correctly.
18935 We can't use the ecoff routines because they make reference to the ecoff
18936 symbol table (in the mdebug section). */
18939 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18942 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18946 if (cur_proc_ptr
== (procS
*) NULL
)
18948 as_warn (_(".frame outside of .ent"));
18949 demand_empty_rest_of_line ();
18953 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18955 SKIP_WHITESPACE ();
18956 if (*input_line_pointer
++ != ','
18957 || get_absolute_expression_and_terminator (&val
) != ',')
18959 as_warn (_("Bad .frame directive"));
18960 --input_line_pointer
;
18961 demand_empty_rest_of_line ();
18965 cur_proc_ptr
->frame_offset
= val
;
18966 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18968 demand_empty_rest_of_line ();
18971 #endif /* OBJ_ELF */
18975 /* The .fmask and .mask directives. If the mdebug section is present
18976 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18977 embedded targets, s_mips_mask is used so that we can set the PDR
18978 information correctly. We can't use the ecoff routines because they
18979 make reference to the ecoff symbol table (in the mdebug section). */
18982 s_mips_mask (int reg_type
)
18985 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18989 if (cur_proc_ptr
== (procS
*) NULL
)
18991 as_warn (_(".mask/.fmask outside of .ent"));
18992 demand_empty_rest_of_line ();
18996 if (get_absolute_expression_and_terminator (&mask
) != ',')
18998 as_warn (_("Bad .mask/.fmask directive"));
18999 --input_line_pointer
;
19000 demand_empty_rest_of_line ();
19004 off
= get_absolute_expression ();
19006 if (reg_type
== 'F')
19008 cur_proc_ptr
->fpreg_mask
= mask
;
19009 cur_proc_ptr
->fpreg_offset
= off
;
19013 cur_proc_ptr
->reg_mask
= mask
;
19014 cur_proc_ptr
->reg_offset
= off
;
19017 demand_empty_rest_of_line ();
19020 #endif /* OBJ_ELF */
19021 s_ignore (reg_type
);
19024 /* A table describing all the processors gas knows about. Names are
19025 matched in the order listed.
19027 To ease comparison, please keep this table in the same order as
19028 gcc's mips_cpu_info_table[]. */
19029 static const struct mips_cpu_info mips_cpu_info_table
[] =
19031 /* Entries for generic ISAs */
19032 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19033 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19034 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19035 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19036 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19037 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19038 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19039 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19040 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19043 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19044 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19045 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19048 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19051 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19052 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19053 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19054 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19055 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19056 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19057 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19058 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19059 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19060 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19061 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19062 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19063 /* ST Microelectronics Loongson 2E and 2F cores */
19064 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19065 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19068 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19069 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19070 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19071 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19072 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19073 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19074 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19075 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19076 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19077 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19078 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19079 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19080 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19081 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19082 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19085 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19086 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19087 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19088 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19090 /* MIPS 32 Release 2 */
19091 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19092 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19093 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19094 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19095 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19096 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19097 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19098 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19099 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19100 ISA_MIPS32R2
, CPU_MIPS32R2
},
19101 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19102 ISA_MIPS32R2
, CPU_MIPS32R2
},
19103 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19104 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19105 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19106 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19107 /* Deprecated forms of the above. */
19108 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19109 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19110 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19111 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19112 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19113 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19114 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19115 /* Deprecated forms of the above. */
19116 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19117 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19118 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19119 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19120 ISA_MIPS32R2
, CPU_MIPS32R2
},
19121 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19122 ISA_MIPS32R2
, CPU_MIPS32R2
},
19123 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19124 ISA_MIPS32R2
, CPU_MIPS32R2
},
19125 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19126 ISA_MIPS32R2
, CPU_MIPS32R2
},
19127 /* Deprecated forms of the above. */
19128 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19129 ISA_MIPS32R2
, CPU_MIPS32R2
},
19130 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19131 ISA_MIPS32R2
, CPU_MIPS32R2
},
19132 /* 34Kn is a 34kc without DSP. */
19133 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19134 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19135 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19136 ISA_MIPS32R2
, CPU_MIPS32R2
},
19137 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19138 ISA_MIPS32R2
, CPU_MIPS32R2
},
19139 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19140 ISA_MIPS32R2
, CPU_MIPS32R2
},
19141 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19142 ISA_MIPS32R2
, CPU_MIPS32R2
},
19143 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19144 ISA_MIPS32R2
, CPU_MIPS32R2
},
19145 /* Deprecated forms of the above. */
19146 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19147 ISA_MIPS32R2
, CPU_MIPS32R2
},
19148 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19149 ISA_MIPS32R2
, CPU_MIPS32R2
},
19150 /* 1004K cores are multiprocessor versions of the 34K. */
19151 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19152 ISA_MIPS32R2
, CPU_MIPS32R2
},
19153 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19154 ISA_MIPS32R2
, CPU_MIPS32R2
},
19155 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19156 ISA_MIPS32R2
, CPU_MIPS32R2
},
19157 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19158 ISA_MIPS32R2
, CPU_MIPS32R2
},
19161 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19162 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19163 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19164 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19166 /* Broadcom SB-1 CPU core */
19167 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19168 ISA_MIPS64
, CPU_SB1
},
19169 /* Broadcom SB-1A CPU core */
19170 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19171 ISA_MIPS64
, CPU_SB1
},
19173 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19175 /* MIPS 64 Release 2 */
19177 /* Cavium Networks Octeon CPU core */
19178 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19179 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19180 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19183 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19186 XLP is mostly like XLR, with the prominent exception that it is
19187 MIPS64R2 rather than MIPS64. */
19188 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19195 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19196 with a final "000" replaced by "k". Ignore case.
19198 Note: this function is shared between GCC and GAS. */
19201 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19203 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19204 given
++, canonical
++;
19206 return ((*given
== 0 && *canonical
== 0)
19207 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19211 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19212 CPU name. We've traditionally allowed a lot of variation here.
19214 Note: this function is shared between GCC and GAS. */
19217 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19219 /* First see if the name matches exactly, or with a final "000"
19220 turned into "k". */
19221 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19224 /* If not, try comparing based on numerical designation alone.
19225 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19226 if (TOLOWER (*given
) == 'r')
19228 if (!ISDIGIT (*given
))
19231 /* Skip over some well-known prefixes in the canonical name,
19232 hoping to find a number there too. */
19233 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19235 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19237 else if (TOLOWER (canonical
[0]) == 'r')
19240 return mips_strict_matching_cpu_name_p (canonical
, given
);
19244 /* Parse an option that takes the name of a processor as its argument.
19245 OPTION is the name of the option and CPU_STRING is the argument.
19246 Return the corresponding processor enumeration if the CPU_STRING is
19247 recognized, otherwise report an error and return null.
19249 A similar function exists in GCC. */
19251 static const struct mips_cpu_info
*
19252 mips_parse_cpu (const char *option
, const char *cpu_string
)
19254 const struct mips_cpu_info
*p
;
19256 /* 'from-abi' selects the most compatible architecture for the given
19257 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19258 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19259 version. Look first at the -mgp options, if given, otherwise base
19260 the choice on MIPS_DEFAULT_64BIT.
19262 Treat NO_ABI like the EABIs. One reason to do this is that the
19263 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19264 architecture. This code picks MIPS I for 'mips' and MIPS III for
19265 'mips64', just as we did in the days before 'from-abi'. */
19266 if (strcasecmp (cpu_string
, "from-abi") == 0)
19268 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19269 return mips_cpu_info_from_isa (ISA_MIPS1
);
19271 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19272 return mips_cpu_info_from_isa (ISA_MIPS3
);
19274 if (file_mips_gp32
>= 0)
19275 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19277 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19282 /* 'default' has traditionally been a no-op. Probably not very useful. */
19283 if (strcasecmp (cpu_string
, "default") == 0)
19286 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19287 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19290 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19294 /* Return the canonical processor information for ISA (a member of the
19295 ISA_MIPS* enumeration). */
19297 static const struct mips_cpu_info
*
19298 mips_cpu_info_from_isa (int isa
)
19302 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19303 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19304 && isa
== mips_cpu_info_table
[i
].isa
)
19305 return (&mips_cpu_info_table
[i
]);
19310 static const struct mips_cpu_info
*
19311 mips_cpu_info_from_arch (int arch
)
19315 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19316 if (arch
== mips_cpu_info_table
[i
].cpu
)
19317 return (&mips_cpu_info_table
[i
]);
19323 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19327 fprintf (stream
, "%24s", "");
19332 fprintf (stream
, ", ");
19336 if (*col_p
+ strlen (string
) > 72)
19338 fprintf (stream
, "\n%24s", "");
19342 fprintf (stream
, "%s", string
);
19343 *col_p
+= strlen (string
);
19349 md_show_usage (FILE *stream
)
19354 fprintf (stream
, _("\
19356 -EB generate big endian output\n\
19357 -EL generate little endian output\n\
19358 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19359 -G NUM allow referencing objects up to NUM bytes\n\
19360 implicitly with the gp register [default 8]\n"));
19361 fprintf (stream
, _("\
19362 -mips1 generate MIPS ISA I instructions\n\
19363 -mips2 generate MIPS ISA II instructions\n\
19364 -mips3 generate MIPS ISA III instructions\n\
19365 -mips4 generate MIPS ISA IV instructions\n\
19366 -mips5 generate MIPS ISA V instructions\n\
19367 -mips32 generate MIPS32 ISA instructions\n\
19368 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19369 -mips64 generate MIPS64 ISA instructions\n\
19370 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19371 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19375 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19376 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19377 show (stream
, "from-abi", &column
, &first
);
19378 fputc ('\n', stream
);
19380 fprintf (stream
, _("\
19381 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19382 -no-mCPU don't generate code specific to CPU.\n\
19383 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19387 show (stream
, "3900", &column
, &first
);
19388 show (stream
, "4010", &column
, &first
);
19389 show (stream
, "4100", &column
, &first
);
19390 show (stream
, "4650", &column
, &first
);
19391 fputc ('\n', stream
);
19393 fprintf (stream
, _("\
19394 -mips16 generate mips16 instructions\n\
19395 -no-mips16 do not generate mips16 instructions\n"));
19396 fprintf (stream
, _("\
19397 -mmicromips generate microMIPS instructions\n\
19398 -mno-micromips do not generate microMIPS instructions\n"));
19399 fprintf (stream
, _("\
19400 -msmartmips generate smartmips instructions\n\
19401 -mno-smartmips do not generate smartmips instructions\n"));
19402 fprintf (stream
, _("\
19403 -mdsp generate DSP instructions\n\
19404 -mno-dsp do not generate DSP instructions\n"));
19405 fprintf (stream
, _("\
19406 -mdspr2 generate DSP R2 instructions\n\
19407 -mno-dspr2 do not generate DSP R2 instructions\n"));
19408 fprintf (stream
, _("\
19409 -mmt generate MT instructions\n\
19410 -mno-mt do not generate MT instructions\n"));
19411 fprintf (stream
, _("\
19412 -mmcu generate MCU instructions\n\
19413 -mno-mcu do not generate MCU instructions\n"));
19414 fprintf (stream
, _("\
19415 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19416 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19417 -mfix-vr4120 work around certain VR4120 errata\n\
19418 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19419 -mfix-24k insert a nop after ERET and DERET instructions\n\
19420 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19421 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19422 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19423 -msym32 assume all symbols have 32-bit values\n\
19424 -O0 remove unneeded NOPs, do not swap branches\n\
19425 -O remove unneeded NOPs and swap branches\n\
19426 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19427 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19428 fprintf (stream
, _("\
19429 -mhard-float allow floating-point instructions\n\
19430 -msoft-float do not allow floating-point instructions\n\
19431 -msingle-float only allow 32-bit floating-point operations\n\
19432 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19433 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19436 fprintf (stream
, _("\
19437 -KPIC, -call_shared generate SVR4 position independent code\n\
19438 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19439 -mvxworks-pic generate VxWorks position independent code\n\
19440 -non_shared do not generate code that can operate with DSOs\n\
19441 -xgot assume a 32 bit GOT\n\
19442 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19443 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19444 position dependent (non shared) code\n\
19445 -mabi=ABI create ABI conformant object file for:\n"));
19449 show (stream
, "32", &column
, &first
);
19450 show (stream
, "o64", &column
, &first
);
19451 show (stream
, "n32", &column
, &first
);
19452 show (stream
, "64", &column
, &first
);
19453 show (stream
, "eabi", &column
, &first
);
19455 fputc ('\n', stream
);
19457 fprintf (stream
, _("\
19458 -32 create o32 ABI object file (default)\n\
19459 -n32 create n32 ABI object file\n\
19460 -64 create 64 ABI object file\n"));
19466 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19468 if (HAVE_64BIT_SYMBOLS
)
19469 return dwarf2_format_64bit_irix
;
19471 return dwarf2_format_32bit
;
19476 mips_dwarf2_addr_size (void)
19478 if (HAVE_64BIT_OBJECTS
)
19484 /* Standard calling conventions leave the CFA at SP on entry. */
19486 mips_cfi_frame_initial_instructions (void)
19488 cfi_add_CFA_def_cfa_register (SP
);
19492 tc_mips_regname_to_dw2regnum (char *regname
)
19494 unsigned int regnum
= -1;
19497 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))