1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
240 /* True if -mgp32 was passed. */
241 static int file_mips_gp32
= -1;
243 /* True if -mfp32 was passed. */
244 static int file_mips_fp32
= -1;
246 /* This is the struct we use to hold the current set of options. Note
247 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
248 -1 to indicate that they have not been initialized. */
250 static struct mips_set_options mips_opts
=
252 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, -1, 0, ATREG
, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
255 /* These variables are filled in with the masks of registers used.
256 The object format code reads them and puts them in the appropriate
258 unsigned long mips_gprmask
;
259 unsigned long mips_cprmask
[4];
261 /* MIPS ISA we are using for this output file. */
262 static int file_mips_isa
= ISA_UNKNOWN
;
264 /* True if -mips16 was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips16
;
268 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
269 || mips_opts.isa == ISA_MIPS32R2 \
270 || mips_opts.isa == ISA_MIPS64 \
271 || mips_opts.isa == ISA_MIPS64R2)
273 /* True if -mips3d was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_mips3d
;
277 /* True if -mdmx was passed or implied by arguments passed on the
278 command line (e.g., by -march). */
279 static int file_ase_mdmx
;
281 /* True if -msmartmips was passed or implied by arguments passed on the
282 command line (e.g., by -march). */
283 static int file_ase_smartmips
;
285 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
286 || mips_opts.isa == ISA_MIPS32R2)
288 /* True if -mdsp was passed or implied by arguments passed on the
289 command line (e.g., by -march). */
290 static int file_ase_dsp
;
292 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64R2)
295 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
297 /* True if -mdspr2 was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_dspr2
;
301 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
302 || mips_opts.isa == ISA_MIPS64R2)
304 /* True if -mmt was passed or implied by arguments passed on the
305 command line (e.g., by -march). */
306 static int file_ase_mt
;
308 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* The argument of the -march= flag. The architecture we are assembling. */
312 static int file_mips_arch
= CPU_UNKNOWN
;
313 static const char *mips_arch_string
;
315 /* The argument of the -mtune= flag. The architecture for which we
317 static int mips_tune
= CPU_UNKNOWN
;
318 static const char *mips_tune_string
;
320 /* True when generating 32-bit code for a 64-bit processor. */
321 static int mips_32bitmode
= 0;
323 /* True if the given ABI requires 32-bit registers. */
324 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
326 /* Likewise 64-bit registers. */
327 #define ABI_NEEDS_64BIT_REGS(ABI) \
329 || (ABI) == N64_ABI \
332 /* Return true if ISA supports 64 bit wide gp registers. */
333 #define ISA_HAS_64BIT_REGS(ISA) \
334 ((ISA) == ISA_MIPS3 \
335 || (ISA) == ISA_MIPS4 \
336 || (ISA) == ISA_MIPS5 \
337 || (ISA) == ISA_MIPS64 \
338 || (ISA) == ISA_MIPS64R2)
340 /* Return true if ISA supports 64 bit wide float registers. */
341 #define ISA_HAS_64BIT_FPRS(ISA) \
342 ((ISA) == ISA_MIPS3 \
343 || (ISA) == ISA_MIPS4 \
344 || (ISA) == ISA_MIPS5 \
345 || (ISA) == ISA_MIPS32R2 \
346 || (ISA) == ISA_MIPS64 \
347 || (ISA) == ISA_MIPS64R2)
349 /* Return true if ISA supports 64-bit right rotate (dror et al.)
351 #define ISA_HAS_DROR(ISA) \
352 ((ISA) == ISA_MIPS64R2)
354 /* Return true if ISA supports 32-bit right rotate (ror et al.)
356 #define ISA_HAS_ROR(ISA) \
357 ((ISA) == ISA_MIPS32R2 \
358 || (ISA) == ISA_MIPS64R2 \
359 || mips_opts.ase_smartmips)
361 /* Return true if ISA supports single-precision floats in odd registers. */
362 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
363 ((ISA) == ISA_MIPS32 \
364 || (ISA) == ISA_MIPS32R2 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2)
368 /* Return true if ISA supports move to/from high part of a 64-bit
369 floating-point register. */
370 #define ISA_HAS_MXHC1(ISA) \
371 ((ISA) == ISA_MIPS32R2 \
372 || (ISA) == ISA_MIPS64R2)
374 #define HAVE_32BIT_GPRS \
375 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
377 #define HAVE_32BIT_FPRS \
378 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
380 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
381 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
383 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
385 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
387 /* True if relocations are stored in-place. */
388 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
390 /* The ABI-derived address size. */
391 #define HAVE_64BIT_ADDRESSES \
392 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
393 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
395 /* The size of symbolic constants (i.e., expressions of the form
396 "SYMBOL" or "SYMBOL + OFFSET"). */
397 #define HAVE_32BIT_SYMBOLS \
398 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
399 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
401 /* Addresses are loaded in different ways, depending on the address size
402 in use. The n32 ABI Documentation also mandates the use of additions
403 with overflow checking, but existing implementations don't follow it. */
404 #define ADDRESS_ADD_INSN \
405 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
407 #define ADDRESS_ADDI_INSN \
408 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
410 #define ADDRESS_LOAD_INSN \
411 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
413 #define ADDRESS_STORE_INSN \
414 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
416 /* Return true if the given CPU supports the MIPS16 ASE. */
417 #define CPU_HAS_MIPS16(cpu) \
418 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
419 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
421 /* True if CPU has a dror instruction. */
422 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
424 /* True if CPU has a ror instruction. */
425 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
427 /* True if mflo and mfhi can be immediately followed by instructions
428 which write to the HI and LO registers.
430 According to MIPS specifications, MIPS ISAs I, II, and III need
431 (at least) two instructions between the reads of HI/LO and
432 instructions which write them, and later ISAs do not. Contradicting
433 the MIPS specifications, some MIPS IV processor user manuals (e.g.
434 the UM for the NEC Vr5000) document needing the instructions between
435 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
436 MIPS64 and later ISAs to have the interlocks, plus any specific
437 earlier-ISA CPUs for which CPU documentation declares that the
438 instructions are really interlocked. */
439 #define hilo_interlocks \
440 (mips_opts.isa == ISA_MIPS32 \
441 || mips_opts.isa == ISA_MIPS32R2 \
442 || mips_opts.isa == ISA_MIPS64 \
443 || mips_opts.isa == ISA_MIPS64R2 \
444 || mips_opts.arch == CPU_R4010 \
445 || mips_opts.arch == CPU_R10000 \
446 || mips_opts.arch == CPU_R12000 \
447 || mips_opts.arch == CPU_RM7000 \
448 || mips_opts.arch == CPU_VR5500 \
451 /* Whether the processor uses hardware interlocks to protect reads
452 from the GPRs after they are loaded from memory, and thus does not
453 require nops to be inserted. This applies to instructions marked
454 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
456 #define gpr_interlocks \
457 (mips_opts.isa != ISA_MIPS1 \
458 || mips_opts.arch == CPU_R3900)
460 /* Whether the processor uses hardware interlocks to avoid delays
461 required by coprocessor instructions, and thus does not require
462 nops to be inserted. This applies to instructions marked
463 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
464 between instructions marked INSN_WRITE_COND_CODE and ones marked
465 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
466 levels I, II, and III. */
467 /* Itbl support may require additional care here. */
468 #define cop_interlocks \
469 ((mips_opts.isa != ISA_MIPS1 \
470 && mips_opts.isa != ISA_MIPS2 \
471 && mips_opts.isa != ISA_MIPS3) \
472 || mips_opts.arch == CPU_R4300 \
475 /* Whether the processor uses hardware interlocks to protect reads
476 from coprocessor registers after they are loaded from memory, and
477 thus does not require nops to be inserted. This applies to
478 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
479 requires at MIPS ISA level I. */
480 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
482 /* Is this a mfhi or mflo instruction? */
483 #define MF_HILO_INSN(PINFO) \
484 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
486 /* MIPS PIC level. */
488 enum mips_pic_level mips_pic
;
490 /* 1 if we should generate 32 bit offsets from the $gp register in
491 SVR4_PIC mode. Currently has no meaning in other modes. */
492 static int mips_big_got
= 0;
494 /* 1 if trap instructions should used for overflow rather than break
496 static int mips_trap
= 0;
498 /* 1 if double width floating point constants should not be constructed
499 by assembling two single width halves into two single width floating
500 point registers which just happen to alias the double width destination
501 register. On some architectures this aliasing can be disabled by a bit
502 in the status register, and the setting of this bit cannot be determined
503 automatically at assemble time. */
504 static int mips_disable_float_construction
;
506 /* Non-zero if any .set noreorder directives were used. */
508 static int mips_any_noreorder
;
510 /* Non-zero if nops should be inserted when the register referenced in
511 an mfhi/mflo instruction is read in the next two instructions. */
512 static int mips_7000_hilo_fix
;
514 /* The size of objects in the small data section. */
515 static unsigned int g_switch_value
= 8;
516 /* Whether the -G option was used. */
517 static int g_switch_seen
= 0;
522 /* If we can determine in advance that GP optimization won't be
523 possible, we can skip the relaxation stuff that tries to produce
524 GP-relative references. This makes delay slot optimization work
527 This function can only provide a guess, but it seems to work for
528 gcc output. It needs to guess right for gcc, otherwise gcc
529 will put what it thinks is a GP-relative instruction in a branch
532 I don't know if a fix is needed for the SVR4_PIC mode. I've only
533 fixed it for the non-PIC mode. KR 95/04/07 */
534 static int nopic_need_relax (symbolS
*, int);
536 /* handle of the OPCODE hash table */
537 static struct hash_control
*op_hash
= NULL
;
539 /* The opcode hash table we use for the mips16. */
540 static struct hash_control
*mips16_op_hash
= NULL
;
542 /* This array holds the chars that always start a comment. If the
543 pre-processor is disabled, these aren't very useful */
544 const char comment_chars
[] = "#";
546 /* This array holds the chars that only start a comment at the beginning of
547 a line. If the line seems to have the form '# 123 filename'
548 .line and .file directives will appear in the pre-processed output */
549 /* Note that input_file.c hand checks for '#' at the beginning of the
550 first line of the input file. This is because the compiler outputs
551 #NO_APP at the beginning of its output. */
552 /* Also note that C style comments are always supported. */
553 const char line_comment_chars
[] = "#";
555 /* This array holds machine specific line separator characters. */
556 const char line_separator_chars
[] = ";";
558 /* Chars that can be used to separate mant from exp in floating point nums */
559 const char EXP_CHARS
[] = "eE";
561 /* Chars that mean this number is a floating point constant */
564 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
566 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
567 changed in read.c . Ideally it shouldn't have to know about it at all,
568 but nothing is ideal around here.
571 static char *insn_error
;
573 static int auto_align
= 1;
575 /* When outputting SVR4 PIC code, the assembler needs to know the
576 offset in the stack frame from which to restore the $gp register.
577 This is set by the .cprestore pseudo-op, and saved in this
579 static offsetT mips_cprestore_offset
= -1;
581 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
582 more optimizations, it can use a register value instead of a memory-saved
583 offset and even an other register than $gp as global pointer. */
584 static offsetT mips_cpreturn_offset
= -1;
585 static int mips_cpreturn_register
= -1;
586 static int mips_gp_register
= GP
;
587 static int mips_gprel_offset
= 0;
589 /* Whether mips_cprestore_offset has been set in the current function
590 (or whether it has already been warned about, if not). */
591 static int mips_cprestore_valid
= 0;
593 /* This is the register which holds the stack frame, as set by the
594 .frame pseudo-op. This is needed to implement .cprestore. */
595 static int mips_frame_reg
= SP
;
597 /* Whether mips_frame_reg has been set in the current function
598 (or whether it has already been warned about, if not). */
599 static int mips_frame_reg_valid
= 0;
601 /* To output NOP instructions correctly, we need to keep information
602 about the previous two instructions. */
604 /* Whether we are optimizing. The default value of 2 means to remove
605 unneeded NOPs and swap branch instructions when possible. A value
606 of 1 means to not swap branches. A value of 0 means to always
608 static int mips_optimize
= 2;
610 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
611 equivalent to seeing no -g option at all. */
612 static int mips_debug
= 0;
614 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
615 #define MAX_VR4130_NOPS 4
617 /* The maximum number of NOPs needed to fill delay slots. */
618 #define MAX_DELAY_NOPS 2
620 /* The maximum number of NOPs needed for any purpose. */
623 /* A list of previous instructions, with index 0 being the most recent.
624 We need to look back MAX_NOPS instructions when filling delay slots
625 or working around processor errata. We need to look back one
626 instruction further if we're thinking about using history[0] to
627 fill a branch delay slot. */
628 static struct mips_cl_insn history
[1 + MAX_NOPS
];
630 /* Nop instructions used by emit_nop. */
631 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
633 /* The appropriate nop for the current mode. */
634 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
636 /* If this is set, it points to a frag holding nop instructions which
637 were inserted before the start of a noreorder section. If those
638 nops turn out to be unnecessary, the size of the frag can be
640 static fragS
*prev_nop_frag
;
642 /* The number of nop instructions we created in prev_nop_frag. */
643 static int prev_nop_frag_holds
;
645 /* The number of nop instructions that we know we need in
647 static int prev_nop_frag_required
;
649 /* The number of instructions we've seen since prev_nop_frag. */
650 static int prev_nop_frag_since
;
652 /* For ECOFF and ELF, relocations against symbols are done in two
653 parts, with a HI relocation and a LO relocation. Each relocation
654 has only 16 bits of space to store an addend. This means that in
655 order for the linker to handle carries correctly, it must be able
656 to locate both the HI and the LO relocation. This means that the
657 relocations must appear in order in the relocation table.
659 In order to implement this, we keep track of each unmatched HI
660 relocation. We then sort them so that they immediately precede the
661 corresponding LO relocation. */
666 struct mips_hi_fixup
*next
;
669 /* The section this fixup is in. */
673 /* The list of unmatched HI relocs. */
675 static struct mips_hi_fixup
*mips_hi_fixup_list
;
677 /* The frag containing the last explicit relocation operator.
678 Null if explicit relocations have not been used. */
680 static fragS
*prev_reloc_op_frag
;
682 /* Map normal MIPS register numbers to mips16 register numbers. */
684 #define X ILLEGAL_REG
685 static const int mips32_to_16_reg_map
[] =
687 X
, X
, 2, 3, 4, 5, 6, 7,
688 X
, X
, X
, X
, X
, X
, X
, X
,
689 0, 1, X
, X
, X
, X
, X
, X
,
690 X
, X
, X
, X
, X
, X
, X
, X
694 /* Map mips16 register numbers to normal MIPS register numbers. */
696 static const unsigned int mips16_to_32_reg_map
[] =
698 16, 17, 2, 3, 4, 5, 6, 7
701 /* Classifies the kind of instructions we're interested in when
702 implementing -mfix-vr4120. */
703 enum fix_vr4120_class
{
710 NUM_FIX_VR4120_CLASSES
713 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
714 there must be at least one other instruction between an instruction
715 of type X and an instruction of type Y. */
716 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
718 /* True if -mfix-vr4120 is in force. */
719 static int mips_fix_vr4120
;
721 /* ...likewise -mfix-vr4130. */
722 static int mips_fix_vr4130
;
724 /* We don't relax branches by default, since this causes us to expand
725 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
726 fail to compute the offset before expanding the macro to the most
727 efficient expansion. */
729 static int mips_relax_branch
;
731 /* The expansion of many macros depends on the type of symbol that
732 they refer to. For example, when generating position-dependent code,
733 a macro that refers to a symbol may have two different expansions,
734 one which uses GP-relative addresses and one which uses absolute
735 addresses. When generating SVR4-style PIC, a macro may have
736 different expansions for local and global symbols.
738 We handle these situations by generating both sequences and putting
739 them in variant frags. In position-dependent code, the first sequence
740 will be the GP-relative one and the second sequence will be the
741 absolute one. In SVR4 PIC, the first sequence will be for global
742 symbols and the second will be for local symbols.
744 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
745 SECOND are the lengths of the two sequences in bytes. These fields
746 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
747 the subtype has the following flags:
750 Set if it has been decided that we should use the second
751 sequence instead of the first.
754 Set in the first variant frag if the macro's second implementation
755 is longer than its first. This refers to the macro as a whole,
756 not an individual relaxation.
759 Set in the first variant frag if the macro appeared in a .set nomacro
760 block and if one alternative requires a warning but the other does not.
763 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
766 The frag's "opcode" points to the first fixup for relaxable code.
768 Relaxable macros are generated using a sequence such as:
770 relax_start (SYMBOL);
771 ... generate first expansion ...
773 ... generate second expansion ...
776 The code and fixups for the unwanted alternative are discarded
777 by md_convert_frag. */
778 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
780 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
781 #define RELAX_SECOND(X) ((X) & 0xff)
782 #define RELAX_USE_SECOND 0x10000
783 #define RELAX_SECOND_LONGER 0x20000
784 #define RELAX_NOMACRO 0x40000
785 #define RELAX_DELAY_SLOT 0x80000
787 /* Branch without likely bit. If label is out of range, we turn:
789 beq reg1, reg2, label
799 with the following opcode replacements:
806 bltzal <-> bgezal (with jal label instead of j label)
808 Even though keeping the delay slot instruction in the delay slot of
809 the branch would be more efficient, it would be very tricky to do
810 correctly, because we'd have to introduce a variable frag *after*
811 the delay slot instruction, and expand that instead. Let's do it
812 the easy way for now, even if the branch-not-taken case now costs
813 one additional instruction. Out-of-range branches are not supposed
814 to be common, anyway.
816 Branch likely. If label is out of range, we turn:
818 beql reg1, reg2, label
819 delay slot (annulled if branch not taken)
828 delay slot (executed only if branch taken)
831 It would be possible to generate a shorter sequence by losing the
832 likely bit, generating something like:
837 delay slot (executed only if branch taken)
849 bltzall -> bgezal (with jal label instead of j label)
850 bgezall -> bltzal (ditto)
853 but it's not clear that it would actually improve performance. */
854 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
857 | ((toofar) ? 1 : 0) \
859 | ((likely) ? 4 : 0) \
860 | ((uncond) ? 8 : 0)))
861 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
862 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
863 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
864 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
865 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
867 /* For mips16 code, we use an entirely different form of relaxation.
868 mips16 supports two versions of most instructions which take
869 immediate values: a small one which takes some small value, and a
870 larger one which takes a 16 bit value. Since branches also follow
871 this pattern, relaxing these values is required.
873 We can assemble both mips16 and normal MIPS code in a single
874 object. Therefore, we need to support this type of relaxation at
875 the same time that we support the relaxation described above. We
876 use the high bit of the subtype field to distinguish these cases.
878 The information we store for this type of relaxation is the
879 argument code found in the opcode file for this relocation, whether
880 the user explicitly requested a small or extended form, and whether
881 the relocation is in a jump or jal delay slot. That tells us the
882 size of the value, and how it should be stored. We also store
883 whether the fragment is considered to be extended or not. We also
884 store whether this is known to be a branch to a different section,
885 whether we have tried to relax this frag yet, and whether we have
886 ever extended a PC relative fragment because of a shift count. */
887 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
890 | ((small) ? 0x100 : 0) \
891 | ((ext) ? 0x200 : 0) \
892 | ((dslot) ? 0x400 : 0) \
893 | ((jal_dslot) ? 0x800 : 0))
894 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
895 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
896 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
897 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
898 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
899 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
900 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
901 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
902 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
903 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
904 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
905 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
907 /* Is the given value a sign-extended 32-bit value? */
908 #define IS_SEXT_32BIT_NUM(x) \
909 (((x) &~ (offsetT) 0x7fffffff) == 0 \
910 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
912 /* Is the given value a sign-extended 16-bit value? */
913 #define IS_SEXT_16BIT_NUM(x) \
914 (((x) &~ (offsetT) 0x7fff) == 0 \
915 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
917 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
918 #define IS_ZEXT_32BIT_NUM(x) \
919 (((x) &~ (offsetT) 0xffffffff) == 0 \
920 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
922 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
923 VALUE << SHIFT. VALUE is evaluated exactly once. */
924 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
925 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
926 | (((VALUE) & (MASK)) << (SHIFT)))
928 /* Extract bits MASK << SHIFT from STRUCT and shift them right
930 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
931 (((STRUCT) >> (SHIFT)) & (MASK))
933 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
934 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
936 include/opcode/mips.h specifies operand fields using the macros
937 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
938 with "MIPS16OP" instead of "OP". */
939 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
940 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
941 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
942 INSERT_BITS ((INSN).insn_opcode, VALUE, \
943 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
945 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
946 #define EXTRACT_OPERAND(FIELD, INSN) \
947 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
948 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
949 EXTRACT_BITS ((INSN).insn_opcode, \
950 MIPS16OP_MASK_##FIELD, \
953 /* Global variables used when generating relaxable macros. See the
954 comment above RELAX_ENCODE for more details about how relaxation
957 /* 0 if we're not emitting a relaxable macro.
958 1 if we're emitting the first of the two relaxation alternatives.
959 2 if we're emitting the second alternative. */
962 /* The first relaxable fixup in the current frag. (In other words,
963 the first fixup that refers to relaxable code.) */
966 /* sizes[0] says how many bytes of the first alternative are stored in
967 the current frag. Likewise sizes[1] for the second alternative. */
968 unsigned int sizes
[2];
970 /* The symbol on which the choice of sequence depends. */
974 /* Global variables used to decide whether a macro needs a warning. */
976 /* True if the macro is in a branch delay slot. */
977 bfd_boolean delay_slot_p
;
979 /* For relaxable macros, sizes[0] is the length of the first alternative
980 in bytes and sizes[1] is the length of the second alternative.
981 For non-relaxable macros, both elements give the length of the
983 unsigned int sizes
[2];
985 /* The first variant frag for this macro. */
987 } mips_macro_warning
;
989 /* Prototypes for static functions. */
991 #define internalError() \
992 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
994 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
996 static void append_insn
997 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
998 static void mips_no_prev_insn (void);
999 static void mips16_macro_build
1000 (expressionS
*, const char *, const char *, va_list);
1001 static void load_register (int, expressionS
*, int);
1002 static void macro_start (void);
1003 static void macro_end (void);
1004 static void macro (struct mips_cl_insn
* ip
);
1005 static void mips16_macro (struct mips_cl_insn
* ip
);
1006 #ifdef LOSING_COMPILER
1007 static void macro2 (struct mips_cl_insn
* ip
);
1009 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1010 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1011 static void mips16_immed
1012 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1013 unsigned long *, bfd_boolean
*, unsigned short *);
1014 static size_t my_getSmallExpression
1015 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1016 static void my_getExpression (expressionS
*, char *);
1017 static void s_align (int);
1018 static void s_change_sec (int);
1019 static void s_change_section (int);
1020 static void s_cons (int);
1021 static void s_float_cons (int);
1022 static void s_mips_globl (int);
1023 static void s_option (int);
1024 static void s_mipsset (int);
1025 static void s_abicalls (int);
1026 static void s_cpload (int);
1027 static void s_cpsetup (int);
1028 static void s_cplocal (int);
1029 static void s_cprestore (int);
1030 static void s_cpreturn (int);
1031 static void s_dtprelword (int);
1032 static void s_dtpreldword (int);
1033 static void s_gpvalue (int);
1034 static void s_gpword (int);
1035 static void s_gpdword (int);
1036 static void s_cpadd (int);
1037 static void s_insn (int);
1038 static void md_obj_begin (void);
1039 static void md_obj_end (void);
1040 static void s_mips_ent (int);
1041 static void s_mips_end (int);
1042 static void s_mips_frame (int);
1043 static void s_mips_mask (int reg_type
);
1044 static void s_mips_stab (int);
1045 static void s_mips_weakext (int);
1046 static void s_mips_file (int);
1047 static void s_mips_loc (int);
1048 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1049 static int relaxed_branch_length (fragS
*, asection
*, int);
1050 static int validate_mips_insn (const struct mips_opcode
*);
1052 /* Table and functions used to map between CPU/ISA names, and
1053 ISA levels, and CPU numbers. */
1055 struct mips_cpu_info
1057 const char *name
; /* CPU or ISA name. */
1058 int flags
; /* ASEs available, or ISA flag. */
1059 int isa
; /* ISA level. */
1060 int cpu
; /* CPU number (default CPU if ISA). */
1063 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1064 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1065 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1066 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1067 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1068 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1069 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1071 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1072 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1073 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1077 The following pseudo-ops from the Kane and Heinrich MIPS book
1078 should be defined here, but are currently unsupported: .alias,
1079 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1081 The following pseudo-ops from the Kane and Heinrich MIPS book are
1082 specific to the type of debugging information being generated, and
1083 should be defined by the object format: .aent, .begin, .bend,
1084 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1087 The following pseudo-ops from the Kane and Heinrich MIPS book are
1088 not MIPS CPU specific, but are also not specific to the object file
1089 format. This file is probably the best place to define them, but
1090 they are not currently supported: .asm0, .endr, .lab, .struct. */
1092 static const pseudo_typeS mips_pseudo_table
[] =
1094 /* MIPS specific pseudo-ops. */
1095 {"option", s_option
, 0},
1096 {"set", s_mipsset
, 0},
1097 {"rdata", s_change_sec
, 'r'},
1098 {"sdata", s_change_sec
, 's'},
1099 {"livereg", s_ignore
, 0},
1100 {"abicalls", s_abicalls
, 0},
1101 {"cpload", s_cpload
, 0},
1102 {"cpsetup", s_cpsetup
, 0},
1103 {"cplocal", s_cplocal
, 0},
1104 {"cprestore", s_cprestore
, 0},
1105 {"cpreturn", s_cpreturn
, 0},
1106 {"dtprelword", s_dtprelword
, 0},
1107 {"dtpreldword", s_dtpreldword
, 0},
1108 {"gpvalue", s_gpvalue
, 0},
1109 {"gpword", s_gpword
, 0},
1110 {"gpdword", s_gpdword
, 0},
1111 {"cpadd", s_cpadd
, 0},
1112 {"insn", s_insn
, 0},
1114 /* Relatively generic pseudo-ops that happen to be used on MIPS
1116 {"asciiz", stringer
, 8 + 1},
1117 {"bss", s_change_sec
, 'b'},
1119 {"half", s_cons
, 1},
1120 {"dword", s_cons
, 3},
1121 {"weakext", s_mips_weakext
, 0},
1122 {"origin", s_org
, 0},
1123 {"repeat", s_rept
, 0},
1125 /* These pseudo-ops are defined in read.c, but must be overridden
1126 here for one reason or another. */
1127 {"align", s_align
, 0},
1128 {"byte", s_cons
, 0},
1129 {"data", s_change_sec
, 'd'},
1130 {"double", s_float_cons
, 'd'},
1131 {"float", s_float_cons
, 'f'},
1132 {"globl", s_mips_globl
, 0},
1133 {"global", s_mips_globl
, 0},
1134 {"hword", s_cons
, 1},
1136 {"long", s_cons
, 2},
1137 {"octa", s_cons
, 4},
1138 {"quad", s_cons
, 3},
1139 {"section", s_change_section
, 0},
1140 {"short", s_cons
, 1},
1141 {"single", s_float_cons
, 'f'},
1142 {"stabn", s_mips_stab
, 'n'},
1143 {"text", s_change_sec
, 't'},
1144 {"word", s_cons
, 2},
1146 { "extern", ecoff_directive_extern
, 0},
1151 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1153 /* These pseudo-ops should be defined by the object file format.
1154 However, a.out doesn't support them, so we have versions here. */
1155 {"aent", s_mips_ent
, 1},
1156 {"bgnb", s_ignore
, 0},
1157 {"end", s_mips_end
, 0},
1158 {"endb", s_ignore
, 0},
1159 {"ent", s_mips_ent
, 0},
1160 {"file", s_mips_file
, 0},
1161 {"fmask", s_mips_mask
, 'F'},
1162 {"frame", s_mips_frame
, 0},
1163 {"loc", s_mips_loc
, 0},
1164 {"mask", s_mips_mask
, 'R'},
1165 {"verstamp", s_ignore
, 0},
1169 extern void pop_insert (const pseudo_typeS
*);
1172 mips_pop_insert (void)
1174 pop_insert (mips_pseudo_table
);
1175 if (! ECOFF_DEBUGGING
)
1176 pop_insert (mips_nonecoff_pseudo_table
);
1179 /* Symbols labelling the current insn. */
1181 struct insn_label_list
1183 struct insn_label_list
*next
;
1187 static struct insn_label_list
*free_insn_labels
;
1188 #define label_list tc_segment_info_data.labels
1190 static void mips_clear_insn_labels (void);
1193 mips_clear_insn_labels (void)
1195 register struct insn_label_list
**pl
;
1196 segment_info_type
*si
;
1200 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1203 si
= seg_info (now_seg
);
1204 *pl
= si
->label_list
;
1205 si
->label_list
= NULL
;
1210 static char *expr_end
;
1212 /* Expressions which appear in instructions. These are set by
1215 static expressionS imm_expr
;
1216 static expressionS imm2_expr
;
1217 static expressionS offset_expr
;
1219 /* Relocs associated with imm_expr and offset_expr. */
1221 static bfd_reloc_code_real_type imm_reloc
[3]
1222 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1223 static bfd_reloc_code_real_type offset_reloc
[3]
1224 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1226 /* These are set by mips16_ip if an explicit extension is used. */
1228 static bfd_boolean mips16_small
, mips16_ext
;
1231 /* The pdr segment for per procedure frame/regmask info. Not used for
1234 static segT pdr_seg
;
1237 /* The default target format to use. */
1240 mips_target_format (void)
1242 switch (OUTPUT_FLAVOR
)
1244 case bfd_target_ecoff_flavour
:
1245 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1246 case bfd_target_coff_flavour
:
1248 case bfd_target_elf_flavour
:
1250 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1251 return (target_big_endian
1252 ? "elf32-bigmips-vxworks"
1253 : "elf32-littlemips-vxworks");
1256 /* This is traditional mips. */
1257 return (target_big_endian
1258 ? (HAVE_64BIT_OBJECTS
1259 ? "elf64-tradbigmips"
1261 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1262 : (HAVE_64BIT_OBJECTS
1263 ? "elf64-tradlittlemips"
1265 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1267 return (target_big_endian
1268 ? (HAVE_64BIT_OBJECTS
1271 ? "elf32-nbigmips" : "elf32-bigmips"))
1272 : (HAVE_64BIT_OBJECTS
1273 ? "elf64-littlemips"
1275 ? "elf32-nlittlemips" : "elf32-littlemips")));
1283 /* Return the length of instruction INSN. */
1285 static inline unsigned int
1286 insn_length (const struct mips_cl_insn
*insn
)
1288 if (!mips_opts
.mips16
)
1290 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1293 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1296 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1301 insn
->use_extend
= FALSE
;
1303 insn
->insn_opcode
= mo
->match
;
1306 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1307 insn
->fixp
[i
] = NULL
;
1308 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1309 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1310 insn
->mips16_absolute_jump_p
= 0;
1313 /* Record the current MIPS16 mode in now_seg. */
1316 mips_record_mips16_mode (void)
1318 segment_info_type
*si
;
1320 si
= seg_info (now_seg
);
1321 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1322 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1325 /* Install INSN at the location specified by its "frag" and "where" fields. */
1328 install_insn (const struct mips_cl_insn
*insn
)
1330 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1331 if (!mips_opts
.mips16
)
1332 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1333 else if (insn
->mips16_absolute_jump_p
)
1335 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1336 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1340 if (insn
->use_extend
)
1342 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1345 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1347 mips_record_mips16_mode ();
1350 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1351 and install the opcode in the new location. */
1354 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1359 insn
->where
= where
;
1360 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1361 if (insn
->fixp
[i
] != NULL
)
1363 insn
->fixp
[i
]->fx_frag
= frag
;
1364 insn
->fixp
[i
]->fx_where
= where
;
1366 install_insn (insn
);
1369 /* Add INSN to the end of the output. */
1372 add_fixed_insn (struct mips_cl_insn
*insn
)
1374 char *f
= frag_more (insn_length (insn
));
1375 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1378 /* Start a variant frag and move INSN to the start of the variant part,
1379 marking it as fixed. The other arguments are as for frag_var. */
1382 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1383 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1385 frag_grow (max_chars
);
1386 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1388 frag_var (rs_machine_dependent
, max_chars
, var
,
1389 subtype
, symbol
, offset
, NULL
);
1392 /* Insert N copies of INSN into the history buffer, starting at
1393 position FIRST. Neither FIRST nor N need to be clipped. */
1396 insert_into_history (unsigned int first
, unsigned int n
,
1397 const struct mips_cl_insn
*insn
)
1399 if (mips_relax
.sequence
!= 2)
1403 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1405 history
[i
] = history
[i
- n
];
1411 /* Emit a nop instruction, recording it in the history buffer. */
1416 add_fixed_insn (NOP_INSN
);
1417 insert_into_history (0, 1, NOP_INSN
);
1420 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1421 the idea is to make it obvious at a glance that each errata is
1425 init_vr4120_conflicts (void)
1427 #define CONFLICT(FIRST, SECOND) \
1428 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1430 /* Errata 21 - [D]DIV[U] after [D]MACC */
1431 CONFLICT (MACC
, DIV
);
1432 CONFLICT (DMACC
, DIV
);
1434 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1435 CONFLICT (DMULT
, DMULT
);
1436 CONFLICT (DMULT
, DMACC
);
1437 CONFLICT (DMACC
, DMULT
);
1438 CONFLICT (DMACC
, DMACC
);
1440 /* Errata 24 - MT{LO,HI} after [D]MACC */
1441 CONFLICT (MACC
, MTHILO
);
1442 CONFLICT (DMACC
, MTHILO
);
1444 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1445 instruction is executed immediately after a MACC or DMACC
1446 instruction, the result of [either instruction] is incorrect." */
1447 CONFLICT (MACC
, MULT
);
1448 CONFLICT (MACC
, DMULT
);
1449 CONFLICT (DMACC
, MULT
);
1450 CONFLICT (DMACC
, DMULT
);
1452 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1453 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1454 DDIV or DDIVU instruction, the result of the MACC or
1455 DMACC instruction is incorrect.". */
1456 CONFLICT (DMULT
, MACC
);
1457 CONFLICT (DMULT
, DMACC
);
1458 CONFLICT (DIV
, MACC
);
1459 CONFLICT (DIV
, DMACC
);
1469 #define RTYPE_MASK 0x1ff00
1470 #define RTYPE_NUM 0x00100
1471 #define RTYPE_FPU 0x00200
1472 #define RTYPE_FCC 0x00400
1473 #define RTYPE_VEC 0x00800
1474 #define RTYPE_GP 0x01000
1475 #define RTYPE_CP0 0x02000
1476 #define RTYPE_PC 0x04000
1477 #define RTYPE_ACC 0x08000
1478 #define RTYPE_CCC 0x10000
1479 #define RNUM_MASK 0x000ff
1480 #define RWARN 0x80000
1482 #define GENERIC_REGISTER_NUMBERS \
1483 {"$0", RTYPE_NUM | 0}, \
1484 {"$1", RTYPE_NUM | 1}, \
1485 {"$2", RTYPE_NUM | 2}, \
1486 {"$3", RTYPE_NUM | 3}, \
1487 {"$4", RTYPE_NUM | 4}, \
1488 {"$5", RTYPE_NUM | 5}, \
1489 {"$6", RTYPE_NUM | 6}, \
1490 {"$7", RTYPE_NUM | 7}, \
1491 {"$8", RTYPE_NUM | 8}, \
1492 {"$9", RTYPE_NUM | 9}, \
1493 {"$10", RTYPE_NUM | 10}, \
1494 {"$11", RTYPE_NUM | 11}, \
1495 {"$12", RTYPE_NUM | 12}, \
1496 {"$13", RTYPE_NUM | 13}, \
1497 {"$14", RTYPE_NUM | 14}, \
1498 {"$15", RTYPE_NUM | 15}, \
1499 {"$16", RTYPE_NUM | 16}, \
1500 {"$17", RTYPE_NUM | 17}, \
1501 {"$18", RTYPE_NUM | 18}, \
1502 {"$19", RTYPE_NUM | 19}, \
1503 {"$20", RTYPE_NUM | 20}, \
1504 {"$21", RTYPE_NUM | 21}, \
1505 {"$22", RTYPE_NUM | 22}, \
1506 {"$23", RTYPE_NUM | 23}, \
1507 {"$24", RTYPE_NUM | 24}, \
1508 {"$25", RTYPE_NUM | 25}, \
1509 {"$26", RTYPE_NUM | 26}, \
1510 {"$27", RTYPE_NUM | 27}, \
1511 {"$28", RTYPE_NUM | 28}, \
1512 {"$29", RTYPE_NUM | 29}, \
1513 {"$30", RTYPE_NUM | 30}, \
1514 {"$31", RTYPE_NUM | 31}
1516 #define FPU_REGISTER_NAMES \
1517 {"$f0", RTYPE_FPU | 0}, \
1518 {"$f1", RTYPE_FPU | 1}, \
1519 {"$f2", RTYPE_FPU | 2}, \
1520 {"$f3", RTYPE_FPU | 3}, \
1521 {"$f4", RTYPE_FPU | 4}, \
1522 {"$f5", RTYPE_FPU | 5}, \
1523 {"$f6", RTYPE_FPU | 6}, \
1524 {"$f7", RTYPE_FPU | 7}, \
1525 {"$f8", RTYPE_FPU | 8}, \
1526 {"$f9", RTYPE_FPU | 9}, \
1527 {"$f10", RTYPE_FPU | 10}, \
1528 {"$f11", RTYPE_FPU | 11}, \
1529 {"$f12", RTYPE_FPU | 12}, \
1530 {"$f13", RTYPE_FPU | 13}, \
1531 {"$f14", RTYPE_FPU | 14}, \
1532 {"$f15", RTYPE_FPU | 15}, \
1533 {"$f16", RTYPE_FPU | 16}, \
1534 {"$f17", RTYPE_FPU | 17}, \
1535 {"$f18", RTYPE_FPU | 18}, \
1536 {"$f19", RTYPE_FPU | 19}, \
1537 {"$f20", RTYPE_FPU | 20}, \
1538 {"$f21", RTYPE_FPU | 21}, \
1539 {"$f22", RTYPE_FPU | 22}, \
1540 {"$f23", RTYPE_FPU | 23}, \
1541 {"$f24", RTYPE_FPU | 24}, \
1542 {"$f25", RTYPE_FPU | 25}, \
1543 {"$f26", RTYPE_FPU | 26}, \
1544 {"$f27", RTYPE_FPU | 27}, \
1545 {"$f28", RTYPE_FPU | 28}, \
1546 {"$f29", RTYPE_FPU | 29}, \
1547 {"$f30", RTYPE_FPU | 30}, \
1548 {"$f31", RTYPE_FPU | 31}
1550 #define FPU_CONDITION_CODE_NAMES \
1551 {"$fcc0", RTYPE_FCC | 0}, \
1552 {"$fcc1", RTYPE_FCC | 1}, \
1553 {"$fcc2", RTYPE_FCC | 2}, \
1554 {"$fcc3", RTYPE_FCC | 3}, \
1555 {"$fcc4", RTYPE_FCC | 4}, \
1556 {"$fcc5", RTYPE_FCC | 5}, \
1557 {"$fcc6", RTYPE_FCC | 6}, \
1558 {"$fcc7", RTYPE_FCC | 7}
1560 #define COPROC_CONDITION_CODE_NAMES \
1561 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1562 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1563 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1564 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1565 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1566 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1567 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1568 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1570 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1571 {"$a4", RTYPE_GP | 8}, \
1572 {"$a5", RTYPE_GP | 9}, \
1573 {"$a6", RTYPE_GP | 10}, \
1574 {"$a7", RTYPE_GP | 11}, \
1575 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1576 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1577 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1578 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1579 {"$t0", RTYPE_GP | 12}, \
1580 {"$t1", RTYPE_GP | 13}, \
1581 {"$t2", RTYPE_GP | 14}, \
1582 {"$t3", RTYPE_GP | 15}
1584 #define O32_SYMBOLIC_REGISTER_NAMES \
1585 {"$t0", RTYPE_GP | 8}, \
1586 {"$t1", RTYPE_GP | 9}, \
1587 {"$t2", RTYPE_GP | 10}, \
1588 {"$t3", RTYPE_GP | 11}, \
1589 {"$t4", RTYPE_GP | 12}, \
1590 {"$t5", RTYPE_GP | 13}, \
1591 {"$t6", RTYPE_GP | 14}, \
1592 {"$t7", RTYPE_GP | 15}, \
1593 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1594 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1595 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1596 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1598 /* Remaining symbolic register names */
1599 #define SYMBOLIC_REGISTER_NAMES \
1600 {"$zero", RTYPE_GP | 0}, \
1601 {"$at", RTYPE_GP | 1}, \
1602 {"$AT", RTYPE_GP | 1}, \
1603 {"$v0", RTYPE_GP | 2}, \
1604 {"$v1", RTYPE_GP | 3}, \
1605 {"$a0", RTYPE_GP | 4}, \
1606 {"$a1", RTYPE_GP | 5}, \
1607 {"$a2", RTYPE_GP | 6}, \
1608 {"$a3", RTYPE_GP | 7}, \
1609 {"$s0", RTYPE_GP | 16}, \
1610 {"$s1", RTYPE_GP | 17}, \
1611 {"$s2", RTYPE_GP | 18}, \
1612 {"$s3", RTYPE_GP | 19}, \
1613 {"$s4", RTYPE_GP | 20}, \
1614 {"$s5", RTYPE_GP | 21}, \
1615 {"$s6", RTYPE_GP | 22}, \
1616 {"$s7", RTYPE_GP | 23}, \
1617 {"$t8", RTYPE_GP | 24}, \
1618 {"$t9", RTYPE_GP | 25}, \
1619 {"$k0", RTYPE_GP | 26}, \
1620 {"$kt0", RTYPE_GP | 26}, \
1621 {"$k1", RTYPE_GP | 27}, \
1622 {"$kt1", RTYPE_GP | 27}, \
1623 {"$gp", RTYPE_GP | 28}, \
1624 {"$sp", RTYPE_GP | 29}, \
1625 {"$s8", RTYPE_GP | 30}, \
1626 {"$fp", RTYPE_GP | 30}, \
1627 {"$ra", RTYPE_GP | 31}
1629 #define MIPS16_SPECIAL_REGISTER_NAMES \
1630 {"$pc", RTYPE_PC | 0}
1632 #define MDMX_VECTOR_REGISTER_NAMES \
1633 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1634 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1635 {"$v2", RTYPE_VEC | 2}, \
1636 {"$v3", RTYPE_VEC | 3}, \
1637 {"$v4", RTYPE_VEC | 4}, \
1638 {"$v5", RTYPE_VEC | 5}, \
1639 {"$v6", RTYPE_VEC | 6}, \
1640 {"$v7", RTYPE_VEC | 7}, \
1641 {"$v8", RTYPE_VEC | 8}, \
1642 {"$v9", RTYPE_VEC | 9}, \
1643 {"$v10", RTYPE_VEC | 10}, \
1644 {"$v11", RTYPE_VEC | 11}, \
1645 {"$v12", RTYPE_VEC | 12}, \
1646 {"$v13", RTYPE_VEC | 13}, \
1647 {"$v14", RTYPE_VEC | 14}, \
1648 {"$v15", RTYPE_VEC | 15}, \
1649 {"$v16", RTYPE_VEC | 16}, \
1650 {"$v17", RTYPE_VEC | 17}, \
1651 {"$v18", RTYPE_VEC | 18}, \
1652 {"$v19", RTYPE_VEC | 19}, \
1653 {"$v20", RTYPE_VEC | 20}, \
1654 {"$v21", RTYPE_VEC | 21}, \
1655 {"$v22", RTYPE_VEC | 22}, \
1656 {"$v23", RTYPE_VEC | 23}, \
1657 {"$v24", RTYPE_VEC | 24}, \
1658 {"$v25", RTYPE_VEC | 25}, \
1659 {"$v26", RTYPE_VEC | 26}, \
1660 {"$v27", RTYPE_VEC | 27}, \
1661 {"$v28", RTYPE_VEC | 28}, \
1662 {"$v29", RTYPE_VEC | 29}, \
1663 {"$v30", RTYPE_VEC | 30}, \
1664 {"$v31", RTYPE_VEC | 31}
1666 #define MIPS_DSP_ACCUMULATOR_NAMES \
1667 {"$ac0", RTYPE_ACC | 0}, \
1668 {"$ac1", RTYPE_ACC | 1}, \
1669 {"$ac2", RTYPE_ACC | 2}, \
1670 {"$ac3", RTYPE_ACC | 3}
1672 static const struct regname reg_names
[] = {
1673 GENERIC_REGISTER_NUMBERS
,
1675 FPU_CONDITION_CODE_NAMES
,
1676 COPROC_CONDITION_CODE_NAMES
,
1678 /* The $txx registers depends on the abi,
1679 these will be added later into the symbol table from
1680 one of the tables below once mips_abi is set after
1681 parsing of arguments from the command line. */
1682 SYMBOLIC_REGISTER_NAMES
,
1684 MIPS16_SPECIAL_REGISTER_NAMES
,
1685 MDMX_VECTOR_REGISTER_NAMES
,
1686 MIPS_DSP_ACCUMULATOR_NAMES
,
1690 static const struct regname reg_names_o32
[] = {
1691 O32_SYMBOLIC_REGISTER_NAMES
,
1695 static const struct regname reg_names_n32n64
[] = {
1696 N32N64_SYMBOLIC_REGISTER_NAMES
,
1701 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1708 /* Find end of name. */
1710 if (is_name_beginner (*e
))
1712 while (is_part_of_name (*e
))
1715 /* Terminate name. */
1719 /* Look for a register symbol. */
1720 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1722 int r
= S_GET_VALUE (symbolP
);
1724 reg
= r
& RNUM_MASK
;
1725 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1726 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1727 reg
= (r
& RNUM_MASK
) - 2;
1729 /* Else see if this is a register defined in an itbl entry. */
1730 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1737 if (itbl_get_reg_val (n
, &r
))
1738 reg
= r
& RNUM_MASK
;
1741 /* Advance to next token if a register was recognised. */
1744 else if (types
& RWARN
)
1745 as_warn ("Unrecognized register name `%s'", *s
);
1753 /* This function is called once, at assembler startup time. It should set up
1754 all the tables, etc. that the MD part of the assembler will need. */
1759 const char *retval
= NULL
;
1763 if (mips_pic
!= NO_PIC
)
1765 if (g_switch_seen
&& g_switch_value
!= 0)
1766 as_bad (_("-G may not be used in position-independent code"));
1770 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1771 as_warn (_("Could not set architecture and machine"));
1773 op_hash
= hash_new ();
1775 for (i
= 0; i
< NUMOPCODES
;)
1777 const char *name
= mips_opcodes
[i
].name
;
1779 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1782 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1783 mips_opcodes
[i
].name
, retval
);
1784 /* Probably a memory allocation problem? Give up now. */
1785 as_fatal (_("Broken assembler. No assembly attempted."));
1789 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1791 if (!validate_mips_insn (&mips_opcodes
[i
]))
1793 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1795 create_insn (&nop_insn
, mips_opcodes
+ i
);
1796 nop_insn
.fixed_p
= 1;
1801 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1804 mips16_op_hash
= hash_new ();
1807 while (i
< bfd_mips16_num_opcodes
)
1809 const char *name
= mips16_opcodes
[i
].name
;
1811 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1813 as_fatal (_("internal: can't hash `%s': %s"),
1814 mips16_opcodes
[i
].name
, retval
);
1817 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1818 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1819 != mips16_opcodes
[i
].match
))
1821 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1822 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1825 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1827 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1828 mips16_nop_insn
.fixed_p
= 1;
1832 while (i
< bfd_mips16_num_opcodes
1833 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1837 as_fatal (_("Broken assembler. No assembly attempted."));
1839 /* We add all the general register names to the symbol table. This
1840 helps us detect invalid uses of them. */
1841 for (i
= 0; reg_names
[i
].name
; i
++)
1842 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1843 reg_names
[i
].num
, // & RNUM_MASK,
1844 &zero_address_frag
));
1846 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1847 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1848 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1849 &zero_address_frag
));
1851 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1852 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1853 reg_names_o32
[i
].num
, // & RNUM_MASK,
1854 &zero_address_frag
));
1856 mips_no_prev_insn ();
1859 mips_cprmask
[0] = 0;
1860 mips_cprmask
[1] = 0;
1861 mips_cprmask
[2] = 0;
1862 mips_cprmask
[3] = 0;
1864 /* set the default alignment for the text section (2**2) */
1865 record_alignment (text_section
, 2);
1867 bfd_set_gp_size (stdoutput
, g_switch_value
);
1872 /* On a native system other than VxWorks, sections must be aligned
1873 to 16 byte boundaries. When configured for an embedded ELF
1874 target, we don't bother. */
1875 if (strcmp (TARGET_OS
, "elf") != 0
1876 && strcmp (TARGET_OS
, "vxworks") != 0)
1878 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1879 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1880 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1883 /* Create a .reginfo section for register masks and a .mdebug
1884 section for debugging information. */
1892 subseg
= now_subseg
;
1894 /* The ABI says this section should be loaded so that the
1895 running program can access it. However, we don't load it
1896 if we are configured for an embedded target */
1897 flags
= SEC_READONLY
| SEC_DATA
;
1898 if (strcmp (TARGET_OS
, "elf") != 0)
1899 flags
|= SEC_ALLOC
| SEC_LOAD
;
1901 if (mips_abi
!= N64_ABI
)
1903 sec
= subseg_new (".reginfo", (subsegT
) 0);
1905 bfd_set_section_flags (stdoutput
, sec
, flags
);
1906 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1908 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1912 /* The 64-bit ABI uses a .MIPS.options section rather than
1913 .reginfo section. */
1914 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1915 bfd_set_section_flags (stdoutput
, sec
, flags
);
1916 bfd_set_section_alignment (stdoutput
, sec
, 3);
1918 /* Set up the option header. */
1920 Elf_Internal_Options opthdr
;
1923 opthdr
.kind
= ODK_REGINFO
;
1924 opthdr
.size
= (sizeof (Elf_External_Options
)
1925 + sizeof (Elf64_External_RegInfo
));
1928 f
= frag_more (sizeof (Elf_External_Options
));
1929 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1930 (Elf_External_Options
*) f
);
1932 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1936 if (ECOFF_DEBUGGING
)
1938 sec
= subseg_new (".mdebug", (subsegT
) 0);
1939 (void) bfd_set_section_flags (stdoutput
, sec
,
1940 SEC_HAS_CONTENTS
| SEC_READONLY
);
1941 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1943 else if (mips_flag_pdr
)
1945 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1946 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1947 SEC_READONLY
| SEC_RELOC
1949 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1952 subseg_set (seg
, subseg
);
1955 #endif /* OBJ_ELF */
1957 if (! ECOFF_DEBUGGING
)
1960 if (mips_fix_vr4120
)
1961 init_vr4120_conflicts ();
1967 if (! ECOFF_DEBUGGING
)
1972 md_assemble (char *str
)
1974 struct mips_cl_insn insn
;
1975 bfd_reloc_code_real_type unused_reloc
[3]
1976 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1978 imm_expr
.X_op
= O_absent
;
1979 imm2_expr
.X_op
= O_absent
;
1980 offset_expr
.X_op
= O_absent
;
1981 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1982 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1983 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1984 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1985 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1986 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1988 if (mips_opts
.mips16
)
1989 mips16_ip (str
, &insn
);
1992 mips_ip (str
, &insn
);
1993 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1994 str
, insn
.insn_opcode
));
1999 as_bad ("%s `%s'", insn_error
, str
);
2003 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2006 if (mips_opts
.mips16
)
2007 mips16_macro (&insn
);
2014 if (imm_expr
.X_op
!= O_absent
)
2015 append_insn (&insn
, &imm_expr
, imm_reloc
);
2016 else if (offset_expr
.X_op
!= O_absent
)
2017 append_insn (&insn
, &offset_expr
, offset_reloc
);
2019 append_insn (&insn
, NULL
, unused_reloc
);
2023 /* Return true if the given relocation might need a matching %lo().
2024 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2025 need a matching %lo() when applied to local symbols. */
2027 static inline bfd_boolean
2028 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2030 return (HAVE_IN_PLACE_ADDENDS
2031 && (reloc
== BFD_RELOC_HI16_S
2032 || reloc
== BFD_RELOC_MIPS16_HI16_S
2033 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2034 all GOT16 relocations evaluate to "G". */
2035 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
2038 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2041 static inline bfd_boolean
2042 fixup_has_matching_lo_p (fixS
*fixp
)
2044 return (fixp
->fx_next
!= NULL
2045 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2046 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2047 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2048 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2051 /* See whether instruction IP reads register REG. CLASS is the type
2055 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2056 enum mips_regclass
class)
2058 if (class == MIPS16_REG
)
2060 assert (mips_opts
.mips16
);
2061 reg
= mips16_to_32_reg_map
[reg
];
2062 class = MIPS_GR_REG
;
2065 /* Don't report on general register ZERO, since it never changes. */
2066 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2069 if (class == MIPS_FP_REG
)
2071 assert (! mips_opts
.mips16
);
2072 /* If we are called with either $f0 or $f1, we must check $f0.
2073 This is not optimal, because it will introduce an unnecessary
2074 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2075 need to distinguish reading both $f0 and $f1 or just one of
2076 them. Note that we don't have to check the other way,
2077 because there is no instruction that sets both $f0 and $f1
2078 and requires a delay. */
2079 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2080 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2081 == (reg
&~ (unsigned) 1)))
2083 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2084 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2085 == (reg
&~ (unsigned) 1)))
2088 else if (! mips_opts
.mips16
)
2090 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2091 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2093 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2094 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2099 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2100 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2102 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2103 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2105 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2106 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2109 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2111 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2113 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2115 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2116 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2123 /* This function returns true if modifying a register requires a
2127 reg_needs_delay (unsigned int reg
)
2129 unsigned long prev_pinfo
;
2131 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2132 if (! mips_opts
.noreorder
2133 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2134 && ! gpr_interlocks
)
2135 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2136 && ! cop_interlocks
)))
2138 /* A load from a coprocessor or from memory. All load delays
2139 delay the use of general register rt for one instruction. */
2140 /* Itbl support may require additional care here. */
2141 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2142 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2149 /* Move all labels in insn_labels to the current insertion point. */
2152 mips_move_labels (void)
2154 segment_info_type
*si
= seg_info (now_seg
);
2155 struct insn_label_list
*l
;
2158 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2160 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2161 symbol_set_frag (l
->label
, frag_now
);
2162 val
= (valueT
) frag_now_fix ();
2163 /* mips16 text labels are stored as odd. */
2164 if (mips_opts
.mips16
)
2166 S_SET_VALUE (l
->label
, val
);
2171 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2173 bfd_boolean linkonce
= FALSE
;
2174 segT symseg
= S_GET_SEGMENT (sym
);
2176 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2178 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2181 /* The GNU toolchain uses an extension for ELF: a section
2182 beginning with the magic string .gnu.linkonce is a
2183 linkonce section. */
2184 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2185 sizeof ".gnu.linkonce" - 1) == 0)
2192 /* Mark instruction labels in mips16 mode. This permits the linker to
2193 handle them specially, such as generating jalx instructions when
2194 needed. We also make them odd for the duration of the assembly, in
2195 order to generate the right sort of code. We will make them even
2196 in the adjust_symtab routine, while leaving them marked. This is
2197 convenient for the debugger and the disassembler. The linker knows
2198 to make them odd again. */
2201 mips16_mark_labels (void)
2203 segment_info_type
*si
= seg_info (now_seg
);
2204 struct insn_label_list
*l
;
2206 if (!mips_opts
.mips16
)
2209 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2211 symbolS
*label
= l
->label
;
2213 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2215 S_SET_OTHER (label
, STO_MIPS16
);
2217 if ((S_GET_VALUE (label
) & 1) == 0
2218 /* Don't adjust the address if the label is global or weak, or
2219 in a link-once section, since we'll be emitting symbol reloc
2220 references to it which will be patched up by the linker, and
2221 the final value of the symbol may or may not be MIPS16. */
2222 && ! S_IS_WEAK (label
)
2223 && ! S_IS_EXTERNAL (label
)
2224 && ! s_is_linkonce (label
, now_seg
))
2225 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2229 /* End the current frag. Make it a variant frag and record the
2233 relax_close_frag (void)
2235 mips_macro_warning
.first_frag
= frag_now
;
2236 frag_var (rs_machine_dependent
, 0, 0,
2237 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2238 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2240 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2241 mips_relax
.first_fixup
= 0;
2244 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2245 See the comment above RELAX_ENCODE for more details. */
2248 relax_start (symbolS
*symbol
)
2250 assert (mips_relax
.sequence
== 0);
2251 mips_relax
.sequence
= 1;
2252 mips_relax
.symbol
= symbol
;
2255 /* Start generating the second version of a relaxable sequence.
2256 See the comment above RELAX_ENCODE for more details. */
2261 assert (mips_relax
.sequence
== 1);
2262 mips_relax
.sequence
= 2;
2265 /* End the current relaxable sequence. */
2270 assert (mips_relax
.sequence
== 2);
2271 relax_close_frag ();
2272 mips_relax
.sequence
= 0;
2275 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2276 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2277 by VR4120 errata. */
2280 classify_vr4120_insn (const char *name
)
2282 if (strncmp (name
, "macc", 4) == 0)
2283 return FIX_VR4120_MACC
;
2284 if (strncmp (name
, "dmacc", 5) == 0)
2285 return FIX_VR4120_DMACC
;
2286 if (strncmp (name
, "mult", 4) == 0)
2287 return FIX_VR4120_MULT
;
2288 if (strncmp (name
, "dmult", 5) == 0)
2289 return FIX_VR4120_DMULT
;
2290 if (strstr (name
, "div"))
2291 return FIX_VR4120_DIV
;
2292 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2293 return FIX_VR4120_MTHILO
;
2294 return NUM_FIX_VR4120_CLASSES
;
2297 /* Return the number of instructions that must separate INSN1 and INSN2,
2298 where INSN1 is the earlier instruction. Return the worst-case value
2299 for any INSN2 if INSN2 is null. */
2302 insns_between (const struct mips_cl_insn
*insn1
,
2303 const struct mips_cl_insn
*insn2
)
2305 unsigned long pinfo1
, pinfo2
;
2307 /* This function needs to know which pinfo flags are set for INSN2
2308 and which registers INSN2 uses. The former is stored in PINFO2 and
2309 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2310 will have every flag set and INSN2_USES_REG will always return true. */
2311 pinfo1
= insn1
->insn_mo
->pinfo
;
2312 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2314 #define INSN2_USES_REG(REG, CLASS) \
2315 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2317 /* For most targets, write-after-read dependencies on the HI and LO
2318 registers must be separated by at least two instructions. */
2319 if (!hilo_interlocks
)
2321 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2323 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2327 /* If we're working around r7000 errata, there must be two instructions
2328 between an mfhi or mflo and any instruction that uses the result. */
2329 if (mips_7000_hilo_fix
2330 && MF_HILO_INSN (pinfo1
)
2331 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2334 /* If working around VR4120 errata, check for combinations that need
2335 a single intervening instruction. */
2336 if (mips_fix_vr4120
)
2338 unsigned int class1
, class2
;
2340 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2341 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2345 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2346 if (vr4120_conflicts
[class1
] & (1 << class2
))
2351 if (!mips_opts
.mips16
)
2353 /* Check for GPR or coprocessor load delays. All such delays
2354 are on the RT register. */
2355 /* Itbl support may require additional care here. */
2356 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2357 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2359 know (pinfo1
& INSN_WRITE_GPR_T
);
2360 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2364 /* Check for generic coprocessor hazards.
2366 This case is not handled very well. There is no special
2367 knowledge of CP0 handling, and the coprocessors other than
2368 the floating point unit are not distinguished at all. */
2369 /* Itbl support may require additional care here. FIXME!
2370 Need to modify this to include knowledge about
2371 user specified delays! */
2372 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2373 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2375 /* Handle cases where INSN1 writes to a known general coprocessor
2376 register. There must be a one instruction delay before INSN2
2377 if INSN2 reads that register, otherwise no delay is needed. */
2378 if (pinfo1
& INSN_WRITE_FPR_T
)
2380 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2383 else if (pinfo1
& INSN_WRITE_FPR_S
)
2385 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2390 /* Read-after-write dependencies on the control registers
2391 require a two-instruction gap. */
2392 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2393 && (pinfo2
& INSN_READ_COND_CODE
))
2396 /* We don't know exactly what INSN1 does. If INSN2 is
2397 also a coprocessor instruction, assume there must be
2398 a one instruction gap. */
2399 if (pinfo2
& INSN_COP
)
2404 /* Check for read-after-write dependencies on the coprocessor
2405 control registers in cases where INSN1 does not need a general
2406 coprocessor delay. This means that INSN1 is a floating point
2407 comparison instruction. */
2408 /* Itbl support may require additional care here. */
2409 else if (!cop_interlocks
2410 && (pinfo1
& INSN_WRITE_COND_CODE
)
2411 && (pinfo2
& INSN_READ_COND_CODE
))
2415 #undef INSN2_USES_REG
2420 /* Return the number of nops that would be needed to work around the
2421 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2422 the MAX_VR4130_NOPS instructions described by HISTORY. */
2425 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2426 const struct mips_cl_insn
*insn
)
2430 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2431 are not affected by the errata. */
2433 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2434 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2435 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2438 /* Search for the first MFLO or MFHI. */
2439 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2440 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2442 /* Extract the destination register. */
2443 if (mips_opts
.mips16
)
2444 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2446 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2448 /* No nops are needed if INSN reads that register. */
2449 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2452 /* ...or if any of the intervening instructions do. */
2453 for (j
= 0; j
< i
; j
++)
2454 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2457 return MAX_VR4130_NOPS
- i
;
2462 /* Return the number of nops that would be needed if instruction INSN
2463 immediately followed the MAX_NOPS instructions given by HISTORY,
2464 where HISTORY[0] is the most recent instruction. If INSN is null,
2465 return the worse-case number of nops for any instruction. */
2468 nops_for_insn (const struct mips_cl_insn
*history
,
2469 const struct mips_cl_insn
*insn
)
2471 int i
, nops
, tmp_nops
;
2474 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2475 if (!history
[i
].noreorder_p
)
2477 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2478 if (tmp_nops
> nops
)
2482 if (mips_fix_vr4130
)
2484 tmp_nops
= nops_for_vr4130 (history
, insn
);
2485 if (tmp_nops
> nops
)
2492 /* The variable arguments provide NUM_INSNS extra instructions that
2493 might be added to HISTORY. Return the largest number of nops that
2494 would be needed after the extended sequence. */
2497 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2500 struct mips_cl_insn buffer
[MAX_NOPS
];
2501 struct mips_cl_insn
*cursor
;
2504 va_start (args
, history
);
2505 cursor
= buffer
+ num_insns
;
2506 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2507 while (cursor
> buffer
)
2508 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2510 nops
= nops_for_insn (buffer
, NULL
);
2515 /* Like nops_for_insn, but if INSN is a branch, take into account the
2516 worst-case delay for the branch target. */
2519 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2520 const struct mips_cl_insn
*insn
)
2524 nops
= nops_for_insn (history
, insn
);
2525 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2526 | INSN_COND_BRANCH_DELAY
2527 | INSN_COND_BRANCH_LIKELY
))
2529 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2530 if (tmp_nops
> nops
)
2533 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2535 tmp_nops
= nops_for_sequence (1, history
, insn
);
2536 if (tmp_nops
> nops
)
2542 /* Output an instruction. IP is the instruction information.
2543 ADDRESS_EXPR is an operand of the instruction to be used with
2547 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2548 bfd_reloc_code_real_type
*reloc_type
)
2550 unsigned long prev_pinfo
, pinfo
;
2551 relax_stateT prev_insn_frag_type
= 0;
2552 bfd_boolean relaxed_branch
= FALSE
;
2553 segment_info_type
*si
= seg_info (now_seg
);
2555 /* Mark instruction labels in mips16 mode. */
2556 mips16_mark_labels ();
2558 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2559 pinfo
= ip
->insn_mo
->pinfo
;
2561 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2563 /* There are a lot of optimizations we could do that we don't.
2564 In particular, we do not, in general, reorder instructions.
2565 If you use gcc with optimization, it will reorder
2566 instructions and generally do much more optimization then we
2567 do here; repeating all that work in the assembler would only
2568 benefit hand written assembly code, and does not seem worth
2570 int nops
= (mips_optimize
== 0
2571 ? nops_for_insn (history
, NULL
)
2572 : nops_for_insn_or_target (history
, ip
));
2576 unsigned long old_frag_offset
;
2579 old_frag
= frag_now
;
2580 old_frag_offset
= frag_now_fix ();
2582 for (i
= 0; i
< nops
; i
++)
2587 listing_prev_line ();
2588 /* We may be at the start of a variant frag. In case we
2589 are, make sure there is enough space for the frag
2590 after the frags created by listing_prev_line. The
2591 argument to frag_grow here must be at least as large
2592 as the argument to all other calls to frag_grow in
2593 this file. We don't have to worry about being in the
2594 middle of a variant frag, because the variants insert
2595 all needed nop instructions themselves. */
2599 mips_move_labels ();
2601 #ifndef NO_ECOFF_DEBUGGING
2602 if (ECOFF_DEBUGGING
)
2603 ecoff_fix_loc (old_frag
, old_frag_offset
);
2607 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2609 /* Work out how many nops in prev_nop_frag are needed by IP. */
2610 int nops
= nops_for_insn_or_target (history
, ip
);
2611 assert (nops
<= prev_nop_frag_holds
);
2613 /* Enforce NOPS as a minimum. */
2614 if (nops
> prev_nop_frag_required
)
2615 prev_nop_frag_required
= nops
;
2617 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2619 /* Settle for the current number of nops. Update the history
2620 accordingly (for the benefit of any future .set reorder code). */
2621 prev_nop_frag
= NULL
;
2622 insert_into_history (prev_nop_frag_since
,
2623 prev_nop_frag_holds
, NOP_INSN
);
2627 /* Allow this instruction to replace one of the nops that was
2628 tentatively added to prev_nop_frag. */
2629 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2630 prev_nop_frag_holds
--;
2631 prev_nop_frag_since
++;
2636 /* The value passed to dwarf2_emit_insn is the distance between
2637 the beginning of the current instruction and the address that
2638 should be recorded in the debug tables. For MIPS16 debug info
2639 we want to use ISA-encoded addresses, so we pass -1 for an
2640 address higher by one than the current. */
2641 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2644 /* Record the frag type before frag_var. */
2645 if (history
[0].frag
)
2646 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2649 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2650 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2651 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2652 && mips_relax_branch
2653 /* Don't try branch relaxation within .set nomacro, or within
2654 .set noat if we use $at for PIC computations. If it turns
2655 out that the branch was out-of-range, we'll get an error. */
2656 && !mips_opts
.warn_about_macros
2657 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2658 && !mips_opts
.mips16
)
2660 relaxed_branch
= TRUE
;
2661 add_relaxed_insn (ip
, (relaxed_branch_length
2663 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2664 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2667 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2668 pinfo
& INSN_COND_BRANCH_LIKELY
,
2669 pinfo
& INSN_WRITE_GPR_31
,
2671 address_expr
->X_add_symbol
,
2672 address_expr
->X_add_number
);
2673 *reloc_type
= BFD_RELOC_UNUSED
;
2675 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2677 /* We need to set up a variant frag. */
2678 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2679 add_relaxed_insn (ip
, 4, 0,
2681 (*reloc_type
- BFD_RELOC_UNUSED
,
2682 mips16_small
, mips16_ext
,
2683 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2684 history
[0].mips16_absolute_jump_p
),
2685 make_expr_symbol (address_expr
), 0);
2687 else if (mips_opts
.mips16
2689 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2691 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2692 /* Make sure there is enough room to swap this instruction with
2693 a following jump instruction. */
2695 add_fixed_insn (ip
);
2699 if (mips_opts
.mips16
2700 && mips_opts
.noreorder
2701 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2702 as_warn (_("extended instruction in delay slot"));
2704 if (mips_relax
.sequence
)
2706 /* If we've reached the end of this frag, turn it into a variant
2707 frag and record the information for the instructions we've
2709 if (frag_room () < 4)
2710 relax_close_frag ();
2711 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2714 if (mips_relax
.sequence
!= 2)
2715 mips_macro_warning
.sizes
[0] += 4;
2716 if (mips_relax
.sequence
!= 1)
2717 mips_macro_warning
.sizes
[1] += 4;
2719 if (mips_opts
.mips16
)
2722 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2724 add_fixed_insn (ip
);
2727 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2729 if (address_expr
->X_op
== O_constant
)
2733 switch (*reloc_type
)
2736 ip
->insn_opcode
|= address_expr
->X_add_number
;
2739 case BFD_RELOC_MIPS_HIGHEST
:
2740 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2741 ip
->insn_opcode
|= tmp
& 0xffff;
2744 case BFD_RELOC_MIPS_HIGHER
:
2745 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2746 ip
->insn_opcode
|= tmp
& 0xffff;
2749 case BFD_RELOC_HI16_S
:
2750 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2751 ip
->insn_opcode
|= tmp
& 0xffff;
2754 case BFD_RELOC_HI16
:
2755 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2758 case BFD_RELOC_UNUSED
:
2759 case BFD_RELOC_LO16
:
2760 case BFD_RELOC_MIPS_GOT_DISP
:
2761 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2764 case BFD_RELOC_MIPS_JMP
:
2765 if ((address_expr
->X_add_number
& 3) != 0)
2766 as_bad (_("jump to misaligned address (0x%lx)"),
2767 (unsigned long) address_expr
->X_add_number
);
2768 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2771 case BFD_RELOC_MIPS16_JMP
:
2772 if ((address_expr
->X_add_number
& 3) != 0)
2773 as_bad (_("jump to misaligned address (0x%lx)"),
2774 (unsigned long) address_expr
->X_add_number
);
2776 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2777 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2778 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2781 case BFD_RELOC_16_PCREL_S2
:
2782 if ((address_expr
->X_add_number
& 3) != 0)
2783 as_bad (_("branch to misaligned address (0x%lx)"),
2784 (unsigned long) address_expr
->X_add_number
);
2785 if (mips_relax_branch
)
2787 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2788 as_bad (_("branch address range overflow (0x%lx)"),
2789 (unsigned long) address_expr
->X_add_number
);
2790 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2797 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2800 reloc_howto_type
*howto
;
2803 /* In a compound relocation, it is the final (outermost)
2804 operator that determines the relocated field. */
2805 for (i
= 1; i
< 3; i
++)
2806 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2809 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2810 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2811 bfd_get_reloc_size (howto
),
2813 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2816 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2817 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2818 && ip
->fixp
[0]->fx_addsy
)
2819 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2821 /* These relocations can have an addend that won't fit in
2822 4 octets for 64bit assembly. */
2824 && ! howto
->partial_inplace
2825 && (reloc_type
[0] == BFD_RELOC_16
2826 || reloc_type
[0] == BFD_RELOC_32
2827 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2828 || reloc_type
[0] == BFD_RELOC_HI16_S
2829 || reloc_type
[0] == BFD_RELOC_LO16
2830 || reloc_type
[0] == BFD_RELOC_GPREL16
2831 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2832 || reloc_type
[0] == BFD_RELOC_GPREL32
2833 || reloc_type
[0] == BFD_RELOC_64
2834 || reloc_type
[0] == BFD_RELOC_CTOR
2835 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2836 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2837 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2838 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2839 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2840 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2841 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2842 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2843 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2844 ip
->fixp
[0]->fx_no_overflow
= 1;
2846 if (mips_relax
.sequence
)
2848 if (mips_relax
.first_fixup
== 0)
2849 mips_relax
.first_fixup
= ip
->fixp
[0];
2851 else if (reloc_needs_lo_p (*reloc_type
))
2853 struct mips_hi_fixup
*hi_fixup
;
2855 /* Reuse the last entry if it already has a matching %lo. */
2856 hi_fixup
= mips_hi_fixup_list
;
2858 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2860 hi_fixup
= ((struct mips_hi_fixup
*)
2861 xmalloc (sizeof (struct mips_hi_fixup
)));
2862 hi_fixup
->next
= mips_hi_fixup_list
;
2863 mips_hi_fixup_list
= hi_fixup
;
2865 hi_fixup
->fixp
= ip
->fixp
[0];
2866 hi_fixup
->seg
= now_seg
;
2869 /* Add fixups for the second and third relocations, if given.
2870 Note that the ABI allows the second relocation to be
2871 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2872 moment we only use RSS_UNDEF, but we could add support
2873 for the others if it ever becomes necessary. */
2874 for (i
= 1; i
< 3; i
++)
2875 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2877 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2878 ip
->fixp
[0]->fx_size
, NULL
, 0,
2879 FALSE
, reloc_type
[i
]);
2881 /* Use fx_tcbit to mark compound relocs. */
2882 ip
->fixp
[0]->fx_tcbit
= 1;
2883 ip
->fixp
[i
]->fx_tcbit
= 1;
2889 /* Update the register mask information. */
2890 if (! mips_opts
.mips16
)
2892 if (pinfo
& INSN_WRITE_GPR_D
)
2893 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2894 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2895 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2896 if (pinfo
& INSN_READ_GPR_S
)
2897 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2898 if (pinfo
& INSN_WRITE_GPR_31
)
2899 mips_gprmask
|= 1 << RA
;
2900 if (pinfo
& INSN_WRITE_FPR_D
)
2901 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2902 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2903 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2904 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2905 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2906 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2907 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2908 if (pinfo
& INSN_COP
)
2910 /* We don't keep enough information to sort these cases out.
2911 The itbl support does keep this information however, although
2912 we currently don't support itbl fprmats as part of the cop
2913 instruction. May want to add this support in the future. */
2915 /* Never set the bit for $0, which is always zero. */
2916 mips_gprmask
&= ~1 << 0;
2920 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2921 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2922 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2923 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2924 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2925 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2926 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2927 mips_gprmask
|= 1 << TREG
;
2928 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2929 mips_gprmask
|= 1 << SP
;
2930 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2931 mips_gprmask
|= 1 << RA
;
2932 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2933 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2934 if (pinfo
& MIPS16_INSN_READ_Z
)
2935 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2936 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2937 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2940 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2942 /* Filling the branch delay slot is more complex. We try to
2943 switch the branch with the previous instruction, which we can
2944 do if the previous instruction does not set up a condition
2945 that the branch tests and if the branch is not itself the
2946 target of any branch. */
2947 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2948 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2950 if (mips_optimize
< 2
2951 /* If we have seen .set volatile or .set nomove, don't
2953 || mips_opts
.nomove
!= 0
2954 /* We can't swap if the previous instruction's position
2956 || history
[0].fixed_p
2957 /* If the previous previous insn was in a .set
2958 noreorder, we can't swap. Actually, the MIPS
2959 assembler will swap in this situation. However, gcc
2960 configured -with-gnu-as will generate code like
2966 in which we can not swap the bne and INSN. If gcc is
2967 not configured -with-gnu-as, it does not output the
2969 || history
[1].noreorder_p
2970 /* If the branch is itself the target of a branch, we
2971 can not swap. We cheat on this; all we check for is
2972 whether there is a label on this instruction. If
2973 there are any branches to anything other than a
2974 label, users must use .set noreorder. */
2975 || si
->label_list
!= NULL
2976 /* If the previous instruction is in a variant frag
2977 other than this branch's one, we cannot do the swap.
2978 This does not apply to the mips16, which uses variant
2979 frags for different purposes. */
2980 || (! mips_opts
.mips16
2981 && prev_insn_frag_type
== rs_machine_dependent
)
2982 /* Check for conflicts between the branch and the instructions
2983 before the candidate delay slot. */
2984 || nops_for_insn (history
+ 1, ip
) > 0
2985 /* Check for conflicts between the swapped sequence and the
2986 target of the branch. */
2987 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2988 /* We do not swap with a trap instruction, since it
2989 complicates trap handlers to have the trap
2990 instruction be in a delay slot. */
2991 || (prev_pinfo
& INSN_TRAP
)
2992 /* If the branch reads a register that the previous
2993 instruction sets, we can not swap. */
2994 || (! mips_opts
.mips16
2995 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2996 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2998 || (! mips_opts
.mips16
2999 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3000 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3002 || (mips_opts
.mips16
3003 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3005 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3007 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3009 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3011 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3013 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3015 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3016 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3017 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3018 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3019 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3020 && insn_uses_reg (ip
,
3021 MIPS16OP_EXTRACT_REG32R
3022 (history
[0].insn_opcode
),
3024 /* If the branch writes a register that the previous
3025 instruction sets, we can not swap (we know that
3026 branches write only to RD or to $31). */
3027 || (! mips_opts
.mips16
3028 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3029 && (((pinfo
& INSN_WRITE_GPR_D
)
3030 && (EXTRACT_OPERAND (RT
, history
[0])
3031 == EXTRACT_OPERAND (RD
, *ip
)))
3032 || ((pinfo
& INSN_WRITE_GPR_31
)
3033 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3034 || (! mips_opts
.mips16
3035 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3036 && (((pinfo
& INSN_WRITE_GPR_D
)
3037 && (EXTRACT_OPERAND (RD
, history
[0])
3038 == EXTRACT_OPERAND (RD
, *ip
)))
3039 || ((pinfo
& INSN_WRITE_GPR_31
)
3040 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3041 || (mips_opts
.mips16
3042 && (pinfo
& MIPS16_INSN_WRITE_31
)
3043 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3044 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3045 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3047 /* If the branch writes a register that the previous
3048 instruction reads, we can not swap (we know that
3049 branches only write to RD or to $31). */
3050 || (! mips_opts
.mips16
3051 && (pinfo
& INSN_WRITE_GPR_D
)
3052 && insn_uses_reg (&history
[0],
3053 EXTRACT_OPERAND (RD
, *ip
),
3055 || (! mips_opts
.mips16
3056 && (pinfo
& INSN_WRITE_GPR_31
)
3057 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3058 || (mips_opts
.mips16
3059 && (pinfo
& MIPS16_INSN_WRITE_31
)
3060 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3061 /* If one instruction sets a condition code and the
3062 other one uses a condition code, we can not swap. */
3063 || ((pinfo
& INSN_READ_COND_CODE
)
3064 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3065 || ((pinfo
& INSN_WRITE_COND_CODE
)
3066 && (prev_pinfo
& INSN_READ_COND_CODE
))
3067 /* If the previous instruction uses the PC, we can not
3069 || (mips_opts
.mips16
3070 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3071 /* If the previous instruction had a fixup in mips16
3072 mode, we can not swap. This normally means that the
3073 previous instruction was a 4 byte branch anyhow. */
3074 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3075 /* If the previous instruction is a sync, sync.l, or
3076 sync.p, we can not swap. */
3077 || (prev_pinfo
& INSN_SYNC
))
3079 if (mips_opts
.mips16
3080 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3081 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3082 && ISA_SUPPORTS_MIPS16E
)
3084 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3085 ip
->insn_opcode
|= 0x0080;
3087 insert_into_history (0, 1, ip
);
3091 /* We could do even better for unconditional branches to
3092 portions of this object file; we could pick up the
3093 instruction at the destination, put it in the delay
3094 slot, and bump the destination address. */
3095 insert_into_history (0, 1, ip
);
3099 if (mips_relax
.sequence
)
3100 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3104 /* It looks like we can actually do the swap. */
3105 struct mips_cl_insn delay
= history
[0];
3106 if (mips_opts
.mips16
)
3108 know (delay
.frag
== ip
->frag
);
3109 move_insn (ip
, delay
.frag
, delay
.where
);
3110 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3112 else if (relaxed_branch
)
3114 /* Add the delay slot instruction to the end of the
3115 current frag and shrink the fixed part of the
3116 original frag. If the branch occupies the tail of
3117 the latter, move it backwards to cover the gap. */
3118 delay
.frag
->fr_fix
-= 4;
3119 if (delay
.frag
== ip
->frag
)
3120 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3121 add_fixed_insn (&delay
);
3125 move_insn (&delay
, ip
->frag
, ip
->where
);
3126 move_insn (ip
, history
[0].frag
, history
[0].where
);
3130 insert_into_history (0, 1, &delay
);
3133 /* If that was an unconditional branch, forget the previous
3134 insn information. */
3135 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3136 mips_no_prev_insn ();
3138 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3140 /* We don't yet optimize a branch likely. What we should do
3141 is look at the target, copy the instruction found there
3142 into the delay slot, and increment the branch to jump to
3143 the next instruction. */
3144 insert_into_history (0, 1, ip
);
3148 insert_into_history (0, 1, ip
);
3151 insert_into_history (0, 1, ip
);
3153 /* We just output an insn, so the next one doesn't have a label. */
3154 mips_clear_insn_labels ();
3157 /* Forget that there was any previous instruction or label. */
3160 mips_no_prev_insn (void)
3162 prev_nop_frag
= NULL
;
3163 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3164 mips_clear_insn_labels ();
3167 /* This function must be called before we emit something other than
3168 instructions. It is like mips_no_prev_insn except that it inserts
3169 any NOPS that might be needed by previous instructions. */
3172 mips_emit_delays (void)
3174 if (! mips_opts
.noreorder
)
3176 int nops
= nops_for_insn (history
, NULL
);
3180 add_fixed_insn (NOP_INSN
);
3181 mips_move_labels ();
3184 mips_no_prev_insn ();
3187 /* Start a (possibly nested) noreorder block. */
3190 start_noreorder (void)
3192 if (mips_opts
.noreorder
== 0)
3197 /* None of the instructions before the .set noreorder can be moved. */
3198 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3199 history
[i
].fixed_p
= 1;
3201 /* Insert any nops that might be needed between the .set noreorder
3202 block and the previous instructions. We will later remove any
3203 nops that turn out not to be needed. */
3204 nops
= nops_for_insn (history
, NULL
);
3207 if (mips_optimize
!= 0)
3209 /* Record the frag which holds the nop instructions, so
3210 that we can remove them if we don't need them. */
3211 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3212 prev_nop_frag
= frag_now
;
3213 prev_nop_frag_holds
= nops
;
3214 prev_nop_frag_required
= 0;
3215 prev_nop_frag_since
= 0;
3218 for (; nops
> 0; --nops
)
3219 add_fixed_insn (NOP_INSN
);
3221 /* Move on to a new frag, so that it is safe to simply
3222 decrease the size of prev_nop_frag. */
3223 frag_wane (frag_now
);
3225 mips_move_labels ();
3227 mips16_mark_labels ();
3228 mips_clear_insn_labels ();
3230 mips_opts
.noreorder
++;
3231 mips_any_noreorder
= 1;
3234 /* End a nested noreorder block. */
3237 end_noreorder (void)
3239 mips_opts
.noreorder
--;
3240 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3242 /* Commit to inserting prev_nop_frag_required nops and go back to
3243 handling nop insertion the .set reorder way. */
3244 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3245 * (mips_opts
.mips16
? 2 : 4));
3246 insert_into_history (prev_nop_frag_since
,
3247 prev_nop_frag_required
, NOP_INSN
);
3248 prev_nop_frag
= NULL
;
3252 /* Set up global variables for the start of a new macro. */
3257 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3258 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3259 && (history
[0].insn_mo
->pinfo
3260 & (INSN_UNCOND_BRANCH_DELAY
3261 | INSN_COND_BRANCH_DELAY
3262 | INSN_COND_BRANCH_LIKELY
)) != 0);
3265 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3266 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3267 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3270 macro_warning (relax_substateT subtype
)
3272 if (subtype
& RELAX_DELAY_SLOT
)
3273 return _("Macro instruction expanded into multiple instructions"
3274 " in a branch delay slot");
3275 else if (subtype
& RELAX_NOMACRO
)
3276 return _("Macro instruction expanded into multiple instructions");
3281 /* Finish up a macro. Emit warnings as appropriate. */
3286 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3288 relax_substateT subtype
;
3290 /* Set up the relaxation warning flags. */
3292 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3293 subtype
|= RELAX_SECOND_LONGER
;
3294 if (mips_opts
.warn_about_macros
)
3295 subtype
|= RELAX_NOMACRO
;
3296 if (mips_macro_warning
.delay_slot_p
)
3297 subtype
|= RELAX_DELAY_SLOT
;
3299 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3301 /* Either the macro has a single implementation or both
3302 implementations are longer than 4 bytes. Emit the
3304 const char *msg
= macro_warning (subtype
);
3310 /* One implementation might need a warning but the other
3311 definitely doesn't. */
3312 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3317 /* Read a macro's relocation codes from *ARGS and store them in *R.
3318 The first argument in *ARGS will be either the code for a single
3319 relocation or -1 followed by the three codes that make up a
3320 composite relocation. */
3323 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3327 next
= va_arg (*args
, int);
3329 r
[0] = (bfd_reloc_code_real_type
) next
;
3331 for (i
= 0; i
< 3; i
++)
3332 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3335 /* Build an instruction created by a macro expansion. This is passed
3336 a pointer to the count of instructions created so far, an
3337 expression, the name of the instruction to build, an operand format
3338 string, and corresponding arguments. */
3341 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3343 const struct mips_opcode
*mo
;
3344 struct mips_cl_insn insn
;
3345 bfd_reloc_code_real_type r
[3];
3348 va_start (args
, fmt
);
3350 if (mips_opts
.mips16
)
3352 mips16_macro_build (ep
, name
, fmt
, args
);
3357 r
[0] = BFD_RELOC_UNUSED
;
3358 r
[1] = BFD_RELOC_UNUSED
;
3359 r
[2] = BFD_RELOC_UNUSED
;
3360 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3362 assert (strcmp (name
, mo
->name
) == 0);
3366 /* Search until we get a match for NAME. It is assumed here that
3367 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3368 if (strcmp (fmt
, mo
->args
) == 0
3369 && mo
->pinfo
!= INSN_MACRO
3370 && OPCODE_IS_MEMBER (mo
,
3372 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3373 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
3374 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
3376 | (mips_opts
.ase_dspr2
? INSN_DSPR2
: 0)
3377 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3379 && (mips_opts
.arch
!= CPU_R4650
|| (mo
->pinfo
& FP_D
) == 0))
3384 assert (strcmp (name
, mo
->name
) == 0);
3387 create_insn (&insn
, mo
);
3405 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3410 /* Note that in the macro case, these arguments are already
3411 in MSB form. (When handling the instruction in the
3412 non-macro case, these arguments are sizes from which
3413 MSB values must be calculated.) */
3414 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3420 /* Note that in the macro case, these arguments are already
3421 in MSBD form. (When handling the instruction in the
3422 non-macro case, these arguments are sizes from which
3423 MSBD values must be calculated.) */
3424 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3433 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3439 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3443 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3448 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3454 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3459 int tmp
= va_arg (args
, int);
3461 INSERT_OPERAND (RT
, insn
, tmp
);
3462 INSERT_OPERAND (RD
, insn
, tmp
);
3468 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3475 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3479 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3483 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3487 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3491 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3498 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3504 macro_read_relocs (&args
, r
);
3505 assert (*r
== BFD_RELOC_GPREL16
3506 || *r
== BFD_RELOC_MIPS_LITERAL
3507 || *r
== BFD_RELOC_MIPS_HIGHER
3508 || *r
== BFD_RELOC_HI16_S
3509 || *r
== BFD_RELOC_LO16
3510 || *r
== BFD_RELOC_MIPS_GOT16
3511 || *r
== BFD_RELOC_MIPS_CALL16
3512 || *r
== BFD_RELOC_MIPS_GOT_DISP
3513 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3514 || *r
== BFD_RELOC_MIPS_GOT_OFST
3515 || *r
== BFD_RELOC_MIPS_GOT_LO16
3516 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3520 macro_read_relocs (&args
, r
);
3522 && (ep
->X_op
== O_constant
3523 || (ep
->X_op
== O_symbol
3524 && (*r
== BFD_RELOC_MIPS_HIGHEST
3525 || *r
== BFD_RELOC_HI16_S
3526 || *r
== BFD_RELOC_HI16
3527 || *r
== BFD_RELOC_GPREL16
3528 || *r
== BFD_RELOC_MIPS_GOT_HI16
3529 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3533 assert (ep
!= NULL
);
3536 * This allows macro() to pass an immediate expression for
3537 * creating short branches without creating a symbol.
3539 * We don't allow branch relaxation for these branches, as
3540 * they should only appear in ".set nomacro" anyway.
3542 if (ep
->X_op
== O_constant
)
3544 if ((ep
->X_add_number
& 3) != 0)
3545 as_bad (_("branch to misaligned address (0x%lx)"),
3546 (unsigned long) ep
->X_add_number
);
3547 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3548 as_bad (_("branch address range overflow (0x%lx)"),
3549 (unsigned long) ep
->X_add_number
);
3550 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3554 *r
= BFD_RELOC_16_PCREL_S2
;
3558 assert (ep
!= NULL
);
3559 *r
= BFD_RELOC_MIPS_JMP
;
3563 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3567 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3576 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3578 append_insn (&insn
, ep
, r
);
3582 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3585 struct mips_opcode
*mo
;
3586 struct mips_cl_insn insn
;
3587 bfd_reloc_code_real_type r
[3]
3588 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3590 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3592 assert (strcmp (name
, mo
->name
) == 0);
3594 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3598 assert (strcmp (name
, mo
->name
) == 0);
3601 create_insn (&insn
, mo
);
3619 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3624 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3628 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3632 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3642 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3649 regno
= va_arg (args
, int);
3650 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3651 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3672 assert (ep
!= NULL
);
3674 if (ep
->X_op
!= O_constant
)
3675 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3678 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3679 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3682 *r
= BFD_RELOC_UNUSED
;
3688 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3695 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3697 append_insn (&insn
, ep
, r
);
3701 * Sign-extend 32-bit mode constants that have bit 31 set and all
3702 * higher bits unset.
3705 normalize_constant_expr (expressionS
*ex
)
3707 if (ex
->X_op
== O_constant
3708 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3709 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3714 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3715 * all higher bits unset.
3718 normalize_address_expr (expressionS
*ex
)
3720 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3721 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3722 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3723 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3728 * Generate a "jalr" instruction with a relocation hint to the called
3729 * function. This occurs in NewABI PIC code.
3732 macro_build_jalr (expressionS
*ep
)
3741 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3743 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3744 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3748 * Generate a "lui" instruction.
3751 macro_build_lui (expressionS
*ep
, int regnum
)
3753 expressionS high_expr
;
3754 const struct mips_opcode
*mo
;
3755 struct mips_cl_insn insn
;
3756 bfd_reloc_code_real_type r
[3]
3757 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3758 const char *name
= "lui";
3759 const char *fmt
= "t,u";
3761 assert (! mips_opts
.mips16
);
3765 if (high_expr
.X_op
== O_constant
)
3767 /* We can compute the instruction now without a relocation entry. */
3768 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3770 *r
= BFD_RELOC_UNUSED
;
3774 assert (ep
->X_op
== O_symbol
);
3775 /* _gp_disp is a special case, used from s_cpload.
3776 __gnu_local_gp is used if mips_no_shared. */
3777 assert (mips_pic
== NO_PIC
3779 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3780 || (! mips_in_shared
3781 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3782 "__gnu_local_gp") == 0));
3783 *r
= BFD_RELOC_HI16_S
;
3786 mo
= hash_find (op_hash
, name
);
3787 assert (strcmp (name
, mo
->name
) == 0);
3788 assert (strcmp (fmt
, mo
->args
) == 0);
3789 create_insn (&insn
, mo
);
3791 insn
.insn_opcode
= insn
.insn_mo
->match
;
3792 INSERT_OPERAND (RT
, insn
, regnum
);
3793 if (*r
== BFD_RELOC_UNUSED
)
3795 insn
.insn_opcode
|= high_expr
.X_add_number
;
3796 append_insn (&insn
, NULL
, r
);
3799 append_insn (&insn
, &high_expr
, r
);
3802 /* Generate a sequence of instructions to do a load or store from a constant
3803 offset off of a base register (breg) into/from a target register (treg),
3804 using AT if necessary. */
3806 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3807 int treg
, int breg
, int dbl
)
3809 assert (ep
->X_op
== O_constant
);
3811 /* Sign-extending 32-bit constants makes their handling easier. */
3813 normalize_constant_expr (ep
);
3815 /* Right now, this routine can only handle signed 32-bit constants. */
3816 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3817 as_warn (_("operand overflow"));
3819 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3821 /* Signed 16-bit offset will fit in the op. Easy! */
3822 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3826 /* 32-bit offset, need multiple instructions and AT, like:
3827 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3828 addu $tempreg,$tempreg,$breg
3829 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3830 to handle the complete offset. */
3831 macro_build_lui (ep
, AT
);
3832 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3833 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3836 as_bad (_("Macro used $at after \".set noat\""));
3841 * Generates code to set the $at register to true (one)
3842 * if reg is less than the immediate expression.
3845 set_at (int reg
, int unsignedp
)
3847 if (imm_expr
.X_op
== O_constant
3848 && imm_expr
.X_add_number
>= -0x8000
3849 && imm_expr
.X_add_number
< 0x8000)
3850 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3851 AT
, reg
, BFD_RELOC_LO16
);
3854 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3855 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3859 /* Warn if an expression is not a constant. */
3862 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3864 if (ex
->X_op
== O_big
)
3865 as_bad (_("unsupported large constant"));
3866 else if (ex
->X_op
!= O_constant
)
3867 as_bad (_("Instruction %s requires absolute expression"),
3870 if (HAVE_32BIT_GPRS
)
3871 normalize_constant_expr (ex
);
3874 /* Count the leading zeroes by performing a binary chop. This is a
3875 bulky bit of source, but performance is a LOT better for the
3876 majority of values than a simple loop to count the bits:
3877 for (lcnt = 0; (lcnt < 32); lcnt++)
3878 if ((v) & (1 << (31 - lcnt)))
3880 However it is not code size friendly, and the gain will drop a bit
3881 on certain cached systems.
3883 #define COUNT_TOP_ZEROES(v) \
3884 (((v) & ~0xffff) == 0 \
3885 ? ((v) & ~0xff) == 0 \
3886 ? ((v) & ~0xf) == 0 \
3887 ? ((v) & ~0x3) == 0 \
3888 ? ((v) & ~0x1) == 0 \
3893 : ((v) & ~0x7) == 0 \
3896 : ((v) & ~0x3f) == 0 \
3897 ? ((v) & ~0x1f) == 0 \
3900 : ((v) & ~0x7f) == 0 \
3903 : ((v) & ~0xfff) == 0 \
3904 ? ((v) & ~0x3ff) == 0 \
3905 ? ((v) & ~0x1ff) == 0 \
3908 : ((v) & ~0x7ff) == 0 \
3911 : ((v) & ~0x3fff) == 0 \
3912 ? ((v) & ~0x1fff) == 0 \
3915 : ((v) & ~0x7fff) == 0 \
3918 : ((v) & ~0xffffff) == 0 \
3919 ? ((v) & ~0xfffff) == 0 \
3920 ? ((v) & ~0x3ffff) == 0 \
3921 ? ((v) & ~0x1ffff) == 0 \
3924 : ((v) & ~0x7ffff) == 0 \
3927 : ((v) & ~0x3fffff) == 0 \
3928 ? ((v) & ~0x1fffff) == 0 \
3931 : ((v) & ~0x7fffff) == 0 \
3934 : ((v) & ~0xfffffff) == 0 \
3935 ? ((v) & ~0x3ffffff) == 0 \
3936 ? ((v) & ~0x1ffffff) == 0 \
3939 : ((v) & ~0x7ffffff) == 0 \
3942 : ((v) & ~0x3fffffff) == 0 \
3943 ? ((v) & ~0x1fffffff) == 0 \
3946 : ((v) & ~0x7fffffff) == 0 \
3951 * This routine generates the least number of instructions necessary to load
3952 * an absolute expression value into a register.
3955 load_register (int reg
, expressionS
*ep
, int dbl
)
3958 expressionS hi32
, lo32
;
3960 if (ep
->X_op
!= O_big
)
3962 assert (ep
->X_op
== O_constant
);
3964 /* Sign-extending 32-bit constants makes their handling easier. */
3966 normalize_constant_expr (ep
);
3968 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3970 /* We can handle 16 bit signed values with an addiu to
3971 $zero. No need to ever use daddiu here, since $zero and
3972 the result are always correct in 32 bit mode. */
3973 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3976 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3978 /* We can handle 16 bit unsigned values with an ori to
3980 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3983 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3985 /* 32 bit values require an lui. */
3986 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3987 if ((ep
->X_add_number
& 0xffff) != 0)
3988 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3993 /* The value is larger than 32 bits. */
3995 if (!dbl
|| HAVE_32BIT_GPRS
)
3999 sprintf_vma (value
, ep
->X_add_number
);
4000 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4001 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4005 if (ep
->X_op
!= O_big
)
4008 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4009 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4010 hi32
.X_add_number
&= 0xffffffff;
4012 lo32
.X_add_number
&= 0xffffffff;
4016 assert (ep
->X_add_number
> 2);
4017 if (ep
->X_add_number
== 3)
4018 generic_bignum
[3] = 0;
4019 else if (ep
->X_add_number
> 4)
4020 as_bad (_("Number larger than 64 bits"));
4021 lo32
.X_op
= O_constant
;
4022 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4023 hi32
.X_op
= O_constant
;
4024 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4027 if (hi32
.X_add_number
== 0)
4032 unsigned long hi
, lo
;
4034 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4036 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4038 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4041 if (lo32
.X_add_number
& 0x80000000)
4043 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4044 if (lo32
.X_add_number
& 0xffff)
4045 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4050 /* Check for 16bit shifted constant. We know that hi32 is
4051 non-zero, so start the mask on the first bit of the hi32
4056 unsigned long himask
, lomask
;
4060 himask
= 0xffff >> (32 - shift
);
4061 lomask
= (0xffff << shift
) & 0xffffffff;
4065 himask
= 0xffff << (shift
- 32);
4068 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4069 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4073 tmp
.X_op
= O_constant
;
4075 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4076 | (lo32
.X_add_number
>> shift
));
4078 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4079 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4080 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4081 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4086 while (shift
<= (64 - 16));
4088 /* Find the bit number of the lowest one bit, and store the
4089 shifted value in hi/lo. */
4090 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4091 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4095 while ((lo
& 1) == 0)
4100 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4106 while ((hi
& 1) == 0)
4115 /* Optimize if the shifted value is a (power of 2) - 1. */
4116 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4117 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4119 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4124 /* This instruction will set the register to be all
4126 tmp
.X_op
= O_constant
;
4127 tmp
.X_add_number
= (offsetT
) -1;
4128 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4132 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4133 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4135 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4136 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4141 /* Sign extend hi32 before calling load_register, because we can
4142 generally get better code when we load a sign extended value. */
4143 if ((hi32
.X_add_number
& 0x80000000) != 0)
4144 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4145 load_register (reg
, &hi32
, 0);
4148 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4152 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4160 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4162 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4163 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4169 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4173 mid16
.X_add_number
>>= 16;
4174 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4175 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4178 if ((lo32
.X_add_number
& 0xffff) != 0)
4179 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4183 load_delay_nop (void)
4185 if (!gpr_interlocks
)
4186 macro_build (NULL
, "nop", "");
4189 /* Load an address into a register. */
4192 load_address (int reg
, expressionS
*ep
, int *used_at
)
4194 if (ep
->X_op
!= O_constant
4195 && ep
->X_op
!= O_symbol
)
4197 as_bad (_("expression too complex"));
4198 ep
->X_op
= O_constant
;
4201 if (ep
->X_op
== O_constant
)
4203 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4207 if (mips_pic
== NO_PIC
)
4209 /* If this is a reference to a GP relative symbol, we want
4210 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4212 lui $reg,<sym> (BFD_RELOC_HI16_S)
4213 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4214 If we have an addend, we always use the latter form.
4216 With 64bit address space and a usable $at we want
4217 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4218 lui $at,<sym> (BFD_RELOC_HI16_S)
4219 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4220 daddiu $at,<sym> (BFD_RELOC_LO16)
4224 If $at is already in use, we use a path which is suboptimal
4225 on superscalar processors.
4226 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4227 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4229 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4231 daddiu $reg,<sym> (BFD_RELOC_LO16)
4233 For GP relative symbols in 64bit address space we can use
4234 the same sequence as in 32bit address space. */
4235 if (HAVE_64BIT_SYMBOLS
)
4237 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4238 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4240 relax_start (ep
->X_add_symbol
);
4241 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4242 mips_gp_register
, BFD_RELOC_GPREL16
);
4246 if (*used_at
== 0 && mips_opts
.at
)
4248 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4249 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4250 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4251 BFD_RELOC_MIPS_HIGHER
);
4252 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4253 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4254 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4259 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4260 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4261 BFD_RELOC_MIPS_HIGHER
);
4262 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4263 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4264 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4265 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4268 if (mips_relax
.sequence
)
4273 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4274 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4276 relax_start (ep
->X_add_symbol
);
4277 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4278 mips_gp_register
, BFD_RELOC_GPREL16
);
4281 macro_build_lui (ep
, reg
);
4282 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4283 reg
, reg
, BFD_RELOC_LO16
);
4284 if (mips_relax
.sequence
)
4288 else if (!mips_big_got
)
4292 /* If this is a reference to an external symbol, we want
4293 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4295 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4297 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4298 If there is a constant, it must be added in after.
4300 If we have NewABI, we want
4301 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4302 unless we're referencing a global symbol with a non-zero
4303 offset, in which case cst must be added separately. */
4306 if (ep
->X_add_number
)
4308 ex
.X_add_number
= ep
->X_add_number
;
4309 ep
->X_add_number
= 0;
4310 relax_start (ep
->X_add_symbol
);
4311 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4312 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4313 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4314 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4315 ex
.X_op
= O_constant
;
4316 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4317 reg
, reg
, BFD_RELOC_LO16
);
4318 ep
->X_add_number
= ex
.X_add_number
;
4321 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4322 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4323 if (mips_relax
.sequence
)
4328 ex
.X_add_number
= ep
->X_add_number
;
4329 ep
->X_add_number
= 0;
4330 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4331 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4333 relax_start (ep
->X_add_symbol
);
4335 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4339 if (ex
.X_add_number
!= 0)
4341 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4342 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4343 ex
.X_op
= O_constant
;
4344 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4345 reg
, reg
, BFD_RELOC_LO16
);
4349 else if (mips_big_got
)
4353 /* This is the large GOT case. If this is a reference to an
4354 external symbol, we want
4355 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4357 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4359 Otherwise, for a reference to a local symbol in old ABI, we want
4360 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4362 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4363 If there is a constant, it must be added in after.
4365 In the NewABI, for local symbols, with or without offsets, we want:
4366 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4367 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4371 ex
.X_add_number
= ep
->X_add_number
;
4372 ep
->X_add_number
= 0;
4373 relax_start (ep
->X_add_symbol
);
4374 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4376 reg
, reg
, mips_gp_register
);
4377 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4378 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4379 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4380 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4381 else if (ex
.X_add_number
)
4383 ex
.X_op
= O_constant
;
4384 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4388 ep
->X_add_number
= ex
.X_add_number
;
4390 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4391 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4392 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4393 BFD_RELOC_MIPS_GOT_OFST
);
4398 ex
.X_add_number
= ep
->X_add_number
;
4399 ep
->X_add_number
= 0;
4400 relax_start (ep
->X_add_symbol
);
4401 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4403 reg
, reg
, mips_gp_register
);
4404 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4405 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4407 if (reg_needs_delay (mips_gp_register
))
4409 /* We need a nop before loading from $gp. This special
4410 check is required because the lui which starts the main
4411 instruction stream does not refer to $gp, and so will not
4412 insert the nop which may be required. */
4413 macro_build (NULL
, "nop", "");
4415 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4416 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4418 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4422 if (ex
.X_add_number
!= 0)
4424 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4425 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4426 ex
.X_op
= O_constant
;
4427 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4435 if (!mips_opts
.at
&& *used_at
== 1)
4436 as_bad (_("Macro used $at after \".set noat\""));
4439 /* Move the contents of register SOURCE into register DEST. */
4442 move_register (int dest
, int source
)
4444 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4448 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4449 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4450 The two alternatives are:
4452 Global symbol Local sybmol
4453 ------------- ------------
4454 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4456 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4458 load_got_offset emits the first instruction and add_got_offset
4459 emits the second for a 16-bit offset or add_got_offset_hilo emits
4460 a sequence to add a 32-bit offset using a scratch register. */
4463 load_got_offset (int dest
, expressionS
*local
)
4468 global
.X_add_number
= 0;
4470 relax_start (local
->X_add_symbol
);
4471 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4472 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4474 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4475 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4480 add_got_offset (int dest
, expressionS
*local
)
4484 global
.X_op
= O_constant
;
4485 global
.X_op_symbol
= NULL
;
4486 global
.X_add_symbol
= NULL
;
4487 global
.X_add_number
= local
->X_add_number
;
4489 relax_start (local
->X_add_symbol
);
4490 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4491 dest
, dest
, BFD_RELOC_LO16
);
4493 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4498 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4501 int hold_mips_optimize
;
4503 global
.X_op
= O_constant
;
4504 global
.X_op_symbol
= NULL
;
4505 global
.X_add_symbol
= NULL
;
4506 global
.X_add_number
= local
->X_add_number
;
4508 relax_start (local
->X_add_symbol
);
4509 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4511 /* Set mips_optimize around the lui instruction to avoid
4512 inserting an unnecessary nop after the lw. */
4513 hold_mips_optimize
= mips_optimize
;
4515 macro_build_lui (&global
, tmp
);
4516 mips_optimize
= hold_mips_optimize
;
4517 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4520 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4525 * This routine implements the seemingly endless macro or synthesized
4526 * instructions and addressing modes in the mips assembly language. Many
4527 * of these macros are simple and are similar to each other. These could
4528 * probably be handled by some kind of table or grammar approach instead of
4529 * this verbose method. Others are not simple macros but are more like
4530 * optimizing code generation.
4531 * One interesting optimization is when several store macros appear
4532 * consecutively that would load AT with the upper half of the same address.
4533 * The ensuing load upper instructions are ommited. This implies some kind
4534 * of global optimization. We currently only optimize within a single macro.
4535 * For many of the load and store macros if the address is specified as a
4536 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4537 * first load register 'at' with zero and use it as the base register. The
4538 * mips assembler simply uses register $zero. Just one tiny optimization
4542 macro (struct mips_cl_insn
*ip
)
4544 unsigned int treg
, sreg
, dreg
, breg
;
4545 unsigned int tempreg
;
4560 bfd_reloc_code_real_type r
;
4561 int hold_mips_optimize
;
4563 assert (! mips_opts
.mips16
);
4565 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4566 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4567 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4568 mask
= ip
->insn_mo
->mask
;
4570 expr1
.X_op
= O_constant
;
4571 expr1
.X_op_symbol
= NULL
;
4572 expr1
.X_add_symbol
= NULL
;
4573 expr1
.X_add_number
= 1;
4587 expr1
.X_add_number
= 8;
4588 macro_build (&expr1
, "bgez", "s,p", sreg
);
4590 macro_build (NULL
, "nop", "", 0);
4592 move_register (dreg
, sreg
);
4593 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4616 if (imm_expr
.X_op
== O_constant
4617 && imm_expr
.X_add_number
>= -0x8000
4618 && imm_expr
.X_add_number
< 0x8000)
4620 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4624 load_register (AT
, &imm_expr
, dbl
);
4625 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4644 if (imm_expr
.X_op
== O_constant
4645 && imm_expr
.X_add_number
>= 0
4646 && imm_expr
.X_add_number
< 0x10000)
4648 if (mask
!= M_NOR_I
)
4649 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4652 macro_build (&imm_expr
, "ori", "t,r,i",
4653 treg
, sreg
, BFD_RELOC_LO16
);
4654 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4660 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4661 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4665 switch (imm_expr
.X_add_number
)
4668 macro_build (NULL
, "nop", "");
4671 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4674 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4675 (int)imm_expr
.X_add_number
);
4694 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4696 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4700 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4701 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4709 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4714 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4718 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4719 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4725 /* check for > max integer */
4726 maxnum
= 0x7fffffff;
4727 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4734 if (imm_expr
.X_op
== O_constant
4735 && imm_expr
.X_add_number
>= maxnum
4736 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4739 /* result is always false */
4741 macro_build (NULL
, "nop", "", 0);
4743 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4746 if (imm_expr
.X_op
!= O_constant
)
4747 as_bad (_("Unsupported large constant"));
4748 ++imm_expr
.X_add_number
;
4752 if (mask
== M_BGEL_I
)
4754 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4756 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4759 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4761 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4764 maxnum
= 0x7fffffff;
4765 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4772 maxnum
= - maxnum
- 1;
4773 if (imm_expr
.X_op
== O_constant
4774 && imm_expr
.X_add_number
<= maxnum
4775 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4778 /* result is always true */
4779 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4780 macro_build (&offset_expr
, "b", "p");
4785 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4795 macro_build (&offset_expr
, likely
? "beql" : "beq",
4800 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4801 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4809 && imm_expr
.X_op
== O_constant
4810 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4812 if (imm_expr
.X_op
!= O_constant
)
4813 as_bad (_("Unsupported large constant"));
4814 ++imm_expr
.X_add_number
;
4818 if (mask
== M_BGEUL_I
)
4820 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4822 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4824 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4830 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4838 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4843 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4847 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4848 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4856 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4863 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4864 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4872 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4877 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4881 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4882 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4888 maxnum
= 0x7fffffff;
4889 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4896 if (imm_expr
.X_op
== O_constant
4897 && imm_expr
.X_add_number
>= maxnum
4898 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4900 if (imm_expr
.X_op
!= O_constant
)
4901 as_bad (_("Unsupported large constant"));
4902 ++imm_expr
.X_add_number
;
4906 if (mask
== M_BLTL_I
)
4908 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4910 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4913 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4915 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4920 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4928 macro_build (&offset_expr
, likely
? "beql" : "beq",
4935 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4936 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4944 && imm_expr
.X_op
== O_constant
4945 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4947 if (imm_expr
.X_op
!= O_constant
)
4948 as_bad (_("Unsupported large constant"));
4949 ++imm_expr
.X_add_number
;
4953 if (mask
== M_BLTUL_I
)
4955 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4957 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4959 macro_build (&offset_expr
, likely
? "beql" : "beq",
4965 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4973 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4978 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4982 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4983 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4993 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4998 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4999 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5007 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5009 as_bad (_("Unsupported large constant"));
5014 pos
= (unsigned long) imm_expr
.X_add_number
;
5015 size
= (unsigned long) imm2_expr
.X_add_number
;
5020 as_bad (_("Improper position (%lu)"), pos
);
5023 if (size
== 0 || size
> 64
5024 || (pos
+ size
- 1) > 63)
5026 as_bad (_("Improper extract size (%lu, position %lu)"),
5031 if (size
<= 32 && pos
< 32)
5036 else if (size
<= 32)
5046 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5055 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5057 as_bad (_("Unsupported large constant"));
5062 pos
= (unsigned long) imm_expr
.X_add_number
;
5063 size
= (unsigned long) imm2_expr
.X_add_number
;
5068 as_bad (_("Improper position (%lu)"), pos
);
5071 if (size
== 0 || size
> 64
5072 || (pos
+ size
- 1) > 63)
5074 as_bad (_("Improper insert size (%lu, position %lu)"),
5079 if (pos
< 32 && (pos
+ size
- 1) < 32)
5094 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5111 as_warn (_("Divide by zero."));
5113 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5115 macro_build (NULL
, "break", "c", 7);
5122 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5123 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5127 expr1
.X_add_number
= 8;
5128 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5129 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5130 macro_build (NULL
, "break", "c", 7);
5132 expr1
.X_add_number
= -1;
5134 load_register (AT
, &expr1
, dbl
);
5135 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5136 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5139 expr1
.X_add_number
= 1;
5140 load_register (AT
, &expr1
, dbl
);
5141 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5145 expr1
.X_add_number
= 0x80000000;
5146 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5150 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5151 /* We want to close the noreorder block as soon as possible, so
5152 that later insns are available for delay slot filling. */
5157 expr1
.X_add_number
= 8;
5158 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5159 macro_build (NULL
, "nop", "", 0);
5161 /* We want to close the noreorder block as soon as possible, so
5162 that later insns are available for delay slot filling. */
5165 macro_build (NULL
, "break", "c", 6);
5167 macro_build (NULL
, s
, "d", dreg
);
5206 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5208 as_warn (_("Divide by zero."));
5210 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5212 macro_build (NULL
, "break", "c", 7);
5215 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5217 if (strcmp (s2
, "mflo") == 0)
5218 move_register (dreg
, sreg
);
5220 move_register (dreg
, 0);
5223 if (imm_expr
.X_op
== O_constant
5224 && imm_expr
.X_add_number
== -1
5225 && s
[strlen (s
) - 1] != 'u')
5227 if (strcmp (s2
, "mflo") == 0)
5229 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5232 move_register (dreg
, 0);
5237 load_register (AT
, &imm_expr
, dbl
);
5238 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5239 macro_build (NULL
, s2
, "d", dreg
);
5261 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5262 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5263 /* We want to close the noreorder block as soon as possible, so
5264 that later insns are available for delay slot filling. */
5269 expr1
.X_add_number
= 8;
5270 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5271 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5273 /* We want to close the noreorder block as soon as possible, so
5274 that later insns are available for delay slot filling. */
5276 macro_build (NULL
, "break", "c", 7);
5278 macro_build (NULL
, s2
, "d", dreg
);
5290 /* Load the address of a symbol into a register. If breg is not
5291 zero, we then add a base register to it. */
5293 if (dbl
&& HAVE_32BIT_GPRS
)
5294 as_warn (_("dla used to load 32-bit register"));
5296 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5297 as_warn (_("la used to load 64-bit address"));
5299 if (offset_expr
.X_op
== O_constant
5300 && offset_expr
.X_add_number
>= -0x8000
5301 && offset_expr
.X_add_number
< 0x8000)
5303 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5304 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5308 if (mips_opts
.at
&& (treg
== breg
))
5318 if (offset_expr
.X_op
!= O_symbol
5319 && offset_expr
.X_op
!= O_constant
)
5321 as_bad (_("expression too complex"));
5322 offset_expr
.X_op
= O_constant
;
5325 if (offset_expr
.X_op
== O_constant
)
5326 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5327 else if (mips_pic
== NO_PIC
)
5329 /* If this is a reference to a GP relative symbol, we want
5330 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5332 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5333 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5334 If we have a constant, we need two instructions anyhow,
5335 so we may as well always use the latter form.
5337 With 64bit address space and a usable $at we want
5338 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5339 lui $at,<sym> (BFD_RELOC_HI16_S)
5340 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5341 daddiu $at,<sym> (BFD_RELOC_LO16)
5343 daddu $tempreg,$tempreg,$at
5345 If $at is already in use, we use a path which is suboptimal
5346 on superscalar processors.
5347 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5348 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5350 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5352 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5354 For GP relative symbols in 64bit address space we can use
5355 the same sequence as in 32bit address space. */
5356 if (HAVE_64BIT_SYMBOLS
)
5358 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5359 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5361 relax_start (offset_expr
.X_add_symbol
);
5362 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5363 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5367 if (used_at
== 0 && mips_opts
.at
)
5369 macro_build (&offset_expr
, "lui", "t,u",
5370 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5371 macro_build (&offset_expr
, "lui", "t,u",
5372 AT
, BFD_RELOC_HI16_S
);
5373 macro_build (&offset_expr
, "daddiu", "t,r,j",
5374 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5375 macro_build (&offset_expr
, "daddiu", "t,r,j",
5376 AT
, AT
, BFD_RELOC_LO16
);
5377 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5378 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5383 macro_build (&offset_expr
, "lui", "t,u",
5384 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5385 macro_build (&offset_expr
, "daddiu", "t,r,j",
5386 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5387 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5388 macro_build (&offset_expr
, "daddiu", "t,r,j",
5389 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5390 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5391 macro_build (&offset_expr
, "daddiu", "t,r,j",
5392 tempreg
, tempreg
, BFD_RELOC_LO16
);
5395 if (mips_relax
.sequence
)
5400 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5401 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5403 relax_start (offset_expr
.X_add_symbol
);
5404 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5405 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5408 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5409 as_bad (_("offset too large"));
5410 macro_build_lui (&offset_expr
, tempreg
);
5411 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5412 tempreg
, tempreg
, BFD_RELOC_LO16
);
5413 if (mips_relax
.sequence
)
5417 else if (!mips_big_got
&& !HAVE_NEWABI
)
5419 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5421 /* If this is a reference to an external symbol, and there
5422 is no constant, we want
5423 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5424 or for lca or if tempreg is PIC_CALL_REG
5425 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5426 For a local symbol, we want
5427 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5429 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5431 If we have a small constant, and this is a reference to
5432 an external symbol, we want
5433 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5435 addiu $tempreg,$tempreg,<constant>
5436 For a local symbol, we want the same instruction
5437 sequence, but we output a BFD_RELOC_LO16 reloc on the
5440 If we have a large constant, and this is a reference to
5441 an external symbol, we want
5442 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5443 lui $at,<hiconstant>
5444 addiu $at,$at,<loconstant>
5445 addu $tempreg,$tempreg,$at
5446 For a local symbol, we want the same instruction
5447 sequence, but we output a BFD_RELOC_LO16 reloc on the
5451 if (offset_expr
.X_add_number
== 0)
5453 if (mips_pic
== SVR4_PIC
5455 && (call
|| tempreg
== PIC_CALL_REG
))
5456 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5458 relax_start (offset_expr
.X_add_symbol
);
5459 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5460 lw_reloc_type
, mips_gp_register
);
5463 /* We're going to put in an addu instruction using
5464 tempreg, so we may as well insert the nop right
5469 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5470 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5472 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5473 tempreg
, tempreg
, BFD_RELOC_LO16
);
5475 /* FIXME: If breg == 0, and the next instruction uses
5476 $tempreg, then if this variant case is used an extra
5477 nop will be generated. */
5479 else if (offset_expr
.X_add_number
>= -0x8000
5480 && offset_expr
.X_add_number
< 0x8000)
5482 load_got_offset (tempreg
, &offset_expr
);
5484 add_got_offset (tempreg
, &offset_expr
);
5488 expr1
.X_add_number
= offset_expr
.X_add_number
;
5489 offset_expr
.X_add_number
=
5490 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5491 load_got_offset (tempreg
, &offset_expr
);
5492 offset_expr
.X_add_number
= expr1
.X_add_number
;
5493 /* If we are going to add in a base register, and the
5494 target register and the base register are the same,
5495 then we are using AT as a temporary register. Since
5496 we want to load the constant into AT, we add our
5497 current AT (from the global offset table) and the
5498 register into the register now, and pretend we were
5499 not using a base register. */
5503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5508 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5512 else if (!mips_big_got
&& HAVE_NEWABI
)
5514 int add_breg_early
= 0;
5516 /* If this is a reference to an external, and there is no
5517 constant, or local symbol (*), with or without a
5519 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5520 or for lca or if tempreg is PIC_CALL_REG
5521 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5523 If we have a small constant, and this is a reference to
5524 an external symbol, we want
5525 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5526 addiu $tempreg,$tempreg,<constant>
5528 If we have a large constant, and this is a reference to
5529 an external symbol, we want
5530 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5531 lui $at,<hiconstant>
5532 addiu $at,$at,<loconstant>
5533 addu $tempreg,$tempreg,$at
5535 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5536 local symbols, even though it introduces an additional
5539 if (offset_expr
.X_add_number
)
5541 expr1
.X_add_number
= offset_expr
.X_add_number
;
5542 offset_expr
.X_add_number
= 0;
5544 relax_start (offset_expr
.X_add_symbol
);
5545 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5546 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5548 if (expr1
.X_add_number
>= -0x8000
5549 && expr1
.X_add_number
< 0x8000)
5551 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5552 tempreg
, tempreg
, BFD_RELOC_LO16
);
5554 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5558 /* If we are going to add in a base register, and the
5559 target register and the base register are the same,
5560 then we are using AT as a temporary register. Since
5561 we want to load the constant into AT, we add our
5562 current AT (from the global offset table) and the
5563 register into the register now, and pretend we were
5564 not using a base register. */
5569 assert (tempreg
== AT
);
5570 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5576 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5583 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5586 offset_expr
.X_add_number
= expr1
.X_add_number
;
5588 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5589 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5592 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5593 treg
, tempreg
, breg
);
5599 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5601 relax_start (offset_expr
.X_add_symbol
);
5602 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5603 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5606 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5611 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5612 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5615 else if (mips_big_got
&& !HAVE_NEWABI
)
5618 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5619 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5620 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5622 /* This is the large GOT case. If this is a reference to an
5623 external symbol, and there is no constant, we want
5624 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5625 addu $tempreg,$tempreg,$gp
5626 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5627 or for lca or if tempreg is PIC_CALL_REG
5628 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5629 addu $tempreg,$tempreg,$gp
5630 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5631 For a local symbol, we want
5632 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5634 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5636 If we have a small constant, and this is a reference to
5637 an external symbol, we want
5638 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5639 addu $tempreg,$tempreg,$gp
5640 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5642 addiu $tempreg,$tempreg,<constant>
5643 For a local symbol, we want
5644 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5646 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5648 If we have a large constant, and this is a reference to
5649 an external symbol, we want
5650 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5651 addu $tempreg,$tempreg,$gp
5652 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5653 lui $at,<hiconstant>
5654 addiu $at,$at,<loconstant>
5655 addu $tempreg,$tempreg,$at
5656 For a local symbol, we want
5657 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5658 lui $at,<hiconstant>
5659 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5660 addu $tempreg,$tempreg,$at
5663 expr1
.X_add_number
= offset_expr
.X_add_number
;
5664 offset_expr
.X_add_number
= 0;
5665 relax_start (offset_expr
.X_add_symbol
);
5666 gpdelay
= reg_needs_delay (mips_gp_register
);
5667 if (expr1
.X_add_number
== 0 && breg
== 0
5668 && (call
|| tempreg
== PIC_CALL_REG
))
5670 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5671 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5673 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5674 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5675 tempreg
, tempreg
, mips_gp_register
);
5676 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5677 tempreg
, lw_reloc_type
, tempreg
);
5678 if (expr1
.X_add_number
== 0)
5682 /* We're going to put in an addu instruction using
5683 tempreg, so we may as well insert the nop right
5688 else if (expr1
.X_add_number
>= -0x8000
5689 && expr1
.X_add_number
< 0x8000)
5692 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5693 tempreg
, tempreg
, BFD_RELOC_LO16
);
5699 /* If we are going to add in a base register, and the
5700 target register and the base register are the same,
5701 then we are using AT as a temporary register. Since
5702 we want to load the constant into AT, we add our
5703 current AT (from the global offset table) and the
5704 register into the register now, and pretend we were
5705 not using a base register. */
5710 assert (tempreg
== AT
);
5712 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5717 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5718 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5722 offset_expr
.X_add_number
=
5723 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5728 /* This is needed because this instruction uses $gp, but
5729 the first instruction on the main stream does not. */
5730 macro_build (NULL
, "nop", "");
5733 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5734 local_reloc_type
, mips_gp_register
);
5735 if (expr1
.X_add_number
>= -0x8000
5736 && expr1
.X_add_number
< 0x8000)
5739 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5740 tempreg
, tempreg
, BFD_RELOC_LO16
);
5741 /* FIXME: If add_number is 0, and there was no base
5742 register, the external symbol case ended with a load,
5743 so if the symbol turns out to not be external, and
5744 the next instruction uses tempreg, an unnecessary nop
5745 will be inserted. */
5751 /* We must add in the base register now, as in the
5752 external symbol case. */
5753 assert (tempreg
== AT
);
5755 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5758 /* We set breg to 0 because we have arranged to add
5759 it in in both cases. */
5763 macro_build_lui (&expr1
, AT
);
5764 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5765 AT
, AT
, BFD_RELOC_LO16
);
5766 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5767 tempreg
, tempreg
, AT
);
5772 else if (mips_big_got
&& HAVE_NEWABI
)
5774 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5775 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5776 int add_breg_early
= 0;
5778 /* This is the large GOT case. If this is a reference to an
5779 external symbol, and there is no constant, we want
5780 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5781 add $tempreg,$tempreg,$gp
5782 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5783 or for lca or if tempreg is PIC_CALL_REG
5784 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5785 add $tempreg,$tempreg,$gp
5786 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5788 If we have a small constant, and this is a reference to
5789 an external symbol, we want
5790 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5791 add $tempreg,$tempreg,$gp
5792 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5793 addi $tempreg,$tempreg,<constant>
5795 If we have a large constant, and this is a reference to
5796 an external symbol, we want
5797 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5798 addu $tempreg,$tempreg,$gp
5799 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5800 lui $at,<hiconstant>
5801 addi $at,$at,<loconstant>
5802 add $tempreg,$tempreg,$at
5804 If we have NewABI, and we know it's a local symbol, we want
5805 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5806 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5807 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5809 relax_start (offset_expr
.X_add_symbol
);
5811 expr1
.X_add_number
= offset_expr
.X_add_number
;
5812 offset_expr
.X_add_number
= 0;
5814 if (expr1
.X_add_number
== 0 && breg
== 0
5815 && (call
|| tempreg
== PIC_CALL_REG
))
5817 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5818 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5820 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5822 tempreg
, tempreg
, mips_gp_register
);
5823 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5824 tempreg
, lw_reloc_type
, tempreg
);
5826 if (expr1
.X_add_number
== 0)
5828 else if (expr1
.X_add_number
>= -0x8000
5829 && expr1
.X_add_number
< 0x8000)
5831 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5832 tempreg
, tempreg
, BFD_RELOC_LO16
);
5834 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5838 /* If we are going to add in a base register, and the
5839 target register and the base register are the same,
5840 then we are using AT as a temporary register. Since
5841 we want to load the constant into AT, we add our
5842 current AT (from the global offset table) and the
5843 register into the register now, and pretend we were
5844 not using a base register. */
5849 assert (tempreg
== AT
);
5850 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5856 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5857 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5862 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5865 offset_expr
.X_add_number
= expr1
.X_add_number
;
5866 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5867 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5868 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5869 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5872 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5873 treg
, tempreg
, breg
);
5883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5887 /* The j instruction may not be used in PIC code, since it
5888 requires an absolute address. We convert it to a b
5890 if (mips_pic
== NO_PIC
)
5891 macro_build (&offset_expr
, "j", "a");
5893 macro_build (&offset_expr
, "b", "p");
5896 /* The jal instructions must be handled as macros because when
5897 generating PIC code they expand to multi-instruction
5898 sequences. Normally they are simple instructions. */
5903 if (mips_pic
== NO_PIC
)
5904 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5907 if (sreg
!= PIC_CALL_REG
)
5908 as_warn (_("MIPS PIC call to register other than $25"));
5910 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5911 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5913 if (mips_cprestore_offset
< 0)
5914 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5917 if (! mips_frame_reg_valid
)
5919 as_warn (_("No .frame pseudo-op used in PIC code"));
5920 /* Quiet this warning. */
5921 mips_frame_reg_valid
= 1;
5923 if (! mips_cprestore_valid
)
5925 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5926 /* Quiet this warning. */
5927 mips_cprestore_valid
= 1;
5929 expr1
.X_add_number
= mips_cprestore_offset
;
5930 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5933 HAVE_64BIT_ADDRESSES
);
5941 if (mips_pic
== NO_PIC
)
5942 macro_build (&offset_expr
, "jal", "a");
5943 else if (mips_pic
== SVR4_PIC
)
5945 /* If this is a reference to an external symbol, and we are
5946 using a small GOT, we want
5947 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5951 lw $gp,cprestore($sp)
5952 The cprestore value is set using the .cprestore
5953 pseudo-op. If we are using a big GOT, we want
5954 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5956 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5960 lw $gp,cprestore($sp)
5961 If the symbol is not external, we want
5962 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5964 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5967 lw $gp,cprestore($sp)
5969 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5970 sequences above, minus nops, unless the symbol is local,
5971 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5977 relax_start (offset_expr
.X_add_symbol
);
5978 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5979 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5982 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5983 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5989 relax_start (offset_expr
.X_add_symbol
);
5990 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5991 BFD_RELOC_MIPS_CALL_HI16
);
5992 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5993 PIC_CALL_REG
, mips_gp_register
);
5994 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5995 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5998 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5999 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6001 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6002 PIC_CALL_REG
, PIC_CALL_REG
,
6003 BFD_RELOC_MIPS_GOT_OFST
);
6007 macro_build_jalr (&offset_expr
);
6011 relax_start (offset_expr
.X_add_symbol
);
6014 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6015 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6024 gpdelay
= reg_needs_delay (mips_gp_register
);
6025 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6026 BFD_RELOC_MIPS_CALL_HI16
);
6027 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6028 PIC_CALL_REG
, mips_gp_register
);
6029 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6030 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6035 macro_build (NULL
, "nop", "");
6037 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6038 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6041 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6042 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6044 macro_build_jalr (&offset_expr
);
6046 if (mips_cprestore_offset
< 0)
6047 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6050 if (! mips_frame_reg_valid
)
6052 as_warn (_("No .frame pseudo-op used in PIC code"));
6053 /* Quiet this warning. */
6054 mips_frame_reg_valid
= 1;
6056 if (! mips_cprestore_valid
)
6058 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6059 /* Quiet this warning. */
6060 mips_cprestore_valid
= 1;
6062 if (mips_opts
.noreorder
)
6063 macro_build (NULL
, "nop", "");
6064 expr1
.X_add_number
= mips_cprestore_offset
;
6065 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6068 HAVE_64BIT_ADDRESSES
);
6072 else if (mips_pic
== VXWORKS_PIC
)
6073 as_bad (_("Non-PIC jump used in PIC library"));
6096 /* Itbl support may require additional care here. */
6101 /* Itbl support may require additional care here. */
6106 /* Itbl support may require additional care here. */
6111 /* Itbl support may require additional care here. */
6123 if (mips_opts
.arch
== CPU_R4650
)
6125 as_bad (_("opcode not supported on this processor"));
6129 /* Itbl support may require additional care here. */
6134 /* Itbl support may require additional care here. */
6139 /* Itbl support may require additional care here. */
6159 if (breg
== treg
|| coproc
|| lr
)
6180 /* Itbl support may require additional care here. */
6185 /* Itbl support may require additional care here. */
6190 /* Itbl support may require additional care here. */
6195 /* Itbl support may require additional care here. */
6214 if (mips_opts
.arch
== CPU_R4650
)
6216 as_bad (_("opcode not supported on this processor"));
6221 /* Itbl support may require additional care here. */
6225 /* Itbl support may require additional care here. */
6230 /* Itbl support may require additional care here. */
6242 /* Itbl support may require additional care here. */
6243 if (mask
== M_LWC1_AB
6244 || mask
== M_SWC1_AB
6245 || mask
== M_LDC1_AB
6246 || mask
== M_SDC1_AB
6250 else if (mask
== M_CACHE_AB
)
6257 if (offset_expr
.X_op
!= O_constant
6258 && offset_expr
.X_op
!= O_symbol
)
6260 as_bad (_("expression too complex"));
6261 offset_expr
.X_op
= O_constant
;
6264 if (HAVE_32BIT_ADDRESSES
6265 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6269 sprintf_vma (value
, offset_expr
.X_add_number
);
6270 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6273 /* A constant expression in PIC code can be handled just as it
6274 is in non PIC code. */
6275 if (offset_expr
.X_op
== O_constant
)
6277 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6278 & ~(bfd_vma
) 0xffff);
6279 normalize_address_expr (&expr1
);
6280 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6282 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6283 tempreg
, tempreg
, breg
);
6284 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6286 else if (mips_pic
== NO_PIC
)
6288 /* If this is a reference to a GP relative symbol, and there
6289 is no base register, we want
6290 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6291 Otherwise, if there is no base register, we want
6292 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6293 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6294 If we have a constant, we need two instructions anyhow,
6295 so we always use the latter form.
6297 If we have a base register, and this is a reference to a
6298 GP relative symbol, we want
6299 addu $tempreg,$breg,$gp
6300 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6302 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6303 addu $tempreg,$tempreg,$breg
6304 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6305 With a constant we always use the latter case.
6307 With 64bit address space and no base register and $at usable,
6309 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6310 lui $at,<sym> (BFD_RELOC_HI16_S)
6311 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6314 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6315 If we have a base register, we want
6316 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6317 lui $at,<sym> (BFD_RELOC_HI16_S)
6318 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6322 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6324 Without $at we can't generate the optimal path for superscalar
6325 processors here since this would require two temporary registers.
6326 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6329 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6331 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6332 If we have a base register, we want
6333 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6334 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6336 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6338 daddu $tempreg,$tempreg,$breg
6339 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6341 For GP relative symbols in 64bit address space we can use
6342 the same sequence as in 32bit address space. */
6343 if (HAVE_64BIT_SYMBOLS
)
6345 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6346 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6348 relax_start (offset_expr
.X_add_symbol
);
6351 macro_build (&offset_expr
, s
, fmt
, treg
,
6352 BFD_RELOC_GPREL16
, mips_gp_register
);
6356 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6357 tempreg
, breg
, mips_gp_register
);
6358 macro_build (&offset_expr
, s
, fmt
, treg
,
6359 BFD_RELOC_GPREL16
, tempreg
);
6364 if (used_at
== 0 && mips_opts
.at
)
6366 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6367 BFD_RELOC_MIPS_HIGHEST
);
6368 macro_build (&offset_expr
, "lui", "t,u", AT
,
6370 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6371 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6373 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6374 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6375 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6376 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6382 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6383 BFD_RELOC_MIPS_HIGHEST
);
6384 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6385 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6386 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6387 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6388 tempreg
, BFD_RELOC_HI16_S
);
6389 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6391 macro_build (NULL
, "daddu", "d,v,t",
6392 tempreg
, tempreg
, breg
);
6393 macro_build (&offset_expr
, s
, fmt
, treg
,
6394 BFD_RELOC_LO16
, tempreg
);
6397 if (mips_relax
.sequence
)
6404 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6405 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6407 relax_start (offset_expr
.X_add_symbol
);
6408 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6412 macro_build_lui (&offset_expr
, tempreg
);
6413 macro_build (&offset_expr
, s
, fmt
, treg
,
6414 BFD_RELOC_LO16
, tempreg
);
6415 if (mips_relax
.sequence
)
6420 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6421 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6423 relax_start (offset_expr
.X_add_symbol
);
6424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6425 tempreg
, breg
, mips_gp_register
);
6426 macro_build (&offset_expr
, s
, fmt
, treg
,
6427 BFD_RELOC_GPREL16
, tempreg
);
6430 macro_build_lui (&offset_expr
, tempreg
);
6431 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6432 tempreg
, tempreg
, breg
);
6433 macro_build (&offset_expr
, s
, fmt
, treg
,
6434 BFD_RELOC_LO16
, tempreg
);
6435 if (mips_relax
.sequence
)
6439 else if (!mips_big_got
)
6441 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6443 /* If this is a reference to an external symbol, we want
6444 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6446 <op> $treg,0($tempreg)
6448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6450 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6451 <op> $treg,0($tempreg)
6454 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6455 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6457 If there is a base register, we add it to $tempreg before
6458 the <op>. If there is a constant, we stick it in the
6459 <op> instruction. We don't handle constants larger than
6460 16 bits, because we have no way to load the upper 16 bits
6461 (actually, we could handle them for the subset of cases
6462 in which we are not using $at). */
6463 assert (offset_expr
.X_op
== O_symbol
);
6466 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6467 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6470 tempreg
, tempreg
, breg
);
6471 macro_build (&offset_expr
, s
, fmt
, treg
,
6472 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6475 expr1
.X_add_number
= offset_expr
.X_add_number
;
6476 offset_expr
.X_add_number
= 0;
6477 if (expr1
.X_add_number
< -0x8000
6478 || expr1
.X_add_number
>= 0x8000)
6479 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6480 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6481 lw_reloc_type
, mips_gp_register
);
6483 relax_start (offset_expr
.X_add_symbol
);
6485 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6486 tempreg
, BFD_RELOC_LO16
);
6489 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6490 tempreg
, tempreg
, breg
);
6491 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6493 else if (mips_big_got
&& !HAVE_NEWABI
)
6497 /* If this is a reference to an external symbol, we want
6498 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6499 addu $tempreg,$tempreg,$gp
6500 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6501 <op> $treg,0($tempreg)
6503 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6505 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6506 <op> $treg,0($tempreg)
6507 If there is a base register, we add it to $tempreg before
6508 the <op>. If there is a constant, we stick it in the
6509 <op> instruction. We don't handle constants larger than
6510 16 bits, because we have no way to load the upper 16 bits
6511 (actually, we could handle them for the subset of cases
6512 in which we are not using $at). */
6513 assert (offset_expr
.X_op
== O_symbol
);
6514 expr1
.X_add_number
= offset_expr
.X_add_number
;
6515 offset_expr
.X_add_number
= 0;
6516 if (expr1
.X_add_number
< -0x8000
6517 || expr1
.X_add_number
>= 0x8000)
6518 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6519 gpdelay
= reg_needs_delay (mips_gp_register
);
6520 relax_start (offset_expr
.X_add_symbol
);
6521 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6522 BFD_RELOC_MIPS_GOT_HI16
);
6523 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6526 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6529 macro_build (NULL
, "nop", "");
6530 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6531 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6533 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6534 tempreg
, BFD_RELOC_LO16
);
6538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6539 tempreg
, tempreg
, breg
);
6540 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6542 else if (mips_big_got
&& HAVE_NEWABI
)
6544 /* If this is a reference to an external symbol, we want
6545 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6546 add $tempreg,$tempreg,$gp
6547 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6548 <op> $treg,<ofst>($tempreg)
6549 Otherwise, for local symbols, we want:
6550 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6551 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6552 assert (offset_expr
.X_op
== O_symbol
);
6553 expr1
.X_add_number
= offset_expr
.X_add_number
;
6554 offset_expr
.X_add_number
= 0;
6555 if (expr1
.X_add_number
< -0x8000
6556 || expr1
.X_add_number
>= 0x8000)
6557 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6558 relax_start (offset_expr
.X_add_symbol
);
6559 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6560 BFD_RELOC_MIPS_GOT_HI16
);
6561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6563 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6564 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6566 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6567 tempreg
, tempreg
, breg
);
6568 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6571 offset_expr
.X_add_number
= expr1
.X_add_number
;
6572 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6573 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6576 tempreg
, tempreg
, breg
);
6577 macro_build (&offset_expr
, s
, fmt
, treg
,
6578 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6588 load_register (treg
, &imm_expr
, 0);
6592 load_register (treg
, &imm_expr
, 1);
6596 if (imm_expr
.X_op
== O_constant
)
6599 load_register (AT
, &imm_expr
, 0);
6600 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6605 assert (offset_expr
.X_op
== O_symbol
6606 && strcmp (segment_name (S_GET_SEGMENT
6607 (offset_expr
.X_add_symbol
)),
6609 && offset_expr
.X_add_number
== 0);
6610 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6611 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6616 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6617 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6618 order 32 bits of the value and the low order 32 bits are either
6619 zero or in OFFSET_EXPR. */
6620 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6622 if (HAVE_64BIT_GPRS
)
6623 load_register (treg
, &imm_expr
, 1);
6628 if (target_big_endian
)
6640 load_register (hreg
, &imm_expr
, 0);
6643 if (offset_expr
.X_op
== O_absent
)
6644 move_register (lreg
, 0);
6647 assert (offset_expr
.X_op
== O_constant
);
6648 load_register (lreg
, &offset_expr
, 0);
6655 /* We know that sym is in the .rdata section. First we get the
6656 upper 16 bits of the address. */
6657 if (mips_pic
== NO_PIC
)
6659 macro_build_lui (&offset_expr
, AT
);
6664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6665 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6669 /* Now we load the register(s). */
6670 if (HAVE_64BIT_GPRS
)
6673 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6678 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6681 /* FIXME: How in the world do we deal with the possible
6683 offset_expr
.X_add_number
+= 4;
6684 macro_build (&offset_expr
, "lw", "t,o(b)",
6685 treg
+ 1, BFD_RELOC_LO16
, AT
);
6691 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6692 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6693 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6694 the value and the low order 32 bits are either zero or in
6696 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6699 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6700 if (HAVE_64BIT_FPRS
)
6702 assert (HAVE_64BIT_GPRS
);
6703 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6707 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6708 if (offset_expr
.X_op
== O_absent
)
6709 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6712 assert (offset_expr
.X_op
== O_constant
);
6713 load_register (AT
, &offset_expr
, 0);
6714 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6720 assert (offset_expr
.X_op
== O_symbol
6721 && offset_expr
.X_add_number
== 0);
6722 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6723 if (strcmp (s
, ".lit8") == 0)
6725 if (mips_opts
.isa
!= ISA_MIPS1
)
6727 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6728 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6731 breg
= mips_gp_register
;
6732 r
= BFD_RELOC_MIPS_LITERAL
;
6737 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6739 if (mips_pic
!= NO_PIC
)
6740 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6741 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6744 /* FIXME: This won't work for a 64 bit address. */
6745 macro_build_lui (&offset_expr
, AT
);
6748 if (mips_opts
.isa
!= ISA_MIPS1
)
6750 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6751 treg
, BFD_RELOC_LO16
, AT
);
6760 if (mips_opts
.arch
== CPU_R4650
)
6762 as_bad (_("opcode not supported on this processor"));
6765 /* Even on a big endian machine $fn comes before $fn+1. We have
6766 to adjust when loading from memory. */
6769 assert (mips_opts
.isa
== ISA_MIPS1
);
6770 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6771 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6772 /* FIXME: A possible overflow which I don't know how to deal
6774 offset_expr
.X_add_number
+= 4;
6775 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6776 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6781 * The MIPS assembler seems to check for X_add_number not
6782 * being double aligned and generating:
6785 * addiu at,at,%lo(foo+1)
6788 * But, the resulting address is the same after relocation so why
6789 * generate the extra instruction?
6791 if (mips_opts
.arch
== CPU_R4650
)
6793 as_bad (_("opcode not supported on this processor"));
6796 /* Itbl support may require additional care here. */
6798 if (mips_opts
.isa
!= ISA_MIPS1
)
6809 if (mips_opts
.arch
== CPU_R4650
)
6811 as_bad (_("opcode not supported on this processor"));
6815 if (mips_opts
.isa
!= ISA_MIPS1
)
6823 /* Itbl support may require additional care here. */
6828 if (HAVE_64BIT_GPRS
)
6839 if (HAVE_64BIT_GPRS
)
6849 if (offset_expr
.X_op
!= O_symbol
6850 && offset_expr
.X_op
!= O_constant
)
6852 as_bad (_("expression too complex"));
6853 offset_expr
.X_op
= O_constant
;
6856 if (HAVE_32BIT_ADDRESSES
6857 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6861 sprintf_vma (value
, offset_expr
.X_add_number
);
6862 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6865 /* Even on a big endian machine $fn comes before $fn+1. We have
6866 to adjust when loading from memory. We set coproc if we must
6867 load $fn+1 first. */
6868 /* Itbl support may require additional care here. */
6869 if (! target_big_endian
)
6872 if (mips_pic
== NO_PIC
6873 || offset_expr
.X_op
== O_constant
)
6875 /* If this is a reference to a GP relative symbol, we want
6876 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6877 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6878 If we have a base register, we use this
6880 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6881 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6882 If this is not a GP relative symbol, we want
6883 lui $at,<sym> (BFD_RELOC_HI16_S)
6884 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6885 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6886 If there is a base register, we add it to $at after the
6887 lui instruction. If there is a constant, we always use
6889 if (offset_expr
.X_op
== O_symbol
6890 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6891 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6893 relax_start (offset_expr
.X_add_symbol
);
6896 tempreg
= mips_gp_register
;
6900 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6901 AT
, breg
, mips_gp_register
);
6906 /* Itbl support may require additional care here. */
6907 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6908 BFD_RELOC_GPREL16
, tempreg
);
6909 offset_expr
.X_add_number
+= 4;
6911 /* Set mips_optimize to 2 to avoid inserting an
6913 hold_mips_optimize
= mips_optimize
;
6915 /* Itbl support may require additional care here. */
6916 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6917 BFD_RELOC_GPREL16
, tempreg
);
6918 mips_optimize
= hold_mips_optimize
;
6922 /* We just generated two relocs. When tc_gen_reloc
6923 handles this case, it will skip the first reloc and
6924 handle the second. The second reloc already has an
6925 extra addend of 4, which we added above. We must
6926 subtract it out, and then subtract another 4 to make
6927 the first reloc come out right. The second reloc
6928 will come out right because we are going to add 4 to
6929 offset_expr when we build its instruction below.
6931 If we have a symbol, then we don't want to include
6932 the offset, because it will wind up being included
6933 when we generate the reloc. */
6935 if (offset_expr
.X_op
== O_constant
)
6936 offset_expr
.X_add_number
-= 8;
6939 offset_expr
.X_add_number
= -4;
6940 offset_expr
.X_op
= O_constant
;
6944 macro_build_lui (&offset_expr
, AT
);
6946 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6947 /* Itbl support may require additional care here. */
6948 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6949 BFD_RELOC_LO16
, AT
);
6950 /* FIXME: How do we handle overflow here? */
6951 offset_expr
.X_add_number
+= 4;
6952 /* Itbl support may require additional care here. */
6953 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6954 BFD_RELOC_LO16
, AT
);
6955 if (mips_relax
.sequence
)
6958 else if (!mips_big_got
)
6960 /* If this is a reference to an external symbol, we want
6961 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6966 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6968 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6969 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6970 If there is a base register we add it to $at before the
6971 lwc1 instructions. If there is a constant we include it
6972 in the lwc1 instructions. */
6974 expr1
.X_add_number
= offset_expr
.X_add_number
;
6975 if (expr1
.X_add_number
< -0x8000
6976 || expr1
.X_add_number
>= 0x8000 - 4)
6977 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6978 load_got_offset (AT
, &offset_expr
);
6981 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6983 /* Set mips_optimize to 2 to avoid inserting an undesired
6985 hold_mips_optimize
= mips_optimize
;
6988 /* Itbl support may require additional care here. */
6989 relax_start (offset_expr
.X_add_symbol
);
6990 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6991 BFD_RELOC_LO16
, AT
);
6992 expr1
.X_add_number
+= 4;
6993 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6994 BFD_RELOC_LO16
, AT
);
6996 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6997 BFD_RELOC_LO16
, AT
);
6998 offset_expr
.X_add_number
+= 4;
6999 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7000 BFD_RELOC_LO16
, AT
);
7003 mips_optimize
= hold_mips_optimize
;
7005 else if (mips_big_got
)
7009 /* If this is a reference to an external symbol, we want
7010 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7012 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7017 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7019 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7020 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7021 If there is a base register we add it to $at before the
7022 lwc1 instructions. If there is a constant we include it
7023 in the lwc1 instructions. */
7025 expr1
.X_add_number
= offset_expr
.X_add_number
;
7026 offset_expr
.X_add_number
= 0;
7027 if (expr1
.X_add_number
< -0x8000
7028 || expr1
.X_add_number
>= 0x8000 - 4)
7029 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7030 gpdelay
= reg_needs_delay (mips_gp_register
);
7031 relax_start (offset_expr
.X_add_symbol
);
7032 macro_build (&offset_expr
, "lui", "t,u",
7033 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7035 AT
, AT
, mips_gp_register
);
7036 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7037 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7041 /* Itbl support may require additional care here. */
7042 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7043 BFD_RELOC_LO16
, AT
);
7044 expr1
.X_add_number
+= 4;
7046 /* Set mips_optimize to 2 to avoid inserting an undesired
7048 hold_mips_optimize
= mips_optimize
;
7050 /* Itbl support may require additional care here. */
7051 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7052 BFD_RELOC_LO16
, AT
);
7053 mips_optimize
= hold_mips_optimize
;
7054 expr1
.X_add_number
-= 4;
7057 offset_expr
.X_add_number
= expr1
.X_add_number
;
7059 macro_build (NULL
, "nop", "");
7060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7061 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7065 /* Itbl support may require additional care here. */
7066 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7067 BFD_RELOC_LO16
, AT
);
7068 offset_expr
.X_add_number
+= 4;
7070 /* Set mips_optimize to 2 to avoid inserting an undesired
7072 hold_mips_optimize
= mips_optimize
;
7074 /* Itbl support may require additional care here. */
7075 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7076 BFD_RELOC_LO16
, AT
);
7077 mips_optimize
= hold_mips_optimize
;
7091 assert (HAVE_32BIT_ADDRESSES
);
7092 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7093 offset_expr
.X_add_number
+= 4;
7094 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7097 /* New code added to support COPZ instructions.
7098 This code builds table entries out of the macros in mip_opcodes.
7099 R4000 uses interlocks to handle coproc delays.
7100 Other chips (like the R3000) require nops to be inserted for delays.
7102 FIXME: Currently, we require that the user handle delays.
7103 In order to fill delay slots for non-interlocked chips,
7104 we must have a way to specify delays based on the coprocessor.
7105 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7106 What are the side-effects of the cop instruction?
7107 What cache support might we have and what are its effects?
7108 Both coprocessor & memory require delays. how long???
7109 What registers are read/set/modified?
7111 If an itbl is provided to interpret cop instructions,
7112 this knowledge can be encoded in the itbl spec. */
7126 /* For now we just do C (same as Cz). The parameter will be
7127 stored in insn_opcode by mips_ip. */
7128 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7132 move_register (dreg
, sreg
);
7135 #ifdef LOSING_COMPILER
7137 /* Try and see if this is a new itbl instruction.
7138 This code builds table entries out of the macros in mip_opcodes.
7139 FIXME: For now we just assemble the expression and pass it's
7140 value along as a 32-bit immediate.
7141 We may want to have the assembler assemble this value,
7142 so that we gain the assembler's knowledge of delay slots,
7144 Would it be more efficient to use mask (id) here? */
7145 if (itbl_have_entries
7146 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7148 s
= ip
->insn_mo
->name
;
7150 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7151 macro_build (&immed_expr
, s
, "C");
7157 if (!mips_opts
.at
&& used_at
)
7158 as_bad (_("Macro used $at after \".set noat\""));
7162 macro2 (struct mips_cl_insn
*ip
)
7164 unsigned int treg
, sreg
, dreg
, breg
;
7165 unsigned int tempreg
;
7179 bfd_reloc_code_real_type r
;
7181 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7182 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7183 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7184 mask
= ip
->insn_mo
->mask
;
7186 expr1
.X_op
= O_constant
;
7187 expr1
.X_op_symbol
= NULL
;
7188 expr1
.X_add_symbol
= NULL
;
7189 expr1
.X_add_number
= 1;
7193 #endif /* LOSING_COMPILER */
7198 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7199 macro_build (NULL
, "mflo", "d", dreg
);
7205 /* The MIPS assembler some times generates shifts and adds. I'm
7206 not trying to be that fancy. GCC should do this for us
7209 load_register (AT
, &imm_expr
, dbl
);
7210 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7211 macro_build (NULL
, "mflo", "d", dreg
);
7227 load_register (AT
, &imm_expr
, dbl
);
7228 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7229 macro_build (NULL
, "mflo", "d", dreg
);
7230 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7231 macro_build (NULL
, "mfhi", "d", AT
);
7233 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7236 expr1
.X_add_number
= 8;
7237 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7238 macro_build (NULL
, "nop", "", 0);
7239 macro_build (NULL
, "break", "c", 6);
7242 macro_build (NULL
, "mflo", "d", dreg
);
7258 load_register (AT
, &imm_expr
, dbl
);
7259 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7260 sreg
, imm
? AT
: treg
);
7261 macro_build (NULL
, "mfhi", "d", AT
);
7262 macro_build (NULL
, "mflo", "d", dreg
);
7264 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7267 expr1
.X_add_number
= 8;
7268 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7269 macro_build (NULL
, "nop", "", 0);
7270 macro_build (NULL
, "break", "c", 6);
7276 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7287 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7288 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7292 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7293 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7294 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7295 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7299 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7310 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7311 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7315 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7316 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7317 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7318 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7326 if (imm_expr
.X_op
!= O_constant
)
7327 as_bad (_("Improper rotate count"));
7328 rot
= imm_expr
.X_add_number
& 0x3f;
7329 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7331 rot
= (64 - rot
) & 0x3f;
7333 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7335 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7340 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7343 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7344 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7347 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7348 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7349 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7357 if (imm_expr
.X_op
!= O_constant
)
7358 as_bad (_("Improper rotate count"));
7359 rot
= imm_expr
.X_add_number
& 0x1f;
7360 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7362 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7367 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7371 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7372 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7373 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7378 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7380 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7384 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7385 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7386 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7387 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7391 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7393 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7397 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7398 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7399 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7400 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7408 if (imm_expr
.X_op
!= O_constant
)
7409 as_bad (_("Improper rotate count"));
7410 rot
= imm_expr
.X_add_number
& 0x3f;
7411 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7414 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7416 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7421 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7424 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7425 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7428 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7429 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7430 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7438 if (imm_expr
.X_op
!= O_constant
)
7439 as_bad (_("Improper rotate count"));
7440 rot
= imm_expr
.X_add_number
& 0x1f;
7441 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7443 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7448 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7452 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7453 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7454 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7459 if (mips_opts
.arch
== CPU_R4650
)
7461 as_bad (_("opcode not supported on this processor"));
7464 assert (mips_opts
.isa
== ISA_MIPS1
);
7465 /* Even on a big endian machine $fn comes before $fn+1. We have
7466 to adjust when storing to memory. */
7467 macro_build (&offset_expr
, "swc1", "T,o(b)",
7468 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7469 offset_expr
.X_add_number
+= 4;
7470 macro_build (&offset_expr
, "swc1", "T,o(b)",
7471 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7476 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7478 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7481 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7482 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7487 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7489 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7494 as_warn (_("Instruction %s: result is always false"),
7496 move_register (dreg
, 0);
7499 if (imm_expr
.X_op
== O_constant
7500 && imm_expr
.X_add_number
>= 0
7501 && imm_expr
.X_add_number
< 0x10000)
7503 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7505 else if (imm_expr
.X_op
== O_constant
7506 && imm_expr
.X_add_number
> -0x8000
7507 && imm_expr
.X_add_number
< 0)
7509 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7510 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7511 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7515 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7516 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7519 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7522 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7528 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7529 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7532 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7534 if (imm_expr
.X_op
== O_constant
7535 && imm_expr
.X_add_number
>= -0x8000
7536 && imm_expr
.X_add_number
< 0x8000)
7538 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7539 dreg
, sreg
, BFD_RELOC_LO16
);
7543 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7544 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7548 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7551 case M_SGT
: /* sreg > treg <==> treg < sreg */
7557 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7560 case M_SGT_I
: /* sreg > I <==> I < sreg */
7567 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7568 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7571 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7577 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7578 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7581 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7588 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7589 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7590 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7594 if (imm_expr
.X_op
== O_constant
7595 && imm_expr
.X_add_number
>= -0x8000
7596 && imm_expr
.X_add_number
< 0x8000)
7598 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7602 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7603 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7607 if (imm_expr
.X_op
== O_constant
7608 && imm_expr
.X_add_number
>= -0x8000
7609 && imm_expr
.X_add_number
< 0x8000)
7611 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7616 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7617 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7622 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7624 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7627 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7628 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7633 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7635 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7640 as_warn (_("Instruction %s: result is always true"),
7642 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7643 dreg
, 0, BFD_RELOC_LO16
);
7646 if (imm_expr
.X_op
== O_constant
7647 && imm_expr
.X_add_number
>= 0
7648 && imm_expr
.X_add_number
< 0x10000)
7650 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7652 else if (imm_expr
.X_op
== O_constant
7653 && imm_expr
.X_add_number
> -0x8000
7654 && imm_expr
.X_add_number
< 0)
7656 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7657 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7658 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7662 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7663 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7666 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7672 if (imm_expr
.X_op
== O_constant
7673 && imm_expr
.X_add_number
> -0x8000
7674 && imm_expr
.X_add_number
<= 0x8000)
7676 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7677 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7678 dreg
, sreg
, BFD_RELOC_LO16
);
7682 load_register (AT
, &imm_expr
, dbl
);
7683 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7689 if (imm_expr
.X_op
== O_constant
7690 && imm_expr
.X_add_number
> -0x8000
7691 && imm_expr
.X_add_number
<= 0x8000)
7693 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7694 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7695 dreg
, sreg
, BFD_RELOC_LO16
);
7699 load_register (AT
, &imm_expr
, dbl
);
7700 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7722 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7723 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7728 assert (mips_opts
.isa
== ISA_MIPS1
);
7730 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7731 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7734 * Is the double cfc1 instruction a bug in the mips assembler;
7735 * or is there a reason for it?
7738 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7739 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7740 macro_build (NULL
, "nop", "");
7741 expr1
.X_add_number
= 3;
7742 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7743 expr1
.X_add_number
= 2;
7744 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7745 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7746 macro_build (NULL
, "nop", "");
7747 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7749 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7750 macro_build (NULL
, "nop", "");
7761 if (offset_expr
.X_add_number
>= 0x7fff)
7762 as_bad (_("operand overflow"));
7763 if (! target_big_endian
)
7764 ++offset_expr
.X_add_number
;
7765 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7766 if (! target_big_endian
)
7767 --offset_expr
.X_add_number
;
7769 ++offset_expr
.X_add_number
;
7770 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7771 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7772 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7785 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7786 as_bad (_("operand overflow"));
7794 if (! target_big_endian
)
7795 offset_expr
.X_add_number
+= off
;
7796 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7797 if (! target_big_endian
)
7798 offset_expr
.X_add_number
-= off
;
7800 offset_expr
.X_add_number
+= off
;
7801 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7803 /* If necessary, move the result in tempreg the final destination. */
7804 if (treg
== tempreg
)
7806 /* Protect second load's delay slot. */
7808 move_register (treg
, tempreg
);
7822 load_address (AT
, &offset_expr
, &used_at
);
7824 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7825 if (! target_big_endian
)
7826 expr1
.X_add_number
= off
;
7828 expr1
.X_add_number
= 0;
7829 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7830 if (! target_big_endian
)
7831 expr1
.X_add_number
= 0;
7833 expr1
.X_add_number
= off
;
7834 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7840 load_address (AT
, &offset_expr
, &used_at
);
7842 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7843 if (target_big_endian
)
7844 expr1
.X_add_number
= 0;
7845 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7846 treg
, BFD_RELOC_LO16
, AT
);
7847 if (target_big_endian
)
7848 expr1
.X_add_number
= 1;
7850 expr1
.X_add_number
= 0;
7851 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7852 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7853 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7858 if (offset_expr
.X_add_number
>= 0x7fff)
7859 as_bad (_("operand overflow"));
7860 if (target_big_endian
)
7861 ++offset_expr
.X_add_number
;
7862 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7863 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7864 if (target_big_endian
)
7865 --offset_expr
.X_add_number
;
7867 ++offset_expr
.X_add_number
;
7868 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7881 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7882 as_bad (_("operand overflow"));
7883 if (! target_big_endian
)
7884 offset_expr
.X_add_number
+= off
;
7885 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7886 if (! target_big_endian
)
7887 offset_expr
.X_add_number
-= off
;
7889 offset_expr
.X_add_number
+= off
;
7890 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7904 load_address (AT
, &offset_expr
, &used_at
);
7906 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7907 if (! target_big_endian
)
7908 expr1
.X_add_number
= off
;
7910 expr1
.X_add_number
= 0;
7911 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7912 if (! target_big_endian
)
7913 expr1
.X_add_number
= 0;
7915 expr1
.X_add_number
= off
;
7916 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7921 load_address (AT
, &offset_expr
, &used_at
);
7923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7924 if (! target_big_endian
)
7925 expr1
.X_add_number
= 0;
7926 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7927 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7928 if (! target_big_endian
)
7929 expr1
.X_add_number
= 1;
7931 expr1
.X_add_number
= 0;
7932 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7933 if (! target_big_endian
)
7934 expr1
.X_add_number
= 0;
7936 expr1
.X_add_number
= 1;
7937 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7938 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7939 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7943 /* FIXME: Check if this is one of the itbl macros, since they
7944 are added dynamically. */
7945 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7948 if (!mips_opts
.at
&& used_at
)
7949 as_bad (_("Macro used $at after \".set noat\""));
7952 /* Implement macros in mips16 mode. */
7955 mips16_macro (struct mips_cl_insn
*ip
)
7958 int xreg
, yreg
, zreg
, tmp
;
7961 const char *s
, *s2
, *s3
;
7963 mask
= ip
->insn_mo
->mask
;
7965 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7966 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7967 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7969 expr1
.X_op
= O_constant
;
7970 expr1
.X_op_symbol
= NULL
;
7971 expr1
.X_add_symbol
= NULL
;
7972 expr1
.X_add_number
= 1;
7992 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7993 expr1
.X_add_number
= 2;
7994 macro_build (&expr1
, "bnez", "x,p", yreg
);
7995 macro_build (NULL
, "break", "6", 7);
7997 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7998 since that causes an overflow. We should do that as well,
7999 but I don't see how to do the comparisons without a temporary
8002 macro_build (NULL
, s
, "x", zreg
);
8022 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8023 expr1
.X_add_number
= 2;
8024 macro_build (&expr1
, "bnez", "x,p", yreg
);
8025 macro_build (NULL
, "break", "6", 7);
8027 macro_build (NULL
, s2
, "x", zreg
);
8033 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8034 macro_build (NULL
, "mflo", "x", zreg
);
8042 if (imm_expr
.X_op
!= O_constant
)
8043 as_bad (_("Unsupported large constant"));
8044 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8045 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8049 if (imm_expr
.X_op
!= O_constant
)
8050 as_bad (_("Unsupported large constant"));
8051 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8052 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8056 if (imm_expr
.X_op
!= O_constant
)
8057 as_bad (_("Unsupported large constant"));
8058 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8059 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8081 goto do_reverse_branch
;
8085 goto do_reverse_branch
;
8097 goto do_reverse_branch
;
8108 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8109 macro_build (&offset_expr
, s2
, "p");
8136 goto do_addone_branch_i
;
8141 goto do_addone_branch_i
;
8156 goto do_addone_branch_i
;
8163 if (imm_expr
.X_op
!= O_constant
)
8164 as_bad (_("Unsupported large constant"));
8165 ++imm_expr
.X_add_number
;
8168 macro_build (&imm_expr
, s
, s3
, xreg
);
8169 macro_build (&offset_expr
, s2
, "p");
8173 expr1
.X_add_number
= 0;
8174 macro_build (&expr1
, "slti", "x,8", yreg
);
8176 move_register (xreg
, yreg
);
8177 expr1
.X_add_number
= 2;
8178 macro_build (&expr1
, "bteqz", "p");
8179 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8183 /* For consistency checking, verify that all bits are specified either
8184 by the match/mask part of the instruction definition, or by the
8187 validate_mips_insn (const struct mips_opcode
*opc
)
8189 const char *p
= opc
->args
;
8191 unsigned long used_bits
= opc
->mask
;
8193 if ((used_bits
& opc
->match
) != opc
->match
)
8195 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8196 opc
->name
, opc
->args
);
8199 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8209 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8210 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8211 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8212 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8213 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8214 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8215 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8216 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8217 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8218 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8219 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8220 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8221 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8223 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8224 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8225 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8227 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8228 c
, opc
->name
, opc
->args
);
8232 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8233 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8235 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8236 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8237 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8238 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8240 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8241 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8243 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8244 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8246 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8247 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8248 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8249 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8250 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8251 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8252 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8253 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8254 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8255 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8256 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8257 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8258 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8259 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8260 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8261 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8262 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8264 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8265 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8266 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8267 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8269 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8270 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8271 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8272 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8273 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8274 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8275 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8276 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8277 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8280 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8281 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8282 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8283 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8284 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8287 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8288 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8289 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8290 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8291 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8292 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8293 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8294 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8295 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8296 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8297 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8298 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8299 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8300 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8301 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8302 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8303 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8305 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8306 c
, opc
->name
, opc
->args
);
8310 if (used_bits
!= 0xffffffff)
8312 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8313 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8319 /* UDI immediates. */
8327 static const struct mips_immed mips_immed
[] = {
8328 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8329 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8330 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8331 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8335 /* Check whether an odd floating-point register is allowed. */
8337 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8339 const char *s
= insn
->name
;
8341 if (insn
->pinfo
== INSN_MACRO
)
8342 /* Let a macro pass, we'll catch it later when it is expanded. */
8345 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8347 /* Allow odd registers for single-precision ops. */
8348 switch (insn
->pinfo
& (FP_S
| FP_D
))
8352 return 1; /* both single precision - ok */
8354 return 0; /* both double precision - fail */
8359 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8360 s
= strchr (insn
->name
, '.');
8362 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8363 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8366 /* Single-precision coprocessor loads and moves are OK too. */
8367 if ((insn
->pinfo
& FP_S
)
8368 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8369 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8375 /* This routine assembles an instruction into its binary format. As a
8376 side effect, it sets one of the global variables imm_reloc or
8377 offset_reloc to the type of relocation to do if one of the operands
8378 is an address expression. */
8381 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8386 struct mips_opcode
*insn
;
8389 unsigned int lastregno
= 0;
8390 unsigned int lastpos
= 0;
8391 unsigned int limlo
, limhi
;
8394 offsetT min_range
, max_range
;
8400 /* If the instruction contains a '.', we first try to match an instruction
8401 including the '.'. Then we try again without the '.'. */
8403 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8406 /* If we stopped on whitespace, then replace the whitespace with null for
8407 the call to hash_find. Save the character we replaced just in case we
8408 have to re-parse the instruction. */
8415 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8417 /* If we didn't find the instruction in the opcode table, try again, but
8418 this time with just the instruction up to, but not including the
8422 /* Restore the character we overwrite above (if any). */
8426 /* Scan up to the first '.' or whitespace. */
8428 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8432 /* If we did not find a '.', then we can quit now. */
8435 insn_error
= "unrecognized opcode";
8439 /* Lookup the instruction in the hash table. */
8441 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8443 insn_error
= "unrecognized opcode";
8453 assert (strcmp (insn
->name
, str
) == 0);
8455 if (OPCODE_IS_MEMBER (insn
,
8457 /* We don't check for mips_opts.mips16 here since
8458 we want to allow jalx if -mips16 was specified
8459 on the command line. */
8460 | (file_ase_mips16
? INSN_MIPS16
: 0)
8461 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8462 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8463 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
8465 | (mips_opts
.ase_dspr2
? INSN_DSPR2
: 0)
8466 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8467 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8468 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8474 if (insn
->pinfo
!= INSN_MACRO
)
8476 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8482 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8483 && strcmp (insn
->name
, insn
[1].name
) == 0)
8492 static char buf
[100];
8494 _("opcode not supported on this processor: %s (%s)"),
8495 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8496 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8505 create_insn (ip
, insn
);
8508 for (args
= insn
->args
;; ++args
)
8512 s
+= strspn (s
, " \t");
8516 case '\0': /* end of args */
8521 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8522 my_getExpression (&imm_expr
, s
);
8523 check_absolute_expr (ip
, &imm_expr
);
8524 if ((unsigned long) imm_expr
.X_add_number
!= 1
8525 && (unsigned long) imm_expr
.X_add_number
!= 3)
8527 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8528 (unsigned long) imm_expr
.X_add_number
);
8530 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8531 imm_expr
.X_op
= O_absent
;
8535 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8536 my_getExpression (&imm_expr
, s
);
8537 check_absolute_expr (ip
, &imm_expr
);
8538 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8540 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8541 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8543 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8544 imm_expr
.X_op
= O_absent
;
8548 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8549 my_getExpression (&imm_expr
, s
);
8550 check_absolute_expr (ip
, &imm_expr
);
8551 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8553 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8554 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8556 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8557 imm_expr
.X_op
= O_absent
;
8561 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8562 my_getExpression (&imm_expr
, s
);
8563 check_absolute_expr (ip
, &imm_expr
);
8564 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8566 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8567 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8569 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8570 imm_expr
.X_op
= O_absent
;
8574 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8575 my_getExpression (&imm_expr
, s
);
8576 check_absolute_expr (ip
, &imm_expr
);
8577 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8579 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8580 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8582 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8583 imm_expr
.X_op
= O_absent
;
8587 case '7': /* four dsp accumulators in bits 11,12 */
8588 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8589 s
[3] >= '0' && s
[3] <= '3')
8593 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8597 as_bad (_("Invalid dsp acc register"));
8600 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8601 my_getExpression (&imm_expr
, s
);
8602 check_absolute_expr (ip
, &imm_expr
);
8603 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8605 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8607 (unsigned long) imm_expr
.X_add_number
);
8609 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8610 imm_expr
.X_op
= O_absent
;
8614 case '9': /* four dsp accumulators in bits 21,22 */
8615 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8616 s
[3] >= '0' && s
[3] <= '3')
8620 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8624 as_bad (_("Invalid dsp acc register"));
8627 case '0': /* dsp 6-bit signed immediate in bit 20 */
8628 my_getExpression (&imm_expr
, s
);
8629 check_absolute_expr (ip
, &imm_expr
);
8630 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8631 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8632 if (imm_expr
.X_add_number
< min_range
||
8633 imm_expr
.X_add_number
> max_range
)
8635 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8636 (long) min_range
, (long) max_range
,
8637 (long) imm_expr
.X_add_number
);
8639 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8640 imm_expr
.X_op
= O_absent
;
8644 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8645 my_getExpression (&imm_expr
, s
);
8646 check_absolute_expr (ip
, &imm_expr
);
8647 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8649 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8651 (unsigned long) imm_expr
.X_add_number
);
8653 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8654 imm_expr
.X_op
= O_absent
;
8658 case ':': /* dsp 7-bit signed immediate in bit 19 */
8659 my_getExpression (&imm_expr
, s
);
8660 check_absolute_expr (ip
, &imm_expr
);
8661 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8662 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8663 if (imm_expr
.X_add_number
< min_range
||
8664 imm_expr
.X_add_number
> max_range
)
8666 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8667 (long) min_range
, (long) max_range
,
8668 (long) imm_expr
.X_add_number
);
8670 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8671 imm_expr
.X_op
= O_absent
;
8675 case '@': /* dsp 10-bit signed immediate in bit 16 */
8676 my_getExpression (&imm_expr
, s
);
8677 check_absolute_expr (ip
, &imm_expr
);
8678 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8679 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8680 if (imm_expr
.X_add_number
< min_range
||
8681 imm_expr
.X_add_number
> max_range
)
8683 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8684 (long) min_range
, (long) max_range
,
8685 (long) imm_expr
.X_add_number
);
8687 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8688 imm_expr
.X_op
= O_absent
;
8692 case '!': /* MT usermode flag bit. */
8693 my_getExpression (&imm_expr
, s
);
8694 check_absolute_expr (ip
, &imm_expr
);
8695 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8696 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8697 (unsigned long) imm_expr
.X_add_number
);
8698 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8699 imm_expr
.X_op
= O_absent
;
8703 case '$': /* MT load high flag bit. */
8704 my_getExpression (&imm_expr
, s
);
8705 check_absolute_expr (ip
, &imm_expr
);
8706 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8707 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8708 (unsigned long) imm_expr
.X_add_number
);
8709 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8710 imm_expr
.X_op
= O_absent
;
8714 case '*': /* four dsp accumulators in bits 18,19 */
8715 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8716 s
[3] >= '0' && s
[3] <= '3')
8720 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8724 as_bad (_("Invalid dsp/smartmips acc register"));
8727 case '&': /* four dsp accumulators in bits 13,14 */
8728 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8729 s
[3] >= '0' && s
[3] <= '3')
8733 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8737 as_bad (_("Invalid dsp/smartmips acc register"));
8749 INSERT_OPERAND (RS
, *ip
, lastregno
);
8753 INSERT_OPERAND (RT
, *ip
, lastregno
);
8757 INSERT_OPERAND (FT
, *ip
, lastregno
);
8761 INSERT_OPERAND (FS
, *ip
, lastregno
);
8767 /* Handle optional base register.
8768 Either the base register is omitted or
8769 we must have a left paren. */
8770 /* This is dependent on the next operand specifier
8771 is a base register specification. */
8772 assert (args
[1] == 'b' || args
[1] == '5'
8773 || args
[1] == '-' || args
[1] == '4');
8777 case ')': /* these must match exactly */
8784 case '+': /* Opcode extension character. */
8787 case '1': /* UDI immediates. */
8792 const struct mips_immed
*imm
= mips_immed
;
8794 while (imm
->type
&& imm
->type
!= *args
)
8798 my_getExpression (&imm_expr
, s
);
8799 check_absolute_expr (ip
, &imm_expr
);
8800 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8802 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8803 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8804 (unsigned long) imm_expr
.X_add_number
,
8805 (unsigned long) imm_expr
.X_add_number
);
8806 imm_expr
.X_add_number
&= imm
->mask
;
8808 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8810 imm_expr
.X_op
= O_absent
;
8815 case 'A': /* ins/ext position, becomes LSB. */
8824 my_getExpression (&imm_expr
, s
);
8825 check_absolute_expr (ip
, &imm_expr
);
8826 if ((unsigned long) imm_expr
.X_add_number
< limlo
8827 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8829 as_bad (_("Improper position (%lu)"),
8830 (unsigned long) imm_expr
.X_add_number
);
8831 imm_expr
.X_add_number
= limlo
;
8833 lastpos
= imm_expr
.X_add_number
;
8834 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8835 imm_expr
.X_op
= O_absent
;
8839 case 'B': /* ins size, becomes MSB. */
8848 my_getExpression (&imm_expr
, s
);
8849 check_absolute_expr (ip
, &imm_expr
);
8850 /* Check for negative input so that small negative numbers
8851 will not succeed incorrectly. The checks against
8852 (pos+size) transitively check "size" itself,
8853 assuming that "pos" is reasonable. */
8854 if ((long) imm_expr
.X_add_number
< 0
8855 || ((unsigned long) imm_expr
.X_add_number
8857 || ((unsigned long) imm_expr
.X_add_number
8860 as_bad (_("Improper insert size (%lu, position %lu)"),
8861 (unsigned long) imm_expr
.X_add_number
,
8862 (unsigned long) lastpos
);
8863 imm_expr
.X_add_number
= limlo
- lastpos
;
8865 INSERT_OPERAND (INSMSB
, *ip
,
8866 lastpos
+ imm_expr
.X_add_number
- 1);
8867 imm_expr
.X_op
= O_absent
;
8871 case 'C': /* ext size, becomes MSBD. */
8884 my_getExpression (&imm_expr
, s
);
8885 check_absolute_expr (ip
, &imm_expr
);
8886 /* Check for negative input so that small negative numbers
8887 will not succeed incorrectly. The checks against
8888 (pos+size) transitively check "size" itself,
8889 assuming that "pos" is reasonable. */
8890 if ((long) imm_expr
.X_add_number
< 0
8891 || ((unsigned long) imm_expr
.X_add_number
8893 || ((unsigned long) imm_expr
.X_add_number
8896 as_bad (_("Improper extract size (%lu, position %lu)"),
8897 (unsigned long) imm_expr
.X_add_number
,
8898 (unsigned long) lastpos
);
8899 imm_expr
.X_add_number
= limlo
- lastpos
;
8901 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8902 imm_expr
.X_op
= O_absent
;
8907 /* +D is for disassembly only; never match. */
8911 /* "+I" is like "I", except that imm2_expr is used. */
8912 my_getExpression (&imm2_expr
, s
);
8913 if (imm2_expr
.X_op
!= O_big
8914 && imm2_expr
.X_op
!= O_constant
)
8915 insn_error
= _("absolute expression required");
8916 if (HAVE_32BIT_GPRS
)
8917 normalize_constant_expr (&imm2_expr
);
8921 case 'T': /* Coprocessor register. */
8922 /* +T is for disassembly only; never match. */
8925 case 't': /* Coprocessor register number. */
8926 if (s
[0] == '$' && ISDIGIT (s
[1]))
8936 while (ISDIGIT (*s
));
8938 as_bad (_("Invalid register number (%d)"), regno
);
8941 INSERT_OPERAND (RT
, *ip
, regno
);
8946 as_bad (_("Invalid coprocessor 0 register number"));
8950 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8951 *args
, insn
->name
, insn
->args
);
8952 /* Further processing is fruitless. */
8957 case '<': /* must be at least one digit */
8959 * According to the manual, if the shift amount is greater
8960 * than 31 or less than 0, then the shift amount should be
8961 * mod 32. In reality the mips assembler issues an error.
8962 * We issue a warning and mask out all but the low 5 bits.
8964 my_getExpression (&imm_expr
, s
);
8965 check_absolute_expr (ip
, &imm_expr
);
8966 if ((unsigned long) imm_expr
.X_add_number
> 31)
8967 as_warn (_("Improper shift amount (%lu)"),
8968 (unsigned long) imm_expr
.X_add_number
);
8969 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8970 imm_expr
.X_op
= O_absent
;
8974 case '>': /* shift amount minus 32 */
8975 my_getExpression (&imm_expr
, s
);
8976 check_absolute_expr (ip
, &imm_expr
);
8977 if ((unsigned long) imm_expr
.X_add_number
< 32
8978 || (unsigned long) imm_expr
.X_add_number
> 63)
8980 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8981 imm_expr
.X_op
= O_absent
;
8985 case 'k': /* cache code */
8986 case 'h': /* prefx code */
8987 my_getExpression (&imm_expr
, s
);
8988 check_absolute_expr (ip
, &imm_expr
);
8989 if ((unsigned long) imm_expr
.X_add_number
> 31)
8990 as_warn (_("Invalid value for `%s' (%lu)"),
8992 (unsigned long) imm_expr
.X_add_number
);
8994 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8996 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8997 imm_expr
.X_op
= O_absent
;
9001 case 'c': /* break code */
9002 my_getExpression (&imm_expr
, s
);
9003 check_absolute_expr (ip
, &imm_expr
);
9004 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9005 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9007 (unsigned long) imm_expr
.X_add_number
);
9008 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9009 imm_expr
.X_op
= O_absent
;
9013 case 'q': /* lower break code */
9014 my_getExpression (&imm_expr
, s
);
9015 check_absolute_expr (ip
, &imm_expr
);
9016 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9017 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9019 (unsigned long) imm_expr
.X_add_number
);
9020 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9021 imm_expr
.X_op
= O_absent
;
9025 case 'B': /* 20-bit syscall/break code. */
9026 my_getExpression (&imm_expr
, s
);
9027 check_absolute_expr (ip
, &imm_expr
);
9028 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9029 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9031 (unsigned long) imm_expr
.X_add_number
);
9032 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9033 imm_expr
.X_op
= O_absent
;
9037 case 'C': /* Coprocessor code */
9038 my_getExpression (&imm_expr
, s
);
9039 check_absolute_expr (ip
, &imm_expr
);
9040 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9042 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9043 (unsigned long) imm_expr
.X_add_number
);
9044 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9046 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9047 imm_expr
.X_op
= O_absent
;
9051 case 'J': /* 19-bit wait code. */
9052 my_getExpression (&imm_expr
, s
);
9053 check_absolute_expr (ip
, &imm_expr
);
9054 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9056 as_warn (_("Illegal 19-bit code (%lu)"),
9057 (unsigned long) imm_expr
.X_add_number
);
9058 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9060 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9061 imm_expr
.X_op
= O_absent
;
9065 case 'P': /* Performance register. */
9066 my_getExpression (&imm_expr
, s
);
9067 check_absolute_expr (ip
, &imm_expr
);
9068 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9069 as_warn (_("Invalid performance register (%lu)"),
9070 (unsigned long) imm_expr
.X_add_number
);
9071 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9072 imm_expr
.X_op
= O_absent
;
9076 case 'G': /* Coprocessor destination register. */
9077 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9078 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9080 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9081 INSERT_OPERAND (RD
, *ip
, regno
);
9090 case 'b': /* base register */
9091 case 'd': /* destination register */
9092 case 's': /* source register */
9093 case 't': /* target register */
9094 case 'r': /* both target and source */
9095 case 'v': /* both dest and source */
9096 case 'w': /* both dest and target */
9097 case 'E': /* coprocessor target register */
9098 case 'K': /* 'rdhwr' destination register */
9099 case 'x': /* ignore register name */
9100 case 'z': /* must be zero register */
9101 case 'U': /* destination register (clo/clz). */
9102 case 'g': /* coprocessor destination register */
9104 if (*args
== 'E' || *args
== 'K')
9105 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9108 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9109 if (regno
== AT
&& mips_opts
.at
)
9111 if (mips_opts
.at
== ATREG
)
9112 as_warn (_("used $at without \".set noat\""));
9114 as_warn (_("used $%u with \".set at=$%u\""),
9115 regno
, mips_opts
.at
);
9125 if (c
== 'r' || c
== 'v' || c
== 'w')
9132 /* 'z' only matches $0. */
9133 if (c
== 'z' && regno
!= 0)
9136 /* Now that we have assembled one operand, we use the args string
9137 * to figure out where it goes in the instruction. */
9144 INSERT_OPERAND (RS
, *ip
, regno
);
9150 INSERT_OPERAND (RD
, *ip
, regno
);
9153 INSERT_OPERAND (RD
, *ip
, regno
);
9154 INSERT_OPERAND (RT
, *ip
, regno
);
9159 INSERT_OPERAND (RT
, *ip
, regno
);
9162 /* This case exists because on the r3000 trunc
9163 expands into a macro which requires a gp
9164 register. On the r6000 or r4000 it is
9165 assembled into a single instruction which
9166 ignores the register. Thus the insn version
9167 is MIPS_ISA2 and uses 'x', and the macro
9168 version is MIPS_ISA1 and uses 't'. */
9171 /* This case is for the div instruction, which
9172 acts differently if the destination argument
9173 is $0. This only matches $0, and is checked
9174 outside the switch. */
9177 /* Itbl operand; not yet implemented. FIXME ?? */
9179 /* What about all other operands like 'i', which
9180 can be specified in the opcode table? */
9189 INSERT_OPERAND (RS
, *ip
, lastregno
);
9192 INSERT_OPERAND (RT
, *ip
, lastregno
);
9197 case 'O': /* MDMX alignment immediate constant. */
9198 my_getExpression (&imm_expr
, s
);
9199 check_absolute_expr (ip
, &imm_expr
);
9200 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9201 as_warn ("Improper align amount (%ld), using low bits",
9202 (long) imm_expr
.X_add_number
);
9203 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9204 imm_expr
.X_op
= O_absent
;
9208 case 'Q': /* MDMX vector, element sel, or const. */
9211 /* MDMX Immediate. */
9212 my_getExpression (&imm_expr
, s
);
9213 check_absolute_expr (ip
, &imm_expr
);
9214 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9215 as_warn (_("Invalid MDMX Immediate (%ld)"),
9216 (long) imm_expr
.X_add_number
);
9217 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9218 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9219 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9221 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9222 imm_expr
.X_op
= O_absent
;
9226 /* Not MDMX Immediate. Fall through. */
9227 case 'X': /* MDMX destination register. */
9228 case 'Y': /* MDMX source register. */
9229 case 'Z': /* MDMX target register. */
9231 case 'D': /* floating point destination register */
9232 case 'S': /* floating point source register */
9233 case 'T': /* floating point target register */
9234 case 'R': /* floating point source register */
9239 || (mips_opts
.ase_mdmx
9240 && (ip
->insn_mo
->pinfo
& FP_D
)
9241 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9242 | INSN_COPROC_MEMORY_DELAY
9243 | INSN_LOAD_COPROC_DELAY
9244 | INSN_LOAD_MEMORY_DELAY
9245 | INSN_STORE_MEMORY
))))
9248 if (reg_lookup (&s
, rtype
, ®no
))
9250 if ((regno
& 1) != 0
9252 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9253 as_warn (_("Float register should be even, was %d"),
9261 if (c
== 'V' || c
== 'W')
9272 INSERT_OPERAND (FD
, *ip
, regno
);
9277 INSERT_OPERAND (FS
, *ip
, regno
);
9280 /* This is like 'Z', but also needs to fix the MDMX
9281 vector/scalar select bits. Note that the
9282 scalar immediate case is handled above. */
9285 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9286 int max_el
= (is_qh
? 3 : 7);
9288 my_getExpression(&imm_expr
, s
);
9289 check_absolute_expr (ip
, &imm_expr
);
9291 if (imm_expr
.X_add_number
> max_el
)
9292 as_bad(_("Bad element selector %ld"),
9293 (long) imm_expr
.X_add_number
);
9294 imm_expr
.X_add_number
&= max_el
;
9295 ip
->insn_opcode
|= (imm_expr
.X_add_number
9298 imm_expr
.X_op
= O_absent
;
9300 as_warn(_("Expecting ']' found '%s'"), s
);
9306 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9307 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9310 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9317 INSERT_OPERAND (FT
, *ip
, regno
);
9320 INSERT_OPERAND (FR
, *ip
, regno
);
9330 INSERT_OPERAND (FS
, *ip
, lastregno
);
9333 INSERT_OPERAND (FT
, *ip
, lastregno
);
9339 my_getExpression (&imm_expr
, s
);
9340 if (imm_expr
.X_op
!= O_big
9341 && imm_expr
.X_op
!= O_constant
)
9342 insn_error
= _("absolute expression required");
9343 if (HAVE_32BIT_GPRS
)
9344 normalize_constant_expr (&imm_expr
);
9349 my_getExpression (&offset_expr
, s
);
9350 normalize_address_expr (&offset_expr
);
9351 *imm_reloc
= BFD_RELOC_32
;
9364 unsigned char temp
[8];
9366 unsigned int length
;
9371 /* These only appear as the last operand in an
9372 instruction, and every instruction that accepts
9373 them in any variant accepts them in all variants.
9374 This means we don't have to worry about backing out
9375 any changes if the instruction does not match.
9377 The difference between them is the size of the
9378 floating point constant and where it goes. For 'F'
9379 and 'L' the constant is 64 bits; for 'f' and 'l' it
9380 is 32 bits. Where the constant is placed is based
9381 on how the MIPS assembler does things:
9384 f -- immediate value
9387 The .lit4 and .lit8 sections are only used if
9388 permitted by the -G argument.
9390 The code below needs to know whether the target register
9391 is 32 or 64 bits wide. It relies on the fact 'f' and
9392 'F' are used with GPR-based instructions and 'l' and
9393 'L' are used with FPR-based instructions. */
9395 f64
= *args
== 'F' || *args
== 'L';
9396 using_gprs
= *args
== 'F' || *args
== 'f';
9398 save_in
= input_line_pointer
;
9399 input_line_pointer
= s
;
9400 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9402 s
= input_line_pointer
;
9403 input_line_pointer
= save_in
;
9404 if (err
!= NULL
&& *err
!= '\0')
9406 as_bad (_("Bad floating point constant: %s"), err
);
9407 memset (temp
, '\0', sizeof temp
);
9408 length
= f64
? 8 : 4;
9411 assert (length
== (unsigned) (f64
? 8 : 4));
9415 && (g_switch_value
< 4
9416 || (temp
[0] == 0 && temp
[1] == 0)
9417 || (temp
[2] == 0 && temp
[3] == 0))))
9419 imm_expr
.X_op
= O_constant
;
9420 if (! target_big_endian
)
9421 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9423 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9426 && ! mips_disable_float_construction
9427 /* Constants can only be constructed in GPRs and
9428 copied to FPRs if the GPRs are at least as wide
9429 as the FPRs. Force the constant into memory if
9430 we are using 64-bit FPRs but the GPRs are only
9433 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9434 && ((temp
[0] == 0 && temp
[1] == 0)
9435 || (temp
[2] == 0 && temp
[3] == 0))
9436 && ((temp
[4] == 0 && temp
[5] == 0)
9437 || (temp
[6] == 0 && temp
[7] == 0)))
9439 /* The value is simple enough to load with a couple of
9440 instructions. If using 32-bit registers, set
9441 imm_expr to the high order 32 bits and offset_expr to
9442 the low order 32 bits. Otherwise, set imm_expr to
9443 the entire 64 bit constant. */
9444 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9446 imm_expr
.X_op
= O_constant
;
9447 offset_expr
.X_op
= O_constant
;
9448 if (! target_big_endian
)
9450 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9451 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9455 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9456 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9458 if (offset_expr
.X_add_number
== 0)
9459 offset_expr
.X_op
= O_absent
;
9461 else if (sizeof (imm_expr
.X_add_number
) > 4)
9463 imm_expr
.X_op
= O_constant
;
9464 if (! target_big_endian
)
9465 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9467 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9471 imm_expr
.X_op
= O_big
;
9472 imm_expr
.X_add_number
= 4;
9473 if (! target_big_endian
)
9475 generic_bignum
[0] = bfd_getl16 (temp
);
9476 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9477 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9478 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9482 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9483 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9484 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9485 generic_bignum
[3] = bfd_getb16 (temp
);
9491 const char *newname
;
9494 /* Switch to the right section. */
9496 subseg
= now_subseg
;
9499 default: /* unused default case avoids warnings. */
9501 newname
= RDATA_SECTION_NAME
;
9502 if (g_switch_value
>= 8)
9506 newname
= RDATA_SECTION_NAME
;
9509 assert (g_switch_value
>= 4);
9513 new_seg
= subseg_new (newname
, (subsegT
) 0);
9515 bfd_set_section_flags (stdoutput
, new_seg
,
9520 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9521 if (IS_ELF
&& strcmp (TARGET_OS
, "elf") != 0)
9522 record_alignment (new_seg
, 4);
9524 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9526 as_bad (_("Can't use floating point insn in this section"));
9528 /* Set the argument to the current address in the
9530 offset_expr
.X_op
= O_symbol
;
9531 offset_expr
.X_add_symbol
=
9532 symbol_new ("L0\001", now_seg
,
9533 (valueT
) frag_now_fix (), frag_now
);
9534 offset_expr
.X_add_number
= 0;
9536 /* Put the floating point number into the section. */
9537 p
= frag_more ((int) length
);
9538 memcpy (p
, temp
, length
);
9540 /* Switch back to the original section. */
9541 subseg_set (seg
, subseg
);
9546 case 'i': /* 16 bit unsigned immediate */
9547 case 'j': /* 16 bit signed immediate */
9548 *imm_reloc
= BFD_RELOC_LO16
;
9549 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9552 offsetT minval
, maxval
;
9554 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9555 && strcmp (insn
->name
, insn
[1].name
) == 0);
9557 /* If the expression was written as an unsigned number,
9558 only treat it as signed if there are no more
9562 && sizeof (imm_expr
.X_add_number
) <= 4
9563 && imm_expr
.X_op
== O_constant
9564 && imm_expr
.X_add_number
< 0
9565 && imm_expr
.X_unsigned
9569 /* For compatibility with older assemblers, we accept
9570 0x8000-0xffff as signed 16-bit numbers when only
9571 signed numbers are allowed. */
9573 minval
= 0, maxval
= 0xffff;
9575 minval
= -0x8000, maxval
= 0x7fff;
9577 minval
= -0x8000, maxval
= 0xffff;
9579 if (imm_expr
.X_op
!= O_constant
9580 || imm_expr
.X_add_number
< minval
9581 || imm_expr
.X_add_number
> maxval
)
9585 if (imm_expr
.X_op
== O_constant
9586 || imm_expr
.X_op
== O_big
)
9587 as_bad (_("expression out of range"));
9593 case 'o': /* 16 bit offset */
9594 /* Check whether there is only a single bracketed expression
9595 left. If so, it must be the base register and the
9596 constant must be zero. */
9597 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9599 offset_expr
.X_op
= O_constant
;
9600 offset_expr
.X_add_number
= 0;
9604 /* If this value won't fit into a 16 bit offset, then go
9605 find a macro that will generate the 32 bit offset
9607 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9608 && (offset_expr
.X_op
!= O_constant
9609 || offset_expr
.X_add_number
>= 0x8000
9610 || offset_expr
.X_add_number
< -0x8000))
9616 case 'p': /* pc relative offset */
9617 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9618 my_getExpression (&offset_expr
, s
);
9622 case 'u': /* upper 16 bits */
9623 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9624 && imm_expr
.X_op
== O_constant
9625 && (imm_expr
.X_add_number
< 0
9626 || imm_expr
.X_add_number
>= 0x10000))
9627 as_bad (_("lui expression not in range 0..65535"));
9631 case 'a': /* 26 bit address */
9632 my_getExpression (&offset_expr
, s
);
9634 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9637 case 'N': /* 3 bit branch condition code */
9638 case 'M': /* 3 bit compare condition code */
9640 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9642 if (!reg_lookup (&s
, rtype
, ®no
))
9644 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9645 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9646 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9647 && (regno
& 1) != 0)
9648 as_warn(_("Condition code register should be even for %s, was %d"),
9650 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9651 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9652 && (regno
& 3) != 0)
9653 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9656 INSERT_OPERAND (BCC
, *ip
, regno
);
9658 INSERT_OPERAND (CCC
, *ip
, regno
);
9662 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9673 while (ISDIGIT (*s
));
9676 c
= 8; /* Invalid sel value. */
9679 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9680 ip
->insn_opcode
|= c
;
9684 /* Must be at least one digit. */
9685 my_getExpression (&imm_expr
, s
);
9686 check_absolute_expr (ip
, &imm_expr
);
9688 if ((unsigned long) imm_expr
.X_add_number
9689 > (unsigned long) OP_MASK_VECBYTE
)
9691 as_bad (_("bad byte vector index (%ld)"),
9692 (long) imm_expr
.X_add_number
);
9693 imm_expr
.X_add_number
= 0;
9696 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9697 imm_expr
.X_op
= O_absent
;
9702 my_getExpression (&imm_expr
, s
);
9703 check_absolute_expr (ip
, &imm_expr
);
9705 if ((unsigned long) imm_expr
.X_add_number
9706 > (unsigned long) OP_MASK_VECALIGN
)
9708 as_bad (_("bad byte vector index (%ld)"),
9709 (long) imm_expr
.X_add_number
);
9710 imm_expr
.X_add_number
= 0;
9713 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9714 imm_expr
.X_op
= O_absent
;
9719 as_bad (_("bad char = '%c'\n"), *args
);
9724 /* Args don't match. */
9725 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9726 !strcmp (insn
->name
, insn
[1].name
))
9730 insn_error
= _("illegal operands");
9735 insn_error
= _("illegal operands");
9740 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9742 /* This routine assembles an instruction into its binary format when
9743 assembling for the mips16. As a side effect, it sets one of the
9744 global variables imm_reloc or offset_reloc to the type of
9745 relocation to do if one of the operands is an address expression.
9746 It also sets mips16_small and mips16_ext if the user explicitly
9747 requested a small or extended instruction. */
9750 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9754 struct mips_opcode
*insn
;
9757 unsigned int lastregno
= 0;
9763 mips16_small
= FALSE
;
9766 for (s
= str
; ISLOWER (*s
); ++s
)
9778 if (s
[1] == 't' && s
[2] == ' ')
9781 mips16_small
= TRUE
;
9785 else if (s
[1] == 'e' && s
[2] == ' ')
9794 insn_error
= _("unknown opcode");
9798 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9799 mips16_small
= TRUE
;
9801 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9803 insn_error
= _("unrecognized opcode");
9812 assert (strcmp (insn
->name
, str
) == 0);
9814 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9821 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9822 && strcmp (insn
->name
, insn
[1].name
) == 0)
9831 static char buf
[100];
9833 _("opcode not supported on this processor: %s (%s)"),
9834 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9835 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9842 create_insn (ip
, insn
);
9843 imm_expr
.X_op
= O_absent
;
9844 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9845 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9846 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9847 imm2_expr
.X_op
= O_absent
;
9848 offset_expr
.X_op
= O_absent
;
9849 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9850 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9851 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9852 for (args
= insn
->args
; 1; ++args
)
9859 /* In this switch statement we call break if we did not find
9860 a match, continue if we did find a match, or return if we
9869 /* Stuff the immediate value in now, if we can. */
9870 if (imm_expr
.X_op
== O_constant
9871 && *imm_reloc
> BFD_RELOC_UNUSED
9872 && insn
->pinfo
!= INSN_MACRO
)
9876 switch (*offset_reloc
)
9878 case BFD_RELOC_MIPS16_HI16_S
:
9879 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9882 case BFD_RELOC_MIPS16_HI16
:
9883 tmp
= imm_expr
.X_add_number
>> 16;
9886 case BFD_RELOC_MIPS16_LO16
:
9887 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9891 case BFD_RELOC_UNUSED
:
9892 tmp
= imm_expr
.X_add_number
;
9898 *offset_reloc
= BFD_RELOC_UNUSED
;
9900 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9901 tmp
, TRUE
, mips16_small
,
9902 mips16_ext
, &ip
->insn_opcode
,
9903 &ip
->use_extend
, &ip
->extend
);
9904 imm_expr
.X_op
= O_absent
;
9905 *imm_reloc
= BFD_RELOC_UNUSED
;
9919 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9922 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9938 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9940 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9955 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9957 if (c
== 'v' || c
== 'w')
9960 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9962 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9973 if (c
== 'v' || c
== 'w')
9975 regno
= mips16_to_32_reg_map
[lastregno
];
9989 regno
= mips32_to_16_reg_map
[regno
];
9994 regno
= ILLEGAL_REG
;
9999 regno
= ILLEGAL_REG
;
10004 regno
= ILLEGAL_REG
;
10009 if (regno
== AT
&& mips_opts
.at
)
10011 if (mips_opts
.at
== ATREG
)
10012 as_warn (_("used $at without \".set noat\""));
10014 as_warn (_("used $%u with \".set at=$%u\""),
10015 regno
, mips_opts
.at
);
10023 if (regno
== ILLEGAL_REG
)
10030 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10034 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10037 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10040 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10046 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10049 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10050 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10060 if (strncmp (s
, "$pc", 3) == 0)
10077 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10080 if (imm_expr
.X_op
!= O_constant
)
10083 ip
->use_extend
= TRUE
;
10088 /* We need to relax this instruction. */
10089 *offset_reloc
= *imm_reloc
;
10090 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10095 *imm_reloc
= BFD_RELOC_UNUSED
;
10096 /* Fall through. */
10103 my_getExpression (&imm_expr
, s
);
10104 if (imm_expr
.X_op
== O_register
)
10106 /* What we thought was an expression turned out to
10109 if (s
[0] == '(' && args
[1] == '(')
10111 /* It looks like the expression was omitted
10112 before a register indirection, which means
10113 that the expression is implicitly zero. We
10114 still set up imm_expr, so that we handle
10115 explicit extensions correctly. */
10116 imm_expr
.X_op
= O_constant
;
10117 imm_expr
.X_add_number
= 0;
10118 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10125 /* We need to relax this instruction. */
10126 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10135 /* We use offset_reloc rather than imm_reloc for the PC
10136 relative operands. This lets macros with both
10137 immediate and address operands work correctly. */
10138 my_getExpression (&offset_expr
, s
);
10140 if (offset_expr
.X_op
== O_register
)
10143 /* We need to relax this instruction. */
10144 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10148 case '6': /* break code */
10149 my_getExpression (&imm_expr
, s
);
10150 check_absolute_expr (ip
, &imm_expr
);
10151 if ((unsigned long) imm_expr
.X_add_number
> 63)
10152 as_warn (_("Invalid value for `%s' (%lu)"),
10154 (unsigned long) imm_expr
.X_add_number
);
10155 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10156 imm_expr
.X_op
= O_absent
;
10160 case 'a': /* 26 bit address */
10161 my_getExpression (&offset_expr
, s
);
10163 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10164 ip
->insn_opcode
<<= 16;
10167 case 'l': /* register list for entry macro */
10168 case 'L': /* register list for exit macro */
10178 unsigned int freg
, reg1
, reg2
;
10180 while (*s
== ' ' || *s
== ',')
10182 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10184 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10188 as_bad (_("can't parse register list"));
10198 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10199 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10201 as_bad (_("invalid register list"));
10205 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10207 mask
&= ~ (7 << 3);
10210 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10212 mask
&= ~ (7 << 3);
10215 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10216 mask
|= (reg2
- 3) << 3;
10217 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10218 mask
|= (reg2
- 15) << 1;
10219 else if (reg1
== RA
&& reg2
== RA
)
10223 as_bad (_("invalid register list"));
10227 /* The mask is filled in in the opcode table for the
10228 benefit of the disassembler. We remove it before
10229 applying the actual mask. */
10230 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10231 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10235 case 'm': /* Register list for save insn. */
10236 case 'M': /* Register list for restore insn. */
10239 int framesz
= 0, seen_framesz
= 0;
10240 int args
= 0, statics
= 0, sregs
= 0;
10244 unsigned int reg1
, reg2
;
10246 SKIP_SPACE_TABS (s
);
10249 SKIP_SPACE_TABS (s
);
10251 my_getExpression (&imm_expr
, s
);
10252 if (imm_expr
.X_op
== O_constant
)
10254 /* Handle the frame size. */
10257 as_bad (_("more than one frame size in list"));
10261 framesz
= imm_expr
.X_add_number
;
10262 imm_expr
.X_op
= O_absent
;
10267 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10269 as_bad (_("can't parse register list"));
10281 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10284 as_bad (_("can't parse register list"));
10289 while (reg1
<= reg2
)
10291 if (reg1
>= 4 && reg1
<= 7)
10295 args
|= 1 << (reg1
- 4);
10297 /* statics $a0-$a3 */
10298 statics
|= 1 << (reg1
- 4);
10300 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10303 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10305 else if (reg1
== 31)
10307 /* Add $ra to insn. */
10312 as_bad (_("unexpected register in list"));
10320 /* Encode args/statics combination. */
10321 if (args
& statics
)
10322 as_bad (_("arg/static registers overlap"));
10323 else if (args
== 0xf)
10324 /* All $a0-$a3 are args. */
10325 opcode
|= MIPS16_ALL_ARGS
<< 16;
10326 else if (statics
== 0xf)
10327 /* All $a0-$a3 are statics. */
10328 opcode
|= MIPS16_ALL_STATICS
<< 16;
10331 int narg
= 0, nstat
= 0;
10333 /* Count arg registers. */
10340 as_bad (_("invalid arg register list"));
10342 /* Count static registers. */
10343 while (statics
& 0x8)
10345 statics
= (statics
<< 1) & 0xf;
10349 as_bad (_("invalid static register list"));
10351 /* Encode args/statics. */
10352 opcode
|= ((narg
<< 2) | nstat
) << 16;
10355 /* Encode $s0/$s1. */
10356 if (sregs
& (1 << 0)) /* $s0 */
10358 if (sregs
& (1 << 1)) /* $s1 */
10364 /* Count regs $s2-$s8. */
10372 as_bad (_("invalid static register list"));
10373 /* Encode $s2-$s8. */
10374 opcode
|= nsreg
<< 24;
10377 /* Encode frame size. */
10379 as_bad (_("missing frame size"));
10380 else if ((framesz
& 7) != 0 || framesz
< 0
10381 || framesz
> 0xff * 8)
10382 as_bad (_("invalid frame size"));
10383 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10386 opcode
|= (((framesz
& 0xf0) << 16)
10387 | (framesz
& 0x0f));
10390 /* Finally build the instruction. */
10391 if ((opcode
>> 16) != 0 || framesz
== 0)
10393 ip
->use_extend
= TRUE
;
10394 ip
->extend
= opcode
>> 16;
10396 ip
->insn_opcode
|= opcode
& 0x7f;
10400 case 'e': /* extend code */
10401 my_getExpression (&imm_expr
, s
);
10402 check_absolute_expr (ip
, &imm_expr
);
10403 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10405 as_warn (_("Invalid value for `%s' (%lu)"),
10407 (unsigned long) imm_expr
.X_add_number
);
10408 imm_expr
.X_add_number
&= 0x7ff;
10410 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10411 imm_expr
.X_op
= O_absent
;
10421 /* Args don't match. */
10422 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10423 strcmp (insn
->name
, insn
[1].name
) == 0)
10430 insn_error
= _("illegal operands");
10436 /* This structure holds information we know about a mips16 immediate
10439 struct mips16_immed_operand
10441 /* The type code used in the argument string in the opcode table. */
10443 /* The number of bits in the short form of the opcode. */
10445 /* The number of bits in the extended form of the opcode. */
10447 /* The amount by which the short form is shifted when it is used;
10448 for example, the sw instruction has a shift count of 2. */
10450 /* The amount by which the short form is shifted when it is stored
10451 into the instruction code. */
10453 /* Non-zero if the short form is unsigned. */
10455 /* Non-zero if the extended form is unsigned. */
10457 /* Non-zero if the value is PC relative. */
10461 /* The mips16 immediate operand types. */
10463 static const struct mips16_immed_operand mips16_immed_operands
[] =
10465 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10466 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10467 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10468 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10469 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10470 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10471 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10472 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10473 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10474 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10475 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10476 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10477 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10478 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10479 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10480 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10481 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10482 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10483 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10484 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10485 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10488 #define MIPS16_NUM_IMMED \
10489 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10491 /* Handle a mips16 instruction with an immediate value. This or's the
10492 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10493 whether an extended value is needed; if one is needed, it sets
10494 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10495 If SMALL is true, an unextended opcode was explicitly requested.
10496 If EXT is true, an extended opcode was explicitly requested. If
10497 WARN is true, warn if EXT does not match reality. */
10500 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10501 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10502 unsigned long *insn
, bfd_boolean
*use_extend
,
10503 unsigned short *extend
)
10505 const struct mips16_immed_operand
*op
;
10506 int mintiny
, maxtiny
;
10507 bfd_boolean needext
;
10509 op
= mips16_immed_operands
;
10510 while (op
->type
!= type
)
10513 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10518 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10521 maxtiny
= 1 << op
->nbits
;
10526 maxtiny
= (1 << op
->nbits
) - 1;
10531 mintiny
= - (1 << (op
->nbits
- 1));
10532 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10535 /* Branch offsets have an implicit 0 in the lowest bit. */
10536 if (type
== 'p' || type
== 'q')
10539 if ((val
& ((1 << op
->shift
) - 1)) != 0
10540 || val
< (mintiny
<< op
->shift
)
10541 || val
> (maxtiny
<< op
->shift
))
10546 if (warn
&& ext
&& ! needext
)
10547 as_warn_where (file
, line
,
10548 _("extended operand requested but not required"));
10549 if (small
&& needext
)
10550 as_bad_where (file
, line
, _("invalid unextended operand value"));
10552 if (small
|| (! ext
&& ! needext
))
10556 *use_extend
= FALSE
;
10557 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10558 insnval
<<= op
->op_shift
;
10563 long minext
, maxext
;
10569 maxext
= (1 << op
->extbits
) - 1;
10573 minext
= - (1 << (op
->extbits
- 1));
10574 maxext
= (1 << (op
->extbits
- 1)) - 1;
10576 if (val
< minext
|| val
> maxext
)
10577 as_bad_where (file
, line
,
10578 _("operand value out of range for instruction"));
10580 *use_extend
= TRUE
;
10581 if (op
->extbits
== 16)
10583 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10586 else if (op
->extbits
== 15)
10588 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10593 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10597 *extend
= (unsigned short) extval
;
10602 struct percent_op_match
10605 bfd_reloc_code_real_type reloc
;
10608 static const struct percent_op_match mips_percent_op
[] =
10610 {"%lo", BFD_RELOC_LO16
},
10612 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10613 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10614 {"%call16", BFD_RELOC_MIPS_CALL16
},
10615 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10616 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10617 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10618 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10619 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10620 {"%got", BFD_RELOC_MIPS_GOT16
},
10621 {"%gp_rel", BFD_RELOC_GPREL16
},
10622 {"%half", BFD_RELOC_16
},
10623 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10624 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10625 {"%neg", BFD_RELOC_MIPS_SUB
},
10626 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10627 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10628 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10629 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10630 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10631 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10632 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10634 {"%hi", BFD_RELOC_HI16_S
}
10637 static const struct percent_op_match mips16_percent_op
[] =
10639 {"%lo", BFD_RELOC_MIPS16_LO16
},
10640 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10641 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10645 /* Return true if *STR points to a relocation operator. When returning true,
10646 move *STR over the operator and store its relocation code in *RELOC.
10647 Leave both *STR and *RELOC alone when returning false. */
10650 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10652 const struct percent_op_match
*percent_op
;
10655 if (mips_opts
.mips16
)
10657 percent_op
= mips16_percent_op
;
10658 limit
= ARRAY_SIZE (mips16_percent_op
);
10662 percent_op
= mips_percent_op
;
10663 limit
= ARRAY_SIZE (mips_percent_op
);
10666 for (i
= 0; i
< limit
; i
++)
10667 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10669 int len
= strlen (percent_op
[i
].str
);
10671 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10674 *str
+= strlen (percent_op
[i
].str
);
10675 *reloc
= percent_op
[i
].reloc
;
10677 /* Check whether the output BFD supports this relocation.
10678 If not, issue an error and fall back on something safe. */
10679 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10681 as_bad ("relocation %s isn't supported by the current ABI",
10682 percent_op
[i
].str
);
10683 *reloc
= BFD_RELOC_UNUSED
;
10691 /* Parse string STR as a 16-bit relocatable operand. Store the
10692 expression in *EP and the relocations in the array starting
10693 at RELOC. Return the number of relocation operators used.
10695 On exit, EXPR_END points to the first character after the expression. */
10698 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10701 bfd_reloc_code_real_type reversed_reloc
[3];
10702 size_t reloc_index
, i
;
10703 int crux_depth
, str_depth
;
10706 /* Search for the start of the main expression, recoding relocations
10707 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10708 of the main expression and with CRUX_DEPTH containing the number
10709 of open brackets at that point. */
10716 crux_depth
= str_depth
;
10718 /* Skip over whitespace and brackets, keeping count of the number
10720 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10725 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10726 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10728 my_getExpression (ep
, crux
);
10731 /* Match every open bracket. */
10732 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10736 if (crux_depth
> 0)
10737 as_bad ("unclosed '('");
10741 if (reloc_index
!= 0)
10743 prev_reloc_op_frag
= frag_now
;
10744 for (i
= 0; i
< reloc_index
; i
++)
10745 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10748 return reloc_index
;
10752 my_getExpression (expressionS
*ep
, char *str
)
10757 save_in
= input_line_pointer
;
10758 input_line_pointer
= str
;
10760 expr_end
= input_line_pointer
;
10761 input_line_pointer
= save_in
;
10763 /* If we are in mips16 mode, and this is an expression based on `.',
10764 then we bump the value of the symbol by 1 since that is how other
10765 text symbols are handled. We don't bother to handle complex
10766 expressions, just `.' plus or minus a constant. */
10767 if (mips_opts
.mips16
10768 && ep
->X_op
== O_symbol
10769 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10770 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10771 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10772 && symbol_constant_p (ep
->X_add_symbol
)
10773 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10774 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10778 md_atof (int type
, char *litP
, int *sizeP
)
10780 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
10784 md_number_to_chars (char *buf
, valueT val
, int n
)
10786 if (target_big_endian
)
10787 number_to_chars_bigendian (buf
, val
, n
);
10789 number_to_chars_littleendian (buf
, val
, n
);
10793 static int support_64bit_objects(void)
10795 const char **list
, **l
;
10798 list
= bfd_target_list ();
10799 for (l
= list
; *l
!= NULL
; l
++)
10801 /* This is traditional mips */
10802 if (strcmp (*l
, "elf64-tradbigmips") == 0
10803 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10805 if (strcmp (*l
, "elf64-bigmips") == 0
10806 || strcmp (*l
, "elf64-littlemips") == 0)
10809 yes
= (*l
!= NULL
);
10813 #endif /* OBJ_ELF */
10815 const char *md_shortopts
= "O::g::G:";
10817 struct option md_longopts
[] =
10819 /* Options which specify architecture. */
10820 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10821 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10822 {"march", required_argument
, NULL
, OPTION_MARCH
},
10823 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10824 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10825 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10826 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10827 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10828 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10829 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10830 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10831 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10832 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10833 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10834 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10835 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10836 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10837 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10838 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10839 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10840 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10841 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10842 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10843 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10845 /* Options which specify Application Specific Extensions (ASEs). */
10846 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10847 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10848 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10849 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10850 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10851 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10852 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10853 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10854 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10855 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10856 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10857 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10858 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10859 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10860 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10861 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10862 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10863 #define OPTION_MT (OPTION_ASE_BASE + 8)
10864 {"mmt", no_argument
, NULL
, OPTION_MT
},
10865 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10866 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10867 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10868 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10869 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10870 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10871 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
10872 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
10873 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
10874 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
10876 /* Old-style architecture options. Don't add more of these. */
10877 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
10878 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10879 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10880 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10881 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10882 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10883 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10884 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10885 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10886 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10887 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10888 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10889 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10890 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10891 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10892 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10893 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10895 /* Options which enable bug fixes. */
10896 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10897 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10898 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10899 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10900 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10901 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10902 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10903 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10904 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10905 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10906 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10907 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10908 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10909 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10911 /* Miscellaneous options. */
10912 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10913 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10914 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10915 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10916 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10917 {"break", no_argument
, NULL
, OPTION_BREAK
},
10918 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10919 #define OPTION_EB (OPTION_MISC_BASE + 2)
10920 {"EB", no_argument
, NULL
, OPTION_EB
},
10921 #define OPTION_EL (OPTION_MISC_BASE + 3)
10922 {"EL", no_argument
, NULL
, OPTION_EL
},
10923 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10924 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10925 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10926 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10927 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10928 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10929 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10930 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10931 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10932 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10933 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10934 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10935 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10936 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10937 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10938 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10939 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10940 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10941 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10942 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10943 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10944 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10945 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10946 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10948 /* ELF-specific options. */
10950 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10951 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10952 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10953 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10954 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10955 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10956 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10957 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10958 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10959 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10960 #define OPTION_32 (OPTION_ELF_BASE + 4)
10961 {"32", no_argument
, NULL
, OPTION_32
},
10962 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10963 {"n32", no_argument
, NULL
, OPTION_N32
},
10964 #define OPTION_64 (OPTION_ELF_BASE + 6)
10965 {"64", no_argument
, NULL
, OPTION_64
},
10966 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10967 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10968 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10969 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10970 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10971 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10972 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10973 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10974 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10975 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10976 #endif /* OBJ_ELF */
10978 {NULL
, no_argument
, NULL
, 0}
10980 size_t md_longopts_size
= sizeof (md_longopts
);
10982 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10983 NEW_VALUE. Warn if another value was already specified. Note:
10984 we have to defer parsing the -march and -mtune arguments in order
10985 to handle 'from-abi' correctly, since the ABI might be specified
10986 in a later argument. */
10989 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10991 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10992 as_warn (_("A different %s was already specified, is now %s"),
10993 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10996 *string_ptr
= new_value
;
11000 md_parse_option (int c
, char *arg
)
11004 case OPTION_CONSTRUCT_FLOATS
:
11005 mips_disable_float_construction
= 0;
11008 case OPTION_NO_CONSTRUCT_FLOATS
:
11009 mips_disable_float_construction
= 1;
11021 target_big_endian
= 1;
11025 target_big_endian
= 0;
11031 else if (arg
[0] == '0')
11033 else if (arg
[0] == '1')
11043 mips_debug
= atoi (arg
);
11047 file_mips_isa
= ISA_MIPS1
;
11051 file_mips_isa
= ISA_MIPS2
;
11055 file_mips_isa
= ISA_MIPS3
;
11059 file_mips_isa
= ISA_MIPS4
;
11063 file_mips_isa
= ISA_MIPS5
;
11066 case OPTION_MIPS32
:
11067 file_mips_isa
= ISA_MIPS32
;
11070 case OPTION_MIPS32R2
:
11071 file_mips_isa
= ISA_MIPS32R2
;
11074 case OPTION_MIPS64R2
:
11075 file_mips_isa
= ISA_MIPS64R2
;
11078 case OPTION_MIPS64
:
11079 file_mips_isa
= ISA_MIPS64
;
11083 mips_set_option_string (&mips_tune_string
, arg
);
11087 mips_set_option_string (&mips_arch_string
, arg
);
11091 mips_set_option_string (&mips_arch_string
, "4650");
11092 mips_set_option_string (&mips_tune_string
, "4650");
11095 case OPTION_NO_M4650
:
11099 mips_set_option_string (&mips_arch_string
, "4010");
11100 mips_set_option_string (&mips_tune_string
, "4010");
11103 case OPTION_NO_M4010
:
11107 mips_set_option_string (&mips_arch_string
, "4100");
11108 mips_set_option_string (&mips_tune_string
, "4100");
11111 case OPTION_NO_M4100
:
11115 mips_set_option_string (&mips_arch_string
, "3900");
11116 mips_set_option_string (&mips_tune_string
, "3900");
11119 case OPTION_NO_M3900
:
11123 mips_opts
.ase_mdmx
= 1;
11126 case OPTION_NO_MDMX
:
11127 mips_opts
.ase_mdmx
= 0;
11131 mips_opts
.ase_dsp
= 1;
11132 mips_opts
.ase_dspr2
= 0;
11135 case OPTION_NO_DSP
:
11136 mips_opts
.ase_dsp
= 0;
11137 mips_opts
.ase_dspr2
= 0;
11141 mips_opts
.ase_dspr2
= 1;
11142 mips_opts
.ase_dsp
= 1;
11145 case OPTION_NO_DSPR2
:
11146 mips_opts
.ase_dspr2
= 0;
11147 mips_opts
.ase_dsp
= 0;
11151 mips_opts
.ase_mt
= 1;
11155 mips_opts
.ase_mt
= 0;
11158 case OPTION_MIPS16
:
11159 mips_opts
.mips16
= 1;
11160 mips_no_prev_insn ();
11163 case OPTION_NO_MIPS16
:
11164 mips_opts
.mips16
= 0;
11165 mips_no_prev_insn ();
11168 case OPTION_MIPS3D
:
11169 mips_opts
.ase_mips3d
= 1;
11172 case OPTION_NO_MIPS3D
:
11173 mips_opts
.ase_mips3d
= 0;
11176 case OPTION_SMARTMIPS
:
11177 mips_opts
.ase_smartmips
= 1;
11180 case OPTION_NO_SMARTMIPS
:
11181 mips_opts
.ase_smartmips
= 0;
11184 case OPTION_FIX_VR4120
:
11185 mips_fix_vr4120
= 1;
11188 case OPTION_NO_FIX_VR4120
:
11189 mips_fix_vr4120
= 0;
11192 case OPTION_FIX_VR4130
:
11193 mips_fix_vr4130
= 1;
11196 case OPTION_NO_FIX_VR4130
:
11197 mips_fix_vr4130
= 0;
11200 case OPTION_RELAX_BRANCH
:
11201 mips_relax_branch
= 1;
11204 case OPTION_NO_RELAX_BRANCH
:
11205 mips_relax_branch
= 0;
11208 case OPTION_MSHARED
:
11209 mips_in_shared
= TRUE
;
11212 case OPTION_MNO_SHARED
:
11213 mips_in_shared
= FALSE
;
11216 case OPTION_MSYM32
:
11217 mips_opts
.sym32
= TRUE
;
11220 case OPTION_MNO_SYM32
:
11221 mips_opts
.sym32
= FALSE
;
11225 /* When generating ELF code, we permit -KPIC and -call_shared to
11226 select SVR4_PIC, and -non_shared to select no PIC. This is
11227 intended to be compatible with Irix 5. */
11228 case OPTION_CALL_SHARED
:
11231 as_bad (_("-call_shared is supported only for ELF format"));
11234 mips_pic
= SVR4_PIC
;
11235 mips_abicalls
= TRUE
;
11238 case OPTION_NON_SHARED
:
11241 as_bad (_("-non_shared is supported only for ELF format"));
11245 mips_abicalls
= FALSE
;
11248 /* The -xgot option tells the assembler to use 32 bit offsets
11249 when accessing the got in SVR4_PIC mode. It is for Irix
11254 #endif /* OBJ_ELF */
11257 g_switch_value
= atoi (arg
);
11262 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11267 as_bad (_("-32 is supported for ELF format only"));
11270 mips_abi
= O32_ABI
;
11276 as_bad (_("-n32 is supported for ELF format only"));
11279 mips_abi
= N32_ABI
;
11285 as_bad (_("-64 is supported for ELF format only"));
11288 mips_abi
= N64_ABI
;
11289 if (!support_64bit_objects())
11290 as_fatal (_("No compiled in support for 64 bit object file format"));
11292 #endif /* OBJ_ELF */
11295 file_mips_gp32
= 1;
11299 file_mips_gp32
= 0;
11303 file_mips_fp32
= 1;
11307 file_mips_fp32
= 0;
11314 as_bad (_("-mabi is supported for ELF format only"));
11317 if (strcmp (arg
, "32") == 0)
11318 mips_abi
= O32_ABI
;
11319 else if (strcmp (arg
, "o64") == 0)
11320 mips_abi
= O64_ABI
;
11321 else if (strcmp (arg
, "n32") == 0)
11322 mips_abi
= N32_ABI
;
11323 else if (strcmp (arg
, "64") == 0)
11325 mips_abi
= N64_ABI
;
11326 if (! support_64bit_objects())
11327 as_fatal (_("No compiled in support for 64 bit object file "
11330 else if (strcmp (arg
, "eabi") == 0)
11331 mips_abi
= EABI_ABI
;
11334 as_fatal (_("invalid abi -mabi=%s"), arg
);
11338 #endif /* OBJ_ELF */
11340 case OPTION_M7000_HILO_FIX
:
11341 mips_7000_hilo_fix
= TRUE
;
11344 case OPTION_MNO_7000_HILO_FIX
:
11345 mips_7000_hilo_fix
= FALSE
;
11349 case OPTION_MDEBUG
:
11350 mips_flag_mdebug
= TRUE
;
11353 case OPTION_NO_MDEBUG
:
11354 mips_flag_mdebug
= FALSE
;
11358 mips_flag_pdr
= TRUE
;
11361 case OPTION_NO_PDR
:
11362 mips_flag_pdr
= FALSE
;
11365 case OPTION_MVXWORKS_PIC
:
11366 mips_pic
= VXWORKS_PIC
;
11368 #endif /* OBJ_ELF */
11377 /* Set up globals to generate code for the ISA or processor
11378 described by INFO. */
11381 mips_set_architecture (const struct mips_cpu_info
*info
)
11385 file_mips_arch
= info
->cpu
;
11386 mips_opts
.arch
= info
->cpu
;
11387 mips_opts
.isa
= info
->isa
;
11392 /* Likewise for tuning. */
11395 mips_set_tune (const struct mips_cpu_info
*info
)
11398 mips_tune
= info
->cpu
;
11403 mips_after_parse_args (void)
11405 const struct mips_cpu_info
*arch_info
= 0;
11406 const struct mips_cpu_info
*tune_info
= 0;
11408 /* GP relative stuff not working for PE */
11409 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11411 if (g_switch_seen
&& g_switch_value
!= 0)
11412 as_bad (_("-G not supported in this configuration."));
11413 g_switch_value
= 0;
11416 if (mips_abi
== NO_ABI
)
11417 mips_abi
= MIPS_DEFAULT_ABI
;
11419 /* The following code determines the architecture and register size.
11420 Similar code was added to GCC 3.3 (see override_options() in
11421 config/mips/mips.c). The GAS and GCC code should be kept in sync
11422 as much as possible. */
11424 if (mips_arch_string
!= 0)
11425 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11427 if (file_mips_isa
!= ISA_UNKNOWN
)
11429 /* Handle -mipsN. At this point, file_mips_isa contains the
11430 ISA level specified by -mipsN, while arch_info->isa contains
11431 the -march selection (if any). */
11432 if (arch_info
!= 0)
11434 /* -march takes precedence over -mipsN, since it is more descriptive.
11435 There's no harm in specifying both as long as the ISA levels
11437 if (file_mips_isa
!= arch_info
->isa
)
11438 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11439 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11440 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11443 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11446 if (arch_info
== 0)
11447 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11449 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11450 as_bad ("-march=%s is not compatible with the selected ABI",
11453 mips_set_architecture (arch_info
);
11455 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11456 if (mips_tune_string
!= 0)
11457 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11459 if (tune_info
== 0)
11460 mips_set_tune (arch_info
);
11462 mips_set_tune (tune_info
);
11464 if (file_mips_gp32
>= 0)
11466 /* The user specified the size of the integer registers. Make sure
11467 it agrees with the ABI and ISA. */
11468 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11469 as_bad (_("-mgp64 used with a 32-bit processor"));
11470 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11471 as_bad (_("-mgp32 used with a 64-bit ABI"));
11472 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11473 as_bad (_("-mgp64 used with a 32-bit ABI"));
11477 /* Infer the integer register size from the ABI and processor.
11478 Restrict ourselves to 32-bit registers if that's all the
11479 processor has, or if the ABI cannot handle 64-bit registers. */
11480 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11481 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11484 switch (file_mips_fp32
)
11488 /* No user specified float register size.
11489 ??? GAS treats single-float processors as though they had 64-bit
11490 float registers (although it complains when double-precision
11491 instructions are used). As things stand, saying they have 32-bit
11492 registers would lead to spurious "register must be even" messages.
11493 So here we assume float registers are never smaller than the
11495 if (file_mips_gp32
== 0)
11496 /* 64-bit integer registers implies 64-bit float registers. */
11497 file_mips_fp32
= 0;
11498 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11499 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11500 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11501 file_mips_fp32
= 0;
11503 /* 32-bit float registers. */
11504 file_mips_fp32
= 1;
11507 /* The user specified the size of the float registers. Check if it
11508 agrees with the ABI and ISA. */
11510 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11511 as_bad (_("-mfp64 used with a 32-bit fpu"));
11512 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11513 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11514 as_warn (_("-mfp64 used with a 32-bit ABI"));
11517 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11518 as_warn (_("-mfp32 used with a 64-bit ABI"));
11522 /* End of GCC-shared inference code. */
11524 /* This flag is set when we have a 64-bit capable CPU but use only
11525 32-bit wide registers. Note that EABI does not use it. */
11526 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11527 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11528 || mips_abi
== O32_ABI
))
11529 mips_32bitmode
= 1;
11531 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11532 as_bad (_("trap exception not supported at ISA 1"));
11534 /* If the selected architecture includes support for ASEs, enable
11535 generation of code for them. */
11536 if (mips_opts
.mips16
== -1)
11537 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11538 if (mips_opts
.ase_mips3d
== -1)
11539 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11540 && file_mips_fp32
== 0) ? 1 : 0;
11541 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11542 as_bad (_("-mfp32 used with -mips3d"));
11544 if (mips_opts
.ase_mdmx
== -1)
11545 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11546 && file_mips_fp32
== 0) ? 1 : 0;
11547 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11548 as_bad (_("-mfp32 used with -mdmx"));
11550 if (mips_opts
.ase_smartmips
== -1)
11551 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11552 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11553 as_warn ("%s ISA does not support SmartMIPS",
11554 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11556 if (mips_opts
.ase_dsp
== -1)
11557 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11558 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11559 as_warn ("%s ISA does not support DSP ASE",
11560 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11562 if (mips_opts
.ase_dspr2
== -1)
11564 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11565 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11567 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11568 as_warn ("%s ISA does not support DSP R2 ASE",
11569 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11571 if (mips_opts
.ase_mt
== -1)
11572 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11573 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11574 as_warn ("%s ISA does not support MT ASE",
11575 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11577 file_mips_isa
= mips_opts
.isa
;
11578 file_ase_mips16
= mips_opts
.mips16
;
11579 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11580 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11581 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11582 file_ase_dsp
= mips_opts
.ase_dsp
;
11583 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11584 file_ase_mt
= mips_opts
.ase_mt
;
11585 mips_opts
.gp32
= file_mips_gp32
;
11586 mips_opts
.fp32
= file_mips_fp32
;
11588 if (mips_flag_mdebug
< 0)
11590 #ifdef OBJ_MAYBE_ECOFF
11591 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11592 mips_flag_mdebug
= 1;
11594 #endif /* OBJ_MAYBE_ECOFF */
11595 mips_flag_mdebug
= 0;
11600 mips_init_after_args (void)
11602 /* initialize opcodes */
11603 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11604 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11608 md_pcrel_from (fixS
*fixP
)
11610 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11611 switch (fixP
->fx_r_type
)
11613 case BFD_RELOC_16_PCREL_S2
:
11614 case BFD_RELOC_MIPS_JMP
:
11615 /* Return the address of the delay slot. */
11618 /* We have no relocation type for PC relative MIPS16 instructions. */
11619 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11621 _("PC relative MIPS16 instruction references a different section"));
11626 /* This is called before the symbol table is processed. In order to
11627 work with gcc when using mips-tfile, we must keep all local labels.
11628 However, in other cases, we want to discard them. If we were
11629 called with -g, but we didn't see any debugging information, it may
11630 mean that gcc is smuggling debugging information through to
11631 mips-tfile, in which case we must generate all local labels. */
11634 mips_frob_file_before_adjust (void)
11636 #ifndef NO_ECOFF_DEBUGGING
11637 if (ECOFF_DEBUGGING
11639 && ! ecoff_debugging_seen
)
11640 flag_keep_locals
= 1;
11644 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11645 the corresponding LO16 reloc. This is called before md_apply_fix and
11646 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11647 relocation operators.
11649 For our purposes, a %lo() expression matches a %got() or %hi()
11652 (a) it refers to the same symbol; and
11653 (b) the offset applied in the %lo() expression is no lower than
11654 the offset applied in the %got() or %hi().
11656 (b) allows us to cope with code like:
11659 lh $4,%lo(foo+2)($4)
11661 ...which is legal on RELA targets, and has a well-defined behaviour
11662 if the user knows that adding 2 to "foo" will not induce a carry to
11665 When several %lo()s match a particular %got() or %hi(), we use the
11666 following rules to distinguish them:
11668 (1) %lo()s with smaller offsets are a better match than %lo()s with
11671 (2) %lo()s with no matching %got() or %hi() are better than those
11672 that already have a matching %got() or %hi().
11674 (3) later %lo()s are better than earlier %lo()s.
11676 These rules are applied in order.
11678 (1) means, among other things, that %lo()s with identical offsets are
11679 chosen if they exist.
11681 (2) means that we won't associate several high-part relocations with
11682 the same low-part relocation unless there's no alternative. Having
11683 several high parts for the same low part is a GNU extension; this rule
11684 allows careful users to avoid it.
11686 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11687 with the last high-part relocation being at the front of the list.
11688 It therefore makes sense to choose the last matching low-part
11689 relocation, all other things being equal. It's also easier
11690 to code that way. */
11693 mips_frob_file (void)
11695 struct mips_hi_fixup
*l
;
11697 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11699 segment_info_type
*seginfo
;
11700 bfd_boolean matched_lo_p
;
11701 fixS
**hi_pos
, **lo_pos
, **pos
;
11703 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11705 /* If a GOT16 relocation turns out to be against a global symbol,
11706 there isn't supposed to be a matching LO. */
11707 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11708 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11711 /* Check quickly whether the next fixup happens to be a matching %lo. */
11712 if (fixup_has_matching_lo_p (l
->fixp
))
11715 seginfo
= seg_info (l
->seg
);
11717 /* Set HI_POS to the position of this relocation in the chain.
11718 Set LO_POS to the position of the chosen low-part relocation.
11719 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11720 relocation that matches an immediately-preceding high-part
11724 matched_lo_p
= FALSE
;
11725 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11727 if (*pos
== l
->fixp
)
11730 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11731 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11732 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11733 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11735 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11737 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11740 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11741 && fixup_has_matching_lo_p (*pos
));
11744 /* If we found a match, remove the high-part relocation from its
11745 current position and insert it before the low-part relocation.
11746 Make the offsets match so that fixup_has_matching_lo_p()
11749 We don't warn about unmatched high-part relocations since some
11750 versions of gcc have been known to emit dead "lui ...%hi(...)"
11752 if (lo_pos
!= NULL
)
11754 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11755 if (l
->fixp
->fx_next
!= *lo_pos
)
11757 *hi_pos
= l
->fixp
->fx_next
;
11758 l
->fixp
->fx_next
= *lo_pos
;
11765 /* We may have combined relocations without symbols in the N32/N64 ABI.
11766 We have to prevent gas from dropping them. */
11769 mips_force_relocation (fixS
*fixp
)
11771 if (generic_force_reloc (fixp
))
11775 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11776 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11777 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11778 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11784 /* Apply a fixup to the object file. */
11787 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11791 reloc_howto_type
*howto
;
11793 /* We ignore generic BFD relocations we don't know about. */
11794 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11798 assert (fixP
->fx_size
== 4
11799 || fixP
->fx_r_type
== BFD_RELOC_16
11800 || fixP
->fx_r_type
== BFD_RELOC_64
11801 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11802 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11803 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11804 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11805 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
11807 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11809 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11811 /* Don't treat parts of a composite relocation as done. There are two
11814 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11815 should nevertheless be emitted if the first part is.
11817 (2) In normal usage, composite relocations are never assembly-time
11818 constants. The easiest way of dealing with the pathological
11819 exceptions is to generate a relocation against STN_UNDEF and
11820 leave everything up to the linker. */
11821 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11824 switch (fixP
->fx_r_type
)
11826 case BFD_RELOC_MIPS_TLS_GD
:
11827 case BFD_RELOC_MIPS_TLS_LDM
:
11828 case BFD_RELOC_MIPS_TLS_DTPREL32
:
11829 case BFD_RELOC_MIPS_TLS_DTPREL64
:
11830 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11831 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11832 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11833 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11834 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11835 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11838 case BFD_RELOC_MIPS_JMP
:
11839 case BFD_RELOC_MIPS_SHIFT5
:
11840 case BFD_RELOC_MIPS_SHIFT6
:
11841 case BFD_RELOC_MIPS_GOT_DISP
:
11842 case BFD_RELOC_MIPS_GOT_PAGE
:
11843 case BFD_RELOC_MIPS_GOT_OFST
:
11844 case BFD_RELOC_MIPS_SUB
:
11845 case BFD_RELOC_MIPS_INSERT_A
:
11846 case BFD_RELOC_MIPS_INSERT_B
:
11847 case BFD_RELOC_MIPS_DELETE
:
11848 case BFD_RELOC_MIPS_HIGHEST
:
11849 case BFD_RELOC_MIPS_HIGHER
:
11850 case BFD_RELOC_MIPS_SCN_DISP
:
11851 case BFD_RELOC_MIPS_REL16
:
11852 case BFD_RELOC_MIPS_RELGOT
:
11853 case BFD_RELOC_MIPS_JALR
:
11854 case BFD_RELOC_HI16
:
11855 case BFD_RELOC_HI16_S
:
11856 case BFD_RELOC_GPREL16
:
11857 case BFD_RELOC_MIPS_LITERAL
:
11858 case BFD_RELOC_MIPS_CALL16
:
11859 case BFD_RELOC_MIPS_GOT16
:
11860 case BFD_RELOC_GPREL32
:
11861 case BFD_RELOC_MIPS_GOT_HI16
:
11862 case BFD_RELOC_MIPS_GOT_LO16
:
11863 case BFD_RELOC_MIPS_CALL_HI16
:
11864 case BFD_RELOC_MIPS_CALL_LO16
:
11865 case BFD_RELOC_MIPS16_GPREL
:
11866 case BFD_RELOC_MIPS16_HI16
:
11867 case BFD_RELOC_MIPS16_HI16_S
:
11868 case BFD_RELOC_MIPS16_JMP
:
11869 /* Nothing needed to do. The value comes from the reloc entry. */
11873 /* This is handled like BFD_RELOC_32, but we output a sign
11874 extended value if we are only 32 bits. */
11877 if (8 <= sizeof (valueT
))
11878 md_number_to_chars ((char *) buf
, *valP
, 8);
11883 if ((*valP
& 0x80000000) != 0)
11887 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11889 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11895 case BFD_RELOC_RVA
:
11898 /* If we are deleting this reloc entry, we must fill in the
11899 value now. This can happen if we have a .word which is not
11900 resolved when it appears but is later defined. */
11902 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
11905 case BFD_RELOC_LO16
:
11906 case BFD_RELOC_MIPS16_LO16
:
11907 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11908 may be safe to remove, but if so it's not obvious. */
11909 /* When handling an embedded PIC switch statement, we can wind
11910 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11913 if (*valP
+ 0x8000 > 0xffff)
11914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11915 _("relocation overflow"));
11916 if (target_big_endian
)
11918 md_number_to_chars ((char *) buf
, *valP
, 2);
11922 case BFD_RELOC_16_PCREL_S2
:
11923 if ((*valP
& 0x3) != 0)
11924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11925 _("Branch to misaligned address (%lx)"), (long) *valP
);
11927 /* We need to save the bits in the instruction since fixup_segment()
11928 might be deleting the relocation entry (i.e., a branch within
11929 the current segment). */
11930 if (! fixP
->fx_done
)
11933 /* Update old instruction data. */
11934 if (target_big_endian
)
11935 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11937 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11939 if (*valP
+ 0x20000 <= 0x3ffff)
11941 insn
|= (*valP
>> 2) & 0xffff;
11942 md_number_to_chars ((char *) buf
, insn
, 4);
11944 else if (mips_pic
== NO_PIC
11946 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11947 && (fixP
->fx_frag
->fr_address
11948 < text_section
->vma
+ bfd_get_section_size (text_section
))
11949 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11950 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11951 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11953 /* The branch offset is too large. If this is an
11954 unconditional branch, and we are not generating PIC code,
11955 we can convert it to an absolute jump instruction. */
11956 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11957 insn
= 0x0c000000; /* jal */
11959 insn
= 0x08000000; /* j */
11960 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11962 fixP
->fx_addsy
= section_symbol (text_section
);
11963 *valP
+= md_pcrel_from (fixP
);
11964 md_number_to_chars ((char *) buf
, insn
, 4);
11968 /* If we got here, we have branch-relaxation disabled,
11969 and there's nothing we can do to fix this instruction
11970 without turning it into a longer sequence. */
11971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11972 _("Branch out of range"));
11976 case BFD_RELOC_VTABLE_INHERIT
:
11979 && !S_IS_DEFINED (fixP
->fx_addsy
)
11980 && !S_IS_WEAK (fixP
->fx_addsy
))
11981 S_SET_WEAK (fixP
->fx_addsy
);
11984 case BFD_RELOC_VTABLE_ENTRY
:
11992 /* Remember value for tc_gen_reloc. */
11993 fixP
->fx_addnumber
= *valP
;
12003 name
= input_line_pointer
;
12004 c
= get_symbol_end ();
12005 p
= (symbolS
*) symbol_find_or_make (name
);
12006 *input_line_pointer
= c
;
12010 /* Align the current frag to a given power of two. If a particular
12011 fill byte should be used, FILL points to an integer that contains
12012 that byte, otherwise FILL is null.
12014 The MIPS assembler also automatically adjusts any preceding
12018 mips_align (int to
, int *fill
, symbolS
*label
)
12020 mips_emit_delays ();
12021 mips_record_mips16_mode ();
12022 if (fill
== NULL
&& subseg_text_p (now_seg
))
12023 frag_align_code (to
, 0);
12025 frag_align (to
, fill
? *fill
: 0, 0);
12026 record_alignment (now_seg
, to
);
12029 assert (S_GET_SEGMENT (label
) == now_seg
);
12030 symbol_set_frag (label
, frag_now
);
12031 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12035 /* Align to a given power of two. .align 0 turns off the automatic
12036 alignment used by the data creating pseudo-ops. */
12039 s_align (int x ATTRIBUTE_UNUSED
)
12041 int temp
, fill_value
, *fill_ptr
;
12042 long max_alignment
= 28;
12044 /* o Note that the assembler pulls down any immediately preceding label
12045 to the aligned address.
12046 o It's not documented but auto alignment is reinstated by
12047 a .align pseudo instruction.
12048 o Note also that after auto alignment is turned off the mips assembler
12049 issues an error on attempt to assemble an improperly aligned data item.
12052 temp
= get_absolute_expression ();
12053 if (temp
> max_alignment
)
12054 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12057 as_warn (_("Alignment negative: 0 assumed."));
12060 if (*input_line_pointer
== ',')
12062 ++input_line_pointer
;
12063 fill_value
= get_absolute_expression ();
12064 fill_ptr
= &fill_value
;
12070 segment_info_type
*si
= seg_info (now_seg
);
12071 struct insn_label_list
*l
= si
->label_list
;
12072 /* Auto alignment should be switched on by next section change. */
12074 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12081 demand_empty_rest_of_line ();
12085 s_change_sec (int sec
)
12090 /* The ELF backend needs to know that we are changing sections, so
12091 that .previous works correctly. We could do something like check
12092 for an obj_section_change_hook macro, but that might be confusing
12093 as it would not be appropriate to use it in the section changing
12094 functions in read.c, since obj-elf.c intercepts those. FIXME:
12095 This should be cleaner, somehow. */
12097 obj_elf_section_change_hook ();
12100 mips_emit_delays ();
12110 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12111 demand_empty_rest_of_line ();
12115 seg
= subseg_new (RDATA_SECTION_NAME
,
12116 (subsegT
) get_absolute_expression ());
12119 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12120 | SEC_READONLY
| SEC_RELOC
12122 if (strcmp (TARGET_OS
, "elf") != 0)
12123 record_alignment (seg
, 4);
12125 demand_empty_rest_of_line ();
12129 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12132 bfd_set_section_flags (stdoutput
, seg
,
12133 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12134 if (strcmp (TARGET_OS
, "elf") != 0)
12135 record_alignment (seg
, 4);
12137 demand_empty_rest_of_line ();
12145 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12148 char *section_name
;
12153 int section_entry_size
;
12154 int section_alignment
;
12159 section_name
= input_line_pointer
;
12160 c
= get_symbol_end ();
12162 next_c
= *(input_line_pointer
+ 1);
12164 /* Do we have .section Name<,"flags">? */
12165 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12167 /* just after name is now '\0'. */
12168 *input_line_pointer
= c
;
12169 input_line_pointer
= section_name
;
12170 obj_elf_section (ignore
);
12173 input_line_pointer
++;
12175 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12177 section_type
= get_absolute_expression ();
12180 if (*input_line_pointer
++ == ',')
12181 section_flag
= get_absolute_expression ();
12184 if (*input_line_pointer
++ == ',')
12185 section_entry_size
= get_absolute_expression ();
12187 section_entry_size
= 0;
12188 if (*input_line_pointer
++ == ',')
12189 section_alignment
= get_absolute_expression ();
12191 section_alignment
= 0;
12193 section_name
= xstrdup (section_name
);
12195 /* When using the generic form of .section (as implemented by obj-elf.c),
12196 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12197 traditionally had to fall back on the more common @progbits instead.
12199 There's nothing really harmful in this, since bfd will correct
12200 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12201 means that, for backwards compatibility, the special_section entries
12202 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12204 Even so, we shouldn't force users of the MIPS .section syntax to
12205 incorrectly label the sections as SHT_PROGBITS. The best compromise
12206 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12207 generic type-checking code. */
12208 if (section_type
== SHT_MIPS_DWARF
)
12209 section_type
= SHT_PROGBITS
;
12211 obj_elf_change_section (section_name
, section_type
, section_flag
,
12212 section_entry_size
, 0, 0, 0);
12214 if (now_seg
->name
!= section_name
)
12215 free (section_name
);
12216 #endif /* OBJ_ELF */
12220 mips_enable_auto_align (void)
12226 s_cons (int log_size
)
12228 segment_info_type
*si
= seg_info (now_seg
);
12229 struct insn_label_list
*l
= si
->label_list
;
12232 label
= l
!= NULL
? l
->label
: NULL
;
12233 mips_emit_delays ();
12234 if (log_size
> 0 && auto_align
)
12235 mips_align (log_size
, 0, label
);
12236 mips_clear_insn_labels ();
12237 cons (1 << log_size
);
12241 s_float_cons (int type
)
12243 segment_info_type
*si
= seg_info (now_seg
);
12244 struct insn_label_list
*l
= si
->label_list
;
12247 label
= l
!= NULL
? l
->label
: NULL
;
12249 mips_emit_delays ();
12254 mips_align (3, 0, label
);
12256 mips_align (2, 0, label
);
12259 mips_clear_insn_labels ();
12264 /* Handle .globl. We need to override it because on Irix 5 you are
12267 where foo is an undefined symbol, to mean that foo should be
12268 considered to be the address of a function. */
12271 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12280 name
= input_line_pointer
;
12281 c
= get_symbol_end ();
12282 symbolP
= symbol_find_or_make (name
);
12283 S_SET_EXTERNAL (symbolP
);
12285 *input_line_pointer
= c
;
12286 SKIP_WHITESPACE ();
12288 /* On Irix 5, every global symbol that is not explicitly labelled as
12289 being a function is apparently labelled as being an object. */
12292 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12293 && (*input_line_pointer
!= ','))
12298 secname
= input_line_pointer
;
12299 c
= get_symbol_end ();
12300 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12302 as_bad (_("%s: no such section"), secname
);
12303 *input_line_pointer
= c
;
12305 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12306 flag
= BSF_FUNCTION
;
12309 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12311 c
= *input_line_pointer
;
12314 input_line_pointer
++;
12315 SKIP_WHITESPACE ();
12316 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12322 demand_empty_rest_of_line ();
12326 s_option (int x ATTRIBUTE_UNUSED
)
12331 opt
= input_line_pointer
;
12332 c
= get_symbol_end ();
12336 /* FIXME: What does this mean? */
12338 else if (strncmp (opt
, "pic", 3) == 0)
12342 i
= atoi (opt
+ 3);
12347 mips_pic
= SVR4_PIC
;
12348 mips_abicalls
= TRUE
;
12351 as_bad (_(".option pic%d not supported"), i
);
12353 if (mips_pic
== SVR4_PIC
)
12355 if (g_switch_seen
&& g_switch_value
!= 0)
12356 as_warn (_("-G may not be used with SVR4 PIC code"));
12357 g_switch_value
= 0;
12358 bfd_set_gp_size (stdoutput
, 0);
12362 as_warn (_("Unrecognized option \"%s\""), opt
);
12364 *input_line_pointer
= c
;
12365 demand_empty_rest_of_line ();
12368 /* This structure is used to hold a stack of .set values. */
12370 struct mips_option_stack
12372 struct mips_option_stack
*next
;
12373 struct mips_set_options options
;
12376 static struct mips_option_stack
*mips_opts_stack
;
12378 /* Handle the .set pseudo-op. */
12381 s_mipsset (int x ATTRIBUTE_UNUSED
)
12383 char *name
= input_line_pointer
, ch
;
12385 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12386 ++input_line_pointer
;
12387 ch
= *input_line_pointer
;
12388 *input_line_pointer
= '\0';
12390 if (strcmp (name
, "reorder") == 0)
12392 if (mips_opts
.noreorder
)
12395 else if (strcmp (name
, "noreorder") == 0)
12397 if (!mips_opts
.noreorder
)
12398 start_noreorder ();
12400 else if (strncmp (name
, "at=", 3) == 0)
12402 char *s
= name
+ 3;
12404 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12405 as_bad (_("Unrecognized register name `%s'"), s
);
12407 else if (strcmp (name
, "at") == 0)
12409 mips_opts
.at
= ATREG
;
12411 else if (strcmp (name
, "noat") == 0)
12413 mips_opts
.at
= ZERO
;
12415 else if (strcmp (name
, "macro") == 0)
12417 mips_opts
.warn_about_macros
= 0;
12419 else if (strcmp (name
, "nomacro") == 0)
12421 if (mips_opts
.noreorder
== 0)
12422 as_bad (_("`noreorder' must be set before `nomacro'"));
12423 mips_opts
.warn_about_macros
= 1;
12425 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12427 mips_opts
.nomove
= 0;
12429 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12431 mips_opts
.nomove
= 1;
12433 else if (strcmp (name
, "bopt") == 0)
12435 mips_opts
.nobopt
= 0;
12437 else if (strcmp (name
, "nobopt") == 0)
12439 mips_opts
.nobopt
= 1;
12441 else if (strcmp (name
, "gp=default") == 0)
12442 mips_opts
.gp32
= file_mips_gp32
;
12443 else if (strcmp (name
, "gp=32") == 0)
12444 mips_opts
.gp32
= 1;
12445 else if (strcmp (name
, "gp=64") == 0)
12447 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12448 as_warn ("%s isa does not support 64-bit registers",
12449 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12450 mips_opts
.gp32
= 0;
12452 else if (strcmp (name
, "fp=default") == 0)
12453 mips_opts
.fp32
= file_mips_fp32
;
12454 else if (strcmp (name
, "fp=32") == 0)
12455 mips_opts
.fp32
= 1;
12456 else if (strcmp (name
, "fp=64") == 0)
12458 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12459 as_warn ("%s isa does not support 64-bit floating point registers",
12460 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12461 mips_opts
.fp32
= 0;
12463 else if (strcmp (name
, "mips16") == 0
12464 || strcmp (name
, "MIPS-16") == 0)
12465 mips_opts
.mips16
= 1;
12466 else if (strcmp (name
, "nomips16") == 0
12467 || strcmp (name
, "noMIPS-16") == 0)
12468 mips_opts
.mips16
= 0;
12469 else if (strcmp (name
, "smartmips") == 0)
12471 if (!ISA_SUPPORTS_SMARTMIPS
)
12472 as_warn ("%s ISA does not support SmartMIPS ASE",
12473 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12474 mips_opts
.ase_smartmips
= 1;
12476 else if (strcmp (name
, "nosmartmips") == 0)
12477 mips_opts
.ase_smartmips
= 0;
12478 else if (strcmp (name
, "mips3d") == 0)
12479 mips_opts
.ase_mips3d
= 1;
12480 else if (strcmp (name
, "nomips3d") == 0)
12481 mips_opts
.ase_mips3d
= 0;
12482 else if (strcmp (name
, "mdmx") == 0)
12483 mips_opts
.ase_mdmx
= 1;
12484 else if (strcmp (name
, "nomdmx") == 0)
12485 mips_opts
.ase_mdmx
= 0;
12486 else if (strcmp (name
, "dsp") == 0)
12488 if (!ISA_SUPPORTS_DSP_ASE
)
12489 as_warn ("%s ISA does not support DSP ASE",
12490 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12491 mips_opts
.ase_dsp
= 1;
12492 mips_opts
.ase_dspr2
= 0;
12494 else if (strcmp (name
, "nodsp") == 0)
12496 mips_opts
.ase_dsp
= 0;
12497 mips_opts
.ase_dspr2
= 0;
12499 else if (strcmp (name
, "dspr2") == 0)
12501 if (!ISA_SUPPORTS_DSPR2_ASE
)
12502 as_warn ("%s ISA does not support DSP R2 ASE",
12503 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12504 mips_opts
.ase_dspr2
= 1;
12505 mips_opts
.ase_dsp
= 1;
12507 else if (strcmp (name
, "nodspr2") == 0)
12509 mips_opts
.ase_dspr2
= 0;
12510 mips_opts
.ase_dsp
= 0;
12512 else if (strcmp (name
, "mt") == 0)
12514 if (!ISA_SUPPORTS_MT_ASE
)
12515 as_warn ("%s ISA does not support MT ASE",
12516 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12517 mips_opts
.ase_mt
= 1;
12519 else if (strcmp (name
, "nomt") == 0)
12520 mips_opts
.ase_mt
= 0;
12521 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12525 /* Permit the user to change the ISA and architecture on the fly.
12526 Needless to say, misuse can cause serious problems. */
12527 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12530 mips_opts
.isa
= file_mips_isa
;
12531 mips_opts
.arch
= file_mips_arch
;
12533 else if (strncmp (name
, "arch=", 5) == 0)
12535 const struct mips_cpu_info
*p
;
12537 p
= mips_parse_cpu("internal use", name
+ 5);
12539 as_bad (_("unknown architecture %s"), name
+ 5);
12542 mips_opts
.arch
= p
->cpu
;
12543 mips_opts
.isa
= p
->isa
;
12546 else if (strncmp (name
, "mips", 4) == 0)
12548 const struct mips_cpu_info
*p
;
12550 p
= mips_parse_cpu("internal use", name
);
12552 as_bad (_("unknown ISA level %s"), name
+ 4);
12555 mips_opts
.arch
= p
->cpu
;
12556 mips_opts
.isa
= p
->isa
;
12560 as_bad (_("unknown ISA or architecture %s"), name
);
12562 switch (mips_opts
.isa
)
12570 mips_opts
.gp32
= 1;
12571 mips_opts
.fp32
= 1;
12578 mips_opts
.gp32
= 0;
12579 mips_opts
.fp32
= 0;
12582 as_bad (_("unknown ISA level %s"), name
+ 4);
12587 mips_opts
.gp32
= file_mips_gp32
;
12588 mips_opts
.fp32
= file_mips_fp32
;
12591 else if (strcmp (name
, "autoextend") == 0)
12592 mips_opts
.noautoextend
= 0;
12593 else if (strcmp (name
, "noautoextend") == 0)
12594 mips_opts
.noautoextend
= 1;
12595 else if (strcmp (name
, "push") == 0)
12597 struct mips_option_stack
*s
;
12599 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12600 s
->next
= mips_opts_stack
;
12601 s
->options
= mips_opts
;
12602 mips_opts_stack
= s
;
12604 else if (strcmp (name
, "pop") == 0)
12606 struct mips_option_stack
*s
;
12608 s
= mips_opts_stack
;
12610 as_bad (_(".set pop with no .set push"));
12613 /* If we're changing the reorder mode we need to handle
12614 delay slots correctly. */
12615 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12616 start_noreorder ();
12617 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12620 mips_opts
= s
->options
;
12621 mips_opts_stack
= s
->next
;
12625 else if (strcmp (name
, "sym32") == 0)
12626 mips_opts
.sym32
= TRUE
;
12627 else if (strcmp (name
, "nosym32") == 0)
12628 mips_opts
.sym32
= FALSE
;
12629 else if (strchr (name
, ','))
12631 /* Generic ".set" directive; use the generic handler. */
12632 *input_line_pointer
= ch
;
12633 input_line_pointer
= name
;
12639 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12641 *input_line_pointer
= ch
;
12642 demand_empty_rest_of_line ();
12645 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12646 .option pic2. It means to generate SVR4 PIC calls. */
12649 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12651 mips_pic
= SVR4_PIC
;
12652 mips_abicalls
= TRUE
;
12654 if (g_switch_seen
&& g_switch_value
!= 0)
12655 as_warn (_("-G may not be used with SVR4 PIC code"));
12656 g_switch_value
= 0;
12658 bfd_set_gp_size (stdoutput
, 0);
12659 demand_empty_rest_of_line ();
12662 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12663 PIC code. It sets the $gp register for the function based on the
12664 function address, which is in the register named in the argument.
12665 This uses a relocation against _gp_disp, which is handled specially
12666 by the linker. The result is:
12667 lui $gp,%hi(_gp_disp)
12668 addiu $gp,$gp,%lo(_gp_disp)
12669 addu $gp,$gp,.cpload argument
12670 The .cpload argument is normally $25 == $t9.
12672 The -mno-shared option changes this to:
12673 lui $gp,%hi(__gnu_local_gp)
12674 addiu $gp,$gp,%lo(__gnu_local_gp)
12675 and the argument is ignored. This saves an instruction, but the
12676 resulting code is not position independent; it uses an absolute
12677 address for __gnu_local_gp. Thus code assembled with -mno-shared
12678 can go into an ordinary executable, but not into a shared library. */
12681 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12687 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12688 .cpload is ignored. */
12689 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12695 /* .cpload should be in a .set noreorder section. */
12696 if (mips_opts
.noreorder
== 0)
12697 as_warn (_(".cpload not in noreorder section"));
12699 reg
= tc_get_register (0);
12701 /* If we need to produce a 64-bit address, we are better off using
12702 the default instruction sequence. */
12703 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12705 ex
.X_op
= O_symbol
;
12706 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12708 ex
.X_op_symbol
= NULL
;
12709 ex
.X_add_number
= 0;
12711 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12712 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12715 macro_build_lui (&ex
, mips_gp_register
);
12716 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12717 mips_gp_register
, BFD_RELOC_LO16
);
12719 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12720 mips_gp_register
, reg
);
12723 demand_empty_rest_of_line ();
12726 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12727 .cpsetup $reg1, offset|$reg2, label
12729 If offset is given, this results in:
12730 sd $gp, offset($sp)
12731 lui $gp, %hi(%neg(%gp_rel(label)))
12732 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12733 daddu $gp, $gp, $reg1
12735 If $reg2 is given, this results in:
12736 daddu $reg2, $gp, $0
12737 lui $gp, %hi(%neg(%gp_rel(label)))
12738 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12739 daddu $gp, $gp, $reg1
12740 $reg1 is normally $25 == $t9.
12742 The -mno-shared option replaces the last three instructions with
12744 addiu $gp,$gp,%lo(_gp) */
12747 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12749 expressionS ex_off
;
12750 expressionS ex_sym
;
12753 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12754 We also need NewABI support. */
12755 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12761 reg1
= tc_get_register (0);
12762 SKIP_WHITESPACE ();
12763 if (*input_line_pointer
!= ',')
12765 as_bad (_("missing argument separator ',' for .cpsetup"));
12769 ++input_line_pointer
;
12770 SKIP_WHITESPACE ();
12771 if (*input_line_pointer
== '$')
12773 mips_cpreturn_register
= tc_get_register (0);
12774 mips_cpreturn_offset
= -1;
12778 mips_cpreturn_offset
= get_absolute_expression ();
12779 mips_cpreturn_register
= -1;
12781 SKIP_WHITESPACE ();
12782 if (*input_line_pointer
!= ',')
12784 as_bad (_("missing argument separator ',' for .cpsetup"));
12788 ++input_line_pointer
;
12789 SKIP_WHITESPACE ();
12790 expression (&ex_sym
);
12793 if (mips_cpreturn_register
== -1)
12795 ex_off
.X_op
= O_constant
;
12796 ex_off
.X_add_symbol
= NULL
;
12797 ex_off
.X_op_symbol
= NULL
;
12798 ex_off
.X_add_number
= mips_cpreturn_offset
;
12800 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12801 BFD_RELOC_LO16
, SP
);
12804 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12805 mips_gp_register
, 0);
12807 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12809 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12810 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12813 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12814 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12815 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12817 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12818 mips_gp_register
, reg1
);
12824 ex
.X_op
= O_symbol
;
12825 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12826 ex
.X_op_symbol
= NULL
;
12827 ex
.X_add_number
= 0;
12829 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12830 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12832 macro_build_lui (&ex
, mips_gp_register
);
12833 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12834 mips_gp_register
, BFD_RELOC_LO16
);
12839 demand_empty_rest_of_line ();
12843 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12845 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12846 .cplocal is ignored. */
12847 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12853 mips_gp_register
= tc_get_register (0);
12854 demand_empty_rest_of_line ();
12857 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12858 offset from $sp. The offset is remembered, and after making a PIC
12859 call $gp is restored from that location. */
12862 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12866 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12867 .cprestore is ignored. */
12868 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12874 mips_cprestore_offset
= get_absolute_expression ();
12875 mips_cprestore_valid
= 1;
12877 ex
.X_op
= O_constant
;
12878 ex
.X_add_symbol
= NULL
;
12879 ex
.X_op_symbol
= NULL
;
12880 ex
.X_add_number
= mips_cprestore_offset
;
12883 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12884 SP
, HAVE_64BIT_ADDRESSES
);
12887 demand_empty_rest_of_line ();
12890 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12891 was given in the preceding .cpsetup, it results in:
12892 ld $gp, offset($sp)
12894 If a register $reg2 was given there, it results in:
12895 daddu $gp, $reg2, $0 */
12898 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12902 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12903 We also need NewABI support. */
12904 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12911 if (mips_cpreturn_register
== -1)
12913 ex
.X_op
= O_constant
;
12914 ex
.X_add_symbol
= NULL
;
12915 ex
.X_op_symbol
= NULL
;
12916 ex
.X_add_number
= mips_cpreturn_offset
;
12918 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12921 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12922 mips_cpreturn_register
, 0);
12925 demand_empty_rest_of_line ();
12928 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
12929 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
12930 use in DWARF debug information. */
12933 s_dtprel_internal (size_t bytes
)
12940 if (ex
.X_op
!= O_symbol
)
12942 as_bad (_("Unsupported use of %s"), (bytes
== 8
12945 ignore_rest_of_line ();
12948 p
= frag_more (bytes
);
12949 md_number_to_chars (p
, 0, bytes
);
12950 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
12952 ? BFD_RELOC_MIPS_TLS_DTPREL64
12953 : BFD_RELOC_MIPS_TLS_DTPREL32
));
12955 demand_empty_rest_of_line ();
12958 /* Handle .dtprelword. */
12961 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
12963 s_dtprel_internal (4);
12966 /* Handle .dtpreldword. */
12969 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
12971 s_dtprel_internal (8);
12974 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12975 code. It sets the offset to use in gp_rel relocations. */
12978 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12980 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12981 We also need NewABI support. */
12982 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12988 mips_gprel_offset
= get_absolute_expression ();
12990 demand_empty_rest_of_line ();
12993 /* Handle the .gpword pseudo-op. This is used when generating PIC
12994 code. It generates a 32 bit GP relative reloc. */
12997 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12999 segment_info_type
*si
;
13000 struct insn_label_list
*l
;
13005 /* When not generating PIC code, this is treated as .word. */
13006 if (mips_pic
!= SVR4_PIC
)
13012 si
= seg_info (now_seg
);
13013 l
= si
->label_list
;
13014 label
= l
!= NULL
? l
->label
: NULL
;
13015 mips_emit_delays ();
13017 mips_align (2, 0, label
);
13018 mips_clear_insn_labels ();
13022 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13024 as_bad (_("Unsupported use of .gpword"));
13025 ignore_rest_of_line ();
13029 md_number_to_chars (p
, 0, 4);
13030 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13031 BFD_RELOC_GPREL32
);
13033 demand_empty_rest_of_line ();
13037 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13039 segment_info_type
*si
;
13040 struct insn_label_list
*l
;
13045 /* When not generating PIC code, this is treated as .dword. */
13046 if (mips_pic
!= SVR4_PIC
)
13052 si
= seg_info (now_seg
);
13053 l
= si
->label_list
;
13054 label
= l
!= NULL
? l
->label
: NULL
;
13055 mips_emit_delays ();
13057 mips_align (3, 0, label
);
13058 mips_clear_insn_labels ();
13062 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13064 as_bad (_("Unsupported use of .gpdword"));
13065 ignore_rest_of_line ();
13069 md_number_to_chars (p
, 0, 8);
13070 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13071 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13073 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13074 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13075 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13077 demand_empty_rest_of_line ();
13080 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13081 tables in SVR4 PIC code. */
13084 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13088 /* This is ignored when not generating SVR4 PIC code. */
13089 if (mips_pic
!= SVR4_PIC
)
13095 /* Add $gp to the register named as an argument. */
13097 reg
= tc_get_register (0);
13098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13101 demand_empty_rest_of_line ();
13104 /* Handle the .insn pseudo-op. This marks instruction labels in
13105 mips16 mode. This permits the linker to handle them specially,
13106 such as generating jalx instructions when needed. We also make
13107 them odd for the duration of the assembly, in order to generate the
13108 right sort of code. We will make them even in the adjust_symtab
13109 routine, while leaving them marked. This is convenient for the
13110 debugger and the disassembler. The linker knows to make them odd
13114 s_insn (int ignore ATTRIBUTE_UNUSED
)
13116 mips16_mark_labels ();
13118 demand_empty_rest_of_line ();
13121 /* Handle a .stabn directive. We need these in order to mark a label
13122 as being a mips16 text label correctly. Sometimes the compiler
13123 will emit a label, followed by a .stabn, and then switch sections.
13124 If the label and .stabn are in mips16 mode, then the label is
13125 really a mips16 text label. */
13128 s_mips_stab (int type
)
13131 mips16_mark_labels ();
13136 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13139 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13146 name
= input_line_pointer
;
13147 c
= get_symbol_end ();
13148 symbolP
= symbol_find_or_make (name
);
13149 S_SET_WEAK (symbolP
);
13150 *input_line_pointer
= c
;
13152 SKIP_WHITESPACE ();
13154 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13156 if (S_IS_DEFINED (symbolP
))
13158 as_bad ("ignoring attempt to redefine symbol %s",
13159 S_GET_NAME (symbolP
));
13160 ignore_rest_of_line ();
13164 if (*input_line_pointer
== ',')
13166 ++input_line_pointer
;
13167 SKIP_WHITESPACE ();
13171 if (exp
.X_op
!= O_symbol
)
13173 as_bad ("bad .weakext directive");
13174 ignore_rest_of_line ();
13177 symbol_set_value_expression (symbolP
, &exp
);
13180 demand_empty_rest_of_line ();
13183 /* Parse a register string into a number. Called from the ECOFF code
13184 to parse .frame. The argument is non-zero if this is the frame
13185 register, so that we can record it in mips_frame_reg. */
13188 tc_get_register (int frame
)
13192 SKIP_WHITESPACE ();
13193 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13197 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13198 mips_frame_reg_valid
= 1;
13199 mips_cprestore_valid
= 0;
13205 md_section_align (asection
*seg
, valueT addr
)
13207 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13211 /* We don't need to align ELF sections to the full alignment.
13212 However, Irix 5 may prefer that we align them at least to a 16
13213 byte boundary. We don't bother to align the sections if we
13214 are targeted for an embedded system. */
13215 if (strcmp (TARGET_OS
, "elf") == 0)
13221 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13224 /* Utility routine, called from above as well. If called while the
13225 input file is still being read, it's only an approximation. (For
13226 example, a symbol may later become defined which appeared to be
13227 undefined earlier.) */
13230 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13235 if (g_switch_value
> 0)
13237 const char *symname
;
13240 /* Find out whether this symbol can be referenced off the $gp
13241 register. It can be if it is smaller than the -G size or if
13242 it is in the .sdata or .sbss section. Certain symbols can
13243 not be referenced off the $gp, although it appears as though
13245 symname
= S_GET_NAME (sym
);
13246 if (symname
!= (const char *) NULL
13247 && (strcmp (symname
, "eprol") == 0
13248 || strcmp (symname
, "etext") == 0
13249 || strcmp (symname
, "_gp") == 0
13250 || strcmp (symname
, "edata") == 0
13251 || strcmp (symname
, "_fbss") == 0
13252 || strcmp (symname
, "_fdata") == 0
13253 || strcmp (symname
, "_ftext") == 0
13254 || strcmp (symname
, "end") == 0
13255 || strcmp (symname
, "_gp_disp") == 0))
13257 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13259 #ifndef NO_ECOFF_DEBUGGING
13260 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13261 && (symbol_get_obj (sym
)->ecoff_extern_size
13262 <= g_switch_value
))
13264 /* We must defer this decision until after the whole
13265 file has been read, since there might be a .extern
13266 after the first use of this symbol. */
13267 || (before_relaxing
13268 #ifndef NO_ECOFF_DEBUGGING
13269 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13271 && S_GET_VALUE (sym
) == 0)
13272 || (S_GET_VALUE (sym
) != 0
13273 && S_GET_VALUE (sym
) <= g_switch_value
)))
13277 const char *segname
;
13279 segname
= segment_name (S_GET_SEGMENT (sym
));
13280 assert (strcmp (segname
, ".lit8") != 0
13281 && strcmp (segname
, ".lit4") != 0);
13282 change
= (strcmp (segname
, ".sdata") != 0
13283 && strcmp (segname
, ".sbss") != 0
13284 && strncmp (segname
, ".sdata.", 7) != 0
13285 && strncmp (segname
, ".sbss.", 6) != 0
13286 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13287 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13292 /* We are not optimizing for the $gp register. */
13297 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13300 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13304 /* Handle the case of a symbol equated to another symbol. */
13305 while (symbol_equated_reloc_p (sym
))
13309 /* It's possible to get a loop here in a badly written program. */
13310 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13316 if (symbol_section_p (sym
))
13319 symsec
= S_GET_SEGMENT (sym
);
13321 /* This must duplicate the test in adjust_reloc_syms. */
13322 return (symsec
!= &bfd_und_section
13323 && symsec
!= &bfd_abs_section
13324 && !bfd_is_com_section (symsec
)
13325 && !s_is_linkonce (sym
, segtype
)
13327 /* A global or weak symbol is treated as external. */
13328 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13334 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13335 extended opcode. SEC is the section the frag is in. */
13338 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13341 const struct mips16_immed_operand
*op
;
13343 int mintiny
, maxtiny
;
13347 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13349 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13352 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13353 op
= mips16_immed_operands
;
13354 while (op
->type
!= type
)
13357 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13362 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13365 maxtiny
= 1 << op
->nbits
;
13370 maxtiny
= (1 << op
->nbits
) - 1;
13375 mintiny
= - (1 << (op
->nbits
- 1));
13376 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13379 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13380 val
= S_GET_VALUE (fragp
->fr_symbol
);
13381 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13387 /* We won't have the section when we are called from
13388 mips_relax_frag. However, we will always have been called
13389 from md_estimate_size_before_relax first. If this is a
13390 branch to a different section, we mark it as such. If SEC is
13391 NULL, and the frag is not marked, then it must be a branch to
13392 the same section. */
13395 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13400 /* Must have been called from md_estimate_size_before_relax. */
13403 fragp
->fr_subtype
=
13404 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13406 /* FIXME: We should support this, and let the linker
13407 catch branches and loads that are out of range. */
13408 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13409 _("unsupported PC relative reference to different section"));
13413 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13414 /* Assume non-extended on the first relaxation pass.
13415 The address we have calculated will be bogus if this is
13416 a forward branch to another frag, as the forward frag
13417 will have fr_address == 0. */
13421 /* In this case, we know for sure that the symbol fragment is in
13422 the same section. If the relax_marker of the symbol fragment
13423 differs from the relax_marker of this fragment, we have not
13424 yet adjusted the symbol fragment fr_address. We want to add
13425 in STRETCH in order to get a better estimate of the address.
13426 This particularly matters because of the shift bits. */
13428 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13432 /* Adjust stretch for any alignment frag. Note that if have
13433 been expanding the earlier code, the symbol may be
13434 defined in what appears to be an earlier frag. FIXME:
13435 This doesn't handle the fr_subtype field, which specifies
13436 a maximum number of bytes to skip when doing an
13438 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13440 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13443 stretch
= - ((- stretch
)
13444 & ~ ((1 << (int) f
->fr_offset
) - 1));
13446 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13455 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13457 /* The base address rules are complicated. The base address of
13458 a branch is the following instruction. The base address of a
13459 PC relative load or add is the instruction itself, but if it
13460 is in a delay slot (in which case it can not be extended) use
13461 the address of the instruction whose delay slot it is in. */
13462 if (type
== 'p' || type
== 'q')
13466 /* If we are currently assuming that this frag should be
13467 extended, then, the current address is two bytes
13469 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13472 /* Ignore the low bit in the target, since it will be set
13473 for a text label. */
13474 if ((val
& 1) != 0)
13477 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13479 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13482 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13484 /* Branch offsets have an implicit 0 in the lowest bit. */
13485 if (type
== 'p' || type
== 'q')
13488 /* If any of the shifted bits are set, we must use an extended
13489 opcode. If the address depends on the size of this
13490 instruction, this can lead to a loop, so we arrange to always
13491 use an extended opcode. We only check this when we are in
13492 the main relaxation loop, when SEC is NULL. */
13493 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13495 fragp
->fr_subtype
=
13496 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13500 /* If we are about to mark a frag as extended because the value
13501 is precisely maxtiny + 1, then there is a chance of an
13502 infinite loop as in the following code:
13507 In this case when the la is extended, foo is 0x3fc bytes
13508 away, so the la can be shrunk, but then foo is 0x400 away, so
13509 the la must be extended. To avoid this loop, we mark the
13510 frag as extended if it was small, and is about to become
13511 extended with a value of maxtiny + 1. */
13512 if (val
== ((maxtiny
+ 1) << op
->shift
)
13513 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13516 fragp
->fr_subtype
=
13517 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13521 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13522 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13524 if ((val
& ((1 << op
->shift
) - 1)) != 0
13525 || val
< (mintiny
<< op
->shift
)
13526 || val
> (maxtiny
<< op
->shift
))
13532 /* Compute the length of a branch sequence, and adjust the
13533 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13534 worst-case length is computed, with UPDATE being used to indicate
13535 whether an unconditional (-1), branch-likely (+1) or regular (0)
13536 branch is to be computed. */
13538 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13540 bfd_boolean toofar
;
13544 && S_IS_DEFINED (fragp
->fr_symbol
)
13545 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13550 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13552 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13556 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13559 /* If the symbol is not defined or it's in a different segment,
13560 assume the user knows what's going on and emit a short
13566 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13568 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13569 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13570 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13576 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13579 if (mips_pic
!= NO_PIC
)
13581 /* Additional space for PIC loading of target address. */
13583 if (mips_opts
.isa
== ISA_MIPS1
)
13584 /* Additional space for $at-stabilizing nop. */
13588 /* If branch is conditional. */
13589 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13596 /* Estimate the size of a frag before relaxing. Unless this is the
13597 mips16, we are not really relaxing here, and the final size is
13598 encoded in the subtype information. For the mips16, we have to
13599 decide whether we are using an extended opcode or not. */
13602 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13606 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13609 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13611 return fragp
->fr_var
;
13614 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13615 /* We don't want to modify the EXTENDED bit here; it might get us
13616 into infinite loops. We change it only in mips_relax_frag(). */
13617 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13619 if (mips_pic
== NO_PIC
)
13620 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13621 else if (mips_pic
== SVR4_PIC
)
13622 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13623 else if (mips_pic
== VXWORKS_PIC
)
13624 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13631 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13632 return -RELAX_FIRST (fragp
->fr_subtype
);
13635 return -RELAX_SECOND (fragp
->fr_subtype
);
13638 /* This is called to see whether a reloc against a defined symbol
13639 should be converted into a reloc against a section. */
13642 mips_fix_adjustable (fixS
*fixp
)
13644 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13645 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13648 if (fixp
->fx_addsy
== NULL
)
13651 /* If symbol SYM is in a mergeable section, relocations of the form
13652 SYM + 0 can usually be made section-relative. The mergeable data
13653 is then identified by the section offset rather than by the symbol.
13655 However, if we're generating REL LO16 relocations, the offset is split
13656 between the LO16 and parterning high part relocation. The linker will
13657 need to recalculate the complete offset in order to correctly identify
13660 The linker has traditionally not looked for the parterning high part
13661 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13662 placed anywhere. Rather than break backwards compatibility by changing
13663 this, it seems better not to force the issue, and instead keep the
13664 original symbol. This will work with either linker behavior. */
13665 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13666 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13667 || reloc_needs_lo_p (fixp
->fx_r_type
))
13668 && HAVE_IN_PLACE_ADDENDS
13669 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13673 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13674 to a floating-point stub. The same is true for non-R_MIPS16_26
13675 relocations against MIPS16 functions; in this case, the stub becomes
13676 the function's canonical address.
13678 Floating-point stubs are stored in unique .mips16.call.* or
13679 .mips16.fn.* sections. If a stub T for function F is in section S,
13680 the first relocation in section S must be against F; this is how the
13681 linker determines the target function. All relocations that might
13682 resolve to T must also be against F. We therefore have the following
13683 restrictions, which are given in an intentionally-redundant way:
13685 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
13688 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
13689 if that stub might be used.
13691 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
13694 4. We cannot reduce a stub's relocations against MIPS16 symbols if
13695 that stub might be used.
13697 There is a further restriction:
13699 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
13700 on targets with in-place addends; the relocation field cannot
13701 encode the low bit.
13703 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
13704 against a MIPS16 symbol.
13706 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
13707 relocation against some symbol R, no relocation against R may be
13708 reduced. (Note that this deals with (2) as well as (1) because
13709 relocations against global symbols will never be reduced on ELF
13710 targets.) This approach is a little simpler than trying to detect
13711 stub sections, and gives the "all or nothing" per-symbol consistency
13712 that we have for MIPS16 symbols. */
13714 && fixp
->fx_subsy
== NULL
13715 && (S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13716 || *symbol_get_tc (fixp
->fx_addsy
)))
13723 /* Translate internal representation of relocation info to BFD target
13727 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13729 static arelent
*retval
[4];
13731 bfd_reloc_code_real_type code
;
13733 memset (retval
, 0, sizeof(retval
));
13734 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13735 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13736 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13737 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13739 if (fixp
->fx_pcrel
)
13741 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13743 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13744 Relocations want only the symbol offset. */
13745 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13748 /* A gruesome hack which is a result of the gruesome gas
13749 reloc handling. What's worse, for COFF (as opposed to
13750 ECOFF), we might need yet another copy of reloc->address.
13751 See bfd_install_relocation. */
13752 reloc
->addend
+= reloc
->address
;
13756 reloc
->addend
= fixp
->fx_addnumber
;
13758 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13759 entry to be used in the relocation's section offset. */
13760 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13762 reloc
->address
= reloc
->addend
;
13766 code
= fixp
->fx_r_type
;
13768 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13769 if (reloc
->howto
== NULL
)
13771 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13772 _("Can not represent %s relocation in this object file format"),
13773 bfd_get_reloc_code_name (code
));
13780 /* Relax a machine dependent frag. This returns the amount by which
13781 the current size of the frag should change. */
13784 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13786 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13788 offsetT old_var
= fragp
->fr_var
;
13790 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13792 return fragp
->fr_var
- old_var
;
13795 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13798 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13800 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13802 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13807 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13809 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13816 /* Convert a machine dependent frag. */
13819 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13821 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13824 unsigned long insn
;
13828 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13830 if (target_big_endian
)
13831 insn
= bfd_getb32 (buf
);
13833 insn
= bfd_getl32 (buf
);
13835 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13837 /* We generate a fixup instead of applying it right now
13838 because, if there are linker relaxations, we're going to
13839 need the relocations. */
13840 exp
.X_op
= O_symbol
;
13841 exp
.X_add_symbol
= fragp
->fr_symbol
;
13842 exp
.X_add_number
= fragp
->fr_offset
;
13844 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13845 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
13846 fixp
->fx_file
= fragp
->fr_file
;
13847 fixp
->fx_line
= fragp
->fr_line
;
13849 md_number_to_chars ((char *) buf
, insn
, 4);
13856 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13857 _("relaxed out-of-range branch into a jump"));
13859 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13862 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13864 /* Reverse the branch. */
13865 switch ((insn
>> 28) & 0xf)
13868 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13869 have the condition reversed by tweaking a single
13870 bit, and their opcodes all have 0x4???????. */
13871 assert ((insn
& 0xf1000000) == 0x41000000);
13872 insn
^= 0x00010000;
13876 /* bltz 0x04000000 bgez 0x04010000
13877 bltzal 0x04100000 bgezal 0x04110000 */
13878 assert ((insn
& 0xfc0e0000) == 0x04000000);
13879 insn
^= 0x00010000;
13883 /* beq 0x10000000 bne 0x14000000
13884 blez 0x18000000 bgtz 0x1c000000 */
13885 insn
^= 0x04000000;
13893 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13895 /* Clear the and-link bit. */
13896 assert ((insn
& 0xfc1c0000) == 0x04100000);
13898 /* bltzal 0x04100000 bgezal 0x04110000
13899 bltzall 0x04120000 bgezall 0x04130000 */
13900 insn
&= ~0x00100000;
13903 /* Branch over the branch (if the branch was likely) or the
13904 full jump (not likely case). Compute the offset from the
13905 current instruction to branch to. */
13906 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13910 /* How many bytes in instructions we've already emitted? */
13911 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13912 /* How many bytes in instructions from here to the end? */
13913 i
= fragp
->fr_var
- i
;
13915 /* Convert to instruction count. */
13917 /* Branch counts from the next instruction. */
13920 /* Branch over the jump. */
13921 md_number_to_chars ((char *) buf
, insn
, 4);
13925 md_number_to_chars ((char *) buf
, 0, 4);
13928 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13930 /* beql $0, $0, 2f */
13932 /* Compute the PC offset from the current instruction to
13933 the end of the variable frag. */
13934 /* How many bytes in instructions we've already emitted? */
13935 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13936 /* How many bytes in instructions from here to the end? */
13937 i
= fragp
->fr_var
- i
;
13938 /* Convert to instruction count. */
13940 /* Don't decrement i, because we want to branch over the
13944 md_number_to_chars ((char *) buf
, insn
, 4);
13947 md_number_to_chars ((char *) buf
, 0, 4);
13952 if (mips_pic
== NO_PIC
)
13955 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13956 ? 0x0c000000 : 0x08000000);
13957 exp
.X_op
= O_symbol
;
13958 exp
.X_add_symbol
= fragp
->fr_symbol
;
13959 exp
.X_add_number
= fragp
->fr_offset
;
13961 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13962 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
13963 fixp
->fx_file
= fragp
->fr_file
;
13964 fixp
->fx_line
= fragp
->fr_line
;
13966 md_number_to_chars ((char *) buf
, insn
, 4);
13971 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13972 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13973 exp
.X_op
= O_symbol
;
13974 exp
.X_add_symbol
= fragp
->fr_symbol
;
13975 exp
.X_add_number
= fragp
->fr_offset
;
13977 if (fragp
->fr_offset
)
13979 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13980 exp
.X_add_number
= 0;
13983 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13984 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
13985 fixp
->fx_file
= fragp
->fr_file
;
13986 fixp
->fx_line
= fragp
->fr_line
;
13988 md_number_to_chars ((char *) buf
, insn
, 4);
13991 if (mips_opts
.isa
== ISA_MIPS1
)
13994 md_number_to_chars ((char *) buf
, 0, 4);
13998 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13999 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14001 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14002 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14003 fixp
->fx_file
= fragp
->fr_file
;
14004 fixp
->fx_line
= fragp
->fr_line
;
14006 md_number_to_chars ((char *) buf
, insn
, 4);
14010 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14015 md_number_to_chars ((char *) buf
, insn
, 4);
14020 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14021 + fragp
->fr_fix
+ fragp
->fr_var
);
14023 fragp
->fr_fix
+= fragp
->fr_var
;
14028 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14031 const struct mips16_immed_operand
*op
;
14032 bfd_boolean small
, ext
;
14035 unsigned long insn
;
14036 bfd_boolean use_extend
;
14037 unsigned short extend
;
14039 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14040 op
= mips16_immed_operands
;
14041 while (op
->type
!= type
)
14044 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14055 resolve_symbol_value (fragp
->fr_symbol
);
14056 val
= S_GET_VALUE (fragp
->fr_symbol
);
14061 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14063 /* The rules for the base address of a PC relative reloc are
14064 complicated; see mips16_extended_frag. */
14065 if (type
== 'p' || type
== 'q')
14070 /* Ignore the low bit in the target, since it will be
14071 set for a text label. */
14072 if ((val
& 1) != 0)
14075 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14077 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14080 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14083 /* Make sure the section winds up with the alignment we have
14086 record_alignment (asec
, op
->shift
);
14090 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14091 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14092 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14093 _("extended instruction in delay slot"));
14095 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14097 if (target_big_endian
)
14098 insn
= bfd_getb16 (buf
);
14100 insn
= bfd_getl16 (buf
);
14102 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14103 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14104 small
, ext
, &insn
, &use_extend
, &extend
);
14108 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14109 fragp
->fr_fix
+= 2;
14113 md_number_to_chars ((char *) buf
, insn
, 2);
14114 fragp
->fr_fix
+= 2;
14122 first
= RELAX_FIRST (fragp
->fr_subtype
);
14123 second
= RELAX_SECOND (fragp
->fr_subtype
);
14124 fixp
= (fixS
*) fragp
->fr_opcode
;
14126 /* Possibly emit a warning if we've chosen the longer option. */
14127 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14128 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14130 const char *msg
= macro_warning (fragp
->fr_subtype
);
14132 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14135 /* Go through all the fixups for the first sequence. Disable them
14136 (by marking them as done) if we're going to use the second
14137 sequence instead. */
14139 && fixp
->fx_frag
== fragp
14140 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14142 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14144 fixp
= fixp
->fx_next
;
14147 /* Go through the fixups for the second sequence. Disable them if
14148 we're going to use the first sequence, otherwise adjust their
14149 addresses to account for the relaxation. */
14150 while (fixp
&& fixp
->fx_frag
== fragp
)
14152 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14153 fixp
->fx_where
-= first
;
14156 fixp
= fixp
->fx_next
;
14159 /* Now modify the frag contents. */
14160 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14164 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14165 memmove (start
, start
+ first
, second
);
14166 fragp
->fr_fix
-= first
;
14169 fragp
->fr_fix
-= second
;
14175 /* This function is called after the relocs have been generated.
14176 We've been storing mips16 text labels as odd. Here we convert them
14177 back to even for the convenience of the debugger. */
14180 mips_frob_file_after_relocs (void)
14183 unsigned int count
, i
;
14188 syms
= bfd_get_outsymbols (stdoutput
);
14189 count
= bfd_get_symcount (stdoutput
);
14190 for (i
= 0; i
< count
; i
++, syms
++)
14192 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14193 && ((*syms
)->value
& 1) != 0)
14195 (*syms
)->value
&= ~1;
14196 /* If the symbol has an odd size, it was probably computed
14197 incorrectly, so adjust that as well. */
14198 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14199 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14206 /* This function is called whenever a label is defined. It is used
14207 when handling branch delays; if a branch has a label, we assume we
14208 can not move it. */
14211 mips_define_label (symbolS
*sym
)
14213 segment_info_type
*si
= seg_info (now_seg
);
14214 struct insn_label_list
*l
;
14216 if (free_insn_labels
== NULL
)
14217 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14220 l
= free_insn_labels
;
14221 free_insn_labels
= l
->next
;
14225 l
->next
= si
->label_list
;
14226 si
->label_list
= l
;
14229 dwarf2_emit_label (sym
);
14233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14235 /* Some special processing for a MIPS ELF file. */
14238 mips_elf_final_processing (void)
14240 /* Write out the register information. */
14241 if (mips_abi
!= N64_ABI
)
14245 s
.ri_gprmask
= mips_gprmask
;
14246 s
.ri_cprmask
[0] = mips_cprmask
[0];
14247 s
.ri_cprmask
[1] = mips_cprmask
[1];
14248 s
.ri_cprmask
[2] = mips_cprmask
[2];
14249 s
.ri_cprmask
[3] = mips_cprmask
[3];
14250 /* The gp_value field is set by the MIPS ELF backend. */
14252 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14253 ((Elf32_External_RegInfo
*)
14254 mips_regmask_frag
));
14258 Elf64_Internal_RegInfo s
;
14260 s
.ri_gprmask
= mips_gprmask
;
14262 s
.ri_cprmask
[0] = mips_cprmask
[0];
14263 s
.ri_cprmask
[1] = mips_cprmask
[1];
14264 s
.ri_cprmask
[2] = mips_cprmask
[2];
14265 s
.ri_cprmask
[3] = mips_cprmask
[3];
14266 /* The gp_value field is set by the MIPS ELF backend. */
14268 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14269 ((Elf64_External_RegInfo
*)
14270 mips_regmask_frag
));
14273 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14274 sort of BFD interface for this. */
14275 if (mips_any_noreorder
)
14276 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14277 if (mips_pic
!= NO_PIC
)
14279 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14280 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14283 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14285 /* Set MIPS ELF flags for ASEs. */
14286 /* We may need to define a new flag for DSP ASE, and set this flag when
14287 file_ase_dsp is true. */
14288 /* Same for DSP R2. */
14289 /* We may need to define a new flag for MT ASE, and set this flag when
14290 file_ase_mt is true. */
14291 if (file_ase_mips16
)
14292 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14293 #if 0 /* XXX FIXME */
14294 if (file_ase_mips3d
)
14295 elf_elfheader (stdoutput
)->e_flags
|= ???;
14298 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14300 /* Set the MIPS ELF ABI flags. */
14301 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14302 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14303 else if (mips_abi
== O64_ABI
)
14304 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14305 else if (mips_abi
== EABI_ABI
)
14307 if (!file_mips_gp32
)
14308 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14310 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14312 else if (mips_abi
== N32_ABI
)
14313 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14315 /* Nothing to do for N64_ABI. */
14317 if (mips_32bitmode
)
14318 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14320 #if 0 /* XXX FIXME */
14321 /* 32 bit code with 64 bit FP registers. */
14322 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14323 elf_elfheader (stdoutput
)->e_flags
|= ???;
14327 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14329 typedef struct proc
{
14331 symbolS
*func_end_sym
;
14332 unsigned long reg_mask
;
14333 unsigned long reg_offset
;
14334 unsigned long fpreg_mask
;
14335 unsigned long fpreg_offset
;
14336 unsigned long frame_offset
;
14337 unsigned long frame_reg
;
14338 unsigned long pc_reg
;
14341 static procS cur_proc
;
14342 static procS
*cur_proc_ptr
;
14343 static int numprocs
;
14345 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14349 mips_nop_opcode (void)
14351 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14354 /* Fill in an rs_align_code fragment. This only needs to do something
14355 for MIPS16 code, where 0 is not a nop. */
14358 mips_handle_align (fragS
*fragp
)
14362 if (fragp
->fr_type
!= rs_align_code
)
14365 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14370 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14376 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14382 md_obj_begin (void)
14389 /* Check for premature end, nesting errors, etc. */
14391 as_warn (_("missing .end at end of assembly"));
14400 if (*input_line_pointer
== '-')
14402 ++input_line_pointer
;
14405 if (!ISDIGIT (*input_line_pointer
))
14406 as_bad (_("expected simple number"));
14407 if (input_line_pointer
[0] == '0')
14409 if (input_line_pointer
[1] == 'x')
14411 input_line_pointer
+= 2;
14412 while (ISXDIGIT (*input_line_pointer
))
14415 val
|= hex_value (*input_line_pointer
++);
14417 return negative
? -val
: val
;
14421 ++input_line_pointer
;
14422 while (ISDIGIT (*input_line_pointer
))
14425 val
|= *input_line_pointer
++ - '0';
14427 return negative
? -val
: val
;
14430 if (!ISDIGIT (*input_line_pointer
))
14432 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14433 *input_line_pointer
, *input_line_pointer
);
14434 as_warn (_("invalid number"));
14437 while (ISDIGIT (*input_line_pointer
))
14440 val
+= *input_line_pointer
++ - '0';
14442 return negative
? -val
: val
;
14445 /* The .file directive; just like the usual .file directive, but there
14446 is an initial number which is the ECOFF file index. In the non-ECOFF
14447 case .file implies DWARF-2. */
14450 s_mips_file (int x ATTRIBUTE_UNUSED
)
14452 static int first_file_directive
= 0;
14454 if (ECOFF_DEBUGGING
)
14463 filename
= dwarf2_directive_file (0);
14465 /* Versions of GCC up to 3.1 start files with a ".file"
14466 directive even for stabs output. Make sure that this
14467 ".file" is handled. Note that you need a version of GCC
14468 after 3.1 in order to support DWARF-2 on MIPS. */
14469 if (filename
!= NULL
&& ! first_file_directive
)
14471 (void) new_logical_line (filename
, -1);
14472 s_app_file_string (filename
, 0);
14474 first_file_directive
= 1;
14478 /* The .loc directive, implying DWARF-2. */
14481 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14483 if (!ECOFF_DEBUGGING
)
14484 dwarf2_directive_loc (0);
14487 /* The .end directive. */
14490 s_mips_end (int x ATTRIBUTE_UNUSED
)
14494 /* Following functions need their own .frame and .cprestore directives. */
14495 mips_frame_reg_valid
= 0;
14496 mips_cprestore_valid
= 0;
14498 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14501 demand_empty_rest_of_line ();
14506 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14507 as_warn (_(".end not in text section"));
14511 as_warn (_(".end directive without a preceding .ent directive."));
14512 demand_empty_rest_of_line ();
14518 assert (S_GET_NAME (p
));
14519 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14520 as_warn (_(".end symbol does not match .ent symbol."));
14522 if (debug_type
== DEBUG_STABS
)
14523 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14527 as_warn (_(".end directive missing or unknown symbol"));
14530 /* Create an expression to calculate the size of the function. */
14531 if (p
&& cur_proc_ptr
)
14533 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14534 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14537 exp
->X_op
= O_subtract
;
14538 exp
->X_add_symbol
= symbol_temp_new_now ();
14539 exp
->X_op_symbol
= p
;
14540 exp
->X_add_number
= 0;
14542 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14545 /* Generate a .pdr section. */
14546 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14548 segT saved_seg
= now_seg
;
14549 subsegT saved_subseg
= now_subseg
;
14554 dot
= frag_now_fix ();
14556 #ifdef md_flush_pending_output
14557 md_flush_pending_output ();
14561 subseg_set (pdr_seg
, 0);
14563 /* Write the symbol. */
14564 exp
.X_op
= O_symbol
;
14565 exp
.X_add_symbol
= p
;
14566 exp
.X_add_number
= 0;
14567 emit_expr (&exp
, 4);
14569 fragp
= frag_more (7 * 4);
14571 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14572 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14573 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14574 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14575 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14576 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14577 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14579 subseg_set (saved_seg
, saved_subseg
);
14581 #endif /* OBJ_ELF */
14583 cur_proc_ptr
= NULL
;
14586 /* The .aent and .ent directives. */
14589 s_mips_ent (int aent
)
14593 symbolP
= get_symbol ();
14594 if (*input_line_pointer
== ',')
14595 ++input_line_pointer
;
14596 SKIP_WHITESPACE ();
14597 if (ISDIGIT (*input_line_pointer
)
14598 || *input_line_pointer
== '-')
14601 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14602 as_warn (_(".ent or .aent not in text section."));
14604 if (!aent
&& cur_proc_ptr
)
14605 as_warn (_("missing .end"));
14609 /* This function needs its own .frame and .cprestore directives. */
14610 mips_frame_reg_valid
= 0;
14611 mips_cprestore_valid
= 0;
14613 cur_proc_ptr
= &cur_proc
;
14614 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14616 cur_proc_ptr
->func_sym
= symbolP
;
14618 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14622 if (debug_type
== DEBUG_STABS
)
14623 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14624 S_GET_NAME (symbolP
));
14627 demand_empty_rest_of_line ();
14630 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14631 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14632 s_mips_frame is used so that we can set the PDR information correctly.
14633 We can't use the ecoff routines because they make reference to the ecoff
14634 symbol table (in the mdebug section). */
14637 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14640 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14644 if (cur_proc_ptr
== (procS
*) NULL
)
14646 as_warn (_(".frame outside of .ent"));
14647 demand_empty_rest_of_line ();
14651 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14653 SKIP_WHITESPACE ();
14654 if (*input_line_pointer
++ != ','
14655 || get_absolute_expression_and_terminator (&val
) != ',')
14657 as_warn (_("Bad .frame directive"));
14658 --input_line_pointer
;
14659 demand_empty_rest_of_line ();
14663 cur_proc_ptr
->frame_offset
= val
;
14664 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14666 demand_empty_rest_of_line ();
14669 #endif /* OBJ_ELF */
14673 /* The .fmask and .mask directives. If the mdebug section is present
14674 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14675 embedded targets, s_mips_mask is used so that we can set the PDR
14676 information correctly. We can't use the ecoff routines because they
14677 make reference to the ecoff symbol table (in the mdebug section). */
14680 s_mips_mask (int reg_type
)
14683 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14687 if (cur_proc_ptr
== (procS
*) NULL
)
14689 as_warn (_(".mask/.fmask outside of .ent"));
14690 demand_empty_rest_of_line ();
14694 if (get_absolute_expression_and_terminator (&mask
) != ',')
14696 as_warn (_("Bad .mask/.fmask directive"));
14697 --input_line_pointer
;
14698 demand_empty_rest_of_line ();
14702 off
= get_absolute_expression ();
14704 if (reg_type
== 'F')
14706 cur_proc_ptr
->fpreg_mask
= mask
;
14707 cur_proc_ptr
->fpreg_offset
= off
;
14711 cur_proc_ptr
->reg_mask
= mask
;
14712 cur_proc_ptr
->reg_offset
= off
;
14715 demand_empty_rest_of_line ();
14718 #endif /* OBJ_ELF */
14719 s_ignore (reg_type
);
14722 /* A table describing all the processors gas knows about. Names are
14723 matched in the order listed.
14725 To ease comparison, please keep this table in the same order as
14726 gcc's mips_cpu_info_table[]. */
14727 static const struct mips_cpu_info mips_cpu_info_table
[] =
14729 /* Entries for generic ISAs */
14730 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14731 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14732 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14733 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14734 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14735 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14736 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14737 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14738 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14741 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14742 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14743 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14746 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14749 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14750 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14751 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14752 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14753 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14754 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14755 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14756 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14757 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14758 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14759 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14760 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14763 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14764 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14765 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14766 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14767 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14768 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14769 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14770 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14771 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14772 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14773 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14774 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14775 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14778 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14779 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14780 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14781 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
14783 /* MIPS 32 Release 2 */
14784 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14785 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14786 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14787 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14788 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14789 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14790 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14791 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14792 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14793 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14794 /* Deprecated forms of the above. */
14795 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14796 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14797 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
14798 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14799 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14800 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14801 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14802 /* Deprecated forms of the above. */
14803 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14804 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14805 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
14806 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14807 ISA_MIPS32R2
, CPU_MIPS32R2
},
14808 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14809 ISA_MIPS32R2
, CPU_MIPS32R2
},
14810 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14811 ISA_MIPS32R2
, CPU_MIPS32R2
},
14812 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14813 ISA_MIPS32R2
, CPU_MIPS32R2
},
14814 /* Deprecated forms of the above. */
14815 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14816 ISA_MIPS32R2
, CPU_MIPS32R2
},
14817 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
14818 ISA_MIPS32R2
, CPU_MIPS32R2
},
14819 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
14820 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14821 ISA_MIPS32R2
, CPU_MIPS32R2
},
14822 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14823 ISA_MIPS32R2
, CPU_MIPS32R2
},
14824 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14825 ISA_MIPS32R2
, CPU_MIPS32R2
},
14826 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14827 ISA_MIPS32R2
, CPU_MIPS32R2
},
14828 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14829 ISA_MIPS32R2
, CPU_MIPS32R2
},
14830 /* Deprecated forms of the above. */
14831 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14832 ISA_MIPS32R2
, CPU_MIPS32R2
},
14833 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
14834 ISA_MIPS32R2
, CPU_MIPS32R2
},
14837 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14838 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14839 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14840 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14842 /* MIPS 64 Release 2 */
14844 /* Broadcom SB-1 CPU core */
14845 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14846 ISA_MIPS64
, CPU_SB1
},
14847 /* Broadcom SB-1A CPU core */
14848 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14849 ISA_MIPS64
, CPU_SB1
},
14851 /* ST Microelectronics Loongson 2E and 2F cores */
14852 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
14853 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
14860 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14861 with a final "000" replaced by "k". Ignore case.
14863 Note: this function is shared between GCC and GAS. */
14866 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14868 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14869 given
++, canonical
++;
14871 return ((*given
== 0 && *canonical
== 0)
14872 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14876 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14877 CPU name. We've traditionally allowed a lot of variation here.
14879 Note: this function is shared between GCC and GAS. */
14882 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14884 /* First see if the name matches exactly, or with a final "000"
14885 turned into "k". */
14886 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14889 /* If not, try comparing based on numerical designation alone.
14890 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14891 if (TOLOWER (*given
) == 'r')
14893 if (!ISDIGIT (*given
))
14896 /* Skip over some well-known prefixes in the canonical name,
14897 hoping to find a number there too. */
14898 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14900 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14902 else if (TOLOWER (canonical
[0]) == 'r')
14905 return mips_strict_matching_cpu_name_p (canonical
, given
);
14909 /* Parse an option that takes the name of a processor as its argument.
14910 OPTION is the name of the option and CPU_STRING is the argument.
14911 Return the corresponding processor enumeration if the CPU_STRING is
14912 recognized, otherwise report an error and return null.
14914 A similar function exists in GCC. */
14916 static const struct mips_cpu_info
*
14917 mips_parse_cpu (const char *option
, const char *cpu_string
)
14919 const struct mips_cpu_info
*p
;
14921 /* 'from-abi' selects the most compatible architecture for the given
14922 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14923 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14924 version. Look first at the -mgp options, if given, otherwise base
14925 the choice on MIPS_DEFAULT_64BIT.
14927 Treat NO_ABI like the EABIs. One reason to do this is that the
14928 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14929 architecture. This code picks MIPS I for 'mips' and MIPS III for
14930 'mips64', just as we did in the days before 'from-abi'. */
14931 if (strcasecmp (cpu_string
, "from-abi") == 0)
14933 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14934 return mips_cpu_info_from_isa (ISA_MIPS1
);
14936 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14937 return mips_cpu_info_from_isa (ISA_MIPS3
);
14939 if (file_mips_gp32
>= 0)
14940 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14942 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14947 /* 'default' has traditionally been a no-op. Probably not very useful. */
14948 if (strcasecmp (cpu_string
, "default") == 0)
14951 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14952 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14955 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14959 /* Return the canonical processor information for ISA (a member of the
14960 ISA_MIPS* enumeration). */
14962 static const struct mips_cpu_info
*
14963 mips_cpu_info_from_isa (int isa
)
14967 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14968 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
14969 && isa
== mips_cpu_info_table
[i
].isa
)
14970 return (&mips_cpu_info_table
[i
]);
14975 static const struct mips_cpu_info
*
14976 mips_cpu_info_from_arch (int arch
)
14980 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14981 if (arch
== mips_cpu_info_table
[i
].cpu
)
14982 return (&mips_cpu_info_table
[i
]);
14988 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14992 fprintf (stream
, "%24s", "");
14997 fprintf (stream
, ", ");
15001 if (*col_p
+ strlen (string
) > 72)
15003 fprintf (stream
, "\n%24s", "");
15007 fprintf (stream
, "%s", string
);
15008 *col_p
+= strlen (string
);
15014 md_show_usage (FILE *stream
)
15019 fprintf (stream
, _("\
15021 -EB generate big endian output\n\
15022 -EL generate little endian output\n\
15023 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15024 -G NUM allow referencing objects up to NUM bytes\n\
15025 implicitly with the gp register [default 8]\n"));
15026 fprintf (stream
, _("\
15027 -mips1 generate MIPS ISA I instructions\n\
15028 -mips2 generate MIPS ISA II instructions\n\
15029 -mips3 generate MIPS ISA III instructions\n\
15030 -mips4 generate MIPS ISA IV instructions\n\
15031 -mips5 generate MIPS ISA V instructions\n\
15032 -mips32 generate MIPS32 ISA instructions\n\
15033 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15034 -mips64 generate MIPS64 ISA instructions\n\
15035 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15036 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15040 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15041 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15042 show (stream
, "from-abi", &column
, &first
);
15043 fputc ('\n', stream
);
15045 fprintf (stream
, _("\
15046 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15047 -no-mCPU don't generate code specific to CPU.\n\
15048 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15052 show (stream
, "3900", &column
, &first
);
15053 show (stream
, "4010", &column
, &first
);
15054 show (stream
, "4100", &column
, &first
);
15055 show (stream
, "4650", &column
, &first
);
15056 fputc ('\n', stream
);
15058 fprintf (stream
, _("\
15059 -mips16 generate mips16 instructions\n\
15060 -no-mips16 do not generate mips16 instructions\n"));
15061 fprintf (stream
, _("\
15062 -msmartmips generate smartmips instructions\n\
15063 -mno-smartmips do not generate smartmips instructions\n"));
15064 fprintf (stream
, _("\
15065 -mdsp generate DSP instructions\n\
15066 -mno-dsp do not generate DSP instructions\n"));
15067 fprintf (stream
, _("\
15068 -mdspr2 generate DSP R2 instructions\n\
15069 -mno-dspr2 do not generate DSP R2 instructions\n"));
15070 fprintf (stream
, _("\
15071 -mmt generate MT instructions\n\
15072 -mno-mt do not generate MT instructions\n"));
15073 fprintf (stream
, _("\
15074 -mfix-vr4120 work around certain VR4120 errata\n\
15075 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15076 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15077 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15078 -msym32 assume all symbols have 32-bit values\n\
15079 -O0 remove unneeded NOPs, do not swap branches\n\
15080 -O remove unneeded NOPs and swap branches\n\
15081 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15082 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15083 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15085 fprintf (stream
, _("\
15086 -KPIC, -call_shared generate SVR4 position independent code\n\
15087 -mvxworks-pic generate VxWorks position independent code\n\
15088 -non_shared do not generate position independent code\n\
15089 -xgot assume a 32 bit GOT\n\
15090 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15091 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15092 position dependent (non shared) code\n\
15093 -mabi=ABI create ABI conformant object file for:\n"));
15097 show (stream
, "32", &column
, &first
);
15098 show (stream
, "o64", &column
, &first
);
15099 show (stream
, "n32", &column
, &first
);
15100 show (stream
, "64", &column
, &first
);
15101 show (stream
, "eabi", &column
, &first
);
15103 fputc ('\n', stream
);
15105 fprintf (stream
, _("\
15106 -32 create o32 ABI object file (default)\n\
15107 -n32 create n32 ABI object file\n\
15108 -64 create 64 ABI object file\n"));
15113 mips_dwarf2_format (void)
15115 if (HAVE_64BIT_SYMBOLS
)
15118 return dwarf2_format_64bit_irix
;
15120 return dwarf2_format_64bit
;
15124 return dwarf2_format_32bit
;
15128 mips_dwarf2_addr_size (void)
15130 if (HAVE_64BIT_SYMBOLS
)
15136 /* Standard calling conventions leave the CFA at SP on entry. */
15138 mips_cfi_frame_initial_instructions (void)
15140 cfi_add_CFA_def_cfa_register (SP
);
15144 tc_mips_regname_to_dw2regnum (char *regname
)
15146 unsigned int regnum
= -1;
15149 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))