1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_coff_flavour
:
124 case bfd_target_elf_flavour
:
126 /* This is traditional mips */
127 return (target_big_endian
128 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
130 return (target_big_endian
131 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
132 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
140 /* The name of the readonly data section. */
141 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
143 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
145 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
151 /* This is the set of options which may be modified by the .set
152 pseudo-op. We use a struct so that .set push and .set pop are more
155 struct mips_set_options
157 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
158 if it has not been initialized. Changed by `.set mipsN', and the
159 -mipsN command line option, and the default CPU. */
161 /* Whether we are assembling for the mips16 processor. 0 if we are
162 not, 1 if we are, and -1 if the value has not been initialized.
163 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
164 -nomips16 command line options, and the default CPU. */
166 /* Non-zero if we should not reorder instructions. Changed by `.set
167 reorder' and `.set noreorder'. */
169 /* Non-zero if we should not permit the $at ($1) register to be used
170 in instructions. Changed by `.set at' and `.set noat'. */
172 /* Non-zero if we should warn when a macro instruction expands into
173 more than one machine instruction. Changed by `.set nomacro' and
175 int warn_about_macros
;
176 /* Non-zero if we should not move instructions. Changed by `.set
177 move', `.set volatile', `.set nomove', and `.set novolatile'. */
179 /* Non-zero if we should not optimize branches by moving the target
180 of the branch into the delay slot. Actually, we don't perform
181 this optimization anyhow. Changed by `.set bopt' and `.set
184 /* Non-zero if we should not autoextend mips16 instructions.
185 Changed by `.set autoextend' and `.set noautoextend'. */
189 /* This is the struct we use to hold the current set of options. Note
190 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
191 -1 to indicate that they have not been initialized. */
193 static struct mips_set_options mips_opts
=
195 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
198 /* These variables are filled in with the masks of registers used.
199 The object format code reads them and puts them in the appropriate
201 unsigned long mips_gprmask
;
202 unsigned long mips_cprmask
[4];
204 /* MIPS ISA we are using for this output file. */
205 static int file_mips_isa
= ISA_UNKNOWN
;
207 /* The CPU type we are using for this output file. */
208 static int mips_cpu
= CPU_UNKNOWN
;
210 /* The argument of the -mabi= flag. */
211 static char* mips_abi_string
= 0;
213 /* Wether we should mark the file EABI64 or EABI32. */
214 static int mips_eabi64
= 0;
216 /* If they asked for mips1 or mips2 and a cpu that is
217 mips3 or greater, then mark the object file 32BITMODE. */
218 static int mips_32bitmode
= 0;
220 /* True if -mgp32 was passed. */
221 static int mips_gp32
= 0;
223 /* Some ISA's have delay slots for instructions which read or write
224 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
225 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
226 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
227 delay slot in this ISA. The uses of this macro assume that any
228 ISA that has delay slots for one of these, has them for all. They
229 also assume that ISAs which don't have delays for these insns, don't
230 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
231 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
233 || (ISA) == ISA_MIPS2 \
234 || (ISA) == ISA_MIPS3 \
237 /* Return true if ISA supports 64 bit gp register instructions. */
238 #define ISA_HAS_64BIT_REGS(ISA) ( \
240 || (ISA) == ISA_MIPS4 \
241 || (ISA) == ISA_MIPS5 \
242 || (ISA) == ISA_MIPS32 \
245 /* Whether the processor uses hardware interlocks to protect
246 reads from the HI and LO registers, and thus does not
247 require nops to be inserted.
249 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
250 -mcpu=FOO schedules for FOO, but still produces code that meets the
251 requirements of MIPS ISA I. For example, it won't generate any
252 FOO-specific instructions, and it will still assume that any
253 scheduling hazards described in MIPS ISA I are there, even if FOO
254 has interlocks. -mFOO gives GCC permission to generate code that
255 will only run on a FOO; it will generate FOO-specific instructions,
256 and assume interlocks provided by a FOO.
258 However, GAS currently doesn't make this distinction; before Jan 28
259 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
260 assumptions. The GCC driver passes these flags through to GAS, so
261 if GAS actually does anything that doesn't meet MIPS ISA I with
262 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
264 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
265 which seems senseless --- why generate code which will only run on
266 a FOO, but schedule for something else?
268 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
270 -- Jim Blandy <jimb@cygnus.com> */
272 #define hilo_interlocks (mips_cpu == CPU_R4010 \
275 /* Whether the processor uses hardware interlocks to protect reads
276 from the GPRs, and thus does not require nops to be inserted. */
277 #define gpr_interlocks \
278 (mips_opts.isa != ISA_MIPS1 \
279 || mips_cpu == CPU_R3900)
281 /* As with other "interlocks" this is used by hardware that has FP
282 (co-processor) interlocks. */
283 /* Itbl support may require additional care here. */
284 #define cop_interlocks (mips_cpu == CPU_R4300 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic
;
314 /* 1 if we should generate 32 bit offsets from the GP register in
315 SVR4_PIC mode. Currently has no meaning in other modes. */
316 static int mips_big_got
;
318 /* 1 if trap instructions should used for overflow rather than break
320 static int mips_trap
;
322 /* 1 if double width floating point constants should not be constructed
323 by a assembling two single width halves into two single width floating
324 point registers which just happen to alias the double width destination
325 register. On some architectures this aliasing can be disabled by a bit
326 in the status register, and the setting of this bit cannot be determined
327 automatically at assemble time. */
328 static int mips_disable_float_construction
;
330 /* Non-zero if any .set noreorder directives were used. */
332 static int mips_any_noreorder
;
334 /* Non-zero if nops should be inserted when the register referenced in
335 an mfhi/mflo instruction is read in the next two instructions. */
336 static int mips_7000_hilo_fix
;
338 /* The size of the small data section. */
339 static unsigned int g_switch_value
= 8;
340 /* Whether the -G option was used. */
341 static int g_switch_seen
= 0;
346 /* If we can determine in advance that GP optimization won't be
347 possible, we can skip the relaxation stuff that tries to produce
348 GP-relative references. This makes delay slot optimization work
351 This function can only provide a guess, but it seems to work for
352 gcc output. It needs to guess right for gcc, otherwise gcc
353 will put what it thinks is a GP-relative instruction in a branch
356 I don't know if a fix is needed for the SVR4_PIC mode. I've only
357 fixed it for the non-PIC mode. KR 95/04/07 */
358 static int nopic_need_relax
PARAMS ((symbolS
*, int));
360 /* handle of the OPCODE hash table */
361 static struct hash_control
*op_hash
= NULL
;
363 /* The opcode hash table we use for the mips16. */
364 static struct hash_control
*mips16_op_hash
= NULL
;
366 /* This array holds the chars that always start a comment. If the
367 pre-processor is disabled, these aren't very useful */
368 const char comment_chars
[] = "#";
370 /* This array holds the chars that only start a comment at the beginning of
371 a line. If the line seems to have the form '# 123 filename'
372 .line and .file directives will appear in the pre-processed output */
373 /* Note that input_file.c hand checks for '#' at the beginning of the
374 first line of the input file. This is because the compiler outputs
375 #NO_APP at the beginning of its output. */
376 /* Also note that C style comments are always supported. */
377 const char line_comment_chars
[] = "#";
379 /* This array holds machine specific line separator characters. */
380 const char line_separator_chars
[] = ";";
382 /* Chars that can be used to separate mant from exp in floating point nums */
383 const char EXP_CHARS
[] = "eE";
385 /* Chars that mean this number is a floating point constant */
388 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
390 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
391 changed in read.c . Ideally it shouldn't have to know about it at all,
392 but nothing is ideal around here.
395 static char *insn_error
;
397 static int auto_align
= 1;
399 /* When outputting SVR4 PIC code, the assembler needs to know the
400 offset in the stack frame from which to restore the $gp register.
401 This is set by the .cprestore pseudo-op, and saved in this
403 static offsetT mips_cprestore_offset
= -1;
405 /* This is the register which holds the stack frame, as set by the
406 .frame pseudo-op. This is needed to implement .cprestore. */
407 static int mips_frame_reg
= SP
;
409 /* To output NOP instructions correctly, we need to keep information
410 about the previous two instructions. */
412 /* Whether we are optimizing. The default value of 2 means to remove
413 unneeded NOPs and swap branch instructions when possible. A value
414 of 1 means to not swap branches. A value of 0 means to always
416 static int mips_optimize
= 2;
418 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
419 equivalent to seeing no -g option at all. */
420 static int mips_debug
= 0;
422 /* The previous instruction. */
423 static struct mips_cl_insn prev_insn
;
425 /* The instruction before prev_insn. */
426 static struct mips_cl_insn prev_prev_insn
;
428 /* If we don't want information for prev_insn or prev_prev_insn, we
429 point the insn_mo field at this dummy integer. */
430 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
432 /* Non-zero if prev_insn is valid. */
433 static int prev_insn_valid
;
435 /* The frag for the previous instruction. */
436 static struct frag
*prev_insn_frag
;
438 /* The offset into prev_insn_frag for the previous instruction. */
439 static long prev_insn_where
;
441 /* The reloc type for the previous instruction, if any. */
442 static bfd_reloc_code_real_type prev_insn_reloc_type
;
444 /* The reloc for the previous instruction, if any. */
445 static fixS
*prev_insn_fixp
;
447 /* Non-zero if the previous instruction was in a delay slot. */
448 static int prev_insn_is_delay_slot
;
450 /* Non-zero if the previous instruction was in a .set noreorder. */
451 static int prev_insn_unreordered
;
453 /* Non-zero if the previous instruction uses an extend opcode (if
455 static int prev_insn_extended
;
457 /* Non-zero if the previous previous instruction was in a .set
459 static int prev_prev_insn_unreordered
;
461 /* If this is set, it points to a frag holding nop instructions which
462 were inserted before the start of a noreorder section. If those
463 nops turn out to be unnecessary, the size of the frag can be
465 static fragS
*prev_nop_frag
;
467 /* The number of nop instructions we created in prev_nop_frag. */
468 static int prev_nop_frag_holds
;
470 /* The number of nop instructions that we know we need in
472 static int prev_nop_frag_required
;
474 /* The number of instructions we've seen since prev_nop_frag. */
475 static int prev_nop_frag_since
;
477 /* For ECOFF and ELF, relocations against symbols are done in two
478 parts, with a HI relocation and a LO relocation. Each relocation
479 has only 16 bits of space to store an addend. This means that in
480 order for the linker to handle carries correctly, it must be able
481 to locate both the HI and the LO relocation. This means that the
482 relocations must appear in order in the relocation table.
484 In order to implement this, we keep track of each unmatched HI
485 relocation. We then sort them so that they immediately precede the
486 corresponding LO relocation. */
491 struct mips_hi_fixup
*next
;
494 /* The section this fixup is in. */
498 /* The list of unmatched HI relocs. */
500 static struct mips_hi_fixup
*mips_hi_fixup_list
;
502 /* Map normal MIPS register numbers to mips16 register numbers. */
504 #define X ILLEGAL_REG
505 static const int mips32_to_16_reg_map
[] =
507 X
, X
, 2, 3, 4, 5, 6, 7,
508 X
, X
, X
, X
, X
, X
, X
, X
,
509 0, 1, X
, X
, X
, X
, X
, X
,
510 X
, X
, X
, X
, X
, X
, X
, X
514 /* Map mips16 register numbers to normal MIPS register numbers. */
516 static const unsigned int mips16_to_32_reg_map
[] =
518 16, 17, 2, 3, 4, 5, 6, 7
521 /* Since the MIPS does not have multiple forms of PC relative
522 instructions, we do not have to do relaxing as is done on other
523 platforms. However, we do have to handle GP relative addressing
524 correctly, which turns out to be a similar problem.
526 Every macro that refers to a symbol can occur in (at least) two
527 forms, one with GP relative addressing and one without. For
528 example, loading a global variable into a register generally uses
529 a macro instruction like this:
531 If i can be addressed off the GP register (this is true if it is in
532 the .sbss or .sdata section, or if it is known to be smaller than
533 the -G argument) this will generate the following instruction:
535 This instruction will use a GPREL reloc. If i can not be addressed
536 off the GP register, the following instruction sequence will be used:
539 In this case the first instruction will have a HI16 reloc, and the
540 second reloc will have a LO16 reloc. Both relocs will be against
543 The issue here is that we may not know whether i is GP addressable
544 until after we see the instruction that uses it. Therefore, we
545 want to be able to choose the final instruction sequence only at
546 the end of the assembly. This is similar to the way other
547 platforms choose the size of a PC relative instruction only at the
550 When generating position independent code we do not use GP
551 addressing in quite the same way, but the issue still arises as
552 external symbols and local symbols must be handled differently.
554 We handle these issues by actually generating both possible
555 instruction sequences. The longer one is put in a frag_var with
556 type rs_machine_dependent. We encode what to do with the frag in
557 the subtype field. We encode (1) the number of existing bytes to
558 replace, (2) the number of new bytes to use, (3) the offset from
559 the start of the existing bytes to the first reloc we must generate
560 (that is, the offset is applied from the start of the existing
561 bytes after they are replaced by the new bytes, if any), (4) the
562 offset from the start of the existing bytes to the second reloc,
563 (5) whether a third reloc is needed (the third reloc is always four
564 bytes after the second reloc), and (6) whether to warn if this
565 variant is used (this is sometimes needed if .set nomacro or .set
566 noat is in effect). All these numbers are reasonably small.
568 Generating two instruction sequences must be handled carefully to
569 ensure that delay slots are handled correctly. Fortunately, there
570 are a limited number of cases. When the second instruction
571 sequence is generated, append_insn is directed to maintain the
572 existing delay slot information, so it continues to apply to any
573 code after the second instruction sequence. This means that the
574 second instruction sequence must not impose any requirements not
575 required by the first instruction sequence.
577 These variant frags are then handled in functions called by the
578 machine independent code. md_estimate_size_before_relax returns
579 the final size of the frag. md_convert_frag sets up the final form
580 of the frag. tc_gen_reloc adjust the first reloc and adds a second
582 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
586 | (((reloc1) + 64) << 9) \
587 | (((reloc2) + 64) << 2) \
588 | ((reloc3) ? (1 << 1) : 0) \
590 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
591 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
592 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
593 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
594 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
595 #define RELAX_WARN(i) ((i) & 1)
597 /* For mips16 code, we use an entirely different form of relaxation.
598 mips16 supports two versions of most instructions which take
599 immediate values: a small one which takes some small value, and a
600 larger one which takes a 16 bit value. Since branches also follow
601 this pattern, relaxing these values is required.
603 We can assemble both mips16 and normal MIPS code in a single
604 object. Therefore, we need to support this type of relaxation at
605 the same time that we support the relaxation described above. We
606 use the high bit of the subtype field to distinguish these cases.
608 The information we store for this type of relaxation is the
609 argument code found in the opcode file for this relocation, whether
610 the user explicitly requested a small or extended form, and whether
611 the relocation is in a jump or jal delay slot. That tells us the
612 size of the value, and how it should be stored. We also store
613 whether the fragment is considered to be extended or not. We also
614 store whether this is known to be a branch to a different section,
615 whether we have tried to relax this frag yet, and whether we have
616 ever extended a PC relative fragment because of a shift count. */
617 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
620 | ((small) ? 0x100 : 0) \
621 | ((ext) ? 0x200 : 0) \
622 | ((dslot) ? 0x400 : 0) \
623 | ((jal_dslot) ? 0x800 : 0))
624 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
625 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
626 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
627 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
628 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
629 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
630 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
631 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
632 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
633 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
634 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
635 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
637 /* Prototypes for static functions. */
640 #define internalError() \
641 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
643 #define internalError() as_fatal (_("MIPS internal Error"));
646 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
648 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
649 unsigned int reg
, enum mips_regclass
class));
650 static int reg_needs_delay
PARAMS ((unsigned int));
651 static void mips16_mark_labels
PARAMS ((void));
652 static void append_insn
PARAMS ((char *place
,
653 struct mips_cl_insn
* ip
,
655 bfd_reloc_code_real_type r
,
657 static void mips_no_prev_insn
PARAMS ((int));
658 static void mips_emit_delays
PARAMS ((boolean
));
660 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
661 const char *name
, const char *fmt
,
664 static void macro_build ();
666 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
667 const char *, const char *,
669 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
670 expressionS
* ep
, int regnum
));
671 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
672 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
674 static void load_register
PARAMS ((int *, int, expressionS
*, int));
675 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
676 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
677 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
678 #ifdef LOSING_COMPILER
679 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
681 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
682 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
683 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
684 boolean
, boolean
, unsigned long *,
685 boolean
*, unsigned short *));
686 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
687 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
688 static symbolS
*get_symbol
PARAMS ((void));
689 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
690 static void s_align
PARAMS ((int));
691 static void s_change_sec
PARAMS ((int));
692 static void s_cons
PARAMS ((int));
693 static void s_float_cons
PARAMS ((int));
694 static void s_mips_globl
PARAMS ((int));
695 static void s_option
PARAMS ((int));
696 static void s_mipsset
PARAMS ((int));
697 static void s_abicalls
PARAMS ((int));
698 static void s_cpload
PARAMS ((int));
699 static void s_cprestore
PARAMS ((int));
700 static void s_gpword
PARAMS ((int));
701 static void s_cpadd
PARAMS ((int));
702 static void s_insn
PARAMS ((int));
703 static void md_obj_begin
PARAMS ((void));
704 static void md_obj_end
PARAMS ((void));
705 static long get_number
PARAMS ((void));
706 static void s_mips_ent
PARAMS ((int));
707 static void s_mips_end
PARAMS ((int));
708 static void s_mips_frame
PARAMS ((int));
709 static void s_mips_mask
PARAMS ((int));
710 static void s_mips_stab
PARAMS ((int));
711 static void s_mips_weakext
PARAMS ((int));
712 static void s_file
PARAMS ((int));
713 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
714 static const char *mips_isa_to_str
PARAMS ((int));
715 static const char *mips_cpu_to_str
PARAMS ((int));
716 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
718 /* Table and functions used to map between CPU/ISA names, and
719 ISA levels, and CPU numbers. */
723 const char *name
; /* CPU or ISA name. */
724 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
725 int isa
; /* ISA level. */
726 int cpu
; /* CPU number (default CPU if ISA). */
729 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
730 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
731 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
735 The following pseudo-ops from the Kane and Heinrich MIPS book
736 should be defined here, but are currently unsupported: .alias,
737 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
739 The following pseudo-ops from the Kane and Heinrich MIPS book are
740 specific to the type of debugging information being generated, and
741 should be defined by the object format: .aent, .begin, .bend,
742 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
745 The following pseudo-ops from the Kane and Heinrich MIPS book are
746 not MIPS CPU specific, but are also not specific to the object file
747 format. This file is probably the best place to define them, but
748 they are not currently supported: .asm0, .endr, .lab, .repeat,
751 static const pseudo_typeS mips_pseudo_table
[] =
753 /* MIPS specific pseudo-ops. */
754 {"option", s_option
, 0},
755 {"set", s_mipsset
, 0},
756 {"rdata", s_change_sec
, 'r'},
757 {"sdata", s_change_sec
, 's'},
758 {"livereg", s_ignore
, 0},
759 {"abicalls", s_abicalls
, 0},
760 {"cpload", s_cpload
, 0},
761 {"cprestore", s_cprestore
, 0},
762 {"gpword", s_gpword
, 0},
763 {"cpadd", s_cpadd
, 0},
766 /* Relatively generic pseudo-ops that happen to be used on MIPS
768 {"asciiz", stringer
, 1},
769 {"bss", s_change_sec
, 'b'},
772 {"dword", s_cons
, 3},
773 {"weakext", s_mips_weakext
, 0},
775 /* These pseudo-ops are defined in read.c, but must be overridden
776 here for one reason or another. */
777 {"align", s_align
, 0},
779 {"data", s_change_sec
, 'd'},
780 {"double", s_float_cons
, 'd'},
781 {"float", s_float_cons
, 'f'},
782 {"globl", s_mips_globl
, 0},
783 {"global", s_mips_globl
, 0},
784 {"hword", s_cons
, 1},
789 {"short", s_cons
, 1},
790 {"single", s_float_cons
, 'f'},
791 {"stabn", s_mips_stab
, 'n'},
792 {"text", s_change_sec
, 't'},
797 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
798 /* These pseudo-ops should be defined by the object file format.
799 However, a.out doesn't support them, so we have versions here. */
800 {"aent", s_mips_ent
, 1},
801 {"bgnb", s_ignore
, 0},
802 {"end", s_mips_end
, 0},
803 {"endb", s_ignore
, 0},
804 {"ent", s_mips_ent
, 0},
806 {"fmask", s_mips_mask
, 'F'},
807 {"frame", s_mips_frame
, 0},
808 {"loc", s_ignore
, 0},
809 {"mask", s_mips_mask
, 'R'},
810 {"verstamp", s_ignore
, 0},
814 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
819 pop_insert (mips_pseudo_table
);
820 if (! ECOFF_DEBUGGING
)
821 pop_insert (mips_nonecoff_pseudo_table
);
824 /* Symbols labelling the current insn. */
826 struct insn_label_list
828 struct insn_label_list
*next
;
832 static struct insn_label_list
*insn_labels
;
833 static struct insn_label_list
*free_insn_labels
;
835 static void mips_clear_insn_labels
PARAMS ((void));
838 mips_clear_insn_labels ()
840 register struct insn_label_list
**pl
;
842 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
848 static char *expr_end
;
850 /* Expressions which appear in instructions. These are set by
853 static expressionS imm_expr
;
854 static expressionS offset_expr
;
856 /* Relocs associated with imm_expr and offset_expr. */
858 static bfd_reloc_code_real_type imm_reloc
;
859 static bfd_reloc_code_real_type offset_reloc
;
861 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
863 static boolean imm_unmatched_hi
;
865 /* These are set by mips16_ip if an explicit extension is used. */
867 static boolean mips16_small
, mips16_ext
;
869 #ifdef MIPS_STABS_ELF
870 /* The pdr segment for per procedure frame/regmask info */
876 mips_isa_to_str (isa
)
879 const struct mips_cpu_info
*ci
;
882 ci
= mips_cpu_info_from_isa (isa
);
886 sprintf (s
, "ISA#%d", isa
);
891 mips_cpu_to_str (cpu
)
894 const struct mips_cpu_info
*ci
;
897 ci
= mips_cpu_info_from_cpu (cpu
);
901 sprintf (s
, "CPU#%d", cpu
);
905 /* This function is called once, at assembler startup time. It should
906 set up all the tables, etc. that the MD part of the assembler will need. */
911 register const char *retval
= NULL
;
916 int mips_isa_from_cpu
;
917 int target_cpu_had_mips16
= 0;
918 const struct mips_cpu_info
*ci
;
920 /* GP relative stuff not working for PE */
921 if (strncmp (TARGET_OS
, "pe", 2) == 0
922 && g_switch_value
!= 0)
925 as_bad (_("-G not supported in this configuration."));
930 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
932 a
= xmalloc (sizeof TARGET_CPU
);
933 strcpy (a
, TARGET_CPU
);
934 a
[(sizeof TARGET_CPU
) - 3] = '\0';
938 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
940 target_cpu_had_mips16
= 1;
941 cpu
+= sizeof "mips16" - 1;
944 if (mips_opts
.mips16
< 0)
945 mips_opts
.mips16
= target_cpu_had_mips16
;
947 /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
948 specified on the command line, or some other value if one was.
949 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
950 the command line, or will be set otherwise if one was. */
951 if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
953 /* We have it all. There's nothing to do. */
955 else if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
957 /* We have CPU, we need ISA. */
958 ci
= mips_cpu_info_from_cpu (mips_cpu
);
960 mips_opts
.isa
= ci
->isa
;
962 else if (mips_cpu
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
964 /* We have ISA, we need default CPU. */
965 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
971 /* We need to set both ISA and CPU from target cpu. */
972 ci
= mips_cpu_info_from_name (cpu
);
974 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
976 mips_opts
.isa
= ci
->isa
;
980 ci
= mips_cpu_info_from_cpu (mips_cpu
);
982 mips_isa_from_cpu
= ci
->isa
;
984 /* End of TARGET_CPU processing, get rid of malloced memory
993 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
994 as_bad (_("trap exception not supported at ISA 1"));
996 /* Set the EABI kind based on the ISA before the user gets
997 to change the ISA with directives. This isn't really
998 the best, but then neither is basing the abi on the isa. */
999 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1001 && 0 == strcmp (mips_abi_string
,"eabi"))
1004 /* If they asked for mips1 or mips2 and a cpu that is
1005 mips3 or greater, then mark the object file 32BITMODE. */
1006 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1007 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1008 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1011 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
))
1012 as_warn (_("Could not set architecture and machine"));
1014 file_mips_isa
= mips_opts
.isa
;
1016 op_hash
= hash_new ();
1018 for (i
= 0; i
< NUMOPCODES
;)
1020 const char *name
= mips_opcodes
[i
].name
;
1022 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1025 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1026 mips_opcodes
[i
].name
, retval
);
1027 /* Probably a memory allocation problem? Give up now. */
1028 as_fatal (_("Broken assembler. No assembly attempted."));
1032 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1034 if (!validate_mips_insn (&mips_opcodes
[i
]))
1039 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1042 mips16_op_hash
= hash_new ();
1045 while (i
< bfd_mips16_num_opcodes
)
1047 const char *name
= mips16_opcodes
[i
].name
;
1049 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1051 as_fatal (_("internal: can't hash `%s': %s"),
1052 mips16_opcodes
[i
].name
, retval
);
1055 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1056 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1057 != mips16_opcodes
[i
].match
))
1059 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1060 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1065 while (i
< bfd_mips16_num_opcodes
1066 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1070 as_fatal (_("Broken assembler. No assembly attempted."));
1072 /* We add all the general register names to the symbol table. This
1073 helps us detect invalid uses of them. */
1074 for (i
= 0; i
< 32; i
++)
1078 sprintf (buf
, "$%d", i
);
1079 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1080 &zero_address_frag
));
1082 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1083 &zero_address_frag
));
1084 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1085 &zero_address_frag
));
1086 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1087 &zero_address_frag
));
1088 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1089 &zero_address_frag
));
1090 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1091 &zero_address_frag
));
1092 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1093 &zero_address_frag
));
1094 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1095 &zero_address_frag
));
1097 mips_no_prev_insn (false);
1100 mips_cprmask
[0] = 0;
1101 mips_cprmask
[1] = 0;
1102 mips_cprmask
[2] = 0;
1103 mips_cprmask
[3] = 0;
1105 /* set the default alignment for the text section (2**2) */
1106 record_alignment (text_section
, 2);
1108 if (USE_GLOBAL_POINTER_OPT
)
1109 bfd_set_gp_size (stdoutput
, g_switch_value
);
1111 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1113 /* On a native system, sections must be aligned to 16 byte
1114 boundaries. When configured for an embedded ELF target, we
1116 if (strcmp (TARGET_OS
, "elf") != 0)
1118 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1119 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1120 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1123 /* Create a .reginfo section for register masks and a .mdebug
1124 section for debugging information. */
1132 subseg
= now_subseg
;
1134 /* The ABI says this section should be loaded so that the
1135 running program can access it. However, we don't load it
1136 if we are configured for an embedded target */
1137 flags
= SEC_READONLY
| SEC_DATA
;
1138 if (strcmp (TARGET_OS
, "elf") != 0)
1139 flags
|= SEC_ALLOC
| SEC_LOAD
;
1143 sec
= subseg_new (".reginfo", (subsegT
) 0);
1145 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1146 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1149 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1154 /* The 64-bit ABI uses a .MIPS.options section rather than
1155 .reginfo section. */
1156 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1157 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1158 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1161 /* Set up the option header. */
1163 Elf_Internal_Options opthdr
;
1166 opthdr
.kind
= ODK_REGINFO
;
1167 opthdr
.size
= (sizeof (Elf_External_Options
)
1168 + sizeof (Elf64_External_RegInfo
));
1171 f
= frag_more (sizeof (Elf_External_Options
));
1172 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1173 (Elf_External_Options
*) f
);
1175 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1180 if (ECOFF_DEBUGGING
)
1182 sec
= subseg_new (".mdebug", (subsegT
) 0);
1183 (void) bfd_set_section_flags (stdoutput
, sec
,
1184 SEC_HAS_CONTENTS
| SEC_READONLY
);
1185 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1188 #ifdef MIPS_STABS_ELF
1189 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1190 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1191 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1192 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1195 subseg_set (seg
, subseg
);
1199 if (! ECOFF_DEBUGGING
)
1206 if (! ECOFF_DEBUGGING
)
1214 struct mips_cl_insn insn
;
1216 imm_expr
.X_op
= O_absent
;
1217 imm_reloc
= BFD_RELOC_UNUSED
;
1218 imm_unmatched_hi
= false;
1219 offset_expr
.X_op
= O_absent
;
1220 offset_reloc
= BFD_RELOC_UNUSED
;
1222 if (mips_opts
.mips16
)
1223 mips16_ip (str
, &insn
);
1226 mips_ip (str
, &insn
);
1227 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1228 str
, insn
.insn_opcode
));
1233 as_bad ("%s `%s'", insn_error
, str
);
1237 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1239 if (mips_opts
.mips16
)
1240 mips16_macro (&insn
);
1246 if (imm_expr
.X_op
!= O_absent
)
1247 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1249 else if (offset_expr
.X_op
!= O_absent
)
1250 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1252 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1256 /* See whether instruction IP reads register REG. CLASS is the type
1260 insn_uses_reg (ip
, reg
, class)
1261 struct mips_cl_insn
*ip
;
1263 enum mips_regclass
class;
1265 if (class == MIPS16_REG
)
1267 assert (mips_opts
.mips16
);
1268 reg
= mips16_to_32_reg_map
[reg
];
1269 class = MIPS_GR_REG
;
1272 /* Don't report on general register 0, since it never changes. */
1273 if (class == MIPS_GR_REG
&& reg
== 0)
1276 if (class == MIPS_FP_REG
)
1278 assert (! mips_opts
.mips16
);
1279 /* If we are called with either $f0 or $f1, we must check $f0.
1280 This is not optimal, because it will introduce an unnecessary
1281 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1282 need to distinguish reading both $f0 and $f1 or just one of
1283 them. Note that we don't have to check the other way,
1284 because there is no instruction that sets both $f0 and $f1
1285 and requires a delay. */
1286 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1287 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1288 == (reg
&~ (unsigned) 1)))
1290 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1291 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1292 == (reg
&~ (unsigned) 1)))
1295 else if (! mips_opts
.mips16
)
1297 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1298 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1300 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1301 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1306 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1307 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1308 & MIPS16OP_MASK_RX
)]
1311 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1312 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1313 & MIPS16OP_MASK_RY
)]
1316 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1317 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1318 & MIPS16OP_MASK_MOVE32Z
)]
1321 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1323 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1325 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1327 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1328 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1329 & MIPS16OP_MASK_REGR32
) == reg
)
1336 /* This function returns true if modifying a register requires a
1340 reg_needs_delay (reg
)
1343 unsigned long prev_pinfo
;
1345 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1346 if (! mips_opts
.noreorder
1347 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1348 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1349 || (! gpr_interlocks
1350 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1352 /* A load from a coprocessor or from memory. All load
1353 delays delay the use of general register rt for one
1354 instruction on the r3000. The r6000 and r4000 use
1356 /* Itbl support may require additional care here. */
1357 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1358 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1365 /* Mark instruction labels in mips16 mode. This permits the linker to
1366 handle them specially, such as generating jalx instructions when
1367 needed. We also make them odd for the duration of the assembly, in
1368 order to generate the right sort of code. We will make them even
1369 in the adjust_symtab routine, while leaving them marked. This is
1370 convenient for the debugger and the disassembler. The linker knows
1371 to make them odd again. */
1374 mips16_mark_labels ()
1376 if (mips_opts
.mips16
)
1378 struct insn_label_list
*l
;
1380 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1383 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1384 S_SET_OTHER (l
->label
, STO_MIPS16
);
1386 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1387 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1392 /* Output an instruction. PLACE is where to put the instruction; if
1393 it is NULL, this uses frag_more to get room. IP is the instruction
1394 information. ADDRESS_EXPR is an operand of the instruction to be
1395 used with RELOC_TYPE. */
1398 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1400 struct mips_cl_insn
*ip
;
1401 expressionS
*address_expr
;
1402 bfd_reloc_code_real_type reloc_type
;
1403 boolean unmatched_hi
;
1405 register unsigned long prev_pinfo
, pinfo
;
1410 /* Mark instruction labels in mips16 mode. */
1411 if (mips_opts
.mips16
)
1412 mips16_mark_labels ();
1414 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1415 pinfo
= ip
->insn_mo
->pinfo
;
1417 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1421 /* If the previous insn required any delay slots, see if we need
1422 to insert a NOP or two. There are eight kinds of possible
1423 hazards, of which an instruction can have at most one type.
1424 (1) a load from memory delay
1425 (2) a load from a coprocessor delay
1426 (3) an unconditional branch delay
1427 (4) a conditional branch delay
1428 (5) a move to coprocessor register delay
1429 (6) a load coprocessor register from memory delay
1430 (7) a coprocessor condition code delay
1431 (8) a HI/LO special register delay
1433 There are a lot of optimizations we could do that we don't.
1434 In particular, we do not, in general, reorder instructions.
1435 If you use gcc with optimization, it will reorder
1436 instructions and generally do much more optimization then we
1437 do here; repeating all that work in the assembler would only
1438 benefit hand written assembly code, and does not seem worth
1441 /* This is how a NOP is emitted. */
1442 #define emit_nop() \
1444 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1445 : md_number_to_chars (frag_more (4), 0, 4))
1447 /* The previous insn might require a delay slot, depending upon
1448 the contents of the current insn. */
1449 if (! mips_opts
.mips16
1450 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1451 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1452 && ! cop_interlocks
)
1453 || (! gpr_interlocks
1454 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1456 /* A load from a coprocessor or from memory. All load
1457 delays delay the use of general register rt for one
1458 instruction on the r3000. The r6000 and r4000 use
1460 /* Itbl support may require additional care here. */
1461 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1462 if (mips_optimize
== 0
1463 || insn_uses_reg (ip
,
1464 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1469 else if (! mips_opts
.mips16
1470 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1471 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1472 && ! cop_interlocks
)
1473 || (mips_opts
.isa
== ISA_MIPS1
1474 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1476 /* A generic coprocessor delay. The previous instruction
1477 modified a coprocessor general or control register. If
1478 it modified a control register, we need to avoid any
1479 coprocessor instruction (this is probably not always
1480 required, but it sometimes is). If it modified a general
1481 register, we avoid using that register.
1483 On the r6000 and r4000 loading a coprocessor register
1484 from memory is interlocked, and does not require a delay.
1486 This case is not handled very well. There is no special
1487 knowledge of CP0 handling, and the coprocessors other
1488 than the floating point unit are not distinguished at
1490 /* Itbl support may require additional care here. FIXME!
1491 Need to modify this to include knowledge about
1492 user specified delays! */
1493 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1495 if (mips_optimize
== 0
1496 || insn_uses_reg (ip
,
1497 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1502 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1504 if (mips_optimize
== 0
1505 || insn_uses_reg (ip
,
1506 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1513 /* We don't know exactly what the previous instruction
1514 does. If the current instruction uses a coprocessor
1515 register, we must insert a NOP. If previous
1516 instruction may set the condition codes, and the
1517 current instruction uses them, we must insert two
1519 /* Itbl support may require additional care here. */
1520 if (mips_optimize
== 0
1521 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1522 && (pinfo
& INSN_READ_COND_CODE
)))
1524 else if (pinfo
& INSN_COP
)
1528 else if (! mips_opts
.mips16
1529 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1530 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1531 && ! cop_interlocks
)
1533 /* The previous instruction sets the coprocessor condition
1534 codes, but does not require a general coprocessor delay
1535 (this means it is a floating point comparison
1536 instruction). If this instruction uses the condition
1537 codes, we need to insert a single NOP. */
1538 /* Itbl support may require additional care here. */
1539 if (mips_optimize
== 0
1540 || (pinfo
& INSN_READ_COND_CODE
))
1544 /* If we're fixing up mfhi/mflo for the r7000 and the
1545 previous insn was an mfhi/mflo and the current insn
1546 reads the register that the mfhi/mflo wrote to, then
1549 else if (mips_7000_hilo_fix
1550 && MF_HILO_INSN (prev_pinfo
)
1551 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1559 /* If we're fixing up mfhi/mflo for the r7000 and the
1560 2nd previous insn was an mfhi/mflo and the current insn
1561 reads the register that the mfhi/mflo wrote to, then
1564 else if (mips_7000_hilo_fix
1565 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1566 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1574 else if (prev_pinfo
& INSN_READ_LO
)
1576 /* The previous instruction reads the LO register; if the
1577 current instruction writes to the LO register, we must
1578 insert two NOPS. Some newer processors have interlocks.
1579 Also the tx39's multiply instructions can be exectuted
1580 immediatly after a read from HI/LO (without the delay),
1581 though the tx39's divide insns still do require the
1583 if (! (hilo_interlocks
1584 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1585 && (mips_optimize
== 0
1586 || (pinfo
& INSN_WRITE_LO
)))
1588 /* Most mips16 branch insns don't have a delay slot.
1589 If a read from LO is immediately followed by a branch
1590 to a write to LO we have a read followed by a write
1591 less than 2 insns away. We assume the target of
1592 a branch might be a write to LO, and insert a nop
1593 between a read and an immediately following branch. */
1594 else if (mips_opts
.mips16
1595 && (mips_optimize
== 0
1596 || (pinfo
& MIPS16_INSN_BRANCH
)))
1599 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1601 /* The previous instruction reads the HI register; if the
1602 current instruction writes to the HI register, we must
1603 insert a NOP. Some newer processors have interlocks.
1604 Also the note tx39's multiply above. */
1605 if (! (hilo_interlocks
1606 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1607 && (mips_optimize
== 0
1608 || (pinfo
& INSN_WRITE_HI
)))
1610 /* Most mips16 branch insns don't have a delay slot.
1611 If a read from HI is immediately followed by a branch
1612 to a write to HI we have a read followed by a write
1613 less than 2 insns away. We assume the target of
1614 a branch might be a write to HI, and insert a nop
1615 between a read and an immediately following branch. */
1616 else if (mips_opts
.mips16
1617 && (mips_optimize
== 0
1618 || (pinfo
& MIPS16_INSN_BRANCH
)))
1622 /* If the previous instruction was in a noreorder section, then
1623 we don't want to insert the nop after all. */
1624 /* Itbl support may require additional care here. */
1625 if (prev_insn_unreordered
)
1628 /* There are two cases which require two intervening
1629 instructions: 1) setting the condition codes using a move to
1630 coprocessor instruction which requires a general coprocessor
1631 delay and then reading the condition codes 2) reading the HI
1632 or LO register and then writing to it (except on processors
1633 which have interlocks). If we are not already emitting a NOP
1634 instruction, we must check for these cases compared to the
1635 instruction previous to the previous instruction. */
1636 if ((! mips_opts
.mips16
1637 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1638 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1639 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1640 && (pinfo
& INSN_READ_COND_CODE
)
1641 && ! cop_interlocks
)
1642 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1643 && (pinfo
& INSN_WRITE_LO
)
1644 && ! (hilo_interlocks
1645 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1646 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1647 && (pinfo
& INSN_WRITE_HI
)
1648 && ! (hilo_interlocks
1649 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1654 if (prev_prev_insn_unreordered
)
1657 if (prev_prev_nop
&& nops
== 0)
1660 /* If we are being given a nop instruction, don't bother with
1661 one of the nops we would otherwise output. This will only
1662 happen when a nop instruction is used with mips_optimize set
1665 && ! mips_opts
.noreorder
1666 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1669 /* Now emit the right number of NOP instructions. */
1670 if (nops
> 0 && ! mips_opts
.noreorder
)
1673 unsigned long old_frag_offset
;
1675 struct insn_label_list
*l
;
1677 old_frag
= frag_now
;
1678 old_frag_offset
= frag_now_fix ();
1680 for (i
= 0; i
< nops
; i
++)
1685 listing_prev_line ();
1686 /* We may be at the start of a variant frag. In case we
1687 are, make sure there is enough space for the frag
1688 after the frags created by listing_prev_line. The
1689 argument to frag_grow here must be at least as large
1690 as the argument to all other calls to frag_grow in
1691 this file. We don't have to worry about being in the
1692 middle of a variant frag, because the variants insert
1693 all needed nop instructions themselves. */
1697 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1699 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1700 symbol_set_frag (l
->label
, frag_now
);
1701 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1702 /* mips16 text labels are stored as odd. */
1703 if (mips_opts
.mips16
)
1704 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1707 #ifndef NO_ECOFF_DEBUGGING
1708 if (ECOFF_DEBUGGING
)
1709 ecoff_fix_loc (old_frag
, old_frag_offset
);
1712 else if (prev_nop_frag
!= NULL
)
1714 /* We have a frag holding nops we may be able to remove. If
1715 we don't need any nops, we can decrease the size of
1716 prev_nop_frag by the size of one instruction. If we do
1717 need some nops, we count them in prev_nops_required. */
1718 if (prev_nop_frag_since
== 0)
1722 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1723 --prev_nop_frag_holds
;
1726 prev_nop_frag_required
+= nops
;
1730 if (prev_prev_nop
== 0)
1732 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1733 --prev_nop_frag_holds
;
1736 ++prev_nop_frag_required
;
1739 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1740 prev_nop_frag
= NULL
;
1742 ++prev_nop_frag_since
;
1744 /* Sanity check: by the time we reach the second instruction
1745 after prev_nop_frag, we should have used up all the nops
1746 one way or another. */
1747 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1751 if (reloc_type
> BFD_RELOC_UNUSED
)
1753 /* We need to set up a variant frag. */
1754 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1755 f
= frag_var (rs_machine_dependent
, 4, 0,
1756 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1757 mips16_small
, mips16_ext
,
1759 & INSN_UNCOND_BRANCH_DELAY
),
1760 (prev_insn_reloc_type
1761 == BFD_RELOC_MIPS16_JMP
)),
1762 make_expr_symbol (address_expr
), (offsetT
) 0,
1765 else if (place
!= NULL
)
1767 else if (mips_opts
.mips16
1769 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1771 /* Make sure there is enough room to swap this instruction with
1772 a following jump instruction. */
1778 if (mips_opts
.mips16
1779 && mips_opts
.noreorder
1780 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1781 as_warn (_("extended instruction in delay slot"));
1787 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1789 if (address_expr
->X_op
== O_constant
)
1794 ip
->insn_opcode
|= address_expr
->X_add_number
;
1797 case BFD_RELOC_LO16
:
1798 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1801 case BFD_RELOC_MIPS_JMP
:
1802 if ((address_expr
->X_add_number
& 3) != 0)
1803 as_bad (_("jump to misaligned address (0x%lx)"),
1804 (unsigned long) address_expr
->X_add_number
);
1805 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1808 case BFD_RELOC_MIPS16_JMP
:
1809 if ((address_expr
->X_add_number
& 3) != 0)
1810 as_bad (_("jump to misaligned address (0x%lx)"),
1811 (unsigned long) address_expr
->X_add_number
);
1813 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1814 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1815 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1818 case BFD_RELOC_16_PCREL_S2
:
1828 /* Don't generate a reloc if we are writing into a variant
1832 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1834 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1838 struct mips_hi_fixup
*hi_fixup
;
1840 assert (reloc_type
== BFD_RELOC_HI16_S
);
1841 hi_fixup
= ((struct mips_hi_fixup
*)
1842 xmalloc (sizeof (struct mips_hi_fixup
)));
1843 hi_fixup
->fixp
= fixp
;
1844 hi_fixup
->seg
= now_seg
;
1845 hi_fixup
->next
= mips_hi_fixup_list
;
1846 mips_hi_fixup_list
= hi_fixup
;
1852 if (! mips_opts
.mips16
)
1853 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1854 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1856 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1857 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1863 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1866 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1869 /* Update the register mask information. */
1870 if (! mips_opts
.mips16
)
1872 if (pinfo
& INSN_WRITE_GPR_D
)
1873 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1874 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1875 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1876 if (pinfo
& INSN_READ_GPR_S
)
1877 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1878 if (pinfo
& INSN_WRITE_GPR_31
)
1879 mips_gprmask
|= 1 << 31;
1880 if (pinfo
& INSN_WRITE_FPR_D
)
1881 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1882 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1883 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1884 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1885 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1886 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1887 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1888 if (pinfo
& INSN_COP
)
1890 /* We don't keep enough information to sort these cases out.
1891 The itbl support does keep this information however, although
1892 we currently don't support itbl fprmats as part of the cop
1893 instruction. May want to add this support in the future. */
1895 /* Never set the bit for $0, which is always zero. */
1896 mips_gprmask
&=~ 1 << 0;
1900 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1901 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1902 & MIPS16OP_MASK_RX
);
1903 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1904 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1905 & MIPS16OP_MASK_RY
);
1906 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1907 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1908 & MIPS16OP_MASK_RZ
);
1909 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1910 mips_gprmask
|= 1 << TREG
;
1911 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1912 mips_gprmask
|= 1 << SP
;
1913 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1914 mips_gprmask
|= 1 << RA
;
1915 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1916 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1917 if (pinfo
& MIPS16_INSN_READ_Z
)
1918 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1919 & MIPS16OP_MASK_MOVE32Z
);
1920 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1921 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1922 & MIPS16OP_MASK_REGR32
);
1925 if (place
== NULL
&& ! mips_opts
.noreorder
)
1927 /* Filling the branch delay slot is more complex. We try to
1928 switch the branch with the previous instruction, which we can
1929 do if the previous instruction does not set up a condition
1930 that the branch tests and if the branch is not itself the
1931 target of any branch. */
1932 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1933 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1935 if (mips_optimize
< 2
1936 /* If we have seen .set volatile or .set nomove, don't
1938 || mips_opts
.nomove
!= 0
1939 /* If we had to emit any NOP instructions, then we
1940 already know we can not swap. */
1942 /* If we don't even know the previous insn, we can not
1944 || ! prev_insn_valid
1945 /* If the previous insn is already in a branch delay
1946 slot, then we can not swap. */
1947 || prev_insn_is_delay_slot
1948 /* If the previous previous insn was in a .set
1949 noreorder, we can't swap. Actually, the MIPS
1950 assembler will swap in this situation. However, gcc
1951 configured -with-gnu-as will generate code like
1957 in which we can not swap the bne and INSN. If gcc is
1958 not configured -with-gnu-as, it does not output the
1959 .set pseudo-ops. We don't have to check
1960 prev_insn_unreordered, because prev_insn_valid will
1961 be 0 in that case. We don't want to use
1962 prev_prev_insn_valid, because we do want to be able
1963 to swap at the start of a function. */
1964 || prev_prev_insn_unreordered
1965 /* If the branch is itself the target of a branch, we
1966 can not swap. We cheat on this; all we check for is
1967 whether there is a label on this instruction. If
1968 there are any branches to anything other than a
1969 label, users must use .set noreorder. */
1970 || insn_labels
!= NULL
1971 /* If the previous instruction is in a variant frag, we
1972 can not do the swap. This does not apply to the
1973 mips16, which uses variant frags for different
1975 || (! mips_opts
.mips16
1976 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1977 /* If the branch reads the condition codes, we don't
1978 even try to swap, because in the sequence
1983 we can not swap, and I don't feel like handling that
1985 || (! mips_opts
.mips16
1986 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1987 && (pinfo
& INSN_READ_COND_CODE
))
1988 /* We can not swap with an instruction that requires a
1989 delay slot, becase the target of the branch might
1990 interfere with that instruction. */
1991 || (! mips_opts
.mips16
1992 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1994 /* Itbl support may require additional care here. */
1995 & (INSN_LOAD_COPROC_DELAY
1996 | INSN_COPROC_MOVE_DELAY
1997 | INSN_WRITE_COND_CODE
)))
1998 || (! (hilo_interlocks
1999 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2003 || (! mips_opts
.mips16
2005 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2006 || (! mips_opts
.mips16
2007 && mips_opts
.isa
== ISA_MIPS1
2008 /* Itbl support may require additional care here. */
2009 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2010 /* We can not swap with a branch instruction. */
2012 & (INSN_UNCOND_BRANCH_DELAY
2013 | INSN_COND_BRANCH_DELAY
2014 | INSN_COND_BRANCH_LIKELY
))
2015 /* We do not swap with a trap instruction, since it
2016 complicates trap handlers to have the trap
2017 instruction be in a delay slot. */
2018 || (prev_pinfo
& INSN_TRAP
)
2019 /* If the branch reads a register that the previous
2020 instruction sets, we can not swap. */
2021 || (! mips_opts
.mips16
2022 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2023 && insn_uses_reg (ip
,
2024 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2027 || (! mips_opts
.mips16
2028 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2029 && insn_uses_reg (ip
,
2030 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2033 || (mips_opts
.mips16
2034 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2035 && insn_uses_reg (ip
,
2036 ((prev_insn
.insn_opcode
2038 & MIPS16OP_MASK_RX
),
2040 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2041 && insn_uses_reg (ip
,
2042 ((prev_insn
.insn_opcode
2044 & MIPS16OP_MASK_RY
),
2046 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2047 && insn_uses_reg (ip
,
2048 ((prev_insn
.insn_opcode
2050 & MIPS16OP_MASK_RZ
),
2052 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2053 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2054 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2055 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2056 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2057 && insn_uses_reg (ip
,
2058 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2061 /* If the branch writes a register that the previous
2062 instruction sets, we can not swap (we know that
2063 branches write only to RD or to $31). */
2064 || (! mips_opts
.mips16
2065 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2066 && (((pinfo
& INSN_WRITE_GPR_D
)
2067 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2068 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2069 || ((pinfo
& INSN_WRITE_GPR_31
)
2070 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2073 || (! mips_opts
.mips16
2074 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2075 && (((pinfo
& INSN_WRITE_GPR_D
)
2076 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2077 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2078 || ((pinfo
& INSN_WRITE_GPR_31
)
2079 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2082 || (mips_opts
.mips16
2083 && (pinfo
& MIPS16_INSN_WRITE_31
)
2084 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2085 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2086 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2088 /* If the branch writes a register that the previous
2089 instruction reads, we can not swap (we know that
2090 branches only write to RD or to $31). */
2091 || (! mips_opts
.mips16
2092 && (pinfo
& INSN_WRITE_GPR_D
)
2093 && insn_uses_reg (&prev_insn
,
2094 ((ip
->insn_opcode
>> OP_SH_RD
)
2097 || (! mips_opts
.mips16
2098 && (pinfo
& INSN_WRITE_GPR_31
)
2099 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2100 || (mips_opts
.mips16
2101 && (pinfo
& MIPS16_INSN_WRITE_31
)
2102 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2103 /* If we are generating embedded PIC code, the branch
2104 might be expanded into a sequence which uses $at, so
2105 we can't swap with an instruction which reads it. */
2106 || (mips_pic
== EMBEDDED_PIC
2107 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2108 /* If the previous previous instruction has a load
2109 delay, and sets a register that the branch reads, we
2111 || (! mips_opts
.mips16
2112 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2113 /* Itbl support may require additional care here. */
2114 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2115 || (! gpr_interlocks
2116 && (prev_prev_insn
.insn_mo
->pinfo
2117 & INSN_LOAD_MEMORY_DELAY
)))
2118 && insn_uses_reg (ip
,
2119 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2122 /* If one instruction sets a condition code and the
2123 other one uses a condition code, we can not swap. */
2124 || ((pinfo
& INSN_READ_COND_CODE
)
2125 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2126 || ((pinfo
& INSN_WRITE_COND_CODE
)
2127 && (prev_pinfo
& INSN_READ_COND_CODE
))
2128 /* If the previous instruction uses the PC, we can not
2130 || (mips_opts
.mips16
2131 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2132 /* If the previous instruction was extended, we can not
2134 || (mips_opts
.mips16
&& prev_insn_extended
)
2135 /* If the previous instruction had a fixup in mips16
2136 mode, we can not swap. This normally means that the
2137 previous instruction was a 4 byte branch anyhow. */
2138 || (mips_opts
.mips16
&& prev_insn_fixp
)
2139 /* If the previous instruction is a sync, sync.l, or
2140 sync.p, we can not swap. */
2141 || (prev_pinfo
& INSN_SYNC
))
2143 /* We could do even better for unconditional branches to
2144 portions of this object file; we could pick up the
2145 instruction at the destination, put it in the delay
2146 slot, and bump the destination address. */
2148 /* Update the previous insn information. */
2149 prev_prev_insn
= *ip
;
2150 prev_insn
.insn_mo
= &dummy_opcode
;
2154 /* It looks like we can actually do the swap. */
2155 if (! mips_opts
.mips16
)
2160 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2161 memcpy (temp
, prev_f
, 4);
2162 memcpy (prev_f
, f
, 4);
2163 memcpy (f
, temp
, 4);
2166 prev_insn_fixp
->fx_frag
= frag_now
;
2167 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2171 fixp
->fx_frag
= prev_insn_frag
;
2172 fixp
->fx_where
= prev_insn_where
;
2180 assert (prev_insn_fixp
== NULL
);
2181 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2182 memcpy (temp
, prev_f
, 2);
2183 memcpy (prev_f
, f
, 2);
2184 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2186 assert (reloc_type
== BFD_RELOC_UNUSED
);
2187 memcpy (f
, temp
, 2);
2191 memcpy (f
, f
+ 2, 2);
2192 memcpy (f
+ 2, temp
, 2);
2196 fixp
->fx_frag
= prev_insn_frag
;
2197 fixp
->fx_where
= prev_insn_where
;
2201 /* Update the previous insn information; leave prev_insn
2203 prev_prev_insn
= *ip
;
2205 prev_insn_is_delay_slot
= 1;
2207 /* If that was an unconditional branch, forget the previous
2208 insn information. */
2209 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2211 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2212 prev_insn
.insn_mo
= &dummy_opcode
;
2215 prev_insn_fixp
= NULL
;
2216 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2217 prev_insn_extended
= 0;
2219 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2221 /* We don't yet optimize a branch likely. What we should do
2222 is look at the target, copy the instruction found there
2223 into the delay slot, and increment the branch to jump to
2224 the next instruction. */
2226 /* Update the previous insn information. */
2227 prev_prev_insn
= *ip
;
2228 prev_insn
.insn_mo
= &dummy_opcode
;
2229 prev_insn_fixp
= NULL
;
2230 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2231 prev_insn_extended
= 0;
2235 /* Update the previous insn information. */
2237 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2239 prev_prev_insn
= prev_insn
;
2242 /* Any time we see a branch, we always fill the delay slot
2243 immediately; since this insn is not a branch, we know it
2244 is not in a delay slot. */
2245 prev_insn_is_delay_slot
= 0;
2247 prev_insn_fixp
= fixp
;
2248 prev_insn_reloc_type
= reloc_type
;
2249 if (mips_opts
.mips16
)
2250 prev_insn_extended
= (ip
->use_extend
2251 || reloc_type
> BFD_RELOC_UNUSED
);
2254 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2255 prev_insn_unreordered
= 0;
2256 prev_insn_frag
= frag_now
;
2257 prev_insn_where
= f
- frag_now
->fr_literal
;
2258 prev_insn_valid
= 1;
2260 else if (place
== NULL
)
2262 /* We need to record a bit of information even when we are not
2263 reordering, in order to determine the base address for mips16
2264 PC relative relocs. */
2265 prev_prev_insn
= prev_insn
;
2267 prev_insn_reloc_type
= reloc_type
;
2268 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2269 prev_insn_unreordered
= 1;
2272 /* We just output an insn, so the next one doesn't have a label. */
2273 mips_clear_insn_labels ();
2275 /* We must ensure that a fixup associated with an unmatched %hi
2276 reloc does not become a variant frag. Otherwise, the
2277 rearrangement of %hi relocs in frob_file may confuse
2281 frag_wane (frag_now
);
2286 /* This function forgets that there was any previous instruction or
2287 label. If PRESERVE is non-zero, it remembers enough information to
2288 know whether nops are needed before a noreorder section. */
2291 mips_no_prev_insn (preserve
)
2296 prev_insn
.insn_mo
= &dummy_opcode
;
2297 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2298 prev_nop_frag
= NULL
;
2299 prev_nop_frag_holds
= 0;
2300 prev_nop_frag_required
= 0;
2301 prev_nop_frag_since
= 0;
2303 prev_insn_valid
= 0;
2304 prev_insn_is_delay_slot
= 0;
2305 prev_insn_unreordered
= 0;
2306 prev_insn_extended
= 0;
2307 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2308 prev_prev_insn_unreordered
= 0;
2309 mips_clear_insn_labels ();
2312 /* This function must be called whenever we turn on noreorder or emit
2313 something other than instructions. It inserts any NOPS which might
2314 be needed by the previous instruction, and clears the information
2315 kept for the previous instructions. The INSNS parameter is true if
2316 instructions are to follow. */
2319 mips_emit_delays (insns
)
2322 if (! mips_opts
.noreorder
)
2327 if ((! mips_opts
.mips16
2328 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2329 && (! cop_interlocks
2330 && (prev_insn
.insn_mo
->pinfo
2331 & (INSN_LOAD_COPROC_DELAY
2332 | INSN_COPROC_MOVE_DELAY
2333 | INSN_WRITE_COND_CODE
))))
2334 || (! hilo_interlocks
2335 && (prev_insn
.insn_mo
->pinfo
2338 || (! mips_opts
.mips16
2340 && (prev_insn
.insn_mo
->pinfo
2341 & INSN_LOAD_MEMORY_DELAY
))
2342 || (! mips_opts
.mips16
2343 && mips_opts
.isa
== ISA_MIPS1
2344 && (prev_insn
.insn_mo
->pinfo
2345 & INSN_COPROC_MEMORY_DELAY
)))
2347 /* Itbl support may require additional care here. */
2349 if ((! mips_opts
.mips16
2350 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2351 && (! cop_interlocks
2352 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2353 || (! hilo_interlocks
2354 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2355 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2358 if (prev_insn_unreordered
)
2361 else if ((! mips_opts
.mips16
2362 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2363 && (! cop_interlocks
2364 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2365 || (! hilo_interlocks
2366 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2367 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2369 /* Itbl support may require additional care here. */
2370 if (! prev_prev_insn_unreordered
)
2376 struct insn_label_list
*l
;
2380 /* Record the frag which holds the nop instructions, so
2381 that we can remove them if we don't need them. */
2382 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2383 prev_nop_frag
= frag_now
;
2384 prev_nop_frag_holds
= nops
;
2385 prev_nop_frag_required
= 0;
2386 prev_nop_frag_since
= 0;
2389 for (; nops
> 0; --nops
)
2394 /* Move on to a new frag, so that it is safe to simply
2395 decrease the size of prev_nop_frag. */
2396 frag_wane (frag_now
);
2400 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2402 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2403 symbol_set_frag (l
->label
, frag_now
);
2404 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2405 /* mips16 text labels are stored as odd. */
2406 if (mips_opts
.mips16
)
2407 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2412 /* Mark instruction labels in mips16 mode. */
2413 if (mips_opts
.mips16
&& insns
)
2414 mips16_mark_labels ();
2416 mips_no_prev_insn (insns
);
2419 /* Build an instruction created by a macro expansion. This is passed
2420 a pointer to the count of instructions created so far, an
2421 expression, the name of the instruction to build, an operand format
2422 string, and corresponding arguments. */
2426 macro_build (char *place
,
2434 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2443 struct mips_cl_insn insn
;
2444 bfd_reloc_code_real_type r
;
2448 va_start (args
, fmt
);
2454 * If the macro is about to expand into a second instruction,
2455 * print a warning if needed. We need to pass ip as a parameter
2456 * to generate a better warning message here...
2458 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2459 as_warn (_("Macro instruction expanded into multiple instructions"));
2462 *counter
+= 1; /* bump instruction counter */
2464 if (mips_opts
.mips16
)
2466 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2471 r
= BFD_RELOC_UNUSED
;
2472 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2473 assert (insn
.insn_mo
);
2474 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2476 /* Search until we get a match for NAME. */
2479 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2480 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2481 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2483 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2487 assert (insn
.insn_mo
->name
);
2488 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2491 insn
.insn_opcode
= insn
.insn_mo
->match
;
2507 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2513 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2518 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2523 int tmp
= va_arg (args
, int);
2525 insn
.insn_opcode
|= tmp
<< 16;
2526 insn
.insn_opcode
|= tmp
<< 11;
2532 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2539 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2543 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2547 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2551 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2555 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2562 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2568 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2569 assert (r
== BFD_RELOC_MIPS_GPREL
2570 || r
== BFD_RELOC_MIPS_LITERAL
2571 || r
== BFD_RELOC_LO16
2572 || r
== BFD_RELOC_MIPS_GOT16
2573 || r
== BFD_RELOC_MIPS_CALL16
2574 || r
== BFD_RELOC_MIPS_GOT_LO16
2575 || r
== BFD_RELOC_MIPS_CALL_LO16
2576 || (ep
->X_op
== O_subtract
2577 && r
== BFD_RELOC_PCREL_LO16
));
2581 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2583 && (ep
->X_op
== O_constant
2584 || (ep
->X_op
== O_symbol
2585 && (r
== BFD_RELOC_HI16_S
2586 || r
== BFD_RELOC_HI16
2587 || r
== BFD_RELOC_MIPS_GOT_HI16
2588 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2589 || (ep
->X_op
== O_subtract
2590 && r
== BFD_RELOC_PCREL_HI16_S
)));
2591 if (ep
->X_op
== O_constant
)
2593 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2595 r
= BFD_RELOC_UNUSED
;
2600 assert (ep
!= NULL
);
2602 * This allows macro() to pass an immediate expression for
2603 * creating short branches without creating a symbol.
2604 * Note that the expression still might come from the assembly
2605 * input, in which case the value is not checked for range nor
2606 * is a relocation entry generated (yuck).
2608 if (ep
->X_op
== O_constant
)
2610 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2614 r
= BFD_RELOC_16_PCREL_S2
;
2618 assert (ep
!= NULL
);
2619 r
= BFD_RELOC_MIPS_JMP
;
2623 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2632 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2634 append_insn (place
, &insn
, ep
, r
, false);
2638 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2640 int *counter ATTRIBUTE_UNUSED
;
2646 struct mips_cl_insn insn
;
2647 bfd_reloc_code_real_type r
;
2649 r
= BFD_RELOC_UNUSED
;
2650 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2651 assert (insn
.insn_mo
);
2652 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2654 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2655 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2658 assert (insn
.insn_mo
->name
);
2659 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2662 insn
.insn_opcode
= insn
.insn_mo
->match
;
2663 insn
.use_extend
= false;
2682 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2687 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2691 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2695 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2705 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2712 regno
= va_arg (args
, int);
2713 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2714 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2735 assert (ep
!= NULL
);
2737 if (ep
->X_op
!= O_constant
)
2738 r
= BFD_RELOC_UNUSED
+ c
;
2741 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2742 false, false, &insn
.insn_opcode
,
2743 &insn
.use_extend
, &insn
.extend
);
2745 r
= BFD_RELOC_UNUSED
;
2751 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2758 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2760 append_insn (place
, &insn
, ep
, r
, false);
2764 * Generate a "lui" instruction.
2767 macro_build_lui (place
, counter
, ep
, regnum
)
2773 expressionS high_expr
;
2774 struct mips_cl_insn insn
;
2775 bfd_reloc_code_real_type r
;
2776 CONST
char *name
= "lui";
2777 CONST
char *fmt
= "t,u";
2779 assert (! mips_opts
.mips16
);
2785 high_expr
.X_op
= O_constant
;
2786 high_expr
.X_add_number
= ep
->X_add_number
;
2789 if (high_expr
.X_op
== O_constant
)
2791 /* we can compute the instruction now without a relocation entry */
2792 if (high_expr
.X_add_number
& 0x8000)
2793 high_expr
.X_add_number
+= 0x10000;
2794 high_expr
.X_add_number
=
2795 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2796 r
= BFD_RELOC_UNUSED
;
2800 assert (ep
->X_op
== O_symbol
);
2801 /* _gp_disp is a special case, used from s_cpload. */
2802 assert (mips_pic
== NO_PIC
2803 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2804 r
= BFD_RELOC_HI16_S
;
2808 * If the macro is about to expand into a second instruction,
2809 * print a warning if needed. We need to pass ip as a parameter
2810 * to generate a better warning message here...
2812 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2813 as_warn (_("Macro instruction expanded into multiple instructions"));
2816 *counter
+= 1; /* bump instruction counter */
2818 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2819 assert (insn
.insn_mo
);
2820 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2821 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2823 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2824 if (r
== BFD_RELOC_UNUSED
)
2826 insn
.insn_opcode
|= high_expr
.X_add_number
;
2827 append_insn (place
, &insn
, NULL
, r
, false);
2830 append_insn (place
, &insn
, &high_expr
, r
, false);
2834 * Generates code to set the $at register to true (one)
2835 * if reg is less than the immediate expression.
2838 set_at (counter
, reg
, unsignedp
)
2843 if (imm_expr
.X_op
== O_constant
2844 && imm_expr
.X_add_number
>= -0x8000
2845 && imm_expr
.X_add_number
< 0x8000)
2846 macro_build ((char *) NULL
, counter
, &imm_expr
,
2847 unsignedp
? "sltiu" : "slti",
2848 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2851 load_register (counter
, AT
, &imm_expr
, 0);
2852 macro_build ((char *) NULL
, counter
, NULL
,
2853 unsignedp
? "sltu" : "slt",
2854 "d,v,t", AT
, reg
, AT
);
2858 /* Warn if an expression is not a constant. */
2861 check_absolute_expr (ip
, ex
)
2862 struct mips_cl_insn
*ip
;
2865 if (ex
->X_op
== O_big
)
2866 as_bad (_("unsupported large constant"));
2867 else if (ex
->X_op
!= O_constant
)
2868 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2871 /* Count the leading zeroes by performing a binary chop. This is a
2872 bulky bit of source, but performance is a LOT better for the
2873 majority of values than a simple loop to count the bits:
2874 for (lcnt = 0; (lcnt < 32); lcnt++)
2875 if ((v) & (1 << (31 - lcnt)))
2877 However it is not code size friendly, and the gain will drop a bit
2878 on certain cached systems.
2880 #define COUNT_TOP_ZEROES(v) \
2881 (((v) & ~0xffff) == 0 \
2882 ? ((v) & ~0xff) == 0 \
2883 ? ((v) & ~0xf) == 0 \
2884 ? ((v) & ~0x3) == 0 \
2885 ? ((v) & ~0x1) == 0 \
2890 : ((v) & ~0x7) == 0 \
2893 : ((v) & ~0x3f) == 0 \
2894 ? ((v) & ~0x1f) == 0 \
2897 : ((v) & ~0x7f) == 0 \
2900 : ((v) & ~0xfff) == 0 \
2901 ? ((v) & ~0x3ff) == 0 \
2902 ? ((v) & ~0x1ff) == 0 \
2905 : ((v) & ~0x7ff) == 0 \
2908 : ((v) & ~0x3fff) == 0 \
2909 ? ((v) & ~0x1fff) == 0 \
2912 : ((v) & ~0x7fff) == 0 \
2915 : ((v) & ~0xffffff) == 0 \
2916 ? ((v) & ~0xfffff) == 0 \
2917 ? ((v) & ~0x3ffff) == 0 \
2918 ? ((v) & ~0x1ffff) == 0 \
2921 : ((v) & ~0x7ffff) == 0 \
2924 : ((v) & ~0x3fffff) == 0 \
2925 ? ((v) & ~0x1fffff) == 0 \
2928 : ((v) & ~0x7fffff) == 0 \
2931 : ((v) & ~0xfffffff) == 0 \
2932 ? ((v) & ~0x3ffffff) == 0 \
2933 ? ((v) & ~0x1ffffff) == 0 \
2936 : ((v) & ~0x7ffffff) == 0 \
2939 : ((v) & ~0x3fffffff) == 0 \
2940 ? ((v) & ~0x1fffffff) == 0 \
2943 : ((v) & ~0x7fffffff) == 0 \
2948 * This routine generates the least number of instructions neccessary to load
2949 * an absolute expression value into a register.
2952 load_register (counter
, reg
, ep
, dbl
)
2959 expressionS hi32
, lo32
;
2961 if (ep
->X_op
!= O_big
)
2963 assert (ep
->X_op
== O_constant
);
2964 if (ep
->X_add_number
< 0x8000
2965 && (ep
->X_add_number
>= 0
2966 || (ep
->X_add_number
>= -0x8000
2969 || sizeof (ep
->X_add_number
) > 4))))
2971 /* We can handle 16 bit signed values with an addiu to
2972 $zero. No need to ever use daddiu here, since $zero and
2973 the result are always correct in 32 bit mode. */
2974 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2975 (int) BFD_RELOC_LO16
);
2978 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2980 /* We can handle 16 bit unsigned values with an ori to
2982 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2983 (int) BFD_RELOC_LO16
);
2986 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2987 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2988 == ~ (offsetT
) 0x7fffffff))
2991 || sizeof (ep
->X_add_number
) > 4
2992 || (ep
->X_add_number
& 0x80000000) == 0))
2993 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
2994 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2995 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
2997 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2998 == ~ (offsetT
) 0xffffffff)))
3000 /* 32 bit values require an lui. */
3001 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3002 (int) BFD_RELOC_HI16
);
3003 if ((ep
->X_add_number
& 0xffff) != 0)
3004 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3005 (int) BFD_RELOC_LO16
);
3010 /* The value is larger than 32 bits. */
3012 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3014 as_bad (_("Number larger than 32 bits"));
3015 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3016 (int) BFD_RELOC_LO16
);
3020 if (ep
->X_op
!= O_big
)
3023 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3024 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3025 hi32
.X_add_number
&= 0xffffffff;
3027 lo32
.X_add_number
&= 0xffffffff;
3031 assert (ep
->X_add_number
> 2);
3032 if (ep
->X_add_number
== 3)
3033 generic_bignum
[3] = 0;
3034 else if (ep
->X_add_number
> 4)
3035 as_bad (_("Number larger than 64 bits"));
3036 lo32
.X_op
= O_constant
;
3037 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3038 hi32
.X_op
= O_constant
;
3039 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3042 if (hi32
.X_add_number
== 0)
3047 unsigned long hi
, lo
;
3049 if (hi32
.X_add_number
== 0xffffffff)
3051 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3053 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3054 reg
, 0, (int) BFD_RELOC_LO16
);
3057 if (lo32
.X_add_number
& 0x80000000)
3059 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3060 (int) BFD_RELOC_HI16
);
3061 if (lo32
.X_add_number
& 0xffff)
3062 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3063 reg
, reg
, (int) BFD_RELOC_LO16
);
3068 /* Check for 16bit shifted constant. We know that hi32 is
3069 non-zero, so start the mask on the first bit of the hi32
3074 unsigned long himask
, lomask
;
3078 himask
= 0xffff >> (32 - shift
);
3079 lomask
= (0xffff << shift
) & 0xffffffff;
3083 himask
= 0xffff << (shift
- 32);
3086 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3087 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3091 tmp
.X_op
= O_constant
;
3093 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3094 | (lo32
.X_add_number
>> shift
));
3096 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3097 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3098 (int) BFD_RELOC_LO16
);
3099 macro_build ((char *) NULL
, counter
, NULL
,
3100 (shift
>= 32) ? "dsll32" : "dsll",
3102 (shift
>= 32) ? shift
- 32 : shift
);
3106 } while (shift
<= (64 - 16));
3108 /* Find the bit number of the lowest one bit, and store the
3109 shifted value in hi/lo. */
3110 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3111 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3115 while ((lo
& 1) == 0)
3120 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3126 while ((hi
& 1) == 0)
3135 /* Optimize if the shifted value is a (power of 2) - 1. */
3136 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3137 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3139 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3144 /* This instruction will set the register to be all
3146 tmp
.X_op
= O_constant
;
3147 tmp
.X_add_number
= (offsetT
) -1;
3148 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3149 reg
, 0, (int) BFD_RELOC_LO16
);
3153 macro_build ((char *) NULL
, counter
, NULL
,
3154 (bit
>= 32) ? "dsll32" : "dsll",
3156 (bit
>= 32) ? bit
- 32 : bit
);
3158 macro_build ((char *) NULL
, counter
, NULL
,
3159 (shift
>= 32) ? "dsrl32" : "dsrl",
3161 (shift
>= 32) ? shift
- 32 : shift
);
3166 /* Sign extend hi32 before calling load_register, because we can
3167 generally get better code when we load a sign extended value. */
3168 if ((hi32
.X_add_number
& 0x80000000) != 0)
3169 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3170 load_register (counter
, reg
, &hi32
, 0);
3173 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3177 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3186 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3188 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3189 (int) BFD_RELOC_HI16
);
3190 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3197 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3202 mid16
.X_add_number
>>= 16;
3203 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3204 freg
, (int) BFD_RELOC_LO16
);
3205 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3209 if ((lo32
.X_add_number
& 0xffff) != 0)
3210 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3211 (int) BFD_RELOC_LO16
);
3214 /* Load an address into a register. */
3217 load_address (counter
, reg
, ep
)
3224 if (ep
->X_op
!= O_constant
3225 && ep
->X_op
!= O_symbol
)
3227 as_bad (_("expression too complex"));
3228 ep
->X_op
= O_constant
;
3231 if (ep
->X_op
== O_constant
)
3233 load_register (counter
, reg
, ep
, 0);
3237 if (mips_pic
== NO_PIC
)
3239 /* If this is a reference to a GP relative symbol, we want
3240 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3242 lui $reg,<sym> (BFD_RELOC_HI16_S)
3243 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3244 If we have an addend, we always use the latter form. */
3245 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3246 || nopic_need_relax (ep
->X_add_symbol
, 1))
3251 macro_build ((char *) NULL
, counter
, ep
,
3252 ((bfd_arch_bits_per_address (stdoutput
) == 32
3253 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3254 ? "addiu" : "daddiu"),
3255 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3256 p
= frag_var (rs_machine_dependent
, 8, 0,
3257 RELAX_ENCODE (4, 8, 0, 4, 0,
3258 mips_opts
.warn_about_macros
),
3259 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3261 macro_build_lui (p
, counter
, ep
, reg
);
3264 macro_build (p
, counter
, ep
,
3265 ((bfd_arch_bits_per_address (stdoutput
) == 32
3266 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3267 ? "addiu" : "daddiu"),
3268 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3270 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3274 /* If this is a reference to an external symbol, we want
3275 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3277 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3279 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3280 If there is a constant, it must be added in after. */
3281 ex
.X_add_number
= ep
->X_add_number
;
3282 ep
->X_add_number
= 0;
3284 macro_build ((char *) NULL
, counter
, ep
,
3285 ((bfd_arch_bits_per_address (stdoutput
) == 32
3286 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3288 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3289 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3290 p
= frag_var (rs_machine_dependent
, 4, 0,
3291 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3292 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3293 macro_build (p
, counter
, ep
,
3294 ((bfd_arch_bits_per_address (stdoutput
) == 32
3295 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3296 ? "addiu" : "daddiu"),
3297 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3298 if (ex
.X_add_number
!= 0)
3300 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3301 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3302 ex
.X_op
= O_constant
;
3303 macro_build ((char *) NULL
, counter
, &ex
,
3304 ((bfd_arch_bits_per_address (stdoutput
) == 32
3305 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3306 ? "addiu" : "daddiu"),
3307 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3310 else if (mips_pic
== SVR4_PIC
)
3315 /* This is the large GOT case. If this is a reference to an
3316 external symbol, we want
3317 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3319 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3320 Otherwise, for a reference to a local symbol, we want
3321 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3323 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3324 If there is a constant, it must be added in after. */
3325 ex
.X_add_number
= ep
->X_add_number
;
3326 ep
->X_add_number
= 0;
3327 if (reg_needs_delay (GP
))
3332 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3333 (int) BFD_RELOC_MIPS_GOT_HI16
);
3334 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3335 ((bfd_arch_bits_per_address (stdoutput
) == 32
3336 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3337 ? "addu" : "daddu"),
3338 "d,v,t", reg
, reg
, GP
);
3339 macro_build ((char *) NULL
, counter
, ep
,
3340 ((bfd_arch_bits_per_address (stdoutput
) == 32
3341 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3343 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3344 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3345 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3346 mips_opts
.warn_about_macros
),
3347 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3350 /* We need a nop before loading from $gp. This special
3351 check is required because the lui which starts the main
3352 instruction stream does not refer to $gp, and so will not
3353 insert the nop which may be required. */
3354 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3357 macro_build (p
, counter
, ep
,
3358 ((bfd_arch_bits_per_address (stdoutput
) == 32
3359 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3361 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3363 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3365 macro_build (p
, counter
, ep
,
3366 ((bfd_arch_bits_per_address (stdoutput
) == 32
3367 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3368 ? "addiu" : "daddiu"),
3369 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3370 if (ex
.X_add_number
!= 0)
3372 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3373 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3374 ex
.X_op
= O_constant
;
3375 macro_build ((char *) NULL
, counter
, &ex
,
3376 ((bfd_arch_bits_per_address (stdoutput
) == 32
3377 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3378 ? "addiu" : "daddiu"),
3379 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3382 else if (mips_pic
== EMBEDDED_PIC
)
3385 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3387 macro_build ((char *) NULL
, counter
, ep
,
3388 ((bfd_arch_bits_per_address (stdoutput
) == 32
3389 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3390 ? "addiu" : "daddiu"),
3391 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3399 * This routine implements the seemingly endless macro or synthesized
3400 * instructions and addressing modes in the mips assembly language. Many
3401 * of these macros are simple and are similar to each other. These could
3402 * probably be handled by some kind of table or grammer aproach instead of
3403 * this verbose method. Others are not simple macros but are more like
3404 * optimizing code generation.
3405 * One interesting optimization is when several store macros appear
3406 * consecutivly that would load AT with the upper half of the same address.
3407 * The ensuing load upper instructions are ommited. This implies some kind
3408 * of global optimization. We currently only optimize within a single macro.
3409 * For many of the load and store macros if the address is specified as a
3410 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3411 * first load register 'at' with zero and use it as the base register. The
3412 * mips assembler simply uses register $zero. Just one tiny optimization
3417 struct mips_cl_insn
*ip
;
3419 register int treg
, sreg
, dreg
, breg
;
3435 bfd_reloc_code_real_type r
;
3437 int hold_mips_optimize
;
3439 assert (! mips_opts
.mips16
);
3441 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3442 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3443 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3444 mask
= ip
->insn_mo
->mask
;
3446 expr1
.X_op
= O_constant
;
3447 expr1
.X_op_symbol
= NULL
;
3448 expr1
.X_add_symbol
= NULL
;
3449 expr1
.X_add_number
= 1;
3461 mips_emit_delays (true);
3462 ++mips_opts
.noreorder
;
3463 mips_any_noreorder
= 1;
3465 expr1
.X_add_number
= 8;
3466 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3468 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3471 macro_build ((char *) NULL
, &icnt
, NULL
,
3472 dbl
? "dsub" : "sub",
3473 "d,v,t", dreg
, 0, sreg
);
3475 --mips_opts
.noreorder
;
3496 if (imm_expr
.X_op
== O_constant
3497 && imm_expr
.X_add_number
>= -0x8000
3498 && imm_expr
.X_add_number
< 0x8000)
3500 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3501 (int) BFD_RELOC_LO16
);
3504 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3505 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3524 if (imm_expr
.X_op
== O_constant
3525 && imm_expr
.X_add_number
>= 0
3526 && imm_expr
.X_add_number
< 0x10000)
3528 if (mask
!= M_NOR_I
)
3529 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3530 sreg
, (int) BFD_RELOC_LO16
);
3533 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3534 treg
, sreg
, (int) BFD_RELOC_LO16
);
3535 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3541 load_register (&icnt
, AT
, &imm_expr
, 0);
3542 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3559 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3565 load_register (&icnt
, AT
, &imm_expr
, 0);
3566 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3574 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3575 likely
? "bgezl" : "bgez",
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3582 likely
? "blezl" : "blez",
3586 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3588 likely
? "beql" : "beq",
3595 /* check for > max integer */
3596 maxnum
= 0x7fffffff;
3597 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3604 if (imm_expr
.X_op
== O_constant
3605 && imm_expr
.X_add_number
>= maxnum
3606 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3609 /* result is always false */
3612 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3613 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3617 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3623 if (imm_expr
.X_op
!= O_constant
)
3624 as_bad (_("Unsupported large constant"));
3625 imm_expr
.X_add_number
++;
3629 if (mask
== M_BGEL_I
)
3631 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3634 likely
? "bgezl" : "bgez",
3638 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3640 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3641 likely
? "bgtzl" : "bgtz",
3645 maxnum
= 0x7fffffff;
3646 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3653 maxnum
= - maxnum
- 1;
3654 if (imm_expr
.X_op
== O_constant
3655 && imm_expr
.X_add_number
<= maxnum
3656 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3659 /* result is always true */
3660 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3661 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3664 set_at (&icnt
, sreg
, 0);
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3666 likely
? "beql" : "beq",
3677 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3678 likely
? "beql" : "beq",
3682 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3685 likely
? "beql" : "beq",
3693 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3694 && imm_expr
.X_op
== O_constant
3695 && imm_expr
.X_add_number
== 0xffffffff))
3697 if (imm_expr
.X_op
!= O_constant
)
3698 as_bad (_("Unsupported large constant"));
3699 imm_expr
.X_add_number
++;
3703 if (mask
== M_BGEUL_I
)
3705 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3707 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3710 likely
? "bnel" : "bne",
3714 set_at (&icnt
, sreg
, 1);
3715 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3716 likely
? "beql" : "beq",
3725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3726 likely
? "bgtzl" : "bgtz",
3732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3733 likely
? "bltzl" : "bltz",
3737 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3739 likely
? "bnel" : "bne",
3748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3749 likely
? "bnel" : "bne",
3755 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3757 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3758 likely
? "bnel" : "bne",
3767 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3768 likely
? "blezl" : "blez",
3774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3775 likely
? "bgezl" : "bgez",
3779 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "beql" : "beq",
3788 maxnum
= 0x7fffffff;
3789 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3796 if (imm_expr
.X_op
== O_constant
3797 && imm_expr
.X_add_number
>= maxnum
3798 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3800 if (imm_expr
.X_op
!= O_constant
)
3801 as_bad (_("Unsupported large constant"));
3802 imm_expr
.X_add_number
++;
3806 if (mask
== M_BLTL_I
)
3808 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3810 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3811 likely
? "bltzl" : "bltz",
3815 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3818 likely
? "blezl" : "blez",
3822 set_at (&icnt
, sreg
, 0);
3823 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3824 likely
? "bnel" : "bne",
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3834 likely
? "beql" : "beq",
3840 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "beql" : "beq",
3851 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3852 && imm_expr
.X_op
== O_constant
3853 && imm_expr
.X_add_number
== 0xffffffff))
3855 if (imm_expr
.X_op
!= O_constant
)
3856 as_bad (_("Unsupported large constant"));
3857 imm_expr
.X_add_number
++;
3861 if (mask
== M_BLTUL_I
)
3863 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3865 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3868 likely
? "beql" : "beq",
3872 set_at (&icnt
, sreg
, 1);
3873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3874 likely
? "bnel" : "bne",
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3884 likely
? "bltzl" : "bltz",
3890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3891 likely
? "bgtzl" : "bgtz",
3895 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "bnel" : "bne",
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3909 likely
? "bnel" : "bne",
3913 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3916 likely
? "bnel" : "bne",
3932 as_warn (_("Divide by zero."));
3934 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3940 mips_emit_delays (true);
3941 ++mips_opts
.noreorder
;
3942 mips_any_noreorder
= 1;
3945 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3946 macro_build ((char *) NULL
, &icnt
, NULL
,
3947 dbl
? "ddiv" : "div",
3948 "z,s,t", sreg
, treg
);
3952 expr1
.X_add_number
= 8;
3953 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3954 macro_build ((char *) NULL
, &icnt
, NULL
,
3955 dbl
? "ddiv" : "div",
3956 "z,s,t", sreg
, treg
);
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3959 expr1
.X_add_number
= -1;
3960 macro_build ((char *) NULL
, &icnt
, &expr1
,
3961 dbl
? "daddiu" : "addiu",
3962 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3963 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3964 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3967 expr1
.X_add_number
= 1;
3968 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3969 (int) BFD_RELOC_LO16
);
3970 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3975 expr1
.X_add_number
= 0x80000000;
3976 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3977 (int) BFD_RELOC_HI16
);
3981 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3982 /* We want to close the noreorder block as soon as possible, so
3983 that later insns are available for delay slot filling. */
3984 --mips_opts
.noreorder
;
3988 expr1
.X_add_number
= 8;
3989 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3990 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3992 /* We want to close the noreorder block as soon as possible, so
3993 that later insns are available for delay slot filling. */
3994 --mips_opts
.noreorder
;
3996 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3998 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4037 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4039 as_warn (_("Divide by zero."));
4041 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4043 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4046 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4048 if (strcmp (s2
, "mflo") == 0)
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4052 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4055 if (imm_expr
.X_op
== O_constant
4056 && imm_expr
.X_add_number
== -1
4057 && s
[strlen (s
) - 1] != 'u')
4059 if (strcmp (s2
, "mflo") == 0)
4062 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4065 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4069 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4073 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4074 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4075 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4094 mips_emit_delays (true);
4095 ++mips_opts
.noreorder
;
4096 mips_any_noreorder
= 1;
4099 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4100 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4101 /* We want to close the noreorder block as soon as possible, so
4102 that later insns are available for delay slot filling. */
4103 --mips_opts
.noreorder
;
4107 expr1
.X_add_number
= 8;
4108 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4109 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4111 /* We want to close the noreorder block as soon as possible, so
4112 that later insns are available for delay slot filling. */
4113 --mips_opts
.noreorder
;
4114 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4116 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4122 /* Load the address of a symbol into a register. If breg is not
4123 zero, we then add a base register to it. */
4125 /* When generating embedded PIC code, we permit expressions of
4128 where bar is an address in the current section. These are used
4129 when getting the addresses of functions. We don't permit
4130 X_add_number to be non-zero, because if the symbol is
4131 external the relaxing code needs to know that any addend is
4132 purely the offset to X_op_symbol. */
4133 if (mips_pic
== EMBEDDED_PIC
4134 && offset_expr
.X_op
== O_subtract
4135 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4136 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4137 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4139 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4143 && (offset_expr
.X_add_number
== 0
4144 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4147 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4149 ((bfd_arch_bits_per_address (stdoutput
) == 32
4150 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4151 ? "addiu" : "daddiu"),
4152 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4156 if (offset_expr
.X_op
!= O_symbol
4157 && offset_expr
.X_op
!= O_constant
)
4159 as_bad (_("expression too complex"));
4160 offset_expr
.X_op
= O_constant
;
4174 if (offset_expr
.X_op
== O_constant
)
4175 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4176 else if (mips_pic
== NO_PIC
)
4178 /* If this is a reference to an GP relative symbol, we want
4179 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4181 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4182 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4183 If we have a constant, we need two instructions anyhow,
4184 so we may as well always use the latter form. */
4185 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4186 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4192 ((bfd_arch_bits_per_address (stdoutput
) == 32
4193 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4194 ? "addiu" : "daddiu"),
4195 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4196 p
= frag_var (rs_machine_dependent
, 8, 0,
4197 RELAX_ENCODE (4, 8, 0, 4, 0,
4198 mips_opts
.warn_about_macros
),
4199 offset_expr
.X_add_symbol
, (offsetT
) 0,
4202 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4205 macro_build (p
, &icnt
, &offset_expr
,
4206 ((bfd_arch_bits_per_address (stdoutput
) == 32
4207 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4208 ? "addiu" : "daddiu"),
4209 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4211 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4213 /* If this is a reference to an external symbol, and there
4214 is no constant, we want
4215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4216 For a local symbol, we want
4217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4219 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4221 If we have a small constant, and this is a reference to
4222 an external symbol, we want
4223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4225 addiu $tempreg,$tempreg,<constant>
4226 For a local symbol, we want the same instruction
4227 sequence, but we output a BFD_RELOC_LO16 reloc on the
4230 If we have a large constant, and this is a reference to
4231 an external symbol, we want
4232 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4233 lui $at,<hiconstant>
4234 addiu $at,$at,<loconstant>
4235 addu $tempreg,$tempreg,$at
4236 For a local symbol, we want the same instruction
4237 sequence, but we output a BFD_RELOC_LO16 reloc on the
4238 addiu instruction. */
4239 expr1
.X_add_number
= offset_expr
.X_add_number
;
4240 offset_expr
.X_add_number
= 0;
4242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4244 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4245 if (expr1
.X_add_number
== 0)
4253 /* We're going to put in an addu instruction using
4254 tempreg, so we may as well insert the nop right
4256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4260 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4261 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4263 ? mips_opts
.warn_about_macros
4265 offset_expr
.X_add_symbol
, (offsetT
) 0,
4269 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4272 macro_build (p
, &icnt
, &expr1
,
4273 ((bfd_arch_bits_per_address (stdoutput
) == 32
4274 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4275 ? "addiu" : "daddiu"),
4276 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4277 /* FIXME: If breg == 0, and the next instruction uses
4278 $tempreg, then if this variant case is used an extra
4279 nop will be generated. */
4281 else if (expr1
.X_add_number
>= -0x8000
4282 && expr1
.X_add_number
< 0x8000)
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4286 macro_build ((char *) NULL
, &icnt
, &expr1
,
4287 ((bfd_arch_bits_per_address (stdoutput
) == 32
4288 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4289 ? "addiu" : "daddiu"),
4290 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4291 (void) frag_var (rs_machine_dependent
, 0, 0,
4292 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4293 offset_expr
.X_add_symbol
, (offsetT
) 0,
4300 /* If we are going to add in a base register, and the
4301 target register and the base register are the same,
4302 then we are using AT as a temporary register. Since
4303 we want to load the constant into AT, we add our
4304 current AT (from the global offset table) and the
4305 register into the register now, and pretend we were
4306 not using a base register. */
4311 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4314 ((bfd_arch_bits_per_address (stdoutput
) == 32
4315 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4316 ? "addu" : "daddu"),
4317 "d,v,t", treg
, AT
, breg
);
4323 /* Set mips_optimize around the lui instruction to avoid
4324 inserting an unnecessary nop after the lw. */
4325 hold_mips_optimize
= mips_optimize
;
4327 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4328 mips_optimize
= hold_mips_optimize
;
4330 macro_build ((char *) NULL
, &icnt
, &expr1
,
4331 ((bfd_arch_bits_per_address (stdoutput
) == 32
4332 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4333 ? "addiu" : "daddiu"),
4334 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4336 ((bfd_arch_bits_per_address (stdoutput
) == 32
4337 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4338 ? "addu" : "daddu"),
4339 "d,v,t", tempreg
, tempreg
, AT
);
4340 (void) frag_var (rs_machine_dependent
, 0, 0,
4341 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4342 offset_expr
.X_add_symbol
, (offsetT
) 0,
4347 else if (mips_pic
== SVR4_PIC
)
4351 /* This is the large GOT case. If this is a reference to an
4352 external symbol, and there is no constant, we want
4353 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4354 addu $tempreg,$tempreg,$gp
4355 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4356 For a local symbol, we want
4357 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4359 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4361 If we have a small constant, and this is a reference to
4362 an external symbol, we want
4363 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4364 addu $tempreg,$tempreg,$gp
4365 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4367 addiu $tempreg,$tempreg,<constant>
4368 For a local symbol, we want
4369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4371 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4373 If we have a large constant, and this is a reference to
4374 an external symbol, we want
4375 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4376 addu $tempreg,$tempreg,$gp
4377 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4378 lui $at,<hiconstant>
4379 addiu $at,$at,<loconstant>
4380 addu $tempreg,$tempreg,$at
4381 For a local symbol, we want
4382 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4383 lui $at,<hiconstant>
4384 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4385 addu $tempreg,$tempreg,$at
4387 expr1
.X_add_number
= offset_expr
.X_add_number
;
4388 offset_expr
.X_add_number
= 0;
4390 if (reg_needs_delay (GP
))
4394 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4395 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4397 ((bfd_arch_bits_per_address (stdoutput
) == 32
4398 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4399 ? "addu" : "daddu"),
4400 "d,v,t", tempreg
, tempreg
, GP
);
4401 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4403 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4405 if (expr1
.X_add_number
== 0)
4413 /* We're going to put in an addu instruction using
4414 tempreg, so we may as well insert the nop right
4416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4421 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4422 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4425 ? mips_opts
.warn_about_macros
4427 offset_expr
.X_add_symbol
, (offsetT
) 0,
4430 else if (expr1
.X_add_number
>= -0x8000
4431 && expr1
.X_add_number
< 0x8000)
4433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4435 macro_build ((char *) NULL
, &icnt
, &expr1
,
4436 ((bfd_arch_bits_per_address (stdoutput
) == 32
4437 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4438 ? "addiu" : "daddiu"),
4439 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4441 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4442 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4444 ? mips_opts
.warn_about_macros
4446 offset_expr
.X_add_symbol
, (offsetT
) 0,
4453 /* If we are going to add in a base register, and the
4454 target register and the base register are the same,
4455 then we are using AT as a temporary register. Since
4456 we want to load the constant into AT, we add our
4457 current AT (from the global offset table) and the
4458 register into the register now, and pretend we were
4459 not using a base register. */
4467 assert (tempreg
== AT
);
4468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4471 ((bfd_arch_bits_per_address (stdoutput
) == 32
4472 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4473 ? "addu" : "daddu"),
4474 "d,v,t", treg
, AT
, breg
);
4479 /* Set mips_optimize around the lui instruction to avoid
4480 inserting an unnecessary nop after the lw. */
4481 hold_mips_optimize
= mips_optimize
;
4483 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4484 mips_optimize
= hold_mips_optimize
;
4486 macro_build ((char *) NULL
, &icnt
, &expr1
,
4487 ((bfd_arch_bits_per_address (stdoutput
) == 32
4488 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4489 ? "addiu" : "daddiu"),
4490 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4492 ((bfd_arch_bits_per_address (stdoutput
) == 32
4493 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4494 ? "addu" : "daddu"),
4495 "d,v,t", dreg
, dreg
, AT
);
4497 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4498 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4501 ? mips_opts
.warn_about_macros
4503 offset_expr
.X_add_symbol
, (offsetT
) 0,
4511 /* This is needed because this instruction uses $gp, but
4512 the first instruction on the main stream does not. */
4513 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4516 macro_build (p
, &icnt
, &offset_expr
,
4518 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4520 if (expr1
.X_add_number
>= -0x8000
4521 && expr1
.X_add_number
< 0x8000)
4523 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4525 macro_build (p
, &icnt
, &expr1
,
4526 ((bfd_arch_bits_per_address (stdoutput
) == 32
4527 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4528 ? "addiu" : "daddiu"),
4529 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4530 /* FIXME: If add_number is 0, and there was no base
4531 register, the external symbol case ended with a load,
4532 so if the symbol turns out to not be external, and
4533 the next instruction uses tempreg, an unnecessary nop
4534 will be inserted. */
4540 /* We must add in the base register now, as in the
4541 external symbol case. */
4542 assert (tempreg
== AT
);
4543 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4545 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4546 ((bfd_arch_bits_per_address (stdoutput
) == 32
4547 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4548 ? "addu" : "daddu"),
4549 "d,v,t", treg
, AT
, breg
);
4552 /* We set breg to 0 because we have arranged to add
4553 it in in both cases. */
4557 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4559 macro_build (p
, &icnt
, &expr1
,
4560 ((bfd_arch_bits_per_address (stdoutput
) == 32
4561 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4562 ? "addiu" : "daddiu"),
4563 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4565 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4566 ((bfd_arch_bits_per_address (stdoutput
) == 32
4567 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4568 ? "addu" : "daddu"),
4569 "d,v,t", tempreg
, tempreg
, AT
);
4573 else if (mips_pic
== EMBEDDED_PIC
)
4576 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4579 ((bfd_arch_bits_per_address (stdoutput
) == 32
4580 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4581 ? "addiu" : "daddiu"),
4582 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4589 ((bfd_arch_bits_per_address (stdoutput
) == 32
4590 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4591 ? "addu" : "daddu"),
4592 "d,v,t", treg
, tempreg
, breg
);
4600 /* The j instruction may not be used in PIC code, since it
4601 requires an absolute address. We convert it to a b
4603 if (mips_pic
== NO_PIC
)
4604 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4606 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4609 /* The jal instructions must be handled as macros because when
4610 generating PIC code they expand to multi-instruction
4611 sequences. Normally they are simple instructions. */
4616 if (mips_pic
== NO_PIC
4617 || mips_pic
== EMBEDDED_PIC
)
4618 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4620 else if (mips_pic
== SVR4_PIC
)
4622 if (sreg
!= PIC_CALL_REG
)
4623 as_warn (_("MIPS PIC call to register other than $25"));
4625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4627 if (mips_cprestore_offset
< 0)
4628 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4631 expr1
.X_add_number
= mips_cprestore_offset
;
4632 macro_build ((char *) NULL
, &icnt
, &expr1
,
4633 ((bfd_arch_bits_per_address (stdoutput
) == 32
4634 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4636 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4645 if (mips_pic
== NO_PIC
)
4646 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4647 else if (mips_pic
== SVR4_PIC
)
4649 /* If this is a reference to an external symbol, and we are
4650 using a small GOT, we want
4651 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4655 lw $gp,cprestore($sp)
4656 The cprestore value is set using the .cprestore
4657 pseudo-op. If we are using a big GOT, we want
4658 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4660 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4664 lw $gp,cprestore($sp)
4665 If the symbol is not external, we want
4666 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4668 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4671 lw $gp,cprestore($sp) */
4675 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4676 ((bfd_arch_bits_per_address (stdoutput
) == 32
4677 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4679 "t,o(b)", PIC_CALL_REG
,
4680 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4683 p
= frag_var (rs_machine_dependent
, 4, 0,
4684 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4685 offset_expr
.X_add_symbol
, (offsetT
) 0,
4692 if (reg_needs_delay (GP
))
4696 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4697 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4699 ((bfd_arch_bits_per_address (stdoutput
) == 32
4700 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4701 ? "addu" : "daddu"),
4702 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4703 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4704 ((bfd_arch_bits_per_address (stdoutput
) == 32
4705 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4707 "t,o(b)", PIC_CALL_REG
,
4708 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4711 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4712 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4714 offset_expr
.X_add_symbol
, (offsetT
) 0,
4718 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4721 macro_build (p
, &icnt
, &offset_expr
,
4722 ((bfd_arch_bits_per_address (stdoutput
) == 32
4723 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4725 "t,o(b)", PIC_CALL_REG
,
4726 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4728 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4731 macro_build (p
, &icnt
, &offset_expr
,
4732 ((bfd_arch_bits_per_address (stdoutput
) == 32
4733 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4734 ? "addiu" : "daddiu"),
4735 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4736 (int) BFD_RELOC_LO16
);
4737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4738 "jalr", "s", PIC_CALL_REG
);
4739 if (mips_cprestore_offset
< 0)
4740 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4743 if (mips_opts
.noreorder
)
4744 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4746 expr1
.X_add_number
= mips_cprestore_offset
;
4747 macro_build ((char *) NULL
, &icnt
, &expr1
,
4748 ((bfd_arch_bits_per_address (stdoutput
) == 32
4749 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4751 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4755 else if (mips_pic
== EMBEDDED_PIC
)
4757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4758 /* The linker may expand the call to a longer sequence which
4759 uses $at, so we must break rather than return. */
4784 /* Itbl support may require additional care here. */
4789 /* Itbl support may require additional care here. */
4794 /* Itbl support may require additional care here. */
4799 /* Itbl support may require additional care here. */
4811 if (mips_cpu
== CPU_R4650
)
4813 as_bad (_("opcode not supported on this processor"));
4817 /* Itbl support may require additional care here. */
4822 /* Itbl support may require additional care here. */
4827 /* Itbl support may require additional care here. */
4847 if (breg
== treg
|| coproc
|| lr
)
4869 /* Itbl support may require additional care here. */
4874 /* Itbl support may require additional care here. */
4879 /* Itbl support may require additional care here. */
4884 /* Itbl support may require additional care here. */
4900 if (mips_cpu
== CPU_R4650
)
4902 as_bad (_("opcode not supported on this processor"));
4907 /* Itbl support may require additional care here. */
4911 /* Itbl support may require additional care here. */
4916 /* Itbl support may require additional care here. */
4928 /* Itbl support may require additional care here. */
4929 if (mask
== M_LWC1_AB
4930 || mask
== M_SWC1_AB
4931 || mask
== M_LDC1_AB
4932 || mask
== M_SDC1_AB
4941 if (offset_expr
.X_op
!= O_constant
4942 && offset_expr
.X_op
!= O_symbol
)
4944 as_bad (_("expression too complex"));
4945 offset_expr
.X_op
= O_constant
;
4948 /* A constant expression in PIC code can be handled just as it
4949 is in non PIC code. */
4950 if (mips_pic
== NO_PIC
4951 || offset_expr
.X_op
== O_constant
)
4953 /* If this is a reference to a GP relative symbol, and there
4954 is no base register, we want
4955 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4956 Otherwise, if there is no base register, we want
4957 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4958 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4959 If we have a constant, we need two instructions anyhow,
4960 so we always use the latter form.
4962 If we have a base register, and this is a reference to a
4963 GP relative symbol, we want
4964 addu $tempreg,$breg,$gp
4965 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4967 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4968 addu $tempreg,$tempreg,$breg
4969 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4970 With a constant we always use the latter case. */
4973 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4974 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4979 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4980 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4981 p
= frag_var (rs_machine_dependent
, 8, 0,
4982 RELAX_ENCODE (4, 8, 0, 4, 0,
4983 (mips_opts
.warn_about_macros
4985 && mips_opts
.noat
))),
4986 offset_expr
.X_add_symbol
, (offsetT
) 0,
4990 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4993 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4994 (int) BFD_RELOC_LO16
, tempreg
);
4998 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4999 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5005 ((bfd_arch_bits_per_address (stdoutput
) == 32
5006 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5007 ? "addu" : "daddu"),
5008 "d,v,t", tempreg
, breg
, GP
);
5009 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5010 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5011 p
= frag_var (rs_machine_dependent
, 12, 0,
5012 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5013 offset_expr
.X_add_symbol
, (offsetT
) 0,
5016 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5019 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5020 ((bfd_arch_bits_per_address (stdoutput
) == 32
5021 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5022 ? "addu" : "daddu"),
5023 "d,v,t", tempreg
, tempreg
, breg
);
5026 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5027 (int) BFD_RELOC_LO16
, tempreg
);
5030 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5032 /* If this is a reference to an external symbol, we want
5033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5035 <op> $treg,0($tempreg)
5037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5039 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5040 <op> $treg,0($tempreg)
5041 If there is a base register, we add it to $tempreg before
5042 the <op>. If there is a constant, we stick it in the
5043 <op> instruction. We don't handle constants larger than
5044 16 bits, because we have no way to load the upper 16 bits
5045 (actually, we could handle them for the subset of cases
5046 in which we are not using $at). */
5047 assert (offset_expr
.X_op
== O_symbol
);
5048 expr1
.X_add_number
= offset_expr
.X_add_number
;
5049 offset_expr
.X_add_number
= 0;
5050 if (expr1
.X_add_number
< -0x8000
5051 || expr1
.X_add_number
>= 0x8000)
5052 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5054 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5055 ((bfd_arch_bits_per_address (stdoutput
) == 32
5056 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5058 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5060 p
= frag_var (rs_machine_dependent
, 4, 0,
5061 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5062 offset_expr
.X_add_symbol
, (offsetT
) 0,
5064 macro_build (p
, &icnt
, &offset_expr
,
5065 ((bfd_arch_bits_per_address (stdoutput
) == 32
5066 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5067 ? "addiu" : "daddiu"),
5068 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5071 ((bfd_arch_bits_per_address (stdoutput
) == 32
5072 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5073 ? "addu" : "daddu"),
5074 "d,v,t", tempreg
, tempreg
, breg
);
5075 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5076 (int) BFD_RELOC_LO16
, tempreg
);
5078 else if (mips_pic
== SVR4_PIC
)
5082 /* If this is a reference to an external symbol, we want
5083 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5084 addu $tempreg,$tempreg,$gp
5085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5086 <op> $treg,0($tempreg)
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5090 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5091 <op> $treg,0($tempreg)
5092 If there is a base register, we add it to $tempreg before
5093 the <op>. If there is a constant, we stick it in the
5094 <op> instruction. We don't handle constants larger than
5095 16 bits, because we have no way to load the upper 16 bits
5096 (actually, we could handle them for the subset of cases
5097 in which we are not using $at). */
5098 assert (offset_expr
.X_op
== O_symbol
);
5099 expr1
.X_add_number
= offset_expr
.X_add_number
;
5100 offset_expr
.X_add_number
= 0;
5101 if (expr1
.X_add_number
< -0x8000
5102 || expr1
.X_add_number
>= 0x8000)
5103 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5104 if (reg_needs_delay (GP
))
5109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5110 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5112 ((bfd_arch_bits_per_address (stdoutput
) == 32
5113 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5114 ? "addu" : "daddu"),
5115 "d,v,t", tempreg
, tempreg
, GP
);
5116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5117 ((bfd_arch_bits_per_address (stdoutput
) == 32
5118 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5120 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5122 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5123 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5124 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5127 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5130 macro_build (p
, &icnt
, &offset_expr
,
5131 ((bfd_arch_bits_per_address (stdoutput
) == 32
5132 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5134 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5136 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5138 macro_build (p
, &icnt
, &offset_expr
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5141 ? "addiu" : "daddiu"),
5142 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5145 ((bfd_arch_bits_per_address (stdoutput
) == 32
5146 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5147 ? "addu" : "daddu"),
5148 "d,v,t", tempreg
, tempreg
, breg
);
5149 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5150 (int) BFD_RELOC_LO16
, tempreg
);
5152 else if (mips_pic
== EMBEDDED_PIC
)
5154 /* If there is no base register, we want
5155 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5156 If there is a base register, we want
5157 addu $tempreg,$breg,$gp
5158 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5160 assert (offset_expr
.X_op
== O_symbol
);
5163 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5164 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5170 ((bfd_arch_bits_per_address (stdoutput
) == 32
5171 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5172 ? "addu" : "daddu"),
5173 "d,v,t", tempreg
, breg
, GP
);
5174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5175 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5188 load_register (&icnt
, treg
, &imm_expr
, 0);
5192 load_register (&icnt
, treg
, &imm_expr
, 1);
5196 if (imm_expr
.X_op
== O_constant
)
5198 load_register (&icnt
, AT
, &imm_expr
, 0);
5199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5200 "mtc1", "t,G", AT
, treg
);
5205 assert (offset_expr
.X_op
== O_symbol
5206 && strcmp (segment_name (S_GET_SEGMENT
5207 (offset_expr
.X_add_symbol
)),
5209 && offset_expr
.X_add_number
== 0);
5210 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5211 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5216 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5217 the entire value, and in mips1 mode it is the high order 32
5218 bits of the value and the low order 32 bits are either zero
5219 or in offset_expr. */
5220 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5222 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5223 load_register (&icnt
, treg
, &imm_expr
, 1);
5228 if (target_big_endian
)
5240 load_register (&icnt
, hreg
, &imm_expr
, 0);
5243 if (offset_expr
.X_op
== O_absent
)
5244 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5248 assert (offset_expr
.X_op
== O_constant
);
5249 load_register (&icnt
, lreg
, &offset_expr
, 0);
5256 /* We know that sym is in the .rdata section. First we get the
5257 upper 16 bits of the address. */
5258 if (mips_pic
== NO_PIC
)
5260 /* FIXME: This won't work for a 64 bit address. */
5261 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5263 else if (mips_pic
== SVR4_PIC
)
5265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5266 ((bfd_arch_bits_per_address (stdoutput
) == 32
5267 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5269 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5271 else if (mips_pic
== EMBEDDED_PIC
)
5273 /* For embedded PIC we pick up the entire address off $gp in
5274 a single instruction. */
5275 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5276 ((bfd_arch_bits_per_address (stdoutput
) == 32
5277 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5278 ? "addiu" : "daddiu"),
5279 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5280 offset_expr
.X_op
= O_constant
;
5281 offset_expr
.X_add_number
= 0;
5286 /* Now we load the register(s). */
5287 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5289 treg
, (int) BFD_RELOC_LO16
, AT
);
5292 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5293 treg
, (int) BFD_RELOC_LO16
, AT
);
5296 /* FIXME: How in the world do we deal with the possible
5298 offset_expr
.X_add_number
+= 4;
5299 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5300 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5304 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5305 does not become a variant frag. */
5306 frag_wane (frag_now
);
5312 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5313 the entire value, and in mips1 mode it is the high order 32
5314 bits of the value and the low order 32 bits are either zero
5315 or in offset_expr. */
5316 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5318 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5319 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5321 "dmtc1", "t,S", AT
, treg
);
5324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5325 "mtc1", "t,G", AT
, treg
+ 1);
5326 if (offset_expr
.X_op
== O_absent
)
5327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5328 "mtc1", "t,G", 0, treg
);
5331 assert (offset_expr
.X_op
== O_constant
);
5332 load_register (&icnt
, AT
, &offset_expr
, 0);
5333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5334 "mtc1", "t,G", AT
, treg
);
5340 assert (offset_expr
.X_op
== O_symbol
5341 && offset_expr
.X_add_number
== 0);
5342 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5343 if (strcmp (s
, ".lit8") == 0)
5345 if (mips_opts
.isa
!= ISA_MIPS1
)
5347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5348 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5352 r
= BFD_RELOC_MIPS_LITERAL
;
5357 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5358 if (mips_pic
== SVR4_PIC
)
5359 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5360 ((bfd_arch_bits_per_address (stdoutput
) == 32
5361 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5363 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5366 /* FIXME: This won't work for a 64 bit address. */
5367 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5370 if (mips_opts
.isa
!= ISA_MIPS1
)
5372 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5373 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5375 /* To avoid confusion in tc_gen_reloc, we must ensure
5376 that this does not become a variant frag. */
5377 frag_wane (frag_now
);
5388 if (mips_cpu
== CPU_R4650
)
5390 as_bad (_("opcode not supported on this processor"));
5393 /* Even on a big endian machine $fn comes before $fn+1. We have
5394 to adjust when loading from memory. */
5397 assert (mips_opts
.isa
== ISA_MIPS1
);
5398 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5399 target_big_endian
? treg
+ 1 : treg
,
5401 /* FIXME: A possible overflow which I don't know how to deal
5403 offset_expr
.X_add_number
+= 4;
5404 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5405 target_big_endian
? treg
: treg
+ 1,
5408 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5409 does not become a variant frag. */
5410 frag_wane (frag_now
);
5419 * The MIPS assembler seems to check for X_add_number not
5420 * being double aligned and generating:
5423 * addiu at,at,%lo(foo+1)
5426 * But, the resulting address is the same after relocation so why
5427 * generate the extra instruction?
5429 if (mips_cpu
== CPU_R4650
)
5431 as_bad (_("opcode not supported on this processor"));
5434 /* Itbl support may require additional care here. */
5436 if (mips_opts
.isa
!= ISA_MIPS1
)
5447 if (mips_cpu
== CPU_R4650
)
5449 as_bad (_("opcode not supported on this processor"));
5453 if (mips_opts
.isa
!= ISA_MIPS1
)
5461 /* Itbl support may require additional care here. */
5466 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5477 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5487 if (offset_expr
.X_op
!= O_symbol
5488 && offset_expr
.X_op
!= O_constant
)
5490 as_bad (_("expression too complex"));
5491 offset_expr
.X_op
= O_constant
;
5494 /* Even on a big endian machine $fn comes before $fn+1. We have
5495 to adjust when loading from memory. We set coproc if we must
5496 load $fn+1 first. */
5497 /* Itbl support may require additional care here. */
5498 if (! target_big_endian
)
5501 if (mips_pic
== NO_PIC
5502 || offset_expr
.X_op
== O_constant
)
5504 /* If this is a reference to a GP relative symbol, we want
5505 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5506 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5507 If we have a base register, we use this
5509 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5510 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5511 If this is not a GP relative symbol, we want
5512 lui $at,<sym> (BFD_RELOC_HI16_S)
5513 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5514 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5515 If there is a base register, we add it to $at after the
5516 lui instruction. If there is a constant, we always use
5518 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5519 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5539 ((bfd_arch_bits_per_address (stdoutput
) == 32
5540 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5541 ? "addu" : "daddu"),
5542 "d,v,t", AT
, breg
, GP
);
5548 /* Itbl support may require additional care here. */
5549 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5550 coproc
? treg
+ 1 : treg
,
5551 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5552 offset_expr
.X_add_number
+= 4;
5554 /* Set mips_optimize to 2 to avoid inserting an
5556 hold_mips_optimize
= mips_optimize
;
5558 /* Itbl support may require additional care here. */
5559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5560 coproc
? treg
: treg
+ 1,
5561 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5562 mips_optimize
= hold_mips_optimize
;
5564 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5565 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5566 used_at
&& mips_opts
.noat
),
5567 offset_expr
.X_add_symbol
, (offsetT
) 0,
5570 /* We just generated two relocs. When tc_gen_reloc
5571 handles this case, it will skip the first reloc and
5572 handle the second. The second reloc already has an
5573 extra addend of 4, which we added above. We must
5574 subtract it out, and then subtract another 4 to make
5575 the first reloc come out right. The second reloc
5576 will come out right because we are going to add 4 to
5577 offset_expr when we build its instruction below.
5579 If we have a symbol, then we don't want to include
5580 the offset, because it will wind up being included
5581 when we generate the reloc. */
5583 if (offset_expr
.X_op
== O_constant
)
5584 offset_expr
.X_add_number
-= 8;
5587 offset_expr
.X_add_number
= -4;
5588 offset_expr
.X_op
= O_constant
;
5591 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5596 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5597 ((bfd_arch_bits_per_address (stdoutput
) == 32
5598 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5599 ? "addu" : "daddu"),
5600 "d,v,t", AT
, breg
, AT
);
5604 /* Itbl support may require additional care here. */
5605 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5606 coproc
? treg
+ 1 : treg
,
5607 (int) BFD_RELOC_LO16
, AT
);
5610 /* FIXME: How do we handle overflow here? */
5611 offset_expr
.X_add_number
+= 4;
5612 /* Itbl support may require additional care here. */
5613 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5614 coproc
? treg
: treg
+ 1,
5615 (int) BFD_RELOC_LO16
, AT
);
5617 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5621 /* If this is a reference to an external symbol, we want
5622 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5627 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5629 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5630 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5631 If there is a base register we add it to $at before the
5632 lwc1 instructions. If there is a constant we include it
5633 in the lwc1 instructions. */
5635 expr1
.X_add_number
= offset_expr
.X_add_number
;
5636 offset_expr
.X_add_number
= 0;
5637 if (expr1
.X_add_number
< -0x8000
5638 || expr1
.X_add_number
>= 0x8000 - 4)
5639 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5644 frag_grow (24 + off
);
5645 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5646 ((bfd_arch_bits_per_address (stdoutput
) == 32
5647 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5649 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5653 ((bfd_arch_bits_per_address (stdoutput
) == 32
5654 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5655 ? "addu" : "daddu"),
5656 "d,v,t", AT
, breg
, AT
);
5657 /* Itbl support may require additional care here. */
5658 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5659 coproc
? treg
+ 1 : treg
,
5660 (int) BFD_RELOC_LO16
, AT
);
5661 expr1
.X_add_number
+= 4;
5663 /* Set mips_optimize to 2 to avoid inserting an undesired
5665 hold_mips_optimize
= mips_optimize
;
5667 /* Itbl support may require additional care here. */
5668 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5669 coproc
? treg
: treg
+ 1,
5670 (int) BFD_RELOC_LO16
, AT
);
5671 mips_optimize
= hold_mips_optimize
;
5673 (void) frag_var (rs_machine_dependent
, 0, 0,
5674 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5675 offset_expr
.X_add_symbol
, (offsetT
) 0,
5678 else if (mips_pic
== SVR4_PIC
)
5682 /* If this is a reference to an external symbol, we want
5683 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5685 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5690 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5692 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5693 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5694 If there is a base register we add it to $at before the
5695 lwc1 instructions. If there is a constant we include it
5696 in the lwc1 instructions. */
5698 expr1
.X_add_number
= offset_expr
.X_add_number
;
5699 offset_expr
.X_add_number
= 0;
5700 if (expr1
.X_add_number
< -0x8000
5701 || expr1
.X_add_number
>= 0x8000 - 4)
5702 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5703 if (reg_needs_delay (GP
))
5712 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5713 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5715 ((bfd_arch_bits_per_address (stdoutput
) == 32
5716 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5717 ? "addu" : "daddu"),
5718 "d,v,t", AT
, AT
, GP
);
5719 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5720 ((bfd_arch_bits_per_address (stdoutput
) == 32
5721 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5723 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5727 ((bfd_arch_bits_per_address (stdoutput
) == 32
5728 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5729 ? "addu" : "daddu"),
5730 "d,v,t", AT
, breg
, AT
);
5731 /* Itbl support may require additional care here. */
5732 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5733 coproc
? treg
+ 1 : treg
,
5734 (int) BFD_RELOC_LO16
, AT
);
5735 expr1
.X_add_number
+= 4;
5737 /* Set mips_optimize to 2 to avoid inserting an undesired
5739 hold_mips_optimize
= mips_optimize
;
5741 /* Itbl support may require additional care here. */
5742 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5743 coproc
? treg
: treg
+ 1,
5744 (int) BFD_RELOC_LO16
, AT
);
5745 mips_optimize
= hold_mips_optimize
;
5746 expr1
.X_add_number
-= 4;
5748 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5749 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5750 8 + gpdel
+ off
, 1, 0),
5751 offset_expr
.X_add_symbol
, (offsetT
) 0,
5755 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5758 macro_build (p
, &icnt
, &offset_expr
,
5759 ((bfd_arch_bits_per_address (stdoutput
) == 32
5760 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5762 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5764 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5768 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5769 ((bfd_arch_bits_per_address (stdoutput
) == 32
5770 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5771 ? "addu" : "daddu"),
5772 "d,v,t", AT
, breg
, AT
);
5775 /* Itbl support may require additional care here. */
5776 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5777 coproc
? treg
+ 1 : treg
,
5778 (int) BFD_RELOC_LO16
, AT
);
5780 expr1
.X_add_number
+= 4;
5782 /* Set mips_optimize to 2 to avoid inserting an undesired
5784 hold_mips_optimize
= mips_optimize
;
5786 /* Itbl support may require additional care here. */
5787 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5788 coproc
? treg
: treg
+ 1,
5789 (int) BFD_RELOC_LO16
, AT
);
5790 mips_optimize
= hold_mips_optimize
;
5792 else if (mips_pic
== EMBEDDED_PIC
)
5794 /* If there is no base register, we use
5795 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5796 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5797 If we have a base register, we use
5799 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5800 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5810 ((bfd_arch_bits_per_address (stdoutput
) == 32
5811 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5812 ? "addu" : "daddu"),
5813 "d,v,t", AT
, breg
, GP
);
5818 /* Itbl support may require additional care here. */
5819 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5820 coproc
? treg
+ 1 : treg
,
5821 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5822 offset_expr
.X_add_number
+= 4;
5823 /* Itbl support may require additional care here. */
5824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5825 coproc
? treg
: treg
+ 1,
5826 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5842 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5843 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5844 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5845 (int) BFD_RELOC_LO16
, breg
);
5846 offset_expr
.X_add_number
+= 4;
5847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5848 (int) BFD_RELOC_LO16
, breg
);
5851 /* New code added to support COPZ instructions.
5852 This code builds table entries out of the macros in mip_opcodes.
5853 R4000 uses interlocks to handle coproc delays.
5854 Other chips (like the R3000) require nops to be inserted for delays.
5856 FIXME: Currently, we require that the user handle delays.
5857 In order to fill delay slots for non-interlocked chips,
5858 we must have a way to specify delays based on the coprocessor.
5859 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5860 What are the side-effects of the cop instruction?
5861 What cache support might we have and what are its effects?
5862 Both coprocessor & memory require delays. how long???
5863 What registers are read/set/modified?
5865 If an itbl is provided to interpret cop instructions,
5866 this knowledge can be encoded in the itbl spec. */
5880 /* For now we just do C (same as Cz). The parameter will be
5881 stored in insn_opcode by mips_ip. */
5882 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5886 #ifdef LOSING_COMPILER
5888 /* Try and see if this is a new itbl instruction.
5889 This code builds table entries out of the macros in mip_opcodes.
5890 FIXME: For now we just assemble the expression and pass it's
5891 value along as a 32-bit immediate.
5892 We may want to have the assembler assemble this value,
5893 so that we gain the assembler's knowledge of delay slots,
5895 Would it be more efficient to use mask (id) here? */
5896 if (itbl_have_entries
5897 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5899 s
= ip
->insn_mo
->name
;
5901 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5902 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5909 as_warn (_("Macro used $at after \".set noat\""));
5914 struct mips_cl_insn
*ip
;
5916 register int treg
, sreg
, dreg
, breg
;
5932 bfd_reloc_code_real_type r
;
5935 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5936 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5937 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5938 mask
= ip
->insn_mo
->mask
;
5940 expr1
.X_op
= O_constant
;
5941 expr1
.X_op_symbol
= NULL
;
5942 expr1
.X_add_symbol
= NULL
;
5943 expr1
.X_add_number
= 1;
5947 #endif /* LOSING_COMPILER */
5952 macro_build ((char *) NULL
, &icnt
, NULL
,
5953 dbl
? "dmultu" : "multu",
5955 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5961 /* The MIPS assembler some times generates shifts and adds. I'm
5962 not trying to be that fancy. GCC should do this for us
5964 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5965 macro_build ((char *) NULL
, &icnt
, NULL
,
5966 dbl
? "dmult" : "mult",
5968 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5981 mips_emit_delays (true);
5982 ++mips_opts
.noreorder
;
5983 mips_any_noreorder
= 1;
5985 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5986 macro_build ((char *) NULL
, &icnt
, NULL
,
5987 dbl
? "dmult" : "mult",
5988 "s,t", sreg
, imm
? AT
: treg
);
5989 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5990 macro_build ((char *) NULL
, &icnt
, NULL
,
5991 dbl
? "dsra32" : "sra",
5992 "d,w,<", dreg
, dreg
, 31);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5998 expr1
.X_add_number
= 8;
5999 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6000 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6003 --mips_opts
.noreorder
;
6004 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6017 mips_emit_delays (true);
6018 ++mips_opts
.noreorder
;
6019 mips_any_noreorder
= 1;
6021 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6022 macro_build ((char *) NULL
, &icnt
, NULL
,
6023 dbl
? "dmultu" : "multu",
6024 "s,t", sreg
, imm
? AT
: treg
);
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6031 expr1
.X_add_number
= 8;
6032 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6034 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6036 --mips_opts
.noreorder
;
6040 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6041 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6042 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6044 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6048 if (imm_expr
.X_op
!= O_constant
)
6049 as_bad (_("rotate count too large"));
6050 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6051 (int) (imm_expr
.X_add_number
& 0x1f));
6052 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6053 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6058 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6060 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6066 if (imm_expr
.X_op
!= O_constant
)
6067 as_bad (_("rotate count too large"));
6068 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6069 (int) (imm_expr
.X_add_number
& 0x1f));
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6071 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6072 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6076 if (mips_cpu
== CPU_R4650
)
6078 as_bad (_("opcode not supported on this processor"));
6081 assert (mips_opts
.isa
== ISA_MIPS1
);
6082 /* Even on a big endian machine $fn comes before $fn+1. We have
6083 to adjust when storing to memory. */
6084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6085 target_big_endian
? treg
+ 1 : treg
,
6086 (int) BFD_RELOC_LO16
, breg
);
6087 offset_expr
.X_add_number
+= 4;
6088 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6089 target_big_endian
? treg
: treg
+ 1,
6090 (int) BFD_RELOC_LO16
, breg
);
6095 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6096 treg
, (int) BFD_RELOC_LO16
);
6098 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6099 sreg
, (int) BFD_RELOC_LO16
);
6102 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6104 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6105 dreg
, (int) BFD_RELOC_LO16
);
6110 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6112 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6113 sreg
, (int) BFD_RELOC_LO16
);
6118 as_warn (_("Instruction %s: result is always false"),
6120 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6123 if (imm_expr
.X_op
== O_constant
6124 && imm_expr
.X_add_number
>= 0
6125 && imm_expr
.X_add_number
< 0x10000)
6127 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6128 sreg
, (int) BFD_RELOC_LO16
);
6131 else if (imm_expr
.X_op
== O_constant
6132 && imm_expr
.X_add_number
> -0x8000
6133 && imm_expr
.X_add_number
< 0)
6135 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6136 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6137 ((bfd_arch_bits_per_address (stdoutput
) == 32
6138 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6139 ? "addiu" : "daddiu"),
6140 "t,r,j", dreg
, sreg
,
6141 (int) BFD_RELOC_LO16
);
6146 load_register (&icnt
, AT
, &imm_expr
, 0);
6147 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6151 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6152 (int) BFD_RELOC_LO16
);
6157 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6163 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6164 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6165 (int) BFD_RELOC_LO16
);
6168 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6170 if (imm_expr
.X_op
== O_constant
6171 && imm_expr
.X_add_number
>= -0x8000
6172 && imm_expr
.X_add_number
< 0x8000)
6174 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6175 mask
== M_SGE_I
? "slti" : "sltiu",
6176 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6181 load_register (&icnt
, AT
, &imm_expr
, 0);
6182 macro_build ((char *) NULL
, &icnt
, NULL
,
6183 mask
== M_SGE_I
? "slt" : "sltu",
6184 "d,v,t", dreg
, sreg
, AT
);
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6188 (int) BFD_RELOC_LO16
);
6193 case M_SGT
: /* sreg > treg <==> treg < sreg */
6199 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6202 case M_SGT_I
: /* sreg > I <==> I < sreg */
6208 load_register (&icnt
, AT
, &imm_expr
, 0);
6209 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6212 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6218 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6219 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6220 (int) BFD_RELOC_LO16
);
6223 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6229 load_register (&icnt
, AT
, &imm_expr
, 0);
6230 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6231 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6232 (int) BFD_RELOC_LO16
);
6236 if (imm_expr
.X_op
== O_constant
6237 && imm_expr
.X_add_number
>= -0x8000
6238 && imm_expr
.X_add_number
< 0x8000)
6240 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6241 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6244 load_register (&icnt
, AT
, &imm_expr
, 0);
6245 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6249 if (imm_expr
.X_op
== O_constant
6250 && imm_expr
.X_add_number
>= -0x8000
6251 && imm_expr
.X_add_number
< 0x8000)
6253 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6254 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6257 load_register (&icnt
, AT
, &imm_expr
, 0);
6258 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6264 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6267 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6271 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6273 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6279 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6281 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6287 as_warn (_("Instruction %s: result is always true"),
6289 macro_build ((char *) NULL
, &icnt
, &expr1
,
6290 ((bfd_arch_bits_per_address (stdoutput
) == 32
6291 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6292 ? "addiu" : "daddiu"),
6293 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6296 if (imm_expr
.X_op
== O_constant
6297 && imm_expr
.X_add_number
>= 0
6298 && imm_expr
.X_add_number
< 0x10000)
6300 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6301 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6304 else if (imm_expr
.X_op
== O_constant
6305 && imm_expr
.X_add_number
> -0x8000
6306 && imm_expr
.X_add_number
< 0)
6308 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6309 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6310 ((bfd_arch_bits_per_address (stdoutput
) == 32
6311 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6312 ? "addiu" : "daddiu"),
6313 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6318 load_register (&icnt
, AT
, &imm_expr
, 0);
6319 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6323 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6331 if (imm_expr
.X_op
== O_constant
6332 && imm_expr
.X_add_number
> -0x8000
6333 && imm_expr
.X_add_number
<= 0x8000)
6335 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6336 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6337 dbl
? "daddi" : "addi",
6338 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6341 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6342 macro_build ((char *) NULL
, &icnt
, NULL
,
6343 dbl
? "dsub" : "sub",
6344 "d,v,t", dreg
, sreg
, AT
);
6350 if (imm_expr
.X_op
== O_constant
6351 && imm_expr
.X_add_number
> -0x8000
6352 && imm_expr
.X_add_number
<= 0x8000)
6354 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6355 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6356 dbl
? "daddiu" : "addiu",
6357 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6360 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6361 macro_build ((char *) NULL
, &icnt
, NULL
,
6362 dbl
? "dsubu" : "subu",
6363 "d,v,t", dreg
, sreg
, AT
);
6384 load_register (&icnt
, AT
, &imm_expr
, 0);
6385 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6390 assert (mips_opts
.isa
== ISA_MIPS1
);
6391 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6392 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6395 * Is the double cfc1 instruction a bug in the mips assembler;
6396 * or is there a reason for it?
6398 mips_emit_delays (true);
6399 ++mips_opts
.noreorder
;
6400 mips_any_noreorder
= 1;
6401 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6402 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6403 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6404 expr1
.X_add_number
= 3;
6405 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6406 (int) BFD_RELOC_LO16
);
6407 expr1
.X_add_number
= 2;
6408 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6409 (int) BFD_RELOC_LO16
);
6410 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6411 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6412 macro_build ((char *) NULL
, &icnt
, NULL
,
6413 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6414 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6415 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6416 --mips_opts
.noreorder
;
6425 if (offset_expr
.X_add_number
>= 0x7fff)
6426 as_bad (_("operand overflow"));
6427 /* avoid load delay */
6428 if (! target_big_endian
)
6429 offset_expr
.X_add_number
+= 1;
6430 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6431 (int) BFD_RELOC_LO16
, breg
);
6432 if (! target_big_endian
)
6433 offset_expr
.X_add_number
-= 1;
6435 offset_expr
.X_add_number
+= 1;
6436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6437 (int) BFD_RELOC_LO16
, breg
);
6438 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6439 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6452 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6453 as_bad (_("operand overflow"));
6454 if (! target_big_endian
)
6455 offset_expr
.X_add_number
+= off
;
6456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6457 (int) BFD_RELOC_LO16
, breg
);
6458 if (! target_big_endian
)
6459 offset_expr
.X_add_number
-= off
;
6461 offset_expr
.X_add_number
+= off
;
6462 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6463 (int) BFD_RELOC_LO16
, breg
);
6476 load_address (&icnt
, AT
, &offset_expr
);
6478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6479 ((bfd_arch_bits_per_address (stdoutput
) == 32
6480 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6481 ? "addu" : "daddu"),
6482 "d,v,t", AT
, AT
, breg
);
6483 if (! target_big_endian
)
6484 expr1
.X_add_number
= off
;
6486 expr1
.X_add_number
= 0;
6487 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6488 (int) BFD_RELOC_LO16
, AT
);
6489 if (! target_big_endian
)
6490 expr1
.X_add_number
= 0;
6492 expr1
.X_add_number
= off
;
6493 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6494 (int) BFD_RELOC_LO16
, AT
);
6499 load_address (&icnt
, AT
, &offset_expr
);
6501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6502 ((bfd_arch_bits_per_address (stdoutput
) == 32
6503 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6504 ? "addu" : "daddu"),
6505 "d,v,t", AT
, AT
, breg
);
6506 if (target_big_endian
)
6507 expr1
.X_add_number
= 0;
6508 macro_build ((char *) NULL
, &icnt
, &expr1
,
6509 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6510 (int) BFD_RELOC_LO16
, AT
);
6511 if (target_big_endian
)
6512 expr1
.X_add_number
= 1;
6514 expr1
.X_add_number
= 0;
6515 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6516 (int) BFD_RELOC_LO16
, AT
);
6517 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6519 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6524 if (offset_expr
.X_add_number
>= 0x7fff)
6525 as_bad (_("operand overflow"));
6526 if (target_big_endian
)
6527 offset_expr
.X_add_number
+= 1;
6528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6529 (int) BFD_RELOC_LO16
, breg
);
6530 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6531 if (target_big_endian
)
6532 offset_expr
.X_add_number
-= 1;
6534 offset_expr
.X_add_number
+= 1;
6535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6536 (int) BFD_RELOC_LO16
, breg
);
6549 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6550 as_bad (_("operand overflow"));
6551 if (! target_big_endian
)
6552 offset_expr
.X_add_number
+= off
;
6553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, breg
);
6555 if (! target_big_endian
)
6556 offset_expr
.X_add_number
-= off
;
6558 offset_expr
.X_add_number
+= off
;
6559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6560 (int) BFD_RELOC_LO16
, breg
);
6573 load_address (&icnt
, AT
, &offset_expr
);
6575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6576 ((bfd_arch_bits_per_address (stdoutput
) == 32
6577 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6578 ? "addu" : "daddu"),
6579 "d,v,t", AT
, AT
, breg
);
6580 if (! target_big_endian
)
6581 expr1
.X_add_number
= off
;
6583 expr1
.X_add_number
= 0;
6584 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6585 (int) BFD_RELOC_LO16
, AT
);
6586 if (! target_big_endian
)
6587 expr1
.X_add_number
= 0;
6589 expr1
.X_add_number
= off
;
6590 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6591 (int) BFD_RELOC_LO16
, AT
);
6595 load_address (&icnt
, AT
, &offset_expr
);
6597 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6598 ((bfd_arch_bits_per_address (stdoutput
) == 32
6599 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6600 ? "addu" : "daddu"),
6601 "d,v,t", AT
, AT
, breg
);
6602 if (! target_big_endian
)
6603 expr1
.X_add_number
= 0;
6604 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6605 (int) BFD_RELOC_LO16
, AT
);
6606 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6608 if (! target_big_endian
)
6609 expr1
.X_add_number
= 1;
6611 expr1
.X_add_number
= 0;
6612 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6613 (int) BFD_RELOC_LO16
, AT
);
6614 if (! target_big_endian
)
6615 expr1
.X_add_number
= 0;
6617 expr1
.X_add_number
= 1;
6618 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6619 (int) BFD_RELOC_LO16
, AT
);
6620 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6622 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6627 /* FIXME: Check if this is one of the itbl macros, since they
6628 are added dynamically. */
6629 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6633 as_warn (_("Macro used $at after \".set noat\""));
6636 /* Implement macros in mips16 mode. */
6640 struct mips_cl_insn
*ip
;
6643 int xreg
, yreg
, zreg
, tmp
;
6647 const char *s
, *s2
, *s3
;
6649 mask
= ip
->insn_mo
->mask
;
6651 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6652 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6653 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6657 expr1
.X_op
= O_constant
;
6658 expr1
.X_op_symbol
= NULL
;
6659 expr1
.X_add_symbol
= NULL
;
6660 expr1
.X_add_number
= 1;
6679 mips_emit_delays (true);
6680 ++mips_opts
.noreorder
;
6681 mips_any_noreorder
= 1;
6682 macro_build ((char *) NULL
, &icnt
, NULL
,
6683 dbl
? "ddiv" : "div",
6684 "0,x,y", xreg
, yreg
);
6685 expr1
.X_add_number
= 2;
6686 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6687 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6689 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6690 since that causes an overflow. We should do that as well,
6691 but I don't see how to do the comparisons without a temporary
6693 --mips_opts
.noreorder
;
6694 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6713 mips_emit_delays (true);
6714 ++mips_opts
.noreorder
;
6715 mips_any_noreorder
= 1;
6716 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6717 expr1
.X_add_number
= 2;
6718 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6719 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6720 --mips_opts
.noreorder
;
6721 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6727 macro_build ((char *) NULL
, &icnt
, NULL
,
6728 dbl
? "dmultu" : "multu",
6730 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6738 if (imm_expr
.X_op
!= O_constant
)
6739 as_bad (_("Unsupported large constant"));
6740 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6741 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6742 dbl
? "daddiu" : "addiu",
6743 "y,x,4", yreg
, xreg
);
6747 if (imm_expr
.X_op
!= O_constant
)
6748 as_bad (_("Unsupported large constant"));
6749 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6750 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6755 if (imm_expr
.X_op
!= O_constant
)
6756 as_bad (_("Unsupported large constant"));
6757 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6758 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6781 goto do_reverse_branch
;
6785 goto do_reverse_branch
;
6797 goto do_reverse_branch
;
6808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6810 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6837 goto do_addone_branch_i
;
6842 goto do_addone_branch_i
;
6857 goto do_addone_branch_i
;
6864 if (imm_expr
.X_op
!= O_constant
)
6865 as_bad (_("Unsupported large constant"));
6866 ++imm_expr
.X_add_number
;
6869 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6874 expr1
.X_add_number
= 0;
6875 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6878 "move", "y,X", xreg
, yreg
);
6879 expr1
.X_add_number
= 2;
6880 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6881 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6882 "neg", "x,w", xreg
, xreg
);
6886 /* For consistency checking, verify that all bits are specified either
6887 by the match/mask part of the instruction definition, or by the
6890 validate_mips_insn (opc
)
6891 const struct mips_opcode
*opc
;
6893 const char *p
= opc
->args
;
6895 unsigned long used_bits
= opc
->mask
;
6897 if ((used_bits
& opc
->match
) != opc
->match
)
6899 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6900 opc
->name
, opc
->args
);
6903 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6910 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6911 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6913 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6914 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6915 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6916 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6918 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6919 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6921 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6923 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6924 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6925 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6926 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6927 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6928 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6929 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6930 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6931 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6932 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6933 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6935 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6936 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6937 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6938 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6940 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6941 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6942 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6943 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6944 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6945 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6946 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6947 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6948 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6951 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6952 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6953 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6955 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6956 c
, opc
->name
, opc
->args
);
6960 if (used_bits
!= 0xffffffff)
6962 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6963 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6969 /* This routine assembles an instruction into its binary format. As a
6970 side effect, it sets one of the global variables imm_reloc or
6971 offset_reloc to the type of relocation to do if one of the operands
6972 is an address expression. */
6977 struct mips_cl_insn
*ip
;
6982 struct mips_opcode
*insn
;
6985 unsigned int lastregno
= 0;
6988 int full_opcode_match
= 1;
6992 /* If the instruction contains a '.', we first try to match an instruction
6993 including the '.'. Then we try again without the '.'. */
6995 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6998 /* If we stopped on whitespace, then replace the whitespace with null for
6999 the call to hash_find. Save the character we replaced just in case we
7000 have to re-parse the instruction. */
7001 if (isspace ((unsigned char) *s
))
7007 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7009 /* If we didn't find the instruction in the opcode table, try again, but
7010 this time with just the instruction up to, but not including the
7014 /* Restore the character we overwrite above (if any). */
7018 /* Scan up to the first '.' or whitespace. */
7019 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7022 /* If we did not find a '.', then we can quit now. */
7025 insn_error
= "unrecognized opcode";
7029 /* Lookup the instruction in the hash table. */
7031 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7033 insn_error
= "unrecognized opcode";
7037 full_opcode_match
= 0;
7045 assert (strcmp (insn
->name
, str
) == 0);
7047 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7052 if (insn
->pinfo
!= INSN_MACRO
)
7054 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7060 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7061 && strcmp (insn
->name
, insn
[1].name
) == 0)
7068 static char buf
[100];
7070 _("opcode not supported on this processor: %s (%s)"),
7071 mips_cpu_to_str (mips_cpu
),
7072 mips_isa_to_str (mips_opts
.isa
));
7080 ip
->insn_opcode
= insn
->match
;
7081 for (args
= insn
->args
;; ++args
)
7087 case '\0': /* end of args */
7100 ip
->insn_opcode
|= lastregno
<< 21;
7105 ip
->insn_opcode
|= lastregno
<< 16;
7109 ip
->insn_opcode
|= lastregno
<< 11;
7115 /* Handle optional base register.
7116 Either the base register is omitted or
7117 we must have a left paren. */
7118 /* This is dependent on the next operand specifier
7119 is a base register specification. */
7120 assert (args
[1] == 'b' || args
[1] == '5'
7121 || args
[1] == '-' || args
[1] == '4');
7125 case ')': /* these must match exactly */
7130 case '<': /* must be at least one digit */
7132 * According to the manual, if the shift amount is greater
7133 * than 31 or less than 0 the the shift amount should be
7134 * mod 32. In reality the mips assembler issues an error.
7135 * We issue a warning and mask out all but the low 5 bits.
7137 my_getExpression (&imm_expr
, s
);
7138 check_absolute_expr (ip
, &imm_expr
);
7139 if ((unsigned long) imm_expr
.X_add_number
> 31)
7141 as_warn (_("Improper shift amount (%ld)"),
7142 (long) imm_expr
.X_add_number
);
7143 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7145 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7146 imm_expr
.X_op
= O_absent
;
7150 case '>': /* shift amount minus 32 */
7151 my_getExpression (&imm_expr
, s
);
7152 check_absolute_expr (ip
, &imm_expr
);
7153 if ((unsigned long) imm_expr
.X_add_number
< 32
7154 || (unsigned long) imm_expr
.X_add_number
> 63)
7156 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7157 imm_expr
.X_op
= O_absent
;
7161 case 'k': /* cache code */
7162 case 'h': /* prefx code */
7163 my_getExpression (&imm_expr
, s
);
7164 check_absolute_expr (ip
, &imm_expr
);
7165 if ((unsigned long) imm_expr
.X_add_number
> 31)
7167 as_warn (_("Invalid value for `%s' (%lu)"),
7169 (unsigned long) imm_expr
.X_add_number
);
7170 imm_expr
.X_add_number
&= 0x1f;
7173 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7175 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7176 imm_expr
.X_op
= O_absent
;
7180 case 'c': /* break code */
7181 my_getExpression (&imm_expr
, s
);
7182 check_absolute_expr (ip
, &imm_expr
);
7183 if ((unsigned) imm_expr
.X_add_number
> 1023)
7185 as_warn (_("Illegal break code (%ld)"),
7186 (long) imm_expr
.X_add_number
);
7187 imm_expr
.X_add_number
&= 0x3ff;
7189 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7190 imm_expr
.X_op
= O_absent
;
7194 case 'q': /* lower break code */
7195 my_getExpression (&imm_expr
, s
);
7196 check_absolute_expr (ip
, &imm_expr
);
7197 if ((unsigned) imm_expr
.X_add_number
> 1023)
7199 as_warn (_("Illegal lower break code (%ld)"),
7200 (long) imm_expr
.X_add_number
);
7201 imm_expr
.X_add_number
&= 0x3ff;
7203 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7204 imm_expr
.X_op
= O_absent
;
7208 case 'B': /* 20-bit syscall/break code. */
7209 my_getExpression (&imm_expr
, s
);
7210 check_absolute_expr (ip
, &imm_expr
);
7211 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7212 as_warn (_("Illegal 20-bit code (%ld)"),
7213 (long) imm_expr
.X_add_number
);
7214 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7215 imm_expr
.X_op
= O_absent
;
7219 case 'C': /* Coprocessor code */
7220 my_getExpression (&imm_expr
, s
);
7221 check_absolute_expr (ip
, &imm_expr
);
7222 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7224 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7225 (long) imm_expr
.X_add_number
);
7226 imm_expr
.X_add_number
&= ((1<<25) - 1);
7228 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7229 imm_expr
.X_op
= O_absent
;
7233 case 'J': /* 19-bit wait code. */
7234 my_getExpression (&imm_expr
, s
);
7235 check_absolute_expr (ip
, &imm_expr
);
7236 if ((unsigned) imm_expr
.X_add_number
> 0x7ffff)
7237 as_warn (_("Illegal 19-bit code (%ld)"),
7238 (long) imm_expr
.X_add_number
);
7239 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7240 imm_expr
.X_op
= O_absent
;
7244 case 'P': /* Performance register */
7245 my_getExpression (&imm_expr
, s
);
7246 check_absolute_expr (ip
, &imm_expr
);
7247 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7249 as_warn (_("Invalidate performance regster (%ld)"),
7250 (long) imm_expr
.X_add_number
);
7251 imm_expr
.X_add_number
&= 1;
7253 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7254 imm_expr
.X_op
= O_absent
;
7258 case 'b': /* base register */
7259 case 'd': /* destination register */
7260 case 's': /* source register */
7261 case 't': /* target register */
7262 case 'r': /* both target and source */
7263 case 'v': /* both dest and source */
7264 case 'w': /* both dest and target */
7265 case 'E': /* coprocessor target register */
7266 case 'G': /* coprocessor destination register */
7267 case 'x': /* ignore register name */
7268 case 'z': /* must be zero register */
7269 case 'U': /* destination register (clo/clz). */
7274 if (isdigit ((unsigned char) s
[1]))
7284 while (isdigit ((unsigned char) *s
));
7286 as_bad (_("Invalid register number (%d)"), regno
);
7288 else if (*args
== 'E' || *args
== 'G')
7292 if (s
[1] == 'f' && s
[2] == 'p')
7297 else if (s
[1] == 's' && s
[2] == 'p')
7302 else if (s
[1] == 'g' && s
[2] == 'p')
7307 else if (s
[1] == 'a' && s
[2] == 't')
7312 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7317 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7322 else if (itbl_have_entries
)
7327 p
= s
+ 1; /* advance past '$' */
7328 n
= itbl_get_field (&p
); /* n is name */
7330 /* See if this is a register defined in an
7332 if (itbl_get_reg_val (n
, &r
))
7334 /* Get_field advances to the start of
7335 the next field, so we need to back
7336 rack to the end of the last field. */
7340 s
= strchr (s
, '\0');
7353 as_warn (_("Used $at without \".set noat\""));
7359 if (c
== 'r' || c
== 'v' || c
== 'w')
7366 /* 'z' only matches $0. */
7367 if (c
== 'z' && regno
!= 0)
7370 /* Now that we have assembled one operand, we use the args string
7371 * to figure out where it goes in the instruction. */
7378 ip
->insn_opcode
|= regno
<< 21;
7382 ip
->insn_opcode
|= regno
<< 11;
7385 ip
->insn_opcode
|= regno
<< 11;
7386 ip
->insn_opcode
|= regno
<< 16;
7391 ip
->insn_opcode
|= regno
<< 16;
7394 /* This case exists because on the r3000 trunc
7395 expands into a macro which requires a gp
7396 register. On the r6000 or r4000 it is
7397 assembled into a single instruction which
7398 ignores the register. Thus the insn version
7399 is MIPS_ISA2 and uses 'x', and the macro
7400 version is MIPS_ISA1 and uses 't'. */
7403 /* This case is for the div instruction, which
7404 acts differently if the destination argument
7405 is $0. This only matches $0, and is checked
7406 outside the switch. */
7409 /* Itbl operand; not yet implemented. FIXME ?? */
7411 /* What about all other operands like 'i', which
7412 can be specified in the opcode table? */
7422 ip
->insn_opcode
|= lastregno
<< 21;
7425 ip
->insn_opcode
|= lastregno
<< 16;
7430 case 'D': /* floating point destination register */
7431 case 'S': /* floating point source register */
7432 case 'T': /* floating point target register */
7433 case 'R': /* floating point source register */
7437 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7447 while (isdigit ((unsigned char) *s
));
7450 as_bad (_("Invalid float register number (%d)"), regno
);
7452 if ((regno
& 1) != 0
7453 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7454 && ! (strcmp (str
, "mtc1") == 0
7455 || strcmp (str
, "mfc1") == 0
7456 || strcmp (str
, "lwc1") == 0
7457 || strcmp (str
, "swc1") == 0
7458 || strcmp (str
, "l.s") == 0
7459 || strcmp (str
, "s.s") == 0))
7460 as_warn (_("Float register should be even, was %d"),
7468 if (c
== 'V' || c
== 'W')
7478 ip
->insn_opcode
|= regno
<< 6;
7482 ip
->insn_opcode
|= regno
<< 11;
7486 ip
->insn_opcode
|= regno
<< 16;
7489 ip
->insn_opcode
|= regno
<< 21;
7499 ip
->insn_opcode
|= lastregno
<< 11;
7502 ip
->insn_opcode
|= lastregno
<< 16;
7508 my_getExpression (&imm_expr
, s
);
7509 if (imm_expr
.X_op
!= O_big
7510 && imm_expr
.X_op
!= O_constant
)
7511 insn_error
= _("absolute expression required");
7516 my_getExpression (&offset_expr
, s
);
7517 imm_reloc
= BFD_RELOC_32
;
7529 unsigned char temp
[8];
7531 unsigned int length
;
7536 /* These only appear as the last operand in an
7537 instruction, and every instruction that accepts
7538 them in any variant accepts them in all variants.
7539 This means we don't have to worry about backing out
7540 any changes if the instruction does not match.
7542 The difference between them is the size of the
7543 floating point constant and where it goes. For 'F'
7544 and 'L' the constant is 64 bits; for 'f' and 'l' it
7545 is 32 bits. Where the constant is placed is based
7546 on how the MIPS assembler does things:
7549 f -- immediate value
7552 The .lit4 and .lit8 sections are only used if
7553 permitted by the -G argument.
7555 When generating embedded PIC code, we use the
7556 .lit8 section but not the .lit4 section (we can do
7557 .lit4 inline easily; we need to put .lit8
7558 somewhere in the data segment, and using .lit8
7559 permits the linker to eventually combine identical
7562 f64
= *args
== 'F' || *args
== 'L';
7564 save_in
= input_line_pointer
;
7565 input_line_pointer
= s
;
7566 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7568 s
= input_line_pointer
;
7569 input_line_pointer
= save_in
;
7570 if (err
!= NULL
&& *err
!= '\0')
7572 as_bad (_("Bad floating point constant: %s"), err
);
7573 memset (temp
, '\0', sizeof temp
);
7574 length
= f64
? 8 : 4;
7577 assert (length
== (unsigned) (f64
? 8 : 4));
7581 && (! USE_GLOBAL_POINTER_OPT
7582 || mips_pic
== EMBEDDED_PIC
7583 || g_switch_value
< 4
7584 || (temp
[0] == 0 && temp
[1] == 0)
7585 || (temp
[2] == 0 && temp
[3] == 0))))
7587 imm_expr
.X_op
= O_constant
;
7588 if (! target_big_endian
)
7589 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7591 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7594 && ! mips_disable_float_construction
7595 && ((temp
[0] == 0 && temp
[1] == 0)
7596 || (temp
[2] == 0 && temp
[3] == 0))
7597 && ((temp
[4] == 0 && temp
[5] == 0)
7598 || (temp
[6] == 0 && temp
[7] == 0)))
7600 /* The value is simple enough to load with a
7601 couple of instructions. In mips1 mode, set
7602 imm_expr to the high order 32 bits and
7603 offset_expr to the low order 32 bits.
7604 Otherwise, set imm_expr to the entire 64 bit
7606 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7608 imm_expr
.X_op
= O_constant
;
7609 offset_expr
.X_op
= O_constant
;
7610 if (! target_big_endian
)
7612 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7613 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7617 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7618 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7620 if (offset_expr
.X_add_number
== 0)
7621 offset_expr
.X_op
= O_absent
;
7623 else if (sizeof (imm_expr
.X_add_number
) > 4)
7625 imm_expr
.X_op
= O_constant
;
7626 if (! target_big_endian
)
7627 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7629 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7633 imm_expr
.X_op
= O_big
;
7634 imm_expr
.X_add_number
= 4;
7635 if (! target_big_endian
)
7637 generic_bignum
[0] = bfd_getl16 (temp
);
7638 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7639 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7640 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7644 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7645 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7646 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7647 generic_bignum
[3] = bfd_getb16 (temp
);
7653 const char *newname
;
7656 /* Switch to the right section. */
7658 subseg
= now_subseg
;
7661 default: /* unused default case avoids warnings. */
7663 newname
= RDATA_SECTION_NAME
;
7664 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7665 || mips_pic
== EMBEDDED_PIC
)
7669 if (mips_pic
== EMBEDDED_PIC
)
7672 newname
= RDATA_SECTION_NAME
;
7675 assert (!USE_GLOBAL_POINTER_OPT
7676 || g_switch_value
>= 4);
7680 new_seg
= subseg_new (newname
, (subsegT
) 0);
7681 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7682 bfd_set_section_flags (stdoutput
, new_seg
,
7687 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7688 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7689 && strcmp (TARGET_OS
, "elf") != 0)
7690 record_alignment (new_seg
, 4);
7692 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7694 as_bad (_("Can't use floating point insn in this section"));
7696 /* Set the argument to the current address in the
7698 offset_expr
.X_op
= O_symbol
;
7699 offset_expr
.X_add_symbol
=
7700 symbol_new ("L0\001", now_seg
,
7701 (valueT
) frag_now_fix (), frag_now
);
7702 offset_expr
.X_add_number
= 0;
7704 /* Put the floating point number into the section. */
7705 p
= frag_more ((int) length
);
7706 memcpy (p
, temp
, length
);
7708 /* Switch back to the original section. */
7709 subseg_set (seg
, subseg
);
7714 case 'i': /* 16 bit unsigned immediate */
7715 case 'j': /* 16 bit signed immediate */
7716 imm_reloc
= BFD_RELOC_LO16
;
7717 c
= my_getSmallExpression (&imm_expr
, s
);
7722 if (imm_expr
.X_op
== O_constant
)
7723 imm_expr
.X_add_number
=
7724 (imm_expr
.X_add_number
>> 16) & 0xffff;
7727 imm_reloc
= BFD_RELOC_HI16_S
;
7728 imm_unmatched_hi
= true;
7731 imm_reloc
= BFD_RELOC_HI16
;
7733 else if (imm_expr
.X_op
== O_constant
)
7734 imm_expr
.X_add_number
&= 0xffff;
7738 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7739 || ((imm_expr
.X_add_number
< 0
7740 || imm_expr
.X_add_number
>= 0x10000)
7741 && imm_expr
.X_op
== O_constant
))
7743 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7744 !strcmp (insn
->name
, insn
[1].name
))
7746 if (imm_expr
.X_op
== O_constant
7747 || imm_expr
.X_op
== O_big
)
7748 as_bad (_("16 bit expression not in range 0..65535"));
7756 /* The upper bound should be 0x8000, but
7757 unfortunately the MIPS assembler accepts numbers
7758 from 0x8000 to 0xffff and sign extends them, and
7759 we want to be compatible. We only permit this
7760 extended range for an instruction which does not
7761 provide any further alternates, since those
7762 alternates may handle other cases. People should
7763 use the numbers they mean, rather than relying on
7764 a mysterious sign extension. */
7765 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7766 strcmp (insn
->name
, insn
[1].name
) == 0);
7771 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7772 || ((imm_expr
.X_add_number
< -0x8000
7773 || imm_expr
.X_add_number
>= max
)
7774 && imm_expr
.X_op
== O_constant
)
7776 && imm_expr
.X_add_number
< 0
7777 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7778 && imm_expr
.X_unsigned
7779 && sizeof (imm_expr
.X_add_number
) <= 4))
7783 if (imm_expr
.X_op
== O_constant
7784 || imm_expr
.X_op
== O_big
)
7785 as_bad (_("16 bit expression not in range -32768..32767"));
7791 case 'o': /* 16 bit offset */
7792 c
= my_getSmallExpression (&offset_expr
, s
);
7794 /* If this value won't fit into a 16 bit offset, then go
7795 find a macro that will generate the 32 bit offset
7796 code pattern. As a special hack, we accept the
7797 difference of two local symbols as a constant. This
7798 is required to suppose embedded PIC switches, which
7799 use an instruction which looks like
7800 lw $4,$L12-$LS12($4)
7801 The problem with handling this in a more general
7802 fashion is that the macro function doesn't expect to
7803 see anything which can be handled in a single
7804 constant instruction. */
7806 && (offset_expr
.X_op
!= O_constant
7807 || offset_expr
.X_add_number
>= 0x8000
7808 || offset_expr
.X_add_number
< -0x8000)
7809 && (mips_pic
!= EMBEDDED_PIC
7810 || offset_expr
.X_op
!= O_subtract
7811 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7812 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7815 if (c
== 'h' || c
== 'H')
7817 if (offset_expr
.X_op
!= O_constant
)
7819 offset_expr
.X_add_number
=
7820 (offset_expr
.X_add_number
>> 16) & 0xffff;
7822 offset_reloc
= BFD_RELOC_LO16
;
7826 case 'p': /* pc relative offset */
7827 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7828 my_getExpression (&offset_expr
, s
);
7832 case 'u': /* upper 16 bits */
7833 c
= my_getSmallExpression (&imm_expr
, s
);
7834 imm_reloc
= BFD_RELOC_LO16
;
7839 if (imm_expr
.X_op
== O_constant
)
7840 imm_expr
.X_add_number
=
7841 (imm_expr
.X_add_number
>> 16) & 0xffff;
7844 imm_reloc
= BFD_RELOC_HI16_S
;
7845 imm_unmatched_hi
= true;
7848 imm_reloc
= BFD_RELOC_HI16
;
7850 else if (imm_expr
.X_op
== O_constant
)
7851 imm_expr
.X_add_number
&= 0xffff;
7853 if (imm_expr
.X_op
== O_constant
7854 && (imm_expr
.X_add_number
< 0
7855 || imm_expr
.X_add_number
>= 0x10000))
7856 as_bad (_("lui expression not in range 0..65535"));
7860 case 'a': /* 26 bit address */
7861 my_getExpression (&offset_expr
, s
);
7863 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7866 case 'N': /* 3 bit branch condition code */
7867 case 'M': /* 3 bit compare condition code */
7868 if (strncmp (s
, "$fcc", 4) != 0)
7878 while (isdigit ((unsigned char) *s
));
7880 as_bad (_("invalid condition code register $fcc%d"), regno
);
7882 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7884 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7888 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7890 if (isdigit ((unsigned char) *s
))
7899 while (isdigit ((unsigned char) *s
));
7902 c
= 8; /* Invalid sel value. */
7905 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7906 ip
->insn_opcode
|= c
;
7910 as_bad (_("bad char = '%c'\n"), *args
);
7915 /* Args don't match. */
7916 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7917 !strcmp (insn
->name
, insn
[1].name
))
7923 insn_error
= _("illegal operands");
7928 /* This routine assembles an instruction into its binary format when
7929 assembling for the mips16. As a side effect, it sets one of the
7930 global variables imm_reloc or offset_reloc to the type of
7931 relocation to do if one of the operands is an address expression.
7932 It also sets mips16_small and mips16_ext if the user explicitly
7933 requested a small or extended instruction. */
7938 struct mips_cl_insn
*ip
;
7942 struct mips_opcode
*insn
;
7945 unsigned int lastregno
= 0;
7950 mips16_small
= false;
7953 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7965 if (s
[1] == 't' && s
[2] == ' ')
7968 mips16_small
= true;
7972 else if (s
[1] == 'e' && s
[2] == ' ')
7981 insn_error
= _("unknown opcode");
7985 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7986 mips16_small
= true;
7988 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7990 insn_error
= _("unrecognized opcode");
7997 assert (strcmp (insn
->name
, str
) == 0);
8000 ip
->insn_opcode
= insn
->match
;
8001 ip
->use_extend
= false;
8002 imm_expr
.X_op
= O_absent
;
8003 imm_reloc
= BFD_RELOC_UNUSED
;
8004 offset_expr
.X_op
= O_absent
;
8005 offset_reloc
= BFD_RELOC_UNUSED
;
8006 for (args
= insn
->args
; 1; ++args
)
8013 /* In this switch statement we call break if we did not find
8014 a match, continue if we did find a match, or return if we
8023 /* Stuff the immediate value in now, if we can. */
8024 if (imm_expr
.X_op
== O_constant
8025 && imm_reloc
> BFD_RELOC_UNUSED
8026 && insn
->pinfo
!= INSN_MACRO
)
8028 mips16_immed ((char *) NULL
, 0,
8029 imm_reloc
- BFD_RELOC_UNUSED
,
8030 imm_expr
.X_add_number
, true, mips16_small
,
8031 mips16_ext
, &ip
->insn_opcode
,
8032 &ip
->use_extend
, &ip
->extend
);
8033 imm_expr
.X_op
= O_absent
;
8034 imm_reloc
= BFD_RELOC_UNUSED
;
8048 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8051 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8067 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8069 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8086 if (isdigit ((unsigned char) s
[1]))
8096 while (isdigit ((unsigned char) *s
));
8099 as_bad (_("invalid register number (%d)"), regno
);
8105 if (s
[1] == 'f' && s
[2] == 'p')
8110 else if (s
[1] == 's' && s
[2] == 'p')
8115 else if (s
[1] == 'g' && s
[2] == 'p')
8120 else if (s
[1] == 'a' && s
[2] == 't')
8125 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8130 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8143 if (c
== 'v' || c
== 'w')
8145 regno
= mips16_to_32_reg_map
[lastregno
];
8159 regno
= mips32_to_16_reg_map
[regno
];
8164 regno
= ILLEGAL_REG
;
8169 regno
= ILLEGAL_REG
;
8174 regno
= ILLEGAL_REG
;
8179 if (regno
== AT
&& ! mips_opts
.noat
)
8180 as_warn (_("used $at without \".set noat\""));
8187 if (regno
== ILLEGAL_REG
)
8194 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8198 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8201 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8204 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8210 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8213 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8214 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8224 if (strncmp (s
, "$pc", 3) == 0)
8248 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8250 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8251 and generate the appropriate reloc. If the text
8252 inside %gprel is not a symbol name with an
8253 optional offset, then we generate a normal reloc
8254 and will probably fail later. */
8255 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8256 if (imm_expr
.X_op
== O_symbol
)
8259 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8261 ip
->use_extend
= true;
8268 /* Just pick up a normal expression. */
8269 my_getExpression (&imm_expr
, s
);
8272 if (imm_expr
.X_op
== O_register
)
8274 /* What we thought was an expression turned out to
8277 if (s
[0] == '(' && args
[1] == '(')
8279 /* It looks like the expression was omitted
8280 before a register indirection, which means
8281 that the expression is implicitly zero. We
8282 still set up imm_expr, so that we handle
8283 explicit extensions correctly. */
8284 imm_expr
.X_op
= O_constant
;
8285 imm_expr
.X_add_number
= 0;
8286 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8293 /* We need to relax this instruction. */
8294 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8303 /* We use offset_reloc rather than imm_reloc for the PC
8304 relative operands. This lets macros with both
8305 immediate and address operands work correctly. */
8306 my_getExpression (&offset_expr
, s
);
8308 if (offset_expr
.X_op
== O_register
)
8311 /* We need to relax this instruction. */
8312 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8316 case '6': /* break code */
8317 my_getExpression (&imm_expr
, s
);
8318 check_absolute_expr (ip
, &imm_expr
);
8319 if ((unsigned long) imm_expr
.X_add_number
> 63)
8321 as_warn (_("Invalid value for `%s' (%lu)"),
8323 (unsigned long) imm_expr
.X_add_number
);
8324 imm_expr
.X_add_number
&= 0x3f;
8326 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8327 imm_expr
.X_op
= O_absent
;
8331 case 'a': /* 26 bit address */
8332 my_getExpression (&offset_expr
, s
);
8334 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8335 ip
->insn_opcode
<<= 16;
8338 case 'l': /* register list for entry macro */
8339 case 'L': /* register list for exit macro */
8349 int freg
, reg1
, reg2
;
8351 while (*s
== ' ' || *s
== ',')
8355 as_bad (_("can't parse register list"));
8367 while (isdigit ((unsigned char) *s
))
8389 as_bad (_("invalid register list"));
8394 while (isdigit ((unsigned char) *s
))
8401 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8406 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8411 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8412 mask
|= (reg2
- 3) << 3;
8413 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8414 mask
|= (reg2
- 15) << 1;
8415 else if (reg1
== 31 && reg2
== 31)
8419 as_bad (_("invalid register list"));
8423 /* The mask is filled in in the opcode table for the
8424 benefit of the disassembler. We remove it before
8425 applying the actual mask. */
8426 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8427 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8431 case 'e': /* extend code */
8432 my_getExpression (&imm_expr
, s
);
8433 check_absolute_expr (ip
, &imm_expr
);
8434 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8436 as_warn (_("Invalid value for `%s' (%lu)"),
8438 (unsigned long) imm_expr
.X_add_number
);
8439 imm_expr
.X_add_number
&= 0x7ff;
8441 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8442 imm_expr
.X_op
= O_absent
;
8452 /* Args don't match. */
8453 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8454 strcmp (insn
->name
, insn
[1].name
) == 0)
8461 insn_error
= _("illegal operands");
8467 /* This structure holds information we know about a mips16 immediate
8470 struct mips16_immed_operand
8472 /* The type code used in the argument string in the opcode table. */
8474 /* The number of bits in the short form of the opcode. */
8476 /* The number of bits in the extended form of the opcode. */
8478 /* The amount by which the short form is shifted when it is used;
8479 for example, the sw instruction has a shift count of 2. */
8481 /* The amount by which the short form is shifted when it is stored
8482 into the instruction code. */
8484 /* Non-zero if the short form is unsigned. */
8486 /* Non-zero if the extended form is unsigned. */
8488 /* Non-zero if the value is PC relative. */
8492 /* The mips16 immediate operand types. */
8494 static const struct mips16_immed_operand mips16_immed_operands
[] =
8496 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8497 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8498 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8499 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8500 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8501 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8502 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8503 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8504 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8505 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8506 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8507 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8508 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8509 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8510 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8511 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8512 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8513 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8514 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8515 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8516 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8519 #define MIPS16_NUM_IMMED \
8520 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8522 /* Handle a mips16 instruction with an immediate value. This or's the
8523 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8524 whether an extended value is needed; if one is needed, it sets
8525 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8526 If SMALL is true, an unextended opcode was explicitly requested.
8527 If EXT is true, an extended opcode was explicitly requested. If
8528 WARN is true, warn if EXT does not match reality. */
8531 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8540 unsigned long *insn
;
8541 boolean
*use_extend
;
8542 unsigned short *extend
;
8544 register const struct mips16_immed_operand
*op
;
8545 int mintiny
, maxtiny
;
8548 op
= mips16_immed_operands
;
8549 while (op
->type
!= type
)
8552 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8557 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8560 maxtiny
= 1 << op
->nbits
;
8565 maxtiny
= (1 << op
->nbits
) - 1;
8570 mintiny
= - (1 << (op
->nbits
- 1));
8571 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8574 /* Branch offsets have an implicit 0 in the lowest bit. */
8575 if (type
== 'p' || type
== 'q')
8578 if ((val
& ((1 << op
->shift
) - 1)) != 0
8579 || val
< (mintiny
<< op
->shift
)
8580 || val
> (maxtiny
<< op
->shift
))
8585 if (warn
&& ext
&& ! needext
)
8586 as_warn_where (file
, line
, _("extended operand requested but not required"));
8587 if (small
&& needext
)
8588 as_bad_where (file
, line
, _("invalid unextended operand value"));
8590 if (small
|| (! ext
&& ! needext
))
8594 *use_extend
= false;
8595 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8596 insnval
<<= op
->op_shift
;
8601 long minext
, maxext
;
8607 maxext
= (1 << op
->extbits
) - 1;
8611 minext
= - (1 << (op
->extbits
- 1));
8612 maxext
= (1 << (op
->extbits
- 1)) - 1;
8614 if (val
< minext
|| val
> maxext
)
8615 as_bad_where (file
, line
,
8616 _("operand value out of range for instruction"));
8619 if (op
->extbits
== 16)
8621 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8624 else if (op
->extbits
== 15)
8626 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8631 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8635 *extend
= (unsigned short) extval
;
8644 my_getSmallExpression (ep
, str
)
8655 ((str
[1] == 'h' && str
[2] == 'i')
8656 || (str
[1] == 'H' && str
[2] == 'I')
8657 || (str
[1] == 'l' && str
[2] == 'o'))
8669 * A small expression may be followed by a base register.
8670 * Scan to the end of this operand, and then back over a possible
8671 * base register. Then scan the small expression up to that
8672 * point. (Based on code in sparc.c...)
8674 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8676 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8678 if (isdigit ((unsigned char) sp
[-2]))
8680 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8682 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8688 else if (sp
- 5 >= str
8691 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8692 || (sp
[-3] == 's' && sp
[-2] == 'p')
8693 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8694 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8700 /* no expression means zero offset */
8703 /* %xx(reg) is an error */
8704 ep
->X_op
= O_absent
;
8709 ep
->X_op
= O_constant
;
8712 ep
->X_add_symbol
= NULL
;
8713 ep
->X_op_symbol
= NULL
;
8714 ep
->X_add_number
= 0;
8719 my_getExpression (ep
, str
);
8726 my_getExpression (ep
, str
);
8727 return c
; /* => %hi or %lo encountered */
8731 my_getExpression (ep
, str
)
8737 save_in
= input_line_pointer
;
8738 input_line_pointer
= str
;
8740 expr_end
= input_line_pointer
;
8741 input_line_pointer
= save_in
;
8743 /* If we are in mips16 mode, and this is an expression based on `.',
8744 then we bump the value of the symbol by 1 since that is how other
8745 text symbols are handled. We don't bother to handle complex
8746 expressions, just `.' plus or minus a constant. */
8747 if (mips_opts
.mips16
8748 && ep
->X_op
== O_symbol
8749 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8750 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8751 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8752 && symbol_constant_p (ep
->X_add_symbol
)
8753 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8754 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8757 /* Turn a string in input_line_pointer into a floating point constant
8758 of type TYPE, and store the appropriate bytes in *LITP. The number
8759 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8760 returned, or NULL on OK. */
8763 md_atof (type
, litP
, sizeP
)
8769 LITTLENUM_TYPE words
[4];
8785 return _("bad call to md_atof");
8788 t
= atof_ieee (input_line_pointer
, type
, words
);
8790 input_line_pointer
= t
;
8794 if (! target_big_endian
)
8796 for (i
= prec
- 1; i
>= 0; i
--)
8798 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8804 for (i
= 0; i
< prec
; i
++)
8806 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8815 md_number_to_chars (buf
, val
, n
)
8820 if (target_big_endian
)
8821 number_to_chars_bigendian (buf
, val
, n
);
8823 number_to_chars_littleendian (buf
, val
, n
);
8826 CONST
char *md_shortopts
= "O::g::G:";
8828 struct option md_longopts
[] =
8830 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8831 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8832 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8833 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8834 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8835 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8836 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8837 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8838 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8839 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8840 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8841 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8842 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8843 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8844 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8845 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8846 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8847 {"break", no_argument
, NULL
, OPTION_BREAK
},
8848 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8849 #define OPTION_EB (OPTION_MD_BASE + 9)
8850 {"EB", no_argument
, NULL
, OPTION_EB
},
8851 #define OPTION_EL (OPTION_MD_BASE + 10)
8852 {"EL", no_argument
, NULL
, OPTION_EL
},
8853 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8854 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8855 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8856 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8857 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8858 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8859 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8860 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8861 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8862 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8863 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8864 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8865 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8866 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8867 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8868 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8869 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8870 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8871 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8872 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8873 #define OPTION_MABI (OPTION_MD_BASE + 21)
8874 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8875 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8876 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8877 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8878 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8879 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8880 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8881 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8882 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8883 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8884 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8885 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8886 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8887 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8888 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8889 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8890 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8891 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8892 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8894 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8895 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8896 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8897 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8898 #define OPTION_32 (OPTION_ELF_BASE + 3)
8899 #define OPTION_64 (OPTION_ELF_BASE + 4)
8900 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8901 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8902 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8903 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8904 {"32", no_argument
, NULL
, OPTION_32
},
8905 {"64", no_argument
, NULL
, OPTION_64
},
8908 {NULL
, no_argument
, NULL
, 0}
8910 size_t md_longopts_size
= sizeof (md_longopts
);
8913 md_parse_option (c
, arg
)
8919 case OPTION_CONSTRUCT_FLOATS
:
8920 mips_disable_float_construction
= 0;
8923 case OPTION_NO_CONSTRUCT_FLOATS
:
8924 mips_disable_float_construction
= 1;
8936 target_big_endian
= 1;
8940 target_big_endian
= 0;
8944 if (arg
&& arg
[1] == '0')
8954 mips_debug
= atoi (arg
);
8955 /* When the MIPS assembler sees -g or -g2, it does not do
8956 optimizations which limit full symbolic debugging. We take
8957 that to be equivalent to -O0. */
8958 if (mips_debug
== 2)
8963 mips_opts
.isa
= ISA_MIPS1
;
8967 mips_opts
.isa
= ISA_MIPS2
;
8971 mips_opts
.isa
= ISA_MIPS3
;
8975 mips_opts
.isa
= ISA_MIPS4
;
8979 mips_opts
.isa
= ISA_MIPS5
;
8983 mips_opts
.isa
= ISA_MIPS32
;
8987 mips_opts
.isa
= ISA_MIPS64
;
8992 /* Identify the processor type. */
8993 if (strcasecmp (arg
, "default") == 0)
8994 mips_cpu
= CPU_UNKNOWN
;
8997 const struct mips_cpu_info
*ci
;
8999 ci
= mips_cpu_info_from_name (arg
);
9000 if (ci
== NULL
|| ci
->is_isa
)
9001 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9009 mips_cpu
= CPU_R4650
;
9012 case OPTION_NO_M4650
:
9016 mips_cpu
= CPU_R4010
;
9019 case OPTION_NO_M4010
:
9023 mips_cpu
= CPU_VR4100
;
9026 case OPTION_NO_M4100
:
9030 mips_cpu
= CPU_R3900
;
9033 case OPTION_NO_M3900
:
9037 mips_opts
.mips16
= 1;
9038 mips_no_prev_insn (false);
9041 case OPTION_NO_MIPS16
:
9042 mips_opts
.mips16
= 0;
9043 mips_no_prev_insn (false);
9046 case OPTION_MEMBEDDED_PIC
:
9047 mips_pic
= EMBEDDED_PIC
;
9048 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9050 as_bad (_("-G may not be used with embedded PIC code"));
9053 g_switch_value
= 0x7fffffff;
9056 /* When generating ELF code, we permit -KPIC and -call_shared to
9057 select SVR4_PIC, and -non_shared to select no PIC. This is
9058 intended to be compatible with Irix 5. */
9059 case OPTION_CALL_SHARED
:
9060 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9062 as_bad (_("-call_shared is supported only for ELF format"));
9065 mips_pic
= SVR4_PIC
;
9066 if (g_switch_seen
&& g_switch_value
!= 0)
9068 as_bad (_("-G may not be used with SVR4 PIC code"));
9074 case OPTION_NON_SHARED
:
9075 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9077 as_bad (_("-non_shared is supported only for ELF format"));
9083 /* The -xgot option tells the assembler to use 32 offsets when
9084 accessing the got in SVR4_PIC mode. It is for Irix
9091 if (! USE_GLOBAL_POINTER_OPT
)
9093 as_bad (_("-G is not supported for this configuration"));
9096 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9098 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9102 g_switch_value
= atoi (arg
);
9106 /* The -32 and -64 options tell the assembler to output the 32
9107 bit or the 64 bit MIPS ELF format. */
9114 const char **list
, **l
;
9116 list
= bfd_target_list ();
9117 for (l
= list
; *l
!= NULL
; l
++)
9118 if (strcmp (*l
, "elf64-bigmips") == 0
9119 || strcmp (*l
, "elf64-littlemips") == 0)
9122 as_fatal (_("No compiled in support for 64 bit object file format"));
9132 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9133 flag in object files because to do so would make it
9134 impossible to link with libraries compiled without "-gp32".
9135 This is unnecessarily restrictive.
9137 We could solve this problem by adding "-gp32" multilibs to
9138 gcc, but to set this flag before gcc is built with such
9139 multilibs will break too many systems. */
9141 /* mips_32bitmode = 1; */
9147 /* mips_32bitmode = 0; */
9151 if (strcmp (arg
,"32") == 0
9152 || strcmp (arg
,"n32") == 0
9153 || strcmp (arg
,"64") == 0
9154 || strcmp (arg
,"o64") == 0
9155 || strcmp (arg
,"eabi") == 0)
9156 mips_abi_string
= arg
;
9159 case OPTION_M7000_HILO_FIX
:
9160 mips_7000_hilo_fix
= true;
9163 case OPTION_NO_M7000_HILO_FIX
:
9164 mips_7000_hilo_fix
= false;
9175 show (stream
, string
, col_p
, first_p
)
9183 fprintf (stream
, "%24s", "");
9188 fprintf (stream
, ", ");
9192 if (*col_p
+ strlen (string
) > 72)
9194 fprintf (stream
, "\n%24s", "");
9198 fprintf (stream
, "%s", string
);
9199 *col_p
+= strlen (string
);
9205 md_show_usage (stream
)
9210 fprintf(stream
, _("\
9212 -membedded-pic generate embedded position independent code\n\
9213 -EB generate big endian output\n\
9214 -EL generate little endian output\n\
9215 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9216 -G NUM allow referencing objects up to NUM bytes\n\
9217 implicitly with the gp register [default 8]\n"));
9218 fprintf(stream
, _("\
9219 -mips1 generate MIPS ISA I instructions\n\
9220 -mips2 generate MIPS ISA II instructions\n\
9221 -mips3 generate MIPS ISA III instructions\n\
9222 -mips4 generate MIPS ISA IV instructions\n\
9223 -mips5 generate MIPS ISA V instructions\n\
9224 -mips32 generate MIPS32 ISA instructions\n\
9225 -mips64 generate MIPS64 ISA instructions\n\
9226 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9230 show (stream
, "2000", &column
, &first
);
9231 show (stream
, "3000", &column
, &first
);
9232 show (stream
, "3900", &column
, &first
);
9233 show (stream
, "4000", &column
, &first
);
9234 show (stream
, "4010", &column
, &first
);
9235 show (stream
, "4100", &column
, &first
);
9236 show (stream
, "4111", &column
, &first
);
9237 show (stream
, "4300", &column
, &first
);
9238 show (stream
, "4400", &column
, &first
);
9239 show (stream
, "4600", &column
, &first
);
9240 show (stream
, "4650", &column
, &first
);
9241 show (stream
, "5000", &column
, &first
);
9242 show (stream
, "6000", &column
, &first
);
9243 show (stream
, "8000", &column
, &first
);
9244 show (stream
, "10000", &column
, &first
);
9245 show (stream
, "mips32-4k", &column
, &first
);
9246 fputc ('\n', stream
);
9248 fprintf (stream
, _("\
9249 -mCPU equivalent to -mcpu=CPU.\n\
9250 -no-mCPU don't generate code specific to CPU.\n\
9251 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9255 show (stream
, "3900", &column
, &first
);
9256 show (stream
, "4010", &column
, &first
);
9257 show (stream
, "4100", &column
, &first
);
9258 show (stream
, "4650", &column
, &first
);
9259 fputc ('\n', stream
);
9261 fprintf(stream
, _("\
9262 -mips16 generate mips16 instructions\n\
9263 -no-mips16 do not generate mips16 instructions\n"));
9264 fprintf(stream
, _("\
9265 -O0 remove unneeded NOPs, do not swap branches\n\
9266 -O remove unneeded NOPs and swap branches\n\
9267 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9268 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9269 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9271 fprintf(stream
, _("\
9272 -KPIC, -call_shared generate SVR4 position independent code\n\
9273 -non_shared do not generate position independent code\n\
9274 -xgot assume a 32 bit GOT\n\
9275 -32 create 32 bit object file (default)\n\
9276 -64 create 64 bit object file\n"));
9281 mips_init_after_args ()
9283 /* initialize opcodes */
9284 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9285 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9289 md_pcrel_from (fixP
)
9292 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9293 && fixP
->fx_addsy
!= (symbolS
*) NULL
9294 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9296 /* This makes a branch to an undefined symbol be a branch to the
9297 current location. */
9301 /* return the address of the delay slot */
9302 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9305 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9306 reloc for a cons. We could use the definition there, except that
9307 we want to handle 64 bit relocs specially. */
9310 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9311 fragS
*frag ATTRIBUTE_UNUSED
;
9313 unsigned int nbytes
;
9317 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9319 if (nbytes
== 8 && ! mips_64
)
9321 if (target_big_endian
)
9327 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9328 as_bad (_("Unsupported reloc size %d"), nbytes
);
9330 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9333 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9336 /* This is called before the symbol table is processed. In order to
9337 work with gcc when using mips-tfile, we must keep all local labels.
9338 However, in other cases, we want to discard them. If we were
9339 called with -g, but we didn't see any debugging information, it may
9340 mean that gcc is smuggling debugging information through to
9341 mips-tfile, in which case we must generate all local labels. */
9344 mips_frob_file_before_adjust ()
9346 #ifndef NO_ECOFF_DEBUGGING
9349 && ! ecoff_debugging_seen
)
9350 flag_keep_locals
= 1;
9354 /* Sort any unmatched HI16_S relocs so that they immediately precede
9355 the corresponding LO reloc. This is called before md_apply_fix and
9356 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9357 explicit use of the %hi modifier. */
9362 struct mips_hi_fixup
*l
;
9364 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9366 segment_info_type
*seginfo
;
9369 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9371 /* Check quickly whether the next fixup happens to be a matching
9373 if (l
->fixp
->fx_next
!= NULL
9374 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9375 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9376 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9379 /* Look through the fixups for this segment for a matching %lo.
9380 When we find one, move the %hi just in front of it. We do
9381 this in two passes. In the first pass, we try to find a
9382 unique %lo. In the second pass, we permit multiple %hi
9383 relocs for a single %lo (this is a GNU extension). */
9384 seginfo
= seg_info (l
->seg
);
9385 for (pass
= 0; pass
< 2; pass
++)
9390 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9392 /* Check whether this is a %lo fixup which matches l->fixp. */
9393 if (f
->fx_r_type
== BFD_RELOC_LO16
9394 && f
->fx_addsy
== l
->fixp
->fx_addsy
9395 && f
->fx_offset
== l
->fixp
->fx_offset
9398 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9399 || prev
->fx_addsy
!= f
->fx_addsy
9400 || prev
->fx_offset
!= f
->fx_offset
))
9404 /* Move l->fixp before f. */
9405 for (pf
= &seginfo
->fix_root
;
9407 pf
= &(*pf
)->fx_next
)
9408 assert (*pf
!= NULL
);
9410 *pf
= l
->fixp
->fx_next
;
9412 l
->fixp
->fx_next
= f
;
9414 seginfo
->fix_root
= l
->fixp
;
9416 prev
->fx_next
= l
->fixp
;
9427 #if 0 /* GCC code motion plus incomplete dead code elimination
9428 can leave a %hi without a %lo. */
9430 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9431 _("Unmatched %%hi reloc"));
9437 /* When generating embedded PIC code we need to use a special
9438 relocation to represent the difference of two symbols in the .text
9439 section (switch tables use a difference of this sort). See
9440 include/coff/mips.h for details. This macro checks whether this
9441 fixup requires the special reloc. */
9442 #define SWITCH_TABLE(fixp) \
9443 ((fixp)->fx_r_type == BFD_RELOC_32 \
9444 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9445 && (fixp)->fx_addsy != NULL \
9446 && (fixp)->fx_subsy != NULL \
9447 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9448 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9450 /* When generating embedded PIC code we must keep all PC relative
9451 relocations, in case the linker has to relax a call. We also need
9452 to keep relocations for switch table entries. */
9456 mips_force_relocation (fixp
)
9459 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9460 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9463 return (mips_pic
== EMBEDDED_PIC
9465 || SWITCH_TABLE (fixp
)
9466 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9467 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9470 /* Apply a fixup to the object file. */
9473 md_apply_fix (fixP
, valueP
)
9480 assert (fixP
->fx_size
== 4
9481 || fixP
->fx_r_type
== BFD_RELOC_16
9482 || fixP
->fx_r_type
== BFD_RELOC_64
9483 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9484 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9488 /* If we aren't adjusting this fixup to be against the section
9489 symbol, we need to adjust the value. */
9491 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9493 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9494 || S_IS_WEAK (fixP
->fx_addsy
)
9495 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9496 && (((bfd_get_section_flags (stdoutput
,
9497 S_GET_SEGMENT (fixP
->fx_addsy
))
9498 & SEC_LINK_ONCE
) != 0)
9499 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9501 sizeof (".gnu.linkonce") - 1))))
9504 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9505 if (value
!= 0 && ! fixP
->fx_pcrel
)
9507 /* In this case, the bfd_install_relocation routine will
9508 incorrectly add the symbol value back in. We just want
9509 the addend to appear in the object file.
9510 FIXME: If this makes VALUE zero, we're toast. */
9511 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9515 /* This code was generated using trial and error and so is
9516 fragile and not trustworthy. If you change it, you should
9517 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9519 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9521 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9523 /* BFD's REL handling, for MIPS, is _very_ weird.
9524 This gives the right results, but it can't possibly
9525 be the way things are supposed to work. */
9526 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9527 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9528 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9533 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9535 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9538 switch (fixP
->fx_r_type
)
9540 case BFD_RELOC_MIPS_JMP
:
9541 case BFD_RELOC_HI16
:
9542 case BFD_RELOC_HI16_S
:
9543 case BFD_RELOC_MIPS_GPREL
:
9544 case BFD_RELOC_MIPS_LITERAL
:
9545 case BFD_RELOC_MIPS_CALL16
:
9546 case BFD_RELOC_MIPS_GOT16
:
9547 case BFD_RELOC_MIPS_GPREL32
:
9548 case BFD_RELOC_MIPS_GOT_HI16
:
9549 case BFD_RELOC_MIPS_GOT_LO16
:
9550 case BFD_RELOC_MIPS_CALL_HI16
:
9551 case BFD_RELOC_MIPS_CALL_LO16
:
9552 case BFD_RELOC_MIPS16_GPREL
:
9554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9555 _("Invalid PC relative reloc"));
9556 /* Nothing needed to do. The value comes from the reloc entry */
9559 case BFD_RELOC_MIPS16_JMP
:
9560 /* We currently always generate a reloc against a symbol, which
9561 means that we don't want an addend even if the symbol is
9563 fixP
->fx_addnumber
= 0;
9566 case BFD_RELOC_PCREL_HI16_S
:
9567 /* The addend for this is tricky if it is internal, so we just
9568 do everything here rather than in bfd_install_relocation. */
9569 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9574 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9576 /* For an external symbol adjust by the address to make it
9577 pcrel_offset. We use the address of the RELLO reloc
9578 which follows this one. */
9579 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9580 + fixP
->fx_next
->fx_where
);
9585 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9586 if (target_big_endian
)
9588 md_number_to_chars (buf
, value
, 2);
9591 case BFD_RELOC_PCREL_LO16
:
9592 /* The addend for this is tricky if it is internal, so we just
9593 do everything here rather than in bfd_install_relocation. */
9594 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9599 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9600 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9601 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9602 if (target_big_endian
)
9604 md_number_to_chars (buf
, value
, 2);
9608 /* This is handled like BFD_RELOC_32, but we output a sign
9609 extended value if we are only 32 bits. */
9611 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9613 if (8 <= sizeof (valueT
))
9614 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9621 w1
= w2
= fixP
->fx_where
;
9622 if (target_big_endian
)
9626 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9627 if ((value
& 0x80000000) != 0)
9631 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9638 /* If we are deleting this reloc entry, we must fill in the
9639 value now. This can happen if we have a .word which is not
9640 resolved when it appears but is later defined. We also need
9641 to fill in the value if this is an embedded PIC switch table
9644 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9645 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9650 /* If we are deleting this reloc entry, we must fill in the
9652 assert (fixP
->fx_size
== 2);
9654 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9658 case BFD_RELOC_LO16
:
9659 /* When handling an embedded PIC switch statement, we can wind
9660 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9663 if (value
< -0x8000 || value
> 0x7fff)
9664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9665 _("relocation overflow"));
9666 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9667 if (target_big_endian
)
9669 md_number_to_chars (buf
, value
, 2);
9673 case BFD_RELOC_16_PCREL_S2
:
9675 * We need to save the bits in the instruction since fixup_segment()
9676 * might be deleting the relocation entry (i.e., a branch within
9677 * the current segment).
9679 if ((value
& 0x3) != 0)
9680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9681 _("Branch to odd address (%lx)"), value
);
9683 if (!fixP
->fx_done
&& value
!= 0)
9685 /* If 'value' is zero, the remaining reloc code won't actually
9686 do the store, so it must be done here. This is probably
9689 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9693 /* update old instruction data */
9694 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9695 if (target_big_endian
)
9696 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9698 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9700 if (value
>= -0x8000 && value
< 0x8000)
9701 insn
|= value
& 0xffff;
9704 /* The branch offset is too large. If this is an
9705 unconditional branch, and we are not generating PIC code,
9706 we can convert it to an absolute jump instruction. */
9707 if (mips_pic
== NO_PIC
9709 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9710 && (fixP
->fx_frag
->fr_address
9711 < text_section
->vma
+ text_section
->_raw_size
)
9712 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9713 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9714 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9716 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9717 insn
= 0x0c000000; /* jal */
9719 insn
= 0x08000000; /* j */
9720 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9722 fixP
->fx_addsy
= section_symbol (text_section
);
9723 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9727 /* FIXME. It would be possible in principle to handle
9728 conditional branches which overflow. They could be
9729 transformed into a branch around a jump. This would
9730 require setting up variant frags for each different
9731 branch type. The native MIPS assembler attempts to
9732 handle these cases, but it appears to do it
9734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9735 _("Branch out of range"));
9739 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9742 case BFD_RELOC_VTABLE_INHERIT
:
9745 && !S_IS_DEFINED (fixP
->fx_addsy
)
9746 && !S_IS_WEAK (fixP
->fx_addsy
))
9747 S_SET_WEAK (fixP
->fx_addsy
);
9750 case BFD_RELOC_VTABLE_ENTRY
:
9766 const struct mips_opcode
*p
;
9767 int treg
, sreg
, dreg
, shamt
;
9772 for (i
= 0; i
< NUMOPCODES
; ++i
)
9774 p
= &mips_opcodes
[i
];
9775 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9777 printf ("%08lx %s\t", oc
, p
->name
);
9778 treg
= (oc
>> 16) & 0x1f;
9779 sreg
= (oc
>> 21) & 0x1f;
9780 dreg
= (oc
>> 11) & 0x1f;
9781 shamt
= (oc
>> 6) & 0x1f;
9783 for (args
= p
->args
;; ++args
)
9794 printf ("%c", *args
);
9798 assert (treg
== sreg
);
9799 printf ("$%d,$%d", treg
, sreg
);
9804 printf ("$%d", dreg
);
9809 printf ("$%d", treg
);
9813 printf ("0x%x", treg
);
9818 printf ("$%d", sreg
);
9822 printf ("0x%08lx", oc
& 0x1ffffff);
9834 printf ("$%d", shamt
);
9845 printf (_("%08lx UNDEFINED\n"), oc
);
9856 name
= input_line_pointer
;
9857 c
= get_symbol_end ();
9858 p
= (symbolS
*) symbol_find_or_make (name
);
9859 *input_line_pointer
= c
;
9863 /* Align the current frag to a given power of two. The MIPS assembler
9864 also automatically adjusts any preceding label. */
9867 mips_align (to
, fill
, label
)
9872 mips_emit_delays (false);
9873 frag_align (to
, fill
, 0);
9874 record_alignment (now_seg
, to
);
9877 assert (S_GET_SEGMENT (label
) == now_seg
);
9878 symbol_set_frag (label
, frag_now
);
9879 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9883 /* Align to a given power of two. .align 0 turns off the automatic
9884 alignment used by the data creating pseudo-ops. */
9888 int x ATTRIBUTE_UNUSED
;
9891 register long temp_fill
;
9892 long max_alignment
= 15;
9896 o Note that the assembler pulls down any immediately preceeding label
9897 to the aligned address.
9898 o It's not documented but auto alignment is reinstated by
9899 a .align pseudo instruction.
9900 o Note also that after auto alignment is turned off the mips assembler
9901 issues an error on attempt to assemble an improperly aligned data item.
9906 temp
= get_absolute_expression ();
9907 if (temp
> max_alignment
)
9908 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9911 as_warn (_("Alignment negative: 0 assumed."));
9914 if (*input_line_pointer
== ',')
9916 input_line_pointer
++;
9917 temp_fill
= get_absolute_expression ();
9924 mips_align (temp
, (int) temp_fill
,
9925 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9932 demand_empty_rest_of_line ();
9936 mips_flush_pending_output ()
9938 mips_emit_delays (false);
9939 mips_clear_insn_labels ();
9948 /* When generating embedded PIC code, we only use the .text, .lit8,
9949 .sdata and .sbss sections. We change the .data and .rdata
9950 pseudo-ops to use .sdata. */
9951 if (mips_pic
== EMBEDDED_PIC
9952 && (sec
== 'd' || sec
== 'r'))
9956 /* The ELF backend needs to know that we are changing sections, so
9957 that .previous works correctly. We could do something like check
9958 for a obj_section_change_hook macro, but that might be confusing
9959 as it would not be appropriate to use it in the section changing
9960 functions in read.c, since obj-elf.c intercepts those. FIXME:
9961 This should be cleaner, somehow. */
9962 obj_elf_section_change_hook ();
9965 mips_emit_delays (false);
9975 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9976 demand_empty_rest_of_line ();
9980 if (USE_GLOBAL_POINTER_OPT
)
9982 seg
= subseg_new (RDATA_SECTION_NAME
,
9983 (subsegT
) get_absolute_expression ());
9984 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9986 bfd_set_section_flags (stdoutput
, seg
,
9992 if (strcmp (TARGET_OS
, "elf") != 0)
9993 record_alignment (seg
, 4);
9995 demand_empty_rest_of_line ();
9999 as_bad (_("No read only data section in this object file format"));
10000 demand_empty_rest_of_line ();
10006 if (USE_GLOBAL_POINTER_OPT
)
10008 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10009 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10011 bfd_set_section_flags (stdoutput
, seg
,
10012 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10014 if (strcmp (TARGET_OS
, "elf") != 0)
10015 record_alignment (seg
, 4);
10017 demand_empty_rest_of_line ();
10022 as_bad (_("Global pointers not supported; recompile -G 0"));
10023 demand_empty_rest_of_line ();
10032 mips_enable_auto_align ()
10043 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10044 mips_emit_delays (false);
10045 if (log_size
> 0 && auto_align
)
10046 mips_align (log_size
, 0, label
);
10047 mips_clear_insn_labels ();
10048 cons (1 << log_size
);
10052 s_float_cons (type
)
10057 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10059 mips_emit_delays (false);
10064 mips_align (3, 0, label
);
10066 mips_align (2, 0, label
);
10069 mips_clear_insn_labels ();
10074 /* Handle .globl. We need to override it because on Irix 5 you are
10077 where foo is an undefined symbol, to mean that foo should be
10078 considered to be the address of a function. */
10082 int x ATTRIBUTE_UNUSED
;
10089 name
= input_line_pointer
;
10090 c
= get_symbol_end ();
10091 symbolP
= symbol_find_or_make (name
);
10092 *input_line_pointer
= c
;
10093 SKIP_WHITESPACE ();
10095 /* On Irix 5, every global symbol that is not explicitly labelled as
10096 being a function is apparently labelled as being an object. */
10099 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10104 secname
= input_line_pointer
;
10105 c
= get_symbol_end ();
10106 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10108 as_bad (_("%s: no such section"), secname
);
10109 *input_line_pointer
= c
;
10111 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10112 flag
= BSF_FUNCTION
;
10115 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10117 S_SET_EXTERNAL (symbolP
);
10118 demand_empty_rest_of_line ();
10123 int x ATTRIBUTE_UNUSED
;
10128 opt
= input_line_pointer
;
10129 c
= get_symbol_end ();
10133 /* FIXME: What does this mean? */
10135 else if (strncmp (opt
, "pic", 3) == 0)
10139 i
= atoi (opt
+ 3);
10143 mips_pic
= SVR4_PIC
;
10145 as_bad (_(".option pic%d not supported"), i
);
10147 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10149 if (g_switch_seen
&& g_switch_value
!= 0)
10150 as_warn (_("-G may not be used with SVR4 PIC code"));
10151 g_switch_value
= 0;
10152 bfd_set_gp_size (stdoutput
, 0);
10156 as_warn (_("Unrecognized option \"%s\""), opt
);
10158 *input_line_pointer
= c
;
10159 demand_empty_rest_of_line ();
10162 /* This structure is used to hold a stack of .set values. */
10164 struct mips_option_stack
10166 struct mips_option_stack
*next
;
10167 struct mips_set_options options
;
10170 static struct mips_option_stack
*mips_opts_stack
;
10172 /* Handle the .set pseudo-op. */
10176 int x ATTRIBUTE_UNUSED
;
10178 char *name
= input_line_pointer
, ch
;
10180 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10181 input_line_pointer
++;
10182 ch
= *input_line_pointer
;
10183 *input_line_pointer
= '\0';
10185 if (strcmp (name
, "reorder") == 0)
10187 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10189 /* If we still have pending nops, we can discard them. The
10190 usual nop handling will insert any that are still
10192 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10193 * (mips_opts
.mips16
? 2 : 4));
10194 prev_nop_frag
= NULL
;
10196 mips_opts
.noreorder
= 0;
10198 else if (strcmp (name
, "noreorder") == 0)
10200 mips_emit_delays (true);
10201 mips_opts
.noreorder
= 1;
10202 mips_any_noreorder
= 1;
10204 else if (strcmp (name
, "at") == 0)
10206 mips_opts
.noat
= 0;
10208 else if (strcmp (name
, "noat") == 0)
10210 mips_opts
.noat
= 1;
10212 else if (strcmp (name
, "macro") == 0)
10214 mips_opts
.warn_about_macros
= 0;
10216 else if (strcmp (name
, "nomacro") == 0)
10218 if (mips_opts
.noreorder
== 0)
10219 as_bad (_("`noreorder' must be set before `nomacro'"));
10220 mips_opts
.warn_about_macros
= 1;
10222 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10224 mips_opts
.nomove
= 0;
10226 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10228 mips_opts
.nomove
= 1;
10230 else if (strcmp (name
, "bopt") == 0)
10232 mips_opts
.nobopt
= 0;
10234 else if (strcmp (name
, "nobopt") == 0)
10236 mips_opts
.nobopt
= 1;
10238 else if (strcmp (name
, "mips16") == 0
10239 || strcmp (name
, "MIPS-16") == 0)
10240 mips_opts
.mips16
= 1;
10241 else if (strcmp (name
, "nomips16") == 0
10242 || strcmp (name
, "noMIPS-16") == 0)
10243 mips_opts
.mips16
= 0;
10244 else if (strncmp (name
, "mips", 4) == 0)
10248 /* Permit the user to change the ISA on the fly. Needless to
10249 say, misuse can cause serious problems. */
10250 isa
= atoi (name
+ 4);
10253 case 0: mips_opts
.isa
= file_mips_isa
; break;
10254 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10255 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10256 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10257 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10258 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10259 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10260 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10261 default: as_bad (_("unknown ISA level")); break;
10264 else if (strcmp (name
, "autoextend") == 0)
10265 mips_opts
.noautoextend
= 0;
10266 else if (strcmp (name
, "noautoextend") == 0)
10267 mips_opts
.noautoextend
= 1;
10268 else if (strcmp (name
, "push") == 0)
10270 struct mips_option_stack
*s
;
10272 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10273 s
->next
= mips_opts_stack
;
10274 s
->options
= mips_opts
;
10275 mips_opts_stack
= s
;
10277 else if (strcmp (name
, "pop") == 0)
10279 struct mips_option_stack
*s
;
10281 s
= mips_opts_stack
;
10283 as_bad (_(".set pop with no .set push"));
10286 /* If we're changing the reorder mode we need to handle
10287 delay slots correctly. */
10288 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10289 mips_emit_delays (true);
10290 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10292 if (prev_nop_frag
!= NULL
)
10294 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10295 * (mips_opts
.mips16
? 2 : 4));
10296 prev_nop_frag
= NULL
;
10300 mips_opts
= s
->options
;
10301 mips_opts_stack
= s
->next
;
10307 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10309 *input_line_pointer
= ch
;
10310 demand_empty_rest_of_line ();
10313 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10314 .option pic2. It means to generate SVR4 PIC calls. */
10317 s_abicalls (ignore
)
10318 int ignore ATTRIBUTE_UNUSED
;
10320 mips_pic
= SVR4_PIC
;
10321 if (USE_GLOBAL_POINTER_OPT
)
10323 if (g_switch_seen
&& g_switch_value
!= 0)
10324 as_warn (_("-G may not be used with SVR4 PIC code"));
10325 g_switch_value
= 0;
10327 bfd_set_gp_size (stdoutput
, 0);
10328 demand_empty_rest_of_line ();
10331 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10332 PIC code. It sets the $gp register for the function based on the
10333 function address, which is in the register named in the argument.
10334 This uses a relocation against _gp_disp, which is handled specially
10335 by the linker. The result is:
10336 lui $gp,%hi(_gp_disp)
10337 addiu $gp,$gp,%lo(_gp_disp)
10338 addu $gp,$gp,.cpload argument
10339 The .cpload argument is normally $25 == $t9. */
10343 int ignore ATTRIBUTE_UNUSED
;
10348 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10349 if (mips_pic
!= SVR4_PIC
)
10355 /* .cpload should be a in .set noreorder section. */
10356 if (mips_opts
.noreorder
== 0)
10357 as_warn (_(".cpload not in noreorder section"));
10359 ex
.X_op
= O_symbol
;
10360 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10361 ex
.X_op_symbol
= NULL
;
10362 ex
.X_add_number
= 0;
10364 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10365 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10367 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10368 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10369 (int) BFD_RELOC_LO16
);
10371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10372 GP
, GP
, tc_get_register (0));
10374 demand_empty_rest_of_line ();
10377 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10378 offset from $sp. The offset is remembered, and after making a PIC
10379 call $gp is restored from that location. */
10382 s_cprestore (ignore
)
10383 int ignore ATTRIBUTE_UNUSED
;
10388 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10389 if (mips_pic
!= SVR4_PIC
)
10395 mips_cprestore_offset
= get_absolute_expression ();
10397 ex
.X_op
= O_constant
;
10398 ex
.X_add_symbol
= NULL
;
10399 ex
.X_op_symbol
= NULL
;
10400 ex
.X_add_number
= mips_cprestore_offset
;
10402 macro_build ((char *) NULL
, &icnt
, &ex
,
10403 ((bfd_arch_bits_per_address (stdoutput
) == 32
10404 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10406 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10408 demand_empty_rest_of_line ();
10411 /* Handle the .gpword pseudo-op. This is used when generating PIC
10412 code. It generates a 32 bit GP relative reloc. */
10416 int ignore ATTRIBUTE_UNUSED
;
10422 /* When not generating PIC code, this is treated as .word. */
10423 if (mips_pic
!= SVR4_PIC
)
10429 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10430 mips_emit_delays (true);
10432 mips_align (2, 0, label
);
10433 mips_clear_insn_labels ();
10437 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10439 as_bad (_("Unsupported use of .gpword"));
10440 ignore_rest_of_line ();
10444 md_number_to_chars (p
, (valueT
) 0, 4);
10445 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10446 BFD_RELOC_MIPS_GPREL32
);
10448 demand_empty_rest_of_line ();
10451 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10452 tables in SVR4 PIC code. */
10456 int ignore ATTRIBUTE_UNUSED
;
10461 /* This is ignored when not generating SVR4 PIC code. */
10462 if (mips_pic
!= SVR4_PIC
)
10468 /* Add $gp to the register named as an argument. */
10469 reg
= tc_get_register (0);
10470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10471 ((bfd_arch_bits_per_address (stdoutput
) == 32
10472 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10473 ? "addu" : "daddu"),
10474 "d,v,t", reg
, reg
, GP
);
10476 demand_empty_rest_of_line ();
10479 /* Handle the .insn pseudo-op. This marks instruction labels in
10480 mips16 mode. This permits the linker to handle them specially,
10481 such as generating jalx instructions when needed. We also make
10482 them odd for the duration of the assembly, in order to generate the
10483 right sort of code. We will make them even in the adjust_symtab
10484 routine, while leaving them marked. This is convenient for the
10485 debugger and the disassembler. The linker knows to make them odd
10490 int ignore ATTRIBUTE_UNUSED
;
10492 if (mips_opts
.mips16
)
10493 mips16_mark_labels ();
10495 demand_empty_rest_of_line ();
10498 /* Handle a .stabn directive. We need these in order to mark a label
10499 as being a mips16 text label correctly. Sometimes the compiler
10500 will emit a label, followed by a .stabn, and then switch sections.
10501 If the label and .stabn are in mips16 mode, then the label is
10502 really a mips16 text label. */
10508 if (type
== 'n' && mips_opts
.mips16
)
10509 mips16_mark_labels ();
10514 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10518 s_mips_weakext (ignore
)
10519 int ignore ATTRIBUTE_UNUSED
;
10526 name
= input_line_pointer
;
10527 c
= get_symbol_end ();
10528 symbolP
= symbol_find_or_make (name
);
10529 S_SET_WEAK (symbolP
);
10530 *input_line_pointer
= c
;
10532 SKIP_WHITESPACE ();
10534 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10536 if (S_IS_DEFINED (symbolP
))
10538 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10539 S_GET_NAME (symbolP
));
10540 ignore_rest_of_line ();
10544 if (*input_line_pointer
== ',')
10546 ++input_line_pointer
;
10547 SKIP_WHITESPACE ();
10551 if (exp
.X_op
!= O_symbol
)
10553 as_bad ("bad .weakext directive");
10554 ignore_rest_of_line();
10557 symbol_set_value_expression (symbolP
, &exp
);
10560 demand_empty_rest_of_line ();
10563 /* Parse a register string into a number. Called from the ECOFF code
10564 to parse .frame. The argument is non-zero if this is the frame
10565 register, so that we can record it in mips_frame_reg. */
10568 tc_get_register (frame
)
10573 SKIP_WHITESPACE ();
10574 if (*input_line_pointer
++ != '$')
10576 as_warn (_("expected `$'"));
10579 else if (isdigit ((unsigned char) *input_line_pointer
))
10581 reg
= get_absolute_expression ();
10582 if (reg
< 0 || reg
>= 32)
10584 as_warn (_("Bad register number"));
10590 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10592 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10594 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10596 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10600 as_warn (_("Unrecognized register name"));
10603 input_line_pointer
+= 2;
10606 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10611 md_section_align (seg
, addr
)
10615 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10618 /* We don't need to align ELF sections to the full alignment.
10619 However, Irix 5 may prefer that we align them at least to a 16
10620 byte boundary. We don't bother to align the sections if we are
10621 targeted for an embedded system. */
10622 if (strcmp (TARGET_OS
, "elf") == 0)
10628 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10631 /* Utility routine, called from above as well. If called while the
10632 input file is still being read, it's only an approximation. (For
10633 example, a symbol may later become defined which appeared to be
10634 undefined earlier.) */
10637 nopic_need_relax (sym
, before_relaxing
)
10639 int before_relaxing
;
10644 if (USE_GLOBAL_POINTER_OPT
)
10646 const char *symname
;
10649 /* Find out whether this symbol can be referenced off the GP
10650 register. It can be if it is smaller than the -G size or if
10651 it is in the .sdata or .sbss section. Certain symbols can
10652 not be referenced off the GP, although it appears as though
10654 symname
= S_GET_NAME (sym
);
10655 if (symname
!= (const char *) NULL
10656 && (strcmp (symname
, "eprol") == 0
10657 || strcmp (symname
, "etext") == 0
10658 || strcmp (symname
, "_gp") == 0
10659 || strcmp (symname
, "edata") == 0
10660 || strcmp (symname
, "_fbss") == 0
10661 || strcmp (symname
, "_fdata") == 0
10662 || strcmp (symname
, "_ftext") == 0
10663 || strcmp (symname
, "end") == 0
10664 || strcmp (symname
, "_gp_disp") == 0))
10666 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10668 #ifndef NO_ECOFF_DEBUGGING
10669 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10670 && (symbol_get_obj (sym
)->ecoff_extern_size
10671 <= g_switch_value
))
10673 /* We must defer this decision until after the whole
10674 file has been read, since there might be a .extern
10675 after the first use of this symbol. */
10676 || (before_relaxing
10677 #ifndef NO_ECOFF_DEBUGGING
10678 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10680 && S_GET_VALUE (sym
) == 0)
10681 || (S_GET_VALUE (sym
) != 0
10682 && S_GET_VALUE (sym
) <= g_switch_value
)))
10686 const char *segname
;
10688 segname
= segment_name (S_GET_SEGMENT (sym
));
10689 assert (strcmp (segname
, ".lit8") != 0
10690 && strcmp (segname
, ".lit4") != 0);
10691 change
= (strcmp (segname
, ".sdata") != 0
10692 && strcmp (segname
, ".sbss") != 0
10693 && strncmp (segname
, ".sdata.", 7) != 0
10694 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10699 /* We are not optimizing for the GP register. */
10703 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10704 extended opcode. SEC is the section the frag is in. */
10707 mips16_extended_frag (fragp
, sec
, stretch
)
10713 register const struct mips16_immed_operand
*op
;
10715 int mintiny
, maxtiny
;
10718 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10720 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10723 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10724 op
= mips16_immed_operands
;
10725 while (op
->type
!= type
)
10728 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10733 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10736 maxtiny
= 1 << op
->nbits
;
10741 maxtiny
= (1 << op
->nbits
) - 1;
10746 mintiny
= - (1 << (op
->nbits
- 1));
10747 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10750 /* We can't always call S_GET_VALUE here, because we don't want to
10751 lock in a particular frag address. */
10752 if (symbol_constant_p (fragp
->fr_symbol
))
10754 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10755 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10756 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10758 else if (symbol_equated_p (fragp
->fr_symbol
)
10759 && (symbol_constant_p
10760 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10764 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10765 val
= (S_GET_VALUE (eqsym
)
10766 + symbol_get_frag (eqsym
)->fr_address
10767 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10768 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10769 symsec
= S_GET_SEGMENT (eqsym
);
10778 /* We won't have the section when we are called from
10779 mips_relax_frag. However, we will always have been called
10780 from md_estimate_size_before_relax first. If this is a
10781 branch to a different section, we mark it as such. If SEC is
10782 NULL, and the frag is not marked, then it must be a branch to
10783 the same section. */
10786 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10793 fragp
->fr_subtype
=
10794 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10796 /* FIXME: We should support this, and let the linker
10797 catch branches and loads that are out of range. */
10798 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10799 _("unsupported PC relative reference to different section"));
10805 /* In this case, we know for sure that the symbol fragment is in
10806 the same section. If the fr_address of the symbol fragment
10807 is greater then the address of this fragment we want to add
10808 in STRETCH in order to get a better estimate of the address.
10809 This particularly matters because of the shift bits. */
10811 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10812 >= fragp
->fr_address
))
10816 /* Adjust stretch for any alignment frag. Note that if have
10817 been expanding the earlier code, the symbol may be
10818 defined in what appears to be an earlier frag. FIXME:
10819 This doesn't handle the fr_subtype field, which specifies
10820 a maximum number of bytes to skip when doing an
10823 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10826 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10829 stretch
= - ((- stretch
)
10830 & ~ ((1 << (int) f
->fr_offset
) - 1));
10832 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10841 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10843 /* The base address rules are complicated. The base address of
10844 a branch is the following instruction. The base address of a
10845 PC relative load or add is the instruction itself, but if it
10846 is in a delay slot (in which case it can not be extended) use
10847 the address of the instruction whose delay slot it is in. */
10848 if (type
== 'p' || type
== 'q')
10852 /* If we are currently assuming that this frag should be
10853 extended, then, the current address is two bytes
10855 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10858 /* Ignore the low bit in the target, since it will be set
10859 for a text label. */
10860 if ((val
& 1) != 0)
10863 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10865 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10868 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10870 /* Branch offsets have an implicit 0 in the lowest bit. */
10871 if (type
== 'p' || type
== 'q')
10874 /* If any of the shifted bits are set, we must use an extended
10875 opcode. If the address depends on the size of this
10876 instruction, this can lead to a loop, so we arrange to always
10877 use an extended opcode. We only check this when we are in
10878 the main relaxation loop, when SEC is NULL. */
10879 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10881 fragp
->fr_subtype
=
10882 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10886 /* If we are about to mark a frag as extended because the value
10887 is precisely maxtiny + 1, then there is a chance of an
10888 infinite loop as in the following code:
10893 In this case when the la is extended, foo is 0x3fc bytes
10894 away, so the la can be shrunk, but then foo is 0x400 away, so
10895 the la must be extended. To avoid this loop, we mark the
10896 frag as extended if it was small, and is about to become
10897 extended with a value of maxtiny + 1. */
10898 if (val
== ((maxtiny
+ 1) << op
->shift
)
10899 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10902 fragp
->fr_subtype
=
10903 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10907 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10908 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10910 if ((val
& ((1 << op
->shift
) - 1)) != 0
10911 || val
< (mintiny
<< op
->shift
)
10912 || val
> (maxtiny
<< op
->shift
))
10918 /* Estimate the size of a frag before relaxing. Unless this is the
10919 mips16, we are not really relaxing here, and the final size is
10920 encoded in the subtype information. For the mips16, we have to
10921 decide whether we are using an extended opcode or not. */
10925 md_estimate_size_before_relax (fragp
, segtype
)
10930 boolean linkonce
= false;
10932 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10934 if (mips16_extended_frag (fragp
, segtype
, 0))
10936 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10941 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10946 if (mips_pic
== NO_PIC
)
10948 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10950 else if (mips_pic
== SVR4_PIC
)
10955 sym
= fragp
->fr_symbol
;
10957 /* Handle the case of a symbol equated to another symbol. */
10958 while (symbol_equated_p (sym
)
10959 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10963 /* It's possible to get a loop here in a badly written
10965 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10971 symsec
= S_GET_SEGMENT (sym
);
10973 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
10974 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
10976 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
10980 /* The GNU toolchain uses an extension for ELF: a section
10981 beginning with the magic string .gnu.linkonce is a linkonce
10983 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
10984 sizeof ".gnu.linkonce" - 1) == 0)
10988 /* This must duplicate the test in adjust_reloc_syms. */
10989 change
= (symsec
!= &bfd_und_section
10990 && symsec
!= &bfd_abs_section
10991 && ! bfd_is_com_section (symsec
)
10994 /* A weak symbol is treated as external. */
10995 && ! S_IS_WEAK (sym
)
11004 /* Record the offset to the first reloc in the fr_opcode field.
11005 This lets md_convert_frag and tc_gen_reloc know that the code
11006 must be expanded. */
11007 fragp
->fr_opcode
= (fragp
->fr_literal
11009 - RELAX_OLD (fragp
->fr_subtype
)
11010 + RELAX_RELOC1 (fragp
->fr_subtype
));
11011 /* FIXME: This really needs as_warn_where. */
11012 if (RELAX_WARN (fragp
->fr_subtype
))
11013 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11019 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11022 /* This is called to see whether a reloc against a defined symbol
11023 should be converted into a reloc against a section. Don't adjust
11024 MIPS16 jump relocations, so we don't have to worry about the format
11025 of the offset in the .o file. Don't adjust relocations against
11026 mips16 symbols, so that the linker can find them if it needs to set
11030 mips_fix_adjustable (fixp
)
11033 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11035 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11036 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11038 if (fixp
->fx_addsy
== NULL
)
11041 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11042 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11043 && fixp
->fx_subsy
== NULL
)
11049 /* Translate internal representation of relocation info to BFD target
11053 tc_gen_reloc (section
, fixp
)
11054 asection
*section ATTRIBUTE_UNUSED
;
11057 static arelent
*retval
[4];
11059 bfd_reloc_code_real_type code
;
11061 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11064 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11065 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11066 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11068 if (mips_pic
== EMBEDDED_PIC
11069 && SWITCH_TABLE (fixp
))
11071 /* For a switch table entry we use a special reloc. The addend
11072 is actually the difference between the reloc address and the
11074 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11075 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11076 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11077 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11079 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11080 reloc
->addend
= fixp
->fx_addnumber
;
11081 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11083 /* We use a special addend for an internal RELLO reloc. */
11084 if (symbol_section_p (fixp
->fx_addsy
))
11085 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11087 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11089 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11091 assert (fixp
->fx_next
!= NULL
11092 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11093 /* We use a special addend for an internal RELHI reloc. The
11094 reloc is relative to the RELLO; adjust the addend
11096 if (symbol_section_p (fixp
->fx_addsy
))
11097 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11098 + fixp
->fx_next
->fx_where
11099 - S_GET_VALUE (fixp
->fx_subsy
));
11101 reloc
->addend
= (fixp
->fx_addnumber
11102 + fixp
->fx_next
->fx_frag
->fr_address
11103 + fixp
->fx_next
->fx_where
);
11107 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11108 /* A gruesome hack which is a result of the gruesome gas reloc
11110 reloc
->addend
= reloc
->address
;
11112 reloc
->addend
= -reloc
->address
;
11115 /* If this is a variant frag, we may need to adjust the existing
11116 reloc and generate a new one. */
11117 if (fixp
->fx_frag
->fr_opcode
!= NULL
11118 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11119 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11120 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11121 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11122 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11123 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11124 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11128 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11130 /* If this is not the last reloc in this frag, then we have two
11131 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11132 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11133 the second one handle all of them. */
11134 if (fixp
->fx_next
!= NULL
11135 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11137 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11138 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11139 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11140 && (fixp
->fx_next
->fx_r_type
11141 == BFD_RELOC_MIPS_GOT_LO16
))
11142 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11143 && (fixp
->fx_next
->fx_r_type
11144 == BFD_RELOC_MIPS_CALL_LO16
)));
11149 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11150 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11151 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11153 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11154 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11155 reloc2
->address
= (reloc
->address
11156 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11157 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11158 reloc2
->addend
= fixp
->fx_addnumber
;
11159 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11160 assert (reloc2
->howto
!= NULL
);
11162 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11166 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11169 reloc3
->address
+= 4;
11172 if (mips_pic
== NO_PIC
)
11174 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11175 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11177 else if (mips_pic
== SVR4_PIC
)
11179 switch (fixp
->fx_r_type
)
11183 case BFD_RELOC_MIPS_GOT16
:
11185 case BFD_RELOC_MIPS_CALL16
:
11186 case BFD_RELOC_MIPS_GOT_LO16
:
11187 case BFD_RELOC_MIPS_CALL_LO16
:
11188 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11196 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11197 to be used in the relocation's section offset. */
11198 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11200 reloc
->address
= reloc
->addend
;
11204 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11205 fixup_segment converted a non-PC relative reloc into a PC
11206 relative reloc. In such a case, we need to convert the reloc
11208 code
= fixp
->fx_r_type
;
11209 if (fixp
->fx_pcrel
)
11214 code
= BFD_RELOC_8_PCREL
;
11217 code
= BFD_RELOC_16_PCREL
;
11220 code
= BFD_RELOC_32_PCREL
;
11223 code
= BFD_RELOC_64_PCREL
;
11225 case BFD_RELOC_8_PCREL
:
11226 case BFD_RELOC_16_PCREL
:
11227 case BFD_RELOC_32_PCREL
:
11228 case BFD_RELOC_64_PCREL
:
11229 case BFD_RELOC_16_PCREL_S2
:
11230 case BFD_RELOC_PCREL_HI16_S
:
11231 case BFD_RELOC_PCREL_LO16
:
11234 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11235 _("Cannot make %s relocation PC relative"),
11236 bfd_get_reloc_code_name (code
));
11240 /* To support a PC relative reloc when generating embedded PIC code
11241 for ECOFF, we use a Cygnus extension. We check for that here to
11242 make sure that we don't let such a reloc escape normally. */
11243 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11244 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11245 && code
== BFD_RELOC_16_PCREL_S2
11246 && mips_pic
!= EMBEDDED_PIC
)
11247 reloc
->howto
= NULL
;
11249 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11251 if (reloc
->howto
== NULL
)
11253 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11254 _("Can not represent %s relocation in this object file format"),
11255 bfd_get_reloc_code_name (code
));
11262 /* Relax a machine dependent frag. This returns the amount by which
11263 the current size of the frag should change. */
11266 mips_relax_frag (fragp
, stretch
)
11270 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11273 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11275 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11277 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11282 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11284 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11291 /* Convert a machine dependent frag. */
11294 md_convert_frag (abfd
, asec
, fragp
)
11295 bfd
*abfd ATTRIBUTE_UNUSED
;
11302 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11305 register const struct mips16_immed_operand
*op
;
11306 boolean small
, ext
;
11309 unsigned long insn
;
11310 boolean use_extend
;
11311 unsigned short extend
;
11313 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11314 op
= mips16_immed_operands
;
11315 while (op
->type
!= type
)
11318 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11329 resolve_symbol_value (fragp
->fr_symbol
, 1);
11330 val
= S_GET_VALUE (fragp
->fr_symbol
);
11335 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11337 /* The rules for the base address of a PC relative reloc are
11338 complicated; see mips16_extended_frag. */
11339 if (type
== 'p' || type
== 'q')
11344 /* Ignore the low bit in the target, since it will be
11345 set for a text label. */
11346 if ((val
& 1) != 0)
11349 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11351 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11354 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11357 /* Make sure the section winds up with the alignment we have
11360 record_alignment (asec
, op
->shift
);
11364 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11365 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11366 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11367 _("extended instruction in delay slot"));
11369 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11371 if (target_big_endian
)
11372 insn
= bfd_getb16 (buf
);
11374 insn
= bfd_getl16 (buf
);
11376 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11377 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11378 small
, ext
, &insn
, &use_extend
, &extend
);
11382 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11383 fragp
->fr_fix
+= 2;
11387 md_number_to_chars (buf
, insn
, 2);
11388 fragp
->fr_fix
+= 2;
11393 if (fragp
->fr_opcode
== NULL
)
11396 old
= RELAX_OLD (fragp
->fr_subtype
);
11397 new = RELAX_NEW (fragp
->fr_subtype
);
11398 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11401 memcpy (fixptr
- old
, fixptr
, new);
11403 fragp
->fr_fix
+= new - old
;
11409 /* This function is called after the relocs have been generated.
11410 We've been storing mips16 text labels as odd. Here we convert them
11411 back to even for the convenience of the debugger. */
11414 mips_frob_file_after_relocs ()
11417 unsigned int count
, i
;
11419 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11422 syms
= bfd_get_outsymbols (stdoutput
);
11423 count
= bfd_get_symcount (stdoutput
);
11424 for (i
= 0; i
< count
; i
++, syms
++)
11426 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11427 && ((*syms
)->value
& 1) != 0)
11429 (*syms
)->value
&= ~1;
11430 /* If the symbol has an odd size, it was probably computed
11431 incorrectly, so adjust that as well. */
11432 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11433 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11440 /* This function is called whenever a label is defined. It is used
11441 when handling branch delays; if a branch has a label, we assume we
11442 can not move it. */
11445 mips_define_label (sym
)
11448 struct insn_label_list
*l
;
11450 if (free_insn_labels
== NULL
)
11451 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11454 l
= free_insn_labels
;
11455 free_insn_labels
= l
->next
;
11459 l
->next
= insn_labels
;
11463 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11465 /* Some special processing for a MIPS ELF file. */
11468 mips_elf_final_processing ()
11470 /* Write out the register information. */
11475 s
.ri_gprmask
= mips_gprmask
;
11476 s
.ri_cprmask
[0] = mips_cprmask
[0];
11477 s
.ri_cprmask
[1] = mips_cprmask
[1];
11478 s
.ri_cprmask
[2] = mips_cprmask
[2];
11479 s
.ri_cprmask
[3] = mips_cprmask
[3];
11480 /* The gp_value field is set by the MIPS ELF backend. */
11482 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11483 ((Elf32_External_RegInfo
*)
11484 mips_regmask_frag
));
11488 Elf64_Internal_RegInfo s
;
11490 s
.ri_gprmask
= mips_gprmask
;
11492 s
.ri_cprmask
[0] = mips_cprmask
[0];
11493 s
.ri_cprmask
[1] = mips_cprmask
[1];
11494 s
.ri_cprmask
[2] = mips_cprmask
[2];
11495 s
.ri_cprmask
[3] = mips_cprmask
[3];
11496 /* The gp_value field is set by the MIPS ELF backend. */
11498 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11499 ((Elf64_External_RegInfo
*)
11500 mips_regmask_frag
));
11503 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11504 sort of BFD interface for this. */
11505 if (mips_any_noreorder
)
11506 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11507 if (mips_pic
!= NO_PIC
)
11508 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11510 /* Set the MIPS ELF ABI flags. */
11511 if (mips_abi_string
== 0)
11513 else if (strcmp (mips_abi_string
,"32") == 0)
11514 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11515 else if (strcmp (mips_abi_string
,"o64") == 0)
11516 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11517 else if (strcmp (mips_abi_string
,"eabi") == 0)
11520 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11522 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11525 if (mips_32bitmode
)
11526 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11529 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11531 typedef struct proc
11534 unsigned long reg_mask
;
11535 unsigned long reg_offset
;
11536 unsigned long fpreg_mask
;
11537 unsigned long fpreg_offset
;
11538 unsigned long frame_offset
;
11539 unsigned long frame_reg
;
11540 unsigned long pc_reg
;
11544 static procS cur_proc
;
11545 static procS
*cur_proc_ptr
;
11546 static int numprocs
;
11548 /* When we align code in the .text section of mips16, use the correct two
11549 byte nop pattern of 0x6500 (move $0,$0) */
11552 mips_do_align (n
, fill
, len
, max
)
11555 int len ATTRIBUTE_UNUSED
;
11559 && subseg_text_p (now_seg
)
11561 && mips_opts
.mips16
)
11563 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11564 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11566 frag_align (1, 0, 0);
11568 if (target_big_endian
)
11569 frag_align_pattern (n
, be_nop
, 2, max
);
11571 frag_align_pattern (n
, le_nop
, 2, max
);
11586 /* check for premature end, nesting errors, etc */
11588 as_warn (_("missing `.end' at end of assembly"));
11597 if (*input_line_pointer
== '-')
11599 ++input_line_pointer
;
11602 if (!isdigit ((unsigned char) *input_line_pointer
))
11603 as_bad (_("Expected simple number."));
11604 if (input_line_pointer
[0] == '0')
11606 if (input_line_pointer
[1] == 'x')
11608 input_line_pointer
+= 2;
11609 while (isxdigit ((unsigned char) *input_line_pointer
))
11612 val
|= hex_value (*input_line_pointer
++);
11614 return negative
? -val
: val
;
11618 ++input_line_pointer
;
11619 while (isdigit ((unsigned char) *input_line_pointer
))
11622 val
|= *input_line_pointer
++ - '0';
11624 return negative
? -val
: val
;
11627 if (!isdigit ((unsigned char) *input_line_pointer
))
11629 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11630 *input_line_pointer
, *input_line_pointer
);
11631 as_warn (_("Invalid number"));
11634 while (isdigit ((unsigned char) *input_line_pointer
))
11637 val
+= *input_line_pointer
++ - '0';
11639 return negative
? -val
: val
;
11642 /* The .file directive; just like the usual .file directive, but there
11643 is an initial number which is the ECOFF file index. */
11647 int x ATTRIBUTE_UNUSED
;
11651 line
= get_number ();
11655 /* The .end directive. */
11659 int x ATTRIBUTE_UNUSED
;
11664 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11667 demand_empty_rest_of_line ();
11672 #ifdef BFD_ASSEMBLER
11673 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11678 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11685 as_warn (_(".end not in text section"));
11689 as_warn (_(".end directive without a preceding .ent directive."));
11690 demand_empty_rest_of_line ();
11696 assert (S_GET_NAME (p
));
11697 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11698 as_warn (_(".end symbol does not match .ent symbol."));
11701 as_warn (_(".end directive missing or unknown symbol"));
11703 #ifdef MIPS_STABS_ELF
11705 segT saved_seg
= now_seg
;
11706 subsegT saved_subseg
= now_subseg
;
11707 fragS
*saved_frag
= frag_now
;
11713 dot
= frag_now_fix ();
11715 #ifdef md_flush_pending_output
11716 md_flush_pending_output ();
11720 subseg_set (pdr_seg
, 0);
11722 /* Write the symbol */
11723 exp
.X_op
= O_symbol
;
11724 exp
.X_add_symbol
= p
;
11725 exp
.X_add_number
= 0;
11726 emit_expr (&exp
, 4);
11728 fragp
= frag_more (7*4);
11730 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11731 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11732 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11733 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11734 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11735 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11736 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11738 subseg_set (saved_seg
, saved_subseg
);
11742 cur_proc_ptr
= NULL
;
11745 /* The .aent and .ent directives. */
11755 symbolP
= get_symbol ();
11756 if (*input_line_pointer
== ',')
11757 input_line_pointer
++;
11758 SKIP_WHITESPACE ();
11759 if (isdigit ((unsigned char) *input_line_pointer
)
11760 || *input_line_pointer
== '-')
11761 number
= get_number ();
11763 #ifdef BFD_ASSEMBLER
11764 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11769 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11776 as_warn (_(".ent or .aent not in text section."));
11778 if (!aent
&& cur_proc_ptr
)
11779 as_warn (_("missing `.end'"));
11783 cur_proc_ptr
= &cur_proc
;
11784 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11786 cur_proc_ptr
->isym
= symbolP
;
11788 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11793 demand_empty_rest_of_line ();
11796 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11797 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11798 s_mips_frame is used so that we can set the PDR information correctly.
11799 We can't use the ecoff routines because they make reference to the ecoff
11800 symbol table (in the mdebug section). */
11803 s_mips_frame (ignore
)
11806 #ifdef MIPS_STABS_ELF
11810 if (cur_proc_ptr
== (procS
*) NULL
)
11812 as_warn (_(".frame outside of .ent"));
11813 demand_empty_rest_of_line ();
11817 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11819 SKIP_WHITESPACE ();
11820 if (*input_line_pointer
++ != ','
11821 || get_absolute_expression_and_terminator (&val
) != ',')
11823 as_warn (_("Bad .frame directive"));
11824 --input_line_pointer
;
11825 demand_empty_rest_of_line ();
11829 cur_proc_ptr
->frame_offset
= val
;
11830 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11832 demand_empty_rest_of_line ();
11835 #endif /* MIPS_STABS_ELF */
11838 /* The .fmask and .mask directives. If the mdebug section is present
11839 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11840 embedded targets, s_mips_mask is used so that we can set the PDR
11841 information correctly. We can't use the ecoff routines because they
11842 make reference to the ecoff symbol table (in the mdebug section). */
11845 s_mips_mask (reg_type
)
11848 #ifdef MIPS_STABS_ELF
11851 if (cur_proc_ptr
== (procS
*) NULL
)
11853 as_warn (_(".mask/.fmask outside of .ent"));
11854 demand_empty_rest_of_line ();
11858 if (get_absolute_expression_and_terminator (&mask
) != ',')
11860 as_warn (_("Bad .mask/.fmask directive"));
11861 --input_line_pointer
;
11862 demand_empty_rest_of_line ();
11866 off
= get_absolute_expression ();
11868 if (reg_type
== 'F')
11870 cur_proc_ptr
->fpreg_mask
= mask
;
11871 cur_proc_ptr
->fpreg_offset
= off
;
11875 cur_proc_ptr
->reg_mask
= mask
;
11876 cur_proc_ptr
->reg_offset
= off
;
11879 demand_empty_rest_of_line ();
11881 s_ignore (reg_type
);
11882 #endif /* MIPS_STABS_ELF */
11885 /* The .loc directive. */
11896 assert (now_seg
== text_section
);
11898 lineno
= get_number ();
11899 addroff
= frag_now_fix ();
11901 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11902 S_SET_TYPE (symbolP
, N_SLINE
);
11903 S_SET_OTHER (symbolP
, 0);
11904 S_SET_DESC (symbolP
, lineno
);
11905 symbolP
->sy_segment
= now_seg
;
11909 /* CPU name/ISA/number mapping table.
11911 Entries are grouped by type. The first matching CPU or ISA entry
11912 gets chosen by CPU or ISA, so it should be the 'canonical' name
11913 for that type. Entries after that within the type are sorted
11916 Case is ignored in comparison, so put the canonical entry in the
11917 appropriate case but everything else in lower case to ease eye pain. */
11918 static const struct mips_cpu_info mips_cpu_info_table
[] =
11921 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
11922 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
11925 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
11928 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
11931 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
11934 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
11935 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
11938 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
11939 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
11942 /* XXX for now, MIPS64 -> MIPS3 because of history */
11943 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
11946 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
11948 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
11949 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
11952 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
11953 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
11954 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
11955 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
11958 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
11959 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
11960 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
11961 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
11964 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
11965 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
11966 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
11969 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
11970 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
11971 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
11972 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
11975 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
11976 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
11979 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
11980 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
11983 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
11984 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
11985 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
11986 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
11989 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
11990 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
11993 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
11994 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
11995 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
11996 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
11999 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12000 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12001 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12002 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12005 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12006 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12007 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12008 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12011 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12012 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12013 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12014 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12017 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12018 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12019 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12020 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12023 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12024 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12025 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12026 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12029 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12030 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12031 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12032 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12033 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12034 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12035 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12036 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12037 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12038 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12039 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12040 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12042 /* MIPS32 4K CPU */
12043 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12044 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12045 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12046 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12047 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12048 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12049 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12052 { NULL
, 0, 0, 0, },
12055 static const struct mips_cpu_info
*
12056 mips_cpu_info_from_name (name
)
12061 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12062 if (strcasecmp(name
, mips_cpu_info_table
[i
].name
) == 0)
12063 return (&mips_cpu_info_table
[i
]);
12068 static const struct mips_cpu_info
*
12069 mips_cpu_info_from_isa (isa
)
12074 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12075 if (mips_cpu_info_table
[i
].is_isa
12076 && isa
== mips_cpu_info_table
[i
].isa
)
12077 return (&mips_cpu_info_table
[i
]);
12082 static const struct mips_cpu_info
*
12083 mips_cpu_info_from_cpu (cpu
)
12088 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12089 if (!mips_cpu_info_table
[i
].is_isa
12090 && cpu
== mips_cpu_info_table
[i
].cpu
)
12091 return (&mips_cpu_info_table
[i
]);