1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2020 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static htab_t op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static htab_t mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static htab_t micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* The maximum number of LABELS detect for the same address. */
816 #define MAX_LABELS_SAME 10
818 /* Arrays of operands for each instruction. */
819 #define MAX_OPERANDS 6
820 struct mips_operand_array
822 const struct mips_operand
*operand
[MAX_OPERANDS
];
824 static struct mips_operand_array
*mips_operands
;
825 static struct mips_operand_array
*mips16_operands
;
826 static struct mips_operand_array
*micromips_operands
;
828 /* Nop instructions used by emit_nop. */
829 static struct mips_cl_insn nop_insn
;
830 static struct mips_cl_insn mips16_nop_insn
;
831 static struct mips_cl_insn micromips_nop16_insn
;
832 static struct mips_cl_insn micromips_nop32_insn
;
834 /* Sync instructions used by insert sync. */
835 static struct mips_cl_insn sync_insn
;
837 /* The appropriate nop for the current mode. */
838 #define NOP_INSN (mips_opts.mips16 \
840 : (mips_opts.micromips \
841 ? (mips_opts.insn32 \
842 ? µmips_nop32_insn \
843 : µmips_nop16_insn) \
846 /* The size of NOP_INSN in bytes. */
847 #define NOP_INSN_SIZE ((mips_opts.mips16 \
848 || (mips_opts.micromips && !mips_opts.insn32)) \
851 /* If this is set, it points to a frag holding nop instructions which
852 were inserted before the start of a noreorder section. If those
853 nops turn out to be unnecessary, the size of the frag can be
855 static fragS
*prev_nop_frag
;
857 /* The number of nop instructions we created in prev_nop_frag. */
858 static int prev_nop_frag_holds
;
860 /* The number of nop instructions that we know we need in
862 static int prev_nop_frag_required
;
864 /* The number of instructions we've seen since prev_nop_frag. */
865 static int prev_nop_frag_since
;
867 /* Relocations against symbols are sometimes done in two parts, with a HI
868 relocation and a LO relocation. Each relocation has only 16 bits of
869 space to store an addend. This means that in order for the linker to
870 handle carries correctly, it must be able to locate both the HI and
871 the LO relocation. This means that the relocations must appear in
872 order in the relocation table.
874 In order to implement this, we keep track of each unmatched HI
875 relocation. We then sort them so that they immediately precede the
876 corresponding LO relocation. */
881 struct mips_hi_fixup
*next
;
884 /* The section this fixup is in. */
888 /* The list of unmatched HI relocs. */
890 static struct mips_hi_fixup
*mips_hi_fixup_list
;
892 /* Map mips16 register numbers to normal MIPS register numbers. */
894 static const unsigned int mips16_to_32_reg_map
[] =
896 16, 17, 2, 3, 4, 5, 6, 7
899 /* Map microMIPS register numbers to normal MIPS register numbers. */
901 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
903 /* The microMIPS registers with type h. */
904 static const unsigned int micromips_to_32_reg_h_map1
[] =
906 5, 5, 6, 4, 4, 4, 4, 4
908 static const unsigned int micromips_to_32_reg_h_map2
[] =
910 6, 7, 7, 21, 22, 5, 6, 7
913 /* The microMIPS registers with type m. */
914 static const unsigned int micromips_to_32_reg_m_map
[] =
916 0, 17, 2, 3, 16, 18, 19, 20
919 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
921 /* Classifies the kind of instructions we're interested in when
922 implementing -mfix-vr4120. */
923 enum fix_vr4120_class
931 NUM_FIX_VR4120_CLASSES
934 /* ...likewise -mfix-loongson2f-jump. */
935 static bfd_boolean mips_fix_loongson2f_jump
;
937 /* ...likewise -mfix-loongson2f-nop. */
938 static bfd_boolean mips_fix_loongson2f_nop
;
940 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
941 static bfd_boolean mips_fix_loongson2f
;
943 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
944 there must be at least one other instruction between an instruction
945 of type X and an instruction of type Y. */
946 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
948 /* True if -mfix-vr4120 is in force. */
949 static int mips_fix_vr4120
;
951 /* ...likewise -mfix-vr4130. */
952 static int mips_fix_vr4130
;
954 /* ...likewise -mfix-24k. */
955 static int mips_fix_24k
;
957 /* ...likewise -mfix-rm7000 */
958 static int mips_fix_rm7000
;
960 /* ...likewise -mfix-cn63xxp1 */
961 static bfd_boolean mips_fix_cn63xxp1
;
963 /* ...likewise -mfix-r5900 */
964 static bfd_boolean mips_fix_r5900
;
965 static bfd_boolean mips_fix_r5900_explicit
;
967 /* ...likewise -mfix-loongson3-llsc. */
968 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
970 /* We don't relax branches by default, since this causes us to expand
971 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
972 fail to compute the offset before expanding the macro to the most
973 efficient expansion. */
975 static int mips_relax_branch
;
977 /* TRUE if checks are suppressed for invalid branches between ISA modes.
978 Needed for broken assembly produced by some GCC versions and some
979 sloppy code out there, where branches to data labels are present. */
980 static bfd_boolean mips_ignore_branch_isa
;
982 /* The expansion of many macros depends on the type of symbol that
983 they refer to. For example, when generating position-dependent code,
984 a macro that refers to a symbol may have two different expansions,
985 one which uses GP-relative addresses and one which uses absolute
986 addresses. When generating SVR4-style PIC, a macro may have
987 different expansions for local and global symbols.
989 We handle these situations by generating both sequences and putting
990 them in variant frags. In position-dependent code, the first sequence
991 will be the GP-relative one and the second sequence will be the
992 absolute one. In SVR4 PIC, the first sequence will be for global
993 symbols and the second will be for local symbols.
995 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
996 SECOND are the lengths of the two sequences in bytes. These fields
997 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
998 the subtype has the following flags:
1001 Set if generating PIC code.
1004 Set if it has been decided that we should use the second
1005 sequence instead of the first.
1008 Set in the first variant frag if the macro's second implementation
1009 is longer than its first. This refers to the macro as a whole,
1010 not an individual relaxation.
1013 Set in the first variant frag if the macro appeared in a .set nomacro
1014 block and if one alternative requires a warning but the other does not.
1017 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1020 RELAX_DELAY_SLOT_16BIT
1021 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1024 RELAX_DELAY_SLOT_SIZE_FIRST
1025 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1026 the macro is of the wrong size for the branch delay slot.
1028 RELAX_DELAY_SLOT_SIZE_SECOND
1029 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1030 the macro is of the wrong size for the branch delay slot.
1032 The frag's "opcode" points to the first fixup for relaxable code.
1034 Relaxable macros are generated using a sequence such as:
1036 relax_start (SYMBOL);
1037 ... generate first expansion ...
1039 ... generate second expansion ...
1042 The code and fixups for the unwanted alternative are discarded
1043 by md_convert_frag. */
1044 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1045 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1047 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1048 #define RELAX_SECOND(X) ((X) & 0xff)
1049 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1050 #define RELAX_USE_SECOND 0x20000
1051 #define RELAX_SECOND_LONGER 0x40000
1052 #define RELAX_NOMACRO 0x80000
1053 #define RELAX_DELAY_SLOT 0x100000
1054 #define RELAX_DELAY_SLOT_16BIT 0x200000
1055 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1056 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1058 /* Branch without likely bit. If label is out of range, we turn:
1060 beq reg1, reg2, label
1070 with the following opcode replacements:
1077 bltzal <-> bgezal (with jal label instead of j label)
1079 Even though keeping the delay slot instruction in the delay slot of
1080 the branch would be more efficient, it would be very tricky to do
1081 correctly, because we'd have to introduce a variable frag *after*
1082 the delay slot instruction, and expand that instead. Let's do it
1083 the easy way for now, even if the branch-not-taken case now costs
1084 one additional instruction. Out-of-range branches are not supposed
1085 to be common, anyway.
1087 Branch likely. If label is out of range, we turn:
1089 beql reg1, reg2, label
1090 delay slot (annulled if branch not taken)
1099 delay slot (executed only if branch taken)
1102 It would be possible to generate a shorter sequence by losing the
1103 likely bit, generating something like:
1108 delay slot (executed only if branch taken)
1120 bltzall -> bgezal (with jal label instead of j label)
1121 bgezall -> bltzal (ditto)
1124 but it's not clear that it would actually improve performance. */
1125 #define RELAX_BRANCH_ENCODE(at, pic, \
1126 uncond, likely, link, toofar) \
1127 ((relax_substateT) \
1130 | ((pic) ? 0x20 : 0) \
1131 | ((toofar) ? 0x40 : 0) \
1132 | ((link) ? 0x80 : 0) \
1133 | ((likely) ? 0x100 : 0) \
1134 | ((uncond) ? 0x200 : 0)))
1135 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1136 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1137 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1138 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1139 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1140 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1141 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1143 /* For mips16 code, we use an entirely different form of relaxation.
1144 mips16 supports two versions of most instructions which take
1145 immediate values: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. Since branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both mips16 and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use the high bit of the subtype field to distinguish these cases.
1154 The information we store for this type of relaxation is the
1155 argument code found in the opcode file for this relocation, whether
1156 the user explicitly requested a small or extended form, and whether
1157 the relocation is in a jump or jal delay slot. That tells us the
1158 size of the value, and how it should be stored. We also store
1159 whether the fragment is considered to be extended or not. We also
1160 store whether this is known to be a branch to a different section,
1161 whether we have tried to relax this frag yet, and whether we have
1162 ever extended a PC relative fragment because of a shift count. */
1163 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1168 | ((e2) ? 0x100 : 0) \
1169 | ((pic) ? 0x200 : 0) \
1170 | ((sym32) ? 0x400 : 0) \
1171 | ((nomacro) ? 0x800 : 0) \
1172 | ((small) ? 0x1000 : 0) \
1173 | ((ext) ? 0x2000 : 0) \
1174 | ((dslot) ? 0x4000 : 0) \
1175 | ((jal_dslot) ? 0x8000 : 0))
1177 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1178 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1180 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1181 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1182 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1183 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1184 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1185 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1186 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1188 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1189 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1190 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1191 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1192 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1193 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1194 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1195 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1196 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1198 /* For microMIPS code, we use relaxation similar to one we use for
1199 MIPS16 code. Some instructions that take immediate values support
1200 two encodings: a small one which takes some small value, and a
1201 larger one which takes a 16 bit value. As some branches also follow
1202 this pattern, relaxing these values is required.
1204 We can assemble both microMIPS and normal MIPS code in a single
1205 object. Therefore, we need to support this type of relaxation at
1206 the same time that we support the relaxation described above. We
1207 use one of the high bits of the subtype field to distinguish these
1210 The information we store for this type of relaxation is the argument
1211 code found in the opcode file for this relocation, the register
1212 selected as the assembler temporary, whether in the 32-bit
1213 instruction mode, whether the branch is unconditional, whether it is
1214 compact, whether there is no delay-slot instruction available to fill
1215 in, whether it stores the link address implicitly in $ra, whether
1216 relaxation of out-of-range 32-bit branches to a sequence of
1217 instructions is enabled, and whether the displacement of a branch is
1218 too large to fit as an immediate argument of a 16-bit and a 32-bit
1219 branch, respectively. */
1220 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1221 uncond, compact, link, nods, \
1222 relax32, toofar16, toofar32) \
1225 | (((at) & 0x1f) << 8) \
1226 | ((insn32) ? 0x2000 : 0) \
1227 | ((pic) ? 0x4000 : 0) \
1228 | ((uncond) ? 0x8000 : 0) \
1229 | ((compact) ? 0x10000 : 0) \
1230 | ((link) ? 0x20000 : 0) \
1231 | ((nods) ? 0x40000 : 0) \
1232 | ((relax32) ? 0x80000 : 0) \
1233 | ((toofar16) ? 0x100000 : 0) \
1234 | ((toofar32) ? 0x200000 : 0))
1235 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1236 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1237 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1238 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1239 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1240 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1241 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1242 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1243 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1244 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1246 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1247 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1248 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1249 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1250 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1251 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1253 /* Sign-extend 16-bit value X. */
1254 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1256 /* Is the given value a sign-extended 32-bit value? */
1257 #define IS_SEXT_32BIT_NUM(x) \
1258 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1259 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1261 /* Is the given value a sign-extended 16-bit value? */
1262 #define IS_SEXT_16BIT_NUM(x) \
1263 (((x) &~ (offsetT) 0x7fff) == 0 \
1264 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1266 /* Is the given value a sign-extended 12-bit value? */
1267 #define IS_SEXT_12BIT_NUM(x) \
1268 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1270 /* Is the given value a sign-extended 9-bit value? */
1271 #define IS_SEXT_9BIT_NUM(x) \
1272 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1274 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1275 #define IS_ZEXT_32BIT_NUM(x) \
1276 (((x) &~ (offsetT) 0xffffffff) == 0 \
1277 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1279 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1281 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1282 (((STRUCT) >> (SHIFT)) & (MASK))
1284 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1285 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1287 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1288 : EXTRACT_BITS ((INSN).insn_opcode, \
1289 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1290 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1291 EXTRACT_BITS ((INSN).insn_opcode, \
1292 MIPS16OP_MASK_##FIELD, \
1293 MIPS16OP_SH_##FIELD)
1295 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1296 #define MIPS16_EXTEND (0xf000U << 16)
1298 /* Whether or not we are emitting a branch-likely macro. */
1299 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1301 /* Global variables used when generating relaxable macros. See the
1302 comment above RELAX_ENCODE for more details about how relaxation
1305 /* 0 if we're not emitting a relaxable macro.
1306 1 if we're emitting the first of the two relaxation alternatives.
1307 2 if we're emitting the second alternative. */
1310 /* The first relaxable fixup in the current frag. (In other words,
1311 the first fixup that refers to relaxable code.) */
1314 /* sizes[0] says how many bytes of the first alternative are stored in
1315 the current frag. Likewise sizes[1] for the second alternative. */
1316 unsigned int sizes
[2];
1318 /* The symbol on which the choice of sequence depends. */
1322 /* Global variables used to decide whether a macro needs a warning. */
1324 /* True if the macro is in a branch delay slot. */
1325 bfd_boolean delay_slot_p
;
1327 /* Set to the length in bytes required if the macro is in a delay slot
1328 that requires a specific length of instruction, otherwise zero. */
1329 unsigned int delay_slot_length
;
1331 /* For relaxable macros, sizes[0] is the length of the first alternative
1332 in bytes and sizes[1] is the length of the second alternative.
1333 For non-relaxable macros, both elements give the length of the
1335 unsigned int sizes
[2];
1337 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1338 instruction of the first alternative in bytes and first_insn_sizes[1]
1339 is the length of the first instruction of the second alternative.
1340 For non-relaxable macros, both elements give the length of the first
1341 instruction in bytes.
1343 Set to zero if we haven't yet seen the first instruction. */
1344 unsigned int first_insn_sizes
[2];
1346 /* For relaxable macros, insns[0] is the number of instructions for the
1347 first alternative and insns[1] is the number of instructions for the
1350 For non-relaxable macros, both elements give the number of
1351 instructions for the macro. */
1352 unsigned int insns
[2];
1354 /* The first variant frag for this macro. */
1356 } mips_macro_warning
;
1358 /* Prototypes for static functions. */
1360 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1362 static void append_insn
1363 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1364 bfd_boolean expansionp
);
1365 static void mips_no_prev_insn (void);
1366 static void macro_build (expressionS
*, const char *, const char *, ...);
1367 static void mips16_macro_build
1368 (expressionS
*, const char *, const char *, va_list *);
1369 static void load_register (int, expressionS
*, int);
1370 static void macro_start (void);
1371 static void macro_end (void);
1372 static void macro (struct mips_cl_insn
*ip
, char *str
);
1373 static void mips16_macro (struct mips_cl_insn
* ip
);
1374 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1375 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1376 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1377 static void mips16_immed
1378 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1379 unsigned int, unsigned long *);
1380 static size_t my_getSmallExpression
1381 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1382 static void my_getExpression (expressionS
*, char *);
1383 static void s_align (int);
1384 static void s_change_sec (int);
1385 static void s_change_section (int);
1386 static void s_cons (int);
1387 static void s_float_cons (int);
1388 static void s_mips_globl (int);
1389 static void s_option (int);
1390 static void s_mipsset (int);
1391 static void s_abicalls (int);
1392 static void s_cpload (int);
1393 static void s_cpsetup (int);
1394 static void s_cplocal (int);
1395 static void s_cprestore (int);
1396 static void s_cpreturn (int);
1397 static void s_dtprelword (int);
1398 static void s_dtpreldword (int);
1399 static void s_tprelword (int);
1400 static void s_tpreldword (int);
1401 static void s_gpvalue (int);
1402 static void s_gpword (int);
1403 static void s_gpdword (int);
1404 static void s_ehword (int);
1405 static void s_cpadd (int);
1406 static void s_insn (int);
1407 static void s_nan (int);
1408 static void s_module (int);
1409 static void s_mips_ent (int);
1410 static void s_mips_end (int);
1411 static void s_mips_frame (int);
1412 static void s_mips_mask (int reg_type
);
1413 static void s_mips_stab (int);
1414 static void s_mips_weakext (int);
1415 static void s_mips_file (int);
1416 static void s_mips_loc (int);
1417 static bfd_boolean
pic_need_relax (symbolS
*);
1418 static int relaxed_branch_length (fragS
*, asection
*, int);
1419 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1420 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1421 static void file_mips_check_options (void);
1423 /* Table and functions used to map between CPU/ISA names, and
1424 ISA levels, and CPU numbers. */
1426 struct mips_cpu_info
1428 const char *name
; /* CPU or ISA name. */
1429 int flags
; /* MIPS_CPU_* flags. */
1430 int ase
; /* Set of ASEs implemented by the CPU. */
1431 int isa
; /* ISA level. */
1432 int cpu
; /* CPU number (default CPU if ISA). */
1435 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1437 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1438 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1439 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1441 /* Command-line options. */
1442 const char *md_shortopts
= "O::g::G:";
1446 OPTION_MARCH
= OPTION_MD_BASE
,
1478 OPTION_NO_SMARTMIPS
,
1488 OPTION_NO_MICROMIPS
,
1503 OPTION_M7000_HILO_FIX
,
1504 OPTION_MNO_7000_HILO_FIX
,
1508 OPTION_NO_FIX_RM7000
,
1509 OPTION_FIX_LOONGSON3_LLSC
,
1510 OPTION_NO_FIX_LOONGSON3_LLSC
,
1511 OPTION_FIX_LOONGSON2F_JUMP
,
1512 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1513 OPTION_FIX_LOONGSON2F_NOP
,
1514 OPTION_NO_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_VR4120
,
1518 OPTION_NO_FIX_VR4130
,
1519 OPTION_FIX_CN63XXP1
,
1520 OPTION_NO_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_R5900
,
1529 OPTION_CONSTRUCT_FLOATS
,
1530 OPTION_NO_CONSTRUCT_FLOATS
,
1534 OPTION_RELAX_BRANCH
,
1535 OPTION_NO_RELAX_BRANCH
,
1536 OPTION_IGNORE_BRANCH_ISA
,
1537 OPTION_NO_IGNORE_BRANCH_ISA
,
1546 OPTION_SINGLE_FLOAT
,
1547 OPTION_DOUBLE_FLOAT
,
1560 OPTION_MVXWORKS_PIC
,
1563 OPTION_NO_ODD_SPREG
,
1566 OPTION_LOONGSON_MMI
,
1567 OPTION_NO_LOONGSON_MMI
,
1568 OPTION_LOONGSON_CAM
,
1569 OPTION_NO_LOONGSON_CAM
,
1570 OPTION_LOONGSON_EXT
,
1571 OPTION_NO_LOONGSON_EXT
,
1572 OPTION_LOONGSON_EXT2
,
1573 OPTION_NO_LOONGSON_EXT2
,
1577 struct option md_longopts
[] =
1579 /* Options which specify architecture. */
1580 {"march", required_argument
, NULL
, OPTION_MARCH
},
1581 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1582 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1583 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1584 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1585 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1586 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1587 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1588 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1589 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1590 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1591 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1592 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1593 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1594 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1595 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1596 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1597 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1599 /* Options which specify Application Specific Extensions (ASEs). */
1600 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1601 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1602 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1603 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1604 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1605 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1606 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1607 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1608 {"mmt", no_argument
, NULL
, OPTION_MT
},
1609 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1610 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1611 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1612 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1613 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1614 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1615 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1616 {"meva", no_argument
, NULL
, OPTION_EVA
},
1617 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1618 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1619 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1620 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1621 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1622 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1623 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1624 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1625 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1626 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1627 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1628 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1629 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1630 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1631 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1632 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1633 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1634 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1635 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1636 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1637 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1638 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1639 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1640 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1641 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1643 /* Old-style architecture options. Don't add more of these. */
1644 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1645 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1646 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1647 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1648 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1649 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1650 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1651 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1653 /* Options which enable bug fixes. */
1654 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1655 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1656 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1657 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1658 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1659 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1660 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1661 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1662 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1663 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1664 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1665 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1666 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1667 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1668 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1669 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1670 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1671 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1672 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1673 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1674 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1676 /* Miscellaneous options. */
1677 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1678 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1679 {"break", no_argument
, NULL
, OPTION_BREAK
},
1680 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1681 {"EB", no_argument
, NULL
, OPTION_EB
},
1682 {"EL", no_argument
, NULL
, OPTION_EL
},
1683 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1684 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1685 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1686 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1687 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1688 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1689 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1690 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1691 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1692 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1693 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1694 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1695 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1696 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1697 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1698 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1699 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1700 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1701 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1702 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1703 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1704 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1705 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1707 /* Strictly speaking this next option is ELF specific,
1708 but we allow it for other ports as well in order to
1709 make testing easier. */
1710 {"32", no_argument
, NULL
, OPTION_32
},
1712 /* ELF-specific options. */
1713 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1714 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1715 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1716 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1717 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1718 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1719 {"n32", no_argument
, NULL
, OPTION_N32
},
1720 {"64", no_argument
, NULL
, OPTION_64
},
1721 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1722 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1723 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1724 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1725 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1726 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1728 {NULL
, no_argument
, NULL
, 0}
1730 size_t md_longopts_size
= sizeof (md_longopts
);
1732 /* Information about either an Application Specific Extension or an
1733 optional architecture feature that, for simplicity, we treat in the
1734 same way as an ASE. */
1737 /* The name of the ASE, used in both the command-line and .set options. */
1740 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1741 and 64-bit architectures, the flags here refer to the subset that
1742 is available on both. */
1745 /* The ASE_* flag used for instructions that are available on 64-bit
1746 architectures but that are not included in FLAGS. */
1747 unsigned int flags64
;
1749 /* The command-line options that turn the ASE on and off. */
1753 /* The minimum required architecture revisions for MIPS32, MIPS64,
1754 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1757 int micromips32_rev
;
1758 int micromips64_rev
;
1760 /* The architecture where the ASE was removed or -1 if the extension has not
1765 /* A table of all supported ASEs. */
1766 static const struct mips_ase mips_ases
[] = {
1767 { "dsp", ASE_DSP
, ASE_DSP64
,
1768 OPTION_DSP
, OPTION_NO_DSP
,
1772 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1773 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1777 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1778 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1782 { "eva", ASE_EVA
, 0,
1783 OPTION_EVA
, OPTION_NO_EVA
,
1787 { "mcu", ASE_MCU
, 0,
1788 OPTION_MCU
, OPTION_NO_MCU
,
1792 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1793 { "mdmx", ASE_MDMX
, 0,
1794 OPTION_MDMX
, OPTION_NO_MDMX
,
1798 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1799 { "mips3d", ASE_MIPS3D
, 0,
1800 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1805 OPTION_MT
, OPTION_NO_MT
,
1809 { "smartmips", ASE_SMARTMIPS
, 0,
1810 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1814 { "virt", ASE_VIRT
, ASE_VIRT64
,
1815 OPTION_VIRT
, OPTION_NO_VIRT
,
1819 { "msa", ASE_MSA
, ASE_MSA64
,
1820 OPTION_MSA
, OPTION_NO_MSA
,
1824 { "xpa", ASE_XPA
, 0,
1825 OPTION_XPA
, OPTION_NO_XPA
,
1829 { "mips16e2", ASE_MIPS16E2
, 0,
1830 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1834 { "crc", ASE_CRC
, ASE_CRC64
,
1835 OPTION_CRC
, OPTION_NO_CRC
,
1839 { "ginv", ASE_GINV
, 0,
1840 OPTION_GINV
, OPTION_NO_GINV
,
1844 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1845 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1849 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1850 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1854 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1855 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1859 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1860 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1865 /* The set of ASEs that require -mfp64. */
1866 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1868 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1869 static const unsigned int mips_ase_groups
[] = {
1870 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1871 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1876 The following pseudo-ops from the Kane and Heinrich MIPS book
1877 should be defined here, but are currently unsupported: .alias,
1878 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1880 The following pseudo-ops from the Kane and Heinrich MIPS book are
1881 specific to the type of debugging information being generated, and
1882 should be defined by the object format: .aent, .begin, .bend,
1883 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1886 The following pseudo-ops from the Kane and Heinrich MIPS book are
1887 not MIPS CPU specific, but are also not specific to the object file
1888 format. This file is probably the best place to define them, but
1889 they are not currently supported: .asm0, .endr, .lab, .struct. */
1891 static const pseudo_typeS mips_pseudo_table
[] =
1893 /* MIPS specific pseudo-ops. */
1894 {"option", s_option
, 0},
1895 {"set", s_mipsset
, 0},
1896 {"rdata", s_change_sec
, 'r'},
1897 {"sdata", s_change_sec
, 's'},
1898 {"livereg", s_ignore
, 0},
1899 {"abicalls", s_abicalls
, 0},
1900 {"cpload", s_cpload
, 0},
1901 {"cpsetup", s_cpsetup
, 0},
1902 {"cplocal", s_cplocal
, 0},
1903 {"cprestore", s_cprestore
, 0},
1904 {"cpreturn", s_cpreturn
, 0},
1905 {"dtprelword", s_dtprelword
, 0},
1906 {"dtpreldword", s_dtpreldword
, 0},
1907 {"tprelword", s_tprelword
, 0},
1908 {"tpreldword", s_tpreldword
, 0},
1909 {"gpvalue", s_gpvalue
, 0},
1910 {"gpword", s_gpword
, 0},
1911 {"gpdword", s_gpdword
, 0},
1912 {"ehword", s_ehword
, 0},
1913 {"cpadd", s_cpadd
, 0},
1914 {"insn", s_insn
, 0},
1916 {"module", s_module
, 0},
1918 /* Relatively generic pseudo-ops that happen to be used on MIPS
1920 {"asciiz", stringer
, 8 + 1},
1921 {"bss", s_change_sec
, 'b'},
1923 {"half", s_cons
, 1},
1924 {"dword", s_cons
, 3},
1925 {"weakext", s_mips_weakext
, 0},
1926 {"origin", s_org
, 0},
1927 {"repeat", s_rept
, 0},
1929 /* For MIPS this is non-standard, but we define it for consistency. */
1930 {"sbss", s_change_sec
, 'B'},
1932 /* These pseudo-ops are defined in read.c, but must be overridden
1933 here for one reason or another. */
1934 {"align", s_align
, 0},
1935 {"byte", s_cons
, 0},
1936 {"data", s_change_sec
, 'd'},
1937 {"double", s_float_cons
, 'd'},
1938 {"float", s_float_cons
, 'f'},
1939 {"globl", s_mips_globl
, 0},
1940 {"global", s_mips_globl
, 0},
1941 {"hword", s_cons
, 1},
1943 {"long", s_cons
, 2},
1944 {"octa", s_cons
, 4},
1945 {"quad", s_cons
, 3},
1946 {"section", s_change_section
, 0},
1947 {"short", s_cons
, 1},
1948 {"single", s_float_cons
, 'f'},
1949 {"stabd", s_mips_stab
, 'd'},
1950 {"stabn", s_mips_stab
, 'n'},
1951 {"stabs", s_mips_stab
, 's'},
1952 {"text", s_change_sec
, 't'},
1953 {"word", s_cons
, 2},
1955 { "extern", ecoff_directive_extern
, 0},
1960 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1962 /* These pseudo-ops should be defined by the object file format.
1963 However, a.out doesn't support them, so we have versions here. */
1964 {"aent", s_mips_ent
, 1},
1965 {"bgnb", s_ignore
, 0},
1966 {"end", s_mips_end
, 0},
1967 {"endb", s_ignore
, 0},
1968 {"ent", s_mips_ent
, 0},
1969 {"file", s_mips_file
, 0},
1970 {"fmask", s_mips_mask
, 'F'},
1971 {"frame", s_mips_frame
, 0},
1972 {"loc", s_mips_loc
, 0},
1973 {"mask", s_mips_mask
, 'R'},
1974 {"verstamp", s_ignore
, 0},
1978 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1979 purpose of the `.dc.a' internal pseudo-op. */
1982 mips_address_bytes (void)
1984 file_mips_check_options ();
1985 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1988 extern void pop_insert (const pseudo_typeS
*);
1991 mips_pop_insert (void)
1993 pop_insert (mips_pseudo_table
);
1994 if (! ECOFF_DEBUGGING
)
1995 pop_insert (mips_nonecoff_pseudo_table
);
1998 /* Symbols labelling the current insn. */
2000 struct insn_label_list
2002 struct insn_label_list
*next
;
2006 static struct insn_label_list
*free_insn_labels
;
2007 #define label_list tc_segment_info_data.labels
2009 static void mips_clear_insn_labels (void);
2010 static void mips_mark_labels (void);
2011 static void mips_compressed_mark_labels (void);
2014 mips_clear_insn_labels (void)
2016 struct insn_label_list
**pl
;
2017 segment_info_type
*si
;
2021 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2024 si
= seg_info (now_seg
);
2025 *pl
= si
->label_list
;
2026 si
->label_list
= NULL
;
2030 /* Mark instruction labels in MIPS16/microMIPS mode. */
2033 mips_mark_labels (void)
2035 if (HAVE_CODE_COMPRESSION
)
2036 mips_compressed_mark_labels ();
2039 static char *expr_end
;
2041 /* An expression in a macro instruction. This is set by mips_ip and
2042 mips16_ip and when populated is always an O_constant. */
2044 static expressionS imm_expr
;
2046 /* The relocatable field in an instruction and the relocs associated
2047 with it. These variables are used for instructions like LUI and
2048 JAL as well as true offsets. They are also used for address
2049 operands in macros. */
2051 static expressionS offset_expr
;
2052 static bfd_reloc_code_real_type offset_reloc
[3]
2053 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2055 /* This is set to the resulting size of the instruction to be produced
2056 by mips16_ip if an explicit extension is used or by mips_ip if an
2057 explicit size is supplied. */
2059 static unsigned int forced_insn_length
;
2061 /* True if we are assembling an instruction. All dot symbols defined during
2062 this time should be treated as code labels. */
2064 static bfd_boolean mips_assembling_insn
;
2066 /* The pdr segment for per procedure frame/regmask info. Not used for
2069 static segT pdr_seg
;
2071 /* The default target format to use. */
2073 #if defined (TE_FreeBSD)
2074 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2075 #elif defined (TE_TMIPS)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2082 mips_target_format (void)
2084 switch (OUTPUT_FLAVOR
)
2086 case bfd_target_elf_flavour
:
2088 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2089 return (target_big_endian
2090 ? "elf32-bigmips-vxworks"
2091 : "elf32-littlemips-vxworks");
2093 return (target_big_endian
2094 ? (HAVE_64BIT_OBJECTS
2095 ? ELF_TARGET ("elf64-", "big")
2097 ? ELF_TARGET ("elf32-n", "big")
2098 : ELF_TARGET ("elf32-", "big")))
2099 : (HAVE_64BIT_OBJECTS
2100 ? ELF_TARGET ("elf64-", "little")
2102 ? ELF_TARGET ("elf32-n", "little")
2103 : ELF_TARGET ("elf32-", "little"))));
2110 /* Return the ISA revision that is currently in use, or 0 if we are
2111 generating code for MIPS V or below. */
2116 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2119 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2122 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2125 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2128 /* microMIPS implies revision 2 or above. */
2129 if (mips_opts
.micromips
)
2132 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2138 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2141 mips_ase_mask (unsigned int flags
)
2145 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2146 if (flags
& mips_ase_groups
[i
])
2147 flags
|= mips_ase_groups
[i
];
2151 /* Check whether the current ISA supports ASE. Issue a warning if
2155 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2159 static unsigned int warned_isa
;
2160 static unsigned int warned_fp32
;
2162 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2163 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2165 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2166 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2167 && (warned_isa
& ase
->flags
) != ase
->flags
)
2169 warned_isa
|= ase
->flags
;
2170 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2171 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2173 as_warn (_("the %d-bit %s architecture does not support the"
2174 " `%s' extension"), size
, base
, ase
->name
);
2176 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2177 ase
->name
, base
, size
, min_rev
);
2179 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2180 && (warned_isa
& ase
->flags
) != ase
->flags
)
2182 warned_isa
|= ase
->flags
;
2183 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2184 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2185 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2186 ase
->name
, base
, size
, ase
->rem_rev
);
2189 if ((ase
->flags
& FP64_ASES
)
2190 && mips_opts
.fp
!= 64
2191 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2193 warned_fp32
|= ase
->flags
;
2194 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2198 /* Check all enabled ASEs to see whether they are supported by the
2199 chosen architecture. */
2202 mips_check_isa_supports_ases (void)
2204 unsigned int i
, mask
;
2206 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2208 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2209 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2210 mips_check_isa_supports_ase (&mips_ases
[i
]);
2214 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2215 that were affected. */
2218 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2219 bfd_boolean enabled_p
)
2223 mask
= mips_ase_mask (ase
->flags
);
2226 /* Clear combination ASE flags, which need to be recalculated based on
2227 updated regular ASE settings. */
2228 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2231 opts
->ase
|= ase
->flags
;
2233 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2234 instructions which are only valid when both ASEs are enabled.
2235 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2236 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2238 opts
->ase
|= ASE_XPA_VIRT
;
2239 mask
|= ASE_XPA_VIRT
;
2241 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2243 opts
->ase
|= ASE_MIPS16E2_MT
;
2244 mask
|= ASE_MIPS16E2_MT
;
2247 /* The EVA Extension has instructions which are only valid when the R6 ISA
2248 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2250 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2252 opts
->ase
|= ASE_EVA_R6
;
2259 /* Return the ASE called NAME, or null if none. */
2261 static const struct mips_ase
*
2262 mips_lookup_ase (const char *name
)
2266 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2267 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2268 return &mips_ases
[i
];
2272 /* Return the length of a microMIPS instruction in bytes. If bits of
2273 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2274 otherwise it is a 32-bit instruction. */
2276 static inline unsigned int
2277 micromips_insn_length (const struct mips_opcode
*mo
)
2279 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2282 /* Return the length of MIPS16 instruction OPCODE. */
2284 static inline unsigned int
2285 mips16_opcode_length (unsigned long opcode
)
2287 return (opcode
>> 16) == 0 ? 2 : 4;
2290 /* Return the length of instruction INSN. */
2292 static inline unsigned int
2293 insn_length (const struct mips_cl_insn
*insn
)
2295 if (mips_opts
.micromips
)
2296 return micromips_insn_length (insn
->insn_mo
);
2297 else if (mips_opts
.mips16
)
2298 return mips16_opcode_length (insn
->insn_opcode
);
2303 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2306 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2311 insn
->insn_opcode
= mo
->match
;
2314 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2315 insn
->fixp
[i
] = NULL
;
2316 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2317 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2318 insn
->mips16_absolute_jump_p
= 0;
2319 insn
->complete_p
= 0;
2320 insn
->cleared_p
= 0;
2323 /* Get a list of all the operands in INSN. */
2325 static const struct mips_operand_array
*
2326 insn_operands (const struct mips_cl_insn
*insn
)
2328 if (insn
->insn_mo
>= &mips_opcodes
[0]
2329 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2330 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2332 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2333 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2334 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2336 if (insn
->insn_mo
>= µmips_opcodes
[0]
2337 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2338 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2343 /* Get a description of operand OPNO of INSN. */
2345 static const struct mips_operand
*
2346 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2348 const struct mips_operand_array
*operands
;
2350 operands
= insn_operands (insn
);
2351 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2353 return operands
->operand
[opno
];
2356 /* Install UVAL as the value of OPERAND in INSN. */
2359 insn_insert_operand (struct mips_cl_insn
*insn
,
2360 const struct mips_operand
*operand
, unsigned int uval
)
2362 if (mips_opts
.mips16
2363 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2364 && mips_opcode_32bit_p (insn
->insn_mo
))
2365 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2367 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2370 /* Extract the value of OPERAND from INSN. */
2372 static inline unsigned
2373 insn_extract_operand (const struct mips_cl_insn
*insn
,
2374 const struct mips_operand
*operand
)
2376 return mips_extract_operand (operand
, insn
->insn_opcode
);
2379 /* Record the current MIPS16/microMIPS mode in now_seg. */
2382 mips_record_compressed_mode (void)
2384 segment_info_type
*si
;
2386 si
= seg_info (now_seg
);
2387 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2388 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2389 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2390 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2393 /* Read a standard MIPS instruction from BUF. */
2395 static unsigned long
2396 read_insn (char *buf
)
2398 if (target_big_endian
)
2399 return bfd_getb32 ((bfd_byte
*) buf
);
2401 return bfd_getl32 ((bfd_byte
*) buf
);
2404 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2408 write_insn (char *buf
, unsigned int insn
)
2410 md_number_to_chars (buf
, insn
, 4);
2414 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2415 has length LENGTH. */
2417 static unsigned long
2418 read_compressed_insn (char *buf
, unsigned int length
)
2424 for (i
= 0; i
< length
; i
+= 2)
2427 if (target_big_endian
)
2428 insn
|= bfd_getb16 ((char *) buf
);
2430 insn
|= bfd_getl16 ((char *) buf
);
2436 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2437 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2440 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2444 for (i
= 0; i
< length
; i
+= 2)
2445 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2446 return buf
+ length
;
2449 /* Install INSN at the location specified by its "frag" and "where" fields. */
2452 install_insn (const struct mips_cl_insn
*insn
)
2454 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2455 if (HAVE_CODE_COMPRESSION
)
2456 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2458 write_insn (f
, insn
->insn_opcode
);
2459 mips_record_compressed_mode ();
2462 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2463 and install the opcode in the new location. */
2466 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2471 insn
->where
= where
;
2472 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2473 if (insn
->fixp
[i
] != NULL
)
2475 insn
->fixp
[i
]->fx_frag
= frag
;
2476 insn
->fixp
[i
]->fx_where
= where
;
2478 install_insn (insn
);
2481 /* Add INSN to the end of the output. */
2484 add_fixed_insn (struct mips_cl_insn
*insn
)
2486 char *f
= frag_more (insn_length (insn
));
2487 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2490 /* Start a variant frag and move INSN to the start of the variant part,
2491 marking it as fixed. The other arguments are as for frag_var. */
2494 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2495 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2497 frag_grow (max_chars
);
2498 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2500 frag_var (rs_machine_dependent
, max_chars
, var
,
2501 subtype
, symbol
, offset
, NULL
);
2504 /* Insert N copies of INSN into the history buffer, starting at
2505 position FIRST. Neither FIRST nor N need to be clipped. */
2508 insert_into_history (unsigned int first
, unsigned int n
,
2509 const struct mips_cl_insn
*insn
)
2511 if (mips_relax
.sequence
!= 2)
2515 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2517 history
[i
] = history
[i
- n
];
2523 /* Clear the error in insn_error. */
2526 clear_insn_error (void)
2528 memset (&insn_error
, 0, sizeof (insn_error
));
2531 /* Possibly record error message MSG for the current instruction.
2532 If the error is about a particular argument, ARGNUM is the 1-based
2533 number of that argument, otherwise it is 0. FORMAT is the format
2534 of MSG. Return true if MSG was used, false if the current message
2538 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2543 /* Give priority to errors against specific arguments, and to
2544 the first whole-instruction message. */
2550 /* Keep insn_error if it is against a later argument. */
2551 if (argnum
< insn_error
.min_argnum
)
2554 /* If both errors are against the same argument but are different,
2555 give up on reporting a specific error for this argument.
2556 See the comment about mips_insn_error for details. */
2557 if (argnum
== insn_error
.min_argnum
2559 && strcmp (insn_error
.msg
, msg
) != 0)
2562 insn_error
.min_argnum
+= 1;
2566 insn_error
.min_argnum
= argnum
;
2567 insn_error
.format
= format
;
2568 insn_error
.msg
= msg
;
2572 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2573 as for set_insn_error_format. */
2576 set_insn_error (int argnum
, const char *msg
)
2578 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2581 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2582 as for set_insn_error_format. */
2585 set_insn_error_i (int argnum
, const char *msg
, int i
)
2587 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2591 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2592 are as for set_insn_error_format. */
2595 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2597 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2599 insn_error
.u
.ss
[0] = s1
;
2600 insn_error
.u
.ss
[1] = s2
;
2604 /* Report the error in insn_error, which is against assembly code STR. */
2607 report_insn_error (const char *str
)
2609 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2611 switch (insn_error
.format
)
2618 as_bad (msg
, insn_error
.u
.i
, str
);
2622 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2626 free ((char *) msg
);
2629 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2630 the idea is to make it obvious at a glance that each errata is
2634 init_vr4120_conflicts (void)
2636 #define CONFLICT(FIRST, SECOND) \
2637 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2639 /* Errata 21 - [D]DIV[U] after [D]MACC */
2640 CONFLICT (MACC
, DIV
);
2641 CONFLICT (DMACC
, DIV
);
2643 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2644 CONFLICT (DMULT
, DMULT
);
2645 CONFLICT (DMULT
, DMACC
);
2646 CONFLICT (DMACC
, DMULT
);
2647 CONFLICT (DMACC
, DMACC
);
2649 /* Errata 24 - MT{LO,HI} after [D]MACC */
2650 CONFLICT (MACC
, MTHILO
);
2651 CONFLICT (DMACC
, MTHILO
);
2653 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2654 instruction is executed immediately after a MACC or DMACC
2655 instruction, the result of [either instruction] is incorrect." */
2656 CONFLICT (MACC
, MULT
);
2657 CONFLICT (MACC
, DMULT
);
2658 CONFLICT (DMACC
, MULT
);
2659 CONFLICT (DMACC
, DMULT
);
2661 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2662 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2663 DDIV or DDIVU instruction, the result of the MACC or
2664 DMACC instruction is incorrect.". */
2665 CONFLICT (DMULT
, MACC
);
2666 CONFLICT (DMULT
, DMACC
);
2667 CONFLICT (DIV
, MACC
);
2668 CONFLICT (DIV
, DMACC
);
2678 #define RNUM_MASK 0x00000ff
2679 #define RTYPE_MASK 0x0ffff00
2680 #define RTYPE_NUM 0x0000100
2681 #define RTYPE_FPU 0x0000200
2682 #define RTYPE_FCC 0x0000400
2683 #define RTYPE_VEC 0x0000800
2684 #define RTYPE_GP 0x0001000
2685 #define RTYPE_CP0 0x0002000
2686 #define RTYPE_PC 0x0004000
2687 #define RTYPE_ACC 0x0008000
2688 #define RTYPE_CCC 0x0010000
2689 #define RTYPE_VI 0x0020000
2690 #define RTYPE_VF 0x0040000
2691 #define RTYPE_R5900_I 0x0080000
2692 #define RTYPE_R5900_Q 0x0100000
2693 #define RTYPE_R5900_R 0x0200000
2694 #define RTYPE_R5900_ACC 0x0400000
2695 #define RTYPE_MSA 0x0800000
2696 #define RWARN 0x8000000
2698 #define GENERIC_REGISTER_NUMBERS \
2699 {"$0", RTYPE_NUM | 0}, \
2700 {"$1", RTYPE_NUM | 1}, \
2701 {"$2", RTYPE_NUM | 2}, \
2702 {"$3", RTYPE_NUM | 3}, \
2703 {"$4", RTYPE_NUM | 4}, \
2704 {"$5", RTYPE_NUM | 5}, \
2705 {"$6", RTYPE_NUM | 6}, \
2706 {"$7", RTYPE_NUM | 7}, \
2707 {"$8", RTYPE_NUM | 8}, \
2708 {"$9", RTYPE_NUM | 9}, \
2709 {"$10", RTYPE_NUM | 10}, \
2710 {"$11", RTYPE_NUM | 11}, \
2711 {"$12", RTYPE_NUM | 12}, \
2712 {"$13", RTYPE_NUM | 13}, \
2713 {"$14", RTYPE_NUM | 14}, \
2714 {"$15", RTYPE_NUM | 15}, \
2715 {"$16", RTYPE_NUM | 16}, \
2716 {"$17", RTYPE_NUM | 17}, \
2717 {"$18", RTYPE_NUM | 18}, \
2718 {"$19", RTYPE_NUM | 19}, \
2719 {"$20", RTYPE_NUM | 20}, \
2720 {"$21", RTYPE_NUM | 21}, \
2721 {"$22", RTYPE_NUM | 22}, \
2722 {"$23", RTYPE_NUM | 23}, \
2723 {"$24", RTYPE_NUM | 24}, \
2724 {"$25", RTYPE_NUM | 25}, \
2725 {"$26", RTYPE_NUM | 26}, \
2726 {"$27", RTYPE_NUM | 27}, \
2727 {"$28", RTYPE_NUM | 28}, \
2728 {"$29", RTYPE_NUM | 29}, \
2729 {"$30", RTYPE_NUM | 30}, \
2730 {"$31", RTYPE_NUM | 31}
2732 #define FPU_REGISTER_NAMES \
2733 {"$f0", RTYPE_FPU | 0}, \
2734 {"$f1", RTYPE_FPU | 1}, \
2735 {"$f2", RTYPE_FPU | 2}, \
2736 {"$f3", RTYPE_FPU | 3}, \
2737 {"$f4", RTYPE_FPU | 4}, \
2738 {"$f5", RTYPE_FPU | 5}, \
2739 {"$f6", RTYPE_FPU | 6}, \
2740 {"$f7", RTYPE_FPU | 7}, \
2741 {"$f8", RTYPE_FPU | 8}, \
2742 {"$f9", RTYPE_FPU | 9}, \
2743 {"$f10", RTYPE_FPU | 10}, \
2744 {"$f11", RTYPE_FPU | 11}, \
2745 {"$f12", RTYPE_FPU | 12}, \
2746 {"$f13", RTYPE_FPU | 13}, \
2747 {"$f14", RTYPE_FPU | 14}, \
2748 {"$f15", RTYPE_FPU | 15}, \
2749 {"$f16", RTYPE_FPU | 16}, \
2750 {"$f17", RTYPE_FPU | 17}, \
2751 {"$f18", RTYPE_FPU | 18}, \
2752 {"$f19", RTYPE_FPU | 19}, \
2753 {"$f20", RTYPE_FPU | 20}, \
2754 {"$f21", RTYPE_FPU | 21}, \
2755 {"$f22", RTYPE_FPU | 22}, \
2756 {"$f23", RTYPE_FPU | 23}, \
2757 {"$f24", RTYPE_FPU | 24}, \
2758 {"$f25", RTYPE_FPU | 25}, \
2759 {"$f26", RTYPE_FPU | 26}, \
2760 {"$f27", RTYPE_FPU | 27}, \
2761 {"$f28", RTYPE_FPU | 28}, \
2762 {"$f29", RTYPE_FPU | 29}, \
2763 {"$f30", RTYPE_FPU | 30}, \
2764 {"$f31", RTYPE_FPU | 31}
2766 #define FPU_CONDITION_CODE_NAMES \
2767 {"$fcc0", RTYPE_FCC | 0}, \
2768 {"$fcc1", RTYPE_FCC | 1}, \
2769 {"$fcc2", RTYPE_FCC | 2}, \
2770 {"$fcc3", RTYPE_FCC | 3}, \
2771 {"$fcc4", RTYPE_FCC | 4}, \
2772 {"$fcc5", RTYPE_FCC | 5}, \
2773 {"$fcc6", RTYPE_FCC | 6}, \
2774 {"$fcc7", RTYPE_FCC | 7}
2776 #define COPROC_CONDITION_CODE_NAMES \
2777 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2778 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2779 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2780 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2781 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2782 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2783 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2784 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2786 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2787 {"$a4", RTYPE_GP | 8}, \
2788 {"$a5", RTYPE_GP | 9}, \
2789 {"$a6", RTYPE_GP | 10}, \
2790 {"$a7", RTYPE_GP | 11}, \
2791 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2792 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2793 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2794 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2795 {"$t0", RTYPE_GP | 12}, \
2796 {"$t1", RTYPE_GP | 13}, \
2797 {"$t2", RTYPE_GP | 14}, \
2798 {"$t3", RTYPE_GP | 15}
2800 #define O32_SYMBOLIC_REGISTER_NAMES \
2801 {"$t0", RTYPE_GP | 8}, \
2802 {"$t1", RTYPE_GP | 9}, \
2803 {"$t2", RTYPE_GP | 10}, \
2804 {"$t3", RTYPE_GP | 11}, \
2805 {"$t4", RTYPE_GP | 12}, \
2806 {"$t5", RTYPE_GP | 13}, \
2807 {"$t6", RTYPE_GP | 14}, \
2808 {"$t7", RTYPE_GP | 15}, \
2809 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2810 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2811 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2812 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2814 /* Remaining symbolic register names. */
2815 #define SYMBOLIC_REGISTER_NAMES \
2816 {"$zero", RTYPE_GP | 0}, \
2817 {"$at", RTYPE_GP | 1}, \
2818 {"$AT", RTYPE_GP | 1}, \
2819 {"$v0", RTYPE_GP | 2}, \
2820 {"$v1", RTYPE_GP | 3}, \
2821 {"$a0", RTYPE_GP | 4}, \
2822 {"$a1", RTYPE_GP | 5}, \
2823 {"$a2", RTYPE_GP | 6}, \
2824 {"$a3", RTYPE_GP | 7}, \
2825 {"$s0", RTYPE_GP | 16}, \
2826 {"$s1", RTYPE_GP | 17}, \
2827 {"$s2", RTYPE_GP | 18}, \
2828 {"$s3", RTYPE_GP | 19}, \
2829 {"$s4", RTYPE_GP | 20}, \
2830 {"$s5", RTYPE_GP | 21}, \
2831 {"$s6", RTYPE_GP | 22}, \
2832 {"$s7", RTYPE_GP | 23}, \
2833 {"$t8", RTYPE_GP | 24}, \
2834 {"$t9", RTYPE_GP | 25}, \
2835 {"$k0", RTYPE_GP | 26}, \
2836 {"$kt0", RTYPE_GP | 26}, \
2837 {"$k1", RTYPE_GP | 27}, \
2838 {"$kt1", RTYPE_GP | 27}, \
2839 {"$gp", RTYPE_GP | 28}, \
2840 {"$sp", RTYPE_GP | 29}, \
2841 {"$s8", RTYPE_GP | 30}, \
2842 {"$fp", RTYPE_GP | 30}, \
2843 {"$ra", RTYPE_GP | 31}
2845 #define MIPS16_SPECIAL_REGISTER_NAMES \
2846 {"$pc", RTYPE_PC | 0}
2848 #define MDMX_VECTOR_REGISTER_NAMES \
2849 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2850 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2851 {"$v2", RTYPE_VEC | 2}, \
2852 {"$v3", RTYPE_VEC | 3}, \
2853 {"$v4", RTYPE_VEC | 4}, \
2854 {"$v5", RTYPE_VEC | 5}, \
2855 {"$v6", RTYPE_VEC | 6}, \
2856 {"$v7", RTYPE_VEC | 7}, \
2857 {"$v8", RTYPE_VEC | 8}, \
2858 {"$v9", RTYPE_VEC | 9}, \
2859 {"$v10", RTYPE_VEC | 10}, \
2860 {"$v11", RTYPE_VEC | 11}, \
2861 {"$v12", RTYPE_VEC | 12}, \
2862 {"$v13", RTYPE_VEC | 13}, \
2863 {"$v14", RTYPE_VEC | 14}, \
2864 {"$v15", RTYPE_VEC | 15}, \
2865 {"$v16", RTYPE_VEC | 16}, \
2866 {"$v17", RTYPE_VEC | 17}, \
2867 {"$v18", RTYPE_VEC | 18}, \
2868 {"$v19", RTYPE_VEC | 19}, \
2869 {"$v20", RTYPE_VEC | 20}, \
2870 {"$v21", RTYPE_VEC | 21}, \
2871 {"$v22", RTYPE_VEC | 22}, \
2872 {"$v23", RTYPE_VEC | 23}, \
2873 {"$v24", RTYPE_VEC | 24}, \
2874 {"$v25", RTYPE_VEC | 25}, \
2875 {"$v26", RTYPE_VEC | 26}, \
2876 {"$v27", RTYPE_VEC | 27}, \
2877 {"$v28", RTYPE_VEC | 28}, \
2878 {"$v29", RTYPE_VEC | 29}, \
2879 {"$v30", RTYPE_VEC | 30}, \
2880 {"$v31", RTYPE_VEC | 31}
2882 #define R5900_I_NAMES \
2883 {"$I", RTYPE_R5900_I | 0}
2885 #define R5900_Q_NAMES \
2886 {"$Q", RTYPE_R5900_Q | 0}
2888 #define R5900_R_NAMES \
2889 {"$R", RTYPE_R5900_R | 0}
2891 #define R5900_ACC_NAMES \
2892 {"$ACC", RTYPE_R5900_ACC | 0 }
2894 #define MIPS_DSP_ACCUMULATOR_NAMES \
2895 {"$ac0", RTYPE_ACC | 0}, \
2896 {"$ac1", RTYPE_ACC | 1}, \
2897 {"$ac2", RTYPE_ACC | 2}, \
2898 {"$ac3", RTYPE_ACC | 3}
2900 static const struct regname reg_names
[] = {
2901 GENERIC_REGISTER_NUMBERS
,
2903 FPU_CONDITION_CODE_NAMES
,
2904 COPROC_CONDITION_CODE_NAMES
,
2906 /* The $txx registers depends on the abi,
2907 these will be added later into the symbol table from
2908 one of the tables below once mips_abi is set after
2909 parsing of arguments from the command line. */
2910 SYMBOLIC_REGISTER_NAMES
,
2912 MIPS16_SPECIAL_REGISTER_NAMES
,
2913 MDMX_VECTOR_REGISTER_NAMES
,
2918 MIPS_DSP_ACCUMULATOR_NAMES
,
2922 static const struct regname reg_names_o32
[] = {
2923 O32_SYMBOLIC_REGISTER_NAMES
,
2927 static const struct regname reg_names_n32n64
[] = {
2928 N32N64_SYMBOLIC_REGISTER_NAMES
,
2932 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2933 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2934 of these register symbols, return the associated vector register,
2935 otherwise return SYMVAL itself. */
2938 mips_prefer_vec_regno (unsigned int symval
)
2940 if ((symval
& -2) == (RTYPE_GP
| 2))
2941 return RTYPE_VEC
| (symval
& 1);
2945 /* Return true if string [S, E) is a valid register name, storing its
2946 symbol value in *SYMVAL_PTR if so. */
2949 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2954 /* Terminate name. */
2958 /* Look up the name. */
2959 symbol
= symbol_find (s
);
2962 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2965 *symval_ptr
= S_GET_VALUE (symbol
);
2969 /* Return true if the string at *SPTR is a valid register name. Allow it
2970 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2973 When returning true, move *SPTR past the register, store the
2974 register's symbol value in *SYMVAL_PTR and the channel mask in
2975 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2976 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2977 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2980 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2981 unsigned int *channels_ptr
)
2985 unsigned int channels
, symval
, bit
;
2987 /* Find end of name. */
2989 if (is_name_beginner (*e
))
2991 while (is_part_of_name (*e
))
2995 if (!mips_parse_register_1 (s
, e
, &symval
))
3000 /* Eat characters from the end of the string that are valid
3001 channel suffixes. The preceding register must be $ACC or
3002 end with a digit, so there is no ambiguity. */
3005 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3006 if (m
> s
&& m
[-1] == *q
)
3013 || !mips_parse_register_1 (s
, m
, &symval
)
3014 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3019 *symval_ptr
= symval
;
3021 *channels_ptr
= channels
;
3025 /* Check if SPTR points at a valid register specifier according to TYPES.
3026 If so, then return 1, advance S to consume the specifier and store
3027 the register's number in REGNOP, otherwise return 0. */
3030 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3034 if (mips_parse_register (s
, ®no
, NULL
))
3036 if (types
& RTYPE_VEC
)
3037 regno
= mips_prefer_vec_regno (regno
);
3046 as_warn (_("unrecognized register name `%s'"), *s
);
3051 return regno
<= RNUM_MASK
;
3054 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3055 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3058 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3063 for (i
= 0; i
< 4; i
++)
3064 if (*s
== "xyzw"[i
])
3066 *channels
|= 1 << (3 - i
);
3072 /* Token types for parsed operand lists. */
3073 enum mips_operand_token_type
{
3074 /* A plain register, e.g. $f2. */
3077 /* A 4-bit XYZW channel mask. */
3080 /* A constant vector index, e.g. [1]. */
3083 /* A register vector index, e.g. [$2]. */
3086 /* A continuous range of registers, e.g. $s0-$s4. */
3089 /* A (possibly relocated) expression. */
3092 /* A floating-point value. */
3095 /* A single character. This can be '(', ')' or ',', but '(' only appears
3099 /* A doubled character, either "--" or "++". */
3102 /* The end of the operand list. */
3106 /* A parsed operand token. */
3107 struct mips_operand_token
3109 /* The type of token. */
3110 enum mips_operand_token_type type
;
3113 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3116 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3117 unsigned int channels
;
3119 /* The integer value of an OT_INTEGER_INDEX. */
3122 /* The two register symbol values involved in an OT_REG_RANGE. */
3124 unsigned int regno1
;
3125 unsigned int regno2
;
3128 /* The value of an OT_INTEGER. The value is represented as an
3129 expression and the relocation operators that were applied to
3130 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3131 relocation operators were used. */
3134 bfd_reloc_code_real_type relocs
[3];
3137 /* The binary data for an OT_FLOAT constant, and the number of bytes
3140 unsigned char data
[8];
3144 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3149 /* An obstack used to construct lists of mips_operand_tokens. */
3150 static struct obstack mips_operand_tokens
;
3152 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3155 mips_add_token (struct mips_operand_token
*token
,
3156 enum mips_operand_token_type type
)
3159 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3162 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3163 and OT_REG tokens for them if so, and return a pointer to the first
3164 unconsumed character. Return null otherwise. */
3167 mips_parse_base_start (char *s
)
3169 struct mips_operand_token token
;
3170 unsigned int regno
, channels
;
3171 bfd_boolean decrement_p
;
3177 SKIP_SPACE_TABS (s
);
3179 /* Only match "--" as part of a base expression. In other contexts "--X"
3180 is a double negative. */
3181 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3185 SKIP_SPACE_TABS (s
);
3188 /* Allow a channel specifier because that leads to better error messages
3189 than treating something like "$vf0x++" as an expression. */
3190 if (!mips_parse_register (&s
, ®no
, &channels
))
3194 mips_add_token (&token
, OT_CHAR
);
3199 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3202 token
.u
.regno
= regno
;
3203 mips_add_token (&token
, OT_REG
);
3207 token
.u
.channels
= channels
;
3208 mips_add_token (&token
, OT_CHANNELS
);
3211 /* For consistency, only match "++" as part of base expressions too. */
3212 SKIP_SPACE_TABS (s
);
3213 if (s
[0] == '+' && s
[1] == '+')
3217 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3223 /* Parse one or more tokens from S. Return a pointer to the first
3224 unconsumed character on success. Return null if an error was found
3225 and store the error text in insn_error. FLOAT_FORMAT is as for
3226 mips_parse_arguments. */
3229 mips_parse_argument_token (char *s
, char float_format
)
3231 char *end
, *save_in
;
3233 unsigned int regno1
, regno2
, channels
;
3234 struct mips_operand_token token
;
3236 /* First look for "($reg", since we want to treat that as an
3237 OT_CHAR and OT_REG rather than an expression. */
3238 end
= mips_parse_base_start (s
);
3242 /* Handle other characters that end up as OT_CHARs. */
3243 if (*s
== ')' || *s
== ',')
3246 mips_add_token (&token
, OT_CHAR
);
3251 /* Handle tokens that start with a register. */
3252 if (mips_parse_register (&s
, ®no1
, &channels
))
3256 /* A register and a VU0 channel suffix. */
3257 token
.u
.regno
= regno1
;
3258 mips_add_token (&token
, OT_REG
);
3260 token
.u
.channels
= channels
;
3261 mips_add_token (&token
, OT_CHANNELS
);
3265 SKIP_SPACE_TABS (s
);
3268 /* A register range. */
3270 SKIP_SPACE_TABS (s
);
3271 if (!mips_parse_register (&s
, ®no2
, NULL
))
3273 set_insn_error (0, _("invalid register range"));
3277 token
.u
.reg_range
.regno1
= regno1
;
3278 token
.u
.reg_range
.regno2
= regno2
;
3279 mips_add_token (&token
, OT_REG_RANGE
);
3283 /* Add the register itself. */
3284 token
.u
.regno
= regno1
;
3285 mips_add_token (&token
, OT_REG
);
3287 /* Check for a vector index. */
3291 SKIP_SPACE_TABS (s
);
3292 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3293 mips_add_token (&token
, OT_REG_INDEX
);
3296 expressionS element
;
3298 my_getExpression (&element
, s
);
3299 if (element
.X_op
!= O_constant
)
3301 set_insn_error (0, _("vector element must be constant"));
3305 token
.u
.index
= element
.X_add_number
;
3306 mips_add_token (&token
, OT_INTEGER_INDEX
);
3308 SKIP_SPACE_TABS (s
);
3311 set_insn_error (0, _("missing `]'"));
3321 /* First try to treat expressions as floats. */
3322 save_in
= input_line_pointer
;
3323 input_line_pointer
= s
;
3324 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3325 &token
.u
.flt
.length
);
3326 end
= input_line_pointer
;
3327 input_line_pointer
= save_in
;
3330 set_insn_error (0, err
);
3335 mips_add_token (&token
, OT_FLOAT
);
3340 /* Treat everything else as an integer expression. */
3341 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3342 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3343 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3344 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3346 mips_add_token (&token
, OT_INTEGER
);
3350 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3351 if expressions should be treated as 32-bit floating-point constants,
3352 'd' if they should be treated as 64-bit floating-point constants,
3353 or 0 if they should be treated as integer expressions (the usual case).
3355 Return a list of tokens on success, otherwise return 0. The caller
3356 must obstack_free the list after use. */
3358 static struct mips_operand_token
*
3359 mips_parse_arguments (char *s
, char float_format
)
3361 struct mips_operand_token token
;
3363 SKIP_SPACE_TABS (s
);
3366 s
= mips_parse_argument_token (s
, float_format
);
3369 obstack_free (&mips_operand_tokens
,
3370 obstack_finish (&mips_operand_tokens
));
3373 SKIP_SPACE_TABS (s
);
3375 mips_add_token (&token
, OT_END
);
3376 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3379 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3380 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3383 is_opcode_valid (const struct mips_opcode
*mo
)
3385 int isa
= mips_opts
.isa
;
3386 int ase
= mips_opts
.ase
;
3390 if (ISA_HAS_64BIT_REGS (isa
))
3391 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3392 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3393 ase
|= mips_ases
[i
].flags64
;
3395 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3398 /* Check whether the instruction or macro requires single-precision or
3399 double-precision floating-point support. Note that this information is
3400 stored differently in the opcode table for insns and macros. */
3401 if (mo
->pinfo
== INSN_MACRO
)
3403 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3404 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3408 fp_s
= mo
->pinfo
& FP_S
;
3409 fp_d
= mo
->pinfo
& FP_D
;
3412 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3415 if (fp_s
&& mips_opts
.soft_float
)
3421 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3422 selected ISA and architecture. */
3425 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3427 int isa
= mips_opts
.isa
;
3428 int ase
= mips_opts
.ase
;
3431 if (ISA_HAS_64BIT_REGS (isa
))
3432 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3433 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3434 ase
|= mips_ases
[i
].flags64
;
3436 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3439 /* Return TRUE if the size of the microMIPS opcode MO matches one
3440 explicitly requested. Always TRUE in the standard MIPS mode.
3441 Use is_size_valid_16 for MIPS16 opcodes. */
3444 is_size_valid (const struct mips_opcode
*mo
)
3446 if (!mips_opts
.micromips
)
3449 if (mips_opts
.insn32
)
3451 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3453 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3456 if (!forced_insn_length
)
3458 if (mo
->pinfo
== INSN_MACRO
)
3460 return forced_insn_length
== micromips_insn_length (mo
);
3463 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3464 explicitly requested. */
3467 is_size_valid_16 (const struct mips_opcode
*mo
)
3469 if (!forced_insn_length
)
3471 if (mo
->pinfo
== INSN_MACRO
)
3473 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3475 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3480 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3481 of the preceding instruction. Always TRUE in the standard MIPS mode.
3483 We don't accept macros in 16-bit delay slots to avoid a case where
3484 a macro expansion fails because it relies on a preceding 32-bit real
3485 instruction to have matched and does not handle the operands correctly.
3486 The only macros that may expand to 16-bit instructions are JAL that
3487 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3488 and BGT (that likewise cannot be placed in a delay slot) that decay to
3489 a NOP. In all these cases the macros precede any corresponding real
3490 instruction definitions in the opcode table, so they will match in the
3491 second pass where the size of the delay slot is ignored and therefore
3492 produce correct code. */
3495 is_delay_slot_valid (const struct mips_opcode
*mo
)
3497 if (!mips_opts
.micromips
)
3500 if (mo
->pinfo
== INSN_MACRO
)
3501 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3502 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3503 && micromips_insn_length (mo
) != 4)
3505 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3506 && micromips_insn_length (mo
) != 2)
3512 /* For consistency checking, verify that all bits of OPCODE are specified
3513 either by the match/mask part of the instruction definition, or by the
3514 operand list. Also build up a list of operands in OPERANDS.
3516 INSN_BITS says which bits of the instruction are significant.
3517 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3518 provides the mips_operand description of each operand. DECODE_OPERAND
3519 is null for MIPS16 instructions. */
3522 validate_mips_insn (const struct mips_opcode
*opcode
,
3523 unsigned long insn_bits
,
3524 const struct mips_operand
*(*decode_operand
) (const char *),
3525 struct mips_operand_array
*operands
)
3528 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3529 const struct mips_operand
*operand
;
3531 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3532 if ((mask
& opcode
->match
) != opcode
->match
)
3534 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3535 opcode
->name
, opcode
->args
);
3540 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3541 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3542 for (s
= opcode
->args
; *s
; ++s
)
3555 if (!decode_operand
)
3556 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3558 operand
= decode_operand (s
);
3559 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3561 as_bad (_("internal: unknown operand type: %s %s"),
3562 opcode
->name
, opcode
->args
);
3565 gas_assert (opno
< MAX_OPERANDS
);
3566 operands
->operand
[opno
] = operand
;
3567 if (!decode_operand
&& operand
3568 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3569 && mips_opcode_32bit_p (opcode
))
3570 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3571 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3573 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3574 if (operand
->type
== OP_MDMX_IMM_REG
)
3575 /* Bit 5 is the format selector (OB vs QH). The opcode table
3576 has separate entries for each format. */
3577 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3578 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3579 used_bits
&= ~(mask
& 0x700);
3580 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3581 operand field that cannot be fully described with LSB/SIZE. */
3582 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3583 used_bits
&= ~0x6000;
3585 /* Skip prefix characters. */
3586 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3591 doubled
= used_bits
& mask
& insn_bits
;
3594 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3595 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3599 undefined
= ~used_bits
& insn_bits
;
3600 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3602 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3603 undefined
, opcode
->name
, opcode
->args
);
3606 used_bits
&= ~insn_bits
;
3609 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3610 used_bits
, opcode
->name
, opcode
->args
);
3616 /* The MIPS16 version of validate_mips_insn. */
3619 validate_mips16_insn (const struct mips_opcode
*opcode
,
3620 struct mips_operand_array
*operands
)
3622 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3624 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3627 /* The microMIPS version of validate_mips_insn. */
3630 validate_micromips_insn (const struct mips_opcode
*opc
,
3631 struct mips_operand_array
*operands
)
3633 unsigned long insn_bits
;
3634 unsigned long major
;
3635 unsigned int length
;
3637 if (opc
->pinfo
== INSN_MACRO
)
3638 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3641 length
= micromips_insn_length (opc
);
3642 if (length
!= 2 && length
!= 4)
3644 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3645 "%s %s"), length
, opc
->name
, opc
->args
);
3648 major
= opc
->match
>> (10 + 8 * (length
- 2));
3649 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3650 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3652 as_bad (_("internal error: bad microMIPS opcode "
3653 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3657 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3658 insn_bits
= 1 << 4 * length
;
3659 insn_bits
<<= 4 * length
;
3661 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3665 /* This function is called once, at assembler startup time. It should set up
3666 all the tables, etc. that the MD part of the assembler will need. */
3674 if (mips_pic
!= NO_PIC
)
3676 if (g_switch_seen
&& g_switch_value
!= 0)
3677 as_bad (_("-G may not be used in position-independent code"));
3680 else if (mips_abicalls
)
3682 if (g_switch_seen
&& g_switch_value
!= 0)
3683 as_bad (_("-G may not be used with abicalls"));
3687 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3688 as_warn (_("could not set architecture and machine"));
3690 op_hash
= str_htab_create ();
3692 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3693 for (i
= 0; i
< NUMOPCODES
;)
3695 const char *name
= mips_opcodes
[i
].name
;
3697 str_hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3700 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3701 decode_mips_operand
, &mips_operands
[i
]))
3704 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3706 create_insn (&nop_insn
, mips_opcodes
+ i
);
3707 if (mips_fix_loongson2f_nop
)
3708 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3709 nop_insn
.fixed_p
= 1;
3712 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3713 create_insn (&sync_insn
, mips_opcodes
+ i
);
3717 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3720 mips16_op_hash
= str_htab_create ();
3721 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3722 bfd_mips16_num_opcodes
);
3725 while (i
< bfd_mips16_num_opcodes
)
3727 const char *name
= mips16_opcodes
[i
].name
;
3729 str_hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3732 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3734 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3736 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3737 mips16_nop_insn
.fixed_p
= 1;
3741 while (i
< bfd_mips16_num_opcodes
3742 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3745 micromips_op_hash
= str_htab_create ();
3746 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3747 bfd_micromips_num_opcodes
);
3750 while (i
< bfd_micromips_num_opcodes
)
3752 const char *name
= micromips_opcodes
[i
].name
;
3754 str_hash_insert (micromips_op_hash
, name
,
3755 (void *) µmips_opcodes
[i
]);
3758 struct mips_cl_insn
*micromips_nop_insn
;
3760 if (!validate_micromips_insn (µmips_opcodes
[i
],
3761 µmips_operands
[i
]))
3764 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3766 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3767 micromips_nop_insn
= µmips_nop16_insn
;
3768 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3769 micromips_nop_insn
= µmips_nop32_insn
;
3773 if (micromips_nop_insn
->insn_mo
== NULL
3774 && strcmp (name
, "nop") == 0)
3776 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3777 micromips_nop_insn
->fixed_p
= 1;
3781 while (++i
< bfd_micromips_num_opcodes
3782 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3786 as_fatal (_("broken assembler, no assembly attempted"));
3788 /* We add all the general register names to the symbol table. This
3789 helps us detect invalid uses of them. */
3790 for (i
= 0; reg_names
[i
].name
; i
++)
3791 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3792 reg_names
[i
].num
, /* & RNUM_MASK, */
3793 &zero_address_frag
));
3795 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3796 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3797 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3798 &zero_address_frag
));
3800 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3801 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3802 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3803 &zero_address_frag
));
3805 for (i
= 0; i
< 32; i
++)
3809 /* R5900 VU0 floating-point register. */
3810 sprintf (regname
, "$vf%d", i
);
3811 symbol_table_insert (symbol_new (regname
, reg_section
,
3812 RTYPE_VF
| i
, &zero_address_frag
));
3814 /* R5900 VU0 integer register. */
3815 sprintf (regname
, "$vi%d", i
);
3816 symbol_table_insert (symbol_new (regname
, reg_section
,
3817 RTYPE_VI
| i
, &zero_address_frag
));
3820 sprintf (regname
, "$w%d", i
);
3821 symbol_table_insert (symbol_new (regname
, reg_section
,
3822 RTYPE_MSA
| i
, &zero_address_frag
));
3825 obstack_init (&mips_operand_tokens
);
3827 mips_no_prev_insn ();
3830 mips_cprmask
[0] = 0;
3831 mips_cprmask
[1] = 0;
3832 mips_cprmask
[2] = 0;
3833 mips_cprmask
[3] = 0;
3835 /* set the default alignment for the text section (2**2) */
3836 record_alignment (text_section
, 2);
3838 bfd_set_gp_size (stdoutput
, g_switch_value
);
3840 /* On a native system other than VxWorks, sections must be aligned
3841 to 16 byte boundaries. When configured for an embedded ELF
3842 target, we don't bother. */
3843 if (strncmp (TARGET_OS
, "elf", 3) != 0
3844 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3846 bfd_set_section_alignment (text_section
, 4);
3847 bfd_set_section_alignment (data_section
, 4);
3848 bfd_set_section_alignment (bss_section
, 4);
3851 /* Create a .reginfo section for register masks and a .mdebug
3852 section for debugging information. */
3860 subseg
= now_subseg
;
3862 /* The ABI says this section should be loaded so that the
3863 running program can access it. However, we don't load it
3864 if we are configured for an embedded target. */
3865 flags
= SEC_READONLY
| SEC_DATA
;
3866 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3867 flags
|= SEC_ALLOC
| SEC_LOAD
;
3869 if (mips_abi
!= N64_ABI
)
3871 sec
= subseg_new (".reginfo", (subsegT
) 0);
3873 bfd_set_section_flags (sec
, flags
);
3874 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3876 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3880 /* The 64-bit ABI uses a .MIPS.options section rather than
3881 .reginfo section. */
3882 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3883 bfd_set_section_flags (sec
, flags
);
3884 bfd_set_section_alignment (sec
, 3);
3886 /* Set up the option header. */
3888 Elf_Internal_Options opthdr
;
3891 opthdr
.kind
= ODK_REGINFO
;
3892 opthdr
.size
= (sizeof (Elf_External_Options
)
3893 + sizeof (Elf64_External_RegInfo
));
3896 f
= frag_more (sizeof (Elf_External_Options
));
3897 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3898 (Elf_External_Options
*) f
);
3900 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3904 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3905 bfd_set_section_flags (sec
,
3906 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3907 bfd_set_section_alignment (sec
, 3);
3908 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3910 if (ECOFF_DEBUGGING
)
3912 sec
= subseg_new (".mdebug", (subsegT
) 0);
3913 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3914 bfd_set_section_alignment (sec
, 2);
3916 else if (mips_flag_pdr
)
3918 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3919 bfd_set_section_flags (pdr_seg
,
3920 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3921 bfd_set_section_alignment (pdr_seg
, 2);
3924 subseg_set (seg
, subseg
);
3927 if (mips_fix_vr4120
)
3928 init_vr4120_conflicts ();
3932 fpabi_incompatible_with (int fpabi
, const char *what
)
3934 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3935 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3939 fpabi_requires (int fpabi
, const char *what
)
3941 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3942 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3945 /* Check -mabi and register sizes against the specified FP ABI. */
3947 check_fpabi (int fpabi
)
3951 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3952 if (file_mips_opts
.soft_float
)
3953 fpabi_incompatible_with (fpabi
, "softfloat");
3954 else if (file_mips_opts
.single_float
)
3955 fpabi_incompatible_with (fpabi
, "singlefloat");
3956 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3957 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3958 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3959 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3962 case Val_GNU_MIPS_ABI_FP_XX
:
3963 if (mips_abi
!= O32_ABI
)
3964 fpabi_requires (fpabi
, "-mabi=32");
3965 else if (file_mips_opts
.soft_float
)
3966 fpabi_incompatible_with (fpabi
, "softfloat");
3967 else if (file_mips_opts
.single_float
)
3968 fpabi_incompatible_with (fpabi
, "singlefloat");
3969 else if (file_mips_opts
.fp
!= 0)
3970 fpabi_requires (fpabi
, "fp=xx");
3973 case Val_GNU_MIPS_ABI_FP_64A
:
3974 case Val_GNU_MIPS_ABI_FP_64
:
3975 if (mips_abi
!= O32_ABI
)
3976 fpabi_requires (fpabi
, "-mabi=32");
3977 else if (file_mips_opts
.soft_float
)
3978 fpabi_incompatible_with (fpabi
, "softfloat");
3979 else if (file_mips_opts
.single_float
)
3980 fpabi_incompatible_with (fpabi
, "singlefloat");
3981 else if (file_mips_opts
.fp
!= 64)
3982 fpabi_requires (fpabi
, "fp=64");
3983 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3984 fpabi_incompatible_with (fpabi
, "nooddspreg");
3985 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3986 fpabi_requires (fpabi
, "nooddspreg");
3989 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3990 if (file_mips_opts
.soft_float
)
3991 fpabi_incompatible_with (fpabi
, "softfloat");
3992 else if (!file_mips_opts
.single_float
)
3993 fpabi_requires (fpabi
, "singlefloat");
3996 case Val_GNU_MIPS_ABI_FP_SOFT
:
3997 if (!file_mips_opts
.soft_float
)
3998 fpabi_requires (fpabi
, "softfloat");
4001 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4002 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4003 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4006 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4007 /* Silently ignore compatibility value. */
4011 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4012 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4017 /* Perform consistency checks on the current options. */
4020 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4022 /* Check the size of integer registers agrees with the ABI and ISA. */
4023 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4024 as_bad (_("`gp=64' used with a 32-bit processor"));
4026 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4027 as_bad (_("`gp=32' used with a 64-bit ABI"));
4029 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4030 as_bad (_("`gp=64' used with a 32-bit ABI"));
4032 /* Check the size of the float registers agrees with the ABI and ISA. */
4036 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4037 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4038 else if (opts
->single_float
== 1)
4039 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4042 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4043 as_bad (_("`fp=64' used with a 32-bit fpu"));
4045 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4046 && !ISA_HAS_MXHC1 (opts
->isa
))
4047 as_warn (_("`fp=64' used with a 32-bit ABI"));
4051 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4052 as_warn (_("`fp=32' used with a 64-bit ABI"));
4053 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4054 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4057 as_bad (_("Unknown size of floating point registers"));
4061 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4062 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4064 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4065 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4066 else if (ISA_IS_R6 (opts
->isa
)
4067 && (opts
->micromips
== 1
4068 || opts
->mips16
== 1))
4069 as_fatal (_("`%s' cannot be used with `%s'"),
4070 opts
->micromips
? "micromips" : "mips16",
4071 mips_cpu_info_from_isa (opts
->isa
)->name
);
4073 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4074 as_fatal (_("branch relaxation is not supported in `%s'"),
4075 mips_cpu_info_from_isa (opts
->isa
)->name
);
4078 /* Perform consistency checks on the module level options exactly once.
4079 This is a deferred check that happens:
4080 at the first .set directive
4081 or, at the first pseudo op that generates code (inc .dc.a)
4082 or, at the first instruction
4086 file_mips_check_options (void)
4088 if (file_mips_opts_checked
)
4091 /* The following code determines the register size.
4092 Similar code was added to GCC 3.3 (see override_options() in
4093 config/mips/mips.c). The GAS and GCC code should be kept in sync
4094 as much as possible. */
4096 if (file_mips_opts
.gp
< 0)
4098 /* Infer the integer register size from the ABI and processor.
4099 Restrict ourselves to 32-bit registers if that's all the
4100 processor has, or if the ABI cannot handle 64-bit registers. */
4101 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4102 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4106 if (file_mips_opts
.fp
< 0)
4108 /* No user specified float register size.
4109 ??? GAS treats single-float processors as though they had 64-bit
4110 float registers (although it complains when double-precision
4111 instructions are used). As things stand, saying they have 32-bit
4112 registers would lead to spurious "register must be even" messages.
4113 So here we assume float registers are never smaller than the
4115 if (file_mips_opts
.gp
== 64)
4116 /* 64-bit integer registers implies 64-bit float registers. */
4117 file_mips_opts
.fp
= 64;
4118 else if ((file_mips_opts
.ase
& FP64_ASES
)
4119 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4120 /* Handle ASEs that require 64-bit float registers, if possible. */
4121 file_mips_opts
.fp
= 64;
4122 else if (ISA_IS_R6 (mips_opts
.isa
))
4123 /* R6 implies 64-bit float registers. */
4124 file_mips_opts
.fp
= 64;
4126 /* 32-bit float registers. */
4127 file_mips_opts
.fp
= 32;
4130 /* Disable operations on odd-numbered floating-point registers by default
4131 when using the FPXX ABI. */
4132 if (file_mips_opts
.oddspreg
< 0)
4134 if (file_mips_opts
.fp
== 0)
4135 file_mips_opts
.oddspreg
= 0;
4137 file_mips_opts
.oddspreg
= 1;
4140 /* End of GCC-shared inference code. */
4142 /* This flag is set when we have a 64-bit capable CPU but use only
4143 32-bit wide registers. Note that EABI does not use it. */
4144 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4145 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4146 || mips_abi
== O32_ABI
))
4149 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4150 as_bad (_("trap exception not supported at ISA 1"));
4152 /* If the selected architecture includes support for ASEs, enable
4153 generation of code for them. */
4154 if (file_mips_opts
.mips16
== -1)
4155 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4156 if (file_mips_opts
.micromips
== -1)
4157 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4160 if (mips_nan2008
== -1)
4161 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4162 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4163 as_fatal (_("`%s' does not support legacy NaN"),
4164 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4166 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4167 being selected implicitly. */
4168 if (file_mips_opts
.fp
!= 64)
4169 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4171 /* If the user didn't explicitly select or deselect a particular ASE,
4172 use the default setting for the CPU. */
4173 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4175 /* Set up the current options. These may change throughout assembly. */
4176 mips_opts
= file_mips_opts
;
4178 mips_check_isa_supports_ases ();
4179 mips_check_options (&file_mips_opts
, TRUE
);
4180 file_mips_opts_checked
= TRUE
;
4182 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4183 as_warn (_("could not set architecture and machine"));
4187 md_assemble (char *str
)
4189 struct mips_cl_insn insn
;
4190 bfd_reloc_code_real_type unused_reloc
[3]
4191 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4193 file_mips_check_options ();
4195 imm_expr
.X_op
= O_absent
;
4196 offset_expr
.X_op
= O_absent
;
4197 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4198 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4199 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4201 mips_mark_labels ();
4202 mips_assembling_insn
= TRUE
;
4203 clear_insn_error ();
4205 if (mips_opts
.mips16
)
4206 mips16_ip (str
, &insn
);
4209 mips_ip (str
, &insn
);
4210 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4211 str
, insn
.insn_opcode
));
4215 report_insn_error (str
);
4216 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4219 if (mips_opts
.mips16
)
4220 mips16_macro (&insn
);
4227 if (offset_expr
.X_op
!= O_absent
)
4228 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4230 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4233 mips_assembling_insn
= FALSE
;
4236 /* Convenience functions for abstracting away the differences between
4237 MIPS16 and non-MIPS16 relocations. */
4239 static inline bfd_boolean
4240 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4244 case BFD_RELOC_MIPS16_JMP
:
4245 case BFD_RELOC_MIPS16_GPREL
:
4246 case BFD_RELOC_MIPS16_GOT16
:
4247 case BFD_RELOC_MIPS16_CALL16
:
4248 case BFD_RELOC_MIPS16_HI16_S
:
4249 case BFD_RELOC_MIPS16_HI16
:
4250 case BFD_RELOC_MIPS16_LO16
:
4251 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4259 static inline bfd_boolean
4260 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4264 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4265 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4266 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4267 case BFD_RELOC_MICROMIPS_GPREL16
:
4268 case BFD_RELOC_MICROMIPS_JMP
:
4269 case BFD_RELOC_MICROMIPS_HI16
:
4270 case BFD_RELOC_MICROMIPS_HI16_S
:
4271 case BFD_RELOC_MICROMIPS_LO16
:
4272 case BFD_RELOC_MICROMIPS_LITERAL
:
4273 case BFD_RELOC_MICROMIPS_GOT16
:
4274 case BFD_RELOC_MICROMIPS_CALL16
:
4275 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4276 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4277 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4278 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4279 case BFD_RELOC_MICROMIPS_SUB
:
4280 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4281 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4282 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4283 case BFD_RELOC_MICROMIPS_HIGHEST
:
4284 case BFD_RELOC_MICROMIPS_HIGHER
:
4285 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4286 case BFD_RELOC_MICROMIPS_JALR
:
4294 static inline bfd_boolean
4295 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4297 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4300 static inline bfd_boolean
4301 b_reloc_p (bfd_reloc_code_real_type reloc
)
4303 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4304 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4305 || reloc
== BFD_RELOC_16_PCREL_S2
4306 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4307 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4308 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4309 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4312 static inline bfd_boolean
4313 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4315 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4316 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4319 static inline bfd_boolean
4320 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4322 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4323 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4326 static inline bfd_boolean
4327 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4329 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4330 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4333 static inline bfd_boolean
4334 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4336 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4339 static inline bfd_boolean
4340 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4342 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4343 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4346 /* Return true if RELOC is a PC-relative relocation that does not have
4347 full address range. */
4349 static inline bfd_boolean
4350 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4354 case BFD_RELOC_16_PCREL_S2
:
4355 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4356 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4357 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4358 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4359 case BFD_RELOC_MIPS_21_PCREL_S2
:
4360 case BFD_RELOC_MIPS_26_PCREL_S2
:
4361 case BFD_RELOC_MIPS_18_PCREL_S3
:
4362 case BFD_RELOC_MIPS_19_PCREL_S2
:
4365 case BFD_RELOC_32_PCREL
:
4366 case BFD_RELOC_HI16_S_PCREL
:
4367 case BFD_RELOC_LO16_PCREL
:
4368 return HAVE_64BIT_ADDRESSES
;
4375 /* Return true if the given relocation might need a matching %lo().
4376 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4377 need a matching %lo() when applied to local symbols. */
4379 static inline bfd_boolean
4380 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4382 return (HAVE_IN_PLACE_ADDENDS
4383 && (hi16_reloc_p (reloc
)
4384 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4385 all GOT16 relocations evaluate to "G". */
4386 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4389 /* Return the type of %lo() reloc needed by RELOC, given that
4390 reloc_needs_lo_p. */
4392 static inline bfd_reloc_code_real_type
4393 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4395 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4396 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4400 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4403 static inline bfd_boolean
4404 fixup_has_matching_lo_p (fixS
*fixp
)
4406 return (fixp
->fx_next
!= NULL
4407 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4408 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4409 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4412 /* Move all labels in LABELS to the current insertion point. TEXT_P
4413 says whether the labels refer to text or data. */
4416 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4418 struct insn_label_list
*l
;
4421 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4423 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4424 symbol_set_frag (l
->label
, frag_now
);
4425 val
= (valueT
) frag_now_fix ();
4426 /* MIPS16/microMIPS text labels are stored as odd.
4427 We just carry the ISA mode bit forward. */
4428 if (text_p
&& HAVE_CODE_COMPRESSION
)
4429 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4430 S_SET_VALUE (l
->label
, val
);
4434 /* Move all labels in insn_labels to the current insertion point
4435 and treat them as text labels. */
4438 mips_move_text_labels (void)
4440 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4443 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4446 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4448 bfd_boolean linkonce
= FALSE
;
4449 segT symseg
= S_GET_SEGMENT (sym
);
4451 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4453 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4455 /* The GNU toolchain uses an extension for ELF: a section
4456 beginning with the magic string .gnu.linkonce is a
4457 linkonce section. */
4458 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4459 sizeof ".gnu.linkonce" - 1) == 0)
4465 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4466 linker to handle them specially, such as generating jalx instructions
4467 when needed. We also make them odd for the duration of the assembly,
4468 in order to generate the right sort of code. We will make them even
4469 in the adjust_symtab routine, while leaving them marked. This is
4470 convenient for the debugger and the disassembler. The linker knows
4471 to make them odd again. */
4474 mips_compressed_mark_label (symbolS
*label
)
4476 gas_assert (HAVE_CODE_COMPRESSION
);
4478 if (mips_opts
.mips16
)
4479 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4481 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4482 if ((S_GET_VALUE (label
) & 1) == 0
4483 /* Don't adjust the address if the label is global or weak, or
4484 in a link-once section, since we'll be emitting symbol reloc
4485 references to it which will be patched up by the linker, and
4486 the final value of the symbol may or may not be MIPS16/microMIPS. */
4487 && !S_IS_WEAK (label
)
4488 && !S_IS_EXTERNAL (label
)
4489 && !s_is_linkonce (label
, now_seg
))
4490 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4493 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4496 mips_compressed_mark_labels (void)
4498 struct insn_label_list
*l
;
4500 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4501 mips_compressed_mark_label (l
->label
);
4504 /* End the current frag. Make it a variant frag and record the
4508 relax_close_frag (void)
4510 mips_macro_warning
.first_frag
= frag_now
;
4511 frag_var (rs_machine_dependent
, 0, 0,
4512 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4513 mips_pic
!= NO_PIC
),
4514 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4516 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4517 mips_relax
.first_fixup
= 0;
4520 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4521 See the comment above RELAX_ENCODE for more details. */
4524 relax_start (symbolS
*symbol
)
4526 gas_assert (mips_relax
.sequence
== 0);
4527 mips_relax
.sequence
= 1;
4528 mips_relax
.symbol
= symbol
;
4531 /* Start generating the second version of a relaxable sequence.
4532 See the comment above RELAX_ENCODE for more details. */
4537 gas_assert (mips_relax
.sequence
== 1);
4538 mips_relax
.sequence
= 2;
4541 /* End the current relaxable sequence. */
4546 gas_assert (mips_relax
.sequence
== 2);
4547 relax_close_frag ();
4548 mips_relax
.sequence
= 0;
4551 /* Return true if IP is a delayed branch or jump. */
4553 static inline bfd_boolean
4554 delayed_branch_p (const struct mips_cl_insn
*ip
)
4556 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4557 | INSN_COND_BRANCH_DELAY
4558 | INSN_COND_BRANCH_LIKELY
)) != 0;
4561 /* Return true if IP is a compact branch or jump. */
4563 static inline bfd_boolean
4564 compact_branch_p (const struct mips_cl_insn
*ip
)
4566 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4567 | INSN2_COND_BRANCH
)) != 0;
4570 /* Return true if IP is an unconditional branch or jump. */
4572 static inline bfd_boolean
4573 uncond_branch_p (const struct mips_cl_insn
*ip
)
4575 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4576 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4579 /* Return true if IP is a branch-likely instruction. */
4581 static inline bfd_boolean
4582 branch_likely_p (const struct mips_cl_insn
*ip
)
4584 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4587 /* Return the type of nop that should be used to fill the delay slot
4588 of delayed branch IP. */
4590 static struct mips_cl_insn
*
4591 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4593 if (mips_opts
.micromips
4594 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4595 return µmips_nop32_insn
;
4599 /* Return a mask that has bit N set if OPCODE reads the register(s)
4603 insn_read_mask (const struct mips_opcode
*opcode
)
4605 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4608 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4612 insn_write_mask (const struct mips_opcode
*opcode
)
4614 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4617 /* Return a mask of the registers specified by operand OPERAND of INSN.
4618 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4622 operand_reg_mask (const struct mips_cl_insn
*insn
,
4623 const struct mips_operand
*operand
,
4624 unsigned int type_mask
)
4626 unsigned int uval
, vsel
;
4628 switch (operand
->type
)
4635 case OP_ADDIUSP_INT
:
4636 case OP_ENTRY_EXIT_LIST
:
4637 case OP_REPEAT_DEST_REG
:
4638 case OP_REPEAT_PREV_REG
:
4641 case OP_VU0_MATCH_SUFFIX
:
4649 case OP_OPTIONAL_REG
:
4651 const struct mips_reg_operand
*reg_op
;
4653 reg_op
= (const struct mips_reg_operand
*) operand
;
4654 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4656 uval
= insn_extract_operand (insn
, operand
);
4657 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4662 const struct mips_reg_pair_operand
*pair_op
;
4664 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4665 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4667 uval
= insn_extract_operand (insn
, operand
);
4668 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4671 case OP_CLO_CLZ_DEST
:
4672 if (!(type_mask
& (1 << OP_REG_GP
)))
4674 uval
= insn_extract_operand (insn
, operand
);
4675 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4678 if (!(type_mask
& (1 << OP_REG_GP
)))
4680 uval
= insn_extract_operand (insn
, operand
);
4681 gas_assert ((uval
& 31) == (uval
>> 5));
4682 return 1 << (uval
& 31);
4685 case OP_NON_ZERO_REG
:
4686 if (!(type_mask
& (1 << OP_REG_GP
)))
4688 uval
= insn_extract_operand (insn
, operand
);
4689 return 1 << (uval
& 31);
4691 case OP_LWM_SWM_LIST
:
4694 case OP_SAVE_RESTORE_LIST
:
4697 case OP_MDMX_IMM_REG
:
4698 if (!(type_mask
& (1 << OP_REG_VEC
)))
4700 uval
= insn_extract_operand (insn
, operand
);
4702 if ((vsel
& 0x18) == 0x18)
4704 return 1 << (uval
& 31);
4707 if (!(type_mask
& (1 << OP_REG_GP
)))
4709 return 1 << insn_extract_operand (insn
, operand
);
4714 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4715 where bit N of OPNO_MASK is set if operand N should be included.
4716 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4720 insn_reg_mask (const struct mips_cl_insn
*insn
,
4721 unsigned int type_mask
, unsigned int opno_mask
)
4723 unsigned int opno
, reg_mask
;
4727 while (opno_mask
!= 0)
4730 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4737 /* Return the mask of core registers that IP reads. */
4740 gpr_read_mask (const struct mips_cl_insn
*ip
)
4742 unsigned long pinfo
, pinfo2
;
4745 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4746 pinfo
= ip
->insn_mo
->pinfo
;
4747 pinfo2
= ip
->insn_mo
->pinfo2
;
4748 if (pinfo
& INSN_UDI
)
4750 /* UDI instructions have traditionally been assumed to read RS
4752 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4753 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4755 if (pinfo
& INSN_READ_GPR_24
)
4757 if (pinfo2
& INSN2_READ_GPR_16
)
4759 if (pinfo2
& INSN2_READ_SP
)
4761 if (pinfo2
& INSN2_READ_GPR_31
)
4763 /* Don't include register 0. */
4767 /* Return the mask of core registers that IP writes. */
4770 gpr_write_mask (const struct mips_cl_insn
*ip
)
4772 unsigned long pinfo
, pinfo2
;
4775 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4776 pinfo
= ip
->insn_mo
->pinfo
;
4777 pinfo2
= ip
->insn_mo
->pinfo2
;
4778 if (pinfo
& INSN_WRITE_GPR_24
)
4780 if (pinfo
& INSN_WRITE_GPR_31
)
4782 if (pinfo
& INSN_UDI
)
4783 /* UDI instructions have traditionally been assumed to write to RD. */
4784 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4785 if (pinfo2
& INSN2_WRITE_SP
)
4787 /* Don't include register 0. */
4791 /* Return the mask of floating-point registers that IP reads. */
4794 fpr_read_mask (const struct mips_cl_insn
*ip
)
4796 unsigned long pinfo
;
4799 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4800 | (1 << OP_REG_MSA
)),
4801 insn_read_mask (ip
->insn_mo
));
4802 pinfo
= ip
->insn_mo
->pinfo
;
4803 /* Conservatively treat all operands to an FP_D instruction are doubles.
4804 (This is overly pessimistic for things like cvt.d.s.) */
4805 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4810 /* Return the mask of floating-point registers that IP writes. */
4813 fpr_write_mask (const struct mips_cl_insn
*ip
)
4815 unsigned long pinfo
;
4818 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4819 | (1 << OP_REG_MSA
)),
4820 insn_write_mask (ip
->insn_mo
));
4821 pinfo
= ip
->insn_mo
->pinfo
;
4822 /* Conservatively treat all operands to an FP_D instruction are doubles.
4823 (This is overly pessimistic for things like cvt.s.d.) */
4824 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4829 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4830 Check whether that is allowed. */
4833 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4835 const char *s
= insn
->name
;
4836 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4838 && mips_opts
.oddspreg
;
4840 if (insn
->pinfo
== INSN_MACRO
)
4841 /* Let a macro pass, we'll catch it later when it is expanded. */
4844 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4845 otherwise it depends on oddspreg. */
4846 if ((insn
->pinfo
& FP_S
)
4847 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4848 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4849 return FPR_SIZE
== 32 || oddspreg
;
4851 /* Allow odd registers for single-precision ops and double-precision if the
4852 floating-point registers are 64-bit wide. */
4853 switch (insn
->pinfo
& (FP_S
| FP_D
))
4859 return FPR_SIZE
== 64;
4864 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4865 s
= strchr (insn
->name
, '.');
4866 if (s
!= NULL
&& opnum
== 2)
4867 s
= strchr (s
+ 1, '.');
4868 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4871 return FPR_SIZE
== 64;
4874 /* Information about an instruction argument that we're trying to match. */
4875 struct mips_arg_info
4877 /* The instruction so far. */
4878 struct mips_cl_insn
*insn
;
4880 /* The first unconsumed operand token. */
4881 struct mips_operand_token
*token
;
4883 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4886 /* The 1-based argument number, for error reporting. This does not
4887 count elided optional registers, etc.. */
4890 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4891 unsigned int last_regno
;
4893 /* If the first operand was an OP_REG, this is the register that it
4894 specified, otherwise it is ILLEGAL_REG. */
4895 unsigned int dest_regno
;
4897 /* The value of the last OP_INT operand. Only used for OP_MSB,
4898 where it gives the lsb position. */
4899 unsigned int last_op_int
;
4901 /* If true, match routines should assume that no later instruction
4902 alternative matches and should therefore be as accommodating as
4903 possible. Match routines should not report errors if something
4904 is only invalid for !LAX_MATCH. */
4905 bfd_boolean lax_match
;
4907 /* True if a reference to the current AT register was seen. */
4908 bfd_boolean seen_at
;
4911 /* Record that the argument is out of range. */
4914 match_out_of_range (struct mips_arg_info
*arg
)
4916 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4919 /* Record that the argument isn't constant but needs to be. */
4922 match_not_constant (struct mips_arg_info
*arg
)
4924 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4928 /* Try to match an OT_CHAR token for character CH. Consume the token
4929 and return true on success, otherwise return false. */
4932 match_char (struct mips_arg_info
*arg
, char ch
)
4934 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4944 /* Try to get an expression from the next tokens in ARG. Consume the
4945 tokens and return true on success, storing the expression value in
4946 VALUE and relocation types in R. */
4949 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4950 bfd_reloc_code_real_type
*r
)
4952 /* If the next token is a '(' that was parsed as being part of a base
4953 expression, assume we have an elided offset. The later match will fail
4954 if this turns out to be wrong. */
4955 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4957 value
->X_op
= O_constant
;
4958 value
->X_add_number
= 0;
4959 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4963 /* Reject register-based expressions such as "0+$2" and "(($2))".
4964 For plain registers the default error seems more appropriate. */
4965 if (arg
->token
->type
== OT_INTEGER
4966 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4968 set_insn_error (arg
->argnum
, _("register value used as expression"));
4972 if (arg
->token
->type
== OT_INTEGER
)
4974 *value
= arg
->token
->u
.integer
.value
;
4975 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4981 (arg
->argnum
, _("operand %d must be an immediate expression"),
4986 /* Try to get a constant expression from the next tokens in ARG. Consume
4987 the tokens and return true on success, storing the constant value
4991 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4994 bfd_reloc_code_real_type r
[3];
4996 if (!match_expression (arg
, &ex
, r
))
4999 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5000 *value
= ex
.X_add_number
;
5003 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5004 match_out_of_range (arg
);
5006 match_not_constant (arg
);
5012 /* Return the RTYPE_* flags for a register operand of type TYPE that
5013 appears in instruction OPCODE. */
5016 convert_reg_type (const struct mips_opcode
*opcode
,
5017 enum mips_reg_operand_type type
)
5022 return RTYPE_NUM
| RTYPE_GP
;
5025 /* Allow vector register names for MDMX if the instruction is a 64-bit
5026 FPR load, store or move (including moves to and from GPRs). */
5027 if ((mips_opts
.ase
& ASE_MDMX
)
5028 && (opcode
->pinfo
& FP_D
)
5029 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5030 | INSN_COPROC_MEMORY_DELAY
5033 | INSN_STORE_MEMORY
)))
5034 return RTYPE_FPU
| RTYPE_VEC
;
5038 if (opcode
->pinfo
& (FP_D
| FP_S
))
5039 return RTYPE_CCC
| RTYPE_FCC
;
5043 if (opcode
->membership
& INSN_5400
)
5045 return RTYPE_FPU
| RTYPE_VEC
;
5051 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5052 return RTYPE_NUM
| RTYPE_CP0
;
5059 return RTYPE_NUM
| RTYPE_VI
;
5062 return RTYPE_NUM
| RTYPE_VF
;
5064 case OP_REG_R5900_I
:
5065 return RTYPE_R5900_I
;
5067 case OP_REG_R5900_Q
:
5068 return RTYPE_R5900_Q
;
5070 case OP_REG_R5900_R
:
5071 return RTYPE_R5900_R
;
5073 case OP_REG_R5900_ACC
:
5074 return RTYPE_R5900_ACC
;
5079 case OP_REG_MSA_CTRL
:
5085 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5088 check_regno (struct mips_arg_info
*arg
,
5089 enum mips_reg_operand_type type
, unsigned int regno
)
5091 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5092 arg
->seen_at
= TRUE
;
5094 if (type
== OP_REG_FP
5096 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5098 /* This was a warning prior to introducing O32 FPXX and FP64 support
5099 so maintain a warning for FP32 but raise an error for the new
5102 as_warn (_("float register should be even, was %d"), regno
);
5104 as_bad (_("float register should be even, was %d"), regno
);
5107 if (type
== OP_REG_CCC
)
5112 name
= arg
->insn
->insn_mo
->name
;
5113 length
= strlen (name
);
5114 if ((regno
& 1) != 0
5115 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5116 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5117 as_warn (_("condition code register should be even for %s, was %d"),
5120 if ((regno
& 3) != 0
5121 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5122 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5127 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5128 a register of type TYPE. Return true on success, storing the register
5129 number in *REGNO and warning about any dubious uses. */
5132 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5133 unsigned int symval
, unsigned int *regno
)
5135 if (type
== OP_REG_VEC
)
5136 symval
= mips_prefer_vec_regno (symval
);
5137 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5140 *regno
= symval
& RNUM_MASK
;
5141 check_regno (arg
, type
, *regno
);
5145 /* Try to interpret the next token in ARG as a register of type TYPE.
5146 Consume the token and return true on success, storing the register
5147 number in *REGNO. Return false on failure. */
5150 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5151 unsigned int *regno
)
5153 if (arg
->token
->type
== OT_REG
5154 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5162 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5163 Consume the token and return true on success, storing the register numbers
5164 in *REGNO1 and *REGNO2. Return false on failure. */
5167 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5168 unsigned int *regno1
, unsigned int *regno2
)
5170 if (match_reg (arg
, type
, regno1
))
5175 if (arg
->token
->type
== OT_REG_RANGE
5176 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5177 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5178 && *regno1
<= *regno2
)
5186 /* OP_INT matcher. */
5189 match_int_operand (struct mips_arg_info
*arg
,
5190 const struct mips_operand
*operand_base
)
5192 const struct mips_int_operand
*operand
;
5194 int min_val
, max_val
, factor
;
5197 operand
= (const struct mips_int_operand
*) operand_base
;
5198 factor
= 1 << operand
->shift
;
5199 min_val
= mips_int_operand_min (operand
);
5200 max_val
= mips_int_operand_max (operand
);
5202 if (operand_base
->lsb
== 0
5203 && operand_base
->size
== 16
5204 && operand
->shift
== 0
5205 && operand
->bias
== 0
5206 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5208 /* The operand can be relocated. */
5209 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5212 if (offset_expr
.X_op
== O_big
)
5214 match_out_of_range (arg
);
5218 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5219 /* Relocation operators were used. Accept the argument and
5220 leave the relocation value in offset_expr and offset_relocs
5221 for the caller to process. */
5224 if (offset_expr
.X_op
!= O_constant
)
5226 /* Accept non-constant operands if no later alternative matches,
5227 leaving it for the caller to process. */
5228 if (!arg
->lax_match
)
5230 match_not_constant (arg
);
5233 offset_reloc
[0] = BFD_RELOC_LO16
;
5237 /* Clear the global state; we're going to install the operand
5239 sval
= offset_expr
.X_add_number
;
5240 offset_expr
.X_op
= O_absent
;
5242 /* For compatibility with older assemblers, we accept
5243 0x8000-0xffff as signed 16-bit numbers when only
5244 signed numbers are allowed. */
5247 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5248 if (!arg
->lax_match
&& sval
<= max_val
)
5250 match_out_of_range (arg
);
5257 if (!match_const_int (arg
, &sval
))
5261 arg
->last_op_int
= sval
;
5263 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5265 match_out_of_range (arg
);
5269 uval
= (unsigned int) sval
>> operand
->shift
;
5270 uval
-= operand
->bias
;
5272 /* Handle -mfix-cn63xxp1. */
5274 && mips_fix_cn63xxp1
5275 && !mips_opts
.micromips
5276 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5291 /* The rest must be changed to 28. */
5296 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5300 /* OP_MAPPED_INT matcher. */
5303 match_mapped_int_operand (struct mips_arg_info
*arg
,
5304 const struct mips_operand
*operand_base
)
5306 const struct mips_mapped_int_operand
*operand
;
5307 unsigned int uval
, num_vals
;
5310 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5311 if (!match_const_int (arg
, &sval
))
5314 num_vals
= 1 << operand_base
->size
;
5315 for (uval
= 0; uval
< num_vals
; uval
++)
5316 if (operand
->int_map
[uval
] == sval
)
5318 if (uval
== num_vals
)
5320 match_out_of_range (arg
);
5324 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5328 /* OP_MSB matcher. */
5331 match_msb_operand (struct mips_arg_info
*arg
,
5332 const struct mips_operand
*operand_base
)
5334 const struct mips_msb_operand
*operand
;
5335 int min_val
, max_val
, max_high
;
5336 offsetT size
, sval
, high
;
5338 operand
= (const struct mips_msb_operand
*) operand_base
;
5339 min_val
= operand
->bias
;
5340 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5341 max_high
= operand
->opsize
;
5343 if (!match_const_int (arg
, &size
))
5346 high
= size
+ arg
->last_op_int
;
5347 sval
= operand
->add_lsb
? high
: size
;
5349 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5351 match_out_of_range (arg
);
5354 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5358 /* OP_REG matcher. */
5361 match_reg_operand (struct mips_arg_info
*arg
,
5362 const struct mips_operand
*operand_base
)
5364 const struct mips_reg_operand
*operand
;
5365 unsigned int regno
, uval
, num_vals
;
5367 operand
= (const struct mips_reg_operand
*) operand_base
;
5368 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5371 if (operand
->reg_map
)
5373 num_vals
= 1 << operand
->root
.size
;
5374 for (uval
= 0; uval
< num_vals
; uval
++)
5375 if (operand
->reg_map
[uval
] == regno
)
5377 if (num_vals
== uval
)
5383 arg
->last_regno
= regno
;
5384 if (arg
->opnum
== 1)
5385 arg
->dest_regno
= regno
;
5386 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5390 /* OP_REG_PAIR matcher. */
5393 match_reg_pair_operand (struct mips_arg_info
*arg
,
5394 const struct mips_operand
*operand_base
)
5396 const struct mips_reg_pair_operand
*operand
;
5397 unsigned int regno1
, regno2
, uval
, num_vals
;
5399 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5400 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5401 || !match_char (arg
, ',')
5402 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5405 num_vals
= 1 << operand_base
->size
;
5406 for (uval
= 0; uval
< num_vals
; uval
++)
5407 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5409 if (uval
== num_vals
)
5412 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5416 /* OP_PCREL matcher. The caller chooses the relocation type. */
5419 match_pcrel_operand (struct mips_arg_info
*arg
)
5421 bfd_reloc_code_real_type r
[3];
5423 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5426 /* OP_PERF_REG matcher. */
5429 match_perf_reg_operand (struct mips_arg_info
*arg
,
5430 const struct mips_operand
*operand
)
5434 if (!match_const_int (arg
, &sval
))
5439 || (mips_opts
.arch
== CPU_R5900
5440 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5441 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5443 set_insn_error (arg
->argnum
, _("invalid performance register"));
5447 insn_insert_operand (arg
->insn
, operand
, sval
);
5451 /* OP_ADDIUSP matcher. */
5454 match_addiusp_operand (struct mips_arg_info
*arg
,
5455 const struct mips_operand
*operand
)
5460 if (!match_const_int (arg
, &sval
))
5465 match_out_of_range (arg
);
5470 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5472 match_out_of_range (arg
);
5476 uval
= (unsigned int) sval
;
5477 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5478 insn_insert_operand (arg
->insn
, operand
, uval
);
5482 /* OP_CLO_CLZ_DEST matcher. */
5485 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5486 const struct mips_operand
*operand
)
5490 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5493 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5497 /* OP_CHECK_PREV matcher. */
5500 match_check_prev_operand (struct mips_arg_info
*arg
,
5501 const struct mips_operand
*operand_base
)
5503 const struct mips_check_prev_operand
*operand
;
5506 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5508 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5511 if (!operand
->zero_ok
&& regno
== 0)
5514 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5515 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5516 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5518 arg
->last_regno
= regno
;
5519 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5526 /* OP_SAME_RS_RT matcher. */
5529 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5530 const struct mips_operand
*operand
)
5534 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5539 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5543 arg
->last_regno
= regno
;
5545 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5549 /* OP_LWM_SWM_LIST matcher. */
5552 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5553 const struct mips_operand
*operand
)
5555 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5556 struct mips_arg_info reset
;
5559 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5563 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5568 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5571 while (match_char (arg
, ',')
5572 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5575 if (operand
->size
== 2)
5577 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5583 and any permutations of these. */
5584 if ((reglist
& 0xfff1ffff) != 0x80010000)
5587 sregs
= (reglist
>> 17) & 7;
5592 /* The list must include at least one of ra and s0-sN,
5593 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5594 which are $23 and $30 respectively.) E.g.:
5602 and any permutations of these. */
5603 if ((reglist
& 0x3f00ffff) != 0)
5606 ra
= (reglist
>> 27) & 0x10;
5607 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5610 if ((sregs
& -sregs
) != sregs
)
5613 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5617 /* OP_ENTRY_EXIT_LIST matcher. */
5620 match_entry_exit_operand (struct mips_arg_info
*arg
,
5621 const struct mips_operand
*operand
)
5624 bfd_boolean is_exit
;
5626 /* The format is the same for both ENTRY and EXIT, but the constraints
5628 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5629 mask
= (is_exit
? 7 << 3 : 0);
5632 unsigned int regno1
, regno2
;
5633 bfd_boolean is_freg
;
5635 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5637 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5642 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5645 mask
|= (5 + regno2
) << 3;
5647 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5648 mask
|= (regno2
- 3) << 3;
5649 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5650 mask
|= (regno2
- 15) << 1;
5651 else if (regno1
== RA
&& regno2
== RA
)
5656 while (match_char (arg
, ','));
5658 insn_insert_operand (arg
->insn
, operand
, mask
);
5662 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5663 the argument register mask AMASK, the number of static registers
5664 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5665 respectively, and the frame size FRAME_SIZE. */
5668 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5669 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5670 unsigned int frame_size
)
5672 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5673 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5676 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5677 argument register mask AMASK, the number of static registers saved
5678 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5679 respectively, and the frame size FRAME_SIZE. */
5682 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5683 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5684 unsigned int frame_size
)
5688 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5689 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5690 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5691 | ((frame_size
& 0xf0) << 16));
5695 /* OP_SAVE_RESTORE_LIST matcher. */
5698 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5700 unsigned int opcode
, args
, statics
, sregs
;
5701 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5702 unsigned int arg_mask
, ra
, s0
, s1
;
5705 opcode
= arg
->insn
->insn_opcode
;
5707 num_frame_sizes
= 0;
5716 unsigned int regno1
, regno2
;
5718 if (arg
->token
->type
== OT_INTEGER
)
5720 /* Handle the frame size. */
5721 if (!match_const_int (arg
, &frame_size
))
5723 num_frame_sizes
+= 1;
5727 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5730 while (regno1
<= regno2
)
5732 if (regno1
>= 4 && regno1
<= 7)
5734 if (num_frame_sizes
== 0)
5736 args
|= 1 << (regno1
- 4);
5738 /* statics $a0-$a3 */
5739 statics
|= 1 << (regno1
- 4);
5741 else if (regno1
>= 16 && regno1
<= 23)
5743 sregs
|= 1 << (regno1
- 16);
5744 else if (regno1
== 30)
5747 else if (regno1
== 31)
5748 /* Add $ra to insn. */
5758 while (match_char (arg
, ','));
5760 /* Encode args/statics combination. */
5763 else if (args
== 0xf)
5764 /* All $a0-$a3 are args. */
5765 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5766 else if (statics
== 0xf)
5767 /* All $a0-$a3 are statics. */
5768 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5771 /* Count arg registers. */
5781 /* Count static registers. */
5783 while (statics
& 0x8)
5785 statics
= (statics
<< 1) & 0xf;
5791 /* Encode args/statics. */
5792 arg_mask
= (num_args
<< 2) | num_statics
;
5795 /* Encode $s0/$s1. */
5796 if (sregs
& (1 << 0)) /* $s0 */
5798 if (sregs
& (1 << 1)) /* $s1 */
5802 /* Encode $s2-$s8. */
5812 /* Encode frame size. */
5813 if (num_frame_sizes
== 0)
5815 set_insn_error (arg
->argnum
, _("missing frame size"));
5818 if (num_frame_sizes
> 1)
5820 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5823 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5825 set_insn_error (arg
->argnum
, _("invalid frame size"));
5830 /* Finally build the instruction. */
5831 if (mips_opts
.mips16
)
5832 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5834 else if (!mips_opts
.micromips
)
5835 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5840 arg
->insn
->insn_opcode
= opcode
;
5844 /* OP_MDMX_IMM_REG matcher. */
5847 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5848 const struct mips_operand
*operand
)
5850 unsigned int regno
, uval
;
5852 const struct mips_opcode
*opcode
;
5854 /* The mips_opcode records whether this is an octobyte or quadhalf
5855 instruction. Start out with that bit in place. */
5856 opcode
= arg
->insn
->insn_mo
;
5857 uval
= mips_extract_operand (operand
, opcode
->match
);
5858 is_qh
= (uval
!= 0);
5860 if (arg
->token
->type
== OT_REG
)
5862 if ((opcode
->membership
& INSN_5400
)
5863 && strcmp (opcode
->name
, "rzu.ob") == 0)
5865 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5870 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5874 /* Check whether this is a vector register or a broadcast of
5875 a single element. */
5876 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5878 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5880 set_insn_error (arg
->argnum
, _("invalid element selector"));
5883 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5888 /* A full vector. */
5889 if ((opcode
->membership
& INSN_5400
)
5890 && (strcmp (opcode
->name
, "sll.ob") == 0
5891 || strcmp (opcode
->name
, "srl.ob") == 0))
5893 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5899 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5901 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5909 if (!match_const_int (arg
, &sval
))
5911 if (sval
< 0 || sval
> 31)
5913 match_out_of_range (arg
);
5916 uval
|= (sval
& 31);
5918 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5920 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5922 insn_insert_operand (arg
->insn
, operand
, uval
);
5926 /* OP_IMM_INDEX matcher. */
5929 match_imm_index_operand (struct mips_arg_info
*arg
,
5930 const struct mips_operand
*operand
)
5932 unsigned int max_val
;
5934 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5937 max_val
= (1 << operand
->size
) - 1;
5938 if (arg
->token
->u
.index
> max_val
)
5940 match_out_of_range (arg
);
5943 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5948 /* OP_REG_INDEX matcher. */
5951 match_reg_index_operand (struct mips_arg_info
*arg
,
5952 const struct mips_operand
*operand
)
5956 if (arg
->token
->type
!= OT_REG_INDEX
)
5959 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5962 insn_insert_operand (arg
->insn
, operand
, regno
);
5967 /* OP_PC matcher. */
5970 match_pc_operand (struct mips_arg_info
*arg
)
5972 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5980 /* OP_REG28 matcher. */
5983 match_reg28_operand (struct mips_arg_info
*arg
)
5987 if (arg
->token
->type
== OT_REG
5988 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5997 /* OP_NON_ZERO_REG matcher. */
6000 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6001 const struct mips_operand
*operand
)
6005 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6010 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6014 arg
->last_regno
= regno
;
6015 insn_insert_operand (arg
->insn
, operand
, regno
);
6019 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6020 register that we need to match. */
6023 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6027 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6030 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6031 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6032 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6034 Return the constant in IMM and OFFSET as follows:
6036 - If the constant should be loaded via memory, set IMM to O_absent and
6037 OFFSET to the memory address.
6039 - Otherwise, if the constant should be loaded into two 32-bit registers,
6040 set IMM to the O_constant to load into the high register and OFFSET
6041 to the corresponding value for the low register.
6043 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6045 These constants only appear as the last operand in an instruction,
6046 and every instruction that accepts them in any variant accepts them
6047 in all variants. This means we don't have to worry about backing out
6048 any changes if the instruction does not match. We just match
6049 unconditionally and report an error if the constant is invalid. */
6052 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6053 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6058 const char *newname
;
6059 unsigned char *data
;
6061 /* Where the constant is placed is based on how the MIPS assembler
6064 length == 4 && using_gprs -- immediate value only
6065 length == 8 && using_gprs -- .rdata or immediate value
6066 length == 4 && !using_gprs -- .lit4 or immediate value
6067 length == 8 && !using_gprs -- .lit8 or immediate value
6069 The .lit4 and .lit8 sections are only used if permitted by the
6071 if (arg
->token
->type
!= OT_FLOAT
)
6073 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6077 gas_assert (arg
->token
->u
.flt
.length
== length
);
6078 data
= arg
->token
->u
.flt
.data
;
6081 /* Handle 32-bit constants for which an immediate value is best. */
6084 || g_switch_value
< 4
6085 || (data
[0] == 0 && data
[1] == 0)
6086 || (data
[2] == 0 && data
[3] == 0)))
6088 imm
->X_op
= O_constant
;
6089 if (!target_big_endian
)
6090 imm
->X_add_number
= bfd_getl32 (data
);
6092 imm
->X_add_number
= bfd_getb32 (data
);
6093 offset
->X_op
= O_absent
;
6097 /* Handle 64-bit constants for which an immediate value is best. */
6099 && !mips_disable_float_construction
6100 /* Constants can only be constructed in GPRs and copied to FPRs if the
6101 GPRs are at least as wide as the FPRs or MTHC1 is available.
6102 Unlike most tests for 32-bit floating-point registers this check
6103 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6104 permit 64-bit moves without MXHC1.
6105 Force the constant into memory otherwise. */
6108 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6110 && ((data
[0] == 0 && data
[1] == 0)
6111 || (data
[2] == 0 && data
[3] == 0))
6112 && ((data
[4] == 0 && data
[5] == 0)
6113 || (data
[6] == 0 && data
[7] == 0)))
6115 /* The value is simple enough to load with a couple of instructions.
6116 If using 32-bit registers, set IMM to the high order 32 bits and
6117 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6119 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6121 imm
->X_op
= O_constant
;
6122 offset
->X_op
= O_constant
;
6123 if (!target_big_endian
)
6125 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6126 offset
->X_add_number
= bfd_getl32 (data
);
6130 imm
->X_add_number
= bfd_getb32 (data
);
6131 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6133 if (offset
->X_add_number
== 0)
6134 offset
->X_op
= O_absent
;
6138 imm
->X_op
= O_constant
;
6139 if (!target_big_endian
)
6140 imm
->X_add_number
= bfd_getl64 (data
);
6142 imm
->X_add_number
= bfd_getb64 (data
);
6143 offset
->X_op
= O_absent
;
6148 /* Switch to the right section. */
6150 subseg
= now_subseg
;
6153 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6158 if (using_gprs
|| g_switch_value
< 8)
6159 newname
= RDATA_SECTION_NAME
;
6164 new_seg
= subseg_new (newname
, (subsegT
) 0);
6165 bfd_set_section_flags (new_seg
,
6166 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6167 frag_align (length
== 4 ? 2 : 3, 0, 0);
6168 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6169 record_alignment (new_seg
, 4);
6171 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6173 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6175 /* Set the argument to the current address in the section. */
6176 imm
->X_op
= O_absent
;
6177 offset
->X_op
= O_symbol
;
6178 offset
->X_add_symbol
= symbol_temp_new_now ();
6179 offset
->X_add_number
= 0;
6181 /* Put the floating point number into the section. */
6182 p
= frag_more (length
);
6183 memcpy (p
, data
, length
);
6185 /* Switch back to the original section. */
6186 subseg_set (seg
, subseg
);
6190 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6194 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6195 const struct mips_operand
*operand
,
6196 bfd_boolean match_p
)
6200 /* The operand can be an XYZW mask or a single 2-bit channel index
6201 (with X being 0). */
6202 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6204 /* The suffix can be omitted when it is already part of the opcode. */
6205 if (arg
->token
->type
!= OT_CHANNELS
)
6208 uval
= arg
->token
->u
.channels
;
6209 if (operand
->size
== 2)
6211 /* Check that a single bit is set and convert it into a 2-bit index. */
6212 if ((uval
& -uval
) != uval
)
6214 uval
= 4 - ffs (uval
);
6217 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6222 insn_insert_operand (arg
->insn
, operand
, uval
);
6226 /* Try to match a token from ARG against OPERAND. Consume the token
6227 and return true on success, otherwise return false. */
6230 match_operand (struct mips_arg_info
*arg
,
6231 const struct mips_operand
*operand
)
6233 switch (operand
->type
)
6236 return match_int_operand (arg
, operand
);
6239 return match_mapped_int_operand (arg
, operand
);
6242 return match_msb_operand (arg
, operand
);
6245 case OP_OPTIONAL_REG
:
6246 return match_reg_operand (arg
, operand
);
6249 return match_reg_pair_operand (arg
, operand
);
6252 return match_pcrel_operand (arg
);
6255 return match_perf_reg_operand (arg
, operand
);
6257 case OP_ADDIUSP_INT
:
6258 return match_addiusp_operand (arg
, operand
);
6260 case OP_CLO_CLZ_DEST
:
6261 return match_clo_clz_dest_operand (arg
, operand
);
6263 case OP_LWM_SWM_LIST
:
6264 return match_lwm_swm_list_operand (arg
, operand
);
6266 case OP_ENTRY_EXIT_LIST
:
6267 return match_entry_exit_operand (arg
, operand
);
6269 case OP_SAVE_RESTORE_LIST
:
6270 return match_save_restore_list_operand (arg
);
6272 case OP_MDMX_IMM_REG
:
6273 return match_mdmx_imm_reg_operand (arg
, operand
);
6275 case OP_REPEAT_DEST_REG
:
6276 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6278 case OP_REPEAT_PREV_REG
:
6279 return match_tied_reg_operand (arg
, arg
->last_regno
);
6282 return match_pc_operand (arg
);
6285 return match_reg28_operand (arg
);
6288 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6290 case OP_VU0_MATCH_SUFFIX
:
6291 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6294 return match_imm_index_operand (arg
, operand
);
6297 return match_reg_index_operand (arg
, operand
);
6300 return match_same_rs_rt_operand (arg
, operand
);
6303 return match_check_prev_operand (arg
, operand
);
6305 case OP_NON_ZERO_REG
:
6306 return match_non_zero_reg_operand (arg
, operand
);
6311 /* ARG is the state after successfully matching an instruction.
6312 Issue any queued-up warnings. */
6315 check_completed_insn (struct mips_arg_info
*arg
)
6320 as_warn (_("used $at without \".set noat\""));
6322 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6326 /* Return true if modifying general-purpose register REG needs a delay. */
6329 reg_needs_delay (unsigned int reg
)
6331 unsigned long prev_pinfo
;
6333 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6334 if (!mips_opts
.noreorder
6335 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6336 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6337 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6343 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6344 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6345 by VR4120 errata. */
6348 classify_vr4120_insn (const char *name
)
6350 if (strncmp (name
, "macc", 4) == 0)
6351 return FIX_VR4120_MACC
;
6352 if (strncmp (name
, "dmacc", 5) == 0)
6353 return FIX_VR4120_DMACC
;
6354 if (strncmp (name
, "mult", 4) == 0)
6355 return FIX_VR4120_MULT
;
6356 if (strncmp (name
, "dmult", 5) == 0)
6357 return FIX_VR4120_DMULT
;
6358 if (strstr (name
, "div"))
6359 return FIX_VR4120_DIV
;
6360 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6361 return FIX_VR4120_MTHILO
;
6362 return NUM_FIX_VR4120_CLASSES
;
6365 #define INSN_ERET 0x42000018
6366 #define INSN_DERET 0x4200001f
6367 #define INSN_DMULT 0x1c
6368 #define INSN_DMULTU 0x1d
6370 /* Return the number of instructions that must separate INSN1 and INSN2,
6371 where INSN1 is the earlier instruction. Return the worst-case value
6372 for any INSN2 if INSN2 is null. */
6375 insns_between (const struct mips_cl_insn
*insn1
,
6376 const struct mips_cl_insn
*insn2
)
6378 unsigned long pinfo1
, pinfo2
;
6381 /* If INFO2 is null, pessimistically assume that all flags are set for
6382 the second instruction. */
6383 pinfo1
= insn1
->insn_mo
->pinfo
;
6384 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6386 /* For most targets, write-after-read dependencies on the HI and LO
6387 registers must be separated by at least two instructions. */
6388 if (!hilo_interlocks
)
6390 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6392 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6396 /* If we're working around r7000 errata, there must be two instructions
6397 between an mfhi or mflo and any instruction that uses the result. */
6398 if (mips_7000_hilo_fix
6399 && !mips_opts
.micromips
6400 && MF_HILO_INSN (pinfo1
)
6401 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6404 /* If we're working around 24K errata, one instruction is required
6405 if an ERET or DERET is followed by a branch instruction. */
6406 if (mips_fix_24k
&& !mips_opts
.micromips
)
6408 if (insn1
->insn_opcode
== INSN_ERET
6409 || insn1
->insn_opcode
== INSN_DERET
)
6412 || insn2
->insn_opcode
== INSN_ERET
6413 || insn2
->insn_opcode
== INSN_DERET
6414 || delayed_branch_p (insn2
))
6419 /* If we're working around PMC RM7000 errata, there must be three
6420 nops between a dmult and a load instruction. */
6421 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6423 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6424 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6426 if (pinfo2
& INSN_LOAD_MEMORY
)
6431 /* If working around VR4120 errata, check for combinations that need
6432 a single intervening instruction. */
6433 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6435 unsigned int class1
, class2
;
6437 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6438 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6442 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6443 if (vr4120_conflicts
[class1
] & (1 << class2
))
6448 if (!HAVE_CODE_COMPRESSION
)
6450 /* Check for GPR or coprocessor load delays. All such delays
6451 are on the RT register. */
6452 /* Itbl support may require additional care here. */
6453 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6454 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6456 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6460 /* Check for generic coprocessor hazards.
6462 This case is not handled very well. There is no special
6463 knowledge of CP0 handling, and the coprocessors other than
6464 the floating point unit are not distinguished at all. */
6465 /* Itbl support may require additional care here. FIXME!
6466 Need to modify this to include knowledge about
6467 user specified delays! */
6468 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6469 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6471 /* Handle cases where INSN1 writes to a known general coprocessor
6472 register. There must be a one instruction delay before INSN2
6473 if INSN2 reads that register, otherwise no delay is needed. */
6474 mask
= fpr_write_mask (insn1
);
6477 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6482 /* Read-after-write dependencies on the control registers
6483 require a two-instruction gap. */
6484 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6485 && (pinfo2
& INSN_READ_COND_CODE
))
6488 /* We don't know exactly what INSN1 does. If INSN2 is
6489 also a coprocessor instruction, assume there must be
6490 a one instruction gap. */
6491 if (pinfo2
& INSN_COP
)
6496 /* Check for read-after-write dependencies on the coprocessor
6497 control registers in cases where INSN1 does not need a general
6498 coprocessor delay. This means that INSN1 is a floating point
6499 comparison instruction. */
6500 /* Itbl support may require additional care here. */
6501 else if (!cop_interlocks
6502 && (pinfo1
& INSN_WRITE_COND_CODE
)
6503 && (pinfo2
& INSN_READ_COND_CODE
))
6507 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6508 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6510 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6511 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6512 || (insn2
&& delayed_branch_p (insn2
))))
6518 /* Return the number of nops that would be needed to work around the
6519 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6520 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6521 that are contained within the first IGNORE instructions of HIST. */
6524 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6525 const struct mips_cl_insn
*insn
)
6530 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6531 are not affected by the errata. */
6533 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6534 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6535 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6538 /* Search for the first MFLO or MFHI. */
6539 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6540 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6542 /* Extract the destination register. */
6543 mask
= gpr_write_mask (&hist
[i
]);
6545 /* No nops are needed if INSN reads that register. */
6546 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6549 /* ...or if any of the intervening instructions do. */
6550 for (j
= 0; j
< i
; j
++)
6551 if (gpr_read_mask (&hist
[j
]) & mask
)
6555 return MAX_VR4130_NOPS
- i
;
6560 #define BASE_REG_EQ(INSN1, INSN2) \
6561 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6562 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6564 /* Return the minimum alignment for this store instruction. */
6567 fix_24k_align_to (const struct mips_opcode
*mo
)
6569 if (strcmp (mo
->name
, "sh") == 0)
6572 if (strcmp (mo
->name
, "swc1") == 0
6573 || strcmp (mo
->name
, "swc2") == 0
6574 || strcmp (mo
->name
, "sw") == 0
6575 || strcmp (mo
->name
, "sc") == 0
6576 || strcmp (mo
->name
, "s.s") == 0)
6579 if (strcmp (mo
->name
, "sdc1") == 0
6580 || strcmp (mo
->name
, "sdc2") == 0
6581 || strcmp (mo
->name
, "s.d") == 0)
6588 struct fix_24k_store_info
6590 /* Immediate offset, if any, for this store instruction. */
6592 /* Alignment required by this store instruction. */
6594 /* True for register offsets. */
6595 int register_offset
;
6598 /* Comparison function used by qsort. */
6601 fix_24k_sort (const void *a
, const void *b
)
6603 const struct fix_24k_store_info
*pos1
= a
;
6604 const struct fix_24k_store_info
*pos2
= b
;
6606 return (pos1
->off
- pos2
->off
);
6609 /* INSN is a store instruction. Try to record the store information
6610 in STINFO. Return false if the information isn't known. */
6613 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6614 const struct mips_cl_insn
*insn
)
6616 /* The instruction must have a known offset. */
6617 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6620 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6621 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6625 /* Return the number of nops that would be needed to work around the 24k
6626 "lost data on stores during refill" errata if instruction INSN
6627 immediately followed the 2 instructions described by HIST.
6628 Ignore hazards that are contained within the first IGNORE
6629 instructions of HIST.
6631 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6632 for the data cache refills and store data. The following describes
6633 the scenario where the store data could be lost.
6635 * A data cache miss, due to either a load or a store, causing fill
6636 data to be supplied by the memory subsystem
6637 * The first three doublewords of fill data are returned and written
6639 * A sequence of four stores occurs in consecutive cycles around the
6640 final doubleword of the fill:
6644 * Zero, One or more instructions
6647 The four stores A-D must be to different doublewords of the line that
6648 is being filled. The fourth instruction in the sequence above permits
6649 the fill of the final doubleword to be transferred from the FSB into
6650 the cache. In the sequence above, the stores may be either integer
6651 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6652 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6653 different doublewords on the line. If the floating point unit is
6654 running in 1:2 mode, it is not possible to create the sequence above
6655 using only floating point store instructions.
6657 In this case, the cache line being filled is incorrectly marked
6658 invalid, thereby losing the data from any store to the line that
6659 occurs between the original miss and the completion of the five
6660 cycle sequence shown above.
6662 The workarounds are:
6664 * Run the data cache in write-through mode.
6665 * Insert a non-store instruction between
6666 Store A and Store B or Store B and Store C. */
6669 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6670 const struct mips_cl_insn
*insn
)
6672 struct fix_24k_store_info pos
[3];
6673 int align
, i
, base_offset
;
6678 /* If the previous instruction wasn't a store, there's nothing to
6680 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6683 /* If the instructions after the previous one are unknown, we have
6684 to assume the worst. */
6688 /* Check whether we are dealing with three consecutive stores. */
6689 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6690 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6693 /* If we don't know the relationship between the store addresses,
6694 assume the worst. */
6695 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6696 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6699 if (!fix_24k_record_store_info (&pos
[0], insn
)
6700 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6701 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6704 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6706 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6707 X bytes and such that the base register + X is known to be aligned
6710 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6714 align
= pos
[0].align_to
;
6715 base_offset
= pos
[0].off
;
6716 for (i
= 1; i
< 3; i
++)
6717 if (align
< pos
[i
].align_to
)
6719 align
= pos
[i
].align_to
;
6720 base_offset
= pos
[i
].off
;
6722 for (i
= 0; i
< 3; i
++)
6723 pos
[i
].off
-= base_offset
;
6726 pos
[0].off
&= ~align
+ 1;
6727 pos
[1].off
&= ~align
+ 1;
6728 pos
[2].off
&= ~align
+ 1;
6730 /* If any two stores write to the same chunk, they also write to the
6731 same doubleword. The offsets are still sorted at this point. */
6732 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6735 /* A range of at least 9 bytes is needed for the stores to be in
6736 non-overlapping doublewords. */
6737 if (pos
[2].off
- pos
[0].off
<= 8)
6740 if (pos
[2].off
- pos
[1].off
>= 24
6741 || pos
[1].off
- pos
[0].off
>= 24
6742 || pos
[2].off
- pos
[0].off
>= 32)
6748 /* Return the number of nops that would be needed if instruction INSN
6749 immediately followed the MAX_NOPS instructions given by HIST,
6750 where HIST[0] is the most recent instruction. Ignore hazards
6751 between INSN and the first IGNORE instructions in HIST.
6753 If INSN is null, return the worse-case number of nops for any
6757 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6758 const struct mips_cl_insn
*insn
)
6760 int i
, nops
, tmp_nops
;
6763 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6765 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6766 if (tmp_nops
> nops
)
6770 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6772 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6773 if (tmp_nops
> nops
)
6777 if (mips_fix_24k
&& !mips_opts
.micromips
)
6779 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6780 if (tmp_nops
> nops
)
6787 /* The variable arguments provide NUM_INSNS extra instructions that
6788 might be added to HIST. Return the largest number of nops that
6789 would be needed after the extended sequence, ignoring hazards
6790 in the first IGNORE instructions. */
6793 nops_for_sequence (int num_insns
, int ignore
,
6794 const struct mips_cl_insn
*hist
, ...)
6797 struct mips_cl_insn buffer
[MAX_NOPS
];
6798 struct mips_cl_insn
*cursor
;
6801 va_start (args
, hist
);
6802 cursor
= buffer
+ num_insns
;
6803 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6804 while (cursor
> buffer
)
6805 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6807 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6812 /* Like nops_for_insn, but if INSN is a branch, take into account the
6813 worst-case delay for the branch target. */
6816 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6817 const struct mips_cl_insn
*insn
)
6821 nops
= nops_for_insn (ignore
, hist
, insn
);
6822 if (delayed_branch_p (insn
))
6824 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6825 hist
, insn
, get_delay_slot_nop (insn
));
6826 if (tmp_nops
> nops
)
6829 else if (compact_branch_p (insn
))
6831 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6832 if (tmp_nops
> nops
)
6838 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6841 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6843 gas_assert (!HAVE_CODE_COMPRESSION
);
6844 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6845 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6848 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6849 jr target pc &= 'hffff_ffff_cfff_ffff. */
6852 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6854 gas_assert (!HAVE_CODE_COMPRESSION
);
6855 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6856 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6857 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6865 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6866 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6869 ep
.X_op
= O_constant
;
6870 ep
.X_add_number
= 0xcfff0000;
6871 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6872 ep
.X_add_number
= 0xffff;
6873 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6874 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6879 fix_loongson2f (struct mips_cl_insn
* ip
)
6881 if (mips_fix_loongson2f_nop
)
6882 fix_loongson2f_nop (ip
);
6884 if (mips_fix_loongson2f_jump
)
6885 fix_loongson2f_jump (ip
);
6889 has_label_name (const char *arr
[], size_t len
,const char *s
)
6892 for (i
= 0; i
< len
; i
++)
6896 if (streq (arr
[i
], s
))
6902 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6905 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6907 gas_assert (!HAVE_CODE_COMPRESSION
);
6909 /* If is an local label and the insn is not sync,
6910 look forward that whether an branch between ll/sc jump to here
6911 if so, insert a sync. */
6912 if (seg_info (now_seg
)->label_list
6913 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6914 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6918 const char *label_names
[MAX_LABELS_SAME
];
6919 const char *label_name
;
6921 label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6922 label_names
[0] = label_name
;
6923 struct insn_label_list
*llist
= seg_info (now_seg
)->label_list
;
6924 label_value
= S_GET_VALUE (llist
->label
);
6926 for (i
= 1; i
< MAX_LABELS_SAME
; i
++)
6928 llist
= llist
->next
;
6931 if (S_GET_VALUE (llist
->label
) == label_value
)
6932 label_names
[i
] = S_GET_NAME (llist
->label
);
6936 for (; i
< MAX_LABELS_SAME
; i
++)
6937 label_names
[i
] = NULL
;
6939 unsigned long lookback
= ARRAY_SIZE (history
);
6940 for (i
= 0; i
< lookback
; i
++)
6942 if (streq (history
[i
].insn_mo
->name
, "ll")
6943 || streq (history
[i
].insn_mo
->name
, "lld"))
6946 if (streq (history
[i
].insn_mo
->name
, "sc")
6947 || streq (history
[i
].insn_mo
->name
, "scd"))
6951 for (j
= i
+ 1; j
< lookback
; j
++)
6953 if (streq (history
[i
].insn_mo
->name
, "ll")
6954 || streq (history
[i
].insn_mo
->name
, "lld"))
6957 if (delayed_branch_p (&history
[j
]))
6959 if (has_label_name (label_names
,
6963 add_fixed_insn (&sync_insn
);
6964 insert_into_history (0, 1, &sync_insn
);
6973 /* If we find a sc, we look forward to look for an branch insn,
6974 and see whether it jump back and out of ll/sc. */
6975 else if (streq (ip
->insn_mo
->name
, "sc") || streq (ip
->insn_mo
->name
, "scd"))
6977 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6980 for (i
= 0; i
< lookback
; i
++)
6982 if (streq (history
[i
].insn_mo
->name
, "ll")
6983 || streq (history
[i
].insn_mo
->name
, "lld"))
6986 if (delayed_branch_p (&history
[i
]))
6990 for (j
= i
+ 1; j
< lookback
; j
++)
6992 if (streq (history
[j
].insn_mo
->name
, "ll")
6993 || streq (history
[i
].insn_mo
->name
, "lld"))
6997 for (; j
< lookback
; j
++)
6999 if (history
[j
].label
[0] != '\0'
7000 && streq (history
[j
].label
, history
[i
].target
)
7001 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
7003 add_fixed_insn (&sync_insn
);
7004 insert_into_history (++j
, 1, &sync_insn
);
7011 /* Skip if there is a sync before ll/lld. */
7012 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
7013 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
7014 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
7016 add_fixed_insn (&sync_insn
);
7017 insert_into_history (0, 1, &sync_insn
);
7021 /* IP is a branch that has a delay slot, and we need to fill it
7022 automatically. Return true if we can do that by swapping IP
7023 with the previous instruction.
7024 ADDRESS_EXPR is an operand of the instruction to be used with
7028 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7029 bfd_reloc_code_real_type
*reloc_type
)
7031 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7032 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7033 unsigned int fpr_read
, prev_fpr_write
;
7035 /* -O2 and above is required for this optimization. */
7036 if (mips_optimize
< 2)
7039 /* If we have seen .set volatile or .set nomove, don't optimize. */
7040 if (mips_opts
.nomove
)
7043 /* We can't swap if the previous instruction's position is fixed. */
7044 if (history
[0].fixed_p
)
7047 /* If the previous previous insn was in a .set noreorder, we can't
7048 swap. Actually, the MIPS assembler will swap in this situation.
7049 However, gcc configured -with-gnu-as will generate code like
7057 in which we can not swap the bne and INSN. If gcc is not configured
7058 -with-gnu-as, it does not output the .set pseudo-ops. */
7059 if (history
[1].noreorder_p
)
7062 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7063 This means that the previous instruction was a 4-byte one anyhow. */
7064 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7067 /* If the branch is itself the target of a branch, we can not swap.
7068 We cheat on this; all we check for is whether there is a label on
7069 this instruction. If there are any branches to anything other than
7070 a label, users must use .set noreorder. */
7071 if (seg_info (now_seg
)->label_list
)
7074 /* If the previous instruction is in a variant frag other than this
7075 branch's one, we cannot do the swap. This does not apply to
7076 MIPS16 code, which uses variant frags for different purposes. */
7077 if (!mips_opts
.mips16
7079 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7082 /* We do not swap with instructions that cannot architecturally
7083 be placed in a branch delay slot, such as SYNC or ERET. We
7084 also refrain from swapping with a trap instruction, since it
7085 complicates trap handlers to have the trap instruction be in
7087 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7088 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7091 /* Check for conflicts between the branch and the instructions
7092 before the candidate delay slot. */
7093 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7096 /* Check for conflicts between the swapped sequence and the
7097 target of the branch. */
7098 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7101 /* If the branch reads a register that the previous
7102 instruction sets, we can not swap. */
7103 gpr_read
= gpr_read_mask (ip
);
7104 prev_gpr_write
= gpr_write_mask (&history
[0]);
7105 if (gpr_read
& prev_gpr_write
)
7108 fpr_read
= fpr_read_mask (ip
);
7109 prev_fpr_write
= fpr_write_mask (&history
[0]);
7110 if (fpr_read
& prev_fpr_write
)
7113 /* If the branch writes a register that the previous
7114 instruction sets, we can not swap. */
7115 gpr_write
= gpr_write_mask (ip
);
7116 if (gpr_write
& prev_gpr_write
)
7119 /* If the branch writes a register that the previous
7120 instruction reads, we can not swap. */
7121 prev_gpr_read
= gpr_read_mask (&history
[0]);
7122 if (gpr_write
& prev_gpr_read
)
7125 /* If one instruction sets a condition code and the
7126 other one uses a condition code, we can not swap. */
7127 pinfo
= ip
->insn_mo
->pinfo
;
7128 if ((pinfo
& INSN_READ_COND_CODE
)
7129 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7131 if ((pinfo
& INSN_WRITE_COND_CODE
)
7132 && (prev_pinfo
& INSN_READ_COND_CODE
))
7135 /* If the previous instruction uses the PC, we can not swap. */
7136 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7137 if (prev_pinfo2
& INSN2_READ_PC
)
7140 /* If the previous instruction has an incorrect size for a fixed
7141 branch delay slot in microMIPS mode, we cannot swap. */
7142 pinfo2
= ip
->insn_mo
->pinfo2
;
7143 if (mips_opts
.micromips
7144 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7145 && insn_length (history
) != 2)
7147 if (mips_opts
.micromips
7148 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7149 && insn_length (history
) != 4)
7152 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7155 The short loop bug under certain conditions causes loops to execute
7156 only once or twice. We must ensure that the assembler never
7157 generates loops that satisfy all of the following conditions:
7159 - a loop consists of less than or equal to six instructions
7160 (including the branch delay slot);
7161 - a loop contains only one conditional branch instruction at the end
7163 - a loop does not contain any other branch or jump instructions;
7164 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7166 We need to do this because of a hardware bug in the R5900 chip. */
7168 /* Check if instruction has a parameter, ignore "j $31". */
7169 && (address_expr
!= NULL
)
7170 /* Parameter must be 16 bit. */
7171 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7172 /* Branch to same segment. */
7173 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7174 /* Branch to same code fragment. */
7175 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7176 /* Can only calculate branch offset if value is known. */
7177 && symbol_constant_p (address_expr
->X_add_symbol
)
7178 /* Check if branch is really conditional. */
7179 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7180 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7181 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7184 /* Check if loop is shorter than or equal to 6 instructions
7185 including branch and delay slot. */
7186 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7193 /* When the loop includes branches or jumps,
7194 it is not a short loop. */
7195 for (i
= 0; i
< (distance
/ 4); i
++)
7197 if ((history
[i
].cleared_p
)
7198 || delayed_branch_p (&history
[i
]))
7206 /* Insert nop after branch to fix short loop. */
7215 /* Decide how we should add IP to the instruction stream.
7216 ADDRESS_EXPR is an operand of the instruction to be used with
7219 static enum append_method
7220 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7221 bfd_reloc_code_real_type
*reloc_type
)
7223 /* The relaxed version of a macro sequence must be inherently
7225 if (mips_relax
.sequence
== 2)
7228 /* We must not dabble with instructions in a ".set noreorder" block. */
7229 if (mips_opts
.noreorder
)
7232 /* Otherwise, it's our responsibility to fill branch delay slots. */
7233 if (delayed_branch_p (ip
))
7235 if (!branch_likely_p (ip
)
7236 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7239 if (mips_opts
.mips16
7240 && ISA_SUPPORTS_MIPS16E
7241 && gpr_read_mask (ip
) != 0)
7242 return APPEND_ADD_COMPACT
;
7244 if (mips_opts
.micromips
7245 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7246 || (!forced_insn_length
7247 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7248 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7249 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7250 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7251 return APPEND_ADD_COMPACT
;
7253 return APPEND_ADD_WITH_NOP
;
7259 /* IP is an instruction whose opcode we have just changed, END points
7260 to the end of the opcode table processed. Point IP->insn_mo to the
7261 new opcode's definition. */
7264 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7266 const struct mips_opcode
*mo
;
7268 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7269 if (mo
->pinfo
!= INSN_MACRO
7270 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7278 /* IP is a MIPS16 instruction whose opcode we have just changed.
7279 Point IP->insn_mo to the new opcode's definition. */
7282 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7284 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7287 /* IP is a microMIPS instruction whose opcode we have just changed.
7288 Point IP->insn_mo to the new opcode's definition. */
7291 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7293 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7296 /* For microMIPS macros, we need to generate a local number label
7297 as the target of branches. */
7298 #define MICROMIPS_LABEL_CHAR '\037'
7299 static unsigned long micromips_target_label
;
7300 static char micromips_target_name
[32];
7303 micromips_label_name (void)
7305 char *p
= micromips_target_name
;
7306 char symbol_name_temporary
[24];
7314 l
= micromips_target_label
;
7315 #ifdef LOCAL_LABEL_PREFIX
7316 *p
++ = LOCAL_LABEL_PREFIX
;
7319 *p
++ = MICROMIPS_LABEL_CHAR
;
7322 symbol_name_temporary
[i
++] = l
% 10 + '0';
7327 *p
++ = symbol_name_temporary
[--i
];
7330 return micromips_target_name
;
7334 micromips_label_expr (expressionS
*label_expr
)
7336 label_expr
->X_op
= O_symbol
;
7337 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7338 label_expr
->X_add_number
= 0;
7342 micromips_label_inc (void)
7344 micromips_target_label
++;
7345 *micromips_target_name
= '\0';
7349 micromips_add_label (void)
7353 s
= colon (micromips_label_name ());
7354 micromips_label_inc ();
7355 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7358 /* If assembling microMIPS code, then return the microMIPS reloc
7359 corresponding to the requested one if any. Otherwise return
7360 the reloc unchanged. */
7362 static bfd_reloc_code_real_type
7363 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7365 static const bfd_reloc_code_real_type relocs
[][2] =
7367 /* Keep sorted incrementally by the left-hand key. */
7368 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7369 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7370 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7371 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7372 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7373 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7374 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7375 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7376 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7377 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7378 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7379 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7380 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7381 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7382 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7383 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7384 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7385 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7386 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7387 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7388 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7389 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7390 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7391 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7392 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7393 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7394 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7396 bfd_reloc_code_real_type r
;
7399 if (!mips_opts
.micromips
)
7401 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7407 return relocs
[i
][1];
7412 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7413 Return true on success, storing the resolved value in RESULT. */
7416 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7421 case BFD_RELOC_MIPS_HIGHEST
:
7422 case BFD_RELOC_MICROMIPS_HIGHEST
:
7423 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7426 case BFD_RELOC_MIPS_HIGHER
:
7427 case BFD_RELOC_MICROMIPS_HIGHER
:
7428 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7431 case BFD_RELOC_HI16_S
:
7432 case BFD_RELOC_HI16_S_PCREL
:
7433 case BFD_RELOC_MICROMIPS_HI16_S
:
7434 case BFD_RELOC_MIPS16_HI16_S
:
7435 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7438 case BFD_RELOC_HI16
:
7439 case BFD_RELOC_MICROMIPS_HI16
:
7440 case BFD_RELOC_MIPS16_HI16
:
7441 *result
= (operand
>> 16) & 0xffff;
7444 case BFD_RELOC_LO16
:
7445 case BFD_RELOC_LO16_PCREL
:
7446 case BFD_RELOC_MICROMIPS_LO16
:
7447 case BFD_RELOC_MIPS16_LO16
:
7448 *result
= operand
& 0xffff;
7451 case BFD_RELOC_UNUSED
:
7460 /* Output an instruction. IP is the instruction information.
7461 ADDRESS_EXPR is an operand of the instruction to be used with
7462 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7463 a macro expansion. */
7466 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7467 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7469 unsigned long prev_pinfo2
, pinfo
;
7470 bfd_boolean relaxed_branch
= FALSE
;
7471 enum append_method method
;
7472 bfd_boolean relax32
;
7475 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7476 fix_loongson2f (ip
);
7478 ip
->target
[0] = '\0';
7479 if (offset_expr
.X_op
== O_symbol
)
7480 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7481 ip
->label
[0] = '\0';
7482 if (seg_info (now_seg
)->label_list
)
7483 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7484 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7485 fix_loongson3_llsc (ip
);
7487 file_ase_mips16
|= mips_opts
.mips16
;
7488 file_ase_micromips
|= mips_opts
.micromips
;
7490 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7491 pinfo
= ip
->insn_mo
->pinfo
;
7493 /* Don't raise alarm about `nods' frags as they'll fill in the right
7494 kind of nop in relaxation if required. */
7495 if (mips_opts
.micromips
7497 && !(history
[0].frag
7498 && history
[0].frag
->fr_type
== rs_machine_dependent
7499 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7500 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7501 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7502 && micromips_insn_length (ip
->insn_mo
) != 2)
7503 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7504 && micromips_insn_length (ip
->insn_mo
) != 4)))
7505 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7506 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7508 if (address_expr
== NULL
)
7510 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7511 && reloc_type
[1] == BFD_RELOC_UNUSED
7512 && reloc_type
[2] == BFD_RELOC_UNUSED
7513 && address_expr
->X_op
== O_constant
)
7515 switch (*reloc_type
)
7517 case BFD_RELOC_MIPS_JMP
:
7521 /* Shift is 2, unusually, for microMIPS JALX. */
7522 shift
= (mips_opts
.micromips
7523 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7524 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7525 as_bad (_("jump to misaligned address (0x%lx)"),
7526 (unsigned long) address_expr
->X_add_number
);
7527 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7533 case BFD_RELOC_MIPS16_JMP
:
7534 if ((address_expr
->X_add_number
& 3) != 0)
7535 as_bad (_("jump to misaligned address (0x%lx)"),
7536 (unsigned long) address_expr
->X_add_number
);
7538 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7539 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7540 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7544 case BFD_RELOC_16_PCREL_S2
:
7548 shift
= mips_opts
.micromips
? 1 : 2;
7549 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7550 as_bad (_("branch to misaligned address (0x%lx)"),
7551 (unsigned long) address_expr
->X_add_number
);
7552 if (!mips_relax_branch
)
7554 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7555 & ~((1 << (shift
+ 16)) - 1))
7556 as_bad (_("branch address range overflow (0x%lx)"),
7557 (unsigned long) address_expr
->X_add_number
);
7558 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7564 case BFD_RELOC_MIPS_21_PCREL_S2
:
7569 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7570 as_bad (_("branch to misaligned address (0x%lx)"),
7571 (unsigned long) address_expr
->X_add_number
);
7572 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7573 & ~((1 << (shift
+ 21)) - 1))
7574 as_bad (_("branch address range overflow (0x%lx)"),
7575 (unsigned long) address_expr
->X_add_number
);
7576 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7581 case BFD_RELOC_MIPS_26_PCREL_S2
:
7586 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7587 as_bad (_("branch to misaligned address (0x%lx)"),
7588 (unsigned long) address_expr
->X_add_number
);
7589 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7590 & ~((1 << (shift
+ 26)) - 1))
7591 as_bad (_("branch address range overflow (0x%lx)"),
7592 (unsigned long) address_expr
->X_add_number
);
7593 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7602 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7605 ip
->insn_opcode
|= value
& 0xffff;
7613 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7615 /* There are a lot of optimizations we could do that we don't.
7616 In particular, we do not, in general, reorder instructions.
7617 If you use gcc with optimization, it will reorder
7618 instructions and generally do much more optimization then we
7619 do here; repeating all that work in the assembler would only
7620 benefit hand written assembly code, and does not seem worth
7622 int nops
= (mips_optimize
== 0
7623 ? nops_for_insn (0, history
, NULL
)
7624 : nops_for_insn_or_target (0, history
, ip
));
7628 unsigned long old_frag_offset
;
7631 old_frag
= frag_now
;
7632 old_frag_offset
= frag_now_fix ();
7634 for (i
= 0; i
< nops
; i
++)
7635 add_fixed_insn (NOP_INSN
);
7636 insert_into_history (0, nops
, NOP_INSN
);
7640 listing_prev_line ();
7641 /* We may be at the start of a variant frag. In case we
7642 are, make sure there is enough space for the frag
7643 after the frags created by listing_prev_line. The
7644 argument to frag_grow here must be at least as large
7645 as the argument to all other calls to frag_grow in
7646 this file. We don't have to worry about being in the
7647 middle of a variant frag, because the variants insert
7648 all needed nop instructions themselves. */
7652 mips_move_text_labels ();
7654 #ifndef NO_ECOFF_DEBUGGING
7655 if (ECOFF_DEBUGGING
)
7656 ecoff_fix_loc (old_frag
, old_frag_offset
);
7660 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7664 /* Work out how many nops in prev_nop_frag are needed by IP,
7665 ignoring hazards generated by the first prev_nop_frag_since
7667 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7668 gas_assert (nops
<= prev_nop_frag_holds
);
7670 /* Enforce NOPS as a minimum. */
7671 if (nops
> prev_nop_frag_required
)
7672 prev_nop_frag_required
= nops
;
7674 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7676 /* Settle for the current number of nops. Update the history
7677 accordingly (for the benefit of any future .set reorder code). */
7678 prev_nop_frag
= NULL
;
7679 insert_into_history (prev_nop_frag_since
,
7680 prev_nop_frag_holds
, NOP_INSN
);
7684 /* Allow this instruction to replace one of the nops that was
7685 tentatively added to prev_nop_frag. */
7686 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7687 prev_nop_frag_holds
--;
7688 prev_nop_frag_since
++;
7692 method
= get_append_method (ip
, address_expr
, reloc_type
);
7693 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7695 dwarf2_emit_insn (0);
7696 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7697 so "move" the instruction address accordingly.
7699 Also, it doesn't seem appropriate for the assembler to reorder .loc
7700 entries. If this instruction is a branch that we are going to swap
7701 with the previous instruction, the two instructions should be
7702 treated as a unit, and the debug information for both instructions
7703 should refer to the start of the branch sequence. Using the
7704 current position is certainly wrong when swapping a 32-bit branch
7705 and a 16-bit delay slot, since the current position would then be
7706 in the middle of a branch. */
7707 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7709 relax32
= (mips_relax_branch
7710 /* Don't try branch relaxation within .set nomacro, or within
7711 .set noat if we use $at for PIC computations. If it turns
7712 out that the branch was out-of-range, we'll get an error. */
7713 && !mips_opts
.warn_about_macros
7714 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7715 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7716 as they have no complementing branches. */
7717 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7719 if (!HAVE_CODE_COMPRESSION
7722 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7723 && delayed_branch_p (ip
))
7725 relaxed_branch
= TRUE
;
7726 add_relaxed_insn (ip
, (relaxed_branch_length
7728 uncond_branch_p (ip
) ? -1
7729 : branch_likely_p (ip
) ? 1
7732 (AT
, mips_pic
!= NO_PIC
,
7733 uncond_branch_p (ip
),
7734 branch_likely_p (ip
),
7735 pinfo
& INSN_WRITE_GPR_31
,
7737 address_expr
->X_add_symbol
,
7738 address_expr
->X_add_number
);
7739 *reloc_type
= BFD_RELOC_UNUSED
;
7741 else if (mips_opts
.micromips
7743 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7744 || *reloc_type
> BFD_RELOC_UNUSED
)
7745 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7746 /* Don't try branch relaxation when users specify
7747 16-bit/32-bit instructions. */
7748 && !forced_insn_length
)
7750 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7751 && *reloc_type
> BFD_RELOC_UNUSED
);
7752 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7753 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7754 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7755 int nods
= method
== APPEND_ADD_WITH_NOP
;
7756 int al
= pinfo
& INSN_WRITE_GPR_31
;
7757 int length32
= nods
? 8 : 4;
7759 gas_assert (address_expr
!= NULL
);
7760 gas_assert (!mips_relax
.sequence
);
7762 relaxed_branch
= TRUE
;
7764 method
= APPEND_ADD
;
7766 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7767 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7768 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7770 uncond
, compact
, al
, nods
,
7772 address_expr
->X_add_symbol
,
7773 address_expr
->X_add_number
);
7774 *reloc_type
= BFD_RELOC_UNUSED
;
7776 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7778 bfd_boolean require_unextended
;
7779 bfd_boolean require_extended
;
7783 if (forced_insn_length
!= 0)
7785 require_unextended
= forced_insn_length
== 2;
7786 require_extended
= forced_insn_length
== 4;
7790 require_unextended
= (mips_opts
.noautoextend
7791 && !mips_opcode_32bit_p (ip
->insn_mo
));
7792 require_extended
= 0;
7795 /* We need to set up a variant frag. */
7796 gas_assert (address_expr
!= NULL
);
7797 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7798 symbol created by `make_expr_symbol' may not get a necessary
7799 external relocation produced. */
7800 if (address_expr
->X_op
== O_symbol
)
7802 symbol
= address_expr
->X_add_symbol
;
7803 offset
= address_expr
->X_add_number
;
7807 symbol
= make_expr_symbol (address_expr
);
7808 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7811 add_relaxed_insn (ip
, 12, 0,
7813 (*reloc_type
- BFD_RELOC_UNUSED
,
7814 mips_opts
.ase
& ASE_MIPS16E2
,
7817 mips_opts
.warn_about_macros
,
7818 require_unextended
, require_extended
,
7819 delayed_branch_p (&history
[0]),
7820 history
[0].mips16_absolute_jump_p
),
7823 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7825 if (!delayed_branch_p (ip
))
7826 /* Make sure there is enough room to swap this instruction with
7827 a following jump instruction. */
7829 add_fixed_insn (ip
);
7833 if (mips_opts
.mips16
7834 && mips_opts
.noreorder
7835 && delayed_branch_p (&history
[0]))
7836 as_warn (_("extended instruction in delay slot"));
7838 if (mips_relax
.sequence
)
7840 /* If we've reached the end of this frag, turn it into a variant
7841 frag and record the information for the instructions we've
7843 if (frag_room () < 4)
7844 relax_close_frag ();
7845 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7848 if (mips_relax
.sequence
!= 2)
7850 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7851 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7852 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7853 mips_macro_warning
.insns
[0]++;
7855 if (mips_relax
.sequence
!= 1)
7857 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7858 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7859 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7860 mips_macro_warning
.insns
[1]++;
7863 if (mips_opts
.mips16
)
7866 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7868 add_fixed_insn (ip
);
7871 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7873 bfd_reloc_code_real_type final_type
[3];
7874 reloc_howto_type
*howto0
;
7875 reloc_howto_type
*howto
;
7878 /* Perform any necessary conversion to microMIPS relocations
7879 and find out how many relocations there actually are. */
7880 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7881 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7883 /* In a compound relocation, it is the final (outermost)
7884 operator that determines the relocated field. */
7885 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7890 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7891 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7892 bfd_get_reloc_size (howto
),
7894 howto0
&& howto0
->pc_relative
,
7896 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7897 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7899 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7900 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7901 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7903 /* These relocations can have an addend that won't fit in
7904 4 octets for 64bit assembly. */
7906 && ! howto
->partial_inplace
7907 && (reloc_type
[0] == BFD_RELOC_16
7908 || reloc_type
[0] == BFD_RELOC_32
7909 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7910 || reloc_type
[0] == BFD_RELOC_GPREL16
7911 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7912 || reloc_type
[0] == BFD_RELOC_GPREL32
7913 || reloc_type
[0] == BFD_RELOC_64
7914 || reloc_type
[0] == BFD_RELOC_CTOR
7915 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7916 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7917 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7918 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7919 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7920 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7921 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7922 || hi16_reloc_p (reloc_type
[0])
7923 || lo16_reloc_p (reloc_type
[0])))
7924 ip
->fixp
[0]->fx_no_overflow
= 1;
7926 /* These relocations can have an addend that won't fit in 2 octets. */
7927 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7928 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7929 ip
->fixp
[0]->fx_no_overflow
= 1;
7931 if (mips_relax
.sequence
)
7933 if (mips_relax
.first_fixup
== 0)
7934 mips_relax
.first_fixup
= ip
->fixp
[0];
7936 else if (reloc_needs_lo_p (*reloc_type
))
7938 struct mips_hi_fixup
*hi_fixup
;
7940 /* Reuse the last entry if it already has a matching %lo. */
7941 hi_fixup
= mips_hi_fixup_list
;
7943 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7945 hi_fixup
= XNEW (struct mips_hi_fixup
);
7946 hi_fixup
->next
= mips_hi_fixup_list
;
7947 mips_hi_fixup_list
= hi_fixup
;
7949 hi_fixup
->fixp
= ip
->fixp
[0];
7950 hi_fixup
->seg
= now_seg
;
7953 /* Add fixups for the second and third relocations, if given.
7954 Note that the ABI allows the second relocation to be
7955 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7956 moment we only use RSS_UNDEF, but we could add support
7957 for the others if it ever becomes necessary. */
7958 for (i
= 1; i
< 3; i
++)
7959 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7961 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7962 ip
->fixp
[0]->fx_size
, NULL
, 0,
7963 FALSE
, final_type
[i
]);
7965 /* Use fx_tcbit to mark compound relocs. */
7966 ip
->fixp
[0]->fx_tcbit
= 1;
7967 ip
->fixp
[i
]->fx_tcbit
= 1;
7971 /* Update the register mask information. */
7972 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7973 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7978 insert_into_history (0, 1, ip
);
7981 case APPEND_ADD_WITH_NOP
:
7983 struct mips_cl_insn
*nop
;
7985 insert_into_history (0, 1, ip
);
7986 nop
= get_delay_slot_nop (ip
);
7987 add_fixed_insn (nop
);
7988 insert_into_history (0, 1, nop
);
7989 if (mips_relax
.sequence
)
7990 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7994 case APPEND_ADD_COMPACT
:
7995 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7996 if (mips_opts
.mips16
)
7998 ip
->insn_opcode
|= 0x0080;
7999 find_altered_mips16_opcode (ip
);
8001 /* Convert microMIPS instructions. */
8002 else if (mips_opts
.micromips
)
8005 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
8006 ip
->insn_opcode
|= 0x0020;
8008 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
8009 ip
->insn_opcode
= 0x40e00000;
8010 /* beqz16->beqzc, bnez16->bnezc */
8011 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
8013 unsigned long regno
;
8015 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
8016 regno
&= MICROMIPSOP_MASK_MD
;
8017 regno
= micromips_to_32_reg_d_map
[regno
];
8018 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8019 | (regno
<< MICROMIPSOP_SH_RS
)
8020 | 0x40a00000) ^ 0x00400000;
8022 /* beqz->beqzc, bnez->bnezc */
8023 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8024 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8025 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8026 | 0x40a00000) ^ 0x00400000;
8027 /* beq $0->beqzc, bne $0->bnezc */
8028 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8029 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8030 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8031 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8032 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8033 | 0x40a00000) ^ 0x00400000;
8036 find_altered_micromips_opcode (ip
);
8041 insert_into_history (0, 1, ip
);
8046 struct mips_cl_insn delay
= history
[0];
8048 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8050 /* Add the delay slot instruction to the end of the
8051 current frag and shrink the fixed part of the
8052 original frag. If the branch occupies the tail of
8053 the latter, move it backwards to cover the gap. */
8054 delay
.frag
->fr_fix
-= branch_disp
;
8055 if (delay
.frag
== ip
->frag
)
8056 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8057 add_fixed_insn (&delay
);
8061 /* If this is not a relaxed branch and we are in the
8062 same frag, then just swap the instructions. */
8063 move_insn (ip
, delay
.frag
, delay
.where
);
8064 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8068 insert_into_history (0, 1, &delay
);
8073 /* If we have just completed an unconditional branch, clear the history. */
8074 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8075 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8079 mips_no_prev_insn ();
8081 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8082 history
[i
].cleared_p
= 1;
8085 /* We need to emit a label at the end of branch-likely macros. */
8086 if (emit_branch_likely_macro
)
8088 emit_branch_likely_macro
= FALSE
;
8089 micromips_add_label ();
8092 /* We just output an insn, so the next one doesn't have a label. */
8093 mips_clear_insn_labels ();
8096 /* Forget that there was any previous instruction or label.
8097 When BRANCH is true, the branch history is also flushed. */
8100 mips_no_prev_insn (void)
8102 prev_nop_frag
= NULL
;
8103 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8104 mips_clear_insn_labels ();
8107 /* This function must be called before we emit something other than
8108 instructions. It is like mips_no_prev_insn except that it inserts
8109 any NOPS that might be needed by previous instructions. */
8112 mips_emit_delays (void)
8114 if (! mips_opts
.noreorder
)
8116 int nops
= nops_for_insn (0, history
, NULL
);
8120 add_fixed_insn (NOP_INSN
);
8121 mips_move_text_labels ();
8124 mips_no_prev_insn ();
8127 /* Start a (possibly nested) noreorder block. */
8130 start_noreorder (void)
8132 if (mips_opts
.noreorder
== 0)
8137 /* None of the instructions before the .set noreorder can be moved. */
8138 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8139 history
[i
].fixed_p
= 1;
8141 /* Insert any nops that might be needed between the .set noreorder
8142 block and the previous instructions. We will later remove any
8143 nops that turn out not to be needed. */
8144 nops
= nops_for_insn (0, history
, NULL
);
8147 if (mips_optimize
!= 0)
8149 /* Record the frag which holds the nop instructions, so
8150 that we can remove them if we don't need them. */
8151 frag_grow (nops
* NOP_INSN_SIZE
);
8152 prev_nop_frag
= frag_now
;
8153 prev_nop_frag_holds
= nops
;
8154 prev_nop_frag_required
= 0;
8155 prev_nop_frag_since
= 0;
8158 for (; nops
> 0; --nops
)
8159 add_fixed_insn (NOP_INSN
);
8161 /* Move on to a new frag, so that it is safe to simply
8162 decrease the size of prev_nop_frag. */
8163 frag_wane (frag_now
);
8165 mips_move_text_labels ();
8167 mips_mark_labels ();
8168 mips_clear_insn_labels ();
8170 mips_opts
.noreorder
++;
8171 mips_any_noreorder
= 1;
8174 /* End a nested noreorder block. */
8177 end_noreorder (void)
8179 mips_opts
.noreorder
--;
8180 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8182 /* Commit to inserting prev_nop_frag_required nops and go back to
8183 handling nop insertion the .set reorder way. */
8184 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8186 insert_into_history (prev_nop_frag_since
,
8187 prev_nop_frag_required
, NOP_INSN
);
8188 prev_nop_frag
= NULL
;
8192 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8193 higher bits unset. */
8196 normalize_constant_expr (expressionS
*ex
)
8198 if (ex
->X_op
== O_constant
8199 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8200 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8204 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8205 all higher bits unset. */
8208 normalize_address_expr (expressionS
*ex
)
8210 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8211 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8212 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8213 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8217 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8218 Return true if the match was successful.
8220 OPCODE_EXTRA is a value that should be ORed into the opcode
8221 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8222 there are more alternatives after OPCODE and SOFT_MATCH is
8223 as for mips_arg_info. */
8226 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8227 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8228 bfd_boolean lax_match
, bfd_boolean complete_p
)
8231 struct mips_arg_info arg
;
8232 const struct mips_operand
*operand
;
8235 imm_expr
.X_op
= O_absent
;
8236 offset_expr
.X_op
= O_absent
;
8237 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8238 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8239 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8241 create_insn (insn
, opcode
);
8242 /* When no opcode suffix is specified, assume ".xyzw". */
8243 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8244 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8246 insn
->insn_opcode
|= opcode_extra
;
8247 memset (&arg
, 0, sizeof (arg
));
8251 arg
.last_regno
= ILLEGAL_REG
;
8252 arg
.dest_regno
= ILLEGAL_REG
;
8253 arg
.lax_match
= lax_match
;
8254 for (args
= opcode
->args
;; ++args
)
8256 if (arg
.token
->type
== OT_END
)
8258 /* Handle unary instructions in which only one operand is given.
8259 The source is then the same as the destination. */
8260 if (arg
.opnum
== 1 && *args
== ',')
8262 operand
= (mips_opts
.micromips
8263 ? decode_micromips_operand (args
+ 1)
8264 : decode_mips_operand (args
+ 1));
8265 if (operand
&& mips_optional_operand_p (operand
))
8273 /* Treat elided base registers as $0. */
8274 if (strcmp (args
, "(b)") == 0)
8282 /* The register suffix is optional. */
8287 /* Fail the match if there were too few operands. */
8291 /* Successful match. */
8294 clear_insn_error ();
8295 if (arg
.dest_regno
== arg
.last_regno
8296 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8300 (0, _("source and destination must be different"));
8301 else if (arg
.last_regno
== 31)
8303 (0, _("a destination register must be supplied"));
8305 else if (arg
.last_regno
== 31
8306 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8307 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8308 set_insn_error (0, _("the source register must not be $31"));
8309 check_completed_insn (&arg
);
8313 /* Fail the match if the line has too many operands. */
8317 /* Handle characters that need to match exactly. */
8318 if (*args
== '(' || *args
== ')' || *args
== ',')
8320 if (match_char (&arg
, *args
))
8327 if (arg
.token
->type
== OT_DOUBLE_CHAR
8328 && arg
.token
->u
.ch
== *args
)
8336 /* Handle special macro operands. Work out the properties of
8345 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8349 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8358 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8362 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8366 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8372 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8374 imm_expr
.X_op
= O_constant
;
8376 normalize_constant_expr (&imm_expr
);
8380 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8382 /* Assume that the offset has been elided and that what
8383 we saw was a base register. The match will fail later
8384 if that assumption turns out to be wrong. */
8385 offset_expr
.X_op
= O_constant
;
8386 offset_expr
.X_add_number
= 0;
8390 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8392 normalize_address_expr (&offset_expr
);
8397 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8403 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8409 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8415 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8421 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8425 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8429 gas_assert (mips_opts
.micromips
);
8435 if (!forced_insn_length
)
8436 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8438 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8440 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8446 operand
= (mips_opts
.micromips
8447 ? decode_micromips_operand (args
)
8448 : decode_mips_operand (args
));
8452 /* Skip prefixes. */
8453 if (*args
== '+' || *args
== 'm' || *args
== '-')
8456 if (mips_optional_operand_p (operand
)
8458 && (arg
.token
[0].type
!= OT_REG
8459 || arg
.token
[1].type
== OT_END
))
8461 /* Assume that the register has been elided and is the
8462 same as the first operand. */
8467 if (!match_operand (&arg
, operand
))
8472 /* Like match_insn, but for MIPS16. */
8475 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8476 struct mips_operand_token
*tokens
)
8479 const struct mips_operand
*operand
;
8480 const struct mips_operand
*ext_operand
;
8481 bfd_boolean pcrel
= FALSE
;
8482 int required_insn_length
;
8483 struct mips_arg_info arg
;
8486 if (forced_insn_length
)
8487 required_insn_length
= forced_insn_length
;
8488 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8489 required_insn_length
= 2;
8491 required_insn_length
= 0;
8493 create_insn (insn
, opcode
);
8494 imm_expr
.X_op
= O_absent
;
8495 offset_expr
.X_op
= O_absent
;
8496 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8497 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8498 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8501 memset (&arg
, 0, sizeof (arg
));
8505 arg
.last_regno
= ILLEGAL_REG
;
8506 arg
.dest_regno
= ILLEGAL_REG
;
8508 for (args
= opcode
->args
;; ++args
)
8512 if (arg
.token
->type
== OT_END
)
8516 /* Handle unary instructions in which only one operand is given.
8517 The source is then the same as the destination. */
8518 if (arg
.opnum
== 1 && *args
== ',')
8520 operand
= decode_mips16_operand (args
[1], FALSE
);
8521 if (operand
&& mips_optional_operand_p (operand
))
8529 /* Fail the match if there were too few operands. */
8533 /* Successful match. Stuff the immediate value in now, if
8535 clear_insn_error ();
8536 if (opcode
->pinfo
== INSN_MACRO
)
8538 gas_assert (relax_char
== 0 || relax_char
== 'p');
8539 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8542 && offset_expr
.X_op
== O_constant
8544 && calculate_reloc (*offset_reloc
,
8545 offset_expr
.X_add_number
,
8548 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8549 required_insn_length
, &insn
->insn_opcode
);
8550 offset_expr
.X_op
= O_absent
;
8551 *offset_reloc
= BFD_RELOC_UNUSED
;
8553 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8555 if (required_insn_length
== 2)
8556 set_insn_error (0, _("invalid unextended operand value"));
8557 else if (!mips_opcode_32bit_p (opcode
))
8559 forced_insn_length
= 4;
8560 insn
->insn_opcode
|= MIPS16_EXTEND
;
8563 else if (relax_char
)
8564 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8566 check_completed_insn (&arg
);
8570 /* Fail the match if the line has too many operands. */
8574 /* Handle characters that need to match exactly. */
8575 if (*args
== '(' || *args
== ')' || *args
== ',')
8577 if (match_char (&arg
, *args
))
8597 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8599 imm_expr
.X_op
= O_constant
;
8601 normalize_constant_expr (&imm_expr
);
8606 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8610 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8614 if (operand
->type
== OP_PCREL
)
8618 ext_operand
= decode_mips16_operand (c
, TRUE
);
8619 if (operand
!= ext_operand
)
8621 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8623 offset_expr
.X_op
= O_constant
;
8624 offset_expr
.X_add_number
= 0;
8629 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8632 /* '8' is used for SLTI(U) and has traditionally not
8633 been allowed to take relocation operators. */
8634 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8635 && (ext_operand
->size
!= 16 || c
== '8'))
8637 match_not_constant (&arg
);
8641 if (offset_expr
.X_op
== O_big
)
8643 match_out_of_range (&arg
);
8652 if (mips_optional_operand_p (operand
)
8654 && (arg
.token
[0].type
!= OT_REG
8655 || arg
.token
[1].type
== OT_END
))
8657 /* Assume that the register has been elided and is the
8658 same as the first operand. */
8663 if (!match_operand (&arg
, operand
))
8668 /* Record that the current instruction is invalid for the current ISA. */
8671 match_invalid_for_isa (void)
8674 (0, _("opcode not supported on this processor: %s (%s)"),
8675 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8676 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8679 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8680 Return true if a definite match or failure was found, storing any match
8681 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8682 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8683 tried and failed to match under normal conditions and now want to try a
8684 more relaxed match. */
8687 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8688 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8689 int opcode_extra
, bfd_boolean lax_match
)
8691 const struct mips_opcode
*opcode
;
8692 const struct mips_opcode
*invalid_delay_slot
;
8693 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8695 /* Search for a match, ignoring alternatives that don't satisfy the
8696 current ISA or forced_length. */
8697 invalid_delay_slot
= 0;
8698 seen_valid_for_isa
= FALSE
;
8699 seen_valid_for_size
= FALSE
;
8703 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8704 if (is_opcode_valid (opcode
))
8706 seen_valid_for_isa
= TRUE
;
8707 if (is_size_valid (opcode
))
8709 bfd_boolean delay_slot_ok
;
8711 seen_valid_for_size
= TRUE
;
8712 delay_slot_ok
= is_delay_slot_valid (opcode
);
8713 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8714 lax_match
, delay_slot_ok
))
8718 if (!invalid_delay_slot
)
8719 invalid_delay_slot
= opcode
;
8728 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8730 /* If the only matches we found had the wrong length for the delay slot,
8731 pick the first such match. We'll issue an appropriate warning later. */
8732 if (invalid_delay_slot
)
8734 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8740 /* Handle the case where we didn't try to match an instruction because
8741 all the alternatives were incompatible with the current ISA. */
8742 if (!seen_valid_for_isa
)
8744 match_invalid_for_isa ();
8748 /* Handle the case where we didn't try to match an instruction because
8749 all the alternatives were of the wrong size. */
8750 if (!seen_valid_for_size
)
8752 if (mips_opts
.insn32
)
8753 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8756 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8757 8 * forced_insn_length
);
8764 /* Like match_insns, but for MIPS16. */
8767 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8768 struct mips_operand_token
*tokens
)
8770 const struct mips_opcode
*opcode
;
8771 bfd_boolean seen_valid_for_isa
;
8772 bfd_boolean seen_valid_for_size
;
8774 /* Search for a match, ignoring alternatives that don't satisfy the
8775 current ISA. There are no separate entries for extended forms so
8776 we deal with forced_length later. */
8777 seen_valid_for_isa
= FALSE
;
8778 seen_valid_for_size
= FALSE
;
8782 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8783 if (is_opcode_valid_16 (opcode
))
8785 seen_valid_for_isa
= TRUE
;
8786 if (is_size_valid_16 (opcode
))
8788 seen_valid_for_size
= TRUE
;
8789 if (match_mips16_insn (insn
, opcode
, tokens
))
8795 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8796 && strcmp (opcode
->name
, first
->name
) == 0);
8798 /* Handle the case where we didn't try to match an instruction because
8799 all the alternatives were incompatible with the current ISA. */
8800 if (!seen_valid_for_isa
)
8802 match_invalid_for_isa ();
8806 /* Handle the case where we didn't try to match an instruction because
8807 all the alternatives were of the wrong size. */
8808 if (!seen_valid_for_size
)
8810 if (forced_insn_length
== 2)
8812 (0, _("unrecognized unextended version of MIPS16 opcode"));
8815 (0, _("unrecognized extended version of MIPS16 opcode"));
8822 /* Set up global variables for the start of a new macro. */
8827 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8828 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8829 sizeof (mips_macro_warning
.first_insn_sizes
));
8830 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8831 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8832 && delayed_branch_p (&history
[0]));
8834 && history
[0].frag
->fr_type
== rs_machine_dependent
8835 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8836 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8837 mips_macro_warning
.delay_slot_length
= 0;
8839 switch (history
[0].insn_mo
->pinfo2
8840 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8842 case INSN2_BRANCH_DELAY_32BIT
:
8843 mips_macro_warning
.delay_slot_length
= 4;
8845 case INSN2_BRANCH_DELAY_16BIT
:
8846 mips_macro_warning
.delay_slot_length
= 2;
8849 mips_macro_warning
.delay_slot_length
= 0;
8852 mips_macro_warning
.first_frag
= NULL
;
8855 /* Given that a macro is longer than one instruction or of the wrong size,
8856 return the appropriate warning for it. Return null if no warning is
8857 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8858 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8859 and RELAX_NOMACRO. */
8862 macro_warning (relax_substateT subtype
)
8864 if (subtype
& RELAX_DELAY_SLOT
)
8865 return _("macro instruction expanded into multiple instructions"
8866 " in a branch delay slot");
8867 else if (subtype
& RELAX_NOMACRO
)
8868 return _("macro instruction expanded into multiple instructions");
8869 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8870 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8871 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8872 ? _("macro instruction expanded into a wrong size instruction"
8873 " in a 16-bit branch delay slot")
8874 : _("macro instruction expanded into a wrong size instruction"
8875 " in a 32-bit branch delay slot"));
8880 /* Finish up a macro. Emit warnings as appropriate. */
8885 /* Relaxation warning flags. */
8886 relax_substateT subtype
= 0;
8888 /* Check delay slot size requirements. */
8889 if (mips_macro_warning
.delay_slot_length
== 2)
8890 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8891 if (mips_macro_warning
.delay_slot_length
!= 0)
8893 if (mips_macro_warning
.delay_slot_length
8894 != mips_macro_warning
.first_insn_sizes
[0])
8895 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8896 if (mips_macro_warning
.delay_slot_length
8897 != mips_macro_warning
.first_insn_sizes
[1])
8898 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8901 /* Check instruction count requirements. */
8902 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8904 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8905 subtype
|= RELAX_SECOND_LONGER
;
8906 if (mips_opts
.warn_about_macros
)
8907 subtype
|= RELAX_NOMACRO
;
8908 if (mips_macro_warning
.delay_slot_p
)
8909 subtype
|= RELAX_DELAY_SLOT
;
8912 /* If both alternatives fail to fill a delay slot correctly,
8913 emit the warning now. */
8914 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8915 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8920 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8921 | RELAX_DELAY_SLOT_SIZE_FIRST
8922 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8923 msg
= macro_warning (s
);
8925 as_warn ("%s", msg
);
8929 /* If both implementations are longer than 1 instruction, then emit the
8931 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8936 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8937 msg
= macro_warning (s
);
8939 as_warn ("%s", msg
);
8943 /* If any flags still set, then one implementation might need a warning
8944 and the other either will need one of a different kind or none at all.
8945 Pass any remaining flags over to relaxation. */
8946 if (mips_macro_warning
.first_frag
!= NULL
)
8947 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8950 /* Instruction operand formats used in macros that vary between
8951 standard MIPS and microMIPS code. */
8953 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8954 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8955 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8956 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8957 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8958 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8959 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8960 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8962 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8963 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8964 : cop12_fmt[mips_opts.micromips])
8965 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8966 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8967 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8968 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8969 : mem12_fmt[mips_opts.micromips])
8970 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8971 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8972 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8974 /* Read a macro's relocation codes from *ARGS and store them in *R.
8975 The first argument in *ARGS will be either the code for a single
8976 relocation or -1 followed by the three codes that make up a
8977 composite relocation. */
8980 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8984 next
= va_arg (*args
, int);
8986 r
[0] = (bfd_reloc_code_real_type
) next
;
8989 for (i
= 0; i
< 3; i
++)
8990 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8991 /* This function is only used for 16-bit relocation fields.
8992 To make the macro code simpler, treat an unrelocated value
8993 in the same way as BFD_RELOC_LO16. */
8994 if (r
[0] == BFD_RELOC_UNUSED
)
8995 r
[0] = BFD_RELOC_LO16
;
8999 /* Build an instruction created by a macro expansion. This is passed
9000 a pointer to the count of instructions created so far, an
9001 expression, the name of the instruction to build, an operand format
9002 string, and corresponding arguments. */
9005 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
9007 const struct mips_opcode
*mo
= NULL
;
9008 bfd_reloc_code_real_type r
[3];
9009 const struct mips_opcode
*amo
;
9010 const struct mips_operand
*operand
;
9012 struct mips_cl_insn insn
;
9016 va_start (args
, fmt
);
9018 if (mips_opts
.mips16
)
9020 mips16_macro_build (ep
, name
, fmt
, &args
);
9025 r
[0] = BFD_RELOC_UNUSED
;
9026 r
[1] = BFD_RELOC_UNUSED
;
9027 r
[2] = BFD_RELOC_UNUSED
;
9028 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9029 amo
= (struct mips_opcode
*) str_hash_find (hash
, name
);
9031 gas_assert (strcmp (name
, amo
->name
) == 0);
9035 /* Search until we get a match for NAME. It is assumed here that
9036 macros will never generate MDMX, MIPS-3D, or MT instructions.
9037 We try to match an instruction that fulfills the branch delay
9038 slot instruction length requirement (if any) of the previous
9039 instruction. While doing this we record the first instruction
9040 seen that matches all the other conditions and use it anyway
9041 if the requirement cannot be met; we will issue an appropriate
9042 warning later on. */
9043 if (strcmp (fmt
, amo
->args
) == 0
9044 && amo
->pinfo
!= INSN_MACRO
9045 && is_opcode_valid (amo
)
9046 && is_size_valid (amo
))
9048 if (is_delay_slot_valid (amo
))
9058 gas_assert (amo
->name
);
9060 while (strcmp (name
, amo
->name
) == 0);
9063 create_insn (&insn
, mo
);
9076 macro_read_relocs (&args
, r
);
9077 gas_assert (*r
== BFD_RELOC_GPREL16
9078 || *r
== BFD_RELOC_MIPS_HIGHER
9079 || *r
== BFD_RELOC_HI16_S
9080 || *r
== BFD_RELOC_LO16
9081 || *r
== BFD_RELOC_MIPS_GOT_OFST
9082 || (mips_opts
.micromips
9083 && (*r
== BFD_RELOC_16
9084 || *r
== BFD_RELOC_MIPS_GOT16
9085 || *r
== BFD_RELOC_MIPS_CALL16
9086 || *r
== BFD_RELOC_MIPS_GOT_HI16
9087 || *r
== BFD_RELOC_MIPS_GOT_LO16
9088 || *r
== BFD_RELOC_MIPS_CALL_HI16
9089 || *r
== BFD_RELOC_MIPS_CALL_LO16
9090 || *r
== BFD_RELOC_MIPS_SUB
9091 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9092 || *r
== BFD_RELOC_MIPS_HIGHEST
9093 || *r
== BFD_RELOC_MIPS_GOT_DISP
9094 || *r
== BFD_RELOC_MIPS_TLS_GD
9095 || *r
== BFD_RELOC_MIPS_TLS_LDM
9096 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9097 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9098 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9099 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9100 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9104 macro_read_relocs (&args
, r
);
9108 macro_read_relocs (&args
, r
);
9109 gas_assert (ep
!= NULL
9110 && (ep
->X_op
== O_constant
9111 || (ep
->X_op
== O_symbol
9112 && (*r
== BFD_RELOC_MIPS_HIGHEST
9113 || *r
== BFD_RELOC_HI16_S
9114 || *r
== BFD_RELOC_HI16
9115 || *r
== BFD_RELOC_GPREL16
9116 || *r
== BFD_RELOC_MIPS_GOT_HI16
9117 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9121 gas_assert (ep
!= NULL
);
9124 * This allows macro() to pass an immediate expression for
9125 * creating short branches without creating a symbol.
9127 * We don't allow branch relaxation for these branches, as
9128 * they should only appear in ".set nomacro" anyway.
9130 if (ep
->X_op
== O_constant
)
9132 /* For microMIPS we always use relocations for branches.
9133 So we should not resolve immediate values. */
9134 gas_assert (!mips_opts
.micromips
);
9136 if ((ep
->X_add_number
& 3) != 0)
9137 as_bad (_("branch to misaligned address (0x%lx)"),
9138 (unsigned long) ep
->X_add_number
);
9139 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9140 as_bad (_("branch address range overflow (0x%lx)"),
9141 (unsigned long) ep
->X_add_number
);
9142 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9146 *r
= BFD_RELOC_16_PCREL_S2
;
9150 gas_assert (ep
!= NULL
);
9151 *r
= BFD_RELOC_MIPS_JMP
;
9155 operand
= (mips_opts
.micromips
9156 ? decode_micromips_operand (fmt
)
9157 : decode_mips_operand (fmt
));
9161 uval
= va_arg (args
, int);
9162 if (operand
->type
== OP_CLO_CLZ_DEST
)
9163 uval
|= (uval
<< 5);
9164 insn_insert_operand (&insn
, operand
, uval
);
9166 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9172 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9174 append_insn (&insn
, ep
, r
, TRUE
);
9178 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9181 struct mips_opcode
*mo
;
9182 struct mips_cl_insn insn
;
9183 const struct mips_operand
*operand
;
9184 bfd_reloc_code_real_type r
[3]
9185 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9187 mo
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, name
);
9189 gas_assert (strcmp (name
, mo
->name
) == 0);
9191 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9194 gas_assert (mo
->name
);
9195 gas_assert (strcmp (name
, mo
->name
) == 0);
9198 create_insn (&insn
, mo
);
9235 gas_assert (ep
!= NULL
);
9237 if (ep
->X_op
!= O_constant
)
9238 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9239 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9241 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9243 *r
= BFD_RELOC_UNUSED
;
9249 operand
= decode_mips16_operand (c
, FALSE
);
9253 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9258 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9260 append_insn (&insn
, ep
, r
, TRUE
);
9264 * Generate a "jalr" instruction with a relocation hint to the called
9265 * function. This occurs in NewABI PIC code.
9268 macro_build_jalr (expressionS
*ep
, int cprestore
)
9270 static const bfd_reloc_code_real_type jalr_relocs
[2]
9271 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9272 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9276 if (MIPS_JALR_HINT_P (ep
))
9281 if (mips_opts
.micromips
)
9283 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9284 ? "jalr" : "jalrs");
9285 if (MIPS_JALR_HINT_P (ep
)
9287 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9288 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9290 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9293 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9294 if (MIPS_JALR_HINT_P (ep
))
9295 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9299 * Generate a "lui" instruction.
9302 macro_build_lui (expressionS
*ep
, int regnum
)
9304 gas_assert (! mips_opts
.mips16
);
9306 if (ep
->X_op
!= O_constant
)
9308 gas_assert (ep
->X_op
== O_symbol
);
9309 /* _gp_disp is a special case, used from s_cpload.
9310 __gnu_local_gp is used if mips_no_shared. */
9311 gas_assert (mips_pic
== NO_PIC
9313 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9314 || (! mips_in_shared
9315 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9316 "__gnu_local_gp") == 0));
9319 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9322 /* Generate a sequence of instructions to do a load or store from a constant
9323 offset off of a base register (breg) into/from a target register (treg),
9324 using AT if necessary. */
9326 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9327 int treg
, int breg
, int dbl
)
9329 gas_assert (ep
->X_op
== O_constant
);
9331 /* Sign-extending 32-bit constants makes their handling easier. */
9333 normalize_constant_expr (ep
);
9335 /* Right now, this routine can only handle signed 32-bit constants. */
9336 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9337 as_warn (_("operand overflow"));
9339 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9341 /* Signed 16-bit offset will fit in the op. Easy! */
9342 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9346 /* 32-bit offset, need multiple instructions and AT, like:
9347 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9348 addu $tempreg,$tempreg,$breg
9349 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9350 to handle the complete offset. */
9351 macro_build_lui (ep
, AT
);
9352 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9353 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9356 as_bad (_("macro used $at after \".set noat\""));
9361 * Generates code to set the $at register to true (one)
9362 * if reg is less than the immediate expression.
9365 set_at (int reg
, int unsignedp
)
9367 if (imm_expr
.X_add_number
>= -0x8000
9368 && imm_expr
.X_add_number
< 0x8000)
9369 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9370 AT
, reg
, BFD_RELOC_LO16
);
9373 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9374 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9378 /* Count the leading zeroes by performing a binary chop. This is a
9379 bulky bit of source, but performance is a LOT better for the
9380 majority of values than a simple loop to count the bits:
9381 for (lcnt = 0; (lcnt < 32); lcnt++)
9382 if ((v) & (1 << (31 - lcnt)))
9384 However it is not code size friendly, and the gain will drop a bit
9385 on certain cached systems.
9387 #define COUNT_TOP_ZEROES(v) \
9388 (((v) & ~0xffff) == 0 \
9389 ? ((v) & ~0xff) == 0 \
9390 ? ((v) & ~0xf) == 0 \
9391 ? ((v) & ~0x3) == 0 \
9392 ? ((v) & ~0x1) == 0 \
9397 : ((v) & ~0x7) == 0 \
9400 : ((v) & ~0x3f) == 0 \
9401 ? ((v) & ~0x1f) == 0 \
9404 : ((v) & ~0x7f) == 0 \
9407 : ((v) & ~0xfff) == 0 \
9408 ? ((v) & ~0x3ff) == 0 \
9409 ? ((v) & ~0x1ff) == 0 \
9412 : ((v) & ~0x7ff) == 0 \
9415 : ((v) & ~0x3fff) == 0 \
9416 ? ((v) & ~0x1fff) == 0 \
9419 : ((v) & ~0x7fff) == 0 \
9422 : ((v) & ~0xffffff) == 0 \
9423 ? ((v) & ~0xfffff) == 0 \
9424 ? ((v) & ~0x3ffff) == 0 \
9425 ? ((v) & ~0x1ffff) == 0 \
9428 : ((v) & ~0x7ffff) == 0 \
9431 : ((v) & ~0x3fffff) == 0 \
9432 ? ((v) & ~0x1fffff) == 0 \
9435 : ((v) & ~0x7fffff) == 0 \
9438 : ((v) & ~0xfffffff) == 0 \
9439 ? ((v) & ~0x3ffffff) == 0 \
9440 ? ((v) & ~0x1ffffff) == 0 \
9443 : ((v) & ~0x7ffffff) == 0 \
9446 : ((v) & ~0x3fffffff) == 0 \
9447 ? ((v) & ~0x1fffffff) == 0 \
9450 : ((v) & ~0x7fffffff) == 0 \
9455 * This routine generates the least number of instructions necessary to load
9456 * an absolute expression value into a register.
9459 load_register (int reg
, expressionS
*ep
, int dbl
)
9462 expressionS hi32
, lo32
;
9464 if (ep
->X_op
!= O_big
)
9466 gas_assert (ep
->X_op
== O_constant
);
9468 /* Sign-extending 32-bit constants makes their handling easier. */
9470 normalize_constant_expr (ep
);
9472 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9474 /* We can handle 16 bit signed values with an addiu to
9475 $zero. No need to ever use daddiu here, since $zero and
9476 the result are always correct in 32 bit mode. */
9477 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9480 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9482 /* We can handle 16 bit unsigned values with an ori to
9484 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9487 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9489 /* 32 bit values require an lui. */
9490 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9491 if ((ep
->X_add_number
& 0xffff) != 0)
9492 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9497 /* The value is larger than 32 bits. */
9499 if (!dbl
|| GPR_SIZE
== 32)
9503 sprintf_vma (value
, ep
->X_add_number
);
9504 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9505 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9509 if (ep
->X_op
!= O_big
)
9512 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9513 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9514 hi32
.X_add_number
&= 0xffffffff;
9516 lo32
.X_add_number
&= 0xffffffff;
9520 gas_assert (ep
->X_add_number
> 2);
9521 if (ep
->X_add_number
== 3)
9522 generic_bignum
[3] = 0;
9523 else if (ep
->X_add_number
> 4)
9524 as_bad (_("number larger than 64 bits"));
9525 lo32
.X_op
= O_constant
;
9526 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9527 hi32
.X_op
= O_constant
;
9528 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9531 if (hi32
.X_add_number
== 0)
9536 unsigned long hi
, lo
;
9538 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9540 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9542 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9545 if (lo32
.X_add_number
& 0x80000000)
9547 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9548 if (lo32
.X_add_number
& 0xffff)
9549 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9554 /* Check for 16bit shifted constant. We know that hi32 is
9555 non-zero, so start the mask on the first bit of the hi32
9560 unsigned long himask
, lomask
;
9564 himask
= 0xffff >> (32 - shift
);
9565 lomask
= (0xffff << shift
) & 0xffffffff;
9569 himask
= 0xffff << (shift
- 32);
9572 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9573 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9577 tmp
.X_op
= O_constant
;
9579 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9580 | (lo32
.X_add_number
>> shift
));
9582 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9583 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9584 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9585 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9590 while (shift
<= (64 - 16));
9592 /* Find the bit number of the lowest one bit, and store the
9593 shifted value in hi/lo. */
9594 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9595 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9599 while ((lo
& 1) == 0)
9604 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9610 while ((hi
& 1) == 0)
9619 /* Optimize if the shifted value is a (power of 2) - 1. */
9620 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9621 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9623 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9628 /* This instruction will set the register to be all
9630 tmp
.X_op
= O_constant
;
9631 tmp
.X_add_number
= (offsetT
) -1;
9632 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9636 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9637 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9639 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9640 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9645 /* Sign extend hi32 before calling load_register, because we can
9646 generally get better code when we load a sign extended value. */
9647 if ((hi32
.X_add_number
& 0x80000000) != 0)
9648 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9649 load_register (reg
, &hi32
, 0);
9652 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9656 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9664 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9666 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9667 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9673 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9677 mid16
.X_add_number
>>= 16;
9678 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9679 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9682 if ((lo32
.X_add_number
& 0xffff) != 0)
9683 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9687 load_delay_nop (void)
9689 if (!gpr_interlocks
)
9690 macro_build (NULL
, "nop", "");
9693 /* Load an address into a register. */
9696 load_address (int reg
, expressionS
*ep
, int *used_at
)
9698 if (ep
->X_op
!= O_constant
9699 && ep
->X_op
!= O_symbol
)
9701 as_bad (_("expression too complex"));
9702 ep
->X_op
= O_constant
;
9705 if (ep
->X_op
== O_constant
)
9707 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9711 if (mips_pic
== NO_PIC
)
9713 /* If this is a reference to a GP relative symbol, we want
9714 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9716 lui $reg,<sym> (BFD_RELOC_HI16_S)
9717 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9718 If we have an addend, we always use the latter form.
9720 With 64bit address space and a usable $at we want
9721 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9722 lui $at,<sym> (BFD_RELOC_HI16_S)
9723 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9724 daddiu $at,<sym> (BFD_RELOC_LO16)
9728 If $at is already in use, we use a path which is suboptimal
9729 on superscalar processors.
9730 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9731 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9733 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9735 daddiu $reg,<sym> (BFD_RELOC_LO16)
9737 For GP relative symbols in 64bit address space we can use
9738 the same sequence as in 32bit address space. */
9739 if (HAVE_64BIT_SYMBOLS
)
9741 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9742 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9744 relax_start (ep
->X_add_symbol
);
9745 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9746 mips_gp_register
, BFD_RELOC_GPREL16
);
9750 if (*used_at
== 0 && mips_opts
.at
)
9752 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9753 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9754 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9755 BFD_RELOC_MIPS_HIGHER
);
9756 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9757 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9758 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9763 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9764 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9765 BFD_RELOC_MIPS_HIGHER
);
9766 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9767 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9768 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9769 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9772 if (mips_relax
.sequence
)
9777 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9778 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9780 relax_start (ep
->X_add_symbol
);
9781 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9782 mips_gp_register
, BFD_RELOC_GPREL16
);
9785 macro_build_lui (ep
, reg
);
9786 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9787 reg
, reg
, BFD_RELOC_LO16
);
9788 if (mips_relax
.sequence
)
9792 else if (!mips_big_got
)
9796 /* If this is a reference to an external symbol, we want
9797 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9799 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9801 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9802 If there is a constant, it must be added in after.
9804 If we have NewABI, we want
9805 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9806 unless we're referencing a global symbol with a non-zero
9807 offset, in which case cst must be added separately. */
9810 if (ep
->X_add_number
)
9812 ex
.X_add_number
= ep
->X_add_number
;
9813 ep
->X_add_number
= 0;
9814 relax_start (ep
->X_add_symbol
);
9815 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9816 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9817 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9818 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9819 ex
.X_op
= O_constant
;
9820 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9821 reg
, reg
, BFD_RELOC_LO16
);
9822 ep
->X_add_number
= ex
.X_add_number
;
9825 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9826 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9827 if (mips_relax
.sequence
)
9832 ex
.X_add_number
= ep
->X_add_number
;
9833 ep
->X_add_number
= 0;
9834 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9835 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9837 relax_start (ep
->X_add_symbol
);
9839 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9843 if (ex
.X_add_number
!= 0)
9845 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9846 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9847 ex
.X_op
= O_constant
;
9848 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9849 reg
, reg
, BFD_RELOC_LO16
);
9853 else if (mips_big_got
)
9857 /* This is the large GOT case. If this is a reference to an
9858 external symbol, we want
9859 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9861 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9863 Otherwise, for a reference to a local symbol in old ABI, we want
9864 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9866 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9867 If there is a constant, it must be added in after.
9869 In the NewABI, for local symbols, with or without offsets, we want:
9870 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9871 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9875 ex
.X_add_number
= ep
->X_add_number
;
9876 ep
->X_add_number
= 0;
9877 relax_start (ep
->X_add_symbol
);
9878 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9879 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9880 reg
, reg
, mips_gp_register
);
9881 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9882 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9883 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9884 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9885 else if (ex
.X_add_number
)
9887 ex
.X_op
= O_constant
;
9888 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9892 ep
->X_add_number
= ex
.X_add_number
;
9894 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9895 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9896 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9897 BFD_RELOC_MIPS_GOT_OFST
);
9902 ex
.X_add_number
= ep
->X_add_number
;
9903 ep
->X_add_number
= 0;
9904 relax_start (ep
->X_add_symbol
);
9905 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9906 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9907 reg
, reg
, mips_gp_register
);
9908 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9909 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9911 if (reg_needs_delay (mips_gp_register
))
9913 /* We need a nop before loading from $gp. This special
9914 check is required because the lui which starts the main
9915 instruction stream does not refer to $gp, and so will not
9916 insert the nop which may be required. */
9917 macro_build (NULL
, "nop", "");
9919 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9920 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9922 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9926 if (ex
.X_add_number
!= 0)
9928 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9929 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9930 ex
.X_op
= O_constant
;
9931 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9939 if (!mips_opts
.at
&& *used_at
== 1)
9940 as_bad (_("macro used $at after \".set noat\""));
9943 /* Move the contents of register SOURCE into register DEST. */
9946 move_register (int dest
, int source
)
9948 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9949 instruction specifically requires a 32-bit one. */
9950 if (mips_opts
.micromips
9951 && !mips_opts
.insn32
9952 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9953 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9955 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9958 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9959 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9960 The two alternatives are:
9962 Global symbol Local symbol
9963 ------------- ------------
9964 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9966 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9968 load_got_offset emits the first instruction and add_got_offset
9969 emits the second for a 16-bit offset or add_got_offset_hilo emits
9970 a sequence to add a 32-bit offset using a scratch register. */
9973 load_got_offset (int dest
, expressionS
*local
)
9978 global
.X_add_number
= 0;
9980 relax_start (local
->X_add_symbol
);
9981 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9982 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9984 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9985 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9990 add_got_offset (int dest
, expressionS
*local
)
9994 global
.X_op
= O_constant
;
9995 global
.X_op_symbol
= NULL
;
9996 global
.X_add_symbol
= NULL
;
9997 global
.X_add_number
= local
->X_add_number
;
9999 relax_start (local
->X_add_symbol
);
10000 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
10001 dest
, dest
, BFD_RELOC_LO16
);
10003 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
10008 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
10010 expressionS global
;
10011 int hold_mips_optimize
;
10013 global
.X_op
= O_constant
;
10014 global
.X_op_symbol
= NULL
;
10015 global
.X_add_symbol
= NULL
;
10016 global
.X_add_number
= local
->X_add_number
;
10018 relax_start (local
->X_add_symbol
);
10019 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10021 /* Set mips_optimize around the lui instruction to avoid
10022 inserting an unnecessary nop after the lw. */
10023 hold_mips_optimize
= mips_optimize
;
10025 macro_build_lui (&global
, tmp
);
10026 mips_optimize
= hold_mips_optimize
;
10027 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10030 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10033 /* Emit a sequence of instructions to emulate a branch likely operation.
10034 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10035 is its complementing branch with the original condition negated.
10036 CALL is set if the original branch specified the link operation.
10037 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10039 Code like this is produced in the noreorder mode:
10044 delay slot (executed only if branch taken)
10047 or, if CALL is set:
10052 delay slot (executed only if branch taken)
10055 In the reorder mode the delay slot would be filled with a nop anyway,
10056 so code produced is simply:
10061 This function is used when producing code for the microMIPS ASE that
10062 does not implement branch likely instructions in hardware. */
10065 macro_build_branch_likely (const char *br
, const char *brneg
,
10066 int call
, expressionS
*ep
, const char *fmt
,
10067 unsigned int sreg
, unsigned int treg
)
10069 int noreorder
= mips_opts
.noreorder
;
10072 gas_assert (mips_opts
.micromips
);
10073 start_noreorder ();
10076 micromips_label_expr (&expr1
);
10077 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10078 macro_build (NULL
, "nop", "");
10079 macro_build (ep
, call
? "bal" : "b", "p");
10081 /* Set to true so that append_insn adds a label. */
10082 emit_branch_likely_macro
= TRUE
;
10086 macro_build (ep
, br
, fmt
, sreg
, treg
);
10087 macro_build (NULL
, "nop", "");
10092 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10093 the condition code tested. EP specifies the branch target. */
10096 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10098 const int call
= 0;
10123 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10126 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10127 the register tested. EP specifies the branch target. */
10130 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10132 const char *brneg
= NULL
;
10142 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10146 gas_assert (mips_opts
.micromips
);
10147 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10155 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10162 br
= mips_opts
.micromips
? "blez" : "blezl";
10169 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10173 gas_assert (mips_opts
.micromips
);
10174 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10181 if (mips_opts
.micromips
&& brneg
)
10182 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10184 macro_build (ep
, br
, "s,p", sreg
);
10187 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10188 TREG as the registers tested. EP specifies the branch target. */
10191 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10192 unsigned int sreg
, unsigned int treg
)
10194 const char *brneg
= NULL
;
10195 const int call
= 0;
10206 br
= mips_opts
.micromips
? "beq" : "beql";
10215 br
= mips_opts
.micromips
? "bne" : "bnel";
10221 if (mips_opts
.micromips
&& brneg
)
10222 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10224 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10227 /* Return the high part that should be loaded in order to make the low
10228 part of VALUE accessible using an offset of OFFBITS bits. */
10231 offset_high_part (offsetT value
, unsigned int offbits
)
10238 bias
= 1 << (offbits
- 1);
10239 low_mask
= bias
* 2 - 1;
10240 return (value
+ bias
) & ~low_mask
;
10243 /* Return true if the value stored in offset_expr and offset_reloc
10244 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10245 amount that the caller wants to add without inducing overflow
10246 and ALIGN is the known alignment of the value in bytes. */
10249 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10253 /* Accept any relocation operator if overflow isn't a concern. */
10254 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10257 /* These relocations are guaranteed not to overflow in correct links. */
10258 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10259 || gprel16_reloc_p (*offset_reloc
))
10262 if (offset_expr
.X_op
== O_constant
10263 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10264 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10271 * This routine implements the seemingly endless macro or synthesized
10272 * instructions and addressing modes in the mips assembly language. Many
10273 * of these macros are simple and are similar to each other. These could
10274 * probably be handled by some kind of table or grammar approach instead of
10275 * this verbose method. Others are not simple macros but are more like
10276 * optimizing code generation.
10277 * One interesting optimization is when several store macros appear
10278 * consecutively that would load AT with the upper half of the same address.
10279 * The ensuing load upper instructions are omitted. This implies some kind
10280 * of global optimization. We currently only optimize within a single macro.
10281 * For many of the load and store macros if the address is specified as a
10282 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10283 * first load register 'at' with zero and use it as the base register. The
10284 * mips assembler simply uses register $zero. Just one tiny optimization
10288 macro (struct mips_cl_insn
*ip
, char *str
)
10290 const struct mips_operand_array
*operands
;
10291 unsigned int breg
, i
;
10292 unsigned int tempreg
;
10295 expressionS label_expr
;
10310 int ll_sc_paired
= 0;
10311 bfd_boolean large_offset
;
10313 int hold_mips_optimize
;
10314 unsigned int align
;
10315 unsigned int op
[MAX_OPERANDS
];
10317 gas_assert (! mips_opts
.mips16
);
10319 operands
= insn_operands (ip
);
10320 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10321 if (operands
->operand
[i
])
10322 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10326 mask
= ip
->insn_mo
->mask
;
10328 label_expr
.X_op
= O_constant
;
10329 label_expr
.X_op_symbol
= NULL
;
10330 label_expr
.X_add_symbol
= NULL
;
10331 label_expr
.X_add_number
= 0;
10333 expr1
.X_op
= O_constant
;
10334 expr1
.X_op_symbol
= NULL
;
10335 expr1
.X_add_symbol
= NULL
;
10336 expr1
.X_add_number
= 1;
10343 /* Fall through. */
10351 start_noreorder ();
10353 if (mips_opts
.micromips
)
10354 micromips_label_expr (&label_expr
);
10356 label_expr
.X_add_number
= 8;
10357 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10358 if (op
[0] == op
[1])
10359 macro_build (NULL
, "nop", "");
10361 move_register (op
[0], op
[1]);
10362 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10363 if (mips_opts
.micromips
)
10364 micromips_add_label ();
10372 if (ISA_IS_R6 (mips_opts
.isa
))
10384 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10386 if (imm_expr
.X_add_number
>= -0x200
10387 && imm_expr
.X_add_number
< 0x200
10388 && !ISA_IS_R6 (mips_opts
.isa
))
10390 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10391 (int) imm_expr
.X_add_number
);
10400 if (imm_expr
.X_add_number
>= -0x8000
10401 && imm_expr
.X_add_number
< 0x8000)
10403 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10408 load_register (AT
, &imm_expr
, dbl
);
10409 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10428 if (imm_expr
.X_add_number
>= 0
10429 && imm_expr
.X_add_number
< 0x10000)
10431 if (mask
!= M_NOR_I
)
10432 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10435 macro_build (&imm_expr
, "ori", "t,r,i",
10436 op
[0], op
[1], BFD_RELOC_LO16
);
10437 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10443 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10444 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10448 switch (imm_expr
.X_add_number
)
10451 macro_build (NULL
, "nop", "");
10454 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10458 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10459 (int) imm_expr
.X_add_number
);
10462 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10463 (unsigned long) imm_expr
.X_add_number
);
10472 gas_assert (mips_opts
.micromips
);
10473 macro_build_branch_ccl (mask
, &offset_expr
,
10474 EXTRACT_OPERAND (1, BCC
, *ip
));
10481 if (imm_expr
.X_add_number
== 0)
10487 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10489 /* Fall through. */
10492 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10497 /* Fall through. */
10500 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10501 else if (op
[0] == 0)
10502 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10506 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10507 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10508 &offset_expr
, AT
, ZERO
);
10518 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10523 /* Fall through. */
10525 /* Check for > max integer. */
10526 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10529 /* Result is always false. */
10531 macro_build (NULL
, "nop", "");
10533 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10536 ++imm_expr
.X_add_number
;
10537 /* Fall through. */
10540 if (mask
== M_BGEL_I
)
10542 if (imm_expr
.X_add_number
== 0)
10544 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10545 &offset_expr
, op
[0]);
10548 if (imm_expr
.X_add_number
== 1)
10550 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10551 &offset_expr
, op
[0]);
10554 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10557 /* Result is always true. */
10558 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10559 macro_build (&offset_expr
, "b", "p");
10564 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10565 &offset_expr
, AT
, ZERO
);
10570 /* Fall through. */
10574 else if (op
[0] == 0)
10575 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10576 &offset_expr
, ZERO
, op
[1]);
10580 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10581 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10582 &offset_expr
, AT
, ZERO
);
10588 /* Fall through. */
10592 && imm_expr
.X_add_number
== -1))
10594 ++imm_expr
.X_add_number
;
10595 /* Fall through. */
10598 if (mask
== M_BGEUL_I
)
10600 if (imm_expr
.X_add_number
== 0)
10602 else if (imm_expr
.X_add_number
== 1)
10603 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10604 &offset_expr
, op
[0], ZERO
);
10609 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10610 &offset_expr
, AT
, ZERO
);
10616 /* Fall through. */
10619 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10620 else if (op
[0] == 0)
10621 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10625 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10626 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10627 &offset_expr
, AT
, ZERO
);
10633 /* Fall through. */
10636 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10637 &offset_expr
, op
[0], ZERO
);
10638 else if (op
[0] == 0)
10643 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10644 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10645 &offset_expr
, AT
, ZERO
);
10651 /* Fall through. */
10654 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10655 else if (op
[0] == 0)
10656 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10660 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10661 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10662 &offset_expr
, AT
, ZERO
);
10668 /* Fall through. */
10670 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10672 ++imm_expr
.X_add_number
;
10673 /* Fall through. */
10676 if (mask
== M_BLTL_I
)
10678 if (imm_expr
.X_add_number
== 0)
10679 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10680 else if (imm_expr
.X_add_number
== 1)
10681 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10686 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10687 &offset_expr
, AT
, ZERO
);
10693 /* Fall through. */
10696 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10697 &offset_expr
, op
[0], ZERO
);
10698 else if (op
[0] == 0)
10703 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10704 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10705 &offset_expr
, AT
, ZERO
);
10711 /* Fall through. */
10715 && imm_expr
.X_add_number
== -1))
10717 ++imm_expr
.X_add_number
;
10718 /* Fall through. */
10721 if (mask
== M_BLTUL_I
)
10723 if (imm_expr
.X_add_number
== 0)
10725 else if (imm_expr
.X_add_number
== 1)
10726 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10727 &offset_expr
, op
[0], ZERO
);
10732 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10733 &offset_expr
, AT
, ZERO
);
10739 /* Fall through. */
10742 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10743 else if (op
[0] == 0)
10744 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10748 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10749 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10750 &offset_expr
, AT
, ZERO
);
10756 /* Fall through. */
10760 else if (op
[0] == 0)
10761 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10762 &offset_expr
, ZERO
, op
[1]);
10766 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10767 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10768 &offset_expr
, AT
, ZERO
);
10774 /* Fall through. */
10780 /* Fall through. */
10786 as_warn (_("divide by zero"));
10788 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10790 macro_build (NULL
, "break", BRK_FMT
, 7);
10794 start_noreorder ();
10797 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10798 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10802 if (mips_opts
.micromips
)
10803 micromips_label_expr (&label_expr
);
10805 label_expr
.X_add_number
= 8;
10806 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10807 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10808 macro_build (NULL
, "break", BRK_FMT
, 7);
10809 if (mips_opts
.micromips
)
10810 micromips_add_label ();
10812 expr1
.X_add_number
= -1;
10814 load_register (AT
, &expr1
, dbl
);
10815 if (mips_opts
.micromips
)
10816 micromips_label_expr (&label_expr
);
10818 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10819 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10822 expr1
.X_add_number
= 1;
10823 load_register (AT
, &expr1
, dbl
);
10824 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10828 expr1
.X_add_number
= 0x80000000;
10829 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10833 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10834 /* We want to close the noreorder block as soon as possible, so
10835 that later insns are available for delay slot filling. */
10840 if (mips_opts
.micromips
)
10841 micromips_label_expr (&label_expr
);
10843 label_expr
.X_add_number
= 8;
10844 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10845 macro_build (NULL
, "nop", "");
10847 /* We want to close the noreorder block as soon as possible, so
10848 that later insns are available for delay slot filling. */
10851 macro_build (NULL
, "break", BRK_FMT
, 6);
10853 if (mips_opts
.micromips
)
10854 micromips_add_label ();
10855 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10894 if (imm_expr
.X_add_number
== 0)
10896 as_warn (_("divide by zero"));
10898 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10900 macro_build (NULL
, "break", BRK_FMT
, 7);
10903 if (imm_expr
.X_add_number
== 1)
10905 if (strcmp (s2
, "mflo") == 0)
10906 move_register (op
[0], op
[1]);
10908 move_register (op
[0], ZERO
);
10911 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10913 if (strcmp (s2
, "mflo") == 0)
10914 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10916 move_register (op
[0], ZERO
);
10921 load_register (AT
, &imm_expr
, dbl
);
10922 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10923 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10942 start_noreorder ();
10945 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10946 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10947 /* We want to close the noreorder block as soon as possible, so
10948 that later insns are available for delay slot filling. */
10953 if (mips_opts
.micromips
)
10954 micromips_label_expr (&label_expr
);
10956 label_expr
.X_add_number
= 8;
10957 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10958 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10960 /* We want to close the noreorder block as soon as possible, so
10961 that later insns are available for delay slot filling. */
10963 macro_build (NULL
, "break", BRK_FMT
, 7);
10964 if (mips_opts
.micromips
)
10965 micromips_add_label ();
10967 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10972 /* Fall through. */
10978 /* Fall through. */
10981 /* Load the address of a symbol into a register. If breg is not
10982 zero, we then add a base register to it. */
10985 if (dbl
&& GPR_SIZE
== 32)
10986 as_warn (_("dla used to load 32-bit register; recommend using la "
10989 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10990 as_warn (_("la used to load 64-bit address; recommend using dla "
10993 if (small_offset_p (0, align
, 16))
10995 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10996 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11000 if (mips_opts
.at
&& (op
[0] == breg
))
11008 if (offset_expr
.X_op
!= O_symbol
11009 && offset_expr
.X_op
!= O_constant
)
11011 as_bad (_("expression too complex"));
11012 offset_expr
.X_op
= O_constant
;
11015 if (offset_expr
.X_op
== O_constant
)
11016 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
11017 else if (mips_pic
== NO_PIC
)
11019 /* If this is a reference to a GP relative symbol, we want
11020 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11022 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11023 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11024 If we have a constant, we need two instructions anyhow,
11025 so we may as well always use the latter form.
11027 With 64bit address space and a usable $at we want
11028 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11029 lui $at,<sym> (BFD_RELOC_HI16_S)
11030 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11031 daddiu $at,<sym> (BFD_RELOC_LO16)
11033 daddu $tempreg,$tempreg,$at
11035 If $at is already in use, we use a path which is suboptimal
11036 on superscalar processors.
11037 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11038 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11040 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11042 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11044 For GP relative symbols in 64bit address space we can use
11045 the same sequence as in 32bit address space. */
11046 if (HAVE_64BIT_SYMBOLS
)
11048 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11049 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11051 relax_start (offset_expr
.X_add_symbol
);
11052 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11053 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11057 if (used_at
== 0 && mips_opts
.at
)
11059 macro_build (&offset_expr
, "lui", LUI_FMT
,
11060 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11061 macro_build (&offset_expr
, "lui", LUI_FMT
,
11062 AT
, BFD_RELOC_HI16_S
);
11063 macro_build (&offset_expr
, "daddiu", "t,r,j",
11064 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11065 macro_build (&offset_expr
, "daddiu", "t,r,j",
11066 AT
, AT
, BFD_RELOC_LO16
);
11067 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11068 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11073 macro_build (&offset_expr
, "lui", LUI_FMT
,
11074 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11075 macro_build (&offset_expr
, "daddiu", "t,r,j",
11076 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11077 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11078 macro_build (&offset_expr
, "daddiu", "t,r,j",
11079 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11080 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11081 macro_build (&offset_expr
, "daddiu", "t,r,j",
11082 tempreg
, tempreg
, BFD_RELOC_LO16
);
11085 if (mips_relax
.sequence
)
11090 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11091 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11093 relax_start (offset_expr
.X_add_symbol
);
11094 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11095 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11098 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11099 as_bad (_("offset too large"));
11100 macro_build_lui (&offset_expr
, tempreg
);
11101 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11102 tempreg
, tempreg
, BFD_RELOC_LO16
);
11103 if (mips_relax
.sequence
)
11107 else if (!mips_big_got
&& !HAVE_NEWABI
)
11109 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11111 /* If this is a reference to an external symbol, and there
11112 is no constant, we want
11113 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11114 or for lca or if tempreg is PIC_CALL_REG
11115 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11116 For a local symbol, we want
11117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11119 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11121 If we have a small constant, and this is a reference to
11122 an external symbol, we want
11123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11125 addiu $tempreg,$tempreg,<constant>
11126 For a local symbol, we want the same instruction
11127 sequence, but we output a BFD_RELOC_LO16 reloc on the
11130 If we have a large constant, and this is a reference to
11131 an external symbol, we want
11132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11133 lui $at,<hiconstant>
11134 addiu $at,$at,<loconstant>
11135 addu $tempreg,$tempreg,$at
11136 For a local symbol, we want the same instruction
11137 sequence, but we output a BFD_RELOC_LO16 reloc on the
11141 if (offset_expr
.X_add_number
== 0)
11143 if (mips_pic
== SVR4_PIC
11145 && (call
|| tempreg
== PIC_CALL_REG
))
11146 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11148 relax_start (offset_expr
.X_add_symbol
);
11149 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11150 lw_reloc_type
, mips_gp_register
);
11153 /* We're going to put in an addu instruction using
11154 tempreg, so we may as well insert the nop right
11159 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11160 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11162 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11163 tempreg
, tempreg
, BFD_RELOC_LO16
);
11165 /* FIXME: If breg == 0, and the next instruction uses
11166 $tempreg, then if this variant case is used an extra
11167 nop will be generated. */
11169 else if (offset_expr
.X_add_number
>= -0x8000
11170 && offset_expr
.X_add_number
< 0x8000)
11172 load_got_offset (tempreg
, &offset_expr
);
11174 add_got_offset (tempreg
, &offset_expr
);
11178 expr1
.X_add_number
= offset_expr
.X_add_number
;
11179 offset_expr
.X_add_number
=
11180 SEXT_16BIT (offset_expr
.X_add_number
);
11181 load_got_offset (tempreg
, &offset_expr
);
11182 offset_expr
.X_add_number
= expr1
.X_add_number
;
11183 /* If we are going to add in a base register, and the
11184 target register and the base register are the same,
11185 then we are using AT as a temporary register. Since
11186 we want to load the constant into AT, we add our
11187 current AT (from the global offset table) and the
11188 register into the register now, and pretend we were
11189 not using a base register. */
11193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11198 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11202 else if (!mips_big_got
&& HAVE_NEWABI
)
11204 int add_breg_early
= 0;
11206 /* If this is a reference to an external, and there is no
11207 constant, or local symbol (*), with or without a
11209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11210 or for lca or if tempreg is PIC_CALL_REG
11211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11213 If we have a small constant, and this is a reference to
11214 an external symbol, we want
11215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11216 addiu $tempreg,$tempreg,<constant>
11218 If we have a large constant, and this is a reference to
11219 an external symbol, we want
11220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11221 lui $at,<hiconstant>
11222 addiu $at,$at,<loconstant>
11223 addu $tempreg,$tempreg,$at
11225 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11226 local symbols, even though it introduces an additional
11229 if (offset_expr
.X_add_number
)
11231 expr1
.X_add_number
= offset_expr
.X_add_number
;
11232 offset_expr
.X_add_number
= 0;
11234 relax_start (offset_expr
.X_add_symbol
);
11235 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11236 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11238 if (expr1
.X_add_number
>= -0x8000
11239 && expr1
.X_add_number
< 0x8000)
11241 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11242 tempreg
, tempreg
, BFD_RELOC_LO16
);
11244 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11248 /* If we are going to add in a base register, and the
11249 target register and the base register are the same,
11250 then we are using AT as a temporary register. Since
11251 we want to load the constant into AT, we add our
11252 current AT (from the global offset table) and the
11253 register into the register now, and pretend we were
11254 not using a base register. */
11259 gas_assert (tempreg
== AT
);
11260 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11263 add_breg_early
= 1;
11266 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11273 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11276 offset_expr
.X_add_number
= expr1
.X_add_number
;
11278 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11279 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11280 if (add_breg_early
)
11282 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11283 op
[0], tempreg
, breg
);
11289 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11291 relax_start (offset_expr
.X_add_symbol
);
11292 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11293 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11295 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11296 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11301 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11302 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11305 else if (mips_big_got
&& !HAVE_NEWABI
)
11308 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11309 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11310 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11312 /* This is the large GOT case. If this is a reference to an
11313 external symbol, and there is no constant, we want
11314 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11315 addu $tempreg,$tempreg,$gp
11316 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11317 or for lca or if tempreg is PIC_CALL_REG
11318 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11319 addu $tempreg,$tempreg,$gp
11320 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11321 For a local symbol, we want
11322 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11324 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11326 If we have a small constant, and this is a reference to
11327 an external symbol, we want
11328 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11329 addu $tempreg,$tempreg,$gp
11330 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11332 addiu $tempreg,$tempreg,<constant>
11333 For a local symbol, we want
11334 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11336 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11338 If we have a large constant, and this is a reference to
11339 an external symbol, we want
11340 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11341 addu $tempreg,$tempreg,$gp
11342 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11343 lui $at,<hiconstant>
11344 addiu $at,$at,<loconstant>
11345 addu $tempreg,$tempreg,$at
11346 For a local symbol, we want
11347 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11348 lui $at,<hiconstant>
11349 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11350 addu $tempreg,$tempreg,$at
11353 expr1
.X_add_number
= offset_expr
.X_add_number
;
11354 offset_expr
.X_add_number
= 0;
11355 relax_start (offset_expr
.X_add_symbol
);
11356 gpdelay
= reg_needs_delay (mips_gp_register
);
11357 if (expr1
.X_add_number
== 0 && breg
== 0
11358 && (call
|| tempreg
== PIC_CALL_REG
))
11360 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11361 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11363 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11364 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11365 tempreg
, tempreg
, mips_gp_register
);
11366 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11367 tempreg
, lw_reloc_type
, tempreg
);
11368 if (expr1
.X_add_number
== 0)
11372 /* We're going to put in an addu instruction using
11373 tempreg, so we may as well insert the nop right
11378 else if (expr1
.X_add_number
>= -0x8000
11379 && expr1
.X_add_number
< 0x8000)
11382 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11383 tempreg
, tempreg
, BFD_RELOC_LO16
);
11389 /* If we are going to add in a base register, and the
11390 target register and the base register are the same,
11391 then we are using AT as a temporary register. Since
11392 we want to load the constant into AT, we add our
11393 current AT (from the global offset table) and the
11394 register into the register now, and pretend we were
11395 not using a base register. */
11400 gas_assert (tempreg
== AT
);
11402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11407 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11412 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11417 /* This is needed because this instruction uses $gp, but
11418 the first instruction on the main stream does not. */
11419 macro_build (NULL
, "nop", "");
11422 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11423 local_reloc_type
, mips_gp_register
);
11424 if (expr1
.X_add_number
>= -0x8000
11425 && expr1
.X_add_number
< 0x8000)
11428 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11429 tempreg
, tempreg
, BFD_RELOC_LO16
);
11430 /* FIXME: If add_number is 0, and there was no base
11431 register, the external symbol case ended with a load,
11432 so if the symbol turns out to not be external, and
11433 the next instruction uses tempreg, an unnecessary nop
11434 will be inserted. */
11440 /* We must add in the base register now, as in the
11441 external symbol case. */
11442 gas_assert (tempreg
== AT
);
11444 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11447 /* We set breg to 0 because we have arranged to add
11448 it in in both cases. */
11452 macro_build_lui (&expr1
, AT
);
11453 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11454 AT
, AT
, BFD_RELOC_LO16
);
11455 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11456 tempreg
, tempreg
, AT
);
11461 else if (mips_big_got
&& HAVE_NEWABI
)
11463 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11464 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11465 int add_breg_early
= 0;
11467 /* This is the large GOT case. If this is a reference to an
11468 external symbol, and there is no constant, we want
11469 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11470 add $tempreg,$tempreg,$gp
11471 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11472 or for lca or if tempreg is PIC_CALL_REG
11473 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11474 add $tempreg,$tempreg,$gp
11475 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11477 If we have a small constant, and this is a reference to
11478 an external symbol, we want
11479 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11480 add $tempreg,$tempreg,$gp
11481 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11482 addi $tempreg,$tempreg,<constant>
11484 If we have a large constant, and this is a reference to
11485 an external symbol, we want
11486 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11487 addu $tempreg,$tempreg,$gp
11488 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11489 lui $at,<hiconstant>
11490 addi $at,$at,<loconstant>
11491 add $tempreg,$tempreg,$at
11493 If we have NewABI, and we know it's a local symbol, we want
11494 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11495 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11496 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11498 relax_start (offset_expr
.X_add_symbol
);
11500 expr1
.X_add_number
= offset_expr
.X_add_number
;
11501 offset_expr
.X_add_number
= 0;
11503 if (expr1
.X_add_number
== 0 && breg
== 0
11504 && (call
|| tempreg
== PIC_CALL_REG
))
11506 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11507 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11509 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11511 tempreg
, tempreg
, mips_gp_register
);
11512 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11513 tempreg
, lw_reloc_type
, tempreg
);
11515 if (expr1
.X_add_number
== 0)
11517 else if (expr1
.X_add_number
>= -0x8000
11518 && expr1
.X_add_number
< 0x8000)
11520 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11521 tempreg
, tempreg
, BFD_RELOC_LO16
);
11523 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11527 /* If we are going to add in a base register, and the
11528 target register and the base register are the same,
11529 then we are using AT as a temporary register. Since
11530 we want to load the constant into AT, we add our
11531 current AT (from the global offset table) and the
11532 register into the register now, and pretend we were
11533 not using a base register. */
11538 gas_assert (tempreg
== AT
);
11539 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11542 add_breg_early
= 1;
11545 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11546 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11551 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11554 offset_expr
.X_add_number
= expr1
.X_add_number
;
11555 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11556 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11557 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11558 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11559 if (add_breg_early
)
11561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11562 op
[0], tempreg
, breg
);
11572 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11576 gas_assert (!mips_opts
.micromips
);
11577 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11581 gas_assert (!mips_opts
.micromips
);
11582 macro_build (NULL
, "c2", "C", 0x02);
11586 gas_assert (!mips_opts
.micromips
);
11587 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11591 gas_assert (!mips_opts
.micromips
);
11592 macro_build (NULL
, "c2", "C", 3);
11596 gas_assert (!mips_opts
.micromips
);
11597 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11601 /* The j instruction may not be used in PIC code, since it
11602 requires an absolute address. We convert it to a b
11604 if (mips_pic
== NO_PIC
)
11605 macro_build (&offset_expr
, "j", "a");
11607 macro_build (&offset_expr
, "b", "p");
11610 /* The jal instructions must be handled as macros because when
11611 generating PIC code they expand to multi-instruction
11612 sequences. Normally they are simple instructions. */
11616 /* Fall through. */
11618 gas_assert (mips_opts
.micromips
);
11619 if (mips_opts
.insn32
)
11621 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11629 /* Fall through. */
11632 if (mips_pic
== NO_PIC
)
11634 s
= jals
? "jalrs" : "jalr";
11635 if (mips_opts
.micromips
11636 && !mips_opts
.insn32
11638 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11639 macro_build (NULL
, s
, "mj", op
[1]);
11641 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11645 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11646 && mips_cprestore_offset
>= 0);
11648 if (op
[1] != PIC_CALL_REG
)
11649 as_warn (_("MIPS PIC call to register other than $25"));
11651 s
= ((mips_opts
.micromips
11652 && !mips_opts
.insn32
11653 && (!mips_opts
.noreorder
|| cprestore
))
11654 ? "jalrs" : "jalr");
11655 if (mips_opts
.micromips
11656 && !mips_opts
.insn32
11658 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11659 macro_build (NULL
, s
, "mj", op
[1]);
11661 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11662 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11664 if (mips_cprestore_offset
< 0)
11665 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11668 if (!mips_frame_reg_valid
)
11670 as_warn (_("no .frame pseudo-op used in PIC code"));
11671 /* Quiet this warning. */
11672 mips_frame_reg_valid
= 1;
11674 if (!mips_cprestore_valid
)
11676 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11677 /* Quiet this warning. */
11678 mips_cprestore_valid
= 1;
11680 if (mips_opts
.noreorder
)
11681 macro_build (NULL
, "nop", "");
11682 expr1
.X_add_number
= mips_cprestore_offset
;
11683 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11686 HAVE_64BIT_ADDRESSES
);
11694 gas_assert (mips_opts
.micromips
);
11695 if (mips_opts
.insn32
)
11697 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11701 /* Fall through. */
11703 if (mips_pic
== NO_PIC
)
11704 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11705 else if (mips_pic
== SVR4_PIC
)
11707 /* If this is a reference to an external symbol, and we are
11708 using a small GOT, we want
11709 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11713 lw $gp,cprestore($sp)
11714 The cprestore value is set using the .cprestore
11715 pseudo-op. If we are using a big GOT, we want
11716 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11718 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11722 lw $gp,cprestore($sp)
11723 If the symbol is not external, we want
11724 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11726 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11729 lw $gp,cprestore($sp)
11731 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11732 sequences above, minus nops, unless the symbol is local,
11733 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11739 relax_start (offset_expr
.X_add_symbol
);
11740 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11741 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11744 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11745 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11751 relax_start (offset_expr
.X_add_symbol
);
11752 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11753 BFD_RELOC_MIPS_CALL_HI16
);
11754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11755 PIC_CALL_REG
, mips_gp_register
);
11756 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11757 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11760 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11761 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11763 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11764 PIC_CALL_REG
, PIC_CALL_REG
,
11765 BFD_RELOC_MIPS_GOT_OFST
);
11769 macro_build_jalr (&offset_expr
, 0);
11773 relax_start (offset_expr
.X_add_symbol
);
11776 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11777 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11786 gpdelay
= reg_needs_delay (mips_gp_register
);
11787 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11788 BFD_RELOC_MIPS_CALL_HI16
);
11789 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11790 PIC_CALL_REG
, mips_gp_register
);
11791 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11792 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11797 macro_build (NULL
, "nop", "");
11799 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11800 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11803 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11804 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11806 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11808 if (mips_cprestore_offset
< 0)
11809 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11812 if (!mips_frame_reg_valid
)
11814 as_warn (_("no .frame pseudo-op used in PIC code"));
11815 /* Quiet this warning. */
11816 mips_frame_reg_valid
= 1;
11818 if (!mips_cprestore_valid
)
11820 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11821 /* Quiet this warning. */
11822 mips_cprestore_valid
= 1;
11824 if (mips_opts
.noreorder
)
11825 macro_build (NULL
, "nop", "");
11826 expr1
.X_add_number
= mips_cprestore_offset
;
11827 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11830 HAVE_64BIT_ADDRESSES
);
11834 else if (mips_pic
== VXWORKS_PIC
)
11835 as_bad (_("non-PIC jump used in PIC library"));
11942 gas_assert (!mips_opts
.micromips
);
11945 /* Itbl support may require additional care here. */
11951 /* Itbl support may require additional care here. */
11957 offbits
= (mips_opts
.micromips
? 12
11958 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11960 /* Itbl support may require additional care here. */
11964 gas_assert (!mips_opts
.micromips
);
11967 /* Itbl support may require additional care here. */
11973 offbits
= (mips_opts
.micromips
? 12 : 16);
11978 offbits
= (mips_opts
.micromips
? 12 : 16);
11983 /* Itbl support may require additional care here. */
11989 offbits
= (mips_opts
.micromips
? 12
11990 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11992 /* Itbl support may require additional care here. */
11998 /* Itbl support may require additional care here. */
12004 /* Itbl support may require additional care here. */
12010 offbits
= (mips_opts
.micromips
? 12 : 16);
12015 offbits
= (mips_opts
.micromips
? 12 : 16);
12020 offbits
= (mips_opts
.micromips
? 12
12021 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12027 offbits
= (mips_opts
.micromips
? 12
12028 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12034 offbits
= (mips_opts
.micromips
? 12 : 16);
12037 gas_assert (mips_opts
.micromips
);
12044 gas_assert (mips_opts
.micromips
);
12053 s
= ip
->insn_mo
->name
;
12059 gas_assert (mips_opts
.micromips
);
12065 gas_assert (mips_opts
.micromips
);
12072 /* Try to use one the the load registers to compute the base address.
12073 We don't want to use $0 as tempreg. */
12076 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12077 || (op
[1] == ZERO
&& op
[3] == op
[0])
12078 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12080 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12087 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12090 tempreg
= op
[0] + lp
;
12107 gas_assert (!mips_opts
.micromips
);
12110 /* Itbl support may require additional care here. */
12116 /* Itbl support may require additional care here. */
12122 offbits
= (mips_opts
.micromips
? 12
12123 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12125 /* Itbl support may require additional care here. */
12129 gas_assert (!mips_opts
.micromips
);
12132 /* Itbl support may require additional care here. */
12138 offbits
= (mips_opts
.micromips
? 12 : 16);
12143 offbits
= (mips_opts
.micromips
? 12 : 16);
12148 offbits
= (mips_opts
.micromips
? 12
12149 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12155 offbits
= (mips_opts
.micromips
? 12
12156 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12162 s
= ip
->insn_mo
->name
;
12169 fmt
= (mips_opts
.micromips
? "k,~(b)"
12170 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12172 offbits
= (mips_opts
.micromips
? 12
12173 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12183 fmt
= (mips_opts
.micromips
? "k,~(b)"
12184 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12186 offbits
= (mips_opts
.micromips
? 12
12187 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12199 /* Itbl support may require additional care here. */
12204 offbits
= (mips_opts
.micromips
? 12
12205 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12207 /* Itbl support may require additional care here. */
12213 /* Itbl support may require additional care here. */
12217 gas_assert (!mips_opts
.micromips
);
12220 /* Itbl support may require additional care here. */
12226 offbits
= (mips_opts
.micromips
? 12 : 16);
12231 offbits
= (mips_opts
.micromips
? 12 : 16);
12234 gas_assert (mips_opts
.micromips
);
12240 gas_assert (mips_opts
.micromips
);
12246 gas_assert (mips_opts
.micromips
);
12252 gas_assert (mips_opts
.micromips
);
12260 breg
= ll_sc_paired
? op
[3] : op
[2];
12261 if (small_offset_p (0, align
, 16))
12263 /* The first case exists for M_LD_AB and M_SD_AB, which are
12264 macros for o32 but which should act like normal instructions
12267 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12268 offset_reloc
[1], offset_reloc
[2], breg
);
12269 else if (small_offset_p (0, align
, offbits
))
12274 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12276 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12279 macro_build (NULL
, s
, fmt
, op
[0],
12280 (int) offset_expr
.X_add_number
, breg
);
12286 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12287 tempreg
, breg
, -1, offset_reloc
[0],
12288 offset_reloc
[1], offset_reloc
[2]);
12292 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12294 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12297 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12305 if (offset_expr
.X_op
!= O_constant
12306 && offset_expr
.X_op
!= O_symbol
)
12308 as_bad (_("expression too complex"));
12309 offset_expr
.X_op
= O_constant
;
12312 if (HAVE_32BIT_ADDRESSES
12313 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12317 sprintf_vma (value
, offset_expr
.X_add_number
);
12318 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12321 /* A constant expression in PIC code can be handled just as it
12322 is in non PIC code. */
12323 if (offset_expr
.X_op
== O_constant
)
12325 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12326 offbits
== 0 ? 16 : offbits
);
12327 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12329 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12331 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12332 tempreg
, tempreg
, breg
);
12335 if (offset_expr
.X_add_number
!= 0)
12336 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12337 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12339 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12341 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12343 else if (offbits
== 16)
12344 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12346 macro_build (NULL
, s
, fmt
, op
[0],
12347 (int) offset_expr
.X_add_number
, tempreg
);
12349 else if (offbits
!= 16)
12351 /* The offset field is too narrow to be used for a low-part
12352 relocation, so load the whole address into the auxiliary
12354 load_address (tempreg
, &offset_expr
, &used_at
);
12356 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12357 tempreg
, tempreg
, breg
);
12361 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12363 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12366 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12368 else if (mips_pic
== NO_PIC
)
12370 /* If this is a reference to a GP relative symbol, and there
12371 is no base register, we want
12372 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12373 Otherwise, if there is no base register, we want
12374 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12375 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12376 If we have a constant, we need two instructions anyhow,
12377 so we always use the latter form.
12379 If we have a base register, and this is a reference to a
12380 GP relative symbol, we want
12381 addu $tempreg,$breg,$gp
12382 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12384 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12385 addu $tempreg,$tempreg,$breg
12386 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12387 With a constant we always use the latter case.
12389 With 64bit address space and no base register and $at usable,
12391 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12392 lui $at,<sym> (BFD_RELOC_HI16_S)
12393 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12396 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12397 If we have a base register, we want
12398 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12399 lui $at,<sym> (BFD_RELOC_HI16_S)
12400 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12404 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12406 Without $at we can't generate the optimal path for superscalar
12407 processors here since this would require two temporary registers.
12408 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12409 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12411 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12413 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12414 If we have a base register, we want
12415 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12416 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12418 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12420 daddu $tempreg,$tempreg,$breg
12421 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12423 For GP relative symbols in 64bit address space we can use
12424 the same sequence as in 32bit address space. */
12425 if (HAVE_64BIT_SYMBOLS
)
12427 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12428 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12430 relax_start (offset_expr
.X_add_symbol
);
12433 macro_build (&offset_expr
, s
, fmt
, op
[0],
12434 BFD_RELOC_GPREL16
, mips_gp_register
);
12438 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12439 tempreg
, breg
, mips_gp_register
);
12440 macro_build (&offset_expr
, s
, fmt
, op
[0],
12441 BFD_RELOC_GPREL16
, tempreg
);
12446 if (used_at
== 0 && mips_opts
.at
)
12448 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12449 BFD_RELOC_MIPS_HIGHEST
);
12450 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12452 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12453 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12455 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12456 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12457 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12458 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12464 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12465 BFD_RELOC_MIPS_HIGHEST
);
12466 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12467 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12468 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12469 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12470 tempreg
, BFD_RELOC_HI16_S
);
12471 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12473 macro_build (NULL
, "daddu", "d,v,t",
12474 tempreg
, tempreg
, breg
);
12475 macro_build (&offset_expr
, s
, fmt
, op
[0],
12476 BFD_RELOC_LO16
, tempreg
);
12479 if (mips_relax
.sequence
)
12486 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12487 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12489 relax_start (offset_expr
.X_add_symbol
);
12490 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12494 macro_build_lui (&offset_expr
, tempreg
);
12495 macro_build (&offset_expr
, s
, fmt
, op
[0],
12496 BFD_RELOC_LO16
, tempreg
);
12497 if (mips_relax
.sequence
)
12502 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12503 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12505 relax_start (offset_expr
.X_add_symbol
);
12506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12507 tempreg
, breg
, mips_gp_register
);
12508 macro_build (&offset_expr
, s
, fmt
, op
[0],
12509 BFD_RELOC_GPREL16
, tempreg
);
12512 macro_build_lui (&offset_expr
, tempreg
);
12513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12514 tempreg
, tempreg
, breg
);
12515 macro_build (&offset_expr
, s
, fmt
, op
[0],
12516 BFD_RELOC_LO16
, tempreg
);
12517 if (mips_relax
.sequence
)
12521 else if (!mips_big_got
)
12523 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12525 /* If this is a reference to an external symbol, we want
12526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12528 <op> op[0],0($tempreg)
12530 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12532 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12533 <op> op[0],0($tempreg)
12535 For NewABI, we want
12536 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12537 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12539 If there is a base register, we add it to $tempreg before
12540 the <op>. If there is a constant, we stick it in the
12541 <op> instruction. We don't handle constants larger than
12542 16 bits, because we have no way to load the upper 16 bits
12543 (actually, we could handle them for the subset of cases
12544 in which we are not using $at). */
12545 gas_assert (offset_expr
.X_op
== O_symbol
);
12548 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12549 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12552 tempreg
, tempreg
, breg
);
12553 macro_build (&offset_expr
, s
, fmt
, op
[0],
12554 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12557 expr1
.X_add_number
= offset_expr
.X_add_number
;
12558 offset_expr
.X_add_number
= 0;
12559 if (expr1
.X_add_number
< -0x8000
12560 || expr1
.X_add_number
>= 0x8000)
12561 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12562 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12563 lw_reloc_type
, mips_gp_register
);
12565 relax_start (offset_expr
.X_add_symbol
);
12567 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12568 tempreg
, BFD_RELOC_LO16
);
12571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12572 tempreg
, tempreg
, breg
);
12573 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12575 else if (mips_big_got
&& !HAVE_NEWABI
)
12579 /* If this is a reference to an external symbol, we want
12580 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12581 addu $tempreg,$tempreg,$gp
12582 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12583 <op> op[0],0($tempreg)
12585 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12587 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12588 <op> op[0],0($tempreg)
12589 If there is a base register, we add it to $tempreg before
12590 the <op>. If there is a constant, we stick it in the
12591 <op> instruction. We don't handle constants larger than
12592 16 bits, because we have no way to load the upper 16 bits
12593 (actually, we could handle them for the subset of cases
12594 in which we are not using $at). */
12595 gas_assert (offset_expr
.X_op
== O_symbol
);
12596 expr1
.X_add_number
= offset_expr
.X_add_number
;
12597 offset_expr
.X_add_number
= 0;
12598 if (expr1
.X_add_number
< -0x8000
12599 || expr1
.X_add_number
>= 0x8000)
12600 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12601 gpdelay
= reg_needs_delay (mips_gp_register
);
12602 relax_start (offset_expr
.X_add_symbol
);
12603 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12604 BFD_RELOC_MIPS_GOT_HI16
);
12605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12608 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12611 macro_build (NULL
, "nop", "");
12612 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12613 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12615 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12616 tempreg
, BFD_RELOC_LO16
);
12620 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12621 tempreg
, tempreg
, breg
);
12622 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12624 else if (mips_big_got
&& HAVE_NEWABI
)
12626 /* If this is a reference to an external symbol, we want
12627 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12628 add $tempreg,$tempreg,$gp
12629 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12630 <op> op[0],<ofst>($tempreg)
12631 Otherwise, for local symbols, we want:
12632 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12633 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12634 gas_assert (offset_expr
.X_op
== O_symbol
);
12635 expr1
.X_add_number
= offset_expr
.X_add_number
;
12636 offset_expr
.X_add_number
= 0;
12637 if (expr1
.X_add_number
< -0x8000
12638 || expr1
.X_add_number
>= 0x8000)
12639 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12640 relax_start (offset_expr
.X_add_symbol
);
12641 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12642 BFD_RELOC_MIPS_GOT_HI16
);
12643 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12646 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12649 tempreg
, tempreg
, breg
);
12650 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12653 offset_expr
.X_add_number
= expr1
.X_add_number
;
12654 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12655 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12658 tempreg
, tempreg
, breg
);
12659 macro_build (&offset_expr
, s
, fmt
, op
[0],
12660 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12669 gas_assert (mips_opts
.micromips
);
12670 gas_assert (mips_opts
.insn32
);
12671 start_noreorder ();
12672 macro_build (NULL
, "jr", "s", RA
);
12673 expr1
.X_add_number
= op
[0] << 2;
12674 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12679 gas_assert (mips_opts
.micromips
);
12680 gas_assert (mips_opts
.insn32
);
12681 macro_build (NULL
, "jr", "s", op
[0]);
12682 if (mips_opts
.noreorder
)
12683 macro_build (NULL
, "nop", "");
12688 load_register (op
[0], &imm_expr
, 0);
12692 load_register (op
[0], &imm_expr
, 1);
12696 if (imm_expr
.X_op
== O_constant
)
12699 load_register (AT
, &imm_expr
, 0);
12700 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12705 gas_assert (imm_expr
.X_op
== O_absent
12706 && offset_expr
.X_op
== O_symbol
12707 && strcmp (segment_name (S_GET_SEGMENT
12708 (offset_expr
.X_add_symbol
)),
12710 && offset_expr
.X_add_number
== 0);
12711 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12712 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12717 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12718 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12719 order 32 bits of the value and the low order 32 bits are either
12720 zero or in OFFSET_EXPR. */
12721 if (imm_expr
.X_op
== O_constant
)
12723 if (GPR_SIZE
== 64)
12724 load_register (op
[0], &imm_expr
, 1);
12729 if (target_big_endian
)
12741 load_register (hreg
, &imm_expr
, 0);
12744 if (offset_expr
.X_op
== O_absent
)
12745 move_register (lreg
, 0);
12748 gas_assert (offset_expr
.X_op
== O_constant
);
12749 load_register (lreg
, &offset_expr
, 0);
12755 gas_assert (imm_expr
.X_op
== O_absent
);
12757 /* We know that sym is in the .rdata section. First we get the
12758 upper 16 bits of the address. */
12759 if (mips_pic
== NO_PIC
)
12761 macro_build_lui (&offset_expr
, AT
);
12766 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12767 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12771 /* Now we load the register(s). */
12772 if (GPR_SIZE
== 64)
12775 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12776 BFD_RELOC_LO16
, AT
);
12781 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12782 BFD_RELOC_LO16
, AT
);
12785 /* FIXME: How in the world do we deal with the possible
12787 offset_expr
.X_add_number
+= 4;
12788 macro_build (&offset_expr
, "lw", "t,o(b)",
12789 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12795 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12796 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12797 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12798 the value and the low order 32 bits are either zero or in
12800 if (imm_expr
.X_op
== O_constant
)
12803 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12804 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12805 && imm_expr
.X_add_number
!= 0)
12809 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12811 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12812 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12815 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12817 if (FPR_SIZE
!= 32)
12818 as_bad (_("Unable to generate `%s' compliant code "
12820 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12822 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12824 if (offset_expr
.X_op
== O_absent
)
12825 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12828 gas_assert (offset_expr
.X_op
== O_constant
);
12829 load_register (AT
, &offset_expr
, 0);
12830 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12832 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12834 if (imm_expr
.X_add_number
!= 0)
12838 load_register (AT
, &imm_expr
, 0);
12840 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12846 gas_assert (imm_expr
.X_op
== O_absent
12847 && offset_expr
.X_op
== O_symbol
12848 && offset_expr
.X_add_number
== 0);
12849 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12850 if (strcmp (s
, ".lit8") == 0)
12852 op
[2] = mips_gp_register
;
12853 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12854 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12855 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12859 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12861 if (mips_pic
!= NO_PIC
)
12862 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12863 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12866 /* FIXME: This won't work for a 64 bit address. */
12867 macro_build_lui (&offset_expr
, AT
);
12871 offset_reloc
[0] = BFD_RELOC_LO16
;
12872 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12873 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12876 /* Fall through. */
12879 /* The MIPS assembler seems to check for X_add_number not
12880 being double aligned and generating:
12883 addiu at,at,%lo(foo+1)
12886 But, the resulting address is the same after relocation so why
12887 generate the extra instruction? */
12888 /* Itbl support may require additional care here. */
12891 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12900 gas_assert (!mips_opts
.micromips
);
12901 /* Itbl support may require additional care here. */
12904 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12924 if (GPR_SIZE
== 64)
12934 if (GPR_SIZE
== 64)
12942 /* Even on a big endian machine $fn comes before $fn+1. We have
12943 to adjust when loading from memory. We set coproc if we must
12944 load $fn+1 first. */
12945 /* Itbl support may require additional care here. */
12946 if (!target_big_endian
)
12950 if (small_offset_p (0, align
, 16))
12953 if (!small_offset_p (4, align
, 16))
12955 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12956 -1, offset_reloc
[0], offset_reloc
[1],
12958 expr1
.X_add_number
= 0;
12962 offset_reloc
[0] = BFD_RELOC_LO16
;
12963 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12964 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12966 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12968 ep
->X_add_number
+= 4;
12969 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12970 offset_reloc
[1], offset_reloc
[2], breg
);
12971 ep
->X_add_number
-= 4;
12972 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12973 offset_reloc
[1], offset_reloc
[2], breg
);
12977 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12978 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12980 ep
->X_add_number
+= 4;
12981 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12982 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12988 if (offset_expr
.X_op
!= O_symbol
12989 && offset_expr
.X_op
!= O_constant
)
12991 as_bad (_("expression too complex"));
12992 offset_expr
.X_op
= O_constant
;
12995 if (HAVE_32BIT_ADDRESSES
12996 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
13000 sprintf_vma (value
, offset_expr
.X_add_number
);
13001 as_bad (_("number (0x%s) larger than 32 bits"), value
);
13004 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
13006 /* If this is a reference to a GP relative symbol, we want
13007 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13008 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13009 If we have a base register, we use this
13011 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13012 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13013 If this is not a GP relative symbol, we want
13014 lui $at,<sym> (BFD_RELOC_HI16_S)
13015 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13016 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13017 If there is a base register, we add it to $at after the
13018 lui instruction. If there is a constant, we always use
13020 if (offset_expr
.X_op
== O_symbol
13021 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13022 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13024 relax_start (offset_expr
.X_add_symbol
);
13027 tempreg
= mips_gp_register
;
13031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13032 AT
, breg
, mips_gp_register
);
13037 /* Itbl support may require additional care here. */
13038 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13039 BFD_RELOC_GPREL16
, tempreg
);
13040 offset_expr
.X_add_number
+= 4;
13042 /* Set mips_optimize to 2 to avoid inserting an
13044 hold_mips_optimize
= mips_optimize
;
13046 /* Itbl support may require additional care here. */
13047 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13048 BFD_RELOC_GPREL16
, tempreg
);
13049 mips_optimize
= hold_mips_optimize
;
13053 offset_expr
.X_add_number
-= 4;
13056 if (offset_high_part (offset_expr
.X_add_number
, 16)
13057 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13059 load_address (AT
, &offset_expr
, &used_at
);
13060 offset_expr
.X_op
= O_constant
;
13061 offset_expr
.X_add_number
= 0;
13064 macro_build_lui (&offset_expr
, AT
);
13066 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13067 /* Itbl support may require additional care here. */
13068 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13069 BFD_RELOC_LO16
, AT
);
13070 /* FIXME: How do we handle overflow here? */
13071 offset_expr
.X_add_number
+= 4;
13072 /* Itbl support may require additional care here. */
13073 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13074 BFD_RELOC_LO16
, AT
);
13075 if (mips_relax
.sequence
)
13078 else if (!mips_big_got
)
13080 /* If this is a reference to an external symbol, we want
13081 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13084 <op> op[0]+1,4($at)
13086 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13088 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13089 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13090 If there is a base register we add it to $at before the
13091 lwc1 instructions. If there is a constant we include it
13092 in the lwc1 instructions. */
13094 expr1
.X_add_number
= offset_expr
.X_add_number
;
13095 if (expr1
.X_add_number
< -0x8000
13096 || expr1
.X_add_number
>= 0x8000 - 4)
13097 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13098 load_got_offset (AT
, &offset_expr
);
13101 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13103 /* Set mips_optimize to 2 to avoid inserting an undesired
13105 hold_mips_optimize
= mips_optimize
;
13108 /* Itbl support may require additional care here. */
13109 relax_start (offset_expr
.X_add_symbol
);
13110 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13111 BFD_RELOC_LO16
, AT
);
13112 expr1
.X_add_number
+= 4;
13113 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13114 BFD_RELOC_LO16
, AT
);
13116 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13117 BFD_RELOC_LO16
, AT
);
13118 offset_expr
.X_add_number
+= 4;
13119 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13120 BFD_RELOC_LO16
, AT
);
13123 mips_optimize
= hold_mips_optimize
;
13125 else if (mips_big_got
)
13129 /* If this is a reference to an external symbol, we want
13130 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13132 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13135 <op> op[0]+1,4($at)
13137 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13139 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13140 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13141 If there is a base register we add it to $at before the
13142 lwc1 instructions. If there is a constant we include it
13143 in the lwc1 instructions. */
13145 expr1
.X_add_number
= offset_expr
.X_add_number
;
13146 offset_expr
.X_add_number
= 0;
13147 if (expr1
.X_add_number
< -0x8000
13148 || expr1
.X_add_number
>= 0x8000 - 4)
13149 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13150 gpdelay
= reg_needs_delay (mips_gp_register
);
13151 relax_start (offset_expr
.X_add_symbol
);
13152 macro_build (&offset_expr
, "lui", LUI_FMT
,
13153 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13155 AT
, AT
, mips_gp_register
);
13156 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13157 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13160 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13161 /* Itbl support may require additional care here. */
13162 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13163 BFD_RELOC_LO16
, AT
);
13164 expr1
.X_add_number
+= 4;
13166 /* Set mips_optimize to 2 to avoid inserting an undesired
13168 hold_mips_optimize
= mips_optimize
;
13170 /* Itbl support may require additional care here. */
13171 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13172 BFD_RELOC_LO16
, AT
);
13173 mips_optimize
= hold_mips_optimize
;
13174 expr1
.X_add_number
-= 4;
13177 offset_expr
.X_add_number
= expr1
.X_add_number
;
13179 macro_build (NULL
, "nop", "");
13180 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13181 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13185 /* Itbl support may require additional care here. */
13186 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13187 BFD_RELOC_LO16
, AT
);
13188 offset_expr
.X_add_number
+= 4;
13190 /* Set mips_optimize to 2 to avoid inserting an undesired
13192 hold_mips_optimize
= mips_optimize
;
13194 /* Itbl support may require additional care here. */
13195 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13196 BFD_RELOC_LO16
, AT
);
13197 mips_optimize
= hold_mips_optimize
;
13211 gas_assert (!mips_opts
.micromips
);
13216 /* New code added to support COPZ instructions.
13217 This code builds table entries out of the macros in mip_opcodes.
13218 R4000 uses interlocks to handle coproc delays.
13219 Other chips (like the R3000) require nops to be inserted for delays.
13221 FIXME: Currently, we require that the user handle delays.
13222 In order to fill delay slots for non-interlocked chips,
13223 we must have a way to specify delays based on the coprocessor.
13224 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13225 What are the side-effects of the cop instruction?
13226 What cache support might we have and what are its effects?
13227 Both coprocessor & memory require delays. how long???
13228 What registers are read/set/modified?
13230 If an itbl is provided to interpret cop instructions,
13231 this knowledge can be encoded in the itbl spec. */
13245 gas_assert (!mips_opts
.micromips
);
13246 /* For now we just do C (same as Cz). The parameter will be
13247 stored in insn_opcode by mips_ip. */
13248 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13252 move_register (op
[0], op
[1]);
13256 gas_assert (mips_opts
.micromips
);
13257 gas_assert (mips_opts
.insn32
);
13258 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13259 micromips_to_32_reg_m_map
[op
[1]]);
13260 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13261 micromips_to_32_reg_n_map
[op
[2]]);
13266 /* Fall through. */
13268 if (mips_opts
.arch
== CPU_R5900
)
13269 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13273 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13274 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13280 /* Fall through. */
13282 /* The MIPS assembler some times generates shifts and adds. I'm
13283 not trying to be that fancy. GCC should do this for us
13286 load_register (AT
, &imm_expr
, dbl
);
13287 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13288 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13293 /* Fall through. */
13300 /* Fall through. */
13303 start_noreorder ();
13306 load_register (AT
, &imm_expr
, dbl
);
13307 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13308 op
[1], imm
? AT
: op
[2]);
13309 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13310 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13311 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13313 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13316 if (mips_opts
.micromips
)
13317 micromips_label_expr (&label_expr
);
13319 label_expr
.X_add_number
= 8;
13320 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13321 macro_build (NULL
, "nop", "");
13322 macro_build (NULL
, "break", BRK_FMT
, 6);
13323 if (mips_opts
.micromips
)
13324 micromips_add_label ();
13327 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13332 /* Fall through. */
13339 /* Fall through. */
13342 start_noreorder ();
13345 load_register (AT
, &imm_expr
, dbl
);
13346 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13347 op
[1], imm
? AT
: op
[2]);
13348 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13349 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13351 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13354 if (mips_opts
.micromips
)
13355 micromips_label_expr (&label_expr
);
13357 label_expr
.X_add_number
= 8;
13358 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13359 macro_build (NULL
, "nop", "");
13360 macro_build (NULL
, "break", BRK_FMT
, 6);
13361 if (mips_opts
.micromips
)
13362 micromips_add_label ();
13368 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13370 if (op
[0] == op
[1])
13377 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13378 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13382 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13383 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13384 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13385 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13389 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13391 if (op
[0] == op
[1])
13398 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13399 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13403 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13404 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13405 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13406 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13415 rot
= imm_expr
.X_add_number
& 0x3f;
13416 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13418 rot
= (64 - rot
) & 0x3f;
13420 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13422 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13427 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13430 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13431 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13434 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13435 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13436 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13444 rot
= imm_expr
.X_add_number
& 0x1f;
13445 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13447 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13448 (32 - rot
) & 0x1f);
13453 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13457 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13458 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13459 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13464 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13466 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13470 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13471 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13472 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13473 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13477 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13479 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13483 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13484 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13485 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13486 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13495 rot
= imm_expr
.X_add_number
& 0x3f;
13496 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13499 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13501 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13506 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13509 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13510 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13513 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13514 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13515 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13523 rot
= imm_expr
.X_add_number
& 0x1f;
13524 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13526 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13531 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13535 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13536 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13537 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13543 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13544 else if (op
[2] == 0)
13545 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13548 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13549 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13554 if (imm_expr
.X_add_number
== 0)
13556 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13561 as_warn (_("instruction %s: result is always false"),
13562 ip
->insn_mo
->name
);
13563 move_register (op
[0], 0);
13566 if (CPU_HAS_SEQ (mips_opts
.arch
)
13567 && -512 <= imm_expr
.X_add_number
13568 && imm_expr
.X_add_number
< 512)
13570 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13571 (int) imm_expr
.X_add_number
);
13574 if (imm_expr
.X_add_number
>= 0
13575 && imm_expr
.X_add_number
< 0x10000)
13576 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13577 else if (imm_expr
.X_add_number
> -0x8000
13578 && imm_expr
.X_add_number
< 0)
13580 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13581 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13582 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13584 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13587 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13588 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13593 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13594 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13597 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13600 case M_SGE
: /* X >= Y <==> not (X < Y) */
13606 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13607 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13610 case M_SGE_I
: /* X >= I <==> not (X < I). */
13612 if (imm_expr
.X_add_number
>= -0x8000
13613 && imm_expr
.X_add_number
< 0x8000)
13614 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13615 op
[0], op
[1], BFD_RELOC_LO16
);
13618 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13619 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13623 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13626 case M_SGT
: /* X > Y <==> Y < X. */
13632 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13635 case M_SGT_I
: /* X > I <==> I < X. */
13642 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13643 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13646 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13652 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13653 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13656 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13663 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13664 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13665 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13669 if (imm_expr
.X_add_number
>= -0x8000
13670 && imm_expr
.X_add_number
< 0x8000)
13672 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13677 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13678 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13682 if (imm_expr
.X_add_number
>= -0x8000
13683 && imm_expr
.X_add_number
< 0x8000)
13685 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13690 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13691 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13696 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13697 else if (op
[2] == 0)
13698 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13701 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13702 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13707 if (imm_expr
.X_add_number
== 0)
13709 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13714 as_warn (_("instruction %s: result is always true"),
13715 ip
->insn_mo
->name
);
13716 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13717 op
[0], 0, BFD_RELOC_LO16
);
13720 if (CPU_HAS_SEQ (mips_opts
.arch
)
13721 && -512 <= imm_expr
.X_add_number
13722 && imm_expr
.X_add_number
< 512)
13724 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13725 (int) imm_expr
.X_add_number
);
13728 if (imm_expr
.X_add_number
>= 0
13729 && imm_expr
.X_add_number
< 0x10000)
13731 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13734 else if (imm_expr
.X_add_number
> -0x8000
13735 && imm_expr
.X_add_number
< 0)
13737 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13738 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13739 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13741 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13744 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13745 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13750 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13751 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13754 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13760 if (ISA_IS_R6 (mips_opts
.isa
))
13772 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13774 if (imm_expr
.X_add_number
> -0x200
13775 && imm_expr
.X_add_number
<= 0x200
13776 && !ISA_IS_R6 (mips_opts
.isa
))
13778 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13779 (int) -imm_expr
.X_add_number
);
13788 if (imm_expr
.X_add_number
> -0x8000
13789 && imm_expr
.X_add_number
<= 0x8000)
13791 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13792 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13797 load_register (AT
, &imm_expr
, dbl
);
13798 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13820 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13821 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13826 gas_assert (!mips_opts
.micromips
);
13827 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13831 * Is the double cfc1 instruction a bug in the mips assembler;
13832 * or is there a reason for it?
13834 start_noreorder ();
13835 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13836 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13837 macro_build (NULL
, "nop", "");
13838 expr1
.X_add_number
= 3;
13839 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13840 expr1
.X_add_number
= 2;
13841 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13842 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13843 macro_build (NULL
, "nop", "");
13844 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13846 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13847 macro_build (NULL
, "nop", "");
13864 offbits
= (mips_opts
.micromips
? 12 : 16);
13870 offbits
= (mips_opts
.micromips
? 12 : 16);
13882 offbits
= (mips_opts
.micromips
? 12 : 16);
13889 offbits
= (mips_opts
.micromips
? 12 : 16);
13895 large_offset
= !small_offset_p (off
, align
, offbits
);
13897 expr1
.X_add_number
= 0;
13902 if (small_offset_p (0, align
, 16))
13903 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13904 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13907 load_address (tempreg
, ep
, &used_at
);
13909 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13910 tempreg
, tempreg
, breg
);
13912 offset_reloc
[0] = BFD_RELOC_LO16
;
13913 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13914 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13919 else if (!ust
&& op
[0] == breg
)
13930 if (!target_big_endian
)
13931 ep
->X_add_number
+= off
;
13933 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13935 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13936 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13938 if (!target_big_endian
)
13939 ep
->X_add_number
-= off
;
13941 ep
->X_add_number
+= off
;
13943 macro_build (NULL
, s2
, "t,~(b)",
13944 tempreg
, (int) ep
->X_add_number
, breg
);
13946 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13947 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13949 /* If necessary, move the result in tempreg to the final destination. */
13950 if (!ust
&& op
[0] != tempreg
)
13952 /* Protect second load's delay slot. */
13954 move_register (op
[0], tempreg
);
13960 if (target_big_endian
== ust
)
13961 ep
->X_add_number
+= off
;
13962 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13963 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13964 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13966 /* For halfword transfers we need a temporary register to shuffle
13967 bytes. Unfortunately for M_USH_A we have none available before
13968 the next store as AT holds the base address. We deal with this
13969 case by clobbering TREG and then restoring it as with ULH. */
13970 tempreg
= ust
== large_offset
? op
[0] : AT
;
13972 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13974 if (target_big_endian
== ust
)
13975 ep
->X_add_number
-= off
;
13977 ep
->X_add_number
+= off
;
13978 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13979 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13981 /* For M_USH_A re-retrieve the LSB. */
13982 if (ust
&& large_offset
)
13984 if (target_big_endian
)
13985 ep
->X_add_number
+= off
;
13987 ep
->X_add_number
-= off
;
13988 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13989 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13991 /* For ULH and M_USH_A OR the LSB in. */
13992 if (!ust
|| large_offset
)
13994 tempreg
= !large_offset
? AT
: op
[0];
13995 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13996 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
14001 /* FIXME: Check if this is one of the itbl macros, since they
14002 are added dynamically. */
14003 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
14006 if (!mips_opts
.at
&& used_at
)
14007 as_bad (_("macro used $at after \".set noat\""));
14010 /* Implement macros in mips16 mode. */
14013 mips16_macro (struct mips_cl_insn
*ip
)
14015 const struct mips_operand_array
*operands
;
14020 const char *s
, *s2
, *s3
;
14021 unsigned int op
[MAX_OPERANDS
];
14024 mask
= ip
->insn_mo
->mask
;
14026 operands
= insn_operands (ip
);
14027 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14028 if (operands
->operand
[i
])
14029 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14033 expr1
.X_op
= O_constant
;
14034 expr1
.X_op_symbol
= NULL
;
14035 expr1
.X_add_symbol
= NULL
;
14036 expr1
.X_add_number
= 1;
14047 /* Fall through. */
14053 /* Fall through. */
14057 start_noreorder ();
14058 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14059 expr1
.X_add_number
= 2;
14060 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14061 macro_build (NULL
, "break", "6", 7);
14063 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14064 since that causes an overflow. We should do that as well,
14065 but I don't see how to do the comparisons without a temporary
14068 macro_build (NULL
, s
, "x", op
[0]);
14087 start_noreorder ();
14088 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14089 expr1
.X_add_number
= 2;
14090 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14091 macro_build (NULL
, "break", "6", 7);
14093 macro_build (NULL
, s2
, "x", op
[0]);
14098 /* Fall through. */
14100 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14101 macro_build (NULL
, "mflo", "x", op
[0]);
14109 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14110 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14114 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14115 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14119 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14120 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14142 goto do_reverse_branch
;
14146 goto do_reverse_branch
;
14158 goto do_reverse_branch
;
14169 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14170 macro_build (&offset_expr
, s2
, "p");
14197 goto do_addone_branch_i
;
14202 goto do_addone_branch_i
;
14217 goto do_addone_branch_i
;
14223 do_addone_branch_i
:
14224 ++imm_expr
.X_add_number
;
14227 macro_build (&imm_expr
, s
, s3
, op
[0]);
14228 macro_build (&offset_expr
, s2
, "p");
14232 expr1
.X_add_number
= 0;
14233 macro_build (&expr1
, "slti", "x,8", op
[1]);
14234 if (op
[0] != op
[1])
14235 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14236 expr1
.X_add_number
= 2;
14237 macro_build (&expr1
, "bteqz", "p");
14238 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14243 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14244 opcode bits in *OPCODE_EXTRA. */
14246 static struct mips_opcode
*
14247 mips_lookup_insn (htab_t hash
, const char *start
,
14248 ssize_t length
, unsigned int *opcode_extra
)
14250 char *name
, *dot
, *p
;
14251 unsigned int mask
, suffix
;
14253 struct mips_opcode
*insn
;
14255 /* Make a copy of the instruction so that we can fiddle with it. */
14256 name
= xstrndup (start
, length
);
14258 /* Look up the instruction as-is. */
14259 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14263 dot
= strchr (name
, '.');
14266 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14267 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14268 if (*p
== 0 && mask
!= 0)
14271 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14273 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14275 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14281 if (mips_opts
.micromips
)
14283 /* See if there's an instruction size override suffix,
14284 either `16' or `32', at the end of the mnemonic proper,
14285 that defines the operation, i.e. before the first `.'
14286 character if any. Strip it and retry. */
14287 opend
= dot
!= NULL
? dot
- name
: length
;
14288 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14290 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14296 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14297 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14300 forced_insn_length
= suffix
;
14312 /* Assemble an instruction into its binary format. If the instruction
14313 is a macro, set imm_expr and offset_expr to the values associated
14314 with "I" and "A" operands respectively. Otherwise store the value
14315 of the relocatable field (if any) in offset_expr. In both cases
14316 set offset_reloc to the relocation operators applied to offset_expr. */
14319 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14321 const struct mips_opcode
*first
, *past
;
14325 struct mips_operand_token
*tokens
;
14326 unsigned int opcode_extra
;
14328 if (mips_opts
.micromips
)
14330 hash
= micromips_op_hash
;
14331 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14336 past
= &mips_opcodes
[NUMOPCODES
];
14338 forced_insn_length
= 0;
14341 /* We first try to match an instruction up to a space or to the end. */
14342 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14345 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14348 set_insn_error (0, _("unrecognized opcode"));
14352 if (strcmp (first
->name
, "li.s") == 0)
14354 else if (strcmp (first
->name
, "li.d") == 0)
14358 tokens
= mips_parse_arguments (str
+ end
, format
);
14362 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14363 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14364 set_insn_error (0, _("invalid operands"));
14366 obstack_free (&mips_operand_tokens
, tokens
);
14369 /* As for mips_ip, but used when assembling MIPS16 code.
14370 Also set forced_insn_length to the resulting instruction size in
14371 bytes if the user explicitly requested a small or extended instruction. */
14374 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14377 struct mips_opcode
*first
;
14378 struct mips_operand_token
*tokens
;
14381 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14403 else if (*s
== 'e')
14410 else if (*s
++ == ' ')
14412 set_insn_error (0, _("unrecognized opcode"));
14415 forced_insn_length
= l
;
14418 first
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, str
);
14423 set_insn_error (0, _("unrecognized opcode"));
14427 tokens
= mips_parse_arguments (s
, 0);
14431 if (!match_mips16_insns (insn
, first
, tokens
))
14432 set_insn_error (0, _("invalid operands"));
14434 obstack_free (&mips_operand_tokens
, tokens
);
14437 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14438 NBITS is the number of significant bits in VAL. */
14440 static unsigned long
14441 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14446 val
&= (1U << nbits
) - 1;
14447 if (nbits
== 16 || nbits
== 9)
14449 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14452 else if (nbits
== 15)
14454 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14457 else if (nbits
== 6)
14459 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14462 return (extval
<< 16) | val
;
14465 /* Like decode_mips16_operand, but require the operand to be defined and
14466 require it to be an integer. */
14468 static const struct mips_int_operand
*
14469 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14471 const struct mips_operand
*operand
;
14473 operand
= decode_mips16_operand (type
, extended_p
);
14474 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14476 return (const struct mips_int_operand
*) operand
;
14479 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14482 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14483 bfd_reloc_code_real_type reloc
, offsetT sval
)
14485 int min_val
, max_val
;
14487 min_val
= mips_int_operand_min (operand
);
14488 max_val
= mips_int_operand_max (operand
);
14489 if (reloc
!= BFD_RELOC_UNUSED
)
14492 sval
= SEXT_16BIT (sval
);
14497 return (sval
>= min_val
14499 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14502 /* Install immediate value VAL into MIPS16 instruction *INSN,
14503 extending it if necessary. The instruction in *INSN may
14504 already be extended.
14506 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14507 if none. In the former case, VAL is a 16-bit number with no
14508 defined signedness.
14510 TYPE is the type of the immediate field. USER_INSN_LENGTH
14511 is the length that the user requested, or 0 if none. */
14514 mips16_immed (const char *file
, unsigned int line
, int type
,
14515 bfd_reloc_code_real_type reloc
, offsetT val
,
14516 unsigned int user_insn_length
, unsigned long *insn
)
14518 const struct mips_int_operand
*operand
;
14519 unsigned int uval
, length
;
14521 operand
= mips16_immed_operand (type
, FALSE
);
14522 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14524 /* We need an extended instruction. */
14525 if (user_insn_length
== 2)
14526 as_bad_where (file
, line
, _("invalid unextended operand value"));
14528 *insn
|= MIPS16_EXTEND
;
14530 else if (user_insn_length
== 4)
14532 /* The operand doesn't force an unextended instruction to be extended.
14533 Warn if the user wanted an extended instruction anyway. */
14534 *insn
|= MIPS16_EXTEND
;
14535 as_warn_where (file
, line
,
14536 _("extended operand requested but not required"));
14539 length
= mips16_opcode_length (*insn
);
14542 operand
= mips16_immed_operand (type
, TRUE
);
14543 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14544 as_bad_where (file
, line
,
14545 _("operand value out of range for instruction"));
14547 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14548 if (length
== 2 || operand
->root
.lsb
!= 0)
14549 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14551 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14554 struct percent_op_match
14557 bfd_reloc_code_real_type reloc
;
14560 static const struct percent_op_match mips_percent_op
[] =
14562 {"%lo", BFD_RELOC_LO16
},
14563 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14564 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14565 {"%call16", BFD_RELOC_MIPS_CALL16
},
14566 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14567 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14568 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14569 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14570 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14571 {"%got", BFD_RELOC_MIPS_GOT16
},
14572 {"%gp_rel", BFD_RELOC_GPREL16
},
14573 {"%gprel", BFD_RELOC_GPREL16
},
14574 {"%half", BFD_RELOC_16
},
14575 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14576 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14577 {"%neg", BFD_RELOC_MIPS_SUB
},
14578 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14579 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14580 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14581 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14582 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14583 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14584 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14585 {"%hi", BFD_RELOC_HI16_S
},
14586 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14587 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14590 static const struct percent_op_match mips16_percent_op
[] =
14592 {"%lo", BFD_RELOC_MIPS16_LO16
},
14593 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14594 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14595 {"%got", BFD_RELOC_MIPS16_GOT16
},
14596 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14597 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14598 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14599 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14600 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14601 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14602 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14603 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14604 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14608 /* Return true if *STR points to a relocation operator. When returning true,
14609 move *STR over the operator and store its relocation code in *RELOC.
14610 Leave both *STR and *RELOC alone when returning false. */
14613 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14615 const struct percent_op_match
*percent_op
;
14618 if (mips_opts
.mips16
)
14620 percent_op
= mips16_percent_op
;
14621 limit
= ARRAY_SIZE (mips16_percent_op
);
14625 percent_op
= mips_percent_op
;
14626 limit
= ARRAY_SIZE (mips_percent_op
);
14629 for (i
= 0; i
< limit
; i
++)
14630 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14632 int len
= strlen (percent_op
[i
].str
);
14634 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14637 *str
+= strlen (percent_op
[i
].str
);
14638 *reloc
= percent_op
[i
].reloc
;
14640 /* Check whether the output BFD supports this relocation.
14641 If not, issue an error and fall back on something safe. */
14642 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14644 as_bad (_("relocation %s isn't supported by the current ABI"),
14645 percent_op
[i
].str
);
14646 *reloc
= BFD_RELOC_UNUSED
;
14654 /* Parse string STR as a 16-bit relocatable operand. Store the
14655 expression in *EP and the relocations in the array starting
14656 at RELOC. Return the number of relocation operators used.
14658 On exit, EXPR_END points to the first character after the expression. */
14661 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14664 bfd_reloc_code_real_type reversed_reloc
[3];
14665 size_t reloc_index
, i
;
14666 int crux_depth
, str_depth
;
14669 /* Search for the start of the main expression, recoding relocations
14670 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14671 of the main expression and with CRUX_DEPTH containing the number
14672 of open brackets at that point. */
14679 crux_depth
= str_depth
;
14681 /* Skip over whitespace and brackets, keeping count of the number
14683 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14688 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14689 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14691 my_getExpression (ep
, crux
);
14694 /* Match every open bracket. */
14695 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14699 if (crux_depth
> 0)
14700 as_bad (_("unclosed '('"));
14704 for (i
= 0; i
< reloc_index
; i
++)
14705 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14707 return reloc_index
;
14711 my_getExpression (expressionS
*ep
, char *str
)
14715 save_in
= input_line_pointer
;
14716 input_line_pointer
= str
;
14718 expr_end
= input_line_pointer
;
14719 input_line_pointer
= save_in
;
14723 md_atof (int type
, char *litP
, int *sizeP
)
14725 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14729 md_number_to_chars (char *buf
, valueT val
, int n
)
14731 if (target_big_endian
)
14732 number_to_chars_bigendian (buf
, val
, n
);
14734 number_to_chars_littleendian (buf
, val
, n
);
14737 static int support_64bit_objects(void)
14739 const char **list
, **l
;
14742 list
= bfd_target_list ();
14743 for (l
= list
; *l
!= NULL
; l
++)
14744 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14745 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14747 yes
= (*l
!= NULL
);
14752 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14753 NEW_VALUE. Warn if another value was already specified. Note:
14754 we have to defer parsing the -march and -mtune arguments in order
14755 to handle 'from-abi' correctly, since the ABI might be specified
14756 in a later argument. */
14759 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14761 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14762 as_warn (_("a different %s was already specified, is now %s"),
14763 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14766 *string_ptr
= new_value
;
14770 md_parse_option (int c
, const char *arg
)
14774 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14775 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14777 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14778 c
== mips_ases
[i
].option_on
);
14784 case OPTION_CONSTRUCT_FLOATS
:
14785 mips_disable_float_construction
= 0;
14788 case OPTION_NO_CONSTRUCT_FLOATS
:
14789 mips_disable_float_construction
= 1;
14801 target_big_endian
= 1;
14805 target_big_endian
= 0;
14811 else if (arg
[0] == '0')
14813 else if (arg
[0] == '1')
14823 mips_debug
= atoi (arg
);
14827 file_mips_opts
.isa
= ISA_MIPS1
;
14831 file_mips_opts
.isa
= ISA_MIPS2
;
14835 file_mips_opts
.isa
= ISA_MIPS3
;
14839 file_mips_opts
.isa
= ISA_MIPS4
;
14843 file_mips_opts
.isa
= ISA_MIPS5
;
14846 case OPTION_MIPS32
:
14847 file_mips_opts
.isa
= ISA_MIPS32
;
14850 case OPTION_MIPS32R2
:
14851 file_mips_opts
.isa
= ISA_MIPS32R2
;
14854 case OPTION_MIPS32R3
:
14855 file_mips_opts
.isa
= ISA_MIPS32R3
;
14858 case OPTION_MIPS32R5
:
14859 file_mips_opts
.isa
= ISA_MIPS32R5
;
14862 case OPTION_MIPS32R6
:
14863 file_mips_opts
.isa
= ISA_MIPS32R6
;
14866 case OPTION_MIPS64R2
:
14867 file_mips_opts
.isa
= ISA_MIPS64R2
;
14870 case OPTION_MIPS64R3
:
14871 file_mips_opts
.isa
= ISA_MIPS64R3
;
14874 case OPTION_MIPS64R5
:
14875 file_mips_opts
.isa
= ISA_MIPS64R5
;
14878 case OPTION_MIPS64R6
:
14879 file_mips_opts
.isa
= ISA_MIPS64R6
;
14882 case OPTION_MIPS64
:
14883 file_mips_opts
.isa
= ISA_MIPS64
;
14887 mips_set_option_string (&mips_tune_string
, arg
);
14891 mips_set_option_string (&mips_arch_string
, arg
);
14895 mips_set_option_string (&mips_arch_string
, "4650");
14896 mips_set_option_string (&mips_tune_string
, "4650");
14899 case OPTION_NO_M4650
:
14903 mips_set_option_string (&mips_arch_string
, "4010");
14904 mips_set_option_string (&mips_tune_string
, "4010");
14907 case OPTION_NO_M4010
:
14911 mips_set_option_string (&mips_arch_string
, "4100");
14912 mips_set_option_string (&mips_tune_string
, "4100");
14915 case OPTION_NO_M4100
:
14919 mips_set_option_string (&mips_arch_string
, "3900");
14920 mips_set_option_string (&mips_tune_string
, "3900");
14923 case OPTION_NO_M3900
:
14926 case OPTION_MICROMIPS
:
14927 if (file_mips_opts
.mips16
== 1)
14929 as_bad (_("-mmicromips cannot be used with -mips16"));
14932 file_mips_opts
.micromips
= 1;
14933 mips_no_prev_insn ();
14936 case OPTION_NO_MICROMIPS
:
14937 file_mips_opts
.micromips
= 0;
14938 mips_no_prev_insn ();
14941 case OPTION_MIPS16
:
14942 if (file_mips_opts
.micromips
== 1)
14944 as_bad (_("-mips16 cannot be used with -micromips"));
14947 file_mips_opts
.mips16
= 1;
14948 mips_no_prev_insn ();
14951 case OPTION_NO_MIPS16
:
14952 file_mips_opts
.mips16
= 0;
14953 mips_no_prev_insn ();
14956 case OPTION_FIX_24K
:
14960 case OPTION_NO_FIX_24K
:
14964 case OPTION_FIX_RM7000
:
14965 mips_fix_rm7000
= 1;
14968 case OPTION_NO_FIX_RM7000
:
14969 mips_fix_rm7000
= 0;
14972 case OPTION_FIX_LOONGSON3_LLSC
:
14973 mips_fix_loongson3_llsc
= TRUE
;
14976 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14977 mips_fix_loongson3_llsc
= FALSE
;
14980 case OPTION_FIX_LOONGSON2F_JUMP
:
14981 mips_fix_loongson2f_jump
= TRUE
;
14984 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14985 mips_fix_loongson2f_jump
= FALSE
;
14988 case OPTION_FIX_LOONGSON2F_NOP
:
14989 mips_fix_loongson2f_nop
= TRUE
;
14992 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14993 mips_fix_loongson2f_nop
= FALSE
;
14996 case OPTION_FIX_VR4120
:
14997 mips_fix_vr4120
= 1;
15000 case OPTION_NO_FIX_VR4120
:
15001 mips_fix_vr4120
= 0;
15004 case OPTION_FIX_VR4130
:
15005 mips_fix_vr4130
= 1;
15008 case OPTION_NO_FIX_VR4130
:
15009 mips_fix_vr4130
= 0;
15012 case OPTION_FIX_CN63XXP1
:
15013 mips_fix_cn63xxp1
= TRUE
;
15016 case OPTION_NO_FIX_CN63XXP1
:
15017 mips_fix_cn63xxp1
= FALSE
;
15020 case OPTION_FIX_R5900
:
15021 mips_fix_r5900
= TRUE
;
15022 mips_fix_r5900_explicit
= TRUE
;
15025 case OPTION_NO_FIX_R5900
:
15026 mips_fix_r5900
= FALSE
;
15027 mips_fix_r5900_explicit
= TRUE
;
15030 case OPTION_RELAX_BRANCH
:
15031 mips_relax_branch
= 1;
15034 case OPTION_NO_RELAX_BRANCH
:
15035 mips_relax_branch
= 0;
15038 case OPTION_IGNORE_BRANCH_ISA
:
15039 mips_ignore_branch_isa
= TRUE
;
15042 case OPTION_NO_IGNORE_BRANCH_ISA
:
15043 mips_ignore_branch_isa
= FALSE
;
15046 case OPTION_INSN32
:
15047 file_mips_opts
.insn32
= TRUE
;
15050 case OPTION_NO_INSN32
:
15051 file_mips_opts
.insn32
= FALSE
;
15054 case OPTION_MSHARED
:
15055 mips_in_shared
= TRUE
;
15058 case OPTION_MNO_SHARED
:
15059 mips_in_shared
= FALSE
;
15062 case OPTION_MSYM32
:
15063 file_mips_opts
.sym32
= TRUE
;
15066 case OPTION_MNO_SYM32
:
15067 file_mips_opts
.sym32
= FALSE
;
15070 /* When generating ELF code, we permit -KPIC and -call_shared to
15071 select SVR4_PIC, and -non_shared to select no PIC. This is
15072 intended to be compatible with Irix 5. */
15073 case OPTION_CALL_SHARED
:
15074 mips_pic
= SVR4_PIC
;
15075 mips_abicalls
= TRUE
;
15078 case OPTION_CALL_NONPIC
:
15080 mips_abicalls
= TRUE
;
15083 case OPTION_NON_SHARED
:
15085 mips_abicalls
= FALSE
;
15088 /* The -xgot option tells the assembler to use 32 bit offsets
15089 when accessing the got in SVR4_PIC mode. It is for Irix
15096 g_switch_value
= atoi (arg
);
15100 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15103 mips_abi
= O32_ABI
;
15107 mips_abi
= N32_ABI
;
15111 mips_abi
= N64_ABI
;
15112 if (!support_64bit_objects())
15113 as_fatal (_("no compiled in support for 64 bit object file format"));
15117 file_mips_opts
.gp
= 32;
15121 file_mips_opts
.gp
= 64;
15125 file_mips_opts
.fp
= 32;
15129 file_mips_opts
.fp
= 0;
15133 file_mips_opts
.fp
= 64;
15136 case OPTION_ODD_SPREG
:
15137 file_mips_opts
.oddspreg
= 1;
15140 case OPTION_NO_ODD_SPREG
:
15141 file_mips_opts
.oddspreg
= 0;
15144 case OPTION_SINGLE_FLOAT
:
15145 file_mips_opts
.single_float
= 1;
15148 case OPTION_DOUBLE_FLOAT
:
15149 file_mips_opts
.single_float
= 0;
15152 case OPTION_SOFT_FLOAT
:
15153 file_mips_opts
.soft_float
= 1;
15156 case OPTION_HARD_FLOAT
:
15157 file_mips_opts
.soft_float
= 0;
15161 if (strcmp (arg
, "32") == 0)
15162 mips_abi
= O32_ABI
;
15163 else if (strcmp (arg
, "o64") == 0)
15164 mips_abi
= O64_ABI
;
15165 else if (strcmp (arg
, "n32") == 0)
15166 mips_abi
= N32_ABI
;
15167 else if (strcmp (arg
, "64") == 0)
15169 mips_abi
= N64_ABI
;
15170 if (! support_64bit_objects())
15171 as_fatal (_("no compiled in support for 64 bit object file "
15174 else if (strcmp (arg
, "eabi") == 0)
15175 mips_abi
= EABI_ABI
;
15178 as_fatal (_("invalid abi -mabi=%s"), arg
);
15183 case OPTION_M7000_HILO_FIX
:
15184 mips_7000_hilo_fix
= TRUE
;
15187 case OPTION_MNO_7000_HILO_FIX
:
15188 mips_7000_hilo_fix
= FALSE
;
15191 case OPTION_MDEBUG
:
15192 mips_flag_mdebug
= TRUE
;
15195 case OPTION_NO_MDEBUG
:
15196 mips_flag_mdebug
= FALSE
;
15200 mips_flag_pdr
= TRUE
;
15203 case OPTION_NO_PDR
:
15204 mips_flag_pdr
= FALSE
;
15207 case OPTION_MVXWORKS_PIC
:
15208 mips_pic
= VXWORKS_PIC
;
15212 if (strcmp (arg
, "2008") == 0)
15214 else if (strcmp (arg
, "legacy") == 0)
15218 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15227 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15232 /* Set up globals to tune for the ISA or processor described by INFO. */
15235 mips_set_tune (const struct mips_cpu_info
*info
)
15238 mips_tune
= info
->cpu
;
15243 mips_after_parse_args (void)
15245 const struct mips_cpu_info
*arch_info
= 0;
15246 const struct mips_cpu_info
*tune_info
= 0;
15248 /* GP relative stuff not working for PE. */
15249 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15251 if (g_switch_seen
&& g_switch_value
!= 0)
15252 as_bad (_("-G not supported in this configuration"));
15253 g_switch_value
= 0;
15256 if (mips_abi
== NO_ABI
)
15257 mips_abi
= MIPS_DEFAULT_ABI
;
15259 /* The following code determines the architecture.
15260 Similar code was added to GCC 3.3 (see override_options() in
15261 config/mips/mips.c). The GAS and GCC code should be kept in sync
15262 as much as possible. */
15264 if (mips_arch_string
!= 0)
15265 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15267 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15269 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15270 ISA level specified by -mipsN, while arch_info->isa contains
15271 the -march selection (if any). */
15272 if (arch_info
!= 0)
15274 /* -march takes precedence over -mipsN, since it is more descriptive.
15275 There's no harm in specifying both as long as the ISA levels
15277 if (file_mips_opts
.isa
!= arch_info
->isa
)
15278 as_bad (_("-%s conflicts with the other architecture options,"
15279 " which imply -%s"),
15280 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15281 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15284 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15287 if (arch_info
== 0)
15289 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15290 gas_assert (arch_info
);
15293 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15294 as_bad (_("-march=%s is not compatible with the selected ABI"),
15297 file_mips_opts
.arch
= arch_info
->cpu
;
15298 file_mips_opts
.isa
= arch_info
->isa
;
15299 file_mips_opts
.init_ase
= arch_info
->ase
;
15301 /* The EVA Extension has instructions which are only valid when the R6 ISA
15302 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15304 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15305 file_mips_opts
.ase
|= ASE_EVA_R6
;
15307 /* Set up initial mips_opts state. */
15308 mips_opts
= file_mips_opts
;
15310 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15311 if (!mips_fix_r5900_explicit
)
15312 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15314 /* The register size inference code is now placed in
15315 file_mips_check_options. */
15317 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15319 if (mips_tune_string
!= 0)
15320 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15322 if (tune_info
== 0)
15323 mips_set_tune (arch_info
);
15325 mips_set_tune (tune_info
);
15327 if (mips_flag_mdebug
< 0)
15328 mips_flag_mdebug
= 0;
15332 mips_init_after_args (void)
15334 /* Initialize opcodes. */
15335 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15336 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15340 md_pcrel_from (fixS
*fixP
)
15342 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15344 switch (fixP
->fx_r_type
)
15346 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15347 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15348 /* Return the address of the delay slot. */
15351 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15352 case BFD_RELOC_MICROMIPS_JMP
:
15353 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15354 case BFD_RELOC_16_PCREL_S2
:
15355 case BFD_RELOC_MIPS_21_PCREL_S2
:
15356 case BFD_RELOC_MIPS_26_PCREL_S2
:
15357 case BFD_RELOC_MIPS_JMP
:
15358 /* Return the address of the delay slot. */
15361 case BFD_RELOC_MIPS_18_PCREL_S3
:
15362 /* Return the aligned address of the doubleword containing
15363 the instruction. */
15371 /* This is called before the symbol table is processed. In order to
15372 work with gcc when using mips-tfile, we must keep all local labels.
15373 However, in other cases, we want to discard them. If we were
15374 called with -g, but we didn't see any debugging information, it may
15375 mean that gcc is smuggling debugging information through to
15376 mips-tfile, in which case we must generate all local labels. */
15379 mips_frob_file_before_adjust (void)
15381 #ifndef NO_ECOFF_DEBUGGING
15382 if (ECOFF_DEBUGGING
15384 && ! ecoff_debugging_seen
)
15385 flag_keep_locals
= 1;
15389 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15390 the corresponding LO16 reloc. This is called before md_apply_fix and
15391 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15392 relocation operators.
15394 For our purposes, a %lo() expression matches a %got() or %hi()
15397 (a) it refers to the same symbol; and
15398 (b) the offset applied in the %lo() expression is no lower than
15399 the offset applied in the %got() or %hi().
15401 (b) allows us to cope with code like:
15404 lh $4,%lo(foo+2)($4)
15406 ...which is legal on RELA targets, and has a well-defined behaviour
15407 if the user knows that adding 2 to "foo" will not induce a carry to
15410 When several %lo()s match a particular %got() or %hi(), we use the
15411 following rules to distinguish them:
15413 (1) %lo()s with smaller offsets are a better match than %lo()s with
15416 (2) %lo()s with no matching %got() or %hi() are better than those
15417 that already have a matching %got() or %hi().
15419 (3) later %lo()s are better than earlier %lo()s.
15421 These rules are applied in order.
15423 (1) means, among other things, that %lo()s with identical offsets are
15424 chosen if they exist.
15426 (2) means that we won't associate several high-part relocations with
15427 the same low-part relocation unless there's no alternative. Having
15428 several high parts for the same low part is a GNU extension; this rule
15429 allows careful users to avoid it.
15431 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15432 with the last high-part relocation being at the front of the list.
15433 It therefore makes sense to choose the last matching low-part
15434 relocation, all other things being equal. It's also easier
15435 to code that way. */
15438 mips_frob_file (void)
15440 struct mips_hi_fixup
*l
;
15441 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15443 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15445 segment_info_type
*seginfo
;
15446 bfd_boolean matched_lo_p
;
15447 fixS
**hi_pos
, **lo_pos
, **pos
;
15449 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15451 /* If a GOT16 relocation turns out to be against a global symbol,
15452 there isn't supposed to be a matching LO. Ignore %gots against
15453 constants; we'll report an error for those later. */
15454 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15455 && !(l
->fixp
->fx_addsy
15456 && pic_need_relax (l
->fixp
->fx_addsy
)))
15459 /* Check quickly whether the next fixup happens to be a matching %lo. */
15460 if (fixup_has_matching_lo_p (l
->fixp
))
15463 seginfo
= seg_info (l
->seg
);
15465 /* Set HI_POS to the position of this relocation in the chain.
15466 Set LO_POS to the position of the chosen low-part relocation.
15467 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15468 relocation that matches an immediately-preceding high-part
15472 matched_lo_p
= FALSE
;
15473 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15475 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15477 if (*pos
== l
->fixp
)
15480 if ((*pos
)->fx_r_type
== looking_for_rtype
15481 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15482 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15484 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15486 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15489 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15490 && fixup_has_matching_lo_p (*pos
));
15493 /* If we found a match, remove the high-part relocation from its
15494 current position and insert it before the low-part relocation.
15495 Make the offsets match so that fixup_has_matching_lo_p()
15498 We don't warn about unmatched high-part relocations since some
15499 versions of gcc have been known to emit dead "lui ...%hi(...)"
15501 if (lo_pos
!= NULL
)
15503 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15504 if (l
->fixp
->fx_next
!= *lo_pos
)
15506 *hi_pos
= l
->fixp
->fx_next
;
15507 l
->fixp
->fx_next
= *lo_pos
;
15515 mips_force_relocation (fixS
*fixp
)
15517 if (generic_force_reloc (fixp
))
15520 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15521 so that the linker relaxation can update targets. */
15522 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15523 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15524 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15527 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15528 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15529 microMIPS symbols so that we can do cross-mode branch diagnostics
15530 and BAL to JALX conversion by the linker. */
15531 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15532 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15533 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15535 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15538 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15539 if (ISA_IS_R6 (file_mips_opts
.isa
)
15540 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15541 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15542 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15543 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15544 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15545 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15546 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15552 /* Implement TC_FORCE_RELOCATION_ABS. */
15555 mips_force_relocation_abs (fixS
*fixp
)
15557 if (generic_force_reloc (fixp
))
15560 /* These relocations do not have enough bits in the in-place addend
15561 to hold an arbitrary absolute section's offset. */
15562 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15568 /* Read the instruction associated with RELOC from BUF. */
15570 static unsigned int
15571 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15573 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15574 return read_compressed_insn (buf
, 4);
15576 return read_insn (buf
);
15579 /* Write instruction INSN to BUF, given that it has been relocated
15583 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15584 unsigned long insn
)
15586 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15587 write_compressed_insn (buf
, insn
, 4);
15589 write_insn (buf
, insn
);
15592 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15593 to a symbol in another ISA mode, which cannot be converted to JALX. */
15596 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15598 unsigned long opcode
;
15602 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15605 other
= S_GET_OTHER (fixP
->fx_addsy
);
15606 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15607 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15608 switch (fixP
->fx_r_type
)
15610 case BFD_RELOC_MIPS_JMP
:
15611 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15612 case BFD_RELOC_MICROMIPS_JMP
:
15613 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15619 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15620 jump to a symbol in the same ISA mode. */
15623 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15625 unsigned long opcode
;
15629 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15632 other
= S_GET_OTHER (fixP
->fx_addsy
);
15633 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15634 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15635 switch (fixP
->fx_r_type
)
15637 case BFD_RELOC_MIPS_JMP
:
15638 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15639 case BFD_RELOC_MIPS16_JMP
:
15640 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15641 case BFD_RELOC_MICROMIPS_JMP
:
15642 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15648 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15649 to a symbol whose value plus addend is not aligned according to the
15650 ultimate (after linker relaxation) jump instruction's immediate field
15651 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15652 regular MIPS code, to (1 << 2). */
15655 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15657 bfd_boolean micro_to_mips_p
;
15661 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15664 other
= S_GET_OTHER (fixP
->fx_addsy
);
15665 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15666 val
+= fixP
->fx_offset
;
15667 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15668 && !ELF_ST_IS_MICROMIPS (other
));
15669 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15670 != ELF_ST_IS_COMPRESSED (other
));
15673 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15674 to a symbol whose annotation indicates another ISA mode. For absolute
15675 symbols check the ISA bit instead.
15677 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15678 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15679 MIPS symbols and associated with BAL instructions as these instructions
15680 may be converted to JALX by the linker. */
15683 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15685 bfd_boolean absolute_p
;
15686 unsigned long opcode
;
15692 if (mips_ignore_branch_isa
)
15695 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15698 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15699 absolute_p
= bfd_is_abs_section (symsec
);
15701 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15702 other
= S_GET_OTHER (fixP
->fx_addsy
);
15704 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15705 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15706 switch (fixP
->fx_r_type
)
15708 case BFD_RELOC_16_PCREL_S2
:
15709 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15710 && opcode
!= 0x0411);
15711 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15712 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15713 && opcode
!= 0x4060);
15714 case BFD_RELOC_MIPS_21_PCREL_S2
:
15715 case BFD_RELOC_MIPS_26_PCREL_S2
:
15716 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15717 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15718 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15719 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15720 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15721 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15727 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15728 branch instruction pointed to by FIXP is not aligned according to the
15729 branch instruction's immediate field requirement. We need the addend
15730 to preserve the ISA bit and also the sum must not have bit 2 set. We
15731 must explicitly OR in the ISA bit from symbol annotation as the bit
15732 won't be set in the symbol's value then. */
15735 fix_bad_misaligned_branch_p (fixS
*fixP
)
15737 bfd_boolean absolute_p
;
15744 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15747 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15748 absolute_p
= bfd_is_abs_section (symsec
);
15750 val
= S_GET_VALUE (fixP
->fx_addsy
);
15751 other
= S_GET_OTHER (fixP
->fx_addsy
);
15752 off
= fixP
->fx_offset
;
15754 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15755 val
|= ELF_ST_IS_COMPRESSED (other
);
15757 return (val
& 0x3) != isa_bit
;
15760 /* Calculate the relocation target by masking off ISA mode bit before
15761 combining symbol and addend. */
15764 fix_bad_misaligned_address (fixS
*fixP
)
15769 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15770 val
= S_GET_VALUE (fixP
->fx_addsy
);
15771 off
= fixP
->fx_offset
;
15772 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15775 return ((val
& ~isa_mode
) + off
);
15778 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15779 and its calculated value VAL. */
15782 fix_validate_branch (fixS
*fixP
, valueT val
)
15784 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15786 _("branch to misaligned address (0x%lx)"),
15787 (long) (val
+ md_pcrel_from (fixP
)));
15788 else if (fix_bad_cross_mode_branch_p (fixP
))
15789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15790 _("branch to a symbol in another ISA mode"));
15791 else if (fix_bad_misaligned_branch_p (fixP
))
15792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15793 _("branch to misaligned address (0x%lx)"),
15794 (long) fix_bad_misaligned_address (fixP
));
15795 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15797 _("cannot encode misaligned addend "
15798 "in the relocatable field (0x%lx)"),
15799 (long) fixP
->fx_offset
);
15802 /* Apply a fixup to the object file. */
15805 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15808 unsigned long insn
;
15809 reloc_howto_type
*howto
;
15811 if (fixP
->fx_pcrel
)
15812 switch (fixP
->fx_r_type
)
15814 case BFD_RELOC_16_PCREL_S2
:
15815 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15816 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15817 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15818 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15819 case BFD_RELOC_32_PCREL
:
15820 case BFD_RELOC_MIPS_21_PCREL_S2
:
15821 case BFD_RELOC_MIPS_26_PCREL_S2
:
15822 case BFD_RELOC_MIPS_18_PCREL_S3
:
15823 case BFD_RELOC_MIPS_19_PCREL_S2
:
15824 case BFD_RELOC_HI16_S_PCREL
:
15825 case BFD_RELOC_LO16_PCREL
:
15829 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15834 _("PC-relative reference to a different section"));
15838 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15839 that have no MIPS ELF equivalent. */
15840 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15842 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15847 gas_assert (fixP
->fx_size
== 2
15848 || fixP
->fx_size
== 4
15849 || fixP
->fx_r_type
== BFD_RELOC_8
15850 || fixP
->fx_r_type
== BFD_RELOC_16
15851 || fixP
->fx_r_type
== BFD_RELOC_64
15852 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15853 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15854 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15855 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15856 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15857 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15858 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15860 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15862 /* Don't treat parts of a composite relocation as done. There are two
15865 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15866 should nevertheless be emitted if the first part is.
15868 (2) In normal usage, composite relocations are never assembly-time
15869 constants. The easiest way of dealing with the pathological
15870 exceptions is to generate a relocation against STN_UNDEF and
15871 leave everything up to the linker. */
15872 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15875 switch (fixP
->fx_r_type
)
15877 case BFD_RELOC_MIPS_TLS_GD
:
15878 case BFD_RELOC_MIPS_TLS_LDM
:
15879 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15880 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15881 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15882 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15883 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15884 case BFD_RELOC_MIPS_TLS_TPREL32
:
15885 case BFD_RELOC_MIPS_TLS_TPREL64
:
15886 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15887 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15888 case BFD_RELOC_MICROMIPS_TLS_GD
:
15889 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15890 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15891 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15892 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15893 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15894 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15895 case BFD_RELOC_MIPS16_TLS_GD
:
15896 case BFD_RELOC_MIPS16_TLS_LDM
:
15897 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15898 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15899 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15900 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15901 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15902 if (fixP
->fx_addsy
)
15903 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15906 _("TLS relocation against a constant"));
15909 case BFD_RELOC_MIPS_JMP
:
15910 case BFD_RELOC_MIPS16_JMP
:
15911 case BFD_RELOC_MICROMIPS_JMP
:
15915 gas_assert (!fixP
->fx_done
);
15917 /* Shift is 2, unusually, for microMIPS JALX. */
15918 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15919 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15924 if (fix_bad_cross_mode_jump_p (fixP
))
15925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15926 _("jump to a symbol in another ISA mode"));
15927 else if (fix_bad_same_mode_jalx_p (fixP
))
15928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15929 _("JALX to a symbol in the same ISA mode"));
15930 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15932 _("jump to misaligned address (0x%lx)"),
15933 (long) fix_bad_misaligned_address (fixP
));
15934 else if (HAVE_IN_PLACE_ADDENDS
15935 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15937 _("cannot encode misaligned addend "
15938 "in the relocatable field (0x%lx)"),
15939 (long) fixP
->fx_offset
);
15941 /* Fall through. */
15943 case BFD_RELOC_MIPS_SHIFT5
:
15944 case BFD_RELOC_MIPS_SHIFT6
:
15945 case BFD_RELOC_MIPS_GOT_DISP
:
15946 case BFD_RELOC_MIPS_GOT_PAGE
:
15947 case BFD_RELOC_MIPS_GOT_OFST
:
15948 case BFD_RELOC_MIPS_SUB
:
15949 case BFD_RELOC_MIPS_INSERT_A
:
15950 case BFD_RELOC_MIPS_INSERT_B
:
15951 case BFD_RELOC_MIPS_DELETE
:
15952 case BFD_RELOC_MIPS_HIGHEST
:
15953 case BFD_RELOC_MIPS_HIGHER
:
15954 case BFD_RELOC_MIPS_SCN_DISP
:
15955 case BFD_RELOC_MIPS_REL16
:
15956 case BFD_RELOC_MIPS_RELGOT
:
15957 case BFD_RELOC_MIPS_JALR
:
15958 case BFD_RELOC_HI16
:
15959 case BFD_RELOC_HI16_S
:
15960 case BFD_RELOC_LO16
:
15961 case BFD_RELOC_GPREL16
:
15962 case BFD_RELOC_MIPS_LITERAL
:
15963 case BFD_RELOC_MIPS_CALL16
:
15964 case BFD_RELOC_MIPS_GOT16
:
15965 case BFD_RELOC_GPREL32
:
15966 case BFD_RELOC_MIPS_GOT_HI16
:
15967 case BFD_RELOC_MIPS_GOT_LO16
:
15968 case BFD_RELOC_MIPS_CALL_HI16
:
15969 case BFD_RELOC_MIPS_CALL_LO16
:
15970 case BFD_RELOC_HI16_S_PCREL
:
15971 case BFD_RELOC_LO16_PCREL
:
15972 case BFD_RELOC_MIPS16_GPREL
:
15973 case BFD_RELOC_MIPS16_GOT16
:
15974 case BFD_RELOC_MIPS16_CALL16
:
15975 case BFD_RELOC_MIPS16_HI16
:
15976 case BFD_RELOC_MIPS16_HI16_S
:
15977 case BFD_RELOC_MIPS16_LO16
:
15978 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15979 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15980 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15981 case BFD_RELOC_MICROMIPS_SUB
:
15982 case BFD_RELOC_MICROMIPS_HIGHEST
:
15983 case BFD_RELOC_MICROMIPS_HIGHER
:
15984 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15985 case BFD_RELOC_MICROMIPS_JALR
:
15986 case BFD_RELOC_MICROMIPS_HI16
:
15987 case BFD_RELOC_MICROMIPS_HI16_S
:
15988 case BFD_RELOC_MICROMIPS_LO16
:
15989 case BFD_RELOC_MICROMIPS_GPREL16
:
15990 case BFD_RELOC_MICROMIPS_LITERAL
:
15991 case BFD_RELOC_MICROMIPS_CALL16
:
15992 case BFD_RELOC_MICROMIPS_GOT16
:
15993 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15994 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15995 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15996 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15997 case BFD_RELOC_MIPS_EH
:
16002 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16004 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16005 if (mips16_reloc_p (fixP
->fx_r_type
))
16006 insn
|= mips16_immed_extend (value
, 16);
16008 insn
|= (value
& 0xffff);
16009 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16013 _("unsupported constant in relocation"));
16018 /* This is handled like BFD_RELOC_32, but we output a sign
16019 extended value if we are only 32 bits. */
16022 if (8 <= sizeof (valueT
))
16023 md_number_to_chars (buf
, *valP
, 8);
16028 if ((*valP
& 0x80000000) != 0)
16032 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16033 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16038 case BFD_RELOC_RVA
:
16040 case BFD_RELOC_32_PCREL
:
16043 /* If we are deleting this reloc entry, we must fill in the
16044 value now. This can happen if we have a .word which is not
16045 resolved when it appears but is later defined. */
16047 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16050 case BFD_RELOC_MIPS_21_PCREL_S2
:
16051 fix_validate_branch (fixP
, *valP
);
16052 if (!fixP
->fx_done
)
16055 if (*valP
+ 0x400000 <= 0x7fffff)
16057 insn
= read_insn (buf
);
16058 insn
|= (*valP
>> 2) & 0x1fffff;
16059 write_insn (buf
, insn
);
16062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16063 _("branch out of range"));
16066 case BFD_RELOC_MIPS_26_PCREL_S2
:
16067 fix_validate_branch (fixP
, *valP
);
16068 if (!fixP
->fx_done
)
16071 if (*valP
+ 0x8000000 <= 0xfffffff)
16073 insn
= read_insn (buf
);
16074 insn
|= (*valP
>> 2) & 0x3ffffff;
16075 write_insn (buf
, insn
);
16078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16079 _("branch out of range"));
16082 case BFD_RELOC_MIPS_18_PCREL_S3
:
16083 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16085 _("PC-relative access using misaligned symbol (%lx)"),
16086 (long) S_GET_VALUE (fixP
->fx_addsy
));
16087 if ((fixP
->fx_offset
& 0x7) != 0)
16088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16089 _("PC-relative access using misaligned offset (%lx)"),
16090 (long) fixP
->fx_offset
);
16091 if (!fixP
->fx_done
)
16094 if (*valP
+ 0x100000 <= 0x1fffff)
16096 insn
= read_insn (buf
);
16097 insn
|= (*valP
>> 3) & 0x3ffff;
16098 write_insn (buf
, insn
);
16101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16102 _("PC-relative access out of range"));
16105 case BFD_RELOC_MIPS_19_PCREL_S2
:
16106 if ((*valP
& 0x3) != 0)
16107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16108 _("PC-relative access to misaligned address (%lx)"),
16110 if (!fixP
->fx_done
)
16113 if (*valP
+ 0x100000 <= 0x1fffff)
16115 insn
= read_insn (buf
);
16116 insn
|= (*valP
>> 2) & 0x7ffff;
16117 write_insn (buf
, insn
);
16120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16121 _("PC-relative access out of range"));
16124 case BFD_RELOC_16_PCREL_S2
:
16125 fix_validate_branch (fixP
, *valP
);
16127 /* We need to save the bits in the instruction since fixup_segment()
16128 might be deleting the relocation entry (i.e., a branch within
16129 the current segment). */
16130 if (! fixP
->fx_done
)
16133 /* Update old instruction data. */
16134 insn
= read_insn (buf
);
16136 if (*valP
+ 0x20000 <= 0x3ffff)
16138 insn
|= (*valP
>> 2) & 0xffff;
16139 write_insn (buf
, insn
);
16141 else if (fixP
->fx_tcbit2
16143 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16144 && (fixP
->fx_frag
->fr_address
16145 < text_section
->vma
+ bfd_section_size (text_section
))
16146 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16147 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16148 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16150 /* The branch offset is too large. If this is an
16151 unconditional branch, and we are not generating PIC code,
16152 we can convert it to an absolute jump instruction. */
16153 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16154 insn
= 0x0c000000; /* jal */
16156 insn
= 0x08000000; /* j */
16157 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16159 fixP
->fx_addsy
= section_symbol (text_section
);
16160 *valP
+= md_pcrel_from (fixP
);
16161 write_insn (buf
, insn
);
16165 /* If we got here, we have branch-relaxation disabled,
16166 and there's nothing we can do to fix this instruction
16167 without turning it into a longer sequence. */
16168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16169 _("branch out of range"));
16173 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16174 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16175 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16176 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16177 gas_assert (!fixP
->fx_done
);
16178 if (fix_bad_cross_mode_branch_p (fixP
))
16179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16180 _("branch to a symbol in another ISA mode"));
16181 else if (fixP
->fx_addsy
16182 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16183 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16184 && (fixP
->fx_offset
& 0x1) != 0)
16185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16186 _("branch to misaligned address (0x%lx)"),
16187 (long) fix_bad_misaligned_address (fixP
));
16188 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16190 _("cannot encode misaligned addend "
16191 "in the relocatable field (0x%lx)"),
16192 (long) fixP
->fx_offset
);
16195 case BFD_RELOC_VTABLE_INHERIT
:
16198 && !S_IS_DEFINED (fixP
->fx_addsy
)
16199 && !S_IS_WEAK (fixP
->fx_addsy
))
16200 S_SET_WEAK (fixP
->fx_addsy
);
16203 case BFD_RELOC_NONE
:
16204 case BFD_RELOC_VTABLE_ENTRY
:
16212 /* Remember value for tc_gen_reloc. */
16213 fixP
->fx_addnumber
= *valP
;
16223 c
= get_symbol_name (&name
);
16224 p
= (symbolS
*) symbol_find_or_make (name
);
16225 (void) restore_line_pointer (c
);
16229 /* Align the current frag to a given power of two. If a particular
16230 fill byte should be used, FILL points to an integer that contains
16231 that byte, otherwise FILL is null.
16233 This function used to have the comment:
16235 The MIPS assembler also automatically adjusts any preceding label.
16237 The implementation therefore applied the adjustment to a maximum of
16238 one label. However, other label adjustments are applied to batches
16239 of labels, and adjusting just one caused problems when new labels
16240 were added for the sake of debugging or unwind information.
16241 We therefore adjust all preceding labels (given as LABELS) instead. */
16244 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16246 mips_emit_delays ();
16247 mips_record_compressed_mode ();
16248 if (fill
== NULL
&& subseg_text_p (now_seg
))
16249 frag_align_code (to
, 0);
16251 frag_align (to
, fill
? *fill
: 0, 0);
16252 record_alignment (now_seg
, to
);
16253 mips_move_labels (labels
, subseg_text_p (now_seg
));
16256 /* Align to a given power of two. .align 0 turns off the automatic
16257 alignment used by the data creating pseudo-ops. */
16260 s_align (int x ATTRIBUTE_UNUSED
)
16262 int temp
, fill_value
, *fill_ptr
;
16263 long max_alignment
= 28;
16265 /* o Note that the assembler pulls down any immediately preceding label
16266 to the aligned address.
16267 o It's not documented but auto alignment is reinstated by
16268 a .align pseudo instruction.
16269 o Note also that after auto alignment is turned off the mips assembler
16270 issues an error on attempt to assemble an improperly aligned data item.
16273 temp
= get_absolute_expression ();
16274 if (temp
> max_alignment
)
16275 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16278 as_warn (_("alignment negative, 0 assumed"));
16281 if (*input_line_pointer
== ',')
16283 ++input_line_pointer
;
16284 fill_value
= get_absolute_expression ();
16285 fill_ptr
= &fill_value
;
16291 segment_info_type
*si
= seg_info (now_seg
);
16292 struct insn_label_list
*l
= si
->label_list
;
16293 /* Auto alignment should be switched on by next section change. */
16295 mips_align (temp
, fill_ptr
, l
);
16302 demand_empty_rest_of_line ();
16306 s_change_sec (int sec
)
16310 /* The ELF backend needs to know that we are changing sections, so
16311 that .previous works correctly. We could do something like check
16312 for an obj_section_change_hook macro, but that might be confusing
16313 as it would not be appropriate to use it in the section changing
16314 functions in read.c, since obj-elf.c intercepts those. FIXME:
16315 This should be cleaner, somehow. */
16316 obj_elf_section_change_hook ();
16318 mips_emit_delays ();
16329 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16330 demand_empty_rest_of_line ();
16334 seg
= subseg_new (RDATA_SECTION_NAME
,
16335 (subsegT
) get_absolute_expression ());
16336 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16337 | SEC_RELOC
| SEC_DATA
));
16338 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16339 record_alignment (seg
, 4);
16340 demand_empty_rest_of_line ();
16344 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16345 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
16346 | SEC_DATA
| SEC_SMALL_DATA
));
16347 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16348 record_alignment (seg
, 4);
16349 demand_empty_rest_of_line ();
16353 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16354 bfd_set_section_flags (seg
, SEC_ALLOC
| SEC_SMALL_DATA
);
16355 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16356 record_alignment (seg
, 4);
16357 demand_empty_rest_of_line ();
16365 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16368 char *section_name
;
16373 int section_entry_size
;
16374 int section_alignment
;
16376 saved_ilp
= input_line_pointer
;
16377 endc
= get_symbol_name (§ion_name
);
16378 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16380 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16382 /* Do we have .section Name<,"flags">? */
16383 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16385 /* Just after name is now '\0'. */
16386 (void) restore_line_pointer (endc
);
16387 input_line_pointer
= saved_ilp
;
16388 obj_elf_section (ignore
);
16392 section_name
= xstrdup (section_name
);
16393 c
= restore_line_pointer (endc
);
16395 input_line_pointer
++;
16397 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16399 section_type
= get_absolute_expression ();
16403 if (*input_line_pointer
++ == ',')
16404 section_flag
= get_absolute_expression ();
16408 if (*input_line_pointer
++ == ',')
16409 section_entry_size
= get_absolute_expression ();
16411 section_entry_size
= 0;
16413 if (*input_line_pointer
++ == ',')
16414 section_alignment
= get_absolute_expression ();
16416 section_alignment
= 0;
16418 /* FIXME: really ignore? */
16419 (void) section_alignment
;
16421 /* When using the generic form of .section (as implemented by obj-elf.c),
16422 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16423 traditionally had to fall back on the more common @progbits instead.
16425 There's nothing really harmful in this, since bfd will correct
16426 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16427 means that, for backwards compatibility, the special_section entries
16428 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16430 Even so, we shouldn't force users of the MIPS .section syntax to
16431 incorrectly label the sections as SHT_PROGBITS. The best compromise
16432 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16433 generic type-checking code. */
16434 if (section_type
== SHT_MIPS_DWARF
)
16435 section_type
= SHT_PROGBITS
;
16437 obj_elf_change_section (section_name
, section_type
, section_flag
,
16438 section_entry_size
, 0, 0, 0);
16440 if (now_seg
->name
!= section_name
)
16441 free (section_name
);
16445 mips_enable_auto_align (void)
16451 s_cons (int log_size
)
16453 segment_info_type
*si
= seg_info (now_seg
);
16454 struct insn_label_list
*l
= si
->label_list
;
16456 mips_emit_delays ();
16457 if (log_size
> 0 && auto_align
)
16458 mips_align (log_size
, 0, l
);
16459 cons (1 << log_size
);
16460 mips_clear_insn_labels ();
16464 s_float_cons (int type
)
16466 segment_info_type
*si
= seg_info (now_seg
);
16467 struct insn_label_list
*l
= si
->label_list
;
16469 mips_emit_delays ();
16474 mips_align (3, 0, l
);
16476 mips_align (2, 0, l
);
16480 mips_clear_insn_labels ();
16483 /* Handle .globl. We need to override it because on Irix 5 you are
16486 where foo is an undefined symbol, to mean that foo should be
16487 considered to be the address of a function. */
16490 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16498 c
= get_symbol_name (&name
);
16499 symbolP
= symbol_find_or_make (name
);
16500 S_SET_EXTERNAL (symbolP
);
16502 *input_line_pointer
= c
;
16503 SKIP_WHITESPACE_AFTER_NAME ();
16505 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16506 && (*input_line_pointer
!= ','))
16511 c
= get_symbol_name (&secname
);
16512 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16514 as_bad (_("%s: no such section"), secname
);
16515 (void) restore_line_pointer (c
);
16517 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16518 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16521 c
= *input_line_pointer
;
16524 input_line_pointer
++;
16525 SKIP_WHITESPACE ();
16526 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16532 demand_empty_rest_of_line ();
16536 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16537 any undefined non-function symbol to STT_OBJECT. We try to be
16538 compatible, since newer Irix 5 and 6 linkers care. */
16541 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16543 /* This late in assembly we can set BSF_OBJECT indiscriminately
16544 and let elf.c:swap_out_syms sort out the symbol type. */
16545 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16546 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16547 || !S_IS_DEFINED (symp
))
16548 *flags
|= BSF_OBJECT
;
16553 s_option (int x ATTRIBUTE_UNUSED
)
16558 c
= get_symbol_name (&opt
);
16562 /* FIXME: What does this mean? */
16564 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16568 i
= atoi (opt
+ 3);
16569 if (i
!= 0 && i
!= 2)
16570 as_bad (_(".option pic%d not supported"), i
);
16571 else if (mips_pic
== VXWORKS_PIC
)
16572 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16577 mips_pic
= SVR4_PIC
;
16578 mips_abicalls
= TRUE
;
16581 if (mips_pic
== SVR4_PIC
)
16583 if (g_switch_seen
&& g_switch_value
!= 0)
16584 as_warn (_("-G may not be used with SVR4 PIC code"));
16585 g_switch_value
= 0;
16586 bfd_set_gp_size (stdoutput
, 0);
16590 as_warn (_("unrecognized option \"%s\""), opt
);
16592 (void) restore_line_pointer (c
);
16593 demand_empty_rest_of_line ();
16596 /* This structure is used to hold a stack of .set values. */
16598 struct mips_option_stack
16600 struct mips_option_stack
*next
;
16601 struct mips_set_options options
;
16604 static struct mips_option_stack
*mips_opts_stack
;
16606 /* Return status for .set/.module option handling. */
16608 enum code_option_type
16610 /* Unrecognized option. */
16611 OPTION_TYPE_BAD
= -1,
16613 /* Ordinary option. */
16614 OPTION_TYPE_NORMAL
,
16616 /* ISA changing option. */
16620 /* Handle common .set/.module options. Return status indicating option
16623 static enum code_option_type
16624 parse_code_option (char * name
)
16626 bfd_boolean isa_set
= FALSE
;
16627 const struct mips_ase
*ase
;
16629 if (strncmp (name
, "at=", 3) == 0)
16631 char *s
= name
+ 3;
16633 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16634 as_bad (_("unrecognized register name `%s'"), s
);
16636 else if (strcmp (name
, "at") == 0)
16637 mips_opts
.at
= ATREG
;
16638 else if (strcmp (name
, "noat") == 0)
16639 mips_opts
.at
= ZERO
;
16640 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16641 mips_opts
.nomove
= 0;
16642 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16643 mips_opts
.nomove
= 1;
16644 else if (strcmp (name
, "bopt") == 0)
16645 mips_opts
.nobopt
= 0;
16646 else if (strcmp (name
, "nobopt") == 0)
16647 mips_opts
.nobopt
= 1;
16648 else if (strcmp (name
, "gp=32") == 0)
16650 else if (strcmp (name
, "gp=64") == 0)
16652 else if (strcmp (name
, "fp=32") == 0)
16654 else if (strcmp (name
, "fp=xx") == 0)
16656 else if (strcmp (name
, "fp=64") == 0)
16658 else if (strcmp (name
, "softfloat") == 0)
16659 mips_opts
.soft_float
= 1;
16660 else if (strcmp (name
, "hardfloat") == 0)
16661 mips_opts
.soft_float
= 0;
16662 else if (strcmp (name
, "singlefloat") == 0)
16663 mips_opts
.single_float
= 1;
16664 else if (strcmp (name
, "doublefloat") == 0)
16665 mips_opts
.single_float
= 0;
16666 else if (strcmp (name
, "nooddspreg") == 0)
16667 mips_opts
.oddspreg
= 0;
16668 else if (strcmp (name
, "oddspreg") == 0)
16669 mips_opts
.oddspreg
= 1;
16670 else if (strcmp (name
, "mips16") == 0
16671 || strcmp (name
, "MIPS-16") == 0)
16672 mips_opts
.mips16
= 1;
16673 else if (strcmp (name
, "nomips16") == 0
16674 || strcmp (name
, "noMIPS-16") == 0)
16675 mips_opts
.mips16
= 0;
16676 else if (strcmp (name
, "micromips") == 0)
16677 mips_opts
.micromips
= 1;
16678 else if (strcmp (name
, "nomicromips") == 0)
16679 mips_opts
.micromips
= 0;
16680 else if (name
[0] == 'n'
16682 && (ase
= mips_lookup_ase (name
+ 2)))
16683 mips_set_ase (ase
, &mips_opts
, FALSE
);
16684 else if ((ase
= mips_lookup_ase (name
)))
16685 mips_set_ase (ase
, &mips_opts
, TRUE
);
16686 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16688 /* Permit the user to change the ISA and architecture on the fly.
16689 Needless to say, misuse can cause serious problems. */
16690 if (strncmp (name
, "arch=", 5) == 0)
16692 const struct mips_cpu_info
*p
;
16694 p
= mips_parse_cpu ("internal use", name
+ 5);
16696 as_bad (_("unknown architecture %s"), name
+ 5);
16699 mips_opts
.arch
= p
->cpu
;
16700 mips_opts
.isa
= p
->isa
;
16702 mips_opts
.init_ase
= p
->ase
;
16705 else if (strncmp (name
, "mips", 4) == 0)
16707 const struct mips_cpu_info
*p
;
16709 p
= mips_parse_cpu ("internal use", name
);
16711 as_bad (_("unknown ISA level %s"), name
+ 4);
16714 mips_opts
.arch
= p
->cpu
;
16715 mips_opts
.isa
= p
->isa
;
16717 mips_opts
.init_ase
= p
->ase
;
16721 as_bad (_("unknown ISA or architecture %s"), name
);
16723 else if (strcmp (name
, "autoextend") == 0)
16724 mips_opts
.noautoextend
= 0;
16725 else if (strcmp (name
, "noautoextend") == 0)
16726 mips_opts
.noautoextend
= 1;
16727 else if (strcmp (name
, "insn32") == 0)
16728 mips_opts
.insn32
= TRUE
;
16729 else if (strcmp (name
, "noinsn32") == 0)
16730 mips_opts
.insn32
= FALSE
;
16731 else if (strcmp (name
, "sym32") == 0)
16732 mips_opts
.sym32
= TRUE
;
16733 else if (strcmp (name
, "nosym32") == 0)
16734 mips_opts
.sym32
= FALSE
;
16736 return OPTION_TYPE_BAD
;
16738 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16741 /* Handle the .set pseudo-op. */
16744 s_mipsset (int x ATTRIBUTE_UNUSED
)
16746 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16747 char *name
= input_line_pointer
, ch
;
16749 file_mips_check_options ();
16751 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16752 ++input_line_pointer
;
16753 ch
= *input_line_pointer
;
16754 *input_line_pointer
= '\0';
16756 if (strchr (name
, ','))
16758 /* Generic ".set" directive; use the generic handler. */
16759 *input_line_pointer
= ch
;
16760 input_line_pointer
= name
;
16765 if (strcmp (name
, "reorder") == 0)
16767 if (mips_opts
.noreorder
)
16770 else if (strcmp (name
, "noreorder") == 0)
16772 if (!mips_opts
.noreorder
)
16773 start_noreorder ();
16775 else if (strcmp (name
, "macro") == 0)
16776 mips_opts
.warn_about_macros
= 0;
16777 else if (strcmp (name
, "nomacro") == 0)
16779 if (mips_opts
.noreorder
== 0)
16780 as_bad (_("`noreorder' must be set before `nomacro'"));
16781 mips_opts
.warn_about_macros
= 1;
16783 else if (strcmp (name
, "gp=default") == 0)
16784 mips_opts
.gp
= file_mips_opts
.gp
;
16785 else if (strcmp (name
, "fp=default") == 0)
16786 mips_opts
.fp
= file_mips_opts
.fp
;
16787 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16789 mips_opts
.isa
= file_mips_opts
.isa
;
16790 mips_opts
.arch
= file_mips_opts
.arch
;
16791 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16792 mips_opts
.gp
= file_mips_opts
.gp
;
16793 mips_opts
.fp
= file_mips_opts
.fp
;
16795 else if (strcmp (name
, "push") == 0)
16797 struct mips_option_stack
*s
;
16799 s
= XNEW (struct mips_option_stack
);
16800 s
->next
= mips_opts_stack
;
16801 s
->options
= mips_opts
;
16802 mips_opts_stack
= s
;
16804 else if (strcmp (name
, "pop") == 0)
16806 struct mips_option_stack
*s
;
16808 s
= mips_opts_stack
;
16810 as_bad (_(".set pop with no .set push"));
16813 /* If we're changing the reorder mode we need to handle
16814 delay slots correctly. */
16815 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16816 start_noreorder ();
16817 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16820 mips_opts
= s
->options
;
16821 mips_opts_stack
= s
->next
;
16827 type
= parse_code_option (name
);
16828 if (type
== OPTION_TYPE_BAD
)
16829 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16832 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16833 registers based on what is supported by the arch/cpu. */
16834 if (type
== OPTION_TYPE_ISA
)
16836 switch (mips_opts
.isa
)
16841 /* MIPS I cannot support FPXX. */
16843 /* fall-through. */
16850 if (mips_opts
.fp
!= 0)
16866 if (mips_opts
.fp
!= 0)
16868 if (mips_opts
.arch
== CPU_R5900
)
16875 as_bad (_("unknown ISA level %s"), name
+ 4);
16880 mips_check_options (&mips_opts
, FALSE
);
16882 mips_check_isa_supports_ases ();
16883 *input_line_pointer
= ch
;
16884 demand_empty_rest_of_line ();
16887 /* Handle the .module pseudo-op. */
16890 s_module (int ignore ATTRIBUTE_UNUSED
)
16892 char *name
= input_line_pointer
, ch
;
16894 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16895 ++input_line_pointer
;
16896 ch
= *input_line_pointer
;
16897 *input_line_pointer
= '\0';
16899 if (!file_mips_opts_checked
)
16901 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16902 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16904 /* Update module level settings from mips_opts. */
16905 file_mips_opts
= mips_opts
;
16908 as_bad (_(".module is not permitted after generating code"));
16910 *input_line_pointer
= ch
;
16911 demand_empty_rest_of_line ();
16914 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16915 .option pic2. It means to generate SVR4 PIC calls. */
16918 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16920 mips_pic
= SVR4_PIC
;
16921 mips_abicalls
= TRUE
;
16923 if (g_switch_seen
&& g_switch_value
!= 0)
16924 as_warn (_("-G may not be used with SVR4 PIC code"));
16925 g_switch_value
= 0;
16927 bfd_set_gp_size (stdoutput
, 0);
16928 demand_empty_rest_of_line ();
16931 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16932 PIC code. It sets the $gp register for the function based on the
16933 function address, which is in the register named in the argument.
16934 This uses a relocation against _gp_disp, which is handled specially
16935 by the linker. The result is:
16936 lui $gp,%hi(_gp_disp)
16937 addiu $gp,$gp,%lo(_gp_disp)
16938 addu $gp,$gp,.cpload argument
16939 The .cpload argument is normally $25 == $t9.
16941 The -mno-shared option changes this to:
16942 lui $gp,%hi(__gnu_local_gp)
16943 addiu $gp,$gp,%lo(__gnu_local_gp)
16944 and the argument is ignored. This saves an instruction, but the
16945 resulting code is not position independent; it uses an absolute
16946 address for __gnu_local_gp. Thus code assembled with -mno-shared
16947 can go into an ordinary executable, but not into a shared library. */
16950 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16956 file_mips_check_options ();
16958 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16959 .cpload is ignored. */
16960 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16966 if (mips_opts
.mips16
)
16968 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16969 ignore_rest_of_line ();
16973 /* .cpload should be in a .set noreorder section. */
16974 if (mips_opts
.noreorder
== 0)
16975 as_warn (_(".cpload not in noreorder section"));
16977 reg
= tc_get_register (0);
16979 /* If we need to produce a 64-bit address, we are better off using
16980 the default instruction sequence. */
16981 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16983 ex
.X_op
= O_symbol
;
16984 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16986 ex
.X_op_symbol
= NULL
;
16987 ex
.X_add_number
= 0;
16989 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16990 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16992 mips_mark_labels ();
16993 mips_assembling_insn
= TRUE
;
16996 macro_build_lui (&ex
, mips_gp_register
);
16997 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16998 mips_gp_register
, BFD_RELOC_LO16
);
17000 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17001 mips_gp_register
, reg
);
17004 mips_assembling_insn
= FALSE
;
17005 demand_empty_rest_of_line ();
17008 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17009 .cpsetup $reg1, offset|$reg2, label
17011 If offset is given, this results in:
17012 sd $gp, offset($sp)
17013 lui $gp, %hi(%neg(%gp_rel(label)))
17014 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17015 daddu $gp, $gp, $reg1
17017 If $reg2 is given, this results in:
17019 lui $gp, %hi(%neg(%gp_rel(label)))
17020 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17021 daddu $gp, $gp, $reg1
17022 $reg1 is normally $25 == $t9.
17024 The -mno-shared option replaces the last three instructions with
17026 addiu $gp,$gp,%lo(_gp) */
17029 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17031 expressionS ex_off
;
17032 expressionS ex_sym
;
17035 file_mips_check_options ();
17037 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17038 We also need NewABI support. */
17039 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17045 if (mips_opts
.mips16
)
17047 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17048 ignore_rest_of_line ();
17052 reg1
= tc_get_register (0);
17053 SKIP_WHITESPACE ();
17054 if (*input_line_pointer
!= ',')
17056 as_bad (_("missing argument separator ',' for .cpsetup"));
17060 ++input_line_pointer
;
17061 SKIP_WHITESPACE ();
17062 if (*input_line_pointer
== '$')
17064 mips_cpreturn_register
= tc_get_register (0);
17065 mips_cpreturn_offset
= -1;
17069 mips_cpreturn_offset
= get_absolute_expression ();
17070 mips_cpreturn_register
= -1;
17072 SKIP_WHITESPACE ();
17073 if (*input_line_pointer
!= ',')
17075 as_bad (_("missing argument separator ',' for .cpsetup"));
17079 ++input_line_pointer
;
17080 SKIP_WHITESPACE ();
17081 expression (&ex_sym
);
17083 mips_mark_labels ();
17084 mips_assembling_insn
= TRUE
;
17087 if (mips_cpreturn_register
== -1)
17089 ex_off
.X_op
= O_constant
;
17090 ex_off
.X_add_symbol
= NULL
;
17091 ex_off
.X_op_symbol
= NULL
;
17092 ex_off
.X_add_number
= mips_cpreturn_offset
;
17094 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17095 BFD_RELOC_LO16
, SP
);
17098 move_register (mips_cpreturn_register
, mips_gp_register
);
17100 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17102 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17103 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17106 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17107 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17108 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17111 mips_gp_register
, reg1
);
17117 ex
.X_op
= O_symbol
;
17118 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17119 ex
.X_op_symbol
= NULL
;
17120 ex
.X_add_number
= 0;
17122 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17123 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17125 macro_build_lui (&ex
, mips_gp_register
);
17126 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17127 mips_gp_register
, BFD_RELOC_LO16
);
17132 mips_assembling_insn
= FALSE
;
17133 demand_empty_rest_of_line ();
17137 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17139 file_mips_check_options ();
17141 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17142 .cplocal is ignored. */
17143 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17149 if (mips_opts
.mips16
)
17151 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17152 ignore_rest_of_line ();
17156 mips_gp_register
= tc_get_register (0);
17157 demand_empty_rest_of_line ();
17160 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17161 offset from $sp. The offset is remembered, and after making a PIC
17162 call $gp is restored from that location. */
17165 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17169 file_mips_check_options ();
17171 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17172 .cprestore is ignored. */
17173 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17179 if (mips_opts
.mips16
)
17181 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17182 ignore_rest_of_line ();
17186 mips_cprestore_offset
= get_absolute_expression ();
17187 mips_cprestore_valid
= 1;
17189 ex
.X_op
= O_constant
;
17190 ex
.X_add_symbol
= NULL
;
17191 ex
.X_op_symbol
= NULL
;
17192 ex
.X_add_number
= mips_cprestore_offset
;
17194 mips_mark_labels ();
17195 mips_assembling_insn
= TRUE
;
17198 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17199 SP
, HAVE_64BIT_ADDRESSES
);
17202 mips_assembling_insn
= FALSE
;
17203 demand_empty_rest_of_line ();
17206 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17207 was given in the preceding .cpsetup, it results in:
17208 ld $gp, offset($sp)
17210 If a register $reg2 was given there, it results in:
17211 or $gp, $reg2, $0 */
17214 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17218 file_mips_check_options ();
17220 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17221 We also need NewABI support. */
17222 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17228 if (mips_opts
.mips16
)
17230 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17231 ignore_rest_of_line ();
17235 mips_mark_labels ();
17236 mips_assembling_insn
= TRUE
;
17239 if (mips_cpreturn_register
== -1)
17241 ex
.X_op
= O_constant
;
17242 ex
.X_add_symbol
= NULL
;
17243 ex
.X_op_symbol
= NULL
;
17244 ex
.X_add_number
= mips_cpreturn_offset
;
17246 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17249 move_register (mips_gp_register
, mips_cpreturn_register
);
17253 mips_assembling_insn
= FALSE
;
17254 demand_empty_rest_of_line ();
17257 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17258 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17259 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17260 debug information or MIPS16 TLS. */
17263 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17264 bfd_reloc_code_real_type rtype
)
17271 if (ex
.X_op
!= O_symbol
)
17273 as_bad (_("unsupported use of %s"), dirstr
);
17274 ignore_rest_of_line ();
17277 p
= frag_more (bytes
);
17278 md_number_to_chars (p
, 0, bytes
);
17279 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17280 demand_empty_rest_of_line ();
17281 mips_clear_insn_labels ();
17284 /* Handle .dtprelword. */
17287 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17289 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17292 /* Handle .dtpreldword. */
17295 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17297 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17300 /* Handle .tprelword. */
17303 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17305 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17308 /* Handle .tpreldword. */
17311 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17313 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17316 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17317 code. It sets the offset to use in gp_rel relocations. */
17320 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17322 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17323 We also need NewABI support. */
17324 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17330 mips_gprel_offset
= get_absolute_expression ();
17332 demand_empty_rest_of_line ();
17335 /* Handle the .gpword pseudo-op. This is used when generating PIC
17336 code. It generates a 32 bit GP relative reloc. */
17339 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17341 segment_info_type
*si
;
17342 struct insn_label_list
*l
;
17346 /* When not generating PIC code, this is treated as .word. */
17347 if (mips_pic
!= SVR4_PIC
)
17353 si
= seg_info (now_seg
);
17354 l
= si
->label_list
;
17355 mips_emit_delays ();
17357 mips_align (2, 0, l
);
17360 mips_clear_insn_labels ();
17362 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17364 as_bad (_("unsupported use of .gpword"));
17365 ignore_rest_of_line ();
17369 md_number_to_chars (p
, 0, 4);
17370 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17371 BFD_RELOC_GPREL32
);
17373 demand_empty_rest_of_line ();
17377 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17379 segment_info_type
*si
;
17380 struct insn_label_list
*l
;
17384 /* When not generating PIC code, this is treated as .dword. */
17385 if (mips_pic
!= SVR4_PIC
)
17391 si
= seg_info (now_seg
);
17392 l
= si
->label_list
;
17393 mips_emit_delays ();
17395 mips_align (3, 0, l
);
17398 mips_clear_insn_labels ();
17400 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17402 as_bad (_("unsupported use of .gpdword"));
17403 ignore_rest_of_line ();
17407 md_number_to_chars (p
, 0, 8);
17408 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17409 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17411 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17412 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17413 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17415 demand_empty_rest_of_line ();
17418 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17419 tables. It generates a R_MIPS_EH reloc. */
17422 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17427 mips_emit_delays ();
17430 mips_clear_insn_labels ();
17432 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17434 as_bad (_("unsupported use of .ehword"));
17435 ignore_rest_of_line ();
17439 md_number_to_chars (p
, 0, 4);
17440 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17441 BFD_RELOC_32_PCREL
);
17443 demand_empty_rest_of_line ();
17446 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17447 tables in SVR4 PIC code. */
17450 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17454 file_mips_check_options ();
17456 /* This is ignored when not generating SVR4 PIC code. */
17457 if (mips_pic
!= SVR4_PIC
)
17463 mips_mark_labels ();
17464 mips_assembling_insn
= TRUE
;
17466 /* Add $gp to the register named as an argument. */
17468 reg
= tc_get_register (0);
17469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17472 mips_assembling_insn
= FALSE
;
17473 demand_empty_rest_of_line ();
17476 /* Handle the .insn pseudo-op. This marks instruction labels in
17477 mips16/micromips mode. This permits the linker to handle them specially,
17478 such as generating jalx instructions when needed. We also make
17479 them odd for the duration of the assembly, in order to generate the
17480 right sort of code. We will make them even in the adjust_symtab
17481 routine, while leaving them marked. This is convenient for the
17482 debugger and the disassembler. The linker knows to make them odd
17486 s_insn (int ignore ATTRIBUTE_UNUSED
)
17488 file_mips_check_options ();
17489 file_ase_mips16
|= mips_opts
.mips16
;
17490 file_ase_micromips
|= mips_opts
.micromips
;
17492 mips_mark_labels ();
17494 demand_empty_rest_of_line ();
17497 /* Handle the .nan pseudo-op. */
17500 s_nan (int ignore ATTRIBUTE_UNUSED
)
17502 static const char str_legacy
[] = "legacy";
17503 static const char str_2008
[] = "2008";
17506 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17508 if (i
== sizeof (str_2008
) - 1
17509 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17511 else if (i
== sizeof (str_legacy
) - 1
17512 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17514 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17517 as_bad (_("`%s' does not support legacy NaN"),
17518 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17521 as_bad (_("bad .nan directive"));
17523 input_line_pointer
+= i
;
17524 demand_empty_rest_of_line ();
17527 /* Handle a .stab[snd] directive. Ideally these directives would be
17528 implemented in a transparent way, so that removing them would not
17529 have any effect on the generated instructions. However, s_stab
17530 internally changes the section, so in practice we need to decide
17531 now whether the preceding label marks compressed code. We do not
17532 support changing the compression mode of a label after a .stab*
17533 directive, such as in:
17539 so the current mode wins. */
17542 s_mips_stab (int type
)
17544 file_mips_check_options ();
17545 mips_mark_labels ();
17549 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17552 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17559 c
= get_symbol_name (&name
);
17560 symbolP
= symbol_find_or_make (name
);
17561 S_SET_WEAK (symbolP
);
17562 *input_line_pointer
= c
;
17564 SKIP_WHITESPACE_AFTER_NAME ();
17566 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17568 if (S_IS_DEFINED (symbolP
))
17570 as_bad (_("ignoring attempt to redefine symbol %s"),
17571 S_GET_NAME (symbolP
));
17572 ignore_rest_of_line ();
17576 if (*input_line_pointer
== ',')
17578 ++input_line_pointer
;
17579 SKIP_WHITESPACE ();
17583 if (exp
.X_op
!= O_symbol
)
17585 as_bad (_("bad .weakext directive"));
17586 ignore_rest_of_line ();
17589 symbol_set_value_expression (symbolP
, &exp
);
17592 demand_empty_rest_of_line ();
17595 /* Parse a register string into a number. Called from the ECOFF code
17596 to parse .frame. The argument is non-zero if this is the frame
17597 register, so that we can record it in mips_frame_reg. */
17600 tc_get_register (int frame
)
17604 SKIP_WHITESPACE ();
17605 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17609 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17610 mips_frame_reg_valid
= 1;
17611 mips_cprestore_valid
= 0;
17617 md_section_align (asection
*seg
, valueT addr
)
17619 int align
= bfd_section_alignment (seg
);
17621 /* We don't need to align ELF sections to the full alignment.
17622 However, Irix 5 may prefer that we align them at least to a 16
17623 byte boundary. We don't bother to align the sections if we
17624 are targeted for an embedded system. */
17625 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17630 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17633 /* Utility routine, called from above as well. If called while the
17634 input file is still being read, it's only an approximation. (For
17635 example, a symbol may later become defined which appeared to be
17636 undefined earlier.) */
17639 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17644 if (g_switch_value
> 0)
17646 const char *symname
;
17649 /* Find out whether this symbol can be referenced off the $gp
17650 register. It can be if it is smaller than the -G size or if
17651 it is in the .sdata or .sbss section. Certain symbols can
17652 not be referenced off the $gp, although it appears as though
17654 symname
= S_GET_NAME (sym
);
17655 if (symname
!= (const char *) NULL
17656 && (strcmp (symname
, "eprol") == 0
17657 || strcmp (symname
, "etext") == 0
17658 || strcmp (symname
, "_gp") == 0
17659 || strcmp (symname
, "edata") == 0
17660 || strcmp (symname
, "_fbss") == 0
17661 || strcmp (symname
, "_fdata") == 0
17662 || strcmp (symname
, "_ftext") == 0
17663 || strcmp (symname
, "end") == 0
17664 || strcmp (symname
, "_gp_disp") == 0))
17666 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17668 #ifndef NO_ECOFF_DEBUGGING
17669 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17670 && (symbol_get_obj (sym
)->ecoff_extern_size
17671 <= g_switch_value
))
17673 /* We must defer this decision until after the whole
17674 file has been read, since there might be a .extern
17675 after the first use of this symbol. */
17676 || (before_relaxing
17677 #ifndef NO_ECOFF_DEBUGGING
17678 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17680 && S_GET_VALUE (sym
) == 0)
17681 || (S_GET_VALUE (sym
) != 0
17682 && S_GET_VALUE (sym
) <= g_switch_value
)))
17686 const char *segname
;
17688 segname
= segment_name (S_GET_SEGMENT (sym
));
17689 gas_assert (strcmp (segname
, ".lit8") != 0
17690 && strcmp (segname
, ".lit4") != 0);
17691 change
= (strcmp (segname
, ".sdata") != 0
17692 && strcmp (segname
, ".sbss") != 0
17693 && strncmp (segname
, ".sdata.", 7) != 0
17694 && strncmp (segname
, ".sbss.", 6) != 0
17695 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17696 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17701 /* We are not optimizing for the $gp register. */
17706 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17709 pic_need_relax (symbolS
*sym
)
17713 /* Handle the case of a symbol equated to another symbol. */
17714 while (symbol_equated_reloc_p (sym
))
17718 /* It's possible to get a loop here in a badly written program. */
17719 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17725 if (symbol_section_p (sym
))
17728 symsec
= S_GET_SEGMENT (sym
);
17730 /* This must duplicate the test in adjust_reloc_syms. */
17731 return (!bfd_is_und_section (symsec
)
17732 && !bfd_is_abs_section (symsec
)
17733 && !bfd_is_com_section (symsec
)
17734 /* A global or weak symbol is treated as external. */
17735 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17738 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17739 convert a section-relative value VAL to the equivalent PC-relative
17743 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17744 offsetT val
, long stretch
)
17749 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17751 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17753 /* If the relax_marker of the symbol fragment differs from the
17754 relax_marker of this fragment, we have not yet adjusted the
17755 symbol fragment fr_address. We want to add in STRETCH in
17756 order to get a better estimate of the address. This
17757 particularly matters because of the shift bits. */
17758 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17762 /* Adjust stretch for any alignment frag. Note that if have
17763 been expanding the earlier code, the symbol may be
17764 defined in what appears to be an earlier frag. FIXME:
17765 This doesn't handle the fr_subtype field, which specifies
17766 a maximum number of bytes to skip when doing an
17768 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17770 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17773 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17775 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17784 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17786 /* The base address rules are complicated. The base address of
17787 a branch is the following instruction. The base address of a
17788 PC relative load or add is the instruction itself, but if it
17789 is in a delay slot (in which case it can not be extended) use
17790 the address of the instruction whose delay slot it is in. */
17791 if (pcrel_op
->include_isa_bit
)
17795 /* If we are currently assuming that this frag should be
17796 extended, then the current address is two bytes higher. */
17797 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17800 /* Ignore the low bit in the target, since it will be set
17801 for a text label. */
17804 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17806 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17809 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17814 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17815 extended opcode. SEC is the section the frag is in. */
17818 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17820 const struct mips_int_operand
*operand
;
17825 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17827 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17830 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17831 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17832 operand
= mips16_immed_operand (type
, FALSE
);
17833 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17834 || (operand
->root
.type
== OP_PCREL
17836 : !bfd_is_abs_section (symsec
)))
17839 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17841 if (operand
->root
.type
== OP_PCREL
)
17843 const struct mips_pcrel_operand
*pcrel_op
;
17846 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17849 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17850 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17852 /* If any of the shifted bits are set, we must use an extended
17853 opcode. If the address depends on the size of this
17854 instruction, this can lead to a loop, so we arrange to always
17855 use an extended opcode. */
17856 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17858 fragp
->fr_subtype
=
17859 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17863 /* If we are about to mark a frag as extended because the value
17864 is precisely the next value above maxtiny, then there is a
17865 chance of an infinite loop as in the following code:
17870 In this case when the la is extended, foo is 0x3fc bytes
17871 away, so the la can be shrunk, but then foo is 0x400 away, so
17872 the la must be extended. To avoid this loop, we mark the
17873 frag as extended if it was small, and is about to become
17874 extended with the next value above maxtiny. */
17875 maxtiny
= mips_int_operand_max (operand
);
17876 if (val
== maxtiny
+ (1 << operand
->shift
)
17877 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17879 fragp
->fr_subtype
=
17880 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17885 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17888 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17889 macro expansion. SEC is the section the frag is in. We only
17890 support PC-relative instructions (LA, DLA, LW, LD) here, in
17891 non-PIC code using 32-bit addressing. */
17894 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17896 const struct mips_pcrel_operand
*pcrel_op
;
17897 const struct mips_int_operand
*operand
;
17902 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17904 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17906 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17909 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17915 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17916 if (bfd_is_abs_section (symsec
))
17918 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17920 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17923 operand
= mips16_immed_operand (type
, TRUE
);
17924 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17925 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17926 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17928 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17935 /* Compute the length of a branch sequence, and adjust the
17936 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17937 worst-case length is computed, with UPDATE being used to indicate
17938 whether an unconditional (-1), branch-likely (+1) or regular (0)
17939 branch is to be computed. */
17941 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17943 bfd_boolean toofar
;
17947 && S_IS_DEFINED (fragp
->fr_symbol
)
17948 && !S_IS_WEAK (fragp
->fr_symbol
)
17949 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17954 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17956 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17960 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17963 /* If the symbol is not defined or it's in a different segment,
17964 we emit the long sequence. */
17967 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17969 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17970 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17971 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17972 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17973 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17979 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17982 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17984 /* Additional space for PIC loading of target address. */
17986 if (mips_opts
.isa
== ISA_MIPS1
)
17987 /* Additional space for $at-stabilizing nop. */
17991 /* If branch is conditional. */
17992 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17999 /* Get a FRAG's branch instruction delay slot size, either from the
18000 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18001 or SHORT_INSN_SIZE otherwise. */
18004 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
18006 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18009 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
18011 return short_insn_size
;
18014 /* Compute the length of a branch sequence, and adjust the
18015 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18016 worst-case length is computed, with UPDATE being used to indicate
18017 whether an unconditional (-1), or regular (0) branch is to be
18021 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18023 bfd_boolean insn32
= TRUE
;
18024 bfd_boolean nods
= TRUE
;
18025 bfd_boolean pic
= TRUE
;
18026 bfd_boolean al
= TRUE
;
18027 int short_insn_size
;
18028 bfd_boolean toofar
;
18033 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18034 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18035 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18036 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18038 short_insn_size
= insn32
? 4 : 2;
18041 && S_IS_DEFINED (fragp
->fr_symbol
)
18042 && !S_IS_WEAK (fragp
->fr_symbol
)
18043 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18048 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18049 /* Ignore the low bit in the target, since it will be set
18050 for a text label. */
18051 if ((val
& 1) != 0)
18054 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18058 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18061 /* If the symbol is not defined or it's in a different segment,
18062 we emit the long sequence. */
18065 if (fragp
&& update
18066 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18067 fragp
->fr_subtype
= (toofar
18068 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18069 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18074 bfd_boolean compact_known
= fragp
!= NULL
;
18075 bfd_boolean compact
= FALSE
;
18076 bfd_boolean uncond
;
18080 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18081 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18084 uncond
= update
< 0;
18086 /* If label is out of range, we turn branch <br>:
18088 <br> label # 4 bytes
18095 # compact && (!PIC || insn32)
18098 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18099 length
+= short_insn_size
;
18101 /* If assembling PIC code, we further turn:
18107 lw/ld at, %got(label)(gp) # 4 bytes
18108 d/addiu at, %lo(label) # 4 bytes
18109 jr/c at # 2/4 bytes
18112 length
+= 4 + short_insn_size
;
18114 /* Add an extra nop if the jump has no compact form and we need
18115 to fill the delay slot. */
18116 if ((!pic
|| al
) && nods
)
18118 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18119 : short_insn_size
);
18121 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18123 <brneg> 0f # 4 bytes
18124 nop # 2/4 bytes if !compact
18127 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18131 /* Add an extra nop to fill the delay slot. */
18132 gas_assert (fragp
);
18133 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18139 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18140 bit accordingly. */
18143 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18145 bfd_boolean toofar
;
18148 && S_IS_DEFINED (fragp
->fr_symbol
)
18149 && !S_IS_WEAK (fragp
->fr_symbol
)
18150 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18156 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18157 /* Ignore the low bit in the target, since it will be set
18158 for a text label. */
18159 if ((val
& 1) != 0)
18162 /* Assume this is a 2-byte branch. */
18163 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18165 /* We try to avoid the infinite loop by not adding 2 more bytes for
18170 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18172 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18173 else if (type
== 'E')
18174 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18179 /* If the symbol is not defined or it's in a different segment,
18180 we emit a normal 32-bit branch. */
18183 if (fragp
&& update
18184 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18186 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18187 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18195 /* Estimate the size of a frag before relaxing. Unless this is the
18196 mips16, we are not really relaxing here, and the final size is
18197 encoded in the subtype information. For the mips16, we have to
18198 decide whether we are using an extended opcode or not. */
18201 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18205 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18208 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18210 return fragp
->fr_var
;
18213 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18215 /* We don't want to modify the EXTENDED bit here; it might get us
18216 into infinite loops. We change it only in mips_relax_frag(). */
18217 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18218 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18220 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18223 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18227 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18228 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18229 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18230 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18231 fragp
->fr_var
= length
;
18236 if (mips_pic
== VXWORKS_PIC
)
18237 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18239 else if (RELAX_PIC (fragp
->fr_subtype
))
18240 change
= pic_need_relax (fragp
->fr_symbol
);
18242 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18246 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18247 return -RELAX_FIRST (fragp
->fr_subtype
);
18250 return -RELAX_SECOND (fragp
->fr_subtype
);
18253 /* This is called to see whether a reloc against a defined symbol
18254 should be converted into a reloc against a section. */
18257 mips_fix_adjustable (fixS
*fixp
)
18259 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18260 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18263 if (fixp
->fx_addsy
== NULL
)
18266 /* Allow relocs used for EH tables. */
18267 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18270 /* If symbol SYM is in a mergeable section, relocations of the form
18271 SYM + 0 can usually be made section-relative. The mergeable data
18272 is then identified by the section offset rather than by the symbol.
18274 However, if we're generating REL LO16 relocations, the offset is split
18275 between the LO16 and partnering high part relocation. The linker will
18276 need to recalculate the complete offset in order to correctly identify
18279 The linker has traditionally not looked for the partnering high part
18280 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18281 placed anywhere. Rather than break backwards compatibility by changing
18282 this, it seems better not to force the issue, and instead keep the
18283 original symbol. This will work with either linker behavior. */
18284 if ((lo16_reloc_p (fixp
->fx_r_type
)
18285 || reloc_needs_lo_p (fixp
->fx_r_type
))
18286 && HAVE_IN_PLACE_ADDENDS
18287 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18290 /* There is no place to store an in-place offset for JALR relocations. */
18291 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18294 /* Likewise an in-range offset of limited PC-relative relocations may
18295 overflow the in-place relocatable field if recalculated against the
18296 start address of the symbol's containing section.
18298 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18299 section relative to allow linker relaxations to be performed later on. */
18300 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18301 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18304 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18305 to a floating-point stub. The same is true for non-R_MIPS16_26
18306 relocations against MIPS16 functions; in this case, the stub becomes
18307 the function's canonical address.
18309 Floating-point stubs are stored in unique .mips16.call.* or
18310 .mips16.fn.* sections. If a stub T for function F is in section S,
18311 the first relocation in section S must be against F; this is how the
18312 linker determines the target function. All relocations that might
18313 resolve to T must also be against F. We therefore have the following
18314 restrictions, which are given in an intentionally-redundant way:
18316 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18319 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18320 if that stub might be used.
18322 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18325 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18326 that stub might be used.
18328 There is a further restriction:
18330 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18331 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18332 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18333 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18334 against MIPS16 or microMIPS symbols because we need to keep the
18335 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18336 detection and JAL or BAL to JALX instruction conversion in the
18339 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18340 against a MIPS16 symbol. We deal with (5) by additionally leaving
18341 alone any jump and branch relocations against a microMIPS symbol.
18343 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18344 relocation against some symbol R, no relocation against R may be
18345 reduced. (Note that this deals with (2) as well as (1) because
18346 relocations against global symbols will never be reduced on ELF
18347 targets.) This approach is a little simpler than trying to detect
18348 stub sections, and gives the "all or nothing" per-symbol consistency
18349 that we have for MIPS16 symbols. */
18350 if (fixp
->fx_subsy
== NULL
18351 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18352 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18353 && (jmp_reloc_p (fixp
->fx_r_type
)
18354 || b_reloc_p (fixp
->fx_r_type
)))
18355 || *symbol_get_tc (fixp
->fx_addsy
)))
18361 /* Translate internal representation of relocation info to BFD target
18365 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18367 static arelent
*retval
[4];
18369 bfd_reloc_code_real_type code
;
18371 memset (retval
, 0, sizeof(retval
));
18372 reloc
= retval
[0] = XCNEW (arelent
);
18373 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18374 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18375 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18377 if (fixp
->fx_pcrel
)
18379 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18380 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18381 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18382 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18383 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18384 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18385 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18386 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18387 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18388 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18389 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18390 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18392 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18393 Relocations want only the symbol offset. */
18394 switch (fixp
->fx_r_type
)
18396 case BFD_RELOC_MIPS_18_PCREL_S3
:
18397 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18400 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18404 else if (HAVE_IN_PLACE_ADDENDS
18405 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18406 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18407 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18409 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18410 addend accordingly. */
18411 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18414 reloc
->addend
= fixp
->fx_addnumber
;
18416 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18417 entry to be used in the relocation's section offset. */
18418 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18420 reloc
->address
= reloc
->addend
;
18424 code
= fixp
->fx_r_type
;
18426 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18427 if (reloc
->howto
== NULL
)
18429 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18430 _("cannot represent %s relocation in this object file"
18432 bfd_get_reloc_code_name (code
));
18439 /* Relax a machine dependent frag. This returns the amount by which
18440 the current size of the frag should change. */
18443 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18445 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18447 offsetT old_var
= fragp
->fr_var
;
18449 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18451 return fragp
->fr_var
- old_var
;
18454 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18456 offsetT old_var
= fragp
->fr_var
;
18457 offsetT new_var
= 4;
18459 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18460 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18461 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18462 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18463 fragp
->fr_var
= new_var
;
18465 return new_var
- old_var
;
18468 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18471 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18473 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18475 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18476 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18478 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18480 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18486 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18488 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18490 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18491 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18492 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18494 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18496 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18504 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18506 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18508 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18509 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18510 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18514 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18515 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18522 /* Convert a machine dependent frag. */
18525 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18527 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18530 unsigned long insn
;
18533 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18534 insn
= read_insn (buf
);
18536 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18538 /* We generate a fixup instead of applying it right now
18539 because, if there are linker relaxations, we're going to
18540 need the relocations. */
18541 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18542 fragp
->fr_symbol
, fragp
->fr_offset
,
18543 TRUE
, BFD_RELOC_16_PCREL_S2
);
18544 fixp
->fx_file
= fragp
->fr_file
;
18545 fixp
->fx_line
= fragp
->fr_line
;
18547 buf
= write_insn (buf
, insn
);
18553 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18554 _("relaxed out-of-range branch into a jump"));
18556 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18559 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18561 /* Reverse the branch. */
18562 switch ((insn
>> 28) & 0xf)
18565 if ((insn
& 0xff000000) == 0x47000000
18566 || (insn
& 0xff600000) == 0x45600000)
18568 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18569 reversed by tweaking bit 23. */
18570 insn
^= 0x00800000;
18574 /* bc[0-3][tf]l? instructions can have the condition
18575 reversed by tweaking a single TF bit, and their
18576 opcodes all have 0x4???????. */
18577 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18578 insn
^= 0x00010000;
18583 /* bltz 0x04000000 bgez 0x04010000
18584 bltzal 0x04100000 bgezal 0x04110000 */
18585 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18586 insn
^= 0x00010000;
18590 /* beq 0x10000000 bne 0x14000000
18591 blez 0x18000000 bgtz 0x1c000000 */
18592 insn
^= 0x04000000;
18600 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18602 /* Clear the and-link bit. */
18603 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18605 /* bltzal 0x04100000 bgezal 0x04110000
18606 bltzall 0x04120000 bgezall 0x04130000 */
18607 insn
&= ~0x00100000;
18610 /* Branch over the branch (if the branch was likely) or the
18611 full jump (not likely case). Compute the offset from the
18612 current instruction to branch to. */
18613 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18617 /* How many bytes in instructions we've already emitted? */
18618 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18619 /* How many bytes in instructions from here to the end? */
18620 i
= fragp
->fr_var
- i
;
18622 /* Convert to instruction count. */
18624 /* Branch counts from the next instruction. */
18627 /* Branch over the jump. */
18628 buf
= write_insn (buf
, insn
);
18631 buf
= write_insn (buf
, 0);
18633 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18635 /* beql $0, $0, 2f */
18637 /* Compute the PC offset from the current instruction to
18638 the end of the variable frag. */
18639 /* How many bytes in instructions we've already emitted? */
18640 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18641 /* How many bytes in instructions from here to the end? */
18642 i
= fragp
->fr_var
- i
;
18643 /* Convert to instruction count. */
18645 /* Don't decrement i, because we want to branch over the
18649 buf
= write_insn (buf
, insn
);
18650 buf
= write_insn (buf
, 0);
18654 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18657 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18658 ? 0x0c000000 : 0x08000000);
18660 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18661 fragp
->fr_symbol
, fragp
->fr_offset
,
18662 FALSE
, BFD_RELOC_MIPS_JMP
);
18663 fixp
->fx_file
= fragp
->fr_file
;
18664 fixp
->fx_line
= fragp
->fr_line
;
18666 buf
= write_insn (buf
, insn
);
18670 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18672 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18673 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18674 insn
|= at
<< OP_SH_RT
;
18676 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18677 fragp
->fr_symbol
, fragp
->fr_offset
,
18678 FALSE
, BFD_RELOC_MIPS_GOT16
);
18679 fixp
->fx_file
= fragp
->fr_file
;
18680 fixp
->fx_line
= fragp
->fr_line
;
18682 buf
= write_insn (buf
, insn
);
18684 if (mips_opts
.isa
== ISA_MIPS1
)
18686 buf
= write_insn (buf
, 0);
18688 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18689 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18690 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18692 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18693 fragp
->fr_symbol
, fragp
->fr_offset
,
18694 FALSE
, BFD_RELOC_LO16
);
18695 fixp
->fx_file
= fragp
->fr_file
;
18696 fixp
->fx_line
= fragp
->fr_line
;
18698 buf
= write_insn (buf
, insn
);
18701 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18705 insn
|= at
<< OP_SH_RS
;
18707 buf
= write_insn (buf
, insn
);
18711 fragp
->fr_fix
+= fragp
->fr_var
;
18712 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18716 /* Relax microMIPS branches. */
18717 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18719 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18720 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18721 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18722 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18723 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18724 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18725 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18726 bfd_boolean short_ds
;
18727 unsigned long insn
;
18730 fragp
->fr_fix
+= fragp
->fr_var
;
18732 /* Handle 16-bit branches that fit or are forced to fit. */
18733 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18735 /* We generate a fixup instead of applying it right now,
18736 because if there is linker relaxation, we're going to
18737 need the relocations. */
18741 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18742 fragp
->fr_symbol
, fragp
->fr_offset
,
18743 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18746 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18747 fragp
->fr_symbol
, fragp
->fr_offset
,
18748 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18754 fixp
->fx_file
= fragp
->fr_file
;
18755 fixp
->fx_line
= fragp
->fr_line
;
18757 /* These relocations can have an addend that won't fit in
18759 fixp
->fx_no_overflow
= 1;
18764 /* Handle 32-bit branches that fit or are forced to fit. */
18765 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18766 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18768 /* We generate a fixup instead of applying it right now,
18769 because if there is linker relaxation, we're going to
18770 need the relocations. */
18771 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18772 fragp
->fr_symbol
, fragp
->fr_offset
,
18773 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18774 fixp
->fx_file
= fragp
->fr_file
;
18775 fixp
->fx_line
= fragp
->fr_line
;
18779 insn
= read_compressed_insn (buf
, 4);
18784 /* Check the short-delay-slot bit. */
18785 if (!al
|| (insn
& 0x02000000) != 0)
18786 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18788 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18791 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18796 /* Relax 16-bit branches to 32-bit branches. */
18799 insn
= read_compressed_insn (buf
, 2);
18801 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18802 insn
= 0x94000000; /* beq */
18803 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18805 unsigned long regno
;
18807 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18808 regno
= micromips_to_32_reg_d_map
[regno
];
18809 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18810 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18815 /* Nothing else to do, just write it out. */
18816 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18817 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18819 buf
= write_compressed_insn (buf
, insn
, 4);
18821 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18822 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18827 insn
= read_compressed_insn (buf
, 4);
18829 /* Relax 32-bit branches to a sequence of instructions. */
18830 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18831 _("relaxed out-of-range branch into a jump"));
18833 /* Set the short-delay-slot bit. */
18834 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18836 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18840 /* Reverse the branch. */
18841 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18842 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18843 insn
^= 0x20000000;
18844 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18845 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18846 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18847 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18848 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18849 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18850 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18851 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18852 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18853 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18854 insn
^= 0x00400000;
18855 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18856 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18857 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18858 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18859 insn
^= 0x00200000;
18860 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18862 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18864 insn
^= 0x00800000;
18870 /* Clear the and-link and short-delay-slot bits. */
18871 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18873 /* bltzal 0x40200000 bgezal 0x40600000 */
18874 /* bltzals 0x42200000 bgezals 0x42600000 */
18875 insn
&= ~0x02200000;
18878 /* Make a label at the end for use with the branch. */
18879 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18880 micromips_label_inc ();
18881 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18884 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18885 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18886 fixp
->fx_file
= fragp
->fr_file
;
18887 fixp
->fx_line
= fragp
->fr_line
;
18889 /* Branch over the jump. */
18890 buf
= write_compressed_insn (buf
, insn
, 4);
18896 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18898 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18904 unsigned long jal
= (short_ds
|| nods
18905 ? 0x74000000 : 0xf4000000); /* jal/s */
18907 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18908 insn
= al
? jal
: 0xd4000000;
18910 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18911 fragp
->fr_symbol
, fragp
->fr_offset
,
18912 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18913 fixp
->fx_file
= fragp
->fr_file
;
18914 fixp
->fx_line
= fragp
->fr_line
;
18916 buf
= write_compressed_insn (buf
, insn
, 4);
18918 if (compact
|| nods
)
18922 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18924 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18929 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18931 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18932 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18933 insn
|= at
<< MICROMIPSOP_SH_RT
;
18935 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18936 fragp
->fr_symbol
, fragp
->fr_offset
,
18937 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18938 fixp
->fx_file
= fragp
->fr_file
;
18939 fixp
->fx_line
= fragp
->fr_line
;
18941 buf
= write_compressed_insn (buf
, insn
, 4);
18943 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18944 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18945 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18947 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18948 fragp
->fr_symbol
, fragp
->fr_offset
,
18949 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18950 fixp
->fx_file
= fragp
->fr_file
;
18951 fixp
->fx_line
= fragp
->fr_line
;
18953 buf
= write_compressed_insn (buf
, insn
, 4);
18958 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18959 insn
|= at
<< MICROMIPSOP_SH_RS
;
18961 buf
= write_compressed_insn (buf
, insn
, 4);
18963 if (compact
|| nods
)
18965 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18969 /* jr/jrc/jalr/jalrs $at */
18970 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18971 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18973 insn
= al
? jalr
: jr
;
18974 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18976 buf
= write_compressed_insn (buf
, insn
, 2);
18981 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18983 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18988 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18992 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18995 const struct mips_int_operand
*operand
;
18998 unsigned int user_length
;
18999 bfd_boolean need_reloc
;
19000 unsigned long insn
;
19005 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
19006 operand
= mips16_immed_operand (type
, FALSE
);
19008 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
19009 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
19010 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
19012 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
19013 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
19014 || (operand
->root
.type
== OP_PCREL
&& !mac
19016 : !bfd_is_abs_section (symsec
)));
19018 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19020 const struct mips_pcrel_operand
*pcrel_op
;
19022 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19024 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19026 if (!mips_ignore_branch_isa
19027 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19028 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19029 _("branch to a symbol in another ISA mode"));
19030 else if ((fragp
->fr_offset
& 0x1) != 0)
19031 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19032 _("branch to misaligned address (0x%lx)"),
19033 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19034 + (fragp
->fr_offset
& ~1)));
19037 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19039 /* Make sure the section winds up with the alignment we have
19041 if (operand
->shift
> 0)
19042 record_alignment (asec
, operand
->shift
);
19045 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19046 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19049 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19050 _("macro instruction expanded into multiple "
19051 "instructions in a branch delay slot"));
19053 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19054 _("extended instruction in a branch delay slot"));
19056 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19057 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19058 _("macro instruction expanded into multiple "
19061 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19063 insn
= read_compressed_insn (buf
, 2);
19065 insn
|= MIPS16_EXTEND
;
19067 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19069 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19081 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19082 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19084 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19090 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19092 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19093 fragp
->fr_symbol
, fragp
->fr_offset
,
19094 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
19095 fixp
->fx_file
= fragp
->fr_file
;
19096 fixp
->fx_line
= fragp
->fr_line
;
19098 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19099 fragp
->fr_symbol
, fragp
->fr_offset
,
19100 FALSE
, BFD_RELOC_MIPS16_LO16
);
19101 fixp
->fx_file
= fragp
->fr_file
;
19102 fixp
->fx_line
= fragp
->fr_line
;
19107 switch (insn
& 0xf800)
19109 case 0x0800: /* ADDIU */
19110 reg
= (insn
>> 8) & 0x7;
19111 op
= 0xf0004800 | (reg
<< 8);
19113 case 0xb000: /* LW */
19114 reg
= (insn
>> 8) & 0x7;
19115 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19117 case 0xf800: /* I64 */
19118 reg
= (insn
>> 5) & 0x7;
19119 switch (insn
& 0x0700)
19121 case 0x0400: /* LD */
19122 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19124 case 0x0600: /* DADDIU */
19125 op
= 0xf000fd00 | (reg
<< 5);
19135 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19136 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19137 buf
= write_compressed_insn (buf
, new, 4);
19140 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19141 buf
= write_compressed_insn (buf
, new, 4);
19143 op
|= mips16_immed_extend (val
, 16);
19144 buf
= write_compressed_insn (buf
, op
, 4);
19146 fragp
->fr_fix
+= e2
? 8 : 12;
19150 unsigned int length
= ext
? 4 : 2;
19154 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19161 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19166 if (mac
|| reloc
== BFD_RELOC_NONE
)
19167 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19168 _("unsupported relocation"));
19171 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19172 fragp
->fr_symbol
, fragp
->fr_offset
,
19174 fixp
->fx_file
= fragp
->fr_file
;
19175 fixp
->fx_line
= fragp
->fr_line
;
19178 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19179 _("invalid unextended operand value"));
19182 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19183 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19185 gas_assert (mips16_opcode_length (insn
) == length
);
19186 write_compressed_insn (buf
, insn
, length
);
19187 fragp
->fr_fix
+= length
;
19192 relax_substateT subtype
= fragp
->fr_subtype
;
19193 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19194 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19195 unsigned int first
, second
;
19198 first
= RELAX_FIRST (subtype
);
19199 second
= RELAX_SECOND (subtype
);
19200 fixp
= (fixS
*) fragp
->fr_opcode
;
19202 /* If the delay slot chosen does not match the size of the instruction,
19203 then emit a warning. */
19204 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19205 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19210 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19211 | RELAX_DELAY_SLOT_SIZE_FIRST
19212 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19213 msg
= macro_warning (s
);
19215 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19219 /* Possibly emit a warning if we've chosen the longer option. */
19220 if (use_second
== second_longer
)
19226 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19227 msg
= macro_warning (s
);
19229 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19233 /* Go through all the fixups for the first sequence. Disable them
19234 (by marking them as done) if we're going to use the second
19235 sequence instead. */
19237 && fixp
->fx_frag
== fragp
19238 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19240 if (subtype
& RELAX_USE_SECOND
)
19242 fixp
= fixp
->fx_next
;
19245 /* Go through the fixups for the second sequence. Disable them if
19246 we're going to use the first sequence, otherwise adjust their
19247 addresses to account for the relaxation. */
19248 while (fixp
&& fixp
->fx_frag
== fragp
)
19250 if (subtype
& RELAX_USE_SECOND
)
19251 fixp
->fx_where
-= first
;
19254 fixp
= fixp
->fx_next
;
19257 /* Now modify the frag contents. */
19258 if (subtype
& RELAX_USE_SECOND
)
19262 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19263 memmove (start
, start
+ first
, second
);
19264 fragp
->fr_fix
-= first
;
19267 fragp
->fr_fix
-= second
;
19271 /* This function is called after the relocs have been generated.
19272 We've been storing mips16 text labels as odd. Here we convert them
19273 back to even for the convenience of the debugger. */
19276 mips_frob_file_after_relocs (void)
19279 unsigned int count
, i
;
19281 syms
= bfd_get_outsymbols (stdoutput
);
19282 count
= bfd_get_symcount (stdoutput
);
19283 for (i
= 0; i
< count
; i
++, syms
++)
19284 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19285 && ((*syms
)->value
& 1) != 0)
19287 (*syms
)->value
&= ~1;
19288 /* If the symbol has an odd size, it was probably computed
19289 incorrectly, so adjust that as well. */
19290 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19291 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19295 /* This function is called whenever a label is defined, including fake
19296 labels instantiated off the dot special symbol. It is used when
19297 handling branch delays; if a branch has a label, we assume we cannot
19298 move it. This also bumps the value of the symbol by 1 in compressed
19302 mips_record_label (symbolS
*sym
)
19304 segment_info_type
*si
= seg_info (now_seg
);
19305 struct insn_label_list
*l
;
19307 if (free_insn_labels
== NULL
)
19308 l
= XNEW (struct insn_label_list
);
19311 l
= free_insn_labels
;
19312 free_insn_labels
= l
->next
;
19316 l
->next
= si
->label_list
;
19317 si
->label_list
= l
;
19320 /* This function is called as tc_frob_label() whenever a label is defined
19321 and adds a DWARF-2 record we only want for true labels. */
19324 mips_define_label (symbolS
*sym
)
19326 mips_record_label (sym
);
19327 dwarf2_emit_label (sym
);
19330 /* This function is called by tc_new_dot_label whenever a new dot symbol
19334 mips_add_dot_label (symbolS
*sym
)
19336 mips_record_label (sym
);
19337 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19338 mips_compressed_mark_label (sym
);
19341 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19342 static unsigned int
19343 mips_convert_ase_flags (int ase
)
19345 unsigned int ext_ases
= 0;
19348 ext_ases
|= AFL_ASE_DSP
;
19349 if (ase
& ASE_DSPR2
)
19350 ext_ases
|= AFL_ASE_DSPR2
;
19351 if (ase
& ASE_DSPR3
)
19352 ext_ases
|= AFL_ASE_DSPR3
;
19354 ext_ases
|= AFL_ASE_EVA
;
19356 ext_ases
|= AFL_ASE_MCU
;
19357 if (ase
& ASE_MDMX
)
19358 ext_ases
|= AFL_ASE_MDMX
;
19359 if (ase
& ASE_MIPS3D
)
19360 ext_ases
|= AFL_ASE_MIPS3D
;
19362 ext_ases
|= AFL_ASE_MT
;
19363 if (ase
& ASE_SMARTMIPS
)
19364 ext_ases
|= AFL_ASE_SMARTMIPS
;
19365 if (ase
& ASE_VIRT
)
19366 ext_ases
|= AFL_ASE_VIRT
;
19368 ext_ases
|= AFL_ASE_MSA
;
19370 ext_ases
|= AFL_ASE_XPA
;
19371 if (ase
& ASE_MIPS16E2
)
19372 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19374 ext_ases
|= AFL_ASE_CRC
;
19375 if (ase
& ASE_GINV
)
19376 ext_ases
|= AFL_ASE_GINV
;
19377 if (ase
& ASE_LOONGSON_MMI
)
19378 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19379 if (ase
& ASE_LOONGSON_CAM
)
19380 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19381 if (ase
& ASE_LOONGSON_EXT
)
19382 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19383 if (ase
& ASE_LOONGSON_EXT2
)
19384 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19388 /* Some special processing for a MIPS ELF file. */
19391 mips_elf_final_processing (void)
19394 Elf_Internal_ABIFlags_v0 flags
;
19398 switch (file_mips_opts
.isa
)
19401 flags
.isa_level
= 1;
19404 flags
.isa_level
= 2;
19407 flags
.isa_level
= 3;
19410 flags
.isa_level
= 4;
19413 flags
.isa_level
= 5;
19416 flags
.isa_level
= 32;
19420 flags
.isa_level
= 32;
19424 flags
.isa_level
= 32;
19428 flags
.isa_level
= 32;
19432 flags
.isa_level
= 32;
19436 flags
.isa_level
= 64;
19440 flags
.isa_level
= 64;
19444 flags
.isa_level
= 64;
19448 flags
.isa_level
= 64;
19452 flags
.isa_level
= 64;
19457 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19458 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19459 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19460 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19462 flags
.cpr2_size
= AFL_REG_NONE
;
19463 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19464 Tag_GNU_MIPS_ABI_FP
);
19465 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19466 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19467 if (file_ase_mips16
)
19468 flags
.ases
|= AFL_ASE_MIPS16
;
19469 if (file_ase_micromips
)
19470 flags
.ases
|= AFL_ASE_MICROMIPS
;
19472 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19473 || file_mips_opts
.fp
== 64)
19474 && file_mips_opts
.oddspreg
)
19475 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19478 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19479 ((Elf_External_ABIFlags_v0
*)
19482 /* Write out the register information. */
19483 if (mips_abi
!= N64_ABI
)
19487 s
.ri_gprmask
= mips_gprmask
;
19488 s
.ri_cprmask
[0] = mips_cprmask
[0];
19489 s
.ri_cprmask
[1] = mips_cprmask
[1];
19490 s
.ri_cprmask
[2] = mips_cprmask
[2];
19491 s
.ri_cprmask
[3] = mips_cprmask
[3];
19492 /* The gp_value field is set by the MIPS ELF backend. */
19494 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19495 ((Elf32_External_RegInfo
*)
19496 mips_regmask_frag
));
19500 Elf64_Internal_RegInfo s
;
19502 s
.ri_gprmask
= mips_gprmask
;
19504 s
.ri_cprmask
[0] = mips_cprmask
[0];
19505 s
.ri_cprmask
[1] = mips_cprmask
[1];
19506 s
.ri_cprmask
[2] = mips_cprmask
[2];
19507 s
.ri_cprmask
[3] = mips_cprmask
[3];
19508 /* The gp_value field is set by the MIPS ELF backend. */
19510 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19511 ((Elf64_External_RegInfo
*)
19512 mips_regmask_frag
));
19515 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19516 sort of BFD interface for this. */
19517 if (mips_any_noreorder
)
19518 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19519 if (mips_pic
!= NO_PIC
)
19521 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19522 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19525 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19527 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19528 defined at present; this might need to change in future. */
19529 if (file_ase_mips16
)
19530 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19531 if (file_ase_micromips
)
19532 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19533 if (file_mips_opts
.ase
& ASE_MDMX
)
19534 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19536 /* Set the MIPS ELF ABI flags. */
19537 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19538 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19539 else if (mips_abi
== O64_ABI
)
19540 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19541 else if (mips_abi
== EABI_ABI
)
19543 if (file_mips_opts
.gp
== 64)
19544 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19546 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19549 /* Nothing to do for N32_ABI or N64_ABI. */
19551 if (mips_32bitmode
)
19552 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19554 if (mips_nan2008
== 1)
19555 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19557 /* 32 bit code with 64 bit FP registers. */
19558 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19559 Tag_GNU_MIPS_ABI_FP
);
19560 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19561 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19564 typedef struct proc
{
19566 symbolS
*func_end_sym
;
19567 unsigned long reg_mask
;
19568 unsigned long reg_offset
;
19569 unsigned long fpreg_mask
;
19570 unsigned long fpreg_offset
;
19571 unsigned long frame_offset
;
19572 unsigned long frame_reg
;
19573 unsigned long pc_reg
;
19576 static procS cur_proc
;
19577 static procS
*cur_proc_ptr
;
19578 static int numprocs
;
19580 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19581 as "2", and a normal nop as "0". */
19583 #define NOP_OPCODE_MIPS 0
19584 #define NOP_OPCODE_MIPS16 1
19585 #define NOP_OPCODE_MICROMIPS 2
19588 mips_nop_opcode (void)
19590 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19591 return NOP_OPCODE_MICROMIPS
;
19592 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19593 return NOP_OPCODE_MIPS16
;
19595 return NOP_OPCODE_MIPS
;
19598 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19599 32-bit microMIPS NOPs here (if applicable). */
19602 mips_handle_align (fragS
*fragp
)
19606 int bytes
, size
, excess
;
19609 if (fragp
->fr_type
!= rs_align_code
)
19612 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19614 switch (nop_opcode
)
19616 case NOP_OPCODE_MICROMIPS
:
19617 opcode
= micromips_nop32_insn
.insn_opcode
;
19620 case NOP_OPCODE_MIPS16
:
19621 opcode
= mips16_nop_insn
.insn_opcode
;
19624 case NOP_OPCODE_MIPS
:
19626 opcode
= nop_insn
.insn_opcode
;
19631 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19632 excess
= bytes
% size
;
19634 /* Handle the leading part if we're not inserting a whole number of
19635 instructions, and make it the end of the fixed part of the frag.
19636 Try to fit in a short microMIPS NOP if applicable and possible,
19637 and use zeroes otherwise. */
19638 gas_assert (excess
< 4);
19639 fragp
->fr_fix
+= excess
;
19644 /* Fall through. */
19646 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19648 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19652 /* Fall through. */
19655 /* Fall through. */
19660 md_number_to_chars (p
, opcode
, size
);
19661 fragp
->fr_var
= size
;
19670 if (*input_line_pointer
== '-')
19672 ++input_line_pointer
;
19675 if (!ISDIGIT (*input_line_pointer
))
19676 as_bad (_("expected simple number"));
19677 if (input_line_pointer
[0] == '0')
19679 if (input_line_pointer
[1] == 'x')
19681 input_line_pointer
+= 2;
19682 while (ISXDIGIT (*input_line_pointer
))
19685 val
|= hex_value (*input_line_pointer
++);
19687 return negative
? -val
: val
;
19691 ++input_line_pointer
;
19692 while (ISDIGIT (*input_line_pointer
))
19695 val
|= *input_line_pointer
++ - '0';
19697 return negative
? -val
: val
;
19700 if (!ISDIGIT (*input_line_pointer
))
19702 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19703 *input_line_pointer
, *input_line_pointer
);
19704 as_warn (_("invalid number"));
19707 while (ISDIGIT (*input_line_pointer
))
19710 val
+= *input_line_pointer
++ - '0';
19712 return negative
? -val
: val
;
19715 /* The .file directive; just like the usual .file directive, but there
19716 is an initial number which is the ECOFF file index. In the non-ECOFF
19717 case .file implies DWARF-2. */
19720 s_mips_file (int x ATTRIBUTE_UNUSED
)
19722 static int first_file_directive
= 0;
19724 if (ECOFF_DEBUGGING
)
19733 filename
= dwarf2_directive_filename ();
19735 /* Versions of GCC up to 3.1 start files with a ".file"
19736 directive even for stabs output. Make sure that this
19737 ".file" is handled. Note that you need a version of GCC
19738 after 3.1 in order to support DWARF-2 on MIPS. */
19739 if (filename
!= NULL
&& ! first_file_directive
)
19741 (void) new_logical_line (filename
, -1);
19742 s_app_file_string (filename
, 0);
19744 first_file_directive
= 1;
19748 /* The .loc directive, implying DWARF-2. */
19751 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19753 if (!ECOFF_DEBUGGING
)
19754 dwarf2_directive_loc (0);
19757 /* The .end directive. */
19760 s_mips_end (int x ATTRIBUTE_UNUSED
)
19764 /* Following functions need their own .frame and .cprestore directives. */
19765 mips_frame_reg_valid
= 0;
19766 mips_cprestore_valid
= 0;
19768 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19771 demand_empty_rest_of_line ();
19776 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19777 as_warn (_(".end not in text section"));
19781 as_warn (_(".end directive without a preceding .ent directive"));
19782 demand_empty_rest_of_line ();
19788 gas_assert (S_GET_NAME (p
));
19789 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19790 as_warn (_(".end symbol does not match .ent symbol"));
19792 if (debug_type
== DEBUG_STABS
)
19793 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19797 as_warn (_(".end directive missing or unknown symbol"));
19799 /* Create an expression to calculate the size of the function. */
19800 if (p
&& cur_proc_ptr
)
19802 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19803 expressionS
*exp
= XNEW (expressionS
);
19806 exp
->X_op
= O_subtract
;
19807 exp
->X_add_symbol
= symbol_temp_new_now ();
19808 exp
->X_op_symbol
= p
;
19809 exp
->X_add_number
= 0;
19811 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19814 #ifdef md_flush_pending_output
19815 md_flush_pending_output ();
19818 /* Generate a .pdr section. */
19819 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19821 segT saved_seg
= now_seg
;
19822 subsegT saved_subseg
= now_subseg
;
19826 gas_assert (pdr_seg
);
19827 subseg_set (pdr_seg
, 0);
19829 /* Write the symbol. */
19830 exp
.X_op
= O_symbol
;
19831 exp
.X_add_symbol
= p
;
19832 exp
.X_add_number
= 0;
19833 emit_expr (&exp
, 4);
19835 fragp
= frag_more (7 * 4);
19837 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19838 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19839 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19840 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19841 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19842 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19843 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19845 subseg_set (saved_seg
, saved_subseg
);
19848 cur_proc_ptr
= NULL
;
19851 /* The .aent and .ent directives. */
19854 s_mips_ent (int aent
)
19858 symbolP
= get_symbol ();
19859 if (*input_line_pointer
== ',')
19860 ++input_line_pointer
;
19861 SKIP_WHITESPACE ();
19862 if (ISDIGIT (*input_line_pointer
)
19863 || *input_line_pointer
== '-')
19866 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19867 as_warn (_(".ent or .aent not in text section"));
19869 if (!aent
&& cur_proc_ptr
)
19870 as_warn (_("missing .end"));
19874 /* This function needs its own .frame and .cprestore directives. */
19875 mips_frame_reg_valid
= 0;
19876 mips_cprestore_valid
= 0;
19878 cur_proc_ptr
= &cur_proc
;
19879 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19881 cur_proc_ptr
->func_sym
= symbolP
;
19885 if (debug_type
== DEBUG_STABS
)
19886 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19887 S_GET_NAME (symbolP
));
19890 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19892 demand_empty_rest_of_line ();
19895 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19896 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19897 s_mips_frame is used so that we can set the PDR information correctly.
19898 We can't use the ecoff routines because they make reference to the ecoff
19899 symbol table (in the mdebug section). */
19902 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19904 if (ECOFF_DEBUGGING
)
19910 if (cur_proc_ptr
== (procS
*) NULL
)
19912 as_warn (_(".frame outside of .ent"));
19913 demand_empty_rest_of_line ();
19917 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19919 SKIP_WHITESPACE ();
19920 if (*input_line_pointer
++ != ','
19921 || get_absolute_expression_and_terminator (&val
) != ',')
19923 as_warn (_("bad .frame directive"));
19924 --input_line_pointer
;
19925 demand_empty_rest_of_line ();
19929 cur_proc_ptr
->frame_offset
= val
;
19930 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19932 demand_empty_rest_of_line ();
19936 /* The .fmask and .mask directives. If the mdebug section is present
19937 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19938 embedded targets, s_mips_mask is used so that we can set the PDR
19939 information correctly. We can't use the ecoff routines because they
19940 make reference to the ecoff symbol table (in the mdebug section). */
19943 s_mips_mask (int reg_type
)
19945 if (ECOFF_DEBUGGING
)
19946 s_ignore (reg_type
);
19951 if (cur_proc_ptr
== (procS
*) NULL
)
19953 as_warn (_(".mask/.fmask outside of .ent"));
19954 demand_empty_rest_of_line ();
19958 if (get_absolute_expression_and_terminator (&mask
) != ',')
19960 as_warn (_("bad .mask/.fmask directive"));
19961 --input_line_pointer
;
19962 demand_empty_rest_of_line ();
19966 off
= get_absolute_expression ();
19968 if (reg_type
== 'F')
19970 cur_proc_ptr
->fpreg_mask
= mask
;
19971 cur_proc_ptr
->fpreg_offset
= off
;
19975 cur_proc_ptr
->reg_mask
= mask
;
19976 cur_proc_ptr
->reg_offset
= off
;
19979 demand_empty_rest_of_line ();
19983 /* A table describing all the processors gas knows about. Names are
19984 matched in the order listed.
19986 To ease comparison, please keep this table in the same order as
19987 gcc's mips_cpu_info_table[]. */
19988 static const struct mips_cpu_info mips_cpu_info_table
[] =
19990 /* Entries for generic ISAs. */
19991 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19992 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19993 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19994 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19995 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19996 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19997 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19998 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19999 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
20000 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
20001 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
20002 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
20003 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
20004 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
20005 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
20008 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20009 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20010 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
20013 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20016 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20017 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20018 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20019 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20020 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20021 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20022 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20023 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20024 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20025 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20026 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20027 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20028 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20029 /* ST Microelectronics Loongson 2E and 2F cores. */
20030 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20031 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20034 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20035 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20036 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20037 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20038 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20039 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20040 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20041 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20042 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20043 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20044 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20045 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20046 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20047 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20048 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20051 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20052 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20053 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20054 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20056 /* MIPS 32 Release 2 */
20057 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20058 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20059 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20060 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20061 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20062 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20064 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20065 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20066 ISA_MIPS32R2
, CPU_MIPS32R2
},
20067 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20068 ISA_MIPS32R2
, CPU_MIPS32R2
},
20069 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20070 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20071 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20072 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20073 /* Deprecated forms of the above. */
20074 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20076 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20077 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20078 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20079 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20080 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20081 /* Deprecated forms of the above. */
20082 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20084 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20085 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20086 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20087 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20088 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20089 /* Deprecated forms of the above. */
20090 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20091 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20092 /* 34Kn is a 34kc without DSP. */
20093 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20094 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20095 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20096 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20097 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20098 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20099 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20100 /* Deprecated forms of the above. */
20101 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20102 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20103 /* 1004K cores are multiprocessor versions of the 34K. */
20104 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20105 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20106 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20107 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20108 /* interaptiv is the new name for 1004kf. */
20109 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20110 { "interaptiv-mr2", 0,
20111 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20112 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20113 /* M5100 family. */
20114 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20115 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20116 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20117 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20120 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20121 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20122 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20123 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20125 /* Broadcom SB-1 CPU core. */
20126 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20127 /* Broadcom SB-1A CPU core. */
20128 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20130 /* MIPS 64 Release 2. */
20131 /* Loongson CPU core. */
20132 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20133 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20134 ISA_MIPS64R2
, CPU_GS464
},
20135 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20136 ISA_MIPS64R2
, CPU_GS464
},
20137 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20138 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20139 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20140 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20142 /* Cavium Networks Octeon CPU core. */
20143 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20144 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20145 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20146 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20149 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20152 XLP is mostly like XLR, with the prominent exception that it is
20153 MIPS64R2 rather than MIPS64. */
20154 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20156 /* MIPS 64 Release 6. */
20157 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20158 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20159 ISA_MIPS64R6
, CPU_MIPS64R6
},
20160 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20163 { NULL
, 0, 0, 0, 0 }
20167 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20168 with a final "000" replaced by "k". Ignore case.
20170 Note: this function is shared between GCC and GAS. */
20173 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20175 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20176 given
++, canonical
++;
20178 return ((*given
== 0 && *canonical
== 0)
20179 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20183 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20184 CPU name. We've traditionally allowed a lot of variation here.
20186 Note: this function is shared between GCC and GAS. */
20189 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20191 /* First see if the name matches exactly, or with a final "000"
20192 turned into "k". */
20193 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20196 /* If not, try comparing based on numerical designation alone.
20197 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20198 if (TOLOWER (*given
) == 'r')
20200 if (!ISDIGIT (*given
))
20203 /* Skip over some well-known prefixes in the canonical name,
20204 hoping to find a number there too. */
20205 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20207 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20209 else if (TOLOWER (canonical
[0]) == 'r')
20212 return mips_strict_matching_cpu_name_p (canonical
, given
);
20216 /* Parse an option that takes the name of a processor as its argument.
20217 OPTION is the name of the option and CPU_STRING is the argument.
20218 Return the corresponding processor enumeration if the CPU_STRING is
20219 recognized, otherwise report an error and return null.
20221 A similar function exists in GCC. */
20223 static const struct mips_cpu_info
*
20224 mips_parse_cpu (const char *option
, const char *cpu_string
)
20226 const struct mips_cpu_info
*p
;
20228 /* 'from-abi' selects the most compatible architecture for the given
20229 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20230 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20231 version. Look first at the -mgp options, if given, otherwise base
20232 the choice on MIPS_DEFAULT_64BIT.
20234 Treat NO_ABI like the EABIs. One reason to do this is that the
20235 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20236 architecture. This code picks MIPS I for 'mips' and MIPS III for
20237 'mips64', just as we did in the days before 'from-abi'. */
20238 if (strcasecmp (cpu_string
, "from-abi") == 0)
20240 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20241 return mips_cpu_info_from_isa (ISA_MIPS1
);
20243 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20244 return mips_cpu_info_from_isa (ISA_MIPS3
);
20246 if (file_mips_opts
.gp
>= 0)
20247 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20248 ? ISA_MIPS1
: ISA_MIPS3
);
20250 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20255 /* 'default' has traditionally been a no-op. Probably not very useful. */
20256 if (strcasecmp (cpu_string
, "default") == 0)
20259 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20260 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20263 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20267 /* Return the canonical processor information for ISA (a member of the
20268 ISA_MIPS* enumeration). */
20270 static const struct mips_cpu_info
*
20271 mips_cpu_info_from_isa (int isa
)
20275 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20276 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20277 && isa
== mips_cpu_info_table
[i
].isa
)
20278 return (&mips_cpu_info_table
[i
]);
20283 static const struct mips_cpu_info
*
20284 mips_cpu_info_from_arch (int arch
)
20288 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20289 if (arch
== mips_cpu_info_table
[i
].cpu
)
20290 return (&mips_cpu_info_table
[i
]);
20296 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20300 fprintf (stream
, "%24s", "");
20305 fprintf (stream
, ", ");
20309 if (*col_p
+ strlen (string
) > 72)
20311 fprintf (stream
, "\n%24s", "");
20315 fprintf (stream
, "%s", string
);
20316 *col_p
+= strlen (string
);
20322 md_show_usage (FILE *stream
)
20327 fprintf (stream
, _("\
20329 -EB generate big endian output\n\
20330 -EL generate little endian output\n\
20331 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20332 -G NUM allow referencing objects up to NUM bytes\n\
20333 implicitly with the gp register [default 8]\n"));
20334 fprintf (stream
, _("\
20335 -mips1 generate MIPS ISA I instructions\n\
20336 -mips2 generate MIPS ISA II instructions\n\
20337 -mips3 generate MIPS ISA III instructions\n\
20338 -mips4 generate MIPS ISA IV instructions\n\
20339 -mips5 generate MIPS ISA V instructions\n\
20340 -mips32 generate MIPS32 ISA instructions\n\
20341 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20342 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20343 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20344 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20345 -mips64 generate MIPS64 ISA instructions\n\
20346 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20347 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20348 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20349 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20350 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20354 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20355 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20356 show (stream
, "from-abi", &column
, &first
);
20357 fputc ('\n', stream
);
20359 fprintf (stream
, _("\
20360 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20361 -no-mCPU don't generate code specific to CPU.\n\
20362 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20366 show (stream
, "3900", &column
, &first
);
20367 show (stream
, "4010", &column
, &first
);
20368 show (stream
, "4100", &column
, &first
);
20369 show (stream
, "4650", &column
, &first
);
20370 fputc ('\n', stream
);
20372 fprintf (stream
, _("\
20373 -mips16 generate mips16 instructions\n\
20374 -no-mips16 do not generate mips16 instructions\n"));
20375 fprintf (stream
, _("\
20376 -mmips16e2 generate MIPS16e2 instructions\n\
20377 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20378 fprintf (stream
, _("\
20379 -mmicromips generate microMIPS instructions\n\
20380 -mno-micromips do not generate microMIPS instructions\n"));
20381 fprintf (stream
, _("\
20382 -msmartmips generate smartmips instructions\n\
20383 -mno-smartmips do not generate smartmips instructions\n"));
20384 fprintf (stream
, _("\
20385 -mdsp generate DSP instructions\n\
20386 -mno-dsp do not generate DSP instructions\n"));
20387 fprintf (stream
, _("\
20388 -mdspr2 generate DSP R2 instructions\n\
20389 -mno-dspr2 do not generate DSP R2 instructions\n"));
20390 fprintf (stream
, _("\
20391 -mdspr3 generate DSP R3 instructions\n\
20392 -mno-dspr3 do not generate DSP R3 instructions\n"));
20393 fprintf (stream
, _("\
20394 -mmt generate MT instructions\n\
20395 -mno-mt do not generate MT instructions\n"));
20396 fprintf (stream
, _("\
20397 -mmcu generate MCU instructions\n\
20398 -mno-mcu do not generate MCU instructions\n"));
20399 fprintf (stream
, _("\
20400 -mmsa generate MSA instructions\n\
20401 -mno-msa do not generate MSA instructions\n"));
20402 fprintf (stream
, _("\
20403 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20404 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20405 fprintf (stream
, _("\
20406 -mvirt generate Virtualization instructions\n\
20407 -mno-virt do not generate Virtualization instructions\n"));
20408 fprintf (stream
, _("\
20409 -mcrc generate CRC instructions\n\
20410 -mno-crc do not generate CRC instructions\n"));
20411 fprintf (stream
, _("\
20412 -mginv generate Global INValidate (GINV) instructions\n\
20413 -mno-ginv do not generate Global INValidate instructions\n"));
20414 fprintf (stream
, _("\
20415 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20416 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20417 fprintf (stream
, _("\
20418 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20419 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20420 fprintf (stream
, _("\
20421 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20422 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20423 fprintf (stream
, _("\
20424 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20425 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20426 fprintf (stream
, _("\
20427 -minsn32 only generate 32-bit microMIPS instructions\n\
20428 -mno-insn32 generate all microMIPS instructions\n"));
20429 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20430 fprintf (stream
, _("\
20431 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20432 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20434 fprintf (stream
, _("\
20435 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20436 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20438 fprintf (stream
, _("\
20439 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20440 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20441 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20442 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20443 -mfix-vr4120 work around certain VR4120 errata\n\
20444 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20445 -mfix-24k insert a nop after ERET and DERET instructions\n\
20446 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20447 -mfix-r5900 work around R5900 short loop errata\n\
20448 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20449 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20450 -msym32 assume all symbols have 32-bit values\n\
20451 -O0 do not remove unneeded NOPs, do not swap branches\n\
20452 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20453 -O2 remove unneeded NOPs and swap branches\n\
20454 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20455 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20456 fprintf (stream
, _("\
20457 -mhard-float allow floating-point instructions\n\
20458 -msoft-float do not allow floating-point instructions\n\
20459 -msingle-float only allow 32-bit floating-point operations\n\
20460 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20461 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20462 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20463 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20464 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20465 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20469 show (stream
, "legacy", &column
, &first
);
20470 show (stream
, "2008", &column
, &first
);
20472 fputc ('\n', stream
);
20474 fprintf (stream
, _("\
20475 -KPIC, -call_shared generate SVR4 position independent code\n\
20476 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20477 -mvxworks-pic generate VxWorks position independent code\n\
20478 -non_shared do not generate code that can operate with DSOs\n\
20479 -xgot assume a 32 bit GOT\n\
20480 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20481 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20482 position dependent (non shared) code\n\
20483 -mabi=ABI create ABI conformant object file for:\n"));
20487 show (stream
, "32", &column
, &first
);
20488 show (stream
, "o64", &column
, &first
);
20489 show (stream
, "n32", &column
, &first
);
20490 show (stream
, "64", &column
, &first
);
20491 show (stream
, "eabi", &column
, &first
);
20493 fputc ('\n', stream
);
20495 fprintf (stream
, _("\
20496 -32 create o32 ABI object file%s\n"),
20497 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20498 fprintf (stream
, _("\
20499 -n32 create n32 ABI object file%s\n"),
20500 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20501 fprintf (stream
, _("\
20502 -64 create 64 ABI object file%s\n"),
20503 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20508 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20510 if (HAVE_64BIT_SYMBOLS
)
20511 return dwarf2_format_64bit_irix
;
20513 return dwarf2_format_32bit
;
20518 mips_dwarf2_addr_size (void)
20520 if (HAVE_64BIT_OBJECTS
)
20526 /* Standard calling conventions leave the CFA at SP on entry. */
20528 mips_cfi_frame_initial_instructions (void)
20530 cfi_add_CFA_def_cfa_register (SP
);
20534 tc_mips_regname_to_dw2regnum (char *regname
)
20536 unsigned int regnum
= -1;
20539 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20545 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20546 Given a symbolic attribute NAME, return the proper integer value.
20547 Returns -1 if the attribute is not known. */
20550 mips_convert_symbolic_attribute (const char *name
)
20552 static const struct
20557 attribute_table
[] =
20559 #define T(tag) {#tag, tag}
20560 T (Tag_GNU_MIPS_ABI_FP
),
20561 T (Tag_GNU_MIPS_ABI_MSA
),
20569 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20570 if (streq (name
, attribute_table
[i
].name
))
20571 return attribute_table
[i
].tag
;
20579 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20581 mips_emit_delays ();
20583 as_warn (_("missing .end at end of assembly"));
20585 /* Just in case no code was emitted, do the consistency check. */
20586 file_mips_check_options ();
20588 /* Set a floating-point ABI if the user did not. */
20589 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20591 /* Perform consistency checks on the floating-point ABI. */
20592 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20593 Tag_GNU_MIPS_ABI_FP
);
20594 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20595 check_fpabi (fpabi
);
20599 /* Soft-float gets precedence over single-float, the two options should
20600 not be used together so this should not matter. */
20601 if (file_mips_opts
.soft_float
== 1)
20602 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20603 /* Single-float gets precedence over all double_float cases. */
20604 else if (file_mips_opts
.single_float
== 1)
20605 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20608 switch (file_mips_opts
.fp
)
20611 if (file_mips_opts
.gp
== 32)
20612 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20615 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20618 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20619 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20620 else if (file_mips_opts
.gp
== 32)
20621 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20623 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20628 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20629 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20633 /* Returns the relocation type required for a particular CFI encoding. */
20635 bfd_reloc_code_real_type
20636 mips_cfi_reloc_for_encoding (int encoding
)
20638 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20639 return BFD_RELOC_32_PCREL
;
20640 else return BFD_RELOC_NONE
;