1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if mflo and mfhi can be immediately followed by instructions
451 which write to the HI and LO registers.
453 According to MIPS specifications, MIPS ISAs I, II, and III need
454 (at least) two instructions between the reads of HI/LO and
455 instructions which write them, and later ISAs do not. Contradicting
456 the MIPS specifications, some MIPS IV processor user manuals (e.g.
457 the UM for the NEC Vr5000) document needing the instructions between
458 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
459 MIPS64 and later ISAs to have the interlocks, plus any specific
460 earlier-ISA CPUs for which CPU documentation declares that the
461 instructions are really interlocked. */
462 #define hilo_interlocks \
463 (mips_opts.isa == ISA_MIPS32 \
464 || mips_opts.isa == ISA_MIPS32R2 \
465 || mips_opts.isa == ISA_MIPS64 \
466 || mips_opts.isa == ISA_MIPS64R2 \
467 || mips_opts.arch == CPU_R4010 \
468 || mips_opts.arch == CPU_R10000 \
469 || mips_opts.arch == CPU_R12000 \
470 || mips_opts.arch == CPU_RM7000 \
471 || mips_opts.arch == CPU_VR5500 \
474 /* Whether the processor uses hardware interlocks to protect reads
475 from the GPRs after they are loaded from memory, and thus does not
476 require nops to be inserted. This applies to instructions marked
477 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
479 #define gpr_interlocks \
480 (mips_opts.isa != ISA_MIPS1 \
481 || mips_opts.arch == CPU_R3900)
483 /* Whether the processor uses hardware interlocks to avoid delays
484 required by coprocessor instructions, and thus does not require
485 nops to be inserted. This applies to instructions marked
486 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
487 between instructions marked INSN_WRITE_COND_CODE and ones marked
488 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
489 levels I, II, and III. */
490 /* Itbl support may require additional care here. */
491 #define cop_interlocks \
492 ((mips_opts.isa != ISA_MIPS1 \
493 && mips_opts.isa != ISA_MIPS2 \
494 && mips_opts.isa != ISA_MIPS3) \
495 || mips_opts.arch == CPU_R4300 \
498 /* Whether the processor uses hardware interlocks to protect reads
499 from coprocessor registers after they are loaded from memory, and
500 thus does not require nops to be inserted. This applies to
501 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
502 requires at MIPS ISA level I. */
503 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
505 /* Is this a mfhi or mflo instruction? */
506 #define MF_HILO_INSN(PINFO) \
507 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
509 /* MIPS PIC level. */
511 enum mips_pic_level mips_pic
;
513 /* 1 if we should generate 32 bit offsets from the $gp register in
514 SVR4_PIC mode. Currently has no meaning in other modes. */
515 static int mips_big_got
= 0;
517 /* 1 if trap instructions should used for overflow rather than break
519 static int mips_trap
= 0;
521 /* 1 if double width floating point constants should not be constructed
522 by assembling two single width halves into two single width floating
523 point registers which just happen to alias the double width destination
524 register. On some architectures this aliasing can be disabled by a bit
525 in the status register, and the setting of this bit cannot be determined
526 automatically at assemble time. */
527 static int mips_disable_float_construction
;
529 /* Non-zero if any .set noreorder directives were used. */
531 static int mips_any_noreorder
;
533 /* Non-zero if nops should be inserted when the register referenced in
534 an mfhi/mflo instruction is read in the next two instructions. */
535 static int mips_7000_hilo_fix
;
537 /* The size of objects in the small data section. */
538 static unsigned int g_switch_value
= 8;
539 /* Whether the -G option was used. */
540 static int g_switch_seen
= 0;
545 /* If we can determine in advance that GP optimization won't be
546 possible, we can skip the relaxation stuff that tries to produce
547 GP-relative references. This makes delay slot optimization work
550 This function can only provide a guess, but it seems to work for
551 gcc output. It needs to guess right for gcc, otherwise gcc
552 will put what it thinks is a GP-relative instruction in a branch
555 I don't know if a fix is needed for the SVR4_PIC mode. I've only
556 fixed it for the non-PIC mode. KR 95/04/07 */
557 static int nopic_need_relax (symbolS
*, int);
559 /* handle of the OPCODE hash table */
560 static struct hash_control
*op_hash
= NULL
;
562 /* The opcode hash table we use for the mips16. */
563 static struct hash_control
*mips16_op_hash
= NULL
;
565 /* This array holds the chars that always start a comment. If the
566 pre-processor is disabled, these aren't very useful */
567 const char comment_chars
[] = "#";
569 /* This array holds the chars that only start a comment at the beginning of
570 a line. If the line seems to have the form '# 123 filename'
571 .line and .file directives will appear in the pre-processed output */
572 /* Note that input_file.c hand checks for '#' at the beginning of the
573 first line of the input file. This is because the compiler outputs
574 #NO_APP at the beginning of its output. */
575 /* Also note that C style comments are always supported. */
576 const char line_comment_chars
[] = "#";
578 /* This array holds machine specific line separator characters. */
579 const char line_separator_chars
[] = ";";
581 /* Chars that can be used to separate mant from exp in floating point nums */
582 const char EXP_CHARS
[] = "eE";
584 /* Chars that mean this number is a floating point constant */
587 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
589 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
590 changed in read.c . Ideally it shouldn't have to know about it at all,
591 but nothing is ideal around here.
594 static char *insn_error
;
596 static int auto_align
= 1;
598 /* When outputting SVR4 PIC code, the assembler needs to know the
599 offset in the stack frame from which to restore the $gp register.
600 This is set by the .cprestore pseudo-op, and saved in this
602 static offsetT mips_cprestore_offset
= -1;
604 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
605 more optimizations, it can use a register value instead of a memory-saved
606 offset and even an other register than $gp as global pointer. */
607 static offsetT mips_cpreturn_offset
= -1;
608 static int mips_cpreturn_register
= -1;
609 static int mips_gp_register
= GP
;
610 static int mips_gprel_offset
= 0;
612 /* Whether mips_cprestore_offset has been set in the current function
613 (or whether it has already been warned about, if not). */
614 static int mips_cprestore_valid
= 0;
616 /* This is the register which holds the stack frame, as set by the
617 .frame pseudo-op. This is needed to implement .cprestore. */
618 static int mips_frame_reg
= SP
;
620 /* Whether mips_frame_reg has been set in the current function
621 (or whether it has already been warned about, if not). */
622 static int mips_frame_reg_valid
= 0;
624 /* To output NOP instructions correctly, we need to keep information
625 about the previous two instructions. */
627 /* Whether we are optimizing. The default value of 2 means to remove
628 unneeded NOPs and swap branch instructions when possible. A value
629 of 1 means to not swap branches. A value of 0 means to always
631 static int mips_optimize
= 2;
633 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
634 equivalent to seeing no -g option at all. */
635 static int mips_debug
= 0;
637 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
638 #define MAX_VR4130_NOPS 4
640 /* The maximum number of NOPs needed to fill delay slots. */
641 #define MAX_DELAY_NOPS 2
643 /* The maximum number of NOPs needed for any purpose. */
646 /* A list of previous instructions, with index 0 being the most recent.
647 We need to look back MAX_NOPS instructions when filling delay slots
648 or working around processor errata. We need to look back one
649 instruction further if we're thinking about using history[0] to
650 fill a branch delay slot. */
651 static struct mips_cl_insn history
[1 + MAX_NOPS
];
653 /* Nop instructions used by emit_nop. */
654 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
656 /* The appropriate nop for the current mode. */
657 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
659 /* If this is set, it points to a frag holding nop instructions which
660 were inserted before the start of a noreorder section. If those
661 nops turn out to be unnecessary, the size of the frag can be
663 static fragS
*prev_nop_frag
;
665 /* The number of nop instructions we created in prev_nop_frag. */
666 static int prev_nop_frag_holds
;
668 /* The number of nop instructions that we know we need in
670 static int prev_nop_frag_required
;
672 /* The number of instructions we've seen since prev_nop_frag. */
673 static int prev_nop_frag_since
;
675 /* For ECOFF and ELF, relocations against symbols are done in two
676 parts, with a HI relocation and a LO relocation. Each relocation
677 has only 16 bits of space to store an addend. This means that in
678 order for the linker to handle carries correctly, it must be able
679 to locate both the HI and the LO relocation. This means that the
680 relocations must appear in order in the relocation table.
682 In order to implement this, we keep track of each unmatched HI
683 relocation. We then sort them so that they immediately precede the
684 corresponding LO relocation. */
689 struct mips_hi_fixup
*next
;
692 /* The section this fixup is in. */
696 /* The list of unmatched HI relocs. */
698 static struct mips_hi_fixup
*mips_hi_fixup_list
;
700 /* The frag containing the last explicit relocation operator.
701 Null if explicit relocations have not been used. */
703 static fragS
*prev_reloc_op_frag
;
705 /* Map normal MIPS register numbers to mips16 register numbers. */
707 #define X ILLEGAL_REG
708 static const int mips32_to_16_reg_map
[] =
710 X
, X
, 2, 3, 4, 5, 6, 7,
711 X
, X
, X
, X
, X
, X
, X
, X
,
712 0, 1, X
, X
, X
, X
, X
, X
,
713 X
, X
, X
, X
, X
, X
, X
, X
717 /* Map mips16 register numbers to normal MIPS register numbers. */
719 static const unsigned int mips16_to_32_reg_map
[] =
721 16, 17, 2, 3, 4, 5, 6, 7
724 /* Classifies the kind of instructions we're interested in when
725 implementing -mfix-vr4120. */
726 enum fix_vr4120_class
{
733 NUM_FIX_VR4120_CLASSES
736 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
737 there must be at least one other instruction between an instruction
738 of type X and an instruction of type Y. */
739 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
741 /* True if -mfix-vr4120 is in force. */
742 static int mips_fix_vr4120
;
744 /* ...likewise -mfix-vr4130. */
745 static int mips_fix_vr4130
;
747 /* We don't relax branches by default, since this causes us to expand
748 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
749 fail to compute the offset before expanding the macro to the most
750 efficient expansion. */
752 static int mips_relax_branch
;
754 /* The expansion of many macros depends on the type of symbol that
755 they refer to. For example, when generating position-dependent code,
756 a macro that refers to a symbol may have two different expansions,
757 one which uses GP-relative addresses and one which uses absolute
758 addresses. When generating SVR4-style PIC, a macro may have
759 different expansions for local and global symbols.
761 We handle these situations by generating both sequences and putting
762 them in variant frags. In position-dependent code, the first sequence
763 will be the GP-relative one and the second sequence will be the
764 absolute one. In SVR4 PIC, the first sequence will be for global
765 symbols and the second will be for local symbols.
767 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
768 SECOND are the lengths of the two sequences in bytes. These fields
769 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
770 the subtype has the following flags:
773 Set if it has been decided that we should use the second
774 sequence instead of the first.
777 Set in the first variant frag if the macro's second implementation
778 is longer than its first. This refers to the macro as a whole,
779 not an individual relaxation.
782 Set in the first variant frag if the macro appeared in a .set nomacro
783 block and if one alternative requires a warning but the other does not.
786 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
789 The frag's "opcode" points to the first fixup for relaxable code.
791 Relaxable macros are generated using a sequence such as:
793 relax_start (SYMBOL);
794 ... generate first expansion ...
796 ... generate second expansion ...
799 The code and fixups for the unwanted alternative are discarded
800 by md_convert_frag. */
801 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
803 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
804 #define RELAX_SECOND(X) ((X) & 0xff)
805 #define RELAX_USE_SECOND 0x10000
806 #define RELAX_SECOND_LONGER 0x20000
807 #define RELAX_NOMACRO 0x40000
808 #define RELAX_DELAY_SLOT 0x80000
810 /* Branch without likely bit. If label is out of range, we turn:
812 beq reg1, reg2, label
822 with the following opcode replacements:
829 bltzal <-> bgezal (with jal label instead of j label)
831 Even though keeping the delay slot instruction in the delay slot of
832 the branch would be more efficient, it would be very tricky to do
833 correctly, because we'd have to introduce a variable frag *after*
834 the delay slot instruction, and expand that instead. Let's do it
835 the easy way for now, even if the branch-not-taken case now costs
836 one additional instruction. Out-of-range branches are not supposed
837 to be common, anyway.
839 Branch likely. If label is out of range, we turn:
841 beql reg1, reg2, label
842 delay slot (annulled if branch not taken)
851 delay slot (executed only if branch taken)
854 It would be possible to generate a shorter sequence by losing the
855 likely bit, generating something like:
860 delay slot (executed only if branch taken)
872 bltzall -> bgezal (with jal label instead of j label)
873 bgezall -> bltzal (ditto)
876 but it's not clear that it would actually improve performance. */
877 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
880 | ((toofar) ? 1 : 0) \
882 | ((likely) ? 4 : 0) \
883 | ((uncond) ? 8 : 0)))
884 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
885 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
886 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
887 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
888 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
890 /* For mips16 code, we use an entirely different form of relaxation.
891 mips16 supports two versions of most instructions which take
892 immediate values: a small one which takes some small value, and a
893 larger one which takes a 16 bit value. Since branches also follow
894 this pattern, relaxing these values is required.
896 We can assemble both mips16 and normal MIPS code in a single
897 object. Therefore, we need to support this type of relaxation at
898 the same time that we support the relaxation described above. We
899 use the high bit of the subtype field to distinguish these cases.
901 The information we store for this type of relaxation is the
902 argument code found in the opcode file for this relocation, whether
903 the user explicitly requested a small or extended form, and whether
904 the relocation is in a jump or jal delay slot. That tells us the
905 size of the value, and how it should be stored. We also store
906 whether the fragment is considered to be extended or not. We also
907 store whether this is known to be a branch to a different section,
908 whether we have tried to relax this frag yet, and whether we have
909 ever extended a PC relative fragment because of a shift count. */
910 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
913 | ((small) ? 0x100 : 0) \
914 | ((ext) ? 0x200 : 0) \
915 | ((dslot) ? 0x400 : 0) \
916 | ((jal_dslot) ? 0x800 : 0))
917 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
918 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
919 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
920 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
921 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
922 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
923 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
924 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
925 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
926 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
927 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
928 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
930 /* Is the given value a sign-extended 32-bit value? */
931 #define IS_SEXT_32BIT_NUM(x) \
932 (((x) &~ (offsetT) 0x7fffffff) == 0 \
933 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
935 /* Is the given value a sign-extended 16-bit value? */
936 #define IS_SEXT_16BIT_NUM(x) \
937 (((x) &~ (offsetT) 0x7fff) == 0 \
938 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
940 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
941 #define IS_ZEXT_32BIT_NUM(x) \
942 (((x) &~ (offsetT) 0xffffffff) == 0 \
943 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
945 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
946 VALUE << SHIFT. VALUE is evaluated exactly once. */
947 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
948 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
949 | (((VALUE) & (MASK)) << (SHIFT)))
951 /* Extract bits MASK << SHIFT from STRUCT and shift them right
953 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
954 (((STRUCT) >> (SHIFT)) & (MASK))
956 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
957 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
959 include/opcode/mips.h specifies operand fields using the macros
960 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
961 with "MIPS16OP" instead of "OP". */
962 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
963 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
964 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
965 INSERT_BITS ((INSN).insn_opcode, VALUE, \
966 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
968 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
969 #define EXTRACT_OPERAND(FIELD, INSN) \
970 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
971 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
972 EXTRACT_BITS ((INSN).insn_opcode, \
973 MIPS16OP_MASK_##FIELD, \
976 /* Global variables used when generating relaxable macros. See the
977 comment above RELAX_ENCODE for more details about how relaxation
980 /* 0 if we're not emitting a relaxable macro.
981 1 if we're emitting the first of the two relaxation alternatives.
982 2 if we're emitting the second alternative. */
985 /* The first relaxable fixup in the current frag. (In other words,
986 the first fixup that refers to relaxable code.) */
989 /* sizes[0] says how many bytes of the first alternative are stored in
990 the current frag. Likewise sizes[1] for the second alternative. */
991 unsigned int sizes
[2];
993 /* The symbol on which the choice of sequence depends. */
997 /* Global variables used to decide whether a macro needs a warning. */
999 /* True if the macro is in a branch delay slot. */
1000 bfd_boolean delay_slot_p
;
1002 /* For relaxable macros, sizes[0] is the length of the first alternative
1003 in bytes and sizes[1] is the length of the second alternative.
1004 For non-relaxable macros, both elements give the length of the
1006 unsigned int sizes
[2];
1008 /* The first variant frag for this macro. */
1010 } mips_macro_warning
;
1012 /* Prototypes for static functions. */
1014 #define internalError() \
1015 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1017 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1019 static void append_insn
1020 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1021 static void mips_no_prev_insn (void);
1022 static void mips16_macro_build
1023 (expressionS
*, const char *, const char *, va_list);
1024 static void load_register (int, expressionS
*, int);
1025 static void macro_start (void);
1026 static void macro_end (void);
1027 static void macro (struct mips_cl_insn
* ip
);
1028 static void mips16_macro (struct mips_cl_insn
* ip
);
1029 #ifdef LOSING_COMPILER
1030 static void macro2 (struct mips_cl_insn
* ip
);
1032 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1033 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1034 static void mips16_immed
1035 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1036 unsigned long *, bfd_boolean
*, unsigned short *);
1037 static size_t my_getSmallExpression
1038 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1039 static void my_getExpression (expressionS
*, char *);
1040 static void s_align (int);
1041 static void s_change_sec (int);
1042 static void s_change_section (int);
1043 static void s_cons (int);
1044 static void s_float_cons (int);
1045 static void s_mips_globl (int);
1046 static void s_option (int);
1047 static void s_mipsset (int);
1048 static void s_abicalls (int);
1049 static void s_cpload (int);
1050 static void s_cpsetup (int);
1051 static void s_cplocal (int);
1052 static void s_cprestore (int);
1053 static void s_cpreturn (int);
1054 static void s_dtprelword (int);
1055 static void s_dtpreldword (int);
1056 static void s_gpvalue (int);
1057 static void s_gpword (int);
1058 static void s_gpdword (int);
1059 static void s_cpadd (int);
1060 static void s_insn (int);
1061 static void md_obj_begin (void);
1062 static void md_obj_end (void);
1063 static void s_mips_ent (int);
1064 static void s_mips_end (int);
1065 static void s_mips_frame (int);
1066 static void s_mips_mask (int reg_type
);
1067 static void s_mips_stab (int);
1068 static void s_mips_weakext (int);
1069 static void s_mips_file (int);
1070 static void s_mips_loc (int);
1071 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1072 static int relaxed_branch_length (fragS
*, asection
*, int);
1073 static int validate_mips_insn (const struct mips_opcode
*);
1075 /* Table and functions used to map between CPU/ISA names, and
1076 ISA levels, and CPU numbers. */
1078 struct mips_cpu_info
1080 const char *name
; /* CPU or ISA name. */
1081 int flags
; /* ASEs available, or ISA flag. */
1082 int isa
; /* ISA level. */
1083 int cpu
; /* CPU number (default CPU if ISA). */
1086 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1087 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1088 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1089 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1090 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1091 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1092 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1094 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1095 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1096 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1100 The following pseudo-ops from the Kane and Heinrich MIPS book
1101 should be defined here, but are currently unsupported: .alias,
1102 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1104 The following pseudo-ops from the Kane and Heinrich MIPS book are
1105 specific to the type of debugging information being generated, and
1106 should be defined by the object format: .aent, .begin, .bend,
1107 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1110 The following pseudo-ops from the Kane and Heinrich MIPS book are
1111 not MIPS CPU specific, but are also not specific to the object file
1112 format. This file is probably the best place to define them, but
1113 they are not currently supported: .asm0, .endr, .lab, .struct. */
1115 static const pseudo_typeS mips_pseudo_table
[] =
1117 /* MIPS specific pseudo-ops. */
1118 {"option", s_option
, 0},
1119 {"set", s_mipsset
, 0},
1120 {"rdata", s_change_sec
, 'r'},
1121 {"sdata", s_change_sec
, 's'},
1122 {"livereg", s_ignore
, 0},
1123 {"abicalls", s_abicalls
, 0},
1124 {"cpload", s_cpload
, 0},
1125 {"cpsetup", s_cpsetup
, 0},
1126 {"cplocal", s_cplocal
, 0},
1127 {"cprestore", s_cprestore
, 0},
1128 {"cpreturn", s_cpreturn
, 0},
1129 {"dtprelword", s_dtprelword
, 0},
1130 {"dtpreldword", s_dtpreldword
, 0},
1131 {"gpvalue", s_gpvalue
, 0},
1132 {"gpword", s_gpword
, 0},
1133 {"gpdword", s_gpdword
, 0},
1134 {"cpadd", s_cpadd
, 0},
1135 {"insn", s_insn
, 0},
1137 /* Relatively generic pseudo-ops that happen to be used on MIPS
1139 {"asciiz", stringer
, 8 + 1},
1140 {"bss", s_change_sec
, 'b'},
1142 {"half", s_cons
, 1},
1143 {"dword", s_cons
, 3},
1144 {"weakext", s_mips_weakext
, 0},
1145 {"origin", s_org
, 0},
1146 {"repeat", s_rept
, 0},
1148 /* These pseudo-ops are defined in read.c, but must be overridden
1149 here for one reason or another. */
1150 {"align", s_align
, 0},
1151 {"byte", s_cons
, 0},
1152 {"data", s_change_sec
, 'd'},
1153 {"double", s_float_cons
, 'd'},
1154 {"float", s_float_cons
, 'f'},
1155 {"globl", s_mips_globl
, 0},
1156 {"global", s_mips_globl
, 0},
1157 {"hword", s_cons
, 1},
1159 {"long", s_cons
, 2},
1160 {"octa", s_cons
, 4},
1161 {"quad", s_cons
, 3},
1162 {"section", s_change_section
, 0},
1163 {"short", s_cons
, 1},
1164 {"single", s_float_cons
, 'f'},
1165 {"stabn", s_mips_stab
, 'n'},
1166 {"text", s_change_sec
, 't'},
1167 {"word", s_cons
, 2},
1169 { "extern", ecoff_directive_extern
, 0},
1174 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1176 /* These pseudo-ops should be defined by the object file format.
1177 However, a.out doesn't support them, so we have versions here. */
1178 {"aent", s_mips_ent
, 1},
1179 {"bgnb", s_ignore
, 0},
1180 {"end", s_mips_end
, 0},
1181 {"endb", s_ignore
, 0},
1182 {"ent", s_mips_ent
, 0},
1183 {"file", s_mips_file
, 0},
1184 {"fmask", s_mips_mask
, 'F'},
1185 {"frame", s_mips_frame
, 0},
1186 {"loc", s_mips_loc
, 0},
1187 {"mask", s_mips_mask
, 'R'},
1188 {"verstamp", s_ignore
, 0},
1192 extern void pop_insert (const pseudo_typeS
*);
1195 mips_pop_insert (void)
1197 pop_insert (mips_pseudo_table
);
1198 if (! ECOFF_DEBUGGING
)
1199 pop_insert (mips_nonecoff_pseudo_table
);
1202 /* Symbols labelling the current insn. */
1204 struct insn_label_list
1206 struct insn_label_list
*next
;
1210 static struct insn_label_list
*free_insn_labels
;
1211 #define label_list tc_segment_info_data.labels
1213 static void mips_clear_insn_labels (void);
1216 mips_clear_insn_labels (void)
1218 register struct insn_label_list
**pl
;
1219 segment_info_type
*si
;
1223 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1226 si
= seg_info (now_seg
);
1227 *pl
= si
->label_list
;
1228 si
->label_list
= NULL
;
1233 static char *expr_end
;
1235 /* Expressions which appear in instructions. These are set by
1238 static expressionS imm_expr
;
1239 static expressionS imm2_expr
;
1240 static expressionS offset_expr
;
1242 /* Relocs associated with imm_expr and offset_expr. */
1244 static bfd_reloc_code_real_type imm_reloc
[3]
1245 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1246 static bfd_reloc_code_real_type offset_reloc
[3]
1247 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1249 /* These are set by mips16_ip if an explicit extension is used. */
1251 static bfd_boolean mips16_small
, mips16_ext
;
1254 /* The pdr segment for per procedure frame/regmask info. Not used for
1257 static segT pdr_seg
;
1260 /* The default target format to use. */
1263 mips_target_format (void)
1265 switch (OUTPUT_FLAVOR
)
1267 case bfd_target_ecoff_flavour
:
1268 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1269 case bfd_target_coff_flavour
:
1271 case bfd_target_elf_flavour
:
1273 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1274 return (target_big_endian
1275 ? "elf32-bigmips-vxworks"
1276 : "elf32-littlemips-vxworks");
1279 /* This is traditional mips. */
1280 return (target_big_endian
1281 ? (HAVE_64BIT_OBJECTS
1282 ? "elf64-tradbigmips"
1284 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1285 : (HAVE_64BIT_OBJECTS
1286 ? "elf64-tradlittlemips"
1288 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1290 return (target_big_endian
1291 ? (HAVE_64BIT_OBJECTS
1294 ? "elf32-nbigmips" : "elf32-bigmips"))
1295 : (HAVE_64BIT_OBJECTS
1296 ? "elf64-littlemips"
1298 ? "elf32-nlittlemips" : "elf32-littlemips")));
1306 /* Return the length of instruction INSN. */
1308 static inline unsigned int
1309 insn_length (const struct mips_cl_insn
*insn
)
1311 if (!mips_opts
.mips16
)
1313 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1316 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1319 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1324 insn
->use_extend
= FALSE
;
1326 insn
->insn_opcode
= mo
->match
;
1329 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1330 insn
->fixp
[i
] = NULL
;
1331 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1332 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1333 insn
->mips16_absolute_jump_p
= 0;
1336 /* Record the current MIPS16 mode in now_seg. */
1339 mips_record_mips16_mode (void)
1341 segment_info_type
*si
;
1343 si
= seg_info (now_seg
);
1344 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1345 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1348 /* Install INSN at the location specified by its "frag" and "where" fields. */
1351 install_insn (const struct mips_cl_insn
*insn
)
1353 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1354 if (!mips_opts
.mips16
)
1355 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1356 else if (insn
->mips16_absolute_jump_p
)
1358 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1359 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1363 if (insn
->use_extend
)
1365 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1368 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1370 mips_record_mips16_mode ();
1373 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1374 and install the opcode in the new location. */
1377 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1382 insn
->where
= where
;
1383 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1384 if (insn
->fixp
[i
] != NULL
)
1386 insn
->fixp
[i
]->fx_frag
= frag
;
1387 insn
->fixp
[i
]->fx_where
= where
;
1389 install_insn (insn
);
1392 /* Add INSN to the end of the output. */
1395 add_fixed_insn (struct mips_cl_insn
*insn
)
1397 char *f
= frag_more (insn_length (insn
));
1398 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1401 /* Start a variant frag and move INSN to the start of the variant part,
1402 marking it as fixed. The other arguments are as for frag_var. */
1405 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1406 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1408 frag_grow (max_chars
);
1409 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1411 frag_var (rs_machine_dependent
, max_chars
, var
,
1412 subtype
, symbol
, offset
, NULL
);
1415 /* Insert N copies of INSN into the history buffer, starting at
1416 position FIRST. Neither FIRST nor N need to be clipped. */
1419 insert_into_history (unsigned int first
, unsigned int n
,
1420 const struct mips_cl_insn
*insn
)
1422 if (mips_relax
.sequence
!= 2)
1426 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1428 history
[i
] = history
[i
- n
];
1434 /* Emit a nop instruction, recording it in the history buffer. */
1439 add_fixed_insn (NOP_INSN
);
1440 insert_into_history (0, 1, NOP_INSN
);
1443 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1444 the idea is to make it obvious at a glance that each errata is
1448 init_vr4120_conflicts (void)
1450 #define CONFLICT(FIRST, SECOND) \
1451 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1453 /* Errata 21 - [D]DIV[U] after [D]MACC */
1454 CONFLICT (MACC
, DIV
);
1455 CONFLICT (DMACC
, DIV
);
1457 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1458 CONFLICT (DMULT
, DMULT
);
1459 CONFLICT (DMULT
, DMACC
);
1460 CONFLICT (DMACC
, DMULT
);
1461 CONFLICT (DMACC
, DMACC
);
1463 /* Errata 24 - MT{LO,HI} after [D]MACC */
1464 CONFLICT (MACC
, MTHILO
);
1465 CONFLICT (DMACC
, MTHILO
);
1467 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1468 instruction is executed immediately after a MACC or DMACC
1469 instruction, the result of [either instruction] is incorrect." */
1470 CONFLICT (MACC
, MULT
);
1471 CONFLICT (MACC
, DMULT
);
1472 CONFLICT (DMACC
, MULT
);
1473 CONFLICT (DMACC
, DMULT
);
1475 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1476 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1477 DDIV or DDIVU instruction, the result of the MACC or
1478 DMACC instruction is incorrect.". */
1479 CONFLICT (DMULT
, MACC
);
1480 CONFLICT (DMULT
, DMACC
);
1481 CONFLICT (DIV
, MACC
);
1482 CONFLICT (DIV
, DMACC
);
1492 #define RTYPE_MASK 0x1ff00
1493 #define RTYPE_NUM 0x00100
1494 #define RTYPE_FPU 0x00200
1495 #define RTYPE_FCC 0x00400
1496 #define RTYPE_VEC 0x00800
1497 #define RTYPE_GP 0x01000
1498 #define RTYPE_CP0 0x02000
1499 #define RTYPE_PC 0x04000
1500 #define RTYPE_ACC 0x08000
1501 #define RTYPE_CCC 0x10000
1502 #define RNUM_MASK 0x000ff
1503 #define RWARN 0x80000
1505 #define GENERIC_REGISTER_NUMBERS \
1506 {"$0", RTYPE_NUM | 0}, \
1507 {"$1", RTYPE_NUM | 1}, \
1508 {"$2", RTYPE_NUM | 2}, \
1509 {"$3", RTYPE_NUM | 3}, \
1510 {"$4", RTYPE_NUM | 4}, \
1511 {"$5", RTYPE_NUM | 5}, \
1512 {"$6", RTYPE_NUM | 6}, \
1513 {"$7", RTYPE_NUM | 7}, \
1514 {"$8", RTYPE_NUM | 8}, \
1515 {"$9", RTYPE_NUM | 9}, \
1516 {"$10", RTYPE_NUM | 10}, \
1517 {"$11", RTYPE_NUM | 11}, \
1518 {"$12", RTYPE_NUM | 12}, \
1519 {"$13", RTYPE_NUM | 13}, \
1520 {"$14", RTYPE_NUM | 14}, \
1521 {"$15", RTYPE_NUM | 15}, \
1522 {"$16", RTYPE_NUM | 16}, \
1523 {"$17", RTYPE_NUM | 17}, \
1524 {"$18", RTYPE_NUM | 18}, \
1525 {"$19", RTYPE_NUM | 19}, \
1526 {"$20", RTYPE_NUM | 20}, \
1527 {"$21", RTYPE_NUM | 21}, \
1528 {"$22", RTYPE_NUM | 22}, \
1529 {"$23", RTYPE_NUM | 23}, \
1530 {"$24", RTYPE_NUM | 24}, \
1531 {"$25", RTYPE_NUM | 25}, \
1532 {"$26", RTYPE_NUM | 26}, \
1533 {"$27", RTYPE_NUM | 27}, \
1534 {"$28", RTYPE_NUM | 28}, \
1535 {"$29", RTYPE_NUM | 29}, \
1536 {"$30", RTYPE_NUM | 30}, \
1537 {"$31", RTYPE_NUM | 31}
1539 #define FPU_REGISTER_NAMES \
1540 {"$f0", RTYPE_FPU | 0}, \
1541 {"$f1", RTYPE_FPU | 1}, \
1542 {"$f2", RTYPE_FPU | 2}, \
1543 {"$f3", RTYPE_FPU | 3}, \
1544 {"$f4", RTYPE_FPU | 4}, \
1545 {"$f5", RTYPE_FPU | 5}, \
1546 {"$f6", RTYPE_FPU | 6}, \
1547 {"$f7", RTYPE_FPU | 7}, \
1548 {"$f8", RTYPE_FPU | 8}, \
1549 {"$f9", RTYPE_FPU | 9}, \
1550 {"$f10", RTYPE_FPU | 10}, \
1551 {"$f11", RTYPE_FPU | 11}, \
1552 {"$f12", RTYPE_FPU | 12}, \
1553 {"$f13", RTYPE_FPU | 13}, \
1554 {"$f14", RTYPE_FPU | 14}, \
1555 {"$f15", RTYPE_FPU | 15}, \
1556 {"$f16", RTYPE_FPU | 16}, \
1557 {"$f17", RTYPE_FPU | 17}, \
1558 {"$f18", RTYPE_FPU | 18}, \
1559 {"$f19", RTYPE_FPU | 19}, \
1560 {"$f20", RTYPE_FPU | 20}, \
1561 {"$f21", RTYPE_FPU | 21}, \
1562 {"$f22", RTYPE_FPU | 22}, \
1563 {"$f23", RTYPE_FPU | 23}, \
1564 {"$f24", RTYPE_FPU | 24}, \
1565 {"$f25", RTYPE_FPU | 25}, \
1566 {"$f26", RTYPE_FPU | 26}, \
1567 {"$f27", RTYPE_FPU | 27}, \
1568 {"$f28", RTYPE_FPU | 28}, \
1569 {"$f29", RTYPE_FPU | 29}, \
1570 {"$f30", RTYPE_FPU | 30}, \
1571 {"$f31", RTYPE_FPU | 31}
1573 #define FPU_CONDITION_CODE_NAMES \
1574 {"$fcc0", RTYPE_FCC | 0}, \
1575 {"$fcc1", RTYPE_FCC | 1}, \
1576 {"$fcc2", RTYPE_FCC | 2}, \
1577 {"$fcc3", RTYPE_FCC | 3}, \
1578 {"$fcc4", RTYPE_FCC | 4}, \
1579 {"$fcc5", RTYPE_FCC | 5}, \
1580 {"$fcc6", RTYPE_FCC | 6}, \
1581 {"$fcc7", RTYPE_FCC | 7}
1583 #define COPROC_CONDITION_CODE_NAMES \
1584 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1585 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1586 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1587 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1588 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1589 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1590 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1591 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1593 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1594 {"$a4", RTYPE_GP | 8}, \
1595 {"$a5", RTYPE_GP | 9}, \
1596 {"$a6", RTYPE_GP | 10}, \
1597 {"$a7", RTYPE_GP | 11}, \
1598 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1599 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1600 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1601 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1602 {"$t0", RTYPE_GP | 12}, \
1603 {"$t1", RTYPE_GP | 13}, \
1604 {"$t2", RTYPE_GP | 14}, \
1605 {"$t3", RTYPE_GP | 15}
1607 #define O32_SYMBOLIC_REGISTER_NAMES \
1608 {"$t0", RTYPE_GP | 8}, \
1609 {"$t1", RTYPE_GP | 9}, \
1610 {"$t2", RTYPE_GP | 10}, \
1611 {"$t3", RTYPE_GP | 11}, \
1612 {"$t4", RTYPE_GP | 12}, \
1613 {"$t5", RTYPE_GP | 13}, \
1614 {"$t6", RTYPE_GP | 14}, \
1615 {"$t7", RTYPE_GP | 15}, \
1616 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1617 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1618 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1619 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1621 /* Remaining symbolic register names */
1622 #define SYMBOLIC_REGISTER_NAMES \
1623 {"$zero", RTYPE_GP | 0}, \
1624 {"$at", RTYPE_GP | 1}, \
1625 {"$AT", RTYPE_GP | 1}, \
1626 {"$v0", RTYPE_GP | 2}, \
1627 {"$v1", RTYPE_GP | 3}, \
1628 {"$a0", RTYPE_GP | 4}, \
1629 {"$a1", RTYPE_GP | 5}, \
1630 {"$a2", RTYPE_GP | 6}, \
1631 {"$a3", RTYPE_GP | 7}, \
1632 {"$s0", RTYPE_GP | 16}, \
1633 {"$s1", RTYPE_GP | 17}, \
1634 {"$s2", RTYPE_GP | 18}, \
1635 {"$s3", RTYPE_GP | 19}, \
1636 {"$s4", RTYPE_GP | 20}, \
1637 {"$s5", RTYPE_GP | 21}, \
1638 {"$s6", RTYPE_GP | 22}, \
1639 {"$s7", RTYPE_GP | 23}, \
1640 {"$t8", RTYPE_GP | 24}, \
1641 {"$t9", RTYPE_GP | 25}, \
1642 {"$k0", RTYPE_GP | 26}, \
1643 {"$kt0", RTYPE_GP | 26}, \
1644 {"$k1", RTYPE_GP | 27}, \
1645 {"$kt1", RTYPE_GP | 27}, \
1646 {"$gp", RTYPE_GP | 28}, \
1647 {"$sp", RTYPE_GP | 29}, \
1648 {"$s8", RTYPE_GP | 30}, \
1649 {"$fp", RTYPE_GP | 30}, \
1650 {"$ra", RTYPE_GP | 31}
1652 #define MIPS16_SPECIAL_REGISTER_NAMES \
1653 {"$pc", RTYPE_PC | 0}
1655 #define MDMX_VECTOR_REGISTER_NAMES \
1656 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1657 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1658 {"$v2", RTYPE_VEC | 2}, \
1659 {"$v3", RTYPE_VEC | 3}, \
1660 {"$v4", RTYPE_VEC | 4}, \
1661 {"$v5", RTYPE_VEC | 5}, \
1662 {"$v6", RTYPE_VEC | 6}, \
1663 {"$v7", RTYPE_VEC | 7}, \
1664 {"$v8", RTYPE_VEC | 8}, \
1665 {"$v9", RTYPE_VEC | 9}, \
1666 {"$v10", RTYPE_VEC | 10}, \
1667 {"$v11", RTYPE_VEC | 11}, \
1668 {"$v12", RTYPE_VEC | 12}, \
1669 {"$v13", RTYPE_VEC | 13}, \
1670 {"$v14", RTYPE_VEC | 14}, \
1671 {"$v15", RTYPE_VEC | 15}, \
1672 {"$v16", RTYPE_VEC | 16}, \
1673 {"$v17", RTYPE_VEC | 17}, \
1674 {"$v18", RTYPE_VEC | 18}, \
1675 {"$v19", RTYPE_VEC | 19}, \
1676 {"$v20", RTYPE_VEC | 20}, \
1677 {"$v21", RTYPE_VEC | 21}, \
1678 {"$v22", RTYPE_VEC | 22}, \
1679 {"$v23", RTYPE_VEC | 23}, \
1680 {"$v24", RTYPE_VEC | 24}, \
1681 {"$v25", RTYPE_VEC | 25}, \
1682 {"$v26", RTYPE_VEC | 26}, \
1683 {"$v27", RTYPE_VEC | 27}, \
1684 {"$v28", RTYPE_VEC | 28}, \
1685 {"$v29", RTYPE_VEC | 29}, \
1686 {"$v30", RTYPE_VEC | 30}, \
1687 {"$v31", RTYPE_VEC | 31}
1689 #define MIPS_DSP_ACCUMULATOR_NAMES \
1690 {"$ac0", RTYPE_ACC | 0}, \
1691 {"$ac1", RTYPE_ACC | 1}, \
1692 {"$ac2", RTYPE_ACC | 2}, \
1693 {"$ac3", RTYPE_ACC | 3}
1695 static const struct regname reg_names
[] = {
1696 GENERIC_REGISTER_NUMBERS
,
1698 FPU_CONDITION_CODE_NAMES
,
1699 COPROC_CONDITION_CODE_NAMES
,
1701 /* The $txx registers depends on the abi,
1702 these will be added later into the symbol table from
1703 one of the tables below once mips_abi is set after
1704 parsing of arguments from the command line. */
1705 SYMBOLIC_REGISTER_NAMES
,
1707 MIPS16_SPECIAL_REGISTER_NAMES
,
1708 MDMX_VECTOR_REGISTER_NAMES
,
1709 MIPS_DSP_ACCUMULATOR_NAMES
,
1713 static const struct regname reg_names_o32
[] = {
1714 O32_SYMBOLIC_REGISTER_NAMES
,
1718 static const struct regname reg_names_n32n64
[] = {
1719 N32N64_SYMBOLIC_REGISTER_NAMES
,
1724 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1731 /* Find end of name. */
1733 if (is_name_beginner (*e
))
1735 while (is_part_of_name (*e
))
1738 /* Terminate name. */
1742 /* Look for a register symbol. */
1743 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1745 int r
= S_GET_VALUE (symbolP
);
1747 reg
= r
& RNUM_MASK
;
1748 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1749 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1750 reg
= (r
& RNUM_MASK
) - 2;
1752 /* Else see if this is a register defined in an itbl entry. */
1753 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1760 if (itbl_get_reg_val (n
, &r
))
1761 reg
= r
& RNUM_MASK
;
1764 /* Advance to next token if a register was recognised. */
1767 else if (types
& RWARN
)
1768 as_warn ("Unrecognized register name `%s'", *s
);
1776 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1777 architecture. If EXPANSIONP is TRUE then this check is done while
1778 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1781 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1783 int isa
= mips_opts
.isa
;
1786 if (mips_opts
.ase_mdmx
)
1788 if (mips_opts
.ase_dsp
)
1790 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1792 if (mips_opts
.ase_dspr2
)
1794 if (mips_opts
.ase_mt
)
1796 if (mips_opts
.ase_mips3d
)
1798 if (mips_opts
.ase_smartmips
)
1799 isa
|= INSN_SMARTMIPS
;
1801 /* For user code we don't check for mips_opts.mips16 since we want
1802 to allow jalx if -mips16 was specified on the command line. */
1803 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1806 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1809 /* Check whether the instruction or macro requires single-precision or
1810 double-precision floating-point support. Note that this information is
1811 stored differently in the opcode table for insns and macros. */
1812 if (mo
->pinfo
== INSN_MACRO
)
1814 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1815 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1819 fp_s
= mo
->pinfo
& FP_S
;
1820 fp_d
= mo
->pinfo
& FP_D
;
1823 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1826 if (fp_s
&& mips_opts
.soft_float
)
1832 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1833 selected ISA and architecture. */
1836 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1838 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1841 /* This function is called once, at assembler startup time. It should set up
1842 all the tables, etc. that the MD part of the assembler will need. */
1847 const char *retval
= NULL
;
1851 if (mips_pic
!= NO_PIC
)
1853 if (g_switch_seen
&& g_switch_value
!= 0)
1854 as_bad (_("-G may not be used in position-independent code"));
1858 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1859 as_warn (_("Could not set architecture and machine"));
1861 op_hash
= hash_new ();
1863 for (i
= 0; i
< NUMOPCODES
;)
1865 const char *name
= mips_opcodes
[i
].name
;
1867 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1870 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1871 mips_opcodes
[i
].name
, retval
);
1872 /* Probably a memory allocation problem? Give up now. */
1873 as_fatal (_("Broken assembler. No assembly attempted."));
1877 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1879 if (!validate_mips_insn (&mips_opcodes
[i
]))
1881 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1883 create_insn (&nop_insn
, mips_opcodes
+ i
);
1884 nop_insn
.fixed_p
= 1;
1889 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1892 mips16_op_hash
= hash_new ();
1895 while (i
< bfd_mips16_num_opcodes
)
1897 const char *name
= mips16_opcodes
[i
].name
;
1899 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1901 as_fatal (_("internal: can't hash `%s': %s"),
1902 mips16_opcodes
[i
].name
, retval
);
1905 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1906 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1907 != mips16_opcodes
[i
].match
))
1909 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1910 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1913 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1915 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1916 mips16_nop_insn
.fixed_p
= 1;
1920 while (i
< bfd_mips16_num_opcodes
1921 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1925 as_fatal (_("Broken assembler. No assembly attempted."));
1927 /* We add all the general register names to the symbol table. This
1928 helps us detect invalid uses of them. */
1929 for (i
= 0; reg_names
[i
].name
; i
++)
1930 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1931 reg_names
[i
].num
, // & RNUM_MASK,
1932 &zero_address_frag
));
1934 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1935 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1936 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1937 &zero_address_frag
));
1939 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1940 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1941 reg_names_o32
[i
].num
, // & RNUM_MASK,
1942 &zero_address_frag
));
1944 mips_no_prev_insn ();
1947 mips_cprmask
[0] = 0;
1948 mips_cprmask
[1] = 0;
1949 mips_cprmask
[2] = 0;
1950 mips_cprmask
[3] = 0;
1952 /* set the default alignment for the text section (2**2) */
1953 record_alignment (text_section
, 2);
1955 bfd_set_gp_size (stdoutput
, g_switch_value
);
1960 /* On a native system other than VxWorks, sections must be aligned
1961 to 16 byte boundaries. When configured for an embedded ELF
1962 target, we don't bother. */
1963 if (strncmp (TARGET_OS
, "elf", 3) != 0
1964 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1966 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1967 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1968 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1971 /* Create a .reginfo section for register masks and a .mdebug
1972 section for debugging information. */
1980 subseg
= now_subseg
;
1982 /* The ABI says this section should be loaded so that the
1983 running program can access it. However, we don't load it
1984 if we are configured for an embedded target */
1985 flags
= SEC_READONLY
| SEC_DATA
;
1986 if (strncmp (TARGET_OS
, "elf", 3) != 0)
1987 flags
|= SEC_ALLOC
| SEC_LOAD
;
1989 if (mips_abi
!= N64_ABI
)
1991 sec
= subseg_new (".reginfo", (subsegT
) 0);
1993 bfd_set_section_flags (stdoutput
, sec
, flags
);
1994 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1996 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2000 /* The 64-bit ABI uses a .MIPS.options section rather than
2001 .reginfo section. */
2002 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2003 bfd_set_section_flags (stdoutput
, sec
, flags
);
2004 bfd_set_section_alignment (stdoutput
, sec
, 3);
2006 /* Set up the option header. */
2008 Elf_Internal_Options opthdr
;
2011 opthdr
.kind
= ODK_REGINFO
;
2012 opthdr
.size
= (sizeof (Elf_External_Options
)
2013 + sizeof (Elf64_External_RegInfo
));
2016 f
= frag_more (sizeof (Elf_External_Options
));
2017 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2018 (Elf_External_Options
*) f
);
2020 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2024 if (ECOFF_DEBUGGING
)
2026 sec
= subseg_new (".mdebug", (subsegT
) 0);
2027 (void) bfd_set_section_flags (stdoutput
, sec
,
2028 SEC_HAS_CONTENTS
| SEC_READONLY
);
2029 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2031 else if (mips_flag_pdr
)
2033 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2034 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2035 SEC_READONLY
| SEC_RELOC
2037 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2040 subseg_set (seg
, subseg
);
2043 #endif /* OBJ_ELF */
2045 if (! ECOFF_DEBUGGING
)
2048 if (mips_fix_vr4120
)
2049 init_vr4120_conflicts ();
2055 if (! ECOFF_DEBUGGING
)
2060 md_assemble (char *str
)
2062 struct mips_cl_insn insn
;
2063 bfd_reloc_code_real_type unused_reloc
[3]
2064 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2066 imm_expr
.X_op
= O_absent
;
2067 imm2_expr
.X_op
= O_absent
;
2068 offset_expr
.X_op
= O_absent
;
2069 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2070 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2071 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2072 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2073 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2074 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2076 if (mips_opts
.mips16
)
2077 mips16_ip (str
, &insn
);
2080 mips_ip (str
, &insn
);
2081 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2082 str
, insn
.insn_opcode
));
2087 as_bad ("%s `%s'", insn_error
, str
);
2091 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2094 if (mips_opts
.mips16
)
2095 mips16_macro (&insn
);
2102 if (imm_expr
.X_op
!= O_absent
)
2103 append_insn (&insn
, &imm_expr
, imm_reloc
);
2104 else if (offset_expr
.X_op
!= O_absent
)
2105 append_insn (&insn
, &offset_expr
, offset_reloc
);
2107 append_insn (&insn
, NULL
, unused_reloc
);
2111 /* Return true if the given relocation might need a matching %lo().
2112 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2113 need a matching %lo() when applied to local symbols. */
2115 static inline bfd_boolean
2116 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2118 return (HAVE_IN_PLACE_ADDENDS
2119 && (reloc
== BFD_RELOC_HI16_S
2120 || reloc
== BFD_RELOC_MIPS16_HI16_S
2121 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2122 all GOT16 relocations evaluate to "G". */
2123 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
2126 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2129 static inline bfd_boolean
2130 fixup_has_matching_lo_p (fixS
*fixp
)
2132 return (fixp
->fx_next
!= NULL
2133 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2134 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2135 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2136 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2139 /* See whether instruction IP reads register REG. CLASS is the type
2143 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2144 enum mips_regclass
class)
2146 if (class == MIPS16_REG
)
2148 assert (mips_opts
.mips16
);
2149 reg
= mips16_to_32_reg_map
[reg
];
2150 class = MIPS_GR_REG
;
2153 /* Don't report on general register ZERO, since it never changes. */
2154 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2157 if (class == MIPS_FP_REG
)
2159 assert (! mips_opts
.mips16
);
2160 /* If we are called with either $f0 or $f1, we must check $f0.
2161 This is not optimal, because it will introduce an unnecessary
2162 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2163 need to distinguish reading both $f0 and $f1 or just one of
2164 them. Note that we don't have to check the other way,
2165 because there is no instruction that sets both $f0 and $f1
2166 and requires a delay. */
2167 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2168 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2169 == (reg
&~ (unsigned) 1)))
2171 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2172 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2173 == (reg
&~ (unsigned) 1)))
2176 else if (! mips_opts
.mips16
)
2178 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2179 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2181 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2182 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2187 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2188 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2190 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2191 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2193 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2194 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2197 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2199 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2201 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2203 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2204 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2211 /* This function returns true if modifying a register requires a
2215 reg_needs_delay (unsigned int reg
)
2217 unsigned long prev_pinfo
;
2219 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2220 if (! mips_opts
.noreorder
2221 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2222 && ! gpr_interlocks
)
2223 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2224 && ! cop_interlocks
)))
2226 /* A load from a coprocessor or from memory. All load delays
2227 delay the use of general register rt for one instruction. */
2228 /* Itbl support may require additional care here. */
2229 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2230 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2237 /* Move all labels in insn_labels to the current insertion point. */
2240 mips_move_labels (void)
2242 segment_info_type
*si
= seg_info (now_seg
);
2243 struct insn_label_list
*l
;
2246 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2248 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2249 symbol_set_frag (l
->label
, frag_now
);
2250 val
= (valueT
) frag_now_fix ();
2251 /* mips16 text labels are stored as odd. */
2252 if (mips_opts
.mips16
)
2254 S_SET_VALUE (l
->label
, val
);
2259 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2261 bfd_boolean linkonce
= FALSE
;
2262 segT symseg
= S_GET_SEGMENT (sym
);
2264 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2266 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2269 /* The GNU toolchain uses an extension for ELF: a section
2270 beginning with the magic string .gnu.linkonce is a
2271 linkonce section. */
2272 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2273 sizeof ".gnu.linkonce" - 1) == 0)
2280 /* Mark instruction labels in mips16 mode. This permits the linker to
2281 handle them specially, such as generating jalx instructions when
2282 needed. We also make them odd for the duration of the assembly, in
2283 order to generate the right sort of code. We will make them even
2284 in the adjust_symtab routine, while leaving them marked. This is
2285 convenient for the debugger and the disassembler. The linker knows
2286 to make them odd again. */
2289 mips16_mark_labels (void)
2291 segment_info_type
*si
= seg_info (now_seg
);
2292 struct insn_label_list
*l
;
2294 if (!mips_opts
.mips16
)
2297 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2299 symbolS
*label
= l
->label
;
2301 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2303 S_SET_OTHER (label
, STO_MIPS16
);
2305 if ((S_GET_VALUE (label
) & 1) == 0
2306 /* Don't adjust the address if the label is global or weak, or
2307 in a link-once section, since we'll be emitting symbol reloc
2308 references to it which will be patched up by the linker, and
2309 the final value of the symbol may or may not be MIPS16. */
2310 && ! S_IS_WEAK (label
)
2311 && ! S_IS_EXTERNAL (label
)
2312 && ! s_is_linkonce (label
, now_seg
))
2313 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2317 /* End the current frag. Make it a variant frag and record the
2321 relax_close_frag (void)
2323 mips_macro_warning
.first_frag
= frag_now
;
2324 frag_var (rs_machine_dependent
, 0, 0,
2325 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2326 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2328 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2329 mips_relax
.first_fixup
= 0;
2332 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2333 See the comment above RELAX_ENCODE for more details. */
2336 relax_start (symbolS
*symbol
)
2338 assert (mips_relax
.sequence
== 0);
2339 mips_relax
.sequence
= 1;
2340 mips_relax
.symbol
= symbol
;
2343 /* Start generating the second version of a relaxable sequence.
2344 See the comment above RELAX_ENCODE for more details. */
2349 assert (mips_relax
.sequence
== 1);
2350 mips_relax
.sequence
= 2;
2353 /* End the current relaxable sequence. */
2358 assert (mips_relax
.sequence
== 2);
2359 relax_close_frag ();
2360 mips_relax
.sequence
= 0;
2363 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2364 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2365 by VR4120 errata. */
2368 classify_vr4120_insn (const char *name
)
2370 if (strncmp (name
, "macc", 4) == 0)
2371 return FIX_VR4120_MACC
;
2372 if (strncmp (name
, "dmacc", 5) == 0)
2373 return FIX_VR4120_DMACC
;
2374 if (strncmp (name
, "mult", 4) == 0)
2375 return FIX_VR4120_MULT
;
2376 if (strncmp (name
, "dmult", 5) == 0)
2377 return FIX_VR4120_DMULT
;
2378 if (strstr (name
, "div"))
2379 return FIX_VR4120_DIV
;
2380 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2381 return FIX_VR4120_MTHILO
;
2382 return NUM_FIX_VR4120_CLASSES
;
2385 /* Return the number of instructions that must separate INSN1 and INSN2,
2386 where INSN1 is the earlier instruction. Return the worst-case value
2387 for any INSN2 if INSN2 is null. */
2390 insns_between (const struct mips_cl_insn
*insn1
,
2391 const struct mips_cl_insn
*insn2
)
2393 unsigned long pinfo1
, pinfo2
;
2395 /* This function needs to know which pinfo flags are set for INSN2
2396 and which registers INSN2 uses. The former is stored in PINFO2 and
2397 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2398 will have every flag set and INSN2_USES_REG will always return true. */
2399 pinfo1
= insn1
->insn_mo
->pinfo
;
2400 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2402 #define INSN2_USES_REG(REG, CLASS) \
2403 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2405 /* For most targets, write-after-read dependencies on the HI and LO
2406 registers must be separated by at least two instructions. */
2407 if (!hilo_interlocks
)
2409 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2411 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2415 /* If we're working around r7000 errata, there must be two instructions
2416 between an mfhi or mflo and any instruction that uses the result. */
2417 if (mips_7000_hilo_fix
2418 && MF_HILO_INSN (pinfo1
)
2419 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2422 /* If working around VR4120 errata, check for combinations that need
2423 a single intervening instruction. */
2424 if (mips_fix_vr4120
)
2426 unsigned int class1
, class2
;
2428 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2429 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2433 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2434 if (vr4120_conflicts
[class1
] & (1 << class2
))
2439 if (!mips_opts
.mips16
)
2441 /* Check for GPR or coprocessor load delays. All such delays
2442 are on the RT register. */
2443 /* Itbl support may require additional care here. */
2444 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2445 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2447 know (pinfo1
& INSN_WRITE_GPR_T
);
2448 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2452 /* Check for generic coprocessor hazards.
2454 This case is not handled very well. There is no special
2455 knowledge of CP0 handling, and the coprocessors other than
2456 the floating point unit are not distinguished at all. */
2457 /* Itbl support may require additional care here. FIXME!
2458 Need to modify this to include knowledge about
2459 user specified delays! */
2460 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2461 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2463 /* Handle cases where INSN1 writes to a known general coprocessor
2464 register. There must be a one instruction delay before INSN2
2465 if INSN2 reads that register, otherwise no delay is needed. */
2466 if (pinfo1
& INSN_WRITE_FPR_T
)
2468 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2471 else if (pinfo1
& INSN_WRITE_FPR_S
)
2473 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2478 /* Read-after-write dependencies on the control registers
2479 require a two-instruction gap. */
2480 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2481 && (pinfo2
& INSN_READ_COND_CODE
))
2484 /* We don't know exactly what INSN1 does. If INSN2 is
2485 also a coprocessor instruction, assume there must be
2486 a one instruction gap. */
2487 if (pinfo2
& INSN_COP
)
2492 /* Check for read-after-write dependencies on the coprocessor
2493 control registers in cases where INSN1 does not need a general
2494 coprocessor delay. This means that INSN1 is a floating point
2495 comparison instruction. */
2496 /* Itbl support may require additional care here. */
2497 else if (!cop_interlocks
2498 && (pinfo1
& INSN_WRITE_COND_CODE
)
2499 && (pinfo2
& INSN_READ_COND_CODE
))
2503 #undef INSN2_USES_REG
2508 /* Return the number of nops that would be needed to work around the
2509 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2510 the MAX_VR4130_NOPS instructions described by HISTORY. */
2513 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2514 const struct mips_cl_insn
*insn
)
2518 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2519 are not affected by the errata. */
2521 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2522 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2523 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2526 /* Search for the first MFLO or MFHI. */
2527 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2528 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2530 /* Extract the destination register. */
2531 if (mips_opts
.mips16
)
2532 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2534 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2536 /* No nops are needed if INSN reads that register. */
2537 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2540 /* ...or if any of the intervening instructions do. */
2541 for (j
= 0; j
< i
; j
++)
2542 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2545 return MAX_VR4130_NOPS
- i
;
2550 /* Return the number of nops that would be needed if instruction INSN
2551 immediately followed the MAX_NOPS instructions given by HISTORY,
2552 where HISTORY[0] is the most recent instruction. If INSN is null,
2553 return the worse-case number of nops for any instruction. */
2556 nops_for_insn (const struct mips_cl_insn
*history
,
2557 const struct mips_cl_insn
*insn
)
2559 int i
, nops
, tmp_nops
;
2562 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2563 if (!history
[i
].noreorder_p
)
2565 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2566 if (tmp_nops
> nops
)
2570 if (mips_fix_vr4130
)
2572 tmp_nops
= nops_for_vr4130 (history
, insn
);
2573 if (tmp_nops
> nops
)
2580 /* The variable arguments provide NUM_INSNS extra instructions that
2581 might be added to HISTORY. Return the largest number of nops that
2582 would be needed after the extended sequence. */
2585 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2588 struct mips_cl_insn buffer
[MAX_NOPS
];
2589 struct mips_cl_insn
*cursor
;
2592 va_start (args
, history
);
2593 cursor
= buffer
+ num_insns
;
2594 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2595 while (cursor
> buffer
)
2596 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2598 nops
= nops_for_insn (buffer
, NULL
);
2603 /* Like nops_for_insn, but if INSN is a branch, take into account the
2604 worst-case delay for the branch target. */
2607 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2608 const struct mips_cl_insn
*insn
)
2612 nops
= nops_for_insn (history
, insn
);
2613 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2614 | INSN_COND_BRANCH_DELAY
2615 | INSN_COND_BRANCH_LIKELY
))
2617 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2618 if (tmp_nops
> nops
)
2621 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2623 tmp_nops
= nops_for_sequence (1, history
, insn
);
2624 if (tmp_nops
> nops
)
2630 /* Output an instruction. IP is the instruction information.
2631 ADDRESS_EXPR is an operand of the instruction to be used with
2635 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2636 bfd_reloc_code_real_type
*reloc_type
)
2638 unsigned long prev_pinfo
, pinfo
;
2639 relax_stateT prev_insn_frag_type
= 0;
2640 bfd_boolean relaxed_branch
= FALSE
;
2641 segment_info_type
*si
= seg_info (now_seg
);
2643 /* Mark instruction labels in mips16 mode. */
2644 mips16_mark_labels ();
2646 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2647 pinfo
= ip
->insn_mo
->pinfo
;
2649 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2651 /* There are a lot of optimizations we could do that we don't.
2652 In particular, we do not, in general, reorder instructions.
2653 If you use gcc with optimization, it will reorder
2654 instructions and generally do much more optimization then we
2655 do here; repeating all that work in the assembler would only
2656 benefit hand written assembly code, and does not seem worth
2658 int nops
= (mips_optimize
== 0
2659 ? nops_for_insn (history
, NULL
)
2660 : nops_for_insn_or_target (history
, ip
));
2664 unsigned long old_frag_offset
;
2667 old_frag
= frag_now
;
2668 old_frag_offset
= frag_now_fix ();
2670 for (i
= 0; i
< nops
; i
++)
2675 listing_prev_line ();
2676 /* We may be at the start of a variant frag. In case we
2677 are, make sure there is enough space for the frag
2678 after the frags created by listing_prev_line. The
2679 argument to frag_grow here must be at least as large
2680 as the argument to all other calls to frag_grow in
2681 this file. We don't have to worry about being in the
2682 middle of a variant frag, because the variants insert
2683 all needed nop instructions themselves. */
2687 mips_move_labels ();
2689 #ifndef NO_ECOFF_DEBUGGING
2690 if (ECOFF_DEBUGGING
)
2691 ecoff_fix_loc (old_frag
, old_frag_offset
);
2695 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2697 /* Work out how many nops in prev_nop_frag are needed by IP. */
2698 int nops
= nops_for_insn_or_target (history
, ip
);
2699 assert (nops
<= prev_nop_frag_holds
);
2701 /* Enforce NOPS as a minimum. */
2702 if (nops
> prev_nop_frag_required
)
2703 prev_nop_frag_required
= nops
;
2705 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2707 /* Settle for the current number of nops. Update the history
2708 accordingly (for the benefit of any future .set reorder code). */
2709 prev_nop_frag
= NULL
;
2710 insert_into_history (prev_nop_frag_since
,
2711 prev_nop_frag_holds
, NOP_INSN
);
2715 /* Allow this instruction to replace one of the nops that was
2716 tentatively added to prev_nop_frag. */
2717 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2718 prev_nop_frag_holds
--;
2719 prev_nop_frag_since
++;
2724 /* The value passed to dwarf2_emit_insn is the distance between
2725 the beginning of the current instruction and the address that
2726 should be recorded in the debug tables. For MIPS16 debug info
2727 we want to use ISA-encoded addresses, so we pass -1 for an
2728 address higher by one than the current. */
2729 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2732 /* Record the frag type before frag_var. */
2733 if (history
[0].frag
)
2734 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2737 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2738 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2739 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2740 && mips_relax_branch
2741 /* Don't try branch relaxation within .set nomacro, or within
2742 .set noat if we use $at for PIC computations. If it turns
2743 out that the branch was out-of-range, we'll get an error. */
2744 && !mips_opts
.warn_about_macros
2745 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2746 && !mips_opts
.mips16
)
2748 relaxed_branch
= TRUE
;
2749 add_relaxed_insn (ip
, (relaxed_branch_length
2751 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2752 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2755 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2756 pinfo
& INSN_COND_BRANCH_LIKELY
,
2757 pinfo
& INSN_WRITE_GPR_31
,
2759 address_expr
->X_add_symbol
,
2760 address_expr
->X_add_number
);
2761 *reloc_type
= BFD_RELOC_UNUSED
;
2763 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2765 /* We need to set up a variant frag. */
2766 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2767 add_relaxed_insn (ip
, 4, 0,
2769 (*reloc_type
- BFD_RELOC_UNUSED
,
2770 mips16_small
, mips16_ext
,
2771 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2772 history
[0].mips16_absolute_jump_p
),
2773 make_expr_symbol (address_expr
), 0);
2775 else if (mips_opts
.mips16
2777 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2779 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2780 /* Make sure there is enough room to swap this instruction with
2781 a following jump instruction. */
2783 add_fixed_insn (ip
);
2787 if (mips_opts
.mips16
2788 && mips_opts
.noreorder
2789 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2790 as_warn (_("extended instruction in delay slot"));
2792 if (mips_relax
.sequence
)
2794 /* If we've reached the end of this frag, turn it into a variant
2795 frag and record the information for the instructions we've
2797 if (frag_room () < 4)
2798 relax_close_frag ();
2799 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2802 if (mips_relax
.sequence
!= 2)
2803 mips_macro_warning
.sizes
[0] += 4;
2804 if (mips_relax
.sequence
!= 1)
2805 mips_macro_warning
.sizes
[1] += 4;
2807 if (mips_opts
.mips16
)
2810 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2812 add_fixed_insn (ip
);
2815 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2817 if (address_expr
->X_op
== O_constant
)
2821 switch (*reloc_type
)
2824 ip
->insn_opcode
|= address_expr
->X_add_number
;
2827 case BFD_RELOC_MIPS_HIGHEST
:
2828 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2829 ip
->insn_opcode
|= tmp
& 0xffff;
2832 case BFD_RELOC_MIPS_HIGHER
:
2833 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2834 ip
->insn_opcode
|= tmp
& 0xffff;
2837 case BFD_RELOC_HI16_S
:
2838 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2839 ip
->insn_opcode
|= tmp
& 0xffff;
2842 case BFD_RELOC_HI16
:
2843 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2846 case BFD_RELOC_UNUSED
:
2847 case BFD_RELOC_LO16
:
2848 case BFD_RELOC_MIPS_GOT_DISP
:
2849 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2852 case BFD_RELOC_MIPS_JMP
:
2853 if ((address_expr
->X_add_number
& 3) != 0)
2854 as_bad (_("jump to misaligned address (0x%lx)"),
2855 (unsigned long) address_expr
->X_add_number
);
2856 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2859 case BFD_RELOC_MIPS16_JMP
:
2860 if ((address_expr
->X_add_number
& 3) != 0)
2861 as_bad (_("jump to misaligned address (0x%lx)"),
2862 (unsigned long) address_expr
->X_add_number
);
2864 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2865 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2866 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2869 case BFD_RELOC_16_PCREL_S2
:
2870 if ((address_expr
->X_add_number
& 3) != 0)
2871 as_bad (_("branch to misaligned address (0x%lx)"),
2872 (unsigned long) address_expr
->X_add_number
);
2873 if (mips_relax_branch
)
2875 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2876 as_bad (_("branch address range overflow (0x%lx)"),
2877 (unsigned long) address_expr
->X_add_number
);
2878 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2885 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2888 reloc_howto_type
*howto
;
2891 /* In a compound relocation, it is the final (outermost)
2892 operator that determines the relocated field. */
2893 for (i
= 1; i
< 3; i
++)
2894 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2897 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2898 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2899 bfd_get_reloc_size (howto
),
2901 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2904 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2905 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2906 && ip
->fixp
[0]->fx_addsy
)
2907 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2909 /* These relocations can have an addend that won't fit in
2910 4 octets for 64bit assembly. */
2912 && ! howto
->partial_inplace
2913 && (reloc_type
[0] == BFD_RELOC_16
2914 || reloc_type
[0] == BFD_RELOC_32
2915 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2916 || reloc_type
[0] == BFD_RELOC_HI16_S
2917 || reloc_type
[0] == BFD_RELOC_LO16
2918 || reloc_type
[0] == BFD_RELOC_GPREL16
2919 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2920 || reloc_type
[0] == BFD_RELOC_GPREL32
2921 || reloc_type
[0] == BFD_RELOC_64
2922 || reloc_type
[0] == BFD_RELOC_CTOR
2923 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2924 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2925 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2926 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2927 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2928 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2929 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2930 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2931 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2932 ip
->fixp
[0]->fx_no_overflow
= 1;
2934 if (mips_relax
.sequence
)
2936 if (mips_relax
.first_fixup
== 0)
2937 mips_relax
.first_fixup
= ip
->fixp
[0];
2939 else if (reloc_needs_lo_p (*reloc_type
))
2941 struct mips_hi_fixup
*hi_fixup
;
2943 /* Reuse the last entry if it already has a matching %lo. */
2944 hi_fixup
= mips_hi_fixup_list
;
2946 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2948 hi_fixup
= ((struct mips_hi_fixup
*)
2949 xmalloc (sizeof (struct mips_hi_fixup
)));
2950 hi_fixup
->next
= mips_hi_fixup_list
;
2951 mips_hi_fixup_list
= hi_fixup
;
2953 hi_fixup
->fixp
= ip
->fixp
[0];
2954 hi_fixup
->seg
= now_seg
;
2957 /* Add fixups for the second and third relocations, if given.
2958 Note that the ABI allows the second relocation to be
2959 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2960 moment we only use RSS_UNDEF, but we could add support
2961 for the others if it ever becomes necessary. */
2962 for (i
= 1; i
< 3; i
++)
2963 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2965 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2966 ip
->fixp
[0]->fx_size
, NULL
, 0,
2967 FALSE
, reloc_type
[i
]);
2969 /* Use fx_tcbit to mark compound relocs. */
2970 ip
->fixp
[0]->fx_tcbit
= 1;
2971 ip
->fixp
[i
]->fx_tcbit
= 1;
2977 /* Update the register mask information. */
2978 if (! mips_opts
.mips16
)
2980 if (pinfo
& INSN_WRITE_GPR_D
)
2981 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2982 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2983 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2984 if (pinfo
& INSN_READ_GPR_S
)
2985 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2986 if (pinfo
& INSN_WRITE_GPR_31
)
2987 mips_gprmask
|= 1 << RA
;
2988 if (pinfo
& INSN_WRITE_FPR_D
)
2989 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2990 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2991 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2992 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2993 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2994 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2995 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2996 if (pinfo
& INSN_COP
)
2998 /* We don't keep enough information to sort these cases out.
2999 The itbl support does keep this information however, although
3000 we currently don't support itbl fprmats as part of the cop
3001 instruction. May want to add this support in the future. */
3003 /* Never set the bit for $0, which is always zero. */
3004 mips_gprmask
&= ~1 << 0;
3008 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3009 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3010 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3011 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3012 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3013 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3014 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3015 mips_gprmask
|= 1 << TREG
;
3016 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3017 mips_gprmask
|= 1 << SP
;
3018 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3019 mips_gprmask
|= 1 << RA
;
3020 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3021 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3022 if (pinfo
& MIPS16_INSN_READ_Z
)
3023 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3024 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3025 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3028 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3030 /* Filling the branch delay slot is more complex. We try to
3031 switch the branch with the previous instruction, which we can
3032 do if the previous instruction does not set up a condition
3033 that the branch tests and if the branch is not itself the
3034 target of any branch. */
3035 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3036 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3038 if (mips_optimize
< 2
3039 /* If we have seen .set volatile or .set nomove, don't
3041 || mips_opts
.nomove
!= 0
3042 /* We can't swap if the previous instruction's position
3044 || history
[0].fixed_p
3045 /* If the previous previous insn was in a .set
3046 noreorder, we can't swap. Actually, the MIPS
3047 assembler will swap in this situation. However, gcc
3048 configured -with-gnu-as will generate code like
3054 in which we can not swap the bne and INSN. If gcc is
3055 not configured -with-gnu-as, it does not output the
3057 || history
[1].noreorder_p
3058 /* If the branch is itself the target of a branch, we
3059 can not swap. We cheat on this; all we check for is
3060 whether there is a label on this instruction. If
3061 there are any branches to anything other than a
3062 label, users must use .set noreorder. */
3063 || si
->label_list
!= NULL
3064 /* If the previous instruction is in a variant frag
3065 other than this branch's one, we cannot do the swap.
3066 This does not apply to the mips16, which uses variant
3067 frags for different purposes. */
3068 || (! mips_opts
.mips16
3069 && prev_insn_frag_type
== rs_machine_dependent
)
3070 /* Check for conflicts between the branch and the instructions
3071 before the candidate delay slot. */
3072 || nops_for_insn (history
+ 1, ip
) > 0
3073 /* Check for conflicts between the swapped sequence and the
3074 target of the branch. */
3075 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3076 /* We do not swap with a trap instruction, since it
3077 complicates trap handlers to have the trap
3078 instruction be in a delay slot. */
3079 || (prev_pinfo
& INSN_TRAP
)
3080 /* If the branch reads a register that the previous
3081 instruction sets, we can not swap. */
3082 || (! mips_opts
.mips16
3083 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3084 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3086 || (! mips_opts
.mips16
3087 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3088 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3090 || (mips_opts
.mips16
3091 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3093 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3095 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3097 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3099 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3101 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3103 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3104 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3105 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3106 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3107 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3108 && insn_uses_reg (ip
,
3109 MIPS16OP_EXTRACT_REG32R
3110 (history
[0].insn_opcode
),
3112 /* If the branch writes a register that the previous
3113 instruction sets, we can not swap (we know that
3114 branches write only to RD or to $31). */
3115 || (! mips_opts
.mips16
3116 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3117 && (((pinfo
& INSN_WRITE_GPR_D
)
3118 && (EXTRACT_OPERAND (RT
, history
[0])
3119 == EXTRACT_OPERAND (RD
, *ip
)))
3120 || ((pinfo
& INSN_WRITE_GPR_31
)
3121 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3122 || (! mips_opts
.mips16
3123 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3124 && (((pinfo
& INSN_WRITE_GPR_D
)
3125 && (EXTRACT_OPERAND (RD
, history
[0])
3126 == EXTRACT_OPERAND (RD
, *ip
)))
3127 || ((pinfo
& INSN_WRITE_GPR_31
)
3128 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3129 || (mips_opts
.mips16
3130 && (pinfo
& MIPS16_INSN_WRITE_31
)
3131 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3132 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3133 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3135 /* If the branch writes a register that the previous
3136 instruction reads, we can not swap (we know that
3137 branches only write to RD or to $31). */
3138 || (! mips_opts
.mips16
3139 && (pinfo
& INSN_WRITE_GPR_D
)
3140 && insn_uses_reg (&history
[0],
3141 EXTRACT_OPERAND (RD
, *ip
),
3143 || (! mips_opts
.mips16
3144 && (pinfo
& INSN_WRITE_GPR_31
)
3145 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3146 || (mips_opts
.mips16
3147 && (pinfo
& MIPS16_INSN_WRITE_31
)
3148 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3149 /* If one instruction sets a condition code and the
3150 other one uses a condition code, we can not swap. */
3151 || ((pinfo
& INSN_READ_COND_CODE
)
3152 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3153 || ((pinfo
& INSN_WRITE_COND_CODE
)
3154 && (prev_pinfo
& INSN_READ_COND_CODE
))
3155 /* If the previous instruction uses the PC, we can not
3157 || (mips_opts
.mips16
3158 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3159 /* If the previous instruction had a fixup in mips16
3160 mode, we can not swap. This normally means that the
3161 previous instruction was a 4 byte branch anyhow. */
3162 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3163 /* If the previous instruction is a sync, sync.l, or
3164 sync.p, we can not swap. */
3165 || (prev_pinfo
& INSN_SYNC
))
3167 if (mips_opts
.mips16
3168 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3169 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3170 && ISA_SUPPORTS_MIPS16E
)
3172 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3173 ip
->insn_opcode
|= 0x0080;
3175 insert_into_history (0, 1, ip
);
3179 /* We could do even better for unconditional branches to
3180 portions of this object file; we could pick up the
3181 instruction at the destination, put it in the delay
3182 slot, and bump the destination address. */
3183 insert_into_history (0, 1, ip
);
3187 if (mips_relax
.sequence
)
3188 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3192 /* It looks like we can actually do the swap. */
3193 struct mips_cl_insn delay
= history
[0];
3194 if (mips_opts
.mips16
)
3196 know (delay
.frag
== ip
->frag
);
3197 move_insn (ip
, delay
.frag
, delay
.where
);
3198 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3200 else if (relaxed_branch
)
3202 /* Add the delay slot instruction to the end of the
3203 current frag and shrink the fixed part of the
3204 original frag. If the branch occupies the tail of
3205 the latter, move it backwards to cover the gap. */
3206 delay
.frag
->fr_fix
-= 4;
3207 if (delay
.frag
== ip
->frag
)
3208 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3209 add_fixed_insn (&delay
);
3213 move_insn (&delay
, ip
->frag
, ip
->where
);
3214 move_insn (ip
, history
[0].frag
, history
[0].where
);
3218 insert_into_history (0, 1, &delay
);
3221 /* If that was an unconditional branch, forget the previous
3222 insn information. */
3223 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3224 mips_no_prev_insn ();
3226 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3228 /* We don't yet optimize a branch likely. What we should do
3229 is look at the target, copy the instruction found there
3230 into the delay slot, and increment the branch to jump to
3231 the next instruction. */
3232 insert_into_history (0, 1, ip
);
3236 insert_into_history (0, 1, ip
);
3239 insert_into_history (0, 1, ip
);
3241 /* We just output an insn, so the next one doesn't have a label. */
3242 mips_clear_insn_labels ();
3245 /* Forget that there was any previous instruction or label. */
3248 mips_no_prev_insn (void)
3250 prev_nop_frag
= NULL
;
3251 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3252 mips_clear_insn_labels ();
3255 /* This function must be called before we emit something other than
3256 instructions. It is like mips_no_prev_insn except that it inserts
3257 any NOPS that might be needed by previous instructions. */
3260 mips_emit_delays (void)
3262 if (! mips_opts
.noreorder
)
3264 int nops
= nops_for_insn (history
, NULL
);
3268 add_fixed_insn (NOP_INSN
);
3269 mips_move_labels ();
3272 mips_no_prev_insn ();
3275 /* Start a (possibly nested) noreorder block. */
3278 start_noreorder (void)
3280 if (mips_opts
.noreorder
== 0)
3285 /* None of the instructions before the .set noreorder can be moved. */
3286 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3287 history
[i
].fixed_p
= 1;
3289 /* Insert any nops that might be needed between the .set noreorder
3290 block and the previous instructions. We will later remove any
3291 nops that turn out not to be needed. */
3292 nops
= nops_for_insn (history
, NULL
);
3295 if (mips_optimize
!= 0)
3297 /* Record the frag which holds the nop instructions, so
3298 that we can remove them if we don't need them. */
3299 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3300 prev_nop_frag
= frag_now
;
3301 prev_nop_frag_holds
= nops
;
3302 prev_nop_frag_required
= 0;
3303 prev_nop_frag_since
= 0;
3306 for (; nops
> 0; --nops
)
3307 add_fixed_insn (NOP_INSN
);
3309 /* Move on to a new frag, so that it is safe to simply
3310 decrease the size of prev_nop_frag. */
3311 frag_wane (frag_now
);
3313 mips_move_labels ();
3315 mips16_mark_labels ();
3316 mips_clear_insn_labels ();
3318 mips_opts
.noreorder
++;
3319 mips_any_noreorder
= 1;
3322 /* End a nested noreorder block. */
3325 end_noreorder (void)
3327 mips_opts
.noreorder
--;
3328 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3330 /* Commit to inserting prev_nop_frag_required nops and go back to
3331 handling nop insertion the .set reorder way. */
3332 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3333 * (mips_opts
.mips16
? 2 : 4));
3334 insert_into_history (prev_nop_frag_since
,
3335 prev_nop_frag_required
, NOP_INSN
);
3336 prev_nop_frag
= NULL
;
3340 /* Set up global variables for the start of a new macro. */
3345 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3346 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3347 && (history
[0].insn_mo
->pinfo
3348 & (INSN_UNCOND_BRANCH_DELAY
3349 | INSN_COND_BRANCH_DELAY
3350 | INSN_COND_BRANCH_LIKELY
)) != 0);
3353 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3354 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3355 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3358 macro_warning (relax_substateT subtype
)
3360 if (subtype
& RELAX_DELAY_SLOT
)
3361 return _("Macro instruction expanded into multiple instructions"
3362 " in a branch delay slot");
3363 else if (subtype
& RELAX_NOMACRO
)
3364 return _("Macro instruction expanded into multiple instructions");
3369 /* Finish up a macro. Emit warnings as appropriate. */
3374 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3376 relax_substateT subtype
;
3378 /* Set up the relaxation warning flags. */
3380 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3381 subtype
|= RELAX_SECOND_LONGER
;
3382 if (mips_opts
.warn_about_macros
)
3383 subtype
|= RELAX_NOMACRO
;
3384 if (mips_macro_warning
.delay_slot_p
)
3385 subtype
|= RELAX_DELAY_SLOT
;
3387 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3389 /* Either the macro has a single implementation or both
3390 implementations are longer than 4 bytes. Emit the
3392 const char *msg
= macro_warning (subtype
);
3398 /* One implementation might need a warning but the other
3399 definitely doesn't. */
3400 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3405 /* Read a macro's relocation codes from *ARGS and store them in *R.
3406 The first argument in *ARGS will be either the code for a single
3407 relocation or -1 followed by the three codes that make up a
3408 composite relocation. */
3411 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3415 next
= va_arg (*args
, int);
3417 r
[0] = (bfd_reloc_code_real_type
) next
;
3419 for (i
= 0; i
< 3; i
++)
3420 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3423 /* Build an instruction created by a macro expansion. This is passed
3424 a pointer to the count of instructions created so far, an
3425 expression, the name of the instruction to build, an operand format
3426 string, and corresponding arguments. */
3429 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3431 const struct mips_opcode
*mo
;
3432 struct mips_cl_insn insn
;
3433 bfd_reloc_code_real_type r
[3];
3436 va_start (args
, fmt
);
3438 if (mips_opts
.mips16
)
3440 mips16_macro_build (ep
, name
, fmt
, args
);
3445 r
[0] = BFD_RELOC_UNUSED
;
3446 r
[1] = BFD_RELOC_UNUSED
;
3447 r
[2] = BFD_RELOC_UNUSED
;
3448 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3450 assert (strcmp (name
, mo
->name
) == 0);
3454 /* Search until we get a match for NAME. It is assumed here that
3455 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3456 if (strcmp (fmt
, mo
->args
) == 0
3457 && mo
->pinfo
!= INSN_MACRO
3458 && is_opcode_valid (mo
, TRUE
))
3463 assert (strcmp (name
, mo
->name
) == 0);
3466 create_insn (&insn
, mo
);
3484 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3489 /* Note that in the macro case, these arguments are already
3490 in MSB form. (When handling the instruction in the
3491 non-macro case, these arguments are sizes from which
3492 MSB values must be calculated.) */
3493 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3499 /* Note that in the macro case, these arguments are already
3500 in MSBD form. (When handling the instruction in the
3501 non-macro case, these arguments are sizes from which
3502 MSBD values must be calculated.) */
3503 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3507 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3516 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3522 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3526 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3531 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3537 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3542 int tmp
= va_arg (args
, int);
3544 INSERT_OPERAND (RT
, insn
, tmp
);
3545 INSERT_OPERAND (RD
, insn
, tmp
);
3551 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3558 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3562 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3566 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3570 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3574 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3581 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3587 macro_read_relocs (&args
, r
);
3588 assert (*r
== BFD_RELOC_GPREL16
3589 || *r
== BFD_RELOC_MIPS_LITERAL
3590 || *r
== BFD_RELOC_MIPS_HIGHER
3591 || *r
== BFD_RELOC_HI16_S
3592 || *r
== BFD_RELOC_LO16
3593 || *r
== BFD_RELOC_MIPS_GOT16
3594 || *r
== BFD_RELOC_MIPS_CALL16
3595 || *r
== BFD_RELOC_MIPS_GOT_DISP
3596 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3597 || *r
== BFD_RELOC_MIPS_GOT_OFST
3598 || *r
== BFD_RELOC_MIPS_GOT_LO16
3599 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3603 macro_read_relocs (&args
, r
);
3605 && (ep
->X_op
== O_constant
3606 || (ep
->X_op
== O_symbol
3607 && (*r
== BFD_RELOC_MIPS_HIGHEST
3608 || *r
== BFD_RELOC_HI16_S
3609 || *r
== BFD_RELOC_HI16
3610 || *r
== BFD_RELOC_GPREL16
3611 || *r
== BFD_RELOC_MIPS_GOT_HI16
3612 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3616 assert (ep
!= NULL
);
3619 * This allows macro() to pass an immediate expression for
3620 * creating short branches without creating a symbol.
3622 * We don't allow branch relaxation for these branches, as
3623 * they should only appear in ".set nomacro" anyway.
3625 if (ep
->X_op
== O_constant
)
3627 if ((ep
->X_add_number
& 3) != 0)
3628 as_bad (_("branch to misaligned address (0x%lx)"),
3629 (unsigned long) ep
->X_add_number
);
3630 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3631 as_bad (_("branch address range overflow (0x%lx)"),
3632 (unsigned long) ep
->X_add_number
);
3633 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3637 *r
= BFD_RELOC_16_PCREL_S2
;
3641 assert (ep
!= NULL
);
3642 *r
= BFD_RELOC_MIPS_JMP
;
3646 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3650 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3659 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3661 append_insn (&insn
, ep
, r
);
3665 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3668 struct mips_opcode
*mo
;
3669 struct mips_cl_insn insn
;
3670 bfd_reloc_code_real_type r
[3]
3671 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3673 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3675 assert (strcmp (name
, mo
->name
) == 0);
3677 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3681 assert (strcmp (name
, mo
->name
) == 0);
3684 create_insn (&insn
, mo
);
3702 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3707 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3711 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3715 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3725 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3732 regno
= va_arg (args
, int);
3733 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3734 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3755 assert (ep
!= NULL
);
3757 if (ep
->X_op
!= O_constant
)
3758 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3761 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3762 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3765 *r
= BFD_RELOC_UNUSED
;
3771 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3778 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3780 append_insn (&insn
, ep
, r
);
3784 * Sign-extend 32-bit mode constants that have bit 31 set and all
3785 * higher bits unset.
3788 normalize_constant_expr (expressionS
*ex
)
3790 if (ex
->X_op
== O_constant
3791 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3792 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3797 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3798 * all higher bits unset.
3801 normalize_address_expr (expressionS
*ex
)
3803 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3804 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3805 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3806 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3811 * Generate a "jalr" instruction with a relocation hint to the called
3812 * function. This occurs in NewABI PIC code.
3815 macro_build_jalr (expressionS
*ep
)
3824 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3826 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3827 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3831 * Generate a "lui" instruction.
3834 macro_build_lui (expressionS
*ep
, int regnum
)
3836 expressionS high_expr
;
3837 const struct mips_opcode
*mo
;
3838 struct mips_cl_insn insn
;
3839 bfd_reloc_code_real_type r
[3]
3840 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3841 const char *name
= "lui";
3842 const char *fmt
= "t,u";
3844 assert (! mips_opts
.mips16
);
3848 if (high_expr
.X_op
== O_constant
)
3850 /* We can compute the instruction now without a relocation entry. */
3851 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3853 *r
= BFD_RELOC_UNUSED
;
3857 assert (ep
->X_op
== O_symbol
);
3858 /* _gp_disp is a special case, used from s_cpload.
3859 __gnu_local_gp is used if mips_no_shared. */
3860 assert (mips_pic
== NO_PIC
3862 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3863 || (! mips_in_shared
3864 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3865 "__gnu_local_gp") == 0));
3866 *r
= BFD_RELOC_HI16_S
;
3869 mo
= hash_find (op_hash
, name
);
3870 assert (strcmp (name
, mo
->name
) == 0);
3871 assert (strcmp (fmt
, mo
->args
) == 0);
3872 create_insn (&insn
, mo
);
3874 insn
.insn_opcode
= insn
.insn_mo
->match
;
3875 INSERT_OPERAND (RT
, insn
, regnum
);
3876 if (*r
== BFD_RELOC_UNUSED
)
3878 insn
.insn_opcode
|= high_expr
.X_add_number
;
3879 append_insn (&insn
, NULL
, r
);
3882 append_insn (&insn
, &high_expr
, r
);
3885 /* Generate a sequence of instructions to do a load or store from a constant
3886 offset off of a base register (breg) into/from a target register (treg),
3887 using AT if necessary. */
3889 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3890 int treg
, int breg
, int dbl
)
3892 assert (ep
->X_op
== O_constant
);
3894 /* Sign-extending 32-bit constants makes their handling easier. */
3896 normalize_constant_expr (ep
);
3898 /* Right now, this routine can only handle signed 32-bit constants. */
3899 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3900 as_warn (_("operand overflow"));
3902 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3904 /* Signed 16-bit offset will fit in the op. Easy! */
3905 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3909 /* 32-bit offset, need multiple instructions and AT, like:
3910 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3911 addu $tempreg,$tempreg,$breg
3912 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3913 to handle the complete offset. */
3914 macro_build_lui (ep
, AT
);
3915 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3916 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3919 as_bad (_("Macro used $at after \".set noat\""));
3924 * Generates code to set the $at register to true (one)
3925 * if reg is less than the immediate expression.
3928 set_at (int reg
, int unsignedp
)
3930 if (imm_expr
.X_op
== O_constant
3931 && imm_expr
.X_add_number
>= -0x8000
3932 && imm_expr
.X_add_number
< 0x8000)
3933 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3934 AT
, reg
, BFD_RELOC_LO16
);
3937 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3938 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3942 /* Warn if an expression is not a constant. */
3945 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3947 if (ex
->X_op
== O_big
)
3948 as_bad (_("unsupported large constant"));
3949 else if (ex
->X_op
!= O_constant
)
3950 as_bad (_("Instruction %s requires absolute expression"),
3953 if (HAVE_32BIT_GPRS
)
3954 normalize_constant_expr (ex
);
3957 /* Count the leading zeroes by performing a binary chop. This is a
3958 bulky bit of source, but performance is a LOT better for the
3959 majority of values than a simple loop to count the bits:
3960 for (lcnt = 0; (lcnt < 32); lcnt++)
3961 if ((v) & (1 << (31 - lcnt)))
3963 However it is not code size friendly, and the gain will drop a bit
3964 on certain cached systems.
3966 #define COUNT_TOP_ZEROES(v) \
3967 (((v) & ~0xffff) == 0 \
3968 ? ((v) & ~0xff) == 0 \
3969 ? ((v) & ~0xf) == 0 \
3970 ? ((v) & ~0x3) == 0 \
3971 ? ((v) & ~0x1) == 0 \
3976 : ((v) & ~0x7) == 0 \
3979 : ((v) & ~0x3f) == 0 \
3980 ? ((v) & ~0x1f) == 0 \
3983 : ((v) & ~0x7f) == 0 \
3986 : ((v) & ~0xfff) == 0 \
3987 ? ((v) & ~0x3ff) == 0 \
3988 ? ((v) & ~0x1ff) == 0 \
3991 : ((v) & ~0x7ff) == 0 \
3994 : ((v) & ~0x3fff) == 0 \
3995 ? ((v) & ~0x1fff) == 0 \
3998 : ((v) & ~0x7fff) == 0 \
4001 : ((v) & ~0xffffff) == 0 \
4002 ? ((v) & ~0xfffff) == 0 \
4003 ? ((v) & ~0x3ffff) == 0 \
4004 ? ((v) & ~0x1ffff) == 0 \
4007 : ((v) & ~0x7ffff) == 0 \
4010 : ((v) & ~0x3fffff) == 0 \
4011 ? ((v) & ~0x1fffff) == 0 \
4014 : ((v) & ~0x7fffff) == 0 \
4017 : ((v) & ~0xfffffff) == 0 \
4018 ? ((v) & ~0x3ffffff) == 0 \
4019 ? ((v) & ~0x1ffffff) == 0 \
4022 : ((v) & ~0x7ffffff) == 0 \
4025 : ((v) & ~0x3fffffff) == 0 \
4026 ? ((v) & ~0x1fffffff) == 0 \
4029 : ((v) & ~0x7fffffff) == 0 \
4034 * This routine generates the least number of instructions necessary to load
4035 * an absolute expression value into a register.
4038 load_register (int reg
, expressionS
*ep
, int dbl
)
4041 expressionS hi32
, lo32
;
4043 if (ep
->X_op
!= O_big
)
4045 assert (ep
->X_op
== O_constant
);
4047 /* Sign-extending 32-bit constants makes their handling easier. */
4049 normalize_constant_expr (ep
);
4051 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4053 /* We can handle 16 bit signed values with an addiu to
4054 $zero. No need to ever use daddiu here, since $zero and
4055 the result are always correct in 32 bit mode. */
4056 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4059 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4061 /* We can handle 16 bit unsigned values with an ori to
4063 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4066 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4068 /* 32 bit values require an lui. */
4069 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4070 if ((ep
->X_add_number
& 0xffff) != 0)
4071 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4076 /* The value is larger than 32 bits. */
4078 if (!dbl
|| HAVE_32BIT_GPRS
)
4082 sprintf_vma (value
, ep
->X_add_number
);
4083 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4084 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4088 if (ep
->X_op
!= O_big
)
4091 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4092 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4093 hi32
.X_add_number
&= 0xffffffff;
4095 lo32
.X_add_number
&= 0xffffffff;
4099 assert (ep
->X_add_number
> 2);
4100 if (ep
->X_add_number
== 3)
4101 generic_bignum
[3] = 0;
4102 else if (ep
->X_add_number
> 4)
4103 as_bad (_("Number larger than 64 bits"));
4104 lo32
.X_op
= O_constant
;
4105 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4106 hi32
.X_op
= O_constant
;
4107 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4110 if (hi32
.X_add_number
== 0)
4115 unsigned long hi
, lo
;
4117 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4119 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4121 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4124 if (lo32
.X_add_number
& 0x80000000)
4126 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4127 if (lo32
.X_add_number
& 0xffff)
4128 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4133 /* Check for 16bit shifted constant. We know that hi32 is
4134 non-zero, so start the mask on the first bit of the hi32
4139 unsigned long himask
, lomask
;
4143 himask
= 0xffff >> (32 - shift
);
4144 lomask
= (0xffff << shift
) & 0xffffffff;
4148 himask
= 0xffff << (shift
- 32);
4151 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4152 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4156 tmp
.X_op
= O_constant
;
4158 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4159 | (lo32
.X_add_number
>> shift
));
4161 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4162 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4163 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4164 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4169 while (shift
<= (64 - 16));
4171 /* Find the bit number of the lowest one bit, and store the
4172 shifted value in hi/lo. */
4173 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4174 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4178 while ((lo
& 1) == 0)
4183 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4189 while ((hi
& 1) == 0)
4198 /* Optimize if the shifted value is a (power of 2) - 1. */
4199 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4200 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4202 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4207 /* This instruction will set the register to be all
4209 tmp
.X_op
= O_constant
;
4210 tmp
.X_add_number
= (offsetT
) -1;
4211 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4215 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4216 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4218 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4219 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4224 /* Sign extend hi32 before calling load_register, because we can
4225 generally get better code when we load a sign extended value. */
4226 if ((hi32
.X_add_number
& 0x80000000) != 0)
4227 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4228 load_register (reg
, &hi32
, 0);
4231 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4235 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4243 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4245 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4246 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4252 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4256 mid16
.X_add_number
>>= 16;
4257 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4258 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4261 if ((lo32
.X_add_number
& 0xffff) != 0)
4262 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4266 load_delay_nop (void)
4268 if (!gpr_interlocks
)
4269 macro_build (NULL
, "nop", "");
4272 /* Load an address into a register. */
4275 load_address (int reg
, expressionS
*ep
, int *used_at
)
4277 if (ep
->X_op
!= O_constant
4278 && ep
->X_op
!= O_symbol
)
4280 as_bad (_("expression too complex"));
4281 ep
->X_op
= O_constant
;
4284 if (ep
->X_op
== O_constant
)
4286 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4290 if (mips_pic
== NO_PIC
)
4292 /* If this is a reference to a GP relative symbol, we want
4293 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4295 lui $reg,<sym> (BFD_RELOC_HI16_S)
4296 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4297 If we have an addend, we always use the latter form.
4299 With 64bit address space and a usable $at we want
4300 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4301 lui $at,<sym> (BFD_RELOC_HI16_S)
4302 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4303 daddiu $at,<sym> (BFD_RELOC_LO16)
4307 If $at is already in use, we use a path which is suboptimal
4308 on superscalar processors.
4309 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4310 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4312 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4314 daddiu $reg,<sym> (BFD_RELOC_LO16)
4316 For GP relative symbols in 64bit address space we can use
4317 the same sequence as in 32bit address space. */
4318 if (HAVE_64BIT_SYMBOLS
)
4320 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4321 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4323 relax_start (ep
->X_add_symbol
);
4324 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4325 mips_gp_register
, BFD_RELOC_GPREL16
);
4329 if (*used_at
== 0 && mips_opts
.at
)
4331 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4332 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4333 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4334 BFD_RELOC_MIPS_HIGHER
);
4335 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4336 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4337 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4342 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4343 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4344 BFD_RELOC_MIPS_HIGHER
);
4345 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4346 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4347 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4348 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4351 if (mips_relax
.sequence
)
4356 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4357 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4359 relax_start (ep
->X_add_symbol
);
4360 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4361 mips_gp_register
, BFD_RELOC_GPREL16
);
4364 macro_build_lui (ep
, reg
);
4365 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4366 reg
, reg
, BFD_RELOC_LO16
);
4367 if (mips_relax
.sequence
)
4371 else if (!mips_big_got
)
4375 /* If this is a reference to an external symbol, we want
4376 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4378 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4380 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4381 If there is a constant, it must be added in after.
4383 If we have NewABI, we want
4384 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4385 unless we're referencing a global symbol with a non-zero
4386 offset, in which case cst must be added separately. */
4389 if (ep
->X_add_number
)
4391 ex
.X_add_number
= ep
->X_add_number
;
4392 ep
->X_add_number
= 0;
4393 relax_start (ep
->X_add_symbol
);
4394 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4395 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4396 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4397 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4398 ex
.X_op
= O_constant
;
4399 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4400 reg
, reg
, BFD_RELOC_LO16
);
4401 ep
->X_add_number
= ex
.X_add_number
;
4404 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4405 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4406 if (mips_relax
.sequence
)
4411 ex
.X_add_number
= ep
->X_add_number
;
4412 ep
->X_add_number
= 0;
4413 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4414 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4416 relax_start (ep
->X_add_symbol
);
4418 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4422 if (ex
.X_add_number
!= 0)
4424 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4425 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4426 ex
.X_op
= O_constant
;
4427 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4428 reg
, reg
, BFD_RELOC_LO16
);
4432 else if (mips_big_got
)
4436 /* This is the large GOT case. If this is a reference to an
4437 external symbol, we want
4438 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4440 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4442 Otherwise, for a reference to a local symbol in old ABI, we want
4443 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4445 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4446 If there is a constant, it must be added in after.
4448 In the NewABI, for local symbols, with or without offsets, we want:
4449 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4450 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4454 ex
.X_add_number
= ep
->X_add_number
;
4455 ep
->X_add_number
= 0;
4456 relax_start (ep
->X_add_symbol
);
4457 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4458 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4459 reg
, reg
, mips_gp_register
);
4460 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4461 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4462 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4463 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4464 else if (ex
.X_add_number
)
4466 ex
.X_op
= O_constant
;
4467 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4471 ep
->X_add_number
= ex
.X_add_number
;
4473 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4474 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4475 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4476 BFD_RELOC_MIPS_GOT_OFST
);
4481 ex
.X_add_number
= ep
->X_add_number
;
4482 ep
->X_add_number
= 0;
4483 relax_start (ep
->X_add_symbol
);
4484 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4486 reg
, reg
, mips_gp_register
);
4487 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4488 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4490 if (reg_needs_delay (mips_gp_register
))
4492 /* We need a nop before loading from $gp. This special
4493 check is required because the lui which starts the main
4494 instruction stream does not refer to $gp, and so will not
4495 insert the nop which may be required. */
4496 macro_build (NULL
, "nop", "");
4498 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4499 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4501 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4505 if (ex
.X_add_number
!= 0)
4507 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4508 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4509 ex
.X_op
= O_constant
;
4510 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4518 if (!mips_opts
.at
&& *used_at
== 1)
4519 as_bad (_("Macro used $at after \".set noat\""));
4522 /* Move the contents of register SOURCE into register DEST. */
4525 move_register (int dest
, int source
)
4527 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4531 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4532 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4533 The two alternatives are:
4535 Global symbol Local sybmol
4536 ------------- ------------
4537 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4539 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4541 load_got_offset emits the first instruction and add_got_offset
4542 emits the second for a 16-bit offset or add_got_offset_hilo emits
4543 a sequence to add a 32-bit offset using a scratch register. */
4546 load_got_offset (int dest
, expressionS
*local
)
4551 global
.X_add_number
= 0;
4553 relax_start (local
->X_add_symbol
);
4554 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4555 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4557 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4558 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4563 add_got_offset (int dest
, expressionS
*local
)
4567 global
.X_op
= O_constant
;
4568 global
.X_op_symbol
= NULL
;
4569 global
.X_add_symbol
= NULL
;
4570 global
.X_add_number
= local
->X_add_number
;
4572 relax_start (local
->X_add_symbol
);
4573 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4574 dest
, dest
, BFD_RELOC_LO16
);
4576 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4581 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4584 int hold_mips_optimize
;
4586 global
.X_op
= O_constant
;
4587 global
.X_op_symbol
= NULL
;
4588 global
.X_add_symbol
= NULL
;
4589 global
.X_add_number
= local
->X_add_number
;
4591 relax_start (local
->X_add_symbol
);
4592 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4594 /* Set mips_optimize around the lui instruction to avoid
4595 inserting an unnecessary nop after the lw. */
4596 hold_mips_optimize
= mips_optimize
;
4598 macro_build_lui (&global
, tmp
);
4599 mips_optimize
= hold_mips_optimize
;
4600 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4603 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4608 * This routine implements the seemingly endless macro or synthesized
4609 * instructions and addressing modes in the mips assembly language. Many
4610 * of these macros are simple and are similar to each other. These could
4611 * probably be handled by some kind of table or grammar approach instead of
4612 * this verbose method. Others are not simple macros but are more like
4613 * optimizing code generation.
4614 * One interesting optimization is when several store macros appear
4615 * consecutively that would load AT with the upper half of the same address.
4616 * The ensuing load upper instructions are ommited. This implies some kind
4617 * of global optimization. We currently only optimize within a single macro.
4618 * For many of the load and store macros if the address is specified as a
4619 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4620 * first load register 'at' with zero and use it as the base register. The
4621 * mips assembler simply uses register $zero. Just one tiny optimization
4625 macro (struct mips_cl_insn
*ip
)
4627 unsigned int treg
, sreg
, dreg
, breg
;
4628 unsigned int tempreg
;
4643 bfd_reloc_code_real_type r
;
4644 int hold_mips_optimize
;
4646 assert (! mips_opts
.mips16
);
4648 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4649 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4650 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4651 mask
= ip
->insn_mo
->mask
;
4653 expr1
.X_op
= O_constant
;
4654 expr1
.X_op_symbol
= NULL
;
4655 expr1
.X_add_symbol
= NULL
;
4656 expr1
.X_add_number
= 1;
4670 expr1
.X_add_number
= 8;
4671 macro_build (&expr1
, "bgez", "s,p", sreg
);
4673 macro_build (NULL
, "nop", "", 0);
4675 move_register (dreg
, sreg
);
4676 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4699 if (imm_expr
.X_op
== O_constant
4700 && imm_expr
.X_add_number
>= -0x8000
4701 && imm_expr
.X_add_number
< 0x8000)
4703 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4707 load_register (AT
, &imm_expr
, dbl
);
4708 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4727 if (imm_expr
.X_op
== O_constant
4728 && imm_expr
.X_add_number
>= 0
4729 && imm_expr
.X_add_number
< 0x10000)
4731 if (mask
!= M_NOR_I
)
4732 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4735 macro_build (&imm_expr
, "ori", "t,r,i",
4736 treg
, sreg
, BFD_RELOC_LO16
);
4737 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4743 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4744 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4748 switch (imm_expr
.X_add_number
)
4751 macro_build (NULL
, "nop", "");
4754 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4757 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4758 (int)imm_expr
.X_add_number
);
4777 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4779 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4783 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4784 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4792 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4797 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4801 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4802 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4808 /* check for > max integer */
4809 maxnum
= 0x7fffffff;
4810 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4817 if (imm_expr
.X_op
== O_constant
4818 && imm_expr
.X_add_number
>= maxnum
4819 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4822 /* result is always false */
4824 macro_build (NULL
, "nop", "", 0);
4826 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4829 if (imm_expr
.X_op
!= O_constant
)
4830 as_bad (_("Unsupported large constant"));
4831 ++imm_expr
.X_add_number
;
4835 if (mask
== M_BGEL_I
)
4837 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4839 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4842 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4844 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4847 maxnum
= 0x7fffffff;
4848 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4855 maxnum
= - maxnum
- 1;
4856 if (imm_expr
.X_op
== O_constant
4857 && imm_expr
.X_add_number
<= maxnum
4858 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4861 /* result is always true */
4862 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4863 macro_build (&offset_expr
, "b", "p");
4868 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4878 macro_build (&offset_expr
, likely
? "beql" : "beq",
4883 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4884 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4892 && imm_expr
.X_op
== O_constant
4893 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4895 if (imm_expr
.X_op
!= O_constant
)
4896 as_bad (_("Unsupported large constant"));
4897 ++imm_expr
.X_add_number
;
4901 if (mask
== M_BGEUL_I
)
4903 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4905 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4907 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4913 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4921 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4926 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4930 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4931 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4939 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4946 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4947 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4955 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4960 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4964 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4965 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4971 maxnum
= 0x7fffffff;
4972 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4979 if (imm_expr
.X_op
== O_constant
4980 && imm_expr
.X_add_number
>= maxnum
4981 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4983 if (imm_expr
.X_op
!= O_constant
)
4984 as_bad (_("Unsupported large constant"));
4985 ++imm_expr
.X_add_number
;
4989 if (mask
== M_BLTL_I
)
4991 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4993 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4996 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4998 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5003 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5011 macro_build (&offset_expr
, likely
? "beql" : "beq",
5018 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5019 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5027 && imm_expr
.X_op
== O_constant
5028 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5030 if (imm_expr
.X_op
!= O_constant
)
5031 as_bad (_("Unsupported large constant"));
5032 ++imm_expr
.X_add_number
;
5036 if (mask
== M_BLTUL_I
)
5038 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5040 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5042 macro_build (&offset_expr
, likely
? "beql" : "beq",
5048 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5056 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5061 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5065 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5066 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5076 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5081 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5082 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5090 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5092 as_bad (_("Unsupported large constant"));
5097 pos
= (unsigned long) imm_expr
.X_add_number
;
5098 size
= (unsigned long) imm2_expr
.X_add_number
;
5103 as_bad (_("Improper position (%lu)"), pos
);
5106 if (size
== 0 || size
> 64
5107 || (pos
+ size
- 1) > 63)
5109 as_bad (_("Improper extract size (%lu, position %lu)"),
5114 if (size
<= 32 && pos
< 32)
5119 else if (size
<= 32)
5129 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5138 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5140 as_bad (_("Unsupported large constant"));
5145 pos
= (unsigned long) imm_expr
.X_add_number
;
5146 size
= (unsigned long) imm2_expr
.X_add_number
;
5151 as_bad (_("Improper position (%lu)"), pos
);
5154 if (size
== 0 || size
> 64
5155 || (pos
+ size
- 1) > 63)
5157 as_bad (_("Improper insert size (%lu, position %lu)"),
5162 if (pos
< 32 && (pos
+ size
- 1) < 32)
5177 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5194 as_warn (_("Divide by zero."));
5196 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5198 macro_build (NULL
, "break", "c", 7);
5205 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5206 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5210 expr1
.X_add_number
= 8;
5211 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5212 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5213 macro_build (NULL
, "break", "c", 7);
5215 expr1
.X_add_number
= -1;
5217 load_register (AT
, &expr1
, dbl
);
5218 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5219 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5222 expr1
.X_add_number
= 1;
5223 load_register (AT
, &expr1
, dbl
);
5224 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5228 expr1
.X_add_number
= 0x80000000;
5229 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5233 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5234 /* We want to close the noreorder block as soon as possible, so
5235 that later insns are available for delay slot filling. */
5240 expr1
.X_add_number
= 8;
5241 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5242 macro_build (NULL
, "nop", "", 0);
5244 /* We want to close the noreorder block as soon as possible, so
5245 that later insns are available for delay slot filling. */
5248 macro_build (NULL
, "break", "c", 6);
5250 macro_build (NULL
, s
, "d", dreg
);
5289 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5291 as_warn (_("Divide by zero."));
5293 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5295 macro_build (NULL
, "break", "c", 7);
5298 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5300 if (strcmp (s2
, "mflo") == 0)
5301 move_register (dreg
, sreg
);
5303 move_register (dreg
, 0);
5306 if (imm_expr
.X_op
== O_constant
5307 && imm_expr
.X_add_number
== -1
5308 && s
[strlen (s
) - 1] != 'u')
5310 if (strcmp (s2
, "mflo") == 0)
5312 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5315 move_register (dreg
, 0);
5320 load_register (AT
, &imm_expr
, dbl
);
5321 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5322 macro_build (NULL
, s2
, "d", dreg
);
5344 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5345 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5346 /* We want to close the noreorder block as soon as possible, so
5347 that later insns are available for delay slot filling. */
5352 expr1
.X_add_number
= 8;
5353 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5354 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5356 /* We want to close the noreorder block as soon as possible, so
5357 that later insns are available for delay slot filling. */
5359 macro_build (NULL
, "break", "c", 7);
5361 macro_build (NULL
, s2
, "d", dreg
);
5373 /* Load the address of a symbol into a register. If breg is not
5374 zero, we then add a base register to it. */
5376 if (dbl
&& HAVE_32BIT_GPRS
)
5377 as_warn (_("dla used to load 32-bit register"));
5379 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5380 as_warn (_("la used to load 64-bit address"));
5382 if (offset_expr
.X_op
== O_constant
5383 && offset_expr
.X_add_number
>= -0x8000
5384 && offset_expr
.X_add_number
< 0x8000)
5386 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5387 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5391 if (mips_opts
.at
&& (treg
== breg
))
5401 if (offset_expr
.X_op
!= O_symbol
5402 && offset_expr
.X_op
!= O_constant
)
5404 as_bad (_("expression too complex"));
5405 offset_expr
.X_op
= O_constant
;
5408 if (offset_expr
.X_op
== O_constant
)
5409 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5410 else if (mips_pic
== NO_PIC
)
5412 /* If this is a reference to a GP relative symbol, we want
5413 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5415 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5416 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5417 If we have a constant, we need two instructions anyhow,
5418 so we may as well always use the latter form.
5420 With 64bit address space and a usable $at we want
5421 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5422 lui $at,<sym> (BFD_RELOC_HI16_S)
5423 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5424 daddiu $at,<sym> (BFD_RELOC_LO16)
5426 daddu $tempreg,$tempreg,$at
5428 If $at is already in use, we use a path which is suboptimal
5429 on superscalar processors.
5430 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5431 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5433 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5435 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5437 For GP relative symbols in 64bit address space we can use
5438 the same sequence as in 32bit address space. */
5439 if (HAVE_64BIT_SYMBOLS
)
5441 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5442 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5444 relax_start (offset_expr
.X_add_symbol
);
5445 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5446 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5450 if (used_at
== 0 && mips_opts
.at
)
5452 macro_build (&offset_expr
, "lui", "t,u",
5453 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5454 macro_build (&offset_expr
, "lui", "t,u",
5455 AT
, BFD_RELOC_HI16_S
);
5456 macro_build (&offset_expr
, "daddiu", "t,r,j",
5457 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5458 macro_build (&offset_expr
, "daddiu", "t,r,j",
5459 AT
, AT
, BFD_RELOC_LO16
);
5460 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5461 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5466 macro_build (&offset_expr
, "lui", "t,u",
5467 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5468 macro_build (&offset_expr
, "daddiu", "t,r,j",
5469 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5470 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5471 macro_build (&offset_expr
, "daddiu", "t,r,j",
5472 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5473 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5474 macro_build (&offset_expr
, "daddiu", "t,r,j",
5475 tempreg
, tempreg
, BFD_RELOC_LO16
);
5478 if (mips_relax
.sequence
)
5483 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5484 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5486 relax_start (offset_expr
.X_add_symbol
);
5487 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5488 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5491 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5492 as_bad (_("offset too large"));
5493 macro_build_lui (&offset_expr
, tempreg
);
5494 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5495 tempreg
, tempreg
, BFD_RELOC_LO16
);
5496 if (mips_relax
.sequence
)
5500 else if (!mips_big_got
&& !HAVE_NEWABI
)
5502 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5504 /* If this is a reference to an external symbol, and there
5505 is no constant, we want
5506 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5507 or for lca or if tempreg is PIC_CALL_REG
5508 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5509 For a local symbol, we want
5510 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5512 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5514 If we have a small constant, and this is a reference to
5515 an external symbol, we want
5516 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5518 addiu $tempreg,$tempreg,<constant>
5519 For a local symbol, we want the same instruction
5520 sequence, but we output a BFD_RELOC_LO16 reloc on the
5523 If we have a large constant, and this is a reference to
5524 an external symbol, we want
5525 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5526 lui $at,<hiconstant>
5527 addiu $at,$at,<loconstant>
5528 addu $tempreg,$tempreg,$at
5529 For a local symbol, we want the same instruction
5530 sequence, but we output a BFD_RELOC_LO16 reloc on the
5534 if (offset_expr
.X_add_number
== 0)
5536 if (mips_pic
== SVR4_PIC
5538 && (call
|| tempreg
== PIC_CALL_REG
))
5539 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5541 relax_start (offset_expr
.X_add_symbol
);
5542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5543 lw_reloc_type
, mips_gp_register
);
5546 /* We're going to put in an addu instruction using
5547 tempreg, so we may as well insert the nop right
5552 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5553 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5555 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5556 tempreg
, tempreg
, BFD_RELOC_LO16
);
5558 /* FIXME: If breg == 0, and the next instruction uses
5559 $tempreg, then if this variant case is used an extra
5560 nop will be generated. */
5562 else if (offset_expr
.X_add_number
>= -0x8000
5563 && offset_expr
.X_add_number
< 0x8000)
5565 load_got_offset (tempreg
, &offset_expr
);
5567 add_got_offset (tempreg
, &offset_expr
);
5571 expr1
.X_add_number
= offset_expr
.X_add_number
;
5572 offset_expr
.X_add_number
=
5573 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5574 load_got_offset (tempreg
, &offset_expr
);
5575 offset_expr
.X_add_number
= expr1
.X_add_number
;
5576 /* If we are going to add in a base register, and the
5577 target register and the base register are the same,
5578 then we are using AT as a temporary register. Since
5579 we want to load the constant into AT, we add our
5580 current AT (from the global offset table) and the
5581 register into the register now, and pretend we were
5582 not using a base register. */
5586 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5591 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5595 else if (!mips_big_got
&& HAVE_NEWABI
)
5597 int add_breg_early
= 0;
5599 /* If this is a reference to an external, and there is no
5600 constant, or local symbol (*), with or without a
5602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5603 or for lca or if tempreg is PIC_CALL_REG
5604 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5606 If we have a small constant, and this is a reference to
5607 an external symbol, we want
5608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5609 addiu $tempreg,$tempreg,<constant>
5611 If we have a large constant, and this is a reference to
5612 an external symbol, we want
5613 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5614 lui $at,<hiconstant>
5615 addiu $at,$at,<loconstant>
5616 addu $tempreg,$tempreg,$at
5618 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5619 local symbols, even though it introduces an additional
5622 if (offset_expr
.X_add_number
)
5624 expr1
.X_add_number
= offset_expr
.X_add_number
;
5625 offset_expr
.X_add_number
= 0;
5627 relax_start (offset_expr
.X_add_symbol
);
5628 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5629 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5631 if (expr1
.X_add_number
>= -0x8000
5632 && expr1
.X_add_number
< 0x8000)
5634 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5635 tempreg
, tempreg
, BFD_RELOC_LO16
);
5637 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5641 /* If we are going to add in a base register, and the
5642 target register and the base register are the same,
5643 then we are using AT as a temporary register. Since
5644 we want to load the constant into AT, we add our
5645 current AT (from the global offset table) and the
5646 register into the register now, and pretend we were
5647 not using a base register. */
5652 assert (tempreg
== AT
);
5653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5659 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5660 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5666 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5669 offset_expr
.X_add_number
= expr1
.X_add_number
;
5671 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5672 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5675 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5676 treg
, tempreg
, breg
);
5682 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5684 relax_start (offset_expr
.X_add_symbol
);
5685 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5686 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5688 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5689 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5694 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5695 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5698 else if (mips_big_got
&& !HAVE_NEWABI
)
5701 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5702 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5703 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5705 /* This is the large GOT case. If this is a reference to an
5706 external symbol, and there is no constant, we want
5707 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5708 addu $tempreg,$tempreg,$gp
5709 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5710 or for lca or if tempreg is PIC_CALL_REG
5711 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5712 addu $tempreg,$tempreg,$gp
5713 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5714 For a local symbol, we want
5715 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5717 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5719 If we have a small constant, and this is a reference to
5720 an external symbol, we want
5721 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5722 addu $tempreg,$tempreg,$gp
5723 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5725 addiu $tempreg,$tempreg,<constant>
5726 For a local symbol, we want
5727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5729 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5731 If we have a large constant, and this is a reference to
5732 an external symbol, we want
5733 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5734 addu $tempreg,$tempreg,$gp
5735 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5736 lui $at,<hiconstant>
5737 addiu $at,$at,<loconstant>
5738 addu $tempreg,$tempreg,$at
5739 For a local symbol, we want
5740 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5741 lui $at,<hiconstant>
5742 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5743 addu $tempreg,$tempreg,$at
5746 expr1
.X_add_number
= offset_expr
.X_add_number
;
5747 offset_expr
.X_add_number
= 0;
5748 relax_start (offset_expr
.X_add_symbol
);
5749 gpdelay
= reg_needs_delay (mips_gp_register
);
5750 if (expr1
.X_add_number
== 0 && breg
== 0
5751 && (call
|| tempreg
== PIC_CALL_REG
))
5753 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5754 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5756 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5757 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5758 tempreg
, tempreg
, mips_gp_register
);
5759 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5760 tempreg
, lw_reloc_type
, tempreg
);
5761 if (expr1
.X_add_number
== 0)
5765 /* We're going to put in an addu instruction using
5766 tempreg, so we may as well insert the nop right
5771 else if (expr1
.X_add_number
>= -0x8000
5772 && expr1
.X_add_number
< 0x8000)
5775 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5776 tempreg
, tempreg
, BFD_RELOC_LO16
);
5782 /* If we are going to add in a base register, and the
5783 target register and the base register are the same,
5784 then we are using AT as a temporary register. Since
5785 we want to load the constant into AT, we add our
5786 current AT (from the global offset table) and the
5787 register into the register now, and pretend we were
5788 not using a base register. */
5793 assert (tempreg
== AT
);
5795 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5800 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5801 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5805 offset_expr
.X_add_number
=
5806 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5811 /* This is needed because this instruction uses $gp, but
5812 the first instruction on the main stream does not. */
5813 macro_build (NULL
, "nop", "");
5816 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5817 local_reloc_type
, mips_gp_register
);
5818 if (expr1
.X_add_number
>= -0x8000
5819 && expr1
.X_add_number
< 0x8000)
5822 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5823 tempreg
, tempreg
, BFD_RELOC_LO16
);
5824 /* FIXME: If add_number is 0, and there was no base
5825 register, the external symbol case ended with a load,
5826 so if the symbol turns out to not be external, and
5827 the next instruction uses tempreg, an unnecessary nop
5828 will be inserted. */
5834 /* We must add in the base register now, as in the
5835 external symbol case. */
5836 assert (tempreg
== AT
);
5838 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5841 /* We set breg to 0 because we have arranged to add
5842 it in in both cases. */
5846 macro_build_lui (&expr1
, AT
);
5847 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5848 AT
, AT
, BFD_RELOC_LO16
);
5849 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5850 tempreg
, tempreg
, AT
);
5855 else if (mips_big_got
&& HAVE_NEWABI
)
5857 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5858 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5859 int add_breg_early
= 0;
5861 /* This is the large GOT case. If this is a reference to an
5862 external symbol, and there is no constant, we want
5863 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5864 add $tempreg,$tempreg,$gp
5865 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5866 or for lca or if tempreg is PIC_CALL_REG
5867 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5868 add $tempreg,$tempreg,$gp
5869 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5871 If we have a small constant, and this is a reference to
5872 an external symbol, we want
5873 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5874 add $tempreg,$tempreg,$gp
5875 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5876 addi $tempreg,$tempreg,<constant>
5878 If we have a large constant, and this is a reference to
5879 an external symbol, we want
5880 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5881 addu $tempreg,$tempreg,$gp
5882 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5883 lui $at,<hiconstant>
5884 addi $at,$at,<loconstant>
5885 add $tempreg,$tempreg,$at
5887 If we have NewABI, and we know it's a local symbol, we want
5888 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5889 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5890 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5892 relax_start (offset_expr
.X_add_symbol
);
5894 expr1
.X_add_number
= offset_expr
.X_add_number
;
5895 offset_expr
.X_add_number
= 0;
5897 if (expr1
.X_add_number
== 0 && breg
== 0
5898 && (call
|| tempreg
== PIC_CALL_REG
))
5900 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5901 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5903 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5904 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5905 tempreg
, tempreg
, mips_gp_register
);
5906 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5907 tempreg
, lw_reloc_type
, tempreg
);
5909 if (expr1
.X_add_number
== 0)
5911 else if (expr1
.X_add_number
>= -0x8000
5912 && expr1
.X_add_number
< 0x8000)
5914 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5915 tempreg
, tempreg
, BFD_RELOC_LO16
);
5917 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5921 /* If we are going to add in a base register, and the
5922 target register and the base register are the same,
5923 then we are using AT as a temporary register. Since
5924 we want to load the constant into AT, we add our
5925 current AT (from the global offset table) and the
5926 register into the register now, and pretend we were
5927 not using a base register. */
5932 assert (tempreg
== AT
);
5933 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5939 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5940 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5945 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5948 offset_expr
.X_add_number
= expr1
.X_add_number
;
5949 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5950 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5951 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5952 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5955 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5956 treg
, tempreg
, breg
);
5966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5970 /* The j instruction may not be used in PIC code, since it
5971 requires an absolute address. We convert it to a b
5973 if (mips_pic
== NO_PIC
)
5974 macro_build (&offset_expr
, "j", "a");
5976 macro_build (&offset_expr
, "b", "p");
5979 /* The jal instructions must be handled as macros because when
5980 generating PIC code they expand to multi-instruction
5981 sequences. Normally they are simple instructions. */
5986 if (mips_pic
== NO_PIC
)
5987 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5990 if (sreg
!= PIC_CALL_REG
)
5991 as_warn (_("MIPS PIC call to register other than $25"));
5993 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5994 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5996 if (mips_cprestore_offset
< 0)
5997 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6000 if (! mips_frame_reg_valid
)
6002 as_warn (_("No .frame pseudo-op used in PIC code"));
6003 /* Quiet this warning. */
6004 mips_frame_reg_valid
= 1;
6006 if (! mips_cprestore_valid
)
6008 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6009 /* Quiet this warning. */
6010 mips_cprestore_valid
= 1;
6012 expr1
.X_add_number
= mips_cprestore_offset
;
6013 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6016 HAVE_64BIT_ADDRESSES
);
6024 if (mips_pic
== NO_PIC
)
6025 macro_build (&offset_expr
, "jal", "a");
6026 else if (mips_pic
== SVR4_PIC
)
6028 /* If this is a reference to an external symbol, and we are
6029 using a small GOT, we want
6030 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6034 lw $gp,cprestore($sp)
6035 The cprestore value is set using the .cprestore
6036 pseudo-op. If we are using a big GOT, we want
6037 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6039 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6043 lw $gp,cprestore($sp)
6044 If the symbol is not external, we want
6045 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6047 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6050 lw $gp,cprestore($sp)
6052 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6053 sequences above, minus nops, unless the symbol is local,
6054 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6060 relax_start (offset_expr
.X_add_symbol
);
6061 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6062 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6065 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6066 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6072 relax_start (offset_expr
.X_add_symbol
);
6073 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6074 BFD_RELOC_MIPS_CALL_HI16
);
6075 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6076 PIC_CALL_REG
, mips_gp_register
);
6077 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6078 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6081 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6082 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6084 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6085 PIC_CALL_REG
, PIC_CALL_REG
,
6086 BFD_RELOC_MIPS_GOT_OFST
);
6090 macro_build_jalr (&offset_expr
);
6094 relax_start (offset_expr
.X_add_symbol
);
6097 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6098 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6107 gpdelay
= reg_needs_delay (mips_gp_register
);
6108 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6109 BFD_RELOC_MIPS_CALL_HI16
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6111 PIC_CALL_REG
, mips_gp_register
);
6112 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6113 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6118 macro_build (NULL
, "nop", "");
6120 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6121 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6124 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6125 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6127 macro_build_jalr (&offset_expr
);
6129 if (mips_cprestore_offset
< 0)
6130 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6133 if (! mips_frame_reg_valid
)
6135 as_warn (_("No .frame pseudo-op used in PIC code"));
6136 /* Quiet this warning. */
6137 mips_frame_reg_valid
= 1;
6139 if (! mips_cprestore_valid
)
6141 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6142 /* Quiet this warning. */
6143 mips_cprestore_valid
= 1;
6145 if (mips_opts
.noreorder
)
6146 macro_build (NULL
, "nop", "");
6147 expr1
.X_add_number
= mips_cprestore_offset
;
6148 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6151 HAVE_64BIT_ADDRESSES
);
6155 else if (mips_pic
== VXWORKS_PIC
)
6156 as_bad (_("Non-PIC jump used in PIC library"));
6179 /* Itbl support may require additional care here. */
6184 /* Itbl support may require additional care here. */
6189 /* Itbl support may require additional care here. */
6194 /* Itbl support may require additional care here. */
6207 /* Itbl support may require additional care here. */
6212 /* Itbl support may require additional care here. */
6217 /* Itbl support may require additional care here. */
6237 if (breg
== treg
|| coproc
|| lr
)
6258 /* Itbl support may require additional care here. */
6263 /* Itbl support may require additional care here. */
6268 /* Itbl support may require additional care here. */
6273 /* Itbl support may require additional care here. */
6294 /* Itbl support may require additional care here. */
6298 /* Itbl support may require additional care here. */
6303 /* Itbl support may require additional care here. */
6315 /* Itbl support may require additional care here. */
6316 if (mask
== M_LWC1_AB
6317 || mask
== M_SWC1_AB
6318 || mask
== M_LDC1_AB
6319 || mask
== M_SDC1_AB
6323 else if (mask
== M_CACHE_AB
)
6330 if (offset_expr
.X_op
!= O_constant
6331 && offset_expr
.X_op
!= O_symbol
)
6333 as_bad (_("expression too complex"));
6334 offset_expr
.X_op
= O_constant
;
6337 if (HAVE_32BIT_ADDRESSES
6338 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6342 sprintf_vma (value
, offset_expr
.X_add_number
);
6343 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6346 /* A constant expression in PIC code can be handled just as it
6347 is in non PIC code. */
6348 if (offset_expr
.X_op
== O_constant
)
6350 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6351 & ~(bfd_vma
) 0xffff);
6352 normalize_address_expr (&expr1
);
6353 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6355 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6356 tempreg
, tempreg
, breg
);
6357 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6359 else if (mips_pic
== NO_PIC
)
6361 /* If this is a reference to a GP relative symbol, and there
6362 is no base register, we want
6363 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6364 Otherwise, if there is no base register, we want
6365 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6366 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6367 If we have a constant, we need two instructions anyhow,
6368 so we always use the latter form.
6370 If we have a base register, and this is a reference to a
6371 GP relative symbol, we want
6372 addu $tempreg,$breg,$gp
6373 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6375 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6376 addu $tempreg,$tempreg,$breg
6377 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6378 With a constant we always use the latter case.
6380 With 64bit address space and no base register and $at usable,
6382 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6383 lui $at,<sym> (BFD_RELOC_HI16_S)
6384 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6387 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6388 If we have a base register, we want
6389 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6390 lui $at,<sym> (BFD_RELOC_HI16_S)
6391 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6395 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6397 Without $at we can't generate the optimal path for superscalar
6398 processors here since this would require two temporary registers.
6399 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6400 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6402 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6404 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6405 If we have a base register, we want
6406 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6407 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6409 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6411 daddu $tempreg,$tempreg,$breg
6412 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6414 For GP relative symbols in 64bit address space we can use
6415 the same sequence as in 32bit address space. */
6416 if (HAVE_64BIT_SYMBOLS
)
6418 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6419 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6421 relax_start (offset_expr
.X_add_symbol
);
6424 macro_build (&offset_expr
, s
, fmt
, treg
,
6425 BFD_RELOC_GPREL16
, mips_gp_register
);
6429 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6430 tempreg
, breg
, mips_gp_register
);
6431 macro_build (&offset_expr
, s
, fmt
, treg
,
6432 BFD_RELOC_GPREL16
, tempreg
);
6437 if (used_at
== 0 && mips_opts
.at
)
6439 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6440 BFD_RELOC_MIPS_HIGHEST
);
6441 macro_build (&offset_expr
, "lui", "t,u", AT
,
6443 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6444 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6446 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6447 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6448 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6449 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6455 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6456 BFD_RELOC_MIPS_HIGHEST
);
6457 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6458 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6459 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6460 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6461 tempreg
, BFD_RELOC_HI16_S
);
6462 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6464 macro_build (NULL
, "daddu", "d,v,t",
6465 tempreg
, tempreg
, breg
);
6466 macro_build (&offset_expr
, s
, fmt
, treg
,
6467 BFD_RELOC_LO16
, tempreg
);
6470 if (mips_relax
.sequence
)
6477 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6478 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6480 relax_start (offset_expr
.X_add_symbol
);
6481 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6485 macro_build_lui (&offset_expr
, tempreg
);
6486 macro_build (&offset_expr
, s
, fmt
, treg
,
6487 BFD_RELOC_LO16
, tempreg
);
6488 if (mips_relax
.sequence
)
6493 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6494 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6496 relax_start (offset_expr
.X_add_symbol
);
6497 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6498 tempreg
, breg
, mips_gp_register
);
6499 macro_build (&offset_expr
, s
, fmt
, treg
,
6500 BFD_RELOC_GPREL16
, tempreg
);
6503 macro_build_lui (&offset_expr
, tempreg
);
6504 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6505 tempreg
, tempreg
, breg
);
6506 macro_build (&offset_expr
, s
, fmt
, treg
,
6507 BFD_RELOC_LO16
, tempreg
);
6508 if (mips_relax
.sequence
)
6512 else if (!mips_big_got
)
6514 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6516 /* If this is a reference to an external symbol, we want
6517 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6519 <op> $treg,0($tempreg)
6521 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6523 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6524 <op> $treg,0($tempreg)
6527 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6528 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6530 If there is a base register, we add it to $tempreg before
6531 the <op>. If there is a constant, we stick it in the
6532 <op> instruction. We don't handle constants larger than
6533 16 bits, because we have no way to load the upper 16 bits
6534 (actually, we could handle them for the subset of cases
6535 in which we are not using $at). */
6536 assert (offset_expr
.X_op
== O_symbol
);
6539 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6540 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6542 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6543 tempreg
, tempreg
, breg
);
6544 macro_build (&offset_expr
, s
, fmt
, treg
,
6545 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6548 expr1
.X_add_number
= offset_expr
.X_add_number
;
6549 offset_expr
.X_add_number
= 0;
6550 if (expr1
.X_add_number
< -0x8000
6551 || expr1
.X_add_number
>= 0x8000)
6552 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6553 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6554 lw_reloc_type
, mips_gp_register
);
6556 relax_start (offset_expr
.X_add_symbol
);
6558 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6559 tempreg
, BFD_RELOC_LO16
);
6562 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6563 tempreg
, tempreg
, breg
);
6564 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6566 else if (mips_big_got
&& !HAVE_NEWABI
)
6570 /* If this is a reference to an external symbol, we want
6571 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6572 addu $tempreg,$tempreg,$gp
6573 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6574 <op> $treg,0($tempreg)
6576 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6578 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6579 <op> $treg,0($tempreg)
6580 If there is a base register, we add it to $tempreg before
6581 the <op>. If there is a constant, we stick it in the
6582 <op> instruction. We don't handle constants larger than
6583 16 bits, because we have no way to load the upper 16 bits
6584 (actually, we could handle them for the subset of cases
6585 in which we are not using $at). */
6586 assert (offset_expr
.X_op
== O_symbol
);
6587 expr1
.X_add_number
= offset_expr
.X_add_number
;
6588 offset_expr
.X_add_number
= 0;
6589 if (expr1
.X_add_number
< -0x8000
6590 || expr1
.X_add_number
>= 0x8000)
6591 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6592 gpdelay
= reg_needs_delay (mips_gp_register
);
6593 relax_start (offset_expr
.X_add_symbol
);
6594 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6595 BFD_RELOC_MIPS_GOT_HI16
);
6596 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6598 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6599 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6602 macro_build (NULL
, "nop", "");
6603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6604 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6606 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6607 tempreg
, BFD_RELOC_LO16
);
6611 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6612 tempreg
, tempreg
, breg
);
6613 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6615 else if (mips_big_got
&& HAVE_NEWABI
)
6617 /* If this is a reference to an external symbol, we want
6618 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6619 add $tempreg,$tempreg,$gp
6620 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6621 <op> $treg,<ofst>($tempreg)
6622 Otherwise, for local symbols, we want:
6623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6624 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6625 assert (offset_expr
.X_op
== O_symbol
);
6626 expr1
.X_add_number
= offset_expr
.X_add_number
;
6627 offset_expr
.X_add_number
= 0;
6628 if (expr1
.X_add_number
< -0x8000
6629 || expr1
.X_add_number
>= 0x8000)
6630 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6631 relax_start (offset_expr
.X_add_symbol
);
6632 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6633 BFD_RELOC_MIPS_GOT_HI16
);
6634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6637 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6640 tempreg
, tempreg
, breg
);
6641 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6644 offset_expr
.X_add_number
= expr1
.X_add_number
;
6645 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6646 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6649 tempreg
, tempreg
, breg
);
6650 macro_build (&offset_expr
, s
, fmt
, treg
,
6651 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6661 load_register (treg
, &imm_expr
, 0);
6665 load_register (treg
, &imm_expr
, 1);
6669 if (imm_expr
.X_op
== O_constant
)
6672 load_register (AT
, &imm_expr
, 0);
6673 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6678 assert (offset_expr
.X_op
== O_symbol
6679 && strcmp (segment_name (S_GET_SEGMENT
6680 (offset_expr
.X_add_symbol
)),
6682 && offset_expr
.X_add_number
== 0);
6683 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6684 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6689 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6690 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6691 order 32 bits of the value and the low order 32 bits are either
6692 zero or in OFFSET_EXPR. */
6693 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6695 if (HAVE_64BIT_GPRS
)
6696 load_register (treg
, &imm_expr
, 1);
6701 if (target_big_endian
)
6713 load_register (hreg
, &imm_expr
, 0);
6716 if (offset_expr
.X_op
== O_absent
)
6717 move_register (lreg
, 0);
6720 assert (offset_expr
.X_op
== O_constant
);
6721 load_register (lreg
, &offset_expr
, 0);
6728 /* We know that sym is in the .rdata section. First we get the
6729 upper 16 bits of the address. */
6730 if (mips_pic
== NO_PIC
)
6732 macro_build_lui (&offset_expr
, AT
);
6737 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6738 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6742 /* Now we load the register(s). */
6743 if (HAVE_64BIT_GPRS
)
6746 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6751 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6754 /* FIXME: How in the world do we deal with the possible
6756 offset_expr
.X_add_number
+= 4;
6757 macro_build (&offset_expr
, "lw", "t,o(b)",
6758 treg
+ 1, BFD_RELOC_LO16
, AT
);
6764 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6765 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6766 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6767 the value and the low order 32 bits are either zero or in
6769 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6772 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6773 if (HAVE_64BIT_FPRS
)
6775 assert (HAVE_64BIT_GPRS
);
6776 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6780 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6781 if (offset_expr
.X_op
== O_absent
)
6782 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6785 assert (offset_expr
.X_op
== O_constant
);
6786 load_register (AT
, &offset_expr
, 0);
6787 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6793 assert (offset_expr
.X_op
== O_symbol
6794 && offset_expr
.X_add_number
== 0);
6795 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6796 if (strcmp (s
, ".lit8") == 0)
6798 if (mips_opts
.isa
!= ISA_MIPS1
)
6800 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6801 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6804 breg
= mips_gp_register
;
6805 r
= BFD_RELOC_MIPS_LITERAL
;
6810 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6812 if (mips_pic
!= NO_PIC
)
6813 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6814 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6817 /* FIXME: This won't work for a 64 bit address. */
6818 macro_build_lui (&offset_expr
, AT
);
6821 if (mips_opts
.isa
!= ISA_MIPS1
)
6823 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6824 treg
, BFD_RELOC_LO16
, AT
);
6833 /* Even on a big endian machine $fn comes before $fn+1. We have
6834 to adjust when loading from memory. */
6837 assert (mips_opts
.isa
== ISA_MIPS1
);
6838 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6839 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6840 /* FIXME: A possible overflow which I don't know how to deal
6842 offset_expr
.X_add_number
+= 4;
6843 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6844 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6849 * The MIPS assembler seems to check for X_add_number not
6850 * being double aligned and generating:
6853 * addiu at,at,%lo(foo+1)
6856 * But, the resulting address is the same after relocation so why
6857 * generate the extra instruction?
6859 /* Itbl support may require additional care here. */
6861 if (mips_opts
.isa
!= ISA_MIPS1
)
6872 if (mips_opts
.isa
!= ISA_MIPS1
)
6880 /* Itbl support may require additional care here. */
6885 if (HAVE_64BIT_GPRS
)
6896 if (HAVE_64BIT_GPRS
)
6906 if (offset_expr
.X_op
!= O_symbol
6907 && offset_expr
.X_op
!= O_constant
)
6909 as_bad (_("expression too complex"));
6910 offset_expr
.X_op
= O_constant
;
6913 if (HAVE_32BIT_ADDRESSES
6914 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6918 sprintf_vma (value
, offset_expr
.X_add_number
);
6919 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6922 /* Even on a big endian machine $fn comes before $fn+1. We have
6923 to adjust when loading from memory. We set coproc if we must
6924 load $fn+1 first. */
6925 /* Itbl support may require additional care here. */
6926 if (! target_big_endian
)
6929 if (mips_pic
== NO_PIC
6930 || offset_expr
.X_op
== O_constant
)
6932 /* If this is a reference to a GP relative symbol, we want
6933 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6934 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6935 If we have a base register, we use this
6937 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6938 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6939 If this is not a GP relative symbol, we want
6940 lui $at,<sym> (BFD_RELOC_HI16_S)
6941 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6942 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6943 If there is a base register, we add it to $at after the
6944 lui instruction. If there is a constant, we always use
6946 if (offset_expr
.X_op
== O_symbol
6947 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6948 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6950 relax_start (offset_expr
.X_add_symbol
);
6953 tempreg
= mips_gp_register
;
6957 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6958 AT
, breg
, mips_gp_register
);
6963 /* Itbl support may require additional care here. */
6964 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6965 BFD_RELOC_GPREL16
, tempreg
);
6966 offset_expr
.X_add_number
+= 4;
6968 /* Set mips_optimize to 2 to avoid inserting an
6970 hold_mips_optimize
= mips_optimize
;
6972 /* Itbl support may require additional care here. */
6973 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6974 BFD_RELOC_GPREL16
, tempreg
);
6975 mips_optimize
= hold_mips_optimize
;
6979 /* We just generated two relocs. When tc_gen_reloc
6980 handles this case, it will skip the first reloc and
6981 handle the second. The second reloc already has an
6982 extra addend of 4, which we added above. We must
6983 subtract it out, and then subtract another 4 to make
6984 the first reloc come out right. The second reloc
6985 will come out right because we are going to add 4 to
6986 offset_expr when we build its instruction below.
6988 If we have a symbol, then we don't want to include
6989 the offset, because it will wind up being included
6990 when we generate the reloc. */
6992 if (offset_expr
.X_op
== O_constant
)
6993 offset_expr
.X_add_number
-= 8;
6996 offset_expr
.X_add_number
= -4;
6997 offset_expr
.X_op
= O_constant
;
7001 macro_build_lui (&offset_expr
, AT
);
7003 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7004 /* Itbl support may require additional care here. */
7005 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7006 BFD_RELOC_LO16
, AT
);
7007 /* FIXME: How do we handle overflow here? */
7008 offset_expr
.X_add_number
+= 4;
7009 /* Itbl support may require additional care here. */
7010 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7011 BFD_RELOC_LO16
, AT
);
7012 if (mips_relax
.sequence
)
7015 else if (!mips_big_got
)
7017 /* If this is a reference to an external symbol, we want
7018 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7023 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7025 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7026 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7027 If there is a base register we add it to $at before the
7028 lwc1 instructions. If there is a constant we include it
7029 in the lwc1 instructions. */
7031 expr1
.X_add_number
= offset_expr
.X_add_number
;
7032 if (expr1
.X_add_number
< -0x8000
7033 || expr1
.X_add_number
>= 0x8000 - 4)
7034 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7035 load_got_offset (AT
, &offset_expr
);
7038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7040 /* Set mips_optimize to 2 to avoid inserting an undesired
7042 hold_mips_optimize
= mips_optimize
;
7045 /* Itbl support may require additional care here. */
7046 relax_start (offset_expr
.X_add_symbol
);
7047 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7048 BFD_RELOC_LO16
, AT
);
7049 expr1
.X_add_number
+= 4;
7050 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7051 BFD_RELOC_LO16
, AT
);
7053 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7054 BFD_RELOC_LO16
, AT
);
7055 offset_expr
.X_add_number
+= 4;
7056 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7057 BFD_RELOC_LO16
, AT
);
7060 mips_optimize
= hold_mips_optimize
;
7062 else if (mips_big_got
)
7066 /* If this is a reference to an external symbol, we want
7067 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7069 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7074 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7076 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7077 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7078 If there is a base register we add it to $at before the
7079 lwc1 instructions. If there is a constant we include it
7080 in the lwc1 instructions. */
7082 expr1
.X_add_number
= offset_expr
.X_add_number
;
7083 offset_expr
.X_add_number
= 0;
7084 if (expr1
.X_add_number
< -0x8000
7085 || expr1
.X_add_number
>= 0x8000 - 4)
7086 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7087 gpdelay
= reg_needs_delay (mips_gp_register
);
7088 relax_start (offset_expr
.X_add_symbol
);
7089 macro_build (&offset_expr
, "lui", "t,u",
7090 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7091 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7092 AT
, AT
, mips_gp_register
);
7093 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7094 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7097 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7098 /* Itbl support may require additional care here. */
7099 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7100 BFD_RELOC_LO16
, AT
);
7101 expr1
.X_add_number
+= 4;
7103 /* Set mips_optimize to 2 to avoid inserting an undesired
7105 hold_mips_optimize
= mips_optimize
;
7107 /* Itbl support may require additional care here. */
7108 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7109 BFD_RELOC_LO16
, AT
);
7110 mips_optimize
= hold_mips_optimize
;
7111 expr1
.X_add_number
-= 4;
7114 offset_expr
.X_add_number
= expr1
.X_add_number
;
7116 macro_build (NULL
, "nop", "");
7117 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7118 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7122 /* Itbl support may require additional care here. */
7123 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7124 BFD_RELOC_LO16
, AT
);
7125 offset_expr
.X_add_number
+= 4;
7127 /* Set mips_optimize to 2 to avoid inserting an undesired
7129 hold_mips_optimize
= mips_optimize
;
7131 /* Itbl support may require additional care here. */
7132 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7133 BFD_RELOC_LO16
, AT
);
7134 mips_optimize
= hold_mips_optimize
;
7148 assert (HAVE_32BIT_ADDRESSES
);
7149 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7150 offset_expr
.X_add_number
+= 4;
7151 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7154 /* New code added to support COPZ instructions.
7155 This code builds table entries out of the macros in mip_opcodes.
7156 R4000 uses interlocks to handle coproc delays.
7157 Other chips (like the R3000) require nops to be inserted for delays.
7159 FIXME: Currently, we require that the user handle delays.
7160 In order to fill delay slots for non-interlocked chips,
7161 we must have a way to specify delays based on the coprocessor.
7162 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7163 What are the side-effects of the cop instruction?
7164 What cache support might we have and what are its effects?
7165 Both coprocessor & memory require delays. how long???
7166 What registers are read/set/modified?
7168 If an itbl is provided to interpret cop instructions,
7169 this knowledge can be encoded in the itbl spec. */
7183 /* For now we just do C (same as Cz). The parameter will be
7184 stored in insn_opcode by mips_ip. */
7185 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7189 move_register (dreg
, sreg
);
7192 #ifdef LOSING_COMPILER
7194 /* Try and see if this is a new itbl instruction.
7195 This code builds table entries out of the macros in mip_opcodes.
7196 FIXME: For now we just assemble the expression and pass it's
7197 value along as a 32-bit immediate.
7198 We may want to have the assembler assemble this value,
7199 so that we gain the assembler's knowledge of delay slots,
7201 Would it be more efficient to use mask (id) here? */
7202 if (itbl_have_entries
7203 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7205 s
= ip
->insn_mo
->name
;
7207 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7208 macro_build (&immed_expr
, s
, "C");
7214 if (!mips_opts
.at
&& used_at
)
7215 as_bad (_("Macro used $at after \".set noat\""));
7219 macro2 (struct mips_cl_insn
*ip
)
7221 unsigned int treg
, sreg
, dreg
, breg
;
7222 unsigned int tempreg
;
7236 bfd_reloc_code_real_type r
;
7238 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7239 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7240 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7241 mask
= ip
->insn_mo
->mask
;
7243 expr1
.X_op
= O_constant
;
7244 expr1
.X_op_symbol
= NULL
;
7245 expr1
.X_add_symbol
= NULL
;
7246 expr1
.X_add_number
= 1;
7250 #endif /* LOSING_COMPILER */
7255 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7256 macro_build (NULL
, "mflo", "d", dreg
);
7262 /* The MIPS assembler some times generates shifts and adds. I'm
7263 not trying to be that fancy. GCC should do this for us
7266 load_register (AT
, &imm_expr
, dbl
);
7267 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7268 macro_build (NULL
, "mflo", "d", dreg
);
7284 load_register (AT
, &imm_expr
, dbl
);
7285 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7286 macro_build (NULL
, "mflo", "d", dreg
);
7287 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7288 macro_build (NULL
, "mfhi", "d", AT
);
7290 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7293 expr1
.X_add_number
= 8;
7294 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7295 macro_build (NULL
, "nop", "", 0);
7296 macro_build (NULL
, "break", "c", 6);
7299 macro_build (NULL
, "mflo", "d", dreg
);
7315 load_register (AT
, &imm_expr
, dbl
);
7316 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7317 sreg
, imm
? AT
: treg
);
7318 macro_build (NULL
, "mfhi", "d", AT
);
7319 macro_build (NULL
, "mflo", "d", dreg
);
7321 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7324 expr1
.X_add_number
= 8;
7325 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7326 macro_build (NULL
, "nop", "", 0);
7327 macro_build (NULL
, "break", "c", 6);
7333 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7344 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7345 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7349 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7350 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7351 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7352 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7356 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7367 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7368 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7372 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7373 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7374 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7375 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7383 if (imm_expr
.X_op
!= O_constant
)
7384 as_bad (_("Improper rotate count"));
7385 rot
= imm_expr
.X_add_number
& 0x3f;
7386 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7388 rot
= (64 - rot
) & 0x3f;
7390 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7392 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7397 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7400 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7401 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7404 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7405 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7406 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7414 if (imm_expr
.X_op
!= O_constant
)
7415 as_bad (_("Improper rotate count"));
7416 rot
= imm_expr
.X_add_number
& 0x1f;
7417 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7419 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7424 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7428 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7429 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7430 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7435 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7437 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7441 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7442 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7443 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7444 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7448 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7450 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7454 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7455 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7456 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7457 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7465 if (imm_expr
.X_op
!= O_constant
)
7466 as_bad (_("Improper rotate count"));
7467 rot
= imm_expr
.X_add_number
& 0x3f;
7468 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7471 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7473 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7478 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7481 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7482 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7485 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7486 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7487 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7495 if (imm_expr
.X_op
!= O_constant
)
7496 as_bad (_("Improper rotate count"));
7497 rot
= imm_expr
.X_add_number
& 0x1f;
7498 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7500 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7505 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7509 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7510 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7511 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7516 assert (mips_opts
.isa
== ISA_MIPS1
);
7517 /* Even on a big endian machine $fn comes before $fn+1. We have
7518 to adjust when storing to memory. */
7519 macro_build (&offset_expr
, "swc1", "T,o(b)",
7520 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7521 offset_expr
.X_add_number
+= 4;
7522 macro_build (&offset_expr
, "swc1", "T,o(b)",
7523 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7528 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7530 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7533 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7534 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7539 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7541 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7546 as_warn (_("Instruction %s: result is always false"),
7548 move_register (dreg
, 0);
7551 if (CPU_HAS_SEQ (mips_opts
.arch
)
7552 && -512 <= imm_expr
.X_add_number
7553 && imm_expr
.X_add_number
< 512)
7555 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7556 imm_expr
.X_add_number
);
7559 if (imm_expr
.X_op
== O_constant
7560 && imm_expr
.X_add_number
>= 0
7561 && imm_expr
.X_add_number
< 0x10000)
7563 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7565 else if (imm_expr
.X_op
== O_constant
7566 && imm_expr
.X_add_number
> -0x8000
7567 && imm_expr
.X_add_number
< 0)
7569 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7570 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7571 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7573 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7576 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7577 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7582 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7583 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7586 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7589 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7595 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7596 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7599 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7601 if (imm_expr
.X_op
== O_constant
7602 && imm_expr
.X_add_number
>= -0x8000
7603 && imm_expr
.X_add_number
< 0x8000)
7605 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7606 dreg
, sreg
, BFD_RELOC_LO16
);
7610 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7611 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7615 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7618 case M_SGT
: /* sreg > treg <==> treg < sreg */
7624 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7627 case M_SGT_I
: /* sreg > I <==> I < sreg */
7634 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7635 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7638 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7644 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7645 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7648 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7655 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7656 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7657 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7661 if (imm_expr
.X_op
== O_constant
7662 && imm_expr
.X_add_number
>= -0x8000
7663 && imm_expr
.X_add_number
< 0x8000)
7665 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7669 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7670 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7674 if (imm_expr
.X_op
== O_constant
7675 && imm_expr
.X_add_number
>= -0x8000
7676 && imm_expr
.X_add_number
< 0x8000)
7678 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7683 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7684 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7689 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7691 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7694 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7695 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7700 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7702 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7707 as_warn (_("Instruction %s: result is always true"),
7709 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7710 dreg
, 0, BFD_RELOC_LO16
);
7713 if (CPU_HAS_SEQ (mips_opts
.arch
)
7714 && -512 <= imm_expr
.X_add_number
7715 && imm_expr
.X_add_number
< 512)
7717 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7718 imm_expr
.X_add_number
);
7721 if (imm_expr
.X_op
== O_constant
7722 && imm_expr
.X_add_number
>= 0
7723 && imm_expr
.X_add_number
< 0x10000)
7725 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7727 else if (imm_expr
.X_op
== O_constant
7728 && imm_expr
.X_add_number
> -0x8000
7729 && imm_expr
.X_add_number
< 0)
7731 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7732 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7733 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7735 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7738 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7739 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7744 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7745 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7748 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7754 if (imm_expr
.X_op
== O_constant
7755 && imm_expr
.X_add_number
> -0x8000
7756 && imm_expr
.X_add_number
<= 0x8000)
7758 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7759 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7760 dreg
, sreg
, BFD_RELOC_LO16
);
7764 load_register (AT
, &imm_expr
, dbl
);
7765 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7771 if (imm_expr
.X_op
== O_constant
7772 && imm_expr
.X_add_number
> -0x8000
7773 && imm_expr
.X_add_number
<= 0x8000)
7775 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7776 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7777 dreg
, sreg
, BFD_RELOC_LO16
);
7781 load_register (AT
, &imm_expr
, dbl
);
7782 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7804 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7805 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7810 assert (mips_opts
.isa
== ISA_MIPS1
);
7812 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7813 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7816 * Is the double cfc1 instruction a bug in the mips assembler;
7817 * or is there a reason for it?
7820 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7821 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7822 macro_build (NULL
, "nop", "");
7823 expr1
.X_add_number
= 3;
7824 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7825 expr1
.X_add_number
= 2;
7826 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7827 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7828 macro_build (NULL
, "nop", "");
7829 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7831 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7832 macro_build (NULL
, "nop", "");
7843 if (offset_expr
.X_add_number
>= 0x7fff)
7844 as_bad (_("operand overflow"));
7845 if (! target_big_endian
)
7846 ++offset_expr
.X_add_number
;
7847 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7848 if (! target_big_endian
)
7849 --offset_expr
.X_add_number
;
7851 ++offset_expr
.X_add_number
;
7852 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7853 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7854 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7867 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7868 as_bad (_("operand overflow"));
7876 if (! target_big_endian
)
7877 offset_expr
.X_add_number
+= off
;
7878 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7879 if (! target_big_endian
)
7880 offset_expr
.X_add_number
-= off
;
7882 offset_expr
.X_add_number
+= off
;
7883 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7885 /* If necessary, move the result in tempreg the final destination. */
7886 if (treg
== tempreg
)
7888 /* Protect second load's delay slot. */
7890 move_register (treg
, tempreg
);
7904 load_address (AT
, &offset_expr
, &used_at
);
7906 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7907 if (! target_big_endian
)
7908 expr1
.X_add_number
= off
;
7910 expr1
.X_add_number
= 0;
7911 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7912 if (! target_big_endian
)
7913 expr1
.X_add_number
= 0;
7915 expr1
.X_add_number
= off
;
7916 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7922 load_address (AT
, &offset_expr
, &used_at
);
7924 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7925 if (target_big_endian
)
7926 expr1
.X_add_number
= 0;
7927 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7928 treg
, BFD_RELOC_LO16
, AT
);
7929 if (target_big_endian
)
7930 expr1
.X_add_number
= 1;
7932 expr1
.X_add_number
= 0;
7933 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7934 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7935 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7940 if (offset_expr
.X_add_number
>= 0x7fff)
7941 as_bad (_("operand overflow"));
7942 if (target_big_endian
)
7943 ++offset_expr
.X_add_number
;
7944 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7945 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7946 if (target_big_endian
)
7947 --offset_expr
.X_add_number
;
7949 ++offset_expr
.X_add_number
;
7950 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7963 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7964 as_bad (_("operand overflow"));
7965 if (! target_big_endian
)
7966 offset_expr
.X_add_number
+= off
;
7967 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7968 if (! target_big_endian
)
7969 offset_expr
.X_add_number
-= off
;
7971 offset_expr
.X_add_number
+= off
;
7972 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7986 load_address (AT
, &offset_expr
, &used_at
);
7988 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7989 if (! target_big_endian
)
7990 expr1
.X_add_number
= off
;
7992 expr1
.X_add_number
= 0;
7993 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7994 if (! target_big_endian
)
7995 expr1
.X_add_number
= 0;
7997 expr1
.X_add_number
= off
;
7998 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8003 load_address (AT
, &offset_expr
, &used_at
);
8005 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8006 if (! target_big_endian
)
8007 expr1
.X_add_number
= 0;
8008 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8009 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8010 if (! target_big_endian
)
8011 expr1
.X_add_number
= 1;
8013 expr1
.X_add_number
= 0;
8014 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8015 if (! target_big_endian
)
8016 expr1
.X_add_number
= 0;
8018 expr1
.X_add_number
= 1;
8019 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8020 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8021 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8025 /* FIXME: Check if this is one of the itbl macros, since they
8026 are added dynamically. */
8027 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8030 if (!mips_opts
.at
&& used_at
)
8031 as_bad (_("Macro used $at after \".set noat\""));
8034 /* Implement macros in mips16 mode. */
8037 mips16_macro (struct mips_cl_insn
*ip
)
8040 int xreg
, yreg
, zreg
, tmp
;
8043 const char *s
, *s2
, *s3
;
8045 mask
= ip
->insn_mo
->mask
;
8047 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8048 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8049 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8051 expr1
.X_op
= O_constant
;
8052 expr1
.X_op_symbol
= NULL
;
8053 expr1
.X_add_symbol
= NULL
;
8054 expr1
.X_add_number
= 1;
8074 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8075 expr1
.X_add_number
= 2;
8076 macro_build (&expr1
, "bnez", "x,p", yreg
);
8077 macro_build (NULL
, "break", "6", 7);
8079 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8080 since that causes an overflow. We should do that as well,
8081 but I don't see how to do the comparisons without a temporary
8084 macro_build (NULL
, s
, "x", zreg
);
8104 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8105 expr1
.X_add_number
= 2;
8106 macro_build (&expr1
, "bnez", "x,p", yreg
);
8107 macro_build (NULL
, "break", "6", 7);
8109 macro_build (NULL
, s2
, "x", zreg
);
8115 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8116 macro_build (NULL
, "mflo", "x", zreg
);
8124 if (imm_expr
.X_op
!= O_constant
)
8125 as_bad (_("Unsupported large constant"));
8126 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8127 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8131 if (imm_expr
.X_op
!= O_constant
)
8132 as_bad (_("Unsupported large constant"));
8133 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8134 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8138 if (imm_expr
.X_op
!= O_constant
)
8139 as_bad (_("Unsupported large constant"));
8140 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8141 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8163 goto do_reverse_branch
;
8167 goto do_reverse_branch
;
8179 goto do_reverse_branch
;
8190 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8191 macro_build (&offset_expr
, s2
, "p");
8218 goto do_addone_branch_i
;
8223 goto do_addone_branch_i
;
8238 goto do_addone_branch_i
;
8245 if (imm_expr
.X_op
!= O_constant
)
8246 as_bad (_("Unsupported large constant"));
8247 ++imm_expr
.X_add_number
;
8250 macro_build (&imm_expr
, s
, s3
, xreg
);
8251 macro_build (&offset_expr
, s2
, "p");
8255 expr1
.X_add_number
= 0;
8256 macro_build (&expr1
, "slti", "x,8", yreg
);
8258 move_register (xreg
, yreg
);
8259 expr1
.X_add_number
= 2;
8260 macro_build (&expr1
, "bteqz", "p");
8261 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8265 /* For consistency checking, verify that all bits are specified either
8266 by the match/mask part of the instruction definition, or by the
8269 validate_mips_insn (const struct mips_opcode
*opc
)
8271 const char *p
= opc
->args
;
8273 unsigned long used_bits
= opc
->mask
;
8275 if ((used_bits
& opc
->match
) != opc
->match
)
8277 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8278 opc
->name
, opc
->args
);
8281 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8291 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8292 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8293 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8294 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8295 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8296 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8297 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8298 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8299 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8300 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8301 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8302 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8303 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8305 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8306 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8307 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8308 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8309 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8310 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8311 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8312 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8313 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8314 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8317 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8318 c
, opc
->name
, opc
->args
);
8322 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8323 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8325 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8326 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8327 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8328 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8330 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8331 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8333 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8334 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8336 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8337 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8338 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8339 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8340 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8341 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8342 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8343 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8344 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8345 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8346 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8347 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8348 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8349 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8350 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8351 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8352 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8354 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8355 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8356 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8357 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8359 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8360 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8361 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8362 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8363 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8364 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8365 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8366 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8367 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8370 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8371 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8372 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8373 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8374 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8377 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8378 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8379 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8380 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8381 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8382 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8383 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8384 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8385 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8386 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8387 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8388 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8389 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8390 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8391 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8392 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8393 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8395 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8396 c
, opc
->name
, opc
->args
);
8400 if (used_bits
!= 0xffffffff)
8402 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8403 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8409 /* UDI immediates. */
8417 static const struct mips_immed mips_immed
[] = {
8418 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8419 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8420 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8421 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8425 /* Check whether an odd floating-point register is allowed. */
8427 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8429 const char *s
= insn
->name
;
8431 if (insn
->pinfo
== INSN_MACRO
)
8432 /* Let a macro pass, we'll catch it later when it is expanded. */
8435 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8437 /* Allow odd registers for single-precision ops. */
8438 switch (insn
->pinfo
& (FP_S
| FP_D
))
8442 return 1; /* both single precision - ok */
8444 return 0; /* both double precision - fail */
8449 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8450 s
= strchr (insn
->name
, '.');
8452 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8453 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8456 /* Single-precision coprocessor loads and moves are OK too. */
8457 if ((insn
->pinfo
& FP_S
)
8458 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8459 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8465 /* This routine assembles an instruction into its binary format. As a
8466 side effect, it sets one of the global variables imm_reloc or
8467 offset_reloc to the type of relocation to do if one of the operands
8468 is an address expression. */
8471 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8476 struct mips_opcode
*insn
;
8479 unsigned int lastregno
= 0;
8480 unsigned int lastpos
= 0;
8481 unsigned int limlo
, limhi
;
8484 offsetT min_range
, max_range
;
8490 /* If the instruction contains a '.', we first try to match an instruction
8491 including the '.'. Then we try again without the '.'. */
8493 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8496 /* If we stopped on whitespace, then replace the whitespace with null for
8497 the call to hash_find. Save the character we replaced just in case we
8498 have to re-parse the instruction. */
8505 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8507 /* If we didn't find the instruction in the opcode table, try again, but
8508 this time with just the instruction up to, but not including the
8512 /* Restore the character we overwrite above (if any). */
8516 /* Scan up to the first '.' or whitespace. */
8518 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8522 /* If we did not find a '.', then we can quit now. */
8525 insn_error
= "unrecognized opcode";
8529 /* Lookup the instruction in the hash table. */
8531 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8533 insn_error
= "unrecognized opcode";
8543 assert (strcmp (insn
->name
, str
) == 0);
8545 ok
= is_opcode_valid (insn
, FALSE
);
8548 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8549 && strcmp (insn
->name
, insn
[1].name
) == 0)
8558 static char buf
[100];
8560 _("opcode not supported on this processor: %s (%s)"),
8561 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8562 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8571 create_insn (ip
, insn
);
8574 for (args
= insn
->args
;; ++args
)
8578 s
+= strspn (s
, " \t");
8582 case '\0': /* end of args */
8587 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8588 my_getExpression (&imm_expr
, s
);
8589 check_absolute_expr (ip
, &imm_expr
);
8590 if ((unsigned long) imm_expr
.X_add_number
!= 1
8591 && (unsigned long) imm_expr
.X_add_number
!= 3)
8593 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8594 (unsigned long) imm_expr
.X_add_number
);
8596 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8597 imm_expr
.X_op
= O_absent
;
8601 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8602 my_getExpression (&imm_expr
, s
);
8603 check_absolute_expr (ip
, &imm_expr
);
8604 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8606 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8607 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8609 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8610 imm_expr
.X_op
= O_absent
;
8614 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8615 my_getExpression (&imm_expr
, s
);
8616 check_absolute_expr (ip
, &imm_expr
);
8617 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8619 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8620 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8622 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8623 imm_expr
.X_op
= O_absent
;
8627 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8628 my_getExpression (&imm_expr
, s
);
8629 check_absolute_expr (ip
, &imm_expr
);
8630 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8632 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8633 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8635 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8636 imm_expr
.X_op
= O_absent
;
8640 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8641 my_getExpression (&imm_expr
, s
);
8642 check_absolute_expr (ip
, &imm_expr
);
8643 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8645 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8646 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8648 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8649 imm_expr
.X_op
= O_absent
;
8653 case '7': /* four dsp accumulators in bits 11,12 */
8654 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8655 s
[3] >= '0' && s
[3] <= '3')
8659 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8663 as_bad (_("Invalid dsp acc register"));
8666 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8667 my_getExpression (&imm_expr
, s
);
8668 check_absolute_expr (ip
, &imm_expr
);
8669 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8671 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8673 (unsigned long) imm_expr
.X_add_number
);
8675 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8676 imm_expr
.X_op
= O_absent
;
8680 case '9': /* four dsp accumulators in bits 21,22 */
8681 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8682 s
[3] >= '0' && s
[3] <= '3')
8686 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8690 as_bad (_("Invalid dsp acc register"));
8693 case '0': /* dsp 6-bit signed immediate in bit 20 */
8694 my_getExpression (&imm_expr
, s
);
8695 check_absolute_expr (ip
, &imm_expr
);
8696 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8697 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8698 if (imm_expr
.X_add_number
< min_range
||
8699 imm_expr
.X_add_number
> max_range
)
8701 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8702 (long) min_range
, (long) max_range
,
8703 (long) imm_expr
.X_add_number
);
8705 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8706 imm_expr
.X_op
= O_absent
;
8710 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8711 my_getExpression (&imm_expr
, s
);
8712 check_absolute_expr (ip
, &imm_expr
);
8713 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8715 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8717 (unsigned long) imm_expr
.X_add_number
);
8719 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8720 imm_expr
.X_op
= O_absent
;
8724 case ':': /* dsp 7-bit signed immediate in bit 19 */
8725 my_getExpression (&imm_expr
, s
);
8726 check_absolute_expr (ip
, &imm_expr
);
8727 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8728 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8729 if (imm_expr
.X_add_number
< min_range
||
8730 imm_expr
.X_add_number
> max_range
)
8732 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8733 (long) min_range
, (long) max_range
,
8734 (long) imm_expr
.X_add_number
);
8736 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8737 imm_expr
.X_op
= O_absent
;
8741 case '@': /* dsp 10-bit signed immediate in bit 16 */
8742 my_getExpression (&imm_expr
, s
);
8743 check_absolute_expr (ip
, &imm_expr
);
8744 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8745 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8746 if (imm_expr
.X_add_number
< min_range
||
8747 imm_expr
.X_add_number
> max_range
)
8749 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8750 (long) min_range
, (long) max_range
,
8751 (long) imm_expr
.X_add_number
);
8753 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8754 imm_expr
.X_op
= O_absent
;
8758 case '!': /* MT usermode flag bit. */
8759 my_getExpression (&imm_expr
, s
);
8760 check_absolute_expr (ip
, &imm_expr
);
8761 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8762 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8763 (unsigned long) imm_expr
.X_add_number
);
8764 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8765 imm_expr
.X_op
= O_absent
;
8769 case '$': /* MT load high flag bit. */
8770 my_getExpression (&imm_expr
, s
);
8771 check_absolute_expr (ip
, &imm_expr
);
8772 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8773 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8774 (unsigned long) imm_expr
.X_add_number
);
8775 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8776 imm_expr
.X_op
= O_absent
;
8780 case '*': /* four dsp accumulators in bits 18,19 */
8781 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8782 s
[3] >= '0' && s
[3] <= '3')
8786 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8790 as_bad (_("Invalid dsp/smartmips acc register"));
8793 case '&': /* four dsp accumulators in bits 13,14 */
8794 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8795 s
[3] >= '0' && s
[3] <= '3')
8799 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8803 as_bad (_("Invalid dsp/smartmips acc register"));
8815 INSERT_OPERAND (RS
, *ip
, lastregno
);
8819 INSERT_OPERAND (RT
, *ip
, lastregno
);
8823 INSERT_OPERAND (FT
, *ip
, lastregno
);
8827 INSERT_OPERAND (FS
, *ip
, lastregno
);
8833 /* Handle optional base register.
8834 Either the base register is omitted or
8835 we must have a left paren. */
8836 /* This is dependent on the next operand specifier
8837 is a base register specification. */
8838 assert (args
[1] == 'b' || args
[1] == '5'
8839 || args
[1] == '-' || args
[1] == '4');
8843 case ')': /* these must match exactly */
8850 case '+': /* Opcode extension character. */
8853 case '1': /* UDI immediates. */
8858 const struct mips_immed
*imm
= mips_immed
;
8860 while (imm
->type
&& imm
->type
!= *args
)
8864 my_getExpression (&imm_expr
, s
);
8865 check_absolute_expr (ip
, &imm_expr
);
8866 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8868 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8869 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8870 (unsigned long) imm_expr
.X_add_number
,
8871 (unsigned long) imm_expr
.X_add_number
);
8872 imm_expr
.X_add_number
&= imm
->mask
;
8874 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8876 imm_expr
.X_op
= O_absent
;
8881 case 'A': /* ins/ext position, becomes LSB. */
8890 my_getExpression (&imm_expr
, s
);
8891 check_absolute_expr (ip
, &imm_expr
);
8892 if ((unsigned long) imm_expr
.X_add_number
< limlo
8893 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8895 as_bad (_("Improper position (%lu)"),
8896 (unsigned long) imm_expr
.X_add_number
);
8897 imm_expr
.X_add_number
= limlo
;
8899 lastpos
= imm_expr
.X_add_number
;
8900 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8901 imm_expr
.X_op
= O_absent
;
8905 case 'B': /* ins size, becomes MSB. */
8914 my_getExpression (&imm_expr
, s
);
8915 check_absolute_expr (ip
, &imm_expr
);
8916 /* Check for negative input so that small negative numbers
8917 will not succeed incorrectly. The checks against
8918 (pos+size) transitively check "size" itself,
8919 assuming that "pos" is reasonable. */
8920 if ((long) imm_expr
.X_add_number
< 0
8921 || ((unsigned long) imm_expr
.X_add_number
8923 || ((unsigned long) imm_expr
.X_add_number
8926 as_bad (_("Improper insert size (%lu, position %lu)"),
8927 (unsigned long) imm_expr
.X_add_number
,
8928 (unsigned long) lastpos
);
8929 imm_expr
.X_add_number
= limlo
- lastpos
;
8931 INSERT_OPERAND (INSMSB
, *ip
,
8932 lastpos
+ imm_expr
.X_add_number
- 1);
8933 imm_expr
.X_op
= O_absent
;
8937 case 'C': /* ext size, becomes MSBD. */
8950 my_getExpression (&imm_expr
, s
);
8951 check_absolute_expr (ip
, &imm_expr
);
8952 /* Check for negative input so that small negative numbers
8953 will not succeed incorrectly. The checks against
8954 (pos+size) transitively check "size" itself,
8955 assuming that "pos" is reasonable. */
8956 if ((long) imm_expr
.X_add_number
< 0
8957 || ((unsigned long) imm_expr
.X_add_number
8959 || ((unsigned long) imm_expr
.X_add_number
8962 as_bad (_("Improper extract size (%lu, position %lu)"),
8963 (unsigned long) imm_expr
.X_add_number
,
8964 (unsigned long) lastpos
);
8965 imm_expr
.X_add_number
= limlo
- lastpos
;
8967 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8968 imm_expr
.X_op
= O_absent
;
8973 /* +D is for disassembly only; never match. */
8977 /* "+I" is like "I", except that imm2_expr is used. */
8978 my_getExpression (&imm2_expr
, s
);
8979 if (imm2_expr
.X_op
!= O_big
8980 && imm2_expr
.X_op
!= O_constant
)
8981 insn_error
= _("absolute expression required");
8982 if (HAVE_32BIT_GPRS
)
8983 normalize_constant_expr (&imm2_expr
);
8987 case 'T': /* Coprocessor register. */
8988 /* +T is for disassembly only; never match. */
8991 case 't': /* Coprocessor register number. */
8992 if (s
[0] == '$' && ISDIGIT (s
[1]))
9002 while (ISDIGIT (*s
));
9004 as_bad (_("Invalid register number (%d)"), regno
);
9007 INSERT_OPERAND (RT
, *ip
, regno
);
9012 as_bad (_("Invalid coprocessor 0 register number"));
9016 /* bbit[01] and bbit[01]32 bit index. Give error if index
9017 is not in the valid range. */
9018 my_getExpression (&imm_expr
, s
);
9019 check_absolute_expr (ip
, &imm_expr
);
9020 if ((unsigned) imm_expr
.X_add_number
> 31)
9022 as_bad (_("Improper bit index (%lu)"),
9023 (unsigned long) imm_expr
.X_add_number
);
9024 imm_expr
.X_add_number
= 0;
9026 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9027 imm_expr
.X_op
= O_absent
;
9032 /* bbit[01] bit index when bbit is used but we generate
9033 bbit[01]32 because the index is over 32. Move to the
9034 next candidate if index is not in the valid range. */
9035 my_getExpression (&imm_expr
, s
);
9036 check_absolute_expr (ip
, &imm_expr
);
9037 if ((unsigned) imm_expr
.X_add_number
< 32
9038 || (unsigned) imm_expr
.X_add_number
> 63)
9040 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9041 imm_expr
.X_op
= O_absent
;
9046 /* cins, cins32, exts and exts32 position field. Give error
9047 if it's not in the valid range. */
9048 my_getExpression (&imm_expr
, s
);
9049 check_absolute_expr (ip
, &imm_expr
);
9050 if ((unsigned) imm_expr
.X_add_number
> 31)
9052 as_bad (_("Improper position (%lu)"),
9053 (unsigned long) imm_expr
.X_add_number
);
9054 imm_expr
.X_add_number
= 0;
9056 /* Make the pos explicit to simplify +S. */
9057 lastpos
= imm_expr
.X_add_number
+ 32;
9058 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9059 imm_expr
.X_op
= O_absent
;
9064 /* cins, cins32, exts and exts32 position field. Move to
9065 the next candidate if it's not in the valid range. */
9066 my_getExpression (&imm_expr
, s
);
9067 check_absolute_expr (ip
, &imm_expr
);
9068 if ((unsigned) imm_expr
.X_add_number
< 32
9069 || (unsigned) imm_expr
.X_add_number
> 63)
9071 lastpos
= imm_expr
.X_add_number
;
9072 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9073 imm_expr
.X_op
= O_absent
;
9078 /* cins and exts length-minus-one field. */
9079 my_getExpression (&imm_expr
, s
);
9080 check_absolute_expr (ip
, &imm_expr
);
9081 if ((unsigned long) imm_expr
.X_add_number
> 31)
9083 as_bad (_("Improper size (%lu)"),
9084 (unsigned long) imm_expr
.X_add_number
);
9085 imm_expr
.X_add_number
= 0;
9087 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9088 imm_expr
.X_op
= O_absent
;
9093 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9094 length-minus-one field. */
9095 my_getExpression (&imm_expr
, s
);
9096 check_absolute_expr (ip
, &imm_expr
);
9097 if ((long) imm_expr
.X_add_number
< 0
9098 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9100 as_bad (_("Improper size (%lu)"),
9101 (unsigned long) imm_expr
.X_add_number
);
9102 imm_expr
.X_add_number
= 0;
9104 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9105 imm_expr
.X_op
= O_absent
;
9110 /* seqi/snei immediate field. */
9111 my_getExpression (&imm_expr
, s
);
9112 check_absolute_expr (ip
, &imm_expr
);
9113 if ((long) imm_expr
.X_add_number
< -512
9114 || (long) imm_expr
.X_add_number
>= 512)
9116 as_bad (_("Improper immediate (%ld)"),
9117 (long) imm_expr
.X_add_number
);
9118 imm_expr
.X_add_number
= 0;
9120 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9121 imm_expr
.X_op
= O_absent
;
9126 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9127 *args
, insn
->name
, insn
->args
);
9128 /* Further processing is fruitless. */
9133 case '<': /* must be at least one digit */
9135 * According to the manual, if the shift amount is greater
9136 * than 31 or less than 0, then the shift amount should be
9137 * mod 32. In reality the mips assembler issues an error.
9138 * We issue a warning and mask out all but the low 5 bits.
9140 my_getExpression (&imm_expr
, s
);
9141 check_absolute_expr (ip
, &imm_expr
);
9142 if ((unsigned long) imm_expr
.X_add_number
> 31)
9143 as_warn (_("Improper shift amount (%lu)"),
9144 (unsigned long) imm_expr
.X_add_number
);
9145 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9146 imm_expr
.X_op
= O_absent
;
9150 case '>': /* shift amount minus 32 */
9151 my_getExpression (&imm_expr
, s
);
9152 check_absolute_expr (ip
, &imm_expr
);
9153 if ((unsigned long) imm_expr
.X_add_number
< 32
9154 || (unsigned long) imm_expr
.X_add_number
> 63)
9156 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9157 imm_expr
.X_op
= O_absent
;
9161 case 'k': /* cache code */
9162 case 'h': /* prefx code */
9163 my_getExpression (&imm_expr
, s
);
9164 check_absolute_expr (ip
, &imm_expr
);
9165 if ((unsigned long) imm_expr
.X_add_number
> 31)
9166 as_warn (_("Invalid value for `%s' (%lu)"),
9168 (unsigned long) imm_expr
.X_add_number
);
9170 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9172 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9173 imm_expr
.X_op
= O_absent
;
9177 case 'c': /* break code */
9178 my_getExpression (&imm_expr
, s
);
9179 check_absolute_expr (ip
, &imm_expr
);
9180 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9181 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9183 (unsigned long) imm_expr
.X_add_number
);
9184 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9185 imm_expr
.X_op
= O_absent
;
9189 case 'q': /* lower break code */
9190 my_getExpression (&imm_expr
, s
);
9191 check_absolute_expr (ip
, &imm_expr
);
9192 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9193 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9195 (unsigned long) imm_expr
.X_add_number
);
9196 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9197 imm_expr
.X_op
= O_absent
;
9201 case 'B': /* 20-bit syscall/break code. */
9202 my_getExpression (&imm_expr
, s
);
9203 check_absolute_expr (ip
, &imm_expr
);
9204 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9205 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9207 (unsigned long) imm_expr
.X_add_number
);
9208 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9209 imm_expr
.X_op
= O_absent
;
9213 case 'C': /* Coprocessor code */
9214 my_getExpression (&imm_expr
, s
);
9215 check_absolute_expr (ip
, &imm_expr
);
9216 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9218 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9219 (unsigned long) imm_expr
.X_add_number
);
9220 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9222 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9223 imm_expr
.X_op
= O_absent
;
9227 case 'J': /* 19-bit wait code. */
9228 my_getExpression (&imm_expr
, s
);
9229 check_absolute_expr (ip
, &imm_expr
);
9230 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9232 as_warn (_("Illegal 19-bit code (%lu)"),
9233 (unsigned long) imm_expr
.X_add_number
);
9234 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9236 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9237 imm_expr
.X_op
= O_absent
;
9241 case 'P': /* Performance register. */
9242 my_getExpression (&imm_expr
, s
);
9243 check_absolute_expr (ip
, &imm_expr
);
9244 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9245 as_warn (_("Invalid performance register (%lu)"),
9246 (unsigned long) imm_expr
.X_add_number
);
9247 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9248 imm_expr
.X_op
= O_absent
;
9252 case 'G': /* Coprocessor destination register. */
9253 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9254 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9256 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9257 INSERT_OPERAND (RD
, *ip
, regno
);
9266 case 'b': /* base register */
9267 case 'd': /* destination register */
9268 case 's': /* source register */
9269 case 't': /* target register */
9270 case 'r': /* both target and source */
9271 case 'v': /* both dest and source */
9272 case 'w': /* both dest and target */
9273 case 'E': /* coprocessor target register */
9274 case 'K': /* 'rdhwr' destination register */
9275 case 'x': /* ignore register name */
9276 case 'z': /* must be zero register */
9277 case 'U': /* destination register (clo/clz). */
9278 case 'g': /* coprocessor destination register */
9280 if (*args
== 'E' || *args
== 'K')
9281 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9284 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9285 if (regno
== AT
&& mips_opts
.at
)
9287 if (mips_opts
.at
== ATREG
)
9288 as_warn (_("used $at without \".set noat\""));
9290 as_warn (_("used $%u with \".set at=$%u\""),
9291 regno
, mips_opts
.at
);
9301 if (c
== 'r' || c
== 'v' || c
== 'w')
9308 /* 'z' only matches $0. */
9309 if (c
== 'z' && regno
!= 0)
9312 if (c
== 's' && !strcmp (ip
->insn_mo
->name
, "jalr"))
9314 if (regno
== lastregno
)
9316 insn_error
= _("source and destinationations must be different");
9319 if (regno
== 31 && lastregno
== 0)
9321 insn_error
= _("a destination register must be supplied");
9325 /* Now that we have assembled one operand, we use the args string
9326 * to figure out where it goes in the instruction. */
9333 INSERT_OPERAND (RS
, *ip
, regno
);
9339 INSERT_OPERAND (RD
, *ip
, regno
);
9342 INSERT_OPERAND (RD
, *ip
, regno
);
9343 INSERT_OPERAND (RT
, *ip
, regno
);
9348 INSERT_OPERAND (RT
, *ip
, regno
);
9351 /* This case exists because on the r3000 trunc
9352 expands into a macro which requires a gp
9353 register. On the r6000 or r4000 it is
9354 assembled into a single instruction which
9355 ignores the register. Thus the insn version
9356 is MIPS_ISA2 and uses 'x', and the macro
9357 version is MIPS_ISA1 and uses 't'. */
9360 /* This case is for the div instruction, which
9361 acts differently if the destination argument
9362 is $0. This only matches $0, and is checked
9363 outside the switch. */
9366 /* Itbl operand; not yet implemented. FIXME ?? */
9368 /* What about all other operands like 'i', which
9369 can be specified in the opcode table? */
9378 INSERT_OPERAND (RS
, *ip
, lastregno
);
9381 INSERT_OPERAND (RT
, *ip
, lastregno
);
9386 case 'O': /* MDMX alignment immediate constant. */
9387 my_getExpression (&imm_expr
, s
);
9388 check_absolute_expr (ip
, &imm_expr
);
9389 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9390 as_warn ("Improper align amount (%ld), using low bits",
9391 (long) imm_expr
.X_add_number
);
9392 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9393 imm_expr
.X_op
= O_absent
;
9397 case 'Q': /* MDMX vector, element sel, or const. */
9400 /* MDMX Immediate. */
9401 my_getExpression (&imm_expr
, s
);
9402 check_absolute_expr (ip
, &imm_expr
);
9403 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9404 as_warn (_("Invalid MDMX Immediate (%ld)"),
9405 (long) imm_expr
.X_add_number
);
9406 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9407 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9408 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9410 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9411 imm_expr
.X_op
= O_absent
;
9415 /* Not MDMX Immediate. Fall through. */
9416 case 'X': /* MDMX destination register. */
9417 case 'Y': /* MDMX source register. */
9418 case 'Z': /* MDMX target register. */
9420 case 'D': /* floating point destination register */
9421 case 'S': /* floating point source register */
9422 case 'T': /* floating point target register */
9423 case 'R': /* floating point source register */
9428 || (mips_opts
.ase_mdmx
9429 && (ip
->insn_mo
->pinfo
& FP_D
)
9430 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9431 | INSN_COPROC_MEMORY_DELAY
9432 | INSN_LOAD_COPROC_DELAY
9433 | INSN_LOAD_MEMORY_DELAY
9434 | INSN_STORE_MEMORY
))))
9437 if (reg_lookup (&s
, rtype
, ®no
))
9439 if ((regno
& 1) != 0
9441 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9442 as_warn (_("Float register should be even, was %d"),
9450 if (c
== 'V' || c
== 'W')
9461 INSERT_OPERAND (FD
, *ip
, regno
);
9466 INSERT_OPERAND (FS
, *ip
, regno
);
9469 /* This is like 'Z', but also needs to fix the MDMX
9470 vector/scalar select bits. Note that the
9471 scalar immediate case is handled above. */
9474 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9475 int max_el
= (is_qh
? 3 : 7);
9477 my_getExpression(&imm_expr
, s
);
9478 check_absolute_expr (ip
, &imm_expr
);
9480 if (imm_expr
.X_add_number
> max_el
)
9481 as_bad(_("Bad element selector %ld"),
9482 (long) imm_expr
.X_add_number
);
9483 imm_expr
.X_add_number
&= max_el
;
9484 ip
->insn_opcode
|= (imm_expr
.X_add_number
9487 imm_expr
.X_op
= O_absent
;
9489 as_warn(_("Expecting ']' found '%s'"), s
);
9495 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9496 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9499 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9506 INSERT_OPERAND (FT
, *ip
, regno
);
9509 INSERT_OPERAND (FR
, *ip
, regno
);
9519 INSERT_OPERAND (FS
, *ip
, lastregno
);
9522 INSERT_OPERAND (FT
, *ip
, lastregno
);
9528 my_getExpression (&imm_expr
, s
);
9529 if (imm_expr
.X_op
!= O_big
9530 && imm_expr
.X_op
!= O_constant
)
9531 insn_error
= _("absolute expression required");
9532 if (HAVE_32BIT_GPRS
)
9533 normalize_constant_expr (&imm_expr
);
9538 my_getExpression (&offset_expr
, s
);
9539 normalize_address_expr (&offset_expr
);
9540 *imm_reloc
= BFD_RELOC_32
;
9553 unsigned char temp
[8];
9555 unsigned int length
;
9560 /* These only appear as the last operand in an
9561 instruction, and every instruction that accepts
9562 them in any variant accepts them in all variants.
9563 This means we don't have to worry about backing out
9564 any changes if the instruction does not match.
9566 The difference between them is the size of the
9567 floating point constant and where it goes. For 'F'
9568 and 'L' the constant is 64 bits; for 'f' and 'l' it
9569 is 32 bits. Where the constant is placed is based
9570 on how the MIPS assembler does things:
9573 f -- immediate value
9576 The .lit4 and .lit8 sections are only used if
9577 permitted by the -G argument.
9579 The code below needs to know whether the target register
9580 is 32 or 64 bits wide. It relies on the fact 'f' and
9581 'F' are used with GPR-based instructions and 'l' and
9582 'L' are used with FPR-based instructions. */
9584 f64
= *args
== 'F' || *args
== 'L';
9585 using_gprs
= *args
== 'F' || *args
== 'f';
9587 save_in
= input_line_pointer
;
9588 input_line_pointer
= s
;
9589 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9591 s
= input_line_pointer
;
9592 input_line_pointer
= save_in
;
9593 if (err
!= NULL
&& *err
!= '\0')
9595 as_bad (_("Bad floating point constant: %s"), err
);
9596 memset (temp
, '\0', sizeof temp
);
9597 length
= f64
? 8 : 4;
9600 assert (length
== (unsigned) (f64
? 8 : 4));
9604 && (g_switch_value
< 4
9605 || (temp
[0] == 0 && temp
[1] == 0)
9606 || (temp
[2] == 0 && temp
[3] == 0))))
9608 imm_expr
.X_op
= O_constant
;
9609 if (! target_big_endian
)
9610 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9612 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9615 && ! mips_disable_float_construction
9616 /* Constants can only be constructed in GPRs and
9617 copied to FPRs if the GPRs are at least as wide
9618 as the FPRs. Force the constant into memory if
9619 we are using 64-bit FPRs but the GPRs are only
9622 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9623 && ((temp
[0] == 0 && temp
[1] == 0)
9624 || (temp
[2] == 0 && temp
[3] == 0))
9625 && ((temp
[4] == 0 && temp
[5] == 0)
9626 || (temp
[6] == 0 && temp
[7] == 0)))
9628 /* The value is simple enough to load with a couple of
9629 instructions. If using 32-bit registers, set
9630 imm_expr to the high order 32 bits and offset_expr to
9631 the low order 32 bits. Otherwise, set imm_expr to
9632 the entire 64 bit constant. */
9633 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9635 imm_expr
.X_op
= O_constant
;
9636 offset_expr
.X_op
= O_constant
;
9637 if (! target_big_endian
)
9639 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9640 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9644 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9645 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9647 if (offset_expr
.X_add_number
== 0)
9648 offset_expr
.X_op
= O_absent
;
9650 else if (sizeof (imm_expr
.X_add_number
) > 4)
9652 imm_expr
.X_op
= O_constant
;
9653 if (! target_big_endian
)
9654 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9656 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9660 imm_expr
.X_op
= O_big
;
9661 imm_expr
.X_add_number
= 4;
9662 if (! target_big_endian
)
9664 generic_bignum
[0] = bfd_getl16 (temp
);
9665 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9666 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9667 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9671 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9672 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9673 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9674 generic_bignum
[3] = bfd_getb16 (temp
);
9680 const char *newname
;
9683 /* Switch to the right section. */
9685 subseg
= now_subseg
;
9688 default: /* unused default case avoids warnings. */
9690 newname
= RDATA_SECTION_NAME
;
9691 if (g_switch_value
>= 8)
9695 newname
= RDATA_SECTION_NAME
;
9698 assert (g_switch_value
>= 4);
9702 new_seg
= subseg_new (newname
, (subsegT
) 0);
9704 bfd_set_section_flags (stdoutput
, new_seg
,
9709 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9710 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9711 record_alignment (new_seg
, 4);
9713 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9715 as_bad (_("Can't use floating point insn in this section"));
9717 /* Set the argument to the current address in the
9719 offset_expr
.X_op
= O_symbol
;
9720 offset_expr
.X_add_symbol
=
9721 symbol_new ("L0\001", now_seg
,
9722 (valueT
) frag_now_fix (), frag_now
);
9723 offset_expr
.X_add_number
= 0;
9725 /* Put the floating point number into the section. */
9726 p
= frag_more ((int) length
);
9727 memcpy (p
, temp
, length
);
9729 /* Switch back to the original section. */
9730 subseg_set (seg
, subseg
);
9735 case 'i': /* 16 bit unsigned immediate */
9736 case 'j': /* 16 bit signed immediate */
9737 *imm_reloc
= BFD_RELOC_LO16
;
9738 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9741 offsetT minval
, maxval
;
9743 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9744 && strcmp (insn
->name
, insn
[1].name
) == 0);
9746 /* If the expression was written as an unsigned number,
9747 only treat it as signed if there are no more
9751 && sizeof (imm_expr
.X_add_number
) <= 4
9752 && imm_expr
.X_op
== O_constant
9753 && imm_expr
.X_add_number
< 0
9754 && imm_expr
.X_unsigned
9758 /* For compatibility with older assemblers, we accept
9759 0x8000-0xffff as signed 16-bit numbers when only
9760 signed numbers are allowed. */
9762 minval
= 0, maxval
= 0xffff;
9764 minval
= -0x8000, maxval
= 0x7fff;
9766 minval
= -0x8000, maxval
= 0xffff;
9768 if (imm_expr
.X_op
!= O_constant
9769 || imm_expr
.X_add_number
< minval
9770 || imm_expr
.X_add_number
> maxval
)
9774 if (imm_expr
.X_op
== O_constant
9775 || imm_expr
.X_op
== O_big
)
9776 as_bad (_("expression out of range"));
9782 case 'o': /* 16 bit offset */
9783 /* Check whether there is only a single bracketed expression
9784 left. If so, it must be the base register and the
9785 constant must be zero. */
9786 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9788 offset_expr
.X_op
= O_constant
;
9789 offset_expr
.X_add_number
= 0;
9793 /* If this value won't fit into a 16 bit offset, then go
9794 find a macro that will generate the 32 bit offset
9796 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9797 && (offset_expr
.X_op
!= O_constant
9798 || offset_expr
.X_add_number
>= 0x8000
9799 || offset_expr
.X_add_number
< -0x8000))
9805 case 'p': /* pc relative offset */
9806 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9807 my_getExpression (&offset_expr
, s
);
9811 case 'u': /* upper 16 bits */
9812 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9813 && imm_expr
.X_op
== O_constant
9814 && (imm_expr
.X_add_number
< 0
9815 || imm_expr
.X_add_number
>= 0x10000))
9816 as_bad (_("lui expression not in range 0..65535"));
9820 case 'a': /* 26 bit address */
9821 my_getExpression (&offset_expr
, s
);
9823 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9826 case 'N': /* 3 bit branch condition code */
9827 case 'M': /* 3 bit compare condition code */
9829 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9831 if (!reg_lookup (&s
, rtype
, ®no
))
9833 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9834 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9835 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9836 && (regno
& 1) != 0)
9837 as_warn(_("Condition code register should be even for %s, was %d"),
9839 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9840 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9841 && (regno
& 3) != 0)
9842 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9845 INSERT_OPERAND (BCC
, *ip
, regno
);
9847 INSERT_OPERAND (CCC
, *ip
, regno
);
9851 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9862 while (ISDIGIT (*s
));
9865 c
= 8; /* Invalid sel value. */
9868 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9869 ip
->insn_opcode
|= c
;
9873 /* Must be at least one digit. */
9874 my_getExpression (&imm_expr
, s
);
9875 check_absolute_expr (ip
, &imm_expr
);
9877 if ((unsigned long) imm_expr
.X_add_number
9878 > (unsigned long) OP_MASK_VECBYTE
)
9880 as_bad (_("bad byte vector index (%ld)"),
9881 (long) imm_expr
.X_add_number
);
9882 imm_expr
.X_add_number
= 0;
9885 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9886 imm_expr
.X_op
= O_absent
;
9891 my_getExpression (&imm_expr
, s
);
9892 check_absolute_expr (ip
, &imm_expr
);
9894 if ((unsigned long) imm_expr
.X_add_number
9895 > (unsigned long) OP_MASK_VECALIGN
)
9897 as_bad (_("bad byte vector index (%ld)"),
9898 (long) imm_expr
.X_add_number
);
9899 imm_expr
.X_add_number
= 0;
9902 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9903 imm_expr
.X_op
= O_absent
;
9908 as_bad (_("bad char = '%c'\n"), *args
);
9913 /* Args don't match. */
9914 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9915 !strcmp (insn
->name
, insn
[1].name
))
9919 insn_error
= _("illegal operands");
9924 insn_error
= _("illegal operands");
9929 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9931 /* This routine assembles an instruction into its binary format when
9932 assembling for the mips16. As a side effect, it sets one of the
9933 global variables imm_reloc or offset_reloc to the type of
9934 relocation to do if one of the operands is an address expression.
9935 It also sets mips16_small and mips16_ext if the user explicitly
9936 requested a small or extended instruction. */
9939 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9943 struct mips_opcode
*insn
;
9946 unsigned int lastregno
= 0;
9952 mips16_small
= FALSE
;
9955 for (s
= str
; ISLOWER (*s
); ++s
)
9967 if (s
[1] == 't' && s
[2] == ' ')
9970 mips16_small
= TRUE
;
9974 else if (s
[1] == 'e' && s
[2] == ' ')
9983 insn_error
= _("unknown opcode");
9987 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9988 mips16_small
= TRUE
;
9990 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9992 insn_error
= _("unrecognized opcode");
10001 assert (strcmp (insn
->name
, str
) == 0);
10003 ok
= is_opcode_valid_16 (insn
);
10006 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10007 && strcmp (insn
->name
, insn
[1].name
) == 0)
10016 static char buf
[100];
10018 _("opcode not supported on this processor: %s (%s)"),
10019 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10020 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10027 create_insn (ip
, insn
);
10028 imm_expr
.X_op
= O_absent
;
10029 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10030 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10031 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10032 imm2_expr
.X_op
= O_absent
;
10033 offset_expr
.X_op
= O_absent
;
10034 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10035 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10036 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10037 for (args
= insn
->args
; 1; ++args
)
10044 /* In this switch statement we call break if we did not find
10045 a match, continue if we did find a match, or return if we
10054 /* Stuff the immediate value in now, if we can. */
10055 if (imm_expr
.X_op
== O_constant
10056 && *imm_reloc
> BFD_RELOC_UNUSED
10057 && insn
->pinfo
!= INSN_MACRO
)
10061 switch (*offset_reloc
)
10063 case BFD_RELOC_MIPS16_HI16_S
:
10064 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10067 case BFD_RELOC_MIPS16_HI16
:
10068 tmp
= imm_expr
.X_add_number
>> 16;
10071 case BFD_RELOC_MIPS16_LO16
:
10072 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10076 case BFD_RELOC_UNUSED
:
10077 tmp
= imm_expr
.X_add_number
;
10083 *offset_reloc
= BFD_RELOC_UNUSED
;
10085 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10086 tmp
, TRUE
, mips16_small
,
10087 mips16_ext
, &ip
->insn_opcode
,
10088 &ip
->use_extend
, &ip
->extend
);
10089 imm_expr
.X_op
= O_absent
;
10090 *imm_reloc
= BFD_RELOC_UNUSED
;
10104 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10107 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10123 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10125 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10129 /* Fall through. */
10140 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10142 if (c
== 'v' || c
== 'w')
10145 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10147 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10158 if (c
== 'v' || c
== 'w')
10160 regno
= mips16_to_32_reg_map
[lastregno
];
10174 regno
= mips32_to_16_reg_map
[regno
];
10179 regno
= ILLEGAL_REG
;
10184 regno
= ILLEGAL_REG
;
10189 regno
= ILLEGAL_REG
;
10194 if (regno
== AT
&& mips_opts
.at
)
10196 if (mips_opts
.at
== ATREG
)
10197 as_warn (_("used $at without \".set noat\""));
10199 as_warn (_("used $%u with \".set at=$%u\""),
10200 regno
, mips_opts
.at
);
10208 if (regno
== ILLEGAL_REG
)
10215 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10219 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10222 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10225 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10231 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10234 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10235 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10245 if (strncmp (s
, "$pc", 3) == 0)
10262 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10265 if (imm_expr
.X_op
!= O_constant
)
10268 ip
->use_extend
= TRUE
;
10273 /* We need to relax this instruction. */
10274 *offset_reloc
= *imm_reloc
;
10275 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10280 *imm_reloc
= BFD_RELOC_UNUSED
;
10281 /* Fall through. */
10288 my_getExpression (&imm_expr
, s
);
10289 if (imm_expr
.X_op
== O_register
)
10291 /* What we thought was an expression turned out to
10294 if (s
[0] == '(' && args
[1] == '(')
10296 /* It looks like the expression was omitted
10297 before a register indirection, which means
10298 that the expression is implicitly zero. We
10299 still set up imm_expr, so that we handle
10300 explicit extensions correctly. */
10301 imm_expr
.X_op
= O_constant
;
10302 imm_expr
.X_add_number
= 0;
10303 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10310 /* We need to relax this instruction. */
10311 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10320 /* We use offset_reloc rather than imm_reloc for the PC
10321 relative operands. This lets macros with both
10322 immediate and address operands work correctly. */
10323 my_getExpression (&offset_expr
, s
);
10325 if (offset_expr
.X_op
== O_register
)
10328 /* We need to relax this instruction. */
10329 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10333 case '6': /* break code */
10334 my_getExpression (&imm_expr
, s
);
10335 check_absolute_expr (ip
, &imm_expr
);
10336 if ((unsigned long) imm_expr
.X_add_number
> 63)
10337 as_warn (_("Invalid value for `%s' (%lu)"),
10339 (unsigned long) imm_expr
.X_add_number
);
10340 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10341 imm_expr
.X_op
= O_absent
;
10345 case 'a': /* 26 bit address */
10346 my_getExpression (&offset_expr
, s
);
10348 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10349 ip
->insn_opcode
<<= 16;
10352 case 'l': /* register list for entry macro */
10353 case 'L': /* register list for exit macro */
10363 unsigned int freg
, reg1
, reg2
;
10365 while (*s
== ' ' || *s
== ',')
10367 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10369 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10373 as_bad (_("can't parse register list"));
10383 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10384 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10386 as_bad (_("invalid register list"));
10390 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10392 mask
&= ~ (7 << 3);
10395 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10397 mask
&= ~ (7 << 3);
10400 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10401 mask
|= (reg2
- 3) << 3;
10402 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10403 mask
|= (reg2
- 15) << 1;
10404 else if (reg1
== RA
&& reg2
== RA
)
10408 as_bad (_("invalid register list"));
10412 /* The mask is filled in in the opcode table for the
10413 benefit of the disassembler. We remove it before
10414 applying the actual mask. */
10415 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10416 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10420 case 'm': /* Register list for save insn. */
10421 case 'M': /* Register list for restore insn. */
10424 int framesz
= 0, seen_framesz
= 0;
10425 int args
= 0, statics
= 0, sregs
= 0;
10429 unsigned int reg1
, reg2
;
10431 SKIP_SPACE_TABS (s
);
10434 SKIP_SPACE_TABS (s
);
10436 my_getExpression (&imm_expr
, s
);
10437 if (imm_expr
.X_op
== O_constant
)
10439 /* Handle the frame size. */
10442 as_bad (_("more than one frame size in list"));
10446 framesz
= imm_expr
.X_add_number
;
10447 imm_expr
.X_op
= O_absent
;
10452 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10454 as_bad (_("can't parse register list"));
10466 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10469 as_bad (_("can't parse register list"));
10474 while (reg1
<= reg2
)
10476 if (reg1
>= 4 && reg1
<= 7)
10480 args
|= 1 << (reg1
- 4);
10482 /* statics $a0-$a3 */
10483 statics
|= 1 << (reg1
- 4);
10485 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10488 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10490 else if (reg1
== 31)
10492 /* Add $ra to insn. */
10497 as_bad (_("unexpected register in list"));
10505 /* Encode args/statics combination. */
10506 if (args
& statics
)
10507 as_bad (_("arg/static registers overlap"));
10508 else if (args
== 0xf)
10509 /* All $a0-$a3 are args. */
10510 opcode
|= MIPS16_ALL_ARGS
<< 16;
10511 else if (statics
== 0xf)
10512 /* All $a0-$a3 are statics. */
10513 opcode
|= MIPS16_ALL_STATICS
<< 16;
10516 int narg
= 0, nstat
= 0;
10518 /* Count arg registers. */
10525 as_bad (_("invalid arg register list"));
10527 /* Count static registers. */
10528 while (statics
& 0x8)
10530 statics
= (statics
<< 1) & 0xf;
10534 as_bad (_("invalid static register list"));
10536 /* Encode args/statics. */
10537 opcode
|= ((narg
<< 2) | nstat
) << 16;
10540 /* Encode $s0/$s1. */
10541 if (sregs
& (1 << 0)) /* $s0 */
10543 if (sregs
& (1 << 1)) /* $s1 */
10549 /* Count regs $s2-$s8. */
10557 as_bad (_("invalid static register list"));
10558 /* Encode $s2-$s8. */
10559 opcode
|= nsreg
<< 24;
10562 /* Encode frame size. */
10564 as_bad (_("missing frame size"));
10565 else if ((framesz
& 7) != 0 || framesz
< 0
10566 || framesz
> 0xff * 8)
10567 as_bad (_("invalid frame size"));
10568 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10571 opcode
|= (((framesz
& 0xf0) << 16)
10572 | (framesz
& 0x0f));
10575 /* Finally build the instruction. */
10576 if ((opcode
>> 16) != 0 || framesz
== 0)
10578 ip
->use_extend
= TRUE
;
10579 ip
->extend
= opcode
>> 16;
10581 ip
->insn_opcode
|= opcode
& 0x7f;
10585 case 'e': /* extend code */
10586 my_getExpression (&imm_expr
, s
);
10587 check_absolute_expr (ip
, &imm_expr
);
10588 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10590 as_warn (_("Invalid value for `%s' (%lu)"),
10592 (unsigned long) imm_expr
.X_add_number
);
10593 imm_expr
.X_add_number
&= 0x7ff;
10595 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10596 imm_expr
.X_op
= O_absent
;
10606 /* Args don't match. */
10607 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10608 strcmp (insn
->name
, insn
[1].name
) == 0)
10615 insn_error
= _("illegal operands");
10621 /* This structure holds information we know about a mips16 immediate
10624 struct mips16_immed_operand
10626 /* The type code used in the argument string in the opcode table. */
10628 /* The number of bits in the short form of the opcode. */
10630 /* The number of bits in the extended form of the opcode. */
10632 /* The amount by which the short form is shifted when it is used;
10633 for example, the sw instruction has a shift count of 2. */
10635 /* The amount by which the short form is shifted when it is stored
10636 into the instruction code. */
10638 /* Non-zero if the short form is unsigned. */
10640 /* Non-zero if the extended form is unsigned. */
10642 /* Non-zero if the value is PC relative. */
10646 /* The mips16 immediate operand types. */
10648 static const struct mips16_immed_operand mips16_immed_operands
[] =
10650 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10651 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10652 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10653 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10654 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10655 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10656 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10657 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10658 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10659 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10660 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10661 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10662 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10663 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10664 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10665 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10666 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10667 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10668 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10669 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10670 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10673 #define MIPS16_NUM_IMMED \
10674 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10676 /* Handle a mips16 instruction with an immediate value. This or's the
10677 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10678 whether an extended value is needed; if one is needed, it sets
10679 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10680 If SMALL is true, an unextended opcode was explicitly requested.
10681 If EXT is true, an extended opcode was explicitly requested. If
10682 WARN is true, warn if EXT does not match reality. */
10685 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10686 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10687 unsigned long *insn
, bfd_boolean
*use_extend
,
10688 unsigned short *extend
)
10690 const struct mips16_immed_operand
*op
;
10691 int mintiny
, maxtiny
;
10692 bfd_boolean needext
;
10694 op
= mips16_immed_operands
;
10695 while (op
->type
!= type
)
10698 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10703 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10706 maxtiny
= 1 << op
->nbits
;
10711 maxtiny
= (1 << op
->nbits
) - 1;
10716 mintiny
= - (1 << (op
->nbits
- 1));
10717 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10720 /* Branch offsets have an implicit 0 in the lowest bit. */
10721 if (type
== 'p' || type
== 'q')
10724 if ((val
& ((1 << op
->shift
) - 1)) != 0
10725 || val
< (mintiny
<< op
->shift
)
10726 || val
> (maxtiny
<< op
->shift
))
10731 if (warn
&& ext
&& ! needext
)
10732 as_warn_where (file
, line
,
10733 _("extended operand requested but not required"));
10734 if (small
&& needext
)
10735 as_bad_where (file
, line
, _("invalid unextended operand value"));
10737 if (small
|| (! ext
&& ! needext
))
10741 *use_extend
= FALSE
;
10742 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10743 insnval
<<= op
->op_shift
;
10748 long minext
, maxext
;
10754 maxext
= (1 << op
->extbits
) - 1;
10758 minext
= - (1 << (op
->extbits
- 1));
10759 maxext
= (1 << (op
->extbits
- 1)) - 1;
10761 if (val
< minext
|| val
> maxext
)
10762 as_bad_where (file
, line
,
10763 _("operand value out of range for instruction"));
10765 *use_extend
= TRUE
;
10766 if (op
->extbits
== 16)
10768 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10771 else if (op
->extbits
== 15)
10773 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10778 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10782 *extend
= (unsigned short) extval
;
10787 struct percent_op_match
10790 bfd_reloc_code_real_type reloc
;
10793 static const struct percent_op_match mips_percent_op
[] =
10795 {"%lo", BFD_RELOC_LO16
},
10797 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10798 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10799 {"%call16", BFD_RELOC_MIPS_CALL16
},
10800 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10801 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10802 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10803 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10804 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10805 {"%got", BFD_RELOC_MIPS_GOT16
},
10806 {"%gp_rel", BFD_RELOC_GPREL16
},
10807 {"%half", BFD_RELOC_16
},
10808 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10809 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10810 {"%neg", BFD_RELOC_MIPS_SUB
},
10811 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10812 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10813 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10814 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10815 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10816 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10817 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10819 {"%hi", BFD_RELOC_HI16_S
}
10822 static const struct percent_op_match mips16_percent_op
[] =
10824 {"%lo", BFD_RELOC_MIPS16_LO16
},
10825 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10826 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10830 /* Return true if *STR points to a relocation operator. When returning true,
10831 move *STR over the operator and store its relocation code in *RELOC.
10832 Leave both *STR and *RELOC alone when returning false. */
10835 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10837 const struct percent_op_match
*percent_op
;
10840 if (mips_opts
.mips16
)
10842 percent_op
= mips16_percent_op
;
10843 limit
= ARRAY_SIZE (mips16_percent_op
);
10847 percent_op
= mips_percent_op
;
10848 limit
= ARRAY_SIZE (mips_percent_op
);
10851 for (i
= 0; i
< limit
; i
++)
10852 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10854 int len
= strlen (percent_op
[i
].str
);
10856 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10859 *str
+= strlen (percent_op
[i
].str
);
10860 *reloc
= percent_op
[i
].reloc
;
10862 /* Check whether the output BFD supports this relocation.
10863 If not, issue an error and fall back on something safe. */
10864 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10866 as_bad ("relocation %s isn't supported by the current ABI",
10867 percent_op
[i
].str
);
10868 *reloc
= BFD_RELOC_UNUSED
;
10876 /* Parse string STR as a 16-bit relocatable operand. Store the
10877 expression in *EP and the relocations in the array starting
10878 at RELOC. Return the number of relocation operators used.
10880 On exit, EXPR_END points to the first character after the expression. */
10883 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10886 bfd_reloc_code_real_type reversed_reloc
[3];
10887 size_t reloc_index
, i
;
10888 int crux_depth
, str_depth
;
10891 /* Search for the start of the main expression, recoding relocations
10892 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10893 of the main expression and with CRUX_DEPTH containing the number
10894 of open brackets at that point. */
10901 crux_depth
= str_depth
;
10903 /* Skip over whitespace and brackets, keeping count of the number
10905 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10910 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10911 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10913 my_getExpression (ep
, crux
);
10916 /* Match every open bracket. */
10917 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10921 if (crux_depth
> 0)
10922 as_bad ("unclosed '('");
10926 if (reloc_index
!= 0)
10928 prev_reloc_op_frag
= frag_now
;
10929 for (i
= 0; i
< reloc_index
; i
++)
10930 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10933 return reloc_index
;
10937 my_getExpression (expressionS
*ep
, char *str
)
10942 save_in
= input_line_pointer
;
10943 input_line_pointer
= str
;
10945 expr_end
= input_line_pointer
;
10946 input_line_pointer
= save_in
;
10948 /* If we are in mips16 mode, and this is an expression based on `.',
10949 then we bump the value of the symbol by 1 since that is how other
10950 text symbols are handled. We don't bother to handle complex
10951 expressions, just `.' plus or minus a constant. */
10952 if (mips_opts
.mips16
10953 && ep
->X_op
== O_symbol
10954 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10955 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10956 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10957 && symbol_constant_p (ep
->X_add_symbol
)
10958 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10959 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10963 md_atof (int type
, char *litP
, int *sizeP
)
10965 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
10969 md_number_to_chars (char *buf
, valueT val
, int n
)
10971 if (target_big_endian
)
10972 number_to_chars_bigendian (buf
, val
, n
);
10974 number_to_chars_littleendian (buf
, val
, n
);
10978 static int support_64bit_objects(void)
10980 const char **list
, **l
;
10983 list
= bfd_target_list ();
10984 for (l
= list
; *l
!= NULL
; l
++)
10986 /* This is traditional mips */
10987 if (strcmp (*l
, "elf64-tradbigmips") == 0
10988 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10990 if (strcmp (*l
, "elf64-bigmips") == 0
10991 || strcmp (*l
, "elf64-littlemips") == 0)
10994 yes
= (*l
!= NULL
);
10998 #endif /* OBJ_ELF */
11000 const char *md_shortopts
= "O::g::G:";
11002 struct option md_longopts
[] =
11004 /* Options which specify architecture. */
11005 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
11006 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
11007 {"march", required_argument
, NULL
, OPTION_MARCH
},
11008 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
11009 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11010 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
11011 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11012 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11013 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
11014 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11015 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
11016 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11017 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
11018 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11019 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
11020 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11021 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
11022 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11023 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
11024 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11025 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
11026 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11027 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
11028 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11030 /* Options which specify Application Specific Extensions (ASEs). */
11031 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
11032 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
11033 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11034 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
11035 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11036 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
11037 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11038 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
11039 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11040 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
11041 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11042 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
11043 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11044 #define OPTION_DSP (OPTION_ASE_BASE + 6)
11045 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11046 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
11047 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11048 #define OPTION_MT (OPTION_ASE_BASE + 8)
11049 {"mmt", no_argument
, NULL
, OPTION_MT
},
11050 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
11051 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11052 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
11053 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11054 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
11055 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11056 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
11057 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11058 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
11059 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11061 /* Old-style architecture options. Don't add more of these. */
11062 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
11063 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
11064 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11065 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
11066 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11067 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
11068 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11069 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
11070 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11071 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
11072 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11073 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
11074 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11075 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
11076 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11077 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
11078 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11080 /* Options which enable bug fixes. */
11081 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
11082 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
11083 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11084 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
11085 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11086 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11087 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
11088 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
11089 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11090 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11091 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
11092 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
11093 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11094 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11096 /* Miscellaneous options. */
11097 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
11098 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
11099 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11100 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11101 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
11102 {"break", no_argument
, NULL
, OPTION_BREAK
},
11103 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11104 #define OPTION_EB (OPTION_MISC_BASE + 2)
11105 {"EB", no_argument
, NULL
, OPTION_EB
},
11106 #define OPTION_EL (OPTION_MISC_BASE + 3)
11107 {"EL", no_argument
, NULL
, OPTION_EL
},
11108 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
11109 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11110 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
11111 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11112 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
11113 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11114 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
11115 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11116 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
11117 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11118 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
11119 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11120 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
11121 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
11122 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11123 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11124 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
11125 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
11126 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11127 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11128 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
11129 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
11130 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11131 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11132 #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16)
11133 #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17)
11134 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11135 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11136 #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18)
11137 #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19)
11138 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11139 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11141 /* ELF-specific options. */
11143 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20)
11144 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
11145 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11146 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11147 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
11148 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11149 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
11150 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11151 #define OPTION_MABI (OPTION_ELF_BASE + 3)
11152 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11153 #define OPTION_32 (OPTION_ELF_BASE + 4)
11154 {"32", no_argument
, NULL
, OPTION_32
},
11155 #define OPTION_N32 (OPTION_ELF_BASE + 5)
11156 {"n32", no_argument
, NULL
, OPTION_N32
},
11157 #define OPTION_64 (OPTION_ELF_BASE + 6)
11158 {"64", no_argument
, NULL
, OPTION_64
},
11159 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
11160 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11161 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
11162 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11163 #define OPTION_PDR (OPTION_ELF_BASE + 9)
11164 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11165 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
11166 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11167 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
11168 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11169 #endif /* OBJ_ELF */
11171 {NULL
, no_argument
, NULL
, 0}
11173 size_t md_longopts_size
= sizeof (md_longopts
);
11175 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11176 NEW_VALUE. Warn if another value was already specified. Note:
11177 we have to defer parsing the -march and -mtune arguments in order
11178 to handle 'from-abi' correctly, since the ABI might be specified
11179 in a later argument. */
11182 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11184 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11185 as_warn (_("A different %s was already specified, is now %s"),
11186 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11189 *string_ptr
= new_value
;
11193 md_parse_option (int c
, char *arg
)
11197 case OPTION_CONSTRUCT_FLOATS
:
11198 mips_disable_float_construction
= 0;
11201 case OPTION_NO_CONSTRUCT_FLOATS
:
11202 mips_disable_float_construction
= 1;
11214 target_big_endian
= 1;
11218 target_big_endian
= 0;
11224 else if (arg
[0] == '0')
11226 else if (arg
[0] == '1')
11236 mips_debug
= atoi (arg
);
11240 file_mips_isa
= ISA_MIPS1
;
11244 file_mips_isa
= ISA_MIPS2
;
11248 file_mips_isa
= ISA_MIPS3
;
11252 file_mips_isa
= ISA_MIPS4
;
11256 file_mips_isa
= ISA_MIPS5
;
11259 case OPTION_MIPS32
:
11260 file_mips_isa
= ISA_MIPS32
;
11263 case OPTION_MIPS32R2
:
11264 file_mips_isa
= ISA_MIPS32R2
;
11267 case OPTION_MIPS64R2
:
11268 file_mips_isa
= ISA_MIPS64R2
;
11271 case OPTION_MIPS64
:
11272 file_mips_isa
= ISA_MIPS64
;
11276 mips_set_option_string (&mips_tune_string
, arg
);
11280 mips_set_option_string (&mips_arch_string
, arg
);
11284 mips_set_option_string (&mips_arch_string
, "4650");
11285 mips_set_option_string (&mips_tune_string
, "4650");
11288 case OPTION_NO_M4650
:
11292 mips_set_option_string (&mips_arch_string
, "4010");
11293 mips_set_option_string (&mips_tune_string
, "4010");
11296 case OPTION_NO_M4010
:
11300 mips_set_option_string (&mips_arch_string
, "4100");
11301 mips_set_option_string (&mips_tune_string
, "4100");
11304 case OPTION_NO_M4100
:
11308 mips_set_option_string (&mips_arch_string
, "3900");
11309 mips_set_option_string (&mips_tune_string
, "3900");
11312 case OPTION_NO_M3900
:
11316 mips_opts
.ase_mdmx
= 1;
11319 case OPTION_NO_MDMX
:
11320 mips_opts
.ase_mdmx
= 0;
11324 mips_opts
.ase_dsp
= 1;
11325 mips_opts
.ase_dspr2
= 0;
11328 case OPTION_NO_DSP
:
11329 mips_opts
.ase_dsp
= 0;
11330 mips_opts
.ase_dspr2
= 0;
11334 mips_opts
.ase_dspr2
= 1;
11335 mips_opts
.ase_dsp
= 1;
11338 case OPTION_NO_DSPR2
:
11339 mips_opts
.ase_dspr2
= 0;
11340 mips_opts
.ase_dsp
= 0;
11344 mips_opts
.ase_mt
= 1;
11348 mips_opts
.ase_mt
= 0;
11351 case OPTION_MIPS16
:
11352 mips_opts
.mips16
= 1;
11353 mips_no_prev_insn ();
11356 case OPTION_NO_MIPS16
:
11357 mips_opts
.mips16
= 0;
11358 mips_no_prev_insn ();
11361 case OPTION_MIPS3D
:
11362 mips_opts
.ase_mips3d
= 1;
11365 case OPTION_NO_MIPS3D
:
11366 mips_opts
.ase_mips3d
= 0;
11369 case OPTION_SMARTMIPS
:
11370 mips_opts
.ase_smartmips
= 1;
11373 case OPTION_NO_SMARTMIPS
:
11374 mips_opts
.ase_smartmips
= 0;
11377 case OPTION_FIX_VR4120
:
11378 mips_fix_vr4120
= 1;
11381 case OPTION_NO_FIX_VR4120
:
11382 mips_fix_vr4120
= 0;
11385 case OPTION_FIX_VR4130
:
11386 mips_fix_vr4130
= 1;
11389 case OPTION_NO_FIX_VR4130
:
11390 mips_fix_vr4130
= 0;
11393 case OPTION_RELAX_BRANCH
:
11394 mips_relax_branch
= 1;
11397 case OPTION_NO_RELAX_BRANCH
:
11398 mips_relax_branch
= 0;
11401 case OPTION_MSHARED
:
11402 mips_in_shared
= TRUE
;
11405 case OPTION_MNO_SHARED
:
11406 mips_in_shared
= FALSE
;
11409 case OPTION_MSYM32
:
11410 mips_opts
.sym32
= TRUE
;
11413 case OPTION_MNO_SYM32
:
11414 mips_opts
.sym32
= FALSE
;
11418 /* When generating ELF code, we permit -KPIC and -call_shared to
11419 select SVR4_PIC, and -non_shared to select no PIC. This is
11420 intended to be compatible with Irix 5. */
11421 case OPTION_CALL_SHARED
:
11424 as_bad (_("-call_shared is supported only for ELF format"));
11427 mips_pic
= SVR4_PIC
;
11428 mips_abicalls
= TRUE
;
11431 case OPTION_NON_SHARED
:
11434 as_bad (_("-non_shared is supported only for ELF format"));
11438 mips_abicalls
= FALSE
;
11441 /* The -xgot option tells the assembler to use 32 bit offsets
11442 when accessing the got in SVR4_PIC mode. It is for Irix
11447 #endif /* OBJ_ELF */
11450 g_switch_value
= atoi (arg
);
11455 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11460 as_bad (_("-32 is supported for ELF format only"));
11463 mips_abi
= O32_ABI
;
11469 as_bad (_("-n32 is supported for ELF format only"));
11472 mips_abi
= N32_ABI
;
11478 as_bad (_("-64 is supported for ELF format only"));
11481 mips_abi
= N64_ABI
;
11482 if (!support_64bit_objects())
11483 as_fatal (_("No compiled in support for 64 bit object file format"));
11485 #endif /* OBJ_ELF */
11488 file_mips_gp32
= 1;
11492 file_mips_gp32
= 0;
11496 file_mips_fp32
= 1;
11500 file_mips_fp32
= 0;
11503 case OPTION_SINGLE_FLOAT
:
11504 file_mips_single_float
= 1;
11507 case OPTION_DOUBLE_FLOAT
:
11508 file_mips_single_float
= 0;
11511 case OPTION_SOFT_FLOAT
:
11512 file_mips_soft_float
= 1;
11515 case OPTION_HARD_FLOAT
:
11516 file_mips_soft_float
= 0;
11523 as_bad (_("-mabi is supported for ELF format only"));
11526 if (strcmp (arg
, "32") == 0)
11527 mips_abi
= O32_ABI
;
11528 else if (strcmp (arg
, "o64") == 0)
11529 mips_abi
= O64_ABI
;
11530 else if (strcmp (arg
, "n32") == 0)
11531 mips_abi
= N32_ABI
;
11532 else if (strcmp (arg
, "64") == 0)
11534 mips_abi
= N64_ABI
;
11535 if (! support_64bit_objects())
11536 as_fatal (_("No compiled in support for 64 bit object file "
11539 else if (strcmp (arg
, "eabi") == 0)
11540 mips_abi
= EABI_ABI
;
11543 as_fatal (_("invalid abi -mabi=%s"), arg
);
11547 #endif /* OBJ_ELF */
11549 case OPTION_M7000_HILO_FIX
:
11550 mips_7000_hilo_fix
= TRUE
;
11553 case OPTION_MNO_7000_HILO_FIX
:
11554 mips_7000_hilo_fix
= FALSE
;
11558 case OPTION_MDEBUG
:
11559 mips_flag_mdebug
= TRUE
;
11562 case OPTION_NO_MDEBUG
:
11563 mips_flag_mdebug
= FALSE
;
11567 mips_flag_pdr
= TRUE
;
11570 case OPTION_NO_PDR
:
11571 mips_flag_pdr
= FALSE
;
11574 case OPTION_MVXWORKS_PIC
:
11575 mips_pic
= VXWORKS_PIC
;
11577 #endif /* OBJ_ELF */
11586 /* Set up globals to generate code for the ISA or processor
11587 described by INFO. */
11590 mips_set_architecture (const struct mips_cpu_info
*info
)
11594 file_mips_arch
= info
->cpu
;
11595 mips_opts
.arch
= info
->cpu
;
11596 mips_opts
.isa
= info
->isa
;
11601 /* Likewise for tuning. */
11604 mips_set_tune (const struct mips_cpu_info
*info
)
11607 mips_tune
= info
->cpu
;
11612 mips_after_parse_args (void)
11614 const struct mips_cpu_info
*arch_info
= 0;
11615 const struct mips_cpu_info
*tune_info
= 0;
11617 /* GP relative stuff not working for PE */
11618 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11620 if (g_switch_seen
&& g_switch_value
!= 0)
11621 as_bad (_("-G not supported in this configuration."));
11622 g_switch_value
= 0;
11625 if (mips_abi
== NO_ABI
)
11626 mips_abi
= MIPS_DEFAULT_ABI
;
11628 /* The following code determines the architecture and register size.
11629 Similar code was added to GCC 3.3 (see override_options() in
11630 config/mips/mips.c). The GAS and GCC code should be kept in sync
11631 as much as possible. */
11633 if (mips_arch_string
!= 0)
11634 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11636 if (file_mips_isa
!= ISA_UNKNOWN
)
11638 /* Handle -mipsN. At this point, file_mips_isa contains the
11639 ISA level specified by -mipsN, while arch_info->isa contains
11640 the -march selection (if any). */
11641 if (arch_info
!= 0)
11643 /* -march takes precedence over -mipsN, since it is more descriptive.
11644 There's no harm in specifying both as long as the ISA levels
11646 if (file_mips_isa
!= arch_info
->isa
)
11647 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11648 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11649 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11652 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11655 if (arch_info
== 0)
11656 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11658 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11659 as_bad ("-march=%s is not compatible with the selected ABI",
11662 mips_set_architecture (arch_info
);
11664 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11665 if (mips_tune_string
!= 0)
11666 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11668 if (tune_info
== 0)
11669 mips_set_tune (arch_info
);
11671 mips_set_tune (tune_info
);
11673 if (file_mips_gp32
>= 0)
11675 /* The user specified the size of the integer registers. Make sure
11676 it agrees with the ABI and ISA. */
11677 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11678 as_bad (_("-mgp64 used with a 32-bit processor"));
11679 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11680 as_bad (_("-mgp32 used with a 64-bit ABI"));
11681 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11682 as_bad (_("-mgp64 used with a 32-bit ABI"));
11686 /* Infer the integer register size from the ABI and processor.
11687 Restrict ourselves to 32-bit registers if that's all the
11688 processor has, or if the ABI cannot handle 64-bit registers. */
11689 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11690 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11693 switch (file_mips_fp32
)
11697 /* No user specified float register size.
11698 ??? GAS treats single-float processors as though they had 64-bit
11699 float registers (although it complains when double-precision
11700 instructions are used). As things stand, saying they have 32-bit
11701 registers would lead to spurious "register must be even" messages.
11702 So here we assume float registers are never smaller than the
11704 if (file_mips_gp32
== 0)
11705 /* 64-bit integer registers implies 64-bit float registers. */
11706 file_mips_fp32
= 0;
11707 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11708 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11709 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11710 file_mips_fp32
= 0;
11712 /* 32-bit float registers. */
11713 file_mips_fp32
= 1;
11716 /* The user specified the size of the float registers. Check if it
11717 agrees with the ABI and ISA. */
11719 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11720 as_bad (_("-mfp64 used with a 32-bit fpu"));
11721 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11722 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11723 as_warn (_("-mfp64 used with a 32-bit ABI"));
11726 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11727 as_warn (_("-mfp32 used with a 64-bit ABI"));
11731 /* End of GCC-shared inference code. */
11733 /* This flag is set when we have a 64-bit capable CPU but use only
11734 32-bit wide registers. Note that EABI does not use it. */
11735 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11736 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11737 || mips_abi
== O32_ABI
))
11738 mips_32bitmode
= 1;
11740 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11741 as_bad (_("trap exception not supported at ISA 1"));
11743 /* If the selected architecture includes support for ASEs, enable
11744 generation of code for them. */
11745 if (mips_opts
.mips16
== -1)
11746 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11747 if (mips_opts
.ase_mips3d
== -1)
11748 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11749 && file_mips_fp32
== 0) ? 1 : 0;
11750 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11751 as_bad (_("-mfp32 used with -mips3d"));
11753 if (mips_opts
.ase_mdmx
== -1)
11754 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11755 && file_mips_fp32
== 0) ? 1 : 0;
11756 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11757 as_bad (_("-mfp32 used with -mdmx"));
11759 if (mips_opts
.ase_smartmips
== -1)
11760 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11761 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11762 as_warn ("%s ISA does not support SmartMIPS",
11763 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11765 if (mips_opts
.ase_dsp
== -1)
11766 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11767 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11768 as_warn ("%s ISA does not support DSP ASE",
11769 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11771 if (mips_opts
.ase_dspr2
== -1)
11773 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11774 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11776 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11777 as_warn ("%s ISA does not support DSP R2 ASE",
11778 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11780 if (mips_opts
.ase_mt
== -1)
11781 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11782 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11783 as_warn ("%s ISA does not support MT ASE",
11784 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11786 file_mips_isa
= mips_opts
.isa
;
11787 file_ase_mips16
= mips_opts
.mips16
;
11788 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11789 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11790 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11791 file_ase_dsp
= mips_opts
.ase_dsp
;
11792 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11793 file_ase_mt
= mips_opts
.ase_mt
;
11794 mips_opts
.gp32
= file_mips_gp32
;
11795 mips_opts
.fp32
= file_mips_fp32
;
11796 mips_opts
.soft_float
= file_mips_soft_float
;
11797 mips_opts
.single_float
= file_mips_single_float
;
11799 if (mips_flag_mdebug
< 0)
11801 #ifdef OBJ_MAYBE_ECOFF
11802 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11803 mips_flag_mdebug
= 1;
11805 #endif /* OBJ_MAYBE_ECOFF */
11806 mips_flag_mdebug
= 0;
11811 mips_init_after_args (void)
11813 /* initialize opcodes */
11814 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11815 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11819 md_pcrel_from (fixS
*fixP
)
11821 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11822 switch (fixP
->fx_r_type
)
11824 case BFD_RELOC_16_PCREL_S2
:
11825 case BFD_RELOC_MIPS_JMP
:
11826 /* Return the address of the delay slot. */
11829 /* We have no relocation type for PC relative MIPS16 instructions. */
11830 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11832 _("PC relative MIPS16 instruction references a different section"));
11837 /* This is called before the symbol table is processed. In order to
11838 work with gcc when using mips-tfile, we must keep all local labels.
11839 However, in other cases, we want to discard them. If we were
11840 called with -g, but we didn't see any debugging information, it may
11841 mean that gcc is smuggling debugging information through to
11842 mips-tfile, in which case we must generate all local labels. */
11845 mips_frob_file_before_adjust (void)
11847 #ifndef NO_ECOFF_DEBUGGING
11848 if (ECOFF_DEBUGGING
11850 && ! ecoff_debugging_seen
)
11851 flag_keep_locals
= 1;
11855 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11856 the corresponding LO16 reloc. This is called before md_apply_fix and
11857 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11858 relocation operators.
11860 For our purposes, a %lo() expression matches a %got() or %hi()
11863 (a) it refers to the same symbol; and
11864 (b) the offset applied in the %lo() expression is no lower than
11865 the offset applied in the %got() or %hi().
11867 (b) allows us to cope with code like:
11870 lh $4,%lo(foo+2)($4)
11872 ...which is legal on RELA targets, and has a well-defined behaviour
11873 if the user knows that adding 2 to "foo" will not induce a carry to
11876 When several %lo()s match a particular %got() or %hi(), we use the
11877 following rules to distinguish them:
11879 (1) %lo()s with smaller offsets are a better match than %lo()s with
11882 (2) %lo()s with no matching %got() or %hi() are better than those
11883 that already have a matching %got() or %hi().
11885 (3) later %lo()s are better than earlier %lo()s.
11887 These rules are applied in order.
11889 (1) means, among other things, that %lo()s with identical offsets are
11890 chosen if they exist.
11892 (2) means that we won't associate several high-part relocations with
11893 the same low-part relocation unless there's no alternative. Having
11894 several high parts for the same low part is a GNU extension; this rule
11895 allows careful users to avoid it.
11897 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11898 with the last high-part relocation being at the front of the list.
11899 It therefore makes sense to choose the last matching low-part
11900 relocation, all other things being equal. It's also easier
11901 to code that way. */
11904 mips_frob_file (void)
11906 struct mips_hi_fixup
*l
;
11907 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
11909 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11911 segment_info_type
*seginfo
;
11912 bfd_boolean matched_lo_p
;
11913 fixS
**hi_pos
, **lo_pos
, **pos
;
11915 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11917 /* If a GOT16 relocation turns out to be against a global symbol,
11918 there isn't supposed to be a matching LO. */
11919 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11920 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11923 /* Check quickly whether the next fixup happens to be a matching %lo. */
11924 if (fixup_has_matching_lo_p (l
->fixp
))
11927 seginfo
= seg_info (l
->seg
);
11929 /* Set HI_POS to the position of this relocation in the chain.
11930 Set LO_POS to the position of the chosen low-part relocation.
11931 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11932 relocation that matches an immediately-preceding high-part
11936 matched_lo_p
= FALSE
;
11938 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS16_HI16
11939 || l
->fixp
->fx_r_type
== BFD_RELOC_MIPS16_HI16_S
)
11940 looking_for_rtype
= BFD_RELOC_MIPS16_LO16
;
11942 looking_for_rtype
= BFD_RELOC_LO16
;
11944 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11946 if (*pos
== l
->fixp
)
11949 if ((*pos
)->fx_r_type
== looking_for_rtype
11950 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11951 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11953 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11955 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11958 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11959 && fixup_has_matching_lo_p (*pos
));
11962 /* If we found a match, remove the high-part relocation from its
11963 current position and insert it before the low-part relocation.
11964 Make the offsets match so that fixup_has_matching_lo_p()
11967 We don't warn about unmatched high-part relocations since some
11968 versions of gcc have been known to emit dead "lui ...%hi(...)"
11970 if (lo_pos
!= NULL
)
11972 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11973 if (l
->fixp
->fx_next
!= *lo_pos
)
11975 *hi_pos
= l
->fixp
->fx_next
;
11976 l
->fixp
->fx_next
= *lo_pos
;
11983 /* We may have combined relocations without symbols in the N32/N64 ABI.
11984 We have to prevent gas from dropping them. */
11987 mips_force_relocation (fixS
*fixp
)
11989 if (generic_force_reloc (fixp
))
11993 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11994 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11995 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11996 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
12002 /* Apply a fixup to the object file. */
12005 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12009 reloc_howto_type
*howto
;
12011 /* We ignore generic BFD relocations we don't know about. */
12012 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12016 assert (fixP
->fx_size
== 4
12017 || fixP
->fx_r_type
== BFD_RELOC_16
12018 || fixP
->fx_r_type
== BFD_RELOC_64
12019 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12020 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12021 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12022 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12023 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12025 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12027 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12029 /* Don't treat parts of a composite relocation as done. There are two
12032 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12033 should nevertheless be emitted if the first part is.
12035 (2) In normal usage, composite relocations are never assembly-time
12036 constants. The easiest way of dealing with the pathological
12037 exceptions is to generate a relocation against STN_UNDEF and
12038 leave everything up to the linker. */
12039 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12042 switch (fixP
->fx_r_type
)
12044 case BFD_RELOC_MIPS_TLS_GD
:
12045 case BFD_RELOC_MIPS_TLS_LDM
:
12046 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12047 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12048 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12049 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12050 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12051 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12052 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12053 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12056 case BFD_RELOC_MIPS_JMP
:
12057 case BFD_RELOC_MIPS_SHIFT5
:
12058 case BFD_RELOC_MIPS_SHIFT6
:
12059 case BFD_RELOC_MIPS_GOT_DISP
:
12060 case BFD_RELOC_MIPS_GOT_PAGE
:
12061 case BFD_RELOC_MIPS_GOT_OFST
:
12062 case BFD_RELOC_MIPS_SUB
:
12063 case BFD_RELOC_MIPS_INSERT_A
:
12064 case BFD_RELOC_MIPS_INSERT_B
:
12065 case BFD_RELOC_MIPS_DELETE
:
12066 case BFD_RELOC_MIPS_HIGHEST
:
12067 case BFD_RELOC_MIPS_HIGHER
:
12068 case BFD_RELOC_MIPS_SCN_DISP
:
12069 case BFD_RELOC_MIPS_REL16
:
12070 case BFD_RELOC_MIPS_RELGOT
:
12071 case BFD_RELOC_MIPS_JALR
:
12072 case BFD_RELOC_HI16
:
12073 case BFD_RELOC_HI16_S
:
12074 case BFD_RELOC_GPREL16
:
12075 case BFD_RELOC_MIPS_LITERAL
:
12076 case BFD_RELOC_MIPS_CALL16
:
12077 case BFD_RELOC_MIPS_GOT16
:
12078 case BFD_RELOC_GPREL32
:
12079 case BFD_RELOC_MIPS_GOT_HI16
:
12080 case BFD_RELOC_MIPS_GOT_LO16
:
12081 case BFD_RELOC_MIPS_CALL_HI16
:
12082 case BFD_RELOC_MIPS_CALL_LO16
:
12083 case BFD_RELOC_MIPS16_GPREL
:
12084 case BFD_RELOC_MIPS16_HI16
:
12085 case BFD_RELOC_MIPS16_HI16_S
:
12086 case BFD_RELOC_MIPS16_JMP
:
12087 /* Nothing needed to do. The value comes from the reloc entry. */
12091 /* This is handled like BFD_RELOC_32, but we output a sign
12092 extended value if we are only 32 bits. */
12095 if (8 <= sizeof (valueT
))
12096 md_number_to_chars ((char *) buf
, *valP
, 8);
12101 if ((*valP
& 0x80000000) != 0)
12105 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12107 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12113 case BFD_RELOC_RVA
:
12116 /* If we are deleting this reloc entry, we must fill in the
12117 value now. This can happen if we have a .word which is not
12118 resolved when it appears but is later defined. */
12120 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12123 case BFD_RELOC_LO16
:
12124 case BFD_RELOC_MIPS16_LO16
:
12125 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12126 may be safe to remove, but if so it's not obvious. */
12127 /* When handling an embedded PIC switch statement, we can wind
12128 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12131 if (*valP
+ 0x8000 > 0xffff)
12132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12133 _("relocation overflow"));
12134 if (target_big_endian
)
12136 md_number_to_chars ((char *) buf
, *valP
, 2);
12140 case BFD_RELOC_16_PCREL_S2
:
12141 if ((*valP
& 0x3) != 0)
12142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12143 _("Branch to misaligned address (%lx)"), (long) *valP
);
12145 /* We need to save the bits in the instruction since fixup_segment()
12146 might be deleting the relocation entry (i.e., a branch within
12147 the current segment). */
12148 if (! fixP
->fx_done
)
12151 /* Update old instruction data. */
12152 if (target_big_endian
)
12153 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12155 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12157 if (*valP
+ 0x20000 <= 0x3ffff)
12159 insn
|= (*valP
>> 2) & 0xffff;
12160 md_number_to_chars ((char *) buf
, insn
, 4);
12162 else if (mips_pic
== NO_PIC
12164 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12165 && (fixP
->fx_frag
->fr_address
12166 < text_section
->vma
+ bfd_get_section_size (text_section
))
12167 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12168 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12169 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12171 /* The branch offset is too large. If this is an
12172 unconditional branch, and we are not generating PIC code,
12173 we can convert it to an absolute jump instruction. */
12174 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12175 insn
= 0x0c000000; /* jal */
12177 insn
= 0x08000000; /* j */
12178 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12180 fixP
->fx_addsy
= section_symbol (text_section
);
12181 *valP
+= md_pcrel_from (fixP
);
12182 md_number_to_chars ((char *) buf
, insn
, 4);
12186 /* If we got here, we have branch-relaxation disabled,
12187 and there's nothing we can do to fix this instruction
12188 without turning it into a longer sequence. */
12189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12190 _("Branch out of range"));
12194 case BFD_RELOC_VTABLE_INHERIT
:
12197 && !S_IS_DEFINED (fixP
->fx_addsy
)
12198 && !S_IS_WEAK (fixP
->fx_addsy
))
12199 S_SET_WEAK (fixP
->fx_addsy
);
12202 case BFD_RELOC_VTABLE_ENTRY
:
12210 /* Remember value for tc_gen_reloc. */
12211 fixP
->fx_addnumber
= *valP
;
12221 name
= input_line_pointer
;
12222 c
= get_symbol_end ();
12223 p
= (symbolS
*) symbol_find_or_make (name
);
12224 *input_line_pointer
= c
;
12228 /* Align the current frag to a given power of two. If a particular
12229 fill byte should be used, FILL points to an integer that contains
12230 that byte, otherwise FILL is null.
12232 The MIPS assembler also automatically adjusts any preceding
12236 mips_align (int to
, int *fill
, symbolS
*label
)
12238 mips_emit_delays ();
12239 mips_record_mips16_mode ();
12240 if (fill
== NULL
&& subseg_text_p (now_seg
))
12241 frag_align_code (to
, 0);
12243 frag_align (to
, fill
? *fill
: 0, 0);
12244 record_alignment (now_seg
, to
);
12247 assert (S_GET_SEGMENT (label
) == now_seg
);
12248 symbol_set_frag (label
, frag_now
);
12249 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12253 /* Align to a given power of two. .align 0 turns off the automatic
12254 alignment used by the data creating pseudo-ops. */
12257 s_align (int x ATTRIBUTE_UNUSED
)
12259 int temp
, fill_value
, *fill_ptr
;
12260 long max_alignment
= 28;
12262 /* o Note that the assembler pulls down any immediately preceding label
12263 to the aligned address.
12264 o It's not documented but auto alignment is reinstated by
12265 a .align pseudo instruction.
12266 o Note also that after auto alignment is turned off the mips assembler
12267 issues an error on attempt to assemble an improperly aligned data item.
12270 temp
= get_absolute_expression ();
12271 if (temp
> max_alignment
)
12272 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12275 as_warn (_("Alignment negative: 0 assumed."));
12278 if (*input_line_pointer
== ',')
12280 ++input_line_pointer
;
12281 fill_value
= get_absolute_expression ();
12282 fill_ptr
= &fill_value
;
12288 segment_info_type
*si
= seg_info (now_seg
);
12289 struct insn_label_list
*l
= si
->label_list
;
12290 /* Auto alignment should be switched on by next section change. */
12292 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12299 demand_empty_rest_of_line ();
12303 s_change_sec (int sec
)
12308 /* The ELF backend needs to know that we are changing sections, so
12309 that .previous works correctly. We could do something like check
12310 for an obj_section_change_hook macro, but that might be confusing
12311 as it would not be appropriate to use it in the section changing
12312 functions in read.c, since obj-elf.c intercepts those. FIXME:
12313 This should be cleaner, somehow. */
12315 obj_elf_section_change_hook ();
12318 mips_emit_delays ();
12328 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12329 demand_empty_rest_of_line ();
12333 seg
= subseg_new (RDATA_SECTION_NAME
,
12334 (subsegT
) get_absolute_expression ());
12337 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12338 | SEC_READONLY
| SEC_RELOC
12340 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12341 record_alignment (seg
, 4);
12343 demand_empty_rest_of_line ();
12347 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12350 bfd_set_section_flags (stdoutput
, seg
,
12351 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12352 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12353 record_alignment (seg
, 4);
12355 demand_empty_rest_of_line ();
12363 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12366 char *section_name
;
12371 int section_entry_size
;
12372 int section_alignment
;
12377 section_name
= input_line_pointer
;
12378 c
= get_symbol_end ();
12380 next_c
= *(input_line_pointer
+ 1);
12382 /* Do we have .section Name<,"flags">? */
12383 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12385 /* just after name is now '\0'. */
12386 *input_line_pointer
= c
;
12387 input_line_pointer
= section_name
;
12388 obj_elf_section (ignore
);
12391 input_line_pointer
++;
12393 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12395 section_type
= get_absolute_expression ();
12398 if (*input_line_pointer
++ == ',')
12399 section_flag
= get_absolute_expression ();
12402 if (*input_line_pointer
++ == ',')
12403 section_entry_size
= get_absolute_expression ();
12405 section_entry_size
= 0;
12406 if (*input_line_pointer
++ == ',')
12407 section_alignment
= get_absolute_expression ();
12409 section_alignment
= 0;
12411 section_name
= xstrdup (section_name
);
12413 /* When using the generic form of .section (as implemented by obj-elf.c),
12414 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12415 traditionally had to fall back on the more common @progbits instead.
12417 There's nothing really harmful in this, since bfd will correct
12418 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12419 means that, for backwards compatibility, the special_section entries
12420 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12422 Even so, we shouldn't force users of the MIPS .section syntax to
12423 incorrectly label the sections as SHT_PROGBITS. The best compromise
12424 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12425 generic type-checking code. */
12426 if (section_type
== SHT_MIPS_DWARF
)
12427 section_type
= SHT_PROGBITS
;
12429 obj_elf_change_section (section_name
, section_type
, section_flag
,
12430 section_entry_size
, 0, 0, 0);
12432 if (now_seg
->name
!= section_name
)
12433 free (section_name
);
12434 #endif /* OBJ_ELF */
12438 mips_enable_auto_align (void)
12444 s_cons (int log_size
)
12446 segment_info_type
*si
= seg_info (now_seg
);
12447 struct insn_label_list
*l
= si
->label_list
;
12450 label
= l
!= NULL
? l
->label
: NULL
;
12451 mips_emit_delays ();
12452 if (log_size
> 0 && auto_align
)
12453 mips_align (log_size
, 0, label
);
12454 mips_clear_insn_labels ();
12455 cons (1 << log_size
);
12459 s_float_cons (int type
)
12461 segment_info_type
*si
= seg_info (now_seg
);
12462 struct insn_label_list
*l
= si
->label_list
;
12465 label
= l
!= NULL
? l
->label
: NULL
;
12467 mips_emit_delays ();
12472 mips_align (3, 0, label
);
12474 mips_align (2, 0, label
);
12477 mips_clear_insn_labels ();
12482 /* Handle .globl. We need to override it because on Irix 5 you are
12485 where foo is an undefined symbol, to mean that foo should be
12486 considered to be the address of a function. */
12489 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12498 name
= input_line_pointer
;
12499 c
= get_symbol_end ();
12500 symbolP
= symbol_find_or_make (name
);
12501 S_SET_EXTERNAL (symbolP
);
12503 *input_line_pointer
= c
;
12504 SKIP_WHITESPACE ();
12506 /* On Irix 5, every global symbol that is not explicitly labelled as
12507 being a function is apparently labelled as being an object. */
12510 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12511 && (*input_line_pointer
!= ','))
12516 secname
= input_line_pointer
;
12517 c
= get_symbol_end ();
12518 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12520 as_bad (_("%s: no such section"), secname
);
12521 *input_line_pointer
= c
;
12523 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12524 flag
= BSF_FUNCTION
;
12527 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12529 c
= *input_line_pointer
;
12532 input_line_pointer
++;
12533 SKIP_WHITESPACE ();
12534 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12540 demand_empty_rest_of_line ();
12544 s_option (int x ATTRIBUTE_UNUSED
)
12549 opt
= input_line_pointer
;
12550 c
= get_symbol_end ();
12554 /* FIXME: What does this mean? */
12556 else if (strncmp (opt
, "pic", 3) == 0)
12560 i
= atoi (opt
+ 3);
12565 mips_pic
= SVR4_PIC
;
12566 mips_abicalls
= TRUE
;
12569 as_bad (_(".option pic%d not supported"), i
);
12571 if (mips_pic
== SVR4_PIC
)
12573 if (g_switch_seen
&& g_switch_value
!= 0)
12574 as_warn (_("-G may not be used with SVR4 PIC code"));
12575 g_switch_value
= 0;
12576 bfd_set_gp_size (stdoutput
, 0);
12580 as_warn (_("Unrecognized option \"%s\""), opt
);
12582 *input_line_pointer
= c
;
12583 demand_empty_rest_of_line ();
12586 /* This structure is used to hold a stack of .set values. */
12588 struct mips_option_stack
12590 struct mips_option_stack
*next
;
12591 struct mips_set_options options
;
12594 static struct mips_option_stack
*mips_opts_stack
;
12596 /* Handle the .set pseudo-op. */
12599 s_mipsset (int x ATTRIBUTE_UNUSED
)
12601 char *name
= input_line_pointer
, ch
;
12603 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12604 ++input_line_pointer
;
12605 ch
= *input_line_pointer
;
12606 *input_line_pointer
= '\0';
12608 if (strcmp (name
, "reorder") == 0)
12610 if (mips_opts
.noreorder
)
12613 else if (strcmp (name
, "noreorder") == 0)
12615 if (!mips_opts
.noreorder
)
12616 start_noreorder ();
12618 else if (strncmp (name
, "at=", 3) == 0)
12620 char *s
= name
+ 3;
12622 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12623 as_bad (_("Unrecognized register name `%s'"), s
);
12625 else if (strcmp (name
, "at") == 0)
12627 mips_opts
.at
= ATREG
;
12629 else if (strcmp (name
, "noat") == 0)
12631 mips_opts
.at
= ZERO
;
12633 else if (strcmp (name
, "macro") == 0)
12635 mips_opts
.warn_about_macros
= 0;
12637 else if (strcmp (name
, "nomacro") == 0)
12639 if (mips_opts
.noreorder
== 0)
12640 as_bad (_("`noreorder' must be set before `nomacro'"));
12641 mips_opts
.warn_about_macros
= 1;
12643 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12645 mips_opts
.nomove
= 0;
12647 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12649 mips_opts
.nomove
= 1;
12651 else if (strcmp (name
, "bopt") == 0)
12653 mips_opts
.nobopt
= 0;
12655 else if (strcmp (name
, "nobopt") == 0)
12657 mips_opts
.nobopt
= 1;
12659 else if (strcmp (name
, "gp=default") == 0)
12660 mips_opts
.gp32
= file_mips_gp32
;
12661 else if (strcmp (name
, "gp=32") == 0)
12662 mips_opts
.gp32
= 1;
12663 else if (strcmp (name
, "gp=64") == 0)
12665 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12666 as_warn ("%s isa does not support 64-bit registers",
12667 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12668 mips_opts
.gp32
= 0;
12670 else if (strcmp (name
, "fp=default") == 0)
12671 mips_opts
.fp32
= file_mips_fp32
;
12672 else if (strcmp (name
, "fp=32") == 0)
12673 mips_opts
.fp32
= 1;
12674 else if (strcmp (name
, "fp=64") == 0)
12676 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12677 as_warn ("%s isa does not support 64-bit floating point registers",
12678 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12679 mips_opts
.fp32
= 0;
12681 else if (strcmp (name
, "softfloat") == 0)
12682 mips_opts
.soft_float
= 1;
12683 else if (strcmp (name
, "hardfloat") == 0)
12684 mips_opts
.soft_float
= 0;
12685 else if (strcmp (name
, "singlefloat") == 0)
12686 mips_opts
.single_float
= 1;
12687 else if (strcmp (name
, "doublefloat") == 0)
12688 mips_opts
.single_float
= 0;
12689 else if (strcmp (name
, "mips16") == 0
12690 || strcmp (name
, "MIPS-16") == 0)
12691 mips_opts
.mips16
= 1;
12692 else if (strcmp (name
, "nomips16") == 0
12693 || strcmp (name
, "noMIPS-16") == 0)
12694 mips_opts
.mips16
= 0;
12695 else if (strcmp (name
, "smartmips") == 0)
12697 if (!ISA_SUPPORTS_SMARTMIPS
)
12698 as_warn ("%s ISA does not support SmartMIPS ASE",
12699 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12700 mips_opts
.ase_smartmips
= 1;
12702 else if (strcmp (name
, "nosmartmips") == 0)
12703 mips_opts
.ase_smartmips
= 0;
12704 else if (strcmp (name
, "mips3d") == 0)
12705 mips_opts
.ase_mips3d
= 1;
12706 else if (strcmp (name
, "nomips3d") == 0)
12707 mips_opts
.ase_mips3d
= 0;
12708 else if (strcmp (name
, "mdmx") == 0)
12709 mips_opts
.ase_mdmx
= 1;
12710 else if (strcmp (name
, "nomdmx") == 0)
12711 mips_opts
.ase_mdmx
= 0;
12712 else if (strcmp (name
, "dsp") == 0)
12714 if (!ISA_SUPPORTS_DSP_ASE
)
12715 as_warn ("%s ISA does not support DSP ASE",
12716 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12717 mips_opts
.ase_dsp
= 1;
12718 mips_opts
.ase_dspr2
= 0;
12720 else if (strcmp (name
, "nodsp") == 0)
12722 mips_opts
.ase_dsp
= 0;
12723 mips_opts
.ase_dspr2
= 0;
12725 else if (strcmp (name
, "dspr2") == 0)
12727 if (!ISA_SUPPORTS_DSPR2_ASE
)
12728 as_warn ("%s ISA does not support DSP R2 ASE",
12729 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12730 mips_opts
.ase_dspr2
= 1;
12731 mips_opts
.ase_dsp
= 1;
12733 else if (strcmp (name
, "nodspr2") == 0)
12735 mips_opts
.ase_dspr2
= 0;
12736 mips_opts
.ase_dsp
= 0;
12738 else if (strcmp (name
, "mt") == 0)
12740 if (!ISA_SUPPORTS_MT_ASE
)
12741 as_warn ("%s ISA does not support MT ASE",
12742 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12743 mips_opts
.ase_mt
= 1;
12745 else if (strcmp (name
, "nomt") == 0)
12746 mips_opts
.ase_mt
= 0;
12747 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12751 /* Permit the user to change the ISA and architecture on the fly.
12752 Needless to say, misuse can cause serious problems. */
12753 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12756 mips_opts
.isa
= file_mips_isa
;
12757 mips_opts
.arch
= file_mips_arch
;
12759 else if (strncmp (name
, "arch=", 5) == 0)
12761 const struct mips_cpu_info
*p
;
12763 p
= mips_parse_cpu("internal use", name
+ 5);
12765 as_bad (_("unknown architecture %s"), name
+ 5);
12768 mips_opts
.arch
= p
->cpu
;
12769 mips_opts
.isa
= p
->isa
;
12772 else if (strncmp (name
, "mips", 4) == 0)
12774 const struct mips_cpu_info
*p
;
12776 p
= mips_parse_cpu("internal use", name
);
12778 as_bad (_("unknown ISA level %s"), name
+ 4);
12781 mips_opts
.arch
= p
->cpu
;
12782 mips_opts
.isa
= p
->isa
;
12786 as_bad (_("unknown ISA or architecture %s"), name
);
12788 switch (mips_opts
.isa
)
12796 mips_opts
.gp32
= 1;
12797 mips_opts
.fp32
= 1;
12804 mips_opts
.gp32
= 0;
12805 mips_opts
.fp32
= 0;
12808 as_bad (_("unknown ISA level %s"), name
+ 4);
12813 mips_opts
.gp32
= file_mips_gp32
;
12814 mips_opts
.fp32
= file_mips_fp32
;
12817 else if (strcmp (name
, "autoextend") == 0)
12818 mips_opts
.noautoextend
= 0;
12819 else if (strcmp (name
, "noautoextend") == 0)
12820 mips_opts
.noautoextend
= 1;
12821 else if (strcmp (name
, "push") == 0)
12823 struct mips_option_stack
*s
;
12825 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12826 s
->next
= mips_opts_stack
;
12827 s
->options
= mips_opts
;
12828 mips_opts_stack
= s
;
12830 else if (strcmp (name
, "pop") == 0)
12832 struct mips_option_stack
*s
;
12834 s
= mips_opts_stack
;
12836 as_bad (_(".set pop with no .set push"));
12839 /* If we're changing the reorder mode we need to handle
12840 delay slots correctly. */
12841 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12842 start_noreorder ();
12843 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12846 mips_opts
= s
->options
;
12847 mips_opts_stack
= s
->next
;
12851 else if (strcmp (name
, "sym32") == 0)
12852 mips_opts
.sym32
= TRUE
;
12853 else if (strcmp (name
, "nosym32") == 0)
12854 mips_opts
.sym32
= FALSE
;
12855 else if (strchr (name
, ','))
12857 /* Generic ".set" directive; use the generic handler. */
12858 *input_line_pointer
= ch
;
12859 input_line_pointer
= name
;
12865 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12867 *input_line_pointer
= ch
;
12868 demand_empty_rest_of_line ();
12871 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12872 .option pic2. It means to generate SVR4 PIC calls. */
12875 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12877 mips_pic
= SVR4_PIC
;
12878 mips_abicalls
= TRUE
;
12880 if (g_switch_seen
&& g_switch_value
!= 0)
12881 as_warn (_("-G may not be used with SVR4 PIC code"));
12882 g_switch_value
= 0;
12884 bfd_set_gp_size (stdoutput
, 0);
12885 demand_empty_rest_of_line ();
12888 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12889 PIC code. It sets the $gp register for the function based on the
12890 function address, which is in the register named in the argument.
12891 This uses a relocation against _gp_disp, which is handled specially
12892 by the linker. The result is:
12893 lui $gp,%hi(_gp_disp)
12894 addiu $gp,$gp,%lo(_gp_disp)
12895 addu $gp,$gp,.cpload argument
12896 The .cpload argument is normally $25 == $t9.
12898 The -mno-shared option changes this to:
12899 lui $gp,%hi(__gnu_local_gp)
12900 addiu $gp,$gp,%lo(__gnu_local_gp)
12901 and the argument is ignored. This saves an instruction, but the
12902 resulting code is not position independent; it uses an absolute
12903 address for __gnu_local_gp. Thus code assembled with -mno-shared
12904 can go into an ordinary executable, but not into a shared library. */
12907 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12913 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12914 .cpload is ignored. */
12915 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12921 /* .cpload should be in a .set noreorder section. */
12922 if (mips_opts
.noreorder
== 0)
12923 as_warn (_(".cpload not in noreorder section"));
12925 reg
= tc_get_register (0);
12927 /* If we need to produce a 64-bit address, we are better off using
12928 the default instruction sequence. */
12929 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12931 ex
.X_op
= O_symbol
;
12932 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12934 ex
.X_op_symbol
= NULL
;
12935 ex
.X_add_number
= 0;
12937 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12938 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12941 macro_build_lui (&ex
, mips_gp_register
);
12942 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12943 mips_gp_register
, BFD_RELOC_LO16
);
12945 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12946 mips_gp_register
, reg
);
12949 demand_empty_rest_of_line ();
12952 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12953 .cpsetup $reg1, offset|$reg2, label
12955 If offset is given, this results in:
12956 sd $gp, offset($sp)
12957 lui $gp, %hi(%neg(%gp_rel(label)))
12958 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12959 daddu $gp, $gp, $reg1
12961 If $reg2 is given, this results in:
12962 daddu $reg2, $gp, $0
12963 lui $gp, %hi(%neg(%gp_rel(label)))
12964 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12965 daddu $gp, $gp, $reg1
12966 $reg1 is normally $25 == $t9.
12968 The -mno-shared option replaces the last three instructions with
12970 addiu $gp,$gp,%lo(_gp) */
12973 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12975 expressionS ex_off
;
12976 expressionS ex_sym
;
12979 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12980 We also need NewABI support. */
12981 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12987 reg1
= tc_get_register (0);
12988 SKIP_WHITESPACE ();
12989 if (*input_line_pointer
!= ',')
12991 as_bad (_("missing argument separator ',' for .cpsetup"));
12995 ++input_line_pointer
;
12996 SKIP_WHITESPACE ();
12997 if (*input_line_pointer
== '$')
12999 mips_cpreturn_register
= tc_get_register (0);
13000 mips_cpreturn_offset
= -1;
13004 mips_cpreturn_offset
= get_absolute_expression ();
13005 mips_cpreturn_register
= -1;
13007 SKIP_WHITESPACE ();
13008 if (*input_line_pointer
!= ',')
13010 as_bad (_("missing argument separator ',' for .cpsetup"));
13014 ++input_line_pointer
;
13015 SKIP_WHITESPACE ();
13016 expression (&ex_sym
);
13019 if (mips_cpreturn_register
== -1)
13021 ex_off
.X_op
= O_constant
;
13022 ex_off
.X_add_symbol
= NULL
;
13023 ex_off
.X_op_symbol
= NULL
;
13024 ex_off
.X_add_number
= mips_cpreturn_offset
;
13026 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13027 BFD_RELOC_LO16
, SP
);
13030 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13031 mips_gp_register
, 0);
13033 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13035 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13036 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13039 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13040 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13041 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13044 mips_gp_register
, reg1
);
13050 ex
.X_op
= O_symbol
;
13051 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13052 ex
.X_op_symbol
= NULL
;
13053 ex
.X_add_number
= 0;
13055 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13056 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13058 macro_build_lui (&ex
, mips_gp_register
);
13059 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13060 mips_gp_register
, BFD_RELOC_LO16
);
13065 demand_empty_rest_of_line ();
13069 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13071 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13072 .cplocal is ignored. */
13073 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13079 mips_gp_register
= tc_get_register (0);
13080 demand_empty_rest_of_line ();
13083 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13084 offset from $sp. The offset is remembered, and after making a PIC
13085 call $gp is restored from that location. */
13088 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13092 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13093 .cprestore is ignored. */
13094 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13100 mips_cprestore_offset
= get_absolute_expression ();
13101 mips_cprestore_valid
= 1;
13103 ex
.X_op
= O_constant
;
13104 ex
.X_add_symbol
= NULL
;
13105 ex
.X_op_symbol
= NULL
;
13106 ex
.X_add_number
= mips_cprestore_offset
;
13109 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13110 SP
, HAVE_64BIT_ADDRESSES
);
13113 demand_empty_rest_of_line ();
13116 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13117 was given in the preceding .cpsetup, it results in:
13118 ld $gp, offset($sp)
13120 If a register $reg2 was given there, it results in:
13121 daddu $gp, $reg2, $0 */
13124 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13128 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13129 We also need NewABI support. */
13130 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13137 if (mips_cpreturn_register
== -1)
13139 ex
.X_op
= O_constant
;
13140 ex
.X_add_symbol
= NULL
;
13141 ex
.X_op_symbol
= NULL
;
13142 ex
.X_add_number
= mips_cpreturn_offset
;
13144 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13147 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13148 mips_cpreturn_register
, 0);
13151 demand_empty_rest_of_line ();
13154 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13155 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13156 use in DWARF debug information. */
13159 s_dtprel_internal (size_t bytes
)
13166 if (ex
.X_op
!= O_symbol
)
13168 as_bad (_("Unsupported use of %s"), (bytes
== 8
13171 ignore_rest_of_line ();
13174 p
= frag_more (bytes
);
13175 md_number_to_chars (p
, 0, bytes
);
13176 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13178 ? BFD_RELOC_MIPS_TLS_DTPREL64
13179 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13181 demand_empty_rest_of_line ();
13184 /* Handle .dtprelword. */
13187 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13189 s_dtprel_internal (4);
13192 /* Handle .dtpreldword. */
13195 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13197 s_dtprel_internal (8);
13200 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13201 code. It sets the offset to use in gp_rel relocations. */
13204 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13206 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13207 We also need NewABI support. */
13208 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13214 mips_gprel_offset
= get_absolute_expression ();
13216 demand_empty_rest_of_line ();
13219 /* Handle the .gpword pseudo-op. This is used when generating PIC
13220 code. It generates a 32 bit GP relative reloc. */
13223 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13225 segment_info_type
*si
;
13226 struct insn_label_list
*l
;
13231 /* When not generating PIC code, this is treated as .word. */
13232 if (mips_pic
!= SVR4_PIC
)
13238 si
= seg_info (now_seg
);
13239 l
= si
->label_list
;
13240 label
= l
!= NULL
? l
->label
: NULL
;
13241 mips_emit_delays ();
13243 mips_align (2, 0, label
);
13244 mips_clear_insn_labels ();
13248 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13250 as_bad (_("Unsupported use of .gpword"));
13251 ignore_rest_of_line ();
13255 md_number_to_chars (p
, 0, 4);
13256 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13257 BFD_RELOC_GPREL32
);
13259 demand_empty_rest_of_line ();
13263 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13265 segment_info_type
*si
;
13266 struct insn_label_list
*l
;
13271 /* When not generating PIC code, this is treated as .dword. */
13272 if (mips_pic
!= SVR4_PIC
)
13278 si
= seg_info (now_seg
);
13279 l
= si
->label_list
;
13280 label
= l
!= NULL
? l
->label
: NULL
;
13281 mips_emit_delays ();
13283 mips_align (3, 0, label
);
13284 mips_clear_insn_labels ();
13288 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13290 as_bad (_("Unsupported use of .gpdword"));
13291 ignore_rest_of_line ();
13295 md_number_to_chars (p
, 0, 8);
13296 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13297 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13299 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13300 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13301 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13303 demand_empty_rest_of_line ();
13306 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13307 tables in SVR4 PIC code. */
13310 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13314 /* This is ignored when not generating SVR4 PIC code. */
13315 if (mips_pic
!= SVR4_PIC
)
13321 /* Add $gp to the register named as an argument. */
13323 reg
= tc_get_register (0);
13324 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13327 demand_empty_rest_of_line ();
13330 /* Handle the .insn pseudo-op. This marks instruction labels in
13331 mips16 mode. This permits the linker to handle them specially,
13332 such as generating jalx instructions when needed. We also make
13333 them odd for the duration of the assembly, in order to generate the
13334 right sort of code. We will make them even in the adjust_symtab
13335 routine, while leaving them marked. This is convenient for the
13336 debugger and the disassembler. The linker knows to make them odd
13340 s_insn (int ignore ATTRIBUTE_UNUSED
)
13342 mips16_mark_labels ();
13344 demand_empty_rest_of_line ();
13347 /* Handle a .stabn directive. We need these in order to mark a label
13348 as being a mips16 text label correctly. Sometimes the compiler
13349 will emit a label, followed by a .stabn, and then switch sections.
13350 If the label and .stabn are in mips16 mode, then the label is
13351 really a mips16 text label. */
13354 s_mips_stab (int type
)
13357 mips16_mark_labels ();
13362 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13365 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13372 name
= input_line_pointer
;
13373 c
= get_symbol_end ();
13374 symbolP
= symbol_find_or_make (name
);
13375 S_SET_WEAK (symbolP
);
13376 *input_line_pointer
= c
;
13378 SKIP_WHITESPACE ();
13380 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13382 if (S_IS_DEFINED (symbolP
))
13384 as_bad ("ignoring attempt to redefine symbol %s",
13385 S_GET_NAME (symbolP
));
13386 ignore_rest_of_line ();
13390 if (*input_line_pointer
== ',')
13392 ++input_line_pointer
;
13393 SKIP_WHITESPACE ();
13397 if (exp
.X_op
!= O_symbol
)
13399 as_bad ("bad .weakext directive");
13400 ignore_rest_of_line ();
13403 symbol_set_value_expression (symbolP
, &exp
);
13406 demand_empty_rest_of_line ();
13409 /* Parse a register string into a number. Called from the ECOFF code
13410 to parse .frame. The argument is non-zero if this is the frame
13411 register, so that we can record it in mips_frame_reg. */
13414 tc_get_register (int frame
)
13418 SKIP_WHITESPACE ();
13419 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13423 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13424 mips_frame_reg_valid
= 1;
13425 mips_cprestore_valid
= 0;
13431 md_section_align (asection
*seg
, valueT addr
)
13433 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13437 /* We don't need to align ELF sections to the full alignment.
13438 However, Irix 5 may prefer that we align them at least to a 16
13439 byte boundary. We don't bother to align the sections if we
13440 are targeted for an embedded system. */
13441 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13447 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13450 /* Utility routine, called from above as well. If called while the
13451 input file is still being read, it's only an approximation. (For
13452 example, a symbol may later become defined which appeared to be
13453 undefined earlier.) */
13456 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13461 if (g_switch_value
> 0)
13463 const char *symname
;
13466 /* Find out whether this symbol can be referenced off the $gp
13467 register. It can be if it is smaller than the -G size or if
13468 it is in the .sdata or .sbss section. Certain symbols can
13469 not be referenced off the $gp, although it appears as though
13471 symname
= S_GET_NAME (sym
);
13472 if (symname
!= (const char *) NULL
13473 && (strcmp (symname
, "eprol") == 0
13474 || strcmp (symname
, "etext") == 0
13475 || strcmp (symname
, "_gp") == 0
13476 || strcmp (symname
, "edata") == 0
13477 || strcmp (symname
, "_fbss") == 0
13478 || strcmp (symname
, "_fdata") == 0
13479 || strcmp (symname
, "_ftext") == 0
13480 || strcmp (symname
, "end") == 0
13481 || strcmp (symname
, "_gp_disp") == 0))
13483 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13485 #ifndef NO_ECOFF_DEBUGGING
13486 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13487 && (symbol_get_obj (sym
)->ecoff_extern_size
13488 <= g_switch_value
))
13490 /* We must defer this decision until after the whole
13491 file has been read, since there might be a .extern
13492 after the first use of this symbol. */
13493 || (before_relaxing
13494 #ifndef NO_ECOFF_DEBUGGING
13495 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13497 && S_GET_VALUE (sym
) == 0)
13498 || (S_GET_VALUE (sym
) != 0
13499 && S_GET_VALUE (sym
) <= g_switch_value
)))
13503 const char *segname
;
13505 segname
= segment_name (S_GET_SEGMENT (sym
));
13506 assert (strcmp (segname
, ".lit8") != 0
13507 && strcmp (segname
, ".lit4") != 0);
13508 change
= (strcmp (segname
, ".sdata") != 0
13509 && strcmp (segname
, ".sbss") != 0
13510 && strncmp (segname
, ".sdata.", 7) != 0
13511 && strncmp (segname
, ".sbss.", 6) != 0
13512 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13513 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13518 /* We are not optimizing for the $gp register. */
13523 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13526 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13530 /* Handle the case of a symbol equated to another symbol. */
13531 while (symbol_equated_reloc_p (sym
))
13535 /* It's possible to get a loop here in a badly written program. */
13536 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13542 if (symbol_section_p (sym
))
13545 symsec
= S_GET_SEGMENT (sym
);
13547 /* This must duplicate the test in adjust_reloc_syms. */
13548 return (symsec
!= &bfd_und_section
13549 && symsec
!= &bfd_abs_section
13550 && !bfd_is_com_section (symsec
)
13551 && !s_is_linkonce (sym
, segtype
)
13553 /* A global or weak symbol is treated as external. */
13554 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13560 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13561 extended opcode. SEC is the section the frag is in. */
13564 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13567 const struct mips16_immed_operand
*op
;
13569 int mintiny
, maxtiny
;
13573 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13575 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13578 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13579 op
= mips16_immed_operands
;
13580 while (op
->type
!= type
)
13583 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13588 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13591 maxtiny
= 1 << op
->nbits
;
13596 maxtiny
= (1 << op
->nbits
) - 1;
13601 mintiny
= - (1 << (op
->nbits
- 1));
13602 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13605 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13606 val
= S_GET_VALUE (fragp
->fr_symbol
);
13607 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13613 /* We won't have the section when we are called from
13614 mips_relax_frag. However, we will always have been called
13615 from md_estimate_size_before_relax first. If this is a
13616 branch to a different section, we mark it as such. If SEC is
13617 NULL, and the frag is not marked, then it must be a branch to
13618 the same section. */
13621 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13626 /* Must have been called from md_estimate_size_before_relax. */
13629 fragp
->fr_subtype
=
13630 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13632 /* FIXME: We should support this, and let the linker
13633 catch branches and loads that are out of range. */
13634 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13635 _("unsupported PC relative reference to different section"));
13639 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13640 /* Assume non-extended on the first relaxation pass.
13641 The address we have calculated will be bogus if this is
13642 a forward branch to another frag, as the forward frag
13643 will have fr_address == 0. */
13647 /* In this case, we know for sure that the symbol fragment is in
13648 the same section. If the relax_marker of the symbol fragment
13649 differs from the relax_marker of this fragment, we have not
13650 yet adjusted the symbol fragment fr_address. We want to add
13651 in STRETCH in order to get a better estimate of the address.
13652 This particularly matters because of the shift bits. */
13654 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13658 /* Adjust stretch for any alignment frag. Note that if have
13659 been expanding the earlier code, the symbol may be
13660 defined in what appears to be an earlier frag. FIXME:
13661 This doesn't handle the fr_subtype field, which specifies
13662 a maximum number of bytes to skip when doing an
13664 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13666 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13669 stretch
= - ((- stretch
)
13670 & ~ ((1 << (int) f
->fr_offset
) - 1));
13672 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13681 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13683 /* The base address rules are complicated. The base address of
13684 a branch is the following instruction. The base address of a
13685 PC relative load or add is the instruction itself, but if it
13686 is in a delay slot (in which case it can not be extended) use
13687 the address of the instruction whose delay slot it is in. */
13688 if (type
== 'p' || type
== 'q')
13692 /* If we are currently assuming that this frag should be
13693 extended, then, the current address is two bytes
13695 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13698 /* Ignore the low bit in the target, since it will be set
13699 for a text label. */
13700 if ((val
& 1) != 0)
13703 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13705 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13708 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13710 /* Branch offsets have an implicit 0 in the lowest bit. */
13711 if (type
== 'p' || type
== 'q')
13714 /* If any of the shifted bits are set, we must use an extended
13715 opcode. If the address depends on the size of this
13716 instruction, this can lead to a loop, so we arrange to always
13717 use an extended opcode. We only check this when we are in
13718 the main relaxation loop, when SEC is NULL. */
13719 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13721 fragp
->fr_subtype
=
13722 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13726 /* If we are about to mark a frag as extended because the value
13727 is precisely maxtiny + 1, then there is a chance of an
13728 infinite loop as in the following code:
13733 In this case when the la is extended, foo is 0x3fc bytes
13734 away, so the la can be shrunk, but then foo is 0x400 away, so
13735 the la must be extended. To avoid this loop, we mark the
13736 frag as extended if it was small, and is about to become
13737 extended with a value of maxtiny + 1. */
13738 if (val
== ((maxtiny
+ 1) << op
->shift
)
13739 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13742 fragp
->fr_subtype
=
13743 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13747 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13748 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13750 if ((val
& ((1 << op
->shift
) - 1)) != 0
13751 || val
< (mintiny
<< op
->shift
)
13752 || val
> (maxtiny
<< op
->shift
))
13758 /* Compute the length of a branch sequence, and adjust the
13759 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13760 worst-case length is computed, with UPDATE being used to indicate
13761 whether an unconditional (-1), branch-likely (+1) or regular (0)
13762 branch is to be computed. */
13764 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13766 bfd_boolean toofar
;
13770 && S_IS_DEFINED (fragp
->fr_symbol
)
13771 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13776 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13778 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13782 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13785 /* If the symbol is not defined or it's in a different segment,
13786 assume the user knows what's going on and emit a short
13792 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13794 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13795 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13796 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13802 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13805 if (mips_pic
!= NO_PIC
)
13807 /* Additional space for PIC loading of target address. */
13809 if (mips_opts
.isa
== ISA_MIPS1
)
13810 /* Additional space for $at-stabilizing nop. */
13814 /* If branch is conditional. */
13815 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13822 /* Estimate the size of a frag before relaxing. Unless this is the
13823 mips16, we are not really relaxing here, and the final size is
13824 encoded in the subtype information. For the mips16, we have to
13825 decide whether we are using an extended opcode or not. */
13828 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13832 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13835 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13837 return fragp
->fr_var
;
13840 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13841 /* We don't want to modify the EXTENDED bit here; it might get us
13842 into infinite loops. We change it only in mips_relax_frag(). */
13843 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13845 if (mips_pic
== NO_PIC
)
13846 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13847 else if (mips_pic
== SVR4_PIC
)
13848 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13849 else if (mips_pic
== VXWORKS_PIC
)
13850 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13857 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13858 return -RELAX_FIRST (fragp
->fr_subtype
);
13861 return -RELAX_SECOND (fragp
->fr_subtype
);
13864 /* This is called to see whether a reloc against a defined symbol
13865 should be converted into a reloc against a section. */
13868 mips_fix_adjustable (fixS
*fixp
)
13870 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13871 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13874 if (fixp
->fx_addsy
== NULL
)
13877 /* If symbol SYM is in a mergeable section, relocations of the form
13878 SYM + 0 can usually be made section-relative. The mergeable data
13879 is then identified by the section offset rather than by the symbol.
13881 However, if we're generating REL LO16 relocations, the offset is split
13882 between the LO16 and parterning high part relocation. The linker will
13883 need to recalculate the complete offset in order to correctly identify
13886 The linker has traditionally not looked for the parterning high part
13887 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13888 placed anywhere. Rather than break backwards compatibility by changing
13889 this, it seems better not to force the issue, and instead keep the
13890 original symbol. This will work with either linker behavior. */
13891 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13892 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13893 || reloc_needs_lo_p (fixp
->fx_r_type
))
13894 && HAVE_IN_PLACE_ADDENDS
13895 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13899 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13900 to a floating-point stub. The same is true for non-R_MIPS16_26
13901 relocations against MIPS16 functions; in this case, the stub becomes
13902 the function's canonical address.
13904 Floating-point stubs are stored in unique .mips16.call.* or
13905 .mips16.fn.* sections. If a stub T for function F is in section S,
13906 the first relocation in section S must be against F; this is how the
13907 linker determines the target function. All relocations that might
13908 resolve to T must also be against F. We therefore have the following
13909 restrictions, which are given in an intentionally-redundant way:
13911 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
13914 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
13915 if that stub might be used.
13917 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
13920 4. We cannot reduce a stub's relocations against MIPS16 symbols if
13921 that stub might be used.
13923 There is a further restriction:
13925 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
13926 on targets with in-place addends; the relocation field cannot
13927 encode the low bit.
13929 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
13930 against a MIPS16 symbol.
13932 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
13933 relocation against some symbol R, no relocation against R may be
13934 reduced. (Note that this deals with (2) as well as (1) because
13935 relocations against global symbols will never be reduced on ELF
13936 targets.) This approach is a little simpler than trying to detect
13937 stub sections, and gives the "all or nothing" per-symbol consistency
13938 that we have for MIPS16 symbols. */
13940 && fixp
->fx_subsy
== NULL
13941 && (S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13942 || *symbol_get_tc (fixp
->fx_addsy
)))
13949 /* Translate internal representation of relocation info to BFD target
13953 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13955 static arelent
*retval
[4];
13957 bfd_reloc_code_real_type code
;
13959 memset (retval
, 0, sizeof(retval
));
13960 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13961 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13962 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13963 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13965 if (fixp
->fx_pcrel
)
13967 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13969 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13970 Relocations want only the symbol offset. */
13971 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13974 /* A gruesome hack which is a result of the gruesome gas
13975 reloc handling. What's worse, for COFF (as opposed to
13976 ECOFF), we might need yet another copy of reloc->address.
13977 See bfd_install_relocation. */
13978 reloc
->addend
+= reloc
->address
;
13982 reloc
->addend
= fixp
->fx_addnumber
;
13984 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13985 entry to be used in the relocation's section offset. */
13986 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13988 reloc
->address
= reloc
->addend
;
13992 code
= fixp
->fx_r_type
;
13994 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13995 if (reloc
->howto
== NULL
)
13997 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13998 _("Can not represent %s relocation in this object file format"),
13999 bfd_get_reloc_code_name (code
));
14006 /* Relax a machine dependent frag. This returns the amount by which
14007 the current size of the frag should change. */
14010 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14012 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14014 offsetT old_var
= fragp
->fr_var
;
14016 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14018 return fragp
->fr_var
- old_var
;
14021 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14024 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14026 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14028 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14033 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14035 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14042 /* Convert a machine dependent frag. */
14045 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14047 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14050 unsigned long insn
;
14054 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14056 if (target_big_endian
)
14057 insn
= bfd_getb32 (buf
);
14059 insn
= bfd_getl32 (buf
);
14061 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14063 /* We generate a fixup instead of applying it right now
14064 because, if there are linker relaxations, we're going to
14065 need the relocations. */
14066 exp
.X_op
= O_symbol
;
14067 exp
.X_add_symbol
= fragp
->fr_symbol
;
14068 exp
.X_add_number
= fragp
->fr_offset
;
14070 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14071 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14072 fixp
->fx_file
= fragp
->fr_file
;
14073 fixp
->fx_line
= fragp
->fr_line
;
14075 md_number_to_chars ((char *) buf
, insn
, 4);
14082 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14083 _("relaxed out-of-range branch into a jump"));
14085 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14088 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14090 /* Reverse the branch. */
14091 switch ((insn
>> 28) & 0xf)
14094 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14095 have the condition reversed by tweaking a single
14096 bit, and their opcodes all have 0x4???????. */
14097 assert ((insn
& 0xf1000000) == 0x41000000);
14098 insn
^= 0x00010000;
14102 /* bltz 0x04000000 bgez 0x04010000
14103 bltzal 0x04100000 bgezal 0x04110000 */
14104 assert ((insn
& 0xfc0e0000) == 0x04000000);
14105 insn
^= 0x00010000;
14109 /* beq 0x10000000 bne 0x14000000
14110 blez 0x18000000 bgtz 0x1c000000 */
14111 insn
^= 0x04000000;
14119 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14121 /* Clear the and-link bit. */
14122 assert ((insn
& 0xfc1c0000) == 0x04100000);
14124 /* bltzal 0x04100000 bgezal 0x04110000
14125 bltzall 0x04120000 bgezall 0x04130000 */
14126 insn
&= ~0x00100000;
14129 /* Branch over the branch (if the branch was likely) or the
14130 full jump (not likely case). Compute the offset from the
14131 current instruction to branch to. */
14132 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14136 /* How many bytes in instructions we've already emitted? */
14137 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14138 /* How many bytes in instructions from here to the end? */
14139 i
= fragp
->fr_var
- i
;
14141 /* Convert to instruction count. */
14143 /* Branch counts from the next instruction. */
14146 /* Branch over the jump. */
14147 md_number_to_chars ((char *) buf
, insn
, 4);
14151 md_number_to_chars ((char *) buf
, 0, 4);
14154 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14156 /* beql $0, $0, 2f */
14158 /* Compute the PC offset from the current instruction to
14159 the end of the variable frag. */
14160 /* How many bytes in instructions we've already emitted? */
14161 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14162 /* How many bytes in instructions from here to the end? */
14163 i
= fragp
->fr_var
- i
;
14164 /* Convert to instruction count. */
14166 /* Don't decrement i, because we want to branch over the
14170 md_number_to_chars ((char *) buf
, insn
, 4);
14173 md_number_to_chars ((char *) buf
, 0, 4);
14178 if (mips_pic
== NO_PIC
)
14181 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14182 ? 0x0c000000 : 0x08000000);
14183 exp
.X_op
= O_symbol
;
14184 exp
.X_add_symbol
= fragp
->fr_symbol
;
14185 exp
.X_add_number
= fragp
->fr_offset
;
14187 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14188 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14189 fixp
->fx_file
= fragp
->fr_file
;
14190 fixp
->fx_line
= fragp
->fr_line
;
14192 md_number_to_chars ((char *) buf
, insn
, 4);
14197 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14198 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14199 exp
.X_op
= O_symbol
;
14200 exp
.X_add_symbol
= fragp
->fr_symbol
;
14201 exp
.X_add_number
= fragp
->fr_offset
;
14203 if (fragp
->fr_offset
)
14205 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14206 exp
.X_add_number
= 0;
14209 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14210 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14211 fixp
->fx_file
= fragp
->fr_file
;
14212 fixp
->fx_line
= fragp
->fr_line
;
14214 md_number_to_chars ((char *) buf
, insn
, 4);
14217 if (mips_opts
.isa
== ISA_MIPS1
)
14220 md_number_to_chars ((char *) buf
, 0, 4);
14224 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14225 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14227 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14228 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14229 fixp
->fx_file
= fragp
->fr_file
;
14230 fixp
->fx_line
= fragp
->fr_line
;
14232 md_number_to_chars ((char *) buf
, insn
, 4);
14236 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14241 md_number_to_chars ((char *) buf
, insn
, 4);
14246 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14247 + fragp
->fr_fix
+ fragp
->fr_var
);
14249 fragp
->fr_fix
+= fragp
->fr_var
;
14254 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14257 const struct mips16_immed_operand
*op
;
14258 bfd_boolean small
, ext
;
14261 unsigned long insn
;
14262 bfd_boolean use_extend
;
14263 unsigned short extend
;
14265 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14266 op
= mips16_immed_operands
;
14267 while (op
->type
!= type
)
14270 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14281 resolve_symbol_value (fragp
->fr_symbol
);
14282 val
= S_GET_VALUE (fragp
->fr_symbol
);
14287 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14289 /* The rules for the base address of a PC relative reloc are
14290 complicated; see mips16_extended_frag. */
14291 if (type
== 'p' || type
== 'q')
14296 /* Ignore the low bit in the target, since it will be
14297 set for a text label. */
14298 if ((val
& 1) != 0)
14301 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14303 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14306 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14309 /* Make sure the section winds up with the alignment we have
14312 record_alignment (asec
, op
->shift
);
14316 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14317 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14318 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14319 _("extended instruction in delay slot"));
14321 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14323 if (target_big_endian
)
14324 insn
= bfd_getb16 (buf
);
14326 insn
= bfd_getl16 (buf
);
14328 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14329 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14330 small
, ext
, &insn
, &use_extend
, &extend
);
14334 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14335 fragp
->fr_fix
+= 2;
14339 md_number_to_chars ((char *) buf
, insn
, 2);
14340 fragp
->fr_fix
+= 2;
14348 first
= RELAX_FIRST (fragp
->fr_subtype
);
14349 second
= RELAX_SECOND (fragp
->fr_subtype
);
14350 fixp
= (fixS
*) fragp
->fr_opcode
;
14352 /* Possibly emit a warning if we've chosen the longer option. */
14353 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14354 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14356 const char *msg
= macro_warning (fragp
->fr_subtype
);
14358 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14361 /* Go through all the fixups for the first sequence. Disable them
14362 (by marking them as done) if we're going to use the second
14363 sequence instead. */
14365 && fixp
->fx_frag
== fragp
14366 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14368 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14370 fixp
= fixp
->fx_next
;
14373 /* Go through the fixups for the second sequence. Disable them if
14374 we're going to use the first sequence, otherwise adjust their
14375 addresses to account for the relaxation. */
14376 while (fixp
&& fixp
->fx_frag
== fragp
)
14378 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14379 fixp
->fx_where
-= first
;
14382 fixp
= fixp
->fx_next
;
14385 /* Now modify the frag contents. */
14386 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14390 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14391 memmove (start
, start
+ first
, second
);
14392 fragp
->fr_fix
-= first
;
14395 fragp
->fr_fix
-= second
;
14401 /* This function is called after the relocs have been generated.
14402 We've been storing mips16 text labels as odd. Here we convert them
14403 back to even for the convenience of the debugger. */
14406 mips_frob_file_after_relocs (void)
14409 unsigned int count
, i
;
14414 syms
= bfd_get_outsymbols (stdoutput
);
14415 count
= bfd_get_symcount (stdoutput
);
14416 for (i
= 0; i
< count
; i
++, syms
++)
14418 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14419 && ((*syms
)->value
& 1) != 0)
14421 (*syms
)->value
&= ~1;
14422 /* If the symbol has an odd size, it was probably computed
14423 incorrectly, so adjust that as well. */
14424 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14425 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14432 /* This function is called whenever a label is defined. It is used
14433 when handling branch delays; if a branch has a label, we assume we
14434 can not move it. */
14437 mips_define_label (symbolS
*sym
)
14439 segment_info_type
*si
= seg_info (now_seg
);
14440 struct insn_label_list
*l
;
14442 if (free_insn_labels
== NULL
)
14443 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14446 l
= free_insn_labels
;
14447 free_insn_labels
= l
->next
;
14451 l
->next
= si
->label_list
;
14452 si
->label_list
= l
;
14455 dwarf2_emit_label (sym
);
14459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14461 /* Some special processing for a MIPS ELF file. */
14464 mips_elf_final_processing (void)
14466 /* Write out the register information. */
14467 if (mips_abi
!= N64_ABI
)
14471 s
.ri_gprmask
= mips_gprmask
;
14472 s
.ri_cprmask
[0] = mips_cprmask
[0];
14473 s
.ri_cprmask
[1] = mips_cprmask
[1];
14474 s
.ri_cprmask
[2] = mips_cprmask
[2];
14475 s
.ri_cprmask
[3] = mips_cprmask
[3];
14476 /* The gp_value field is set by the MIPS ELF backend. */
14478 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14479 ((Elf32_External_RegInfo
*)
14480 mips_regmask_frag
));
14484 Elf64_Internal_RegInfo s
;
14486 s
.ri_gprmask
= mips_gprmask
;
14488 s
.ri_cprmask
[0] = mips_cprmask
[0];
14489 s
.ri_cprmask
[1] = mips_cprmask
[1];
14490 s
.ri_cprmask
[2] = mips_cprmask
[2];
14491 s
.ri_cprmask
[3] = mips_cprmask
[3];
14492 /* The gp_value field is set by the MIPS ELF backend. */
14494 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14495 ((Elf64_External_RegInfo
*)
14496 mips_regmask_frag
));
14499 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14500 sort of BFD interface for this. */
14501 if (mips_any_noreorder
)
14502 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14503 if (mips_pic
!= NO_PIC
)
14505 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14506 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14509 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14511 /* Set MIPS ELF flags for ASEs. */
14512 /* We may need to define a new flag for DSP ASE, and set this flag when
14513 file_ase_dsp is true. */
14514 /* Same for DSP R2. */
14515 /* We may need to define a new flag for MT ASE, and set this flag when
14516 file_ase_mt is true. */
14517 if (file_ase_mips16
)
14518 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14519 #if 0 /* XXX FIXME */
14520 if (file_ase_mips3d
)
14521 elf_elfheader (stdoutput
)->e_flags
|= ???;
14524 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14526 /* Set the MIPS ELF ABI flags. */
14527 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14528 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14529 else if (mips_abi
== O64_ABI
)
14530 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14531 else if (mips_abi
== EABI_ABI
)
14533 if (!file_mips_gp32
)
14534 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14536 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14538 else if (mips_abi
== N32_ABI
)
14539 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14541 /* Nothing to do for N64_ABI. */
14543 if (mips_32bitmode
)
14544 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14546 #if 0 /* XXX FIXME */
14547 /* 32 bit code with 64 bit FP registers. */
14548 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14549 elf_elfheader (stdoutput
)->e_flags
|= ???;
14553 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14555 typedef struct proc
{
14557 symbolS
*func_end_sym
;
14558 unsigned long reg_mask
;
14559 unsigned long reg_offset
;
14560 unsigned long fpreg_mask
;
14561 unsigned long fpreg_offset
;
14562 unsigned long frame_offset
;
14563 unsigned long frame_reg
;
14564 unsigned long pc_reg
;
14567 static procS cur_proc
;
14568 static procS
*cur_proc_ptr
;
14569 static int numprocs
;
14571 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14575 mips_nop_opcode (void)
14577 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14580 /* Fill in an rs_align_code fragment. This only needs to do something
14581 for MIPS16 code, where 0 is not a nop. */
14584 mips_handle_align (fragS
*fragp
)
14588 if (fragp
->fr_type
!= rs_align_code
)
14591 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14596 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14602 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14608 md_obj_begin (void)
14615 /* Check for premature end, nesting errors, etc. */
14617 as_warn (_("missing .end at end of assembly"));
14626 if (*input_line_pointer
== '-')
14628 ++input_line_pointer
;
14631 if (!ISDIGIT (*input_line_pointer
))
14632 as_bad (_("expected simple number"));
14633 if (input_line_pointer
[0] == '0')
14635 if (input_line_pointer
[1] == 'x')
14637 input_line_pointer
+= 2;
14638 while (ISXDIGIT (*input_line_pointer
))
14641 val
|= hex_value (*input_line_pointer
++);
14643 return negative
? -val
: val
;
14647 ++input_line_pointer
;
14648 while (ISDIGIT (*input_line_pointer
))
14651 val
|= *input_line_pointer
++ - '0';
14653 return negative
? -val
: val
;
14656 if (!ISDIGIT (*input_line_pointer
))
14658 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14659 *input_line_pointer
, *input_line_pointer
);
14660 as_warn (_("invalid number"));
14663 while (ISDIGIT (*input_line_pointer
))
14666 val
+= *input_line_pointer
++ - '0';
14668 return negative
? -val
: val
;
14671 /* The .file directive; just like the usual .file directive, but there
14672 is an initial number which is the ECOFF file index. In the non-ECOFF
14673 case .file implies DWARF-2. */
14676 s_mips_file (int x ATTRIBUTE_UNUSED
)
14678 static int first_file_directive
= 0;
14680 if (ECOFF_DEBUGGING
)
14689 filename
= dwarf2_directive_file (0);
14691 /* Versions of GCC up to 3.1 start files with a ".file"
14692 directive even for stabs output. Make sure that this
14693 ".file" is handled. Note that you need a version of GCC
14694 after 3.1 in order to support DWARF-2 on MIPS. */
14695 if (filename
!= NULL
&& ! first_file_directive
)
14697 (void) new_logical_line (filename
, -1);
14698 s_app_file_string (filename
, 0);
14700 first_file_directive
= 1;
14704 /* The .loc directive, implying DWARF-2. */
14707 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14709 if (!ECOFF_DEBUGGING
)
14710 dwarf2_directive_loc (0);
14713 /* The .end directive. */
14716 s_mips_end (int x ATTRIBUTE_UNUSED
)
14720 /* Following functions need their own .frame and .cprestore directives. */
14721 mips_frame_reg_valid
= 0;
14722 mips_cprestore_valid
= 0;
14724 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14727 demand_empty_rest_of_line ();
14732 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14733 as_warn (_(".end not in text section"));
14737 as_warn (_(".end directive without a preceding .ent directive."));
14738 demand_empty_rest_of_line ();
14744 assert (S_GET_NAME (p
));
14745 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14746 as_warn (_(".end symbol does not match .ent symbol."));
14748 if (debug_type
== DEBUG_STABS
)
14749 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14753 as_warn (_(".end directive missing or unknown symbol"));
14756 /* Create an expression to calculate the size of the function. */
14757 if (p
&& cur_proc_ptr
)
14759 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14760 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14763 exp
->X_op
= O_subtract
;
14764 exp
->X_add_symbol
= symbol_temp_new_now ();
14765 exp
->X_op_symbol
= p
;
14766 exp
->X_add_number
= 0;
14768 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14771 /* Generate a .pdr section. */
14772 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14774 segT saved_seg
= now_seg
;
14775 subsegT saved_subseg
= now_subseg
;
14780 dot
= frag_now_fix ();
14782 #ifdef md_flush_pending_output
14783 md_flush_pending_output ();
14787 subseg_set (pdr_seg
, 0);
14789 /* Write the symbol. */
14790 exp
.X_op
= O_symbol
;
14791 exp
.X_add_symbol
= p
;
14792 exp
.X_add_number
= 0;
14793 emit_expr (&exp
, 4);
14795 fragp
= frag_more (7 * 4);
14797 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14798 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14799 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14800 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14801 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14802 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14803 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14805 subseg_set (saved_seg
, saved_subseg
);
14807 #endif /* OBJ_ELF */
14809 cur_proc_ptr
= NULL
;
14812 /* The .aent and .ent directives. */
14815 s_mips_ent (int aent
)
14819 symbolP
= get_symbol ();
14820 if (*input_line_pointer
== ',')
14821 ++input_line_pointer
;
14822 SKIP_WHITESPACE ();
14823 if (ISDIGIT (*input_line_pointer
)
14824 || *input_line_pointer
== '-')
14827 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14828 as_warn (_(".ent or .aent not in text section."));
14830 if (!aent
&& cur_proc_ptr
)
14831 as_warn (_("missing .end"));
14835 /* This function needs its own .frame and .cprestore directives. */
14836 mips_frame_reg_valid
= 0;
14837 mips_cprestore_valid
= 0;
14839 cur_proc_ptr
= &cur_proc
;
14840 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14842 cur_proc_ptr
->func_sym
= symbolP
;
14844 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14848 if (debug_type
== DEBUG_STABS
)
14849 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14850 S_GET_NAME (symbolP
));
14853 demand_empty_rest_of_line ();
14856 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14857 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14858 s_mips_frame is used so that we can set the PDR information correctly.
14859 We can't use the ecoff routines because they make reference to the ecoff
14860 symbol table (in the mdebug section). */
14863 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14866 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14870 if (cur_proc_ptr
== (procS
*) NULL
)
14872 as_warn (_(".frame outside of .ent"));
14873 demand_empty_rest_of_line ();
14877 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14879 SKIP_WHITESPACE ();
14880 if (*input_line_pointer
++ != ','
14881 || get_absolute_expression_and_terminator (&val
) != ',')
14883 as_warn (_("Bad .frame directive"));
14884 --input_line_pointer
;
14885 demand_empty_rest_of_line ();
14889 cur_proc_ptr
->frame_offset
= val
;
14890 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14892 demand_empty_rest_of_line ();
14895 #endif /* OBJ_ELF */
14899 /* The .fmask and .mask directives. If the mdebug section is present
14900 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14901 embedded targets, s_mips_mask is used so that we can set the PDR
14902 information correctly. We can't use the ecoff routines because they
14903 make reference to the ecoff symbol table (in the mdebug section). */
14906 s_mips_mask (int reg_type
)
14909 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14913 if (cur_proc_ptr
== (procS
*) NULL
)
14915 as_warn (_(".mask/.fmask outside of .ent"));
14916 demand_empty_rest_of_line ();
14920 if (get_absolute_expression_and_terminator (&mask
) != ',')
14922 as_warn (_("Bad .mask/.fmask directive"));
14923 --input_line_pointer
;
14924 demand_empty_rest_of_line ();
14928 off
= get_absolute_expression ();
14930 if (reg_type
== 'F')
14932 cur_proc_ptr
->fpreg_mask
= mask
;
14933 cur_proc_ptr
->fpreg_offset
= off
;
14937 cur_proc_ptr
->reg_mask
= mask
;
14938 cur_proc_ptr
->reg_offset
= off
;
14941 demand_empty_rest_of_line ();
14944 #endif /* OBJ_ELF */
14945 s_ignore (reg_type
);
14948 /* A table describing all the processors gas knows about. Names are
14949 matched in the order listed.
14951 To ease comparison, please keep this table in the same order as
14952 gcc's mips_cpu_info_table[]. */
14953 static const struct mips_cpu_info mips_cpu_info_table
[] =
14955 /* Entries for generic ISAs */
14956 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14957 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14958 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14959 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14960 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14961 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14962 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14963 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14964 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14967 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14968 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14969 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14972 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14975 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14976 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14977 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14978 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14979 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14980 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14981 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14982 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14983 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14984 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14985 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14986 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14987 /* ST Microelectronics Loongson 2E and 2F cores */
14988 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
14989 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
14992 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14993 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14994 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14995 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14996 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14997 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14998 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14999 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15000 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15001 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15002 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15003 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15004 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15007 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15008 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15009 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15010 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15012 /* MIPS 32 Release 2 */
15013 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15014 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15015 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15016 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15017 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15018 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15019 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15020 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15021 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15022 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15023 /* Deprecated forms of the above. */
15024 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15025 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15026 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15027 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15028 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15029 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15030 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15031 /* Deprecated forms of the above. */
15032 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15033 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15034 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15035 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15036 ISA_MIPS32R2
, CPU_MIPS32R2
},
15037 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15038 ISA_MIPS32R2
, CPU_MIPS32R2
},
15039 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15040 ISA_MIPS32R2
, CPU_MIPS32R2
},
15041 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15042 ISA_MIPS32R2
, CPU_MIPS32R2
},
15043 /* Deprecated forms of the above. */
15044 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15045 ISA_MIPS32R2
, CPU_MIPS32R2
},
15046 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15047 ISA_MIPS32R2
, CPU_MIPS32R2
},
15048 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15049 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15050 ISA_MIPS32R2
, CPU_MIPS32R2
},
15051 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15052 ISA_MIPS32R2
, CPU_MIPS32R2
},
15053 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15054 ISA_MIPS32R2
, CPU_MIPS32R2
},
15055 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15056 ISA_MIPS32R2
, CPU_MIPS32R2
},
15057 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15058 ISA_MIPS32R2
, CPU_MIPS32R2
},
15059 /* Deprecated forms of the above. */
15060 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15061 ISA_MIPS32R2
, CPU_MIPS32R2
},
15062 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15063 ISA_MIPS32R2
, CPU_MIPS32R2
},
15066 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15067 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15068 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15069 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15071 /* MIPS 64 Release 2 */
15073 /* Broadcom SB-1 CPU core */
15074 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15075 ISA_MIPS64
, CPU_SB1
},
15076 /* Broadcom SB-1A CPU core */
15077 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15078 ISA_MIPS64
, CPU_SB1
},
15080 /* Cavium Networks Octeon CPU core */
15081 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15088 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15089 with a final "000" replaced by "k". Ignore case.
15091 Note: this function is shared between GCC and GAS. */
15094 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15096 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15097 given
++, canonical
++;
15099 return ((*given
== 0 && *canonical
== 0)
15100 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15104 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15105 CPU name. We've traditionally allowed a lot of variation here.
15107 Note: this function is shared between GCC and GAS. */
15110 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15112 /* First see if the name matches exactly, or with a final "000"
15113 turned into "k". */
15114 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15117 /* If not, try comparing based on numerical designation alone.
15118 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15119 if (TOLOWER (*given
) == 'r')
15121 if (!ISDIGIT (*given
))
15124 /* Skip over some well-known prefixes in the canonical name,
15125 hoping to find a number there too. */
15126 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15128 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15130 else if (TOLOWER (canonical
[0]) == 'r')
15133 return mips_strict_matching_cpu_name_p (canonical
, given
);
15137 /* Parse an option that takes the name of a processor as its argument.
15138 OPTION is the name of the option and CPU_STRING is the argument.
15139 Return the corresponding processor enumeration if the CPU_STRING is
15140 recognized, otherwise report an error and return null.
15142 A similar function exists in GCC. */
15144 static const struct mips_cpu_info
*
15145 mips_parse_cpu (const char *option
, const char *cpu_string
)
15147 const struct mips_cpu_info
*p
;
15149 /* 'from-abi' selects the most compatible architecture for the given
15150 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15151 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15152 version. Look first at the -mgp options, if given, otherwise base
15153 the choice on MIPS_DEFAULT_64BIT.
15155 Treat NO_ABI like the EABIs. One reason to do this is that the
15156 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15157 architecture. This code picks MIPS I for 'mips' and MIPS III for
15158 'mips64', just as we did in the days before 'from-abi'. */
15159 if (strcasecmp (cpu_string
, "from-abi") == 0)
15161 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15162 return mips_cpu_info_from_isa (ISA_MIPS1
);
15164 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15165 return mips_cpu_info_from_isa (ISA_MIPS3
);
15167 if (file_mips_gp32
>= 0)
15168 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15170 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15175 /* 'default' has traditionally been a no-op. Probably not very useful. */
15176 if (strcasecmp (cpu_string
, "default") == 0)
15179 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15180 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15183 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15187 /* Return the canonical processor information for ISA (a member of the
15188 ISA_MIPS* enumeration). */
15190 static const struct mips_cpu_info
*
15191 mips_cpu_info_from_isa (int isa
)
15195 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15196 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15197 && isa
== mips_cpu_info_table
[i
].isa
)
15198 return (&mips_cpu_info_table
[i
]);
15203 static const struct mips_cpu_info
*
15204 mips_cpu_info_from_arch (int arch
)
15208 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15209 if (arch
== mips_cpu_info_table
[i
].cpu
)
15210 return (&mips_cpu_info_table
[i
]);
15216 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15220 fprintf (stream
, "%24s", "");
15225 fprintf (stream
, ", ");
15229 if (*col_p
+ strlen (string
) > 72)
15231 fprintf (stream
, "\n%24s", "");
15235 fprintf (stream
, "%s", string
);
15236 *col_p
+= strlen (string
);
15242 md_show_usage (FILE *stream
)
15247 fprintf (stream
, _("\
15249 -EB generate big endian output\n\
15250 -EL generate little endian output\n\
15251 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15252 -G NUM allow referencing objects up to NUM bytes\n\
15253 implicitly with the gp register [default 8]\n"));
15254 fprintf (stream
, _("\
15255 -mips1 generate MIPS ISA I instructions\n\
15256 -mips2 generate MIPS ISA II instructions\n\
15257 -mips3 generate MIPS ISA III instructions\n\
15258 -mips4 generate MIPS ISA IV instructions\n\
15259 -mips5 generate MIPS ISA V instructions\n\
15260 -mips32 generate MIPS32 ISA instructions\n\
15261 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15262 -mips64 generate MIPS64 ISA instructions\n\
15263 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15264 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15268 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15269 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15270 show (stream
, "from-abi", &column
, &first
);
15271 fputc ('\n', stream
);
15273 fprintf (stream
, _("\
15274 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15275 -no-mCPU don't generate code specific to CPU.\n\
15276 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15280 show (stream
, "3900", &column
, &first
);
15281 show (stream
, "4010", &column
, &first
);
15282 show (stream
, "4100", &column
, &first
);
15283 show (stream
, "4650", &column
, &first
);
15284 fputc ('\n', stream
);
15286 fprintf (stream
, _("\
15287 -mips16 generate mips16 instructions\n\
15288 -no-mips16 do not generate mips16 instructions\n"));
15289 fprintf (stream
, _("\
15290 -msmartmips generate smartmips instructions\n\
15291 -mno-smartmips do not generate smartmips instructions\n"));
15292 fprintf (stream
, _("\
15293 -mdsp generate DSP instructions\n\
15294 -mno-dsp do not generate DSP instructions\n"));
15295 fprintf (stream
, _("\
15296 -mdspr2 generate DSP R2 instructions\n\
15297 -mno-dspr2 do not generate DSP R2 instructions\n"));
15298 fprintf (stream
, _("\
15299 -mmt generate MT instructions\n\
15300 -mno-mt do not generate MT instructions\n"));
15301 fprintf (stream
, _("\
15302 -mfix-vr4120 work around certain VR4120 errata\n\
15303 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15304 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15305 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15306 -msym32 assume all symbols have 32-bit values\n\
15307 -O0 remove unneeded NOPs, do not swap branches\n\
15308 -O remove unneeded NOPs and swap branches\n\
15309 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15310 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15311 fprintf (stream
, _("\
15312 -mhard-float allow floating-point instructions\n\
15313 -msoft-float do not allow floating-point instructions\n\
15314 -msingle-float only allow 32-bit floating-point operations\n\
15315 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15316 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15319 fprintf (stream
, _("\
15320 -KPIC, -call_shared generate SVR4 position independent code\n\
15321 -mvxworks-pic generate VxWorks position independent code\n\
15322 -non_shared do not generate position independent code\n\
15323 -xgot assume a 32 bit GOT\n\
15324 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15325 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15326 position dependent (non shared) code\n\
15327 -mabi=ABI create ABI conformant object file for:\n"));
15331 show (stream
, "32", &column
, &first
);
15332 show (stream
, "o64", &column
, &first
);
15333 show (stream
, "n32", &column
, &first
);
15334 show (stream
, "64", &column
, &first
);
15335 show (stream
, "eabi", &column
, &first
);
15337 fputc ('\n', stream
);
15339 fprintf (stream
, _("\
15340 -32 create o32 ABI object file (default)\n\
15341 -n32 create n32 ABI object file\n\
15342 -64 create 64 ABI object file\n"));
15347 mips_dwarf2_format (void)
15349 if (HAVE_64BIT_SYMBOLS
)
15352 return dwarf2_format_64bit_irix
;
15354 return dwarf2_format_64bit
;
15358 return dwarf2_format_32bit
;
15362 mips_dwarf2_addr_size (void)
15364 if (HAVE_64BIT_SYMBOLS
)
15370 /* Standard calling conventions leave the CFA at SP on entry. */
15372 mips_cfi_frame_initial_instructions (void)
15374 cfi_add_CFA_def_cfa_register (SP
);
15378 tc_mips_regname_to_dw2regnum (char *regname
)
15380 unsigned int regnum
= -1;
15383 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))