1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_elf_flavour
:
122 return (target_big_endian
123 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
124 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
131 /* The name of the readonly data section. */
132 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
134 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
136 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
140 /* This is the set of options which may be modified by the .set
141 pseudo-op. We use a struct so that .set push and .set pop are more
144 struct mips_set_options
146 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
147 if it has not been initialized. Changed by `.set mipsN', and the
148 -mipsN command line option, and the default CPU. */
150 /* Whether we are assembling for the mips16 processor. 0 if we are
151 not, 1 if we are, and -1 if the value has not been initialized.
152 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
153 -nomips16 command line options, and the default CPU. */
155 /* Non-zero if we should not reorder instructions. Changed by `.set
156 reorder' and `.set noreorder'. */
158 /* Non-zero if we should not permit the $at ($1) register to be used
159 in instructions. Changed by `.set at' and `.set noat'. */
161 /* Non-zero if we should warn when a macro instruction expands into
162 more than one machine instruction. Changed by `.set nomacro' and
164 int warn_about_macros
;
165 /* Non-zero if we should not move instructions. Changed by `.set
166 move', `.set volatile', `.set nomove', and `.set novolatile'. */
168 /* Non-zero if we should not optimize branches by moving the target
169 of the branch into the delay slot. Actually, we don't perform
170 this optimization anyhow. Changed by `.set bopt' and `.set
173 /* Non-zero if we should not autoextend mips16 instructions.
174 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* This is the struct we use to hold the current set of options. Note
179 that we must set the isa and mips16 fields to -1 to indicate that
180 they have not been initialized. */
182 static struct mips_set_options mips_opts
= { -1, -1 };
184 /* These variables are filled in with the masks of registers used.
185 The object format code reads them and puts them in the appropriate
187 unsigned long mips_gprmask
;
188 unsigned long mips_cprmask
[4];
190 /* MIPS ISA we are using for this output file. */
191 static int file_mips_isa
;
193 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
194 static int mips_cpu
= -1;
196 /* The argument of the -mabi= flag. */
197 static char* mips_abi_string
= 0;
199 /* Wether we should mark the file EABI64 or EABI32. */
200 static int mips_eabi64
= 0;
202 /* If they asked for mips1 or mips2 and a cpu that is
203 mips3 or greater, then mark the object file 32BITMODE. */
204 static int mips_32bitmode
= 0;
206 /* Some ISA's have delay slots for instructions which read or write
207 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
208 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
209 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
210 delay slot in this ISA. The uses of this macro assume that any
211 ISA that has delay slots for one of these, has them for all. They
212 also assume that ISAs which don't have delays for these insns, don't
213 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
214 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
220 /* Return true if ISA supports 64 bit gp register instructions. */
221 #define ISA_HAS_64BIT_REGS(ISA) ( \
226 /* Whether the processor uses hardware interlocks to protect
227 reads from the HI and LO registers, and thus does not
228 require nops to be inserted.
230 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
231 -mcpu=FOO schedules for FOO, but still produces code that meets the
232 requirements of MIPS ISA I. For example, it won't generate any
233 FOO-specific instructions, and it will still assume that any
234 scheduling hazards described in MIPS ISA I are there, even if FOO
235 has interlocks. -mFOO gives GCC permission to generate code that
236 will only run on a FOO; it will generate FOO-specific instructions,
237 and assume interlocks provided by a FOO.
239 However, GAS currently doesn't make this distinction; before Jan 28
240 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
241 assumptions. The GCC driver passes these flags through to GAS, so
242 if GAS actually does anything that doesn't meet MIPS ISA I with
243 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
245 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
246 which seems senseless --- why generate code which will only run on
247 a FOO, but schedule for something else?
249 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
251 -- Jim Blandy <jimb@cygnus.com> */
253 #define hilo_interlocks (mips_cpu == 4010 \
256 /* Whether the processor uses hardware interlocks to protect reads
257 from the GPRs, and thus does not require nops to be inserted. */
258 #define gpr_interlocks \
259 (mips_opts.isa != 1 \
262 /* As with other "interlocks" this is used by hardware that has FP
263 (co-processor) interlocks. */
264 /* Itbl support may require additional care here. */
265 #define cop_interlocks (mips_cpu == 4300 \
268 /* Is this a mfhi or mflo instruction? */
269 #define MF_HILO_INSN(PINFO) \
270 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
272 /* MIPS PIC level. */
276 /* Do not generate PIC code. */
279 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
280 not sure what it is supposed to do. */
283 /* Generate PIC code as in the SVR4 MIPS ABI. */
286 /* Generate PIC code without using a global offset table: the data
287 segment has a maximum size of 64K, all data references are off
288 the $gp register, and all text references are PC relative. This
289 is used on some embedded systems. */
293 static enum mips_pic_level mips_pic
;
295 /* 1 if we should generate 32 bit offsets from the GP register in
296 SVR4_PIC mode. Currently has no meaning in other modes. */
297 static int mips_big_got
;
299 /* 1 if trap instructions should used for overflow rather than break
301 static int mips_trap
;
303 /* Non-zero if any .set noreorder directives were used. */
305 static int mips_any_noreorder
;
307 /* Non-zero if nops should be inserted when the register referenced in
308 an mfhi/mflo instruction is read in the next two instructions. */
309 static int mips_7000_hilo_fix
;
311 /* The size of the small data section. */
312 static int g_switch_value
= 8;
313 /* Whether the -G option was used. */
314 static int g_switch_seen
= 0;
319 /* If we can determine in advance that GP optimization won't be
320 possible, we can skip the relaxation stuff that tries to produce
321 GP-relative references. This makes delay slot optimization work
324 This function can only provide a guess, but it seems to work for
325 gcc output. It needs to guess right for gcc, otherwise gcc
326 will put what it thinks is a GP-relative instruction in a branch
329 I don't know if a fix is needed for the SVR4_PIC mode. I've only
330 fixed it for the non-PIC mode. KR 95/04/07 */
331 static int nopic_need_relax
PARAMS ((symbolS
*, int));
333 /* handle of the OPCODE hash table */
334 static struct hash_control
*op_hash
= NULL
;
336 /* The opcode hash table we use for the mips16. */
337 static struct hash_control
*mips16_op_hash
= NULL
;
339 /* This array holds the chars that always start a comment. If the
340 pre-processor is disabled, these aren't very useful */
341 const char comment_chars
[] = "#";
343 /* This array holds the chars that only start a comment at the beginning of
344 a line. If the line seems to have the form '# 123 filename'
345 .line and .file directives will appear in the pre-processed output */
346 /* Note that input_file.c hand checks for '#' at the beginning of the
347 first line of the input file. This is because the compiler outputs
348 #NO_APP at the beginning of its output. */
349 /* Also note that C style comments are always supported. */
350 const char line_comment_chars
[] = "#";
352 /* This array holds machine specific line separator characters. */
353 const char line_separator_chars
[] = "";
355 /* Chars that can be used to separate mant from exp in floating point nums */
356 const char EXP_CHARS
[] = "eE";
358 /* Chars that mean this number is a floating point constant */
361 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
363 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
364 changed in read.c . Ideally it shouldn't have to know about it at all,
365 but nothing is ideal around here.
368 static char *insn_error
;
370 static int auto_align
= 1;
372 /* When outputting SVR4 PIC code, the assembler needs to know the
373 offset in the stack frame from which to restore the $gp register.
374 This is set by the .cprestore pseudo-op, and saved in this
376 static offsetT mips_cprestore_offset
= -1;
378 /* This is the register which holds the stack frame, as set by the
379 .frame pseudo-op. This is needed to implement .cprestore. */
380 static int mips_frame_reg
= SP
;
382 /* To output NOP instructions correctly, we need to keep information
383 about the previous two instructions. */
385 /* Whether we are optimizing. The default value of 2 means to remove
386 unneeded NOPs and swap branch instructions when possible. A value
387 of 1 means to not swap branches. A value of 0 means to always
389 static int mips_optimize
= 2;
391 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
392 equivalent to seeing no -g option at all. */
393 static int mips_debug
= 0;
395 /* The previous instruction. */
396 static struct mips_cl_insn prev_insn
;
398 /* The instruction before prev_insn. */
399 static struct mips_cl_insn prev_prev_insn
;
401 /* If we don't want information for prev_insn or prev_prev_insn, we
402 point the insn_mo field at this dummy integer. */
403 static const struct mips_opcode dummy_opcode
= { 0 };
405 /* Non-zero if prev_insn is valid. */
406 static int prev_insn_valid
;
408 /* The frag for the previous instruction. */
409 static struct frag
*prev_insn_frag
;
411 /* The offset into prev_insn_frag for the previous instruction. */
412 static long prev_insn_where
;
414 /* The reloc type for the previous instruction, if any. */
415 static bfd_reloc_code_real_type prev_insn_reloc_type
;
417 /* The reloc for the previous instruction, if any. */
418 static fixS
*prev_insn_fixp
;
420 /* Non-zero if the previous instruction was in a delay slot. */
421 static int prev_insn_is_delay_slot
;
423 /* Non-zero if the previous instruction was in a .set noreorder. */
424 static int prev_insn_unreordered
;
426 /* Non-zero if the previous instruction uses an extend opcode (if
428 static int prev_insn_extended
;
430 /* Non-zero if the previous previous instruction was in a .set
432 static int prev_prev_insn_unreordered
;
434 /* If this is set, it points to a frag holding nop instructions which
435 were inserted before the start of a noreorder section. If those
436 nops turn out to be unnecessary, the size of the frag can be
438 static fragS
*prev_nop_frag
;
440 /* The number of nop instructions we created in prev_nop_frag. */
441 static int prev_nop_frag_holds
;
443 /* The number of nop instructions that we know we need in
445 static int prev_nop_frag_required
;
447 /* The number of instructions we've seen since prev_nop_frag. */
448 static int prev_nop_frag_since
;
450 /* For ECOFF and ELF, relocations against symbols are done in two
451 parts, with a HI relocation and a LO relocation. Each relocation
452 has only 16 bits of space to store an addend. This means that in
453 order for the linker to handle carries correctly, it must be able
454 to locate both the HI and the LO relocation. This means that the
455 relocations must appear in order in the relocation table.
457 In order to implement this, we keep track of each unmatched HI
458 relocation. We then sort them so that they immediately precede the
459 corresponding LO relocation. */
464 struct mips_hi_fixup
*next
;
467 /* The section this fixup is in. */
471 /* The list of unmatched HI relocs. */
473 static struct mips_hi_fixup
*mips_hi_fixup_list
;
475 /* Map normal MIPS register numbers to mips16 register numbers. */
477 #define X ILLEGAL_REG
478 static const int mips32_to_16_reg_map
[] =
480 X
, X
, 2, 3, 4, 5, 6, 7,
481 X
, X
, X
, X
, X
, X
, X
, X
,
482 0, 1, X
, X
, X
, X
, X
, X
,
483 X
, X
, X
, X
, X
, X
, X
, X
487 /* Map mips16 register numbers to normal MIPS register numbers. */
489 static const int mips16_to_32_reg_map
[] =
491 16, 17, 2, 3, 4, 5, 6, 7
494 /* Since the MIPS does not have multiple forms of PC relative
495 instructions, we do not have to do relaxing as is done on other
496 platforms. However, we do have to handle GP relative addressing
497 correctly, which turns out to be a similar problem.
499 Every macro that refers to a symbol can occur in (at least) two
500 forms, one with GP relative addressing and one without. For
501 example, loading a global variable into a register generally uses
502 a macro instruction like this:
504 If i can be addressed off the GP register (this is true if it is in
505 the .sbss or .sdata section, or if it is known to be smaller than
506 the -G argument) this will generate the following instruction:
508 This instruction will use a GPREL reloc. If i can not be addressed
509 off the GP register, the following instruction sequence will be used:
512 In this case the first instruction will have a HI16 reloc, and the
513 second reloc will have a LO16 reloc. Both relocs will be against
516 The issue here is that we may not know whether i is GP addressable
517 until after we see the instruction that uses it. Therefore, we
518 want to be able to choose the final instruction sequence only at
519 the end of the assembly. This is similar to the way other
520 platforms choose the size of a PC relative instruction only at the
523 When generating position independent code we do not use GP
524 addressing in quite the same way, but the issue still arises as
525 external symbols and local symbols must be handled differently.
527 We handle these issues by actually generating both possible
528 instruction sequences. The longer one is put in a frag_var with
529 type rs_machine_dependent. We encode what to do with the frag in
530 the subtype field. We encode (1) the number of existing bytes to
531 replace, (2) the number of new bytes to use, (3) the offset from
532 the start of the existing bytes to the first reloc we must generate
533 (that is, the offset is applied from the start of the existing
534 bytes after they are replaced by the new bytes, if any), (4) the
535 offset from the start of the existing bytes to the second reloc,
536 (5) whether a third reloc is needed (the third reloc is always four
537 bytes after the second reloc), and (6) whether to warn if this
538 variant is used (this is sometimes needed if .set nomacro or .set
539 noat is in effect). All these numbers are reasonably small.
541 Generating two instruction sequences must be handled carefully to
542 ensure that delay slots are handled correctly. Fortunately, there
543 are a limited number of cases. When the second instruction
544 sequence is generated, append_insn is directed to maintain the
545 existing delay slot information, so it continues to apply to any
546 code after the second instruction sequence. This means that the
547 second instruction sequence must not impose any requirements not
548 required by the first instruction sequence.
550 These variant frags are then handled in functions called by the
551 machine independent code. md_estimate_size_before_relax returns
552 the final size of the frag. md_convert_frag sets up the final form
553 of the frag. tc_gen_reloc adjust the first reloc and adds a second
555 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
559 | (((reloc1) + 64) << 9) \
560 | (((reloc2) + 64) << 2) \
561 | ((reloc3) ? (1 << 1) : 0) \
563 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
564 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
565 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
566 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
567 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
568 #define RELAX_WARN(i) ((i) & 1)
570 /* For mips16 code, we use an entirely different form of relaxation.
571 mips16 supports two versions of most instructions which take
572 immediate values: a small one which takes some small value, and a
573 larger one which takes a 16 bit value. Since branches also follow
574 this pattern, relaxing these values is required.
576 We can assemble both mips16 and normal MIPS code in a single
577 object. Therefore, we need to support this type of relaxation at
578 the same time that we support the relaxation described above. We
579 use the high bit of the subtype field to distinguish these cases.
581 The information we store for this type of relaxation is the
582 argument code found in the opcode file for this relocation, whether
583 the user explicitly requested a small or extended form, and whether
584 the relocation is in a jump or jal delay slot. That tells us the
585 size of the value, and how it should be stored. We also store
586 whether the fragment is considered to be extended or not. We also
587 store whether this is known to be a branch to a different section,
588 whether we have tried to relax this frag yet, and whether we have
589 ever extended a PC relative fragment because of a shift count. */
590 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
593 | ((small) ? 0x100 : 0) \
594 | ((ext) ? 0x200 : 0) \
595 | ((dslot) ? 0x400 : 0) \
596 | ((jal_dslot) ? 0x800 : 0))
597 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
598 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
599 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
600 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
601 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
602 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
603 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
604 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
605 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
606 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
607 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
608 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
610 /* Prototypes for static functions. */
613 #define internalError() \
614 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
616 #define internalError() as_fatal (_("MIPS internal Error"));
619 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
621 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
622 unsigned int reg
, enum mips_regclass
class));
623 static int reg_needs_delay
PARAMS ((int));
624 static void mips16_mark_labels
PARAMS ((void));
625 static void append_insn
PARAMS ((char *place
,
626 struct mips_cl_insn
* ip
,
628 bfd_reloc_code_real_type r
,
630 static void mips_no_prev_insn
PARAMS ((int));
631 static void mips_emit_delays
PARAMS ((boolean
));
633 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
634 const char *name
, const char *fmt
,
637 static void macro_build ();
639 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
640 const char *, const char *,
642 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
643 expressionS
* ep
, int regnum
));
644 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
645 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
647 static void load_register
PARAMS ((int *, int, expressionS
*, int));
648 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
649 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
650 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
651 #ifdef LOSING_COMPILER
652 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
654 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
655 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
656 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
657 boolean
, boolean
, unsigned long *,
658 boolean
*, unsigned short *));
659 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
660 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
661 static symbolS
*get_symbol
PARAMS ((void));
662 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
663 static void s_align
PARAMS ((int));
664 static void s_change_sec
PARAMS ((int));
665 static void s_cons
PARAMS ((int));
666 static void s_float_cons
PARAMS ((int));
667 static void s_mips_globl
PARAMS ((int));
668 static void s_option
PARAMS ((int));
669 static void s_mipsset
PARAMS ((int));
670 static void s_abicalls
PARAMS ((int));
671 static void s_cpload
PARAMS ((int));
672 static void s_cprestore
PARAMS ((int));
673 static void s_gpword
PARAMS ((int));
674 static void s_cpadd
PARAMS ((int));
675 static void s_insn
PARAMS ((int));
676 static void md_obj_begin
PARAMS ((void));
677 static void md_obj_end
PARAMS ((void));
678 static long get_number
PARAMS ((void));
679 static void s_mips_ent
PARAMS ((int));
680 static void s_mips_end
PARAMS ((int));
681 static void s_mips_frame
PARAMS ((int));
682 static void s_mips_mask
PARAMS ((int));
683 static void s_mips_stab
PARAMS ((int));
684 static void s_mips_weakext
PARAMS ((int));
685 static void s_file
PARAMS ((int));
686 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
689 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
693 The following pseudo-ops from the Kane and Heinrich MIPS book
694 should be defined here, but are currently unsupported: .alias,
695 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
697 The following pseudo-ops from the Kane and Heinrich MIPS book are
698 specific to the type of debugging information being generated, and
699 should be defined by the object format: .aent, .begin, .bend,
700 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
703 The following pseudo-ops from the Kane and Heinrich MIPS book are
704 not MIPS CPU specific, but are also not specific to the object file
705 format. This file is probably the best place to define them, but
706 they are not currently supported: .asm0, .endr, .lab, .repeat,
709 static const pseudo_typeS mips_pseudo_table
[] =
711 /* MIPS specific pseudo-ops. */
712 {"option", s_option
, 0},
713 {"set", s_mipsset
, 0},
714 {"rdata", s_change_sec
, 'r'},
715 {"sdata", s_change_sec
, 's'},
716 {"livereg", s_ignore
, 0},
717 {"abicalls", s_abicalls
, 0},
718 {"cpload", s_cpload
, 0},
719 {"cprestore", s_cprestore
, 0},
720 {"gpword", s_gpword
, 0},
721 {"cpadd", s_cpadd
, 0},
724 /* Relatively generic pseudo-ops that happen to be used on MIPS
726 {"asciiz", stringer
, 1},
727 {"bss", s_change_sec
, 'b'},
730 {"dword", s_cons
, 3},
731 {"weakext", s_mips_weakext
, 0},
733 /* These pseudo-ops are defined in read.c, but must be overridden
734 here for one reason or another. */
735 {"align", s_align
, 0},
737 {"data", s_change_sec
, 'd'},
738 {"double", s_float_cons
, 'd'},
739 {"float", s_float_cons
, 'f'},
740 {"globl", s_mips_globl
, 0},
741 {"global", s_mips_globl
, 0},
742 {"hword", s_cons
, 1},
747 {"short", s_cons
, 1},
748 {"single", s_float_cons
, 'f'},
749 {"stabn", s_mips_stab
, 'n'},
750 {"text", s_change_sec
, 't'},
755 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
756 /* These pseudo-ops should be defined by the object file format.
757 However, a.out doesn't support them, so we have versions here. */
758 {"aent", s_mips_ent
, 1},
759 {"bgnb", s_ignore
, 0},
760 {"end", s_mips_end
, 0},
761 {"endb", s_ignore
, 0},
762 {"ent", s_mips_ent
, 0},
764 {"fmask", s_mips_mask
, 'F'},
765 {"frame", s_mips_frame
, 0},
766 {"loc", s_ignore
, 0},
767 {"mask", s_mips_mask
, 'R'},
768 {"verstamp", s_ignore
, 0},
772 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
777 pop_insert (mips_pseudo_table
);
778 if (! ECOFF_DEBUGGING
)
779 pop_insert (mips_nonecoff_pseudo_table
);
782 /* Symbols labelling the current insn. */
784 struct insn_label_list
786 struct insn_label_list
*next
;
790 static struct insn_label_list
*insn_labels
;
791 static struct insn_label_list
*free_insn_labels
;
793 static void mips_clear_insn_labels
PARAMS ((void));
796 mips_clear_insn_labels ()
798 register struct insn_label_list
**pl
;
800 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
806 static char *expr_end
;
808 /* Expressions which appear in instructions. These are set by
811 static expressionS imm_expr
;
812 static expressionS offset_expr
;
814 /* Relocs associated with imm_expr and offset_expr. */
816 static bfd_reloc_code_real_type imm_reloc
;
817 static bfd_reloc_code_real_type offset_reloc
;
819 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
821 static boolean imm_unmatched_hi
;
823 /* These are set by mips16_ip if an explicit extension is used. */
825 static boolean mips16_small
, mips16_ext
;
827 #ifdef MIPS_STABS_ELF
828 /* The pdr segment for per procedure frame/regmask info */
834 * This function is called once, at assembler startup time. It should
835 * set up all the tables, etc. that the MD part of the assembler will need.
841 register const char *retval
= NULL
;
842 register unsigned int i
= 0;
846 int mips_isa_from_cpu
;
849 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
851 a
= xmalloc (sizeof TARGET_CPU
);
852 strcpy (a
, TARGET_CPU
);
853 a
[(sizeof TARGET_CPU
) - 3] = '\0';
859 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
860 just the generic 'mips', in which case set mips_cpu based
861 on the given ISA, if any. */
863 if (strcmp (cpu
, "mips") == 0)
865 if (mips_opts
.isa
< 0)
868 else if (mips_opts
.isa
== 2)
871 else if (mips_opts
.isa
== 3)
874 else if (mips_opts
.isa
== 4)
881 else if (strcmp (cpu
, "r3900") == 0
882 || strcmp (cpu
, "mipstx39") == 0
886 else if (strcmp (cpu
, "r6000") == 0
887 || strcmp (cpu
, "mips2") == 0)
890 else if (strcmp (cpu
, "mips64") == 0
891 || strcmp (cpu
, "r4000") == 0
892 || strcmp (cpu
, "mips3") == 0)
895 else if (strcmp (cpu
, "r4400") == 0)
898 else if (strcmp (cpu
, "mips64orion") == 0
899 || strcmp (cpu
, "r4600") == 0)
902 else if (strcmp (cpu
, "r4650") == 0)
905 else if (strcmp (cpu
, "mips64vr4300") == 0)
908 else if (strcmp (cpu
, "mips64vr4111") == 0)
911 else if (strcmp (cpu
, "mips64vr4100") == 0)
914 else if (strcmp (cpu
, "r4010") == 0)
918 else if (strcmp (cpu
, "r5000") == 0
919 || strcmp (cpu
, "mips64vr5000") == 0)
924 else if (strcmp (cpu
, "r8000") == 0
925 || strcmp (cpu
, "mips4") == 0)
928 else if (strcmp (cpu
, "r10000") == 0)
931 else if (strcmp (cpu
, "mips16") == 0)
932 mips_cpu
= 0; /* FIXME */
940 mips_isa_from_cpu
= 1;
942 else if (mips_cpu
== 6000
944 mips_isa_from_cpu
= 2;
946 else if (mips_cpu
== 4000
953 mips_isa_from_cpu
= 3;
955 else if (mips_cpu
== 5000
957 || mips_cpu
== 10000)
958 mips_isa_from_cpu
= 4;
961 mips_isa_from_cpu
= -1;
963 if (mips_opts
.isa
== -1)
965 if (mips_isa_from_cpu
!= -1)
966 mips_opts
.isa
= mips_isa_from_cpu
;
971 if (mips_opts
.mips16
< 0)
973 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
974 mips_opts
.mips16
= 1;
976 mips_opts
.mips16
= 0;
979 /* End of TARGET_CPU processing, get rid of malloced memory
988 if (mips_opts
.isa
== 1 && mips_trap
)
989 as_bad (_("trap exception not supported at ISA 1"));
991 /* Set the EABI kind based on the ISA before the user gets
992 to change the ISA with directives. This isn't really
993 the best, but then neither is basing the abi on the isa. */
994 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
996 && 0 == strcmp (mips_abi_string
,"eabi"))
999 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1001 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1003 /* If they asked for mips1 or mips2 and a cpu that is
1004 mips3 or greater, then mark the object file 32BITMODE. */
1005 if (mips_isa_from_cpu
!= -1
1006 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1007 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1012 switch (mips_opts
.isa
)
1015 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1018 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1021 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1024 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1030 as_warn (_("Could not set architecture and machine"));
1032 file_mips_isa
= mips_opts
.isa
;
1034 op_hash
= hash_new ();
1036 for (i
= 0; i
< NUMOPCODES
;)
1038 const char *name
= mips_opcodes
[i
].name
;
1040 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1043 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1044 mips_opcodes
[i
].name
, retval
);
1045 /* Probably a memory allocation problem? Give up now. */
1046 as_fatal (_("Broken assembler. No assembly attempted."));
1050 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1052 if (!validate_mips_insn (&mips_opcodes
[i
]))
1057 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1060 mips16_op_hash
= hash_new ();
1063 while (i
< bfd_mips16_num_opcodes
)
1065 const char *name
= mips16_opcodes
[i
].name
;
1067 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1069 as_fatal (_("internal: can't hash `%s': %s"),
1070 mips16_opcodes
[i
].name
, retval
);
1073 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1074 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1075 != mips16_opcodes
[i
].match
))
1077 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1078 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1083 while (i
< bfd_mips16_num_opcodes
1084 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1088 as_fatal (_("Broken assembler. No assembly attempted."));
1090 /* We add all the general register names to the symbol table. This
1091 helps us detect invalid uses of them. */
1092 for (i
= 0; i
< 32; i
++)
1096 sprintf (buf
, "$%d", i
);
1097 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1098 &zero_address_frag
));
1100 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1101 &zero_address_frag
));
1102 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1103 &zero_address_frag
));
1104 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1105 &zero_address_frag
));
1106 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1107 &zero_address_frag
));
1108 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1109 &zero_address_frag
));
1110 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1111 &zero_address_frag
));
1112 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1113 &zero_address_frag
));
1115 mips_no_prev_insn (false);
1118 mips_cprmask
[0] = 0;
1119 mips_cprmask
[1] = 0;
1120 mips_cprmask
[2] = 0;
1121 mips_cprmask
[3] = 0;
1123 /* set the default alignment for the text section (2**2) */
1124 record_alignment (text_section
, 2);
1126 if (USE_GLOBAL_POINTER_OPT
)
1127 bfd_set_gp_size (stdoutput
, g_switch_value
);
1129 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1131 /* On a native system, sections must be aligned to 16 byte
1132 boundaries. When configured for an embedded ELF target, we
1134 if (strcmp (TARGET_OS
, "elf") != 0)
1136 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1137 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1138 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1141 /* Create a .reginfo section for register masks and a .mdebug
1142 section for debugging information. */
1150 subseg
= now_subseg
;
1152 /* The ABI says this section should be loaded so that the
1153 running program can access it. However, we don't load it
1154 if we are configured for an embedded target */
1155 flags
= SEC_READONLY
| SEC_DATA
;
1156 if (strcmp (TARGET_OS
, "elf") != 0)
1157 flags
|= SEC_ALLOC
| SEC_LOAD
;
1161 sec
= subseg_new (".reginfo", (subsegT
) 0);
1164 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1165 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1168 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1173 /* The 64-bit ABI uses a .MIPS.options section rather than
1174 .reginfo section. */
1175 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1176 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1177 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1180 /* Set up the option header. */
1182 Elf_Internal_Options opthdr
;
1185 opthdr
.kind
= ODK_REGINFO
;
1186 opthdr
.size
= (sizeof (Elf_External_Options
)
1187 + sizeof (Elf64_External_RegInfo
));
1190 f
= frag_more (sizeof (Elf_External_Options
));
1191 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1192 (Elf_External_Options
*) f
);
1194 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1199 if (ECOFF_DEBUGGING
)
1201 sec
= subseg_new (".mdebug", (subsegT
) 0);
1202 (void) bfd_set_section_flags (stdoutput
, sec
,
1203 SEC_HAS_CONTENTS
| SEC_READONLY
);
1204 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1207 #ifdef MIPS_STABS_ELF
1208 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1209 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1210 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1211 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1214 subseg_set (seg
, subseg
);
1218 if (! ECOFF_DEBUGGING
)
1225 if (! ECOFF_DEBUGGING
)
1233 struct mips_cl_insn insn
;
1235 imm_expr
.X_op
= O_absent
;
1236 imm_reloc
= BFD_RELOC_UNUSED
;
1237 imm_unmatched_hi
= false;
1238 offset_expr
.X_op
= O_absent
;
1239 offset_reloc
= BFD_RELOC_UNUSED
;
1241 if (mips_opts
.mips16
)
1242 mips16_ip (str
, &insn
);
1245 mips_ip (str
, &insn
);
1246 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1247 str
, insn
.insn_opcode
));
1252 as_bad ("%s `%s'", insn_error
, str
);
1256 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1258 if (mips_opts
.mips16
)
1259 mips16_macro (&insn
);
1265 if (imm_expr
.X_op
!= O_absent
)
1266 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1268 else if (offset_expr
.X_op
!= O_absent
)
1269 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1271 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1275 /* See whether instruction IP reads register REG. CLASS is the type
1279 insn_uses_reg (ip
, reg
, class)
1280 struct mips_cl_insn
*ip
;
1282 enum mips_regclass
class;
1284 if (class == MIPS16_REG
)
1286 assert (mips_opts
.mips16
);
1287 reg
= mips16_to_32_reg_map
[reg
];
1288 class = MIPS_GR_REG
;
1291 /* Don't report on general register 0, since it never changes. */
1292 if (class == MIPS_GR_REG
&& reg
== 0)
1295 if (class == MIPS_FP_REG
)
1297 assert (! mips_opts
.mips16
);
1298 /* If we are called with either $f0 or $f1, we must check $f0.
1299 This is not optimal, because it will introduce an unnecessary
1300 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1301 need to distinguish reading both $f0 and $f1 or just one of
1302 them. Note that we don't have to check the other way,
1303 because there is no instruction that sets both $f0 and $f1
1304 and requires a delay. */
1305 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1306 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1307 == (reg
&~ (unsigned) 1)))
1309 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1310 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1311 == (reg
&~ (unsigned) 1)))
1314 else if (! mips_opts
.mips16
)
1316 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1317 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1319 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1320 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1325 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1326 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1327 & MIPS16OP_MASK_RX
)]
1330 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1331 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1332 & MIPS16OP_MASK_RY
)]
1335 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1336 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1337 & MIPS16OP_MASK_MOVE32Z
)]
1340 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1342 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1344 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1346 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1347 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1348 & MIPS16OP_MASK_REGR32
) == reg
)
1355 /* This function returns true if modifying a register requires a
1359 reg_needs_delay (reg
)
1362 unsigned long prev_pinfo
;
1364 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1365 if (! mips_opts
.noreorder
1366 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1367 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1368 || (! gpr_interlocks
1369 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1371 /* A load from a coprocessor or from memory. All load
1372 delays delay the use of general register rt for one
1373 instruction on the r3000. The r6000 and r4000 use
1375 /* Itbl support may require additional care here. */
1376 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1377 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1384 /* Mark instruction labels in mips16 mode. This permits the linker to
1385 handle them specially, such as generating jalx instructions when
1386 needed. We also make them odd for the duration of the assembly, in
1387 order to generate the right sort of code. We will make them even
1388 in the adjust_symtab routine, while leaving them marked. This is
1389 convenient for the debugger and the disassembler. The linker knows
1390 to make them odd again. */
1393 mips16_mark_labels ()
1395 if (mips_opts
.mips16
)
1397 struct insn_label_list
*l
;
1399 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1402 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1403 S_SET_OTHER (l
->label
, STO_MIPS16
);
1405 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1406 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1411 /* Output an instruction. PLACE is where to put the instruction; if
1412 it is NULL, this uses frag_more to get room. IP is the instruction
1413 information. ADDRESS_EXPR is an operand of the instruction to be
1414 used with RELOC_TYPE. */
1417 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1419 struct mips_cl_insn
*ip
;
1420 expressionS
*address_expr
;
1421 bfd_reloc_code_real_type reloc_type
;
1422 boolean unmatched_hi
;
1424 register unsigned long prev_pinfo
, pinfo
;
1429 /* Mark instruction labels in mips16 mode. */
1430 if (mips_opts
.mips16
)
1431 mips16_mark_labels ();
1433 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1434 pinfo
= ip
->insn_mo
->pinfo
;
1436 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1440 /* If the previous insn required any delay slots, see if we need
1441 to insert a NOP or two. There are eight kinds of possible
1442 hazards, of which an instruction can have at most one type.
1443 (1) a load from memory delay
1444 (2) a load from a coprocessor delay
1445 (3) an unconditional branch delay
1446 (4) a conditional branch delay
1447 (5) a move to coprocessor register delay
1448 (6) a load coprocessor register from memory delay
1449 (7) a coprocessor condition code delay
1450 (8) a HI/LO special register delay
1452 There are a lot of optimizations we could do that we don't.
1453 In particular, we do not, in general, reorder instructions.
1454 If you use gcc with optimization, it will reorder
1455 instructions and generally do much more optimization then we
1456 do here; repeating all that work in the assembler would only
1457 benefit hand written assembly code, and does not seem worth
1460 /* This is how a NOP is emitted. */
1461 #define emit_nop() \
1463 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1464 : md_number_to_chars (frag_more (4), 0, 4))
1466 /* The previous insn might require a delay slot, depending upon
1467 the contents of the current insn. */
1468 if (! mips_opts
.mips16
1469 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1470 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1471 && ! cop_interlocks
)
1472 || (! gpr_interlocks
1473 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1475 /* A load from a coprocessor or from memory. All load
1476 delays delay the use of general register rt for one
1477 instruction on the r3000. The r6000 and r4000 use
1479 /* Itbl support may require additional care here. */
1480 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1481 if (mips_optimize
== 0
1482 || insn_uses_reg (ip
,
1483 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1488 else if (! mips_opts
.mips16
1489 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1490 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1491 && ! cop_interlocks
)
1492 || (mips_opts
.isa
== 1
1493 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1495 /* A generic coprocessor delay. The previous instruction
1496 modified a coprocessor general or control register. If
1497 it modified a control register, we need to avoid any
1498 coprocessor instruction (this is probably not always
1499 required, but it sometimes is). If it modified a general
1500 register, we avoid using that register.
1502 On the r6000 and r4000 loading a coprocessor register
1503 from memory is interlocked, and does not require a delay.
1505 This case is not handled very well. There is no special
1506 knowledge of CP0 handling, and the coprocessors other
1507 than the floating point unit are not distinguished at
1509 /* Itbl support may require additional care here. FIXME!
1510 Need to modify this to include knowledge about
1511 user specified delays! */
1512 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1514 if (mips_optimize
== 0
1515 || insn_uses_reg (ip
,
1516 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1521 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1523 if (mips_optimize
== 0
1524 || insn_uses_reg (ip
,
1525 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1532 /* We don't know exactly what the previous instruction
1533 does. If the current instruction uses a coprocessor
1534 register, we must insert a NOP. If previous
1535 instruction may set the condition codes, and the
1536 current instruction uses them, we must insert two
1538 /* Itbl support may require additional care here. */
1539 if (mips_optimize
== 0
1540 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1541 && (pinfo
& INSN_READ_COND_CODE
)))
1543 else if (pinfo
& INSN_COP
)
1547 else if (! mips_opts
.mips16
1548 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1549 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1550 && ! cop_interlocks
)
1552 /* The previous instruction sets the coprocessor condition
1553 codes, but does not require a general coprocessor delay
1554 (this means it is a floating point comparison
1555 instruction). If this instruction uses the condition
1556 codes, we need to insert a single NOP. */
1557 /* Itbl support may require additional care here. */
1558 if (mips_optimize
== 0
1559 || (pinfo
& INSN_READ_COND_CODE
))
1563 /* If we're fixing up mfhi/mflo for the r7000 and the
1564 previous insn was an mfhi/mflo and the current insn
1565 reads the register that the mfhi/mflo wrote to, then
1568 else if (mips_7000_hilo_fix
1569 && MF_HILO_INSN (prev_pinfo
)
1570 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1578 /* If we're fixing up mfhi/mflo for the r7000 and the
1579 2nd previous insn was an mfhi/mflo and the current insn
1580 reads the register that the mfhi/mflo wrote to, then
1583 else if (mips_7000_hilo_fix
1584 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1585 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1593 else if (prev_pinfo
& INSN_READ_LO
)
1595 /* The previous instruction reads the LO register; if the
1596 current instruction writes to the LO register, we must
1597 insert two NOPS. Some newer processors have interlocks.
1598 Also the tx39's multiply instructions can be exectuted
1599 immediatly after a read from HI/LO (without the delay),
1600 though the tx39's divide insns still do require the
1602 if (! (hilo_interlocks
1603 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1604 && (mips_optimize
== 0
1605 || (pinfo
& INSN_WRITE_LO
)))
1607 /* Most mips16 branch insns don't have a delay slot.
1608 If a read from LO is immediately followed by a branch
1609 to a write to LO we have a read followed by a write
1610 less than 2 insns away. We assume the target of
1611 a branch might be a write to LO, and insert a nop
1612 between a read and an immediately following branch. */
1613 else if (mips_opts
.mips16
1614 && (mips_optimize
== 0
1615 || (pinfo
& MIPS16_INSN_BRANCH
)))
1618 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1620 /* The previous instruction reads the HI register; if the
1621 current instruction writes to the HI register, we must
1622 insert a NOP. Some newer processors have interlocks.
1623 Also the note tx39's multiply above. */
1624 if (! (hilo_interlocks
1625 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1626 && (mips_optimize
== 0
1627 || (pinfo
& INSN_WRITE_HI
)))
1629 /* Most mips16 branch insns don't have a delay slot.
1630 If a read from HI is immediately followed by a branch
1631 to a write to HI we have a read followed by a write
1632 less than 2 insns away. We assume the target of
1633 a branch might be a write to HI, and insert a nop
1634 between a read and an immediately following branch. */
1635 else if (mips_opts
.mips16
1636 && (mips_optimize
== 0
1637 || (pinfo
& MIPS16_INSN_BRANCH
)))
1641 /* If the previous instruction was in a noreorder section, then
1642 we don't want to insert the nop after all. */
1643 /* Itbl support may require additional care here. */
1644 if (prev_insn_unreordered
)
1647 /* There are two cases which require two intervening
1648 instructions: 1) setting the condition codes using a move to
1649 coprocessor instruction which requires a general coprocessor
1650 delay and then reading the condition codes 2) reading the HI
1651 or LO register and then writing to it (except on processors
1652 which have interlocks). If we are not already emitting a NOP
1653 instruction, we must check for these cases compared to the
1654 instruction previous to the previous instruction. */
1655 if ((! mips_opts
.mips16
1656 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1657 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1658 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1659 && (pinfo
& INSN_READ_COND_CODE
)
1660 && ! cop_interlocks
)
1661 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1662 && (pinfo
& INSN_WRITE_LO
)
1663 && ! (hilo_interlocks
1664 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1665 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1666 && (pinfo
& INSN_WRITE_HI
)
1667 && ! (hilo_interlocks
1668 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1673 if (prev_prev_insn_unreordered
)
1676 if (prev_prev_nop
&& nops
== 0)
1679 /* If we are being given a nop instruction, don't bother with
1680 one of the nops we would otherwise output. This will only
1681 happen when a nop instruction is used with mips_optimize set
1684 && ! mips_opts
.noreorder
1685 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1688 /* Now emit the right number of NOP instructions. */
1689 if (nops
> 0 && ! mips_opts
.noreorder
)
1692 unsigned long old_frag_offset
;
1694 struct insn_label_list
*l
;
1696 old_frag
= frag_now
;
1697 old_frag_offset
= frag_now_fix ();
1699 for (i
= 0; i
< nops
; i
++)
1704 listing_prev_line ();
1705 /* We may be at the start of a variant frag. In case we
1706 are, make sure there is enough space for the frag
1707 after the frags created by listing_prev_line. The
1708 argument to frag_grow here must be at least as large
1709 as the argument to all other calls to frag_grow in
1710 this file. We don't have to worry about being in the
1711 middle of a variant frag, because the variants insert
1712 all needed nop instructions themselves. */
1716 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1718 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1719 symbol_set_frag (l
->label
, frag_now
);
1720 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1721 /* mips16 text labels are stored as odd. */
1722 if (mips_opts
.mips16
)
1723 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1726 #ifndef NO_ECOFF_DEBUGGING
1727 if (ECOFF_DEBUGGING
)
1728 ecoff_fix_loc (old_frag
, old_frag_offset
);
1731 else if (prev_nop_frag
!= NULL
)
1733 /* We have a frag holding nops we may be able to remove. If
1734 we don't need any nops, we can decrease the size of
1735 prev_nop_frag by the size of one instruction. If we do
1736 need some nops, we count them in prev_nops_required. */
1737 if (prev_nop_frag_since
== 0)
1741 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1742 --prev_nop_frag_holds
;
1745 prev_nop_frag_required
+= nops
;
1749 if (prev_prev_nop
== 0)
1751 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1752 --prev_nop_frag_holds
;
1755 ++prev_nop_frag_required
;
1758 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1759 prev_nop_frag
= NULL
;
1761 ++prev_nop_frag_since
;
1763 /* Sanity check: by the time we reach the second instruction
1764 after prev_nop_frag, we should have used up all the nops
1765 one way or another. */
1766 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1770 if (reloc_type
> BFD_RELOC_UNUSED
)
1772 /* We need to set up a variant frag. */
1773 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1774 f
= frag_var (rs_machine_dependent
, 4, 0,
1775 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1776 mips16_small
, mips16_ext
,
1778 & INSN_UNCOND_BRANCH_DELAY
),
1779 (prev_insn_reloc_type
1780 == BFD_RELOC_MIPS16_JMP
)),
1781 make_expr_symbol (address_expr
), (offsetT
) 0,
1784 else if (place
!= NULL
)
1786 else if (mips_opts
.mips16
1788 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1790 /* Make sure there is enough room to swap this instruction with
1791 a following jump instruction. */
1797 if (mips_opts
.mips16
1798 && mips_opts
.noreorder
1799 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1800 as_warn (_("extended instruction in delay slot"));
1806 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1808 if (address_expr
->X_op
== O_constant
)
1813 ip
->insn_opcode
|= address_expr
->X_add_number
;
1816 case BFD_RELOC_LO16
:
1817 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1820 case BFD_RELOC_MIPS_JMP
:
1821 if ((address_expr
->X_add_number
& 3) != 0)
1822 as_bad (_("jump to misaligned address (0x%lx)"),
1823 (unsigned long) address_expr
->X_add_number
);
1824 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1827 case BFD_RELOC_MIPS16_JMP
:
1828 if ((address_expr
->X_add_number
& 3) != 0)
1829 as_bad (_("jump to misaligned address (0x%lx)"),
1830 (unsigned long) address_expr
->X_add_number
);
1832 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1833 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1834 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1838 case BFD_RELOC_16_PCREL_S2
:
1848 /* Don't generate a reloc if we are writing into a variant
1852 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1854 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1858 struct mips_hi_fixup
*hi_fixup
;
1860 assert (reloc_type
== BFD_RELOC_HI16_S
);
1861 hi_fixup
= ((struct mips_hi_fixup
*)
1862 xmalloc (sizeof (struct mips_hi_fixup
)));
1863 hi_fixup
->fixp
= fixp
;
1864 hi_fixup
->seg
= now_seg
;
1865 hi_fixup
->next
= mips_hi_fixup_list
;
1866 mips_hi_fixup_list
= hi_fixup
;
1872 if (! mips_opts
.mips16
)
1873 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1874 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1876 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1877 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1883 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1886 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1889 /* Update the register mask information. */
1890 if (! mips_opts
.mips16
)
1892 if (pinfo
& INSN_WRITE_GPR_D
)
1893 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1894 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1895 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1896 if (pinfo
& INSN_READ_GPR_S
)
1897 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1898 if (pinfo
& INSN_WRITE_GPR_31
)
1899 mips_gprmask
|= 1 << 31;
1900 if (pinfo
& INSN_WRITE_FPR_D
)
1901 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1902 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1903 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1904 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1905 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1906 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1907 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1908 if (pinfo
& INSN_COP
)
1910 /* We don't keep enough information to sort these cases out.
1911 The itbl support does keep this information however, although
1912 we currently don't support itbl fprmats as part of the cop
1913 instruction. May want to add this support in the future. */
1915 /* Never set the bit for $0, which is always zero. */
1916 mips_gprmask
&=~ 1 << 0;
1920 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1921 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1922 & MIPS16OP_MASK_RX
);
1923 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1924 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1925 & MIPS16OP_MASK_RY
);
1926 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1928 & MIPS16OP_MASK_RZ
);
1929 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1930 mips_gprmask
|= 1 << TREG
;
1931 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1932 mips_gprmask
|= 1 << SP
;
1933 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1934 mips_gprmask
|= 1 << RA
;
1935 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1936 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1937 if (pinfo
& MIPS16_INSN_READ_Z
)
1938 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1939 & MIPS16OP_MASK_MOVE32Z
);
1940 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1941 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1942 & MIPS16OP_MASK_REGR32
);
1945 if (place
== NULL
&& ! mips_opts
.noreorder
)
1947 /* Filling the branch delay slot is more complex. We try to
1948 switch the branch with the previous instruction, which we can
1949 do if the previous instruction does not set up a condition
1950 that the branch tests and if the branch is not itself the
1951 target of any branch. */
1952 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1953 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1955 if (mips_optimize
< 2
1956 /* If we have seen .set volatile or .set nomove, don't
1958 || mips_opts
.nomove
!= 0
1959 /* If we had to emit any NOP instructions, then we
1960 already know we can not swap. */
1962 /* If we don't even know the previous insn, we can not
1964 || ! prev_insn_valid
1965 /* If the previous insn is already in a branch delay
1966 slot, then we can not swap. */
1967 || prev_insn_is_delay_slot
1968 /* If the previous previous insn was in a .set
1969 noreorder, we can't swap. Actually, the MIPS
1970 assembler will swap in this situation. However, gcc
1971 configured -with-gnu-as will generate code like
1977 in which we can not swap the bne and INSN. If gcc is
1978 not configured -with-gnu-as, it does not output the
1979 .set pseudo-ops. We don't have to check
1980 prev_insn_unreordered, because prev_insn_valid will
1981 be 0 in that case. We don't want to use
1982 prev_prev_insn_valid, because we do want to be able
1983 to swap at the start of a function. */
1984 || prev_prev_insn_unreordered
1985 /* If the branch is itself the target of a branch, we
1986 can not swap. We cheat on this; all we check for is
1987 whether there is a label on this instruction. If
1988 there are any branches to anything other than a
1989 label, users must use .set noreorder. */
1990 || insn_labels
!= NULL
1991 /* If the previous instruction is in a variant frag, we
1992 can not do the swap. This does not apply to the
1993 mips16, which uses variant frags for different
1995 || (! mips_opts
.mips16
1996 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1997 /* If the branch reads the condition codes, we don't
1998 even try to swap, because in the sequence
2003 we can not swap, and I don't feel like handling that
2005 || (! mips_opts
.mips16
2006 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2007 && (pinfo
& INSN_READ_COND_CODE
))
2008 /* We can not swap with an instruction that requires a
2009 delay slot, becase the target of the branch might
2010 interfere with that instruction. */
2011 || (! mips_opts
.mips16
2012 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2014 /* Itbl support may require additional care here. */
2015 & (INSN_LOAD_COPROC_DELAY
2016 | INSN_COPROC_MOVE_DELAY
2017 | INSN_WRITE_COND_CODE
)))
2018 || (! (hilo_interlocks
2019 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2023 || (! mips_opts
.mips16
2025 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2026 || (! mips_opts
.mips16
2027 && mips_opts
.isa
== 1
2028 /* Itbl support may require additional care here. */
2029 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2030 /* We can not swap with a branch instruction. */
2032 & (INSN_UNCOND_BRANCH_DELAY
2033 | INSN_COND_BRANCH_DELAY
2034 | INSN_COND_BRANCH_LIKELY
))
2035 /* We do not swap with a trap instruction, since it
2036 complicates trap handlers to have the trap
2037 instruction be in a delay slot. */
2038 || (prev_pinfo
& INSN_TRAP
)
2039 /* If the branch reads a register that the previous
2040 instruction sets, we can not swap. */
2041 || (! mips_opts
.mips16
2042 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2043 && insn_uses_reg (ip
,
2044 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2047 || (! mips_opts
.mips16
2048 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2049 && insn_uses_reg (ip
,
2050 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2053 || (mips_opts
.mips16
2054 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2055 && insn_uses_reg (ip
,
2056 ((prev_insn
.insn_opcode
2058 & MIPS16OP_MASK_RX
),
2060 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2061 && insn_uses_reg (ip
,
2062 ((prev_insn
.insn_opcode
2064 & MIPS16OP_MASK_RY
),
2066 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2067 && insn_uses_reg (ip
,
2068 ((prev_insn
.insn_opcode
2070 & MIPS16OP_MASK_RZ
),
2072 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2073 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2074 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2075 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2076 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2077 && insn_uses_reg (ip
,
2078 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2081 /* If the branch writes a register that the previous
2082 instruction sets, we can not swap (we know that
2083 branches write only to RD or to $31). */
2084 || (! mips_opts
.mips16
2085 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2086 && (((pinfo
& INSN_WRITE_GPR_D
)
2087 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2088 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2089 || ((pinfo
& INSN_WRITE_GPR_31
)
2090 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2093 || (! mips_opts
.mips16
2094 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2095 && (((pinfo
& INSN_WRITE_GPR_D
)
2096 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2097 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2098 || ((pinfo
& INSN_WRITE_GPR_31
)
2099 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2102 || (mips_opts
.mips16
2103 && (pinfo
& MIPS16_INSN_WRITE_31
)
2104 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2105 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2106 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2108 /* If the branch writes a register that the previous
2109 instruction reads, we can not swap (we know that
2110 branches only write to RD or to $31). */
2111 || (! mips_opts
.mips16
2112 && (pinfo
& INSN_WRITE_GPR_D
)
2113 && insn_uses_reg (&prev_insn
,
2114 ((ip
->insn_opcode
>> OP_SH_RD
)
2117 || (! mips_opts
.mips16
2118 && (pinfo
& INSN_WRITE_GPR_31
)
2119 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2120 || (mips_opts
.mips16
2121 && (pinfo
& MIPS16_INSN_WRITE_31
)
2122 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2123 /* If we are generating embedded PIC code, the branch
2124 might be expanded into a sequence which uses $at, so
2125 we can't swap with an instruction which reads it. */
2126 || (mips_pic
== EMBEDDED_PIC
2127 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2128 /* If the previous previous instruction has a load
2129 delay, and sets a register that the branch reads, we
2131 || (! mips_opts
.mips16
2132 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2133 /* Itbl support may require additional care here. */
2134 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2135 || (! gpr_interlocks
2136 && (prev_prev_insn
.insn_mo
->pinfo
2137 & INSN_LOAD_MEMORY_DELAY
)))
2138 && insn_uses_reg (ip
,
2139 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2142 /* If one instruction sets a condition code and the
2143 other one uses a condition code, we can not swap. */
2144 || ((pinfo
& INSN_READ_COND_CODE
)
2145 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2146 || ((pinfo
& INSN_WRITE_COND_CODE
)
2147 && (prev_pinfo
& INSN_READ_COND_CODE
))
2148 /* If the previous instruction uses the PC, we can not
2150 || (mips_opts
.mips16
2151 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2152 /* If the previous instruction was extended, we can not
2154 || (mips_opts
.mips16
&& prev_insn_extended
)
2155 /* If the previous instruction had a fixup in mips16
2156 mode, we can not swap. This normally means that the
2157 previous instruction was a 4 byte branch anyhow. */
2158 || (mips_opts
.mips16
&& prev_insn_fixp
)
2159 /* If the previous instruction is a sync, sync.l, or
2160 sync.p, we can not swap. */
2161 || (prev_pinfo
& INSN_SYNC
))
2163 /* We could do even better for unconditional branches to
2164 portions of this object file; we could pick up the
2165 instruction at the destination, put it in the delay
2166 slot, and bump the destination address. */
2168 /* Update the previous insn information. */
2169 prev_prev_insn
= *ip
;
2170 prev_insn
.insn_mo
= &dummy_opcode
;
2174 /* It looks like we can actually do the swap. */
2175 if (! mips_opts
.mips16
)
2180 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2181 memcpy (temp
, prev_f
, 4);
2182 memcpy (prev_f
, f
, 4);
2183 memcpy (f
, temp
, 4);
2186 prev_insn_fixp
->fx_frag
= frag_now
;
2187 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2191 fixp
->fx_frag
= prev_insn_frag
;
2192 fixp
->fx_where
= prev_insn_where
;
2200 assert (prev_insn_fixp
== NULL
);
2201 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2202 memcpy (temp
, prev_f
, 2);
2203 memcpy (prev_f
, f
, 2);
2204 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2206 assert (reloc_type
== BFD_RELOC_UNUSED
);
2207 memcpy (f
, temp
, 2);
2211 memcpy (f
, f
+ 2, 2);
2212 memcpy (f
+ 2, temp
, 2);
2216 fixp
->fx_frag
= prev_insn_frag
;
2217 fixp
->fx_where
= prev_insn_where
;
2221 /* Update the previous insn information; leave prev_insn
2223 prev_prev_insn
= *ip
;
2225 prev_insn_is_delay_slot
= 1;
2227 /* If that was an unconditional branch, forget the previous
2228 insn information. */
2229 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2231 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2232 prev_insn
.insn_mo
= &dummy_opcode
;
2235 prev_insn_fixp
= NULL
;
2236 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2237 prev_insn_extended
= 0;
2239 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2241 /* We don't yet optimize a branch likely. What we should do
2242 is look at the target, copy the instruction found there
2243 into the delay slot, and increment the branch to jump to
2244 the next instruction. */
2246 /* Update the previous insn information. */
2247 prev_prev_insn
= *ip
;
2248 prev_insn
.insn_mo
= &dummy_opcode
;
2249 prev_insn_fixp
= NULL
;
2250 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2251 prev_insn_extended
= 0;
2255 /* Update the previous insn information. */
2257 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2259 prev_prev_insn
= prev_insn
;
2262 /* Any time we see a branch, we always fill the delay slot
2263 immediately; since this insn is not a branch, we know it
2264 is not in a delay slot. */
2265 prev_insn_is_delay_slot
= 0;
2267 prev_insn_fixp
= fixp
;
2268 prev_insn_reloc_type
= reloc_type
;
2269 if (mips_opts
.mips16
)
2270 prev_insn_extended
= (ip
->use_extend
2271 || reloc_type
> BFD_RELOC_UNUSED
);
2274 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2275 prev_insn_unreordered
= 0;
2276 prev_insn_frag
= frag_now
;
2277 prev_insn_where
= f
- frag_now
->fr_literal
;
2278 prev_insn_valid
= 1;
2280 else if (place
== NULL
)
2282 /* We need to record a bit of information even when we are not
2283 reordering, in order to determine the base address for mips16
2284 PC relative relocs. */
2285 prev_prev_insn
= prev_insn
;
2287 prev_insn_reloc_type
= reloc_type
;
2288 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2289 prev_insn_unreordered
= 1;
2292 /* We just output an insn, so the next one doesn't have a label. */
2293 mips_clear_insn_labels ();
2295 /* We must ensure that a fixup associated with an unmatched %hi
2296 reloc does not become a variant frag. Otherwise, the
2297 rearrangement of %hi relocs in frob_file may confuse
2301 frag_wane (frag_now
);
2306 /* This function forgets that there was any previous instruction or
2307 label. If PRESERVE is non-zero, it remembers enough information to
2308 know whether nops are needed before a noreorder section. */
2311 mips_no_prev_insn (preserve
)
2316 prev_insn
.insn_mo
= &dummy_opcode
;
2317 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2318 prev_nop_frag
= NULL
;
2319 prev_nop_frag_holds
= 0;
2320 prev_nop_frag_required
= 0;
2321 prev_nop_frag_since
= 0;
2323 prev_insn_valid
= 0;
2324 prev_insn_is_delay_slot
= 0;
2325 prev_insn_unreordered
= 0;
2326 prev_insn_extended
= 0;
2327 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2328 prev_prev_insn_unreordered
= 0;
2329 mips_clear_insn_labels ();
2332 /* This function must be called whenever we turn on noreorder or emit
2333 something other than instructions. It inserts any NOPS which might
2334 be needed by the previous instruction, and clears the information
2335 kept for the previous instructions. The INSNS parameter is true if
2336 instructions are to follow. */
2339 mips_emit_delays (insns
)
2342 if (! mips_opts
.noreorder
)
2347 if ((! mips_opts
.mips16
2348 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2349 && (! cop_interlocks
2350 && (prev_insn
.insn_mo
->pinfo
2351 & (INSN_LOAD_COPROC_DELAY
2352 | INSN_COPROC_MOVE_DELAY
2353 | INSN_WRITE_COND_CODE
))))
2354 || (! hilo_interlocks
2355 && (prev_insn
.insn_mo
->pinfo
2358 || (! mips_opts
.mips16
2360 && (prev_insn
.insn_mo
->pinfo
2361 & INSN_LOAD_MEMORY_DELAY
))
2362 || (! mips_opts
.mips16
2363 && mips_opts
.isa
== 1
2364 && (prev_insn
.insn_mo
->pinfo
2365 & INSN_COPROC_MEMORY_DELAY
)))
2367 /* Itbl support may require additional care here. */
2369 if ((! mips_opts
.mips16
2370 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2371 && (! cop_interlocks
2372 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2373 || (! hilo_interlocks
2374 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2375 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2378 if (prev_insn_unreordered
)
2381 else if ((! mips_opts
.mips16
2382 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2383 && (! cop_interlocks
2384 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2385 || (! hilo_interlocks
2386 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2387 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2389 /* Itbl support may require additional care here. */
2390 if (! prev_prev_insn_unreordered
)
2396 struct insn_label_list
*l
;
2400 /* Record the frag which holds the nop instructions, so
2401 that we can remove them if we don't need them. */
2402 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2403 prev_nop_frag
= frag_now
;
2404 prev_nop_frag_holds
= nops
;
2405 prev_nop_frag_required
= 0;
2406 prev_nop_frag_since
= 0;
2409 for (; nops
> 0; --nops
)
2414 /* Move on to a new frag, so that it is safe to simply
2415 decrease the size of prev_nop_frag. */
2416 frag_wane (frag_now
);
2420 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2422 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2423 symbol_set_frag (l
->label
, frag_now
);
2424 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2425 /* mips16 text labels are stored as odd. */
2426 if (mips_opts
.mips16
)
2427 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2432 /* Mark instruction labels in mips16 mode. */
2433 if (mips_opts
.mips16
&& insns
)
2434 mips16_mark_labels ();
2436 mips_no_prev_insn (insns
);
2439 /* Build an instruction created by a macro expansion. This is passed
2440 a pointer to the count of instructions created so far, an
2441 expression, the name of the instruction to build, an operand format
2442 string, and corresponding arguments. */
2446 macro_build (char *place
,
2454 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2463 struct mips_cl_insn insn
;
2464 bfd_reloc_code_real_type r
;
2468 va_start (args
, fmt
);
2474 * If the macro is about to expand into a second instruction,
2475 * print a warning if needed. We need to pass ip as a parameter
2476 * to generate a better warning message here...
2478 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2479 as_warn (_("Macro instruction expanded into multiple instructions"));
2482 *counter
+= 1; /* bump instruction counter */
2484 if (mips_opts
.mips16
)
2486 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2491 r
= BFD_RELOC_UNUSED
;
2492 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2493 assert (insn
.insn_mo
);
2494 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2496 /* Search until we get a match for NAME. */
2499 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2500 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2501 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
)
2502 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2506 assert (insn
.insn_mo
->name
);
2507 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2510 insn
.insn_opcode
= insn
.insn_mo
->match
;
2526 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2532 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2537 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2542 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2553 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2557 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2561 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2568 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2574 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2575 assert (r
== BFD_RELOC_MIPS_GPREL
2576 || r
== BFD_RELOC_MIPS_LITERAL
2577 || r
== BFD_RELOC_LO16
2578 || r
== BFD_RELOC_MIPS_GOT16
2579 || r
== BFD_RELOC_MIPS_CALL16
2580 || r
== BFD_RELOC_MIPS_GOT_LO16
2581 || r
== BFD_RELOC_MIPS_CALL_LO16
2582 || (ep
->X_op
== O_subtract
2583 && now_seg
== text_section
2584 && r
== BFD_RELOC_PCREL_LO16
));
2588 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2590 && (ep
->X_op
== O_constant
2591 || (ep
->X_op
== O_symbol
2592 && (r
== BFD_RELOC_HI16_S
2593 || r
== BFD_RELOC_HI16
2594 || r
== BFD_RELOC_MIPS_GOT_HI16
2595 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2596 || (ep
->X_op
== O_subtract
2597 && now_seg
== text_section
2598 && r
== BFD_RELOC_PCREL_HI16_S
)));
2599 if (ep
->X_op
== O_constant
)
2601 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2603 r
= BFD_RELOC_UNUSED
;
2608 assert (ep
!= NULL
);
2610 * This allows macro() to pass an immediate expression for
2611 * creating short branches without creating a symbol.
2612 * Note that the expression still might come from the assembly
2613 * input, in which case the value is not checked for range nor
2614 * is a relocation entry generated (yuck).
2616 if (ep
->X_op
== O_constant
)
2618 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2622 r
= BFD_RELOC_16_PCREL_S2
;
2626 assert (ep
!= NULL
);
2627 r
= BFD_RELOC_MIPS_JMP
;
2631 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2640 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2642 append_insn (place
, &insn
, ep
, r
, false);
2646 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2654 struct mips_cl_insn insn
;
2655 bfd_reloc_code_real_type r
;
2657 r
= BFD_RELOC_UNUSED
;
2658 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2659 assert (insn
.insn_mo
);
2660 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2662 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2663 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2666 assert (insn
.insn_mo
->name
);
2667 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2670 insn
.insn_opcode
= insn
.insn_mo
->match
;
2671 insn
.use_extend
= false;
2690 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2695 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2699 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2703 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2713 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2720 regno
= va_arg (args
, int);
2721 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2722 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2743 assert (ep
!= NULL
);
2745 if (ep
->X_op
!= O_constant
)
2746 r
= BFD_RELOC_UNUSED
+ c
;
2749 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2750 false, false, &insn
.insn_opcode
,
2751 &insn
.use_extend
, &insn
.extend
);
2753 r
= BFD_RELOC_UNUSED
;
2759 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2766 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2768 append_insn (place
, &insn
, ep
, r
, false);
2772 * Generate a "lui" instruction.
2775 macro_build_lui (place
, counter
, ep
, regnum
)
2781 expressionS high_expr
;
2782 struct mips_cl_insn insn
;
2783 bfd_reloc_code_real_type r
;
2784 CONST
char *name
= "lui";
2785 CONST
char *fmt
= "t,u";
2787 assert (! mips_opts
.mips16
);
2793 high_expr
.X_op
= O_constant
;
2794 high_expr
.X_add_number
= ep
->X_add_number
;
2797 if (high_expr
.X_op
== O_constant
)
2799 /* we can compute the instruction now without a relocation entry */
2800 if (high_expr
.X_add_number
& 0x8000)
2801 high_expr
.X_add_number
+= 0x10000;
2802 high_expr
.X_add_number
=
2803 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2804 r
= BFD_RELOC_UNUSED
;
2808 assert (ep
->X_op
== O_symbol
);
2809 /* _gp_disp is a special case, used from s_cpload. */
2810 assert (mips_pic
== NO_PIC
2811 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2812 r
= BFD_RELOC_HI16_S
;
2816 * If the macro is about to expand into a second instruction,
2817 * print a warning if needed. We need to pass ip as a parameter
2818 * to generate a better warning message here...
2820 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2821 as_warn (_("Macro instruction expanded into multiple instructions"));
2824 *counter
+= 1; /* bump instruction counter */
2826 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2827 assert (insn
.insn_mo
);
2828 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2829 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2831 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2832 if (r
== BFD_RELOC_UNUSED
)
2834 insn
.insn_opcode
|= high_expr
.X_add_number
;
2835 append_insn (place
, &insn
, NULL
, r
, false);
2838 append_insn (place
, &insn
, &high_expr
, r
, false);
2842 * Generates code to set the $at register to true (one)
2843 * if reg is less than the immediate expression.
2846 set_at (counter
, reg
, unsignedp
)
2851 if (imm_expr
.X_op
== O_constant
2852 && imm_expr
.X_add_number
>= -0x8000
2853 && imm_expr
.X_add_number
< 0x8000)
2854 macro_build ((char *) NULL
, counter
, &imm_expr
,
2855 unsignedp
? "sltiu" : "slti",
2856 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2859 load_register (counter
, AT
, &imm_expr
, 0);
2860 macro_build ((char *) NULL
, counter
, NULL
,
2861 unsignedp
? "sltu" : "slt",
2862 "d,v,t", AT
, reg
, AT
);
2866 /* Warn if an expression is not a constant. */
2869 check_absolute_expr (ip
, ex
)
2870 struct mips_cl_insn
*ip
;
2873 if (ex
->X_op
== O_big
)
2874 as_bad (_("unsupported large constant"));
2875 else if (ex
->X_op
!= O_constant
)
2876 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2879 /* Count the leading zeroes by performing a binary chop. This is a
2880 bulky bit of source, but performance is a LOT better for the
2881 majority of values than a simple loop to count the bits:
2882 for (lcnt = 0; (lcnt < 32); lcnt++)
2883 if ((v) & (1 << (31 - lcnt)))
2885 However it is not code size friendly, and the gain will drop a bit
2886 on certain cached systems.
2888 #define COUNT_TOP_ZEROES(v) \
2889 (((v) & ~0xffff) == 0 \
2890 ? ((v) & ~0xff) == 0 \
2891 ? ((v) & ~0xf) == 0 \
2892 ? ((v) & ~0x3) == 0 \
2893 ? ((v) & ~0x1) == 0 \
2898 : ((v) & ~0x7) == 0 \
2901 : ((v) & ~0x3f) == 0 \
2902 ? ((v) & ~0x1f) == 0 \
2905 : ((v) & ~0x7f) == 0 \
2908 : ((v) & ~0xfff) == 0 \
2909 ? ((v) & ~0x3ff) == 0 \
2910 ? ((v) & ~0x1ff) == 0 \
2913 : ((v) & ~0x7ff) == 0 \
2916 : ((v) & ~0x3fff) == 0 \
2917 ? ((v) & ~0x1fff) == 0 \
2920 : ((v) & ~0x7fff) == 0 \
2923 : ((v) & ~0xffffff) == 0 \
2924 ? ((v) & ~0xfffff) == 0 \
2925 ? ((v) & ~0x3ffff) == 0 \
2926 ? ((v) & ~0x1ffff) == 0 \
2929 : ((v) & ~0x7ffff) == 0 \
2932 : ((v) & ~0x3fffff) == 0 \
2933 ? ((v) & ~0x1fffff) == 0 \
2936 : ((v) & ~0x7fffff) == 0 \
2939 : ((v) & ~0xfffffff) == 0 \
2940 ? ((v) & ~0x3ffffff) == 0 \
2941 ? ((v) & ~0x1ffffff) == 0 \
2944 : ((v) & ~0x7ffffff) == 0 \
2947 : ((v) & ~0x3fffffff) == 0 \
2948 ? ((v) & ~0x1fffffff) == 0 \
2951 : ((v) & ~0x7fffffff) == 0 \
2956 * This routine generates the least number of instructions neccessary to load
2957 * an absolute expression value into a register.
2960 load_register (counter
, reg
, ep
, dbl
)
2967 expressionS hi32
, lo32
;
2969 if (ep
->X_op
!= O_big
)
2971 assert (ep
->X_op
== O_constant
);
2972 if (ep
->X_add_number
< 0x8000
2973 && (ep
->X_add_number
>= 0
2974 || (ep
->X_add_number
>= -0x8000
2977 || sizeof (ep
->X_add_number
) > 4))))
2979 /* We can handle 16 bit signed values with an addiu to
2980 $zero. No need to ever use daddiu here, since $zero and
2981 the result are always correct in 32 bit mode. */
2982 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2983 (int) BFD_RELOC_LO16
);
2986 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2988 /* We can handle 16 bit unsigned values with an ori to
2990 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2991 (int) BFD_RELOC_LO16
);
2994 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2995 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2996 == ~ (offsetT
) 0x7fffffff))
2999 || sizeof (ep
->X_add_number
) > 4
3000 || (ep
->X_add_number
& 0x80000000) == 0))
3001 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3002 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3003 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3005 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3006 == ~ (offsetT
) 0xffffffff)))
3008 /* 32 bit values require an lui. */
3009 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3010 (int) BFD_RELOC_HI16
);
3011 if ((ep
->X_add_number
& 0xffff) != 0)
3012 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3013 (int) BFD_RELOC_LO16
);
3018 /* The value is larger than 32 bits. */
3020 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3022 as_bad (_("Number larger than 32 bits"));
3023 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3024 (int) BFD_RELOC_LO16
);
3028 if (ep
->X_op
!= O_big
)
3031 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3032 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3033 hi32
.X_add_number
&= 0xffffffff;
3035 lo32
.X_add_number
&= 0xffffffff;
3039 assert (ep
->X_add_number
> 2);
3040 if (ep
->X_add_number
== 3)
3041 generic_bignum
[3] = 0;
3042 else if (ep
->X_add_number
> 4)
3043 as_bad (_("Number larger than 64 bits"));
3044 lo32
.X_op
= O_constant
;
3045 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3046 hi32
.X_op
= O_constant
;
3047 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3050 if (hi32
.X_add_number
== 0)
3055 unsigned long hi
, lo
;
3057 if (hi32
.X_add_number
== 0xffffffff)
3059 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3061 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3062 reg
, 0, (int) BFD_RELOC_LO16
);
3065 if (lo32
.X_add_number
& 0x80000000)
3067 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3068 (int) BFD_RELOC_HI16
);
3069 if (lo32
.X_add_number
& 0xffff)
3070 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3071 reg
, reg
, (int) BFD_RELOC_LO16
);
3076 /* Check for 16bit shifted constant. We know that hi32 is
3077 non-zero, so start the mask on the first bit of the hi32
3082 unsigned long himask
, lomask
;
3086 himask
= 0xffff >> (32 - shift
);
3087 lomask
= (0xffff << shift
) & 0xffffffff;
3091 himask
= 0xffff << (shift
- 32);
3094 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3095 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3099 tmp
.X_op
= O_constant
;
3101 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3102 | (lo32
.X_add_number
>> shift
));
3104 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3105 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3106 (int) BFD_RELOC_LO16
);
3107 macro_build ((char *) NULL
, counter
, NULL
,
3108 (shift
>= 32) ? "dsll32" : "dsll",
3110 (shift
>= 32) ? shift
- 32 : shift
);
3114 } while (shift
<= (64 - 16));
3116 /* Find the bit number of the lowest one bit, and store the
3117 shifted value in hi/lo. */
3118 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3119 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3123 while ((lo
& 1) == 0)
3128 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3134 while ((hi
& 1) == 0)
3143 /* Optimize if the shifted value is a (power of 2) - 1. */
3144 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3145 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3147 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3152 /* This instruction will set the register to be all
3154 tmp
.X_op
= O_constant
;
3155 tmp
.X_add_number
= (offsetT
) -1;
3156 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3157 reg
, 0, (int) BFD_RELOC_LO16
);
3161 macro_build ((char *) NULL
, counter
, NULL
,
3162 (bit
>= 32) ? "dsll32" : "dsll",
3164 (bit
>= 32) ? bit
- 32 : bit
);
3166 macro_build ((char *) NULL
, counter
, NULL
,
3167 (shift
>= 32) ? "dsrl32" : "dsrl",
3169 (shift
>= 32) ? shift
- 32 : shift
);
3174 /* Sign extend hi32 before calling load_register, because we can
3175 generally get better code when we load a sign extended value. */
3176 if ((hi32
.X_add_number
& 0x80000000) != 0)
3177 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3178 load_register (counter
, reg
, &hi32
, 0);
3181 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3185 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3194 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3196 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3197 (int) BFD_RELOC_HI16
);
3198 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3205 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3210 mid16
.X_add_number
>>= 16;
3211 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3212 freg
, (int) BFD_RELOC_LO16
);
3213 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3217 if ((lo32
.X_add_number
& 0xffff) != 0)
3218 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3219 (int) BFD_RELOC_LO16
);
3222 /* Load an address into a register. */
3225 load_address (counter
, reg
, ep
)
3232 if (ep
->X_op
!= O_constant
3233 && ep
->X_op
!= O_symbol
)
3235 as_bad (_("expression too complex"));
3236 ep
->X_op
= O_constant
;
3239 if (ep
->X_op
== O_constant
)
3241 load_register (counter
, reg
, ep
, 0);
3245 if (mips_pic
== NO_PIC
)
3247 /* If this is a reference to a GP relative symbol, we want
3248 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3250 lui $reg,<sym> (BFD_RELOC_HI16_S)
3251 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3252 If we have an addend, we always use the latter form. */
3253 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3254 || nopic_need_relax (ep
->X_add_symbol
, 1))
3259 macro_build ((char *) NULL
, counter
, ep
,
3260 ((bfd_arch_bits_per_address (stdoutput
) == 32
3261 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3262 ? "addiu" : "daddiu"),
3263 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3264 p
= frag_var (rs_machine_dependent
, 8, 0,
3265 RELAX_ENCODE (4, 8, 0, 4, 0,
3266 mips_opts
.warn_about_macros
),
3267 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3269 macro_build_lui (p
, counter
, ep
, reg
);
3272 macro_build (p
, counter
, ep
,
3273 ((bfd_arch_bits_per_address (stdoutput
) == 32
3274 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3275 ? "addiu" : "daddiu"),
3276 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3278 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3282 /* If this is a reference to an external symbol, we want
3283 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3285 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3287 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3288 If there is a constant, it must be added in after. */
3289 ex
.X_add_number
= ep
->X_add_number
;
3290 ep
->X_add_number
= 0;
3292 macro_build ((char *) NULL
, counter
, ep
,
3293 ((bfd_arch_bits_per_address (stdoutput
) == 32
3294 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3296 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3297 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3298 p
= frag_var (rs_machine_dependent
, 4, 0,
3299 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3300 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3301 macro_build (p
, counter
, ep
,
3302 ((bfd_arch_bits_per_address (stdoutput
) == 32
3303 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3304 ? "addiu" : "daddiu"),
3305 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3306 if (ex
.X_add_number
!= 0)
3308 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3309 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3310 ex
.X_op
= O_constant
;
3311 macro_build ((char *) NULL
, counter
, &ex
,
3312 ((bfd_arch_bits_per_address (stdoutput
) == 32
3313 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3314 ? "addiu" : "daddiu"),
3315 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3318 else if (mips_pic
== SVR4_PIC
)
3323 /* This is the large GOT case. If this is a reference to an
3324 external symbol, we want
3325 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3327 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3328 Otherwise, for a reference to a local symbol, we want
3329 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3331 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3332 If there is a constant, it must be added in after. */
3333 ex
.X_add_number
= ep
->X_add_number
;
3334 ep
->X_add_number
= 0;
3335 if (reg_needs_delay (GP
))
3340 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3341 (int) BFD_RELOC_MIPS_GOT_HI16
);
3342 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3343 ((bfd_arch_bits_per_address (stdoutput
) == 32
3344 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3345 ? "addu" : "daddu"),
3346 "d,v,t", reg
, reg
, GP
);
3347 macro_build ((char *) NULL
, counter
, ep
,
3348 ((bfd_arch_bits_per_address (stdoutput
) == 32
3349 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3351 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3352 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3353 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3354 mips_opts
.warn_about_macros
),
3355 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3358 /* We need a nop before loading from $gp. This special
3359 check is required because the lui which starts the main
3360 instruction stream does not refer to $gp, and so will not
3361 insert the nop which may be required. */
3362 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3365 macro_build (p
, counter
, ep
,
3366 ((bfd_arch_bits_per_address (stdoutput
) == 32
3367 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3369 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3371 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3373 macro_build (p
, counter
, ep
,
3374 ((bfd_arch_bits_per_address (stdoutput
) == 32
3375 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3376 ? "addiu" : "daddiu"),
3377 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3378 if (ex
.X_add_number
!= 0)
3380 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3381 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3382 ex
.X_op
= O_constant
;
3383 macro_build ((char *) NULL
, counter
, &ex
,
3384 ((bfd_arch_bits_per_address (stdoutput
) == 32
3385 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3386 ? "addiu" : "daddiu"),
3387 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3390 else if (mips_pic
== EMBEDDED_PIC
)
3393 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3395 macro_build ((char *) NULL
, counter
, ep
,
3396 ((bfd_arch_bits_per_address (stdoutput
) == 32
3397 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3398 ? "addiu" : "daddiu"),
3399 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3407 * This routine implements the seemingly endless macro or synthesized
3408 * instructions and addressing modes in the mips assembly language. Many
3409 * of these macros are simple and are similar to each other. These could
3410 * probably be handled by some kind of table or grammer aproach instead of
3411 * this verbose method. Others are not simple macros but are more like
3412 * optimizing code generation.
3413 * One interesting optimization is when several store macros appear
3414 * consecutivly that would load AT with the upper half of the same address.
3415 * The ensuing load upper instructions are ommited. This implies some kind
3416 * of global optimization. We currently only optimize within a single macro.
3417 * For many of the load and store macros if the address is specified as a
3418 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3419 * first load register 'at' with zero and use it as the base register. The
3420 * mips assembler simply uses register $zero. Just one tiny optimization
3425 struct mips_cl_insn
*ip
;
3427 register int treg
, sreg
, dreg
, breg
;
3443 bfd_reloc_code_real_type r
;
3445 int hold_mips_optimize
;
3447 assert (! mips_opts
.mips16
);
3449 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3450 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3451 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3452 mask
= ip
->insn_mo
->mask
;
3454 expr1
.X_op
= O_constant
;
3455 expr1
.X_op_symbol
= NULL
;
3456 expr1
.X_add_symbol
= NULL
;
3457 expr1
.X_add_number
= 1;
3469 mips_emit_delays (true);
3470 ++mips_opts
.noreorder
;
3471 mips_any_noreorder
= 1;
3473 expr1
.X_add_number
= 8;
3474 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3476 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3478 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3479 macro_build ((char *) NULL
, &icnt
, NULL
,
3480 dbl
? "dsub" : "sub",
3481 "d,v,t", dreg
, 0, sreg
);
3483 --mips_opts
.noreorder
;
3504 if (imm_expr
.X_op
== O_constant
3505 && imm_expr
.X_add_number
>= -0x8000
3506 && imm_expr
.X_add_number
< 0x8000)
3508 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3509 (int) BFD_RELOC_LO16
);
3512 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3513 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3532 if (imm_expr
.X_op
== O_constant
3533 && imm_expr
.X_add_number
>= 0
3534 && imm_expr
.X_add_number
< 0x10000)
3536 if (mask
!= M_NOR_I
)
3537 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3538 sreg
, (int) BFD_RELOC_LO16
);
3541 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3542 treg
, sreg
, (int) BFD_RELOC_LO16
);
3543 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3549 load_register (&icnt
, AT
, &imm_expr
, 0);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3567 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3573 load_register (&icnt
, AT
, &imm_expr
, 0);
3574 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3582 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3583 likely
? "bgezl" : "bgez",
3589 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3590 likely
? "blezl" : "blez",
3594 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3596 likely
? "beql" : "beq",
3603 /* check for > max integer */
3604 maxnum
= 0x7fffffff;
3605 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3612 if (imm_expr
.X_op
== O_constant
3613 && imm_expr
.X_add_number
>= maxnum
3614 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3617 /* result is always false */
3620 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3621 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3625 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3631 if (imm_expr
.X_op
!= O_constant
)
3632 as_bad (_("Unsupported large constant"));
3633 imm_expr
.X_add_number
++;
3637 if (mask
== M_BGEL_I
)
3639 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3641 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3642 likely
? "bgezl" : "bgez",
3646 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3648 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3649 likely
? "bgtzl" : "bgtz",
3653 maxnum
= 0x7fffffff;
3654 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3661 maxnum
= - maxnum
- 1;
3662 if (imm_expr
.X_op
== O_constant
3663 && imm_expr
.X_add_number
<= maxnum
3664 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3667 /* result is always true */
3668 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3672 set_at (&icnt
, sreg
, 0);
3673 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3674 likely
? "beql" : "beq",
3685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3686 likely
? "beql" : "beq",
3690 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3692 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3693 likely
? "beql" : "beq",
3701 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3702 && imm_expr
.X_op
== O_constant
3703 && imm_expr
.X_add_number
== 0xffffffff))
3705 if (imm_expr
.X_op
!= O_constant
)
3706 as_bad (_("Unsupported large constant"));
3707 imm_expr
.X_add_number
++;
3711 if (mask
== M_BGEUL_I
)
3713 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3715 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3717 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3718 likely
? "bnel" : "bne",
3722 set_at (&icnt
, sreg
, 1);
3723 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3724 likely
? "beql" : "beq",
3733 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3734 likely
? "bgtzl" : "bgtz",
3740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3741 likely
? "bltzl" : "bltz",
3745 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 likely
? "bnel" : "bne",
3756 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3757 likely
? "bnel" : "bne",
3763 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3765 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3766 likely
? "bnel" : "bne",
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "blezl" : "blez",
3782 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3783 likely
? "bgezl" : "bgez",
3787 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3788 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3789 likely
? "beql" : "beq",
3796 maxnum
= 0x7fffffff;
3797 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3804 if (imm_expr
.X_op
== O_constant
3805 && imm_expr
.X_add_number
>= maxnum
3806 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3808 if (imm_expr
.X_op
!= O_constant
)
3809 as_bad (_("Unsupported large constant"));
3810 imm_expr
.X_add_number
++;
3814 if (mask
== M_BLTL_I
)
3816 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3818 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3819 likely
? "bltzl" : "bltz",
3823 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3826 likely
? "blezl" : "blez",
3830 set_at (&icnt
, sreg
, 0);
3831 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3832 likely
? "bnel" : "bne",
3841 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3842 likely
? "beql" : "beq",
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3850 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3851 likely
? "beql" : "beq",
3859 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3860 && imm_expr
.X_op
== O_constant
3861 && imm_expr
.X_add_number
== 0xffffffff))
3863 if (imm_expr
.X_op
!= O_constant
)
3864 as_bad (_("Unsupported large constant"));
3865 imm_expr
.X_add_number
++;
3869 if (mask
== M_BLTUL_I
)
3871 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3873 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3875 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3876 likely
? "beql" : "beq",
3880 set_at (&icnt
, sreg
, 1);
3881 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3882 likely
? "bnel" : "bne",
3891 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3892 likely
? "bltzl" : "bltz",
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3899 likely
? "bgtzl" : "bgtz",
3903 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3905 likely
? "bnel" : "bne",
3916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3917 likely
? "bnel" : "bne",
3921 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3924 likely
? "bnel" : "bne",
3940 as_warn (_("Divide by zero."));
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3944 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3948 mips_emit_delays (true);
3949 ++mips_opts
.noreorder
;
3950 mips_any_noreorder
= 1;
3953 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3954 macro_build ((char *) NULL
, &icnt
, NULL
,
3955 dbl
? "ddiv" : "div",
3956 "z,s,t", sreg
, treg
);
3960 expr1
.X_add_number
= 8;
3961 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3962 macro_build ((char *) NULL
, &icnt
, NULL
,
3963 dbl
? "ddiv" : "div",
3964 "z,s,t", sreg
, treg
);
3965 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3967 expr1
.X_add_number
= -1;
3968 macro_build ((char *) NULL
, &icnt
, &expr1
,
3969 dbl
? "daddiu" : "addiu",
3970 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3971 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3972 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3975 expr1
.X_add_number
= 1;
3976 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3977 (int) BFD_RELOC_LO16
);
3978 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3983 expr1
.X_add_number
= 0x80000000;
3984 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3985 (int) BFD_RELOC_HI16
);
3989 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3990 /* We want to close the noreorder block as soon as possible, so
3991 that later insns are available for delay slot filling. */
3992 --mips_opts
.noreorder
;
3996 expr1
.X_add_number
= 8;
3997 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3998 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4000 /* We want to close the noreorder block as soon as possible, so
4001 that later insns are available for delay slot filling. */
4002 --mips_opts
.noreorder
;
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4006 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4045 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4047 as_warn (_("Divide by zero."));
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4051 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4054 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4056 if (strcmp (s2
, "mflo") == 0)
4057 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4060 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4063 if (imm_expr
.X_op
== O_constant
4064 && imm_expr
.X_add_number
== -1
4065 && s
[strlen (s
) - 1] != 'u')
4067 if (strcmp (s2
, "mflo") == 0)
4070 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4073 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4077 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4081 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4082 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4083 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4102 mips_emit_delays (true);
4103 ++mips_opts
.noreorder
;
4104 mips_any_noreorder
= 1;
4107 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4108 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4109 /* We want to close the noreorder block as soon as possible, so
4110 that later insns are available for delay slot filling. */
4111 --mips_opts
.noreorder
;
4115 expr1
.X_add_number
= 8;
4116 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4117 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4119 /* We want to close the noreorder block as soon as possible, so
4120 that later insns are available for delay slot filling. */
4121 --mips_opts
.noreorder
;
4122 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4124 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4130 /* Load the address of a symbol into a register. If breg is not
4131 zero, we then add a base register to it. */
4133 /* When generating embedded PIC code, we permit expressions of
4136 where bar is an address in the .text section. These are used
4137 when getting the addresses of functions. We don't permit
4138 X_add_number to be non-zero, because if the symbol is
4139 external the relaxing code needs to know that any addend is
4140 purely the offset to X_op_symbol. */
4141 if (mips_pic
== EMBEDDED_PIC
4142 && offset_expr
.X_op
== O_subtract
4143 && now_seg
== text_section
4144 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4145 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4146 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4148 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4152 && offset_expr
.X_add_number
== 0)
4154 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4155 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4156 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4157 ((bfd_arch_bits_per_address (stdoutput
) == 32
4158 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4159 ? "addiu" : "daddiu"),
4160 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4164 if (offset_expr
.X_op
!= O_symbol
4165 && offset_expr
.X_op
!= O_constant
)
4167 as_bad (_("expression too complex"));
4168 offset_expr
.X_op
= O_constant
;
4182 if (offset_expr
.X_op
== O_constant
)
4183 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4184 else if (mips_pic
== NO_PIC
)
4186 /* If this is a reference to an GP relative symbol, we want
4187 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4189 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4190 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4191 If we have a constant, we need two instructions anyhow,
4192 so we may as well always use the latter form. */
4193 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4194 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4199 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4200 ((bfd_arch_bits_per_address (stdoutput
) == 32
4201 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4202 ? "addiu" : "daddiu"),
4203 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4204 p
= frag_var (rs_machine_dependent
, 8, 0,
4205 RELAX_ENCODE (4, 8, 0, 4, 0,
4206 mips_opts
.warn_about_macros
),
4207 offset_expr
.X_add_symbol
, (offsetT
) 0,
4210 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4213 macro_build (p
, &icnt
, &offset_expr
,
4214 ((bfd_arch_bits_per_address (stdoutput
) == 32
4215 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4216 ? "addiu" : "daddiu"),
4217 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4219 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4221 /* If this is a reference to an external symbol, and there
4222 is no constant, we want
4223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4224 For a local symbol, we want
4225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4227 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4229 If we have a small constant, and this is a reference to
4230 an external symbol, we want
4231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4233 addiu $tempreg,$tempreg,<constant>
4234 For a local symbol, we want the same instruction
4235 sequence, but we output a BFD_RELOC_LO16 reloc on the
4238 If we have a large constant, and this is a reference to
4239 an external symbol, we want
4240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4241 lui $at,<hiconstant>
4242 addiu $at,$at,<loconstant>
4243 addu $tempreg,$tempreg,$at
4244 For a local symbol, we want the same instruction
4245 sequence, but we output a BFD_RELOC_LO16 reloc on the
4246 addiu instruction. */
4247 expr1
.X_add_number
= offset_expr
.X_add_number
;
4248 offset_expr
.X_add_number
= 0;
4250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4252 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4253 if (expr1
.X_add_number
== 0)
4261 /* We're going to put in an addu instruction using
4262 tempreg, so we may as well insert the nop right
4264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4268 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4269 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4271 ? mips_opts
.warn_about_macros
4273 offset_expr
.X_add_symbol
, (offsetT
) 0,
4277 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4280 macro_build (p
, &icnt
, &expr1
,
4281 ((bfd_arch_bits_per_address (stdoutput
) == 32
4282 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4283 ? "addiu" : "daddiu"),
4284 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4285 /* FIXME: If breg == 0, and the next instruction uses
4286 $tempreg, then if this variant case is used an extra
4287 nop will be generated. */
4289 else if (expr1
.X_add_number
>= -0x8000
4290 && expr1
.X_add_number
< 0x8000)
4292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4294 macro_build ((char *) NULL
, &icnt
, &expr1
,
4295 ((bfd_arch_bits_per_address (stdoutput
) == 32
4296 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4297 ? "addiu" : "daddiu"),
4298 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4299 (void) frag_var (rs_machine_dependent
, 0, 0,
4300 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4301 offset_expr
.X_add_symbol
, (offsetT
) 0,
4308 /* If we are going to add in a base register, and the
4309 target register and the base register are the same,
4310 then we are using AT as a temporary register. Since
4311 we want to load the constant into AT, we add our
4312 current AT (from the global offset table) and the
4313 register into the register now, and pretend we were
4314 not using a base register. */
4319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4322 ((bfd_arch_bits_per_address (stdoutput
) == 32
4323 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4324 ? "addu" : "daddu"),
4325 "d,v,t", treg
, AT
, breg
);
4331 /* Set mips_optimize around the lui instruction to avoid
4332 inserting an unnecessary nop after the lw. */
4333 hold_mips_optimize
= mips_optimize
;
4335 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4336 mips_optimize
= hold_mips_optimize
;
4338 macro_build ((char *) NULL
, &icnt
, &expr1
,
4339 ((bfd_arch_bits_per_address (stdoutput
) == 32
4340 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4341 ? "addiu" : "daddiu"),
4342 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4344 ((bfd_arch_bits_per_address (stdoutput
) == 32
4345 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4346 ? "addu" : "daddu"),
4347 "d,v,t", tempreg
, tempreg
, AT
);
4348 (void) frag_var (rs_machine_dependent
, 0, 0,
4349 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4350 offset_expr
.X_add_symbol
, (offsetT
) 0,
4355 else if (mips_pic
== SVR4_PIC
)
4359 /* This is the large GOT case. If this is a reference to an
4360 external symbol, and there is no constant, we want
4361 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4362 addu $tempreg,$tempreg,$gp
4363 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4364 For a local symbol, we want
4365 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4367 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4369 If we have a small constant, and this is a reference to
4370 an external symbol, we want
4371 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4372 addu $tempreg,$tempreg,$gp
4373 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4375 addiu $tempreg,$tempreg,<constant>
4376 For a local symbol, we want
4377 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4379 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4381 If we have a large constant, and this is a reference to
4382 an external symbol, we want
4383 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4384 addu $tempreg,$tempreg,$gp
4385 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4386 lui $at,<hiconstant>
4387 addiu $at,$at,<loconstant>
4388 addu $tempreg,$tempreg,$at
4389 For a local symbol, we want
4390 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4391 lui $at,<hiconstant>
4392 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4393 addu $tempreg,$tempreg,$at
4395 expr1
.X_add_number
= offset_expr
.X_add_number
;
4396 offset_expr
.X_add_number
= 0;
4398 if (reg_needs_delay (GP
))
4402 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4403 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4404 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4405 ((bfd_arch_bits_per_address (stdoutput
) == 32
4406 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4407 ? "addu" : "daddu"),
4408 "d,v,t", tempreg
, tempreg
, GP
);
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4411 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4413 if (expr1
.X_add_number
== 0)
4421 /* We're going to put in an addu instruction using
4422 tempreg, so we may as well insert the nop right
4424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4429 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4430 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4433 ? mips_opts
.warn_about_macros
4435 offset_expr
.X_add_symbol
, (offsetT
) 0,
4438 else if (expr1
.X_add_number
>= -0x8000
4439 && expr1
.X_add_number
< 0x8000)
4441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4443 macro_build ((char *) NULL
, &icnt
, &expr1
,
4444 ((bfd_arch_bits_per_address (stdoutput
) == 32
4445 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4446 ? "addiu" : "daddiu"),
4447 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4449 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4450 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4452 ? mips_opts
.warn_about_macros
4454 offset_expr
.X_add_symbol
, (offsetT
) 0,
4461 /* If we are going to add in a base register, and the
4462 target register and the base register are the same,
4463 then we are using AT as a temporary register. Since
4464 we want to load the constant into AT, we add our
4465 current AT (from the global offset table) and the
4466 register into the register now, and pretend we were
4467 not using a base register. */
4475 assert (tempreg
== AT
);
4476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4479 ((bfd_arch_bits_per_address (stdoutput
) == 32
4480 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4481 ? "addu" : "daddu"),
4482 "d,v,t", treg
, AT
, breg
);
4487 /* Set mips_optimize around the lui instruction to avoid
4488 inserting an unnecessary nop after the lw. */
4489 hold_mips_optimize
= mips_optimize
;
4491 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4492 mips_optimize
= hold_mips_optimize
;
4494 macro_build ((char *) NULL
, &icnt
, &expr1
,
4495 ((bfd_arch_bits_per_address (stdoutput
) == 32
4496 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4497 ? "addiu" : "daddiu"),
4498 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4499 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4500 ((bfd_arch_bits_per_address (stdoutput
) == 32
4501 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4502 ? "addu" : "daddu"),
4503 "d,v,t", dreg
, dreg
, AT
);
4505 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4506 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4509 ? mips_opts
.warn_about_macros
4511 offset_expr
.X_add_symbol
, (offsetT
) 0,
4519 /* This is needed because this instruction uses $gp, but
4520 the first instruction on the main stream does not. */
4521 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4524 macro_build (p
, &icnt
, &offset_expr
,
4526 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4528 if (expr1
.X_add_number
>= -0x8000
4529 && expr1
.X_add_number
< 0x8000)
4531 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4533 macro_build (p
, &icnt
, &expr1
,
4534 ((bfd_arch_bits_per_address (stdoutput
) == 32
4535 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4536 ? "addiu" : "daddiu"),
4537 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4538 /* FIXME: If add_number is 0, and there was no base
4539 register, the external symbol case ended with a load,
4540 so if the symbol turns out to not be external, and
4541 the next instruction uses tempreg, an unnecessary nop
4542 will be inserted. */
4548 /* We must add in the base register now, as in the
4549 external symbol case. */
4550 assert (tempreg
== AT
);
4551 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4553 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4554 ((bfd_arch_bits_per_address (stdoutput
) == 32
4555 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4556 ? "addu" : "daddu"),
4557 "d,v,t", treg
, AT
, breg
);
4560 /* We set breg to 0 because we have arranged to add
4561 it in in both cases. */
4565 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4567 macro_build (p
, &icnt
, &expr1
,
4568 ((bfd_arch_bits_per_address (stdoutput
) == 32
4569 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4570 ? "addiu" : "daddiu"),
4571 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4573 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4574 ((bfd_arch_bits_per_address (stdoutput
) == 32
4575 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4576 ? "addu" : "daddu"),
4577 "d,v,t", tempreg
, tempreg
, AT
);
4581 else if (mips_pic
== EMBEDDED_PIC
)
4584 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4587 ((bfd_arch_bits_per_address (stdoutput
) == 32
4588 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4589 ? "addiu" : "daddiu"),
4590 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4597 ((bfd_arch_bits_per_address (stdoutput
) == 32
4598 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4599 ? "addu" : "daddu"),
4600 "d,v,t", treg
, tempreg
, breg
);
4608 /* The j instruction may not be used in PIC code, since it
4609 requires an absolute address. We convert it to a b
4611 if (mips_pic
== NO_PIC
)
4612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4617 /* The jal instructions must be handled as macros because when
4618 generating PIC code they expand to multi-instruction
4619 sequences. Normally they are simple instructions. */
4624 if (mips_pic
== NO_PIC
4625 || mips_pic
== EMBEDDED_PIC
)
4626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4628 else if (mips_pic
== SVR4_PIC
)
4630 if (sreg
!= PIC_CALL_REG
)
4631 as_warn (_("MIPS PIC call to register other than $25"));
4633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4635 if (mips_cprestore_offset
< 0)
4636 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4639 expr1
.X_add_number
= mips_cprestore_offset
;
4640 macro_build ((char *) NULL
, &icnt
, &expr1
,
4641 ((bfd_arch_bits_per_address (stdoutput
) == 32
4642 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4644 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4653 if (mips_pic
== NO_PIC
)
4654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4655 else if (mips_pic
== SVR4_PIC
)
4657 /* If this is a reference to an external symbol, and we are
4658 using a small GOT, we want
4659 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4663 lw $gp,cprestore($sp)
4664 The cprestore value is set using the .cprestore
4665 pseudo-op. If we are using a big GOT, we want
4666 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4668 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4672 lw $gp,cprestore($sp)
4673 If the symbol is not external, we want
4674 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4676 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4679 lw $gp,cprestore($sp) */
4683 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4684 ((bfd_arch_bits_per_address (stdoutput
) == 32
4685 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4687 "t,o(b)", PIC_CALL_REG
,
4688 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4691 p
= frag_var (rs_machine_dependent
, 4, 0,
4692 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4693 offset_expr
.X_add_symbol
, (offsetT
) 0,
4700 if (reg_needs_delay (GP
))
4704 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4705 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4707 ((bfd_arch_bits_per_address (stdoutput
) == 32
4708 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4709 ? "addu" : "daddu"),
4710 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4711 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4712 ((bfd_arch_bits_per_address (stdoutput
) == 32
4713 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4715 "t,o(b)", PIC_CALL_REG
,
4716 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4719 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4720 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4722 offset_expr
.X_add_symbol
, (offsetT
) 0,
4726 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4729 macro_build (p
, &icnt
, &offset_expr
,
4730 ((bfd_arch_bits_per_address (stdoutput
) == 32
4731 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4733 "t,o(b)", PIC_CALL_REG
,
4734 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4736 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4739 macro_build (p
, &icnt
, &offset_expr
,
4740 ((bfd_arch_bits_per_address (stdoutput
) == 32
4741 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4742 ? "addiu" : "daddiu"),
4743 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4744 (int) BFD_RELOC_LO16
);
4745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4746 "jalr", "s", PIC_CALL_REG
);
4747 if (mips_cprestore_offset
< 0)
4748 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4751 if (mips_opts
.noreorder
)
4752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4754 expr1
.X_add_number
= mips_cprestore_offset
;
4755 macro_build ((char *) NULL
, &icnt
, &expr1
,
4756 ((bfd_arch_bits_per_address (stdoutput
) == 32
4757 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4759 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4763 else if (mips_pic
== EMBEDDED_PIC
)
4765 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4766 /* The linker may expand the call to a longer sequence which
4767 uses $at, so we must break rather than return. */
4792 /* Itbl support may require additional care here. */
4797 /* Itbl support may require additional care here. */
4802 /* Itbl support may require additional care here. */
4807 /* Itbl support may require additional care here. */
4819 if (mips_cpu
== 4650)
4821 as_bad (_("opcode not supported on this processor"));
4825 /* Itbl support may require additional care here. */
4830 /* Itbl support may require additional care here. */
4835 /* Itbl support may require additional care here. */
4855 if (breg
== treg
|| coproc
|| lr
)
4877 /* Itbl support may require additional care here. */
4882 /* Itbl support may require additional care here. */
4887 /* Itbl support may require additional care here. */
4892 /* Itbl support may require additional care here. */
4908 if (mips_cpu
== 4650)
4910 as_bad (_("opcode not supported on this processor"));
4915 /* Itbl support may require additional care here. */
4919 /* Itbl support may require additional care here. */
4924 /* Itbl support may require additional care here. */
4936 /* Itbl support may require additional care here. */
4937 if (mask
== M_LWC1_AB
4938 || mask
== M_SWC1_AB
4939 || mask
== M_LDC1_AB
4940 || mask
== M_SDC1_AB
4949 if (offset_expr
.X_op
!= O_constant
4950 && offset_expr
.X_op
!= O_symbol
)
4952 as_bad (_("expression too complex"));
4953 offset_expr
.X_op
= O_constant
;
4956 /* A constant expression in PIC code can be handled just as it
4957 is in non PIC code. */
4958 if (mips_pic
== NO_PIC
4959 || offset_expr
.X_op
== O_constant
)
4961 /* If this is a reference to a GP relative symbol, and there
4962 is no base register, we want
4963 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4964 Otherwise, if there is no base register, we want
4965 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4966 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4967 If we have a constant, we need two instructions anyhow,
4968 so we always use the latter form.
4970 If we have a base register, and this is a reference to a
4971 GP relative symbol, we want
4972 addu $tempreg,$breg,$gp
4973 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4975 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4976 addu $tempreg,$tempreg,$breg
4977 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4978 With a constant we always use the latter case. */
4981 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4982 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4988 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4989 p
= frag_var (rs_machine_dependent
, 8, 0,
4990 RELAX_ENCODE (4, 8, 0, 4, 0,
4991 (mips_opts
.warn_about_macros
4993 && mips_opts
.noat
))),
4994 offset_expr
.X_add_symbol
, (offsetT
) 0,
4998 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5001 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5002 (int) BFD_RELOC_LO16
, tempreg
);
5006 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5007 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5012 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5013 ((bfd_arch_bits_per_address (stdoutput
) == 32
5014 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5015 ? "addu" : "daddu"),
5016 "d,v,t", tempreg
, breg
, GP
);
5017 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5018 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5019 p
= frag_var (rs_machine_dependent
, 12, 0,
5020 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5021 offset_expr
.X_add_symbol
, (offsetT
) 0,
5024 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5027 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5028 ((bfd_arch_bits_per_address (stdoutput
) == 32
5029 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5030 ? "addu" : "daddu"),
5031 "d,v,t", tempreg
, tempreg
, breg
);
5034 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5035 (int) BFD_RELOC_LO16
, tempreg
);
5038 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5040 /* If this is a reference to an external symbol, we want
5041 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5043 <op> $treg,0($tempreg)
5045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5047 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5048 <op> $treg,0($tempreg)
5049 If there is a base register, we add it to $tempreg before
5050 the <op>. If there is a constant, we stick it in the
5051 <op> instruction. We don't handle constants larger than
5052 16 bits, because we have no way to load the upper 16 bits
5053 (actually, we could handle them for the subset of cases
5054 in which we are not using $at). */
5055 assert (offset_expr
.X_op
== O_symbol
);
5056 expr1
.X_add_number
= offset_expr
.X_add_number
;
5057 offset_expr
.X_add_number
= 0;
5058 if (expr1
.X_add_number
< -0x8000
5059 || expr1
.X_add_number
>= 0x8000)
5060 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5062 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5063 ((bfd_arch_bits_per_address (stdoutput
) == 32
5064 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5066 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5068 p
= frag_var (rs_machine_dependent
, 4, 0,
5069 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5070 offset_expr
.X_add_symbol
, (offsetT
) 0,
5072 macro_build (p
, &icnt
, &offset_expr
,
5073 ((bfd_arch_bits_per_address (stdoutput
) == 32
5074 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5075 ? "addiu" : "daddiu"),
5076 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5079 ((bfd_arch_bits_per_address (stdoutput
) == 32
5080 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5081 ? "addu" : "daddu"),
5082 "d,v,t", tempreg
, tempreg
, breg
);
5083 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5084 (int) BFD_RELOC_LO16
, tempreg
);
5086 else if (mips_pic
== SVR4_PIC
)
5090 /* If this is a reference to an external symbol, we want
5091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5092 addu $tempreg,$tempreg,$gp
5093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5094 <op> $treg,0($tempreg)
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5098 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5099 <op> $treg,0($tempreg)
5100 If there is a base register, we add it to $tempreg before
5101 the <op>. If there is a constant, we stick it in the
5102 <op> instruction. We don't handle constants larger than
5103 16 bits, because we have no way to load the upper 16 bits
5104 (actually, we could handle them for the subset of cases
5105 in which we are not using $at). */
5106 assert (offset_expr
.X_op
== O_symbol
);
5107 expr1
.X_add_number
= offset_expr
.X_add_number
;
5108 offset_expr
.X_add_number
= 0;
5109 if (expr1
.X_add_number
< -0x8000
5110 || expr1
.X_add_number
>= 0x8000)
5111 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5112 if (reg_needs_delay (GP
))
5117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5118 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5120 ((bfd_arch_bits_per_address (stdoutput
) == 32
5121 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5122 ? "addu" : "daddu"),
5123 "d,v,t", tempreg
, tempreg
, GP
);
5124 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5125 ((bfd_arch_bits_per_address (stdoutput
) == 32
5126 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5128 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5130 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5131 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5132 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5135 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5138 macro_build (p
, &icnt
, &offset_expr
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5142 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5144 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5146 macro_build (p
, &icnt
, &offset_expr
,
5147 ((bfd_arch_bits_per_address (stdoutput
) == 32
5148 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5149 ? "addiu" : "daddiu"),
5150 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5152 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5153 ((bfd_arch_bits_per_address (stdoutput
) == 32
5154 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5155 ? "addu" : "daddu"),
5156 "d,v,t", tempreg
, tempreg
, breg
);
5157 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5158 (int) BFD_RELOC_LO16
, tempreg
);
5160 else if (mips_pic
== EMBEDDED_PIC
)
5162 /* If there is no base register, we want
5163 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5164 If there is a base register, we want
5165 addu $tempreg,$breg,$gp
5166 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5168 assert (offset_expr
.X_op
== O_symbol
);
5171 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5172 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5178 ((bfd_arch_bits_per_address (stdoutput
) == 32
5179 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5180 ? "addu" : "daddu"),
5181 "d,v,t", tempreg
, breg
, GP
);
5182 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5183 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5196 load_register (&icnt
, treg
, &imm_expr
, 0);
5200 load_register (&icnt
, treg
, &imm_expr
, 1);
5204 if (imm_expr
.X_op
== O_constant
)
5206 load_register (&icnt
, AT
, &imm_expr
, 0);
5207 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5208 "mtc1", "t,G", AT
, treg
);
5213 assert (offset_expr
.X_op
== O_symbol
5214 && strcmp (segment_name (S_GET_SEGMENT
5215 (offset_expr
.X_add_symbol
)),
5217 && offset_expr
.X_add_number
== 0);
5218 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5219 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5224 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5225 the entire value, and in mips1 mode it is the high order 32
5226 bits of the value and the low order 32 bits are either zero
5227 or in offset_expr. */
5228 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5230 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5231 load_register (&icnt
, treg
, &imm_expr
, 1);
5236 if (target_big_endian
)
5248 load_register (&icnt
, hreg
, &imm_expr
, 0);
5251 if (offset_expr
.X_op
== O_absent
)
5252 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5256 assert (offset_expr
.X_op
== O_constant
);
5257 load_register (&icnt
, lreg
, &offset_expr
, 0);
5264 /* We know that sym is in the .rdata section. First we get the
5265 upper 16 bits of the address. */
5266 if (mips_pic
== NO_PIC
)
5268 /* FIXME: This won't work for a 64 bit address. */
5269 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5271 else if (mips_pic
== SVR4_PIC
)
5273 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5274 ((bfd_arch_bits_per_address (stdoutput
) == 32
5275 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5277 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5279 else if (mips_pic
== EMBEDDED_PIC
)
5281 /* For embedded PIC we pick up the entire address off $gp in
5282 a single instruction. */
5283 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5284 ((bfd_arch_bits_per_address (stdoutput
) == 32
5285 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5286 ? "addiu" : "daddiu"),
5287 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5288 offset_expr
.X_op
= O_constant
;
5289 offset_expr
.X_add_number
= 0;
5294 /* Now we load the register(s). */
5295 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5297 treg
, (int) BFD_RELOC_LO16
, AT
);
5300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5301 treg
, (int) BFD_RELOC_LO16
, AT
);
5304 /* FIXME: How in the world do we deal with the possible
5306 offset_expr
.X_add_number
+= 4;
5307 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5308 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5312 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5313 does not become a variant frag. */
5314 frag_wane (frag_now
);
5320 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5321 the entire value, and in mips1 mode it is the high order 32
5322 bits of the value and the low order 32 bits are either zero
5323 or in offset_expr. */
5324 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5326 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5327 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5329 "dmtc1", "t,S", AT
, treg
);
5332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5333 "mtc1", "t,G", AT
, treg
+ 1);
5334 if (offset_expr
.X_op
== O_absent
)
5335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5336 "mtc1", "t,G", 0, treg
);
5339 assert (offset_expr
.X_op
== O_constant
);
5340 load_register (&icnt
, AT
, &offset_expr
, 0);
5341 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5342 "mtc1", "t,G", AT
, treg
);
5348 assert (offset_expr
.X_op
== O_symbol
5349 && offset_expr
.X_add_number
== 0);
5350 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5351 if (strcmp (s
, ".lit8") == 0)
5353 if (mips_opts
.isa
!= 1)
5355 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5356 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5360 r
= BFD_RELOC_MIPS_LITERAL
;
5365 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5366 if (mips_pic
== SVR4_PIC
)
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5368 ((bfd_arch_bits_per_address (stdoutput
) == 32
5369 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5371 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5374 /* FIXME: This won't work for a 64 bit address. */
5375 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5378 if (mips_opts
.isa
!= 1)
5380 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5381 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5383 /* To avoid confusion in tc_gen_reloc, we must ensure
5384 that this does not become a variant frag. */
5385 frag_wane (frag_now
);
5396 if (mips_cpu
== 4650)
5398 as_bad (_("opcode not supported on this processor"));
5401 /* Even on a big endian machine $fn comes before $fn+1. We have
5402 to adjust when loading from memory. */
5405 assert (mips_opts
.isa
== 1);
5406 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5407 target_big_endian
? treg
+ 1 : treg
,
5409 /* FIXME: A possible overflow which I don't know how to deal
5411 offset_expr
.X_add_number
+= 4;
5412 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5413 target_big_endian
? treg
: treg
+ 1,
5416 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5417 does not become a variant frag. */
5418 frag_wane (frag_now
);
5427 * The MIPS assembler seems to check for X_add_number not
5428 * being double aligned and generating:
5431 * addiu at,at,%lo(foo+1)
5434 * But, the resulting address is the same after relocation so why
5435 * generate the extra instruction?
5437 if (mips_cpu
== 4650)
5439 as_bad (_("opcode not supported on this processor"));
5442 /* Itbl support may require additional care here. */
5444 if (mips_opts
.isa
!= 1)
5455 if (mips_cpu
== 4650)
5457 as_bad (_("opcode not supported on this processor"));
5461 if (mips_opts
.isa
!= 1)
5469 /* Itbl support may require additional care here. */
5474 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5485 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5495 if (offset_expr
.X_op
!= O_symbol
5496 && offset_expr
.X_op
!= O_constant
)
5498 as_bad (_("expression too complex"));
5499 offset_expr
.X_op
= O_constant
;
5502 /* Even on a big endian machine $fn comes before $fn+1. We have
5503 to adjust when loading from memory. We set coproc if we must
5504 load $fn+1 first. */
5505 /* Itbl support may require additional care here. */
5506 if (! target_big_endian
)
5509 if (mips_pic
== NO_PIC
5510 || offset_expr
.X_op
== O_constant
)
5512 /* If this is a reference to a GP relative symbol, we want
5513 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5514 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5515 If we have a base register, we use this
5517 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5518 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5519 If this is not a GP relative symbol, we want
5520 lui $at,<sym> (BFD_RELOC_HI16_S)
5521 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5522 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5523 If there is a base register, we add it to $at after the
5524 lui instruction. If there is a constant, we always use
5526 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5527 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5546 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5547 ((bfd_arch_bits_per_address (stdoutput
) == 32
5548 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5549 ? "addu" : "daddu"),
5550 "d,v,t", AT
, breg
, GP
);
5556 /* Itbl support may require additional care here. */
5557 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5558 coproc
? treg
+ 1 : treg
,
5559 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5560 offset_expr
.X_add_number
+= 4;
5562 /* Set mips_optimize to 2 to avoid inserting an
5564 hold_mips_optimize
= mips_optimize
;
5566 /* Itbl support may require additional care here. */
5567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5568 coproc
? treg
: treg
+ 1,
5569 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5570 mips_optimize
= hold_mips_optimize
;
5572 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5573 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5574 used_at
&& mips_opts
.noat
),
5575 offset_expr
.X_add_symbol
, (offsetT
) 0,
5578 /* We just generated two relocs. When tc_gen_reloc
5579 handles this case, it will skip the first reloc and
5580 handle the second. The second reloc already has an
5581 extra addend of 4, which we added above. We must
5582 subtract it out, and then subtract another 4 to make
5583 the first reloc come out right. The second reloc
5584 will come out right because we are going to add 4 to
5585 offset_expr when we build its instruction below.
5587 If we have a symbol, then we don't want to include
5588 the offset, because it will wind up being included
5589 when we generate the reloc. */
5591 if (offset_expr
.X_op
== O_constant
)
5592 offset_expr
.X_add_number
-= 8;
5595 offset_expr
.X_add_number
= -4;
5596 offset_expr
.X_op
= O_constant
;
5599 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5604 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5605 ((bfd_arch_bits_per_address (stdoutput
) == 32
5606 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5607 ? "addu" : "daddu"),
5608 "d,v,t", AT
, breg
, AT
);
5612 /* Itbl support may require additional care here. */
5613 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5614 coproc
? treg
+ 1 : treg
,
5615 (int) BFD_RELOC_LO16
, AT
);
5618 /* FIXME: How do we handle overflow here? */
5619 offset_expr
.X_add_number
+= 4;
5620 /* Itbl support may require additional care here. */
5621 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5622 coproc
? treg
: treg
+ 1,
5623 (int) BFD_RELOC_LO16
, AT
);
5625 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5629 /* If this is a reference to an external symbol, we want
5630 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5635 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5637 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5638 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5639 If there is a base register we add it to $at before the
5640 lwc1 instructions. If there is a constant we include it
5641 in the lwc1 instructions. */
5643 expr1
.X_add_number
= offset_expr
.X_add_number
;
5644 offset_expr
.X_add_number
= 0;
5645 if (expr1
.X_add_number
< -0x8000
5646 || expr1
.X_add_number
>= 0x8000 - 4)
5647 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5652 frag_grow (24 + off
);
5653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5654 ((bfd_arch_bits_per_address (stdoutput
) == 32
5655 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5657 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5661 ((bfd_arch_bits_per_address (stdoutput
) == 32
5662 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5663 ? "addu" : "daddu"),
5664 "d,v,t", AT
, breg
, AT
);
5665 /* Itbl support may require additional care here. */
5666 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5667 coproc
? treg
+ 1 : treg
,
5668 (int) BFD_RELOC_LO16
, AT
);
5669 expr1
.X_add_number
+= 4;
5671 /* Set mips_optimize to 2 to avoid inserting an undesired
5673 hold_mips_optimize
= mips_optimize
;
5675 /* Itbl support may require additional care here. */
5676 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5677 coproc
? treg
: treg
+ 1,
5678 (int) BFD_RELOC_LO16
, AT
);
5679 mips_optimize
= hold_mips_optimize
;
5681 (void) frag_var (rs_machine_dependent
, 0, 0,
5682 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5683 offset_expr
.X_add_symbol
, (offsetT
) 0,
5686 else if (mips_pic
== SVR4_PIC
)
5690 /* If this is a reference to an external symbol, we want
5691 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5693 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5698 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5700 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5701 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5702 If there is a base register we add it to $at before the
5703 lwc1 instructions. If there is a constant we include it
5704 in the lwc1 instructions. */
5706 expr1
.X_add_number
= offset_expr
.X_add_number
;
5707 offset_expr
.X_add_number
= 0;
5708 if (expr1
.X_add_number
< -0x8000
5709 || expr1
.X_add_number
>= 0x8000 - 4)
5710 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5711 if (reg_needs_delay (GP
))
5720 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5721 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5723 ((bfd_arch_bits_per_address (stdoutput
) == 32
5724 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5725 ? "addu" : "daddu"),
5726 "d,v,t", AT
, AT
, GP
);
5727 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5728 ((bfd_arch_bits_per_address (stdoutput
) == 32
5729 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5731 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5732 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5735 ((bfd_arch_bits_per_address (stdoutput
) == 32
5736 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5737 ? "addu" : "daddu"),
5738 "d,v,t", AT
, breg
, AT
);
5739 /* Itbl support may require additional care here. */
5740 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5741 coproc
? treg
+ 1 : treg
,
5742 (int) BFD_RELOC_LO16
, AT
);
5743 expr1
.X_add_number
+= 4;
5745 /* Set mips_optimize to 2 to avoid inserting an undesired
5747 hold_mips_optimize
= mips_optimize
;
5749 /* Itbl support may require additional care here. */
5750 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5751 coproc
? treg
: treg
+ 1,
5752 (int) BFD_RELOC_LO16
, AT
);
5753 mips_optimize
= hold_mips_optimize
;
5754 expr1
.X_add_number
-= 4;
5756 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5757 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5758 8 + gpdel
+ off
, 1, 0),
5759 offset_expr
.X_add_symbol
, (offsetT
) 0,
5763 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5766 macro_build (p
, &icnt
, &offset_expr
,
5767 ((bfd_arch_bits_per_address (stdoutput
) == 32
5768 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5770 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5772 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5776 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5777 ((bfd_arch_bits_per_address (stdoutput
) == 32
5778 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5779 ? "addu" : "daddu"),
5780 "d,v,t", AT
, breg
, AT
);
5783 /* Itbl support may require additional care here. */
5784 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5785 coproc
? treg
+ 1 : treg
,
5786 (int) BFD_RELOC_LO16
, AT
);
5788 expr1
.X_add_number
+= 4;
5790 /* Set mips_optimize to 2 to avoid inserting an undesired
5792 hold_mips_optimize
= mips_optimize
;
5794 /* Itbl support may require additional care here. */
5795 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5796 coproc
? treg
: treg
+ 1,
5797 (int) BFD_RELOC_LO16
, AT
);
5798 mips_optimize
= hold_mips_optimize
;
5800 else if (mips_pic
== EMBEDDED_PIC
)
5802 /* If there is no base register, we use
5803 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5804 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5805 If we have a base register, we use
5807 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5808 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5817 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5818 ((bfd_arch_bits_per_address (stdoutput
) == 32
5819 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5820 ? "addu" : "daddu"),
5821 "d,v,t", AT
, breg
, GP
);
5826 /* Itbl support may require additional care here. */
5827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5828 coproc
? treg
+ 1 : treg
,
5829 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5830 offset_expr
.X_add_number
+= 4;
5831 /* Itbl support may require additional care here. */
5832 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5833 coproc
? treg
: treg
+ 1,
5834 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5850 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5851 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5852 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5853 (int) BFD_RELOC_LO16
, breg
);
5854 offset_expr
.X_add_number
+= 4;
5855 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5856 (int) BFD_RELOC_LO16
, breg
);
5859 /* New code added to support COPZ instructions.
5860 This code builds table entries out of the macros in mip_opcodes.
5861 R4000 uses interlocks to handle coproc delays.
5862 Other chips (like the R3000) require nops to be inserted for delays.
5864 FIXME: Currently, we require that the user handle delays.
5865 In order to fill delay slots for non-interlocked chips,
5866 we must have a way to specify delays based on the coprocessor.
5867 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5868 What are the side-effects of the cop instruction?
5869 What cache support might we have and what are its effects?
5870 Both coprocessor & memory require delays. how long???
5871 What registers are read/set/modified?
5873 If an itbl is provided to interpret cop instructions,
5874 this knowledge can be encoded in the itbl spec. */
5888 /* For now we just do C (same as Cz). The parameter will be
5889 stored in insn_opcode by mips_ip. */
5890 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5894 #ifdef LOSING_COMPILER
5896 /* Try and see if this is a new itbl instruction.
5897 This code builds table entries out of the macros in mip_opcodes.
5898 FIXME: For now we just assemble the expression and pass it's
5899 value along as a 32-bit immediate.
5900 We may want to have the assembler assemble this value,
5901 so that we gain the assembler's knowledge of delay slots,
5903 Would it be more efficient to use mask (id) here? */
5904 if (itbl_have_entries
5905 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5907 s
= ip
->insn_mo
->name
;
5909 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5910 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5917 as_warn (_("Macro used $at after \".set noat\""));
5922 struct mips_cl_insn
*ip
;
5924 register int treg
, sreg
, dreg
, breg
;
5940 bfd_reloc_code_real_type r
;
5943 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5944 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5945 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5946 mask
= ip
->insn_mo
->mask
;
5948 expr1
.X_op
= O_constant
;
5949 expr1
.X_op_symbol
= NULL
;
5950 expr1
.X_add_symbol
= NULL
;
5951 expr1
.X_add_number
= 1;
5955 #endif /* LOSING_COMPILER */
5960 macro_build ((char *) NULL
, &icnt
, NULL
,
5961 dbl
? "dmultu" : "multu",
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5969 /* The MIPS assembler some times generates shifts and adds. I'm
5970 not trying to be that fancy. GCC should do this for us
5972 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5973 macro_build ((char *) NULL
, &icnt
, NULL
,
5974 dbl
? "dmult" : "mult",
5976 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5989 mips_emit_delays (true);
5990 ++mips_opts
.noreorder
;
5991 mips_any_noreorder
= 1;
5993 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
,
5995 dbl
? "dmult" : "mult",
5996 "s,t", sreg
, imm
? AT
: treg
);
5997 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5998 macro_build ((char *) NULL
, &icnt
, NULL
,
5999 dbl
? "dsra32" : "sra",
6000 "d,w,<", dreg
, dreg
, 31);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6003 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6006 expr1
.X_add_number
= 8;
6007 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6008 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6011 --mips_opts
.noreorder
;
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6025 mips_emit_delays (true);
6026 ++mips_opts
.noreorder
;
6027 mips_any_noreorder
= 1;
6029 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6030 macro_build ((char *) NULL
, &icnt
, NULL
,
6031 dbl
? "dmultu" : "multu",
6032 "s,t", sreg
, imm
? AT
: treg
);
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6034 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6036 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6039 expr1
.X_add_number
= 8;
6040 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6041 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6042 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6044 --mips_opts
.noreorder
;
6048 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6049 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6050 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6052 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6056 if (imm_expr
.X_op
!= O_constant
)
6057 as_bad (_("rotate count too large"));
6058 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6059 (int) (imm_expr
.X_add_number
& 0x1f));
6060 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6061 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6068 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6074 if (imm_expr
.X_op
!= O_constant
)
6075 as_bad (_("rotate count too large"));
6076 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6077 (int) (imm_expr
.X_add_number
& 0x1f));
6078 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6079 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6080 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6084 if (mips_cpu
== 4650)
6086 as_bad (_("opcode not supported on this processor"));
6089 assert (mips_opts
.isa
== 1);
6090 /* Even on a big endian machine $fn comes before $fn+1. We have
6091 to adjust when storing to memory. */
6092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6093 target_big_endian
? treg
+ 1 : treg
,
6094 (int) BFD_RELOC_LO16
, breg
);
6095 offset_expr
.X_add_number
+= 4;
6096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6097 target_big_endian
? treg
: treg
+ 1,
6098 (int) BFD_RELOC_LO16
, breg
);
6103 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6104 treg
, (int) BFD_RELOC_LO16
);
6106 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6107 sreg
, (int) BFD_RELOC_LO16
);
6110 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6112 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6113 dreg
, (int) BFD_RELOC_LO16
);
6118 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6120 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6121 sreg
, (int) BFD_RELOC_LO16
);
6126 as_warn (_("Instruction %s: result is always false"),
6128 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6131 if (imm_expr
.X_op
== O_constant
6132 && imm_expr
.X_add_number
>= 0
6133 && imm_expr
.X_add_number
< 0x10000)
6135 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6136 sreg
, (int) BFD_RELOC_LO16
);
6139 else if (imm_expr
.X_op
== O_constant
6140 && imm_expr
.X_add_number
> -0x8000
6141 && imm_expr
.X_add_number
< 0)
6143 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6144 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6145 ((bfd_arch_bits_per_address (stdoutput
) == 32
6146 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6147 ? "addiu" : "daddiu"),
6148 "t,r,j", dreg
, sreg
,
6149 (int) BFD_RELOC_LO16
);
6154 load_register (&icnt
, AT
, &imm_expr
, 0);
6155 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6159 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6160 (int) BFD_RELOC_LO16
);
6165 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6171 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6172 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6173 (int) BFD_RELOC_LO16
);
6176 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6178 if (imm_expr
.X_op
== O_constant
6179 && imm_expr
.X_add_number
>= -0x8000
6180 && imm_expr
.X_add_number
< 0x8000)
6182 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6183 mask
== M_SGE_I
? "slti" : "sltiu",
6184 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6189 load_register (&icnt
, AT
, &imm_expr
, 0);
6190 macro_build ((char *) NULL
, &icnt
, NULL
,
6191 mask
== M_SGE_I
? "slt" : "sltu",
6192 "d,v,t", dreg
, sreg
, AT
);
6195 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6196 (int) BFD_RELOC_LO16
);
6201 case M_SGT
: /* sreg > treg <==> treg < sreg */
6207 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6210 case M_SGT_I
: /* sreg > I <==> I < sreg */
6216 load_register (&icnt
, AT
, &imm_expr
, 0);
6217 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6220 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6226 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6227 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6228 (int) BFD_RELOC_LO16
);
6231 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6237 load_register (&icnt
, AT
, &imm_expr
, 0);
6238 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6239 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6240 (int) BFD_RELOC_LO16
);
6244 if (imm_expr
.X_op
== O_constant
6245 && imm_expr
.X_add_number
>= -0x8000
6246 && imm_expr
.X_add_number
< 0x8000)
6248 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6249 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6252 load_register (&icnt
, AT
, &imm_expr
, 0);
6253 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6257 if (imm_expr
.X_op
== O_constant
6258 && imm_expr
.X_add_number
>= -0x8000
6259 && imm_expr
.X_add_number
< 0x8000)
6261 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6262 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6265 load_register (&icnt
, AT
, &imm_expr
, 0);
6266 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6272 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6275 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6279 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6281 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6287 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6289 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6295 as_warn (_("Instruction %s: result is always true"),
6297 macro_build ((char *) NULL
, &icnt
, &expr1
,
6298 ((bfd_arch_bits_per_address (stdoutput
) == 32
6299 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6300 ? "addiu" : "daddiu"),
6301 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6304 if (imm_expr
.X_op
== O_constant
6305 && imm_expr
.X_add_number
>= 0
6306 && imm_expr
.X_add_number
< 0x10000)
6308 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6309 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6312 else if (imm_expr
.X_op
== O_constant
6313 && imm_expr
.X_add_number
> -0x8000
6314 && imm_expr
.X_add_number
< 0)
6316 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6317 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6318 ((bfd_arch_bits_per_address (stdoutput
) == 32
6319 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6320 ? "addiu" : "daddiu"),
6321 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6326 load_register (&icnt
, AT
, &imm_expr
, 0);
6327 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6331 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6339 if (imm_expr
.X_op
== O_constant
6340 && imm_expr
.X_add_number
> -0x8000
6341 && imm_expr
.X_add_number
<= 0x8000)
6343 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6344 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6345 dbl
? "daddi" : "addi",
6346 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6349 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6350 macro_build ((char *) NULL
, &icnt
, NULL
,
6351 dbl
? "dsub" : "sub",
6352 "d,v,t", dreg
, sreg
, AT
);
6358 if (imm_expr
.X_op
== O_constant
6359 && imm_expr
.X_add_number
> -0x8000
6360 && imm_expr
.X_add_number
<= 0x8000)
6362 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6363 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6364 dbl
? "daddiu" : "addiu",
6365 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6368 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6369 macro_build ((char *) NULL
, &icnt
, NULL
,
6370 dbl
? "dsubu" : "subu",
6371 "d,v,t", dreg
, sreg
, AT
);
6392 load_register (&icnt
, AT
, &imm_expr
, 0);
6393 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6398 assert (mips_opts
.isa
== 1);
6399 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6400 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6403 * Is the double cfc1 instruction a bug in the mips assembler;
6404 * or is there a reason for it?
6406 mips_emit_delays (true);
6407 ++mips_opts
.noreorder
;
6408 mips_any_noreorder
= 1;
6409 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6410 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6411 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6412 expr1
.X_add_number
= 3;
6413 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6414 (int) BFD_RELOC_LO16
);
6415 expr1
.X_add_number
= 2;
6416 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6417 (int) BFD_RELOC_LO16
);
6418 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6419 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6420 macro_build ((char *) NULL
, &icnt
, NULL
,
6421 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6422 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6423 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6424 --mips_opts
.noreorder
;
6433 if (offset_expr
.X_add_number
>= 0x7fff)
6434 as_bad (_("operand overflow"));
6435 /* avoid load delay */
6436 if (! target_big_endian
)
6437 offset_expr
.X_add_number
+= 1;
6438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6439 (int) BFD_RELOC_LO16
, breg
);
6440 if (! target_big_endian
)
6441 offset_expr
.X_add_number
-= 1;
6443 offset_expr
.X_add_number
+= 1;
6444 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6445 (int) BFD_RELOC_LO16
, breg
);
6446 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6447 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6460 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6461 as_bad (_("operand overflow"));
6462 if (! target_big_endian
)
6463 offset_expr
.X_add_number
+= off
;
6464 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6465 (int) BFD_RELOC_LO16
, breg
);
6466 if (! target_big_endian
)
6467 offset_expr
.X_add_number
-= off
;
6469 offset_expr
.X_add_number
+= off
;
6470 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6471 (int) BFD_RELOC_LO16
, breg
);
6484 load_address (&icnt
, AT
, &offset_expr
);
6486 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6487 ((bfd_arch_bits_per_address (stdoutput
) == 32
6488 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6489 ? "addu" : "daddu"),
6490 "d,v,t", AT
, AT
, breg
);
6491 if (! target_big_endian
)
6492 expr1
.X_add_number
= off
;
6494 expr1
.X_add_number
= 0;
6495 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6496 (int) BFD_RELOC_LO16
, AT
);
6497 if (! target_big_endian
)
6498 expr1
.X_add_number
= 0;
6500 expr1
.X_add_number
= off
;
6501 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6502 (int) BFD_RELOC_LO16
, AT
);
6507 load_address (&icnt
, AT
, &offset_expr
);
6509 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6510 ((bfd_arch_bits_per_address (stdoutput
) == 32
6511 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6512 ? "addu" : "daddu"),
6513 "d,v,t", AT
, AT
, breg
);
6514 if (target_big_endian
)
6515 expr1
.X_add_number
= 0;
6516 macro_build ((char *) NULL
, &icnt
, &expr1
,
6517 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6518 (int) BFD_RELOC_LO16
, AT
);
6519 if (target_big_endian
)
6520 expr1
.X_add_number
= 1;
6522 expr1
.X_add_number
= 0;
6523 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6524 (int) BFD_RELOC_LO16
, AT
);
6525 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6527 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6532 if (offset_expr
.X_add_number
>= 0x7fff)
6533 as_bad (_("operand overflow"));
6534 if (target_big_endian
)
6535 offset_expr
.X_add_number
+= 1;
6536 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6537 (int) BFD_RELOC_LO16
, breg
);
6538 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6539 if (target_big_endian
)
6540 offset_expr
.X_add_number
-= 1;
6542 offset_expr
.X_add_number
+= 1;
6543 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6544 (int) BFD_RELOC_LO16
, breg
);
6557 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6558 as_bad (_("operand overflow"));
6559 if (! target_big_endian
)
6560 offset_expr
.X_add_number
+= off
;
6561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6562 (int) BFD_RELOC_LO16
, breg
);
6563 if (! target_big_endian
)
6564 offset_expr
.X_add_number
-= off
;
6566 offset_expr
.X_add_number
+= off
;
6567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6568 (int) BFD_RELOC_LO16
, breg
);
6581 load_address (&icnt
, AT
, &offset_expr
);
6583 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6584 ((bfd_arch_bits_per_address (stdoutput
) == 32
6585 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6586 ? "addu" : "daddu"),
6587 "d,v,t", AT
, AT
, breg
);
6588 if (! target_big_endian
)
6589 expr1
.X_add_number
= off
;
6591 expr1
.X_add_number
= 0;
6592 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6593 (int) BFD_RELOC_LO16
, AT
);
6594 if (! target_big_endian
)
6595 expr1
.X_add_number
= 0;
6597 expr1
.X_add_number
= off
;
6598 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6599 (int) BFD_RELOC_LO16
, AT
);
6603 load_address (&icnt
, AT
, &offset_expr
);
6605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6606 ((bfd_arch_bits_per_address (stdoutput
) == 32
6607 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6608 ? "addu" : "daddu"),
6609 "d,v,t", AT
, AT
, breg
);
6610 if (! target_big_endian
)
6611 expr1
.X_add_number
= 0;
6612 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6613 (int) BFD_RELOC_LO16
, AT
);
6614 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6616 if (! target_big_endian
)
6617 expr1
.X_add_number
= 1;
6619 expr1
.X_add_number
= 0;
6620 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6621 (int) BFD_RELOC_LO16
, AT
);
6622 if (! target_big_endian
)
6623 expr1
.X_add_number
= 0;
6625 expr1
.X_add_number
= 1;
6626 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6627 (int) BFD_RELOC_LO16
, AT
);
6628 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6630 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6635 /* FIXME: Check if this is one of the itbl macros, since they
6636 are added dynamically. */
6637 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6641 as_warn (_("Macro used $at after \".set noat\""));
6644 /* Implement macros in mips16 mode. */
6648 struct mips_cl_insn
*ip
;
6651 int xreg
, yreg
, zreg
, tmp
;
6655 const char *s
, *s2
, *s3
;
6657 mask
= ip
->insn_mo
->mask
;
6659 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6660 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6661 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6665 expr1
.X_op
= O_constant
;
6666 expr1
.X_op_symbol
= NULL
;
6667 expr1
.X_add_symbol
= NULL
;
6668 expr1
.X_add_number
= 1;
6687 mips_emit_delays (true);
6688 ++mips_opts
.noreorder
;
6689 mips_any_noreorder
= 1;
6690 macro_build ((char *) NULL
, &icnt
, NULL
,
6691 dbl
? "ddiv" : "div",
6692 "0,x,y", xreg
, yreg
);
6693 expr1
.X_add_number
= 2;
6694 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6695 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6697 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6698 since that causes an overflow. We should do that as well,
6699 but I don't see how to do the comparisons without a temporary
6701 --mips_opts
.noreorder
;
6702 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6721 mips_emit_delays (true);
6722 ++mips_opts
.noreorder
;
6723 mips_any_noreorder
= 1;
6724 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6725 expr1
.X_add_number
= 2;
6726 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6727 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6728 --mips_opts
.noreorder
;
6729 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6735 macro_build ((char *) NULL
, &icnt
, NULL
,
6736 dbl
? "dmultu" : "multu",
6738 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6746 if (imm_expr
.X_op
!= O_constant
)
6747 as_bad (_("Unsupported large constant"));
6748 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6749 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6750 dbl
? "daddiu" : "addiu",
6751 "y,x,4", yreg
, xreg
);
6755 if (imm_expr
.X_op
!= O_constant
)
6756 as_bad (_("Unsupported large constant"));
6757 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6758 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6763 if (imm_expr
.X_op
!= O_constant
)
6764 as_bad (_("Unsupported large constant"));
6765 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6766 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6789 goto do_reverse_branch
;
6793 goto do_reverse_branch
;
6805 goto do_reverse_branch
;
6816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6845 goto do_addone_branch_i
;
6850 goto do_addone_branch_i
;
6865 goto do_addone_branch_i
;
6872 if (imm_expr
.X_op
!= O_constant
)
6873 as_bad (_("Unsupported large constant"));
6874 ++imm_expr
.X_add_number
;
6877 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6878 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6882 expr1
.X_add_number
= 0;
6883 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6886 "move", "y,X", xreg
, yreg
);
6887 expr1
.X_add_number
= 2;
6888 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6890 "neg", "x,w", xreg
, xreg
);
6894 /* For consistency checking, verify that all bits are specified either
6895 by the match/mask part of the instruction definition, or by the
6898 validate_mips_insn (opc
)
6899 const struct mips_opcode
*opc
;
6901 const char *p
= opc
->args
;
6903 unsigned long used_bits
= opc
->mask
;
6905 if ((used_bits
& opc
->match
) != opc
->match
)
6907 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6908 opc
->name
, opc
->args
);
6911 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6918 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6919 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6921 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6922 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6923 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6924 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6926 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6929 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6930 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6931 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6932 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6933 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6934 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6935 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6936 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6937 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6938 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6939 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6941 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6942 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6943 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6944 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6946 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6947 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6948 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6949 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6950 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6951 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6952 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6953 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6954 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6957 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6959 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6960 c
, opc
->name
, opc
->args
);
6964 if (used_bits
!= 0xffffffff)
6966 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6967 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6973 /* This routine assembles an instruction into its binary format. As a
6974 side effect, it sets one of the global variables imm_reloc or
6975 offset_reloc to the type of relocation to do if one of the operands
6976 is an address expression. */
6981 struct mips_cl_insn
*ip
;
6986 struct mips_opcode
*insn
;
6989 unsigned int lastregno
= 0;
6992 int full_opcode_match
= 1;
6996 /* If the instruction contains a '.', we first try to match an instruction
6997 including the '.'. Then we try again without the '.'. */
6999 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7002 /* If we stopped on whitespace, then replace the whitespace with null for
7003 the call to hash_find. Save the character we replaced just in case we
7004 have to re-parse the instruction. */
7005 if (isspace ((unsigned char) *s
))
7011 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7013 /* If we didn't find the instruction in the opcode table, try again, but
7014 this time with just the instruction up to, but not including the
7018 /* Restore the character we overwrite above (if any). */
7022 /* Scan up to the first '.' or whitespace. */
7023 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7026 /* If we did not find a '.', then we can quit now. */
7029 insn_error
= "unrecognized opcode";
7033 /* Lookup the instruction in the hash table. */
7035 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7037 insn_error
= "unrecognized opcode";
7041 full_opcode_match
= 0;
7049 assert (strcmp (insn
->name
, str
) == 0);
7051 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
))
7056 if (insn
->pinfo
!= INSN_MACRO
)
7058 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7064 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7065 && strcmp (insn
->name
, insn
[1].name
) == 0)
7072 static char buf
[100];
7074 _("opcode not supported on this processor: %d (MIPS%d)"),
7075 mips_cpu
, mips_opts
.isa
);
7083 ip
->insn_opcode
= insn
->match
;
7084 for (args
= insn
->args
;; ++args
)
7090 case '\0': /* end of args */
7103 ip
->insn_opcode
|= lastregno
<< 21;
7108 ip
->insn_opcode
|= lastregno
<< 16;
7112 ip
->insn_opcode
|= lastregno
<< 11;
7118 /* Handle optional base register.
7119 Either the base register is omitted or
7120 we must have a left paren. */
7121 /* This is dependent on the next operand specifier
7122 is a base register specification. */
7123 assert (args
[1] == 'b' || args
[1] == '5'
7124 || args
[1] == '-' || args
[1] == '4');
7128 case ')': /* these must match exactly */
7133 case '<': /* must be at least one digit */
7135 * According to the manual, if the shift amount is greater
7136 * than 31 or less than 0 the the shift amount should be
7137 * mod 32. In reality the mips assembler issues an error.
7138 * We issue a warning and mask out all but the low 5 bits.
7140 my_getExpression (&imm_expr
, s
);
7141 check_absolute_expr (ip
, &imm_expr
);
7142 if ((unsigned long) imm_expr
.X_add_number
> 31)
7144 as_warn (_("Improper shift amount (%ld)"),
7145 (long) imm_expr
.X_add_number
);
7146 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7148 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7149 imm_expr
.X_op
= O_absent
;
7153 case '>': /* shift amount minus 32 */
7154 my_getExpression (&imm_expr
, s
);
7155 check_absolute_expr (ip
, &imm_expr
);
7156 if ((unsigned long) imm_expr
.X_add_number
< 32
7157 || (unsigned long) imm_expr
.X_add_number
> 63)
7159 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7160 imm_expr
.X_op
= O_absent
;
7165 case 'k': /* cache code */
7166 case 'h': /* prefx code */
7167 my_getExpression (&imm_expr
, s
);
7168 check_absolute_expr (ip
, &imm_expr
);
7169 if ((unsigned long) imm_expr
.X_add_number
> 31)
7171 as_warn (_("Invalid value for `%s' (%lu)"),
7173 (unsigned long) imm_expr
.X_add_number
);
7174 imm_expr
.X_add_number
&= 0x1f;
7177 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7179 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7180 imm_expr
.X_op
= O_absent
;
7184 case 'c': /* break code */
7185 my_getExpression (&imm_expr
, s
);
7186 check_absolute_expr (ip
, &imm_expr
);
7187 if ((unsigned) imm_expr
.X_add_number
> 1023)
7189 as_warn (_("Illegal break code (%ld)"),
7190 (long) imm_expr
.X_add_number
);
7191 imm_expr
.X_add_number
&= 0x3ff;
7193 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7194 imm_expr
.X_op
= O_absent
;
7198 case 'q': /* lower break code */
7199 my_getExpression (&imm_expr
, s
);
7200 check_absolute_expr (ip
, &imm_expr
);
7201 if ((unsigned) imm_expr
.X_add_number
> 1023)
7203 as_warn (_("Illegal lower break code (%ld)"),
7204 (long) imm_expr
.X_add_number
);
7205 imm_expr
.X_add_number
&= 0x3ff;
7207 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7208 imm_expr
.X_op
= O_absent
;
7212 case 'B': /* syscall code */
7213 my_getExpression (&imm_expr
, s
);
7214 check_absolute_expr (ip
, &imm_expr
);
7215 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7216 as_warn (_("Illegal syscall code (%ld)"),
7217 (long) imm_expr
.X_add_number
);
7218 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7219 imm_expr
.X_op
= O_absent
;
7223 case 'C': /* Coprocessor code */
7224 my_getExpression (&imm_expr
, s
);
7225 check_absolute_expr (ip
, &imm_expr
);
7226 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7228 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7229 (long) imm_expr
.X_add_number
);
7230 imm_expr
.X_add_number
&= ((1<<25) - 1);
7232 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7233 imm_expr
.X_op
= O_absent
;
7237 case 'P': /* Performance register */
7238 my_getExpression (&imm_expr
, s
);
7239 check_absolute_expr (ip
, &imm_expr
);
7240 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7242 as_warn (_("Invalidate performance regster (%ld)"),
7243 (long) imm_expr
.X_add_number
);
7244 imm_expr
.X_add_number
&= 1;
7246 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7247 imm_expr
.X_op
= O_absent
;
7251 case 'b': /* base register */
7252 case 'd': /* destination register */
7253 case 's': /* source register */
7254 case 't': /* target register */
7255 case 'r': /* both target and source */
7256 case 'v': /* both dest and source */
7257 case 'w': /* both dest and target */
7258 case 'E': /* coprocessor target register */
7259 case 'G': /* coprocessor destination register */
7260 case 'x': /* ignore register name */
7261 case 'z': /* must be zero register */
7266 if (isdigit ((unsigned char) s
[1]))
7276 while (isdigit ((unsigned char) *s
));
7278 as_bad (_("Invalid register number (%d)"), regno
);
7280 else if (*args
== 'E' || *args
== 'G')
7284 if (s
[1] == 'f' && s
[2] == 'p')
7289 else if (s
[1] == 's' && s
[2] == 'p')
7294 else if (s
[1] == 'g' && s
[2] == 'p')
7299 else if (s
[1] == 'a' && s
[2] == 't')
7304 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7309 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7314 else if (itbl_have_entries
)
7319 p
= s
+ 1; /* advance past '$' */
7320 n
= itbl_get_field (&p
); /* n is name */
7322 /* See if this is a register defined in an
7324 if (itbl_get_reg_val (n
, &r
))
7326 /* Get_field advances to the start of
7327 the next field, so we need to back
7328 rack to the end of the last field. */
7332 s
= strchr (s
, '\0');
7345 as_warn (_("Used $at without \".set noat\""));
7351 if (c
== 'r' || c
== 'v' || c
== 'w')
7358 /* 'z' only matches $0. */
7359 if (c
== 'z' && regno
!= 0)
7362 /* Now that we have assembled one operand, we use the args string
7363 * to figure out where it goes in the instruction. */
7370 ip
->insn_opcode
|= regno
<< 21;
7374 ip
->insn_opcode
|= regno
<< 11;
7379 ip
->insn_opcode
|= regno
<< 16;
7382 /* This case exists because on the r3000 trunc
7383 expands into a macro which requires a gp
7384 register. On the r6000 or r4000 it is
7385 assembled into a single instruction which
7386 ignores the register. Thus the insn version
7387 is MIPS_ISA2 and uses 'x', and the macro
7388 version is MIPS_ISA1 and uses 't'. */
7391 /* This case is for the div instruction, which
7392 acts differently if the destination argument
7393 is $0. This only matches $0, and is checked
7394 outside the switch. */
7397 /* Itbl operand; not yet implemented. FIXME ?? */
7399 /* What about all other operands like 'i', which
7400 can be specified in the opcode table? */
7410 ip
->insn_opcode
|= lastregno
<< 21;
7413 ip
->insn_opcode
|= lastregno
<< 16;
7418 case 'D': /* floating point destination register */
7419 case 'S': /* floating point source register */
7420 case 'T': /* floating point target register */
7421 case 'R': /* floating point source register */
7425 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7435 while (isdigit ((unsigned char) *s
));
7438 as_bad (_("Invalid float register number (%d)"), regno
);
7440 if ((regno
& 1) != 0
7441 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7442 && ! (strcmp (str
, "mtc1") == 0
7443 || strcmp (str
, "mfc1") == 0
7444 || strcmp (str
, "lwc1") == 0
7445 || strcmp (str
, "swc1") == 0
7446 || strcmp (str
, "l.s") == 0
7447 || strcmp (str
, "s.s") == 0))
7448 as_warn (_("Float register should be even, was %d"),
7456 if (c
== 'V' || c
== 'W')
7466 ip
->insn_opcode
|= regno
<< 6;
7470 ip
->insn_opcode
|= regno
<< 11;
7474 ip
->insn_opcode
|= regno
<< 16;
7477 ip
->insn_opcode
|= regno
<< 21;
7488 ip
->insn_opcode
|= lastregno
<< 11;
7491 ip
->insn_opcode
|= lastregno
<< 16;
7497 my_getExpression (&imm_expr
, s
);
7498 if (imm_expr
.X_op
!= O_big
7499 && imm_expr
.X_op
!= O_constant
)
7500 insn_error
= _("absolute expression required");
7505 my_getExpression (&offset_expr
, s
);
7506 imm_reloc
= BFD_RELOC_32
;
7518 unsigned char temp
[8];
7520 unsigned int length
;
7525 /* These only appear as the last operand in an
7526 instruction, and every instruction that accepts
7527 them in any variant accepts them in all variants.
7528 This means we don't have to worry about backing out
7529 any changes if the instruction does not match.
7531 The difference between them is the size of the
7532 floating point constant and where it goes. For 'F'
7533 and 'L' the constant is 64 bits; for 'f' and 'l' it
7534 is 32 bits. Where the constant is placed is based
7535 on how the MIPS assembler does things:
7538 f -- immediate value
7541 The .lit4 and .lit8 sections are only used if
7542 permitted by the -G argument.
7544 When generating embedded PIC code, we use the
7545 .lit8 section but not the .lit4 section (we can do
7546 .lit4 inline easily; we need to put .lit8
7547 somewhere in the data segment, and using .lit8
7548 permits the linker to eventually combine identical
7551 f64
= *args
== 'F' || *args
== 'L';
7553 save_in
= input_line_pointer
;
7554 input_line_pointer
= s
;
7555 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7557 s
= input_line_pointer
;
7558 input_line_pointer
= save_in
;
7559 if (err
!= NULL
&& *err
!= '\0')
7561 as_bad (_("Bad floating point constant: %s"), err
);
7562 memset (temp
, '\0', sizeof temp
);
7563 length
= f64
? 8 : 4;
7566 assert (length
== (f64
? 8 : 4));
7570 && (! USE_GLOBAL_POINTER_OPT
7571 || mips_pic
== EMBEDDED_PIC
7572 || g_switch_value
< 4
7573 || (temp
[0] == 0 && temp
[1] == 0)
7574 || (temp
[2] == 0 && temp
[3] == 0))))
7576 imm_expr
.X_op
= O_constant
;
7577 if (! target_big_endian
)
7578 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7580 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7583 && ((temp
[0] == 0 && temp
[1] == 0)
7584 || (temp
[2] == 0 && temp
[3] == 0))
7585 && ((temp
[4] == 0 && temp
[5] == 0)
7586 || (temp
[6] == 0 && temp
[7] == 0)))
7588 /* The value is simple enough to load with a
7589 couple of instructions. In mips1 mode, set
7590 imm_expr to the high order 32 bits and
7591 offset_expr to the low order 32 bits.
7592 Otherwise, set imm_expr to the entire 64 bit
7594 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7596 imm_expr
.X_op
= O_constant
;
7597 offset_expr
.X_op
= O_constant
;
7598 if (! target_big_endian
)
7600 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7601 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7605 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7606 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7608 if (offset_expr
.X_add_number
== 0)
7609 offset_expr
.X_op
= O_absent
;
7611 else if (sizeof (imm_expr
.X_add_number
) > 4)
7613 imm_expr
.X_op
= O_constant
;
7614 if (! target_big_endian
)
7615 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7617 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7621 imm_expr
.X_op
= O_big
;
7622 imm_expr
.X_add_number
= 4;
7623 if (! target_big_endian
)
7625 generic_bignum
[0] = bfd_getl16 (temp
);
7626 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7627 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7628 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7632 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7633 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7634 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7635 generic_bignum
[3] = bfd_getb16 (temp
);
7641 const char *newname
;
7644 /* Switch to the right section. */
7646 subseg
= now_subseg
;
7649 default: /* unused default case avoids warnings. */
7651 newname
= RDATA_SECTION_NAME
;
7652 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7656 newname
= RDATA_SECTION_NAME
;
7659 assert (!USE_GLOBAL_POINTER_OPT
7660 || g_switch_value
>= 4);
7664 new_seg
= subseg_new (newname
, (subsegT
) 0);
7665 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7666 bfd_set_section_flags (stdoutput
, new_seg
,
7671 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7672 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7673 && strcmp (TARGET_OS
, "elf") != 0)
7674 record_alignment (new_seg
, 4);
7676 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7678 as_bad (_("Can't use floating point insn in this section"));
7680 /* Set the argument to the current address in the
7682 offset_expr
.X_op
= O_symbol
;
7683 offset_expr
.X_add_symbol
=
7684 symbol_new ("L0\001", now_seg
,
7685 (valueT
) frag_now_fix (), frag_now
);
7686 offset_expr
.X_add_number
= 0;
7688 /* Put the floating point number into the section. */
7689 p
= frag_more ((int) length
);
7690 memcpy (p
, temp
, length
);
7692 /* Switch back to the original section. */
7693 subseg_set (seg
, subseg
);
7698 case 'i': /* 16 bit unsigned immediate */
7699 case 'j': /* 16 bit signed immediate */
7700 imm_reloc
= BFD_RELOC_LO16
;
7701 c
= my_getSmallExpression (&imm_expr
, s
);
7706 if (imm_expr
.X_op
== O_constant
)
7707 imm_expr
.X_add_number
=
7708 (imm_expr
.X_add_number
>> 16) & 0xffff;
7711 imm_reloc
= BFD_RELOC_HI16_S
;
7712 imm_unmatched_hi
= true;
7715 imm_reloc
= BFD_RELOC_HI16
;
7717 else if (imm_expr
.X_op
== O_constant
)
7718 imm_expr
.X_add_number
&= 0xffff;
7722 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7723 || ((imm_expr
.X_add_number
< 0
7724 || imm_expr
.X_add_number
>= 0x10000)
7725 && imm_expr
.X_op
== O_constant
))
7727 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7728 !strcmp (insn
->name
, insn
[1].name
))
7730 if (imm_expr
.X_op
!= O_constant
7731 && imm_expr
.X_op
!= O_big
)
7732 insn_error
= _("absolute expression required");
7734 as_bad (_("16 bit expression not in range 0..65535"));
7742 /* The upper bound should be 0x8000, but
7743 unfortunately the MIPS assembler accepts numbers
7744 from 0x8000 to 0xffff and sign extends them, and
7745 we want to be compatible. We only permit this
7746 extended range for an instruction which does not
7747 provide any further alternates, since those
7748 alternates may handle other cases. People should
7749 use the numbers they mean, rather than relying on
7750 a mysterious sign extension. */
7751 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7752 strcmp (insn
->name
, insn
[1].name
) == 0);
7757 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7758 || ((imm_expr
.X_add_number
< -0x8000
7759 || imm_expr
.X_add_number
>= max
)
7760 && imm_expr
.X_op
== O_constant
)
7762 && imm_expr
.X_add_number
< 0
7763 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7764 && imm_expr
.X_unsigned
7765 && sizeof (imm_expr
.X_add_number
) <= 4))
7769 if (imm_expr
.X_op
!= O_constant
7770 && imm_expr
.X_op
!= O_big
)
7771 insn_error
= _("absolute expression required");
7773 as_bad (_("16 bit expression not in range -32768..32767"));
7779 case 'o': /* 16 bit offset */
7780 c
= my_getSmallExpression (&offset_expr
, s
);
7782 /* If this value won't fit into a 16 bit offset, then go
7783 find a macro that will generate the 32 bit offset
7784 code pattern. As a special hack, we accept the
7785 difference of two local symbols as a constant. This
7786 is required to suppose embedded PIC switches, which
7787 use an instruction which looks like
7788 lw $4,$L12-$LS12($4)
7789 The problem with handling this in a more general
7790 fashion is that the macro function doesn't expect to
7791 see anything which can be handled in a single
7792 constant instruction. */
7794 && (offset_expr
.X_op
!= O_constant
7795 || offset_expr
.X_add_number
>= 0x8000
7796 || offset_expr
.X_add_number
< -0x8000)
7797 && (mips_pic
!= EMBEDDED_PIC
7798 || offset_expr
.X_op
!= O_subtract
7799 || now_seg
!= text_section
7800 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7804 if (c
== 'h' || c
== 'H')
7806 if (offset_expr
.X_op
!= O_constant
)
7808 offset_expr
.X_add_number
=
7809 (offset_expr
.X_add_number
>> 16) & 0xffff;
7811 offset_reloc
= BFD_RELOC_LO16
;
7815 case 'p': /* pc relative offset */
7816 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7817 my_getExpression (&offset_expr
, s
);
7821 case 'u': /* upper 16 bits */
7822 c
= my_getSmallExpression (&imm_expr
, s
);
7823 imm_reloc
= BFD_RELOC_LO16
;
7828 if (imm_expr
.X_op
== O_constant
)
7829 imm_expr
.X_add_number
=
7830 (imm_expr
.X_add_number
>> 16) & 0xffff;
7833 imm_reloc
= BFD_RELOC_HI16_S
;
7834 imm_unmatched_hi
= true;
7837 imm_reloc
= BFD_RELOC_HI16
;
7839 else if (imm_expr
.X_op
== O_constant
)
7840 imm_expr
.X_add_number
&= 0xffff;
7842 if (imm_expr
.X_op
== O_constant
7843 && (imm_expr
.X_add_number
< 0
7844 || imm_expr
.X_add_number
>= 0x10000))
7845 as_bad (_("lui expression not in range 0..65535"));
7849 case 'a': /* 26 bit address */
7850 my_getExpression (&offset_expr
, s
);
7852 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7855 case 'N': /* 3 bit branch condition code */
7856 case 'M': /* 3 bit compare condition code */
7857 if (strncmp (s
, "$fcc", 4) != 0)
7867 while (isdigit ((unsigned char) *s
));
7869 as_bad (_("invalid condition code register $fcc%d"), regno
);
7871 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7873 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7877 as_bad (_("bad char = '%c'\n"), *args
);
7882 /* Args don't match. */
7883 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7884 !strcmp (insn
->name
, insn
[1].name
))
7890 insn_error
= _("illegal operands");
7895 /* This routine assembles an instruction into its binary format when
7896 assembling for the mips16. As a side effect, it sets one of the
7897 global variables imm_reloc or offset_reloc to the type of
7898 relocation to do if one of the operands is an address expression.
7899 It also sets mips16_small and mips16_ext if the user explicitly
7900 requested a small or extended instruction. */
7905 struct mips_cl_insn
*ip
;
7909 struct mips_opcode
*insn
;
7912 unsigned int lastregno
= 0;
7917 mips16_small
= false;
7920 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7932 if (s
[1] == 't' && s
[2] == ' ')
7935 mips16_small
= true;
7939 else if (s
[1] == 'e' && s
[2] == ' ')
7948 insn_error
= _("unknown opcode");
7952 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7953 mips16_small
= true;
7955 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7957 insn_error
= _("unrecognized opcode");
7964 assert (strcmp (insn
->name
, str
) == 0);
7967 ip
->insn_opcode
= insn
->match
;
7968 ip
->use_extend
= false;
7969 imm_expr
.X_op
= O_absent
;
7970 imm_reloc
= BFD_RELOC_UNUSED
;
7971 offset_expr
.X_op
= O_absent
;
7972 offset_reloc
= BFD_RELOC_UNUSED
;
7973 for (args
= insn
->args
; 1; ++args
)
7980 /* In this switch statement we call break if we did not find
7981 a match, continue if we did find a match, or return if we
7990 /* Stuff the immediate value in now, if we can. */
7991 if (imm_expr
.X_op
== O_constant
7992 && imm_reloc
> BFD_RELOC_UNUSED
7993 && insn
->pinfo
!= INSN_MACRO
)
7995 mips16_immed ((char *) NULL
, 0,
7996 imm_reloc
- BFD_RELOC_UNUSED
,
7997 imm_expr
.X_add_number
, true, mips16_small
,
7998 mips16_ext
, &ip
->insn_opcode
,
7999 &ip
->use_extend
, &ip
->extend
);
8000 imm_expr
.X_op
= O_absent
;
8001 imm_reloc
= BFD_RELOC_UNUSED
;
8015 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8018 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8034 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8036 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8053 if (isdigit ((unsigned char) s
[1]))
8063 while (isdigit ((unsigned char) *s
));
8066 as_bad (_("invalid register number (%d)"), regno
);
8072 if (s
[1] == 'f' && s
[2] == 'p')
8077 else if (s
[1] == 's' && s
[2] == 'p')
8082 else if (s
[1] == 'g' && s
[2] == 'p')
8087 else if (s
[1] == 'a' && s
[2] == 't')
8092 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8097 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8110 if (c
== 'v' || c
== 'w')
8112 regno
= mips16_to_32_reg_map
[lastregno
];
8126 regno
= mips32_to_16_reg_map
[regno
];
8131 regno
= ILLEGAL_REG
;
8136 regno
= ILLEGAL_REG
;
8141 regno
= ILLEGAL_REG
;
8146 if (regno
== AT
&& ! mips_opts
.noat
)
8147 as_warn (_("used $at without \".set noat\""));
8154 if (regno
== ILLEGAL_REG
)
8161 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8165 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8168 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8171 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8177 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8180 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8181 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8191 if (strncmp (s
, "$pc", 3) == 0)
8215 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8217 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8218 and generate the appropriate reloc. If the text
8219 inside %gprel is not a symbol name with an
8220 optional offset, then we generate a normal reloc
8221 and will probably fail later. */
8222 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8223 if (imm_expr
.X_op
== O_symbol
)
8226 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8228 ip
->use_extend
= true;
8235 /* Just pick up a normal expression. */
8236 my_getExpression (&imm_expr
, s
);
8239 if (imm_expr
.X_op
== O_register
)
8241 /* What we thought was an expression turned out to
8244 if (s
[0] == '(' && args
[1] == '(')
8246 /* It looks like the expression was omitted
8247 before a register indirection, which means
8248 that the expression is implicitly zero. We
8249 still set up imm_expr, so that we handle
8250 explicit extensions correctly. */
8251 imm_expr
.X_op
= O_constant
;
8252 imm_expr
.X_add_number
= 0;
8253 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8260 /* We need to relax this instruction. */
8261 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8270 /* We use offset_reloc rather than imm_reloc for the PC
8271 relative operands. This lets macros with both
8272 immediate and address operands work correctly. */
8273 my_getExpression (&offset_expr
, s
);
8275 if (offset_expr
.X_op
== O_register
)
8278 /* We need to relax this instruction. */
8279 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8283 case '6': /* break code */
8284 my_getExpression (&imm_expr
, s
);
8285 check_absolute_expr (ip
, &imm_expr
);
8286 if ((unsigned long) imm_expr
.X_add_number
> 63)
8288 as_warn (_("Invalid value for `%s' (%lu)"),
8290 (unsigned long) imm_expr
.X_add_number
);
8291 imm_expr
.X_add_number
&= 0x3f;
8293 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8294 imm_expr
.X_op
= O_absent
;
8298 case 'a': /* 26 bit address */
8299 my_getExpression (&offset_expr
, s
);
8301 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8302 ip
->insn_opcode
<<= 16;
8305 case 'l': /* register list for entry macro */
8306 case 'L': /* register list for exit macro */
8316 int freg
, reg1
, reg2
;
8318 while (*s
== ' ' || *s
== ',')
8322 as_bad (_("can't parse register list"));
8334 while (isdigit ((unsigned char) *s
))
8356 as_bad (_("invalid register list"));
8361 while (isdigit ((unsigned char) *s
))
8368 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8373 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8378 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8379 mask
|= (reg2
- 3) << 3;
8380 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8381 mask
|= (reg2
- 15) << 1;
8382 else if (reg1
== 31 && reg2
== 31)
8386 as_bad (_("invalid register list"));
8390 /* The mask is filled in in the opcode table for the
8391 benefit of the disassembler. We remove it before
8392 applying the actual mask. */
8393 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8394 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8398 case 'e': /* extend code */
8399 my_getExpression (&imm_expr
, s
);
8400 check_absolute_expr (ip
, &imm_expr
);
8401 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8403 as_warn (_("Invalid value for `%s' (%lu)"),
8405 (unsigned long) imm_expr
.X_add_number
);
8406 imm_expr
.X_add_number
&= 0x7ff;
8408 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8409 imm_expr
.X_op
= O_absent
;
8419 /* Args don't match. */
8420 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8421 strcmp (insn
->name
, insn
[1].name
) == 0)
8428 insn_error
= _("illegal operands");
8434 /* This structure holds information we know about a mips16 immediate
8437 struct mips16_immed_operand
8439 /* The type code used in the argument string in the opcode table. */
8441 /* The number of bits in the short form of the opcode. */
8443 /* The number of bits in the extended form of the opcode. */
8445 /* The amount by which the short form is shifted when it is used;
8446 for example, the sw instruction has a shift count of 2. */
8448 /* The amount by which the short form is shifted when it is stored
8449 into the instruction code. */
8451 /* Non-zero if the short form is unsigned. */
8453 /* Non-zero if the extended form is unsigned. */
8455 /* Non-zero if the value is PC relative. */
8459 /* The mips16 immediate operand types. */
8461 static const struct mips16_immed_operand mips16_immed_operands
[] =
8463 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8464 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8465 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8466 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8467 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8468 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8469 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8470 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8471 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8472 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8473 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8474 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8475 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8476 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8477 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8478 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8479 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8480 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8481 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8482 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8483 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8486 #define MIPS16_NUM_IMMED \
8487 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8489 /* Handle a mips16 instruction with an immediate value. This or's the
8490 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8491 whether an extended value is needed; if one is needed, it sets
8492 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8493 If SMALL is true, an unextended opcode was explicitly requested.
8494 If EXT is true, an extended opcode was explicitly requested. If
8495 WARN is true, warn if EXT does not match reality. */
8498 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8507 unsigned long *insn
;
8508 boolean
*use_extend
;
8509 unsigned short *extend
;
8511 register const struct mips16_immed_operand
*op
;
8512 int mintiny
, maxtiny
;
8515 op
= mips16_immed_operands
;
8516 while (op
->type
!= type
)
8519 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8524 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8527 maxtiny
= 1 << op
->nbits
;
8532 maxtiny
= (1 << op
->nbits
) - 1;
8537 mintiny
= - (1 << (op
->nbits
- 1));
8538 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8541 /* Branch offsets have an implicit 0 in the lowest bit. */
8542 if (type
== 'p' || type
== 'q')
8545 if ((val
& ((1 << op
->shift
) - 1)) != 0
8546 || val
< (mintiny
<< op
->shift
)
8547 || val
> (maxtiny
<< op
->shift
))
8552 if (warn
&& ext
&& ! needext
)
8553 as_warn_where (file
, line
, _("extended operand requested but not required"));
8554 if (small
&& needext
)
8555 as_bad_where (file
, line
, _("invalid unextended operand value"));
8557 if (small
|| (! ext
&& ! needext
))
8561 *use_extend
= false;
8562 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8563 insnval
<<= op
->op_shift
;
8568 long minext
, maxext
;
8574 maxext
= (1 << op
->extbits
) - 1;
8578 minext
= - (1 << (op
->extbits
- 1));
8579 maxext
= (1 << (op
->extbits
- 1)) - 1;
8581 if (val
< minext
|| val
> maxext
)
8582 as_bad_where (file
, line
,
8583 _("operand value out of range for instruction"));
8586 if (op
->extbits
== 16)
8588 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8591 else if (op
->extbits
== 15)
8593 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8598 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8602 *extend
= (unsigned short) extval
;
8611 my_getSmallExpression (ep
, str
)
8622 ((str
[1] == 'h' && str
[2] == 'i')
8623 || (str
[1] == 'H' && str
[2] == 'I')
8624 || (str
[1] == 'l' && str
[2] == 'o'))
8636 * A small expression may be followed by a base register.
8637 * Scan to the end of this operand, and then back over a possible
8638 * base register. Then scan the small expression up to that
8639 * point. (Based on code in sparc.c...)
8641 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8643 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8645 if (isdigit ((unsigned char) sp
[-2]))
8647 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8649 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8655 else if (sp
- 5 >= str
8658 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8659 || (sp
[-3] == 's' && sp
[-2] == 'p')
8660 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8661 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8667 /* no expression means zero offset */
8670 /* %xx(reg) is an error */
8671 ep
->X_op
= O_absent
;
8676 ep
->X_op
= O_constant
;
8679 ep
->X_add_symbol
= NULL
;
8680 ep
->X_op_symbol
= NULL
;
8681 ep
->X_add_number
= 0;
8686 my_getExpression (ep
, str
);
8693 my_getExpression (ep
, str
);
8694 return c
; /* => %hi or %lo encountered */
8698 my_getExpression (ep
, str
)
8704 save_in
= input_line_pointer
;
8705 input_line_pointer
= str
;
8707 expr_end
= input_line_pointer
;
8708 input_line_pointer
= save_in
;
8710 /* If we are in mips16 mode, and this is an expression based on `.',
8711 then we bump the value of the symbol by 1 since that is how other
8712 text symbols are handled. We don't bother to handle complex
8713 expressions, just `.' plus or minus a constant. */
8714 if (mips_opts
.mips16
8715 && ep
->X_op
== O_symbol
8716 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8717 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8718 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8719 && symbol_constant_p (ep
->X_add_symbol
)
8720 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8721 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8724 /* Turn a string in input_line_pointer into a floating point constant
8725 of type type, and store the appropriate bytes in *litP. The number
8726 of LITTLENUMS emitted is stored in *sizeP . An error message is
8727 returned, or NULL on OK. */
8730 md_atof (type
, litP
, sizeP
)
8736 LITTLENUM_TYPE words
[4];
8752 return _("bad call to md_atof");
8755 t
= atof_ieee (input_line_pointer
, type
, words
);
8757 input_line_pointer
= t
;
8761 if (! target_big_endian
)
8763 for (i
= prec
- 1; i
>= 0; i
--)
8765 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8771 for (i
= 0; i
< prec
; i
++)
8773 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8782 md_number_to_chars (buf
, val
, n
)
8787 if (target_big_endian
)
8788 number_to_chars_bigendian (buf
, val
, n
);
8790 number_to_chars_littleendian (buf
, val
, n
);
8793 CONST
char *md_shortopts
= "O::g::G:";
8795 struct option md_longopts
[] = {
8796 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8797 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8798 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8799 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8800 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8801 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8802 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8803 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8804 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8805 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8806 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8807 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8808 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8809 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8810 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8811 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8812 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8813 {"break", no_argument
, NULL
, OPTION_BREAK
},
8814 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8815 #define OPTION_EB (OPTION_MD_BASE + 11)
8816 {"EB", no_argument
, NULL
, OPTION_EB
},
8817 #define OPTION_EL (OPTION_MD_BASE + 12)
8818 {"EL", no_argument
, NULL
, OPTION_EL
},
8819 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8820 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8821 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8822 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8823 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8824 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8825 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8826 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8827 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8828 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8829 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8830 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8831 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8832 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8833 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8834 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8835 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8836 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8837 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8838 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8841 #define OPTION_MABI (OPTION_MD_BASE + 38)
8842 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8844 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8845 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8846 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8847 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8849 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8850 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8851 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8852 #define OPTION_32 (OPTION_MD_BASE + 20)
8853 #define OPTION_64 (OPTION_MD_BASE + 21)
8855 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8856 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8857 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8858 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8859 {"32", no_argument
, NULL
, OPTION_32
},
8860 {"64", no_argument
, NULL
, OPTION_64
},
8863 {NULL
, no_argument
, NULL
, 0}
8865 size_t md_longopts_size
= sizeof(md_longopts
);
8868 md_parse_option (c
, arg
)
8883 target_big_endian
= 1;
8887 target_big_endian
= 0;
8891 if (arg
&& arg
[1] == '0')
8901 mips_debug
= atoi (arg
);
8902 /* When the MIPS assembler sees -g or -g2, it does not do
8903 optimizations which limit full symbolic debugging. We take
8904 that to be equivalent to -O0. */
8905 if (mips_debug
== 2)
8929 /* Identify the processor type */
8931 if (strcmp (p
, "default") == 0
8932 || strcmp (p
, "DEFAULT") == 0)
8938 /* We need to cope with the various "vr" prefixes for the 4300
8940 if (*p
== 'v' || *p
== 'V')
8946 if (*p
== 'r' || *p
== 'R')
8953 if (strcmp (p
, "10000") == 0
8954 || strcmp (p
, "10k") == 0
8955 || strcmp (p
, "10K") == 0)
8960 if (strcmp (p
, "2000") == 0
8961 || strcmp (p
, "2k") == 0
8962 || strcmp (p
, "2K") == 0)
8967 if (strcmp (p
, "3000") == 0
8968 || strcmp (p
, "3k") == 0
8969 || strcmp (p
, "3K") == 0)
8971 else if (strcmp (p
, "3900") == 0)
8976 if (strcmp (p
, "4000") == 0
8977 || strcmp (p
, "4k") == 0
8978 || strcmp (p
, "4K") == 0)
8980 else if (strcmp (p
, "4100") == 0)
8982 else if (strcmp (p
, "4111") == 0)
8984 else if (strcmp (p
, "4300") == 0)
8986 else if (strcmp (p
, "4400") == 0)
8988 else if (strcmp (p
, "4600") == 0)
8990 else if (strcmp (p
, "4650") == 0)
8992 else if (strcmp (p
, "4010") == 0)
8997 if (strcmp (p
, "5000") == 0
8998 || strcmp (p
, "5k") == 0
8999 || strcmp (p
, "5K") == 0)
9004 if (strcmp (p
, "6000") == 0
9005 || strcmp (p
, "6k") == 0
9006 || strcmp (p
, "6K") == 0)
9011 if (strcmp (p
, "8000") == 0
9012 || strcmp (p
, "8k") == 0
9013 || strcmp (p
, "8K") == 0)
9018 if (strcmp (p
, "orion") == 0)
9024 && (mips_cpu
!= 4300
9027 && mips_cpu
!= 5000))
9029 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9035 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9046 case OPTION_NO_M4650
:
9053 case OPTION_NO_M4010
:
9060 case OPTION_NO_M4100
:
9068 case OPTION_NO_M3900
:
9072 mips_opts
.mips16
= 1;
9073 mips_no_prev_insn (false);
9076 case OPTION_NO_MIPS16
:
9077 mips_opts
.mips16
= 0;
9078 mips_no_prev_insn (false);
9081 case OPTION_MEMBEDDED_PIC
:
9082 mips_pic
= EMBEDDED_PIC
;
9083 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9085 as_bad (_("-G may not be used with embedded PIC code"));
9088 g_switch_value
= 0x7fffffff;
9091 /* When generating ELF code, we permit -KPIC and -call_shared to
9092 select SVR4_PIC, and -non_shared to select no PIC. This is
9093 intended to be compatible with Irix 5. */
9094 case OPTION_CALL_SHARED
:
9095 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9097 as_bad (_("-call_shared is supported only for ELF format"));
9100 mips_pic
= SVR4_PIC
;
9101 if (g_switch_seen
&& g_switch_value
!= 0)
9103 as_bad (_("-G may not be used with SVR4 PIC code"));
9109 case OPTION_NON_SHARED
:
9110 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9112 as_bad (_("-non_shared is supported only for ELF format"));
9118 /* The -xgot option tells the assembler to use 32 offsets when
9119 accessing the got in SVR4_PIC mode. It is for Irix
9126 if (! USE_GLOBAL_POINTER_OPT
)
9128 as_bad (_("-G is not supported for this configuration"));
9131 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9133 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9137 g_switch_value
= atoi (arg
);
9141 /* The -32 and -64 options tell the assembler to output the 32
9142 bit or the 64 bit MIPS ELF format. */
9149 const char **list
, **l
;
9151 list
= bfd_target_list ();
9152 for (l
= list
; *l
!= NULL
; l
++)
9153 if (strcmp (*l
, "elf64-bigmips") == 0
9154 || strcmp (*l
, "elf64-littlemips") == 0)
9157 as_fatal (_("No compiled in support for 64 bit object file format"));
9165 if (strcmp (arg
,"32") == 0
9166 || strcmp (arg
,"n32") == 0
9167 || strcmp (arg
,"64") == 0
9168 || strcmp (arg
,"o64") == 0
9169 || strcmp (arg
,"eabi") == 0)
9170 mips_abi_string
= arg
;
9173 case OPTION_M7000_HILO_FIX
:
9174 mips_7000_hilo_fix
= true;
9177 case OPTION_NO_M7000_HILO_FIX
:
9178 mips_7000_hilo_fix
= false;
9190 show (stream
, string
, col_p
, first_p
)
9198 fprintf (stream
, "%24s", "");
9203 fprintf (stream
, ", ");
9207 if (*col_p
+ strlen (string
) > 72)
9209 fprintf (stream
, "\n%24s", "");
9213 fprintf (stream
, "%s", string
);
9214 *col_p
+= strlen (string
);
9221 md_show_usage (stream
)
9226 fprintf(stream
, _("\
9228 -membedded-pic generate embedded position independent code\n\
9229 -EB generate big endian output\n\
9230 -EL generate little endian output\n\
9231 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9232 -G NUM allow referencing objects up to NUM bytes\n\
9233 implicitly with the gp register [default 8]\n"));
9234 fprintf(stream
, _("\
9235 -mips1 generate MIPS ISA I instructions\n\
9236 -mips2 generate MIPS ISA II instructions\n\
9237 -mips3 generate MIPS ISA III instructions\n\
9238 -mips4 generate MIPS ISA IV instructions\n\
9239 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9243 show (stream
, "2000", &column
, &first
);
9244 show (stream
, "3000", &column
, &first
);
9245 show (stream
, "3900", &column
, &first
);
9246 show (stream
, "4000", &column
, &first
);
9247 show (stream
, "4010", &column
, &first
);
9248 show (stream
, "4100", &column
, &first
);
9249 show (stream
, "4111", &column
, &first
);
9250 show (stream
, "4300", &column
, &first
);
9251 show (stream
, "4400", &column
, &first
);
9252 show (stream
, "4600", &column
, &first
);
9253 show (stream
, "4650", &column
, &first
);
9254 show (stream
, "5000", &column
, &first
);
9255 show (stream
, "6000", &column
, &first
);
9256 show (stream
, "8000", &column
, &first
);
9257 show (stream
, "10000", &column
, &first
);
9258 fputc ('\n', stream
);
9260 fprintf (stream
, _("\
9261 -mCPU equivalent to -mcpu=CPU.\n\
9262 -no-mCPU don't generate code specific to CPU.\n\
9263 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9267 show (stream
, "3900", &column
, &first
);
9268 show (stream
, "4010", &column
, &first
);
9269 show (stream
, "4100", &column
, &first
);
9270 show (stream
, "4650", &column
, &first
);
9271 fputc ('\n', stream
);
9273 fprintf(stream
, _("\
9274 -mips16 generate mips16 instructions\n\
9275 -no-mips16 do not generate mips16 instructions\n"));
9276 fprintf(stream
, _("\
9277 -O0 remove unneeded NOPs, do not swap branches\n\
9278 -O remove unneeded NOPs and swap branches\n\
9279 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9280 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9282 fprintf(stream
, _("\
9283 -KPIC, -call_shared generate SVR4 position independent code\n\
9284 -non_shared do not generate position independent code\n\
9285 -xgot assume a 32 bit GOT\n\
9286 -32 create 32 bit object file (default)\n\
9287 -64 create 64 bit object file\n"));
9292 mips_init_after_args ()
9294 /* initialize opcodes */
9295 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9296 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9300 md_pcrel_from (fixP
)
9303 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9304 && fixP
->fx_addsy
!= (symbolS
*) NULL
9305 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9307 /* This makes a branch to an undefined symbol be a branch to the
9308 current location. */
9312 /* return the address of the delay slot */
9313 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9316 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9317 reloc for a cons. We could use the definition there, except that
9318 we want to handle 64 bit relocs specially. */
9321 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9324 unsigned int nbytes
;
9328 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9330 if (nbytes
== 8 && ! mips_64
)
9332 if (target_big_endian
)
9338 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9339 as_bad (_("Unsupported reloc size %d"), nbytes
);
9341 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9344 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9347 /* This is called before the symbol table is processed. In order to
9348 work with gcc when using mips-tfile, we must keep all local labels.
9349 However, in other cases, we want to discard them. If we were
9350 called with -g, but we didn't see any debugging information, it may
9351 mean that gcc is smuggling debugging information through to
9352 mips-tfile, in which case we must generate all local labels. */
9355 mips_frob_file_before_adjust ()
9357 #ifndef NO_ECOFF_DEBUGGING
9360 && ! ecoff_debugging_seen
)
9361 flag_keep_locals
= 1;
9365 /* Sort any unmatched HI16_S relocs so that they immediately precede
9366 the corresponding LO reloc. This is called before md_apply_fix and
9367 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9368 explicit use of the %hi modifier. */
9373 struct mips_hi_fixup
*l
;
9375 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9377 segment_info_type
*seginfo
;
9380 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9382 /* Check quickly whether the next fixup happens to be a matching
9384 if (l
->fixp
->fx_next
!= NULL
9385 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9386 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9387 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9390 /* Look through the fixups for this segment for a matching %lo.
9391 When we find one, move the %hi just in front of it. We do
9392 this in two passes. In the first pass, we try to find a
9393 unique %lo. In the second pass, we permit multiple %hi
9394 relocs for a single %lo (this is a GNU extension). */
9395 seginfo
= seg_info (l
->seg
);
9396 for (pass
= 0; pass
< 2; pass
++)
9401 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9403 /* Check whether this is a %lo fixup which matches l->fixp. */
9404 if (f
->fx_r_type
== BFD_RELOC_LO16
9405 && f
->fx_addsy
== l
->fixp
->fx_addsy
9406 && f
->fx_offset
== l
->fixp
->fx_offset
9409 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9410 || prev
->fx_addsy
!= f
->fx_addsy
9411 || prev
->fx_offset
!= f
->fx_offset
))
9415 /* Move l->fixp before f. */
9416 for (pf
= &seginfo
->fix_root
;
9418 pf
= &(*pf
)->fx_next
)
9419 assert (*pf
!= NULL
);
9421 *pf
= l
->fixp
->fx_next
;
9423 l
->fixp
->fx_next
= f
;
9425 seginfo
->fix_root
= l
->fixp
;
9427 prev
->fx_next
= l
->fixp
;
9438 #if 0 /* GCC code motion plus incomplete dead code elimination
9439 can leave a %hi without a %lo. */
9441 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9442 _("Unmatched %%hi reloc"));
9448 /* When generating embedded PIC code we need to use a special
9449 relocation to represent the difference of two symbols in the .text
9450 section (switch tables use a difference of this sort). See
9451 include/coff/mips.h for details. This macro checks whether this
9452 fixup requires the special reloc. */
9453 #define SWITCH_TABLE(fixp) \
9454 ((fixp)->fx_r_type == BFD_RELOC_32 \
9455 && (fixp)->fx_addsy != NULL \
9456 && (fixp)->fx_subsy != NULL \
9457 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9458 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9460 /* When generating embedded PIC code we must keep all PC relative
9461 relocations, in case the linker has to relax a call. We also need
9462 to keep relocations for switch table entries. */
9466 mips_force_relocation (fixp
)
9469 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9470 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9473 return (mips_pic
== EMBEDDED_PIC
9475 || SWITCH_TABLE (fixp
)
9476 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9477 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9480 /* Apply a fixup to the object file. */
9483 md_apply_fix (fixP
, valueP
)
9490 assert (fixP
->fx_size
== 4
9491 || fixP
->fx_r_type
== BFD_RELOC_16
9492 || fixP
->fx_r_type
== BFD_RELOC_64
9493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9498 /* If we aren't adjusting this fixup to be against the section
9499 symbol, we need to adjust the value. */
9501 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9502 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9503 || S_IS_WEAK (fixP
->fx_addsy
)
9504 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9505 && (((bfd_get_section_flags (stdoutput
,
9506 S_GET_SEGMENT (fixP
->fx_addsy
))
9507 & SEC_LINK_ONCE
) != 0)
9508 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9510 sizeof (".gnu.linkonce") - 1))))
9513 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9514 if (value
!= 0 && ! fixP
->fx_pcrel
)
9516 /* In this case, the bfd_install_relocation routine will
9517 incorrectly add the symbol value back in. We just want
9518 the addend to appear in the object file. */
9519 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9525 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9527 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9530 switch (fixP
->fx_r_type
)
9532 case BFD_RELOC_MIPS_JMP
:
9533 case BFD_RELOC_HI16
:
9534 case BFD_RELOC_HI16_S
:
9535 case BFD_RELOC_MIPS_GPREL
:
9536 case BFD_RELOC_MIPS_LITERAL
:
9537 case BFD_RELOC_MIPS_CALL16
:
9538 case BFD_RELOC_MIPS_GOT16
:
9539 case BFD_RELOC_MIPS_GPREL32
:
9540 case BFD_RELOC_MIPS_GOT_HI16
:
9541 case BFD_RELOC_MIPS_GOT_LO16
:
9542 case BFD_RELOC_MIPS_CALL_HI16
:
9543 case BFD_RELOC_MIPS_CALL_LO16
:
9544 case BFD_RELOC_MIPS16_GPREL
:
9546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9547 _("Invalid PC relative reloc"));
9548 /* Nothing needed to do. The value comes from the reloc entry */
9551 case BFD_RELOC_MIPS16_JMP
:
9552 /* We currently always generate a reloc against a symbol, which
9553 means that we don't want an addend even if the symbol is
9555 fixP
->fx_addnumber
= 0;
9558 case BFD_RELOC_PCREL_HI16_S
:
9559 /* The addend for this is tricky if it is internal, so we just
9560 do everything here rather than in bfd_install_relocation. */
9561 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9563 /* For an external symbol adjust by the address to make it
9564 pcrel_offset. We use the address of the RELLO reloc
9565 which follows this one. */
9566 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9567 + fixP
->fx_next
->fx_where
);
9572 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9573 if (target_big_endian
)
9575 md_number_to_chars (buf
, value
, 2);
9578 case BFD_RELOC_PCREL_LO16
:
9579 /* The addend for this is tricky if it is internal, so we just
9580 do everything here rather than in bfd_install_relocation. */
9581 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9582 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9583 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9584 if (target_big_endian
)
9586 md_number_to_chars (buf
, value
, 2);
9590 /* This is handled like BFD_RELOC_32, but we output a sign
9591 extended value if we are only 32 bits. */
9593 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9595 if (8 <= sizeof (valueT
))
9596 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9603 w1
= w2
= fixP
->fx_where
;
9604 if (target_big_endian
)
9608 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9609 if ((value
& 0x80000000) != 0)
9613 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9619 /* If we are deleting this reloc entry, we must fill in the
9620 value now. This can happen if we have a .word which is not
9621 resolved when it appears but is later defined. We also need
9622 to fill in the value if this is an embedded PIC switch table
9625 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9626 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9631 /* If we are deleting this reloc entry, we must fill in the
9633 assert (fixP
->fx_size
== 2);
9635 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9639 case BFD_RELOC_LO16
:
9640 /* When handling an embedded PIC switch statement, we can wind
9641 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9644 if (value
< -0x8000 || value
> 0x7fff)
9645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9646 _("relocation overflow"));
9647 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9648 if (target_big_endian
)
9650 md_number_to_chars (buf
, value
, 2);
9654 case BFD_RELOC_16_PCREL_S2
:
9656 * We need to save the bits in the instruction since fixup_segment()
9657 * might be deleting the relocation entry (i.e., a branch within
9658 * the current segment).
9660 if ((value
& 0x3) != 0)
9661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9662 _("Branch to odd address (%lx)"), value
);
9665 /* update old instruction data */
9666 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9667 if (target_big_endian
)
9668 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9670 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9672 if (value
>= -0x8000 && value
< 0x8000)
9673 insn
|= value
& 0xffff;
9676 /* The branch offset is too large. If this is an
9677 unconditional branch, and we are not generating PIC code,
9678 we can convert it to an absolute jump instruction. */
9679 if (mips_pic
== NO_PIC
9681 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9682 && (fixP
->fx_frag
->fr_address
9683 < text_section
->vma
+ text_section
->_raw_size
)
9684 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9685 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9686 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9688 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9689 insn
= 0x0c000000; /* jal */
9691 insn
= 0x08000000; /* j */
9692 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9694 fixP
->fx_addsy
= section_symbol (text_section
);
9695 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9699 /* FIXME. It would be possible in principle to handle
9700 conditional branches which overflow. They could be
9701 transformed into a branch around a jump. This would
9702 require setting up variant frags for each different
9703 branch type. The native MIPS assembler attempts to
9704 handle these cases, but it appears to do it
9706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9707 _("Branch out of range"));
9711 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9714 case BFD_RELOC_VTABLE_INHERIT
:
9717 && !S_IS_DEFINED (fixP
->fx_addsy
)
9718 && !S_IS_WEAK (fixP
->fx_addsy
))
9719 S_SET_WEAK (fixP
->fx_addsy
);
9722 case BFD_RELOC_VTABLE_ENTRY
:
9738 const struct mips_opcode
*p
;
9739 int treg
, sreg
, dreg
, shamt
;
9744 for (i
= 0; i
< NUMOPCODES
; ++i
)
9746 p
= &mips_opcodes
[i
];
9747 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9749 printf ("%08lx %s\t", oc
, p
->name
);
9750 treg
= (oc
>> 16) & 0x1f;
9751 sreg
= (oc
>> 21) & 0x1f;
9752 dreg
= (oc
>> 11) & 0x1f;
9753 shamt
= (oc
>> 6) & 0x1f;
9755 for (args
= p
->args
;; ++args
)
9766 printf ("%c", *args
);
9770 assert (treg
== sreg
);
9771 printf ("$%d,$%d", treg
, sreg
);
9776 printf ("$%d", dreg
);
9781 printf ("$%d", treg
);
9785 printf ("0x%x", treg
);
9790 printf ("$%d", sreg
);
9794 printf ("0x%08lx", oc
& 0x1ffffff);
9806 printf ("$%d", shamt
);
9817 printf (_("%08lx UNDEFINED\n"), oc
);
9828 name
= input_line_pointer
;
9829 c
= get_symbol_end ();
9830 p
= (symbolS
*) symbol_find_or_make (name
);
9831 *input_line_pointer
= c
;
9835 /* Align the current frag to a given power of two. The MIPS assembler
9836 also automatically adjusts any preceding label. */
9839 mips_align (to
, fill
, label
)
9844 mips_emit_delays (false);
9845 frag_align (to
, fill
, 0);
9846 record_alignment (now_seg
, to
);
9849 assert (S_GET_SEGMENT (label
) == now_seg
);
9850 symbol_set_frag (label
, frag_now
);
9851 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9855 /* Align to a given power of two. .align 0 turns off the automatic
9856 alignment used by the data creating pseudo-ops. */
9863 register long temp_fill
;
9864 long max_alignment
= 15;
9868 o Note that the assembler pulls down any immediately preceeding label
9869 to the aligned address.
9870 o It's not documented but auto alignment is reinstated by
9871 a .align pseudo instruction.
9872 o Note also that after auto alignment is turned off the mips assembler
9873 issues an error on attempt to assemble an improperly aligned data item.
9878 temp
= get_absolute_expression ();
9879 if (temp
> max_alignment
)
9880 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9883 as_warn (_("Alignment negative: 0 assumed."));
9886 if (*input_line_pointer
== ',')
9888 input_line_pointer
++;
9889 temp_fill
= get_absolute_expression ();
9896 mips_align (temp
, (int) temp_fill
,
9897 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9904 demand_empty_rest_of_line ();
9908 mips_flush_pending_output ()
9910 mips_emit_delays (false);
9911 mips_clear_insn_labels ();
9920 /* When generating embedded PIC code, we only use the .text, .lit8,
9921 .sdata and .sbss sections. We change the .data and .rdata
9922 pseudo-ops to use .sdata. */
9923 if (mips_pic
== EMBEDDED_PIC
9924 && (sec
== 'd' || sec
== 'r'))
9928 /* The ELF backend needs to know that we are changing sections, so
9929 that .previous works correctly. We could do something like check
9930 for a obj_section_change_hook macro, but that might be confusing
9931 as it would not be appropriate to use it in the section changing
9932 functions in read.c, since obj-elf.c intercepts those. FIXME:
9933 This should be cleaner, somehow. */
9934 obj_elf_section_change_hook ();
9937 mips_emit_delays (false);
9947 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9948 demand_empty_rest_of_line ();
9952 if (USE_GLOBAL_POINTER_OPT
)
9954 seg
= subseg_new (RDATA_SECTION_NAME
,
9955 (subsegT
) get_absolute_expression ());
9956 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9958 bfd_set_section_flags (stdoutput
, seg
,
9964 if (strcmp (TARGET_OS
, "elf") != 0)
9965 bfd_set_section_alignment (stdoutput
, seg
, 4);
9967 demand_empty_rest_of_line ();
9971 as_bad (_("No read only data section in this object file format"));
9972 demand_empty_rest_of_line ();
9978 if (USE_GLOBAL_POINTER_OPT
)
9980 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9981 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9983 bfd_set_section_flags (stdoutput
, seg
,
9984 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9986 if (strcmp (TARGET_OS
, "elf") != 0)
9987 bfd_set_section_alignment (stdoutput
, seg
, 4);
9989 demand_empty_rest_of_line ();
9994 as_bad (_("Global pointers not supported; recompile -G 0"));
9995 demand_empty_rest_of_line ();
10004 mips_enable_auto_align ()
10015 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10016 mips_emit_delays (false);
10017 if (log_size
> 0 && auto_align
)
10018 mips_align (log_size
, 0, label
);
10019 mips_clear_insn_labels ();
10020 cons (1 << log_size
);
10024 s_float_cons (type
)
10029 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10031 mips_emit_delays (false);
10036 mips_align (3, 0, label
);
10038 mips_align (2, 0, label
);
10041 mips_clear_insn_labels ();
10046 /* Handle .globl. We need to override it because on Irix 5 you are
10049 where foo is an undefined symbol, to mean that foo should be
10050 considered to be the address of a function. */
10061 name
= input_line_pointer
;
10062 c
= get_symbol_end ();
10063 symbolP
= symbol_find_or_make (name
);
10064 *input_line_pointer
= c
;
10065 SKIP_WHITESPACE ();
10067 /* On Irix 5, every global symbol that is not explicitly labelled as
10068 being a function is apparently labelled as being an object. */
10071 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10076 secname
= input_line_pointer
;
10077 c
= get_symbol_end ();
10078 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10080 as_bad (_("%s: no such section"), secname
);
10081 *input_line_pointer
= c
;
10083 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10084 flag
= BSF_FUNCTION
;
10087 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10089 S_SET_EXTERNAL (symbolP
);
10090 demand_empty_rest_of_line ();
10100 opt
= input_line_pointer
;
10101 c
= get_symbol_end ();
10105 /* FIXME: What does this mean? */
10107 else if (strncmp (opt
, "pic", 3) == 0)
10111 i
= atoi (opt
+ 3);
10115 mips_pic
= SVR4_PIC
;
10117 as_bad (_(".option pic%d not supported"), i
);
10119 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10121 if (g_switch_seen
&& g_switch_value
!= 0)
10122 as_warn (_("-G may not be used with SVR4 PIC code"));
10123 g_switch_value
= 0;
10124 bfd_set_gp_size (stdoutput
, 0);
10128 as_warn (_("Unrecognized option \"%s\""), opt
);
10130 *input_line_pointer
= c
;
10131 demand_empty_rest_of_line ();
10134 /* This structure is used to hold a stack of .set values. */
10136 struct mips_option_stack
10138 struct mips_option_stack
*next
;
10139 struct mips_set_options options
;
10142 static struct mips_option_stack
*mips_opts_stack
;
10144 /* Handle the .set pseudo-op. */
10150 char *name
= input_line_pointer
, ch
;
10152 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10153 input_line_pointer
++;
10154 ch
= *input_line_pointer
;
10155 *input_line_pointer
= '\0';
10157 if (strcmp (name
, "reorder") == 0)
10159 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10161 /* If we still have pending nops, we can discard them. The
10162 usual nop handling will insert any that are still
10164 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10165 * (mips_opts
.mips16
? 2 : 4));
10166 prev_nop_frag
= NULL
;
10168 mips_opts
.noreorder
= 0;
10170 else if (strcmp (name
, "noreorder") == 0)
10172 mips_emit_delays (true);
10173 mips_opts
.noreorder
= 1;
10174 mips_any_noreorder
= 1;
10176 else if (strcmp (name
, "at") == 0)
10178 mips_opts
.noat
= 0;
10180 else if (strcmp (name
, "noat") == 0)
10182 mips_opts
.noat
= 1;
10184 else if (strcmp (name
, "macro") == 0)
10186 mips_opts
.warn_about_macros
= 0;
10188 else if (strcmp (name
, "nomacro") == 0)
10190 if (mips_opts
.noreorder
== 0)
10191 as_bad (_("`noreorder' must be set before `nomacro'"));
10192 mips_opts
.warn_about_macros
= 1;
10194 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10196 mips_opts
.nomove
= 0;
10198 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10200 mips_opts
.nomove
= 1;
10202 else if (strcmp (name
, "bopt") == 0)
10204 mips_opts
.nobopt
= 0;
10206 else if (strcmp (name
, "nobopt") == 0)
10208 mips_opts
.nobopt
= 1;
10210 else if (strcmp (name
, "mips16") == 0
10211 || strcmp (name
, "MIPS-16") == 0)
10212 mips_opts
.mips16
= 1;
10213 else if (strcmp (name
, "nomips16") == 0
10214 || strcmp (name
, "noMIPS-16") == 0)
10215 mips_opts
.mips16
= 0;
10216 else if (strncmp (name
, "mips", 4) == 0)
10220 /* Permit the user to change the ISA on the fly. Needless to
10221 say, misuse can cause serious problems. */
10222 isa
= atoi (name
+ 4);
10224 mips_opts
.isa
= file_mips_isa
;
10225 else if (isa
< 1 || isa
> 4)
10226 as_bad (_("unknown ISA level"));
10228 mips_opts
.isa
= isa
;
10230 else if (strcmp (name
, "autoextend") == 0)
10231 mips_opts
.noautoextend
= 0;
10232 else if (strcmp (name
, "noautoextend") == 0)
10233 mips_opts
.noautoextend
= 1;
10234 else if (strcmp (name
, "push") == 0)
10236 struct mips_option_stack
*s
;
10238 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10239 s
->next
= mips_opts_stack
;
10240 s
->options
= mips_opts
;
10241 mips_opts_stack
= s
;
10243 else if (strcmp (name
, "pop") == 0)
10245 struct mips_option_stack
*s
;
10247 s
= mips_opts_stack
;
10249 as_bad (_(".set pop with no .set push"));
10252 /* If we're changing the reorder mode we need to handle
10253 delay slots correctly. */
10254 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10255 mips_emit_delays (true);
10256 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10258 if (prev_nop_frag
!= NULL
)
10260 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10261 * (mips_opts
.mips16
? 2 : 4));
10262 prev_nop_frag
= NULL
;
10266 mips_opts
= s
->options
;
10267 mips_opts_stack
= s
->next
;
10273 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10275 *input_line_pointer
= ch
;
10276 demand_empty_rest_of_line ();
10279 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10280 .option pic2. It means to generate SVR4 PIC calls. */
10283 s_abicalls (ignore
)
10286 mips_pic
= SVR4_PIC
;
10287 if (USE_GLOBAL_POINTER_OPT
)
10289 if (g_switch_seen
&& g_switch_value
!= 0)
10290 as_warn (_("-G may not be used with SVR4 PIC code"));
10291 g_switch_value
= 0;
10293 bfd_set_gp_size (stdoutput
, 0);
10294 demand_empty_rest_of_line ();
10297 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10298 PIC code. It sets the $gp register for the function based on the
10299 function address, which is in the register named in the argument.
10300 This uses a relocation against _gp_disp, which is handled specially
10301 by the linker. The result is:
10302 lui $gp,%hi(_gp_disp)
10303 addiu $gp,$gp,%lo(_gp_disp)
10304 addu $gp,$gp,.cpload argument
10305 The .cpload argument is normally $25 == $t9. */
10314 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10315 if (mips_pic
!= SVR4_PIC
)
10321 /* .cpload should be a in .set noreorder section. */
10322 if (mips_opts
.noreorder
== 0)
10323 as_warn (_(".cpload not in noreorder section"));
10325 ex
.X_op
= O_symbol
;
10326 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10327 ex
.X_op_symbol
= NULL
;
10328 ex
.X_add_number
= 0;
10330 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10331 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10333 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10334 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10335 (int) BFD_RELOC_LO16
);
10337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10338 GP
, GP
, tc_get_register (0));
10340 demand_empty_rest_of_line ();
10343 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10344 offset from $sp. The offset is remembered, and after making a PIC
10345 call $gp is restored from that location. */
10348 s_cprestore (ignore
)
10354 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10355 if (mips_pic
!= SVR4_PIC
)
10361 mips_cprestore_offset
= get_absolute_expression ();
10363 ex
.X_op
= O_constant
;
10364 ex
.X_add_symbol
= NULL
;
10365 ex
.X_op_symbol
= NULL
;
10366 ex
.X_add_number
= mips_cprestore_offset
;
10368 macro_build ((char *) NULL
, &icnt
, &ex
,
10369 ((bfd_arch_bits_per_address (stdoutput
) == 32
10370 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10372 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10374 demand_empty_rest_of_line ();
10377 /* Handle the .gpword pseudo-op. This is used when generating PIC
10378 code. It generates a 32 bit GP relative reloc. */
10388 /* When not generating PIC code, this is treated as .word. */
10389 if (mips_pic
!= SVR4_PIC
)
10395 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10396 mips_emit_delays (true);
10398 mips_align (2, 0, label
);
10399 mips_clear_insn_labels ();
10403 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10405 as_bad (_("Unsupported use of .gpword"));
10406 ignore_rest_of_line ();
10410 md_number_to_chars (p
, (valueT
) 0, 4);
10411 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10412 BFD_RELOC_MIPS_GPREL32
);
10414 demand_empty_rest_of_line ();
10417 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10418 tables in SVR4 PIC code. */
10427 /* This is ignored when not generating SVR4 PIC code. */
10428 if (mips_pic
!= SVR4_PIC
)
10434 /* Add $gp to the register named as an argument. */
10435 reg
= tc_get_register (0);
10436 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10437 ((bfd_arch_bits_per_address (stdoutput
) == 32
10438 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10439 ? "addu" : "daddu"),
10440 "d,v,t", reg
, reg
, GP
);
10442 demand_empty_rest_of_line ();
10445 /* Handle the .insn pseudo-op. This marks instruction labels in
10446 mips16 mode. This permits the linker to handle them specially,
10447 such as generating jalx instructions when needed. We also make
10448 them odd for the duration of the assembly, in order to generate the
10449 right sort of code. We will make them even in the adjust_symtab
10450 routine, while leaving them marked. This is convenient for the
10451 debugger and the disassembler. The linker knows to make them odd
10458 if (mips_opts
.mips16
)
10459 mips16_mark_labels ();
10461 demand_empty_rest_of_line ();
10464 /* Handle a .stabn directive. We need these in order to mark a label
10465 as being a mips16 text label correctly. Sometimes the compiler
10466 will emit a label, followed by a .stabn, and then switch sections.
10467 If the label and .stabn are in mips16 mode, then the label is
10468 really a mips16 text label. */
10474 if (type
== 'n' && mips_opts
.mips16
)
10475 mips16_mark_labels ();
10480 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10484 s_mips_weakext (ignore
)
10492 name
= input_line_pointer
;
10493 c
= get_symbol_end ();
10494 symbolP
= symbol_find_or_make (name
);
10495 S_SET_WEAK (symbolP
);
10496 *input_line_pointer
= c
;
10498 SKIP_WHITESPACE ();
10500 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10502 if (S_IS_DEFINED (symbolP
))
10504 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10505 S_GET_NAME (symbolP
));
10506 ignore_rest_of_line ();
10510 if (*input_line_pointer
== ',')
10512 ++input_line_pointer
;
10513 SKIP_WHITESPACE ();
10517 if (exp
.X_op
!= O_symbol
)
10519 as_bad ("bad .weakext directive");
10520 ignore_rest_of_line();
10523 symbol_set_value_expression (symbolP
, &exp
);
10526 demand_empty_rest_of_line ();
10529 /* Parse a register string into a number. Called from the ECOFF code
10530 to parse .frame. The argument is non-zero if this is the frame
10531 register, so that we can record it in mips_frame_reg. */
10534 tc_get_register (frame
)
10539 SKIP_WHITESPACE ();
10540 if (*input_line_pointer
++ != '$')
10542 as_warn (_("expected `$'"));
10545 else if (isdigit ((unsigned char) *input_line_pointer
))
10547 reg
= get_absolute_expression ();
10548 if (reg
< 0 || reg
>= 32)
10550 as_warn (_("Bad register number"));
10556 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10558 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10560 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10562 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10566 as_warn (_("Unrecognized register name"));
10569 input_line_pointer
+= 2;
10572 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10577 md_section_align (seg
, addr
)
10581 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10584 /* We don't need to align ELF sections to the full alignment.
10585 However, Irix 5 may prefer that we align them at least to a 16
10586 byte boundary. We don't bother to align the sections if we are
10587 targeted for an embedded system. */
10588 if (strcmp (TARGET_OS
, "elf") == 0)
10594 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10597 /* Utility routine, called from above as well. If called while the
10598 input file is still being read, it's only an approximation. (For
10599 example, a symbol may later become defined which appeared to be
10600 undefined earlier.) */
10603 nopic_need_relax (sym
, before_relaxing
)
10605 int before_relaxing
;
10610 if (USE_GLOBAL_POINTER_OPT
)
10612 const char *symname
;
10615 /* Find out whether this symbol can be referenced off the GP
10616 register. It can be if it is smaller than the -G size or if
10617 it is in the .sdata or .sbss section. Certain symbols can
10618 not be referenced off the GP, although it appears as though
10620 symname
= S_GET_NAME (sym
);
10621 if (symname
!= (const char *) NULL
10622 && (strcmp (symname
, "eprol") == 0
10623 || strcmp (symname
, "etext") == 0
10624 || strcmp (symname
, "_gp") == 0
10625 || strcmp (symname
, "edata") == 0
10626 || strcmp (symname
, "_fbss") == 0
10627 || strcmp (symname
, "_fdata") == 0
10628 || strcmp (symname
, "_ftext") == 0
10629 || strcmp (symname
, "end") == 0
10630 || strcmp (symname
, "_gp_disp") == 0))
10632 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10634 #ifndef NO_ECOFF_DEBUGGING
10635 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10636 && (symbol_get_obj (sym
)->ecoff_extern_size
10637 <= g_switch_value
))
10639 /* We must defer this decision until after the whole
10640 file has been read, since there might be a .extern
10641 after the first use of this symbol. */
10642 || (before_relaxing
10643 #ifndef NO_ECOFF_DEBUGGING
10644 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10646 && S_GET_VALUE (sym
) == 0)
10647 || (S_GET_VALUE (sym
) != 0
10648 && S_GET_VALUE (sym
) <= g_switch_value
)))
10652 const char *segname
;
10654 segname
= segment_name (S_GET_SEGMENT (sym
));
10655 assert (strcmp (segname
, ".lit8") != 0
10656 && strcmp (segname
, ".lit4") != 0);
10657 change
= (strcmp (segname
, ".sdata") != 0
10658 && strcmp (segname
, ".sbss") != 0
10659 && strncmp (segname
, ".sdata.", 7) != 0
10660 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10665 /* We are not optimizing for the GP register. */
10669 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10670 extended opcode. SEC is the section the frag is in. */
10673 mips16_extended_frag (fragp
, sec
, stretch
)
10679 register const struct mips16_immed_operand
*op
;
10681 int mintiny
, maxtiny
;
10684 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10686 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10689 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10690 op
= mips16_immed_operands
;
10691 while (op
->type
!= type
)
10694 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10699 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10702 maxtiny
= 1 << op
->nbits
;
10707 maxtiny
= (1 << op
->nbits
) - 1;
10712 mintiny
= - (1 << (op
->nbits
- 1));
10713 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10716 /* We can't always call S_GET_VALUE here, because we don't want to
10717 lock in a particular frag address. */
10718 if (symbol_constant_p (fragp
->fr_symbol
))
10720 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10721 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10722 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10724 else if (symbol_equated_p (fragp
->fr_symbol
)
10725 && (symbol_constant_p
10726 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10730 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10731 val
= (S_GET_VALUE (eqsym
)
10732 + symbol_get_frag (eqsym
)->fr_address
10733 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10734 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10735 symsec
= S_GET_SEGMENT (eqsym
);
10744 /* We won't have the section when we are called from
10745 mips_relax_frag. However, we will always have been called
10746 from md_estimate_size_before_relax first. If this is a
10747 branch to a different section, we mark it as such. If SEC is
10748 NULL, and the frag is not marked, then it must be a branch to
10749 the same section. */
10752 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10759 fragp
->fr_subtype
=
10760 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10762 /* FIXME: We should support this, and let the linker
10763 catch branches and loads that are out of range. */
10764 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10765 _("unsupported PC relative reference to different section"));
10771 /* In this case, we know for sure that the symbol fragment is in
10772 the same section. If the fr_address of the symbol fragment
10773 is greater then the address of this fragment we want to add
10774 in STRETCH in order to get a better estimate of the address.
10775 This particularly matters because of the shift bits. */
10777 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10778 >= fragp
->fr_address
))
10782 /* Adjust stretch for any alignment frag. Note that if have
10783 been expanding the earlier code, the symbol may be
10784 defined in what appears to be an earlier frag. FIXME:
10785 This doesn't handle the fr_subtype field, which specifies
10786 a maximum number of bytes to skip when doing an
10789 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10792 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10795 stretch
= - ((- stretch
)
10796 & ~ ((1 << (int) f
->fr_offset
) - 1));
10798 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10807 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10809 /* The base address rules are complicated. The base address of
10810 a branch is the following instruction. The base address of a
10811 PC relative load or add is the instruction itself, but if it
10812 is in a delay slot (in which case it can not be extended) use
10813 the address of the instruction whose delay slot it is in. */
10814 if (type
== 'p' || type
== 'q')
10818 /* If we are currently assuming that this frag should be
10819 extended, then, the current address is two bytes
10821 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10824 /* Ignore the low bit in the target, since it will be set
10825 for a text label. */
10826 if ((val
& 1) != 0)
10829 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10831 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10834 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10836 /* Branch offsets have an implicit 0 in the lowest bit. */
10837 if (type
== 'p' || type
== 'q')
10840 /* If any of the shifted bits are set, we must use an extended
10841 opcode. If the address depends on the size of this
10842 instruction, this can lead to a loop, so we arrange to always
10843 use an extended opcode. We only check this when we are in
10844 the main relaxation loop, when SEC is NULL. */
10845 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10847 fragp
->fr_subtype
=
10848 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10852 /* If we are about to mark a frag as extended because the value
10853 is precisely maxtiny + 1, then there is a chance of an
10854 infinite loop as in the following code:
10859 In this case when the la is extended, foo is 0x3fc bytes
10860 away, so the la can be shrunk, but then foo is 0x400 away, so
10861 the la must be extended. To avoid this loop, we mark the
10862 frag as extended if it was small, and is about to become
10863 extended with a value of maxtiny + 1. */
10864 if (val
== ((maxtiny
+ 1) << op
->shift
)
10865 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10868 fragp
->fr_subtype
=
10869 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10873 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10874 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10876 if ((val
& ((1 << op
->shift
) - 1)) != 0
10877 || val
< (mintiny
<< op
->shift
)
10878 || val
> (maxtiny
<< op
->shift
))
10884 /* Estimate the size of a frag before relaxing. Unless this is the
10885 mips16, we are not really relaxing here, and the final size is
10886 encoded in the subtype information. For the mips16, we have to
10887 decide whether we are using an extended opcode or not. */
10891 md_estimate_size_before_relax (fragp
, segtype
)
10897 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10899 if (mips16_extended_frag (fragp
, segtype
, 0))
10901 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10906 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10911 if (mips_pic
== NO_PIC
)
10913 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10915 else if (mips_pic
== SVR4_PIC
)
10920 sym
= fragp
->fr_symbol
;
10922 /* Handle the case of a symbol equated to another symbol. */
10923 while (symbol_equated_p (sym
)
10924 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10928 /* It's possible to get a loop here in a badly written
10930 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10936 symsec
= S_GET_SEGMENT (sym
);
10938 /* This must duplicate the test in adjust_reloc_syms. */
10939 change
= (symsec
!= &bfd_und_section
10940 && symsec
!= &bfd_abs_section
10941 && ! bfd_is_com_section (symsec
));
10948 /* Record the offset to the first reloc in the fr_opcode field.
10949 This lets md_convert_frag and tc_gen_reloc know that the code
10950 must be expanded. */
10951 fragp
->fr_opcode
= (fragp
->fr_literal
10953 - RELAX_OLD (fragp
->fr_subtype
)
10954 + RELAX_RELOC1 (fragp
->fr_subtype
));
10955 /* FIXME: This really needs as_warn_where. */
10956 if (RELAX_WARN (fragp
->fr_subtype
))
10957 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
10963 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10966 /* This is called to see whether a reloc against a defined symbol
10967 should be converted into a reloc against a section. Don't adjust
10968 MIPS16 jump relocations, so we don't have to worry about the format
10969 of the offset in the .o file. Don't adjust relocations against
10970 mips16 symbols, so that the linker can find them if it needs to set
10974 mips_fix_adjustable (fixp
)
10977 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10979 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10980 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10982 if (fixp
->fx_addsy
== NULL
)
10985 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10986 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10987 && fixp
->fx_subsy
== NULL
)
10993 /* Translate internal representation of relocation info to BFD target
10997 tc_gen_reloc (section
, fixp
)
11001 static arelent
*retval
[4];
11003 bfd_reloc_code_real_type code
;
11005 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11008 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11009 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11010 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11012 if (mips_pic
== EMBEDDED_PIC
11013 && SWITCH_TABLE (fixp
))
11015 /* For a switch table entry we use a special reloc. The addend
11016 is actually the difference between the reloc address and the
11018 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11019 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11020 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11021 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11023 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11025 /* We use a special addend for an internal RELLO reloc. */
11026 if (symbol_section_p (fixp
->fx_addsy
))
11027 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11029 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11031 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11033 assert (fixp
->fx_next
!= NULL
11034 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11035 /* We use a special addend for an internal RELHI reloc. The
11036 reloc is relative to the RELLO; adjust the addend
11038 if (symbol_section_p (fixp
->fx_addsy
))
11039 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11040 + fixp
->fx_next
->fx_where
11041 - S_GET_VALUE (fixp
->fx_subsy
));
11043 reloc
->addend
= (fixp
->fx_addnumber
11044 + fixp
->fx_next
->fx_frag
->fr_address
11045 + fixp
->fx_next
->fx_where
);
11047 else if (fixp
->fx_pcrel
== 0)
11048 reloc
->addend
= fixp
->fx_addnumber
;
11051 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11052 /* A gruesome hack which is a result of the gruesome gas reloc
11054 reloc
->addend
= reloc
->address
;
11056 reloc
->addend
= -reloc
->address
;
11059 /* If this is a variant frag, we may need to adjust the existing
11060 reloc and generate a new one. */
11061 if (fixp
->fx_frag
->fr_opcode
!= NULL
11062 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11063 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11064 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11065 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11066 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11067 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11068 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11072 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11074 /* If this is not the last reloc in this frag, then we have two
11075 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11076 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11077 the second one handle all of them. */
11078 if (fixp
->fx_next
!= NULL
11079 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11081 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11082 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11083 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11084 && (fixp
->fx_next
->fx_r_type
11085 == BFD_RELOC_MIPS_GOT_LO16
))
11086 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11087 && (fixp
->fx_next
->fx_r_type
11088 == BFD_RELOC_MIPS_CALL_LO16
)));
11093 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11094 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11095 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11097 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11098 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11099 reloc2
->address
= (reloc
->address
11100 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11101 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11102 reloc2
->addend
= fixp
->fx_addnumber
;
11103 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11104 assert (reloc2
->howto
!= NULL
);
11106 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11110 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11113 reloc3
->address
+= 4;
11116 if (mips_pic
== NO_PIC
)
11118 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11119 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11121 else if (mips_pic
== SVR4_PIC
)
11123 switch (fixp
->fx_r_type
)
11127 case BFD_RELOC_MIPS_GOT16
:
11129 case BFD_RELOC_MIPS_CALL16
:
11130 case BFD_RELOC_MIPS_GOT_LO16
:
11131 case BFD_RELOC_MIPS_CALL_LO16
:
11132 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11140 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11141 to be used in the relocation's section offset. */
11142 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11144 reloc
->address
= reloc
->addend
;
11148 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11149 fixup_segment converted a non-PC relative reloc into a PC
11150 relative reloc. In such a case, we need to convert the reloc
11152 code
= fixp
->fx_r_type
;
11153 if (fixp
->fx_pcrel
)
11158 code
= BFD_RELOC_8_PCREL
;
11161 code
= BFD_RELOC_16_PCREL
;
11164 code
= BFD_RELOC_32_PCREL
;
11167 code
= BFD_RELOC_64_PCREL
;
11169 case BFD_RELOC_8_PCREL
:
11170 case BFD_RELOC_16_PCREL
:
11171 case BFD_RELOC_32_PCREL
:
11172 case BFD_RELOC_64_PCREL
:
11173 case BFD_RELOC_16_PCREL_S2
:
11174 case BFD_RELOC_PCREL_HI16_S
:
11175 case BFD_RELOC_PCREL_LO16
:
11178 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11179 _("Cannot make %s relocation PC relative"),
11180 bfd_get_reloc_code_name (code
));
11184 /* To support a PC relative reloc when generating embedded PIC code
11185 for ECOFF, we use a Cygnus extension. We check for that here to
11186 make sure that we don't let such a reloc escape normally. */
11187 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11188 && code
== BFD_RELOC_16_PCREL_S2
11189 && mips_pic
!= EMBEDDED_PIC
)
11190 reloc
->howto
= NULL
;
11192 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11194 if (reloc
->howto
== NULL
)
11196 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11197 _("Can not represent %s relocation in this object file format"),
11198 bfd_get_reloc_code_name (code
));
11205 /* Relax a machine dependent frag. This returns the amount by which
11206 the current size of the frag should change. */
11209 mips_relax_frag (fragp
, stretch
)
11213 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11216 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11218 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11220 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11225 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11227 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11234 /* Convert a machine dependent frag. */
11237 md_convert_frag (abfd
, asec
, fragp
)
11245 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11248 register const struct mips16_immed_operand
*op
;
11249 boolean small
, ext
;
11252 unsigned long insn
;
11253 boolean use_extend
;
11254 unsigned short extend
;
11256 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11257 op
= mips16_immed_operands
;
11258 while (op
->type
!= type
)
11261 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11272 resolve_symbol_value (fragp
->fr_symbol
, 1);
11273 val
= S_GET_VALUE (fragp
->fr_symbol
);
11278 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11280 /* The rules for the base address of a PC relative reloc are
11281 complicated; see mips16_extended_frag. */
11282 if (type
== 'p' || type
== 'q')
11287 /* Ignore the low bit in the target, since it will be
11288 set for a text label. */
11289 if ((val
& 1) != 0)
11292 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11294 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11297 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11300 /* Make sure the section winds up with the alignment we have
11303 record_alignment (asec
, op
->shift
);
11307 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11308 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11309 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11310 _("extended instruction in delay slot"));
11312 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11314 if (target_big_endian
)
11315 insn
= bfd_getb16 (buf
);
11317 insn
= bfd_getl16 (buf
);
11319 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11320 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11321 small
, ext
, &insn
, &use_extend
, &extend
);
11325 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11326 fragp
->fr_fix
+= 2;
11330 md_number_to_chars (buf
, insn
, 2);
11331 fragp
->fr_fix
+= 2;
11336 if (fragp
->fr_opcode
== NULL
)
11339 old
= RELAX_OLD (fragp
->fr_subtype
);
11340 new = RELAX_NEW (fragp
->fr_subtype
);
11341 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11344 memcpy (fixptr
- old
, fixptr
, new);
11346 fragp
->fr_fix
+= new - old
;
11352 /* This function is called after the relocs have been generated.
11353 We've been storing mips16 text labels as odd. Here we convert them
11354 back to even for the convenience of the debugger. */
11357 mips_frob_file_after_relocs ()
11360 unsigned int count
, i
;
11362 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11365 syms
= bfd_get_outsymbols (stdoutput
);
11366 count
= bfd_get_symcount (stdoutput
);
11367 for (i
= 0; i
< count
; i
++, syms
++)
11369 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11370 && ((*syms
)->value
& 1) != 0)
11372 (*syms
)->value
&= ~1;
11373 /* If the symbol has an odd size, it was probably computed
11374 incorrectly, so adjust that as well. */
11375 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11376 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11383 /* This function is called whenever a label is defined. It is used
11384 when handling branch delays; if a branch has a label, we assume we
11385 can not move it. */
11388 mips_define_label (sym
)
11391 struct insn_label_list
*l
;
11393 if (free_insn_labels
== NULL
)
11394 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11397 l
= free_insn_labels
;
11398 free_insn_labels
= l
->next
;
11402 l
->next
= insn_labels
;
11406 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11408 /* Some special processing for a MIPS ELF file. */
11411 mips_elf_final_processing ()
11413 /* Write out the register information. */
11418 s
.ri_gprmask
= mips_gprmask
;
11419 s
.ri_cprmask
[0] = mips_cprmask
[0];
11420 s
.ri_cprmask
[1] = mips_cprmask
[1];
11421 s
.ri_cprmask
[2] = mips_cprmask
[2];
11422 s
.ri_cprmask
[3] = mips_cprmask
[3];
11423 /* The gp_value field is set by the MIPS ELF backend. */
11425 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11426 ((Elf32_External_RegInfo
*)
11427 mips_regmask_frag
));
11431 Elf64_Internal_RegInfo s
;
11433 s
.ri_gprmask
= mips_gprmask
;
11435 s
.ri_cprmask
[0] = mips_cprmask
[0];
11436 s
.ri_cprmask
[1] = mips_cprmask
[1];
11437 s
.ri_cprmask
[2] = mips_cprmask
[2];
11438 s
.ri_cprmask
[3] = mips_cprmask
[3];
11439 /* The gp_value field is set by the MIPS ELF backend. */
11441 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11442 ((Elf64_External_RegInfo
*)
11443 mips_regmask_frag
));
11446 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11447 sort of BFD interface for this. */
11448 if (mips_any_noreorder
)
11449 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11450 if (mips_pic
!= NO_PIC
)
11451 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11453 /* Set the MIPS ELF ABI flags. */
11454 if (mips_abi_string
== 0)
11456 else if (strcmp (mips_abi_string
,"32") == 0)
11457 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11458 else if (strcmp (mips_abi_string
,"o64") == 0)
11459 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11460 else if (strcmp (mips_abi_string
,"eabi") == 0)
11463 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11465 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11468 if (mips_32bitmode
)
11469 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11472 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11474 typedef struct proc
11477 unsigned long reg_mask
;
11478 unsigned long reg_offset
;
11479 unsigned long fpreg_mask
;
11480 unsigned long fpreg_offset
;
11481 unsigned long frame_offset
;
11482 unsigned long frame_reg
;
11483 unsigned long pc_reg
;
11487 static procS cur_proc
;
11488 static procS
*cur_proc_ptr
;
11489 static int numprocs
;
11491 /* When we align code in the .text section of mips16, use the correct two
11492 byte nop pattern of 0x6500 (move $0,$0) */
11495 mips_do_align (n
, fill
, len
, max
)
11502 && subseg_text_p (now_seg
)
11504 && mips_opts
.mips16
)
11506 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11507 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11509 frag_align (1, 0, 0);
11511 if (target_big_endian
)
11512 frag_align_pattern (n
, be_nop
, 2, max
);
11514 frag_align_pattern (n
, le_nop
, 2, max
);
11529 /* check for premature end, nesting errors, etc */
11531 as_warn (_("missing `.end' at end of assembly"));
11540 if (*input_line_pointer
== '-')
11542 ++input_line_pointer
;
11545 if (!isdigit ((unsigned char) *input_line_pointer
))
11546 as_bad (_("Expected simple number."));
11547 if (input_line_pointer
[0] == '0')
11549 if (input_line_pointer
[1] == 'x')
11551 input_line_pointer
+= 2;
11552 while (isxdigit ((unsigned char) *input_line_pointer
))
11555 val
|= hex_value (*input_line_pointer
++);
11557 return negative
? -val
: val
;
11561 ++input_line_pointer
;
11562 while (isdigit ((unsigned char) *input_line_pointer
))
11565 val
|= *input_line_pointer
++ - '0';
11567 return negative
? -val
: val
;
11570 if (!isdigit ((unsigned char) *input_line_pointer
))
11572 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11573 *input_line_pointer
, *input_line_pointer
);
11574 as_warn (_("Invalid number"));
11577 while (isdigit ((unsigned char) *input_line_pointer
))
11580 val
+= *input_line_pointer
++ - '0';
11582 return negative
? -val
: val
;
11585 /* The .file directive; just like the usual .file directive, but there
11586 is an initial number which is the ECOFF file index. */
11594 line
= get_number ();
11599 /* The .end directive. */
11608 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11611 demand_empty_rest_of_line ();
11616 #ifdef BFD_ASSEMBLER
11617 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11622 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11629 as_warn (_(".end not in text section"));
11633 as_warn (_(".end directive without a preceding .ent directive."));
11634 demand_empty_rest_of_line ();
11640 assert (S_GET_NAME (p
));
11641 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11642 as_warn (_(".end symbol does not match .ent symbol."));
11645 as_warn (_(".end directive missing or unknown symbol"));
11647 #ifdef MIPS_STABS_ELF
11649 segT saved_seg
= now_seg
;
11650 subsegT saved_subseg
= now_subseg
;
11651 fragS
*saved_frag
= frag_now
;
11657 dot
= frag_now_fix ();
11659 #ifdef md_flush_pending_output
11660 md_flush_pending_output ();
11664 subseg_set (pdr_seg
, 0);
11666 /* Write the symbol */
11667 exp
.X_op
= O_symbol
;
11668 exp
.X_add_symbol
= p
;
11669 exp
.X_add_number
= 0;
11670 emit_expr (&exp
, 4);
11672 fragp
= frag_more (7*4);
11674 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11675 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11676 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11677 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11678 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11679 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11680 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11682 subseg_set (saved_seg
, saved_subseg
);
11686 cur_proc_ptr
= NULL
;
11689 /* The .aent and .ent directives. */
11699 symbolP
= get_symbol ();
11700 if (*input_line_pointer
== ',')
11701 input_line_pointer
++;
11702 SKIP_WHITESPACE ();
11703 if (isdigit ((unsigned char) *input_line_pointer
)
11704 || *input_line_pointer
== '-')
11705 number
= get_number ();
11707 #ifdef BFD_ASSEMBLER
11708 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11713 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11720 as_warn (_(".ent or .aent not in text section."));
11722 if (!aent
&& cur_proc_ptr
)
11723 as_warn (_("missing `.end'"));
11727 cur_proc_ptr
= &cur_proc
;
11728 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11730 cur_proc_ptr
->isym
= symbolP
;
11732 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11737 demand_empty_rest_of_line ();
11740 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11741 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11742 s_mips_frame is used so that we can set the PDR information correctly.
11743 We can't use the ecoff routines because they make reference to the ecoff
11744 symbol table (in the mdebug section). */
11747 s_mips_frame (ignore
)
11750 #ifdef MIPS_STABS_ELF
11754 if (cur_proc_ptr
== (procS
*) NULL
)
11756 as_warn (_(".frame outside of .ent"));
11757 demand_empty_rest_of_line ();
11761 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11763 SKIP_WHITESPACE ();
11764 if (*input_line_pointer
++ != ','
11765 || get_absolute_expression_and_terminator (&val
) != ',')
11767 as_warn (_("Bad .frame directive"));
11768 --input_line_pointer
;
11769 demand_empty_rest_of_line ();
11773 cur_proc_ptr
->frame_offset
= val
;
11774 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11776 demand_empty_rest_of_line ();
11779 #endif /* MIPS_STABS_ELF */
11782 /* The .fmask and .mask directives. If the mdebug section is present
11783 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11784 embedded targets, s_mips_mask is used so that we can set the PDR
11785 information correctly. We can't use the ecoff routines because they
11786 make reference to the ecoff symbol table (in the mdebug section). */
11789 s_mips_mask (reg_type
)
11792 #ifdef MIPS_STABS_ELF
11795 if (cur_proc_ptr
== (procS
*) NULL
)
11797 as_warn (_(".mask/.fmask outside of .ent"));
11798 demand_empty_rest_of_line ();
11802 if (get_absolute_expression_and_terminator (&mask
) != ',')
11804 as_warn (_("Bad .mask/.fmask directive"));
11805 --input_line_pointer
;
11806 demand_empty_rest_of_line ();
11810 off
= get_absolute_expression ();
11812 if (reg_type
== 'F')
11814 cur_proc_ptr
->fpreg_mask
= mask
;
11815 cur_proc_ptr
->fpreg_offset
= off
;
11819 cur_proc_ptr
->reg_mask
= mask
;
11820 cur_proc_ptr
->reg_offset
= off
;
11823 demand_empty_rest_of_line ();
11825 s_ignore (reg_type
);
11826 #endif /* MIPS_STABS_ELF */
11829 /* The .loc directive. */
11840 assert (now_seg
== text_section
);
11842 lineno
= get_number ();
11843 addroff
= frag_now_fix ();
11845 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11846 S_SET_TYPE (symbolP
, N_SLINE
);
11847 S_SET_OTHER (symbolP
, 0);
11848 S_SET_DESC (symbolP
, lineno
);
11849 symbolP
->sy_segment
= now_seg
;