1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2015 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes
[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p
;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length
;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes
[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes
[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns
[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning
;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1295 static void append_insn
1296 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1297 bfd_boolean expansionp
);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS
*, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS
*, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS
*, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn
*ip
, char *str
);
1306 static void mips16_macro (struct mips_cl_insn
* ip
);
1307 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1308 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1309 static void mips16_immed
1310 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1314 static void my_getExpression (expressionS
*, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type
);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1350 static int relaxed_branch_length (fragS
*, asection
*, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name
; /* CPU or ISA name. */
1361 int flags
; /* MIPS_CPU_* flags. */
1362 int ase
; /* Set of ASEs implemented by the CPU. */
1363 int isa
; /* ISA level. */
1364 int cpu
; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts
= "O::g::G:";
1378 OPTION_MARCH
= OPTION_MD_BASE
,
1410 OPTION_NO_SMARTMIPS
,
1418 OPTION_NO_MICROMIPS
,
1421 OPTION_COMPAT_ARCH_BASE
,
1430 OPTION_M7000_HILO_FIX
,
1431 OPTION_MNO_7000_HILO_FIX
,
1435 OPTION_NO_FIX_RM7000
,
1436 OPTION_FIX_LOONGSON2F_JUMP
,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1438 OPTION_FIX_LOONGSON2F_NOP
,
1439 OPTION_NO_FIX_LOONGSON2F_NOP
,
1441 OPTION_NO_FIX_VR4120
,
1443 OPTION_NO_FIX_VR4130
,
1444 OPTION_FIX_CN63XXP1
,
1445 OPTION_NO_FIX_CN63XXP1
,
1452 OPTION_CONSTRUCT_FLOATS
,
1453 OPTION_NO_CONSTRUCT_FLOATS
,
1457 OPTION_RELAX_BRANCH
,
1458 OPTION_NO_RELAX_BRANCH
,
1467 OPTION_SINGLE_FLOAT
,
1468 OPTION_DOUBLE_FLOAT
,
1481 OPTION_MVXWORKS_PIC
,
1484 OPTION_NO_ODD_SPREG
,
1488 struct option md_longopts
[] =
1490 /* Options which specify architecture. */
1491 {"march", required_argument
, NULL
, OPTION_MARCH
},
1492 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1493 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1494 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1495 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1496 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1497 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1498 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1499 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1500 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1501 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1502 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1503 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1504 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1505 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1506 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1507 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1508 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1512 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1513 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1514 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1515 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1516 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1517 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1518 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1519 {"mmt", no_argument
, NULL
, OPTION_MT
},
1520 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1521 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1522 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1523 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1524 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1525 {"meva", no_argument
, NULL
, OPTION_EVA
},
1526 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1527 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1528 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1529 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1530 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1531 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1532 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1533 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1534 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1535 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1536 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1540 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1541 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1542 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1543 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1544 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1545 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1546 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1550 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1551 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1552 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1553 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1554 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1555 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1556 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1557 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1558 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1559 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1560 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1561 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1562 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1563 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1564 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1565 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1567 /* Miscellaneous options. */
1568 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1569 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1570 {"break", no_argument
, NULL
, OPTION_BREAK
},
1571 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1572 {"EB", no_argument
, NULL
, OPTION_EB
},
1573 {"EL", no_argument
, NULL
, OPTION_EL
},
1574 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1575 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1576 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1577 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1578 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1579 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1580 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1581 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1582 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1583 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1584 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1585 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1586 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1587 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1588 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1589 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1590 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1591 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1592 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1593 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1594 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument
, NULL
, OPTION_32
},
1601 /* ELF-specific options. */
1602 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1603 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1604 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1605 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1606 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1607 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1608 {"n32", no_argument
, NULL
, OPTION_N32
},
1609 {"64", no_argument
, NULL
, OPTION_64
},
1610 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1611 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1612 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1613 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1614 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1615 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1617 {NULL
, no_argument
, NULL
, 0}
1619 size_t md_longopts_size
= sizeof (md_longopts
);
1621 /* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1626 /* The name of the ASE, used in both the command-line and .set options. */
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64
;
1638 /* The command-line options that turn the ASE on and off. */
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1646 int micromips32_rev
;
1647 int micromips64_rev
;
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1654 /* A table of all supported ASEs. */
1655 static const struct mips_ase mips_ases
[] = {
1656 { "dsp", ASE_DSP
, ASE_DSP64
,
1657 OPTION_DSP
, OPTION_NO_DSP
,
1661 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1662 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1666 { "eva", ASE_EVA
, 0,
1667 OPTION_EVA
, OPTION_NO_EVA
,
1671 { "mcu", ASE_MCU
, 0,
1672 OPTION_MCU
, OPTION_NO_MCU
,
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX
, 0,
1678 OPTION_MDMX
, OPTION_NO_MDMX
,
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D
, 0,
1684 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1689 OPTION_MT
, OPTION_NO_MT
,
1693 { "smartmips", ASE_SMARTMIPS
, 0,
1694 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1698 { "virt", ASE_VIRT
, ASE_VIRT64
,
1699 OPTION_VIRT
, OPTION_NO_VIRT
,
1703 { "msa", ASE_MSA
, ASE_MSA64
,
1704 OPTION_MSA
, OPTION_NO_MSA
,
1708 { "xpa", ASE_XPA
, 0,
1709 OPTION_XPA
, OPTION_NO_XPA
,
1714 /* The set of ASEs that require -mfp64. */
1715 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1717 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1718 static const unsigned int mips_ase_groups
[] = {
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
1739 static const pseudo_typeS mips_pseudo_table
[] =
1741 /* MIPS specific pseudo-ops. */
1742 {"option", s_option
, 0},
1743 {"set", s_mipsset
, 0},
1744 {"rdata", s_change_sec
, 'r'},
1745 {"sdata", s_change_sec
, 's'},
1746 {"livereg", s_ignore
, 0},
1747 {"abicalls", s_abicalls
, 0},
1748 {"cpload", s_cpload
, 0},
1749 {"cpsetup", s_cpsetup
, 0},
1750 {"cplocal", s_cplocal
, 0},
1751 {"cprestore", s_cprestore
, 0},
1752 {"cpreturn", s_cpreturn
, 0},
1753 {"dtprelword", s_dtprelword
, 0},
1754 {"dtpreldword", s_dtpreldword
, 0},
1755 {"tprelword", s_tprelword
, 0},
1756 {"tpreldword", s_tpreldword
, 0},
1757 {"gpvalue", s_gpvalue
, 0},
1758 {"gpword", s_gpword
, 0},
1759 {"gpdword", s_gpdword
, 0},
1760 {"ehword", s_ehword
, 0},
1761 {"cpadd", s_cpadd
, 0},
1762 {"insn", s_insn
, 0},
1764 {"module", s_module
, 0},
1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
1768 {"asciiz", stringer
, 8 + 1},
1769 {"bss", s_change_sec
, 'b'},
1771 {"half", s_cons
, 1},
1772 {"dword", s_cons
, 3},
1773 {"weakext", s_mips_weakext
, 0},
1774 {"origin", s_org
, 0},
1775 {"repeat", s_rept
, 0},
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec
, 'B'},
1780 /* These pseudo-ops are defined in read.c, but must be overridden
1781 here for one reason or another. */
1782 {"align", s_align
, 0},
1783 {"byte", s_cons
, 0},
1784 {"data", s_change_sec
, 'd'},
1785 {"double", s_float_cons
, 'd'},
1786 {"float", s_float_cons
, 'f'},
1787 {"globl", s_mips_globl
, 0},
1788 {"global", s_mips_globl
, 0},
1789 {"hword", s_cons
, 1},
1791 {"long", s_cons
, 2},
1792 {"octa", s_cons
, 4},
1793 {"quad", s_cons
, 3},
1794 {"section", s_change_section
, 0},
1795 {"short", s_cons
, 1},
1796 {"single", s_float_cons
, 'f'},
1797 {"stabd", s_mips_stab
, 'd'},
1798 {"stabn", s_mips_stab
, 'n'},
1799 {"stabs", s_mips_stab
, 's'},
1800 {"text", s_change_sec
, 't'},
1801 {"word", s_cons
, 2},
1803 { "extern", ecoff_directive_extern
, 0},
1808 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
1812 {"aent", s_mips_ent
, 1},
1813 {"bgnb", s_ignore
, 0},
1814 {"end", s_mips_end
, 0},
1815 {"endb", s_ignore
, 0},
1816 {"ent", s_mips_ent
, 0},
1817 {"file", s_mips_file
, 0},
1818 {"fmask", s_mips_mask
, 'F'},
1819 {"frame", s_mips_frame
, 0},
1820 {"loc", s_mips_loc
, 0},
1821 {"mask", s_mips_mask
, 'R'},
1822 {"verstamp", s_ignore
, 0},
1826 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1830 mips_address_bytes (void)
1832 file_mips_check_options ();
1833 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1836 extern void pop_insert (const pseudo_typeS
*);
1839 mips_pop_insert (void)
1841 pop_insert (mips_pseudo_table
);
1842 if (! ECOFF_DEBUGGING
)
1843 pop_insert (mips_nonecoff_pseudo_table
);
1846 /* Symbols labelling the current insn. */
1848 struct insn_label_list
1850 struct insn_label_list
*next
;
1854 static struct insn_label_list
*free_insn_labels
;
1855 #define label_list tc_segment_info_data.labels
1857 static void mips_clear_insn_labels (void);
1858 static void mips_mark_labels (void);
1859 static void mips_compressed_mark_labels (void);
1862 mips_clear_insn_labels (void)
1864 struct insn_label_list
**pl
;
1865 segment_info_type
*si
;
1869 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1872 si
= seg_info (now_seg
);
1873 *pl
= si
->label_list
;
1874 si
->label_list
= NULL
;
1878 /* Mark instruction labels in MIPS16/microMIPS mode. */
1881 mips_mark_labels (void)
1883 if (HAVE_CODE_COMPRESSION
)
1884 mips_compressed_mark_labels ();
1887 static char *expr_end
;
1889 /* An expression in a macro instruction. This is set by mips_ip and
1890 mips16_ip and when populated is always an O_constant. */
1892 static expressionS imm_expr
;
1894 /* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
1899 static expressionS offset_expr
;
1900 static bfd_reloc_code_real_type offset_reloc
[3]
1901 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1903 /* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
1907 static unsigned int forced_insn_length
;
1909 /* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1912 static bfd_boolean mips_assembling_insn
;
1914 /* The pdr segment for per procedure frame/regmask info. Not used for
1917 static segT pdr_seg
;
1919 /* The default target format to use. */
1921 #if defined (TE_FreeBSD)
1922 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923 #elif defined (TE_TMIPS)
1924 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1926 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1930 mips_target_format (void)
1932 switch (OUTPUT_FLAVOR
)
1934 case bfd_target_elf_flavour
:
1936 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1941 return (target_big_endian
1942 ? (HAVE_64BIT_OBJECTS
1943 ? ELF_TARGET ("elf64-", "big")
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
1947 : (HAVE_64BIT_OBJECTS
1948 ? ELF_TARGET ("elf64-", "little")
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
1958 /* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1964 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1967 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1970 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1973 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts
.micromips
)
1980 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1986 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1989 mips_ase_mask (unsigned int flags
)
1993 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1994 if (flags
& mips_ase_groups
[i
])
1995 flags
|= mips_ase_groups
[i
];
1999 /* Check whether the current ISA supports ASE. Issue a warning if
2003 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2007 static unsigned int warned_isa
;
2008 static unsigned int warned_fp32
;
2010 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2011 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2013 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2014 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2015 && (warned_isa
& ase
->flags
) != ase
->flags
)
2017 warned_isa
|= ase
->flags
;
2018 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2019 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2021 as_warn (_("the %d-bit %s architecture does not support the"
2022 " `%s' extension"), size
, base
, ase
->name
);
2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2025 ase
->name
, base
, size
, min_rev
);
2027 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2028 && (warned_isa
& ase
->flags
) != ase
->flags
)
2030 warned_isa
|= ase
->flags
;
2031 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2032 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase
->name
, base
, size
, ase
->rem_rev
);
2037 if ((ase
->flags
& FP64_ASES
)
2038 && mips_opts
.fp
!= 64
2039 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2041 warned_fp32
|= ase
->flags
;
2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2046 /* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2050 mips_check_isa_supports_ases (void)
2052 unsigned int i
, mask
;
2054 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2056 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2057 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2058 mips_check_isa_supports_ase (&mips_ases
[i
]);
2062 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2066 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2067 bfd_boolean enabled_p
)
2071 mask
= mips_ase_mask (ase
->flags
);
2074 opts
->ase
|= ase
->flags
;
2078 /* Return the ASE called NAME, or null if none. */
2080 static const struct mips_ase
*
2081 mips_lookup_ase (const char *name
)
2085 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2086 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2087 return &mips_ases
[i
];
2091 /* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2093 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2094 major opcode) will require further modifications to the opcode
2097 static inline unsigned int
2098 micromips_insn_length (const struct mips_opcode
*mo
)
2100 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2103 /* Return the length of MIPS16 instruction OPCODE. */
2105 static inline unsigned int
2106 mips16_opcode_length (unsigned long opcode
)
2108 return (opcode
>> 16) == 0 ? 2 : 4;
2111 /* Return the length of instruction INSN. */
2113 static inline unsigned int
2114 insn_length (const struct mips_cl_insn
*insn
)
2116 if (mips_opts
.micromips
)
2117 return micromips_insn_length (insn
->insn_mo
);
2118 else if (mips_opts
.mips16
)
2119 return mips16_opcode_length (insn
->insn_opcode
);
2124 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2127 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2132 insn
->insn_opcode
= mo
->match
;
2135 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2136 insn
->fixp
[i
] = NULL
;
2137 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2138 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2139 insn
->mips16_absolute_jump_p
= 0;
2140 insn
->complete_p
= 0;
2141 insn
->cleared_p
= 0;
2144 /* Get a list of all the operands in INSN. */
2146 static const struct mips_operand_array
*
2147 insn_operands (const struct mips_cl_insn
*insn
)
2149 if (insn
->insn_mo
>= &mips_opcodes
[0]
2150 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2151 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2153 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2154 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2155 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2157 if (insn
->insn_mo
>= µmips_opcodes
[0]
2158 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2159 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2164 /* Get a description of operand OPNO of INSN. */
2166 static const struct mips_operand
*
2167 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2169 const struct mips_operand_array
*operands
;
2171 operands
= insn_operands (insn
);
2172 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2174 return operands
->operand
[opno
];
2177 /* Install UVAL as the value of OPERAND in INSN. */
2180 insn_insert_operand (struct mips_cl_insn
*insn
,
2181 const struct mips_operand
*operand
, unsigned int uval
)
2183 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2186 /* Extract the value of OPERAND from INSN. */
2188 static inline unsigned
2189 insn_extract_operand (const struct mips_cl_insn
*insn
,
2190 const struct mips_operand
*operand
)
2192 return mips_extract_operand (operand
, insn
->insn_opcode
);
2195 /* Record the current MIPS16/microMIPS mode in now_seg. */
2198 mips_record_compressed_mode (void)
2200 segment_info_type
*si
;
2202 si
= seg_info (now_seg
);
2203 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2204 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2205 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2206 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2209 /* Read a standard MIPS instruction from BUF. */
2211 static unsigned long
2212 read_insn (char *buf
)
2214 if (target_big_endian
)
2215 return bfd_getb32 ((bfd_byte
*) buf
);
2217 return bfd_getl32 ((bfd_byte
*) buf
);
2220 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2224 write_insn (char *buf
, unsigned int insn
)
2226 md_number_to_chars (buf
, insn
, 4);
2230 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2231 has length LENGTH. */
2233 static unsigned long
2234 read_compressed_insn (char *buf
, unsigned int length
)
2240 for (i
= 0; i
< length
; i
+= 2)
2243 if (target_big_endian
)
2244 insn
|= bfd_getb16 ((char *) buf
);
2246 insn
|= bfd_getl16 ((char *) buf
);
2252 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2253 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2256 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2260 for (i
= 0; i
< length
; i
+= 2)
2261 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2262 return buf
+ length
;
2265 /* Install INSN at the location specified by its "frag" and "where" fields. */
2268 install_insn (const struct mips_cl_insn
*insn
)
2270 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2271 if (HAVE_CODE_COMPRESSION
)
2272 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2274 write_insn (f
, insn
->insn_opcode
);
2275 mips_record_compressed_mode ();
2278 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2279 and install the opcode in the new location. */
2282 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2287 insn
->where
= where
;
2288 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2289 if (insn
->fixp
[i
] != NULL
)
2291 insn
->fixp
[i
]->fx_frag
= frag
;
2292 insn
->fixp
[i
]->fx_where
= where
;
2294 install_insn (insn
);
2297 /* Add INSN to the end of the output. */
2300 add_fixed_insn (struct mips_cl_insn
*insn
)
2302 char *f
= frag_more (insn_length (insn
));
2303 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2306 /* Start a variant frag and move INSN to the start of the variant part,
2307 marking it as fixed. The other arguments are as for frag_var. */
2310 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2311 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2313 frag_grow (max_chars
);
2314 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2316 frag_var (rs_machine_dependent
, max_chars
, var
,
2317 subtype
, symbol
, offset
, NULL
);
2320 /* Insert N copies of INSN into the history buffer, starting at
2321 position FIRST. Neither FIRST nor N need to be clipped. */
2324 insert_into_history (unsigned int first
, unsigned int n
,
2325 const struct mips_cl_insn
*insn
)
2327 if (mips_relax
.sequence
!= 2)
2331 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2333 history
[i
] = history
[i
- n
];
2339 /* Clear the error in insn_error. */
2342 clear_insn_error (void)
2344 memset (&insn_error
, 0, sizeof (insn_error
));
2347 /* Possibly record error message MSG for the current instruction.
2348 If the error is about a particular argument, ARGNUM is the 1-based
2349 number of that argument, otherwise it is 0. FORMAT is the format
2350 of MSG. Return true if MSG was used, false if the current message
2354 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2359 /* Give priority to errors against specific arguments, and to
2360 the first whole-instruction message. */
2366 /* Keep insn_error if it is against a later argument. */
2367 if (argnum
< insn_error
.min_argnum
)
2370 /* If both errors are against the same argument but are different,
2371 give up on reporting a specific error for this argument.
2372 See the comment about mips_insn_error for details. */
2373 if (argnum
== insn_error
.min_argnum
2375 && strcmp (insn_error
.msg
, msg
) != 0)
2378 insn_error
.min_argnum
+= 1;
2382 insn_error
.min_argnum
= argnum
;
2383 insn_error
.format
= format
;
2384 insn_error
.msg
= msg
;
2388 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2389 as for set_insn_error_format. */
2392 set_insn_error (int argnum
, const char *msg
)
2394 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2397 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2398 as for set_insn_error_format. */
2401 set_insn_error_i (int argnum
, const char *msg
, int i
)
2403 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2407 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2408 are as for set_insn_error_format. */
2411 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2413 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2415 insn_error
.u
.ss
[0] = s1
;
2416 insn_error
.u
.ss
[1] = s2
;
2420 /* Report the error in insn_error, which is against assembly code STR. */
2423 report_insn_error (const char *str
)
2427 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2428 switch (insn_error
.format
)
2435 as_bad (msg
, insn_error
.u
.i
, str
);
2439 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2444 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2445 the idea is to make it obvious at a glance that each errata is
2449 init_vr4120_conflicts (void)
2451 #define CONFLICT(FIRST, SECOND) \
2452 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2454 /* Errata 21 - [D]DIV[U] after [D]MACC */
2455 CONFLICT (MACC
, DIV
);
2456 CONFLICT (DMACC
, DIV
);
2458 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2459 CONFLICT (DMULT
, DMULT
);
2460 CONFLICT (DMULT
, DMACC
);
2461 CONFLICT (DMACC
, DMULT
);
2462 CONFLICT (DMACC
, DMACC
);
2464 /* Errata 24 - MT{LO,HI} after [D]MACC */
2465 CONFLICT (MACC
, MTHILO
);
2466 CONFLICT (DMACC
, MTHILO
);
2468 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2469 instruction is executed immediately after a MACC or DMACC
2470 instruction, the result of [either instruction] is incorrect." */
2471 CONFLICT (MACC
, MULT
);
2472 CONFLICT (MACC
, DMULT
);
2473 CONFLICT (DMACC
, MULT
);
2474 CONFLICT (DMACC
, DMULT
);
2476 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2477 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2478 DDIV or DDIVU instruction, the result of the MACC or
2479 DMACC instruction is incorrect.". */
2480 CONFLICT (DMULT
, MACC
);
2481 CONFLICT (DMULT
, DMACC
);
2482 CONFLICT (DIV
, MACC
);
2483 CONFLICT (DIV
, DMACC
);
2493 #define RNUM_MASK 0x00000ff
2494 #define RTYPE_MASK 0x0ffff00
2495 #define RTYPE_NUM 0x0000100
2496 #define RTYPE_FPU 0x0000200
2497 #define RTYPE_FCC 0x0000400
2498 #define RTYPE_VEC 0x0000800
2499 #define RTYPE_GP 0x0001000
2500 #define RTYPE_CP0 0x0002000
2501 #define RTYPE_PC 0x0004000
2502 #define RTYPE_ACC 0x0008000
2503 #define RTYPE_CCC 0x0010000
2504 #define RTYPE_VI 0x0020000
2505 #define RTYPE_VF 0x0040000
2506 #define RTYPE_R5900_I 0x0080000
2507 #define RTYPE_R5900_Q 0x0100000
2508 #define RTYPE_R5900_R 0x0200000
2509 #define RTYPE_R5900_ACC 0x0400000
2510 #define RTYPE_MSA 0x0800000
2511 #define RWARN 0x8000000
2513 #define GENERIC_REGISTER_NUMBERS \
2514 {"$0", RTYPE_NUM | 0}, \
2515 {"$1", RTYPE_NUM | 1}, \
2516 {"$2", RTYPE_NUM | 2}, \
2517 {"$3", RTYPE_NUM | 3}, \
2518 {"$4", RTYPE_NUM | 4}, \
2519 {"$5", RTYPE_NUM | 5}, \
2520 {"$6", RTYPE_NUM | 6}, \
2521 {"$7", RTYPE_NUM | 7}, \
2522 {"$8", RTYPE_NUM | 8}, \
2523 {"$9", RTYPE_NUM | 9}, \
2524 {"$10", RTYPE_NUM | 10}, \
2525 {"$11", RTYPE_NUM | 11}, \
2526 {"$12", RTYPE_NUM | 12}, \
2527 {"$13", RTYPE_NUM | 13}, \
2528 {"$14", RTYPE_NUM | 14}, \
2529 {"$15", RTYPE_NUM | 15}, \
2530 {"$16", RTYPE_NUM | 16}, \
2531 {"$17", RTYPE_NUM | 17}, \
2532 {"$18", RTYPE_NUM | 18}, \
2533 {"$19", RTYPE_NUM | 19}, \
2534 {"$20", RTYPE_NUM | 20}, \
2535 {"$21", RTYPE_NUM | 21}, \
2536 {"$22", RTYPE_NUM | 22}, \
2537 {"$23", RTYPE_NUM | 23}, \
2538 {"$24", RTYPE_NUM | 24}, \
2539 {"$25", RTYPE_NUM | 25}, \
2540 {"$26", RTYPE_NUM | 26}, \
2541 {"$27", RTYPE_NUM | 27}, \
2542 {"$28", RTYPE_NUM | 28}, \
2543 {"$29", RTYPE_NUM | 29}, \
2544 {"$30", RTYPE_NUM | 30}, \
2545 {"$31", RTYPE_NUM | 31}
2547 #define FPU_REGISTER_NAMES \
2548 {"$f0", RTYPE_FPU | 0}, \
2549 {"$f1", RTYPE_FPU | 1}, \
2550 {"$f2", RTYPE_FPU | 2}, \
2551 {"$f3", RTYPE_FPU | 3}, \
2552 {"$f4", RTYPE_FPU | 4}, \
2553 {"$f5", RTYPE_FPU | 5}, \
2554 {"$f6", RTYPE_FPU | 6}, \
2555 {"$f7", RTYPE_FPU | 7}, \
2556 {"$f8", RTYPE_FPU | 8}, \
2557 {"$f9", RTYPE_FPU | 9}, \
2558 {"$f10", RTYPE_FPU | 10}, \
2559 {"$f11", RTYPE_FPU | 11}, \
2560 {"$f12", RTYPE_FPU | 12}, \
2561 {"$f13", RTYPE_FPU | 13}, \
2562 {"$f14", RTYPE_FPU | 14}, \
2563 {"$f15", RTYPE_FPU | 15}, \
2564 {"$f16", RTYPE_FPU | 16}, \
2565 {"$f17", RTYPE_FPU | 17}, \
2566 {"$f18", RTYPE_FPU | 18}, \
2567 {"$f19", RTYPE_FPU | 19}, \
2568 {"$f20", RTYPE_FPU | 20}, \
2569 {"$f21", RTYPE_FPU | 21}, \
2570 {"$f22", RTYPE_FPU | 22}, \
2571 {"$f23", RTYPE_FPU | 23}, \
2572 {"$f24", RTYPE_FPU | 24}, \
2573 {"$f25", RTYPE_FPU | 25}, \
2574 {"$f26", RTYPE_FPU | 26}, \
2575 {"$f27", RTYPE_FPU | 27}, \
2576 {"$f28", RTYPE_FPU | 28}, \
2577 {"$f29", RTYPE_FPU | 29}, \
2578 {"$f30", RTYPE_FPU | 30}, \
2579 {"$f31", RTYPE_FPU | 31}
2581 #define FPU_CONDITION_CODE_NAMES \
2582 {"$fcc0", RTYPE_FCC | 0}, \
2583 {"$fcc1", RTYPE_FCC | 1}, \
2584 {"$fcc2", RTYPE_FCC | 2}, \
2585 {"$fcc3", RTYPE_FCC | 3}, \
2586 {"$fcc4", RTYPE_FCC | 4}, \
2587 {"$fcc5", RTYPE_FCC | 5}, \
2588 {"$fcc6", RTYPE_FCC | 6}, \
2589 {"$fcc7", RTYPE_FCC | 7}
2591 #define COPROC_CONDITION_CODE_NAMES \
2592 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2593 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2594 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2595 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2596 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2597 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2598 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2599 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2601 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2602 {"$a4", RTYPE_GP | 8}, \
2603 {"$a5", RTYPE_GP | 9}, \
2604 {"$a6", RTYPE_GP | 10}, \
2605 {"$a7", RTYPE_GP | 11}, \
2606 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2607 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2608 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2609 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2610 {"$t0", RTYPE_GP | 12}, \
2611 {"$t1", RTYPE_GP | 13}, \
2612 {"$t2", RTYPE_GP | 14}, \
2613 {"$t3", RTYPE_GP | 15}
2615 #define O32_SYMBOLIC_REGISTER_NAMES \
2616 {"$t0", RTYPE_GP | 8}, \
2617 {"$t1", RTYPE_GP | 9}, \
2618 {"$t2", RTYPE_GP | 10}, \
2619 {"$t3", RTYPE_GP | 11}, \
2620 {"$t4", RTYPE_GP | 12}, \
2621 {"$t5", RTYPE_GP | 13}, \
2622 {"$t6", RTYPE_GP | 14}, \
2623 {"$t7", RTYPE_GP | 15}, \
2624 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2625 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2626 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2627 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2629 /* Remaining symbolic register names */
2630 #define SYMBOLIC_REGISTER_NAMES \
2631 {"$zero", RTYPE_GP | 0}, \
2632 {"$at", RTYPE_GP | 1}, \
2633 {"$AT", RTYPE_GP | 1}, \
2634 {"$v0", RTYPE_GP | 2}, \
2635 {"$v1", RTYPE_GP | 3}, \
2636 {"$a0", RTYPE_GP | 4}, \
2637 {"$a1", RTYPE_GP | 5}, \
2638 {"$a2", RTYPE_GP | 6}, \
2639 {"$a3", RTYPE_GP | 7}, \
2640 {"$s0", RTYPE_GP | 16}, \
2641 {"$s1", RTYPE_GP | 17}, \
2642 {"$s2", RTYPE_GP | 18}, \
2643 {"$s3", RTYPE_GP | 19}, \
2644 {"$s4", RTYPE_GP | 20}, \
2645 {"$s5", RTYPE_GP | 21}, \
2646 {"$s6", RTYPE_GP | 22}, \
2647 {"$s7", RTYPE_GP | 23}, \
2648 {"$t8", RTYPE_GP | 24}, \
2649 {"$t9", RTYPE_GP | 25}, \
2650 {"$k0", RTYPE_GP | 26}, \
2651 {"$kt0", RTYPE_GP | 26}, \
2652 {"$k1", RTYPE_GP | 27}, \
2653 {"$kt1", RTYPE_GP | 27}, \
2654 {"$gp", RTYPE_GP | 28}, \
2655 {"$sp", RTYPE_GP | 29}, \
2656 {"$s8", RTYPE_GP | 30}, \
2657 {"$fp", RTYPE_GP | 30}, \
2658 {"$ra", RTYPE_GP | 31}
2660 #define MIPS16_SPECIAL_REGISTER_NAMES \
2661 {"$pc", RTYPE_PC | 0}
2663 #define MDMX_VECTOR_REGISTER_NAMES \
2664 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2665 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2666 {"$v2", RTYPE_VEC | 2}, \
2667 {"$v3", RTYPE_VEC | 3}, \
2668 {"$v4", RTYPE_VEC | 4}, \
2669 {"$v5", RTYPE_VEC | 5}, \
2670 {"$v6", RTYPE_VEC | 6}, \
2671 {"$v7", RTYPE_VEC | 7}, \
2672 {"$v8", RTYPE_VEC | 8}, \
2673 {"$v9", RTYPE_VEC | 9}, \
2674 {"$v10", RTYPE_VEC | 10}, \
2675 {"$v11", RTYPE_VEC | 11}, \
2676 {"$v12", RTYPE_VEC | 12}, \
2677 {"$v13", RTYPE_VEC | 13}, \
2678 {"$v14", RTYPE_VEC | 14}, \
2679 {"$v15", RTYPE_VEC | 15}, \
2680 {"$v16", RTYPE_VEC | 16}, \
2681 {"$v17", RTYPE_VEC | 17}, \
2682 {"$v18", RTYPE_VEC | 18}, \
2683 {"$v19", RTYPE_VEC | 19}, \
2684 {"$v20", RTYPE_VEC | 20}, \
2685 {"$v21", RTYPE_VEC | 21}, \
2686 {"$v22", RTYPE_VEC | 22}, \
2687 {"$v23", RTYPE_VEC | 23}, \
2688 {"$v24", RTYPE_VEC | 24}, \
2689 {"$v25", RTYPE_VEC | 25}, \
2690 {"$v26", RTYPE_VEC | 26}, \
2691 {"$v27", RTYPE_VEC | 27}, \
2692 {"$v28", RTYPE_VEC | 28}, \
2693 {"$v29", RTYPE_VEC | 29}, \
2694 {"$v30", RTYPE_VEC | 30}, \
2695 {"$v31", RTYPE_VEC | 31}
2697 #define R5900_I_NAMES \
2698 {"$I", RTYPE_R5900_I | 0}
2700 #define R5900_Q_NAMES \
2701 {"$Q", RTYPE_R5900_Q | 0}
2703 #define R5900_R_NAMES \
2704 {"$R", RTYPE_R5900_R | 0}
2706 #define R5900_ACC_NAMES \
2707 {"$ACC", RTYPE_R5900_ACC | 0 }
2709 #define MIPS_DSP_ACCUMULATOR_NAMES \
2710 {"$ac0", RTYPE_ACC | 0}, \
2711 {"$ac1", RTYPE_ACC | 1}, \
2712 {"$ac2", RTYPE_ACC | 2}, \
2713 {"$ac3", RTYPE_ACC | 3}
2715 static const struct regname reg_names
[] = {
2716 GENERIC_REGISTER_NUMBERS
,
2718 FPU_CONDITION_CODE_NAMES
,
2719 COPROC_CONDITION_CODE_NAMES
,
2721 /* The $txx registers depends on the abi,
2722 these will be added later into the symbol table from
2723 one of the tables below once mips_abi is set after
2724 parsing of arguments from the command line. */
2725 SYMBOLIC_REGISTER_NAMES
,
2727 MIPS16_SPECIAL_REGISTER_NAMES
,
2728 MDMX_VECTOR_REGISTER_NAMES
,
2733 MIPS_DSP_ACCUMULATOR_NAMES
,
2737 static const struct regname reg_names_o32
[] = {
2738 O32_SYMBOLIC_REGISTER_NAMES
,
2742 static const struct regname reg_names_n32n64
[] = {
2743 N32N64_SYMBOLIC_REGISTER_NAMES
,
2747 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2748 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2749 of these register symbols, return the associated vector register,
2750 otherwise return SYMVAL itself. */
2753 mips_prefer_vec_regno (unsigned int symval
)
2755 if ((symval
& -2) == (RTYPE_GP
| 2))
2756 return RTYPE_VEC
| (symval
& 1);
2760 /* Return true if string [S, E) is a valid register name, storing its
2761 symbol value in *SYMVAL_PTR if so. */
2764 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2769 /* Terminate name. */
2773 /* Look up the name. */
2774 symbol
= symbol_find (s
);
2777 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2780 *symval_ptr
= S_GET_VALUE (symbol
);
2784 /* Return true if the string at *SPTR is a valid register name. Allow it
2785 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2788 When returning true, move *SPTR past the register, store the
2789 register's symbol value in *SYMVAL_PTR and the channel mask in
2790 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2791 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2792 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2795 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2796 unsigned int *channels_ptr
)
2800 unsigned int channels
, symval
, bit
;
2802 /* Find end of name. */
2804 if (is_name_beginner (*e
))
2806 while (is_part_of_name (*e
))
2810 if (!mips_parse_register_1 (s
, e
, &symval
))
2815 /* Eat characters from the end of the string that are valid
2816 channel suffixes. The preceding register must be $ACC or
2817 end with a digit, so there is no ambiguity. */
2820 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2821 if (m
> s
&& m
[-1] == *q
)
2828 || !mips_parse_register_1 (s
, m
, &symval
)
2829 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2834 *symval_ptr
= symval
;
2836 *channels_ptr
= channels
;
2840 /* Check if SPTR points at a valid register specifier according to TYPES.
2841 If so, then return 1, advance S to consume the specifier and store
2842 the register's number in REGNOP, otherwise return 0. */
2845 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2849 if (mips_parse_register (s
, ®no
, NULL
))
2851 if (types
& RTYPE_VEC
)
2852 regno
= mips_prefer_vec_regno (regno
);
2861 as_warn (_("unrecognized register name `%s'"), *s
);
2866 return regno
<= RNUM_MASK
;
2869 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2870 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2873 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2878 for (i
= 0; i
< 4; i
++)
2879 if (*s
== "xyzw"[i
])
2881 *channels
|= 1 << (3 - i
);
2887 /* Token types for parsed operand lists. */
2888 enum mips_operand_token_type
{
2889 /* A plain register, e.g. $f2. */
2892 /* A 4-bit XYZW channel mask. */
2895 /* A constant vector index, e.g. [1]. */
2898 /* A register vector index, e.g. [$2]. */
2901 /* A continuous range of registers, e.g. $s0-$s4. */
2904 /* A (possibly relocated) expression. */
2907 /* A floating-point value. */
2910 /* A single character. This can be '(', ')' or ',', but '(' only appears
2914 /* A doubled character, either "--" or "++". */
2917 /* The end of the operand list. */
2921 /* A parsed operand token. */
2922 struct mips_operand_token
2924 /* The type of token. */
2925 enum mips_operand_token_type type
;
2928 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2931 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2932 unsigned int channels
;
2934 /* The integer value of an OT_INTEGER_INDEX. */
2937 /* The two register symbol values involved in an OT_REG_RANGE. */
2939 unsigned int regno1
;
2940 unsigned int regno2
;
2943 /* The value of an OT_INTEGER. The value is represented as an
2944 expression and the relocation operators that were applied to
2945 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2946 relocation operators were used. */
2949 bfd_reloc_code_real_type relocs
[3];
2952 /* The binary data for an OT_FLOAT constant, and the number of bytes
2955 unsigned char data
[8];
2959 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2964 /* An obstack used to construct lists of mips_operand_tokens. */
2965 static struct obstack mips_operand_tokens
;
2967 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2970 mips_add_token (struct mips_operand_token
*token
,
2971 enum mips_operand_token_type type
)
2974 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2977 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2978 and OT_REG tokens for them if so, and return a pointer to the first
2979 unconsumed character. Return null otherwise. */
2982 mips_parse_base_start (char *s
)
2984 struct mips_operand_token token
;
2985 unsigned int regno
, channels
;
2986 bfd_boolean decrement_p
;
2992 SKIP_SPACE_TABS (s
);
2994 /* Only match "--" as part of a base expression. In other contexts "--X"
2995 is a double negative. */
2996 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3000 SKIP_SPACE_TABS (s
);
3003 /* Allow a channel specifier because that leads to better error messages
3004 than treating something like "$vf0x++" as an expression. */
3005 if (!mips_parse_register (&s
, ®no
, &channels
))
3009 mips_add_token (&token
, OT_CHAR
);
3014 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3017 token
.u
.regno
= regno
;
3018 mips_add_token (&token
, OT_REG
);
3022 token
.u
.channels
= channels
;
3023 mips_add_token (&token
, OT_CHANNELS
);
3026 /* For consistency, only match "++" as part of base expressions too. */
3027 SKIP_SPACE_TABS (s
);
3028 if (s
[0] == '+' && s
[1] == '+')
3032 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3038 /* Parse one or more tokens from S. Return a pointer to the first
3039 unconsumed character on success. Return null if an error was found
3040 and store the error text in insn_error. FLOAT_FORMAT is as for
3041 mips_parse_arguments. */
3044 mips_parse_argument_token (char *s
, char float_format
)
3046 char *end
, *save_in
, *err
;
3047 unsigned int regno1
, regno2
, channels
;
3048 struct mips_operand_token token
;
3050 /* First look for "($reg", since we want to treat that as an
3051 OT_CHAR and OT_REG rather than an expression. */
3052 end
= mips_parse_base_start (s
);
3056 /* Handle other characters that end up as OT_CHARs. */
3057 if (*s
== ')' || *s
== ',')
3060 mips_add_token (&token
, OT_CHAR
);
3065 /* Handle tokens that start with a register. */
3066 if (mips_parse_register (&s
, ®no1
, &channels
))
3070 /* A register and a VU0 channel suffix. */
3071 token
.u
.regno
= regno1
;
3072 mips_add_token (&token
, OT_REG
);
3074 token
.u
.channels
= channels
;
3075 mips_add_token (&token
, OT_CHANNELS
);
3079 SKIP_SPACE_TABS (s
);
3082 /* A register range. */
3084 SKIP_SPACE_TABS (s
);
3085 if (!mips_parse_register (&s
, ®no2
, NULL
))
3087 set_insn_error (0, _("invalid register range"));
3091 token
.u
.reg_range
.regno1
= regno1
;
3092 token
.u
.reg_range
.regno2
= regno2
;
3093 mips_add_token (&token
, OT_REG_RANGE
);
3097 /* Add the register itself. */
3098 token
.u
.regno
= regno1
;
3099 mips_add_token (&token
, OT_REG
);
3101 /* Check for a vector index. */
3105 SKIP_SPACE_TABS (s
);
3106 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3107 mips_add_token (&token
, OT_REG_INDEX
);
3110 expressionS element
;
3112 my_getExpression (&element
, s
);
3113 if (element
.X_op
!= O_constant
)
3115 set_insn_error (0, _("vector element must be constant"));
3119 token
.u
.index
= element
.X_add_number
;
3120 mips_add_token (&token
, OT_INTEGER_INDEX
);
3122 SKIP_SPACE_TABS (s
);
3125 set_insn_error (0, _("missing `]'"));
3135 /* First try to treat expressions as floats. */
3136 save_in
= input_line_pointer
;
3137 input_line_pointer
= s
;
3138 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3139 &token
.u
.flt
.length
);
3140 end
= input_line_pointer
;
3141 input_line_pointer
= save_in
;
3144 set_insn_error (0, err
);
3149 mips_add_token (&token
, OT_FLOAT
);
3154 /* Treat everything else as an integer expression. */
3155 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3156 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3157 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3158 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3160 mips_add_token (&token
, OT_INTEGER
);
3164 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3165 if expressions should be treated as 32-bit floating-point constants,
3166 'd' if they should be treated as 64-bit floating-point constants,
3167 or 0 if they should be treated as integer expressions (the usual case).
3169 Return a list of tokens on success, otherwise return 0. The caller
3170 must obstack_free the list after use. */
3172 static struct mips_operand_token
*
3173 mips_parse_arguments (char *s
, char float_format
)
3175 struct mips_operand_token token
;
3177 SKIP_SPACE_TABS (s
);
3180 s
= mips_parse_argument_token (s
, float_format
);
3183 obstack_free (&mips_operand_tokens
,
3184 obstack_finish (&mips_operand_tokens
));
3187 SKIP_SPACE_TABS (s
);
3189 mips_add_token (&token
, OT_END
);
3190 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3193 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3194 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3197 is_opcode_valid (const struct mips_opcode
*mo
)
3199 int isa
= mips_opts
.isa
;
3200 int ase
= mips_opts
.ase
;
3204 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3205 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3206 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3207 ase
|= mips_ases
[i
].flags64
;
3209 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3212 /* Check whether the instruction or macro requires single-precision or
3213 double-precision floating-point support. Note that this information is
3214 stored differently in the opcode table for insns and macros. */
3215 if (mo
->pinfo
== INSN_MACRO
)
3217 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3218 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3222 fp_s
= mo
->pinfo
& FP_S
;
3223 fp_d
= mo
->pinfo
& FP_D
;
3226 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3229 if (fp_s
&& mips_opts
.soft_float
)
3235 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3236 selected ISA and architecture. */
3239 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3241 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3244 /* Return TRUE if the size of the microMIPS opcode MO matches one
3245 explicitly requested. Always TRUE in the standard MIPS mode. */
3248 is_size_valid (const struct mips_opcode
*mo
)
3250 if (!mips_opts
.micromips
)
3253 if (mips_opts
.insn32
)
3255 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3257 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3260 if (!forced_insn_length
)
3262 if (mo
->pinfo
== INSN_MACRO
)
3264 return forced_insn_length
== micromips_insn_length (mo
);
3267 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3268 of the preceding instruction. Always TRUE in the standard MIPS mode.
3270 We don't accept macros in 16-bit delay slots to avoid a case where
3271 a macro expansion fails because it relies on a preceding 32-bit real
3272 instruction to have matched and does not handle the operands correctly.
3273 The only macros that may expand to 16-bit instructions are JAL that
3274 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3275 and BGT (that likewise cannot be placed in a delay slot) that decay to
3276 a NOP. In all these cases the macros precede any corresponding real
3277 instruction definitions in the opcode table, so they will match in the
3278 second pass where the size of the delay slot is ignored and therefore
3279 produce correct code. */
3282 is_delay_slot_valid (const struct mips_opcode
*mo
)
3284 if (!mips_opts
.micromips
)
3287 if (mo
->pinfo
== INSN_MACRO
)
3288 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3289 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3290 && micromips_insn_length (mo
) != 4)
3292 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3293 && micromips_insn_length (mo
) != 2)
3299 /* For consistency checking, verify that all bits of OPCODE are specified
3300 either by the match/mask part of the instruction definition, or by the
3301 operand list. Also build up a list of operands in OPERANDS.
3303 INSN_BITS says which bits of the instruction are significant.
3304 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3305 provides the mips_operand description of each operand. DECODE_OPERAND
3306 is null for MIPS16 instructions. */
3309 validate_mips_insn (const struct mips_opcode
*opcode
,
3310 unsigned long insn_bits
,
3311 const struct mips_operand
*(*decode_operand
) (const char *),
3312 struct mips_operand_array
*operands
)
3315 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3316 const struct mips_operand
*operand
;
3318 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3319 if ((mask
& opcode
->match
) != opcode
->match
)
3321 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3322 opcode
->name
, opcode
->args
);
3327 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3328 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3329 for (s
= opcode
->args
; *s
; ++s
)
3342 if (!decode_operand
)
3343 operand
= decode_mips16_operand (*s
, FALSE
);
3345 operand
= decode_operand (s
);
3346 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3348 as_bad (_("internal: unknown operand type: %s %s"),
3349 opcode
->name
, opcode
->args
);
3352 gas_assert (opno
< MAX_OPERANDS
);
3353 operands
->operand
[opno
] = operand
;
3354 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3356 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3357 if (operand
->type
== OP_MDMX_IMM_REG
)
3358 /* Bit 5 is the format selector (OB vs QH). The opcode table
3359 has separate entries for each format. */
3360 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3361 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3362 used_bits
&= ~(mask
& 0x700);
3364 /* Skip prefix characters. */
3365 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3370 doubled
= used_bits
& mask
& insn_bits
;
3373 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3374 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3378 undefined
= ~used_bits
& insn_bits
;
3379 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3381 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3382 undefined
, opcode
->name
, opcode
->args
);
3385 used_bits
&= ~insn_bits
;
3388 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3389 used_bits
, opcode
->name
, opcode
->args
);
3395 /* The MIPS16 version of validate_mips_insn. */
3398 validate_mips16_insn (const struct mips_opcode
*opcode
,
3399 struct mips_operand_array
*operands
)
3401 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3403 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3404 instruction. Use TMP to describe the full instruction. */
3405 struct mips_opcode tmp
;
3410 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3412 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3415 /* The microMIPS version of validate_mips_insn. */
3418 validate_micromips_insn (const struct mips_opcode
*opc
,
3419 struct mips_operand_array
*operands
)
3421 unsigned long insn_bits
;
3422 unsigned long major
;
3423 unsigned int length
;
3425 if (opc
->pinfo
== INSN_MACRO
)
3426 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3429 length
= micromips_insn_length (opc
);
3430 if (length
!= 2 && length
!= 4)
3432 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3433 "%s %s"), length
, opc
->name
, opc
->args
);
3436 major
= opc
->match
>> (10 + 8 * (length
- 2));
3437 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3438 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3440 as_bad (_("internal error: bad microMIPS opcode "
3441 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3445 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3446 insn_bits
= 1 << 4 * length
;
3447 insn_bits
<<= 4 * length
;
3449 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3453 /* This function is called once, at assembler startup time. It should set up
3454 all the tables, etc. that the MD part of the assembler will need. */
3459 const char *retval
= NULL
;
3463 if (mips_pic
!= NO_PIC
)
3465 if (g_switch_seen
&& g_switch_value
!= 0)
3466 as_bad (_("-G may not be used in position-independent code"));
3470 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3471 as_warn (_("could not set architecture and machine"));
3473 op_hash
= hash_new ();
3475 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3476 for (i
= 0; i
< NUMOPCODES
;)
3478 const char *name
= mips_opcodes
[i
].name
;
3480 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3483 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3484 mips_opcodes
[i
].name
, retval
);
3485 /* Probably a memory allocation problem? Give up now. */
3486 as_fatal (_("broken assembler, no assembly attempted"));
3490 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3491 decode_mips_operand
, &mips_operands
[i
]))
3493 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3495 create_insn (&nop_insn
, mips_opcodes
+ i
);
3496 if (mips_fix_loongson2f_nop
)
3497 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3498 nop_insn
.fixed_p
= 1;
3502 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3505 mips16_op_hash
= hash_new ();
3506 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3507 bfd_mips16_num_opcodes
);
3510 while (i
< bfd_mips16_num_opcodes
)
3512 const char *name
= mips16_opcodes
[i
].name
;
3514 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3516 as_fatal (_("internal: can't hash `%s': %s"),
3517 mips16_opcodes
[i
].name
, retval
);
3520 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3522 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3524 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3525 mips16_nop_insn
.fixed_p
= 1;
3529 while (i
< bfd_mips16_num_opcodes
3530 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3533 micromips_op_hash
= hash_new ();
3534 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3535 bfd_micromips_num_opcodes
);
3538 while (i
< bfd_micromips_num_opcodes
)
3540 const char *name
= micromips_opcodes
[i
].name
;
3542 retval
= hash_insert (micromips_op_hash
, name
,
3543 (void *) µmips_opcodes
[i
]);
3545 as_fatal (_("internal: can't hash `%s': %s"),
3546 micromips_opcodes
[i
].name
, retval
);
3549 struct mips_cl_insn
*micromips_nop_insn
;
3551 if (!validate_micromips_insn (µmips_opcodes
[i
],
3552 µmips_operands
[i
]))
3555 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3557 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3558 micromips_nop_insn
= µmips_nop16_insn
;
3559 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3560 micromips_nop_insn
= µmips_nop32_insn
;
3564 if (micromips_nop_insn
->insn_mo
== NULL
3565 && strcmp (name
, "nop") == 0)
3567 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3568 micromips_nop_insn
->fixed_p
= 1;
3572 while (++i
< bfd_micromips_num_opcodes
3573 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3577 as_fatal (_("broken assembler, no assembly attempted"));
3579 /* We add all the general register names to the symbol table. This
3580 helps us detect invalid uses of them. */
3581 for (i
= 0; reg_names
[i
].name
; i
++)
3582 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3583 reg_names
[i
].num
, /* & RNUM_MASK, */
3584 &zero_address_frag
));
3586 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3587 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3588 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3589 &zero_address_frag
));
3591 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3592 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3593 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3594 &zero_address_frag
));
3596 for (i
= 0; i
< 32; i
++)
3600 /* R5900 VU0 floating-point register. */
3601 regname
[sizeof (rename
) - 1] = 0;
3602 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3603 symbol_table_insert (symbol_new (regname
, reg_section
,
3604 RTYPE_VF
| i
, &zero_address_frag
));
3606 /* R5900 VU0 integer register. */
3607 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3608 symbol_table_insert (symbol_new (regname
, reg_section
,
3609 RTYPE_VI
| i
, &zero_address_frag
));
3612 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3613 symbol_table_insert (symbol_new (regname
, reg_section
,
3614 RTYPE_MSA
| i
, &zero_address_frag
));
3617 obstack_init (&mips_operand_tokens
);
3619 mips_no_prev_insn ();
3622 mips_cprmask
[0] = 0;
3623 mips_cprmask
[1] = 0;
3624 mips_cprmask
[2] = 0;
3625 mips_cprmask
[3] = 0;
3627 /* set the default alignment for the text section (2**2) */
3628 record_alignment (text_section
, 2);
3630 bfd_set_gp_size (stdoutput
, g_switch_value
);
3632 /* On a native system other than VxWorks, sections must be aligned
3633 to 16 byte boundaries. When configured for an embedded ELF
3634 target, we don't bother. */
3635 if (strncmp (TARGET_OS
, "elf", 3) != 0
3636 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3638 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3639 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3640 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3643 /* Create a .reginfo section for register masks and a .mdebug
3644 section for debugging information. */
3652 subseg
= now_subseg
;
3654 /* The ABI says this section should be loaded so that the
3655 running program can access it. However, we don't load it
3656 if we are configured for an embedded target */
3657 flags
= SEC_READONLY
| SEC_DATA
;
3658 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3659 flags
|= SEC_ALLOC
| SEC_LOAD
;
3661 if (mips_abi
!= N64_ABI
)
3663 sec
= subseg_new (".reginfo", (subsegT
) 0);
3665 bfd_set_section_flags (stdoutput
, sec
, flags
);
3666 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3668 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3672 /* The 64-bit ABI uses a .MIPS.options section rather than
3673 .reginfo section. */
3674 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3675 bfd_set_section_flags (stdoutput
, sec
, flags
);
3676 bfd_set_section_alignment (stdoutput
, sec
, 3);
3678 /* Set up the option header. */
3680 Elf_Internal_Options opthdr
;
3683 opthdr
.kind
= ODK_REGINFO
;
3684 opthdr
.size
= (sizeof (Elf_External_Options
)
3685 + sizeof (Elf64_External_RegInfo
));
3688 f
= frag_more (sizeof (Elf_External_Options
));
3689 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3690 (Elf_External_Options
*) f
);
3692 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3696 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3697 bfd_set_section_flags (stdoutput
, sec
,
3698 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3699 bfd_set_section_alignment (stdoutput
, sec
, 3);
3700 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3702 if (ECOFF_DEBUGGING
)
3704 sec
= subseg_new (".mdebug", (subsegT
) 0);
3705 (void) bfd_set_section_flags (stdoutput
, sec
,
3706 SEC_HAS_CONTENTS
| SEC_READONLY
);
3707 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3709 else if (mips_flag_pdr
)
3711 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3712 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3713 SEC_READONLY
| SEC_RELOC
3715 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3718 subseg_set (seg
, subseg
);
3721 if (mips_fix_vr4120
)
3722 init_vr4120_conflicts ();
3726 fpabi_incompatible_with (int fpabi
, const char *what
)
3728 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3729 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3733 fpabi_requires (int fpabi
, const char *what
)
3735 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3736 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3739 /* Check -mabi and register sizes against the specified FP ABI. */
3741 check_fpabi (int fpabi
)
3745 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3746 if (file_mips_opts
.soft_float
)
3747 fpabi_incompatible_with (fpabi
, "softfloat");
3748 else if (file_mips_opts
.single_float
)
3749 fpabi_incompatible_with (fpabi
, "singlefloat");
3750 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3751 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3752 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3753 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3756 case Val_GNU_MIPS_ABI_FP_XX
:
3757 if (mips_abi
!= O32_ABI
)
3758 fpabi_requires (fpabi
, "-mabi=32");
3759 else if (file_mips_opts
.soft_float
)
3760 fpabi_incompatible_with (fpabi
, "softfloat");
3761 else if (file_mips_opts
.single_float
)
3762 fpabi_incompatible_with (fpabi
, "singlefloat");
3763 else if (file_mips_opts
.fp
!= 0)
3764 fpabi_requires (fpabi
, "fp=xx");
3767 case Val_GNU_MIPS_ABI_FP_64A
:
3768 case Val_GNU_MIPS_ABI_FP_64
:
3769 if (mips_abi
!= O32_ABI
)
3770 fpabi_requires (fpabi
, "-mabi=32");
3771 else if (file_mips_opts
.soft_float
)
3772 fpabi_incompatible_with (fpabi
, "softfloat");
3773 else if (file_mips_opts
.single_float
)
3774 fpabi_incompatible_with (fpabi
, "singlefloat");
3775 else if (file_mips_opts
.fp
!= 64)
3776 fpabi_requires (fpabi
, "fp=64");
3777 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3778 fpabi_incompatible_with (fpabi
, "nooddspreg");
3779 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3780 fpabi_requires (fpabi
, "nooddspreg");
3783 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3784 if (file_mips_opts
.soft_float
)
3785 fpabi_incompatible_with (fpabi
, "softfloat");
3786 else if (!file_mips_opts
.single_float
)
3787 fpabi_requires (fpabi
, "singlefloat");
3790 case Val_GNU_MIPS_ABI_FP_SOFT
:
3791 if (!file_mips_opts
.soft_float
)
3792 fpabi_requires (fpabi
, "softfloat");
3795 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3796 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3797 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3800 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3801 /* Silently ignore compatibility value. */
3805 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3806 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3811 /* Perform consistency checks on the current options. */
3814 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3816 /* Check the size of integer registers agrees with the ABI and ISA. */
3817 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3818 as_bad (_("`gp=64' used with a 32-bit processor"));
3820 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3821 as_bad (_("`gp=32' used with a 64-bit ABI"));
3823 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3824 as_bad (_("`gp=64' used with a 32-bit ABI"));
3826 /* Check the size of the float registers agrees with the ABI and ISA. */
3830 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3831 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3832 else if (opts
->single_float
== 1)
3833 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3836 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3837 as_bad (_("`fp=64' used with a 32-bit fpu"));
3839 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3840 && !ISA_HAS_MXHC1 (opts
->isa
))
3841 as_warn (_("`fp=64' used with a 32-bit ABI"));
3845 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3846 as_warn (_("`fp=32' used with a 64-bit ABI"));
3847 if (ISA_IS_R6 (mips_opts
.isa
) && opts
->single_float
== 0)
3848 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3851 as_bad (_("Unknown size of floating point registers"));
3855 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3856 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3858 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3859 as_bad (_("`mips16' cannot be used with `micromips'"));
3860 else if (ISA_IS_R6 (mips_opts
.isa
)
3861 && (opts
->micromips
== 1
3862 || opts
->mips16
== 1))
3863 as_fatal (_("`%s' can not be used with `%s'"),
3864 opts
->micromips
? "micromips" : "mips16",
3865 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
3867 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3868 as_fatal (_("branch relaxation is not supported in `%s'"),
3869 mips_cpu_info_from_isa (opts
->isa
)->name
);
3872 /* Perform consistency checks on the module level options exactly once.
3873 This is a deferred check that happens:
3874 at the first .set directive
3875 or, at the first pseudo op that generates code (inc .dc.a)
3876 or, at the first instruction
3880 file_mips_check_options (void)
3882 const struct mips_cpu_info
*arch_info
= 0;
3884 if (file_mips_opts_checked
)
3887 /* The following code determines the register size.
3888 Similar code was added to GCC 3.3 (see override_options() in
3889 config/mips/mips.c). The GAS and GCC code should be kept in sync
3890 as much as possible. */
3892 if (file_mips_opts
.gp
< 0)
3894 /* Infer the integer register size from the ABI and processor.
3895 Restrict ourselves to 32-bit registers if that's all the
3896 processor has, or if the ABI cannot handle 64-bit registers. */
3897 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3898 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3902 if (file_mips_opts
.fp
< 0)
3904 /* No user specified float register size.
3905 ??? GAS treats single-float processors as though they had 64-bit
3906 float registers (although it complains when double-precision
3907 instructions are used). As things stand, saying they have 32-bit
3908 registers would lead to spurious "register must be even" messages.
3909 So here we assume float registers are never smaller than the
3911 if (file_mips_opts
.gp
== 64)
3912 /* 64-bit integer registers implies 64-bit float registers. */
3913 file_mips_opts
.fp
= 64;
3914 else if ((file_mips_opts
.ase
& FP64_ASES
)
3915 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3916 /* Handle ASEs that require 64-bit float registers, if possible. */
3917 file_mips_opts
.fp
= 64;
3918 else if (ISA_IS_R6 (mips_opts
.isa
))
3919 /* R6 implies 64-bit float registers. */
3920 file_mips_opts
.fp
= 64;
3922 /* 32-bit float registers. */
3923 file_mips_opts
.fp
= 32;
3926 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3928 /* Disable operations on odd-numbered floating-point registers by default
3929 when using the FPXX ABI. */
3930 if (file_mips_opts
.oddspreg
< 0)
3932 if (file_mips_opts
.fp
== 0)
3933 file_mips_opts
.oddspreg
= 0;
3935 file_mips_opts
.oddspreg
= 1;
3938 /* End of GCC-shared inference code. */
3940 /* This flag is set when we have a 64-bit capable CPU but use only
3941 32-bit wide registers. Note that EABI does not use it. */
3942 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3943 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3944 || mips_abi
== O32_ABI
))
3947 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3948 as_bad (_("trap exception not supported at ISA 1"));
3950 /* If the selected architecture includes support for ASEs, enable
3951 generation of code for them. */
3952 if (file_mips_opts
.mips16
== -1)
3953 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
3954 if (file_mips_opts
.micromips
== -1)
3955 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
3958 if (mips_nan2008
== -1)
3959 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
3960 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
3961 as_fatal (_("`%s' does not support legacy NaN"),
3962 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
3964 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3965 being selected implicitly. */
3966 if (file_mips_opts
.fp
!= 64)
3967 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
3969 /* If the user didn't explicitly select or deselect a particular ASE,
3970 use the default setting for the CPU. */
3971 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
3973 /* Set up the current options. These may change throughout assembly. */
3974 mips_opts
= file_mips_opts
;
3976 mips_check_isa_supports_ases ();
3977 mips_check_options (&file_mips_opts
, TRUE
);
3978 file_mips_opts_checked
= TRUE
;
3980 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3981 as_warn (_("could not set architecture and machine"));
3985 md_assemble (char *str
)
3987 struct mips_cl_insn insn
;
3988 bfd_reloc_code_real_type unused_reloc
[3]
3989 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3991 file_mips_check_options ();
3993 imm_expr
.X_op
= O_absent
;
3994 offset_expr
.X_op
= O_absent
;
3995 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3996 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3997 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3999 mips_mark_labels ();
4000 mips_assembling_insn
= TRUE
;
4001 clear_insn_error ();
4003 if (mips_opts
.mips16
)
4004 mips16_ip (str
, &insn
);
4007 mips_ip (str
, &insn
);
4008 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4009 str
, insn
.insn_opcode
));
4013 report_insn_error (str
);
4014 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4017 if (mips_opts
.mips16
)
4018 mips16_macro (&insn
);
4025 if (offset_expr
.X_op
!= O_absent
)
4026 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4028 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4031 mips_assembling_insn
= FALSE
;
4034 /* Convenience functions for abstracting away the differences between
4035 MIPS16 and non-MIPS16 relocations. */
4037 static inline bfd_boolean
4038 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4042 case BFD_RELOC_MIPS16_JMP
:
4043 case BFD_RELOC_MIPS16_GPREL
:
4044 case BFD_RELOC_MIPS16_GOT16
:
4045 case BFD_RELOC_MIPS16_CALL16
:
4046 case BFD_RELOC_MIPS16_HI16_S
:
4047 case BFD_RELOC_MIPS16_HI16
:
4048 case BFD_RELOC_MIPS16_LO16
:
4056 static inline bfd_boolean
4057 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4061 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4062 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4063 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4064 case BFD_RELOC_MICROMIPS_GPREL16
:
4065 case BFD_RELOC_MICROMIPS_JMP
:
4066 case BFD_RELOC_MICROMIPS_HI16
:
4067 case BFD_RELOC_MICROMIPS_HI16_S
:
4068 case BFD_RELOC_MICROMIPS_LO16
:
4069 case BFD_RELOC_MICROMIPS_LITERAL
:
4070 case BFD_RELOC_MICROMIPS_GOT16
:
4071 case BFD_RELOC_MICROMIPS_CALL16
:
4072 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4073 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4074 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4075 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4076 case BFD_RELOC_MICROMIPS_SUB
:
4077 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4078 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4079 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4080 case BFD_RELOC_MICROMIPS_HIGHEST
:
4081 case BFD_RELOC_MICROMIPS_HIGHER
:
4082 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4083 case BFD_RELOC_MICROMIPS_JALR
:
4091 static inline bfd_boolean
4092 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4094 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4097 static inline bfd_boolean
4098 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4100 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4101 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4104 static inline bfd_boolean
4105 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4107 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4108 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4111 static inline bfd_boolean
4112 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4114 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4115 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4118 static inline bfd_boolean
4119 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4121 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4124 static inline bfd_boolean
4125 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4127 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4128 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4131 /* Return true if RELOC is a PC-relative relocation that does not have
4132 full address range. */
4134 static inline bfd_boolean
4135 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4139 case BFD_RELOC_16_PCREL_S2
:
4140 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4141 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4142 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4143 case BFD_RELOC_MIPS_21_PCREL_S2
:
4144 case BFD_RELOC_MIPS_26_PCREL_S2
:
4145 case BFD_RELOC_MIPS_18_PCREL_S3
:
4146 case BFD_RELOC_MIPS_19_PCREL_S2
:
4149 case BFD_RELOC_32_PCREL
:
4150 case BFD_RELOC_HI16_S_PCREL
:
4151 case BFD_RELOC_LO16_PCREL
:
4152 return HAVE_64BIT_ADDRESSES
;
4159 /* Return true if the given relocation might need a matching %lo().
4160 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4161 need a matching %lo() when applied to local symbols. */
4163 static inline bfd_boolean
4164 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4166 return (HAVE_IN_PLACE_ADDENDS
4167 && (hi16_reloc_p (reloc
)
4168 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4169 all GOT16 relocations evaluate to "G". */
4170 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4173 /* Return the type of %lo() reloc needed by RELOC, given that
4174 reloc_needs_lo_p. */
4176 static inline bfd_reloc_code_real_type
4177 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4179 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4180 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4184 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4187 static inline bfd_boolean
4188 fixup_has_matching_lo_p (fixS
*fixp
)
4190 return (fixp
->fx_next
!= NULL
4191 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4192 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4193 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4196 /* Move all labels in LABELS to the current insertion point. TEXT_P
4197 says whether the labels refer to text or data. */
4200 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4202 struct insn_label_list
*l
;
4205 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4207 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4208 symbol_set_frag (l
->label
, frag_now
);
4209 val
= (valueT
) frag_now_fix ();
4210 /* MIPS16/microMIPS text labels are stored as odd. */
4211 if (text_p
&& HAVE_CODE_COMPRESSION
)
4213 S_SET_VALUE (l
->label
, val
);
4217 /* Move all labels in insn_labels to the current insertion point
4218 and treat them as text labels. */
4221 mips_move_text_labels (void)
4223 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4227 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4229 bfd_boolean linkonce
= FALSE
;
4230 segT symseg
= S_GET_SEGMENT (sym
);
4232 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4234 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4236 /* The GNU toolchain uses an extension for ELF: a section
4237 beginning with the magic string .gnu.linkonce is a
4238 linkonce section. */
4239 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4240 sizeof ".gnu.linkonce" - 1) == 0)
4246 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4247 linker to handle them specially, such as generating jalx instructions
4248 when needed. We also make them odd for the duration of the assembly,
4249 in order to generate the right sort of code. We will make them even
4250 in the adjust_symtab routine, while leaving them marked. This is
4251 convenient for the debugger and the disassembler. The linker knows
4252 to make them odd again. */
4255 mips_compressed_mark_label (symbolS
*label
)
4257 gas_assert (HAVE_CODE_COMPRESSION
);
4259 if (mips_opts
.mips16
)
4260 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4262 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4263 if ((S_GET_VALUE (label
) & 1) == 0
4264 /* Don't adjust the address if the label is global or weak, or
4265 in a link-once section, since we'll be emitting symbol reloc
4266 references to it which will be patched up by the linker, and
4267 the final value of the symbol may or may not be MIPS16/microMIPS. */
4268 && !S_IS_WEAK (label
)
4269 && !S_IS_EXTERNAL (label
)
4270 && !s_is_linkonce (label
, now_seg
))
4271 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4274 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4277 mips_compressed_mark_labels (void)
4279 struct insn_label_list
*l
;
4281 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4282 mips_compressed_mark_label (l
->label
);
4285 /* End the current frag. Make it a variant frag and record the
4289 relax_close_frag (void)
4291 mips_macro_warning
.first_frag
= frag_now
;
4292 frag_var (rs_machine_dependent
, 0, 0,
4293 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
4294 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4296 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4297 mips_relax
.first_fixup
= 0;
4300 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4301 See the comment above RELAX_ENCODE for more details. */
4304 relax_start (symbolS
*symbol
)
4306 gas_assert (mips_relax
.sequence
== 0);
4307 mips_relax
.sequence
= 1;
4308 mips_relax
.symbol
= symbol
;
4311 /* Start generating the second version of a relaxable sequence.
4312 See the comment above RELAX_ENCODE for more details. */
4317 gas_assert (mips_relax
.sequence
== 1);
4318 mips_relax
.sequence
= 2;
4321 /* End the current relaxable sequence. */
4326 gas_assert (mips_relax
.sequence
== 2);
4327 relax_close_frag ();
4328 mips_relax
.sequence
= 0;
4331 /* Return true if IP is a delayed branch or jump. */
4333 static inline bfd_boolean
4334 delayed_branch_p (const struct mips_cl_insn
*ip
)
4336 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4337 | INSN_COND_BRANCH_DELAY
4338 | INSN_COND_BRANCH_LIKELY
)) != 0;
4341 /* Return true if IP is a compact branch or jump. */
4343 static inline bfd_boolean
4344 compact_branch_p (const struct mips_cl_insn
*ip
)
4346 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4347 | INSN2_COND_BRANCH
)) != 0;
4350 /* Return true if IP is an unconditional branch or jump. */
4352 static inline bfd_boolean
4353 uncond_branch_p (const struct mips_cl_insn
*ip
)
4355 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4356 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4359 /* Return true if IP is a branch-likely instruction. */
4361 static inline bfd_boolean
4362 branch_likely_p (const struct mips_cl_insn
*ip
)
4364 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4367 /* Return the type of nop that should be used to fill the delay slot
4368 of delayed branch IP. */
4370 static struct mips_cl_insn
*
4371 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4373 if (mips_opts
.micromips
4374 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4375 return µmips_nop32_insn
;
4379 /* Return a mask that has bit N set if OPCODE reads the register(s)
4383 insn_read_mask (const struct mips_opcode
*opcode
)
4385 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4388 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4392 insn_write_mask (const struct mips_opcode
*opcode
)
4394 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4397 /* Return a mask of the registers specified by operand OPERAND of INSN.
4398 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4402 operand_reg_mask (const struct mips_cl_insn
*insn
,
4403 const struct mips_operand
*operand
,
4404 unsigned int type_mask
)
4406 unsigned int uval
, vsel
;
4408 switch (operand
->type
)
4415 case OP_ADDIUSP_INT
:
4416 case OP_ENTRY_EXIT_LIST
:
4417 case OP_REPEAT_DEST_REG
:
4418 case OP_REPEAT_PREV_REG
:
4421 case OP_VU0_MATCH_SUFFIX
:
4426 case OP_OPTIONAL_REG
:
4428 const struct mips_reg_operand
*reg_op
;
4430 reg_op
= (const struct mips_reg_operand
*) operand
;
4431 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4433 uval
= insn_extract_operand (insn
, operand
);
4434 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4439 const struct mips_reg_pair_operand
*pair_op
;
4441 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4442 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4444 uval
= insn_extract_operand (insn
, operand
);
4445 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4448 case OP_CLO_CLZ_DEST
:
4449 if (!(type_mask
& (1 << OP_REG_GP
)))
4451 uval
= insn_extract_operand (insn
, operand
);
4452 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4455 if (!(type_mask
& (1 << OP_REG_GP
)))
4457 uval
= insn_extract_operand (insn
, operand
);
4458 gas_assert ((uval
& 31) == (uval
>> 5));
4459 return 1 << (uval
& 31);
4462 case OP_NON_ZERO_REG
:
4463 if (!(type_mask
& (1 << OP_REG_GP
)))
4465 uval
= insn_extract_operand (insn
, operand
);
4466 return 1 << (uval
& 31);
4468 case OP_LWM_SWM_LIST
:
4471 case OP_SAVE_RESTORE_LIST
:
4474 case OP_MDMX_IMM_REG
:
4475 if (!(type_mask
& (1 << OP_REG_VEC
)))
4477 uval
= insn_extract_operand (insn
, operand
);
4479 if ((vsel
& 0x18) == 0x18)
4481 return 1 << (uval
& 31);
4484 if (!(type_mask
& (1 << OP_REG_GP
)))
4486 return 1 << insn_extract_operand (insn
, operand
);
4491 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4492 where bit N of OPNO_MASK is set if operand N should be included.
4493 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4497 insn_reg_mask (const struct mips_cl_insn
*insn
,
4498 unsigned int type_mask
, unsigned int opno_mask
)
4500 unsigned int opno
, reg_mask
;
4504 while (opno_mask
!= 0)
4507 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4514 /* Return the mask of core registers that IP reads. */
4517 gpr_read_mask (const struct mips_cl_insn
*ip
)
4519 unsigned long pinfo
, pinfo2
;
4522 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4523 pinfo
= ip
->insn_mo
->pinfo
;
4524 pinfo2
= ip
->insn_mo
->pinfo2
;
4525 if (pinfo
& INSN_UDI
)
4527 /* UDI instructions have traditionally been assumed to read RS
4529 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4530 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4532 if (pinfo
& INSN_READ_GPR_24
)
4534 if (pinfo2
& INSN2_READ_GPR_16
)
4536 if (pinfo2
& INSN2_READ_SP
)
4538 if (pinfo2
& INSN2_READ_GPR_31
)
4540 /* Don't include register 0. */
4544 /* Return the mask of core registers that IP writes. */
4547 gpr_write_mask (const struct mips_cl_insn
*ip
)
4549 unsigned long pinfo
, pinfo2
;
4552 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4553 pinfo
= ip
->insn_mo
->pinfo
;
4554 pinfo2
= ip
->insn_mo
->pinfo2
;
4555 if (pinfo
& INSN_WRITE_GPR_24
)
4557 if (pinfo
& INSN_WRITE_GPR_31
)
4559 if (pinfo
& INSN_UDI
)
4560 /* UDI instructions have traditionally been assumed to write to RD. */
4561 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4562 if (pinfo2
& INSN2_WRITE_SP
)
4564 /* Don't include register 0. */
4568 /* Return the mask of floating-point registers that IP reads. */
4571 fpr_read_mask (const struct mips_cl_insn
*ip
)
4573 unsigned long pinfo
;
4576 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4577 | (1 << OP_REG_MSA
)),
4578 insn_read_mask (ip
->insn_mo
));
4579 pinfo
= ip
->insn_mo
->pinfo
;
4580 /* Conservatively treat all operands to an FP_D instruction are doubles.
4581 (This is overly pessimistic for things like cvt.d.s.) */
4582 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4587 /* Return the mask of floating-point registers that IP writes. */
4590 fpr_write_mask (const struct mips_cl_insn
*ip
)
4592 unsigned long pinfo
;
4595 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4596 | (1 << OP_REG_MSA
)),
4597 insn_write_mask (ip
->insn_mo
));
4598 pinfo
= ip
->insn_mo
->pinfo
;
4599 /* Conservatively treat all operands to an FP_D instruction are doubles.
4600 (This is overly pessimistic for things like cvt.s.d.) */
4601 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4606 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4607 Check whether that is allowed. */
4610 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4612 const char *s
= insn
->name
;
4613 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4615 && mips_opts
.oddspreg
;
4617 if (insn
->pinfo
== INSN_MACRO
)
4618 /* Let a macro pass, we'll catch it later when it is expanded. */
4621 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4622 otherwise it depends on oddspreg. */
4623 if ((insn
->pinfo
& FP_S
)
4624 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4625 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4626 return FPR_SIZE
== 32 || oddspreg
;
4628 /* Allow odd registers for single-precision ops and double-precision if the
4629 floating-point registers are 64-bit wide. */
4630 switch (insn
->pinfo
& (FP_S
| FP_D
))
4636 return FPR_SIZE
== 64;
4641 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4642 s
= strchr (insn
->name
, '.');
4643 if (s
!= NULL
&& opnum
== 2)
4644 s
= strchr (s
+ 1, '.');
4645 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4648 return FPR_SIZE
== 64;
4651 /* Information about an instruction argument that we're trying to match. */
4652 struct mips_arg_info
4654 /* The instruction so far. */
4655 struct mips_cl_insn
*insn
;
4657 /* The first unconsumed operand token. */
4658 struct mips_operand_token
*token
;
4660 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4663 /* The 1-based argument number, for error reporting. This does not
4664 count elided optional registers, etc.. */
4667 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4668 unsigned int last_regno
;
4670 /* If the first operand was an OP_REG, this is the register that it
4671 specified, otherwise it is ILLEGAL_REG. */
4672 unsigned int dest_regno
;
4674 /* The value of the last OP_INT operand. Only used for OP_MSB,
4675 where it gives the lsb position. */
4676 unsigned int last_op_int
;
4678 /* If true, match routines should assume that no later instruction
4679 alternative matches and should therefore be as accomodating as
4680 possible. Match routines should not report errors if something
4681 is only invalid for !LAX_MATCH. */
4682 bfd_boolean lax_match
;
4684 /* True if a reference to the current AT register was seen. */
4685 bfd_boolean seen_at
;
4688 /* Record that the argument is out of range. */
4691 match_out_of_range (struct mips_arg_info
*arg
)
4693 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4696 /* Record that the argument isn't constant but needs to be. */
4699 match_not_constant (struct mips_arg_info
*arg
)
4701 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4705 /* Try to match an OT_CHAR token for character CH. Consume the token
4706 and return true on success, otherwise return false. */
4709 match_char (struct mips_arg_info
*arg
, char ch
)
4711 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4721 /* Try to get an expression from the next tokens in ARG. Consume the
4722 tokens and return true on success, storing the expression value in
4723 VALUE and relocation types in R. */
4726 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4727 bfd_reloc_code_real_type
*r
)
4729 /* If the next token is a '(' that was parsed as being part of a base
4730 expression, assume we have an elided offset. The later match will fail
4731 if this turns out to be wrong. */
4732 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4734 value
->X_op
= O_constant
;
4735 value
->X_add_number
= 0;
4736 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4740 /* Reject register-based expressions such as "0+$2" and "(($2))".
4741 For plain registers the default error seems more appropriate. */
4742 if (arg
->token
->type
== OT_INTEGER
4743 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4745 set_insn_error (arg
->argnum
, _("register value used as expression"));
4749 if (arg
->token
->type
== OT_INTEGER
)
4751 *value
= arg
->token
->u
.integer
.value
;
4752 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4758 (arg
->argnum
, _("operand %d must be an immediate expression"),
4763 /* Try to get a constant expression from the next tokens in ARG. Consume
4764 the tokens and return return true on success, storing the constant value
4765 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4769 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4772 bfd_reloc_code_real_type r
[3];
4774 if (!match_expression (arg
, &ex
, r
))
4777 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4778 *value
= ex
.X_add_number
;
4781 match_not_constant (arg
);
4787 /* Return the RTYPE_* flags for a register operand of type TYPE that
4788 appears in instruction OPCODE. */
4791 convert_reg_type (const struct mips_opcode
*opcode
,
4792 enum mips_reg_operand_type type
)
4797 return RTYPE_NUM
| RTYPE_GP
;
4800 /* Allow vector register names for MDMX if the instruction is a 64-bit
4801 FPR load, store or move (including moves to and from GPRs). */
4802 if ((mips_opts
.ase
& ASE_MDMX
)
4803 && (opcode
->pinfo
& FP_D
)
4804 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4805 | INSN_COPROC_MEMORY_DELAY
4808 | INSN_STORE_MEMORY
)))
4809 return RTYPE_FPU
| RTYPE_VEC
;
4813 if (opcode
->pinfo
& (FP_D
| FP_S
))
4814 return RTYPE_CCC
| RTYPE_FCC
;
4818 if (opcode
->membership
& INSN_5400
)
4820 return RTYPE_FPU
| RTYPE_VEC
;
4826 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4827 return RTYPE_NUM
| RTYPE_CP0
;
4834 return RTYPE_NUM
| RTYPE_VI
;
4837 return RTYPE_NUM
| RTYPE_VF
;
4839 case OP_REG_R5900_I
:
4840 return RTYPE_R5900_I
;
4842 case OP_REG_R5900_Q
:
4843 return RTYPE_R5900_Q
;
4845 case OP_REG_R5900_R
:
4846 return RTYPE_R5900_R
;
4848 case OP_REG_R5900_ACC
:
4849 return RTYPE_R5900_ACC
;
4854 case OP_REG_MSA_CTRL
:
4860 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4863 check_regno (struct mips_arg_info
*arg
,
4864 enum mips_reg_operand_type type
, unsigned int regno
)
4866 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4867 arg
->seen_at
= TRUE
;
4869 if (type
== OP_REG_FP
4871 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4873 /* This was a warning prior to introducing O32 FPXX and FP64 support
4874 so maintain a warning for FP32 but raise an error for the new
4877 as_warn (_("float register should be even, was %d"), regno
);
4879 as_bad (_("float register should be even, was %d"), regno
);
4882 if (type
== OP_REG_CCC
)
4887 name
= arg
->insn
->insn_mo
->name
;
4888 length
= strlen (name
);
4889 if ((regno
& 1) != 0
4890 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4891 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4892 as_warn (_("condition code register should be even for %s, was %d"),
4895 if ((regno
& 3) != 0
4896 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4897 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4902 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4903 a register of type TYPE. Return true on success, storing the register
4904 number in *REGNO and warning about any dubious uses. */
4907 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4908 unsigned int symval
, unsigned int *regno
)
4910 if (type
== OP_REG_VEC
)
4911 symval
= mips_prefer_vec_regno (symval
);
4912 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4915 *regno
= symval
& RNUM_MASK
;
4916 check_regno (arg
, type
, *regno
);
4920 /* Try to interpret the next token in ARG as a register of type TYPE.
4921 Consume the token and return true on success, storing the register
4922 number in *REGNO. Return false on failure. */
4925 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4926 unsigned int *regno
)
4928 if (arg
->token
->type
== OT_REG
4929 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4937 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4938 Consume the token and return true on success, storing the register numbers
4939 in *REGNO1 and *REGNO2. Return false on failure. */
4942 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4943 unsigned int *regno1
, unsigned int *regno2
)
4945 if (match_reg (arg
, type
, regno1
))
4950 if (arg
->token
->type
== OT_REG_RANGE
4951 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4952 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4953 && *regno1
<= *regno2
)
4961 /* OP_INT matcher. */
4964 match_int_operand (struct mips_arg_info
*arg
,
4965 const struct mips_operand
*operand_base
)
4967 const struct mips_int_operand
*operand
;
4969 int min_val
, max_val
, factor
;
4972 operand
= (const struct mips_int_operand
*) operand_base
;
4973 factor
= 1 << operand
->shift
;
4974 min_val
= mips_int_operand_min (operand
);
4975 max_val
= mips_int_operand_max (operand
);
4977 if (operand_base
->lsb
== 0
4978 && operand_base
->size
== 16
4979 && operand
->shift
== 0
4980 && operand
->bias
== 0
4981 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4983 /* The operand can be relocated. */
4984 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4987 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4988 /* Relocation operators were used. Accept the arguent and
4989 leave the relocation value in offset_expr and offset_relocs
4990 for the caller to process. */
4993 if (offset_expr
.X_op
!= O_constant
)
4995 /* Accept non-constant operands if no later alternative matches,
4996 leaving it for the caller to process. */
4997 if (!arg
->lax_match
)
4999 offset_reloc
[0] = BFD_RELOC_LO16
;
5003 /* Clear the global state; we're going to install the operand
5005 sval
= offset_expr
.X_add_number
;
5006 offset_expr
.X_op
= O_absent
;
5008 /* For compatibility with older assemblers, we accept
5009 0x8000-0xffff as signed 16-bit numbers when only
5010 signed numbers are allowed. */
5013 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5014 if (!arg
->lax_match
&& sval
<= max_val
)
5020 if (!match_const_int (arg
, &sval
))
5024 arg
->last_op_int
= sval
;
5026 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5028 match_out_of_range (arg
);
5032 uval
= (unsigned int) sval
>> operand
->shift
;
5033 uval
-= operand
->bias
;
5035 /* Handle -mfix-cn63xxp1. */
5037 && mips_fix_cn63xxp1
5038 && !mips_opts
.micromips
5039 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5054 /* The rest must be changed to 28. */
5059 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5063 /* OP_MAPPED_INT matcher. */
5066 match_mapped_int_operand (struct mips_arg_info
*arg
,
5067 const struct mips_operand
*operand_base
)
5069 const struct mips_mapped_int_operand
*operand
;
5070 unsigned int uval
, num_vals
;
5073 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5074 if (!match_const_int (arg
, &sval
))
5077 num_vals
= 1 << operand_base
->size
;
5078 for (uval
= 0; uval
< num_vals
; uval
++)
5079 if (operand
->int_map
[uval
] == sval
)
5081 if (uval
== num_vals
)
5083 match_out_of_range (arg
);
5087 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5091 /* OP_MSB matcher. */
5094 match_msb_operand (struct mips_arg_info
*arg
,
5095 const struct mips_operand
*operand_base
)
5097 const struct mips_msb_operand
*operand
;
5098 int min_val
, max_val
, max_high
;
5099 offsetT size
, sval
, high
;
5101 operand
= (const struct mips_msb_operand
*) operand_base
;
5102 min_val
= operand
->bias
;
5103 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5104 max_high
= operand
->opsize
;
5106 if (!match_const_int (arg
, &size
))
5109 high
= size
+ arg
->last_op_int
;
5110 sval
= operand
->add_lsb
? high
: size
;
5112 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5114 match_out_of_range (arg
);
5117 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5121 /* OP_REG matcher. */
5124 match_reg_operand (struct mips_arg_info
*arg
,
5125 const struct mips_operand
*operand_base
)
5127 const struct mips_reg_operand
*operand
;
5128 unsigned int regno
, uval
, num_vals
;
5130 operand
= (const struct mips_reg_operand
*) operand_base
;
5131 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5134 if (operand
->reg_map
)
5136 num_vals
= 1 << operand
->root
.size
;
5137 for (uval
= 0; uval
< num_vals
; uval
++)
5138 if (operand
->reg_map
[uval
] == regno
)
5140 if (num_vals
== uval
)
5146 arg
->last_regno
= regno
;
5147 if (arg
->opnum
== 1)
5148 arg
->dest_regno
= regno
;
5149 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5153 /* OP_REG_PAIR matcher. */
5156 match_reg_pair_operand (struct mips_arg_info
*arg
,
5157 const struct mips_operand
*operand_base
)
5159 const struct mips_reg_pair_operand
*operand
;
5160 unsigned int regno1
, regno2
, uval
, num_vals
;
5162 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5163 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5164 || !match_char (arg
, ',')
5165 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5168 num_vals
= 1 << operand_base
->size
;
5169 for (uval
= 0; uval
< num_vals
; uval
++)
5170 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5172 if (uval
== num_vals
)
5175 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5179 /* OP_PCREL matcher. The caller chooses the relocation type. */
5182 match_pcrel_operand (struct mips_arg_info
*arg
)
5184 bfd_reloc_code_real_type r
[3];
5186 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5189 /* OP_PERF_REG matcher. */
5192 match_perf_reg_operand (struct mips_arg_info
*arg
,
5193 const struct mips_operand
*operand
)
5197 if (!match_const_int (arg
, &sval
))
5202 || (mips_opts
.arch
== CPU_R5900
5203 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5204 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5206 set_insn_error (arg
->argnum
, _("invalid performance register"));
5210 insn_insert_operand (arg
->insn
, operand
, sval
);
5214 /* OP_ADDIUSP matcher. */
5217 match_addiusp_operand (struct mips_arg_info
*arg
,
5218 const struct mips_operand
*operand
)
5223 if (!match_const_int (arg
, &sval
))
5228 match_out_of_range (arg
);
5233 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5235 match_out_of_range (arg
);
5239 uval
= (unsigned int) sval
;
5240 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5241 insn_insert_operand (arg
->insn
, operand
, uval
);
5245 /* OP_CLO_CLZ_DEST matcher. */
5248 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5249 const struct mips_operand
*operand
)
5253 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5256 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5260 /* OP_CHECK_PREV matcher. */
5263 match_check_prev_operand (struct mips_arg_info
*arg
,
5264 const struct mips_operand
*operand_base
)
5266 const struct mips_check_prev_operand
*operand
;
5269 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5271 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5274 if (!operand
->zero_ok
&& regno
== 0)
5277 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5278 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5279 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5281 arg
->last_regno
= regno
;
5282 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5289 /* OP_SAME_RS_RT matcher. */
5292 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5293 const struct mips_operand
*operand
)
5297 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5302 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5306 arg
->last_regno
= regno
;
5308 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5312 /* OP_LWM_SWM_LIST matcher. */
5315 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5316 const struct mips_operand
*operand
)
5318 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5319 struct mips_arg_info reset
;
5322 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5326 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5331 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5334 while (match_char (arg
, ',')
5335 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5338 if (operand
->size
== 2)
5340 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5346 and any permutations of these. */
5347 if ((reglist
& 0xfff1ffff) != 0x80010000)
5350 sregs
= (reglist
>> 17) & 7;
5355 /* The list must include at least one of ra and s0-sN,
5356 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5357 which are $23 and $30 respectively.) E.g.:
5365 and any permutations of these. */
5366 if ((reglist
& 0x3f00ffff) != 0)
5369 ra
= (reglist
>> 27) & 0x10;
5370 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5373 if ((sregs
& -sregs
) != sregs
)
5376 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5380 /* OP_ENTRY_EXIT_LIST matcher. */
5383 match_entry_exit_operand (struct mips_arg_info
*arg
,
5384 const struct mips_operand
*operand
)
5387 bfd_boolean is_exit
;
5389 /* The format is the same for both ENTRY and EXIT, but the constraints
5391 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5392 mask
= (is_exit
? 7 << 3 : 0);
5395 unsigned int regno1
, regno2
;
5396 bfd_boolean is_freg
;
5398 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5400 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5405 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5408 mask
|= (5 + regno2
) << 3;
5410 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5411 mask
|= (regno2
- 3) << 3;
5412 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5413 mask
|= (regno2
- 15) << 1;
5414 else if (regno1
== RA
&& regno2
== RA
)
5419 while (match_char (arg
, ','));
5421 insn_insert_operand (arg
->insn
, operand
, mask
);
5425 /* OP_SAVE_RESTORE_LIST matcher. */
5428 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5430 unsigned int opcode
, args
, statics
, sregs
;
5431 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5434 opcode
= arg
->insn
->insn_opcode
;
5436 num_frame_sizes
= 0;
5442 unsigned int regno1
, regno2
;
5444 if (arg
->token
->type
== OT_INTEGER
)
5446 /* Handle the frame size. */
5447 if (!match_const_int (arg
, &frame_size
))
5449 num_frame_sizes
+= 1;
5453 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5456 while (regno1
<= regno2
)
5458 if (regno1
>= 4 && regno1
<= 7)
5460 if (num_frame_sizes
== 0)
5462 args
|= 1 << (regno1
- 4);
5464 /* statics $a0-$a3 */
5465 statics
|= 1 << (regno1
- 4);
5467 else if (regno1
>= 16 && regno1
<= 23)
5469 sregs
|= 1 << (regno1
- 16);
5470 else if (regno1
== 30)
5473 else if (regno1
== 31)
5474 /* Add $ra to insn. */
5484 while (match_char (arg
, ','));
5486 /* Encode args/statics combination. */
5489 else if (args
== 0xf)
5490 /* All $a0-$a3 are args. */
5491 opcode
|= MIPS16_ALL_ARGS
<< 16;
5492 else if (statics
== 0xf)
5493 /* All $a0-$a3 are statics. */
5494 opcode
|= MIPS16_ALL_STATICS
<< 16;
5497 /* Count arg registers. */
5507 /* Count static registers. */
5509 while (statics
& 0x8)
5511 statics
= (statics
<< 1) & 0xf;
5517 /* Encode args/statics. */
5518 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5521 /* Encode $s0/$s1. */
5522 if (sregs
& (1 << 0)) /* $s0 */
5524 if (sregs
& (1 << 1)) /* $s1 */
5528 /* Encode $s2-$s8. */
5537 opcode
|= num_sregs
<< 24;
5539 /* Encode frame size. */
5540 if (num_frame_sizes
== 0)
5542 set_insn_error (arg
->argnum
, _("missing frame size"));
5545 if (num_frame_sizes
> 1)
5547 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5550 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5552 set_insn_error (arg
->argnum
, _("invalid frame size"));
5555 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5558 opcode
|= (((frame_size
& 0xf0) << 16)
5559 | (frame_size
& 0x0f));
5562 /* Finally build the instruction. */
5563 if ((opcode
>> 16) != 0 || frame_size
== 0)
5564 opcode
|= MIPS16_EXTEND
;
5565 arg
->insn
->insn_opcode
= opcode
;
5569 /* OP_MDMX_IMM_REG matcher. */
5572 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5573 const struct mips_operand
*operand
)
5575 unsigned int regno
, uval
;
5577 const struct mips_opcode
*opcode
;
5579 /* The mips_opcode records whether this is an octobyte or quadhalf
5580 instruction. Start out with that bit in place. */
5581 opcode
= arg
->insn
->insn_mo
;
5582 uval
= mips_extract_operand (operand
, opcode
->match
);
5583 is_qh
= (uval
!= 0);
5585 if (arg
->token
->type
== OT_REG
)
5587 if ((opcode
->membership
& INSN_5400
)
5588 && strcmp (opcode
->name
, "rzu.ob") == 0)
5590 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5595 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5599 /* Check whether this is a vector register or a broadcast of
5600 a single element. */
5601 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5603 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5605 set_insn_error (arg
->argnum
, _("invalid element selector"));
5608 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5613 /* A full vector. */
5614 if ((opcode
->membership
& INSN_5400
)
5615 && (strcmp (opcode
->name
, "sll.ob") == 0
5616 || strcmp (opcode
->name
, "srl.ob") == 0))
5618 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5624 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5626 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5634 if (!match_const_int (arg
, &sval
))
5636 if (sval
< 0 || sval
> 31)
5638 match_out_of_range (arg
);
5641 uval
|= (sval
& 31);
5643 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5645 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5647 insn_insert_operand (arg
->insn
, operand
, uval
);
5651 /* OP_IMM_INDEX matcher. */
5654 match_imm_index_operand (struct mips_arg_info
*arg
,
5655 const struct mips_operand
*operand
)
5657 unsigned int max_val
;
5659 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5662 max_val
= (1 << operand
->size
) - 1;
5663 if (arg
->token
->u
.index
> max_val
)
5665 match_out_of_range (arg
);
5668 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5673 /* OP_REG_INDEX matcher. */
5676 match_reg_index_operand (struct mips_arg_info
*arg
,
5677 const struct mips_operand
*operand
)
5681 if (arg
->token
->type
!= OT_REG_INDEX
)
5684 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5687 insn_insert_operand (arg
->insn
, operand
, regno
);
5692 /* OP_PC matcher. */
5695 match_pc_operand (struct mips_arg_info
*arg
)
5697 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5705 /* OP_NON_ZERO_REG matcher. */
5708 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5709 const struct mips_operand
*operand
)
5713 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5719 arg
->last_regno
= regno
;
5720 insn_insert_operand (arg
->insn
, operand
, regno
);
5724 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5725 register that we need to match. */
5728 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5732 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5735 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5736 the length of the value in bytes (4 for float, 8 for double) and
5737 USING_GPRS says whether the destination is a GPR rather than an FPR.
5739 Return the constant in IMM and OFFSET as follows:
5741 - If the constant should be loaded via memory, set IMM to O_absent and
5742 OFFSET to the memory address.
5744 - Otherwise, if the constant should be loaded into two 32-bit registers,
5745 set IMM to the O_constant to load into the high register and OFFSET
5746 to the corresponding value for the low register.
5748 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5750 These constants only appear as the last operand in an instruction,
5751 and every instruction that accepts them in any variant accepts them
5752 in all variants. This means we don't have to worry about backing out
5753 any changes if the instruction does not match. We just match
5754 unconditionally and report an error if the constant is invalid. */
5757 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5758 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5763 const char *newname
;
5764 unsigned char *data
;
5766 /* Where the constant is placed is based on how the MIPS assembler
5769 length == 4 && using_gprs -- immediate value only
5770 length == 8 && using_gprs -- .rdata or immediate value
5771 length == 4 && !using_gprs -- .lit4 or immediate value
5772 length == 8 && !using_gprs -- .lit8 or immediate value
5774 The .lit4 and .lit8 sections are only used if permitted by the
5776 if (arg
->token
->type
!= OT_FLOAT
)
5778 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5782 gas_assert (arg
->token
->u
.flt
.length
== length
);
5783 data
= arg
->token
->u
.flt
.data
;
5786 /* Handle 32-bit constants for which an immediate value is best. */
5789 || g_switch_value
< 4
5790 || (data
[0] == 0 && data
[1] == 0)
5791 || (data
[2] == 0 && data
[3] == 0)))
5793 imm
->X_op
= O_constant
;
5794 if (!target_big_endian
)
5795 imm
->X_add_number
= bfd_getl32 (data
);
5797 imm
->X_add_number
= bfd_getb32 (data
);
5798 offset
->X_op
= O_absent
;
5802 /* Handle 64-bit constants for which an immediate value is best. */
5804 && !mips_disable_float_construction
5805 /* Constants can only be constructed in GPRs and copied to FPRs if the
5806 GPRs are at least as wide as the FPRs or MTHC1 is available.
5807 Unlike most tests for 32-bit floating-point registers this check
5808 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5809 permit 64-bit moves without MXHC1.
5810 Force the constant into memory otherwise. */
5813 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5815 && ((data
[0] == 0 && data
[1] == 0)
5816 || (data
[2] == 0 && data
[3] == 0))
5817 && ((data
[4] == 0 && data
[5] == 0)
5818 || (data
[6] == 0 && data
[7] == 0)))
5820 /* The value is simple enough to load with a couple of instructions.
5821 If using 32-bit registers, set IMM to the high order 32 bits and
5822 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5824 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5826 imm
->X_op
= O_constant
;
5827 offset
->X_op
= O_constant
;
5828 if (!target_big_endian
)
5830 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5831 offset
->X_add_number
= bfd_getl32 (data
);
5835 imm
->X_add_number
= bfd_getb32 (data
);
5836 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5838 if (offset
->X_add_number
== 0)
5839 offset
->X_op
= O_absent
;
5843 imm
->X_op
= O_constant
;
5844 if (!target_big_endian
)
5845 imm
->X_add_number
= bfd_getl64 (data
);
5847 imm
->X_add_number
= bfd_getb64 (data
);
5848 offset
->X_op
= O_absent
;
5853 /* Switch to the right section. */
5855 subseg
= now_subseg
;
5858 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5863 if (using_gprs
|| g_switch_value
< 8)
5864 newname
= RDATA_SECTION_NAME
;
5869 new_seg
= subseg_new (newname
, (subsegT
) 0);
5870 bfd_set_section_flags (stdoutput
, new_seg
,
5871 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5872 frag_align (length
== 4 ? 2 : 3, 0, 0);
5873 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5874 record_alignment (new_seg
, 4);
5876 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5878 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5880 /* Set the argument to the current address in the section. */
5881 imm
->X_op
= O_absent
;
5882 offset
->X_op
= O_symbol
;
5883 offset
->X_add_symbol
= symbol_temp_new_now ();
5884 offset
->X_add_number
= 0;
5886 /* Put the floating point number into the section. */
5887 p
= frag_more (length
);
5888 memcpy (p
, data
, length
);
5890 /* Switch back to the original section. */
5891 subseg_set (seg
, subseg
);
5895 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5899 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5900 const struct mips_operand
*operand
,
5901 bfd_boolean match_p
)
5905 /* The operand can be an XYZW mask or a single 2-bit channel index
5906 (with X being 0). */
5907 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5909 /* The suffix can be omitted when it is already part of the opcode. */
5910 if (arg
->token
->type
!= OT_CHANNELS
)
5913 uval
= arg
->token
->u
.channels
;
5914 if (operand
->size
== 2)
5916 /* Check that a single bit is set and convert it into a 2-bit index. */
5917 if ((uval
& -uval
) != uval
)
5919 uval
= 4 - ffs (uval
);
5922 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5927 insn_insert_operand (arg
->insn
, operand
, uval
);
5931 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5932 of the argument text if the match is successful, otherwise return null. */
5935 match_operand (struct mips_arg_info
*arg
,
5936 const struct mips_operand
*operand
)
5938 switch (operand
->type
)
5941 return match_int_operand (arg
, operand
);
5944 return match_mapped_int_operand (arg
, operand
);
5947 return match_msb_operand (arg
, operand
);
5950 case OP_OPTIONAL_REG
:
5951 return match_reg_operand (arg
, operand
);
5954 return match_reg_pair_operand (arg
, operand
);
5957 return match_pcrel_operand (arg
);
5960 return match_perf_reg_operand (arg
, operand
);
5962 case OP_ADDIUSP_INT
:
5963 return match_addiusp_operand (arg
, operand
);
5965 case OP_CLO_CLZ_DEST
:
5966 return match_clo_clz_dest_operand (arg
, operand
);
5968 case OP_LWM_SWM_LIST
:
5969 return match_lwm_swm_list_operand (arg
, operand
);
5971 case OP_ENTRY_EXIT_LIST
:
5972 return match_entry_exit_operand (arg
, operand
);
5974 case OP_SAVE_RESTORE_LIST
:
5975 return match_save_restore_list_operand (arg
);
5977 case OP_MDMX_IMM_REG
:
5978 return match_mdmx_imm_reg_operand (arg
, operand
);
5980 case OP_REPEAT_DEST_REG
:
5981 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5983 case OP_REPEAT_PREV_REG
:
5984 return match_tied_reg_operand (arg
, arg
->last_regno
);
5987 return match_pc_operand (arg
);
5990 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5992 case OP_VU0_MATCH_SUFFIX
:
5993 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5996 return match_imm_index_operand (arg
, operand
);
5999 return match_reg_index_operand (arg
, operand
);
6002 return match_same_rs_rt_operand (arg
, operand
);
6005 return match_check_prev_operand (arg
, operand
);
6007 case OP_NON_ZERO_REG
:
6008 return match_non_zero_reg_operand (arg
, operand
);
6013 /* ARG is the state after successfully matching an instruction.
6014 Issue any queued-up warnings. */
6017 check_completed_insn (struct mips_arg_info
*arg
)
6022 as_warn (_("used $at without \".set noat\""));
6024 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6028 /* Return true if modifying general-purpose register REG needs a delay. */
6031 reg_needs_delay (unsigned int reg
)
6033 unsigned long prev_pinfo
;
6035 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6036 if (!mips_opts
.noreorder
6037 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6038 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6039 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6045 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6046 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6047 by VR4120 errata. */
6050 classify_vr4120_insn (const char *name
)
6052 if (strncmp (name
, "macc", 4) == 0)
6053 return FIX_VR4120_MACC
;
6054 if (strncmp (name
, "dmacc", 5) == 0)
6055 return FIX_VR4120_DMACC
;
6056 if (strncmp (name
, "mult", 4) == 0)
6057 return FIX_VR4120_MULT
;
6058 if (strncmp (name
, "dmult", 5) == 0)
6059 return FIX_VR4120_DMULT
;
6060 if (strstr (name
, "div"))
6061 return FIX_VR4120_DIV
;
6062 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6063 return FIX_VR4120_MTHILO
;
6064 return NUM_FIX_VR4120_CLASSES
;
6067 #define INSN_ERET 0x42000018
6068 #define INSN_DERET 0x4200001f
6069 #define INSN_DMULT 0x1c
6070 #define INSN_DMULTU 0x1d
6072 /* Return the number of instructions that must separate INSN1 and INSN2,
6073 where INSN1 is the earlier instruction. Return the worst-case value
6074 for any INSN2 if INSN2 is null. */
6077 insns_between (const struct mips_cl_insn
*insn1
,
6078 const struct mips_cl_insn
*insn2
)
6080 unsigned long pinfo1
, pinfo2
;
6083 /* If INFO2 is null, pessimistically assume that all flags are set for
6084 the second instruction. */
6085 pinfo1
= insn1
->insn_mo
->pinfo
;
6086 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6088 /* For most targets, write-after-read dependencies on the HI and LO
6089 registers must be separated by at least two instructions. */
6090 if (!hilo_interlocks
)
6092 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6094 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6098 /* If we're working around r7000 errata, there must be two instructions
6099 between an mfhi or mflo and any instruction that uses the result. */
6100 if (mips_7000_hilo_fix
6101 && !mips_opts
.micromips
6102 && MF_HILO_INSN (pinfo1
)
6103 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6106 /* If we're working around 24K errata, one instruction is required
6107 if an ERET or DERET is followed by a branch instruction. */
6108 if (mips_fix_24k
&& !mips_opts
.micromips
)
6110 if (insn1
->insn_opcode
== INSN_ERET
6111 || insn1
->insn_opcode
== INSN_DERET
)
6114 || insn2
->insn_opcode
== INSN_ERET
6115 || insn2
->insn_opcode
== INSN_DERET
6116 || delayed_branch_p (insn2
))
6121 /* If we're working around PMC RM7000 errata, there must be three
6122 nops between a dmult and a load instruction. */
6123 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6125 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6126 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6128 if (pinfo2
& INSN_LOAD_MEMORY
)
6133 /* If working around VR4120 errata, check for combinations that need
6134 a single intervening instruction. */
6135 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6137 unsigned int class1
, class2
;
6139 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6140 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6144 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6145 if (vr4120_conflicts
[class1
] & (1 << class2
))
6150 if (!HAVE_CODE_COMPRESSION
)
6152 /* Check for GPR or coprocessor load delays. All such delays
6153 are on the RT register. */
6154 /* Itbl support may require additional care here. */
6155 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6156 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6158 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6162 /* Check for generic coprocessor hazards.
6164 This case is not handled very well. There is no special
6165 knowledge of CP0 handling, and the coprocessors other than
6166 the floating point unit are not distinguished at all. */
6167 /* Itbl support may require additional care here. FIXME!
6168 Need to modify this to include knowledge about
6169 user specified delays! */
6170 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6171 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6173 /* Handle cases where INSN1 writes to a known general coprocessor
6174 register. There must be a one instruction delay before INSN2
6175 if INSN2 reads that register, otherwise no delay is needed. */
6176 mask
= fpr_write_mask (insn1
);
6179 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6184 /* Read-after-write dependencies on the control registers
6185 require a two-instruction gap. */
6186 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6187 && (pinfo2
& INSN_READ_COND_CODE
))
6190 /* We don't know exactly what INSN1 does. If INSN2 is
6191 also a coprocessor instruction, assume there must be
6192 a one instruction gap. */
6193 if (pinfo2
& INSN_COP
)
6198 /* Check for read-after-write dependencies on the coprocessor
6199 control registers in cases where INSN1 does not need a general
6200 coprocessor delay. This means that INSN1 is a floating point
6201 comparison instruction. */
6202 /* Itbl support may require additional care here. */
6203 else if (!cop_interlocks
6204 && (pinfo1
& INSN_WRITE_COND_CODE
)
6205 && (pinfo2
& INSN_READ_COND_CODE
))
6209 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6210 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6212 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6213 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6214 || (insn2
&& delayed_branch_p (insn2
))))
6220 /* Return the number of nops that would be needed to work around the
6221 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6222 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6223 that are contained within the first IGNORE instructions of HIST. */
6226 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6227 const struct mips_cl_insn
*insn
)
6232 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6233 are not affected by the errata. */
6235 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6236 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6237 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6240 /* Search for the first MFLO or MFHI. */
6241 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6242 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6244 /* Extract the destination register. */
6245 mask
= gpr_write_mask (&hist
[i
]);
6247 /* No nops are needed if INSN reads that register. */
6248 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6251 /* ...or if any of the intervening instructions do. */
6252 for (j
= 0; j
< i
; j
++)
6253 if (gpr_read_mask (&hist
[j
]) & mask
)
6257 return MAX_VR4130_NOPS
- i
;
6262 #define BASE_REG_EQ(INSN1, INSN2) \
6263 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6264 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6266 /* Return the minimum alignment for this store instruction. */
6269 fix_24k_align_to (const struct mips_opcode
*mo
)
6271 if (strcmp (mo
->name
, "sh") == 0)
6274 if (strcmp (mo
->name
, "swc1") == 0
6275 || strcmp (mo
->name
, "swc2") == 0
6276 || strcmp (mo
->name
, "sw") == 0
6277 || strcmp (mo
->name
, "sc") == 0
6278 || strcmp (mo
->name
, "s.s") == 0)
6281 if (strcmp (mo
->name
, "sdc1") == 0
6282 || strcmp (mo
->name
, "sdc2") == 0
6283 || strcmp (mo
->name
, "s.d") == 0)
6290 struct fix_24k_store_info
6292 /* Immediate offset, if any, for this store instruction. */
6294 /* Alignment required by this store instruction. */
6296 /* True for register offsets. */
6297 int register_offset
;
6300 /* Comparison function used by qsort. */
6303 fix_24k_sort (const void *a
, const void *b
)
6305 const struct fix_24k_store_info
*pos1
= a
;
6306 const struct fix_24k_store_info
*pos2
= b
;
6308 return (pos1
->off
- pos2
->off
);
6311 /* INSN is a store instruction. Try to record the store information
6312 in STINFO. Return false if the information isn't known. */
6315 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6316 const struct mips_cl_insn
*insn
)
6318 /* The instruction must have a known offset. */
6319 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6322 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6323 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6327 /* Return the number of nops that would be needed to work around the 24k
6328 "lost data on stores during refill" errata if instruction INSN
6329 immediately followed the 2 instructions described by HIST.
6330 Ignore hazards that are contained within the first IGNORE
6331 instructions of HIST.
6333 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6334 for the data cache refills and store data. The following describes
6335 the scenario where the store data could be lost.
6337 * A data cache miss, due to either a load or a store, causing fill
6338 data to be supplied by the memory subsystem
6339 * The first three doublewords of fill data are returned and written
6341 * A sequence of four stores occurs in consecutive cycles around the
6342 final doubleword of the fill:
6346 * Zero, One or more instructions
6349 The four stores A-D must be to different doublewords of the line that
6350 is being filled. The fourth instruction in the sequence above permits
6351 the fill of the final doubleword to be transferred from the FSB into
6352 the cache. In the sequence above, the stores may be either integer
6353 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6354 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6355 different doublewords on the line. If the floating point unit is
6356 running in 1:2 mode, it is not possible to create the sequence above
6357 using only floating point store instructions.
6359 In this case, the cache line being filled is incorrectly marked
6360 invalid, thereby losing the data from any store to the line that
6361 occurs between the original miss and the completion of the five
6362 cycle sequence shown above.
6364 The workarounds are:
6366 * Run the data cache in write-through mode.
6367 * Insert a non-store instruction between
6368 Store A and Store B or Store B and Store C. */
6371 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6372 const struct mips_cl_insn
*insn
)
6374 struct fix_24k_store_info pos
[3];
6375 int align
, i
, base_offset
;
6380 /* If the previous instruction wasn't a store, there's nothing to
6382 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6385 /* If the instructions after the previous one are unknown, we have
6386 to assume the worst. */
6390 /* Check whether we are dealing with three consecutive stores. */
6391 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6392 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6395 /* If we don't know the relationship between the store addresses,
6396 assume the worst. */
6397 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6398 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6401 if (!fix_24k_record_store_info (&pos
[0], insn
)
6402 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6403 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6406 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6408 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6409 X bytes and such that the base register + X is known to be aligned
6412 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6416 align
= pos
[0].align_to
;
6417 base_offset
= pos
[0].off
;
6418 for (i
= 1; i
< 3; i
++)
6419 if (align
< pos
[i
].align_to
)
6421 align
= pos
[i
].align_to
;
6422 base_offset
= pos
[i
].off
;
6424 for (i
= 0; i
< 3; i
++)
6425 pos
[i
].off
-= base_offset
;
6428 pos
[0].off
&= ~align
+ 1;
6429 pos
[1].off
&= ~align
+ 1;
6430 pos
[2].off
&= ~align
+ 1;
6432 /* If any two stores write to the same chunk, they also write to the
6433 same doubleword. The offsets are still sorted at this point. */
6434 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6437 /* A range of at least 9 bytes is needed for the stores to be in
6438 non-overlapping doublewords. */
6439 if (pos
[2].off
- pos
[0].off
<= 8)
6442 if (pos
[2].off
- pos
[1].off
>= 24
6443 || pos
[1].off
- pos
[0].off
>= 24
6444 || pos
[2].off
- pos
[0].off
>= 32)
6450 /* Return the number of nops that would be needed if instruction INSN
6451 immediately followed the MAX_NOPS instructions given by HIST,
6452 where HIST[0] is the most recent instruction. Ignore hazards
6453 between INSN and the first IGNORE instructions in HIST.
6455 If INSN is null, return the worse-case number of nops for any
6459 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6460 const struct mips_cl_insn
*insn
)
6462 int i
, nops
, tmp_nops
;
6465 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6467 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6468 if (tmp_nops
> nops
)
6472 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6474 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6475 if (tmp_nops
> nops
)
6479 if (mips_fix_24k
&& !mips_opts
.micromips
)
6481 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6482 if (tmp_nops
> nops
)
6489 /* The variable arguments provide NUM_INSNS extra instructions that
6490 might be added to HIST. Return the largest number of nops that
6491 would be needed after the extended sequence, ignoring hazards
6492 in the first IGNORE instructions. */
6495 nops_for_sequence (int num_insns
, int ignore
,
6496 const struct mips_cl_insn
*hist
, ...)
6499 struct mips_cl_insn buffer
[MAX_NOPS
];
6500 struct mips_cl_insn
*cursor
;
6503 va_start (args
, hist
);
6504 cursor
= buffer
+ num_insns
;
6505 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6506 while (cursor
> buffer
)
6507 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6509 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6514 /* Like nops_for_insn, but if INSN is a branch, take into account the
6515 worst-case delay for the branch target. */
6518 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6519 const struct mips_cl_insn
*insn
)
6523 nops
= nops_for_insn (ignore
, hist
, insn
);
6524 if (delayed_branch_p (insn
))
6526 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6527 hist
, insn
, get_delay_slot_nop (insn
));
6528 if (tmp_nops
> nops
)
6531 else if (compact_branch_p (insn
))
6533 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6534 if (tmp_nops
> nops
)
6540 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6543 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6545 gas_assert (!HAVE_CODE_COMPRESSION
);
6546 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6547 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6550 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6551 jr target pc &= 'hffff_ffff_cfff_ffff. */
6554 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6556 gas_assert (!HAVE_CODE_COMPRESSION
);
6557 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6558 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6559 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6567 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6568 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6571 ep
.X_op
= O_constant
;
6572 ep
.X_add_number
= 0xcfff0000;
6573 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6574 ep
.X_add_number
= 0xffff;
6575 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6576 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6581 fix_loongson2f (struct mips_cl_insn
* ip
)
6583 if (mips_fix_loongson2f_nop
)
6584 fix_loongson2f_nop (ip
);
6586 if (mips_fix_loongson2f_jump
)
6587 fix_loongson2f_jump (ip
);
6590 /* IP is a branch that has a delay slot, and we need to fill it
6591 automatically. Return true if we can do that by swapping IP
6592 with the previous instruction.
6593 ADDRESS_EXPR is an operand of the instruction to be used with
6597 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6598 bfd_reloc_code_real_type
*reloc_type
)
6600 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6601 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6602 unsigned int fpr_read
, prev_fpr_write
;
6604 /* -O2 and above is required for this optimization. */
6605 if (mips_optimize
< 2)
6608 /* If we have seen .set volatile or .set nomove, don't optimize. */
6609 if (mips_opts
.nomove
)
6612 /* We can't swap if the previous instruction's position is fixed. */
6613 if (history
[0].fixed_p
)
6616 /* If the previous previous insn was in a .set noreorder, we can't
6617 swap. Actually, the MIPS assembler will swap in this situation.
6618 However, gcc configured -with-gnu-as will generate code like
6626 in which we can not swap the bne and INSN. If gcc is not configured
6627 -with-gnu-as, it does not output the .set pseudo-ops. */
6628 if (history
[1].noreorder_p
)
6631 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6632 This means that the previous instruction was a 4-byte one anyhow. */
6633 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6636 /* If the branch is itself the target of a branch, we can not swap.
6637 We cheat on this; all we check for is whether there is a label on
6638 this instruction. If there are any branches to anything other than
6639 a label, users must use .set noreorder. */
6640 if (seg_info (now_seg
)->label_list
)
6643 /* If the previous instruction is in a variant frag other than this
6644 branch's one, we cannot do the swap. This does not apply to
6645 MIPS16 code, which uses variant frags for different purposes. */
6646 if (!mips_opts
.mips16
6648 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6651 /* We do not swap with instructions that cannot architecturally
6652 be placed in a branch delay slot, such as SYNC or ERET. We
6653 also refrain from swapping with a trap instruction, since it
6654 complicates trap handlers to have the trap instruction be in
6656 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6657 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6660 /* Check for conflicts between the branch and the instructions
6661 before the candidate delay slot. */
6662 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6665 /* Check for conflicts between the swapped sequence and the
6666 target of the branch. */
6667 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6670 /* If the branch reads a register that the previous
6671 instruction sets, we can not swap. */
6672 gpr_read
= gpr_read_mask (ip
);
6673 prev_gpr_write
= gpr_write_mask (&history
[0]);
6674 if (gpr_read
& prev_gpr_write
)
6677 fpr_read
= fpr_read_mask (ip
);
6678 prev_fpr_write
= fpr_write_mask (&history
[0]);
6679 if (fpr_read
& prev_fpr_write
)
6682 /* If the branch writes a register that the previous
6683 instruction sets, we can not swap. */
6684 gpr_write
= gpr_write_mask (ip
);
6685 if (gpr_write
& prev_gpr_write
)
6688 /* If the branch writes a register that the previous
6689 instruction reads, we can not swap. */
6690 prev_gpr_read
= gpr_read_mask (&history
[0]);
6691 if (gpr_write
& prev_gpr_read
)
6694 /* If one instruction sets a condition code and the
6695 other one uses a condition code, we can not swap. */
6696 pinfo
= ip
->insn_mo
->pinfo
;
6697 if ((pinfo
& INSN_READ_COND_CODE
)
6698 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6700 if ((pinfo
& INSN_WRITE_COND_CODE
)
6701 && (prev_pinfo
& INSN_READ_COND_CODE
))
6704 /* If the previous instruction uses the PC, we can not swap. */
6705 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6706 if (prev_pinfo2
& INSN2_READ_PC
)
6709 /* If the previous instruction has an incorrect size for a fixed
6710 branch delay slot in microMIPS mode, we cannot swap. */
6711 pinfo2
= ip
->insn_mo
->pinfo2
;
6712 if (mips_opts
.micromips
6713 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6714 && insn_length (history
) != 2)
6716 if (mips_opts
.micromips
6717 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6718 && insn_length (history
) != 4)
6721 /* On R5900 short loops need to be fixed by inserting a nop in
6722 the branch delay slots.
6723 A short loop can be terminated too early. */
6724 if (mips_opts
.arch
== CPU_R5900
6725 /* Check if instruction has a parameter, ignore "j $31". */
6726 && (address_expr
!= NULL
)
6727 /* Parameter must be 16 bit. */
6728 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6729 /* Branch to same segment. */
6730 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6731 /* Branch to same code fragment. */
6732 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6733 /* Can only calculate branch offset if value is known. */
6734 && symbol_constant_p(address_expr
->X_add_symbol
)
6735 /* Check if branch is really conditional. */
6736 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6737 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6738 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6741 /* Check if loop is shorter than 6 instructions including
6742 branch and delay slot. */
6743 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6750 /* When the loop includes branches or jumps,
6751 it is not a short loop. */
6752 for (i
= 0; i
< (distance
/ 4); i
++)
6754 if ((history
[i
].cleared_p
)
6755 || delayed_branch_p(&history
[i
]))
6763 /* Insert nop after branch to fix short loop. */
6772 /* Decide how we should add IP to the instruction stream.
6773 ADDRESS_EXPR is an operand of the instruction to be used with
6776 static enum append_method
6777 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6778 bfd_reloc_code_real_type
*reloc_type
)
6780 /* The relaxed version of a macro sequence must be inherently
6782 if (mips_relax
.sequence
== 2)
6785 /* We must not dabble with instructions in a ".set norerorder" block. */
6786 if (mips_opts
.noreorder
)
6789 /* Otherwise, it's our responsibility to fill branch delay slots. */
6790 if (delayed_branch_p (ip
))
6792 if (!branch_likely_p (ip
)
6793 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6796 if (mips_opts
.mips16
6797 && ISA_SUPPORTS_MIPS16E
6798 && gpr_read_mask (ip
) != 0)
6799 return APPEND_ADD_COMPACT
;
6801 return APPEND_ADD_WITH_NOP
;
6807 /* IP is a MIPS16 instruction whose opcode we have just changed.
6808 Point IP->insn_mo to the new opcode's definition. */
6811 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6813 const struct mips_opcode
*mo
, *end
;
6815 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6816 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6817 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6825 /* For microMIPS macros, we need to generate a local number label
6826 as the target of branches. */
6827 #define MICROMIPS_LABEL_CHAR '\037'
6828 static unsigned long micromips_target_label
;
6829 static char micromips_target_name
[32];
6832 micromips_label_name (void)
6834 char *p
= micromips_target_name
;
6835 char symbol_name_temporary
[24];
6843 l
= micromips_target_label
;
6844 #ifdef LOCAL_LABEL_PREFIX
6845 *p
++ = LOCAL_LABEL_PREFIX
;
6848 *p
++ = MICROMIPS_LABEL_CHAR
;
6851 symbol_name_temporary
[i
++] = l
% 10 + '0';
6856 *p
++ = symbol_name_temporary
[--i
];
6859 return micromips_target_name
;
6863 micromips_label_expr (expressionS
*label_expr
)
6865 label_expr
->X_op
= O_symbol
;
6866 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6867 label_expr
->X_add_number
= 0;
6871 micromips_label_inc (void)
6873 micromips_target_label
++;
6874 *micromips_target_name
= '\0';
6878 micromips_add_label (void)
6882 s
= colon (micromips_label_name ());
6883 micromips_label_inc ();
6884 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6887 /* If assembling microMIPS code, then return the microMIPS reloc
6888 corresponding to the requested one if any. Otherwise return
6889 the reloc unchanged. */
6891 static bfd_reloc_code_real_type
6892 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6894 static const bfd_reloc_code_real_type relocs
[][2] =
6896 /* Keep sorted incrementally by the left-hand key. */
6897 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6898 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6899 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6900 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6901 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6902 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6903 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6904 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6905 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6906 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6907 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6908 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6909 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6910 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6911 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6912 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6913 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6914 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6915 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6916 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6917 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6918 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6919 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6920 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6921 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6922 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6923 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6925 bfd_reloc_code_real_type r
;
6928 if (!mips_opts
.micromips
)
6930 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6936 return relocs
[i
][1];
6941 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6942 Return true on success, storing the resolved value in RESULT. */
6945 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6950 case BFD_RELOC_MIPS_HIGHEST
:
6951 case BFD_RELOC_MICROMIPS_HIGHEST
:
6952 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6955 case BFD_RELOC_MIPS_HIGHER
:
6956 case BFD_RELOC_MICROMIPS_HIGHER
:
6957 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6960 case BFD_RELOC_HI16_S
:
6961 case BFD_RELOC_MICROMIPS_HI16_S
:
6962 case BFD_RELOC_MIPS16_HI16_S
:
6963 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6966 case BFD_RELOC_HI16
:
6967 case BFD_RELOC_MICROMIPS_HI16
:
6968 case BFD_RELOC_MIPS16_HI16
:
6969 *result
= (operand
>> 16) & 0xffff;
6972 case BFD_RELOC_LO16
:
6973 case BFD_RELOC_MICROMIPS_LO16
:
6974 case BFD_RELOC_MIPS16_LO16
:
6975 *result
= operand
& 0xffff;
6978 case BFD_RELOC_UNUSED
:
6987 /* Output an instruction. IP is the instruction information.
6988 ADDRESS_EXPR is an operand of the instruction to be used with
6989 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6990 a macro expansion. */
6993 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6994 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6996 unsigned long prev_pinfo2
, pinfo
;
6997 bfd_boolean relaxed_branch
= FALSE
;
6998 enum append_method method
;
6999 bfd_boolean relax32
;
7002 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7003 fix_loongson2f (ip
);
7005 file_ase_mips16
|= mips_opts
.mips16
;
7006 file_ase_micromips
|= mips_opts
.micromips
;
7008 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7009 pinfo
= ip
->insn_mo
->pinfo
;
7011 if (mips_opts
.micromips
7013 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7014 && micromips_insn_length (ip
->insn_mo
) != 2)
7015 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7016 && micromips_insn_length (ip
->insn_mo
) != 4)))
7017 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7018 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7020 if (address_expr
== NULL
)
7022 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7023 && reloc_type
[1] == BFD_RELOC_UNUSED
7024 && reloc_type
[2] == BFD_RELOC_UNUSED
7025 && address_expr
->X_op
== O_constant
)
7027 switch (*reloc_type
)
7029 case BFD_RELOC_MIPS_JMP
:
7033 shift
= mips_opts
.micromips
? 1 : 2;
7034 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7035 as_bad (_("jump to misaligned address (0x%lx)"),
7036 (unsigned long) address_expr
->X_add_number
);
7037 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7043 case BFD_RELOC_MIPS16_JMP
:
7044 if ((address_expr
->X_add_number
& 3) != 0)
7045 as_bad (_("jump to misaligned address (0x%lx)"),
7046 (unsigned long) address_expr
->X_add_number
);
7048 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7049 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7050 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7054 case BFD_RELOC_16_PCREL_S2
:
7058 shift
= mips_opts
.micromips
? 1 : 2;
7059 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7060 as_bad (_("branch to misaligned address (0x%lx)"),
7061 (unsigned long) address_expr
->X_add_number
);
7062 if (!mips_relax_branch
)
7064 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7065 & ~((1 << (shift
+ 16)) - 1))
7066 as_bad (_("branch address range overflow (0x%lx)"),
7067 (unsigned long) address_expr
->X_add_number
);
7068 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7074 case BFD_RELOC_MIPS_21_PCREL_S2
:
7079 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7080 as_bad (_("branch to misaligned address (0x%lx)"),
7081 (unsigned long) address_expr
->X_add_number
);
7082 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7083 & ~((1 << (shift
+ 21)) - 1))
7084 as_bad (_("branch address range overflow (0x%lx)"),
7085 (unsigned long) address_expr
->X_add_number
);
7086 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7091 case BFD_RELOC_MIPS_26_PCREL_S2
:
7096 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7097 as_bad (_("branch to misaligned address (0x%lx)"),
7098 (unsigned long) address_expr
->X_add_number
);
7099 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7100 & ~((1 << (shift
+ 26)) - 1))
7101 as_bad (_("branch address range overflow (0x%lx)"),
7102 (unsigned long) address_expr
->X_add_number
);
7103 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7112 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7115 ip
->insn_opcode
|= value
& 0xffff;
7123 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7125 /* There are a lot of optimizations we could do that we don't.
7126 In particular, we do not, in general, reorder instructions.
7127 If you use gcc with optimization, it will reorder
7128 instructions and generally do much more optimization then we
7129 do here; repeating all that work in the assembler would only
7130 benefit hand written assembly code, and does not seem worth
7132 int nops
= (mips_optimize
== 0
7133 ? nops_for_insn (0, history
, NULL
)
7134 : nops_for_insn_or_target (0, history
, ip
));
7138 unsigned long old_frag_offset
;
7141 old_frag
= frag_now
;
7142 old_frag_offset
= frag_now_fix ();
7144 for (i
= 0; i
< nops
; i
++)
7145 add_fixed_insn (NOP_INSN
);
7146 insert_into_history (0, nops
, NOP_INSN
);
7150 listing_prev_line ();
7151 /* We may be at the start of a variant frag. In case we
7152 are, make sure there is enough space for the frag
7153 after the frags created by listing_prev_line. The
7154 argument to frag_grow here must be at least as large
7155 as the argument to all other calls to frag_grow in
7156 this file. We don't have to worry about being in the
7157 middle of a variant frag, because the variants insert
7158 all needed nop instructions themselves. */
7162 mips_move_text_labels ();
7164 #ifndef NO_ECOFF_DEBUGGING
7165 if (ECOFF_DEBUGGING
)
7166 ecoff_fix_loc (old_frag
, old_frag_offset
);
7170 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7174 /* Work out how many nops in prev_nop_frag are needed by IP,
7175 ignoring hazards generated by the first prev_nop_frag_since
7177 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7178 gas_assert (nops
<= prev_nop_frag_holds
);
7180 /* Enforce NOPS as a minimum. */
7181 if (nops
> prev_nop_frag_required
)
7182 prev_nop_frag_required
= nops
;
7184 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7186 /* Settle for the current number of nops. Update the history
7187 accordingly (for the benefit of any future .set reorder code). */
7188 prev_nop_frag
= NULL
;
7189 insert_into_history (prev_nop_frag_since
,
7190 prev_nop_frag_holds
, NOP_INSN
);
7194 /* Allow this instruction to replace one of the nops that was
7195 tentatively added to prev_nop_frag. */
7196 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7197 prev_nop_frag_holds
--;
7198 prev_nop_frag_since
++;
7202 method
= get_append_method (ip
, address_expr
, reloc_type
);
7203 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7205 dwarf2_emit_insn (0);
7206 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7207 so "move" the instruction address accordingly.
7209 Also, it doesn't seem appropriate for the assembler to reorder .loc
7210 entries. If this instruction is a branch that we are going to swap
7211 with the previous instruction, the two instructions should be
7212 treated as a unit, and the debug information for both instructions
7213 should refer to the start of the branch sequence. Using the
7214 current position is certainly wrong when swapping a 32-bit branch
7215 and a 16-bit delay slot, since the current position would then be
7216 in the middle of a branch. */
7217 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7219 relax32
= (mips_relax_branch
7220 /* Don't try branch relaxation within .set nomacro, or within
7221 .set noat if we use $at for PIC computations. If it turns
7222 out that the branch was out-of-range, we'll get an error. */
7223 && !mips_opts
.warn_about_macros
7224 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7225 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7226 as they have no complementing branches. */
7227 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7229 if (!HAVE_CODE_COMPRESSION
7232 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7233 && delayed_branch_p (ip
))
7235 relaxed_branch
= TRUE
;
7236 add_relaxed_insn (ip
, (relaxed_branch_length
7238 uncond_branch_p (ip
) ? -1
7239 : branch_likely_p (ip
) ? 1
7243 uncond_branch_p (ip
),
7244 branch_likely_p (ip
),
7245 pinfo
& INSN_WRITE_GPR_31
,
7247 address_expr
->X_add_symbol
,
7248 address_expr
->X_add_number
);
7249 *reloc_type
= BFD_RELOC_UNUSED
;
7251 else if (mips_opts
.micromips
7253 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7254 || *reloc_type
> BFD_RELOC_UNUSED
)
7255 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7256 /* Don't try branch relaxation when users specify
7257 16-bit/32-bit instructions. */
7258 && !forced_insn_length
)
7260 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
7261 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7262 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7263 int compact
= compact_branch_p (ip
);
7264 int al
= pinfo
& INSN_WRITE_GPR_31
;
7267 gas_assert (address_expr
!= NULL
);
7268 gas_assert (!mips_relax
.sequence
);
7270 relaxed_branch
= TRUE
;
7271 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7272 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
7273 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
7275 address_expr
->X_add_symbol
,
7276 address_expr
->X_add_number
);
7277 *reloc_type
= BFD_RELOC_UNUSED
;
7279 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7281 /* We need to set up a variant frag. */
7282 gas_assert (address_expr
!= NULL
);
7283 add_relaxed_insn (ip
, 4, 0,
7285 (*reloc_type
- BFD_RELOC_UNUSED
,
7286 forced_insn_length
== 2, forced_insn_length
== 4,
7287 delayed_branch_p (&history
[0]),
7288 history
[0].mips16_absolute_jump_p
),
7289 make_expr_symbol (address_expr
), 0);
7291 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7293 if (!delayed_branch_p (ip
))
7294 /* Make sure there is enough room to swap this instruction with
7295 a following jump instruction. */
7297 add_fixed_insn (ip
);
7301 if (mips_opts
.mips16
7302 && mips_opts
.noreorder
7303 && delayed_branch_p (&history
[0]))
7304 as_warn (_("extended instruction in delay slot"));
7306 if (mips_relax
.sequence
)
7308 /* If we've reached the end of this frag, turn it into a variant
7309 frag and record the information for the instructions we've
7311 if (frag_room () < 4)
7312 relax_close_frag ();
7313 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7316 if (mips_relax
.sequence
!= 2)
7318 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7319 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7320 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7321 mips_macro_warning
.insns
[0]++;
7323 if (mips_relax
.sequence
!= 1)
7325 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7326 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7327 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7328 mips_macro_warning
.insns
[1]++;
7331 if (mips_opts
.mips16
)
7334 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7336 add_fixed_insn (ip
);
7339 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7341 bfd_reloc_code_real_type final_type
[3];
7342 reloc_howto_type
*howto0
;
7343 reloc_howto_type
*howto
;
7346 /* Perform any necessary conversion to microMIPS relocations
7347 and find out how many relocations there actually are. */
7348 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7349 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7351 /* In a compound relocation, it is the final (outermost)
7352 operator that determines the relocated field. */
7353 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7358 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7359 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7360 bfd_get_reloc_size (howto
),
7362 howto0
&& howto0
->pc_relative
,
7365 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7366 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7367 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7369 /* These relocations can have an addend that won't fit in
7370 4 octets for 64bit assembly. */
7372 && ! howto
->partial_inplace
7373 && (reloc_type
[0] == BFD_RELOC_16
7374 || reloc_type
[0] == BFD_RELOC_32
7375 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7376 || reloc_type
[0] == BFD_RELOC_GPREL16
7377 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7378 || reloc_type
[0] == BFD_RELOC_GPREL32
7379 || reloc_type
[0] == BFD_RELOC_64
7380 || reloc_type
[0] == BFD_RELOC_CTOR
7381 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7382 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7383 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7384 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7385 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7386 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7387 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7388 || hi16_reloc_p (reloc_type
[0])
7389 || lo16_reloc_p (reloc_type
[0])))
7390 ip
->fixp
[0]->fx_no_overflow
= 1;
7392 /* These relocations can have an addend that won't fit in 2 octets. */
7393 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7394 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7395 ip
->fixp
[0]->fx_no_overflow
= 1;
7397 if (mips_relax
.sequence
)
7399 if (mips_relax
.first_fixup
== 0)
7400 mips_relax
.first_fixup
= ip
->fixp
[0];
7402 else if (reloc_needs_lo_p (*reloc_type
))
7404 struct mips_hi_fixup
*hi_fixup
;
7406 /* Reuse the last entry if it already has a matching %lo. */
7407 hi_fixup
= mips_hi_fixup_list
;
7409 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7411 hi_fixup
= ((struct mips_hi_fixup
*)
7412 xmalloc (sizeof (struct mips_hi_fixup
)));
7413 hi_fixup
->next
= mips_hi_fixup_list
;
7414 mips_hi_fixup_list
= hi_fixup
;
7416 hi_fixup
->fixp
= ip
->fixp
[0];
7417 hi_fixup
->seg
= now_seg
;
7420 /* Add fixups for the second and third relocations, if given.
7421 Note that the ABI allows the second relocation to be
7422 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7423 moment we only use RSS_UNDEF, but we could add support
7424 for the others if it ever becomes necessary. */
7425 for (i
= 1; i
< 3; i
++)
7426 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7428 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7429 ip
->fixp
[0]->fx_size
, NULL
, 0,
7430 FALSE
, final_type
[i
]);
7432 /* Use fx_tcbit to mark compound relocs. */
7433 ip
->fixp
[0]->fx_tcbit
= 1;
7434 ip
->fixp
[i
]->fx_tcbit
= 1;
7439 /* Update the register mask information. */
7440 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7441 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7446 insert_into_history (0, 1, ip
);
7449 case APPEND_ADD_WITH_NOP
:
7451 struct mips_cl_insn
*nop
;
7453 insert_into_history (0, 1, ip
);
7454 nop
= get_delay_slot_nop (ip
);
7455 add_fixed_insn (nop
);
7456 insert_into_history (0, 1, nop
);
7457 if (mips_relax
.sequence
)
7458 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7462 case APPEND_ADD_COMPACT
:
7463 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7464 gas_assert (mips_opts
.mips16
);
7465 ip
->insn_opcode
|= 0x0080;
7466 find_altered_mips16_opcode (ip
);
7468 insert_into_history (0, 1, ip
);
7473 struct mips_cl_insn delay
= history
[0];
7474 if (mips_opts
.mips16
)
7476 know (delay
.frag
== ip
->frag
);
7477 move_insn (ip
, delay
.frag
, delay
.where
);
7478 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7480 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7482 /* Add the delay slot instruction to the end of the
7483 current frag and shrink the fixed part of the
7484 original frag. If the branch occupies the tail of
7485 the latter, move it backwards to cover the gap. */
7486 delay
.frag
->fr_fix
-= branch_disp
;
7487 if (delay
.frag
== ip
->frag
)
7488 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7489 add_fixed_insn (&delay
);
7493 move_insn (&delay
, ip
->frag
,
7494 ip
->where
- branch_disp
+ insn_length (ip
));
7495 move_insn (ip
, history
[0].frag
, history
[0].where
);
7499 insert_into_history (0, 1, &delay
);
7504 /* If we have just completed an unconditional branch, clear the history. */
7505 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7506 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7510 mips_no_prev_insn ();
7512 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7513 history
[i
].cleared_p
= 1;
7516 /* We need to emit a label at the end of branch-likely macros. */
7517 if (emit_branch_likely_macro
)
7519 emit_branch_likely_macro
= FALSE
;
7520 micromips_add_label ();
7523 /* We just output an insn, so the next one doesn't have a label. */
7524 mips_clear_insn_labels ();
7527 /* Forget that there was any previous instruction or label.
7528 When BRANCH is true, the branch history is also flushed. */
7531 mips_no_prev_insn (void)
7533 prev_nop_frag
= NULL
;
7534 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7535 mips_clear_insn_labels ();
7538 /* This function must be called before we emit something other than
7539 instructions. It is like mips_no_prev_insn except that it inserts
7540 any NOPS that might be needed by previous instructions. */
7543 mips_emit_delays (void)
7545 if (! mips_opts
.noreorder
)
7547 int nops
= nops_for_insn (0, history
, NULL
);
7551 add_fixed_insn (NOP_INSN
);
7552 mips_move_text_labels ();
7555 mips_no_prev_insn ();
7558 /* Start a (possibly nested) noreorder block. */
7561 start_noreorder (void)
7563 if (mips_opts
.noreorder
== 0)
7568 /* None of the instructions before the .set noreorder can be moved. */
7569 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7570 history
[i
].fixed_p
= 1;
7572 /* Insert any nops that might be needed between the .set noreorder
7573 block and the previous instructions. We will later remove any
7574 nops that turn out not to be needed. */
7575 nops
= nops_for_insn (0, history
, NULL
);
7578 if (mips_optimize
!= 0)
7580 /* Record the frag which holds the nop instructions, so
7581 that we can remove them if we don't need them. */
7582 frag_grow (nops
* NOP_INSN_SIZE
);
7583 prev_nop_frag
= frag_now
;
7584 prev_nop_frag_holds
= nops
;
7585 prev_nop_frag_required
= 0;
7586 prev_nop_frag_since
= 0;
7589 for (; nops
> 0; --nops
)
7590 add_fixed_insn (NOP_INSN
);
7592 /* Move on to a new frag, so that it is safe to simply
7593 decrease the size of prev_nop_frag. */
7594 frag_wane (frag_now
);
7596 mips_move_text_labels ();
7598 mips_mark_labels ();
7599 mips_clear_insn_labels ();
7601 mips_opts
.noreorder
++;
7602 mips_any_noreorder
= 1;
7605 /* End a nested noreorder block. */
7608 end_noreorder (void)
7610 mips_opts
.noreorder
--;
7611 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7613 /* Commit to inserting prev_nop_frag_required nops and go back to
7614 handling nop insertion the .set reorder way. */
7615 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7617 insert_into_history (prev_nop_frag_since
,
7618 prev_nop_frag_required
, NOP_INSN
);
7619 prev_nop_frag
= NULL
;
7623 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7624 higher bits unset. */
7627 normalize_constant_expr (expressionS
*ex
)
7629 if (ex
->X_op
== O_constant
7630 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7631 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7635 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7636 all higher bits unset. */
7639 normalize_address_expr (expressionS
*ex
)
7641 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7642 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7643 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7644 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7648 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7649 Return true if the match was successful.
7651 OPCODE_EXTRA is a value that should be ORed into the opcode
7652 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7653 there are more alternatives after OPCODE and SOFT_MATCH is
7654 as for mips_arg_info. */
7657 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7658 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7659 bfd_boolean lax_match
, bfd_boolean complete_p
)
7662 struct mips_arg_info arg
;
7663 const struct mips_operand
*operand
;
7666 imm_expr
.X_op
= O_absent
;
7667 offset_expr
.X_op
= O_absent
;
7668 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7669 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7670 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7672 create_insn (insn
, opcode
);
7673 /* When no opcode suffix is specified, assume ".xyzw". */
7674 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7675 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7677 insn
->insn_opcode
|= opcode_extra
;
7678 memset (&arg
, 0, sizeof (arg
));
7682 arg
.last_regno
= ILLEGAL_REG
;
7683 arg
.dest_regno
= ILLEGAL_REG
;
7684 arg
.lax_match
= lax_match
;
7685 for (args
= opcode
->args
;; ++args
)
7687 if (arg
.token
->type
== OT_END
)
7689 /* Handle unary instructions in which only one operand is given.
7690 The source is then the same as the destination. */
7691 if (arg
.opnum
== 1 && *args
== ',')
7693 operand
= (mips_opts
.micromips
7694 ? decode_micromips_operand (args
+ 1)
7695 : decode_mips_operand (args
+ 1));
7696 if (operand
&& mips_optional_operand_p (operand
))
7704 /* Treat elided base registers as $0. */
7705 if (strcmp (args
, "(b)") == 0)
7713 /* The register suffix is optional. */
7718 /* Fail the match if there were too few operands. */
7722 /* Successful match. */
7725 clear_insn_error ();
7726 if (arg
.dest_regno
== arg
.last_regno
7727 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7731 (0, _("source and destination must be different"));
7732 else if (arg
.last_regno
== 31)
7734 (0, _("a destination register must be supplied"));
7736 else if (arg
.last_regno
== 31
7737 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7738 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7739 set_insn_error (0, _("the source register must not be $31"));
7740 check_completed_insn (&arg
);
7744 /* Fail the match if the line has too many operands. */
7748 /* Handle characters that need to match exactly. */
7749 if (*args
== '(' || *args
== ')' || *args
== ',')
7751 if (match_char (&arg
, *args
))
7758 if (arg
.token
->type
== OT_DOUBLE_CHAR
7759 && arg
.token
->u
.ch
== *args
)
7767 /* Handle special macro operands. Work out the properties of
7776 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7780 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7789 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7793 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7797 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7803 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7805 imm_expr
.X_op
= O_constant
;
7807 normalize_constant_expr (&imm_expr
);
7811 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7813 /* Assume that the offset has been elided and that what
7814 we saw was a base register. The match will fail later
7815 if that assumption turns out to be wrong. */
7816 offset_expr
.X_op
= O_constant
;
7817 offset_expr
.X_add_number
= 0;
7821 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7823 normalize_address_expr (&offset_expr
);
7828 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7834 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7840 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7846 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7852 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7856 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7860 gas_assert (mips_opts
.micromips
);
7866 if (!forced_insn_length
)
7867 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7869 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7871 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7877 operand
= (mips_opts
.micromips
7878 ? decode_micromips_operand (args
)
7879 : decode_mips_operand (args
));
7883 /* Skip prefixes. */
7884 if (*args
== '+' || *args
== 'm' || *args
== '-')
7887 if (mips_optional_operand_p (operand
)
7889 && (arg
.token
[0].type
!= OT_REG
7890 || arg
.token
[1].type
== OT_END
))
7892 /* Assume that the register has been elided and is the
7893 same as the first operand. */
7898 if (!match_operand (&arg
, operand
))
7903 /* Like match_insn, but for MIPS16. */
7906 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7907 struct mips_operand_token
*tokens
)
7910 const struct mips_operand
*operand
;
7911 const struct mips_operand
*ext_operand
;
7912 struct mips_arg_info arg
;
7915 create_insn (insn
, opcode
);
7916 imm_expr
.X_op
= O_absent
;
7917 offset_expr
.X_op
= O_absent
;
7918 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7919 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7920 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7923 memset (&arg
, 0, sizeof (arg
));
7927 arg
.last_regno
= ILLEGAL_REG
;
7928 arg
.dest_regno
= ILLEGAL_REG
;
7930 for (args
= opcode
->args
;; ++args
)
7934 if (arg
.token
->type
== OT_END
)
7938 /* Handle unary instructions in which only one operand is given.
7939 The source is then the same as the destination. */
7940 if (arg
.opnum
== 1 && *args
== ',')
7942 operand
= decode_mips16_operand (args
[1], FALSE
);
7943 if (operand
&& mips_optional_operand_p (operand
))
7951 /* Fail the match if there were too few operands. */
7955 /* Successful match. Stuff the immediate value in now, if
7957 clear_insn_error ();
7958 if (opcode
->pinfo
== INSN_MACRO
)
7960 gas_assert (relax_char
== 0 || relax_char
== 'p');
7961 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7964 && offset_expr
.X_op
== O_constant
7965 && calculate_reloc (*offset_reloc
,
7966 offset_expr
.X_add_number
,
7969 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7970 forced_insn_length
, &insn
->insn_opcode
);
7971 offset_expr
.X_op
= O_absent
;
7972 *offset_reloc
= BFD_RELOC_UNUSED
;
7974 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7976 if (forced_insn_length
== 2)
7977 set_insn_error (0, _("invalid unextended operand value"));
7978 forced_insn_length
= 4;
7979 insn
->insn_opcode
|= MIPS16_EXTEND
;
7981 else if (relax_char
)
7982 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7984 check_completed_insn (&arg
);
7988 /* Fail the match if the line has too many operands. */
7992 /* Handle characters that need to match exactly. */
7993 if (*args
== '(' || *args
== ')' || *args
== ',')
7995 if (match_char (&arg
, *args
))
8013 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8015 imm_expr
.X_op
= O_constant
;
8017 normalize_constant_expr (&imm_expr
);
8022 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8023 insn
->insn_opcode
<<= 16;
8027 operand
= decode_mips16_operand (c
, FALSE
);
8031 /* '6' is a special case. It is used for BREAK and SDBBP,
8032 whose operands are only meaningful to the software that decodes
8033 them. This means that there is no architectural reason why
8034 they cannot be prefixed by EXTEND, but in practice,
8035 exception handlers will only look at the instruction
8036 itself. We therefore allow '6' to be extended when
8037 disassembling but not when assembling. */
8038 if (operand
->type
!= OP_PCREL
&& c
!= '6')
8040 ext_operand
= decode_mips16_operand (c
, TRUE
);
8041 if (operand
!= ext_operand
)
8043 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8045 offset_expr
.X_op
= O_constant
;
8046 offset_expr
.X_add_number
= 0;
8051 /* We need the OT_INTEGER check because some MIPS16
8052 immediate variants are listed before the register ones. */
8053 if (arg
.token
->type
!= OT_INTEGER
8054 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8057 /* '8' is used for SLTI(U) and has traditionally not
8058 been allowed to take relocation operators. */
8059 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8060 && (ext_operand
->size
!= 16 || c
== '8'))
8068 if (mips_optional_operand_p (operand
)
8070 && (arg
.token
[0].type
!= OT_REG
8071 || arg
.token
[1].type
== OT_END
))
8073 /* Assume that the register has been elided and is the
8074 same as the first operand. */
8079 if (!match_operand (&arg
, operand
))
8084 /* Record that the current instruction is invalid for the current ISA. */
8087 match_invalid_for_isa (void)
8090 (0, _("opcode not supported on this processor: %s (%s)"),
8091 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8092 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8095 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8096 Return true if a definite match or failure was found, storing any match
8097 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8098 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8099 tried and failed to match under normal conditions and now want to try a
8100 more relaxed match. */
8103 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8104 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8105 int opcode_extra
, bfd_boolean lax_match
)
8107 const struct mips_opcode
*opcode
;
8108 const struct mips_opcode
*invalid_delay_slot
;
8109 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8111 /* Search for a match, ignoring alternatives that don't satisfy the
8112 current ISA or forced_length. */
8113 invalid_delay_slot
= 0;
8114 seen_valid_for_isa
= FALSE
;
8115 seen_valid_for_size
= FALSE
;
8119 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8120 if (is_opcode_valid (opcode
))
8122 seen_valid_for_isa
= TRUE
;
8123 if (is_size_valid (opcode
))
8125 bfd_boolean delay_slot_ok
;
8127 seen_valid_for_size
= TRUE
;
8128 delay_slot_ok
= is_delay_slot_valid (opcode
);
8129 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8130 lax_match
, delay_slot_ok
))
8134 if (!invalid_delay_slot
)
8135 invalid_delay_slot
= opcode
;
8144 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8146 /* If the only matches we found had the wrong length for the delay slot,
8147 pick the first such match. We'll issue an appropriate warning later. */
8148 if (invalid_delay_slot
)
8150 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8156 /* Handle the case where we didn't try to match an instruction because
8157 all the alternatives were incompatible with the current ISA. */
8158 if (!seen_valid_for_isa
)
8160 match_invalid_for_isa ();
8164 /* Handle the case where we didn't try to match an instruction because
8165 all the alternatives were of the wrong size. */
8166 if (!seen_valid_for_size
)
8168 if (mips_opts
.insn32
)
8169 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8172 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8173 8 * forced_insn_length
);
8180 /* Like match_insns, but for MIPS16. */
8183 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8184 struct mips_operand_token
*tokens
)
8186 const struct mips_opcode
*opcode
;
8187 bfd_boolean seen_valid_for_isa
;
8189 /* Search for a match, ignoring alternatives that don't satisfy the
8190 current ISA. There are no separate entries for extended forms so
8191 we deal with forced_length later. */
8192 seen_valid_for_isa
= FALSE
;
8196 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8197 if (is_opcode_valid_16 (opcode
))
8199 seen_valid_for_isa
= TRUE
;
8200 if (match_mips16_insn (insn
, opcode
, tokens
))
8205 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8206 && strcmp (opcode
->name
, first
->name
) == 0);
8208 /* Handle the case where we didn't try to match an instruction because
8209 all the alternatives were incompatible with the current ISA. */
8210 if (!seen_valid_for_isa
)
8212 match_invalid_for_isa ();
8219 /* Set up global variables for the start of a new macro. */
8224 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8225 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8226 sizeof (mips_macro_warning
.first_insn_sizes
));
8227 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8228 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8229 && delayed_branch_p (&history
[0]));
8230 switch (history
[0].insn_mo
->pinfo2
8231 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8233 case INSN2_BRANCH_DELAY_32BIT
:
8234 mips_macro_warning
.delay_slot_length
= 4;
8236 case INSN2_BRANCH_DELAY_16BIT
:
8237 mips_macro_warning
.delay_slot_length
= 2;
8240 mips_macro_warning
.delay_slot_length
= 0;
8243 mips_macro_warning
.first_frag
= NULL
;
8246 /* Given that a macro is longer than one instruction or of the wrong size,
8247 return the appropriate warning for it. Return null if no warning is
8248 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8249 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8250 and RELAX_NOMACRO. */
8253 macro_warning (relax_substateT subtype
)
8255 if (subtype
& RELAX_DELAY_SLOT
)
8256 return _("macro instruction expanded into multiple instructions"
8257 " in a branch delay slot");
8258 else if (subtype
& RELAX_NOMACRO
)
8259 return _("macro instruction expanded into multiple instructions");
8260 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8261 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8262 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8263 ? _("macro instruction expanded into a wrong size instruction"
8264 " in a 16-bit branch delay slot")
8265 : _("macro instruction expanded into a wrong size instruction"
8266 " in a 32-bit branch delay slot"));
8271 /* Finish up a macro. Emit warnings as appropriate. */
8276 /* Relaxation warning flags. */
8277 relax_substateT subtype
= 0;
8279 /* Check delay slot size requirements. */
8280 if (mips_macro_warning
.delay_slot_length
== 2)
8281 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8282 if (mips_macro_warning
.delay_slot_length
!= 0)
8284 if (mips_macro_warning
.delay_slot_length
8285 != mips_macro_warning
.first_insn_sizes
[0])
8286 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8287 if (mips_macro_warning
.delay_slot_length
8288 != mips_macro_warning
.first_insn_sizes
[1])
8289 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8292 /* Check instruction count requirements. */
8293 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8295 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8296 subtype
|= RELAX_SECOND_LONGER
;
8297 if (mips_opts
.warn_about_macros
)
8298 subtype
|= RELAX_NOMACRO
;
8299 if (mips_macro_warning
.delay_slot_p
)
8300 subtype
|= RELAX_DELAY_SLOT
;
8303 /* If both alternatives fail to fill a delay slot correctly,
8304 emit the warning now. */
8305 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8306 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8311 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8312 | RELAX_DELAY_SLOT_SIZE_FIRST
8313 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8314 msg
= macro_warning (s
);
8316 as_warn ("%s", msg
);
8320 /* If both implementations are longer than 1 instruction, then emit the
8322 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8327 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8328 msg
= macro_warning (s
);
8330 as_warn ("%s", msg
);
8334 /* If any flags still set, then one implementation might need a warning
8335 and the other either will need one of a different kind or none at all.
8336 Pass any remaining flags over to relaxation. */
8337 if (mips_macro_warning
.first_frag
!= NULL
)
8338 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8341 /* Instruction operand formats used in macros that vary between
8342 standard MIPS and microMIPS code. */
8344 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8345 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8346 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8347 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8348 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8349 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8350 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8351 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8353 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8354 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8355 : cop12_fmt[mips_opts.micromips])
8356 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8357 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8358 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8359 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8360 : mem12_fmt[mips_opts.micromips])
8361 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8362 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8363 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8365 /* Read a macro's relocation codes from *ARGS and store them in *R.
8366 The first argument in *ARGS will be either the code for a single
8367 relocation or -1 followed by the three codes that make up a
8368 composite relocation. */
8371 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8375 next
= va_arg (*args
, int);
8377 r
[0] = (bfd_reloc_code_real_type
) next
;
8380 for (i
= 0; i
< 3; i
++)
8381 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8382 /* This function is only used for 16-bit relocation fields.
8383 To make the macro code simpler, treat an unrelocated value
8384 in the same way as BFD_RELOC_LO16. */
8385 if (r
[0] == BFD_RELOC_UNUSED
)
8386 r
[0] = BFD_RELOC_LO16
;
8390 /* Build an instruction created by a macro expansion. This is passed
8391 a pointer to the count of instructions created so far, an
8392 expression, the name of the instruction to build, an operand format
8393 string, and corresponding arguments. */
8396 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8398 const struct mips_opcode
*mo
= NULL
;
8399 bfd_reloc_code_real_type r
[3];
8400 const struct mips_opcode
*amo
;
8401 const struct mips_operand
*operand
;
8402 struct hash_control
*hash
;
8403 struct mips_cl_insn insn
;
8407 va_start (args
, fmt
);
8409 if (mips_opts
.mips16
)
8411 mips16_macro_build (ep
, name
, fmt
, &args
);
8416 r
[0] = BFD_RELOC_UNUSED
;
8417 r
[1] = BFD_RELOC_UNUSED
;
8418 r
[2] = BFD_RELOC_UNUSED
;
8419 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8420 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8422 gas_assert (strcmp (name
, amo
->name
) == 0);
8426 /* Search until we get a match for NAME. It is assumed here that
8427 macros will never generate MDMX, MIPS-3D, or MT instructions.
8428 We try to match an instruction that fulfils the branch delay
8429 slot instruction length requirement (if any) of the previous
8430 instruction. While doing this we record the first instruction
8431 seen that matches all the other conditions and use it anyway
8432 if the requirement cannot be met; we will issue an appropriate
8433 warning later on. */
8434 if (strcmp (fmt
, amo
->args
) == 0
8435 && amo
->pinfo
!= INSN_MACRO
8436 && is_opcode_valid (amo
)
8437 && is_size_valid (amo
))
8439 if (is_delay_slot_valid (amo
))
8449 gas_assert (amo
->name
);
8451 while (strcmp (name
, amo
->name
) == 0);
8454 create_insn (&insn
, mo
);
8467 macro_read_relocs (&args
, r
);
8468 gas_assert (*r
== BFD_RELOC_GPREL16
8469 || *r
== BFD_RELOC_MIPS_HIGHER
8470 || *r
== BFD_RELOC_HI16_S
8471 || *r
== BFD_RELOC_LO16
8472 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8476 macro_read_relocs (&args
, r
);
8480 macro_read_relocs (&args
, r
);
8481 gas_assert (ep
!= NULL
8482 && (ep
->X_op
== O_constant
8483 || (ep
->X_op
== O_symbol
8484 && (*r
== BFD_RELOC_MIPS_HIGHEST
8485 || *r
== BFD_RELOC_HI16_S
8486 || *r
== BFD_RELOC_HI16
8487 || *r
== BFD_RELOC_GPREL16
8488 || *r
== BFD_RELOC_MIPS_GOT_HI16
8489 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8493 gas_assert (ep
!= NULL
);
8496 * This allows macro() to pass an immediate expression for
8497 * creating short branches without creating a symbol.
8499 * We don't allow branch relaxation for these branches, as
8500 * they should only appear in ".set nomacro" anyway.
8502 if (ep
->X_op
== O_constant
)
8504 /* For microMIPS we always use relocations for branches.
8505 So we should not resolve immediate values. */
8506 gas_assert (!mips_opts
.micromips
);
8508 if ((ep
->X_add_number
& 3) != 0)
8509 as_bad (_("branch to misaligned address (0x%lx)"),
8510 (unsigned long) ep
->X_add_number
);
8511 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8512 as_bad (_("branch address range overflow (0x%lx)"),
8513 (unsigned long) ep
->X_add_number
);
8514 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8518 *r
= BFD_RELOC_16_PCREL_S2
;
8522 gas_assert (ep
!= NULL
);
8523 *r
= BFD_RELOC_MIPS_JMP
;
8527 operand
= (mips_opts
.micromips
8528 ? decode_micromips_operand (fmt
)
8529 : decode_mips_operand (fmt
));
8533 uval
= va_arg (args
, int);
8534 if (operand
->type
== OP_CLO_CLZ_DEST
)
8535 uval
|= (uval
<< 5);
8536 insn_insert_operand (&insn
, operand
, uval
);
8538 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8544 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8546 append_insn (&insn
, ep
, r
, TRUE
);
8550 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8553 struct mips_opcode
*mo
;
8554 struct mips_cl_insn insn
;
8555 const struct mips_operand
*operand
;
8556 bfd_reloc_code_real_type r
[3]
8557 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8559 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8561 gas_assert (strcmp (name
, mo
->name
) == 0);
8563 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8566 gas_assert (mo
->name
);
8567 gas_assert (strcmp (name
, mo
->name
) == 0);
8570 create_insn (&insn
, mo
);
8608 gas_assert (ep
!= NULL
);
8610 if (ep
->X_op
!= O_constant
)
8611 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8612 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8614 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8616 *r
= BFD_RELOC_UNUSED
;
8622 operand
= decode_mips16_operand (c
, FALSE
);
8626 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8631 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8633 append_insn (&insn
, ep
, r
, TRUE
);
8637 * Generate a "jalr" instruction with a relocation hint to the called
8638 * function. This occurs in NewABI PIC code.
8641 macro_build_jalr (expressionS
*ep
, int cprestore
)
8643 static const bfd_reloc_code_real_type jalr_relocs
[2]
8644 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8645 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8649 if (MIPS_JALR_HINT_P (ep
))
8654 if (mips_opts
.micromips
)
8656 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8657 ? "jalr" : "jalrs");
8658 if (MIPS_JALR_HINT_P (ep
)
8660 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8661 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8663 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8666 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8667 if (MIPS_JALR_HINT_P (ep
))
8668 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8672 * Generate a "lui" instruction.
8675 macro_build_lui (expressionS
*ep
, int regnum
)
8677 gas_assert (! mips_opts
.mips16
);
8679 if (ep
->X_op
!= O_constant
)
8681 gas_assert (ep
->X_op
== O_symbol
);
8682 /* _gp_disp is a special case, used from s_cpload.
8683 __gnu_local_gp is used if mips_no_shared. */
8684 gas_assert (mips_pic
== NO_PIC
8686 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8687 || (! mips_in_shared
8688 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8689 "__gnu_local_gp") == 0));
8692 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8695 /* Generate a sequence of instructions to do a load or store from a constant
8696 offset off of a base register (breg) into/from a target register (treg),
8697 using AT if necessary. */
8699 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8700 int treg
, int breg
, int dbl
)
8702 gas_assert (ep
->X_op
== O_constant
);
8704 /* Sign-extending 32-bit constants makes their handling easier. */
8706 normalize_constant_expr (ep
);
8708 /* Right now, this routine can only handle signed 32-bit constants. */
8709 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8710 as_warn (_("operand overflow"));
8712 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8714 /* Signed 16-bit offset will fit in the op. Easy! */
8715 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8719 /* 32-bit offset, need multiple instructions and AT, like:
8720 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8721 addu $tempreg,$tempreg,$breg
8722 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8723 to handle the complete offset. */
8724 macro_build_lui (ep
, AT
);
8725 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8726 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8729 as_bad (_("macro used $at after \".set noat\""));
8734 * Generates code to set the $at register to true (one)
8735 * if reg is less than the immediate expression.
8738 set_at (int reg
, int unsignedp
)
8740 if (imm_expr
.X_add_number
>= -0x8000
8741 && imm_expr
.X_add_number
< 0x8000)
8742 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8743 AT
, reg
, BFD_RELOC_LO16
);
8746 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8747 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8751 /* Count the leading zeroes by performing a binary chop. This is a
8752 bulky bit of source, but performance is a LOT better for the
8753 majority of values than a simple loop to count the bits:
8754 for (lcnt = 0; (lcnt < 32); lcnt++)
8755 if ((v) & (1 << (31 - lcnt)))
8757 However it is not code size friendly, and the gain will drop a bit
8758 on certain cached systems.
8760 #define COUNT_TOP_ZEROES(v) \
8761 (((v) & ~0xffff) == 0 \
8762 ? ((v) & ~0xff) == 0 \
8763 ? ((v) & ~0xf) == 0 \
8764 ? ((v) & ~0x3) == 0 \
8765 ? ((v) & ~0x1) == 0 \
8770 : ((v) & ~0x7) == 0 \
8773 : ((v) & ~0x3f) == 0 \
8774 ? ((v) & ~0x1f) == 0 \
8777 : ((v) & ~0x7f) == 0 \
8780 : ((v) & ~0xfff) == 0 \
8781 ? ((v) & ~0x3ff) == 0 \
8782 ? ((v) & ~0x1ff) == 0 \
8785 : ((v) & ~0x7ff) == 0 \
8788 : ((v) & ~0x3fff) == 0 \
8789 ? ((v) & ~0x1fff) == 0 \
8792 : ((v) & ~0x7fff) == 0 \
8795 : ((v) & ~0xffffff) == 0 \
8796 ? ((v) & ~0xfffff) == 0 \
8797 ? ((v) & ~0x3ffff) == 0 \
8798 ? ((v) & ~0x1ffff) == 0 \
8801 : ((v) & ~0x7ffff) == 0 \
8804 : ((v) & ~0x3fffff) == 0 \
8805 ? ((v) & ~0x1fffff) == 0 \
8808 : ((v) & ~0x7fffff) == 0 \
8811 : ((v) & ~0xfffffff) == 0 \
8812 ? ((v) & ~0x3ffffff) == 0 \
8813 ? ((v) & ~0x1ffffff) == 0 \
8816 : ((v) & ~0x7ffffff) == 0 \
8819 : ((v) & ~0x3fffffff) == 0 \
8820 ? ((v) & ~0x1fffffff) == 0 \
8823 : ((v) & ~0x7fffffff) == 0 \
8828 * This routine generates the least number of instructions necessary to load
8829 * an absolute expression value into a register.
8832 load_register (int reg
, expressionS
*ep
, int dbl
)
8835 expressionS hi32
, lo32
;
8837 if (ep
->X_op
!= O_big
)
8839 gas_assert (ep
->X_op
== O_constant
);
8841 /* Sign-extending 32-bit constants makes their handling easier. */
8843 normalize_constant_expr (ep
);
8845 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8847 /* We can handle 16 bit signed values with an addiu to
8848 $zero. No need to ever use daddiu here, since $zero and
8849 the result are always correct in 32 bit mode. */
8850 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8853 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8855 /* We can handle 16 bit unsigned values with an ori to
8857 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8860 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8862 /* 32 bit values require an lui. */
8863 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8864 if ((ep
->X_add_number
& 0xffff) != 0)
8865 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8870 /* The value is larger than 32 bits. */
8872 if (!dbl
|| GPR_SIZE
== 32)
8876 sprintf_vma (value
, ep
->X_add_number
);
8877 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8878 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8882 if (ep
->X_op
!= O_big
)
8885 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8886 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8887 hi32
.X_add_number
&= 0xffffffff;
8889 lo32
.X_add_number
&= 0xffffffff;
8893 gas_assert (ep
->X_add_number
> 2);
8894 if (ep
->X_add_number
== 3)
8895 generic_bignum
[3] = 0;
8896 else if (ep
->X_add_number
> 4)
8897 as_bad (_("number larger than 64 bits"));
8898 lo32
.X_op
= O_constant
;
8899 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8900 hi32
.X_op
= O_constant
;
8901 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8904 if (hi32
.X_add_number
== 0)
8909 unsigned long hi
, lo
;
8911 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8913 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8915 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8918 if (lo32
.X_add_number
& 0x80000000)
8920 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8921 if (lo32
.X_add_number
& 0xffff)
8922 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8927 /* Check for 16bit shifted constant. We know that hi32 is
8928 non-zero, so start the mask on the first bit of the hi32
8933 unsigned long himask
, lomask
;
8937 himask
= 0xffff >> (32 - shift
);
8938 lomask
= (0xffff << shift
) & 0xffffffff;
8942 himask
= 0xffff << (shift
- 32);
8945 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8946 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8950 tmp
.X_op
= O_constant
;
8952 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8953 | (lo32
.X_add_number
>> shift
));
8955 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8956 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8957 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8958 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8963 while (shift
<= (64 - 16));
8965 /* Find the bit number of the lowest one bit, and store the
8966 shifted value in hi/lo. */
8967 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8968 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8972 while ((lo
& 1) == 0)
8977 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8983 while ((hi
& 1) == 0)
8992 /* Optimize if the shifted value is a (power of 2) - 1. */
8993 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8994 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8996 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9001 /* This instruction will set the register to be all
9003 tmp
.X_op
= O_constant
;
9004 tmp
.X_add_number
= (offsetT
) -1;
9005 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9009 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9010 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9012 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9013 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9018 /* Sign extend hi32 before calling load_register, because we can
9019 generally get better code when we load a sign extended value. */
9020 if ((hi32
.X_add_number
& 0x80000000) != 0)
9021 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9022 load_register (reg
, &hi32
, 0);
9025 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9029 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9037 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9039 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9040 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9046 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9050 mid16
.X_add_number
>>= 16;
9051 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9052 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9055 if ((lo32
.X_add_number
& 0xffff) != 0)
9056 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9060 load_delay_nop (void)
9062 if (!gpr_interlocks
)
9063 macro_build (NULL
, "nop", "");
9066 /* Load an address into a register. */
9069 load_address (int reg
, expressionS
*ep
, int *used_at
)
9071 if (ep
->X_op
!= O_constant
9072 && ep
->X_op
!= O_symbol
)
9074 as_bad (_("expression too complex"));
9075 ep
->X_op
= O_constant
;
9078 if (ep
->X_op
== O_constant
)
9080 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9084 if (mips_pic
== NO_PIC
)
9086 /* If this is a reference to a GP relative symbol, we want
9087 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9089 lui $reg,<sym> (BFD_RELOC_HI16_S)
9090 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9091 If we have an addend, we always use the latter form.
9093 With 64bit address space and a usable $at we want
9094 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9095 lui $at,<sym> (BFD_RELOC_HI16_S)
9096 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9097 daddiu $at,<sym> (BFD_RELOC_LO16)
9101 If $at is already in use, we use a path which is suboptimal
9102 on superscalar processors.
9103 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9104 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9106 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9108 daddiu $reg,<sym> (BFD_RELOC_LO16)
9110 For GP relative symbols in 64bit address space we can use
9111 the same sequence as in 32bit address space. */
9112 if (HAVE_64BIT_SYMBOLS
)
9114 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9115 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9117 relax_start (ep
->X_add_symbol
);
9118 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9119 mips_gp_register
, BFD_RELOC_GPREL16
);
9123 if (*used_at
== 0 && mips_opts
.at
)
9125 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9126 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9127 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9128 BFD_RELOC_MIPS_HIGHER
);
9129 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9130 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9131 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9136 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9137 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9138 BFD_RELOC_MIPS_HIGHER
);
9139 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9140 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9141 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9142 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9145 if (mips_relax
.sequence
)
9150 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9151 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9153 relax_start (ep
->X_add_symbol
);
9154 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9155 mips_gp_register
, BFD_RELOC_GPREL16
);
9158 macro_build_lui (ep
, reg
);
9159 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9160 reg
, reg
, BFD_RELOC_LO16
);
9161 if (mips_relax
.sequence
)
9165 else if (!mips_big_got
)
9169 /* If this is a reference to an external symbol, we want
9170 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9172 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9174 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9175 If there is a constant, it must be added in after.
9177 If we have NewABI, we want
9178 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9179 unless we're referencing a global symbol with a non-zero
9180 offset, in which case cst must be added separately. */
9183 if (ep
->X_add_number
)
9185 ex
.X_add_number
= ep
->X_add_number
;
9186 ep
->X_add_number
= 0;
9187 relax_start (ep
->X_add_symbol
);
9188 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9189 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9190 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9191 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9192 ex
.X_op
= O_constant
;
9193 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9194 reg
, reg
, BFD_RELOC_LO16
);
9195 ep
->X_add_number
= ex
.X_add_number
;
9198 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9199 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9200 if (mips_relax
.sequence
)
9205 ex
.X_add_number
= ep
->X_add_number
;
9206 ep
->X_add_number
= 0;
9207 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9208 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9210 relax_start (ep
->X_add_symbol
);
9212 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9216 if (ex
.X_add_number
!= 0)
9218 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9219 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9220 ex
.X_op
= O_constant
;
9221 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9222 reg
, reg
, BFD_RELOC_LO16
);
9226 else if (mips_big_got
)
9230 /* This is the large GOT case. If this is a reference to an
9231 external symbol, we want
9232 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9234 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9236 Otherwise, for a reference to a local symbol in old ABI, we want
9237 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9239 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9240 If there is a constant, it must be added in after.
9242 In the NewABI, for local symbols, with or without offsets, we want:
9243 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9244 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9248 ex
.X_add_number
= ep
->X_add_number
;
9249 ep
->X_add_number
= 0;
9250 relax_start (ep
->X_add_symbol
);
9251 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9252 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9253 reg
, reg
, mips_gp_register
);
9254 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9255 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9256 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9257 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9258 else if (ex
.X_add_number
)
9260 ex
.X_op
= O_constant
;
9261 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9265 ep
->X_add_number
= ex
.X_add_number
;
9267 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9268 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9269 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9270 BFD_RELOC_MIPS_GOT_OFST
);
9275 ex
.X_add_number
= ep
->X_add_number
;
9276 ep
->X_add_number
= 0;
9277 relax_start (ep
->X_add_symbol
);
9278 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9280 reg
, reg
, mips_gp_register
);
9281 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9282 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9284 if (reg_needs_delay (mips_gp_register
))
9286 /* We need a nop before loading from $gp. This special
9287 check is required because the lui which starts the main
9288 instruction stream does not refer to $gp, and so will not
9289 insert the nop which may be required. */
9290 macro_build (NULL
, "nop", "");
9292 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9293 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9295 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9299 if (ex
.X_add_number
!= 0)
9301 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9302 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9303 ex
.X_op
= O_constant
;
9304 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9312 if (!mips_opts
.at
&& *used_at
== 1)
9313 as_bad (_("macro used $at after \".set noat\""));
9316 /* Move the contents of register SOURCE into register DEST. */
9319 move_register (int dest
, int source
)
9321 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9322 instruction specifically requires a 32-bit one. */
9323 if (mips_opts
.micromips
9324 && !mips_opts
.insn32
9325 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9326 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9328 macro_build (NULL
, GPR_SIZE
== 32 ? "addu" : "daddu", "d,v,t",
9332 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9333 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9334 The two alternatives are:
9336 Global symbol Local sybmol
9337 ------------- ------------
9338 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9340 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9342 load_got_offset emits the first instruction and add_got_offset
9343 emits the second for a 16-bit offset or add_got_offset_hilo emits
9344 a sequence to add a 32-bit offset using a scratch register. */
9347 load_got_offset (int dest
, expressionS
*local
)
9352 global
.X_add_number
= 0;
9354 relax_start (local
->X_add_symbol
);
9355 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9356 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9358 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9359 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9364 add_got_offset (int dest
, expressionS
*local
)
9368 global
.X_op
= O_constant
;
9369 global
.X_op_symbol
= NULL
;
9370 global
.X_add_symbol
= NULL
;
9371 global
.X_add_number
= local
->X_add_number
;
9373 relax_start (local
->X_add_symbol
);
9374 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9375 dest
, dest
, BFD_RELOC_LO16
);
9377 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9382 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9385 int hold_mips_optimize
;
9387 global
.X_op
= O_constant
;
9388 global
.X_op_symbol
= NULL
;
9389 global
.X_add_symbol
= NULL
;
9390 global
.X_add_number
= local
->X_add_number
;
9392 relax_start (local
->X_add_symbol
);
9393 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9395 /* Set mips_optimize around the lui instruction to avoid
9396 inserting an unnecessary nop after the lw. */
9397 hold_mips_optimize
= mips_optimize
;
9399 macro_build_lui (&global
, tmp
);
9400 mips_optimize
= hold_mips_optimize
;
9401 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9404 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9407 /* Emit a sequence of instructions to emulate a branch likely operation.
9408 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9409 is its complementing branch with the original condition negated.
9410 CALL is set if the original branch specified the link operation.
9411 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9413 Code like this is produced in the noreorder mode:
9418 delay slot (executed only if branch taken)
9426 delay slot (executed only if branch taken)
9429 In the reorder mode the delay slot would be filled with a nop anyway,
9430 so code produced is simply:
9435 This function is used when producing code for the microMIPS ASE that
9436 does not implement branch likely instructions in hardware. */
9439 macro_build_branch_likely (const char *br
, const char *brneg
,
9440 int call
, expressionS
*ep
, const char *fmt
,
9441 unsigned int sreg
, unsigned int treg
)
9443 int noreorder
= mips_opts
.noreorder
;
9446 gas_assert (mips_opts
.micromips
);
9450 micromips_label_expr (&expr1
);
9451 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9452 macro_build (NULL
, "nop", "");
9453 macro_build (ep
, call
? "bal" : "b", "p");
9455 /* Set to true so that append_insn adds a label. */
9456 emit_branch_likely_macro
= TRUE
;
9460 macro_build (ep
, br
, fmt
, sreg
, treg
);
9461 macro_build (NULL
, "nop", "");
9466 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9467 the condition code tested. EP specifies the branch target. */
9470 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9497 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9500 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9501 the register tested. EP specifies the branch target. */
9504 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9506 const char *brneg
= NULL
;
9516 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9520 gas_assert (mips_opts
.micromips
);
9521 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9529 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9536 br
= mips_opts
.micromips
? "blez" : "blezl";
9543 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9547 gas_assert (mips_opts
.micromips
);
9548 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9555 if (mips_opts
.micromips
&& brneg
)
9556 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9558 macro_build (ep
, br
, "s,p", sreg
);
9561 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9562 TREG as the registers tested. EP specifies the branch target. */
9565 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9566 unsigned int sreg
, unsigned int treg
)
9568 const char *brneg
= NULL
;
9580 br
= mips_opts
.micromips
? "beq" : "beql";
9589 br
= mips_opts
.micromips
? "bne" : "bnel";
9595 if (mips_opts
.micromips
&& brneg
)
9596 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9598 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9601 /* Return the high part that should be loaded in order to make the low
9602 part of VALUE accessible using an offset of OFFBITS bits. */
9605 offset_high_part (offsetT value
, unsigned int offbits
)
9612 bias
= 1 << (offbits
- 1);
9613 low_mask
= bias
* 2 - 1;
9614 return (value
+ bias
) & ~low_mask
;
9617 /* Return true if the value stored in offset_expr and offset_reloc
9618 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9619 amount that the caller wants to add without inducing overflow
9620 and ALIGN is the known alignment of the value in bytes. */
9623 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9627 /* Accept any relocation operator if overflow isn't a concern. */
9628 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9631 /* These relocations are guaranteed not to overflow in correct links. */
9632 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9633 || gprel16_reloc_p (*offset_reloc
))
9636 if (offset_expr
.X_op
== O_constant
9637 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9638 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9645 * This routine implements the seemingly endless macro or synthesized
9646 * instructions and addressing modes in the mips assembly language. Many
9647 * of these macros are simple and are similar to each other. These could
9648 * probably be handled by some kind of table or grammar approach instead of
9649 * this verbose method. Others are not simple macros but are more like
9650 * optimizing code generation.
9651 * One interesting optimization is when several store macros appear
9652 * consecutively that would load AT with the upper half of the same address.
9653 * The ensuing load upper instructions are ommited. This implies some kind
9654 * of global optimization. We currently only optimize within a single macro.
9655 * For many of the load and store macros if the address is specified as a
9656 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9657 * first load register 'at' with zero and use it as the base register. The
9658 * mips assembler simply uses register $zero. Just one tiny optimization
9662 macro (struct mips_cl_insn
*ip
, char *str
)
9664 const struct mips_operand_array
*operands
;
9665 unsigned int breg
, i
;
9666 unsigned int tempreg
;
9669 expressionS label_expr
;
9684 bfd_boolean large_offset
;
9686 int hold_mips_optimize
;
9688 unsigned int op
[MAX_OPERANDS
];
9690 gas_assert (! mips_opts
.mips16
);
9692 operands
= insn_operands (ip
);
9693 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9694 if (operands
->operand
[i
])
9695 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9699 mask
= ip
->insn_mo
->mask
;
9701 label_expr
.X_op
= O_constant
;
9702 label_expr
.X_op_symbol
= NULL
;
9703 label_expr
.X_add_symbol
= NULL
;
9704 label_expr
.X_add_number
= 0;
9706 expr1
.X_op
= O_constant
;
9707 expr1
.X_op_symbol
= NULL
;
9708 expr1
.X_add_symbol
= NULL
;
9709 expr1
.X_add_number
= 1;
9725 if (mips_opts
.micromips
)
9726 micromips_label_expr (&label_expr
);
9728 label_expr
.X_add_number
= 8;
9729 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9731 macro_build (NULL
, "nop", "");
9733 move_register (op
[0], op
[1]);
9734 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9735 if (mips_opts
.micromips
)
9736 micromips_add_label ();
9753 if (!mips_opts
.micromips
)
9755 if (imm_expr
.X_add_number
>= -0x200
9756 && imm_expr
.X_add_number
< 0x200)
9758 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9759 (int) imm_expr
.X_add_number
);
9768 if (imm_expr
.X_add_number
>= -0x8000
9769 && imm_expr
.X_add_number
< 0x8000)
9771 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9776 load_register (AT
, &imm_expr
, dbl
);
9777 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9796 if (imm_expr
.X_add_number
>= 0
9797 && imm_expr
.X_add_number
< 0x10000)
9799 if (mask
!= M_NOR_I
)
9800 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9803 macro_build (&imm_expr
, "ori", "t,r,i",
9804 op
[0], op
[1], BFD_RELOC_LO16
);
9805 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9811 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9812 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9816 switch (imm_expr
.X_add_number
)
9819 macro_build (NULL
, "nop", "");
9822 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9826 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9827 (int) imm_expr
.X_add_number
);
9830 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9831 (unsigned long) imm_expr
.X_add_number
);
9840 gas_assert (mips_opts
.micromips
);
9841 macro_build_branch_ccl (mask
, &offset_expr
,
9842 EXTRACT_OPERAND (1, BCC
, *ip
));
9849 if (imm_expr
.X_add_number
== 0)
9855 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
9860 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9867 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9868 else if (op
[0] == 0)
9869 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9873 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9874 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9875 &offset_expr
, AT
, ZERO
);
9885 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9891 /* Check for > max integer. */
9892 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9895 /* Result is always false. */
9897 macro_build (NULL
, "nop", "");
9899 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9902 ++imm_expr
.X_add_number
;
9906 if (mask
== M_BGEL_I
)
9908 if (imm_expr
.X_add_number
== 0)
9910 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9911 &offset_expr
, op
[0]);
9914 if (imm_expr
.X_add_number
== 1)
9916 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9917 &offset_expr
, op
[0]);
9920 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9923 /* result is always true */
9924 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9925 macro_build (&offset_expr
, "b", "p");
9930 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9931 &offset_expr
, AT
, ZERO
);
9939 else if (op
[0] == 0)
9940 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9941 &offset_expr
, ZERO
, op
[1]);
9945 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9946 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9947 &offset_expr
, AT
, ZERO
);
9956 && imm_expr
.X_add_number
== -1))
9958 ++imm_expr
.X_add_number
;
9962 if (mask
== M_BGEUL_I
)
9964 if (imm_expr
.X_add_number
== 0)
9966 else if (imm_expr
.X_add_number
== 1)
9967 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9968 &offset_expr
, op
[0], ZERO
);
9973 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9974 &offset_expr
, AT
, ZERO
);
9982 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9983 else if (op
[0] == 0)
9984 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9988 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9989 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9990 &offset_expr
, AT
, ZERO
);
9998 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9999 &offset_expr
, op
[0], ZERO
);
10000 else if (op
[0] == 0)
10005 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10006 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10007 &offset_expr
, AT
, ZERO
);
10015 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10016 else if (op
[0] == 0)
10017 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10021 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10022 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10023 &offset_expr
, AT
, ZERO
);
10030 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10032 ++imm_expr
.X_add_number
;
10036 if (mask
== M_BLTL_I
)
10038 if (imm_expr
.X_add_number
== 0)
10039 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10040 else if (imm_expr
.X_add_number
== 1)
10041 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10046 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10047 &offset_expr
, AT
, ZERO
);
10055 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10056 &offset_expr
, op
[0], ZERO
);
10057 else if (op
[0] == 0)
10062 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10063 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10064 &offset_expr
, AT
, ZERO
);
10073 && imm_expr
.X_add_number
== -1))
10075 ++imm_expr
.X_add_number
;
10079 if (mask
== M_BLTUL_I
)
10081 if (imm_expr
.X_add_number
== 0)
10083 else if (imm_expr
.X_add_number
== 1)
10084 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10085 &offset_expr
, op
[0], ZERO
);
10090 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10091 &offset_expr
, AT
, ZERO
);
10099 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10100 else if (op
[0] == 0)
10101 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10105 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10106 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10107 &offset_expr
, AT
, ZERO
);
10116 else if (op
[0] == 0)
10117 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10118 &offset_expr
, ZERO
, op
[1]);
10122 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10123 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10124 &offset_expr
, AT
, ZERO
);
10140 as_warn (_("divide by zero"));
10142 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10144 macro_build (NULL
, "break", BRK_FMT
, 7);
10148 start_noreorder ();
10151 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10152 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10156 if (mips_opts
.micromips
)
10157 micromips_label_expr (&label_expr
);
10159 label_expr
.X_add_number
= 8;
10160 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10161 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10162 macro_build (NULL
, "break", BRK_FMT
, 7);
10163 if (mips_opts
.micromips
)
10164 micromips_add_label ();
10166 expr1
.X_add_number
= -1;
10168 load_register (AT
, &expr1
, dbl
);
10169 if (mips_opts
.micromips
)
10170 micromips_label_expr (&label_expr
);
10172 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10173 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10176 expr1
.X_add_number
= 1;
10177 load_register (AT
, &expr1
, dbl
);
10178 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10182 expr1
.X_add_number
= 0x80000000;
10183 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10187 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10188 /* We want to close the noreorder block as soon as possible, so
10189 that later insns are available for delay slot filling. */
10194 if (mips_opts
.micromips
)
10195 micromips_label_expr (&label_expr
);
10197 label_expr
.X_add_number
= 8;
10198 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10199 macro_build (NULL
, "nop", "");
10201 /* We want to close the noreorder block as soon as possible, so
10202 that later insns are available for delay slot filling. */
10205 macro_build (NULL
, "break", BRK_FMT
, 6);
10207 if (mips_opts
.micromips
)
10208 micromips_add_label ();
10209 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10248 if (imm_expr
.X_add_number
== 0)
10250 as_warn (_("divide by zero"));
10252 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10254 macro_build (NULL
, "break", BRK_FMT
, 7);
10257 if (imm_expr
.X_add_number
== 1)
10259 if (strcmp (s2
, "mflo") == 0)
10260 move_register (op
[0], op
[1]);
10262 move_register (op
[0], ZERO
);
10265 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10267 if (strcmp (s2
, "mflo") == 0)
10268 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10270 move_register (op
[0], ZERO
);
10275 load_register (AT
, &imm_expr
, dbl
);
10276 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10277 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10296 start_noreorder ();
10299 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10300 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10301 /* We want to close the noreorder block as soon as possible, so
10302 that later insns are available for delay slot filling. */
10307 if (mips_opts
.micromips
)
10308 micromips_label_expr (&label_expr
);
10310 label_expr
.X_add_number
= 8;
10311 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10312 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10314 /* We want to close the noreorder block as soon as possible, so
10315 that later insns are available for delay slot filling. */
10317 macro_build (NULL
, "break", BRK_FMT
, 7);
10318 if (mips_opts
.micromips
)
10319 micromips_add_label ();
10321 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10333 /* Load the address of a symbol into a register. If breg is not
10334 zero, we then add a base register to it. */
10337 if (dbl
&& GPR_SIZE
== 32)
10338 as_warn (_("dla used to load 32-bit register; recommend using la "
10341 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10342 as_warn (_("la used to load 64-bit address; recommend using dla "
10345 if (small_offset_p (0, align
, 16))
10347 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10348 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10352 if (mips_opts
.at
&& (op
[0] == breg
))
10360 if (offset_expr
.X_op
!= O_symbol
10361 && offset_expr
.X_op
!= O_constant
)
10363 as_bad (_("expression too complex"));
10364 offset_expr
.X_op
= O_constant
;
10367 if (offset_expr
.X_op
== O_constant
)
10368 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10369 else if (mips_pic
== NO_PIC
)
10371 /* If this is a reference to a GP relative symbol, we want
10372 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10374 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10375 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10376 If we have a constant, we need two instructions anyhow,
10377 so we may as well always use the latter form.
10379 With 64bit address space and a usable $at we want
10380 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10381 lui $at,<sym> (BFD_RELOC_HI16_S)
10382 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10383 daddiu $at,<sym> (BFD_RELOC_LO16)
10385 daddu $tempreg,$tempreg,$at
10387 If $at is already in use, we use a path which is suboptimal
10388 on superscalar processors.
10389 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10390 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10392 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10394 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10396 For GP relative symbols in 64bit address space we can use
10397 the same sequence as in 32bit address space. */
10398 if (HAVE_64BIT_SYMBOLS
)
10400 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10401 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10403 relax_start (offset_expr
.X_add_symbol
);
10404 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10405 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10409 if (used_at
== 0 && mips_opts
.at
)
10411 macro_build (&offset_expr
, "lui", LUI_FMT
,
10412 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10413 macro_build (&offset_expr
, "lui", LUI_FMT
,
10414 AT
, BFD_RELOC_HI16_S
);
10415 macro_build (&offset_expr
, "daddiu", "t,r,j",
10416 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10417 macro_build (&offset_expr
, "daddiu", "t,r,j",
10418 AT
, AT
, BFD_RELOC_LO16
);
10419 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10420 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10425 macro_build (&offset_expr
, "lui", LUI_FMT
,
10426 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10427 macro_build (&offset_expr
, "daddiu", "t,r,j",
10428 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10429 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10430 macro_build (&offset_expr
, "daddiu", "t,r,j",
10431 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10432 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10433 macro_build (&offset_expr
, "daddiu", "t,r,j",
10434 tempreg
, tempreg
, BFD_RELOC_LO16
);
10437 if (mips_relax
.sequence
)
10442 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10443 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10445 relax_start (offset_expr
.X_add_symbol
);
10446 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10447 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10450 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10451 as_bad (_("offset too large"));
10452 macro_build_lui (&offset_expr
, tempreg
);
10453 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10454 tempreg
, tempreg
, BFD_RELOC_LO16
);
10455 if (mips_relax
.sequence
)
10459 else if (!mips_big_got
&& !HAVE_NEWABI
)
10461 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10463 /* If this is a reference to an external symbol, and there
10464 is no constant, we want
10465 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10466 or for lca or if tempreg is PIC_CALL_REG
10467 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10468 For a local symbol, we want
10469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10471 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10473 If we have a small constant, and this is a reference to
10474 an external symbol, we want
10475 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10477 addiu $tempreg,$tempreg,<constant>
10478 For a local symbol, we want the same instruction
10479 sequence, but we output a BFD_RELOC_LO16 reloc on the
10482 If we have a large constant, and this is a reference to
10483 an external symbol, we want
10484 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10485 lui $at,<hiconstant>
10486 addiu $at,$at,<loconstant>
10487 addu $tempreg,$tempreg,$at
10488 For a local symbol, we want the same instruction
10489 sequence, but we output a BFD_RELOC_LO16 reloc on the
10493 if (offset_expr
.X_add_number
== 0)
10495 if (mips_pic
== SVR4_PIC
10497 && (call
|| tempreg
== PIC_CALL_REG
))
10498 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10500 relax_start (offset_expr
.X_add_symbol
);
10501 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10502 lw_reloc_type
, mips_gp_register
);
10505 /* We're going to put in an addu instruction using
10506 tempreg, so we may as well insert the nop right
10511 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10512 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10514 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10515 tempreg
, tempreg
, BFD_RELOC_LO16
);
10517 /* FIXME: If breg == 0, and the next instruction uses
10518 $tempreg, then if this variant case is used an extra
10519 nop will be generated. */
10521 else if (offset_expr
.X_add_number
>= -0x8000
10522 && offset_expr
.X_add_number
< 0x8000)
10524 load_got_offset (tempreg
, &offset_expr
);
10526 add_got_offset (tempreg
, &offset_expr
);
10530 expr1
.X_add_number
= offset_expr
.X_add_number
;
10531 offset_expr
.X_add_number
=
10532 SEXT_16BIT (offset_expr
.X_add_number
);
10533 load_got_offset (tempreg
, &offset_expr
);
10534 offset_expr
.X_add_number
= expr1
.X_add_number
;
10535 /* If we are going to add in a base register, and the
10536 target register and the base register are the same,
10537 then we are using AT as a temporary register. Since
10538 we want to load the constant into AT, we add our
10539 current AT (from the global offset table) and the
10540 register into the register now, and pretend we were
10541 not using a base register. */
10545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10550 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10554 else if (!mips_big_got
&& HAVE_NEWABI
)
10556 int add_breg_early
= 0;
10558 /* If this is a reference to an external, and there is no
10559 constant, or local symbol (*), with or without a
10561 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10562 or for lca or if tempreg is PIC_CALL_REG
10563 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10565 If we have a small constant, and this is a reference to
10566 an external symbol, we want
10567 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10568 addiu $tempreg,$tempreg,<constant>
10570 If we have a large constant, and this is a reference to
10571 an external symbol, we want
10572 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10573 lui $at,<hiconstant>
10574 addiu $at,$at,<loconstant>
10575 addu $tempreg,$tempreg,$at
10577 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10578 local symbols, even though it introduces an additional
10581 if (offset_expr
.X_add_number
)
10583 expr1
.X_add_number
= offset_expr
.X_add_number
;
10584 offset_expr
.X_add_number
= 0;
10586 relax_start (offset_expr
.X_add_symbol
);
10587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10588 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10590 if (expr1
.X_add_number
>= -0x8000
10591 && expr1
.X_add_number
< 0x8000)
10593 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10594 tempreg
, tempreg
, BFD_RELOC_LO16
);
10596 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10600 /* If we are going to add in a base register, and the
10601 target register and the base register are the same,
10602 then we are using AT as a temporary register. Since
10603 we want to load the constant into AT, we add our
10604 current AT (from the global offset table) and the
10605 register into the register now, and pretend we were
10606 not using a base register. */
10611 gas_assert (tempreg
== AT
);
10612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10615 add_breg_early
= 1;
10618 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10625 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10628 offset_expr
.X_add_number
= expr1
.X_add_number
;
10630 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10631 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10632 if (add_breg_early
)
10634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10635 op
[0], tempreg
, breg
);
10641 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10643 relax_start (offset_expr
.X_add_symbol
);
10644 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10645 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10647 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10648 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10653 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10654 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10657 else if (mips_big_got
&& !HAVE_NEWABI
)
10660 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10661 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10662 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10664 /* This is the large GOT case. If this is a reference to an
10665 external symbol, and there is no constant, we want
10666 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10667 addu $tempreg,$tempreg,$gp
10668 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10669 or for lca or if tempreg is PIC_CALL_REG
10670 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10671 addu $tempreg,$tempreg,$gp
10672 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10673 For a local symbol, we want
10674 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10676 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10678 If we have a small constant, and this is a reference to
10679 an external symbol, we want
10680 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10681 addu $tempreg,$tempreg,$gp
10682 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10684 addiu $tempreg,$tempreg,<constant>
10685 For a local symbol, we want
10686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10688 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10690 If we have a large constant, and this is a reference to
10691 an external symbol, we want
10692 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10693 addu $tempreg,$tempreg,$gp
10694 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10695 lui $at,<hiconstant>
10696 addiu $at,$at,<loconstant>
10697 addu $tempreg,$tempreg,$at
10698 For a local symbol, we want
10699 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10700 lui $at,<hiconstant>
10701 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10702 addu $tempreg,$tempreg,$at
10705 expr1
.X_add_number
= offset_expr
.X_add_number
;
10706 offset_expr
.X_add_number
= 0;
10707 relax_start (offset_expr
.X_add_symbol
);
10708 gpdelay
= reg_needs_delay (mips_gp_register
);
10709 if (expr1
.X_add_number
== 0 && breg
== 0
10710 && (call
|| tempreg
== PIC_CALL_REG
))
10712 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10713 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10715 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10716 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10717 tempreg
, tempreg
, mips_gp_register
);
10718 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10719 tempreg
, lw_reloc_type
, tempreg
);
10720 if (expr1
.X_add_number
== 0)
10724 /* We're going to put in an addu instruction using
10725 tempreg, so we may as well insert the nop right
10730 else if (expr1
.X_add_number
>= -0x8000
10731 && expr1
.X_add_number
< 0x8000)
10734 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10735 tempreg
, tempreg
, BFD_RELOC_LO16
);
10741 /* If we are going to add in a base register, and the
10742 target register and the base register are the same,
10743 then we are using AT as a temporary register. Since
10744 we want to load the constant into AT, we add our
10745 current AT (from the global offset table) and the
10746 register into the register now, and pretend we were
10747 not using a base register. */
10752 gas_assert (tempreg
== AT
);
10754 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10759 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10764 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10769 /* This is needed because this instruction uses $gp, but
10770 the first instruction on the main stream does not. */
10771 macro_build (NULL
, "nop", "");
10774 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10775 local_reloc_type
, mips_gp_register
);
10776 if (expr1
.X_add_number
>= -0x8000
10777 && expr1
.X_add_number
< 0x8000)
10780 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10781 tempreg
, tempreg
, BFD_RELOC_LO16
);
10782 /* FIXME: If add_number is 0, and there was no base
10783 register, the external symbol case ended with a load,
10784 so if the symbol turns out to not be external, and
10785 the next instruction uses tempreg, an unnecessary nop
10786 will be inserted. */
10792 /* We must add in the base register now, as in the
10793 external symbol case. */
10794 gas_assert (tempreg
== AT
);
10796 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10799 /* We set breg to 0 because we have arranged to add
10800 it in in both cases. */
10804 macro_build_lui (&expr1
, AT
);
10805 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10806 AT
, AT
, BFD_RELOC_LO16
);
10807 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10808 tempreg
, tempreg
, AT
);
10813 else if (mips_big_got
&& HAVE_NEWABI
)
10815 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10816 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10817 int add_breg_early
= 0;
10819 /* This is the large GOT case. If this is a reference to an
10820 external symbol, and there is no constant, we want
10821 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10822 add $tempreg,$tempreg,$gp
10823 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10824 or for lca or if tempreg is PIC_CALL_REG
10825 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10826 add $tempreg,$tempreg,$gp
10827 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10829 If we have a small constant, and this is a reference to
10830 an external symbol, we want
10831 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10832 add $tempreg,$tempreg,$gp
10833 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10834 addi $tempreg,$tempreg,<constant>
10836 If we have a large constant, and this is a reference to
10837 an external symbol, we want
10838 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10839 addu $tempreg,$tempreg,$gp
10840 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10841 lui $at,<hiconstant>
10842 addi $at,$at,<loconstant>
10843 add $tempreg,$tempreg,$at
10845 If we have NewABI, and we know it's a local symbol, we want
10846 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10847 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10848 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10850 relax_start (offset_expr
.X_add_symbol
);
10852 expr1
.X_add_number
= offset_expr
.X_add_number
;
10853 offset_expr
.X_add_number
= 0;
10855 if (expr1
.X_add_number
== 0 && breg
== 0
10856 && (call
|| tempreg
== PIC_CALL_REG
))
10858 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10859 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10861 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10862 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10863 tempreg
, tempreg
, mips_gp_register
);
10864 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10865 tempreg
, lw_reloc_type
, tempreg
);
10867 if (expr1
.X_add_number
== 0)
10869 else if (expr1
.X_add_number
>= -0x8000
10870 && expr1
.X_add_number
< 0x8000)
10872 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10873 tempreg
, tempreg
, BFD_RELOC_LO16
);
10875 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10879 /* If we are going to add in a base register, and the
10880 target register and the base register are the same,
10881 then we are using AT as a temporary register. Since
10882 we want to load the constant into AT, we add our
10883 current AT (from the global offset table) and the
10884 register into the register now, and pretend we were
10885 not using a base register. */
10890 gas_assert (tempreg
== AT
);
10891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10894 add_breg_early
= 1;
10897 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10898 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10903 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10906 offset_expr
.X_add_number
= expr1
.X_add_number
;
10907 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10908 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10909 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10910 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10911 if (add_breg_early
)
10913 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10914 op
[0], tempreg
, breg
);
10924 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10928 gas_assert (!mips_opts
.micromips
);
10929 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10933 gas_assert (!mips_opts
.micromips
);
10934 macro_build (NULL
, "c2", "C", 0x02);
10938 gas_assert (!mips_opts
.micromips
);
10939 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10943 gas_assert (!mips_opts
.micromips
);
10944 macro_build (NULL
, "c2", "C", 3);
10948 gas_assert (!mips_opts
.micromips
);
10949 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10953 /* The j instruction may not be used in PIC code, since it
10954 requires an absolute address. We convert it to a b
10956 if (mips_pic
== NO_PIC
)
10957 macro_build (&offset_expr
, "j", "a");
10959 macro_build (&offset_expr
, "b", "p");
10962 /* The jal instructions must be handled as macros because when
10963 generating PIC code they expand to multi-instruction
10964 sequences. Normally they are simple instructions. */
10968 /* Fall through. */
10970 gas_assert (mips_opts
.micromips
);
10971 if (mips_opts
.insn32
)
10973 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10981 /* Fall through. */
10984 if (mips_pic
== NO_PIC
)
10986 s
= jals
? "jalrs" : "jalr";
10987 if (mips_opts
.micromips
10988 && !mips_opts
.insn32
10990 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10991 macro_build (NULL
, s
, "mj", op
[1]);
10993 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10997 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10998 && mips_cprestore_offset
>= 0);
11000 if (op
[1] != PIC_CALL_REG
)
11001 as_warn (_("MIPS PIC call to register other than $25"));
11003 s
= ((mips_opts
.micromips
11004 && !mips_opts
.insn32
11005 && (!mips_opts
.noreorder
|| cprestore
))
11006 ? "jalrs" : "jalr");
11007 if (mips_opts
.micromips
11008 && !mips_opts
.insn32
11010 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11011 macro_build (NULL
, s
, "mj", op
[1]);
11013 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11014 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11016 if (mips_cprestore_offset
< 0)
11017 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11020 if (!mips_frame_reg_valid
)
11022 as_warn (_("no .frame pseudo-op used in PIC code"));
11023 /* Quiet this warning. */
11024 mips_frame_reg_valid
= 1;
11026 if (!mips_cprestore_valid
)
11028 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11029 /* Quiet this warning. */
11030 mips_cprestore_valid
= 1;
11032 if (mips_opts
.noreorder
)
11033 macro_build (NULL
, "nop", "");
11034 expr1
.X_add_number
= mips_cprestore_offset
;
11035 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11038 HAVE_64BIT_ADDRESSES
);
11046 gas_assert (mips_opts
.micromips
);
11047 if (mips_opts
.insn32
)
11049 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11053 /* Fall through. */
11055 if (mips_pic
== NO_PIC
)
11056 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11057 else if (mips_pic
== SVR4_PIC
)
11059 /* If this is a reference to an external symbol, and we are
11060 using a small GOT, we want
11061 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11065 lw $gp,cprestore($sp)
11066 The cprestore value is set using the .cprestore
11067 pseudo-op. If we are using a big GOT, we want
11068 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11070 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11074 lw $gp,cprestore($sp)
11075 If the symbol is not external, we want
11076 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11078 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11081 lw $gp,cprestore($sp)
11083 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11084 sequences above, minus nops, unless the symbol is local,
11085 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11091 relax_start (offset_expr
.X_add_symbol
);
11092 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11093 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11096 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11097 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11103 relax_start (offset_expr
.X_add_symbol
);
11104 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11105 BFD_RELOC_MIPS_CALL_HI16
);
11106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11107 PIC_CALL_REG
, mips_gp_register
);
11108 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11109 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11112 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11113 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11115 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11116 PIC_CALL_REG
, PIC_CALL_REG
,
11117 BFD_RELOC_MIPS_GOT_OFST
);
11121 macro_build_jalr (&offset_expr
, 0);
11125 relax_start (offset_expr
.X_add_symbol
);
11128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11129 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11138 gpdelay
= reg_needs_delay (mips_gp_register
);
11139 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11140 BFD_RELOC_MIPS_CALL_HI16
);
11141 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11142 PIC_CALL_REG
, mips_gp_register
);
11143 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11144 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11149 macro_build (NULL
, "nop", "");
11151 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11152 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11155 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11156 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11158 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11160 if (mips_cprestore_offset
< 0)
11161 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11164 if (!mips_frame_reg_valid
)
11166 as_warn (_("no .frame pseudo-op used in PIC code"));
11167 /* Quiet this warning. */
11168 mips_frame_reg_valid
= 1;
11170 if (!mips_cprestore_valid
)
11172 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11173 /* Quiet this warning. */
11174 mips_cprestore_valid
= 1;
11176 if (mips_opts
.noreorder
)
11177 macro_build (NULL
, "nop", "");
11178 expr1
.X_add_number
= mips_cprestore_offset
;
11179 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11182 HAVE_64BIT_ADDRESSES
);
11186 else if (mips_pic
== VXWORKS_PIC
)
11187 as_bad (_("non-PIC jump used in PIC library"));
11294 gas_assert (!mips_opts
.micromips
);
11297 /* Itbl support may require additional care here. */
11303 /* Itbl support may require additional care here. */
11309 offbits
= (mips_opts
.micromips
? 12
11310 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11312 /* Itbl support may require additional care here. */
11316 gas_assert (!mips_opts
.micromips
);
11319 /* Itbl support may require additional care here. */
11325 offbits
= (mips_opts
.micromips
? 12 : 16);
11330 offbits
= (mips_opts
.micromips
? 12 : 16);
11335 /* Itbl support may require additional care here. */
11341 offbits
= (mips_opts
.micromips
? 12
11342 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11344 /* Itbl support may require additional care here. */
11350 /* Itbl support may require additional care here. */
11356 /* Itbl support may require additional care here. */
11362 offbits
= (mips_opts
.micromips
? 12 : 16);
11367 offbits
= (mips_opts
.micromips
? 12 : 16);
11372 offbits
= (mips_opts
.micromips
? 12
11373 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11379 offbits
= (mips_opts
.micromips
? 12
11380 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11386 offbits
= (mips_opts
.micromips
? 12 : 16);
11389 gas_assert (mips_opts
.micromips
);
11396 gas_assert (mips_opts
.micromips
);
11403 gas_assert (mips_opts
.micromips
);
11409 gas_assert (mips_opts
.micromips
);
11416 /* We don't want to use $0 as tempreg. */
11417 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11420 tempreg
= op
[0] + lp
;
11436 gas_assert (!mips_opts
.micromips
);
11439 /* Itbl support may require additional care here. */
11445 /* Itbl support may require additional care here. */
11451 offbits
= (mips_opts
.micromips
? 12
11452 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11454 /* Itbl support may require additional care here. */
11458 gas_assert (!mips_opts
.micromips
);
11461 /* Itbl support may require additional care here. */
11467 offbits
= (mips_opts
.micromips
? 12 : 16);
11472 offbits
= (mips_opts
.micromips
? 12 : 16);
11477 offbits
= (mips_opts
.micromips
? 12
11478 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11484 offbits
= (mips_opts
.micromips
? 12
11485 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11490 fmt
= (mips_opts
.micromips
? "k,~(b)"
11491 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11493 offbits
= (mips_opts
.micromips
? 12
11494 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11504 fmt
= (mips_opts
.micromips
? "k,~(b)"
11505 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11507 offbits
= (mips_opts
.micromips
? 12
11508 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11520 /* Itbl support may require additional care here. */
11525 offbits
= (mips_opts
.micromips
? 12
11526 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11528 /* Itbl support may require additional care here. */
11534 /* Itbl support may require additional care here. */
11538 gas_assert (!mips_opts
.micromips
);
11541 /* Itbl support may require additional care here. */
11547 offbits
= (mips_opts
.micromips
? 12 : 16);
11552 offbits
= (mips_opts
.micromips
? 12 : 16);
11555 gas_assert (mips_opts
.micromips
);
11561 gas_assert (mips_opts
.micromips
);
11567 gas_assert (mips_opts
.micromips
);
11573 gas_assert (mips_opts
.micromips
);
11582 if (small_offset_p (0, align
, 16))
11584 /* The first case exists for M_LD_AB and M_SD_AB, which are
11585 macros for o32 but which should act like normal instructions
11588 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11589 offset_reloc
[1], offset_reloc
[2], breg
);
11590 else if (small_offset_p (0, align
, offbits
))
11593 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11595 macro_build (NULL
, s
, fmt
, op
[0],
11596 (int) offset_expr
.X_add_number
, breg
);
11602 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11603 tempreg
, breg
, -1, offset_reloc
[0],
11604 offset_reloc
[1], offset_reloc
[2]);
11606 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11608 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11616 if (offset_expr
.X_op
!= O_constant
11617 && offset_expr
.X_op
!= O_symbol
)
11619 as_bad (_("expression too complex"));
11620 offset_expr
.X_op
= O_constant
;
11623 if (HAVE_32BIT_ADDRESSES
11624 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11628 sprintf_vma (value
, offset_expr
.X_add_number
);
11629 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11632 /* A constant expression in PIC code can be handled just as it
11633 is in non PIC code. */
11634 if (offset_expr
.X_op
== O_constant
)
11636 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11637 offbits
== 0 ? 16 : offbits
);
11638 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11640 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11642 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11643 tempreg
, tempreg
, breg
);
11646 if (offset_expr
.X_add_number
!= 0)
11647 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11648 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11649 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11651 else if (offbits
== 16)
11652 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11654 macro_build (NULL
, s
, fmt
, op
[0],
11655 (int) offset_expr
.X_add_number
, tempreg
);
11657 else if (offbits
!= 16)
11659 /* The offset field is too narrow to be used for a low-part
11660 relocation, so load the whole address into the auxillary
11662 load_address (tempreg
, &offset_expr
, &used_at
);
11664 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11665 tempreg
, tempreg
, breg
);
11667 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11669 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11671 else if (mips_pic
== NO_PIC
)
11673 /* If this is a reference to a GP relative symbol, and there
11674 is no base register, we want
11675 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11676 Otherwise, if there is no base register, we want
11677 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11678 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11679 If we have a constant, we need two instructions anyhow,
11680 so we always use the latter form.
11682 If we have a base register, and this is a reference to a
11683 GP relative symbol, we want
11684 addu $tempreg,$breg,$gp
11685 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11687 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11688 addu $tempreg,$tempreg,$breg
11689 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11690 With a constant we always use the latter case.
11692 With 64bit address space and no base register and $at usable,
11694 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11695 lui $at,<sym> (BFD_RELOC_HI16_S)
11696 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11699 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11700 If we have a base register, we want
11701 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11702 lui $at,<sym> (BFD_RELOC_HI16_S)
11703 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11707 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11709 Without $at we can't generate the optimal path for superscalar
11710 processors here since this would require two temporary registers.
11711 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11712 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11714 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11716 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11717 If we have a base register, we want
11718 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11719 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11721 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11723 daddu $tempreg,$tempreg,$breg
11724 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11726 For GP relative symbols in 64bit address space we can use
11727 the same sequence as in 32bit address space. */
11728 if (HAVE_64BIT_SYMBOLS
)
11730 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11731 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11733 relax_start (offset_expr
.X_add_symbol
);
11736 macro_build (&offset_expr
, s
, fmt
, op
[0],
11737 BFD_RELOC_GPREL16
, mips_gp_register
);
11741 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11742 tempreg
, breg
, mips_gp_register
);
11743 macro_build (&offset_expr
, s
, fmt
, op
[0],
11744 BFD_RELOC_GPREL16
, tempreg
);
11749 if (used_at
== 0 && mips_opts
.at
)
11751 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11752 BFD_RELOC_MIPS_HIGHEST
);
11753 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11755 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11756 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11758 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11759 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11760 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11761 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11767 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11768 BFD_RELOC_MIPS_HIGHEST
);
11769 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11770 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11771 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11772 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11773 tempreg
, BFD_RELOC_HI16_S
);
11774 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11776 macro_build (NULL
, "daddu", "d,v,t",
11777 tempreg
, tempreg
, breg
);
11778 macro_build (&offset_expr
, s
, fmt
, op
[0],
11779 BFD_RELOC_LO16
, tempreg
);
11782 if (mips_relax
.sequence
)
11789 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11790 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11792 relax_start (offset_expr
.X_add_symbol
);
11793 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11797 macro_build_lui (&offset_expr
, tempreg
);
11798 macro_build (&offset_expr
, s
, fmt
, op
[0],
11799 BFD_RELOC_LO16
, tempreg
);
11800 if (mips_relax
.sequence
)
11805 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11806 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11808 relax_start (offset_expr
.X_add_symbol
);
11809 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11810 tempreg
, breg
, mips_gp_register
);
11811 macro_build (&offset_expr
, s
, fmt
, op
[0],
11812 BFD_RELOC_GPREL16
, tempreg
);
11815 macro_build_lui (&offset_expr
, tempreg
);
11816 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11817 tempreg
, tempreg
, breg
);
11818 macro_build (&offset_expr
, s
, fmt
, op
[0],
11819 BFD_RELOC_LO16
, tempreg
);
11820 if (mips_relax
.sequence
)
11824 else if (!mips_big_got
)
11826 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11828 /* If this is a reference to an external symbol, we want
11829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11831 <op> op[0],0($tempreg)
11833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11835 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11836 <op> op[0],0($tempreg)
11838 For NewABI, we want
11839 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11840 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11842 If there is a base register, we add it to $tempreg before
11843 the <op>. If there is a constant, we stick it in the
11844 <op> instruction. We don't handle constants larger than
11845 16 bits, because we have no way to load the upper 16 bits
11846 (actually, we could handle them for the subset of cases
11847 in which we are not using $at). */
11848 gas_assert (offset_expr
.X_op
== O_symbol
);
11851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11852 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11854 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11855 tempreg
, tempreg
, breg
);
11856 macro_build (&offset_expr
, s
, fmt
, op
[0],
11857 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11860 expr1
.X_add_number
= offset_expr
.X_add_number
;
11861 offset_expr
.X_add_number
= 0;
11862 if (expr1
.X_add_number
< -0x8000
11863 || expr1
.X_add_number
>= 0x8000)
11864 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11865 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11866 lw_reloc_type
, mips_gp_register
);
11868 relax_start (offset_expr
.X_add_symbol
);
11870 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11871 tempreg
, BFD_RELOC_LO16
);
11874 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11875 tempreg
, tempreg
, breg
);
11876 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11878 else if (mips_big_got
&& !HAVE_NEWABI
)
11882 /* If this is a reference to an external symbol, we want
11883 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11884 addu $tempreg,$tempreg,$gp
11885 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11886 <op> op[0],0($tempreg)
11888 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11890 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11891 <op> op[0],0($tempreg)
11892 If there is a base register, we add it to $tempreg before
11893 the <op>. If there is a constant, we stick it in the
11894 <op> instruction. We don't handle constants larger than
11895 16 bits, because we have no way to load the upper 16 bits
11896 (actually, we could handle them for the subset of cases
11897 in which we are not using $at). */
11898 gas_assert (offset_expr
.X_op
== O_symbol
);
11899 expr1
.X_add_number
= offset_expr
.X_add_number
;
11900 offset_expr
.X_add_number
= 0;
11901 if (expr1
.X_add_number
< -0x8000
11902 || expr1
.X_add_number
>= 0x8000)
11903 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11904 gpdelay
= reg_needs_delay (mips_gp_register
);
11905 relax_start (offset_expr
.X_add_symbol
);
11906 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11907 BFD_RELOC_MIPS_GOT_HI16
);
11908 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11910 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11911 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11914 macro_build (NULL
, "nop", "");
11915 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11916 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11918 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11919 tempreg
, BFD_RELOC_LO16
);
11923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11924 tempreg
, tempreg
, breg
);
11925 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11927 else if (mips_big_got
&& HAVE_NEWABI
)
11929 /* If this is a reference to an external symbol, we want
11930 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11931 add $tempreg,$tempreg,$gp
11932 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11933 <op> op[0],<ofst>($tempreg)
11934 Otherwise, for local symbols, we want:
11935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11936 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11937 gas_assert (offset_expr
.X_op
== O_symbol
);
11938 expr1
.X_add_number
= offset_expr
.X_add_number
;
11939 offset_expr
.X_add_number
= 0;
11940 if (expr1
.X_add_number
< -0x8000
11941 || expr1
.X_add_number
>= 0x8000)
11942 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11943 relax_start (offset_expr
.X_add_symbol
);
11944 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11945 BFD_RELOC_MIPS_GOT_HI16
);
11946 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11948 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11949 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11951 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11952 tempreg
, tempreg
, breg
);
11953 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11956 offset_expr
.X_add_number
= expr1
.X_add_number
;
11957 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11958 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11960 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11961 tempreg
, tempreg
, breg
);
11962 macro_build (&offset_expr
, s
, fmt
, op
[0],
11963 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11972 gas_assert (mips_opts
.micromips
);
11973 gas_assert (mips_opts
.insn32
);
11974 start_noreorder ();
11975 macro_build (NULL
, "jr", "s", RA
);
11976 expr1
.X_add_number
= op
[0] << 2;
11977 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11982 gas_assert (mips_opts
.micromips
);
11983 gas_assert (mips_opts
.insn32
);
11984 macro_build (NULL
, "jr", "s", op
[0]);
11985 if (mips_opts
.noreorder
)
11986 macro_build (NULL
, "nop", "");
11991 load_register (op
[0], &imm_expr
, 0);
11995 load_register (op
[0], &imm_expr
, 1);
11999 if (imm_expr
.X_op
== O_constant
)
12002 load_register (AT
, &imm_expr
, 0);
12003 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12008 gas_assert (imm_expr
.X_op
== O_absent
12009 && offset_expr
.X_op
== O_symbol
12010 && strcmp (segment_name (S_GET_SEGMENT
12011 (offset_expr
.X_add_symbol
)),
12013 && offset_expr
.X_add_number
== 0);
12014 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12015 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12020 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12021 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12022 order 32 bits of the value and the low order 32 bits are either
12023 zero or in OFFSET_EXPR. */
12024 if (imm_expr
.X_op
== O_constant
)
12026 if (GPR_SIZE
== 64)
12027 load_register (op
[0], &imm_expr
, 1);
12032 if (target_big_endian
)
12044 load_register (hreg
, &imm_expr
, 0);
12047 if (offset_expr
.X_op
== O_absent
)
12048 move_register (lreg
, 0);
12051 gas_assert (offset_expr
.X_op
== O_constant
);
12052 load_register (lreg
, &offset_expr
, 0);
12058 gas_assert (imm_expr
.X_op
== O_absent
);
12060 /* We know that sym is in the .rdata section. First we get the
12061 upper 16 bits of the address. */
12062 if (mips_pic
== NO_PIC
)
12064 macro_build_lui (&offset_expr
, AT
);
12069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12070 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12074 /* Now we load the register(s). */
12075 if (GPR_SIZE
== 64)
12078 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12079 BFD_RELOC_LO16
, AT
);
12084 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12085 BFD_RELOC_LO16
, AT
);
12088 /* FIXME: How in the world do we deal with the possible
12090 offset_expr
.X_add_number
+= 4;
12091 macro_build (&offset_expr
, "lw", "t,o(b)",
12092 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12098 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12099 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12100 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12101 the value and the low order 32 bits are either zero or in
12103 if (imm_expr
.X_op
== O_constant
)
12106 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12107 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12108 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12111 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12112 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12113 else if (FPR_SIZE
!= 32)
12114 as_bad (_("Unable to generate `%s' compliant code "
12116 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12118 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12119 if (offset_expr
.X_op
== O_absent
)
12120 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12123 gas_assert (offset_expr
.X_op
== O_constant
);
12124 load_register (AT
, &offset_expr
, 0);
12125 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12131 gas_assert (imm_expr
.X_op
== O_absent
12132 && offset_expr
.X_op
== O_symbol
12133 && offset_expr
.X_add_number
== 0);
12134 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12135 if (strcmp (s
, ".lit8") == 0)
12137 op
[2] = mips_gp_register
;
12138 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12139 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12140 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12144 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12146 if (mips_pic
!= NO_PIC
)
12147 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12148 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12151 /* FIXME: This won't work for a 64 bit address. */
12152 macro_build_lui (&offset_expr
, AT
);
12156 offset_reloc
[0] = BFD_RELOC_LO16
;
12157 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12158 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12165 * The MIPS assembler seems to check for X_add_number not
12166 * being double aligned and generating:
12167 * lui at,%hi(foo+1)
12169 * addiu at,at,%lo(foo+1)
12172 * But, the resulting address is the same after relocation so why
12173 * generate the extra instruction?
12175 /* Itbl support may require additional care here. */
12178 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12187 gas_assert (!mips_opts
.micromips
);
12188 /* Itbl support may require additional care here. */
12191 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12211 if (GPR_SIZE
== 64)
12221 if (GPR_SIZE
== 64)
12229 /* Even on a big endian machine $fn comes before $fn+1. We have
12230 to adjust when loading from memory. We set coproc if we must
12231 load $fn+1 first. */
12232 /* Itbl support may require additional care here. */
12233 if (!target_big_endian
)
12237 if (small_offset_p (0, align
, 16))
12240 if (!small_offset_p (4, align
, 16))
12242 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12243 -1, offset_reloc
[0], offset_reloc
[1],
12245 expr1
.X_add_number
= 0;
12249 offset_reloc
[0] = BFD_RELOC_LO16
;
12250 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12251 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12253 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12255 ep
->X_add_number
+= 4;
12256 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12257 offset_reloc
[1], offset_reloc
[2], breg
);
12258 ep
->X_add_number
-= 4;
12259 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12260 offset_reloc
[1], offset_reloc
[2], breg
);
12264 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12265 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12267 ep
->X_add_number
+= 4;
12268 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12269 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12275 if (offset_expr
.X_op
!= O_symbol
12276 && offset_expr
.X_op
!= O_constant
)
12278 as_bad (_("expression too complex"));
12279 offset_expr
.X_op
= O_constant
;
12282 if (HAVE_32BIT_ADDRESSES
12283 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12287 sprintf_vma (value
, offset_expr
.X_add_number
);
12288 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12291 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12293 /* If this is a reference to a GP relative symbol, we want
12294 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12295 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12296 If we have a base register, we use this
12298 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12299 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12300 If this is not a GP relative symbol, we want
12301 lui $at,<sym> (BFD_RELOC_HI16_S)
12302 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12303 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12304 If there is a base register, we add it to $at after the
12305 lui instruction. If there is a constant, we always use
12307 if (offset_expr
.X_op
== O_symbol
12308 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12309 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12311 relax_start (offset_expr
.X_add_symbol
);
12314 tempreg
= mips_gp_register
;
12318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12319 AT
, breg
, mips_gp_register
);
12324 /* Itbl support may require additional care here. */
12325 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12326 BFD_RELOC_GPREL16
, tempreg
);
12327 offset_expr
.X_add_number
+= 4;
12329 /* Set mips_optimize to 2 to avoid inserting an
12331 hold_mips_optimize
= mips_optimize
;
12333 /* Itbl support may require additional care here. */
12334 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12335 BFD_RELOC_GPREL16
, tempreg
);
12336 mips_optimize
= hold_mips_optimize
;
12340 offset_expr
.X_add_number
-= 4;
12343 if (offset_high_part (offset_expr
.X_add_number
, 16)
12344 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12346 load_address (AT
, &offset_expr
, &used_at
);
12347 offset_expr
.X_op
= O_constant
;
12348 offset_expr
.X_add_number
= 0;
12351 macro_build_lui (&offset_expr
, AT
);
12353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12354 /* Itbl support may require additional care here. */
12355 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12356 BFD_RELOC_LO16
, AT
);
12357 /* FIXME: How do we handle overflow here? */
12358 offset_expr
.X_add_number
+= 4;
12359 /* Itbl support may require additional care here. */
12360 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12361 BFD_RELOC_LO16
, AT
);
12362 if (mips_relax
.sequence
)
12365 else if (!mips_big_got
)
12367 /* If this is a reference to an external symbol, we want
12368 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12371 <op> op[0]+1,4($at)
12373 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12375 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12376 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12377 If there is a base register we add it to $at before the
12378 lwc1 instructions. If there is a constant we include it
12379 in the lwc1 instructions. */
12381 expr1
.X_add_number
= offset_expr
.X_add_number
;
12382 if (expr1
.X_add_number
< -0x8000
12383 || expr1
.X_add_number
>= 0x8000 - 4)
12384 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12385 load_got_offset (AT
, &offset_expr
);
12388 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12390 /* Set mips_optimize to 2 to avoid inserting an undesired
12392 hold_mips_optimize
= mips_optimize
;
12395 /* Itbl support may require additional care here. */
12396 relax_start (offset_expr
.X_add_symbol
);
12397 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12398 BFD_RELOC_LO16
, AT
);
12399 expr1
.X_add_number
+= 4;
12400 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12401 BFD_RELOC_LO16
, AT
);
12403 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12404 BFD_RELOC_LO16
, AT
);
12405 offset_expr
.X_add_number
+= 4;
12406 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12407 BFD_RELOC_LO16
, AT
);
12410 mips_optimize
= hold_mips_optimize
;
12412 else if (mips_big_got
)
12416 /* If this is a reference to an external symbol, we want
12417 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12419 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12422 <op> op[0]+1,4($at)
12424 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12426 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12427 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12428 If there is a base register we add it to $at before the
12429 lwc1 instructions. If there is a constant we include it
12430 in the lwc1 instructions. */
12432 expr1
.X_add_number
= offset_expr
.X_add_number
;
12433 offset_expr
.X_add_number
= 0;
12434 if (expr1
.X_add_number
< -0x8000
12435 || expr1
.X_add_number
>= 0x8000 - 4)
12436 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12437 gpdelay
= reg_needs_delay (mips_gp_register
);
12438 relax_start (offset_expr
.X_add_symbol
);
12439 macro_build (&offset_expr
, "lui", LUI_FMT
,
12440 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12441 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12442 AT
, AT
, mips_gp_register
);
12443 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12444 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12447 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12448 /* Itbl support may require additional care here. */
12449 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12450 BFD_RELOC_LO16
, AT
);
12451 expr1
.X_add_number
+= 4;
12453 /* Set mips_optimize to 2 to avoid inserting an undesired
12455 hold_mips_optimize
= mips_optimize
;
12457 /* Itbl support may require additional care here. */
12458 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12459 BFD_RELOC_LO16
, AT
);
12460 mips_optimize
= hold_mips_optimize
;
12461 expr1
.X_add_number
-= 4;
12464 offset_expr
.X_add_number
= expr1
.X_add_number
;
12466 macro_build (NULL
, "nop", "");
12467 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12468 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12472 /* Itbl support may require additional care here. */
12473 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12474 BFD_RELOC_LO16
, AT
);
12475 offset_expr
.X_add_number
+= 4;
12477 /* Set mips_optimize to 2 to avoid inserting an undesired
12479 hold_mips_optimize
= mips_optimize
;
12481 /* Itbl support may require additional care here. */
12482 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12483 BFD_RELOC_LO16
, AT
);
12484 mips_optimize
= hold_mips_optimize
;
12498 gas_assert (!mips_opts
.micromips
);
12503 /* New code added to support COPZ instructions.
12504 This code builds table entries out of the macros in mip_opcodes.
12505 R4000 uses interlocks to handle coproc delays.
12506 Other chips (like the R3000) require nops to be inserted for delays.
12508 FIXME: Currently, we require that the user handle delays.
12509 In order to fill delay slots for non-interlocked chips,
12510 we must have a way to specify delays based on the coprocessor.
12511 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12512 What are the side-effects of the cop instruction?
12513 What cache support might we have and what are its effects?
12514 Both coprocessor & memory require delays. how long???
12515 What registers are read/set/modified?
12517 If an itbl is provided to interpret cop instructions,
12518 this knowledge can be encoded in the itbl spec. */
12532 gas_assert (!mips_opts
.micromips
);
12533 /* For now we just do C (same as Cz). The parameter will be
12534 stored in insn_opcode by mips_ip. */
12535 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12539 move_register (op
[0], op
[1]);
12543 gas_assert (mips_opts
.micromips
);
12544 gas_assert (mips_opts
.insn32
);
12545 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12546 micromips_to_32_reg_m_map
[op
[1]]);
12547 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12548 micromips_to_32_reg_n_map
[op
[2]]);
12554 if (mips_opts
.arch
== CPU_R5900
)
12555 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12559 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12560 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12567 /* The MIPS assembler some times generates shifts and adds. I'm
12568 not trying to be that fancy. GCC should do this for us
12571 load_register (AT
, &imm_expr
, dbl
);
12572 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12573 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12586 start_noreorder ();
12589 load_register (AT
, &imm_expr
, dbl
);
12590 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12591 op
[1], imm
? AT
: op
[2]);
12592 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12593 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12594 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12596 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12599 if (mips_opts
.micromips
)
12600 micromips_label_expr (&label_expr
);
12602 label_expr
.X_add_number
= 8;
12603 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12604 macro_build (NULL
, "nop", "");
12605 macro_build (NULL
, "break", BRK_FMT
, 6);
12606 if (mips_opts
.micromips
)
12607 micromips_add_label ();
12610 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12623 start_noreorder ();
12626 load_register (AT
, &imm_expr
, dbl
);
12627 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12628 op
[1], imm
? AT
: op
[2]);
12629 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12630 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12632 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12635 if (mips_opts
.micromips
)
12636 micromips_label_expr (&label_expr
);
12638 label_expr
.X_add_number
= 8;
12639 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12640 macro_build (NULL
, "nop", "");
12641 macro_build (NULL
, "break", BRK_FMT
, 6);
12642 if (mips_opts
.micromips
)
12643 micromips_add_label ();
12649 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12651 if (op
[0] == op
[1])
12658 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12659 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12663 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12664 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12665 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12666 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12670 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12672 if (op
[0] == op
[1])
12679 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12680 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12684 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12685 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12686 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12687 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12696 rot
= imm_expr
.X_add_number
& 0x3f;
12697 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12699 rot
= (64 - rot
) & 0x3f;
12701 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12703 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12708 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12711 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12712 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12715 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12716 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12717 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12725 rot
= imm_expr
.X_add_number
& 0x1f;
12726 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12728 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12729 (32 - rot
) & 0x1f);
12734 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12738 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12739 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12740 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12745 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12747 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12751 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12752 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12753 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12754 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12758 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12760 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12764 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12765 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12766 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12767 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12776 rot
= imm_expr
.X_add_number
& 0x3f;
12777 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12780 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12782 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12787 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12790 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12791 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12794 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12795 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12796 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12804 rot
= imm_expr
.X_add_number
& 0x1f;
12805 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12807 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12812 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12816 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12817 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12818 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12824 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12825 else if (op
[2] == 0)
12826 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12829 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12830 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12835 if (imm_expr
.X_add_number
== 0)
12837 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12842 as_warn (_("instruction %s: result is always false"),
12843 ip
->insn_mo
->name
);
12844 move_register (op
[0], 0);
12847 if (CPU_HAS_SEQ (mips_opts
.arch
)
12848 && -512 <= imm_expr
.X_add_number
12849 && imm_expr
.X_add_number
< 512)
12851 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12852 (int) imm_expr
.X_add_number
);
12855 if (imm_expr
.X_add_number
>= 0
12856 && imm_expr
.X_add_number
< 0x10000)
12857 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12858 else if (imm_expr
.X_add_number
> -0x8000
12859 && imm_expr
.X_add_number
< 0)
12861 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12862 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
12863 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12865 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12868 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12869 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12874 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12875 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12878 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12881 case M_SGE
: /* X >= Y <==> not (X < Y) */
12887 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12888 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12891 case M_SGE_I
: /* X >= I <==> not (X < I) */
12893 if (imm_expr
.X_add_number
>= -0x8000
12894 && imm_expr
.X_add_number
< 0x8000)
12895 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12896 op
[0], op
[1], BFD_RELOC_LO16
);
12899 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12900 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12904 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12907 case M_SGT
: /* X > Y <==> Y < X */
12913 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12916 case M_SGT_I
: /* X > I <==> I < X */
12923 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12924 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12927 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12933 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12934 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12937 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12944 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12945 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12946 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12950 if (imm_expr
.X_add_number
>= -0x8000
12951 && imm_expr
.X_add_number
< 0x8000)
12953 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12958 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12959 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12963 if (imm_expr
.X_add_number
>= -0x8000
12964 && imm_expr
.X_add_number
< 0x8000)
12966 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12971 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12972 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12977 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12978 else if (op
[2] == 0)
12979 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12982 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12983 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12988 if (imm_expr
.X_add_number
== 0)
12990 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12995 as_warn (_("instruction %s: result is always true"),
12996 ip
->insn_mo
->name
);
12997 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
12998 op
[0], 0, BFD_RELOC_LO16
);
13001 if (CPU_HAS_SEQ (mips_opts
.arch
)
13002 && -512 <= imm_expr
.X_add_number
13003 && imm_expr
.X_add_number
< 512)
13005 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13006 (int) imm_expr
.X_add_number
);
13009 if (imm_expr
.X_add_number
>= 0
13010 && imm_expr
.X_add_number
< 0x10000)
13012 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13015 else if (imm_expr
.X_add_number
> -0x8000
13016 && imm_expr
.X_add_number
< 0)
13018 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13019 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13020 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13022 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13025 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13026 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13031 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13032 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13035 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13050 if (!mips_opts
.micromips
)
13052 if (imm_expr
.X_add_number
> -0x200
13053 && imm_expr
.X_add_number
<= 0x200)
13055 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13056 (int) -imm_expr
.X_add_number
);
13065 if (imm_expr
.X_add_number
> -0x8000
13066 && imm_expr
.X_add_number
<= 0x8000)
13068 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13069 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13074 load_register (AT
, &imm_expr
, dbl
);
13075 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13097 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13098 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13103 gas_assert (!mips_opts
.micromips
);
13104 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13108 * Is the double cfc1 instruction a bug in the mips assembler;
13109 * or is there a reason for it?
13111 start_noreorder ();
13112 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13113 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13114 macro_build (NULL
, "nop", "");
13115 expr1
.X_add_number
= 3;
13116 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13117 expr1
.X_add_number
= 2;
13118 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13119 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13120 macro_build (NULL
, "nop", "");
13121 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13123 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13124 macro_build (NULL
, "nop", "");
13141 offbits
= (mips_opts
.micromips
? 12 : 16);
13147 offbits
= (mips_opts
.micromips
? 12 : 16);
13159 offbits
= (mips_opts
.micromips
? 12 : 16);
13166 offbits
= (mips_opts
.micromips
? 12 : 16);
13172 large_offset
= !small_offset_p (off
, align
, offbits
);
13174 expr1
.X_add_number
= 0;
13179 if (small_offset_p (0, align
, 16))
13180 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13181 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13184 load_address (tempreg
, ep
, &used_at
);
13186 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13187 tempreg
, tempreg
, breg
);
13189 offset_reloc
[0] = BFD_RELOC_LO16
;
13190 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13191 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13196 else if (!ust
&& op
[0] == breg
)
13207 if (!target_big_endian
)
13208 ep
->X_add_number
+= off
;
13210 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13212 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13213 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13215 if (!target_big_endian
)
13216 ep
->X_add_number
-= off
;
13218 ep
->X_add_number
+= off
;
13220 macro_build (NULL
, s2
, "t,~(b)",
13221 tempreg
, (int) ep
->X_add_number
, breg
);
13223 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13224 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13226 /* If necessary, move the result in tempreg to the final destination. */
13227 if (!ust
&& op
[0] != tempreg
)
13229 /* Protect second load's delay slot. */
13231 move_register (op
[0], tempreg
);
13237 if (target_big_endian
== ust
)
13238 ep
->X_add_number
+= off
;
13239 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13240 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13241 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13243 /* For halfword transfers we need a temporary register to shuffle
13244 bytes. Unfortunately for M_USH_A we have none available before
13245 the next store as AT holds the base address. We deal with this
13246 case by clobbering TREG and then restoring it as with ULH. */
13247 tempreg
= ust
== large_offset
? op
[0] : AT
;
13249 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13251 if (target_big_endian
== ust
)
13252 ep
->X_add_number
-= off
;
13254 ep
->X_add_number
+= off
;
13255 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13256 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13258 /* For M_USH_A re-retrieve the LSB. */
13259 if (ust
&& large_offset
)
13261 if (target_big_endian
)
13262 ep
->X_add_number
+= off
;
13264 ep
->X_add_number
-= off
;
13265 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13266 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13268 /* For ULH and M_USH_A OR the LSB in. */
13269 if (!ust
|| large_offset
)
13271 tempreg
= !large_offset
? AT
: op
[0];
13272 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13273 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13278 /* FIXME: Check if this is one of the itbl macros, since they
13279 are added dynamically. */
13280 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13283 if (!mips_opts
.at
&& used_at
)
13284 as_bad (_("macro used $at after \".set noat\""));
13287 /* Implement macros in mips16 mode. */
13290 mips16_macro (struct mips_cl_insn
*ip
)
13292 const struct mips_operand_array
*operands
;
13297 const char *s
, *s2
, *s3
;
13298 unsigned int op
[MAX_OPERANDS
];
13301 mask
= ip
->insn_mo
->mask
;
13303 operands
= insn_operands (ip
);
13304 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13305 if (operands
->operand
[i
])
13306 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13310 expr1
.X_op
= O_constant
;
13311 expr1
.X_op_symbol
= NULL
;
13312 expr1
.X_add_symbol
= NULL
;
13313 expr1
.X_add_number
= 1;
13332 start_noreorder ();
13333 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
13334 expr1
.X_add_number
= 2;
13335 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13336 macro_build (NULL
, "break", "6", 7);
13338 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13339 since that causes an overflow. We should do that as well,
13340 but I don't see how to do the comparisons without a temporary
13343 macro_build (NULL
, s
, "x", op
[0]);
13362 start_noreorder ();
13363 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
13364 expr1
.X_add_number
= 2;
13365 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13366 macro_build (NULL
, "break", "6", 7);
13368 macro_build (NULL
, s2
, "x", op
[0]);
13374 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13375 macro_build (NULL
, "mflo", "x", op
[0]);
13383 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13384 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
13388 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13389 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13393 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13394 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13416 goto do_reverse_branch
;
13420 goto do_reverse_branch
;
13432 goto do_reverse_branch
;
13443 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13444 macro_build (&offset_expr
, s2
, "p");
13471 goto do_addone_branch_i
;
13476 goto do_addone_branch_i
;
13491 goto do_addone_branch_i
;
13497 do_addone_branch_i
:
13498 ++imm_expr
.X_add_number
;
13501 macro_build (&imm_expr
, s
, s3
, op
[0]);
13502 macro_build (&offset_expr
, s2
, "p");
13506 expr1
.X_add_number
= 0;
13507 macro_build (&expr1
, "slti", "x,8", op
[1]);
13508 if (op
[0] != op
[1])
13509 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13510 expr1
.X_add_number
= 2;
13511 macro_build (&expr1
, "bteqz", "p");
13512 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13517 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13518 opcode bits in *OPCODE_EXTRA. */
13520 static struct mips_opcode
*
13521 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13522 ssize_t length
, unsigned int *opcode_extra
)
13524 char *name
, *dot
, *p
;
13525 unsigned int mask
, suffix
;
13527 struct mips_opcode
*insn
;
13529 /* Make a copy of the instruction so that we can fiddle with it. */
13530 name
= alloca (length
+ 1);
13531 memcpy (name
, start
, length
);
13532 name
[length
] = '\0';
13534 /* Look up the instruction as-is. */
13535 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13539 dot
= strchr (name
, '.');
13542 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13543 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13544 if (*p
== 0 && mask
!= 0)
13547 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13549 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13551 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13557 if (mips_opts
.micromips
)
13559 /* See if there's an instruction size override suffix,
13560 either `16' or `32', at the end of the mnemonic proper,
13561 that defines the operation, i.e. before the first `.'
13562 character if any. Strip it and retry. */
13563 opend
= dot
!= NULL
? dot
- name
: length
;
13564 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13566 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13572 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13573 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13576 forced_insn_length
= suffix
;
13585 /* Assemble an instruction into its binary format. If the instruction
13586 is a macro, set imm_expr and offset_expr to the values associated
13587 with "I" and "A" operands respectively. Otherwise store the value
13588 of the relocatable field (if any) in offset_expr. In both cases
13589 set offset_reloc to the relocation operators applied to offset_expr. */
13592 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13594 const struct mips_opcode
*first
, *past
;
13595 struct hash_control
*hash
;
13598 struct mips_operand_token
*tokens
;
13599 unsigned int opcode_extra
;
13601 if (mips_opts
.micromips
)
13603 hash
= micromips_op_hash
;
13604 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13609 past
= &mips_opcodes
[NUMOPCODES
];
13611 forced_insn_length
= 0;
13614 /* We first try to match an instruction up to a space or to the end. */
13615 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13618 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13621 set_insn_error (0, _("unrecognized opcode"));
13625 if (strcmp (first
->name
, "li.s") == 0)
13627 else if (strcmp (first
->name
, "li.d") == 0)
13631 tokens
= mips_parse_arguments (str
+ end
, format
);
13635 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13636 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13637 set_insn_error (0, _("invalid operands"));
13639 obstack_free (&mips_operand_tokens
, tokens
);
13642 /* As for mips_ip, but used when assembling MIPS16 code.
13643 Also set forced_insn_length to the resulting instruction size in
13644 bytes if the user explicitly requested a small or extended instruction. */
13647 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13650 struct mips_opcode
*first
;
13651 struct mips_operand_token
*tokens
;
13653 forced_insn_length
= 0;
13655 for (s
= str
; ISLOWER (*s
); ++s
)
13669 if (s
[1] == 't' && s
[2] == ' ')
13671 forced_insn_length
= 2;
13675 else if (s
[1] == 'e' && s
[2] == ' ')
13677 forced_insn_length
= 4;
13681 /* Fall through. */
13683 set_insn_error (0, _("unrecognized opcode"));
13687 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13688 forced_insn_length
= 2;
13691 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13696 set_insn_error (0, _("unrecognized opcode"));
13700 tokens
= mips_parse_arguments (s
, 0);
13704 if (!match_mips16_insns (insn
, first
, tokens
))
13705 set_insn_error (0, _("invalid operands"));
13707 obstack_free (&mips_operand_tokens
, tokens
);
13710 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13711 NBITS is the number of significant bits in VAL. */
13713 static unsigned long
13714 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13719 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13722 else if (nbits
== 15)
13724 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13729 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13732 return (extval
<< 16) | val
;
13735 /* Like decode_mips16_operand, but require the operand to be defined and
13736 require it to be an integer. */
13738 static const struct mips_int_operand
*
13739 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13741 const struct mips_operand
*operand
;
13743 operand
= decode_mips16_operand (type
, extended_p
);
13744 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13746 return (const struct mips_int_operand
*) operand
;
13749 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13752 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13753 bfd_reloc_code_real_type reloc
, offsetT sval
)
13755 int min_val
, max_val
;
13757 min_val
= mips_int_operand_min (operand
);
13758 max_val
= mips_int_operand_max (operand
);
13759 if (reloc
!= BFD_RELOC_UNUSED
)
13762 sval
= SEXT_16BIT (sval
);
13767 return (sval
>= min_val
13769 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13772 /* Install immediate value VAL into MIPS16 instruction *INSN,
13773 extending it if necessary. The instruction in *INSN may
13774 already be extended.
13776 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13777 if none. In the former case, VAL is a 16-bit number with no
13778 defined signedness.
13780 TYPE is the type of the immediate field. USER_INSN_LENGTH
13781 is the length that the user requested, or 0 if none. */
13784 mips16_immed (char *file
, unsigned int line
, int type
,
13785 bfd_reloc_code_real_type reloc
, offsetT val
,
13786 unsigned int user_insn_length
, unsigned long *insn
)
13788 const struct mips_int_operand
*operand
;
13789 unsigned int uval
, length
;
13791 operand
= mips16_immed_operand (type
, FALSE
);
13792 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13794 /* We need an extended instruction. */
13795 if (user_insn_length
== 2)
13796 as_bad_where (file
, line
, _("invalid unextended operand value"));
13798 *insn
|= MIPS16_EXTEND
;
13800 else if (user_insn_length
== 4)
13802 /* The operand doesn't force an unextended instruction to be extended.
13803 Warn if the user wanted an extended instruction anyway. */
13804 *insn
|= MIPS16_EXTEND
;
13805 as_warn_where (file
, line
,
13806 _("extended operand requested but not required"));
13809 length
= mips16_opcode_length (*insn
);
13812 operand
= mips16_immed_operand (type
, TRUE
);
13813 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13814 as_bad_where (file
, line
,
13815 _("operand value out of range for instruction"));
13817 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13819 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13821 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13824 struct percent_op_match
13827 bfd_reloc_code_real_type reloc
;
13830 static const struct percent_op_match mips_percent_op
[] =
13832 {"%lo", BFD_RELOC_LO16
},
13833 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13834 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13835 {"%call16", BFD_RELOC_MIPS_CALL16
},
13836 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13837 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13838 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13839 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13840 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13841 {"%got", BFD_RELOC_MIPS_GOT16
},
13842 {"%gp_rel", BFD_RELOC_GPREL16
},
13843 {"%half", BFD_RELOC_16
},
13844 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13845 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13846 {"%neg", BFD_RELOC_MIPS_SUB
},
13847 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13848 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13849 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13850 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13851 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13852 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13853 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13854 {"%hi", BFD_RELOC_HI16_S
},
13855 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
13856 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
13859 static const struct percent_op_match mips16_percent_op
[] =
13861 {"%lo", BFD_RELOC_MIPS16_LO16
},
13862 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13863 {"%got", BFD_RELOC_MIPS16_GOT16
},
13864 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13865 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13866 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13867 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13868 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13869 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13870 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13871 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13872 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13876 /* Return true if *STR points to a relocation operator. When returning true,
13877 move *STR over the operator and store its relocation code in *RELOC.
13878 Leave both *STR and *RELOC alone when returning false. */
13881 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13883 const struct percent_op_match
*percent_op
;
13886 if (mips_opts
.mips16
)
13888 percent_op
= mips16_percent_op
;
13889 limit
= ARRAY_SIZE (mips16_percent_op
);
13893 percent_op
= mips_percent_op
;
13894 limit
= ARRAY_SIZE (mips_percent_op
);
13897 for (i
= 0; i
< limit
; i
++)
13898 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13900 int len
= strlen (percent_op
[i
].str
);
13902 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13905 *str
+= strlen (percent_op
[i
].str
);
13906 *reloc
= percent_op
[i
].reloc
;
13908 /* Check whether the output BFD supports this relocation.
13909 If not, issue an error and fall back on something safe. */
13910 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13912 as_bad (_("relocation %s isn't supported by the current ABI"),
13913 percent_op
[i
].str
);
13914 *reloc
= BFD_RELOC_UNUSED
;
13922 /* Parse string STR as a 16-bit relocatable operand. Store the
13923 expression in *EP and the relocations in the array starting
13924 at RELOC. Return the number of relocation operators used.
13926 On exit, EXPR_END points to the first character after the expression. */
13929 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13932 bfd_reloc_code_real_type reversed_reloc
[3];
13933 size_t reloc_index
, i
;
13934 int crux_depth
, str_depth
;
13937 /* Search for the start of the main expression, recoding relocations
13938 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13939 of the main expression and with CRUX_DEPTH containing the number
13940 of open brackets at that point. */
13947 crux_depth
= str_depth
;
13949 /* Skip over whitespace and brackets, keeping count of the number
13951 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13956 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13957 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13959 my_getExpression (ep
, crux
);
13962 /* Match every open bracket. */
13963 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13967 if (crux_depth
> 0)
13968 as_bad (_("unclosed '('"));
13972 if (reloc_index
!= 0)
13974 prev_reloc_op_frag
= frag_now
;
13975 for (i
= 0; i
< reloc_index
; i
++)
13976 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13979 return reloc_index
;
13983 my_getExpression (expressionS
*ep
, char *str
)
13987 save_in
= input_line_pointer
;
13988 input_line_pointer
= str
;
13990 expr_end
= input_line_pointer
;
13991 input_line_pointer
= save_in
;
13995 md_atof (int type
, char *litP
, int *sizeP
)
13997 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14001 md_number_to_chars (char *buf
, valueT val
, int n
)
14003 if (target_big_endian
)
14004 number_to_chars_bigendian (buf
, val
, n
);
14006 number_to_chars_littleendian (buf
, val
, n
);
14009 static int support_64bit_objects(void)
14011 const char **list
, **l
;
14014 list
= bfd_target_list ();
14015 for (l
= list
; *l
!= NULL
; l
++)
14016 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14017 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14019 yes
= (*l
!= NULL
);
14024 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14025 NEW_VALUE. Warn if another value was already specified. Note:
14026 we have to defer parsing the -march and -mtune arguments in order
14027 to handle 'from-abi' correctly, since the ABI might be specified
14028 in a later argument. */
14031 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14033 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14034 as_warn (_("a different %s was already specified, is now %s"),
14035 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14038 *string_ptr
= new_value
;
14042 md_parse_option (int c
, char *arg
)
14046 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14047 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14049 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14050 c
== mips_ases
[i
].option_on
);
14056 case OPTION_CONSTRUCT_FLOATS
:
14057 mips_disable_float_construction
= 0;
14060 case OPTION_NO_CONSTRUCT_FLOATS
:
14061 mips_disable_float_construction
= 1;
14073 target_big_endian
= 1;
14077 target_big_endian
= 0;
14083 else if (arg
[0] == '0')
14085 else if (arg
[0] == '1')
14095 mips_debug
= atoi (arg
);
14099 file_mips_opts
.isa
= ISA_MIPS1
;
14103 file_mips_opts
.isa
= ISA_MIPS2
;
14107 file_mips_opts
.isa
= ISA_MIPS3
;
14111 file_mips_opts
.isa
= ISA_MIPS4
;
14115 file_mips_opts
.isa
= ISA_MIPS5
;
14118 case OPTION_MIPS32
:
14119 file_mips_opts
.isa
= ISA_MIPS32
;
14122 case OPTION_MIPS32R2
:
14123 file_mips_opts
.isa
= ISA_MIPS32R2
;
14126 case OPTION_MIPS32R3
:
14127 file_mips_opts
.isa
= ISA_MIPS32R3
;
14130 case OPTION_MIPS32R5
:
14131 file_mips_opts
.isa
= ISA_MIPS32R5
;
14134 case OPTION_MIPS32R6
:
14135 file_mips_opts
.isa
= ISA_MIPS32R6
;
14138 case OPTION_MIPS64R2
:
14139 file_mips_opts
.isa
= ISA_MIPS64R2
;
14142 case OPTION_MIPS64R3
:
14143 file_mips_opts
.isa
= ISA_MIPS64R3
;
14146 case OPTION_MIPS64R5
:
14147 file_mips_opts
.isa
= ISA_MIPS64R5
;
14150 case OPTION_MIPS64R6
:
14151 file_mips_opts
.isa
= ISA_MIPS64R6
;
14154 case OPTION_MIPS64
:
14155 file_mips_opts
.isa
= ISA_MIPS64
;
14159 mips_set_option_string (&mips_tune_string
, arg
);
14163 mips_set_option_string (&mips_arch_string
, arg
);
14167 mips_set_option_string (&mips_arch_string
, "4650");
14168 mips_set_option_string (&mips_tune_string
, "4650");
14171 case OPTION_NO_M4650
:
14175 mips_set_option_string (&mips_arch_string
, "4010");
14176 mips_set_option_string (&mips_tune_string
, "4010");
14179 case OPTION_NO_M4010
:
14183 mips_set_option_string (&mips_arch_string
, "4100");
14184 mips_set_option_string (&mips_tune_string
, "4100");
14187 case OPTION_NO_M4100
:
14191 mips_set_option_string (&mips_arch_string
, "3900");
14192 mips_set_option_string (&mips_tune_string
, "3900");
14195 case OPTION_NO_M3900
:
14198 case OPTION_MICROMIPS
:
14199 if (file_mips_opts
.mips16
== 1)
14201 as_bad (_("-mmicromips cannot be used with -mips16"));
14204 file_mips_opts
.micromips
= 1;
14205 mips_no_prev_insn ();
14208 case OPTION_NO_MICROMIPS
:
14209 file_mips_opts
.micromips
= 0;
14210 mips_no_prev_insn ();
14213 case OPTION_MIPS16
:
14214 if (file_mips_opts
.micromips
== 1)
14216 as_bad (_("-mips16 cannot be used with -micromips"));
14219 file_mips_opts
.mips16
= 1;
14220 mips_no_prev_insn ();
14223 case OPTION_NO_MIPS16
:
14224 file_mips_opts
.mips16
= 0;
14225 mips_no_prev_insn ();
14228 case OPTION_FIX_24K
:
14232 case OPTION_NO_FIX_24K
:
14236 case OPTION_FIX_RM7000
:
14237 mips_fix_rm7000
= 1;
14240 case OPTION_NO_FIX_RM7000
:
14241 mips_fix_rm7000
= 0;
14244 case OPTION_FIX_LOONGSON2F_JUMP
:
14245 mips_fix_loongson2f_jump
= TRUE
;
14248 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14249 mips_fix_loongson2f_jump
= FALSE
;
14252 case OPTION_FIX_LOONGSON2F_NOP
:
14253 mips_fix_loongson2f_nop
= TRUE
;
14256 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14257 mips_fix_loongson2f_nop
= FALSE
;
14260 case OPTION_FIX_VR4120
:
14261 mips_fix_vr4120
= 1;
14264 case OPTION_NO_FIX_VR4120
:
14265 mips_fix_vr4120
= 0;
14268 case OPTION_FIX_VR4130
:
14269 mips_fix_vr4130
= 1;
14272 case OPTION_NO_FIX_VR4130
:
14273 mips_fix_vr4130
= 0;
14276 case OPTION_FIX_CN63XXP1
:
14277 mips_fix_cn63xxp1
= TRUE
;
14280 case OPTION_NO_FIX_CN63XXP1
:
14281 mips_fix_cn63xxp1
= FALSE
;
14284 case OPTION_RELAX_BRANCH
:
14285 mips_relax_branch
= 1;
14288 case OPTION_NO_RELAX_BRANCH
:
14289 mips_relax_branch
= 0;
14292 case OPTION_INSN32
:
14293 file_mips_opts
.insn32
= TRUE
;
14296 case OPTION_NO_INSN32
:
14297 file_mips_opts
.insn32
= FALSE
;
14300 case OPTION_MSHARED
:
14301 mips_in_shared
= TRUE
;
14304 case OPTION_MNO_SHARED
:
14305 mips_in_shared
= FALSE
;
14308 case OPTION_MSYM32
:
14309 file_mips_opts
.sym32
= TRUE
;
14312 case OPTION_MNO_SYM32
:
14313 file_mips_opts
.sym32
= FALSE
;
14316 /* When generating ELF code, we permit -KPIC and -call_shared to
14317 select SVR4_PIC, and -non_shared to select no PIC. This is
14318 intended to be compatible with Irix 5. */
14319 case OPTION_CALL_SHARED
:
14320 mips_pic
= SVR4_PIC
;
14321 mips_abicalls
= TRUE
;
14324 case OPTION_CALL_NONPIC
:
14326 mips_abicalls
= TRUE
;
14329 case OPTION_NON_SHARED
:
14331 mips_abicalls
= FALSE
;
14334 /* The -xgot option tells the assembler to use 32 bit offsets
14335 when accessing the got in SVR4_PIC mode. It is for Irix
14342 g_switch_value
= atoi (arg
);
14346 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14349 mips_abi
= O32_ABI
;
14353 mips_abi
= N32_ABI
;
14357 mips_abi
= N64_ABI
;
14358 if (!support_64bit_objects())
14359 as_fatal (_("no compiled in support for 64 bit object file format"));
14363 file_mips_opts
.gp
= 32;
14367 file_mips_opts
.gp
= 64;
14371 file_mips_opts
.fp
= 32;
14375 file_mips_opts
.fp
= 0;
14379 file_mips_opts
.fp
= 64;
14382 case OPTION_ODD_SPREG
:
14383 file_mips_opts
.oddspreg
= 1;
14386 case OPTION_NO_ODD_SPREG
:
14387 file_mips_opts
.oddspreg
= 0;
14390 case OPTION_SINGLE_FLOAT
:
14391 file_mips_opts
.single_float
= 1;
14394 case OPTION_DOUBLE_FLOAT
:
14395 file_mips_opts
.single_float
= 0;
14398 case OPTION_SOFT_FLOAT
:
14399 file_mips_opts
.soft_float
= 1;
14402 case OPTION_HARD_FLOAT
:
14403 file_mips_opts
.soft_float
= 0;
14407 if (strcmp (arg
, "32") == 0)
14408 mips_abi
= O32_ABI
;
14409 else if (strcmp (arg
, "o64") == 0)
14410 mips_abi
= O64_ABI
;
14411 else if (strcmp (arg
, "n32") == 0)
14412 mips_abi
= N32_ABI
;
14413 else if (strcmp (arg
, "64") == 0)
14415 mips_abi
= N64_ABI
;
14416 if (! support_64bit_objects())
14417 as_fatal (_("no compiled in support for 64 bit object file "
14420 else if (strcmp (arg
, "eabi") == 0)
14421 mips_abi
= EABI_ABI
;
14424 as_fatal (_("invalid abi -mabi=%s"), arg
);
14429 case OPTION_M7000_HILO_FIX
:
14430 mips_7000_hilo_fix
= TRUE
;
14433 case OPTION_MNO_7000_HILO_FIX
:
14434 mips_7000_hilo_fix
= FALSE
;
14437 case OPTION_MDEBUG
:
14438 mips_flag_mdebug
= TRUE
;
14441 case OPTION_NO_MDEBUG
:
14442 mips_flag_mdebug
= FALSE
;
14446 mips_flag_pdr
= TRUE
;
14449 case OPTION_NO_PDR
:
14450 mips_flag_pdr
= FALSE
;
14453 case OPTION_MVXWORKS_PIC
:
14454 mips_pic
= VXWORKS_PIC
;
14458 if (strcmp (arg
, "2008") == 0)
14460 else if (strcmp (arg
, "legacy") == 0)
14464 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14473 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14478 /* Set up globals to tune for the ISA or processor described by INFO. */
14481 mips_set_tune (const struct mips_cpu_info
*info
)
14484 mips_tune
= info
->cpu
;
14489 mips_after_parse_args (void)
14491 const struct mips_cpu_info
*arch_info
= 0;
14492 const struct mips_cpu_info
*tune_info
= 0;
14494 /* GP relative stuff not working for PE */
14495 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14497 if (g_switch_seen
&& g_switch_value
!= 0)
14498 as_bad (_("-G not supported in this configuration"));
14499 g_switch_value
= 0;
14502 if (mips_abi
== NO_ABI
)
14503 mips_abi
= MIPS_DEFAULT_ABI
;
14505 /* The following code determines the architecture.
14506 Similar code was added to GCC 3.3 (see override_options() in
14507 config/mips/mips.c). The GAS and GCC code should be kept in sync
14508 as much as possible. */
14510 if (mips_arch_string
!= 0)
14511 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14513 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14515 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14516 ISA level specified by -mipsN, while arch_info->isa contains
14517 the -march selection (if any). */
14518 if (arch_info
!= 0)
14520 /* -march takes precedence over -mipsN, since it is more descriptive.
14521 There's no harm in specifying both as long as the ISA levels
14523 if (file_mips_opts
.isa
!= arch_info
->isa
)
14524 as_bad (_("-%s conflicts with the other architecture options,"
14525 " which imply -%s"),
14526 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14527 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14530 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14533 if (arch_info
== 0)
14535 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14536 gas_assert (arch_info
);
14539 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14540 as_bad (_("-march=%s is not compatible with the selected ABI"),
14543 file_mips_opts
.arch
= arch_info
->cpu
;
14544 file_mips_opts
.isa
= arch_info
->isa
;
14546 /* Set up initial mips_opts state. */
14547 mips_opts
= file_mips_opts
;
14549 /* The register size inference code is now placed in
14550 file_mips_check_options. */
14552 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14554 if (mips_tune_string
!= 0)
14555 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14557 if (tune_info
== 0)
14558 mips_set_tune (arch_info
);
14560 mips_set_tune (tune_info
);
14562 if (mips_flag_mdebug
< 0)
14563 mips_flag_mdebug
= 0;
14567 mips_init_after_args (void)
14569 /* initialize opcodes */
14570 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14571 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14575 md_pcrel_from (fixS
*fixP
)
14577 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14578 switch (fixP
->fx_r_type
)
14580 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14581 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14582 /* Return the address of the delay slot. */
14585 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14586 case BFD_RELOC_MICROMIPS_JMP
:
14587 case BFD_RELOC_16_PCREL_S2
:
14588 case BFD_RELOC_MIPS_21_PCREL_S2
:
14589 case BFD_RELOC_MIPS_26_PCREL_S2
:
14590 case BFD_RELOC_MIPS_JMP
:
14591 /* Return the address of the delay slot. */
14599 /* This is called before the symbol table is processed. In order to
14600 work with gcc when using mips-tfile, we must keep all local labels.
14601 However, in other cases, we want to discard them. If we were
14602 called with -g, but we didn't see any debugging information, it may
14603 mean that gcc is smuggling debugging information through to
14604 mips-tfile, in which case we must generate all local labels. */
14607 mips_frob_file_before_adjust (void)
14609 #ifndef NO_ECOFF_DEBUGGING
14610 if (ECOFF_DEBUGGING
14612 && ! ecoff_debugging_seen
)
14613 flag_keep_locals
= 1;
14617 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14618 the corresponding LO16 reloc. This is called before md_apply_fix and
14619 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14620 relocation operators.
14622 For our purposes, a %lo() expression matches a %got() or %hi()
14625 (a) it refers to the same symbol; and
14626 (b) the offset applied in the %lo() expression is no lower than
14627 the offset applied in the %got() or %hi().
14629 (b) allows us to cope with code like:
14632 lh $4,%lo(foo+2)($4)
14634 ...which is legal on RELA targets, and has a well-defined behaviour
14635 if the user knows that adding 2 to "foo" will not induce a carry to
14638 When several %lo()s match a particular %got() or %hi(), we use the
14639 following rules to distinguish them:
14641 (1) %lo()s with smaller offsets are a better match than %lo()s with
14644 (2) %lo()s with no matching %got() or %hi() are better than those
14645 that already have a matching %got() or %hi().
14647 (3) later %lo()s are better than earlier %lo()s.
14649 These rules are applied in order.
14651 (1) means, among other things, that %lo()s with identical offsets are
14652 chosen if they exist.
14654 (2) means that we won't associate several high-part relocations with
14655 the same low-part relocation unless there's no alternative. Having
14656 several high parts for the same low part is a GNU extension; this rule
14657 allows careful users to avoid it.
14659 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14660 with the last high-part relocation being at the front of the list.
14661 It therefore makes sense to choose the last matching low-part
14662 relocation, all other things being equal. It's also easier
14663 to code that way. */
14666 mips_frob_file (void)
14668 struct mips_hi_fixup
*l
;
14669 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14671 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14673 segment_info_type
*seginfo
;
14674 bfd_boolean matched_lo_p
;
14675 fixS
**hi_pos
, **lo_pos
, **pos
;
14677 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14679 /* If a GOT16 relocation turns out to be against a global symbol,
14680 there isn't supposed to be a matching LO. Ignore %gots against
14681 constants; we'll report an error for those later. */
14682 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14683 && !(l
->fixp
->fx_addsy
14684 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14687 /* Check quickly whether the next fixup happens to be a matching %lo. */
14688 if (fixup_has_matching_lo_p (l
->fixp
))
14691 seginfo
= seg_info (l
->seg
);
14693 /* Set HI_POS to the position of this relocation in the chain.
14694 Set LO_POS to the position of the chosen low-part relocation.
14695 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14696 relocation that matches an immediately-preceding high-part
14700 matched_lo_p
= FALSE
;
14701 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14703 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14705 if (*pos
== l
->fixp
)
14708 if ((*pos
)->fx_r_type
== looking_for_rtype
14709 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14710 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14712 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14714 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14717 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14718 && fixup_has_matching_lo_p (*pos
));
14721 /* If we found a match, remove the high-part relocation from its
14722 current position and insert it before the low-part relocation.
14723 Make the offsets match so that fixup_has_matching_lo_p()
14726 We don't warn about unmatched high-part relocations since some
14727 versions of gcc have been known to emit dead "lui ...%hi(...)"
14729 if (lo_pos
!= NULL
)
14731 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14732 if (l
->fixp
->fx_next
!= *lo_pos
)
14734 *hi_pos
= l
->fixp
->fx_next
;
14735 l
->fixp
->fx_next
= *lo_pos
;
14743 mips_force_relocation (fixS
*fixp
)
14745 if (generic_force_reloc (fixp
))
14748 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14749 so that the linker relaxation can update targets. */
14750 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14751 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14752 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14755 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14756 if (ISA_IS_R6 (mips_opts
.isa
)
14757 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14758 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14759 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
14760 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
14761 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
14762 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
14763 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
14769 /* Read the instruction associated with RELOC from BUF. */
14771 static unsigned int
14772 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14774 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14775 return read_compressed_insn (buf
, 4);
14777 return read_insn (buf
);
14780 /* Write instruction INSN to BUF, given that it has been relocated
14784 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14785 unsigned long insn
)
14787 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14788 write_compressed_insn (buf
, insn
, 4);
14790 write_insn (buf
, insn
);
14793 /* Apply a fixup to the object file. */
14796 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14799 unsigned long insn
;
14800 reloc_howto_type
*howto
;
14802 if (fixP
->fx_pcrel
)
14803 switch (fixP
->fx_r_type
)
14805 case BFD_RELOC_16_PCREL_S2
:
14806 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14807 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14808 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14809 case BFD_RELOC_32_PCREL
:
14810 case BFD_RELOC_MIPS_21_PCREL_S2
:
14811 case BFD_RELOC_MIPS_26_PCREL_S2
:
14812 case BFD_RELOC_MIPS_18_PCREL_S3
:
14813 case BFD_RELOC_MIPS_19_PCREL_S2
:
14814 case BFD_RELOC_HI16_S_PCREL
:
14815 case BFD_RELOC_LO16_PCREL
:
14819 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14824 _("PC-relative reference to a different section"));
14828 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14829 that have no MIPS ELF equivalent. */
14830 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14832 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14837 gas_assert (fixP
->fx_size
== 2
14838 || fixP
->fx_size
== 4
14839 || fixP
->fx_r_type
== BFD_RELOC_8
14840 || fixP
->fx_r_type
== BFD_RELOC_16
14841 || fixP
->fx_r_type
== BFD_RELOC_64
14842 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14843 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14844 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14845 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14846 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14847 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
14848 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
14850 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14852 /* Don't treat parts of a composite relocation as done. There are two
14855 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14856 should nevertheless be emitted if the first part is.
14858 (2) In normal usage, composite relocations are never assembly-time
14859 constants. The easiest way of dealing with the pathological
14860 exceptions is to generate a relocation against STN_UNDEF and
14861 leave everything up to the linker. */
14862 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14865 switch (fixP
->fx_r_type
)
14867 case BFD_RELOC_MIPS_TLS_GD
:
14868 case BFD_RELOC_MIPS_TLS_LDM
:
14869 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14870 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14871 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14872 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14873 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14874 case BFD_RELOC_MIPS_TLS_TPREL32
:
14875 case BFD_RELOC_MIPS_TLS_TPREL64
:
14876 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14877 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14878 case BFD_RELOC_MICROMIPS_TLS_GD
:
14879 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14880 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14881 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14882 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14883 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14884 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14885 case BFD_RELOC_MIPS16_TLS_GD
:
14886 case BFD_RELOC_MIPS16_TLS_LDM
:
14887 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14888 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14889 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14890 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14891 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14892 if (!fixP
->fx_addsy
)
14894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14895 _("TLS relocation against a constant"));
14898 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14901 case BFD_RELOC_MIPS_JMP
:
14902 case BFD_RELOC_MIPS_SHIFT5
:
14903 case BFD_RELOC_MIPS_SHIFT6
:
14904 case BFD_RELOC_MIPS_GOT_DISP
:
14905 case BFD_RELOC_MIPS_GOT_PAGE
:
14906 case BFD_RELOC_MIPS_GOT_OFST
:
14907 case BFD_RELOC_MIPS_SUB
:
14908 case BFD_RELOC_MIPS_INSERT_A
:
14909 case BFD_RELOC_MIPS_INSERT_B
:
14910 case BFD_RELOC_MIPS_DELETE
:
14911 case BFD_RELOC_MIPS_HIGHEST
:
14912 case BFD_RELOC_MIPS_HIGHER
:
14913 case BFD_RELOC_MIPS_SCN_DISP
:
14914 case BFD_RELOC_MIPS_REL16
:
14915 case BFD_RELOC_MIPS_RELGOT
:
14916 case BFD_RELOC_MIPS_JALR
:
14917 case BFD_RELOC_HI16
:
14918 case BFD_RELOC_HI16_S
:
14919 case BFD_RELOC_LO16
:
14920 case BFD_RELOC_GPREL16
:
14921 case BFD_RELOC_MIPS_LITERAL
:
14922 case BFD_RELOC_MIPS_CALL16
:
14923 case BFD_RELOC_MIPS_GOT16
:
14924 case BFD_RELOC_GPREL32
:
14925 case BFD_RELOC_MIPS_GOT_HI16
:
14926 case BFD_RELOC_MIPS_GOT_LO16
:
14927 case BFD_RELOC_MIPS_CALL_HI16
:
14928 case BFD_RELOC_MIPS_CALL_LO16
:
14929 case BFD_RELOC_MIPS16_GPREL
:
14930 case BFD_RELOC_MIPS16_GOT16
:
14931 case BFD_RELOC_MIPS16_CALL16
:
14932 case BFD_RELOC_MIPS16_HI16
:
14933 case BFD_RELOC_MIPS16_HI16_S
:
14934 case BFD_RELOC_MIPS16_LO16
:
14935 case BFD_RELOC_MIPS16_JMP
:
14936 case BFD_RELOC_MICROMIPS_JMP
:
14937 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14938 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14939 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14940 case BFD_RELOC_MICROMIPS_SUB
:
14941 case BFD_RELOC_MICROMIPS_HIGHEST
:
14942 case BFD_RELOC_MICROMIPS_HIGHER
:
14943 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14944 case BFD_RELOC_MICROMIPS_JALR
:
14945 case BFD_RELOC_MICROMIPS_HI16
:
14946 case BFD_RELOC_MICROMIPS_HI16_S
:
14947 case BFD_RELOC_MICROMIPS_LO16
:
14948 case BFD_RELOC_MICROMIPS_GPREL16
:
14949 case BFD_RELOC_MICROMIPS_LITERAL
:
14950 case BFD_RELOC_MICROMIPS_CALL16
:
14951 case BFD_RELOC_MICROMIPS_GOT16
:
14952 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14953 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14954 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14955 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14956 case BFD_RELOC_MIPS_EH
:
14961 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14963 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14964 if (mips16_reloc_p (fixP
->fx_r_type
))
14965 insn
|= mips16_immed_extend (value
, 16);
14967 insn
|= (value
& 0xffff);
14968 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14972 _("unsupported constant in relocation"));
14977 /* This is handled like BFD_RELOC_32, but we output a sign
14978 extended value if we are only 32 bits. */
14981 if (8 <= sizeof (valueT
))
14982 md_number_to_chars (buf
, *valP
, 8);
14987 if ((*valP
& 0x80000000) != 0)
14991 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14992 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14997 case BFD_RELOC_RVA
:
14999 case BFD_RELOC_32_PCREL
:
15002 /* If we are deleting this reloc entry, we must fill in the
15003 value now. This can happen if we have a .word which is not
15004 resolved when it appears but is later defined. */
15006 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15009 case BFD_RELOC_MIPS_21_PCREL_S2
:
15010 case BFD_RELOC_MIPS_26_PCREL_S2
:
15011 if ((*valP
& 0x3) != 0)
15012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15013 _("branch to misaligned address (%lx)"), (long) *valP
);
15015 gas_assert (!fixP
->fx_done
);
15018 case BFD_RELOC_MIPS_18_PCREL_S3
:
15019 if ((S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15021 _("PC-relative access using misaligned symbol (%lx)"),
15022 (long) S_GET_VALUE (fixP
->fx_addsy
));
15023 if ((fixP
->fx_offset
& 0x7) != 0)
15024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15025 _("PC-relative access using misaligned offset (%lx)"),
15026 (long) fixP
->fx_offset
);
15028 gas_assert (!fixP
->fx_done
);
15031 case BFD_RELOC_MIPS_19_PCREL_S2
:
15032 if ((*valP
& 0x3) != 0)
15033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15034 _("PC-relative access to misaligned address (%lx)"),
15035 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15037 gas_assert (!fixP
->fx_done
);
15040 case BFD_RELOC_HI16_S_PCREL
:
15041 case BFD_RELOC_LO16_PCREL
:
15042 gas_assert (!fixP
->fx_done
);
15045 case BFD_RELOC_16_PCREL_S2
:
15046 if ((*valP
& 0x3) != 0)
15047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15048 _("branch to misaligned address (%lx)"), (long) *valP
);
15050 /* We need to save the bits in the instruction since fixup_segment()
15051 might be deleting the relocation entry (i.e., a branch within
15052 the current segment). */
15053 if (! fixP
->fx_done
)
15056 /* Update old instruction data. */
15057 insn
= read_insn (buf
);
15059 if (*valP
+ 0x20000 <= 0x3ffff)
15061 insn
|= (*valP
>> 2) & 0xffff;
15062 write_insn (buf
, insn
);
15064 else if (mips_pic
== NO_PIC
15066 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15067 && (fixP
->fx_frag
->fr_address
15068 < text_section
->vma
+ bfd_get_section_size (text_section
))
15069 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15070 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15071 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15073 /* The branch offset is too large. If this is an
15074 unconditional branch, and we are not generating PIC code,
15075 we can convert it to an absolute jump instruction. */
15076 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15077 insn
= 0x0c000000; /* jal */
15079 insn
= 0x08000000; /* j */
15080 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15082 fixP
->fx_addsy
= section_symbol (text_section
);
15083 *valP
+= md_pcrel_from (fixP
);
15084 write_insn (buf
, insn
);
15088 /* If we got here, we have branch-relaxation disabled,
15089 and there's nothing we can do to fix this instruction
15090 without turning it into a longer sequence. */
15091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15092 _("branch out of range"));
15096 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15097 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15098 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15099 /* We adjust the offset back to even. */
15100 if ((*valP
& 0x1) != 0)
15103 if (! fixP
->fx_done
)
15106 /* Should never visit here, because we keep the relocation. */
15110 case BFD_RELOC_VTABLE_INHERIT
:
15113 && !S_IS_DEFINED (fixP
->fx_addsy
)
15114 && !S_IS_WEAK (fixP
->fx_addsy
))
15115 S_SET_WEAK (fixP
->fx_addsy
);
15118 case BFD_RELOC_NONE
:
15119 case BFD_RELOC_VTABLE_ENTRY
:
15127 /* Remember value for tc_gen_reloc. */
15128 fixP
->fx_addnumber
= *valP
;
15138 name
= input_line_pointer
;
15139 c
= get_symbol_end ();
15140 p
= (symbolS
*) symbol_find_or_make (name
);
15141 *input_line_pointer
= c
;
15145 /* Align the current frag to a given power of two. If a particular
15146 fill byte should be used, FILL points to an integer that contains
15147 that byte, otherwise FILL is null.
15149 This function used to have the comment:
15151 The MIPS assembler also automatically adjusts any preceding label.
15153 The implementation therefore applied the adjustment to a maximum of
15154 one label. However, other label adjustments are applied to batches
15155 of labels, and adjusting just one caused problems when new labels
15156 were added for the sake of debugging or unwind information.
15157 We therefore adjust all preceding labels (given as LABELS) instead. */
15160 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15162 mips_emit_delays ();
15163 mips_record_compressed_mode ();
15164 if (fill
== NULL
&& subseg_text_p (now_seg
))
15165 frag_align_code (to
, 0);
15167 frag_align (to
, fill
? *fill
: 0, 0);
15168 record_alignment (now_seg
, to
);
15169 mips_move_labels (labels
, FALSE
);
15172 /* Align to a given power of two. .align 0 turns off the automatic
15173 alignment used by the data creating pseudo-ops. */
15176 s_align (int x ATTRIBUTE_UNUSED
)
15178 int temp
, fill_value
, *fill_ptr
;
15179 long max_alignment
= 28;
15181 /* o Note that the assembler pulls down any immediately preceding label
15182 to the aligned address.
15183 o It's not documented but auto alignment is reinstated by
15184 a .align pseudo instruction.
15185 o Note also that after auto alignment is turned off the mips assembler
15186 issues an error on attempt to assemble an improperly aligned data item.
15189 temp
= get_absolute_expression ();
15190 if (temp
> max_alignment
)
15191 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15194 as_warn (_("alignment negative, 0 assumed"));
15197 if (*input_line_pointer
== ',')
15199 ++input_line_pointer
;
15200 fill_value
= get_absolute_expression ();
15201 fill_ptr
= &fill_value
;
15207 segment_info_type
*si
= seg_info (now_seg
);
15208 struct insn_label_list
*l
= si
->label_list
;
15209 /* Auto alignment should be switched on by next section change. */
15211 mips_align (temp
, fill_ptr
, l
);
15218 demand_empty_rest_of_line ();
15222 s_change_sec (int sec
)
15226 /* The ELF backend needs to know that we are changing sections, so
15227 that .previous works correctly. We could do something like check
15228 for an obj_section_change_hook macro, but that might be confusing
15229 as it would not be appropriate to use it in the section changing
15230 functions in read.c, since obj-elf.c intercepts those. FIXME:
15231 This should be cleaner, somehow. */
15232 obj_elf_section_change_hook ();
15234 mips_emit_delays ();
15245 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15246 demand_empty_rest_of_line ();
15250 seg
= subseg_new (RDATA_SECTION_NAME
,
15251 (subsegT
) get_absolute_expression ());
15252 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15253 | SEC_READONLY
| SEC_RELOC
15255 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15256 record_alignment (seg
, 4);
15257 demand_empty_rest_of_line ();
15261 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15262 bfd_set_section_flags (stdoutput
, seg
,
15263 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15264 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15265 record_alignment (seg
, 4);
15266 demand_empty_rest_of_line ();
15270 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15271 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15272 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15273 record_alignment (seg
, 4);
15274 demand_empty_rest_of_line ();
15282 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15284 char *section_name
;
15289 int section_entry_size
;
15290 int section_alignment
;
15292 section_name
= input_line_pointer
;
15293 c
= get_symbol_end ();
15295 next_c
= *(input_line_pointer
+ 1);
15297 /* Do we have .section Name<,"flags">? */
15298 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15300 /* just after name is now '\0'. */
15301 *input_line_pointer
= c
;
15302 input_line_pointer
= section_name
;
15303 obj_elf_section (ignore
);
15306 input_line_pointer
++;
15308 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15310 section_type
= get_absolute_expression ();
15313 if (*input_line_pointer
++ == ',')
15314 section_flag
= get_absolute_expression ();
15317 if (*input_line_pointer
++ == ',')
15318 section_entry_size
= get_absolute_expression ();
15320 section_entry_size
= 0;
15321 if (*input_line_pointer
++ == ',')
15322 section_alignment
= get_absolute_expression ();
15324 section_alignment
= 0;
15325 /* FIXME: really ignore? */
15326 (void) section_alignment
;
15328 section_name
= xstrdup (section_name
);
15330 /* When using the generic form of .section (as implemented by obj-elf.c),
15331 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15332 traditionally had to fall back on the more common @progbits instead.
15334 There's nothing really harmful in this, since bfd will correct
15335 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15336 means that, for backwards compatibility, the special_section entries
15337 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15339 Even so, we shouldn't force users of the MIPS .section syntax to
15340 incorrectly label the sections as SHT_PROGBITS. The best compromise
15341 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15342 generic type-checking code. */
15343 if (section_type
== SHT_MIPS_DWARF
)
15344 section_type
= SHT_PROGBITS
;
15346 obj_elf_change_section (section_name
, section_type
, section_flag
,
15347 section_entry_size
, 0, 0, 0);
15349 if (now_seg
->name
!= section_name
)
15350 free (section_name
);
15354 mips_enable_auto_align (void)
15360 s_cons (int log_size
)
15362 segment_info_type
*si
= seg_info (now_seg
);
15363 struct insn_label_list
*l
= si
->label_list
;
15365 mips_emit_delays ();
15366 if (log_size
> 0 && auto_align
)
15367 mips_align (log_size
, 0, l
);
15368 cons (1 << log_size
);
15369 mips_clear_insn_labels ();
15373 s_float_cons (int type
)
15375 segment_info_type
*si
= seg_info (now_seg
);
15376 struct insn_label_list
*l
= si
->label_list
;
15378 mips_emit_delays ();
15383 mips_align (3, 0, l
);
15385 mips_align (2, 0, l
);
15389 mips_clear_insn_labels ();
15392 /* Handle .globl. We need to override it because on Irix 5 you are
15395 where foo is an undefined symbol, to mean that foo should be
15396 considered to be the address of a function. */
15399 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15408 name
= input_line_pointer
;
15409 c
= get_symbol_end ();
15410 symbolP
= symbol_find_or_make (name
);
15411 S_SET_EXTERNAL (symbolP
);
15413 *input_line_pointer
= c
;
15414 SKIP_WHITESPACE ();
15416 /* On Irix 5, every global symbol that is not explicitly labelled as
15417 being a function is apparently labelled as being an object. */
15420 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15421 && (*input_line_pointer
!= ','))
15426 secname
= input_line_pointer
;
15427 c
= get_symbol_end ();
15428 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15430 as_bad (_("%s: no such section"), secname
);
15431 *input_line_pointer
= c
;
15433 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15434 flag
= BSF_FUNCTION
;
15437 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15439 c
= *input_line_pointer
;
15442 input_line_pointer
++;
15443 SKIP_WHITESPACE ();
15444 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15450 demand_empty_rest_of_line ();
15454 s_option (int x ATTRIBUTE_UNUSED
)
15459 opt
= input_line_pointer
;
15460 c
= get_symbol_end ();
15464 /* FIXME: What does this mean? */
15466 else if (strncmp (opt
, "pic", 3) == 0)
15470 i
= atoi (opt
+ 3);
15475 mips_pic
= SVR4_PIC
;
15476 mips_abicalls
= TRUE
;
15479 as_bad (_(".option pic%d not supported"), i
);
15481 if (mips_pic
== SVR4_PIC
)
15483 if (g_switch_seen
&& g_switch_value
!= 0)
15484 as_warn (_("-G may not be used with SVR4 PIC code"));
15485 g_switch_value
= 0;
15486 bfd_set_gp_size (stdoutput
, 0);
15490 as_warn (_("unrecognized option \"%s\""), opt
);
15492 *input_line_pointer
= c
;
15493 demand_empty_rest_of_line ();
15496 /* This structure is used to hold a stack of .set values. */
15498 struct mips_option_stack
15500 struct mips_option_stack
*next
;
15501 struct mips_set_options options
;
15504 static struct mips_option_stack
*mips_opts_stack
;
15507 parse_code_option (char * name
)
15509 const struct mips_ase
*ase
;
15510 if (strncmp (name
, "at=", 3) == 0)
15512 char *s
= name
+ 3;
15514 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15515 as_bad (_("unrecognized register name `%s'"), s
);
15517 else if (strcmp (name
, "at") == 0)
15518 mips_opts
.at
= ATREG
;
15519 else if (strcmp (name
, "noat") == 0)
15520 mips_opts
.at
= ZERO
;
15521 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15522 mips_opts
.nomove
= 0;
15523 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15524 mips_opts
.nomove
= 1;
15525 else if (strcmp (name
, "bopt") == 0)
15526 mips_opts
.nobopt
= 0;
15527 else if (strcmp (name
, "nobopt") == 0)
15528 mips_opts
.nobopt
= 1;
15529 else if (strcmp (name
, "gp=32") == 0)
15531 else if (strcmp (name
, "gp=64") == 0)
15533 else if (strcmp (name
, "fp=32") == 0)
15535 else if (strcmp (name
, "fp=xx") == 0)
15537 else if (strcmp (name
, "fp=64") == 0)
15539 else if (strcmp (name
, "softfloat") == 0)
15540 mips_opts
.soft_float
= 1;
15541 else if (strcmp (name
, "hardfloat") == 0)
15542 mips_opts
.soft_float
= 0;
15543 else if (strcmp (name
, "singlefloat") == 0)
15544 mips_opts
.single_float
= 1;
15545 else if (strcmp (name
, "doublefloat") == 0)
15546 mips_opts
.single_float
= 0;
15547 else if (strcmp (name
, "nooddspreg") == 0)
15548 mips_opts
.oddspreg
= 0;
15549 else if (strcmp (name
, "oddspreg") == 0)
15550 mips_opts
.oddspreg
= 1;
15551 else if (strcmp (name
, "mips16") == 0
15552 || strcmp (name
, "MIPS-16") == 0)
15553 mips_opts
.mips16
= 1;
15554 else if (strcmp (name
, "nomips16") == 0
15555 || strcmp (name
, "noMIPS-16") == 0)
15556 mips_opts
.mips16
= 0;
15557 else if (strcmp (name
, "micromips") == 0)
15558 mips_opts
.micromips
= 1;
15559 else if (strcmp (name
, "nomicromips") == 0)
15560 mips_opts
.micromips
= 0;
15561 else if (name
[0] == 'n'
15563 && (ase
= mips_lookup_ase (name
+ 2)))
15564 mips_set_ase (ase
, &mips_opts
, FALSE
);
15565 else if ((ase
= mips_lookup_ase (name
)))
15566 mips_set_ase (ase
, &mips_opts
, TRUE
);
15567 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15569 /* Permit the user to change the ISA and architecture on the fly.
15570 Needless to say, misuse can cause serious problems. */
15571 if (strncmp (name
, "arch=", 5) == 0)
15573 const struct mips_cpu_info
*p
;
15575 p
= mips_parse_cpu ("internal use", name
+ 5);
15577 as_bad (_("unknown architecture %s"), name
+ 5);
15580 mips_opts
.arch
= p
->cpu
;
15581 mips_opts
.isa
= p
->isa
;
15584 else if (strncmp (name
, "mips", 4) == 0)
15586 const struct mips_cpu_info
*p
;
15588 p
= mips_parse_cpu ("internal use", name
);
15590 as_bad (_("unknown ISA level %s"), name
+ 4);
15593 mips_opts
.arch
= p
->cpu
;
15594 mips_opts
.isa
= p
->isa
;
15598 as_bad (_("unknown ISA or architecture %s"), name
);
15600 else if (strcmp (name
, "autoextend") == 0)
15601 mips_opts
.noautoextend
= 0;
15602 else if (strcmp (name
, "noautoextend") == 0)
15603 mips_opts
.noautoextend
= 1;
15604 else if (strcmp (name
, "insn32") == 0)
15605 mips_opts
.insn32
= TRUE
;
15606 else if (strcmp (name
, "noinsn32") == 0)
15607 mips_opts
.insn32
= FALSE
;
15608 else if (strcmp (name
, "sym32") == 0)
15609 mips_opts
.sym32
= TRUE
;
15610 else if (strcmp (name
, "nosym32") == 0)
15611 mips_opts
.sym32
= FALSE
;
15617 /* Handle the .set pseudo-op. */
15620 s_mipsset (int x ATTRIBUTE_UNUSED
)
15622 char *name
= input_line_pointer
, ch
;
15623 int prev_isa
= mips_opts
.isa
;
15625 file_mips_check_options ();
15627 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15628 ++input_line_pointer
;
15629 ch
= *input_line_pointer
;
15630 *input_line_pointer
= '\0';
15632 if (strchr (name
, ','))
15634 /* Generic ".set" directive; use the generic handler. */
15635 *input_line_pointer
= ch
;
15636 input_line_pointer
= name
;
15641 if (strcmp (name
, "reorder") == 0)
15643 if (mips_opts
.noreorder
)
15646 else if (strcmp (name
, "noreorder") == 0)
15648 if (!mips_opts
.noreorder
)
15649 start_noreorder ();
15651 else if (strcmp (name
, "macro") == 0)
15652 mips_opts
.warn_about_macros
= 0;
15653 else if (strcmp (name
, "nomacro") == 0)
15655 if (mips_opts
.noreorder
== 0)
15656 as_bad (_("`noreorder' must be set before `nomacro'"));
15657 mips_opts
.warn_about_macros
= 1;
15659 else if (strcmp (name
, "gp=default") == 0)
15660 mips_opts
.gp
= file_mips_opts
.gp
;
15661 else if (strcmp (name
, "fp=default") == 0)
15662 mips_opts
.fp
= file_mips_opts
.fp
;
15663 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15665 mips_opts
.isa
= file_mips_opts
.isa
;
15666 mips_opts
.arch
= file_mips_opts
.arch
;
15667 mips_opts
.gp
= file_mips_opts
.gp
;
15668 mips_opts
.fp
= file_mips_opts
.fp
;
15670 else if (strcmp (name
, "push") == 0)
15672 struct mips_option_stack
*s
;
15674 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15675 s
->next
= mips_opts_stack
;
15676 s
->options
= mips_opts
;
15677 mips_opts_stack
= s
;
15679 else if (strcmp (name
, "pop") == 0)
15681 struct mips_option_stack
*s
;
15683 s
= mips_opts_stack
;
15685 as_bad (_(".set pop with no .set push"));
15688 /* If we're changing the reorder mode we need to handle
15689 delay slots correctly. */
15690 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15691 start_noreorder ();
15692 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15695 mips_opts
= s
->options
;
15696 mips_opts_stack
= s
->next
;
15700 else if (!parse_code_option (name
))
15701 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15703 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15704 registers based on what is supported by the arch/cpu. */
15705 if (mips_opts
.isa
!= prev_isa
)
15707 switch (mips_opts
.isa
)
15712 /* MIPS I cannot support FPXX. */
15714 /* fall-through. */
15721 if (mips_opts
.fp
!= 0)
15737 if (mips_opts
.fp
!= 0)
15739 if (mips_opts
.arch
== CPU_R5900
)
15746 as_bad (_("unknown ISA level %s"), name
+ 4);
15751 mips_check_options (&mips_opts
, FALSE
);
15753 mips_check_isa_supports_ases ();
15754 *input_line_pointer
= ch
;
15755 demand_empty_rest_of_line ();
15758 /* Handle the .module pseudo-op. */
15761 s_module (int ignore ATTRIBUTE_UNUSED
)
15763 char *name
= input_line_pointer
, ch
;
15765 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15766 ++input_line_pointer
;
15767 ch
= *input_line_pointer
;
15768 *input_line_pointer
= '\0';
15770 if (!file_mips_opts_checked
)
15772 if (!parse_code_option (name
))
15773 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
15775 /* Update module level settings from mips_opts. */
15776 file_mips_opts
= mips_opts
;
15779 as_bad (_(".module is not permitted after generating code"));
15781 *input_line_pointer
= ch
;
15782 demand_empty_rest_of_line ();
15785 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15786 .option pic2. It means to generate SVR4 PIC calls. */
15789 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15791 mips_pic
= SVR4_PIC
;
15792 mips_abicalls
= TRUE
;
15794 if (g_switch_seen
&& g_switch_value
!= 0)
15795 as_warn (_("-G may not be used with SVR4 PIC code"));
15796 g_switch_value
= 0;
15798 bfd_set_gp_size (stdoutput
, 0);
15799 demand_empty_rest_of_line ();
15802 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15803 PIC code. It sets the $gp register for the function based on the
15804 function address, which is in the register named in the argument.
15805 This uses a relocation against _gp_disp, which is handled specially
15806 by the linker. The result is:
15807 lui $gp,%hi(_gp_disp)
15808 addiu $gp,$gp,%lo(_gp_disp)
15809 addu $gp,$gp,.cpload argument
15810 The .cpload argument is normally $25 == $t9.
15812 The -mno-shared option changes this to:
15813 lui $gp,%hi(__gnu_local_gp)
15814 addiu $gp,$gp,%lo(__gnu_local_gp)
15815 and the argument is ignored. This saves an instruction, but the
15816 resulting code is not position independent; it uses an absolute
15817 address for __gnu_local_gp. Thus code assembled with -mno-shared
15818 can go into an ordinary executable, but not into a shared library. */
15821 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15827 file_mips_check_options ();
15829 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15830 .cpload is ignored. */
15831 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15837 if (mips_opts
.mips16
)
15839 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15840 ignore_rest_of_line ();
15844 /* .cpload should be in a .set noreorder section. */
15845 if (mips_opts
.noreorder
== 0)
15846 as_warn (_(".cpload not in noreorder section"));
15848 reg
= tc_get_register (0);
15850 /* If we need to produce a 64-bit address, we are better off using
15851 the default instruction sequence. */
15852 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15854 ex
.X_op
= O_symbol
;
15855 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15857 ex
.X_op_symbol
= NULL
;
15858 ex
.X_add_number
= 0;
15860 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15861 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15863 mips_mark_labels ();
15864 mips_assembling_insn
= TRUE
;
15867 macro_build_lui (&ex
, mips_gp_register
);
15868 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15869 mips_gp_register
, BFD_RELOC_LO16
);
15871 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15872 mips_gp_register
, reg
);
15875 mips_assembling_insn
= FALSE
;
15876 demand_empty_rest_of_line ();
15879 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15880 .cpsetup $reg1, offset|$reg2, label
15882 If offset is given, this results in:
15883 sd $gp, offset($sp)
15884 lui $gp, %hi(%neg(%gp_rel(label)))
15885 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15886 daddu $gp, $gp, $reg1
15888 If $reg2 is given, this results in:
15889 daddu $reg2, $gp, $0
15890 lui $gp, %hi(%neg(%gp_rel(label)))
15891 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15892 daddu $gp, $gp, $reg1
15893 $reg1 is normally $25 == $t9.
15895 The -mno-shared option replaces the last three instructions with
15897 addiu $gp,$gp,%lo(_gp) */
15900 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15902 expressionS ex_off
;
15903 expressionS ex_sym
;
15906 file_mips_check_options ();
15908 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15909 We also need NewABI support. */
15910 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15916 if (mips_opts
.mips16
)
15918 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15919 ignore_rest_of_line ();
15923 reg1
= tc_get_register (0);
15924 SKIP_WHITESPACE ();
15925 if (*input_line_pointer
!= ',')
15927 as_bad (_("missing argument separator ',' for .cpsetup"));
15931 ++input_line_pointer
;
15932 SKIP_WHITESPACE ();
15933 if (*input_line_pointer
== '$')
15935 mips_cpreturn_register
= tc_get_register (0);
15936 mips_cpreturn_offset
= -1;
15940 mips_cpreturn_offset
= get_absolute_expression ();
15941 mips_cpreturn_register
= -1;
15943 SKIP_WHITESPACE ();
15944 if (*input_line_pointer
!= ',')
15946 as_bad (_("missing argument separator ',' for .cpsetup"));
15950 ++input_line_pointer
;
15951 SKIP_WHITESPACE ();
15952 expression (&ex_sym
);
15954 mips_mark_labels ();
15955 mips_assembling_insn
= TRUE
;
15958 if (mips_cpreturn_register
== -1)
15960 ex_off
.X_op
= O_constant
;
15961 ex_off
.X_add_symbol
= NULL
;
15962 ex_off
.X_op_symbol
= NULL
;
15963 ex_off
.X_add_number
= mips_cpreturn_offset
;
15965 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15966 BFD_RELOC_LO16
, SP
);
15969 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15970 mips_gp_register
, 0);
15972 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15974 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15975 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15978 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15979 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15980 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15982 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15983 mips_gp_register
, reg1
);
15989 ex
.X_op
= O_symbol
;
15990 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15991 ex
.X_op_symbol
= NULL
;
15992 ex
.X_add_number
= 0;
15994 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15995 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15997 macro_build_lui (&ex
, mips_gp_register
);
15998 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15999 mips_gp_register
, BFD_RELOC_LO16
);
16004 mips_assembling_insn
= FALSE
;
16005 demand_empty_rest_of_line ();
16009 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16011 file_mips_check_options ();
16013 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16014 .cplocal is ignored. */
16015 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16021 if (mips_opts
.mips16
)
16023 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16024 ignore_rest_of_line ();
16028 mips_gp_register
= tc_get_register (0);
16029 demand_empty_rest_of_line ();
16032 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16033 offset from $sp. The offset is remembered, and after making a PIC
16034 call $gp is restored from that location. */
16037 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16041 file_mips_check_options ();
16043 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16044 .cprestore is ignored. */
16045 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16051 if (mips_opts
.mips16
)
16053 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16054 ignore_rest_of_line ();
16058 mips_cprestore_offset
= get_absolute_expression ();
16059 mips_cprestore_valid
= 1;
16061 ex
.X_op
= O_constant
;
16062 ex
.X_add_symbol
= NULL
;
16063 ex
.X_op_symbol
= NULL
;
16064 ex
.X_add_number
= mips_cprestore_offset
;
16066 mips_mark_labels ();
16067 mips_assembling_insn
= TRUE
;
16070 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16071 SP
, HAVE_64BIT_ADDRESSES
);
16074 mips_assembling_insn
= FALSE
;
16075 demand_empty_rest_of_line ();
16078 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16079 was given in the preceding .cpsetup, it results in:
16080 ld $gp, offset($sp)
16082 If a register $reg2 was given there, it results in:
16083 daddu $gp, $reg2, $0 */
16086 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16090 file_mips_check_options ();
16092 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16093 We also need NewABI support. */
16094 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16100 if (mips_opts
.mips16
)
16102 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16103 ignore_rest_of_line ();
16107 mips_mark_labels ();
16108 mips_assembling_insn
= TRUE
;
16111 if (mips_cpreturn_register
== -1)
16113 ex
.X_op
= O_constant
;
16114 ex
.X_add_symbol
= NULL
;
16115 ex
.X_op_symbol
= NULL
;
16116 ex
.X_add_number
= mips_cpreturn_offset
;
16118 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16121 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16122 mips_cpreturn_register
, 0);
16125 mips_assembling_insn
= FALSE
;
16126 demand_empty_rest_of_line ();
16129 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16130 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16131 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16132 debug information or MIPS16 TLS. */
16135 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16136 bfd_reloc_code_real_type rtype
)
16143 if (ex
.X_op
!= O_symbol
)
16145 as_bad (_("unsupported use of %s"), dirstr
);
16146 ignore_rest_of_line ();
16149 p
= frag_more (bytes
);
16150 md_number_to_chars (p
, 0, bytes
);
16151 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16152 demand_empty_rest_of_line ();
16153 mips_clear_insn_labels ();
16156 /* Handle .dtprelword. */
16159 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16161 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16164 /* Handle .dtpreldword. */
16167 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16169 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16172 /* Handle .tprelword. */
16175 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16177 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16180 /* Handle .tpreldword. */
16183 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16185 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16188 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16189 code. It sets the offset to use in gp_rel relocations. */
16192 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16194 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16195 We also need NewABI support. */
16196 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16202 mips_gprel_offset
= get_absolute_expression ();
16204 demand_empty_rest_of_line ();
16207 /* Handle the .gpword pseudo-op. This is used when generating PIC
16208 code. It generates a 32 bit GP relative reloc. */
16211 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16213 segment_info_type
*si
;
16214 struct insn_label_list
*l
;
16218 /* When not generating PIC code, this is treated as .word. */
16219 if (mips_pic
!= SVR4_PIC
)
16225 si
= seg_info (now_seg
);
16226 l
= si
->label_list
;
16227 mips_emit_delays ();
16229 mips_align (2, 0, l
);
16232 mips_clear_insn_labels ();
16234 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16236 as_bad (_("unsupported use of .gpword"));
16237 ignore_rest_of_line ();
16241 md_number_to_chars (p
, 0, 4);
16242 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16243 BFD_RELOC_GPREL32
);
16245 demand_empty_rest_of_line ();
16249 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16251 segment_info_type
*si
;
16252 struct insn_label_list
*l
;
16256 /* When not generating PIC code, this is treated as .dword. */
16257 if (mips_pic
!= SVR4_PIC
)
16263 si
= seg_info (now_seg
);
16264 l
= si
->label_list
;
16265 mips_emit_delays ();
16267 mips_align (3, 0, l
);
16270 mips_clear_insn_labels ();
16272 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16274 as_bad (_("unsupported use of .gpdword"));
16275 ignore_rest_of_line ();
16279 md_number_to_chars (p
, 0, 8);
16280 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16281 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16283 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16284 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16285 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16287 demand_empty_rest_of_line ();
16290 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16291 tables. It generates a R_MIPS_EH reloc. */
16294 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16299 mips_emit_delays ();
16302 mips_clear_insn_labels ();
16304 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16306 as_bad (_("unsupported use of .ehword"));
16307 ignore_rest_of_line ();
16311 md_number_to_chars (p
, 0, 4);
16312 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16313 BFD_RELOC_32_PCREL
);
16315 demand_empty_rest_of_line ();
16318 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16319 tables in SVR4 PIC code. */
16322 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16326 file_mips_check_options ();
16328 /* This is ignored when not generating SVR4 PIC code. */
16329 if (mips_pic
!= SVR4_PIC
)
16335 mips_mark_labels ();
16336 mips_assembling_insn
= TRUE
;
16338 /* Add $gp to the register named as an argument. */
16340 reg
= tc_get_register (0);
16341 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16344 mips_assembling_insn
= FALSE
;
16345 demand_empty_rest_of_line ();
16348 /* Handle the .insn pseudo-op. This marks instruction labels in
16349 mips16/micromips mode. This permits the linker to handle them specially,
16350 such as generating jalx instructions when needed. We also make
16351 them odd for the duration of the assembly, in order to generate the
16352 right sort of code. We will make them even in the adjust_symtab
16353 routine, while leaving them marked. This is convenient for the
16354 debugger and the disassembler. The linker knows to make them odd
16358 s_insn (int ignore ATTRIBUTE_UNUSED
)
16360 file_mips_check_options ();
16361 file_ase_mips16
|= mips_opts
.mips16
;
16362 file_ase_micromips
|= mips_opts
.micromips
;
16364 mips_mark_labels ();
16366 demand_empty_rest_of_line ();
16369 /* Handle the .nan pseudo-op. */
16372 s_nan (int ignore ATTRIBUTE_UNUSED
)
16374 static const char str_legacy
[] = "legacy";
16375 static const char str_2008
[] = "2008";
16378 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16380 if (i
== sizeof (str_2008
) - 1
16381 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16383 else if (i
== sizeof (str_legacy
) - 1
16384 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16386 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16389 as_bad (_("`%s' does not support legacy NaN"),
16390 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16393 as_bad (_("bad .nan directive"));
16395 input_line_pointer
+= i
;
16396 demand_empty_rest_of_line ();
16399 /* Handle a .stab[snd] directive. Ideally these directives would be
16400 implemented in a transparent way, so that removing them would not
16401 have any effect on the generated instructions. However, s_stab
16402 internally changes the section, so in practice we need to decide
16403 now whether the preceding label marks compressed code. We do not
16404 support changing the compression mode of a label after a .stab*
16405 directive, such as in:
16411 so the current mode wins. */
16414 s_mips_stab (int type
)
16416 mips_mark_labels ();
16420 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16423 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16430 name
= input_line_pointer
;
16431 c
= get_symbol_end ();
16432 symbolP
= symbol_find_or_make (name
);
16433 S_SET_WEAK (symbolP
);
16434 *input_line_pointer
= c
;
16436 SKIP_WHITESPACE ();
16438 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16440 if (S_IS_DEFINED (symbolP
))
16442 as_bad (_("ignoring attempt to redefine symbol %s"),
16443 S_GET_NAME (symbolP
));
16444 ignore_rest_of_line ();
16448 if (*input_line_pointer
== ',')
16450 ++input_line_pointer
;
16451 SKIP_WHITESPACE ();
16455 if (exp
.X_op
!= O_symbol
)
16457 as_bad (_("bad .weakext directive"));
16458 ignore_rest_of_line ();
16461 symbol_set_value_expression (symbolP
, &exp
);
16464 demand_empty_rest_of_line ();
16467 /* Parse a register string into a number. Called from the ECOFF code
16468 to parse .frame. The argument is non-zero if this is the frame
16469 register, so that we can record it in mips_frame_reg. */
16472 tc_get_register (int frame
)
16476 SKIP_WHITESPACE ();
16477 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16481 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16482 mips_frame_reg_valid
= 1;
16483 mips_cprestore_valid
= 0;
16489 md_section_align (asection
*seg
, valueT addr
)
16491 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16493 /* We don't need to align ELF sections to the full alignment.
16494 However, Irix 5 may prefer that we align them at least to a 16
16495 byte boundary. We don't bother to align the sections if we
16496 are targeted for an embedded system. */
16497 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16502 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16505 /* Utility routine, called from above as well. If called while the
16506 input file is still being read, it's only an approximation. (For
16507 example, a symbol may later become defined which appeared to be
16508 undefined earlier.) */
16511 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16516 if (g_switch_value
> 0)
16518 const char *symname
;
16521 /* Find out whether this symbol can be referenced off the $gp
16522 register. It can be if it is smaller than the -G size or if
16523 it is in the .sdata or .sbss section. Certain symbols can
16524 not be referenced off the $gp, although it appears as though
16526 symname
= S_GET_NAME (sym
);
16527 if (symname
!= (const char *) NULL
16528 && (strcmp (symname
, "eprol") == 0
16529 || strcmp (symname
, "etext") == 0
16530 || strcmp (symname
, "_gp") == 0
16531 || strcmp (symname
, "edata") == 0
16532 || strcmp (symname
, "_fbss") == 0
16533 || strcmp (symname
, "_fdata") == 0
16534 || strcmp (symname
, "_ftext") == 0
16535 || strcmp (symname
, "end") == 0
16536 || strcmp (symname
, "_gp_disp") == 0))
16538 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16540 #ifndef NO_ECOFF_DEBUGGING
16541 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16542 && (symbol_get_obj (sym
)->ecoff_extern_size
16543 <= g_switch_value
))
16545 /* We must defer this decision until after the whole
16546 file has been read, since there might be a .extern
16547 after the first use of this symbol. */
16548 || (before_relaxing
16549 #ifndef NO_ECOFF_DEBUGGING
16550 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16552 && S_GET_VALUE (sym
) == 0)
16553 || (S_GET_VALUE (sym
) != 0
16554 && S_GET_VALUE (sym
) <= g_switch_value
)))
16558 const char *segname
;
16560 segname
= segment_name (S_GET_SEGMENT (sym
));
16561 gas_assert (strcmp (segname
, ".lit8") != 0
16562 && strcmp (segname
, ".lit4") != 0);
16563 change
= (strcmp (segname
, ".sdata") != 0
16564 && strcmp (segname
, ".sbss") != 0
16565 && strncmp (segname
, ".sdata.", 7) != 0
16566 && strncmp (segname
, ".sbss.", 6) != 0
16567 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16568 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16573 /* We are not optimizing for the $gp register. */
16578 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16581 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16585 /* Handle the case of a symbol equated to another symbol. */
16586 while (symbol_equated_reloc_p (sym
))
16590 /* It's possible to get a loop here in a badly written program. */
16591 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16597 if (symbol_section_p (sym
))
16600 symsec
= S_GET_SEGMENT (sym
);
16602 /* This must duplicate the test in adjust_reloc_syms. */
16603 return (!bfd_is_und_section (symsec
)
16604 && !bfd_is_abs_section (symsec
)
16605 && !bfd_is_com_section (symsec
)
16606 && !s_is_linkonce (sym
, segtype
)
16607 /* A global or weak symbol is treated as external. */
16608 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16612 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16613 extended opcode. SEC is the section the frag is in. */
16616 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16619 const struct mips_int_operand
*operand
;
16624 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16626 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16629 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16630 operand
= mips16_immed_operand (type
, FALSE
);
16632 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16633 val
= S_GET_VALUE (fragp
->fr_symbol
);
16634 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16636 if (operand
->root
.type
== OP_PCREL
)
16638 const struct mips_pcrel_operand
*pcrel_op
;
16642 /* We won't have the section when we are called from
16643 mips_relax_frag. However, we will always have been called
16644 from md_estimate_size_before_relax first. If this is a
16645 branch to a different section, we mark it as such. If SEC is
16646 NULL, and the frag is not marked, then it must be a branch to
16647 the same section. */
16648 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16651 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16656 /* Must have been called from md_estimate_size_before_relax. */
16659 fragp
->fr_subtype
=
16660 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16662 /* FIXME: We should support this, and let the linker
16663 catch branches and loads that are out of range. */
16664 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16665 _("unsupported PC relative reference to different section"));
16669 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16670 /* Assume non-extended on the first relaxation pass.
16671 The address we have calculated will be bogus if this is
16672 a forward branch to another frag, as the forward frag
16673 will have fr_address == 0. */
16677 /* In this case, we know for sure that the symbol fragment is in
16678 the same section. If the relax_marker of the symbol fragment
16679 differs from the relax_marker of this fragment, we have not
16680 yet adjusted the symbol fragment fr_address. We want to add
16681 in STRETCH in order to get a better estimate of the address.
16682 This particularly matters because of the shift bits. */
16684 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16688 /* Adjust stretch for any alignment frag. Note that if have
16689 been expanding the earlier code, the symbol may be
16690 defined in what appears to be an earlier frag. FIXME:
16691 This doesn't handle the fr_subtype field, which specifies
16692 a maximum number of bytes to skip when doing an
16694 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16696 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16699 stretch
= - ((- stretch
)
16700 & ~ ((1 << (int) f
->fr_offset
) - 1));
16702 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16711 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16713 /* The base address rules are complicated. The base address of
16714 a branch is the following instruction. The base address of a
16715 PC relative load or add is the instruction itself, but if it
16716 is in a delay slot (in which case it can not be extended) use
16717 the address of the instruction whose delay slot it is in. */
16718 if (pcrel_op
->include_isa_bit
)
16722 /* If we are currently assuming that this frag should be
16723 extended, then, the current address is two bytes
16725 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16728 /* Ignore the low bit in the target, since it will be set
16729 for a text label. */
16732 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16734 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16737 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16739 /* If any of the shifted bits are set, we must use an extended
16740 opcode. If the address depends on the size of this
16741 instruction, this can lead to a loop, so we arrange to always
16742 use an extended opcode. We only check this when we are in
16743 the main relaxation loop, when SEC is NULL. */
16744 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16746 fragp
->fr_subtype
=
16747 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16751 /* If we are about to mark a frag as extended because the value
16752 is precisely the next value above maxtiny, then there is a
16753 chance of an infinite loop as in the following code:
16758 In this case when the la is extended, foo is 0x3fc bytes
16759 away, so the la can be shrunk, but then foo is 0x400 away, so
16760 the la must be extended. To avoid this loop, we mark the
16761 frag as extended if it was small, and is about to become
16762 extended with the next value above maxtiny. */
16763 maxtiny
= mips_int_operand_max (operand
);
16764 if (val
== maxtiny
+ (1 << operand
->shift
)
16765 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16768 fragp
->fr_subtype
=
16769 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16773 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16774 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16776 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16779 /* Compute the length of a branch sequence, and adjust the
16780 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16781 worst-case length is computed, with UPDATE being used to indicate
16782 whether an unconditional (-1), branch-likely (+1) or regular (0)
16783 branch is to be computed. */
16785 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16787 bfd_boolean toofar
;
16791 && S_IS_DEFINED (fragp
->fr_symbol
)
16792 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16797 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16799 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16803 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16806 /* If the symbol is not defined or it's in a different segment,
16807 assume the user knows what's going on and emit a short
16813 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16815 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16816 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16817 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16818 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16824 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16827 if (mips_pic
!= NO_PIC
)
16829 /* Additional space for PIC loading of target address. */
16831 if (mips_opts
.isa
== ISA_MIPS1
)
16832 /* Additional space for $at-stabilizing nop. */
16836 /* If branch is conditional. */
16837 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16844 /* Compute the length of a branch sequence, and adjust the
16845 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16846 worst-case length is computed, with UPDATE being used to indicate
16847 whether an unconditional (-1), or regular (0) branch is to be
16851 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16853 bfd_boolean toofar
;
16857 && S_IS_DEFINED (fragp
->fr_symbol
)
16858 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16863 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16864 /* Ignore the low bit in the target, since it will be set
16865 for a text label. */
16866 if ((val
& 1) != 0)
16869 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16873 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16876 /* If the symbol is not defined or it's in a different segment,
16877 assume the user knows what's going on and emit a short
16883 if (fragp
&& update
16884 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16885 fragp
->fr_subtype
= (toofar
16886 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16887 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16892 bfd_boolean compact_known
= fragp
!= NULL
;
16893 bfd_boolean compact
= FALSE
;
16894 bfd_boolean uncond
;
16897 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16899 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16901 uncond
= update
< 0;
16903 /* If label is out of range, we turn branch <br>:
16905 <br> label # 4 bytes
16911 nop # 2 bytes if compact && !PIC
16914 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16917 /* If assembling PIC code, we further turn:
16923 lw/ld at, %got(label)(gp) # 4 bytes
16924 d/addiu at, %lo(label) # 4 bytes
16927 if (mips_pic
!= NO_PIC
)
16930 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16932 <brneg> 0f # 4 bytes
16933 nop # 2 bytes if !compact
16936 length
+= (compact_known
&& compact
) ? 4 : 6;
16942 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16943 bit accordingly. */
16946 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16948 bfd_boolean toofar
;
16951 && S_IS_DEFINED (fragp
->fr_symbol
)
16952 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16958 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16959 /* Ignore the low bit in the target, since it will be set
16960 for a text label. */
16961 if ((val
& 1) != 0)
16964 /* Assume this is a 2-byte branch. */
16965 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16967 /* We try to avoid the infinite loop by not adding 2 more bytes for
16972 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16974 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16975 else if (type
== 'E')
16976 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16981 /* If the symbol is not defined or it's in a different segment,
16982 we emit a normal 32-bit branch. */
16985 if (fragp
&& update
16986 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16988 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16989 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16997 /* Estimate the size of a frag before relaxing. Unless this is the
16998 mips16, we are not really relaxing here, and the final size is
16999 encoded in the subtype information. For the mips16, we have to
17000 decide whether we are using an extended opcode or not. */
17003 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17007 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17010 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17012 return fragp
->fr_var
;
17015 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17016 /* We don't want to modify the EXTENDED bit here; it might get us
17017 into infinite loops. We change it only in mips_relax_frag(). */
17018 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17020 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17024 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17025 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17026 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17027 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17028 fragp
->fr_var
= length
;
17033 if (mips_pic
== NO_PIC
)
17034 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17035 else if (mips_pic
== SVR4_PIC
)
17036 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17037 else if (mips_pic
== VXWORKS_PIC
)
17038 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17045 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17046 return -RELAX_FIRST (fragp
->fr_subtype
);
17049 return -RELAX_SECOND (fragp
->fr_subtype
);
17052 /* This is called to see whether a reloc against a defined symbol
17053 should be converted into a reloc against a section. */
17056 mips_fix_adjustable (fixS
*fixp
)
17058 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17059 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17062 if (fixp
->fx_addsy
== NULL
)
17065 /* Allow relocs used for EH tables. */
17066 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17069 /* If symbol SYM is in a mergeable section, relocations of the form
17070 SYM + 0 can usually be made section-relative. The mergeable data
17071 is then identified by the section offset rather than by the symbol.
17073 However, if we're generating REL LO16 relocations, the offset is split
17074 between the LO16 and parterning high part relocation. The linker will
17075 need to recalculate the complete offset in order to correctly identify
17078 The linker has traditionally not looked for the parterning high part
17079 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17080 placed anywhere. Rather than break backwards compatibility by changing
17081 this, it seems better not to force the issue, and instead keep the
17082 original symbol. This will work with either linker behavior. */
17083 if ((lo16_reloc_p (fixp
->fx_r_type
)
17084 || reloc_needs_lo_p (fixp
->fx_r_type
))
17085 && HAVE_IN_PLACE_ADDENDS
17086 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17089 /* There is no place to store an in-place offset for JALR relocations.
17090 Likewise an in-range offset of limited PC-relative relocations may
17091 overflow the in-place relocatable field if recalculated against the
17092 start address of the symbol's containing section.
17094 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17095 section relative to allow linker relaxations to be performed later on. */
17096 if ((HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (mips_opts
.isa
))
17097 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17098 || jalr_reloc_p (fixp
->fx_r_type
)))
17101 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17102 to a floating-point stub. The same is true for non-R_MIPS16_26
17103 relocations against MIPS16 functions; in this case, the stub becomes
17104 the function's canonical address.
17106 Floating-point stubs are stored in unique .mips16.call.* or
17107 .mips16.fn.* sections. If a stub T for function F is in section S,
17108 the first relocation in section S must be against F; this is how the
17109 linker determines the target function. All relocations that might
17110 resolve to T must also be against F. We therefore have the following
17111 restrictions, which are given in an intentionally-redundant way:
17113 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17116 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17117 if that stub might be used.
17119 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17122 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17123 that stub might be used.
17125 There is a further restriction:
17127 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17128 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17129 targets with in-place addends; the relocation field cannot
17130 encode the low bit.
17132 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17133 against a MIPS16 symbol. We deal with (5) by by not reducing any
17134 such relocations on REL targets.
17136 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17137 relocation against some symbol R, no relocation against R may be
17138 reduced. (Note that this deals with (2) as well as (1) because
17139 relocations against global symbols will never be reduced on ELF
17140 targets.) This approach is a little simpler than trying to detect
17141 stub sections, and gives the "all or nothing" per-symbol consistency
17142 that we have for MIPS16 symbols. */
17143 if (fixp
->fx_subsy
== NULL
17144 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17145 || *symbol_get_tc (fixp
->fx_addsy
)
17146 || (HAVE_IN_PLACE_ADDENDS
17147 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17148 && jmp_reloc_p (fixp
->fx_r_type
))))
17154 /* Translate internal representation of relocation info to BFD target
17158 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17160 static arelent
*retval
[4];
17162 bfd_reloc_code_real_type code
;
17164 memset (retval
, 0, sizeof(retval
));
17165 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17166 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17167 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17168 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17170 if (fixp
->fx_pcrel
)
17172 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17173 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17174 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17175 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17176 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17177 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17178 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17179 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17180 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17181 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17182 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17184 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17185 Relocations want only the symbol offset. */
17186 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17189 reloc
->addend
= fixp
->fx_addnumber
;
17191 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17192 entry to be used in the relocation's section offset. */
17193 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17195 reloc
->address
= reloc
->addend
;
17199 code
= fixp
->fx_r_type
;
17201 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17202 if (reloc
->howto
== NULL
)
17204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17205 _("cannot represent %s relocation in this object file"
17207 bfd_get_reloc_code_name (code
));
17214 /* Relax a machine dependent frag. This returns the amount by which
17215 the current size of the frag should change. */
17218 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17220 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17222 offsetT old_var
= fragp
->fr_var
;
17224 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17226 return fragp
->fr_var
- old_var
;
17229 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17231 offsetT old_var
= fragp
->fr_var
;
17232 offsetT new_var
= 4;
17234 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17235 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17236 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17237 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17238 fragp
->fr_var
= new_var
;
17240 return new_var
- old_var
;
17243 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17246 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17248 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17250 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17255 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17257 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17264 /* Convert a machine dependent frag. */
17267 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17269 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17272 unsigned long insn
;
17276 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17277 insn
= read_insn (buf
);
17279 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17281 /* We generate a fixup instead of applying it right now
17282 because, if there are linker relaxations, we're going to
17283 need the relocations. */
17284 exp
.X_op
= O_symbol
;
17285 exp
.X_add_symbol
= fragp
->fr_symbol
;
17286 exp
.X_add_number
= fragp
->fr_offset
;
17288 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17289 BFD_RELOC_16_PCREL_S2
);
17290 fixp
->fx_file
= fragp
->fr_file
;
17291 fixp
->fx_line
= fragp
->fr_line
;
17293 buf
= write_insn (buf
, insn
);
17299 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17300 _("relaxed out-of-range branch into a jump"));
17302 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17305 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17307 /* Reverse the branch. */
17308 switch ((insn
>> 28) & 0xf)
17311 if ((insn
& 0xff000000) == 0x47000000
17312 || (insn
& 0xff600000) == 0x45600000)
17314 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17315 reversed by tweaking bit 23. */
17316 insn
^= 0x00800000;
17320 /* bc[0-3][tf]l? instructions can have the condition
17321 reversed by tweaking a single TF bit, and their
17322 opcodes all have 0x4???????. */
17323 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17324 insn
^= 0x00010000;
17329 /* bltz 0x04000000 bgez 0x04010000
17330 bltzal 0x04100000 bgezal 0x04110000 */
17331 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17332 insn
^= 0x00010000;
17336 /* beq 0x10000000 bne 0x14000000
17337 blez 0x18000000 bgtz 0x1c000000 */
17338 insn
^= 0x04000000;
17346 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17348 /* Clear the and-link bit. */
17349 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17351 /* bltzal 0x04100000 bgezal 0x04110000
17352 bltzall 0x04120000 bgezall 0x04130000 */
17353 insn
&= ~0x00100000;
17356 /* Branch over the branch (if the branch was likely) or the
17357 full jump (not likely case). Compute the offset from the
17358 current instruction to branch to. */
17359 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17363 /* How many bytes in instructions we've already emitted? */
17364 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17365 /* How many bytes in instructions from here to the end? */
17366 i
= fragp
->fr_var
- i
;
17368 /* Convert to instruction count. */
17370 /* Branch counts from the next instruction. */
17373 /* Branch over the jump. */
17374 buf
= write_insn (buf
, insn
);
17377 buf
= write_insn (buf
, 0);
17379 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17381 /* beql $0, $0, 2f */
17383 /* Compute the PC offset from the current instruction to
17384 the end of the variable frag. */
17385 /* How many bytes in instructions we've already emitted? */
17386 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17387 /* How many bytes in instructions from here to the end? */
17388 i
= fragp
->fr_var
- i
;
17389 /* Convert to instruction count. */
17391 /* Don't decrement i, because we want to branch over the
17395 buf
= write_insn (buf
, insn
);
17396 buf
= write_insn (buf
, 0);
17400 if (mips_pic
== NO_PIC
)
17403 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17404 ? 0x0c000000 : 0x08000000);
17405 exp
.X_op
= O_symbol
;
17406 exp
.X_add_symbol
= fragp
->fr_symbol
;
17407 exp
.X_add_number
= fragp
->fr_offset
;
17409 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17410 FALSE
, BFD_RELOC_MIPS_JMP
);
17411 fixp
->fx_file
= fragp
->fr_file
;
17412 fixp
->fx_line
= fragp
->fr_line
;
17414 buf
= write_insn (buf
, insn
);
17418 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17420 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17421 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17422 insn
|= at
<< OP_SH_RT
;
17423 exp
.X_op
= O_symbol
;
17424 exp
.X_add_symbol
= fragp
->fr_symbol
;
17425 exp
.X_add_number
= fragp
->fr_offset
;
17427 if (fragp
->fr_offset
)
17429 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17430 exp
.X_add_number
= 0;
17433 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17434 FALSE
, BFD_RELOC_MIPS_GOT16
);
17435 fixp
->fx_file
= fragp
->fr_file
;
17436 fixp
->fx_line
= fragp
->fr_line
;
17438 buf
= write_insn (buf
, insn
);
17440 if (mips_opts
.isa
== ISA_MIPS1
)
17442 buf
= write_insn (buf
, 0);
17444 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17445 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17446 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17448 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17449 FALSE
, BFD_RELOC_LO16
);
17450 fixp
->fx_file
= fragp
->fr_file
;
17451 fixp
->fx_line
= fragp
->fr_line
;
17453 buf
= write_insn (buf
, insn
);
17456 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17460 insn
|= at
<< OP_SH_RS
;
17462 buf
= write_insn (buf
, insn
);
17466 fragp
->fr_fix
+= fragp
->fr_var
;
17467 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17471 /* Relax microMIPS branches. */
17472 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17474 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17475 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17476 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17477 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17478 bfd_boolean short_ds
;
17479 unsigned long insn
;
17483 exp
.X_op
= O_symbol
;
17484 exp
.X_add_symbol
= fragp
->fr_symbol
;
17485 exp
.X_add_number
= fragp
->fr_offset
;
17487 fragp
->fr_fix
+= fragp
->fr_var
;
17489 /* Handle 16-bit branches that fit or are forced to fit. */
17490 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17492 /* We generate a fixup instead of applying it right now,
17493 because if there is linker relaxation, we're going to
17494 need the relocations. */
17496 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17497 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17498 else if (type
== 'E')
17499 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17500 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17504 fixp
->fx_file
= fragp
->fr_file
;
17505 fixp
->fx_line
= fragp
->fr_line
;
17507 /* These relocations can have an addend that won't fit in
17509 fixp
->fx_no_overflow
= 1;
17514 /* Handle 32-bit branches that fit or are forced to fit. */
17515 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17516 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17518 /* We generate a fixup instead of applying it right now,
17519 because if there is linker relaxation, we're going to
17520 need the relocations. */
17521 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17522 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17523 fixp
->fx_file
= fragp
->fr_file
;
17524 fixp
->fx_line
= fragp
->fr_line
;
17530 /* Relax 16-bit branches to 32-bit branches. */
17533 insn
= read_compressed_insn (buf
, 2);
17535 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17536 insn
= 0x94000000; /* beq */
17537 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17539 unsigned long regno
;
17541 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17542 regno
= micromips_to_32_reg_d_map
[regno
];
17543 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17544 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17549 /* Nothing else to do, just write it out. */
17550 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17551 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17553 buf
= write_compressed_insn (buf
, insn
, 4);
17554 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17559 insn
= read_compressed_insn (buf
, 4);
17561 /* Relax 32-bit branches to a sequence of instructions. */
17562 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17563 _("relaxed out-of-range branch into a jump"));
17565 /* Set the short-delay-slot bit. */
17566 short_ds
= al
&& (insn
& 0x02000000) != 0;
17568 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17572 /* Reverse the branch. */
17573 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17574 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17575 insn
^= 0x20000000;
17576 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17577 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17578 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17579 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17580 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17581 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17582 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17583 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17584 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17585 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17586 insn
^= 0x00400000;
17587 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17588 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17589 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17590 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17591 insn
^= 0x00200000;
17592 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17594 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17596 insn
^= 0x00800000;
17602 /* Clear the and-link and short-delay-slot bits. */
17603 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17605 /* bltzal 0x40200000 bgezal 0x40600000 */
17606 /* bltzals 0x42200000 bgezals 0x42600000 */
17607 insn
&= ~0x02200000;
17610 /* Make a label at the end for use with the branch. */
17611 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17612 micromips_label_inc ();
17613 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17616 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17617 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17618 fixp
->fx_file
= fragp
->fr_file
;
17619 fixp
->fx_line
= fragp
->fr_line
;
17621 /* Branch over the jump. */
17622 buf
= write_compressed_insn (buf
, insn
, 4);
17625 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17628 if (mips_pic
== NO_PIC
)
17630 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17632 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17633 insn
= al
? jal
: 0xd4000000;
17635 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17636 BFD_RELOC_MICROMIPS_JMP
);
17637 fixp
->fx_file
= fragp
->fr_file
;
17638 fixp
->fx_line
= fragp
->fr_line
;
17640 buf
= write_compressed_insn (buf
, insn
, 4);
17643 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17647 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17648 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17649 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17651 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17652 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17653 insn
|= at
<< MICROMIPSOP_SH_RT
;
17655 if (exp
.X_add_number
)
17657 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17658 exp
.X_add_number
= 0;
17661 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17662 BFD_RELOC_MICROMIPS_GOT16
);
17663 fixp
->fx_file
= fragp
->fr_file
;
17664 fixp
->fx_line
= fragp
->fr_line
;
17666 buf
= write_compressed_insn (buf
, insn
, 4);
17668 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17669 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17670 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17672 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17673 BFD_RELOC_MICROMIPS_LO16
);
17674 fixp
->fx_file
= fragp
->fr_file
;
17675 fixp
->fx_line
= fragp
->fr_line
;
17677 buf
= write_compressed_insn (buf
, insn
, 4);
17679 /* jr/jrc/jalr/jalrs $at */
17680 insn
= al
? jalr
: jr
;
17681 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17683 buf
= write_compressed_insn (buf
, insn
, 2);
17686 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17690 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17693 const struct mips_int_operand
*operand
;
17696 unsigned int user_length
, length
;
17697 unsigned long insn
;
17700 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17701 operand
= mips16_immed_operand (type
, FALSE
);
17703 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17704 val
= resolve_symbol_value (fragp
->fr_symbol
);
17705 if (operand
->root
.type
== OP_PCREL
)
17707 const struct mips_pcrel_operand
*pcrel_op
;
17710 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17711 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17713 /* The rules for the base address of a PC relative reloc are
17714 complicated; see mips16_extended_frag. */
17715 if (pcrel_op
->include_isa_bit
)
17720 /* Ignore the low bit in the target, since it will be
17721 set for a text label. */
17724 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17726 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17729 addr
&= -(1 << pcrel_op
->align_log2
);
17732 /* Make sure the section winds up with the alignment we have
17734 if (operand
->shift
> 0)
17735 record_alignment (asec
, operand
->shift
);
17739 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17740 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17741 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17742 _("extended instruction in delay slot"));
17744 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17746 insn
= read_compressed_insn (buf
, 2);
17748 insn
|= MIPS16_EXTEND
;
17750 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17752 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17757 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17758 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17760 length
= (ext
? 4 : 2);
17761 gas_assert (mips16_opcode_length (insn
) == length
);
17762 write_compressed_insn (buf
, insn
, length
);
17763 fragp
->fr_fix
+= length
;
17767 relax_substateT subtype
= fragp
->fr_subtype
;
17768 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17769 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17773 first
= RELAX_FIRST (subtype
);
17774 second
= RELAX_SECOND (subtype
);
17775 fixp
= (fixS
*) fragp
->fr_opcode
;
17777 /* If the delay slot chosen does not match the size of the instruction,
17778 then emit a warning. */
17779 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17780 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17785 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17786 | RELAX_DELAY_SLOT_SIZE_FIRST
17787 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17788 msg
= macro_warning (s
);
17790 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17794 /* Possibly emit a warning if we've chosen the longer option. */
17795 if (use_second
== second_longer
)
17801 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17802 msg
= macro_warning (s
);
17804 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17808 /* Go through all the fixups for the first sequence. Disable them
17809 (by marking them as done) if we're going to use the second
17810 sequence instead. */
17812 && fixp
->fx_frag
== fragp
17813 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17815 if (subtype
& RELAX_USE_SECOND
)
17817 fixp
= fixp
->fx_next
;
17820 /* Go through the fixups for the second sequence. Disable them if
17821 we're going to use the first sequence, otherwise adjust their
17822 addresses to account for the relaxation. */
17823 while (fixp
&& fixp
->fx_frag
== fragp
)
17825 if (subtype
& RELAX_USE_SECOND
)
17826 fixp
->fx_where
-= first
;
17829 fixp
= fixp
->fx_next
;
17832 /* Now modify the frag contents. */
17833 if (subtype
& RELAX_USE_SECOND
)
17837 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17838 memmove (start
, start
+ first
, second
);
17839 fragp
->fr_fix
-= first
;
17842 fragp
->fr_fix
-= second
;
17846 /* This function is called after the relocs have been generated.
17847 We've been storing mips16 text labels as odd. Here we convert them
17848 back to even for the convenience of the debugger. */
17851 mips_frob_file_after_relocs (void)
17854 unsigned int count
, i
;
17856 syms
= bfd_get_outsymbols (stdoutput
);
17857 count
= bfd_get_symcount (stdoutput
);
17858 for (i
= 0; i
< count
; i
++, syms
++)
17859 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17860 && ((*syms
)->value
& 1) != 0)
17862 (*syms
)->value
&= ~1;
17863 /* If the symbol has an odd size, it was probably computed
17864 incorrectly, so adjust that as well. */
17865 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17866 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17870 /* This function is called whenever a label is defined, including fake
17871 labels instantiated off the dot special symbol. It is used when
17872 handling branch delays; if a branch has a label, we assume we cannot
17873 move it. This also bumps the value of the symbol by 1 in compressed
17877 mips_record_label (symbolS
*sym
)
17879 segment_info_type
*si
= seg_info (now_seg
);
17880 struct insn_label_list
*l
;
17882 if (free_insn_labels
== NULL
)
17883 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17886 l
= free_insn_labels
;
17887 free_insn_labels
= l
->next
;
17891 l
->next
= si
->label_list
;
17892 si
->label_list
= l
;
17895 /* This function is called as tc_frob_label() whenever a label is defined
17896 and adds a DWARF-2 record we only want for true labels. */
17899 mips_define_label (symbolS
*sym
)
17901 mips_record_label (sym
);
17902 dwarf2_emit_label (sym
);
17905 /* This function is called by tc_new_dot_label whenever a new dot symbol
17909 mips_add_dot_label (symbolS
*sym
)
17911 mips_record_label (sym
);
17912 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17913 mips_compressed_mark_label (sym
);
17916 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17917 static unsigned int
17918 mips_convert_ase_flags (int ase
)
17920 unsigned int ext_ases
= 0;
17923 ext_ases
|= AFL_ASE_DSP
;
17924 if (ase
& ASE_DSPR2
)
17925 ext_ases
|= AFL_ASE_DSPR2
;
17927 ext_ases
|= AFL_ASE_EVA
;
17929 ext_ases
|= AFL_ASE_MCU
;
17930 if (ase
& ASE_MDMX
)
17931 ext_ases
|= AFL_ASE_MDMX
;
17932 if (ase
& ASE_MIPS3D
)
17933 ext_ases
|= AFL_ASE_MIPS3D
;
17935 ext_ases
|= AFL_ASE_MT
;
17936 if (ase
& ASE_SMARTMIPS
)
17937 ext_ases
|= AFL_ASE_SMARTMIPS
;
17938 if (ase
& ASE_VIRT
)
17939 ext_ases
|= AFL_ASE_VIRT
;
17941 ext_ases
|= AFL_ASE_MSA
;
17943 ext_ases
|= AFL_ASE_XPA
;
17947 /* Some special processing for a MIPS ELF file. */
17950 mips_elf_final_processing (void)
17953 Elf_Internal_ABIFlags_v0 flags
;
17957 switch (file_mips_opts
.isa
)
17960 flags
.isa_level
= 1;
17963 flags
.isa_level
= 2;
17966 flags
.isa_level
= 3;
17969 flags
.isa_level
= 4;
17972 flags
.isa_level
= 5;
17975 flags
.isa_level
= 32;
17979 flags
.isa_level
= 32;
17983 flags
.isa_level
= 32;
17987 flags
.isa_level
= 32;
17991 flags
.isa_level
= 32;
17995 flags
.isa_level
= 64;
17999 flags
.isa_level
= 64;
18003 flags
.isa_level
= 64;
18007 flags
.isa_level
= 64;
18011 flags
.isa_level
= 64;
18016 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18017 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18018 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18019 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18021 flags
.cpr2_size
= AFL_REG_NONE
;
18022 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18023 Tag_GNU_MIPS_ABI_FP
);
18024 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18025 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18026 if (file_ase_mips16
)
18027 flags
.ases
|= AFL_ASE_MIPS16
;
18028 if (file_ase_micromips
)
18029 flags
.ases
|= AFL_ASE_MICROMIPS
;
18031 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18032 || file_mips_opts
.fp
== 64)
18033 && file_mips_opts
.oddspreg
)
18034 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18037 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18038 ((Elf_External_ABIFlags_v0
*)
18041 /* Write out the register information. */
18042 if (mips_abi
!= N64_ABI
)
18046 s
.ri_gprmask
= mips_gprmask
;
18047 s
.ri_cprmask
[0] = mips_cprmask
[0];
18048 s
.ri_cprmask
[1] = mips_cprmask
[1];
18049 s
.ri_cprmask
[2] = mips_cprmask
[2];
18050 s
.ri_cprmask
[3] = mips_cprmask
[3];
18051 /* The gp_value field is set by the MIPS ELF backend. */
18053 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18054 ((Elf32_External_RegInfo
*)
18055 mips_regmask_frag
));
18059 Elf64_Internal_RegInfo s
;
18061 s
.ri_gprmask
= mips_gprmask
;
18063 s
.ri_cprmask
[0] = mips_cprmask
[0];
18064 s
.ri_cprmask
[1] = mips_cprmask
[1];
18065 s
.ri_cprmask
[2] = mips_cprmask
[2];
18066 s
.ri_cprmask
[3] = mips_cprmask
[3];
18067 /* The gp_value field is set by the MIPS ELF backend. */
18069 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18070 ((Elf64_External_RegInfo
*)
18071 mips_regmask_frag
));
18074 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18075 sort of BFD interface for this. */
18076 if (mips_any_noreorder
)
18077 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18078 if (mips_pic
!= NO_PIC
)
18080 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18081 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18084 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18086 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18087 defined at present; this might need to change in future. */
18088 if (file_ase_mips16
)
18089 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18090 if (file_ase_micromips
)
18091 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18092 if (file_mips_opts
.ase
& ASE_MDMX
)
18093 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18095 /* Set the MIPS ELF ABI flags. */
18096 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18097 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18098 else if (mips_abi
== O64_ABI
)
18099 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18100 else if (mips_abi
== EABI_ABI
)
18102 if (file_mips_opts
.gp
== 64)
18103 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18105 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18107 else if (mips_abi
== N32_ABI
)
18108 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18110 /* Nothing to do for N64_ABI. */
18112 if (mips_32bitmode
)
18113 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18115 if (mips_nan2008
== 1)
18116 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18118 /* 32 bit code with 64 bit FP registers. */
18119 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18120 Tag_GNU_MIPS_ABI_FP
);
18121 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18122 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18125 typedef struct proc
{
18127 symbolS
*func_end_sym
;
18128 unsigned long reg_mask
;
18129 unsigned long reg_offset
;
18130 unsigned long fpreg_mask
;
18131 unsigned long fpreg_offset
;
18132 unsigned long frame_offset
;
18133 unsigned long frame_reg
;
18134 unsigned long pc_reg
;
18137 static procS cur_proc
;
18138 static procS
*cur_proc_ptr
;
18139 static int numprocs
;
18141 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18142 as "2", and a normal nop as "0". */
18144 #define NOP_OPCODE_MIPS 0
18145 #define NOP_OPCODE_MIPS16 1
18146 #define NOP_OPCODE_MICROMIPS 2
18149 mips_nop_opcode (void)
18151 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18152 return NOP_OPCODE_MICROMIPS
;
18153 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18154 return NOP_OPCODE_MIPS16
;
18156 return NOP_OPCODE_MIPS
;
18159 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18160 32-bit microMIPS NOPs here (if applicable). */
18163 mips_handle_align (fragS
*fragp
)
18167 int bytes
, size
, excess
;
18170 if (fragp
->fr_type
!= rs_align_code
)
18173 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18175 switch (nop_opcode
)
18177 case NOP_OPCODE_MICROMIPS
:
18178 opcode
= micromips_nop32_insn
.insn_opcode
;
18181 case NOP_OPCODE_MIPS16
:
18182 opcode
= mips16_nop_insn
.insn_opcode
;
18185 case NOP_OPCODE_MIPS
:
18187 opcode
= nop_insn
.insn_opcode
;
18192 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18193 excess
= bytes
% size
;
18195 /* Handle the leading part if we're not inserting a whole number of
18196 instructions, and make it the end of the fixed part of the frag.
18197 Try to fit in a short microMIPS NOP if applicable and possible,
18198 and use zeroes otherwise. */
18199 gas_assert (excess
< 4);
18200 fragp
->fr_fix
+= excess
;
18205 /* Fall through. */
18207 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18209 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18213 /* Fall through. */
18216 /* Fall through. */
18221 md_number_to_chars (p
, opcode
, size
);
18222 fragp
->fr_var
= size
;
18231 if (*input_line_pointer
== '-')
18233 ++input_line_pointer
;
18236 if (!ISDIGIT (*input_line_pointer
))
18237 as_bad (_("expected simple number"));
18238 if (input_line_pointer
[0] == '0')
18240 if (input_line_pointer
[1] == 'x')
18242 input_line_pointer
+= 2;
18243 while (ISXDIGIT (*input_line_pointer
))
18246 val
|= hex_value (*input_line_pointer
++);
18248 return negative
? -val
: val
;
18252 ++input_line_pointer
;
18253 while (ISDIGIT (*input_line_pointer
))
18256 val
|= *input_line_pointer
++ - '0';
18258 return negative
? -val
: val
;
18261 if (!ISDIGIT (*input_line_pointer
))
18263 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18264 *input_line_pointer
, *input_line_pointer
);
18265 as_warn (_("invalid number"));
18268 while (ISDIGIT (*input_line_pointer
))
18271 val
+= *input_line_pointer
++ - '0';
18273 return negative
? -val
: val
;
18276 /* The .file directive; just like the usual .file directive, but there
18277 is an initial number which is the ECOFF file index. In the non-ECOFF
18278 case .file implies DWARF-2. */
18281 s_mips_file (int x ATTRIBUTE_UNUSED
)
18283 static int first_file_directive
= 0;
18285 if (ECOFF_DEBUGGING
)
18294 filename
= dwarf2_directive_file (0);
18296 /* Versions of GCC up to 3.1 start files with a ".file"
18297 directive even for stabs output. Make sure that this
18298 ".file" is handled. Note that you need a version of GCC
18299 after 3.1 in order to support DWARF-2 on MIPS. */
18300 if (filename
!= NULL
&& ! first_file_directive
)
18302 (void) new_logical_line (filename
, -1);
18303 s_app_file_string (filename
, 0);
18305 first_file_directive
= 1;
18309 /* The .loc directive, implying DWARF-2. */
18312 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18314 if (!ECOFF_DEBUGGING
)
18315 dwarf2_directive_loc (0);
18318 /* The .end directive. */
18321 s_mips_end (int x ATTRIBUTE_UNUSED
)
18325 /* Following functions need their own .frame and .cprestore directives. */
18326 mips_frame_reg_valid
= 0;
18327 mips_cprestore_valid
= 0;
18329 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18332 demand_empty_rest_of_line ();
18337 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18338 as_warn (_(".end not in text section"));
18342 as_warn (_(".end directive without a preceding .ent directive"));
18343 demand_empty_rest_of_line ();
18349 gas_assert (S_GET_NAME (p
));
18350 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18351 as_warn (_(".end symbol does not match .ent symbol"));
18353 if (debug_type
== DEBUG_STABS
)
18354 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18358 as_warn (_(".end directive missing or unknown symbol"));
18360 /* Create an expression to calculate the size of the function. */
18361 if (p
&& cur_proc_ptr
)
18363 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18364 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18367 exp
->X_op
= O_subtract
;
18368 exp
->X_add_symbol
= symbol_temp_new_now ();
18369 exp
->X_op_symbol
= p
;
18370 exp
->X_add_number
= 0;
18372 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18375 /* Generate a .pdr section. */
18376 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
18378 segT saved_seg
= now_seg
;
18379 subsegT saved_subseg
= now_subseg
;
18383 #ifdef md_flush_pending_output
18384 md_flush_pending_output ();
18387 gas_assert (pdr_seg
);
18388 subseg_set (pdr_seg
, 0);
18390 /* Write the symbol. */
18391 exp
.X_op
= O_symbol
;
18392 exp
.X_add_symbol
= p
;
18393 exp
.X_add_number
= 0;
18394 emit_expr (&exp
, 4);
18396 fragp
= frag_more (7 * 4);
18398 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18399 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18400 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18401 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18402 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18403 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18404 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18406 subseg_set (saved_seg
, saved_subseg
);
18409 cur_proc_ptr
= NULL
;
18412 /* The .aent and .ent directives. */
18415 s_mips_ent (int aent
)
18419 symbolP
= get_symbol ();
18420 if (*input_line_pointer
== ',')
18421 ++input_line_pointer
;
18422 SKIP_WHITESPACE ();
18423 if (ISDIGIT (*input_line_pointer
)
18424 || *input_line_pointer
== '-')
18427 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18428 as_warn (_(".ent or .aent not in text section"));
18430 if (!aent
&& cur_proc_ptr
)
18431 as_warn (_("missing .end"));
18435 /* This function needs its own .frame and .cprestore directives. */
18436 mips_frame_reg_valid
= 0;
18437 mips_cprestore_valid
= 0;
18439 cur_proc_ptr
= &cur_proc
;
18440 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18442 cur_proc_ptr
->func_sym
= symbolP
;
18446 if (debug_type
== DEBUG_STABS
)
18447 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18448 S_GET_NAME (symbolP
));
18451 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18453 demand_empty_rest_of_line ();
18456 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18457 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18458 s_mips_frame is used so that we can set the PDR information correctly.
18459 We can't use the ecoff routines because they make reference to the ecoff
18460 symbol table (in the mdebug section). */
18463 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18465 if (ECOFF_DEBUGGING
)
18471 if (cur_proc_ptr
== (procS
*) NULL
)
18473 as_warn (_(".frame outside of .ent"));
18474 demand_empty_rest_of_line ();
18478 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18480 SKIP_WHITESPACE ();
18481 if (*input_line_pointer
++ != ','
18482 || get_absolute_expression_and_terminator (&val
) != ',')
18484 as_warn (_("bad .frame directive"));
18485 --input_line_pointer
;
18486 demand_empty_rest_of_line ();
18490 cur_proc_ptr
->frame_offset
= val
;
18491 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18493 demand_empty_rest_of_line ();
18497 /* The .fmask and .mask directives. If the mdebug section is present
18498 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18499 embedded targets, s_mips_mask is used so that we can set the PDR
18500 information correctly. We can't use the ecoff routines because they
18501 make reference to the ecoff symbol table (in the mdebug section). */
18504 s_mips_mask (int reg_type
)
18506 if (ECOFF_DEBUGGING
)
18507 s_ignore (reg_type
);
18512 if (cur_proc_ptr
== (procS
*) NULL
)
18514 as_warn (_(".mask/.fmask outside of .ent"));
18515 demand_empty_rest_of_line ();
18519 if (get_absolute_expression_and_terminator (&mask
) != ',')
18521 as_warn (_("bad .mask/.fmask directive"));
18522 --input_line_pointer
;
18523 demand_empty_rest_of_line ();
18527 off
= get_absolute_expression ();
18529 if (reg_type
== 'F')
18531 cur_proc_ptr
->fpreg_mask
= mask
;
18532 cur_proc_ptr
->fpreg_offset
= off
;
18536 cur_proc_ptr
->reg_mask
= mask
;
18537 cur_proc_ptr
->reg_offset
= off
;
18540 demand_empty_rest_of_line ();
18544 /* A table describing all the processors gas knows about. Names are
18545 matched in the order listed.
18547 To ease comparison, please keep this table in the same order as
18548 gcc's mips_cpu_info_table[]. */
18549 static const struct mips_cpu_info mips_cpu_info_table
[] =
18551 /* Entries for generic ISAs */
18552 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
18553 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
18554 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
18555 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
18556 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
18557 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
18558 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18559 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
18560 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
18561 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
18562 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
18563 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
18564 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
18565 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
18566 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
18569 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18570 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18571 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
18574 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
18577 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
18578 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
18579 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
18580 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
18581 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18582 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18583 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
18584 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
18585 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
18586 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
18587 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
18588 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
18589 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
18590 /* ST Microelectronics Loongson 2E and 2F cores */
18591 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18592 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
18595 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
18596 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
18597 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
18598 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
18599 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
18600 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
18601 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
18602 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
18603 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
18604 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
18605 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
18606 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
18607 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
18608 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
18609 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
18612 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18613 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18614 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18615 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
18617 /* MIPS 32 Release 2 */
18618 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18619 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18620 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18621 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18622 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18623 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18624 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18625 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18626 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18627 ISA_MIPS32R2
, CPU_MIPS32R2
},
18628 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18629 ISA_MIPS32R2
, CPU_MIPS32R2
},
18630 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18631 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18632 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18633 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18634 /* Deprecated forms of the above. */
18635 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18636 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18637 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18638 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18639 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18640 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18641 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18642 /* Deprecated forms of the above. */
18643 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18644 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18645 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18646 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18647 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18648 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18649 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18650 /* Deprecated forms of the above. */
18651 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18652 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18653 /* 34Kn is a 34kc without DSP. */
18654 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18655 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18656 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18657 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18658 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18659 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18660 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18661 /* Deprecated forms of the above. */
18662 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18663 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18664 /* 1004K cores are multiprocessor versions of the 34K. */
18665 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18666 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18667 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18668 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18669 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18670 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18673 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18674 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18675 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18676 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18678 /* Broadcom SB-1 CPU core */
18679 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18680 /* Broadcom SB-1A CPU core */
18681 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18683 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
18685 /* MIPS 64 Release 2 */
18687 /* Cavium Networks Octeon CPU core */
18688 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18689 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18690 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18691 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
18694 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18697 XLP is mostly like XLR, with the prominent exception that it is
18698 MIPS64R2 rather than MIPS64. */
18699 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18702 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
18705 { NULL
, 0, 0, 0, 0 }
18709 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18710 with a final "000" replaced by "k". Ignore case.
18712 Note: this function is shared between GCC and GAS. */
18715 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18717 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18718 given
++, canonical
++;
18720 return ((*given
== 0 && *canonical
== 0)
18721 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18725 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18726 CPU name. We've traditionally allowed a lot of variation here.
18728 Note: this function is shared between GCC and GAS. */
18731 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18733 /* First see if the name matches exactly, or with a final "000"
18734 turned into "k". */
18735 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18738 /* If not, try comparing based on numerical designation alone.
18739 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18740 if (TOLOWER (*given
) == 'r')
18742 if (!ISDIGIT (*given
))
18745 /* Skip over some well-known prefixes in the canonical name,
18746 hoping to find a number there too. */
18747 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18749 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18751 else if (TOLOWER (canonical
[0]) == 'r')
18754 return mips_strict_matching_cpu_name_p (canonical
, given
);
18758 /* Parse an option that takes the name of a processor as its argument.
18759 OPTION is the name of the option and CPU_STRING is the argument.
18760 Return the corresponding processor enumeration if the CPU_STRING is
18761 recognized, otherwise report an error and return null.
18763 A similar function exists in GCC. */
18765 static const struct mips_cpu_info
*
18766 mips_parse_cpu (const char *option
, const char *cpu_string
)
18768 const struct mips_cpu_info
*p
;
18770 /* 'from-abi' selects the most compatible architecture for the given
18771 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18772 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18773 version. Look first at the -mgp options, if given, otherwise base
18774 the choice on MIPS_DEFAULT_64BIT.
18776 Treat NO_ABI like the EABIs. One reason to do this is that the
18777 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18778 architecture. This code picks MIPS I for 'mips' and MIPS III for
18779 'mips64', just as we did in the days before 'from-abi'. */
18780 if (strcasecmp (cpu_string
, "from-abi") == 0)
18782 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18783 return mips_cpu_info_from_isa (ISA_MIPS1
);
18785 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18786 return mips_cpu_info_from_isa (ISA_MIPS3
);
18788 if (file_mips_opts
.gp
>= 0)
18789 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
18790 ? ISA_MIPS1
: ISA_MIPS3
);
18792 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18797 /* 'default' has traditionally been a no-op. Probably not very useful. */
18798 if (strcasecmp (cpu_string
, "default") == 0)
18801 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18802 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18805 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18809 /* Return the canonical processor information for ISA (a member of the
18810 ISA_MIPS* enumeration). */
18812 static const struct mips_cpu_info
*
18813 mips_cpu_info_from_isa (int isa
)
18817 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18818 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18819 && isa
== mips_cpu_info_table
[i
].isa
)
18820 return (&mips_cpu_info_table
[i
]);
18825 static const struct mips_cpu_info
*
18826 mips_cpu_info_from_arch (int arch
)
18830 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18831 if (arch
== mips_cpu_info_table
[i
].cpu
)
18832 return (&mips_cpu_info_table
[i
]);
18838 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18842 fprintf (stream
, "%24s", "");
18847 fprintf (stream
, ", ");
18851 if (*col_p
+ strlen (string
) > 72)
18853 fprintf (stream
, "\n%24s", "");
18857 fprintf (stream
, "%s", string
);
18858 *col_p
+= strlen (string
);
18864 md_show_usage (FILE *stream
)
18869 fprintf (stream
, _("\
18871 -EB generate big endian output\n\
18872 -EL generate little endian output\n\
18873 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18874 -G NUM allow referencing objects up to NUM bytes\n\
18875 implicitly with the gp register [default 8]\n"));
18876 fprintf (stream
, _("\
18877 -mips1 generate MIPS ISA I instructions\n\
18878 -mips2 generate MIPS ISA II instructions\n\
18879 -mips3 generate MIPS ISA III instructions\n\
18880 -mips4 generate MIPS ISA IV instructions\n\
18881 -mips5 generate MIPS ISA V instructions\n\
18882 -mips32 generate MIPS32 ISA instructions\n\
18883 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18884 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18885 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18886 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18887 -mips64 generate MIPS64 ISA instructions\n\
18888 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18889 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18890 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18891 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18892 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18896 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18897 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18898 show (stream
, "from-abi", &column
, &first
);
18899 fputc ('\n', stream
);
18901 fprintf (stream
, _("\
18902 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18903 -no-mCPU don't generate code specific to CPU.\n\
18904 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18908 show (stream
, "3900", &column
, &first
);
18909 show (stream
, "4010", &column
, &first
);
18910 show (stream
, "4100", &column
, &first
);
18911 show (stream
, "4650", &column
, &first
);
18912 fputc ('\n', stream
);
18914 fprintf (stream
, _("\
18915 -mips16 generate mips16 instructions\n\
18916 -no-mips16 do not generate mips16 instructions\n"));
18917 fprintf (stream
, _("\
18918 -mmicromips generate microMIPS instructions\n\
18919 -mno-micromips do not generate microMIPS instructions\n"));
18920 fprintf (stream
, _("\
18921 -msmartmips generate smartmips instructions\n\
18922 -mno-smartmips do not generate smartmips instructions\n"));
18923 fprintf (stream
, _("\
18924 -mdsp generate DSP instructions\n\
18925 -mno-dsp do not generate DSP instructions\n"));
18926 fprintf (stream
, _("\
18927 -mdspr2 generate DSP R2 instructions\n\
18928 -mno-dspr2 do not generate DSP R2 instructions\n"));
18929 fprintf (stream
, _("\
18930 -mmt generate MT instructions\n\
18931 -mno-mt do not generate MT instructions\n"));
18932 fprintf (stream
, _("\
18933 -mmcu generate MCU instructions\n\
18934 -mno-mcu do not generate MCU instructions\n"));
18935 fprintf (stream
, _("\
18936 -mmsa generate MSA instructions\n\
18937 -mno-msa do not generate MSA instructions\n"));
18938 fprintf (stream
, _("\
18939 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18940 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18941 fprintf (stream
, _("\
18942 -mvirt generate Virtualization instructions\n\
18943 -mno-virt do not generate Virtualization instructions\n"));
18944 fprintf (stream
, _("\
18945 -minsn32 only generate 32-bit microMIPS instructions\n\
18946 -mno-insn32 generate all microMIPS instructions\n"));
18947 fprintf (stream
, _("\
18948 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18949 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18950 -mfix-vr4120 work around certain VR4120 errata\n\
18951 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18952 -mfix-24k insert a nop after ERET and DERET instructions\n\
18953 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18954 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18955 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18956 -msym32 assume all symbols have 32-bit values\n\
18957 -O0 remove unneeded NOPs, do not swap branches\n\
18958 -O remove unneeded NOPs and swap branches\n\
18959 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18960 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18961 fprintf (stream
, _("\
18962 -mhard-float allow floating-point instructions\n\
18963 -msoft-float do not allow floating-point instructions\n\
18964 -msingle-float only allow 32-bit floating-point operations\n\
18965 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18966 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18967 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18968 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18972 show (stream
, "legacy", &column
, &first
);
18973 show (stream
, "2008", &column
, &first
);
18975 fputc ('\n', stream
);
18977 fprintf (stream
, _("\
18978 -KPIC, -call_shared generate SVR4 position independent code\n\
18979 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18980 -mvxworks-pic generate VxWorks position independent code\n\
18981 -non_shared do not generate code that can operate with DSOs\n\
18982 -xgot assume a 32 bit GOT\n\
18983 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18984 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18985 position dependent (non shared) code\n\
18986 -mabi=ABI create ABI conformant object file for:\n"));
18990 show (stream
, "32", &column
, &first
);
18991 show (stream
, "o64", &column
, &first
);
18992 show (stream
, "n32", &column
, &first
);
18993 show (stream
, "64", &column
, &first
);
18994 show (stream
, "eabi", &column
, &first
);
18996 fputc ('\n', stream
);
18998 fprintf (stream
, _("\
18999 -32 create o32 ABI object file (default)\n\
19000 -n32 create n32 ABI object file\n\
19001 -64 create 64 ABI object file\n"));
19006 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19008 if (HAVE_64BIT_SYMBOLS
)
19009 return dwarf2_format_64bit_irix
;
19011 return dwarf2_format_32bit
;
19016 mips_dwarf2_addr_size (void)
19018 if (HAVE_64BIT_OBJECTS
)
19024 /* Standard calling conventions leave the CFA at SP on entry. */
19026 mips_cfi_frame_initial_instructions (void)
19028 cfi_add_CFA_def_cfa_register (SP
);
19032 tc_mips_regname_to_dw2regnum (char *regname
)
19034 unsigned int regnum
= -1;
19037 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19043 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19044 Given a symbolic attribute NAME, return the proper integer value.
19045 Returns -1 if the attribute is not known. */
19048 mips_convert_symbolic_attribute (const char *name
)
19050 static const struct
19055 attribute_table
[] =
19057 #define T(tag) {#tag, tag}
19058 T (Tag_GNU_MIPS_ABI_FP
),
19059 T (Tag_GNU_MIPS_ABI_MSA
),
19067 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19068 if (streq (name
, attribute_table
[i
].name
))
19069 return attribute_table
[i
].tag
;
19077 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19079 mips_emit_delays ();
19081 as_warn (_("missing .end at end of assembly"));
19083 /* Just in case no code was emitted, do the consistency check. */
19084 file_mips_check_options ();
19086 /* Set a floating-point ABI if the user did not. */
19087 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19089 /* Perform consistency checks on the floating-point ABI. */
19090 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19091 Tag_GNU_MIPS_ABI_FP
);
19092 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19093 check_fpabi (fpabi
);
19097 /* Soft-float gets precedence over single-float, the two options should
19098 not be used together so this should not matter. */
19099 if (file_mips_opts
.soft_float
== 1)
19100 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19101 /* Single-float gets precedence over all double_float cases. */
19102 else if (file_mips_opts
.single_float
== 1)
19103 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19106 switch (file_mips_opts
.fp
)
19109 if (file_mips_opts
.gp
== 32)
19110 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19113 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19116 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19117 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19118 else if (file_mips_opts
.gp
== 32)
19119 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19121 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19126 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19127 Tag_GNU_MIPS_ABI_FP
, fpabi
);
19131 /* Returns the relocation type required for a particular CFI encoding. */
19133 bfd_reloc_code_real_type
19134 mips_cfi_reloc_for_encoding (int encoding
)
19136 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
19137 return BFD_RELOC_32_PCREL
;
19138 else return BFD_RELOC_NONE
;