1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? (mips_64
? "elf64-tradbigmips" : "elf32-tradbigmips")
130 : (mips_64
? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
132 return (target_big_endian
133 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
134 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
142 /* The name of the readonly data section. */
143 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
145 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
149 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
153 /* This is the set of options which may be modified by the .set
154 pseudo-op. We use a struct so that .set push and .set pop are more
157 struct mips_set_options
159 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
160 if it has not been initialized. Changed by `.set mipsN', and the
161 -mipsN command line option, and the default CPU. */
163 /* Whether we are assembling for the mips16 processor. 0 if we are
164 not, 1 if we are, and -1 if the value has not been initialized.
165 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
166 -nomips16 command line options, and the default CPU. */
168 /* Non-zero if we should not reorder instructions. Changed by `.set
169 reorder' and `.set noreorder'. */
171 /* Non-zero if we should not permit the $at ($1) register to be used
172 in instructions. Changed by `.set at' and `.set noat'. */
174 /* Non-zero if we should warn when a macro instruction expands into
175 more than one machine instruction. Changed by `.set nomacro' and
177 int warn_about_macros
;
178 /* Non-zero if we should not move instructions. Changed by `.set
179 move', `.set volatile', `.set nomove', and `.set novolatile'. */
181 /* Non-zero if we should not optimize branches by moving the target
182 of the branch into the delay slot. Actually, we don't perform
183 this optimization anyhow. Changed by `.set bopt' and `.set
186 /* Non-zero if we should not autoextend mips16 instructions.
187 Changed by `.set autoextend' and `.set noautoextend'. */
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* The argument of the -mcpu= flag. Historical for code generation. */
210 static int mips_cpu
= CPU_UNKNOWN
;
212 /* The argument of the -march= flag. The architecture we are assembling. */
213 static int mips_arch
= CPU_UNKNOWN
;
215 /* The argument of the -mtune= flag. The architecture for which we
217 static int mips_tune
= CPU_UNKNOWN
;
219 /* The argument of the -mabi= flag. */
220 static char * mips_abi_string
= NULL
;
222 /* Whether we should mark the file EABI64 or EABI32. */
223 static int mips_eabi64
= 0;
225 /* If they asked for mips1 or mips2 and a cpu that is
226 mips3 or greater, then mark the object file 32BITMODE. */
227 static int mips_32bitmode
= 0;
229 /* True if -mgp32 was passed. */
230 static int mips_gp32
= 0;
232 /* True if -mfp32 was passed. */
233 static int mips_fp32
= 0;
235 /* True if the selected ABI is defined for 32-bit registers only. */
236 static int mips_32bit_abi
= 0;
238 /* Some ISA's have delay slots for instructions which read or write
239 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
240 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
241 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
242 delay slot in this ISA. The uses of this macro assume that any
243 ISA that has delay slots for one of these, has them for all. They
244 also assume that ISAs which don't have delays for these insns, don't
245 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
246 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
248 || (ISA) == ISA_MIPS2 \
249 || (ISA) == ISA_MIPS3 \
252 /* Return true if ISA supports 64 bit gp register instructions. */
253 #define ISA_HAS_64BIT_REGS(ISA) ( \
255 || (ISA) == ISA_MIPS4 \
256 || (ISA) == ISA_MIPS5 \
257 || (ISA) == ISA_MIPS64 \
260 #define HAVE_32BIT_GPRS \
263 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
265 #define HAVE_32BIT_FPRS \
268 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
270 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
271 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
273 #define HAVE_32BIT_ADDRESSES \
275 || bfd_arch_bits_per_address (stdoutput) == 32)
277 /* Whether the processor uses hardware interlocks to protect
278 reads from the HI and LO registers, and thus does not
279 require nops to be inserted. */
281 #define hilo_interlocks (mips_arch == CPU_R4010 \
284 /* Whether the processor uses hardware interlocks to protect reads
285 from the GPRs, and thus does not require nops to be inserted. */
286 #define gpr_interlocks \
287 (mips_opts.isa != ISA_MIPS1 \
288 || mips_arch == CPU_R3900)
290 /* As with other "interlocks" this is used by hardware that has FP
291 (co-processor) interlocks. */
292 /* Itbl support may require additional care here. */
293 #define cop_interlocks (mips_arch == CPU_R4300 \
296 /* Is this a mfhi or mflo instruction? */
297 #define MF_HILO_INSN(PINFO) \
298 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
300 /* MIPS PIC level. */
304 /* Do not generate PIC code. */
307 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
308 not sure what it is supposed to do. */
311 /* Generate PIC code as in the SVR4 MIPS ABI. */
314 /* Generate PIC code without using a global offset table: the data
315 segment has a maximum size of 64K, all data references are off
316 the $gp register, and all text references are PC relative. This
317 is used on some embedded systems. */
321 static enum mips_pic_level mips_pic
;
323 /* Warn about all NOPS that the assembler generates. */
324 static int warn_nops
= 0;
326 /* 1 if we should generate 32 bit offsets from the GP register in
327 SVR4_PIC mode. Currently has no meaning in other modes. */
328 static int mips_big_got
;
330 /* 1 if trap instructions should used for overflow rather than break
332 static int mips_trap
;
334 /* 1 if double width floating point constants should not be constructed
335 by a assembling two single width halves into two single width floating
336 point registers which just happen to alias the double width destination
337 register. On some architectures this aliasing can be disabled by a bit
338 in the status register, and the setting of this bit cannot be determined
339 automatically at assemble time. */
340 static int mips_disable_float_construction
;
342 /* Non-zero if any .set noreorder directives were used. */
344 static int mips_any_noreorder
;
346 /* Non-zero if nops should be inserted when the register referenced in
347 an mfhi/mflo instruction is read in the next two instructions. */
348 static int mips_7000_hilo_fix
;
350 /* The size of the small data section. */
351 static unsigned int g_switch_value
= 8;
352 /* Whether the -G option was used. */
353 static int g_switch_seen
= 0;
358 /* If we can determine in advance that GP optimization won't be
359 possible, we can skip the relaxation stuff that tries to produce
360 GP-relative references. This makes delay slot optimization work
363 This function can only provide a guess, but it seems to work for
364 gcc output. It needs to guess right for gcc, otherwise gcc
365 will put what it thinks is a GP-relative instruction in a branch
368 I don't know if a fix is needed for the SVR4_PIC mode. I've only
369 fixed it for the non-PIC mode. KR 95/04/07 */
370 static int nopic_need_relax
PARAMS ((symbolS
*, int));
372 /* handle of the OPCODE hash table */
373 static struct hash_control
*op_hash
= NULL
;
375 /* The opcode hash table we use for the mips16. */
376 static struct hash_control
*mips16_op_hash
= NULL
;
378 /* This array holds the chars that always start a comment. If the
379 pre-processor is disabled, these aren't very useful */
380 const char comment_chars
[] = "#";
382 /* This array holds the chars that only start a comment at the beginning of
383 a line. If the line seems to have the form '# 123 filename'
384 .line and .file directives will appear in the pre-processed output */
385 /* Note that input_file.c hand checks for '#' at the beginning of the
386 first line of the input file. This is because the compiler outputs
387 #NO_APP at the beginning of its output. */
388 /* Also note that C style comments are always supported. */
389 const char line_comment_chars
[] = "#";
391 /* This array holds machine specific line separator characters. */
392 const char line_separator_chars
[] = ";";
394 /* Chars that can be used to separate mant from exp in floating point nums */
395 const char EXP_CHARS
[] = "eE";
397 /* Chars that mean this number is a floating point constant */
400 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
402 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
403 changed in read.c . Ideally it shouldn't have to know about it at all,
404 but nothing is ideal around here.
407 static char *insn_error
;
409 static int auto_align
= 1;
411 /* When outputting SVR4 PIC code, the assembler needs to know the
412 offset in the stack frame from which to restore the $gp register.
413 This is set by the .cprestore pseudo-op, and saved in this
415 static offsetT mips_cprestore_offset
= -1;
417 /* This is the register which holds the stack frame, as set by the
418 .frame pseudo-op. This is needed to implement .cprestore. */
419 static int mips_frame_reg
= SP
;
421 /* To output NOP instructions correctly, we need to keep information
422 about the previous two instructions. */
424 /* Whether we are optimizing. The default value of 2 means to remove
425 unneeded NOPs and swap branch instructions when possible. A value
426 of 1 means to not swap branches. A value of 0 means to always
428 static int mips_optimize
= 2;
430 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
431 equivalent to seeing no -g option at all. */
432 static int mips_debug
= 0;
434 /* The previous instruction. */
435 static struct mips_cl_insn prev_insn
;
437 /* The instruction before prev_insn. */
438 static struct mips_cl_insn prev_prev_insn
;
440 /* If we don't want information for prev_insn or prev_prev_insn, we
441 point the insn_mo field at this dummy integer. */
442 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
444 /* Non-zero if prev_insn is valid. */
445 static int prev_insn_valid
;
447 /* The frag for the previous instruction. */
448 static struct frag
*prev_insn_frag
;
450 /* The offset into prev_insn_frag for the previous instruction. */
451 static long prev_insn_where
;
453 /* The reloc type for the previous instruction, if any. */
454 static bfd_reloc_code_real_type prev_insn_reloc_type
;
456 /* The reloc for the previous instruction, if any. */
457 static fixS
*prev_insn_fixp
;
459 /* Non-zero if the previous instruction was in a delay slot. */
460 static int prev_insn_is_delay_slot
;
462 /* Non-zero if the previous instruction was in a .set noreorder. */
463 static int prev_insn_unreordered
;
465 /* Non-zero if the previous instruction uses an extend opcode (if
467 static int prev_insn_extended
;
469 /* Non-zero if the previous previous instruction was in a .set
471 static int prev_prev_insn_unreordered
;
473 /* If this is set, it points to a frag holding nop instructions which
474 were inserted before the start of a noreorder section. If those
475 nops turn out to be unnecessary, the size of the frag can be
477 static fragS
*prev_nop_frag
;
479 /* The number of nop instructions we created in prev_nop_frag. */
480 static int prev_nop_frag_holds
;
482 /* The number of nop instructions that we know we need in
484 static int prev_nop_frag_required
;
486 /* The number of instructions we've seen since prev_nop_frag. */
487 static int prev_nop_frag_since
;
489 /* For ECOFF and ELF, relocations against symbols are done in two
490 parts, with a HI relocation and a LO relocation. Each relocation
491 has only 16 bits of space to store an addend. This means that in
492 order for the linker to handle carries correctly, it must be able
493 to locate both the HI and the LO relocation. This means that the
494 relocations must appear in order in the relocation table.
496 In order to implement this, we keep track of each unmatched HI
497 relocation. We then sort them so that they immediately precede the
498 corresponding LO relocation. */
503 struct mips_hi_fixup
*next
;
506 /* The section this fixup is in. */
510 /* The list of unmatched HI relocs. */
512 static struct mips_hi_fixup
*mips_hi_fixup_list
;
514 /* Map normal MIPS register numbers to mips16 register numbers. */
516 #define X ILLEGAL_REG
517 static const int mips32_to_16_reg_map
[] =
519 X
, X
, 2, 3, 4, 5, 6, 7,
520 X
, X
, X
, X
, X
, X
, X
, X
,
521 0, 1, X
, X
, X
, X
, X
, X
,
522 X
, X
, X
, X
, X
, X
, X
, X
526 /* Map mips16 register numbers to normal MIPS register numbers. */
528 static const unsigned int mips16_to_32_reg_map
[] =
530 16, 17, 2, 3, 4, 5, 6, 7
533 /* Since the MIPS does not have multiple forms of PC relative
534 instructions, we do not have to do relaxing as is done on other
535 platforms. However, we do have to handle GP relative addressing
536 correctly, which turns out to be a similar problem.
538 Every macro that refers to a symbol can occur in (at least) two
539 forms, one with GP relative addressing and one without. For
540 example, loading a global variable into a register generally uses
541 a macro instruction like this:
543 If i can be addressed off the GP register (this is true if it is in
544 the .sbss or .sdata section, or if it is known to be smaller than
545 the -G argument) this will generate the following instruction:
547 This instruction will use a GPREL reloc. If i can not be addressed
548 off the GP register, the following instruction sequence will be used:
551 In this case the first instruction will have a HI16 reloc, and the
552 second reloc will have a LO16 reloc. Both relocs will be against
555 The issue here is that we may not know whether i is GP addressable
556 until after we see the instruction that uses it. Therefore, we
557 want to be able to choose the final instruction sequence only at
558 the end of the assembly. This is similar to the way other
559 platforms choose the size of a PC relative instruction only at the
562 When generating position independent code we do not use GP
563 addressing in quite the same way, but the issue still arises as
564 external symbols and local symbols must be handled differently.
566 We handle these issues by actually generating both possible
567 instruction sequences. The longer one is put in a frag_var with
568 type rs_machine_dependent. We encode what to do with the frag in
569 the subtype field. We encode (1) the number of existing bytes to
570 replace, (2) the number of new bytes to use, (3) the offset from
571 the start of the existing bytes to the first reloc we must generate
572 (that is, the offset is applied from the start of the existing
573 bytes after they are replaced by the new bytes, if any), (4) the
574 offset from the start of the existing bytes to the second reloc,
575 (5) whether a third reloc is needed (the third reloc is always four
576 bytes after the second reloc), and (6) whether to warn if this
577 variant is used (this is sometimes needed if .set nomacro or .set
578 noat is in effect). All these numbers are reasonably small.
580 Generating two instruction sequences must be handled carefully to
581 ensure that delay slots are handled correctly. Fortunately, there
582 are a limited number of cases. When the second instruction
583 sequence is generated, append_insn is directed to maintain the
584 existing delay slot information, so it continues to apply to any
585 code after the second instruction sequence. This means that the
586 second instruction sequence must not impose any requirements not
587 required by the first instruction sequence.
589 These variant frags are then handled in functions called by the
590 machine independent code. md_estimate_size_before_relax returns
591 the final size of the frag. md_convert_frag sets up the final form
592 of the frag. tc_gen_reloc adjust the first reloc and adds a second
594 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
598 | (((reloc1) + 64) << 9) \
599 | (((reloc2) + 64) << 2) \
600 | ((reloc3) ? (1 << 1) : 0) \
602 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
603 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
604 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
605 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
606 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
607 #define RELAX_WARN(i) ((i) & 1)
609 /* For mips16 code, we use an entirely different form of relaxation.
610 mips16 supports two versions of most instructions which take
611 immediate values: a small one which takes some small value, and a
612 larger one which takes a 16 bit value. Since branches also follow
613 this pattern, relaxing these values is required.
615 We can assemble both mips16 and normal MIPS code in a single
616 object. Therefore, we need to support this type of relaxation at
617 the same time that we support the relaxation described above. We
618 use the high bit of the subtype field to distinguish these cases.
620 The information we store for this type of relaxation is the
621 argument code found in the opcode file for this relocation, whether
622 the user explicitly requested a small or extended form, and whether
623 the relocation is in a jump or jal delay slot. That tells us the
624 size of the value, and how it should be stored. We also store
625 whether the fragment is considered to be extended or not. We also
626 store whether this is known to be a branch to a different section,
627 whether we have tried to relax this frag yet, and whether we have
628 ever extended a PC relative fragment because of a shift count. */
629 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
632 | ((small) ? 0x100 : 0) \
633 | ((ext) ? 0x200 : 0) \
634 | ((dslot) ? 0x400 : 0) \
635 | ((jal_dslot) ? 0x800 : 0))
636 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
637 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
638 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
639 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
640 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
641 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
642 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
643 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
644 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
645 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
646 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
647 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
649 /* Prototypes for static functions. */
652 #define internalError() \
653 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
655 #define internalError() as_fatal (_("MIPS internal Error"));
658 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
660 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
661 unsigned int reg
, enum mips_regclass
class));
662 static int reg_needs_delay
PARAMS ((unsigned int));
663 static void mips16_mark_labels
PARAMS ((void));
664 static void append_insn
PARAMS ((char *place
,
665 struct mips_cl_insn
* ip
,
667 bfd_reloc_code_real_type r
,
669 static void mips_no_prev_insn
PARAMS ((int));
670 static void mips_emit_delays
PARAMS ((boolean
));
672 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
673 const char *name
, const char *fmt
,
676 static void macro_build ();
678 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
679 const char *, const char *,
681 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
682 expressionS
* ep
, int regnum
));
683 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
684 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
686 static void load_register
PARAMS ((int *, int, expressionS
*, int));
687 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
688 static void move_register
PARAMS ((int *, int, int));
689 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
690 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
691 #ifdef LOSING_COMPILER
692 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
694 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
695 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
696 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
697 boolean
, boolean
, unsigned long *,
698 boolean
*, unsigned short *));
699 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
700 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
701 static symbolS
*get_symbol
PARAMS ((void));
702 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
703 static void s_align
PARAMS ((int));
704 static void s_change_sec
PARAMS ((int));
705 static void s_cons
PARAMS ((int));
706 static void s_float_cons
PARAMS ((int));
707 static void s_mips_globl
PARAMS ((int));
708 static void s_option
PARAMS ((int));
709 static void s_mipsset
PARAMS ((int));
710 static void s_abicalls
PARAMS ((int));
711 static void s_cpload
PARAMS ((int));
712 static void s_cprestore
PARAMS ((int));
713 static void s_gpword
PARAMS ((int));
714 static void s_cpadd
PARAMS ((int));
715 static void s_insn
PARAMS ((int));
716 static void md_obj_begin
PARAMS ((void));
717 static void md_obj_end
PARAMS ((void));
718 static long get_number
PARAMS ((void));
719 static void s_mips_ent
PARAMS ((int));
720 static void s_mips_end
PARAMS ((int));
721 static void s_mips_frame
PARAMS ((int));
722 static void s_mips_mask
PARAMS ((int));
723 static void s_mips_stab
PARAMS ((int));
724 static void s_mips_weakext
PARAMS ((int));
725 static void s_file
PARAMS ((int));
726 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
727 static const char *mips_isa_to_str
PARAMS ((int));
728 static const char *mips_cpu_to_str
PARAMS ((int));
729 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
730 static void show
PARAMS ((FILE *, char *, int *, int *));
732 /* Return values of my_getSmallExpression() */
745 /* Table and functions used to map between CPU/ISA names, and
746 ISA levels, and CPU numbers. */
750 const char *name
; /* CPU or ISA name. */
751 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
752 int isa
; /* ISA level. */
753 int cpu
; /* CPU number (default CPU if ISA). */
756 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
757 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
758 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
762 The following pseudo-ops from the Kane and Heinrich MIPS book
763 should be defined here, but are currently unsupported: .alias,
764 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
766 The following pseudo-ops from the Kane and Heinrich MIPS book are
767 specific to the type of debugging information being generated, and
768 should be defined by the object format: .aent, .begin, .bend,
769 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
772 The following pseudo-ops from the Kane and Heinrich MIPS book are
773 not MIPS CPU specific, but are also not specific to the object file
774 format. This file is probably the best place to define them, but
775 they are not currently supported: .asm0, .endr, .lab, .repeat,
778 static const pseudo_typeS mips_pseudo_table
[] =
780 /* MIPS specific pseudo-ops. */
781 {"option", s_option
, 0},
782 {"set", s_mipsset
, 0},
783 {"rdata", s_change_sec
, 'r'},
784 {"sdata", s_change_sec
, 's'},
785 {"livereg", s_ignore
, 0},
786 {"abicalls", s_abicalls
, 0},
787 {"cpload", s_cpload
, 0},
788 {"cprestore", s_cprestore
, 0},
789 {"gpword", s_gpword
, 0},
790 {"cpadd", s_cpadd
, 0},
793 /* Relatively generic pseudo-ops that happen to be used on MIPS
795 {"asciiz", stringer
, 1},
796 {"bss", s_change_sec
, 'b'},
799 {"dword", s_cons
, 3},
800 {"weakext", s_mips_weakext
, 0},
802 /* These pseudo-ops are defined in read.c, but must be overridden
803 here for one reason or another. */
804 {"align", s_align
, 0},
806 {"data", s_change_sec
, 'd'},
807 {"double", s_float_cons
, 'd'},
808 {"float", s_float_cons
, 'f'},
809 {"globl", s_mips_globl
, 0},
810 {"global", s_mips_globl
, 0},
811 {"hword", s_cons
, 1},
816 {"short", s_cons
, 1},
817 {"single", s_float_cons
, 'f'},
818 {"stabn", s_mips_stab
, 'n'},
819 {"text", s_change_sec
, 't'},
822 #ifdef MIPS_STABS_ELF
823 { "extern", ecoff_directive_extern
, 0},
829 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
831 /* These pseudo-ops should be defined by the object file format.
832 However, a.out doesn't support them, so we have versions here. */
833 {"aent", s_mips_ent
, 1},
834 {"bgnb", s_ignore
, 0},
835 {"end", s_mips_end
, 0},
836 {"endb", s_ignore
, 0},
837 {"ent", s_mips_ent
, 0},
839 {"fmask", s_mips_mask
, 'F'},
840 {"frame", s_mips_frame
, 0},
841 {"loc", s_ignore
, 0},
842 {"mask", s_mips_mask
, 'R'},
843 {"verstamp", s_ignore
, 0},
847 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
852 pop_insert (mips_pseudo_table
);
853 if (! ECOFF_DEBUGGING
)
854 pop_insert (mips_nonecoff_pseudo_table
);
857 /* Symbols labelling the current insn. */
859 struct insn_label_list
861 struct insn_label_list
*next
;
865 static struct insn_label_list
*insn_labels
;
866 static struct insn_label_list
*free_insn_labels
;
868 static void mips_clear_insn_labels
PARAMS ((void));
871 mips_clear_insn_labels ()
873 register struct insn_label_list
**pl
;
875 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
881 static char *expr_end
;
883 /* Expressions which appear in instructions. These are set by
886 static expressionS imm_expr
;
887 static expressionS offset_expr
;
889 /* Relocs associated with imm_expr and offset_expr. */
891 static bfd_reloc_code_real_type imm_reloc
;
892 static bfd_reloc_code_real_type offset_reloc
;
894 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
896 static boolean imm_unmatched_hi
;
898 /* These are set by mips16_ip if an explicit extension is used. */
900 static boolean mips16_small
, mips16_ext
;
902 #ifdef MIPS_STABS_ELF
903 /* The pdr segment for per procedure frame/regmask info */
909 mips_isa_to_str (isa
)
912 const struct mips_cpu_info
*ci
;
915 ci
= mips_cpu_info_from_isa (isa
);
919 sprintf (s
, "ISA#%d", isa
);
924 mips_cpu_to_str (cpu
)
927 const struct mips_cpu_info
*ci
;
930 ci
= mips_cpu_info_from_cpu (cpu
);
934 sprintf (s
, "CPU#%d", cpu
);
938 /* This function is called once, at assembler startup time. It should
939 set up all the tables, etc. that the MD part of the assembler will need. */
944 register const char *retval
= NULL
;
949 int mips_isa_from_cpu
;
950 int target_cpu_had_mips16
= 0;
951 const struct mips_cpu_info
*ci
;
953 /* GP relative stuff not working for PE */
954 if (strncmp (TARGET_OS
, "pe", 2) == 0
955 && g_switch_value
!= 0)
958 as_bad (_("-G not supported in this configuration."));
963 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
965 a
= xmalloc (sizeof TARGET_CPU
);
966 strcpy (a
, TARGET_CPU
);
967 a
[(sizeof TARGET_CPU
) - 3] = '\0';
971 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
973 target_cpu_had_mips16
= 1;
974 cpu
+= sizeof "mips16" - 1;
977 if (mips_opts
.mips16
< 0)
978 mips_opts
.mips16
= target_cpu_had_mips16
;
980 /* Backward compatibility for historic -mcpu= option. Check for
981 incompatible options, warn if -mcpu is used. */
982 if (mips_cpu
!= CPU_UNKNOWN
983 && mips_arch
!= CPU_UNKNOWN
984 && mips_cpu
!= mips_arch
)
986 as_fatal (_("The -mcpu option can't be used together with -march. "
987 "Use -mtune instead of -mcpu."));
990 if (mips_cpu
!= CPU_UNKNOWN
991 && mips_tune
!= CPU_UNKNOWN
992 && mips_cpu
!= mips_tune
)
994 as_fatal (_("The -mcpu option can't be used together with -mtune. "
995 "Use -march instead of -mcpu."));
998 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1000 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1001 assert (ci
!= NULL
);
1002 mips_arch
= ci
->cpu
;
1003 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1004 "-mtune instead."));
1007 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1008 specified on the command line, or some other value if one was.
1009 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1010 the command line, or will be set otherwise if one was. */
1011 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1013 /* We have to check if the isa is the default isa of arch. Otherwise
1014 we'll get invalid object file headers. */
1015 ci
= mips_cpu_info_from_cpu (mips_arch
);
1016 assert (ci
!= NULL
);
1017 if (mips_opts
.isa
!= ci
->isa
)
1019 /* This really should be an error instead of a warning, but old
1020 compilers only have -mcpu which sets both arch and tune. For
1021 now, we discard arch and preserve tune. */
1022 as_warn (_("The -march option is incompatible to -mipsN and "
1023 "therefore ignored."));
1024 if (mips_tune
== CPU_UNKNOWN
)
1025 mips_tune
= mips_arch
;
1026 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1027 assert (ci
!= NULL
);
1028 mips_arch
= ci
->cpu
;
1031 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1033 /* We have ARCH, we need ISA. */
1034 ci
= mips_cpu_info_from_cpu (mips_arch
);
1035 assert (ci
!= NULL
);
1036 mips_opts
.isa
= ci
->isa
;
1038 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1040 /* We have ISA, we need default ARCH. */
1041 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1042 assert (ci
!= NULL
);
1043 mips_arch
= ci
->cpu
;
1047 /* We need to set both ISA and ARCH from target cpu. */
1048 ci
= mips_cpu_info_from_name (cpu
);
1050 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1051 assert (ci
!= NULL
);
1052 mips_opts
.isa
= ci
->isa
;
1053 mips_arch
= ci
->cpu
;
1056 if (mips_tune
== CPU_UNKNOWN
)
1057 mips_tune
= mips_arch
;
1059 ci
= mips_cpu_info_from_cpu (mips_arch
);
1060 assert (ci
!= NULL
);
1061 mips_isa_from_cpu
= ci
->isa
;
1063 /* End of TARGET_CPU processing, get rid of malloced memory
1072 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1073 as_bad (_("trap exception not supported at ISA 1"));
1075 /* Set the EABI kind based on the ISA before the user gets
1076 to change the ISA with directives. This isn't really
1077 the best, but then neither is basing the abi on the isa. */
1078 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1080 && 0 == strcmp (mips_abi_string
, "eabi"))
1083 /* If they asked for mips1 or mips2 and a cpu that is
1084 mips3 or greater, then mark the object file 32BITMODE. */
1085 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1086 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1087 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1090 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1091 as_warn (_("Could not set architecture and machine"));
1093 file_mips_isa
= mips_opts
.isa
;
1095 op_hash
= hash_new ();
1097 for (i
= 0; i
< NUMOPCODES
;)
1099 const char *name
= mips_opcodes
[i
].name
;
1101 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1104 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1105 mips_opcodes
[i
].name
, retval
);
1106 /* Probably a memory allocation problem? Give up now. */
1107 as_fatal (_("Broken assembler. No assembly attempted."));
1111 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1113 if (!validate_mips_insn (&mips_opcodes
[i
]))
1118 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1121 mips16_op_hash
= hash_new ();
1124 while (i
< bfd_mips16_num_opcodes
)
1126 const char *name
= mips16_opcodes
[i
].name
;
1128 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1130 as_fatal (_("internal: can't hash `%s': %s"),
1131 mips16_opcodes
[i
].name
, retval
);
1134 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1135 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1136 != mips16_opcodes
[i
].match
))
1138 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1139 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1144 while (i
< bfd_mips16_num_opcodes
1145 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1149 as_fatal (_("Broken assembler. No assembly attempted."));
1151 /* We add all the general register names to the symbol table. This
1152 helps us detect invalid uses of them. */
1153 for (i
= 0; i
< 32; i
++)
1157 sprintf (buf
, "$%d", i
);
1158 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1159 &zero_address_frag
));
1161 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1162 &zero_address_frag
));
1163 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1164 &zero_address_frag
));
1165 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1166 &zero_address_frag
));
1167 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1168 &zero_address_frag
));
1169 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1170 &zero_address_frag
));
1171 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1172 &zero_address_frag
));
1173 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1174 &zero_address_frag
));
1176 mips_no_prev_insn (false);
1179 mips_cprmask
[0] = 0;
1180 mips_cprmask
[1] = 0;
1181 mips_cprmask
[2] = 0;
1182 mips_cprmask
[3] = 0;
1184 /* set the default alignment for the text section (2**2) */
1185 record_alignment (text_section
, 2);
1187 if (USE_GLOBAL_POINTER_OPT
)
1188 bfd_set_gp_size (stdoutput
, g_switch_value
);
1190 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1192 /* On a native system, sections must be aligned to 16 byte
1193 boundaries. When configured for an embedded ELF target, we
1195 if (strcmp (TARGET_OS
, "elf") != 0)
1197 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1198 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1199 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1202 /* Create a .reginfo section for register masks and a .mdebug
1203 section for debugging information. */
1211 subseg
= now_subseg
;
1213 /* The ABI says this section should be loaded so that the
1214 running program can access it. However, we don't load it
1215 if we are configured for an embedded target */
1216 flags
= SEC_READONLY
| SEC_DATA
;
1217 if (strcmp (TARGET_OS
, "elf") != 0)
1218 flags
|= SEC_ALLOC
| SEC_LOAD
;
1222 sec
= subseg_new (".reginfo", (subsegT
) 0);
1224 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1225 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1228 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1233 /* The 64-bit ABI uses a .MIPS.options section rather than
1234 .reginfo section. */
1235 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1236 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1237 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1240 /* Set up the option header. */
1242 Elf_Internal_Options opthdr
;
1245 opthdr
.kind
= ODK_REGINFO
;
1246 opthdr
.size
= (sizeof (Elf_External_Options
)
1247 + sizeof (Elf64_External_RegInfo
));
1250 f
= frag_more (sizeof (Elf_External_Options
));
1251 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1252 (Elf_External_Options
*) f
);
1254 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1259 if (ECOFF_DEBUGGING
)
1261 sec
= subseg_new (".mdebug", (subsegT
) 0);
1262 (void) bfd_set_section_flags (stdoutput
, sec
,
1263 SEC_HAS_CONTENTS
| SEC_READONLY
);
1264 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1267 #ifdef MIPS_STABS_ELF
1268 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1269 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1270 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1271 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1274 subseg_set (seg
, subseg
);
1278 if (! ECOFF_DEBUGGING
)
1285 if (! ECOFF_DEBUGGING
)
1293 struct mips_cl_insn insn
;
1295 imm_expr
.X_op
= O_absent
;
1296 imm_reloc
= BFD_RELOC_UNUSED
;
1297 imm_unmatched_hi
= false;
1298 offset_expr
.X_op
= O_absent
;
1299 offset_reloc
= BFD_RELOC_UNUSED
;
1301 if (mips_opts
.mips16
)
1302 mips16_ip (str
, &insn
);
1305 mips_ip (str
, &insn
);
1306 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1307 str
, insn
.insn_opcode
));
1312 as_bad ("%s `%s'", insn_error
, str
);
1316 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1318 if (mips_opts
.mips16
)
1319 mips16_macro (&insn
);
1325 if (imm_expr
.X_op
!= O_absent
)
1326 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1328 else if (offset_expr
.X_op
!= O_absent
)
1329 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1331 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1335 /* See whether instruction IP reads register REG. CLASS is the type
1339 insn_uses_reg (ip
, reg
, class)
1340 struct mips_cl_insn
*ip
;
1342 enum mips_regclass
class;
1344 if (class == MIPS16_REG
)
1346 assert (mips_opts
.mips16
);
1347 reg
= mips16_to_32_reg_map
[reg
];
1348 class = MIPS_GR_REG
;
1351 /* Don't report on general register 0, since it never changes. */
1352 if (class == MIPS_GR_REG
&& reg
== 0)
1355 if (class == MIPS_FP_REG
)
1357 assert (! mips_opts
.mips16
);
1358 /* If we are called with either $f0 or $f1, we must check $f0.
1359 This is not optimal, because it will introduce an unnecessary
1360 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1361 need to distinguish reading both $f0 and $f1 or just one of
1362 them. Note that we don't have to check the other way,
1363 because there is no instruction that sets both $f0 and $f1
1364 and requires a delay. */
1365 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1366 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1367 == (reg
&~ (unsigned) 1)))
1369 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1370 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1371 == (reg
&~ (unsigned) 1)))
1374 else if (! mips_opts
.mips16
)
1376 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1377 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1379 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1380 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1385 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1386 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1387 & MIPS16OP_MASK_RX
)]
1390 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1391 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1392 & MIPS16OP_MASK_RY
)]
1395 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1396 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1397 & MIPS16OP_MASK_MOVE32Z
)]
1400 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1402 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1404 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1406 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1407 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1408 & MIPS16OP_MASK_REGR32
) == reg
)
1415 /* This function returns true if modifying a register requires a
1419 reg_needs_delay (reg
)
1422 unsigned long prev_pinfo
;
1424 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1425 if (! mips_opts
.noreorder
1426 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1427 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1428 || (! gpr_interlocks
1429 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1431 /* A load from a coprocessor or from memory. All load
1432 delays delay the use of general register rt for one
1433 instruction on the r3000. The r6000 and r4000 use
1435 /* Itbl support may require additional care here. */
1436 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1437 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1444 /* Mark instruction labels in mips16 mode. This permits the linker to
1445 handle them specially, such as generating jalx instructions when
1446 needed. We also make them odd for the duration of the assembly, in
1447 order to generate the right sort of code. We will make them even
1448 in the adjust_symtab routine, while leaving them marked. This is
1449 convenient for the debugger and the disassembler. The linker knows
1450 to make them odd again. */
1453 mips16_mark_labels ()
1455 if (mips_opts
.mips16
)
1457 struct insn_label_list
*l
;
1460 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1463 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1464 S_SET_OTHER (l
->label
, STO_MIPS16
);
1466 val
= S_GET_VALUE (l
->label
);
1468 S_SET_VALUE (l
->label
, val
+ 1);
1473 /* Output an instruction. PLACE is where to put the instruction; if
1474 it is NULL, this uses frag_more to get room. IP is the instruction
1475 information. ADDRESS_EXPR is an operand of the instruction to be
1476 used with RELOC_TYPE. */
1479 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1481 struct mips_cl_insn
*ip
;
1482 expressionS
*address_expr
;
1483 bfd_reloc_code_real_type reloc_type
;
1484 boolean unmatched_hi
;
1486 register unsigned long prev_pinfo
, pinfo
;
1491 /* Mark instruction labels in mips16 mode. */
1492 if (mips_opts
.mips16
)
1493 mips16_mark_labels ();
1495 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1496 pinfo
= ip
->insn_mo
->pinfo
;
1498 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1502 /* If the previous insn required any delay slots, see if we need
1503 to insert a NOP or two. There are eight kinds of possible
1504 hazards, of which an instruction can have at most one type.
1505 (1) a load from memory delay
1506 (2) a load from a coprocessor delay
1507 (3) an unconditional branch delay
1508 (4) a conditional branch delay
1509 (5) a move to coprocessor register delay
1510 (6) a load coprocessor register from memory delay
1511 (7) a coprocessor condition code delay
1512 (8) a HI/LO special register delay
1514 There are a lot of optimizations we could do that we don't.
1515 In particular, we do not, in general, reorder instructions.
1516 If you use gcc with optimization, it will reorder
1517 instructions and generally do much more optimization then we
1518 do here; repeating all that work in the assembler would only
1519 benefit hand written assembly code, and does not seem worth
1522 /* This is how a NOP is emitted. */
1523 #define emit_nop() \
1525 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1526 : md_number_to_chars (frag_more (4), 0, 4))
1528 /* The previous insn might require a delay slot, depending upon
1529 the contents of the current insn. */
1530 if (! mips_opts
.mips16
1531 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1532 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1533 && ! cop_interlocks
)
1534 || (! gpr_interlocks
1535 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1537 /* A load from a coprocessor or from memory. All load
1538 delays delay the use of general register rt for one
1539 instruction on the r3000. The r6000 and r4000 use
1541 /* Itbl support may require additional care here. */
1542 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1543 if (mips_optimize
== 0
1544 || insn_uses_reg (ip
,
1545 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1550 else if (! mips_opts
.mips16
1551 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1552 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1553 && ! cop_interlocks
)
1554 || (mips_opts
.isa
== ISA_MIPS1
1555 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1557 /* A generic coprocessor delay. The previous instruction
1558 modified a coprocessor general or control register. If
1559 it modified a control register, we need to avoid any
1560 coprocessor instruction (this is probably not always
1561 required, but it sometimes is). If it modified a general
1562 register, we avoid using that register.
1564 On the r6000 and r4000 loading a coprocessor register
1565 from memory is interlocked, and does not require a delay.
1567 This case is not handled very well. There is no special
1568 knowledge of CP0 handling, and the coprocessors other
1569 than the floating point unit are not distinguished at
1571 /* Itbl support may require additional care here. FIXME!
1572 Need to modify this to include knowledge about
1573 user specified delays! */
1574 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1576 if (mips_optimize
== 0
1577 || insn_uses_reg (ip
,
1578 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1583 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1585 if (mips_optimize
== 0
1586 || insn_uses_reg (ip
,
1587 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1594 /* We don't know exactly what the previous instruction
1595 does. If the current instruction uses a coprocessor
1596 register, we must insert a NOP. If previous
1597 instruction may set the condition codes, and the
1598 current instruction uses them, we must insert two
1600 /* Itbl support may require additional care here. */
1601 if (mips_optimize
== 0
1602 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1603 && (pinfo
& INSN_READ_COND_CODE
)))
1605 else if (pinfo
& INSN_COP
)
1609 else if (! mips_opts
.mips16
1610 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1611 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1612 && ! cop_interlocks
)
1614 /* The previous instruction sets the coprocessor condition
1615 codes, but does not require a general coprocessor delay
1616 (this means it is a floating point comparison
1617 instruction). If this instruction uses the condition
1618 codes, we need to insert a single NOP. */
1619 /* Itbl support may require additional care here. */
1620 if (mips_optimize
== 0
1621 || (pinfo
& INSN_READ_COND_CODE
))
1625 /* If we're fixing up mfhi/mflo for the r7000 and the
1626 previous insn was an mfhi/mflo and the current insn
1627 reads the register that the mfhi/mflo wrote to, then
1630 else if (mips_7000_hilo_fix
1631 && MF_HILO_INSN (prev_pinfo
)
1632 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1639 /* If we're fixing up mfhi/mflo for the r7000 and the
1640 2nd previous insn was an mfhi/mflo and the current insn
1641 reads the register that the mfhi/mflo wrote to, then
1644 else if (mips_7000_hilo_fix
1645 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1646 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1654 else if (prev_pinfo
& INSN_READ_LO
)
1656 /* The previous instruction reads the LO register; if the
1657 current instruction writes to the LO register, we must
1658 insert two NOPS. Some newer processors have interlocks.
1659 Also the tx39's multiply instructions can be exectuted
1660 immediatly after a read from HI/LO (without the delay),
1661 though the tx39's divide insns still do require the
1663 if (! (hilo_interlocks
1664 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1665 && (mips_optimize
== 0
1666 || (pinfo
& INSN_WRITE_LO
)))
1668 /* Most mips16 branch insns don't have a delay slot.
1669 If a read from LO is immediately followed by a branch
1670 to a write to LO we have a read followed by a write
1671 less than 2 insns away. We assume the target of
1672 a branch might be a write to LO, and insert a nop
1673 between a read and an immediately following branch. */
1674 else if (mips_opts
.mips16
1675 && (mips_optimize
== 0
1676 || (pinfo
& MIPS16_INSN_BRANCH
)))
1679 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1681 /* The previous instruction reads the HI register; if the
1682 current instruction writes to the HI register, we must
1683 insert a NOP. Some newer processors have interlocks.
1684 Also the note tx39's multiply above. */
1685 if (! (hilo_interlocks
1686 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1687 && (mips_optimize
== 0
1688 || (pinfo
& INSN_WRITE_HI
)))
1690 /* Most mips16 branch insns don't have a delay slot.
1691 If a read from HI is immediately followed by a branch
1692 to a write to HI we have a read followed by a write
1693 less than 2 insns away. We assume the target of
1694 a branch might be a write to HI, and insert a nop
1695 between a read and an immediately following branch. */
1696 else if (mips_opts
.mips16
1697 && (mips_optimize
== 0
1698 || (pinfo
& MIPS16_INSN_BRANCH
)))
1702 /* If the previous instruction was in a noreorder section, then
1703 we don't want to insert the nop after all. */
1704 /* Itbl support may require additional care here. */
1705 if (prev_insn_unreordered
)
1708 /* There are two cases which require two intervening
1709 instructions: 1) setting the condition codes using a move to
1710 coprocessor instruction which requires a general coprocessor
1711 delay and then reading the condition codes 2) reading the HI
1712 or LO register and then writing to it (except on processors
1713 which have interlocks). If we are not already emitting a NOP
1714 instruction, we must check for these cases compared to the
1715 instruction previous to the previous instruction. */
1716 if ((! mips_opts
.mips16
1717 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1718 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1719 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1720 && (pinfo
& INSN_READ_COND_CODE
)
1721 && ! cop_interlocks
)
1722 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1723 && (pinfo
& INSN_WRITE_LO
)
1724 && ! (hilo_interlocks
1725 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1726 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1727 && (pinfo
& INSN_WRITE_HI
)
1728 && ! (hilo_interlocks
1729 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1734 if (prev_prev_insn_unreordered
)
1737 if (prev_prev_nop
&& nops
== 0)
1740 /* If we are being given a nop instruction, don't bother with
1741 one of the nops we would otherwise output. This will only
1742 happen when a nop instruction is used with mips_optimize set
1745 && ! mips_opts
.noreorder
1746 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1749 /* Now emit the right number of NOP instructions. */
1750 if (nops
> 0 && ! mips_opts
.noreorder
)
1753 unsigned long old_frag_offset
;
1755 struct insn_label_list
*l
;
1757 old_frag
= frag_now
;
1758 old_frag_offset
= frag_now_fix ();
1760 for (i
= 0; i
< nops
; i
++)
1765 listing_prev_line ();
1766 /* We may be at the start of a variant frag. In case we
1767 are, make sure there is enough space for the frag
1768 after the frags created by listing_prev_line. The
1769 argument to frag_grow here must be at least as large
1770 as the argument to all other calls to frag_grow in
1771 this file. We don't have to worry about being in the
1772 middle of a variant frag, because the variants insert
1773 all needed nop instructions themselves. */
1777 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1781 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1782 symbol_set_frag (l
->label
, frag_now
);
1783 val
= (valueT
) frag_now_fix ();
1784 /* mips16 text labels are stored as odd. */
1785 if (mips_opts
.mips16
)
1787 S_SET_VALUE (l
->label
, val
);
1790 #ifndef NO_ECOFF_DEBUGGING
1791 if (ECOFF_DEBUGGING
)
1792 ecoff_fix_loc (old_frag
, old_frag_offset
);
1795 else if (prev_nop_frag
!= NULL
)
1797 /* We have a frag holding nops we may be able to remove. If
1798 we don't need any nops, we can decrease the size of
1799 prev_nop_frag by the size of one instruction. If we do
1800 need some nops, we count them in prev_nops_required. */
1801 if (prev_nop_frag_since
== 0)
1805 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1806 --prev_nop_frag_holds
;
1809 prev_nop_frag_required
+= nops
;
1813 if (prev_prev_nop
== 0)
1815 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1816 --prev_nop_frag_holds
;
1819 ++prev_nop_frag_required
;
1822 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1823 prev_nop_frag
= NULL
;
1825 ++prev_nop_frag_since
;
1827 /* Sanity check: by the time we reach the second instruction
1828 after prev_nop_frag, we should have used up all the nops
1829 one way or another. */
1830 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1834 if (reloc_type
> BFD_RELOC_UNUSED
)
1836 /* We need to set up a variant frag. */
1837 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1838 f
= frag_var (rs_machine_dependent
, 4, 0,
1839 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1840 mips16_small
, mips16_ext
,
1842 & INSN_UNCOND_BRANCH_DELAY
),
1843 (prev_insn_reloc_type
1844 == BFD_RELOC_MIPS16_JMP
)),
1845 make_expr_symbol (address_expr
), (offsetT
) 0,
1848 else if (place
!= NULL
)
1850 else if (mips_opts
.mips16
1852 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1854 /* Make sure there is enough room to swap this instruction with
1855 a following jump instruction. */
1861 if (mips_opts
.mips16
1862 && mips_opts
.noreorder
1863 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1864 as_warn (_("extended instruction in delay slot"));
1870 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1872 if (address_expr
->X_op
== O_constant
)
1877 ip
->insn_opcode
|= address_expr
->X_add_number
;
1880 case BFD_RELOC_LO16
:
1881 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1884 case BFD_RELOC_MIPS_JMP
:
1885 if ((address_expr
->X_add_number
& 3) != 0)
1886 as_bad (_("jump to misaligned address (0x%lx)"),
1887 (unsigned long) address_expr
->X_add_number
);
1888 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1891 case BFD_RELOC_MIPS16_JMP
:
1892 if ((address_expr
->X_add_number
& 3) != 0)
1893 as_bad (_("jump to misaligned address (0x%lx)"),
1894 (unsigned long) address_expr
->X_add_number
);
1896 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1897 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1898 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1901 case BFD_RELOC_16_PCREL
:
1902 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
1905 case BFD_RELOC_16_PCREL_S2
:
1915 /* Don't generate a reloc if we are writing into a variant
1919 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1921 (reloc_type
== BFD_RELOC_16_PCREL
1922 || reloc_type
== BFD_RELOC_16_PCREL_S2
),
1926 struct mips_hi_fixup
*hi_fixup
;
1928 assert (reloc_type
== BFD_RELOC_HI16_S
);
1929 hi_fixup
= ((struct mips_hi_fixup
*)
1930 xmalloc (sizeof (struct mips_hi_fixup
)));
1931 hi_fixup
->fixp
= fixp
;
1932 hi_fixup
->seg
= now_seg
;
1933 hi_fixup
->next
= mips_hi_fixup_list
;
1934 mips_hi_fixup_list
= hi_fixup
;
1940 if (! mips_opts
.mips16
)
1941 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1942 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1944 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1945 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1951 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1954 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1957 /* Update the register mask information. */
1958 if (! mips_opts
.mips16
)
1960 if (pinfo
& INSN_WRITE_GPR_D
)
1961 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1962 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1963 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1964 if (pinfo
& INSN_READ_GPR_S
)
1965 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1966 if (pinfo
& INSN_WRITE_GPR_31
)
1967 mips_gprmask
|= 1 << 31;
1968 if (pinfo
& INSN_WRITE_FPR_D
)
1969 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1970 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1971 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1972 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1973 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1974 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1975 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1976 if (pinfo
& INSN_COP
)
1978 /* We don't keep enough information to sort these cases out.
1979 The itbl support does keep this information however, although
1980 we currently don't support itbl fprmats as part of the cop
1981 instruction. May want to add this support in the future. */
1983 /* Never set the bit for $0, which is always zero. */
1984 mips_gprmask
&= ~1 << 0;
1988 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1989 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1990 & MIPS16OP_MASK_RX
);
1991 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1992 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1993 & MIPS16OP_MASK_RY
);
1994 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1995 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1996 & MIPS16OP_MASK_RZ
);
1997 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1998 mips_gprmask
|= 1 << TREG
;
1999 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2000 mips_gprmask
|= 1 << SP
;
2001 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2002 mips_gprmask
|= 1 << RA
;
2003 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2004 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2005 if (pinfo
& MIPS16_INSN_READ_Z
)
2006 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2007 & MIPS16OP_MASK_MOVE32Z
);
2008 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2009 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2010 & MIPS16OP_MASK_REGR32
);
2013 if (place
== NULL
&& ! mips_opts
.noreorder
)
2015 /* Filling the branch delay slot is more complex. We try to
2016 switch the branch with the previous instruction, which we can
2017 do if the previous instruction does not set up a condition
2018 that the branch tests and if the branch is not itself the
2019 target of any branch. */
2020 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2021 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2023 if (mips_optimize
< 2
2024 /* If we have seen .set volatile or .set nomove, don't
2026 || mips_opts
.nomove
!= 0
2027 /* If we had to emit any NOP instructions, then we
2028 already know we can not swap. */
2030 /* If we don't even know the previous insn, we can not
2032 || ! prev_insn_valid
2033 /* If the previous insn is already in a branch delay
2034 slot, then we can not swap. */
2035 || prev_insn_is_delay_slot
2036 /* If the previous previous insn was in a .set
2037 noreorder, we can't swap. Actually, the MIPS
2038 assembler will swap in this situation. However, gcc
2039 configured -with-gnu-as will generate code like
2045 in which we can not swap the bne and INSN. If gcc is
2046 not configured -with-gnu-as, it does not output the
2047 .set pseudo-ops. We don't have to check
2048 prev_insn_unreordered, because prev_insn_valid will
2049 be 0 in that case. We don't want to use
2050 prev_prev_insn_valid, because we do want to be able
2051 to swap at the start of a function. */
2052 || prev_prev_insn_unreordered
2053 /* If the branch is itself the target of a branch, we
2054 can not swap. We cheat on this; all we check for is
2055 whether there is a label on this instruction. If
2056 there are any branches to anything other than a
2057 label, users must use .set noreorder. */
2058 || insn_labels
!= NULL
2059 /* If the previous instruction is in a variant frag, we
2060 can not do the swap. This does not apply to the
2061 mips16, which uses variant frags for different
2063 || (! mips_opts
.mips16
2064 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2065 /* If the branch reads the condition codes, we don't
2066 even try to swap, because in the sequence
2071 we can not swap, and I don't feel like handling that
2073 || (! mips_opts
.mips16
2074 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2075 && (pinfo
& INSN_READ_COND_CODE
))
2076 /* We can not swap with an instruction that requires a
2077 delay slot, becase the target of the branch might
2078 interfere with that instruction. */
2079 || (! mips_opts
.mips16
2080 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2082 /* Itbl support may require additional care here. */
2083 & (INSN_LOAD_COPROC_DELAY
2084 | INSN_COPROC_MOVE_DELAY
2085 | INSN_WRITE_COND_CODE
)))
2086 || (! (hilo_interlocks
2087 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2091 || (! mips_opts
.mips16
2093 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2094 || (! mips_opts
.mips16
2095 && mips_opts
.isa
== ISA_MIPS1
2096 /* Itbl support may require additional care here. */
2097 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2098 /* We can not swap with a branch instruction. */
2100 & (INSN_UNCOND_BRANCH_DELAY
2101 | INSN_COND_BRANCH_DELAY
2102 | INSN_COND_BRANCH_LIKELY
))
2103 /* We do not swap with a trap instruction, since it
2104 complicates trap handlers to have the trap
2105 instruction be in a delay slot. */
2106 || (prev_pinfo
& INSN_TRAP
)
2107 /* If the branch reads a register that the previous
2108 instruction sets, we can not swap. */
2109 || (! mips_opts
.mips16
2110 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2111 && insn_uses_reg (ip
,
2112 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2115 || (! mips_opts
.mips16
2116 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2117 && insn_uses_reg (ip
,
2118 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2121 || (mips_opts
.mips16
2122 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2123 && insn_uses_reg (ip
,
2124 ((prev_insn
.insn_opcode
2126 & MIPS16OP_MASK_RX
),
2128 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2129 && insn_uses_reg (ip
,
2130 ((prev_insn
.insn_opcode
2132 & MIPS16OP_MASK_RY
),
2134 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2135 && insn_uses_reg (ip
,
2136 ((prev_insn
.insn_opcode
2138 & MIPS16OP_MASK_RZ
),
2140 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2141 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2142 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2143 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2144 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2145 && insn_uses_reg (ip
,
2146 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2149 /* If the branch writes a register that the previous
2150 instruction sets, we can not swap (we know that
2151 branches write only to RD or to $31). */
2152 || (! mips_opts
.mips16
2153 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2154 && (((pinfo
& INSN_WRITE_GPR_D
)
2155 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2156 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2157 || ((pinfo
& INSN_WRITE_GPR_31
)
2158 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2161 || (! mips_opts
.mips16
2162 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2163 && (((pinfo
& INSN_WRITE_GPR_D
)
2164 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2165 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2166 || ((pinfo
& INSN_WRITE_GPR_31
)
2167 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2170 || (mips_opts
.mips16
2171 && (pinfo
& MIPS16_INSN_WRITE_31
)
2172 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2173 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2174 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2176 /* If the branch writes a register that the previous
2177 instruction reads, we can not swap (we know that
2178 branches only write to RD or to $31). */
2179 || (! mips_opts
.mips16
2180 && (pinfo
& INSN_WRITE_GPR_D
)
2181 && insn_uses_reg (&prev_insn
,
2182 ((ip
->insn_opcode
>> OP_SH_RD
)
2185 || (! mips_opts
.mips16
2186 && (pinfo
& INSN_WRITE_GPR_31
)
2187 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2188 || (mips_opts
.mips16
2189 && (pinfo
& MIPS16_INSN_WRITE_31
)
2190 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2191 /* If we are generating embedded PIC code, the branch
2192 might be expanded into a sequence which uses $at, so
2193 we can't swap with an instruction which reads it. */
2194 || (mips_pic
== EMBEDDED_PIC
2195 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2196 /* If the previous previous instruction has a load
2197 delay, and sets a register that the branch reads, we
2199 || (! mips_opts
.mips16
2200 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2201 /* Itbl support may require additional care here. */
2202 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2203 || (! gpr_interlocks
2204 && (prev_prev_insn
.insn_mo
->pinfo
2205 & INSN_LOAD_MEMORY_DELAY
)))
2206 && insn_uses_reg (ip
,
2207 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2210 /* If one instruction sets a condition code and the
2211 other one uses a condition code, we can not swap. */
2212 || ((pinfo
& INSN_READ_COND_CODE
)
2213 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2214 || ((pinfo
& INSN_WRITE_COND_CODE
)
2215 && (prev_pinfo
& INSN_READ_COND_CODE
))
2216 /* If the previous instruction uses the PC, we can not
2218 || (mips_opts
.mips16
2219 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2220 /* If the previous instruction was extended, we can not
2222 || (mips_opts
.mips16
&& prev_insn_extended
)
2223 /* If the previous instruction had a fixup in mips16
2224 mode, we can not swap. This normally means that the
2225 previous instruction was a 4 byte branch anyhow. */
2226 || (mips_opts
.mips16
&& prev_insn_fixp
)
2227 /* If the previous instruction is a sync, sync.l, or
2228 sync.p, we can not swap. */
2229 || (prev_pinfo
& INSN_SYNC
))
2231 /* We could do even better for unconditional branches to
2232 portions of this object file; we could pick up the
2233 instruction at the destination, put it in the delay
2234 slot, and bump the destination address. */
2236 /* Update the previous insn information. */
2237 prev_prev_insn
= *ip
;
2238 prev_insn
.insn_mo
= &dummy_opcode
;
2242 /* It looks like we can actually do the swap. */
2243 if (! mips_opts
.mips16
)
2248 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2249 memcpy (temp
, prev_f
, 4);
2250 memcpy (prev_f
, f
, 4);
2251 memcpy (f
, temp
, 4);
2254 prev_insn_fixp
->fx_frag
= frag_now
;
2255 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2259 fixp
->fx_frag
= prev_insn_frag
;
2260 fixp
->fx_where
= prev_insn_where
;
2268 assert (prev_insn_fixp
== NULL
);
2269 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2270 memcpy (temp
, prev_f
, 2);
2271 memcpy (prev_f
, f
, 2);
2272 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2274 assert (reloc_type
== BFD_RELOC_UNUSED
);
2275 memcpy (f
, temp
, 2);
2279 memcpy (f
, f
+ 2, 2);
2280 memcpy (f
+ 2, temp
, 2);
2284 fixp
->fx_frag
= prev_insn_frag
;
2285 fixp
->fx_where
= prev_insn_where
;
2289 /* Update the previous insn information; leave prev_insn
2291 prev_prev_insn
= *ip
;
2293 prev_insn_is_delay_slot
= 1;
2295 /* If that was an unconditional branch, forget the previous
2296 insn information. */
2297 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2299 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2300 prev_insn
.insn_mo
= &dummy_opcode
;
2303 prev_insn_fixp
= NULL
;
2304 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2305 prev_insn_extended
= 0;
2307 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2309 /* We don't yet optimize a branch likely. What we should do
2310 is look at the target, copy the instruction found there
2311 into the delay slot, and increment the branch to jump to
2312 the next instruction. */
2314 /* Update the previous insn information. */
2315 prev_prev_insn
= *ip
;
2316 prev_insn
.insn_mo
= &dummy_opcode
;
2317 prev_insn_fixp
= NULL
;
2318 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2319 prev_insn_extended
= 0;
2323 /* Update the previous insn information. */
2325 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2327 prev_prev_insn
= prev_insn
;
2330 /* Any time we see a branch, we always fill the delay slot
2331 immediately; since this insn is not a branch, we know it
2332 is not in a delay slot. */
2333 prev_insn_is_delay_slot
= 0;
2335 prev_insn_fixp
= fixp
;
2336 prev_insn_reloc_type
= reloc_type
;
2337 if (mips_opts
.mips16
)
2338 prev_insn_extended
= (ip
->use_extend
2339 || reloc_type
> BFD_RELOC_UNUSED
);
2342 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2343 prev_insn_unreordered
= 0;
2344 prev_insn_frag
= frag_now
;
2345 prev_insn_where
= f
- frag_now
->fr_literal
;
2346 prev_insn_valid
= 1;
2348 else if (place
== NULL
)
2350 /* We need to record a bit of information even when we are not
2351 reordering, in order to determine the base address for mips16
2352 PC relative relocs. */
2353 prev_prev_insn
= prev_insn
;
2355 prev_insn_reloc_type
= reloc_type
;
2356 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2357 prev_insn_unreordered
= 1;
2360 /* We just output an insn, so the next one doesn't have a label. */
2361 mips_clear_insn_labels ();
2363 /* We must ensure that a fixup associated with an unmatched %hi
2364 reloc does not become a variant frag. Otherwise, the
2365 rearrangement of %hi relocs in frob_file may confuse
2369 frag_wane (frag_now
);
2374 /* This function forgets that there was any previous instruction or
2375 label. If PRESERVE is non-zero, it remembers enough information to
2376 know whether nops are needed before a noreorder section. */
2379 mips_no_prev_insn (preserve
)
2384 prev_insn
.insn_mo
= &dummy_opcode
;
2385 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2386 prev_nop_frag
= NULL
;
2387 prev_nop_frag_holds
= 0;
2388 prev_nop_frag_required
= 0;
2389 prev_nop_frag_since
= 0;
2391 prev_insn_valid
= 0;
2392 prev_insn_is_delay_slot
= 0;
2393 prev_insn_unreordered
= 0;
2394 prev_insn_extended
= 0;
2395 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2396 prev_prev_insn_unreordered
= 0;
2397 mips_clear_insn_labels ();
2400 /* This function must be called whenever we turn on noreorder or emit
2401 something other than instructions. It inserts any NOPS which might
2402 be needed by the previous instruction, and clears the information
2403 kept for the previous instructions. The INSNS parameter is true if
2404 instructions are to follow. */
2407 mips_emit_delays (insns
)
2410 if (! mips_opts
.noreorder
)
2415 if ((! mips_opts
.mips16
2416 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2417 && (! cop_interlocks
2418 && (prev_insn
.insn_mo
->pinfo
2419 & (INSN_LOAD_COPROC_DELAY
2420 | INSN_COPROC_MOVE_DELAY
2421 | INSN_WRITE_COND_CODE
))))
2422 || (! hilo_interlocks
2423 && (prev_insn
.insn_mo
->pinfo
2426 || (! mips_opts
.mips16
2428 && (prev_insn
.insn_mo
->pinfo
2429 & INSN_LOAD_MEMORY_DELAY
))
2430 || (! mips_opts
.mips16
2431 && mips_opts
.isa
== ISA_MIPS1
2432 && (prev_insn
.insn_mo
->pinfo
2433 & INSN_COPROC_MEMORY_DELAY
)))
2435 /* Itbl support may require additional care here. */
2437 if ((! mips_opts
.mips16
2438 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2439 && (! cop_interlocks
2440 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2441 || (! hilo_interlocks
2442 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2443 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2446 if (prev_insn_unreordered
)
2449 else if ((! mips_opts
.mips16
2450 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2451 && (! cop_interlocks
2452 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2453 || (! hilo_interlocks
2454 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2455 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2457 /* Itbl support may require additional care here. */
2458 if (! prev_prev_insn_unreordered
)
2464 struct insn_label_list
*l
;
2468 /* Record the frag which holds the nop instructions, so
2469 that we can remove them if we don't need them. */
2470 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2471 prev_nop_frag
= frag_now
;
2472 prev_nop_frag_holds
= nops
;
2473 prev_nop_frag_required
= 0;
2474 prev_nop_frag_since
= 0;
2477 for (; nops
> 0; --nops
)
2482 /* Move on to a new frag, so that it is safe to simply
2483 decrease the size of prev_nop_frag. */
2484 frag_wane (frag_now
);
2488 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2492 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2493 symbol_set_frag (l
->label
, frag_now
);
2494 val
= (valueT
) frag_now_fix ();
2495 /* mips16 text labels are stored as odd. */
2496 if (mips_opts
.mips16
)
2498 S_SET_VALUE (l
->label
, val
);
2503 /* Mark instruction labels in mips16 mode. */
2504 if (mips_opts
.mips16
&& insns
)
2505 mips16_mark_labels ();
2507 mips_no_prev_insn (insns
);
2510 /* Build an instruction created by a macro expansion. This is passed
2511 a pointer to the count of instructions created so far, an
2512 expression, the name of the instruction to build, an operand format
2513 string, and corresponding arguments. */
2517 macro_build (char *place
,
2525 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2534 struct mips_cl_insn insn
;
2535 bfd_reloc_code_real_type r
;
2539 va_start (args
, fmt
);
2545 * If the macro is about to expand into a second instruction,
2546 * print a warning if needed. We need to pass ip as a parameter
2547 * to generate a better warning message here...
2549 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2550 as_warn (_("Macro instruction expanded into multiple instructions"));
2553 *counter
+= 1; /* bump instruction counter */
2555 if (mips_opts
.mips16
)
2557 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2562 r
= BFD_RELOC_UNUSED
;
2563 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2564 assert (insn
.insn_mo
);
2565 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2567 /* Search until we get a match for NAME. */
2570 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2571 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2572 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2573 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2577 assert (insn
.insn_mo
->name
);
2578 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2581 insn
.insn_opcode
= insn
.insn_mo
->match
;
2597 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2601 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2606 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2611 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2616 int tmp
= va_arg (args
, int);
2618 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2619 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2625 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2632 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2636 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2640 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2644 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2648 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2655 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2661 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2662 assert (r
== BFD_RELOC_MIPS_GPREL
2663 || r
== BFD_RELOC_MIPS_LITERAL
2664 || r
== BFD_RELOC_LO16
2665 || r
== BFD_RELOC_MIPS_GOT16
2666 || r
== BFD_RELOC_MIPS_CALL16
2667 || r
== BFD_RELOC_MIPS_GOT_LO16
2668 || r
== BFD_RELOC_MIPS_CALL_LO16
2669 || (ep
->X_op
== O_subtract
2670 && r
== BFD_RELOC_PCREL_LO16
));
2674 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2676 && (ep
->X_op
== O_constant
2677 || (ep
->X_op
== O_symbol
2678 && (r
== BFD_RELOC_HI16_S
2679 || r
== BFD_RELOC_HI16
2680 || r
== BFD_RELOC_MIPS_GOT_HI16
2681 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2682 || (ep
->X_op
== O_subtract
2683 && r
== BFD_RELOC_PCREL_HI16_S
)));
2684 if (ep
->X_op
== O_constant
)
2686 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2688 r
= BFD_RELOC_UNUSED
;
2693 assert (ep
!= NULL
);
2695 * This allows macro() to pass an immediate expression for
2696 * creating short branches without creating a symbol.
2697 * Note that the expression still might come from the assembly
2698 * input, in which case the value is not checked for range nor
2699 * is a relocation entry generated (yuck).
2701 if (ep
->X_op
== O_constant
)
2703 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2707 if (mips_pic
== EMBEDDED_PIC
)
2708 r
= BFD_RELOC_16_PCREL_S2
;
2710 r
= BFD_RELOC_16_PCREL
;
2714 assert (ep
!= NULL
);
2715 r
= BFD_RELOC_MIPS_JMP
;
2719 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2728 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2730 append_insn (place
, &insn
, ep
, r
, false);
2734 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2736 int *counter ATTRIBUTE_UNUSED
;
2742 struct mips_cl_insn insn
;
2743 bfd_reloc_code_real_type r
;
2745 r
= BFD_RELOC_UNUSED
;
2746 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2747 assert (insn
.insn_mo
);
2748 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2750 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2751 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2754 assert (insn
.insn_mo
->name
);
2755 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2758 insn
.insn_opcode
= insn
.insn_mo
->match
;
2759 insn
.use_extend
= false;
2778 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2783 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2787 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2791 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2801 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2808 regno
= va_arg (args
, int);
2809 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2810 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2831 assert (ep
!= NULL
);
2833 if (ep
->X_op
!= O_constant
)
2834 r
= BFD_RELOC_UNUSED
+ c
;
2837 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2838 false, false, &insn
.insn_opcode
,
2839 &insn
.use_extend
, &insn
.extend
);
2841 r
= BFD_RELOC_UNUSED
;
2847 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2854 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2856 append_insn (place
, &insn
, ep
, r
, false);
2860 * Generate a "lui" instruction.
2863 macro_build_lui (place
, counter
, ep
, regnum
)
2869 expressionS high_expr
;
2870 struct mips_cl_insn insn
;
2871 bfd_reloc_code_real_type r
;
2872 CONST
char *name
= "lui";
2873 CONST
char *fmt
= "t,u";
2875 assert (! mips_opts
.mips16
);
2881 high_expr
.X_op
= O_constant
;
2882 high_expr
.X_add_number
= ep
->X_add_number
;
2885 if (high_expr
.X_op
== O_constant
)
2887 /* we can compute the instruction now without a relocation entry */
2888 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
2890 r
= BFD_RELOC_UNUSED
;
2894 assert (ep
->X_op
== O_symbol
);
2895 /* _gp_disp is a special case, used from s_cpload. */
2896 assert (mips_pic
== NO_PIC
2897 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2898 r
= BFD_RELOC_HI16_S
;
2902 * If the macro is about to expand into a second instruction,
2903 * print a warning if needed. We need to pass ip as a parameter
2904 * to generate a better warning message here...
2906 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2907 as_warn (_("Macro instruction expanded into multiple instructions"));
2910 *counter
+= 1; /* bump instruction counter */
2912 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2913 assert (insn
.insn_mo
);
2914 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2915 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2917 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2918 if (r
== BFD_RELOC_UNUSED
)
2920 insn
.insn_opcode
|= high_expr
.X_add_number
;
2921 append_insn (place
, &insn
, NULL
, r
, false);
2924 append_insn (place
, &insn
, &high_expr
, r
, false);
2928 * Generates code to set the $at register to true (one)
2929 * if reg is less than the immediate expression.
2932 set_at (counter
, reg
, unsignedp
)
2937 if (imm_expr
.X_op
== O_constant
2938 && imm_expr
.X_add_number
>= -0x8000
2939 && imm_expr
.X_add_number
< 0x8000)
2940 macro_build ((char *) NULL
, counter
, &imm_expr
,
2941 unsignedp
? "sltiu" : "slti",
2942 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2945 load_register (counter
, AT
, &imm_expr
, 0);
2946 macro_build ((char *) NULL
, counter
, NULL
,
2947 unsignedp
? "sltu" : "slt",
2948 "d,v,t", AT
, reg
, AT
);
2952 /* Warn if an expression is not a constant. */
2955 check_absolute_expr (ip
, ex
)
2956 struct mips_cl_insn
*ip
;
2959 if (ex
->X_op
== O_big
)
2960 as_bad (_("unsupported large constant"));
2961 else if (ex
->X_op
!= O_constant
)
2962 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2965 /* Count the leading zeroes by performing a binary chop. This is a
2966 bulky bit of source, but performance is a LOT better for the
2967 majority of values than a simple loop to count the bits:
2968 for (lcnt = 0; (lcnt < 32); lcnt++)
2969 if ((v) & (1 << (31 - lcnt)))
2971 However it is not code size friendly, and the gain will drop a bit
2972 on certain cached systems.
2974 #define COUNT_TOP_ZEROES(v) \
2975 (((v) & ~0xffff) == 0 \
2976 ? ((v) & ~0xff) == 0 \
2977 ? ((v) & ~0xf) == 0 \
2978 ? ((v) & ~0x3) == 0 \
2979 ? ((v) & ~0x1) == 0 \
2984 : ((v) & ~0x7) == 0 \
2987 : ((v) & ~0x3f) == 0 \
2988 ? ((v) & ~0x1f) == 0 \
2991 : ((v) & ~0x7f) == 0 \
2994 : ((v) & ~0xfff) == 0 \
2995 ? ((v) & ~0x3ff) == 0 \
2996 ? ((v) & ~0x1ff) == 0 \
2999 : ((v) & ~0x7ff) == 0 \
3002 : ((v) & ~0x3fff) == 0 \
3003 ? ((v) & ~0x1fff) == 0 \
3006 : ((v) & ~0x7fff) == 0 \
3009 : ((v) & ~0xffffff) == 0 \
3010 ? ((v) & ~0xfffff) == 0 \
3011 ? ((v) & ~0x3ffff) == 0 \
3012 ? ((v) & ~0x1ffff) == 0 \
3015 : ((v) & ~0x7ffff) == 0 \
3018 : ((v) & ~0x3fffff) == 0 \
3019 ? ((v) & ~0x1fffff) == 0 \
3022 : ((v) & ~0x7fffff) == 0 \
3025 : ((v) & ~0xfffffff) == 0 \
3026 ? ((v) & ~0x3ffffff) == 0 \
3027 ? ((v) & ~0x1ffffff) == 0 \
3030 : ((v) & ~0x7ffffff) == 0 \
3033 : ((v) & ~0x3fffffff) == 0 \
3034 ? ((v) & ~0x1fffffff) == 0 \
3037 : ((v) & ~0x7fffffff) == 0 \
3042 * This routine generates the least number of instructions neccessary to load
3043 * an absolute expression value into a register.
3046 load_register (counter
, reg
, ep
, dbl
)
3053 expressionS hi32
, lo32
;
3055 if (ep
->X_op
!= O_big
)
3057 assert (ep
->X_op
== O_constant
);
3058 if (ep
->X_add_number
< 0x8000
3059 && (ep
->X_add_number
>= 0
3060 || (ep
->X_add_number
>= -0x8000
3063 || sizeof (ep
->X_add_number
) > 4))))
3065 /* We can handle 16 bit signed values with an addiu to
3066 $zero. No need to ever use daddiu here, since $zero and
3067 the result are always correct in 32 bit mode. */
3068 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3069 (int) BFD_RELOC_LO16
);
3072 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3074 /* We can handle 16 bit unsigned values with an ori to
3076 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3077 (int) BFD_RELOC_LO16
);
3080 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3081 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3082 == ~ (offsetT
) 0x7fffffff))
3085 || sizeof (ep
->X_add_number
) > 4
3086 || (ep
->X_add_number
& 0x80000000) == 0))
3087 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3088 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3091 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3092 == ~ (offsetT
) 0xffffffff)))
3094 /* 32 bit values require an lui. */
3095 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3096 (int) BFD_RELOC_HI16
);
3097 if ((ep
->X_add_number
& 0xffff) != 0)
3098 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3099 (int) BFD_RELOC_LO16
);
3104 /* The value is larger than 32 bits. */
3106 if (HAVE_32BIT_GPRS
)
3108 as_bad (_("Number larger than 32 bits"));
3109 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3110 (int) BFD_RELOC_LO16
);
3114 if (ep
->X_op
!= O_big
)
3117 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3118 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3119 hi32
.X_add_number
&= 0xffffffff;
3121 lo32
.X_add_number
&= 0xffffffff;
3125 assert (ep
->X_add_number
> 2);
3126 if (ep
->X_add_number
== 3)
3127 generic_bignum
[3] = 0;
3128 else if (ep
->X_add_number
> 4)
3129 as_bad (_("Number larger than 64 bits"));
3130 lo32
.X_op
= O_constant
;
3131 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3132 hi32
.X_op
= O_constant
;
3133 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3136 if (hi32
.X_add_number
== 0)
3141 unsigned long hi
, lo
;
3143 if (hi32
.X_add_number
== 0xffffffff)
3145 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3147 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3148 reg
, 0, (int) BFD_RELOC_LO16
);
3151 if (lo32
.X_add_number
& 0x80000000)
3153 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3154 (int) BFD_RELOC_HI16
);
3155 if (lo32
.X_add_number
& 0xffff)
3156 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3157 reg
, reg
, (int) BFD_RELOC_LO16
);
3162 /* Check for 16bit shifted constant. We know that hi32 is
3163 non-zero, so start the mask on the first bit of the hi32
3168 unsigned long himask
, lomask
;
3172 himask
= 0xffff >> (32 - shift
);
3173 lomask
= (0xffff << shift
) & 0xffffffff;
3177 himask
= 0xffff << (shift
- 32);
3180 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3181 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3185 tmp
.X_op
= O_constant
;
3187 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3188 | (lo32
.X_add_number
>> shift
));
3190 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3191 macro_build ((char *) NULL
, counter
, &tmp
,
3192 "ori", "t,r,i", reg
, 0,
3193 (int) BFD_RELOC_LO16
);
3194 macro_build ((char *) NULL
, counter
, NULL
,
3195 (shift
>= 32) ? "dsll32" : "dsll",
3197 (shift
>= 32) ? shift
- 32 : shift
);
3202 while (shift
<= (64 - 16));
3204 /* Find the bit number of the lowest one bit, and store the
3205 shifted value in hi/lo. */
3206 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3207 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3211 while ((lo
& 1) == 0)
3216 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3222 while ((hi
& 1) == 0)
3231 /* Optimize if the shifted value is a (power of 2) - 1. */
3232 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3233 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3235 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3240 /* This instruction will set the register to be all
3242 tmp
.X_op
= O_constant
;
3243 tmp
.X_add_number
= (offsetT
) -1;
3244 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3245 reg
, 0, (int) BFD_RELOC_LO16
);
3249 macro_build ((char *) NULL
, counter
, NULL
,
3250 (bit
>= 32) ? "dsll32" : "dsll",
3252 (bit
>= 32) ? bit
- 32 : bit
);
3254 macro_build ((char *) NULL
, counter
, NULL
,
3255 (shift
>= 32) ? "dsrl32" : "dsrl",
3257 (shift
>= 32) ? shift
- 32 : shift
);
3262 /* Sign extend hi32 before calling load_register, because we can
3263 generally get better code when we load a sign extended value. */
3264 if ((hi32
.X_add_number
& 0x80000000) != 0)
3265 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3266 load_register (counter
, reg
, &hi32
, 0);
3269 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3273 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3282 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3284 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3285 (int) BFD_RELOC_HI16
);
3286 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3293 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3298 mid16
.X_add_number
>>= 16;
3299 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3300 freg
, (int) BFD_RELOC_LO16
);
3301 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3305 if ((lo32
.X_add_number
& 0xffff) != 0)
3306 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3307 (int) BFD_RELOC_LO16
);
3310 /* Load an address into a register. */
3313 load_address (counter
, reg
, ep
)
3320 if (ep
->X_op
!= O_constant
3321 && ep
->X_op
!= O_symbol
)
3323 as_bad (_("expression too complex"));
3324 ep
->X_op
= O_constant
;
3327 if (ep
->X_op
== O_constant
)
3329 load_register (counter
, reg
, ep
, 0);
3333 if (mips_pic
== NO_PIC
)
3335 /* If this is a reference to a GP relative symbol, we want
3336 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3338 lui $reg,<sym> (BFD_RELOC_HI16_S)
3339 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3340 If we have an addend, we always use the latter form. */
3341 if ((valueT
) ep
->X_add_number
> MAX_GPREL_OFFSET
3342 || nopic_need_relax (ep
->X_add_symbol
, 1))
3347 macro_build ((char *) NULL
, counter
, ep
,
3348 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3349 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3350 p
= frag_var (rs_machine_dependent
, 8, 0,
3351 RELAX_ENCODE (4, 8, 0, 4, 0,
3352 mips_opts
.warn_about_macros
),
3353 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3355 macro_build_lui (p
, counter
, ep
, reg
);
3358 macro_build (p
, counter
, ep
,
3359 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3360 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3362 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3366 /* If this is a reference to an external symbol, we want
3367 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3369 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3371 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3372 If there is a constant, it must be added in after. */
3373 ex
.X_add_number
= ep
->X_add_number
;
3374 ep
->X_add_number
= 0;
3376 macro_build ((char *) NULL
, counter
, ep
,
3377 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3378 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3379 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3380 p
= frag_var (rs_machine_dependent
, 4, 0,
3381 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3382 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3383 macro_build (p
, counter
, ep
,
3384 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3385 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3386 if (ex
.X_add_number
!= 0)
3388 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3389 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3390 ex
.X_op
= O_constant
;
3391 macro_build ((char *) NULL
, counter
, &ex
,
3392 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3393 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3396 else if (mips_pic
== SVR4_PIC
)
3401 /* This is the large GOT case. If this is a reference to an
3402 external symbol, we want
3403 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3405 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3406 Otherwise, for a reference to a local symbol, we want
3407 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3409 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3410 If there is a constant, it must be added in after. */
3411 ex
.X_add_number
= ep
->X_add_number
;
3412 ep
->X_add_number
= 0;
3413 if (reg_needs_delay (GP
))
3418 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3419 (int) BFD_RELOC_MIPS_GOT_HI16
);
3420 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3421 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3422 "d,v,t", reg
, reg
, GP
);
3423 macro_build ((char *) NULL
, counter
, ep
,
3424 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3425 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3426 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3427 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3428 mips_opts
.warn_about_macros
),
3429 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3432 /* We need a nop before loading from $gp. This special
3433 check is required because the lui which starts the main
3434 instruction stream does not refer to $gp, and so will not
3435 insert the nop which may be required. */
3436 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3439 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3440 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3442 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3444 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3445 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3446 if (ex
.X_add_number
!= 0)
3448 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3449 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3450 ex
.X_op
= O_constant
;
3451 macro_build ((char *) NULL
, counter
, &ex
,
3452 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3453 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3456 else if (mips_pic
== EMBEDDED_PIC
)
3459 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3461 macro_build ((char *) NULL
, counter
, ep
,
3462 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3463 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3469 /* Move the contents of register SOURCE into register DEST. */
3472 move_register (counter
, dest
, source
)
3477 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3478 HAVE_32BIT_GPRS
? "addu" : "daddu",
3479 "d,v,t", dest
, source
, 0);
3484 * This routine implements the seemingly endless macro or synthesized
3485 * instructions and addressing modes in the mips assembly language. Many
3486 * of these macros are simple and are similar to each other. These could
3487 * probably be handled by some kind of table or grammer aproach instead of
3488 * this verbose method. Others are not simple macros but are more like
3489 * optimizing code generation.
3490 * One interesting optimization is when several store macros appear
3491 * consecutivly that would load AT with the upper half of the same address.
3492 * The ensuing load upper instructions are ommited. This implies some kind
3493 * of global optimization. We currently only optimize within a single macro.
3494 * For many of the load and store macros if the address is specified as a
3495 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3496 * first load register 'at' with zero and use it as the base register. The
3497 * mips assembler simply uses register $zero. Just one tiny optimization
3502 struct mips_cl_insn
*ip
;
3504 register int treg
, sreg
, dreg
, breg
;
3520 bfd_reloc_code_real_type r
;
3522 int hold_mips_optimize
;
3524 assert (! mips_opts
.mips16
);
3526 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3527 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3528 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3529 mask
= ip
->insn_mo
->mask
;
3531 expr1
.X_op
= O_constant
;
3532 expr1
.X_op_symbol
= NULL
;
3533 expr1
.X_add_symbol
= NULL
;
3534 expr1
.X_add_number
= 1;
3546 mips_emit_delays (true);
3547 ++mips_opts
.noreorder
;
3548 mips_any_noreorder
= 1;
3550 expr1
.X_add_number
= 8;
3551 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3553 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3555 move_register (&icnt
, dreg
, sreg
);
3556 macro_build ((char *) NULL
, &icnt
, NULL
,
3557 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3559 --mips_opts
.noreorder
;
3580 if (imm_expr
.X_op
== O_constant
3581 && imm_expr
.X_add_number
>= -0x8000
3582 && imm_expr
.X_add_number
< 0x8000)
3584 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3585 (int) BFD_RELOC_LO16
);
3588 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3589 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3608 if (imm_expr
.X_op
== O_constant
3609 && imm_expr
.X_add_number
>= 0
3610 && imm_expr
.X_add_number
< 0x10000)
3612 if (mask
!= M_NOR_I
)
3613 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3614 sreg
, (int) BFD_RELOC_LO16
);
3617 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3618 treg
, sreg
, (int) BFD_RELOC_LO16
);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3625 load_register (&icnt
, AT
, &imm_expr
, 0);
3626 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3643 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3645 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3649 load_register (&icnt
, AT
, &imm_expr
, 0);
3650 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3659 likely
? "bgezl" : "bgez",
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3666 likely
? "blezl" : "blez",
3670 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3672 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3678 /* check for > max integer */
3679 maxnum
= 0x7fffffff;
3680 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3687 if (imm_expr
.X_op
== O_constant
3688 && imm_expr
.X_add_number
>= maxnum
3689 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3692 /* result is always false */
3696 as_warn (_("Branch %s is always false (nop)"),
3698 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3703 as_warn (_("Branch likely %s is always false"),
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3710 if (imm_expr
.X_op
!= O_constant
)
3711 as_bad (_("Unsupported large constant"));
3712 imm_expr
.X_add_number
++;
3716 if (mask
== M_BGEL_I
)
3718 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3720 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3721 likely
? "bgezl" : "bgez", "s,p", sreg
);
3724 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3727 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3730 maxnum
= 0x7fffffff;
3731 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3738 maxnum
= - maxnum
- 1;
3739 if (imm_expr
.X_op
== O_constant
3740 && imm_expr
.X_add_number
<= maxnum
3741 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3744 /* result is always true */
3745 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3749 set_at (&icnt
, sreg
, 0);
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3762 likely
? "beql" : "beq", "s,t,p", 0, treg
);
3765 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3767 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3768 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3776 && imm_expr
.X_op
== O_constant
3777 && imm_expr
.X_add_number
== 0xffffffff))
3779 if (imm_expr
.X_op
!= O_constant
)
3780 as_bad (_("Unsupported large constant"));
3781 imm_expr
.X_add_number
++;
3785 if (mask
== M_BGEUL_I
)
3787 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3789 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3792 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3795 set_at (&icnt
, sreg
, 1);
3796 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3797 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3806 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "bltzl" : "bltz", "s,p", treg
);
3815 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3816 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3817 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3826 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3831 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3834 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "blezl" : "blez", "s,p", sreg
);
3848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3849 likely
? "bgezl" : "bgez", "s,p", treg
);
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3853 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3854 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3860 maxnum
= 0x7fffffff;
3861 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3868 if (imm_expr
.X_op
== O_constant
3869 && imm_expr
.X_add_number
>= maxnum
3870 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3872 if (imm_expr
.X_op
!= O_constant
)
3873 as_bad (_("Unsupported large constant"));
3874 imm_expr
.X_add_number
++;
3878 if (mask
== M_BLTL_I
)
3880 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3882 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3883 likely
? "bltzl" : "bltz", "s,p", sreg
);
3886 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3888 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3889 likely
? "blezl" : "blez", "s,p", sreg
);
3892 set_at (&icnt
, sreg
, 0);
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3894 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
3908 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3910 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3911 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3919 && imm_expr
.X_op
== O_constant
3920 && imm_expr
.X_add_number
== 0xffffffff))
3922 if (imm_expr
.X_op
!= O_constant
)
3923 as_bad (_("Unsupported large constant"));
3924 imm_expr
.X_add_number
++;
3928 if (mask
== M_BLTUL_I
)
3930 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3932 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3934 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3935 likely
? "beql" : "beq",
3939 set_at (&icnt
, sreg
, 1);
3940 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3941 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3950 likely
? "bltzl" : "bltz", "s,p", sreg
);
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3956 likely
? "bgtzl" : "bgtz", "s,p", treg
);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3960 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3961 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3972 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
3975 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3977 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3978 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3993 as_warn (_("Divide by zero."));
3995 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3997 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4001 mips_emit_delays (true);
4002 ++mips_opts
.noreorder
;
4003 mips_any_noreorder
= 1;
4006 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4007 macro_build ((char *) NULL
, &icnt
, NULL
,
4008 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4012 expr1
.X_add_number
= 8;
4013 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4014 macro_build ((char *) NULL
, &icnt
, NULL
,
4015 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4016 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4018 expr1
.X_add_number
= -1;
4019 macro_build ((char *) NULL
, &icnt
, &expr1
,
4020 dbl
? "daddiu" : "addiu",
4021 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4022 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4023 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4026 expr1
.X_add_number
= 1;
4027 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4028 (int) BFD_RELOC_LO16
);
4029 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4034 expr1
.X_add_number
= 0x80000000;
4035 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4036 (int) BFD_RELOC_HI16
);
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4041 /* We want to close the noreorder block as soon as possible, so
4042 that later insns are available for delay slot filling. */
4043 --mips_opts
.noreorder
;
4047 expr1
.X_add_number
= 8;
4048 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4051 /* We want to close the noreorder block as soon as possible, so
4052 that later insns are available for delay slot filling. */
4053 --mips_opts
.noreorder
;
4055 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4057 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4096 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4098 as_warn (_("Divide by zero."));
4100 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4105 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4107 if (strcmp (s2
, "mflo") == 0)
4108 move_register (&icnt
, dreg
, sreg
);
4110 move_register (&icnt
, dreg
, 0);
4113 if (imm_expr
.X_op
== O_constant
4114 && imm_expr
.X_add_number
== -1
4115 && s
[strlen (s
) - 1] != 'u')
4117 if (strcmp (s2
, "mflo") == 0)
4119 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4123 move_register (&icnt
, dreg
, 0);
4127 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4128 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4129 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4148 mips_emit_delays (true);
4149 ++mips_opts
.noreorder
;
4150 mips_any_noreorder
= 1;
4153 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4154 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4155 /* We want to close the noreorder block as soon as possible, so
4156 that later insns are available for delay slot filling. */
4157 --mips_opts
.noreorder
;
4161 expr1
.X_add_number
= 8;
4162 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4163 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4165 /* We want to close the noreorder block as soon as possible, so
4166 that later insns are available for delay slot filling. */
4167 --mips_opts
.noreorder
;
4168 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4170 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4176 /* Load the address of a symbol into a register. If breg is not
4177 zero, we then add a base register to it. */
4179 /* When generating embedded PIC code, we permit expressions of
4182 where bar is an address in the current section. These are used
4183 when getting the addresses of functions. We don't permit
4184 X_add_number to be non-zero, because if the symbol is
4185 external the relaxing code needs to know that any addend is
4186 purely the offset to X_op_symbol. */
4187 if (mips_pic
== EMBEDDED_PIC
4188 && offset_expr
.X_op
== O_subtract
4189 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4190 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4191 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4193 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4197 && (offset_expr
.X_add_number
== 0
4198 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4201 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4202 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4203 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4204 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4208 if (offset_expr
.X_op
!= O_symbol
4209 && offset_expr
.X_op
!= O_constant
)
4211 as_bad (_("expression too complex"));
4212 offset_expr
.X_op
= O_constant
;
4226 if (offset_expr
.X_op
== O_constant
)
4227 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4228 else if (mips_pic
== NO_PIC
)
4230 /* If this is a reference to an GP relative symbol, we want
4231 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4233 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4234 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4235 If we have a constant, we need two instructions anyhow,
4236 so we may as well always use the latter form. */
4237 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
4238 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4244 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4245 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4246 p
= frag_var (rs_machine_dependent
, 8, 0,
4247 RELAX_ENCODE (4, 8, 0, 4, 0,
4248 mips_opts
.warn_about_macros
),
4249 offset_expr
.X_add_symbol
, (offsetT
) 0,
4252 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4255 macro_build (p
, &icnt
, &offset_expr
,
4256 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4257 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4259 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4261 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4263 /* If this is a reference to an external symbol, and there
4264 is no constant, we want
4265 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4266 or if tempreg is PIC_CALL_REG
4267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4268 For a local symbol, we want
4269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4271 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4273 If we have a small constant, and this is a reference to
4274 an external symbol, we want
4275 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4277 addiu $tempreg,$tempreg,<constant>
4278 For a local symbol, we want the same instruction
4279 sequence, but we output a BFD_RELOC_LO16 reloc on the
4282 If we have a large constant, and this is a reference to
4283 an external symbol, we want
4284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4285 lui $at,<hiconstant>
4286 addiu $at,$at,<loconstant>
4287 addu $tempreg,$tempreg,$at
4288 For a local symbol, we want the same instruction
4289 sequence, but we output a BFD_RELOC_LO16 reloc on the
4290 addiu instruction. */
4291 expr1
.X_add_number
= offset_expr
.X_add_number
;
4292 offset_expr
.X_add_number
= 0;
4294 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4295 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4296 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4298 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4299 if (expr1
.X_add_number
== 0)
4307 /* We're going to put in an addu instruction using
4308 tempreg, so we may as well insert the nop right
4310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4314 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4315 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4317 ? mips_opts
.warn_about_macros
4319 offset_expr
.X_add_symbol
, (offsetT
) 0,
4323 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4326 macro_build (p
, &icnt
, &expr1
,
4327 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4328 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4329 /* FIXME: If breg == 0, and the next instruction uses
4330 $tempreg, then if this variant case is used an extra
4331 nop will be generated. */
4333 else if (expr1
.X_add_number
>= -0x8000
4334 && expr1
.X_add_number
< 0x8000)
4336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4338 macro_build ((char *) NULL
, &icnt
, &expr1
,
4339 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4340 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4341 (void) frag_var (rs_machine_dependent
, 0, 0,
4342 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4343 offset_expr
.X_add_symbol
, (offsetT
) 0,
4350 /* If we are going to add in a base register, and the
4351 target register and the base register are the same,
4352 then we are using AT as a temporary register. Since
4353 we want to load the constant into AT, we add our
4354 current AT (from the global offset table) and the
4355 register into the register now, and pretend we were
4356 not using a base register. */
4361 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4363 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4364 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4365 "d,v,t", treg
, AT
, breg
);
4371 /* Set mips_optimize around the lui instruction to avoid
4372 inserting an unnecessary nop after the lw. */
4373 hold_mips_optimize
= mips_optimize
;
4375 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4376 mips_optimize
= hold_mips_optimize
;
4378 macro_build ((char *) NULL
, &icnt
, &expr1
,
4379 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4380 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4382 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4383 "d,v,t", tempreg
, tempreg
, AT
);
4384 (void) frag_var (rs_machine_dependent
, 0, 0,
4385 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4386 offset_expr
.X_add_symbol
, (offsetT
) 0,
4391 else if (mips_pic
== SVR4_PIC
)
4394 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4395 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4397 /* This is the large GOT case. If this is a reference to an
4398 external symbol, and there is no constant, we want
4399 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4400 addu $tempreg,$tempreg,$gp
4401 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4402 or if tempreg is PIC_CALL_REG
4403 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4404 addu $tempreg,$tempreg,$gp
4405 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4406 For a local symbol, we want
4407 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4409 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4411 If we have a small constant, and this is a reference to
4412 an external symbol, we want
4413 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4414 addu $tempreg,$tempreg,$gp
4415 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4417 addiu $tempreg,$tempreg,<constant>
4418 For a local symbol, we want
4419 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4421 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4423 If we have a large constant, and this is a reference to
4424 an external symbol, we want
4425 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4426 addu $tempreg,$tempreg,$gp
4427 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4428 lui $at,<hiconstant>
4429 addiu $at,$at,<loconstant>
4430 addu $tempreg,$tempreg,$at
4431 For a local symbol, we want
4432 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4433 lui $at,<hiconstant>
4434 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4435 addu $tempreg,$tempreg,$at
4437 expr1
.X_add_number
= offset_expr
.X_add_number
;
4438 offset_expr
.X_add_number
= 0;
4440 if (reg_needs_delay (GP
))
4444 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4446 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4447 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4450 tempreg
, lui_reloc_type
);
4451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4452 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4453 "d,v,t", tempreg
, tempreg
, GP
);
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4456 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4457 if (expr1
.X_add_number
== 0)
4465 /* We're going to put in an addu instruction using
4466 tempreg, so we may as well insert the nop right
4468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4473 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4474 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4477 ? mips_opts
.warn_about_macros
4479 offset_expr
.X_add_symbol
, (offsetT
) 0,
4482 else if (expr1
.X_add_number
>= -0x8000
4483 && expr1
.X_add_number
< 0x8000)
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4487 macro_build ((char *) NULL
, &icnt
, &expr1
,
4488 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4489 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4491 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4492 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4494 ? mips_opts
.warn_about_macros
4496 offset_expr
.X_add_symbol
, (offsetT
) 0,
4503 /* If we are going to add in a base register, and the
4504 target register and the base register are the same,
4505 then we are using AT as a temporary register. Since
4506 we want to load the constant into AT, we add our
4507 current AT (from the global offset table) and the
4508 register into the register now, and pretend we were
4509 not using a base register. */
4517 assert (tempreg
== AT
);
4518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4521 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4522 "d,v,t", treg
, AT
, breg
);
4527 /* Set mips_optimize around the lui instruction to avoid
4528 inserting an unnecessary nop after the lw. */
4529 hold_mips_optimize
= mips_optimize
;
4531 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4532 mips_optimize
= hold_mips_optimize
;
4534 macro_build ((char *) NULL
, &icnt
, &expr1
,
4535 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4536 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4538 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4539 "d,v,t", dreg
, dreg
, AT
);
4541 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4542 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4545 ? mips_opts
.warn_about_macros
4547 offset_expr
.X_add_symbol
, (offsetT
) 0,
4555 /* This is needed because this instruction uses $gp, but
4556 the first instruction on the main stream does not. */
4557 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4560 macro_build (p
, &icnt
, &offset_expr
,
4562 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4564 if (expr1
.X_add_number
>= -0x8000
4565 && expr1
.X_add_number
< 0x8000)
4567 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4569 macro_build (p
, &icnt
, &expr1
,
4570 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4571 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4572 /* FIXME: If add_number is 0, and there was no base
4573 register, the external symbol case ended with a load,
4574 so if the symbol turns out to not be external, and
4575 the next instruction uses tempreg, an unnecessary nop
4576 will be inserted. */
4582 /* We must add in the base register now, as in the
4583 external symbol case. */
4584 assert (tempreg
== AT
);
4585 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4587 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4588 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4589 "d,v,t", treg
, AT
, breg
);
4592 /* We set breg to 0 because we have arranged to add
4593 it in in both cases. */
4597 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4599 macro_build (p
, &icnt
, &expr1
,
4600 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4601 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4603 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4604 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4605 "d,v,t", tempreg
, tempreg
, AT
);
4609 else if (mips_pic
== EMBEDDED_PIC
)
4612 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4614 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4615 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4616 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4623 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4624 "d,v,t", treg
, tempreg
, breg
);
4632 /* The j instruction may not be used in PIC code, since it
4633 requires an absolute address. We convert it to a b
4635 if (mips_pic
== NO_PIC
)
4636 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4638 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4641 /* The jal instructions must be handled as macros because when
4642 generating PIC code they expand to multi-instruction
4643 sequences. Normally they are simple instructions. */
4648 if (mips_pic
== NO_PIC
4649 || mips_pic
== EMBEDDED_PIC
)
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4652 else if (mips_pic
== SVR4_PIC
)
4654 if (sreg
!= PIC_CALL_REG
)
4655 as_warn (_("MIPS PIC call to register other than $25"));
4657 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4659 if (mips_cprestore_offset
< 0)
4660 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4663 expr1
.X_add_number
= mips_cprestore_offset
;
4664 macro_build ((char *) NULL
, &icnt
, &expr1
,
4665 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4666 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4675 if (mips_pic
== NO_PIC
)
4676 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4677 else if (mips_pic
== SVR4_PIC
)
4679 /* If this is a reference to an external symbol, and we are
4680 using a small GOT, we want
4681 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4685 lw $gp,cprestore($sp)
4686 The cprestore value is set using the .cprestore
4687 pseudo-op. If we are using a big GOT, we want
4688 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4690 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4694 lw $gp,cprestore($sp)
4695 If the symbol is not external, we want
4696 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4698 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4701 lw $gp,cprestore($sp) */
4705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4706 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4707 "t,o(b)", PIC_CALL_REG
,
4708 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4711 p
= frag_var (rs_machine_dependent
, 4, 0,
4712 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4713 offset_expr
.X_add_symbol
, (offsetT
) 0,
4720 if (reg_needs_delay (GP
))
4724 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4725 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4727 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4728 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4730 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4731 "t,o(b)", PIC_CALL_REG
,
4732 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4733 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4735 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4736 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4738 offset_expr
.X_add_symbol
, (offsetT
) 0,
4742 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4745 macro_build (p
, &icnt
, &offset_expr
,
4746 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4747 "t,o(b)", PIC_CALL_REG
,
4748 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4750 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4753 macro_build (p
, &icnt
, &offset_expr
,
4754 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4755 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4756 (int) BFD_RELOC_LO16
);
4757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4758 "jalr", "s", PIC_CALL_REG
);
4759 if (mips_cprestore_offset
< 0)
4760 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4763 if (mips_opts
.noreorder
)
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4766 expr1
.X_add_number
= mips_cprestore_offset
;
4767 macro_build ((char *) NULL
, &icnt
, &expr1
,
4768 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4769 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4773 else if (mips_pic
== EMBEDDED_PIC
)
4775 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4776 /* The linker may expand the call to a longer sequence which
4777 uses $at, so we must break rather than return. */
4802 /* Itbl support may require additional care here. */
4807 /* Itbl support may require additional care here. */
4812 /* Itbl support may require additional care here. */
4817 /* Itbl support may require additional care here. */
4829 if (mips_arch
== CPU_R4650
)
4831 as_bad (_("opcode not supported on this processor"));
4835 /* Itbl support may require additional care here. */
4840 /* Itbl support may require additional care here. */
4845 /* Itbl support may require additional care here. */
4865 if (breg
== treg
|| coproc
|| lr
)
4887 /* Itbl support may require additional care here. */
4892 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4902 /* Itbl support may require additional care here. */
4918 if (mips_arch
== CPU_R4650
)
4920 as_bad (_("opcode not supported on this processor"));
4925 /* Itbl support may require additional care here. */
4929 /* Itbl support may require additional care here. */
4934 /* Itbl support may require additional care here. */
4946 /* Itbl support may require additional care here. */
4947 if (mask
== M_LWC1_AB
4948 || mask
== M_SWC1_AB
4949 || mask
== M_LDC1_AB
4950 || mask
== M_SDC1_AB
4959 if (offset_expr
.X_op
!= O_constant
4960 && offset_expr
.X_op
!= O_symbol
)
4962 as_bad (_("expression too complex"));
4963 offset_expr
.X_op
= O_constant
;
4966 /* A constant expression in PIC code can be handled just as it
4967 is in non PIC code. */
4968 if (mips_pic
== NO_PIC
4969 || offset_expr
.X_op
== O_constant
)
4971 /* If this is a reference to a GP relative symbol, and there
4972 is no base register, we want
4973 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4974 Otherwise, if there is no base register, we want
4975 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4976 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4977 If we have a constant, we need two instructions anyhow,
4978 so we always use the latter form.
4980 If we have a base register, and this is a reference to a
4981 GP relative symbol, we want
4982 addu $tempreg,$breg,$gp
4983 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4985 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4986 addu $tempreg,$tempreg,$breg
4987 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4988 With a constant we always use the latter case. */
4991 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
4992 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4997 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4998 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4999 p
= frag_var (rs_machine_dependent
, 8, 0,
5000 RELAX_ENCODE (4, 8, 0, 4, 0,
5001 (mips_opts
.warn_about_macros
5003 && mips_opts
.noat
))),
5004 offset_expr
.X_add_symbol
, (offsetT
) 0,
5008 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5011 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5012 (int) BFD_RELOC_LO16
, tempreg
);
5016 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5017 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5022 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5023 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5024 "d,v,t", tempreg
, breg
, GP
);
5025 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5026 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5027 p
= frag_var (rs_machine_dependent
, 12, 0,
5028 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5029 offset_expr
.X_add_symbol
, (offsetT
) 0,
5032 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5035 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5036 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5037 "d,v,t", tempreg
, tempreg
, breg
);
5040 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5041 (int) BFD_RELOC_LO16
, tempreg
);
5044 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5046 /* If this is a reference to an external symbol, we want
5047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5049 <op> $treg,0($tempreg)
5051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5053 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5054 <op> $treg,0($tempreg)
5055 If there is a base register, we add it to $tempreg before
5056 the <op>. If there is a constant, we stick it in the
5057 <op> instruction. We don't handle constants larger than
5058 16 bits, because we have no way to load the upper 16 bits
5059 (actually, we could handle them for the subset of cases
5060 in which we are not using $at). */
5061 assert (offset_expr
.X_op
== O_symbol
);
5062 expr1
.X_add_number
= offset_expr
.X_add_number
;
5063 offset_expr
.X_add_number
= 0;
5064 if (expr1
.X_add_number
< -0x8000
5065 || expr1
.X_add_number
>= 0x8000)
5066 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5069 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5070 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5072 p
= frag_var (rs_machine_dependent
, 4, 0,
5073 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5074 offset_expr
.X_add_symbol
, (offsetT
) 0,
5076 macro_build (p
, &icnt
, &offset_expr
,
5077 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5078 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5081 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5082 "d,v,t", tempreg
, tempreg
, breg
);
5083 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5084 (int) BFD_RELOC_LO16
, tempreg
);
5086 else if (mips_pic
== SVR4_PIC
)
5090 /* If this is a reference to an external symbol, we want
5091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5092 addu $tempreg,$tempreg,$gp
5093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5094 <op> $treg,0($tempreg)
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5098 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5099 <op> $treg,0($tempreg)
5100 If there is a base register, we add it to $tempreg before
5101 the <op>. If there is a constant, we stick it in the
5102 <op> instruction. We don't handle constants larger than
5103 16 bits, because we have no way to load the upper 16 bits
5104 (actually, we could handle them for the subset of cases
5105 in which we are not using $at). */
5106 assert (offset_expr
.X_op
== O_symbol
);
5107 expr1
.X_add_number
= offset_expr
.X_add_number
;
5108 offset_expr
.X_add_number
= 0;
5109 if (expr1
.X_add_number
< -0x8000
5110 || expr1
.X_add_number
>= 0x8000)
5111 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5112 if (reg_needs_delay (GP
))
5117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5118 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5120 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5121 "d,v,t", tempreg
, tempreg
, GP
);
5122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5123 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5124 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5126 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5127 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5128 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5131 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5134 macro_build (p
, &icnt
, &offset_expr
,
5135 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5136 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5138 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5140 macro_build (p
, &icnt
, &offset_expr
,
5141 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5142 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5145 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5146 "d,v,t", tempreg
, tempreg
, breg
);
5147 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5148 (int) BFD_RELOC_LO16
, tempreg
);
5150 else if (mips_pic
== EMBEDDED_PIC
)
5152 /* If there is no base register, we want
5153 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5154 If there is a base register, we want
5155 addu $tempreg,$breg,$gp
5156 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5158 assert (offset_expr
.X_op
== O_symbol
);
5161 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5162 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5168 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5169 "d,v,t", tempreg
, breg
, GP
);
5170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5171 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5184 load_register (&icnt
, treg
, &imm_expr
, 0);
5188 load_register (&icnt
, treg
, &imm_expr
, 1);
5192 if (imm_expr
.X_op
== O_constant
)
5194 load_register (&icnt
, AT
, &imm_expr
, 0);
5195 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5196 "mtc1", "t,G", AT
, treg
);
5201 assert (offset_expr
.X_op
== O_symbol
5202 && strcmp (segment_name (S_GET_SEGMENT
5203 (offset_expr
.X_add_symbol
)),
5205 && offset_expr
.X_add_number
== 0);
5206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5207 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5212 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5213 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5214 order 32 bits of the value and the low order 32 bits are either
5215 zero or in OFFSET_EXPR. */
5216 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5218 if (HAVE_64BIT_GPRS
)
5219 load_register (&icnt
, treg
, &imm_expr
, 1);
5224 if (target_big_endian
)
5236 load_register (&icnt
, hreg
, &imm_expr
, 0);
5239 if (offset_expr
.X_op
== O_absent
)
5240 move_register (&icnt
, lreg
, 0);
5243 assert (offset_expr
.X_op
== O_constant
);
5244 load_register (&icnt
, lreg
, &offset_expr
, 0);
5251 /* We know that sym is in the .rdata section. First we get the
5252 upper 16 bits of the address. */
5253 if (mips_pic
== NO_PIC
)
5255 /* FIXME: This won't work for a 64 bit address. */
5256 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5258 else if (mips_pic
== SVR4_PIC
)
5260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5261 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5262 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5264 else if (mips_pic
== EMBEDDED_PIC
)
5266 /* For embedded PIC we pick up the entire address off $gp in
5267 a single instruction. */
5268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5269 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5270 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5271 offset_expr
.X_op
= O_constant
;
5272 offset_expr
.X_add_number
= 0;
5277 /* Now we load the register(s). */
5278 if (HAVE_64BIT_GPRS
)
5279 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5280 treg
, (int) BFD_RELOC_LO16
, AT
);
5283 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5284 treg
, (int) BFD_RELOC_LO16
, AT
);
5287 /* FIXME: How in the world do we deal with the possible
5289 offset_expr
.X_add_number
+= 4;
5290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5291 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5295 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5296 does not become a variant frag. */
5297 frag_wane (frag_now
);
5303 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5304 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5305 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5306 the value and the low order 32 bits are either zero or in
5308 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5310 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5311 if (HAVE_64BIT_FPRS
)
5313 assert (HAVE_64BIT_GPRS
);
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "dmtc1", "t,S", AT
, treg
);
5319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5320 "mtc1", "t,G", AT
, treg
+ 1);
5321 if (offset_expr
.X_op
== O_absent
)
5322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5323 "mtc1", "t,G", 0, treg
);
5326 assert (offset_expr
.X_op
== O_constant
);
5327 load_register (&icnt
, AT
, &offset_expr
, 0);
5328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5329 "mtc1", "t,G", AT
, treg
);
5335 assert (offset_expr
.X_op
== O_symbol
5336 && offset_expr
.X_add_number
== 0);
5337 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5338 if (strcmp (s
, ".lit8") == 0)
5340 if (mips_opts
.isa
!= ISA_MIPS1
)
5342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5343 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5347 r
= BFD_RELOC_MIPS_LITERAL
;
5352 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5353 if (mips_pic
== SVR4_PIC
)
5354 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5355 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5356 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5359 /* FIXME: This won't work for a 64 bit address. */
5360 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5363 if (mips_opts
.isa
!= ISA_MIPS1
)
5365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5366 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5368 /* To avoid confusion in tc_gen_reloc, we must ensure
5369 that this does not become a variant frag. */
5370 frag_wane (frag_now
);
5381 if (mips_arch
== CPU_R4650
)
5383 as_bad (_("opcode not supported on this processor"));
5386 /* Even on a big endian machine $fn comes before $fn+1. We have
5387 to adjust when loading from memory. */
5390 assert (mips_opts
.isa
== ISA_MIPS1
);
5391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5392 target_big_endian
? treg
+ 1 : treg
,
5394 /* FIXME: A possible overflow which I don't know how to deal
5396 offset_expr
.X_add_number
+= 4;
5397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5398 target_big_endian
? treg
: treg
+ 1,
5401 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5402 does not become a variant frag. */
5403 frag_wane (frag_now
);
5412 * The MIPS assembler seems to check for X_add_number not
5413 * being double aligned and generating:
5416 * addiu at,at,%lo(foo+1)
5419 * But, the resulting address is the same after relocation so why
5420 * generate the extra instruction?
5422 if (mips_arch
== CPU_R4650
)
5424 as_bad (_("opcode not supported on this processor"));
5427 /* Itbl support may require additional care here. */
5429 if (mips_opts
.isa
!= ISA_MIPS1
)
5440 if (mips_arch
== CPU_R4650
)
5442 as_bad (_("opcode not supported on this processor"));
5446 if (mips_opts
.isa
!= ISA_MIPS1
)
5454 /* Itbl support may require additional care here. */
5459 if (HAVE_64BIT_GPRS
)
5470 if (HAVE_64BIT_GPRS
)
5480 if (offset_expr
.X_op
!= O_symbol
5481 && offset_expr
.X_op
!= O_constant
)
5483 as_bad (_("expression too complex"));
5484 offset_expr
.X_op
= O_constant
;
5487 /* Even on a big endian machine $fn comes before $fn+1. We have
5488 to adjust when loading from memory. We set coproc if we must
5489 load $fn+1 first. */
5490 /* Itbl support may require additional care here. */
5491 if (! target_big_endian
)
5494 if (mips_pic
== NO_PIC
5495 || offset_expr
.X_op
== O_constant
)
5497 /* If this is a reference to a GP relative symbol, we want
5498 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5499 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5500 If we have a base register, we use this
5502 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5503 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5504 If this is not a GP relative symbol, we want
5505 lui $at,<sym> (BFD_RELOC_HI16_S)
5506 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5507 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5508 If there is a base register, we add it to $at after the
5509 lui instruction. If there is a constant, we always use
5511 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5512 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5531 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5532 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5533 "d,v,t", AT
, breg
, GP
);
5539 /* Itbl support may require additional care here. */
5540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5541 coproc
? treg
+ 1 : treg
,
5542 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5543 offset_expr
.X_add_number
+= 4;
5545 /* Set mips_optimize to 2 to avoid inserting an
5547 hold_mips_optimize
= mips_optimize
;
5549 /* Itbl support may require additional care here. */
5550 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5551 coproc
? treg
: treg
+ 1,
5552 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5553 mips_optimize
= hold_mips_optimize
;
5555 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5556 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5557 used_at
&& mips_opts
.noat
),
5558 offset_expr
.X_add_symbol
, (offsetT
) 0,
5561 /* We just generated two relocs. When tc_gen_reloc
5562 handles this case, it will skip the first reloc and
5563 handle the second. The second reloc already has an
5564 extra addend of 4, which we added above. We must
5565 subtract it out, and then subtract another 4 to make
5566 the first reloc come out right. The second reloc
5567 will come out right because we are going to add 4 to
5568 offset_expr when we build its instruction below.
5570 If we have a symbol, then we don't want to include
5571 the offset, because it will wind up being included
5572 when we generate the reloc. */
5574 if (offset_expr
.X_op
== O_constant
)
5575 offset_expr
.X_add_number
-= 8;
5578 offset_expr
.X_add_number
= -4;
5579 offset_expr
.X_op
= O_constant
;
5582 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5587 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5588 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5589 "d,v,t", AT
, breg
, AT
);
5593 /* Itbl support may require additional care here. */
5594 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5595 coproc
? treg
+ 1 : treg
,
5596 (int) BFD_RELOC_LO16
, AT
);
5599 /* FIXME: How do we handle overflow here? */
5600 offset_expr
.X_add_number
+= 4;
5601 /* Itbl support may require additional care here. */
5602 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5603 coproc
? treg
: treg
+ 1,
5604 (int) BFD_RELOC_LO16
, AT
);
5606 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5610 /* If this is a reference to an external symbol, we want
5611 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5616 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5618 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5619 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5620 If there is a base register we add it to $at before the
5621 lwc1 instructions. If there is a constant we include it
5622 in the lwc1 instructions. */
5624 expr1
.X_add_number
= offset_expr
.X_add_number
;
5625 offset_expr
.X_add_number
= 0;
5626 if (expr1
.X_add_number
< -0x8000
5627 || expr1
.X_add_number
>= 0x8000 - 4)
5628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5633 frag_grow (24 + off
);
5634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5635 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5636 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5640 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5641 "d,v,t", AT
, breg
, AT
);
5642 /* Itbl support may require additional care here. */
5643 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5644 coproc
? treg
+ 1 : treg
,
5645 (int) BFD_RELOC_LO16
, AT
);
5646 expr1
.X_add_number
+= 4;
5648 /* Set mips_optimize to 2 to avoid inserting an undesired
5650 hold_mips_optimize
= mips_optimize
;
5652 /* Itbl support may require additional care here. */
5653 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5654 coproc
? treg
: treg
+ 1,
5655 (int) BFD_RELOC_LO16
, AT
);
5656 mips_optimize
= hold_mips_optimize
;
5658 (void) frag_var (rs_machine_dependent
, 0, 0,
5659 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5660 offset_expr
.X_add_symbol
, (offsetT
) 0,
5663 else if (mips_pic
== SVR4_PIC
)
5667 /* If this is a reference to an external symbol, we want
5668 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5670 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5675 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5677 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5678 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5679 If there is a base register we add it to $at before the
5680 lwc1 instructions. If there is a constant we include it
5681 in the lwc1 instructions. */
5683 expr1
.X_add_number
= offset_expr
.X_add_number
;
5684 offset_expr
.X_add_number
= 0;
5685 if (expr1
.X_add_number
< -0x8000
5686 || expr1
.X_add_number
>= 0x8000 - 4)
5687 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5688 if (reg_needs_delay (GP
))
5697 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5698 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5700 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5701 "d,v,t", AT
, AT
, GP
);
5702 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5703 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5704 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5708 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5709 "d,v,t", AT
, breg
, AT
);
5710 /* Itbl support may require additional care here. */
5711 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5712 coproc
? treg
+ 1 : treg
,
5713 (int) BFD_RELOC_LO16
, AT
);
5714 expr1
.X_add_number
+= 4;
5716 /* Set mips_optimize to 2 to avoid inserting an undesired
5718 hold_mips_optimize
= mips_optimize
;
5720 /* Itbl support may require additional care here. */
5721 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5722 coproc
? treg
: treg
+ 1,
5723 (int) BFD_RELOC_LO16
, AT
);
5724 mips_optimize
= hold_mips_optimize
;
5725 expr1
.X_add_number
-= 4;
5727 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5728 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5729 8 + gpdel
+ off
, 1, 0),
5730 offset_expr
.X_add_symbol
, (offsetT
) 0,
5734 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, &offset_expr
,
5738 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5739 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5741 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5745 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5746 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5747 "d,v,t", AT
, breg
, AT
);
5750 /* Itbl support may require additional care here. */
5751 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5752 coproc
? treg
+ 1 : treg
,
5753 (int) BFD_RELOC_LO16
, AT
);
5755 expr1
.X_add_number
+= 4;
5757 /* Set mips_optimize to 2 to avoid inserting an undesired
5759 hold_mips_optimize
= mips_optimize
;
5761 /* Itbl support may require additional care here. */
5762 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5763 coproc
? treg
: treg
+ 1,
5764 (int) BFD_RELOC_LO16
, AT
);
5765 mips_optimize
= hold_mips_optimize
;
5767 else if (mips_pic
== EMBEDDED_PIC
)
5769 /* If there is no base register, we use
5770 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5771 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5772 If we have a base register, we use
5774 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5775 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5785 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5786 "d,v,t", AT
, breg
, GP
);
5791 /* Itbl support may require additional care here. */
5792 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5793 coproc
? treg
+ 1 : treg
,
5794 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5795 offset_expr
.X_add_number
+= 4;
5796 /* Itbl support may require additional care here. */
5797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5798 coproc
? treg
: treg
+ 1,
5799 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5815 assert (HAVE_32BIT_ADDRESSES
);
5816 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5817 (int) BFD_RELOC_LO16
, breg
);
5818 offset_expr
.X_add_number
+= 4;
5819 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5820 (int) BFD_RELOC_LO16
, breg
);
5823 /* New code added to support COPZ instructions.
5824 This code builds table entries out of the macros in mip_opcodes.
5825 R4000 uses interlocks to handle coproc delays.
5826 Other chips (like the R3000) require nops to be inserted for delays.
5828 FIXME: Currently, we require that the user handle delays.
5829 In order to fill delay slots for non-interlocked chips,
5830 we must have a way to specify delays based on the coprocessor.
5831 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5832 What are the side-effects of the cop instruction?
5833 What cache support might we have and what are its effects?
5834 Both coprocessor & memory require delays. how long???
5835 What registers are read/set/modified?
5837 If an itbl is provided to interpret cop instructions,
5838 this knowledge can be encoded in the itbl spec. */
5852 /* For now we just do C (same as Cz). The parameter will be
5853 stored in insn_opcode by mips_ip. */
5854 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5859 move_register (&icnt
, dreg
, sreg
);
5862 #ifdef LOSING_COMPILER
5864 /* Try and see if this is a new itbl instruction.
5865 This code builds table entries out of the macros in mip_opcodes.
5866 FIXME: For now we just assemble the expression and pass it's
5867 value along as a 32-bit immediate.
5868 We may want to have the assembler assemble this value,
5869 so that we gain the assembler's knowledge of delay slots,
5871 Would it be more efficient to use mask (id) here? */
5872 if (itbl_have_entries
5873 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5875 s
= ip
->insn_mo
->name
;
5877 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5878 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5885 as_warn (_("Macro used $at after \".set noat\""));
5890 struct mips_cl_insn
*ip
;
5892 register int treg
, sreg
, dreg
, breg
;
5908 bfd_reloc_code_real_type r
;
5911 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5912 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5913 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5914 mask
= ip
->insn_mo
->mask
;
5916 expr1
.X_op
= O_constant
;
5917 expr1
.X_op_symbol
= NULL
;
5918 expr1
.X_add_symbol
= NULL
;
5919 expr1
.X_add_number
= 1;
5923 #endif /* LOSING_COMPILER */
5928 macro_build ((char *) NULL
, &icnt
, NULL
,
5929 dbl
? "dmultu" : "multu",
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5937 /* The MIPS assembler some times generates shifts and adds. I'm
5938 not trying to be that fancy. GCC should do this for us
5940 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5941 macro_build ((char *) NULL
, &icnt
, NULL
,
5942 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
5943 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5956 mips_emit_delays (true);
5957 ++mips_opts
.noreorder
;
5958 mips_any_noreorder
= 1;
5960 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5961 macro_build ((char *) NULL
, &icnt
, NULL
,
5962 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5964 macro_build ((char *) NULL
, &icnt
, NULL
,
5965 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
5966 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5968 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5971 expr1
.X_add_number
= 8;
5972 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5973 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5976 --mips_opts
.noreorder
;
5977 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5990 mips_emit_delays (true);
5991 ++mips_opts
.noreorder
;
5992 mips_any_noreorder
= 1;
5994 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5995 macro_build ((char *) NULL
, &icnt
, NULL
,
5996 dbl
? "dmultu" : "multu",
5997 "s,t", sreg
, imm
? AT
: treg
);
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5999 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6004 expr1
.X_add_number
= 8;
6005 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6006 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6009 --mips_opts
.noreorder
;
6013 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6014 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6015 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6017 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6021 if (imm_expr
.X_op
!= O_constant
)
6022 as_bad (_("rotate count too large"));
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6024 (int) (imm_expr
.X_add_number
& 0x1f));
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6026 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6031 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6032 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6039 if (imm_expr
.X_op
!= O_constant
)
6040 as_bad (_("rotate count too large"));
6041 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6042 (int) (imm_expr
.X_add_number
& 0x1f));
6043 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6044 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6045 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6049 if (mips_arch
== CPU_R4650
)
6051 as_bad (_("opcode not supported on this processor"));
6054 assert (mips_opts
.isa
== ISA_MIPS1
);
6055 /* Even on a big endian machine $fn comes before $fn+1. We have
6056 to adjust when storing to memory. */
6057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6058 target_big_endian
? treg
+ 1 : treg
,
6059 (int) BFD_RELOC_LO16
, breg
);
6060 offset_expr
.X_add_number
+= 4;
6061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6062 target_big_endian
? treg
: treg
+ 1,
6063 (int) BFD_RELOC_LO16
, breg
);
6068 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6069 treg
, (int) BFD_RELOC_LO16
);
6071 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6072 sreg
, (int) BFD_RELOC_LO16
);
6075 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6077 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6078 dreg
, (int) BFD_RELOC_LO16
);
6083 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6085 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6086 sreg
, (int) BFD_RELOC_LO16
);
6091 as_warn (_("Instruction %s: result is always false"),
6093 move_register (&icnt
, dreg
, 0);
6096 if (imm_expr
.X_op
== O_constant
6097 && imm_expr
.X_add_number
>= 0
6098 && imm_expr
.X_add_number
< 0x10000)
6100 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6101 sreg
, (int) BFD_RELOC_LO16
);
6104 else if (imm_expr
.X_op
== O_constant
6105 && imm_expr
.X_add_number
> -0x8000
6106 && imm_expr
.X_add_number
< 0)
6108 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6109 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6110 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6111 "t,r,j", dreg
, sreg
,
6112 (int) BFD_RELOC_LO16
);
6117 load_register (&icnt
, AT
, &imm_expr
, 0);
6118 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6122 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6123 (int) BFD_RELOC_LO16
);
6128 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6134 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6135 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6136 (int) BFD_RELOC_LO16
);
6139 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6141 if (imm_expr
.X_op
== O_constant
6142 && imm_expr
.X_add_number
>= -0x8000
6143 && imm_expr
.X_add_number
< 0x8000)
6145 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6146 mask
== M_SGE_I
? "slti" : "sltiu",
6147 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6152 load_register (&icnt
, AT
, &imm_expr
, 0);
6153 macro_build ((char *) NULL
, &icnt
, NULL
,
6154 mask
== M_SGE_I
? "slt" : "sltu",
6155 "d,v,t", dreg
, sreg
, AT
);
6158 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6159 (int) BFD_RELOC_LO16
);
6164 case M_SGT
: /* sreg > treg <==> treg < sreg */
6170 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6173 case M_SGT_I
: /* sreg > I <==> I < sreg */
6179 load_register (&icnt
, AT
, &imm_expr
, 0);
6180 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6183 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6189 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6190 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6191 (int) BFD_RELOC_LO16
);
6194 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6200 load_register (&icnt
, AT
, &imm_expr
, 0);
6201 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6202 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6203 (int) BFD_RELOC_LO16
);
6207 if (imm_expr
.X_op
== O_constant
6208 && imm_expr
.X_add_number
>= -0x8000
6209 && imm_expr
.X_add_number
< 0x8000)
6211 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6212 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6215 load_register (&icnt
, AT
, &imm_expr
, 0);
6216 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6220 if (imm_expr
.X_op
== O_constant
6221 && imm_expr
.X_add_number
>= -0x8000
6222 && imm_expr
.X_add_number
< 0x8000)
6224 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6225 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6228 load_register (&icnt
, AT
, &imm_expr
, 0);
6229 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6235 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6238 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6242 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6244 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6250 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6252 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6258 as_warn (_("Instruction %s: result is always true"),
6260 macro_build ((char *) NULL
, &icnt
, &expr1
,
6261 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6262 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6265 if (imm_expr
.X_op
== O_constant
6266 && imm_expr
.X_add_number
>= 0
6267 && imm_expr
.X_add_number
< 0x10000)
6269 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6270 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6273 else if (imm_expr
.X_op
== O_constant
6274 && imm_expr
.X_add_number
> -0x8000
6275 && imm_expr
.X_add_number
< 0)
6277 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6278 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6279 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6280 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6285 load_register (&icnt
, AT
, &imm_expr
, 0);
6286 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6290 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6298 if (imm_expr
.X_op
== O_constant
6299 && imm_expr
.X_add_number
> -0x8000
6300 && imm_expr
.X_add_number
<= 0x8000)
6302 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6303 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6304 dbl
? "daddi" : "addi",
6305 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6308 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6309 macro_build ((char *) NULL
, &icnt
, NULL
,
6310 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6316 if (imm_expr
.X_op
== O_constant
6317 && imm_expr
.X_add_number
> -0x8000
6318 && imm_expr
.X_add_number
<= 0x8000)
6320 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6321 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6322 dbl
? "daddiu" : "addiu",
6323 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6326 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6327 macro_build ((char *) NULL
, &icnt
, NULL
,
6328 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6349 load_register (&icnt
, AT
, &imm_expr
, 0);
6350 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6355 assert (mips_opts
.isa
== ISA_MIPS1
);
6356 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6357 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6360 * Is the double cfc1 instruction a bug in the mips assembler;
6361 * or is there a reason for it?
6363 mips_emit_delays (true);
6364 ++mips_opts
.noreorder
;
6365 mips_any_noreorder
= 1;
6366 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6367 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6369 expr1
.X_add_number
= 3;
6370 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6371 (int) BFD_RELOC_LO16
);
6372 expr1
.X_add_number
= 2;
6373 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6374 (int) BFD_RELOC_LO16
);
6375 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6376 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6377 macro_build ((char *) NULL
, &icnt
, NULL
,
6378 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6380 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6381 --mips_opts
.noreorder
;
6390 if (offset_expr
.X_add_number
>= 0x7fff)
6391 as_bad (_("operand overflow"));
6392 /* avoid load delay */
6393 if (! target_big_endian
)
6394 offset_expr
.X_add_number
+= 1;
6395 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6396 (int) BFD_RELOC_LO16
, breg
);
6397 if (! target_big_endian
)
6398 offset_expr
.X_add_number
-= 1;
6400 offset_expr
.X_add_number
+= 1;
6401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6402 (int) BFD_RELOC_LO16
, breg
);
6403 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6404 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6417 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6418 as_bad (_("operand overflow"));
6419 if (! target_big_endian
)
6420 offset_expr
.X_add_number
+= off
;
6421 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6422 (int) BFD_RELOC_LO16
, breg
);
6423 if (! target_big_endian
)
6424 offset_expr
.X_add_number
-= off
;
6426 offset_expr
.X_add_number
+= off
;
6427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6428 (int) BFD_RELOC_LO16
, breg
);
6441 load_address (&icnt
, AT
, &offset_expr
);
6443 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6444 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6445 "d,v,t", AT
, AT
, breg
);
6446 if (! target_big_endian
)
6447 expr1
.X_add_number
= off
;
6449 expr1
.X_add_number
= 0;
6450 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6451 (int) BFD_RELOC_LO16
, AT
);
6452 if (! target_big_endian
)
6453 expr1
.X_add_number
= 0;
6455 expr1
.X_add_number
= off
;
6456 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6457 (int) BFD_RELOC_LO16
, AT
);
6462 load_address (&icnt
, AT
, &offset_expr
);
6464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6465 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6466 "d,v,t", AT
, AT
, breg
);
6467 if (target_big_endian
)
6468 expr1
.X_add_number
= 0;
6469 macro_build ((char *) NULL
, &icnt
, &expr1
,
6470 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6471 (int) BFD_RELOC_LO16
, AT
);
6472 if (target_big_endian
)
6473 expr1
.X_add_number
= 1;
6475 expr1
.X_add_number
= 0;
6476 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6477 (int) BFD_RELOC_LO16
, AT
);
6478 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6480 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6485 if (offset_expr
.X_add_number
>= 0x7fff)
6486 as_bad (_("operand overflow"));
6487 if (target_big_endian
)
6488 offset_expr
.X_add_number
+= 1;
6489 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6490 (int) BFD_RELOC_LO16
, breg
);
6491 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6492 if (target_big_endian
)
6493 offset_expr
.X_add_number
-= 1;
6495 offset_expr
.X_add_number
+= 1;
6496 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6497 (int) BFD_RELOC_LO16
, breg
);
6510 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6511 as_bad (_("operand overflow"));
6512 if (! target_big_endian
)
6513 offset_expr
.X_add_number
+= off
;
6514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6515 (int) BFD_RELOC_LO16
, breg
);
6516 if (! target_big_endian
)
6517 offset_expr
.X_add_number
-= off
;
6519 offset_expr
.X_add_number
+= off
;
6520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6521 (int) BFD_RELOC_LO16
, breg
);
6534 load_address (&icnt
, AT
, &offset_expr
);
6536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6537 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6538 "d,v,t", AT
, AT
, breg
);
6539 if (! target_big_endian
)
6540 expr1
.X_add_number
= off
;
6542 expr1
.X_add_number
= 0;
6543 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6544 (int) BFD_RELOC_LO16
, AT
);
6545 if (! target_big_endian
)
6546 expr1
.X_add_number
= 0;
6548 expr1
.X_add_number
= off
;
6549 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6550 (int) BFD_RELOC_LO16
, AT
);
6554 load_address (&icnt
, AT
, &offset_expr
);
6556 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6557 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6558 "d,v,t", AT
, AT
, breg
);
6559 if (! target_big_endian
)
6560 expr1
.X_add_number
= 0;
6561 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6562 (int) BFD_RELOC_LO16
, AT
);
6563 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6565 if (! target_big_endian
)
6566 expr1
.X_add_number
= 1;
6568 expr1
.X_add_number
= 0;
6569 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6570 (int) BFD_RELOC_LO16
, AT
);
6571 if (! target_big_endian
)
6572 expr1
.X_add_number
= 0;
6574 expr1
.X_add_number
= 1;
6575 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6576 (int) BFD_RELOC_LO16
, AT
);
6577 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6579 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6584 /* FIXME: Check if this is one of the itbl macros, since they
6585 are added dynamically. */
6586 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6590 as_warn (_("Macro used $at after \".set noat\""));
6593 /* Implement macros in mips16 mode. */
6597 struct mips_cl_insn
*ip
;
6600 int xreg
, yreg
, zreg
, tmp
;
6604 const char *s
, *s2
, *s3
;
6606 mask
= ip
->insn_mo
->mask
;
6608 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6609 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6610 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6614 expr1
.X_op
= O_constant
;
6615 expr1
.X_op_symbol
= NULL
;
6616 expr1
.X_add_symbol
= NULL
;
6617 expr1
.X_add_number
= 1;
6636 mips_emit_delays (true);
6637 ++mips_opts
.noreorder
;
6638 mips_any_noreorder
= 1;
6639 macro_build ((char *) NULL
, &icnt
, NULL
,
6640 dbl
? "ddiv" : "div",
6641 "0,x,y", xreg
, yreg
);
6642 expr1
.X_add_number
= 2;
6643 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6644 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6646 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6647 since that causes an overflow. We should do that as well,
6648 but I don't see how to do the comparisons without a temporary
6650 --mips_opts
.noreorder
;
6651 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6670 mips_emit_delays (true);
6671 ++mips_opts
.noreorder
;
6672 mips_any_noreorder
= 1;
6673 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6674 expr1
.X_add_number
= 2;
6675 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6676 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6677 --mips_opts
.noreorder
;
6678 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6684 macro_build ((char *) NULL
, &icnt
, NULL
,
6685 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
6686 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6694 if (imm_expr
.X_op
!= O_constant
)
6695 as_bad (_("Unsupported large constant"));
6696 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6697 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6698 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
6702 if (imm_expr
.X_op
!= O_constant
)
6703 as_bad (_("Unsupported large constant"));
6704 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6705 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6710 if (imm_expr
.X_op
!= O_constant
)
6711 as_bad (_("Unsupported large constant"));
6712 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6713 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6736 goto do_reverse_branch
;
6740 goto do_reverse_branch
;
6752 goto do_reverse_branch
;
6763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6765 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6792 goto do_addone_branch_i
;
6797 goto do_addone_branch_i
;
6812 goto do_addone_branch_i
;
6819 if (imm_expr
.X_op
!= O_constant
)
6820 as_bad (_("Unsupported large constant"));
6821 ++imm_expr
.X_add_number
;
6824 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6829 expr1
.X_add_number
= 0;
6830 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6832 move_register (&icnt
, xreg
, yreg
);
6833 expr1
.X_add_number
= 2;
6834 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6836 "neg", "x,w", xreg
, xreg
);
6840 /* For consistency checking, verify that all bits are specified either
6841 by the match/mask part of the instruction definition, or by the
6844 validate_mips_insn (opc
)
6845 const struct mips_opcode
*opc
;
6847 const char *p
= opc
->args
;
6849 unsigned long used_bits
= opc
->mask
;
6851 if ((used_bits
& opc
->match
) != opc
->match
)
6853 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6854 opc
->name
, opc
->args
);
6857 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6864 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6865 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6867 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6868 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6869 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6870 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6872 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6873 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6875 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6877 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6878 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6879 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6880 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6881 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6882 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6883 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6884 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6885 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6886 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6887 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6889 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6890 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6891 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6892 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6894 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6895 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6896 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6897 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6898 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6899 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6900 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6901 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6902 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6905 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6906 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6907 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6909 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6910 c
, opc
->name
, opc
->args
);
6914 if (used_bits
!= 0xffffffff)
6916 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6917 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6923 /* This routine assembles an instruction into its binary format. As a
6924 side effect, it sets one of the global variables imm_reloc or
6925 offset_reloc to the type of relocation to do if one of the operands
6926 is an address expression. */
6931 struct mips_cl_insn
*ip
;
6936 struct mips_opcode
*insn
;
6939 unsigned int lastregno
= 0;
6942 int full_opcode_match
= 1;
6946 /* If the instruction contains a '.', we first try to match an instruction
6947 including the '.'. Then we try again without the '.'. */
6949 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6952 /* If we stopped on whitespace, then replace the whitespace with null for
6953 the call to hash_find. Save the character we replaced just in case we
6954 have to re-parse the instruction. */
6955 if (isspace ((unsigned char) *s
))
6961 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6963 /* If we didn't find the instruction in the opcode table, try again, but
6964 this time with just the instruction up to, but not including the
6968 /* Restore the character we overwrite above (if any). */
6972 /* Scan up to the first '.' or whitespace. */
6973 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
6976 /* If we did not find a '.', then we can quit now. */
6979 insn_error
= "unrecognized opcode";
6983 /* Lookup the instruction in the hash table. */
6985 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6987 insn_error
= "unrecognized opcode";
6991 full_opcode_match
= 0;
6999 assert (strcmp (insn
->name
, str
) == 0);
7001 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7006 if (insn
->pinfo
!= INSN_MACRO
)
7008 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7014 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7015 && strcmp (insn
->name
, insn
[1].name
) == 0)
7024 static char buf
[100];
7026 _("opcode not supported on this processor: %s (%s)"),
7027 mips_cpu_to_str (mips_arch
),
7028 mips_isa_to_str (mips_opts
.isa
));
7039 ip
->insn_opcode
= insn
->match
;
7041 for (args
= insn
->args
;; ++args
)
7047 case '\0': /* end of args */
7060 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7064 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7068 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7072 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7078 /* Handle optional base register.
7079 Either the base register is omitted or
7080 we must have a left paren. */
7081 /* This is dependent on the next operand specifier
7082 is a base register specification. */
7083 assert (args
[1] == 'b' || args
[1] == '5'
7084 || args
[1] == '-' || args
[1] == '4');
7088 case ')': /* these must match exactly */
7093 case '<': /* must be at least one digit */
7095 * According to the manual, if the shift amount is greater
7096 * than 31 or less than 0 the the shift amount should be
7097 * mod 32. In reality the mips assembler issues an error.
7098 * We issue a warning and mask out all but the low 5 bits.
7100 my_getExpression (&imm_expr
, s
);
7101 check_absolute_expr (ip
, &imm_expr
);
7102 if ((unsigned long) imm_expr
.X_add_number
> 31)
7104 as_warn (_("Improper shift amount (%ld)"),
7105 (long) imm_expr
.X_add_number
);
7106 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7108 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7109 imm_expr
.X_op
= O_absent
;
7113 case '>': /* shift amount minus 32 */
7114 my_getExpression (&imm_expr
, s
);
7115 check_absolute_expr (ip
, &imm_expr
);
7116 if ((unsigned long) imm_expr
.X_add_number
< 32
7117 || (unsigned long) imm_expr
.X_add_number
> 63)
7119 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7120 imm_expr
.X_op
= O_absent
;
7124 case 'k': /* cache code */
7125 case 'h': /* prefx code */
7126 my_getExpression (&imm_expr
, s
);
7127 check_absolute_expr (ip
, &imm_expr
);
7128 if ((unsigned long) imm_expr
.X_add_number
> 31)
7130 as_warn (_("Invalid value for `%s' (%lu)"),
7132 (unsigned long) imm_expr
.X_add_number
);
7133 imm_expr
.X_add_number
&= 0x1f;
7136 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7138 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7139 imm_expr
.X_op
= O_absent
;
7143 case 'c': /* break code */
7144 my_getExpression (&imm_expr
, s
);
7145 check_absolute_expr (ip
, &imm_expr
);
7146 if ((unsigned) imm_expr
.X_add_number
> 1023)
7148 as_warn (_("Illegal break code (%ld)"),
7149 (long) imm_expr
.X_add_number
);
7150 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7152 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7153 imm_expr
.X_op
= O_absent
;
7157 case 'q': /* lower break code */
7158 my_getExpression (&imm_expr
, s
);
7159 check_absolute_expr (ip
, &imm_expr
);
7160 if ((unsigned) imm_expr
.X_add_number
> 1023)
7162 as_warn (_("Illegal lower break code (%ld)"),
7163 (long) imm_expr
.X_add_number
);
7164 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7166 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7167 imm_expr
.X_op
= O_absent
;
7171 case 'B': /* 20-bit syscall/break code. */
7172 my_getExpression (&imm_expr
, s
);
7173 check_absolute_expr (ip
, &imm_expr
);
7174 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7175 as_warn (_("Illegal 20-bit code (%ld)"),
7176 (long) imm_expr
.X_add_number
);
7177 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7178 imm_expr
.X_op
= O_absent
;
7182 case 'C': /* Coprocessor code */
7183 my_getExpression (&imm_expr
, s
);
7184 check_absolute_expr (ip
, &imm_expr
);
7185 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7187 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7188 (long) imm_expr
.X_add_number
);
7189 imm_expr
.X_add_number
&= ((1<<25) - 1);
7191 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7192 imm_expr
.X_op
= O_absent
;
7196 case 'J': /* 19-bit wait code. */
7197 my_getExpression (&imm_expr
, s
);
7198 check_absolute_expr (ip
, &imm_expr
);
7199 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7200 as_warn (_("Illegal 19-bit code (%ld)"),
7201 (long) imm_expr
.X_add_number
);
7202 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7203 imm_expr
.X_op
= O_absent
;
7207 case 'P': /* Performance register */
7208 my_getExpression (&imm_expr
, s
);
7209 check_absolute_expr (ip
, &imm_expr
);
7210 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7212 as_warn (_("Invalid performance register (%ld)"),
7213 (long) imm_expr
.X_add_number
);
7214 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7216 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7217 imm_expr
.X_op
= O_absent
;
7221 case 'b': /* base register */
7222 case 'd': /* destination register */
7223 case 's': /* source register */
7224 case 't': /* target register */
7225 case 'r': /* both target and source */
7226 case 'v': /* both dest and source */
7227 case 'w': /* both dest and target */
7228 case 'E': /* coprocessor target register */
7229 case 'G': /* coprocessor destination register */
7230 case 'x': /* ignore register name */
7231 case 'z': /* must be zero register */
7232 case 'U': /* destination register (clo/clz). */
7237 if (isdigit ((unsigned char) s
[1]))
7247 while (isdigit ((unsigned char) *s
));
7249 as_bad (_("Invalid register number (%d)"), regno
);
7251 else if (*args
== 'E' || *args
== 'G')
7255 if (s
[1] == 'f' && s
[2] == 'p')
7260 else if (s
[1] == 's' && s
[2] == 'p')
7265 else if (s
[1] == 'g' && s
[2] == 'p')
7270 else if (s
[1] == 'a' && s
[2] == 't')
7275 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7280 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7285 else if (itbl_have_entries
)
7290 p
= s
+ 1; /* advance past '$' */
7291 n
= itbl_get_field (&p
); /* n is name */
7293 /* See if this is a register defined in an
7295 if (itbl_get_reg_val (n
, &r
))
7297 /* Get_field advances to the start of
7298 the next field, so we need to back
7299 rack to the end of the last field. */
7303 s
= strchr (s
, '\0');
7316 as_warn (_("Used $at without \".set noat\""));
7322 if (c
== 'r' || c
== 'v' || c
== 'w')
7329 /* 'z' only matches $0. */
7330 if (c
== 'z' && regno
!= 0)
7333 /* Now that we have assembled one operand, we use the args string
7334 * to figure out where it goes in the instruction. */
7341 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7345 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7348 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7349 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7354 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7357 /* This case exists because on the r3000 trunc
7358 expands into a macro which requires a gp
7359 register. On the r6000 or r4000 it is
7360 assembled into a single instruction which
7361 ignores the register. Thus the insn version
7362 is MIPS_ISA2 and uses 'x', and the macro
7363 version is MIPS_ISA1 and uses 't'. */
7366 /* This case is for the div instruction, which
7367 acts differently if the destination argument
7368 is $0. This only matches $0, and is checked
7369 outside the switch. */
7372 /* Itbl operand; not yet implemented. FIXME ?? */
7374 /* What about all other operands like 'i', which
7375 can be specified in the opcode table? */
7385 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7388 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7393 case 'D': /* floating point destination register */
7394 case 'S': /* floating point source register */
7395 case 'T': /* floating point target register */
7396 case 'R': /* floating point source register */
7400 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7410 while (isdigit ((unsigned char) *s
));
7413 as_bad (_("Invalid float register number (%d)"), regno
);
7415 if ((regno
& 1) != 0
7417 && ! (strcmp (str
, "mtc1") == 0
7418 || strcmp (str
, "mfc1") == 0
7419 || strcmp (str
, "lwc1") == 0
7420 || strcmp (str
, "swc1") == 0
7421 || strcmp (str
, "l.s") == 0
7422 || strcmp (str
, "s.s") == 0))
7423 as_warn (_("Float register should be even, was %d"),
7431 if (c
== 'V' || c
== 'W')
7441 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7445 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7449 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7452 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7462 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7465 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7471 my_getExpression (&imm_expr
, s
);
7472 if (imm_expr
.X_op
!= O_big
7473 && imm_expr
.X_op
!= O_constant
)
7474 insn_error
= _("absolute expression required");
7479 my_getExpression (&offset_expr
, s
);
7480 imm_reloc
= BFD_RELOC_32
;
7493 unsigned char temp
[8];
7495 unsigned int length
;
7500 /* These only appear as the last operand in an
7501 instruction, and every instruction that accepts
7502 them in any variant accepts them in all variants.
7503 This means we don't have to worry about backing out
7504 any changes if the instruction does not match.
7506 The difference between them is the size of the
7507 floating point constant and where it goes. For 'F'
7508 and 'L' the constant is 64 bits; for 'f' and 'l' it
7509 is 32 bits. Where the constant is placed is based
7510 on how the MIPS assembler does things:
7513 f -- immediate value
7516 The .lit4 and .lit8 sections are only used if
7517 permitted by the -G argument.
7519 When generating embedded PIC code, we use the
7520 .lit8 section but not the .lit4 section (we can do
7521 .lit4 inline easily; we need to put .lit8
7522 somewhere in the data segment, and using .lit8
7523 permits the linker to eventually combine identical
7526 The code below needs to know whether the target register
7527 is 32 or 64 bits wide. It relies on the fact 'f' and
7528 'F' are used with GPR-based instructions and 'l' and
7529 'L' are used with FPR-based instructions. */
7531 f64
= *args
== 'F' || *args
== 'L';
7532 using_gprs
= *args
== 'F' || *args
== 'f';
7534 save_in
= input_line_pointer
;
7535 input_line_pointer
= s
;
7536 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7538 s
= input_line_pointer
;
7539 input_line_pointer
= save_in
;
7540 if (err
!= NULL
&& *err
!= '\0')
7542 as_bad (_("Bad floating point constant: %s"), err
);
7543 memset (temp
, '\0', sizeof temp
);
7544 length
= f64
? 8 : 4;
7547 assert (length
== (unsigned) (f64
? 8 : 4));
7551 && (! USE_GLOBAL_POINTER_OPT
7552 || mips_pic
== EMBEDDED_PIC
7553 || g_switch_value
< 4
7554 || (temp
[0] == 0 && temp
[1] == 0)
7555 || (temp
[2] == 0 && temp
[3] == 0))))
7557 imm_expr
.X_op
= O_constant
;
7558 if (! target_big_endian
)
7559 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7561 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7564 && ! mips_disable_float_construction
7565 /* Constants can only be constructed in GPRs and
7566 copied to FPRs if the GPRs are at least as wide
7567 as the FPRs. Force the constant into memory if
7568 we are using 64-bit FPRs but the GPRs are only
7571 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
7572 && ((temp
[0] == 0 && temp
[1] == 0)
7573 || (temp
[2] == 0 && temp
[3] == 0))
7574 && ((temp
[4] == 0 && temp
[5] == 0)
7575 || (temp
[6] == 0 && temp
[7] == 0)))
7577 /* The value is simple enough to load with a couple of
7578 instructions. If using 32-bit registers, set
7579 imm_expr to the high order 32 bits and offset_expr to
7580 the low order 32 bits. Otherwise, set imm_expr to
7581 the entire 64 bit constant. */
7582 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
7584 imm_expr
.X_op
= O_constant
;
7585 offset_expr
.X_op
= O_constant
;
7586 if (! target_big_endian
)
7588 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7589 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7593 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7594 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7596 if (offset_expr
.X_add_number
== 0)
7597 offset_expr
.X_op
= O_absent
;
7599 else if (sizeof (imm_expr
.X_add_number
) > 4)
7601 imm_expr
.X_op
= O_constant
;
7602 if (! target_big_endian
)
7603 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7605 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7609 imm_expr
.X_op
= O_big
;
7610 imm_expr
.X_add_number
= 4;
7611 if (! target_big_endian
)
7613 generic_bignum
[0] = bfd_getl16 (temp
);
7614 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7615 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7616 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7620 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7621 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7622 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7623 generic_bignum
[3] = bfd_getb16 (temp
);
7629 const char *newname
;
7632 /* Switch to the right section. */
7634 subseg
= now_subseg
;
7637 default: /* unused default case avoids warnings. */
7639 newname
= RDATA_SECTION_NAME
;
7640 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7641 || mips_pic
== EMBEDDED_PIC
)
7645 if (mips_pic
== EMBEDDED_PIC
)
7648 newname
= RDATA_SECTION_NAME
;
7651 assert (!USE_GLOBAL_POINTER_OPT
7652 || g_switch_value
>= 4);
7656 new_seg
= subseg_new (newname
, (subsegT
) 0);
7657 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7658 bfd_set_section_flags (stdoutput
, new_seg
,
7663 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7664 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7665 && strcmp (TARGET_OS
, "elf") != 0)
7666 record_alignment (new_seg
, 4);
7668 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7670 as_bad (_("Can't use floating point insn in this section"));
7672 /* Set the argument to the current address in the
7674 offset_expr
.X_op
= O_symbol
;
7675 offset_expr
.X_add_symbol
=
7676 symbol_new ("L0\001", now_seg
,
7677 (valueT
) frag_now_fix (), frag_now
);
7678 offset_expr
.X_add_number
= 0;
7680 /* Put the floating point number into the section. */
7681 p
= frag_more ((int) length
);
7682 memcpy (p
, temp
, length
);
7684 /* Switch back to the original section. */
7685 subseg_set (seg
, subseg
);
7690 case 'i': /* 16 bit unsigned immediate */
7691 case 'j': /* 16 bit signed immediate */
7692 imm_reloc
= BFD_RELOC_LO16
;
7693 c
= my_getSmallExpression (&imm_expr
, s
);
7698 if (imm_expr
.X_op
== O_constant
)
7699 imm_expr
.X_add_number
=
7700 (imm_expr
.X_add_number
>> 16) & 0xffff;
7701 else if (c
== S_EX_HIGHEST
)
7702 imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
7703 else if (c
== S_EX_HIGHER
)
7704 imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
7705 else if (c
== S_EX_HI
)
7707 imm_reloc
= BFD_RELOC_HI16_S
;
7708 imm_unmatched_hi
= true;
7711 imm_reloc
= BFD_RELOC_HI16
;
7713 else if (imm_expr
.X_op
== O_constant
)
7714 imm_expr
.X_add_number
&= 0xffff;
7718 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7719 || ((imm_expr
.X_add_number
< 0
7720 || imm_expr
.X_add_number
>= 0x10000)
7721 && imm_expr
.X_op
== O_constant
))
7723 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7724 !strcmp (insn
->name
, insn
[1].name
))
7726 if (imm_expr
.X_op
== O_constant
7727 || imm_expr
.X_op
== O_big
)
7728 as_bad (_("16 bit expression not in range 0..65535"));
7736 /* The upper bound should be 0x8000, but
7737 unfortunately the MIPS assembler accepts numbers
7738 from 0x8000 to 0xffff and sign extends them, and
7739 we want to be compatible. We only permit this
7740 extended range for an instruction which does not
7741 provide any further alternates, since those
7742 alternates may handle other cases. People should
7743 use the numbers they mean, rather than relying on
7744 a mysterious sign extension. */
7745 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7746 strcmp (insn
->name
, insn
[1].name
) == 0);
7751 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7752 || ((imm_expr
.X_add_number
< -0x8000
7753 || imm_expr
.X_add_number
>= max
)
7754 && imm_expr
.X_op
== O_constant
)
7756 && imm_expr
.X_add_number
< 0
7758 && imm_expr
.X_unsigned
7759 && sizeof (imm_expr
.X_add_number
) <= 4))
7763 if (imm_expr
.X_op
== O_constant
7764 || imm_expr
.X_op
== O_big
)
7765 as_bad (_("16 bit expression not in range -32768..32767"));
7771 case 'o': /* 16 bit offset */
7772 c
= my_getSmallExpression (&offset_expr
, s
);
7774 /* If this value won't fit into a 16 bit offset, then go
7775 find a macro that will generate the 32 bit offset
7776 code pattern. As a special hack, we accept the
7777 difference of two local symbols as a constant. This
7778 is required to suppose embedded PIC switches, which
7779 use an instruction which looks like
7780 lw $4,$L12-$LS12($4)
7781 The problem with handling this in a more general
7782 fashion is that the macro function doesn't expect to
7783 see anything which can be handled in a single
7784 constant instruction. */
7786 && (offset_expr
.X_op
!= O_constant
7787 || offset_expr
.X_add_number
>= 0x8000
7788 || offset_expr
.X_add_number
< -0x8000)
7789 && (mips_pic
!= EMBEDDED_PIC
7790 || offset_expr
.X_op
!= O_subtract
7791 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7792 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7797 if (offset_expr
.X_op
!= O_constant
)
7799 offset_expr
.X_add_number
=
7800 (offset_expr
.X_add_number
>> 16) & 0xffff;
7802 offset_reloc
= BFD_RELOC_LO16
;
7806 case 'p': /* pc relative offset */
7807 if (mips_pic
== EMBEDDED_PIC
)
7808 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7810 offset_reloc
= BFD_RELOC_16_PCREL
;
7811 my_getExpression (&offset_expr
, s
);
7815 case 'u': /* upper 16 bits */
7816 c
= my_getSmallExpression (&imm_expr
, s
);
7817 imm_reloc
= BFD_RELOC_LO16
;
7822 if (imm_expr
.X_op
== O_constant
)
7823 imm_expr
.X_add_number
=
7824 (imm_expr
.X_add_number
>> 16) & 0xffff;
7825 else if (c
== S_EX_HIGHEST
)
7826 imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
7827 else if (c
== S_EX_HI
)
7829 imm_reloc
= BFD_RELOC_HI16_S
;
7830 imm_unmatched_hi
= true;
7833 imm_reloc
= BFD_RELOC_HI16
;
7835 else if (imm_expr
.X_op
== O_constant
)
7836 imm_expr
.X_add_number
&= 0xffff;
7838 if (imm_expr
.X_op
== O_constant
7839 && (imm_expr
.X_add_number
< 0
7840 || imm_expr
.X_add_number
>= 0x10000))
7841 as_bad (_("lui expression not in range 0..65535"));
7845 case 'a': /* 26 bit address */
7846 my_getExpression (&offset_expr
, s
);
7848 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7851 case 'N': /* 3 bit branch condition code */
7852 case 'M': /* 3 bit compare condition code */
7853 if (strncmp (s
, "$fcc", 4) != 0)
7863 while (isdigit ((unsigned char) *s
));
7865 as_bad (_("invalid condition code register $fcc%d"), regno
);
7867 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7869 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7873 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7875 if (isdigit ((unsigned char) *s
))
7884 while (isdigit ((unsigned char) *s
));
7887 c
= 8; /* Invalid sel value. */
7890 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7891 ip
->insn_opcode
|= c
;
7895 as_bad (_("bad char = '%c'\n"), *args
);
7900 /* Args don't match. */
7901 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7902 !strcmp (insn
->name
, insn
[1].name
))
7906 insn_error
= _("illegal operands");
7911 insn_error
= _("illegal operands");
7916 /* This routine assembles an instruction into its binary format when
7917 assembling for the mips16. As a side effect, it sets one of the
7918 global variables imm_reloc or offset_reloc to the type of
7919 relocation to do if one of the operands is an address expression.
7920 It also sets mips16_small and mips16_ext if the user explicitly
7921 requested a small or extended instruction. */
7926 struct mips_cl_insn
*ip
;
7930 struct mips_opcode
*insn
;
7933 unsigned int lastregno
= 0;
7938 mips16_small
= false;
7941 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7953 if (s
[1] == 't' && s
[2] == ' ')
7956 mips16_small
= true;
7960 else if (s
[1] == 'e' && s
[2] == ' ')
7969 insn_error
= _("unknown opcode");
7973 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7974 mips16_small
= true;
7976 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7978 insn_error
= _("unrecognized opcode");
7985 assert (strcmp (insn
->name
, str
) == 0);
7988 ip
->insn_opcode
= insn
->match
;
7989 ip
->use_extend
= false;
7990 imm_expr
.X_op
= O_absent
;
7991 imm_reloc
= BFD_RELOC_UNUSED
;
7992 offset_expr
.X_op
= O_absent
;
7993 offset_reloc
= BFD_RELOC_UNUSED
;
7994 for (args
= insn
->args
; 1; ++args
)
8001 /* In this switch statement we call break if we did not find
8002 a match, continue if we did find a match, or return if we
8011 /* Stuff the immediate value in now, if we can. */
8012 if (imm_expr
.X_op
== O_constant
8013 && imm_reloc
> BFD_RELOC_UNUSED
8014 && insn
->pinfo
!= INSN_MACRO
)
8016 mips16_immed ((char *) NULL
, 0,
8017 imm_reloc
- BFD_RELOC_UNUSED
,
8018 imm_expr
.X_add_number
, true, mips16_small
,
8019 mips16_ext
, &ip
->insn_opcode
,
8020 &ip
->use_extend
, &ip
->extend
);
8021 imm_expr
.X_op
= O_absent
;
8022 imm_reloc
= BFD_RELOC_UNUSED
;
8036 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8039 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8055 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8057 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8074 if (isdigit ((unsigned char) s
[1]))
8084 while (isdigit ((unsigned char) *s
));
8087 as_bad (_("invalid register number (%d)"), regno
);
8093 if (s
[1] == 'f' && s
[2] == 'p')
8098 else if (s
[1] == 's' && s
[2] == 'p')
8103 else if (s
[1] == 'g' && s
[2] == 'p')
8108 else if (s
[1] == 'a' && s
[2] == 't')
8113 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8118 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8131 if (c
== 'v' || c
== 'w')
8133 regno
= mips16_to_32_reg_map
[lastregno
];
8147 regno
= mips32_to_16_reg_map
[regno
];
8152 regno
= ILLEGAL_REG
;
8157 regno
= ILLEGAL_REG
;
8162 regno
= ILLEGAL_REG
;
8167 if (regno
== AT
&& ! mips_opts
.noat
)
8168 as_warn (_("used $at without \".set noat\""));
8175 if (regno
== ILLEGAL_REG
)
8182 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8186 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8189 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8192 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8198 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8201 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8202 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8212 if (strncmp (s
, "$pc", 3) == 0)
8236 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8238 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8239 and generate the appropriate reloc. If the text
8240 inside %gprel is not a symbol name with an
8241 optional offset, then we generate a normal reloc
8242 and will probably fail later. */
8243 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8244 if (imm_expr
.X_op
== O_symbol
)
8247 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8249 ip
->use_extend
= true;
8256 /* Just pick up a normal expression. */
8257 my_getExpression (&imm_expr
, s
);
8260 if (imm_expr
.X_op
== O_register
)
8262 /* What we thought was an expression turned out to
8265 if (s
[0] == '(' && args
[1] == '(')
8267 /* It looks like the expression was omitted
8268 before a register indirection, which means
8269 that the expression is implicitly zero. We
8270 still set up imm_expr, so that we handle
8271 explicit extensions correctly. */
8272 imm_expr
.X_op
= O_constant
;
8273 imm_expr
.X_add_number
= 0;
8274 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8281 /* We need to relax this instruction. */
8282 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8291 /* We use offset_reloc rather than imm_reloc for the PC
8292 relative operands. This lets macros with both
8293 immediate and address operands work correctly. */
8294 my_getExpression (&offset_expr
, s
);
8296 if (offset_expr
.X_op
== O_register
)
8299 /* We need to relax this instruction. */
8300 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8304 case '6': /* break code */
8305 my_getExpression (&imm_expr
, s
);
8306 check_absolute_expr (ip
, &imm_expr
);
8307 if ((unsigned long) imm_expr
.X_add_number
> 63)
8309 as_warn (_("Invalid value for `%s' (%lu)"),
8311 (unsigned long) imm_expr
.X_add_number
);
8312 imm_expr
.X_add_number
&= 0x3f;
8314 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8315 imm_expr
.X_op
= O_absent
;
8319 case 'a': /* 26 bit address */
8320 my_getExpression (&offset_expr
, s
);
8322 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8323 ip
->insn_opcode
<<= 16;
8326 case 'l': /* register list for entry macro */
8327 case 'L': /* register list for exit macro */
8337 int freg
, reg1
, reg2
;
8339 while (*s
== ' ' || *s
== ',')
8343 as_bad (_("can't parse register list"));
8355 while (isdigit ((unsigned char) *s
))
8377 as_bad (_("invalid register list"));
8382 while (isdigit ((unsigned char) *s
))
8389 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8394 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8399 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8400 mask
|= (reg2
- 3) << 3;
8401 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8402 mask
|= (reg2
- 15) << 1;
8403 else if (reg1
== 31 && reg2
== 31)
8407 as_bad (_("invalid register list"));
8411 /* The mask is filled in in the opcode table for the
8412 benefit of the disassembler. We remove it before
8413 applying the actual mask. */
8414 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8415 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8419 case 'e': /* extend code */
8420 my_getExpression (&imm_expr
, s
);
8421 check_absolute_expr (ip
, &imm_expr
);
8422 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8424 as_warn (_("Invalid value for `%s' (%lu)"),
8426 (unsigned long) imm_expr
.X_add_number
);
8427 imm_expr
.X_add_number
&= 0x7ff;
8429 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8430 imm_expr
.X_op
= O_absent
;
8440 /* Args don't match. */
8441 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8442 strcmp (insn
->name
, insn
[1].name
) == 0)
8449 insn_error
= _("illegal operands");
8455 /* This structure holds information we know about a mips16 immediate
8458 struct mips16_immed_operand
8460 /* The type code used in the argument string in the opcode table. */
8462 /* The number of bits in the short form of the opcode. */
8464 /* The number of bits in the extended form of the opcode. */
8466 /* The amount by which the short form is shifted when it is used;
8467 for example, the sw instruction has a shift count of 2. */
8469 /* The amount by which the short form is shifted when it is stored
8470 into the instruction code. */
8472 /* Non-zero if the short form is unsigned. */
8474 /* Non-zero if the extended form is unsigned. */
8476 /* Non-zero if the value is PC relative. */
8480 /* The mips16 immediate operand types. */
8482 static const struct mips16_immed_operand mips16_immed_operands
[] =
8484 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8485 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8486 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8487 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8488 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8489 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8490 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8491 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8492 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8493 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8494 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8495 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8496 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8497 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8498 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8499 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8500 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8501 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8502 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8503 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8504 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8507 #define MIPS16_NUM_IMMED \
8508 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8510 /* Handle a mips16 instruction with an immediate value. This or's the
8511 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8512 whether an extended value is needed; if one is needed, it sets
8513 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8514 If SMALL is true, an unextended opcode was explicitly requested.
8515 If EXT is true, an extended opcode was explicitly requested. If
8516 WARN is true, warn if EXT does not match reality. */
8519 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8528 unsigned long *insn
;
8529 boolean
*use_extend
;
8530 unsigned short *extend
;
8532 register const struct mips16_immed_operand
*op
;
8533 int mintiny
, maxtiny
;
8536 op
= mips16_immed_operands
;
8537 while (op
->type
!= type
)
8540 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8545 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8548 maxtiny
= 1 << op
->nbits
;
8553 maxtiny
= (1 << op
->nbits
) - 1;
8558 mintiny
= - (1 << (op
->nbits
- 1));
8559 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8562 /* Branch offsets have an implicit 0 in the lowest bit. */
8563 if (type
== 'p' || type
== 'q')
8566 if ((val
& ((1 << op
->shift
) - 1)) != 0
8567 || val
< (mintiny
<< op
->shift
)
8568 || val
> (maxtiny
<< op
->shift
))
8573 if (warn
&& ext
&& ! needext
)
8574 as_warn_where (file
, line
,
8575 _("extended operand requested but not required"));
8576 if (small
&& needext
)
8577 as_bad_where (file
, line
, _("invalid unextended operand value"));
8579 if (small
|| (! ext
&& ! needext
))
8583 *use_extend
= false;
8584 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8585 insnval
<<= op
->op_shift
;
8590 long minext
, maxext
;
8596 maxext
= (1 << op
->extbits
) - 1;
8600 minext
= - (1 << (op
->extbits
- 1));
8601 maxext
= (1 << (op
->extbits
- 1)) - 1;
8603 if (val
< minext
|| val
> maxext
)
8604 as_bad_where (file
, line
,
8605 _("operand value out of range for instruction"));
8608 if (op
->extbits
== 16)
8610 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8613 else if (op
->extbits
== 15)
8615 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8620 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8624 *extend
= (unsigned short) extval
;
8631 my_getSmallExpression (ep
, str
)
8643 else if (str
[0] == '%'
8644 && tolower(str
[1]) == 'l'
8645 && tolower(str
[2]) == 'o'
8649 str
+= sizeof ("%lo(") - 2;
8651 else if (str
[0] == '%'
8652 && tolower(str
[1]) == 'h'
8653 && tolower(str
[2]) == 'i'
8657 str
+= sizeof ("%hi(") - 2;
8659 else if (str
[0] == '%'
8660 && tolower(str
[1]) == 'h'
8661 && tolower(str
[2]) == 'i'
8662 && tolower(str
[3]) == 'g'
8663 && tolower(str
[4]) == 'h'
8664 && tolower(str
[5]) == 'e'
8665 && tolower(str
[6]) == 'r'
8669 str
+= sizeof ("%higher(") - 2;
8671 else if (str
[0] == '%'
8672 && tolower(str
[1]) == 'h'
8673 && tolower(str
[2]) == 'i'
8674 && tolower(str
[3]) == 'g'
8675 && tolower(str
[4]) == 'h'
8676 && tolower(str
[5]) == 'e'
8677 && tolower(str
[6]) == 's'
8678 && tolower(str
[7]) == 't'
8682 str
+= sizeof ("%highest(") - 2;
8684 /* currently unsupported */
8686 else if (str
[0] == '%'
8687 && tolower(str
[1]) == 'g'
8688 && tolower(str
[2]) == 'p'
8689 && tolower(str
[3]) == '_'
8690 && tolower(str
[4]) == 'r'
8691 && tolower(str
[5]) == 'e'
8692 && tolower(str
[6]) == 'l'
8696 str
+= sizeof ("%gp_rel(") - 2;
8698 else if (str
[0] == '%'
8699 && tolower(str
[1]) == 'n'
8700 && tolower(str
[2]) == 'e'
8701 && tolower(str
[3]) == 'g'
8705 str
+= sizeof ("%neg(") - 2;
8710 my_getExpression (ep
, str
);
8715 * A small expression may be followed by a base register.
8716 * Scan to the end of this operand, and then back over a possible
8717 * base register. Then scan the small expression up to that
8718 * point. (Based on code in sparc.c...)
8720 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8722 if (sp
- 4 >= str
&& sp
[-1] == ')')
8724 if (isdigit ((unsigned char) sp
[-2]))
8726 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8728 if (*sp
== '$' && sp
> str
&& sp
[-1] == '(')
8734 else if (sp
- 5 >= str
8737 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8738 || (sp
[-3] == 's' && sp
[-2] == 'p')
8739 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8740 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8746 /* no expression means zero offset */
8749 /* %xx(reg) is an error */
8750 ep
->X_op
= O_absent
;
8755 ep
->X_op
= O_constant
;
8758 ep
->X_add_symbol
= NULL
;
8759 ep
->X_op_symbol
= NULL
;
8760 ep
->X_add_number
= 0;
8765 my_getExpression (ep
, str
);
8771 my_getExpression (ep
, str
);
8773 /* => %highest, %higher, %hi, %lo, %gprel, %neg encountered */
8778 my_getExpression (ep
, str
)
8785 save_in
= input_line_pointer
;
8786 input_line_pointer
= str
;
8788 expr_end
= input_line_pointer
;
8789 input_line_pointer
= save_in
;
8791 /* If we are in mips16 mode, and this is an expression based on `.',
8792 then we bump the value of the symbol by 1 since that is how other
8793 text symbols are handled. We don't bother to handle complex
8794 expressions, just `.' plus or minus a constant. */
8795 if (mips_opts
.mips16
8796 && ep
->X_op
== O_symbol
8797 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8798 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8799 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8800 && symbol_constant_p (ep
->X_add_symbol
)
8801 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
8802 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
8805 /* Turn a string in input_line_pointer into a floating point constant
8806 of type TYPE, and store the appropriate bytes in *LITP. The number
8807 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8808 returned, or NULL on OK. */
8811 md_atof (type
, litP
, sizeP
)
8817 LITTLENUM_TYPE words
[4];
8833 return _("bad call to md_atof");
8836 t
= atof_ieee (input_line_pointer
, type
, words
);
8838 input_line_pointer
= t
;
8842 if (! target_big_endian
)
8844 for (i
= prec
- 1; i
>= 0; i
--)
8846 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8852 for (i
= 0; i
< prec
; i
++)
8854 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8863 md_number_to_chars (buf
, val
, n
)
8868 if (target_big_endian
)
8869 number_to_chars_bigendian (buf
, val
, n
);
8871 number_to_chars_littleendian (buf
, val
, n
);
8874 CONST
char *md_shortopts
= "nO::g::G:";
8876 struct option md_longopts
[] =
8878 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8879 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8880 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8881 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8882 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8883 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8884 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8885 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8886 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8887 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8888 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8889 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8890 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8891 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8892 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8893 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8894 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8895 {"break", no_argument
, NULL
, OPTION_BREAK
},
8896 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8897 #define OPTION_EB (OPTION_MD_BASE + 9)
8898 {"EB", no_argument
, NULL
, OPTION_EB
},
8899 #define OPTION_EL (OPTION_MD_BASE + 10)
8900 {"EL", no_argument
, NULL
, OPTION_EL
},
8901 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8902 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8903 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8904 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8905 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8906 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8907 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8908 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8909 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8910 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8911 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8912 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8913 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8914 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8915 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8916 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8917 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8918 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8919 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8920 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8921 #define OPTION_MABI (OPTION_MD_BASE + 21)
8922 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8923 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8924 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8925 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8926 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8927 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8928 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8929 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8930 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8931 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8932 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8933 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8934 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8935 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8936 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8937 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8938 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8939 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8940 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8941 #define OPTION_MARCH (OPTION_MD_BASE + 31)
8942 {"march", required_argument
, NULL
, OPTION_MARCH
},
8943 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
8944 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8945 #define OPTION_FP32 (OPTION_MD_BASE + 33)
8946 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
8948 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8949 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8950 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8951 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8952 #define OPTION_32 (OPTION_ELF_BASE + 3)
8953 #define OPTION_64 (OPTION_ELF_BASE + 4)
8954 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8955 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8956 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8957 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8958 {"32", no_argument
, NULL
, OPTION_32
},
8959 {"64", no_argument
, NULL
, OPTION_64
},
8962 {NULL
, no_argument
, NULL
, 0}
8964 size_t md_longopts_size
= sizeof (md_longopts
);
8967 md_parse_option (c
, arg
)
8973 case OPTION_CONSTRUCT_FLOATS
:
8974 mips_disable_float_construction
= 0;
8977 case OPTION_NO_CONSTRUCT_FLOATS
:
8978 mips_disable_float_construction
= 1;
8990 target_big_endian
= 1;
8994 target_big_endian
= 0;
9002 if (arg
&& arg
[1] == '0')
9012 mips_debug
= atoi (arg
);
9013 /* When the MIPS assembler sees -g or -g2, it does not do
9014 optimizations which limit full symbolic debugging. We take
9015 that to be equivalent to -O0. */
9016 if (mips_debug
== 2)
9021 mips_opts
.isa
= ISA_MIPS1
;
9025 mips_opts
.isa
= ISA_MIPS2
;
9029 mips_opts
.isa
= ISA_MIPS3
;
9033 mips_opts
.isa
= ISA_MIPS4
;
9037 mips_opts
.isa
= ISA_MIPS5
;
9041 mips_opts
.isa
= ISA_MIPS32
;
9045 mips_opts
.isa
= ISA_MIPS64
;
9052 int cpu
= CPU_UNKNOWN
;
9054 /* Identify the processor type. */
9055 if (strcasecmp (arg
, "default") != 0)
9057 const struct mips_cpu_info
*ci
;
9059 ci
= mips_cpu_info_from_name (arg
);
9060 if (ci
== NULL
|| ci
->is_isa
)
9065 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9068 as_fatal (_("invalid architecture -march=%s"), arg
);
9071 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9082 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9083 as_warn(_("A different -mtune= was already specified, is now "
9088 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9089 as_warn(_("A different -march= was already specified, is now "
9094 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9095 as_warn(_("A different -mcpu= was already specified, is now "
9103 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9104 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9105 as_warn(_("A different -march= or -mtune= was already specified, "
9107 mips_arch
= CPU_R4650
;
9108 mips_tune
= CPU_R4650
;
9111 case OPTION_NO_M4650
:
9115 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9116 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9117 as_warn(_("A different -march= or -mtune= was already specified, "
9119 mips_arch
= CPU_R4010
;
9120 mips_tune
= CPU_R4010
;
9123 case OPTION_NO_M4010
:
9127 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9128 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9129 as_warn(_("A different -march= or -mtune= was already specified, "
9131 mips_arch
= CPU_VR4100
;
9132 mips_tune
= CPU_VR4100
;
9135 case OPTION_NO_M4100
:
9139 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9140 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9141 as_warn(_("A different -march= or -mtune= was already specified, "
9143 mips_arch
= CPU_R3900
;
9144 mips_tune
= CPU_R3900
;
9147 case OPTION_NO_M3900
:
9151 mips_opts
.mips16
= 1;
9152 mips_no_prev_insn (false);
9155 case OPTION_NO_MIPS16
:
9156 mips_opts
.mips16
= 0;
9157 mips_no_prev_insn (false);
9160 case OPTION_MEMBEDDED_PIC
:
9161 mips_pic
= EMBEDDED_PIC
;
9162 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9164 as_bad (_("-G may not be used with embedded PIC code"));
9167 g_switch_value
= 0x7fffffff;
9171 /* When generating ELF code, we permit -KPIC and -call_shared to
9172 select SVR4_PIC, and -non_shared to select no PIC. This is
9173 intended to be compatible with Irix 5. */
9174 case OPTION_CALL_SHARED
:
9175 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9177 as_bad (_("-call_shared is supported only for ELF format"));
9180 mips_pic
= SVR4_PIC
;
9181 if (g_switch_seen
&& g_switch_value
!= 0)
9183 as_bad (_("-G may not be used with SVR4 PIC code"));
9189 case OPTION_NON_SHARED
:
9190 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9192 as_bad (_("-non_shared is supported only for ELF format"));
9198 /* The -xgot option tells the assembler to use 32 offsets when
9199 accessing the got in SVR4_PIC mode. It is for Irix
9204 #endif /* OBJ_ELF */
9207 if (! USE_GLOBAL_POINTER_OPT
)
9209 as_bad (_("-G is not supported for this configuration"));
9212 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9214 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9218 g_switch_value
= atoi (arg
);
9223 /* The -32 and -64 options tell the assembler to output the 32
9224 bit or the 64 bit MIPS ELF format. */
9231 const char **list
, **l
;
9233 list
= bfd_target_list ();
9234 for (l
= list
; *l
!= NULL
; l
++)
9236 /* This is traditional mips */
9237 if (strcmp (*l
, "elf64-tradbigmips") == 0
9238 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9240 if (strcmp (*l
, "elf64-bigmips") == 0
9241 || strcmp (*l
, "elf64-littlemips") == 0)
9245 as_fatal (_("No compiled in support for 64 bit object file format"));
9250 #endif /* OBJ_ELF */
9256 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9257 flag in object files because to do so would make it
9258 impossible to link with libraries compiled without "-gp32".
9259 This is unnecessarily restrictive.
9261 We could solve this problem by adding "-gp32" multilibs to
9262 gcc, but to set this flag before gcc is built with such
9263 multilibs will break too many systems. */
9283 if (strcmp (arg
, "32") == 0
9284 || strcmp (arg
, "n32") == 0
9285 || strcmp (arg
, "64") == 0
9286 || strcmp (arg
, "o64") == 0
9287 || strcmp (arg
, "eabi") == 0)
9289 mips_abi_string
= arg
;
9290 mips_32bit_abi
= (strcmp (arg
, "32") == 0);
9294 case OPTION_M7000_HILO_FIX
:
9295 mips_7000_hilo_fix
= true;
9298 case OPTION_NO_M7000_HILO_FIX
:
9299 mips_7000_hilo_fix
= false;
9310 show (stream
, string
, col_p
, first_p
)
9318 fprintf (stream
, "%24s", "");
9323 fprintf (stream
, ", ");
9327 if (*col_p
+ strlen (string
) > 72)
9329 fprintf (stream
, "\n%24s", "");
9333 fprintf (stream
, "%s", string
);
9334 *col_p
+= strlen (string
);
9340 md_show_usage (stream
)
9345 fprintf (stream
, _("\
9347 -membedded-pic generate embedded position independent code\n\
9348 -EB generate big endian output\n\
9349 -EL generate little endian output\n\
9350 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9351 -G NUM allow referencing objects up to NUM bytes\n\
9352 implicitly with the gp register [default 8]\n"));
9353 fprintf (stream
, _("\
9354 -mips1 generate MIPS ISA I instructions\n\
9355 -mips2 generate MIPS ISA II instructions\n\
9356 -mips3 generate MIPS ISA III instructions\n\
9357 -mips4 generate MIPS ISA IV instructions\n\
9358 -mips5 generate MIPS ISA V instructions\n\
9359 -mips32 generate MIPS32 ISA instructions\n\
9360 -mips64 generate MIPS64 ISA instructions\n\
9361 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9365 show (stream
, "2000", &column
, &first
);
9366 show (stream
, "3000", &column
, &first
);
9367 show (stream
, "3900", &column
, &first
);
9368 show (stream
, "4000", &column
, &first
);
9369 show (stream
, "4010", &column
, &first
);
9370 show (stream
, "4100", &column
, &first
);
9371 show (stream
, "4111", &column
, &first
);
9372 show (stream
, "4300", &column
, &first
);
9373 show (stream
, "4400", &column
, &first
);
9374 show (stream
, "4600", &column
, &first
);
9375 show (stream
, "4650", &column
, &first
);
9376 show (stream
, "5000", &column
, &first
);
9377 show (stream
, "5200", &column
, &first
);
9378 show (stream
, "5230", &column
, &first
);
9379 show (stream
, "5231", &column
, &first
);
9380 show (stream
, "5261", &column
, &first
);
9381 show (stream
, "5721", &column
, &first
);
9382 show (stream
, "6000", &column
, &first
);
9383 show (stream
, "8000", &column
, &first
);
9384 show (stream
, "10000", &column
, &first
);
9385 show (stream
, "12000", &column
, &first
);
9386 show (stream
, "sb-1", &column
, &first
);
9387 fputc ('\n', stream
);
9389 fprintf (stream
, _("\
9390 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9391 -no-mCPU don't generate code specific to CPU.\n\
9392 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9396 show (stream
, "3900", &column
, &first
);
9397 show (stream
, "4010", &column
, &first
);
9398 show (stream
, "4100", &column
, &first
);
9399 show (stream
, "4650", &column
, &first
);
9400 fputc ('\n', stream
);
9402 fprintf (stream
, _("\
9403 -mips16 generate mips16 instructions\n\
9404 -no-mips16 do not generate mips16 instructions\n"));
9405 fprintf (stream
, _("\
9406 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9407 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9408 -O0 remove unneeded NOPs, do not swap branches\n\
9409 -O remove unneeded NOPs and swap branches\n\
9410 -n warn about NOPs generated from macros\n\
9411 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9412 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9413 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9415 fprintf (stream
, _("\
9416 -KPIC, -call_shared generate SVR4 position independent code\n\
9417 -non_shared do not generate position independent code\n\
9418 -xgot assume a 32 bit GOT\n\
9419 -32 create 32 bit object file (default)\n\
9420 -64 create 64 bit object file\n"));
9425 mips_init_after_args ()
9427 /* initialize opcodes */
9428 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9429 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9433 md_pcrel_from (fixP
)
9436 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9437 && fixP
->fx_addsy
!= (symbolS
*) NULL
9438 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9440 if (mips_pic
== EMBEDDED_PIC
)
9442 /* This makes a branch to an undefined symbol be a branch to the
9443 current location. */
9452 /* return the address of the delay slot */
9453 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9456 /* This is called before the symbol table is processed. In order to
9457 work with gcc when using mips-tfile, we must keep all local labels.
9458 However, in other cases, we want to discard them. If we were
9459 called with -g, but we didn't see any debugging information, it may
9460 mean that gcc is smuggling debugging information through to
9461 mips-tfile, in which case we must generate all local labels. */
9464 mips_frob_file_before_adjust ()
9466 #ifndef NO_ECOFF_DEBUGGING
9469 && ! ecoff_debugging_seen
)
9470 flag_keep_locals
= 1;
9474 /* Sort any unmatched HI16_S relocs so that they immediately precede
9475 the corresponding LO reloc. This is called before md_apply_fix and
9476 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9477 explicit use of the %hi modifier. */
9482 struct mips_hi_fixup
*l
;
9484 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9486 segment_info_type
*seginfo
;
9489 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9491 /* Check quickly whether the next fixup happens to be a matching
9493 if (l
->fixp
->fx_next
!= NULL
9494 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9495 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9496 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9499 /* Look through the fixups for this segment for a matching %lo.
9500 When we find one, move the %hi just in front of it. We do
9501 this in two passes. In the first pass, we try to find a
9502 unique %lo. In the second pass, we permit multiple %hi
9503 relocs for a single %lo (this is a GNU extension). */
9504 seginfo
= seg_info (l
->seg
);
9505 for (pass
= 0; pass
< 2; pass
++)
9510 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9512 /* Check whether this is a %lo fixup which matches l->fixp. */
9513 if (f
->fx_r_type
== BFD_RELOC_LO16
9514 && f
->fx_addsy
== l
->fixp
->fx_addsy
9515 && f
->fx_offset
== l
->fixp
->fx_offset
9518 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9519 || prev
->fx_addsy
!= f
->fx_addsy
9520 || prev
->fx_offset
!= f
->fx_offset
))
9524 /* Move l->fixp before f. */
9525 for (pf
= &seginfo
->fix_root
;
9527 pf
= &(*pf
)->fx_next
)
9528 assert (*pf
!= NULL
);
9530 *pf
= l
->fixp
->fx_next
;
9532 l
->fixp
->fx_next
= f
;
9534 seginfo
->fix_root
= l
->fixp
;
9536 prev
->fx_next
= l
->fixp
;
9547 #if 0 /* GCC code motion plus incomplete dead code elimination
9548 can leave a %hi without a %lo. */
9550 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9551 _("Unmatched %%hi reloc"));
9557 /* When generating embedded PIC code we need to use a special
9558 relocation to represent the difference of two symbols in the .text
9559 section (switch tables use a difference of this sort). See
9560 include/coff/mips.h for details. This macro checks whether this
9561 fixup requires the special reloc. */
9562 #define SWITCH_TABLE(fixp) \
9563 ((fixp)->fx_r_type == BFD_RELOC_32 \
9564 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9565 && (fixp)->fx_addsy != NULL \
9566 && (fixp)->fx_subsy != NULL \
9567 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9568 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9570 /* When generating embedded PIC code we must keep all PC relative
9571 relocations, in case the linker has to relax a call. We also need
9572 to keep relocations for switch table entries. */
9575 mips_force_relocation (fixp
)
9578 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9579 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9582 return (mips_pic
== EMBEDDED_PIC
9584 || SWITCH_TABLE (fixp
)
9585 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9586 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9589 /* Apply a fixup to the object file. */
9592 md_apply_fix (fixP
, valueP
)
9600 assert (fixP
->fx_size
== 4
9601 || fixP
->fx_r_type
== BFD_RELOC_16
9602 || fixP
->fx_r_type
== BFD_RELOC_64
9603 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9604 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9608 /* If we aren't adjusting this fixup to be against the section
9609 symbol, we need to adjust the value. */
9611 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9613 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9614 || ((S_IS_WEAK (fixP
->fx_addsy
)
9615 || S_IS_EXTERN (fixP
->fx_addsy
))
9616 && !S_IS_COMMON (fixP
->fx_addsy
))
9617 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9618 && (((bfd_get_section_flags (stdoutput
,
9619 S_GET_SEGMENT (fixP
->fx_addsy
))
9620 & SEC_LINK_ONCE
) != 0)
9621 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9623 sizeof (".gnu.linkonce") - 1))))
9626 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
9630 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
9632 /* In this case, the bfd_install_relocation routine will
9633 incorrectly add the symbol value back in. We just want
9634 the addend to appear in the object file. */
9637 /* Make sure the addend is still non-zero. If it became zero
9638 after the last operation, set it to a spurious value and
9639 subtract the same value from the object file's contents. */
9644 /* The in-place addends for LO16 relocations are signed;
9645 leave the matching HI16 in-place addends as zero. */
9646 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
9648 reloc_howto_type
*howto
;
9649 bfd_vma contents
, mask
, field
;
9651 howto
= bfd_reloc_type_lookup (stdoutput
,
9654 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
9659 /* MASK has bits set where the relocation should go.
9660 FIELD is -value, shifted into the appropriate place
9661 for this relocation. */
9662 mask
= 1 << (howto
->bitsize
- 1);
9663 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
9664 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
9666 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
9667 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9675 /* This code was generated using trial and error and so is
9676 fragile and not trustworthy. If you change it, you should
9677 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9679 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9681 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9683 /* BFD's REL handling, for MIPS, is _very_ weird.
9684 This gives the right results, but it can't possibly
9685 be the way things are supposed to work. */
9686 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
9687 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
9688 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9689 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9694 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9696 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9699 switch (fixP
->fx_r_type
)
9701 case BFD_RELOC_MIPS_JMP
:
9702 case BFD_RELOC_HI16
:
9703 case BFD_RELOC_HI16_S
:
9704 case BFD_RELOC_MIPS_GPREL
:
9705 case BFD_RELOC_MIPS_LITERAL
:
9706 case BFD_RELOC_MIPS_CALL16
:
9707 case BFD_RELOC_MIPS_GOT16
:
9708 case BFD_RELOC_MIPS_GPREL32
:
9709 case BFD_RELOC_MIPS_GOT_HI16
:
9710 case BFD_RELOC_MIPS_GOT_LO16
:
9711 case BFD_RELOC_MIPS_CALL_HI16
:
9712 case BFD_RELOC_MIPS_CALL_LO16
:
9713 case BFD_RELOC_MIPS16_GPREL
:
9715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9716 _("Invalid PC relative reloc"));
9717 /* Nothing needed to do. The value comes from the reloc entry */
9720 case BFD_RELOC_MIPS16_JMP
:
9721 /* We currently always generate a reloc against a symbol, which
9722 means that we don't want an addend even if the symbol is
9724 fixP
->fx_addnumber
= 0;
9727 case BFD_RELOC_PCREL_HI16_S
:
9728 /* The addend for this is tricky if it is internal, so we just
9729 do everything here rather than in bfd_install_relocation. */
9730 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9735 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9737 /* For an external symbol adjust by the address to make it
9738 pcrel_offset. We use the address of the RELLO reloc
9739 which follows this one. */
9740 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9741 + fixP
->fx_next
->fx_where
);
9743 value
= ((value
+ 0x8000) >> 16) & 0xffff;
9744 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9745 if (target_big_endian
)
9747 md_number_to_chars (buf
, value
, 2);
9750 case BFD_RELOC_PCREL_LO16
:
9751 /* The addend for this is tricky if it is internal, so we just
9752 do everything here rather than in bfd_install_relocation. */
9753 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9758 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9759 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9760 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9761 if (target_big_endian
)
9763 md_number_to_chars (buf
, value
, 2);
9767 /* This is handled like BFD_RELOC_32, but we output a sign
9768 extended value if we are only 32 bits. */
9770 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9772 if (8 <= sizeof (valueT
))
9773 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9780 w1
= w2
= fixP
->fx_where
;
9781 if (target_big_endian
)
9785 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9786 if ((value
& 0x80000000) != 0)
9790 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9797 /* If we are deleting this reloc entry, we must fill in the
9798 value now. This can happen if we have a .word which is not
9799 resolved when it appears but is later defined. We also need
9800 to fill in the value if this is an embedded PIC switch table
9803 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9804 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9809 /* If we are deleting this reloc entry, we must fill in the
9811 assert (fixP
->fx_size
== 2);
9813 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9817 case BFD_RELOC_LO16
:
9818 /* When handling an embedded PIC switch statement, we can wind
9819 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9822 if (value
+ 0x8000 > 0xffff)
9823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9824 _("relocation overflow"));
9825 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9826 if (target_big_endian
)
9828 md_number_to_chars (buf
, value
, 2);
9832 case BFD_RELOC_16_PCREL_S2
:
9833 if ((value
& 0x3) != 0)
9834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9835 _("Branch to odd address (%lx)"), (long) value
);
9839 case BFD_RELOC_16_PCREL
:
9841 * We need to save the bits in the instruction since fixup_segment()
9842 * might be deleting the relocation entry (i.e., a branch within
9843 * the current segment).
9845 if (!fixP
->fx_done
&& value
!= 0)
9847 /* If 'value' is zero, the remaining reloc code won't actually
9848 do the store, so it must be done here. This is probably
9851 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9853 value
= (offsetT
) value
>> 2;
9855 /* update old instruction data */
9856 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9857 if (target_big_endian
)
9858 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9860 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9862 if (value
+ 0x8000 <= 0xffff)
9863 insn
|= value
& 0xffff;
9866 /* The branch offset is too large. If this is an
9867 unconditional branch, and we are not generating PIC code,
9868 we can convert it to an absolute jump instruction. */
9869 if (mips_pic
== NO_PIC
9871 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9872 && (fixP
->fx_frag
->fr_address
9873 < text_section
->vma
+ text_section
->_raw_size
)
9874 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9875 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9876 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9878 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9879 insn
= 0x0c000000; /* jal */
9881 insn
= 0x08000000; /* j */
9882 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9884 fixP
->fx_addsy
= section_symbol (text_section
);
9885 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9889 /* FIXME. It would be possible in principle to handle
9890 conditional branches which overflow. They could be
9891 transformed into a branch around a jump. This would
9892 require setting up variant frags for each different
9893 branch type. The native MIPS assembler attempts to
9894 handle these cases, but it appears to do it
9896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9897 _("Branch out of range"));
9901 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9904 case BFD_RELOC_VTABLE_INHERIT
:
9907 && !S_IS_DEFINED (fixP
->fx_addsy
)
9908 && !S_IS_WEAK (fixP
->fx_addsy
))
9909 S_SET_WEAK (fixP
->fx_addsy
);
9912 case BFD_RELOC_VTABLE_ENTRY
:
9928 const struct mips_opcode
*p
;
9929 int treg
, sreg
, dreg
, shamt
;
9934 for (i
= 0; i
< NUMOPCODES
; ++i
)
9936 p
= &mips_opcodes
[i
];
9937 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9939 printf ("%08lx %s\t", oc
, p
->name
);
9940 treg
= (oc
>> 16) & 0x1f;
9941 sreg
= (oc
>> 21) & 0x1f;
9942 dreg
= (oc
>> 11) & 0x1f;
9943 shamt
= (oc
>> 6) & 0x1f;
9945 for (args
= p
->args
;; ++args
)
9956 printf ("%c", *args
);
9960 assert (treg
== sreg
);
9961 printf ("$%d,$%d", treg
, sreg
);
9966 printf ("$%d", dreg
);
9971 printf ("$%d", treg
);
9975 printf ("0x%x", treg
);
9980 printf ("$%d", sreg
);
9984 printf ("0x%08lx", oc
& 0x1ffffff);
9996 printf ("$%d", shamt
);
10007 printf (_("%08lx UNDEFINED\n"), oc
);
10018 name
= input_line_pointer
;
10019 c
= get_symbol_end ();
10020 p
= (symbolS
*) symbol_find_or_make (name
);
10021 *input_line_pointer
= c
;
10025 /* Align the current frag to a given power of two. The MIPS assembler
10026 also automatically adjusts any preceding label. */
10029 mips_align (to
, fill
, label
)
10034 mips_emit_delays (false);
10035 frag_align (to
, fill
, 0);
10036 record_alignment (now_seg
, to
);
10039 assert (S_GET_SEGMENT (label
) == now_seg
);
10040 symbol_set_frag (label
, frag_now
);
10041 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10045 /* Align to a given power of two. .align 0 turns off the automatic
10046 alignment used by the data creating pseudo-ops. */
10050 int x ATTRIBUTE_UNUSED
;
10053 register long temp_fill
;
10054 long max_alignment
= 15;
10058 o Note that the assembler pulls down any immediately preceeding label
10059 to the aligned address.
10060 o It's not documented but auto alignment is reinstated by
10061 a .align pseudo instruction.
10062 o Note also that after auto alignment is turned off the mips assembler
10063 issues an error on attempt to assemble an improperly aligned data item.
10068 temp
= get_absolute_expression ();
10069 if (temp
> max_alignment
)
10070 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10073 as_warn (_("Alignment negative: 0 assumed."));
10076 if (*input_line_pointer
== ',')
10078 input_line_pointer
++;
10079 temp_fill
= get_absolute_expression ();
10086 mips_align (temp
, (int) temp_fill
,
10087 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10094 demand_empty_rest_of_line ();
10098 mips_flush_pending_output ()
10100 mips_emit_delays (false);
10101 mips_clear_insn_labels ();
10110 /* When generating embedded PIC code, we only use the .text, .lit8,
10111 .sdata and .sbss sections. We change the .data and .rdata
10112 pseudo-ops to use .sdata. */
10113 if (mips_pic
== EMBEDDED_PIC
10114 && (sec
== 'd' || sec
== 'r'))
10118 /* The ELF backend needs to know that we are changing sections, so
10119 that .previous works correctly. We could do something like check
10120 for a obj_section_change_hook macro, but that might be confusing
10121 as it would not be appropriate to use it in the section changing
10122 functions in read.c, since obj-elf.c intercepts those. FIXME:
10123 This should be cleaner, somehow. */
10124 obj_elf_section_change_hook ();
10127 mips_emit_delays (false);
10137 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10138 demand_empty_rest_of_line ();
10142 if (USE_GLOBAL_POINTER_OPT
)
10144 seg
= subseg_new (RDATA_SECTION_NAME
,
10145 (subsegT
) get_absolute_expression ());
10146 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10148 bfd_set_section_flags (stdoutput
, seg
,
10154 if (strcmp (TARGET_OS
, "elf") != 0)
10155 record_alignment (seg
, 4);
10157 demand_empty_rest_of_line ();
10161 as_bad (_("No read only data section in this object file format"));
10162 demand_empty_rest_of_line ();
10168 if (USE_GLOBAL_POINTER_OPT
)
10170 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10171 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10173 bfd_set_section_flags (stdoutput
, seg
,
10174 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10176 if (strcmp (TARGET_OS
, "elf") != 0)
10177 record_alignment (seg
, 4);
10179 demand_empty_rest_of_line ();
10184 as_bad (_("Global pointers not supported; recompile -G 0"));
10185 demand_empty_rest_of_line ();
10194 mips_enable_auto_align ()
10205 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10206 mips_emit_delays (false);
10207 if (log_size
> 0 && auto_align
)
10208 mips_align (log_size
, 0, label
);
10209 mips_clear_insn_labels ();
10210 cons (1 << log_size
);
10214 s_float_cons (type
)
10219 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10221 mips_emit_delays (false);
10226 mips_align (3, 0, label
);
10228 mips_align (2, 0, label
);
10231 mips_clear_insn_labels ();
10236 /* Handle .globl. We need to override it because on Irix 5 you are
10239 where foo is an undefined symbol, to mean that foo should be
10240 considered to be the address of a function. */
10244 int x ATTRIBUTE_UNUSED
;
10251 name
= input_line_pointer
;
10252 c
= get_symbol_end ();
10253 symbolP
= symbol_find_or_make (name
);
10254 *input_line_pointer
= c
;
10255 SKIP_WHITESPACE ();
10257 /* On Irix 5, every global symbol that is not explicitly labelled as
10258 being a function is apparently labelled as being an object. */
10261 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10266 secname
= input_line_pointer
;
10267 c
= get_symbol_end ();
10268 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10270 as_bad (_("%s: no such section"), secname
);
10271 *input_line_pointer
= c
;
10273 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10274 flag
= BSF_FUNCTION
;
10277 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10279 S_SET_EXTERNAL (symbolP
);
10280 demand_empty_rest_of_line ();
10285 int x ATTRIBUTE_UNUSED
;
10290 opt
= input_line_pointer
;
10291 c
= get_symbol_end ();
10295 /* FIXME: What does this mean? */
10297 else if (strncmp (opt
, "pic", 3) == 0)
10301 i
= atoi (opt
+ 3);
10305 mips_pic
= SVR4_PIC
;
10307 as_bad (_(".option pic%d not supported"), i
);
10309 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10311 if (g_switch_seen
&& g_switch_value
!= 0)
10312 as_warn (_("-G may not be used with SVR4 PIC code"));
10313 g_switch_value
= 0;
10314 bfd_set_gp_size (stdoutput
, 0);
10318 as_warn (_("Unrecognized option \"%s\""), opt
);
10320 *input_line_pointer
= c
;
10321 demand_empty_rest_of_line ();
10324 /* This structure is used to hold a stack of .set values. */
10326 struct mips_option_stack
10328 struct mips_option_stack
*next
;
10329 struct mips_set_options options
;
10332 static struct mips_option_stack
*mips_opts_stack
;
10334 /* Handle the .set pseudo-op. */
10338 int x ATTRIBUTE_UNUSED
;
10340 char *name
= input_line_pointer
, ch
;
10342 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10343 input_line_pointer
++;
10344 ch
= *input_line_pointer
;
10345 *input_line_pointer
= '\0';
10347 if (strcmp (name
, "reorder") == 0)
10349 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10351 /* If we still have pending nops, we can discard them. The
10352 usual nop handling will insert any that are still
10354 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10355 * (mips_opts
.mips16
? 2 : 4));
10356 prev_nop_frag
= NULL
;
10358 mips_opts
.noreorder
= 0;
10360 else if (strcmp (name
, "noreorder") == 0)
10362 mips_emit_delays (true);
10363 mips_opts
.noreorder
= 1;
10364 mips_any_noreorder
= 1;
10366 else if (strcmp (name
, "at") == 0)
10368 mips_opts
.noat
= 0;
10370 else if (strcmp (name
, "noat") == 0)
10372 mips_opts
.noat
= 1;
10374 else if (strcmp (name
, "macro") == 0)
10376 mips_opts
.warn_about_macros
= 0;
10378 else if (strcmp (name
, "nomacro") == 0)
10380 if (mips_opts
.noreorder
== 0)
10381 as_bad (_("`noreorder' must be set before `nomacro'"));
10382 mips_opts
.warn_about_macros
= 1;
10384 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10386 mips_opts
.nomove
= 0;
10388 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10390 mips_opts
.nomove
= 1;
10392 else if (strcmp (name
, "bopt") == 0)
10394 mips_opts
.nobopt
= 0;
10396 else if (strcmp (name
, "nobopt") == 0)
10398 mips_opts
.nobopt
= 1;
10400 else if (strcmp (name
, "mips16") == 0
10401 || strcmp (name
, "MIPS-16") == 0)
10402 mips_opts
.mips16
= 1;
10403 else if (strcmp (name
, "nomips16") == 0
10404 || strcmp (name
, "noMIPS-16") == 0)
10405 mips_opts
.mips16
= 0;
10406 else if (strncmp (name
, "mips", 4) == 0)
10409 static int saved_mips_gp32
;
10410 static int saved_mips_fp32
;
10411 static int saved_mips_32bit_abi
;
10412 static int is_saved
;
10414 /* Permit the user to change the ISA on the fly. Needless to
10415 say, misuse can cause serious problems. */
10416 isa
= atoi (name
+ 4);
10420 mips_gp32
= saved_mips_gp32
;
10421 mips_fp32
= saved_mips_fp32
;
10422 mips_32bit_abi
= saved_mips_32bit_abi
;
10430 saved_mips_gp32
= mips_gp32
;
10431 saved_mips_fp32
= mips_fp32
;
10432 saved_mips_32bit_abi
= mips_32bit_abi
;
10444 saved_mips_gp32
= mips_gp32
;
10445 saved_mips_fp32
= mips_fp32
;
10446 saved_mips_32bit_abi
= mips_32bit_abi
;
10450 mips_32bit_abi
= 0;
10454 as_bad (_("unknown ISA level"));
10460 case 0: mips_opts
.isa
= file_mips_isa
; break;
10461 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10462 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10463 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10464 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10465 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10466 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10467 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10468 default: as_bad (_("unknown ISA level")); break;
10471 else if (strcmp (name
, "autoextend") == 0)
10472 mips_opts
.noautoextend
= 0;
10473 else if (strcmp (name
, "noautoextend") == 0)
10474 mips_opts
.noautoextend
= 1;
10475 else if (strcmp (name
, "push") == 0)
10477 struct mips_option_stack
*s
;
10479 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10480 s
->next
= mips_opts_stack
;
10481 s
->options
= mips_opts
;
10482 mips_opts_stack
= s
;
10484 else if (strcmp (name
, "pop") == 0)
10486 struct mips_option_stack
*s
;
10488 s
= mips_opts_stack
;
10490 as_bad (_(".set pop with no .set push"));
10493 /* If we're changing the reorder mode we need to handle
10494 delay slots correctly. */
10495 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10496 mips_emit_delays (true);
10497 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10499 if (prev_nop_frag
!= NULL
)
10501 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10502 * (mips_opts
.mips16
? 2 : 4));
10503 prev_nop_frag
= NULL
;
10507 mips_opts
= s
->options
;
10508 mips_opts_stack
= s
->next
;
10514 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10516 *input_line_pointer
= ch
;
10517 demand_empty_rest_of_line ();
10520 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10521 .option pic2. It means to generate SVR4 PIC calls. */
10524 s_abicalls (ignore
)
10525 int ignore ATTRIBUTE_UNUSED
;
10527 mips_pic
= SVR4_PIC
;
10528 if (USE_GLOBAL_POINTER_OPT
)
10530 if (g_switch_seen
&& g_switch_value
!= 0)
10531 as_warn (_("-G may not be used with SVR4 PIC code"));
10532 g_switch_value
= 0;
10534 bfd_set_gp_size (stdoutput
, 0);
10535 demand_empty_rest_of_line ();
10538 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10539 PIC code. It sets the $gp register for the function based on the
10540 function address, which is in the register named in the argument.
10541 This uses a relocation against _gp_disp, which is handled specially
10542 by the linker. The result is:
10543 lui $gp,%hi(_gp_disp)
10544 addiu $gp,$gp,%lo(_gp_disp)
10545 addu $gp,$gp,.cpload argument
10546 The .cpload argument is normally $25 == $t9. */
10550 int ignore ATTRIBUTE_UNUSED
;
10555 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10556 if (mips_pic
!= SVR4_PIC
)
10562 /* .cpload should be a in .set noreorder section. */
10563 if (mips_opts
.noreorder
== 0)
10564 as_warn (_(".cpload not in noreorder section"));
10566 ex
.X_op
= O_symbol
;
10567 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10568 ex
.X_op_symbol
= NULL
;
10569 ex
.X_add_number
= 0;
10571 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10572 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10574 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10575 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10576 (int) BFD_RELOC_LO16
);
10578 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10579 GP
, GP
, tc_get_register (0));
10581 demand_empty_rest_of_line ();
10584 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10585 offset from $sp. The offset is remembered, and after making a PIC
10586 call $gp is restored from that location. */
10589 s_cprestore (ignore
)
10590 int ignore ATTRIBUTE_UNUSED
;
10595 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10596 if (mips_pic
!= SVR4_PIC
)
10602 mips_cprestore_offset
= get_absolute_expression ();
10604 ex
.X_op
= O_constant
;
10605 ex
.X_add_symbol
= NULL
;
10606 ex
.X_op_symbol
= NULL
;
10607 ex
.X_add_number
= mips_cprestore_offset
;
10609 macro_build ((char *) NULL
, &icnt
, &ex
,
10610 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
10611 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10613 demand_empty_rest_of_line ();
10616 /* Handle the .gpword pseudo-op. This is used when generating PIC
10617 code. It generates a 32 bit GP relative reloc. */
10621 int ignore ATTRIBUTE_UNUSED
;
10627 /* When not generating PIC code, this is treated as .word. */
10628 if (mips_pic
!= SVR4_PIC
)
10634 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10635 mips_emit_delays (true);
10637 mips_align (2, 0, label
);
10638 mips_clear_insn_labels ();
10642 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10644 as_bad (_("Unsupported use of .gpword"));
10645 ignore_rest_of_line ();
10649 md_number_to_chars (p
, (valueT
) 0, 4);
10650 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10651 BFD_RELOC_MIPS_GPREL32
);
10653 demand_empty_rest_of_line ();
10656 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10657 tables in SVR4 PIC code. */
10661 int ignore ATTRIBUTE_UNUSED
;
10666 /* This is ignored when not generating SVR4 PIC code. */
10667 if (mips_pic
!= SVR4_PIC
)
10673 /* Add $gp to the register named as an argument. */
10674 reg
= tc_get_register (0);
10675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10676 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
10677 "d,v,t", reg
, reg
, GP
);
10679 demand_empty_rest_of_line ();
10682 /* Handle the .insn pseudo-op. This marks instruction labels in
10683 mips16 mode. This permits the linker to handle them specially,
10684 such as generating jalx instructions when needed. We also make
10685 them odd for the duration of the assembly, in order to generate the
10686 right sort of code. We will make them even in the adjust_symtab
10687 routine, while leaving them marked. This is convenient for the
10688 debugger and the disassembler. The linker knows to make them odd
10693 int ignore ATTRIBUTE_UNUSED
;
10695 if (mips_opts
.mips16
)
10696 mips16_mark_labels ();
10698 demand_empty_rest_of_line ();
10701 /* Handle a .stabn directive. We need these in order to mark a label
10702 as being a mips16 text label correctly. Sometimes the compiler
10703 will emit a label, followed by a .stabn, and then switch sections.
10704 If the label and .stabn are in mips16 mode, then the label is
10705 really a mips16 text label. */
10711 if (type
== 'n' && mips_opts
.mips16
)
10712 mips16_mark_labels ();
10717 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10721 s_mips_weakext (ignore
)
10722 int ignore ATTRIBUTE_UNUSED
;
10729 name
= input_line_pointer
;
10730 c
= get_symbol_end ();
10731 symbolP
= symbol_find_or_make (name
);
10732 S_SET_WEAK (symbolP
);
10733 *input_line_pointer
= c
;
10735 SKIP_WHITESPACE ();
10737 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10739 if (S_IS_DEFINED (symbolP
))
10741 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10742 S_GET_NAME (symbolP
));
10743 ignore_rest_of_line ();
10747 if (*input_line_pointer
== ',')
10749 ++input_line_pointer
;
10750 SKIP_WHITESPACE ();
10754 if (exp
.X_op
!= O_symbol
)
10756 as_bad ("bad .weakext directive");
10757 ignore_rest_of_line();
10760 symbol_set_value_expression (symbolP
, &exp
);
10763 demand_empty_rest_of_line ();
10766 /* Parse a register string into a number. Called from the ECOFF code
10767 to parse .frame. The argument is non-zero if this is the frame
10768 register, so that we can record it in mips_frame_reg. */
10771 tc_get_register (frame
)
10776 SKIP_WHITESPACE ();
10777 if (*input_line_pointer
++ != '$')
10779 as_warn (_("expected `$'"));
10782 else if (isdigit ((unsigned char) *input_line_pointer
))
10784 reg
= get_absolute_expression ();
10785 if (reg
< 0 || reg
>= 32)
10787 as_warn (_("Bad register number"));
10793 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10795 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10797 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10799 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10803 as_warn (_("Unrecognized register name"));
10806 input_line_pointer
+= 2;
10809 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10814 md_section_align (seg
, addr
)
10818 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10821 /* We don't need to align ELF sections to the full alignment.
10822 However, Irix 5 may prefer that we align them at least to a 16
10823 byte boundary. We don't bother to align the sections if we are
10824 targeted for an embedded system. */
10825 if (strcmp (TARGET_OS
, "elf") == 0)
10831 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10834 /* Utility routine, called from above as well. If called while the
10835 input file is still being read, it's only an approximation. (For
10836 example, a symbol may later become defined which appeared to be
10837 undefined earlier.) */
10840 nopic_need_relax (sym
, before_relaxing
)
10842 int before_relaxing
;
10847 if (USE_GLOBAL_POINTER_OPT
)
10849 const char *symname
;
10852 /* Find out whether this symbol can be referenced off the GP
10853 register. It can be if it is smaller than the -G size or if
10854 it is in the .sdata or .sbss section. Certain symbols can
10855 not be referenced off the GP, although it appears as though
10857 symname
= S_GET_NAME (sym
);
10858 if (symname
!= (const char *) NULL
10859 && (strcmp (symname
, "eprol") == 0
10860 || strcmp (symname
, "etext") == 0
10861 || strcmp (symname
, "_gp") == 0
10862 || strcmp (symname
, "edata") == 0
10863 || strcmp (symname
, "_fbss") == 0
10864 || strcmp (symname
, "_fdata") == 0
10865 || strcmp (symname
, "_ftext") == 0
10866 || strcmp (symname
, "end") == 0
10867 || strcmp (symname
, "_gp_disp") == 0))
10869 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10871 #ifndef NO_ECOFF_DEBUGGING
10872 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10873 && (symbol_get_obj (sym
)->ecoff_extern_size
10874 <= g_switch_value
))
10876 /* We must defer this decision until after the whole
10877 file has been read, since there might be a .extern
10878 after the first use of this symbol. */
10879 || (before_relaxing
10880 #ifndef NO_ECOFF_DEBUGGING
10881 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10883 && S_GET_VALUE (sym
) == 0)
10884 || (S_GET_VALUE (sym
) != 0
10885 && S_GET_VALUE (sym
) <= g_switch_value
)))
10889 const char *segname
;
10891 segname
= segment_name (S_GET_SEGMENT (sym
));
10892 assert (strcmp (segname
, ".lit8") != 0
10893 && strcmp (segname
, ".lit4") != 0);
10894 change
= (strcmp (segname
, ".sdata") != 0
10895 && strcmp (segname
, ".sbss") != 0
10896 && strncmp (segname
, ".sdata.", 7) != 0
10897 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10902 /* We are not optimizing for the GP register. */
10906 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10907 extended opcode. SEC is the section the frag is in. */
10910 mips16_extended_frag (fragp
, sec
, stretch
)
10916 register const struct mips16_immed_operand
*op
;
10918 int mintiny
, maxtiny
;
10922 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10924 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10927 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10928 op
= mips16_immed_operands
;
10929 while (op
->type
!= type
)
10932 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10937 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10940 maxtiny
= 1 << op
->nbits
;
10945 maxtiny
= (1 << op
->nbits
) - 1;
10950 mintiny
= - (1 << (op
->nbits
- 1));
10951 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10954 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
10955 val
= S_GET_VALUE (fragp
->fr_symbol
);
10956 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10962 /* We won't have the section when we are called from
10963 mips_relax_frag. However, we will always have been called
10964 from md_estimate_size_before_relax first. If this is a
10965 branch to a different section, we mark it as such. If SEC is
10966 NULL, and the frag is not marked, then it must be a branch to
10967 the same section. */
10970 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10975 /* Must have been called from md_estimate_size_before_relax. */
10978 fragp
->fr_subtype
=
10979 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10981 /* FIXME: We should support this, and let the linker
10982 catch branches and loads that are out of range. */
10983 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10984 _("unsupported PC relative reference to different section"));
10988 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
10989 /* Assume non-extended on the first relaxation pass.
10990 The address we have calculated will be bogus if this is
10991 a forward branch to another frag, as the forward frag
10992 will have fr_address == 0. */
10996 /* In this case, we know for sure that the symbol fragment is in
10997 the same section. If the relax_marker of the symbol fragment
10998 differs from the relax_marker of this fragment, we have not
10999 yet adjusted the symbol fragment fr_address. We want to add
11000 in STRETCH in order to get a better estimate of the address.
11001 This particularly matters because of the shift bits. */
11003 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11007 /* Adjust stretch for any alignment frag. Note that if have
11008 been expanding the earlier code, the symbol may be
11009 defined in what appears to be an earlier frag. FIXME:
11010 This doesn't handle the fr_subtype field, which specifies
11011 a maximum number of bytes to skip when doing an
11013 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11015 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11018 stretch
= - ((- stretch
)
11019 & ~ ((1 << (int) f
->fr_offset
) - 1));
11021 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11030 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11032 /* The base address rules are complicated. The base address of
11033 a branch is the following instruction. The base address of a
11034 PC relative load or add is the instruction itself, but if it
11035 is in a delay slot (in which case it can not be extended) use
11036 the address of the instruction whose delay slot it is in. */
11037 if (type
== 'p' || type
== 'q')
11041 /* If we are currently assuming that this frag should be
11042 extended, then, the current address is two bytes
11044 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11047 /* Ignore the low bit in the target, since it will be set
11048 for a text label. */
11049 if ((val
& 1) != 0)
11052 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11054 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11057 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11059 /* Branch offsets have an implicit 0 in the lowest bit. */
11060 if (type
== 'p' || type
== 'q')
11063 /* If any of the shifted bits are set, we must use an extended
11064 opcode. If the address depends on the size of this
11065 instruction, this can lead to a loop, so we arrange to always
11066 use an extended opcode. We only check this when we are in
11067 the main relaxation loop, when SEC is NULL. */
11068 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11070 fragp
->fr_subtype
=
11071 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11075 /* If we are about to mark a frag as extended because the value
11076 is precisely maxtiny + 1, then there is a chance of an
11077 infinite loop as in the following code:
11082 In this case when the la is extended, foo is 0x3fc bytes
11083 away, so the la can be shrunk, but then foo is 0x400 away, so
11084 the la must be extended. To avoid this loop, we mark the
11085 frag as extended if it was small, and is about to become
11086 extended with a value of maxtiny + 1. */
11087 if (val
== ((maxtiny
+ 1) << op
->shift
)
11088 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11091 fragp
->fr_subtype
=
11092 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11096 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11097 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11099 if ((val
& ((1 << op
->shift
) - 1)) != 0
11100 || val
< (mintiny
<< op
->shift
)
11101 || val
> (maxtiny
<< op
->shift
))
11107 /* Estimate the size of a frag before relaxing. Unless this is the
11108 mips16, we are not really relaxing here, and the final size is
11109 encoded in the subtype information. For the mips16, we have to
11110 decide whether we are using an extended opcode or not. */
11113 md_estimate_size_before_relax (fragp
, segtype
)
11118 boolean linkonce
= false;
11120 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11122 if (mips16_extended_frag (fragp
, segtype
, 0))
11124 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11129 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11134 if (mips_pic
== NO_PIC
)
11136 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11138 else if (mips_pic
== SVR4_PIC
)
11143 sym
= fragp
->fr_symbol
;
11145 /* Handle the case of a symbol equated to another symbol. */
11146 while (symbol_equated_reloc_p (sym
))
11150 /* It's possible to get a loop here in a badly written
11152 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11158 symsec
= S_GET_SEGMENT (sym
);
11160 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11161 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11163 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11167 /* The GNU toolchain uses an extension for ELF: a section
11168 beginning with the magic string .gnu.linkonce is a linkonce
11170 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11171 sizeof ".gnu.linkonce" - 1) == 0)
11175 /* This must duplicate the test in adjust_reloc_syms. */
11176 change
= (symsec
!= &bfd_und_section
11177 && symsec
!= &bfd_abs_section
11178 && ! bfd_is_com_section (symsec
)
11181 /* A global or weak symbol is treated as external. */
11182 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11183 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11192 /* Record the offset to the first reloc in the fr_opcode field.
11193 This lets md_convert_frag and tc_gen_reloc know that the code
11194 must be expanded. */
11195 fragp
->fr_opcode
= (fragp
->fr_literal
11197 - RELAX_OLD (fragp
->fr_subtype
)
11198 + RELAX_RELOC1 (fragp
->fr_subtype
));
11199 /* FIXME: This really needs as_warn_where. */
11200 if (RELAX_WARN (fragp
->fr_subtype
))
11201 as_warn (_("AT used after \".set noat\" or macro used after "
11202 "\".set nomacro\""));
11204 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11210 /* This is called to see whether a reloc against a defined symbol
11211 should be converted into a reloc against a section. Don't adjust
11212 MIPS16 jump relocations, so we don't have to worry about the format
11213 of the offset in the .o file. Don't adjust relocations against
11214 mips16 symbols, so that the linker can find them if it needs to set
11218 mips_fix_adjustable (fixp
)
11222 /* Prevent all adjustments to global symbols. */
11223 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11224 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
11227 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11229 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11230 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11232 if (fixp
->fx_addsy
== NULL
)
11235 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11236 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11237 && fixp
->fx_subsy
== NULL
)
11243 /* Translate internal representation of relocation info to BFD target
11247 tc_gen_reloc (section
, fixp
)
11248 asection
*section ATTRIBUTE_UNUSED
;
11251 static arelent
*retval
[4];
11253 bfd_reloc_code_real_type code
;
11255 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11258 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11259 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11260 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11262 if (mips_pic
== EMBEDDED_PIC
11263 && SWITCH_TABLE (fixp
))
11265 /* For a switch table entry we use a special reloc. The addend
11266 is actually the difference between the reloc address and the
11268 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11269 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11270 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11271 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11273 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11274 reloc
->addend
= fixp
->fx_addnumber
;
11275 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11277 /* We use a special addend for an internal RELLO reloc. */
11278 if (symbol_section_p (fixp
->fx_addsy
))
11279 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11281 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11283 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11285 assert (fixp
->fx_next
!= NULL
11286 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11287 /* We use a special addend for an internal RELHI reloc. The
11288 reloc is relative to the RELLO; adjust the addend
11290 if (symbol_section_p (fixp
->fx_addsy
))
11291 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11292 + fixp
->fx_next
->fx_where
11293 - S_GET_VALUE (fixp
->fx_subsy
));
11295 reloc
->addend
= (fixp
->fx_addnumber
11296 + fixp
->fx_next
->fx_frag
->fr_address
11297 + fixp
->fx_next
->fx_where
);
11301 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11302 /* A gruesome hack which is a result of the gruesome gas reloc
11304 reloc
->addend
= reloc
->address
;
11306 reloc
->addend
= -reloc
->address
;
11309 /* If this is a variant frag, we may need to adjust the existing
11310 reloc and generate a new one. */
11311 if (fixp
->fx_frag
->fr_opcode
!= NULL
11312 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11313 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11314 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11315 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11316 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11317 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11318 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11322 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11324 /* If this is not the last reloc in this frag, then we have two
11325 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11326 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11327 the second one handle all of them. */
11328 if (fixp
->fx_next
!= NULL
11329 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11331 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11332 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11333 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11334 && (fixp
->fx_next
->fx_r_type
11335 == BFD_RELOC_MIPS_GOT_LO16
))
11336 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11337 && (fixp
->fx_next
->fx_r_type
11338 == BFD_RELOC_MIPS_CALL_LO16
)));
11343 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11344 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11345 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11347 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11348 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11349 reloc2
->address
= (reloc
->address
11350 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11351 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11352 reloc2
->addend
= fixp
->fx_addnumber
;
11353 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11354 assert (reloc2
->howto
!= NULL
);
11356 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11360 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11363 reloc3
->address
+= 4;
11366 if (mips_pic
== NO_PIC
)
11368 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11369 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11371 else if (mips_pic
== SVR4_PIC
)
11373 switch (fixp
->fx_r_type
)
11377 case BFD_RELOC_MIPS_GOT16
:
11379 case BFD_RELOC_MIPS_CALL16
:
11380 case BFD_RELOC_MIPS_GOT_LO16
:
11381 case BFD_RELOC_MIPS_CALL_LO16
:
11382 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11390 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11391 to be used in the relocation's section offset. */
11392 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11394 reloc
->address
= reloc
->addend
;
11398 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11399 fixup_segment converted a non-PC relative reloc into a PC
11400 relative reloc. In such a case, we need to convert the reloc
11402 code
= fixp
->fx_r_type
;
11403 if (fixp
->fx_pcrel
)
11408 code
= BFD_RELOC_8_PCREL
;
11411 code
= BFD_RELOC_16_PCREL
;
11414 code
= BFD_RELOC_32_PCREL
;
11417 code
= BFD_RELOC_64_PCREL
;
11419 case BFD_RELOC_8_PCREL
:
11420 case BFD_RELOC_16_PCREL
:
11421 case BFD_RELOC_32_PCREL
:
11422 case BFD_RELOC_64_PCREL
:
11423 case BFD_RELOC_16_PCREL_S2
:
11424 case BFD_RELOC_PCREL_HI16_S
:
11425 case BFD_RELOC_PCREL_LO16
:
11428 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11429 _("Cannot make %s relocation PC relative"),
11430 bfd_get_reloc_code_name (code
));
11434 /* To support a PC relative reloc when generating embedded PIC code
11435 for ECOFF, we use a Cygnus extension. We check for that here to
11436 make sure that we don't let such a reloc escape normally. */
11437 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11438 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11439 && code
== BFD_RELOC_16_PCREL_S2
11440 && mips_pic
!= EMBEDDED_PIC
)
11441 reloc
->howto
= NULL
;
11443 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11445 if (reloc
->howto
== NULL
)
11447 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11448 _("Can not represent %s relocation in this object file format"),
11449 bfd_get_reloc_code_name (code
));
11456 /* Relax a machine dependent frag. This returns the amount by which
11457 the current size of the frag should change. */
11460 mips_relax_frag (fragp
, stretch
)
11464 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11467 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11469 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11471 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11476 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11478 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11485 /* Convert a machine dependent frag. */
11488 md_convert_frag (abfd
, asec
, fragp
)
11489 bfd
*abfd ATTRIBUTE_UNUSED
;
11496 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11499 register const struct mips16_immed_operand
*op
;
11500 boolean small
, ext
;
11503 unsigned long insn
;
11504 boolean use_extend
;
11505 unsigned short extend
;
11507 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11508 op
= mips16_immed_operands
;
11509 while (op
->type
!= type
)
11512 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11523 resolve_symbol_value (fragp
->fr_symbol
);
11524 val
= S_GET_VALUE (fragp
->fr_symbol
);
11529 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11531 /* The rules for the base address of a PC relative reloc are
11532 complicated; see mips16_extended_frag. */
11533 if (type
== 'p' || type
== 'q')
11538 /* Ignore the low bit in the target, since it will be
11539 set for a text label. */
11540 if ((val
& 1) != 0)
11543 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11545 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11548 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11551 /* Make sure the section winds up with the alignment we have
11554 record_alignment (asec
, op
->shift
);
11558 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11559 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11560 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11561 _("extended instruction in delay slot"));
11563 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11565 if (target_big_endian
)
11566 insn
= bfd_getb16 (buf
);
11568 insn
= bfd_getl16 (buf
);
11570 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11571 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11572 small
, ext
, &insn
, &use_extend
, &extend
);
11576 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11577 fragp
->fr_fix
+= 2;
11581 md_number_to_chars (buf
, insn
, 2);
11582 fragp
->fr_fix
+= 2;
11587 if (fragp
->fr_opcode
== NULL
)
11590 old
= RELAX_OLD (fragp
->fr_subtype
);
11591 new = RELAX_NEW (fragp
->fr_subtype
);
11592 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11595 memcpy (fixptr
- old
, fixptr
, new);
11597 fragp
->fr_fix
+= new - old
;
11603 /* This function is called after the relocs have been generated.
11604 We've been storing mips16 text labels as odd. Here we convert them
11605 back to even for the convenience of the debugger. */
11608 mips_frob_file_after_relocs ()
11611 unsigned int count
, i
;
11613 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11616 syms
= bfd_get_outsymbols (stdoutput
);
11617 count
= bfd_get_symcount (stdoutput
);
11618 for (i
= 0; i
< count
; i
++, syms
++)
11620 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11621 && ((*syms
)->value
& 1) != 0)
11623 (*syms
)->value
&= ~1;
11624 /* If the symbol has an odd size, it was probably computed
11625 incorrectly, so adjust that as well. */
11626 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11627 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11634 /* This function is called whenever a label is defined. It is used
11635 when handling branch delays; if a branch has a label, we assume we
11636 can not move it. */
11639 mips_define_label (sym
)
11642 struct insn_label_list
*l
;
11644 if (free_insn_labels
== NULL
)
11645 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11648 l
= free_insn_labels
;
11649 free_insn_labels
= l
->next
;
11653 l
->next
= insn_labels
;
11657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11659 /* Some special processing for a MIPS ELF file. */
11662 mips_elf_final_processing ()
11664 /* Write out the register information. */
11669 s
.ri_gprmask
= mips_gprmask
;
11670 s
.ri_cprmask
[0] = mips_cprmask
[0];
11671 s
.ri_cprmask
[1] = mips_cprmask
[1];
11672 s
.ri_cprmask
[2] = mips_cprmask
[2];
11673 s
.ri_cprmask
[3] = mips_cprmask
[3];
11674 /* The gp_value field is set by the MIPS ELF backend. */
11676 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11677 ((Elf32_External_RegInfo
*)
11678 mips_regmask_frag
));
11682 Elf64_Internal_RegInfo s
;
11684 s
.ri_gprmask
= mips_gprmask
;
11686 s
.ri_cprmask
[0] = mips_cprmask
[0];
11687 s
.ri_cprmask
[1] = mips_cprmask
[1];
11688 s
.ri_cprmask
[2] = mips_cprmask
[2];
11689 s
.ri_cprmask
[3] = mips_cprmask
[3];
11690 /* The gp_value field is set by the MIPS ELF backend. */
11692 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11693 ((Elf64_External_RegInfo
*)
11694 mips_regmask_frag
));
11697 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11698 sort of BFD interface for this. */
11699 if (mips_any_noreorder
)
11700 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11701 if (mips_pic
!= NO_PIC
)
11702 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11704 /* Set the MIPS ELF ABI flags. */
11705 if (mips_abi_string
== NULL
)
11707 else if (strcmp (mips_abi_string
, "32") == 0)
11708 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11709 else if (strcmp (mips_abi_string
, "o64") == 0)
11710 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11711 else if (strcmp (mips_abi_string
, "eabi") == 0)
11714 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11716 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11718 else if (strcmp (mips_abi_string
, "n32") == 0)
11719 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
11721 /* Nothing to do for "64". */
11723 if (mips_32bitmode
)
11724 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11727 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11729 typedef struct proc
{
11731 unsigned long reg_mask
;
11732 unsigned long reg_offset
;
11733 unsigned long fpreg_mask
;
11734 unsigned long fpreg_offset
;
11735 unsigned long frame_offset
;
11736 unsigned long frame_reg
;
11737 unsigned long pc_reg
;
11740 static procS cur_proc
;
11741 static procS
*cur_proc_ptr
;
11742 static int numprocs
;
11744 /* Fill in an rs_align_code fragment. */
11747 mips_handle_align (fragp
)
11750 if (fragp
->fr_type
!= rs_align_code
)
11753 if (mips_opts
.mips16
)
11755 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11756 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11761 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11762 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11767 fragp
->fr_fix
+= 1;
11770 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11774 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11785 /* check for premature end, nesting errors, etc */
11787 as_warn (_("missing .end at end of assembly"));
11796 if (*input_line_pointer
== '-')
11798 ++input_line_pointer
;
11801 if (!isdigit ((unsigned char) *input_line_pointer
))
11802 as_bad (_("Expected simple number."));
11803 if (input_line_pointer
[0] == '0')
11805 if (input_line_pointer
[1] == 'x')
11807 input_line_pointer
+= 2;
11808 while (isxdigit ((unsigned char) *input_line_pointer
))
11811 val
|= hex_value (*input_line_pointer
++);
11813 return negative
? -val
: val
;
11817 ++input_line_pointer
;
11818 while (isdigit ((unsigned char) *input_line_pointer
))
11821 val
|= *input_line_pointer
++ - '0';
11823 return negative
? -val
: val
;
11826 if (!isdigit ((unsigned char) *input_line_pointer
))
11828 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11829 *input_line_pointer
, *input_line_pointer
);
11830 as_warn (_("Invalid number"));
11833 while (isdigit ((unsigned char) *input_line_pointer
))
11836 val
+= *input_line_pointer
++ - '0';
11838 return negative
? -val
: val
;
11841 /* The .file directive; just like the usual .file directive, but there
11842 is an initial number which is the ECOFF file index. */
11846 int x ATTRIBUTE_UNUSED
;
11850 line
= get_number ();
11854 /* The .end directive. */
11858 int x ATTRIBUTE_UNUSED
;
11863 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11866 demand_empty_rest_of_line ();
11871 #ifdef BFD_ASSEMBLER
11872 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11877 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11884 as_warn (_(".end not in text section"));
11888 as_warn (_(".end directive without a preceding .ent directive."));
11889 demand_empty_rest_of_line ();
11895 assert (S_GET_NAME (p
));
11896 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11897 as_warn (_(".end symbol does not match .ent symbol."));
11900 as_warn (_(".end directive missing or unknown symbol"));
11902 #ifdef MIPS_STABS_ELF
11904 segT saved_seg
= now_seg
;
11905 subsegT saved_subseg
= now_subseg
;
11910 dot
= frag_now_fix ();
11912 #ifdef md_flush_pending_output
11913 md_flush_pending_output ();
11917 subseg_set (pdr_seg
, 0);
11919 /* Write the symbol. */
11920 exp
.X_op
= O_symbol
;
11921 exp
.X_add_symbol
= p
;
11922 exp
.X_add_number
= 0;
11923 emit_expr (&exp
, 4);
11925 fragp
= frag_more (7 * 4);
11927 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11928 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11929 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11930 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11931 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11932 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11933 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11935 subseg_set (saved_seg
, saved_subseg
);
11939 cur_proc_ptr
= NULL
;
11942 /* The .aent and .ent directives. */
11952 symbolP
= get_symbol ();
11953 if (*input_line_pointer
== ',')
11954 input_line_pointer
++;
11955 SKIP_WHITESPACE ();
11956 if (isdigit ((unsigned char) *input_line_pointer
)
11957 || *input_line_pointer
== '-')
11958 number
= get_number ();
11960 #ifdef BFD_ASSEMBLER
11961 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11966 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11973 as_warn (_(".ent or .aent not in text section."));
11975 if (!aent
&& cur_proc_ptr
)
11976 as_warn (_("missing .end"));
11980 cur_proc_ptr
= &cur_proc
;
11981 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11983 cur_proc_ptr
->isym
= symbolP
;
11985 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11990 demand_empty_rest_of_line ();
11993 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11994 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11995 s_mips_frame is used so that we can set the PDR information correctly.
11996 We can't use the ecoff routines because they make reference to the ecoff
11997 symbol table (in the mdebug section). */
12000 s_mips_frame (ignore
)
12001 int ignore ATTRIBUTE_UNUSED
;
12003 #ifdef MIPS_STABS_ELF
12007 if (cur_proc_ptr
== (procS
*) NULL
)
12009 as_warn (_(".frame outside of .ent"));
12010 demand_empty_rest_of_line ();
12014 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12016 SKIP_WHITESPACE ();
12017 if (*input_line_pointer
++ != ','
12018 || get_absolute_expression_and_terminator (&val
) != ',')
12020 as_warn (_("Bad .frame directive"));
12021 --input_line_pointer
;
12022 demand_empty_rest_of_line ();
12026 cur_proc_ptr
->frame_offset
= val
;
12027 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12029 demand_empty_rest_of_line ();
12032 #endif /* MIPS_STABS_ELF */
12035 /* The .fmask and .mask directives. If the mdebug section is present
12036 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12037 embedded targets, s_mips_mask is used so that we can set the PDR
12038 information correctly. We can't use the ecoff routines because they
12039 make reference to the ecoff symbol table (in the mdebug section). */
12042 s_mips_mask (reg_type
)
12045 #ifdef MIPS_STABS_ELF
12048 if (cur_proc_ptr
== (procS
*) NULL
)
12050 as_warn (_(".mask/.fmask outside of .ent"));
12051 demand_empty_rest_of_line ();
12055 if (get_absolute_expression_and_terminator (&mask
) != ',')
12057 as_warn (_("Bad .mask/.fmask directive"));
12058 --input_line_pointer
;
12059 demand_empty_rest_of_line ();
12063 off
= get_absolute_expression ();
12065 if (reg_type
== 'F')
12067 cur_proc_ptr
->fpreg_mask
= mask
;
12068 cur_proc_ptr
->fpreg_offset
= off
;
12072 cur_proc_ptr
->reg_mask
= mask
;
12073 cur_proc_ptr
->reg_offset
= off
;
12076 demand_empty_rest_of_line ();
12078 s_ignore (reg_type
);
12079 #endif /* MIPS_STABS_ELF */
12082 /* The .loc directive. */
12093 assert (now_seg
== text_section
);
12095 lineno
= get_number ();
12096 addroff
= frag_now_fix ();
12098 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12099 S_SET_TYPE (symbolP
, N_SLINE
);
12100 S_SET_OTHER (symbolP
, 0);
12101 S_SET_DESC (symbolP
, lineno
);
12102 symbolP
->sy_segment
= now_seg
;
12106 /* CPU name/ISA/number mapping table.
12108 Entries are grouped by type. The first matching CPU or ISA entry
12109 gets chosen by CPU or ISA, so it should be the 'canonical' name
12110 for that type. Entries after that within the type are sorted
12113 Case is ignored in comparison, so put the canonical entry in the
12114 appropriate case but everything else in lower case to ease eye pain. */
12115 static const struct mips_cpu_info mips_cpu_info_table
[] =
12118 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12119 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12122 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12125 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12128 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12131 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12132 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12135 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12136 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12137 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12138 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12139 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12140 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12142 /* For historical reasons. */
12143 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12146 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12147 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12148 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12149 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12152 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12153 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12154 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12155 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12158 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12159 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12160 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12161 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12164 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12165 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12166 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12169 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12170 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12171 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12172 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12175 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12176 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12179 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12180 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12183 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12184 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12185 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12186 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12189 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12190 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12193 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12194 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12195 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12196 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12199 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12200 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12201 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12202 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12205 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12206 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12207 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12208 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12211 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12212 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12213 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12214 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12217 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12218 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12219 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12220 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12223 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12224 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12225 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12226 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12229 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12230 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12231 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12232 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12235 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12236 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12237 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12238 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12239 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12240 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12241 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
12242 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12243 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
12244 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12245 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
12246 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12247 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
12248 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12249 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
12250 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12251 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12253 /* SiByte SB-1 CPU */
12254 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12255 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12256 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12257 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12260 { NULL
, 0, 0, 0, },
12263 static const struct mips_cpu_info
*
12264 mips_cpu_info_from_name (name
)
12269 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12270 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12271 return (&mips_cpu_info_table
[i
]);
12276 static const struct mips_cpu_info
*
12277 mips_cpu_info_from_isa (isa
)
12282 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12283 if (mips_cpu_info_table
[i
].is_isa
12284 && isa
== mips_cpu_info_table
[i
].isa
)
12285 return (&mips_cpu_info_table
[i
]);
12290 static const struct mips_cpu_info
*
12291 mips_cpu_info_from_cpu (cpu
)
12296 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12297 if (!mips_cpu_info_table
[i
].is_isa
12298 && cpu
== mips_cpu_info_table
[i
].cpu
)
12299 return (&mips_cpu_info_table
[i
]);