1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 FIXME: The CPU specific variables (mips_4010, et. al.) should
146 probably be in here as well, and there should probably be some way
149 struct mips_set_options
151 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
152 if it has not been initialized. Changed by `.set mipsN', and the
153 -mipsN command line option, and the default CPU. */
155 /* Whether we are assembling for the mips16 processor. 0 if we are
156 not, 1 if we are, and -1 if the value has not been initialized.
157 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
158 -nomips16 command line options, and the default CPU. */
160 /* Non-zero if we should not reorder instructions. Changed by `.set
161 reorder' and `.set noreorder'. */
163 /* Non-zero if we should not permit the $at ($1) register to be used
164 in instructions. Changed by `.set at' and `.set noat'. */
166 /* Non-zero if we should warn when a macro instruction expands into
167 more than one machine instruction. Changed by `.set nomacro' and
169 int warn_about_macros
;
170 /* Non-zero if we should not move instructions. Changed by `.set
171 move', `.set volatile', `.set nomove', and `.set novolatile'. */
173 /* Non-zero if we should not optimize branches by moving the target
174 of the branch into the delay slot. Actually, we don't perform
175 this optimization anyhow. Changed by `.set bopt' and `.set
178 /* Non-zero if we should not autoextend mips16 instructions.
179 Changed by `.set autoextend' and `.set noautoextend'. */
183 /* This is the struct we use to hold the current set of options. Note
184 that we must set the isa and mips16 fields to -1 to indicate that
185 they have not been initialized. */
187 static struct mips_set_options mips_opts
= { -1, -1 };
189 /* These variables are filled in with the masks of registers used.
190 The object format code reads them and puts them in the appropriate
192 unsigned long mips_gprmask
;
193 unsigned long mips_cprmask
[4];
195 /* MIPS ISA we are using for this output file. */
196 static int file_mips_isa
;
198 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
199 static int mips_cpu
= -1;
201 /* Whether the 4650 instructions (mad/madu) are permitted. */
202 static int mips_4650
= -1;
204 /* Whether the 4010 instructions are permitted. */
205 static int mips_4010
= -1;
207 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
208 static int mips_4100
= -1;
210 /* start-sanitize-vr4320 */
211 /* Whether NEC vr4320 instructions are permitted. */
212 static int mips_4320
= -1;
214 /* end-sanitize-vr4320 */
215 /* start-sanitize-cygnus */
216 /* Whether NEC vr5400 instructions are permitted. */
217 static int mips_5400
= -1;
219 /* end-sanitize-cygnus */
220 /* start-sanitize-r5900 */
221 /* Whether Toshiba r5900 instructions are permitted. */
222 static int mips_5900
= -1;
224 /* end-sanitize-r5900 */
225 /* Whether Toshiba r3900 instructions are permitted. */
226 static int mips_3900
= -1;
228 /* start-sanitize-tx49 */
229 /* Whether Toshiba r4900 instructions are permitted. */
230 static int mips_4900
= -1;
232 /* end-sanitize-tx49 */
233 /* start-sanitize-tx19 */
234 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
235 The tx19 related options and configuration bits are handled by
237 /* end-sanitize-tx19 */
239 /* Whether the processor uses hardware interlocks to protect
240 reads from the HI and LO registers, and thus does not
241 require nops to be inserted.
243 FIXME: We really should not be checking mips_cpu here. The -mcpu=
244 option is documented to not do anything special. In gcc, the
245 -mcpu= option only affects scheduling, and does not affect code
246 generation. Each test of -mcpu= here should actually be testing a
247 specific variable, such as mips_4010, and each such variable should
248 have a command line option to set it. The -mcpu= option may be
249 used to set the default value of these options, as is the case for
252 #define hilo_interlocks (mips_4010 || mips_3900 \
253 /* start-sanitize-tx49 */ \
254 || mips_cpu == 4900 || mips_4900 \
255 /* end-sanitize-tx49 */ \
256 /* start-sanitize-vr4320 */ \
257 || mips_cpu == 4320 \
258 /* end-sanitize-vr4320 */ \
259 /* start-sanitize-r5900 */ \
261 /* end-sanitize-r5900 */ \
264 /* Whether the processor uses hardware interlocks to protect reads
265 from the GPRs, and thus does not require nops to be inserted. */
266 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
267 /* start-sanitize-cygnus */
268 #undef gpr_interlocks
269 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
270 /* end-sanitize-cygnus */
273 /* As with other "interlocks" this is used by hardware that has FP
274 (co-processor) interlocks. */
275 /* Itbl support may require additional care here. */
276 #define cop_interlocks (mips_cpu == 4300 \
277 /* start-sanitize-vr4320 */ \
278 || mips_cpu == 4320 \
279 /* end-sanitize-vr4320 */ \
280 /* start-sanitize-cygnus */ \
281 || mips_cpu == 5400 \
282 /* end-sanitize-cygnus */ \
285 /* MIPS PIC level. */
289 /* Do not generate PIC code. */
292 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
293 not sure what it is supposed to do. */
296 /* Generate PIC code as in the SVR4 MIPS ABI. */
299 /* Generate PIC code without using a global offset table: the data
300 segment has a maximum size of 64K, all data references are off
301 the $gp register, and all text references are PC relative. This
302 is used on some embedded systems. */
306 static enum mips_pic_level mips_pic
;
308 /* 1 if we should generate 32 bit offsets from the GP register in
309 SVR4_PIC mode. Currently has no meaning in other modes. */
310 static int mips_big_got
;
312 /* 1 if trap instructions should used for overflow rather than break
314 static int mips_trap
;
316 /* Non-zero if any .set noreorder directives were used. */
318 static int mips_any_noreorder
;
320 /* The size of the small data section. */
321 static int g_switch_value
= 8;
322 /* Whether the -G option was used. */
323 static int g_switch_seen
= 0;
328 /* If we can determine in advance that GP optimization won't be
329 possible, we can skip the relaxation stuff that tries to produce
330 GP-relative references. This makes delay slot optimization work
333 This function can only provide a guess, but it seems to work for
334 gcc output. If it guesses wrong, the only loss should be in
335 efficiency; it shouldn't introduce any bugs.
337 I don't know if a fix is needed for the SVR4_PIC mode. I've only
338 fixed it for the non-PIC mode. KR 95/04/07 */
339 static int nopic_need_relax
PARAMS ((symbolS
*, int));
341 /* handle of the OPCODE hash table */
342 static struct hash_control
*op_hash
= NULL
;
344 /* The opcode hash table we use for the mips16. */
345 static struct hash_control
*mips16_op_hash
= NULL
;
347 /* This array holds the chars that always start a comment. If the
348 pre-processor is disabled, these aren't very useful */
349 const char comment_chars
[] = "#";
351 /* This array holds the chars that only start a comment at the beginning of
352 a line. If the line seems to have the form '# 123 filename'
353 .line and .file directives will appear in the pre-processed output */
354 /* Note that input_file.c hand checks for '#' at the beginning of the
355 first line of the input file. This is because the compiler outputs
356 #NO_APP at the beginning of its output. */
357 /* Also note that C style comments are always supported. */
358 const char line_comment_chars
[] = "#";
360 /* This array holds machine specific line separator characters. */
361 const char line_separator_chars
[] = "";
363 /* Chars that can be used to separate mant from exp in floating point nums */
364 const char EXP_CHARS
[] = "eE";
366 /* Chars that mean this number is a floating point constant */
369 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
371 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
372 changed in read.c . Ideally it shouldn't have to know about it at all,
373 but nothing is ideal around here.
376 static char *insn_error
;
378 static int auto_align
= 1;
380 /* When outputting SVR4 PIC code, the assembler needs to know the
381 offset in the stack frame from which to restore the $gp register.
382 This is set by the .cprestore pseudo-op, and saved in this
384 static offsetT mips_cprestore_offset
= -1;
386 /* This is the register which holds the stack frame, as set by the
387 .frame pseudo-op. This is needed to implement .cprestore. */
388 static int mips_frame_reg
= SP
;
390 /* To output NOP instructions correctly, we need to keep information
391 about the previous two instructions. */
393 /* Whether we are optimizing. The default value of 2 means to remove
394 unneeded NOPs and swap branch instructions when possible. A value
395 of 1 means to not swap branches. A value of 0 means to always
397 static int mips_optimize
= 2;
399 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
400 equivalent to seeing no -g option at all. */
401 static int mips_debug
= 0;
403 /* The previous instruction. */
404 static struct mips_cl_insn prev_insn
;
406 /* The instruction before prev_insn. */
407 static struct mips_cl_insn prev_prev_insn
;
409 /* If we don't want information for prev_insn or prev_prev_insn, we
410 point the insn_mo field at this dummy integer. */
411 static const struct mips_opcode dummy_opcode
= { 0 };
413 /* Non-zero if prev_insn is valid. */
414 static int prev_insn_valid
;
416 /* The frag for the previous instruction. */
417 static struct frag
*prev_insn_frag
;
419 /* The offset into prev_insn_frag for the previous instruction. */
420 static long prev_insn_where
;
422 /* The reloc type for the previous instruction, if any. */
423 static bfd_reloc_code_real_type prev_insn_reloc_type
;
425 /* The reloc for the previous instruction, if any. */
426 static fixS
*prev_insn_fixp
;
428 /* Non-zero if the previous instruction was in a delay slot. */
429 static int prev_insn_is_delay_slot
;
431 /* Non-zero if the previous instruction was in a .set noreorder. */
432 static int prev_insn_unreordered
;
434 /* Non-zero if the previous instruction uses an extend opcode (if
436 static int prev_insn_extended
;
438 /* Non-zero if the previous previous instruction was in a .set
440 static int prev_prev_insn_unreordered
;
442 /* start-sanitize-branchbug4011 */
443 /* Non-zero if the previous insn had one or more labels */
444 static int prev_insn_labels
;
446 /* end-sanitize-branchbug4011 */
447 /* If this is set, it points to a frag holding nop instructions which
448 were inserted before the start of a noreorder section. If those
449 nops turn out to be unnecessary, the size of the frag can be
451 static fragS
*prev_nop_frag
;
453 /* The number of nop instructions we created in prev_nop_frag. */
454 static int prev_nop_frag_holds
;
456 /* The number of nop instructions that we know we need in
458 static int prev_nop_frag_required
;
460 /* The number of instructions we've seen since prev_nop_frag. */
461 static int prev_nop_frag_since
;
463 /* For ECOFF and ELF, relocations against symbols are done in two
464 parts, with a HI relocation and a LO relocation. Each relocation
465 has only 16 bits of space to store an addend. This means that in
466 order for the linker to handle carries correctly, it must be able
467 to locate both the HI and the LO relocation. This means that the
468 relocations must appear in order in the relocation table.
470 In order to implement this, we keep track of each unmatched HI
471 relocation. We then sort them so that they immediately precede the
472 corresponding LO relocation. */
477 struct mips_hi_fixup
*next
;
480 /* The section this fixup is in. */
484 /* The list of unmatched HI relocs. */
486 static struct mips_hi_fixup
*mips_hi_fixup_list
;
488 /* Map normal MIPS register numbers to mips16 register numbers. */
490 #define X ILLEGAL_REG
491 static const int mips32_to_16_reg_map
[] =
493 X
, X
, 2, 3, 4, 5, 6, 7,
494 X
, X
, X
, X
, X
, X
, X
, X
,
495 0, 1, X
, X
, X
, X
, X
, X
,
496 X
, X
, X
, X
, X
, X
, X
, X
500 /* Map mips16 register numbers to normal MIPS register numbers. */
502 static const int mips16_to_32_reg_map
[] =
504 16, 17, 2, 3, 4, 5, 6, 7
507 /* Since the MIPS does not have multiple forms of PC relative
508 instructions, we do not have to do relaxing as is done on other
509 platforms. However, we do have to handle GP relative addressing
510 correctly, which turns out to be a similar problem.
512 Every macro that refers to a symbol can occur in (at least) two
513 forms, one with GP relative addressing and one without. For
514 example, loading a global variable into a register generally uses
515 a macro instruction like this:
517 If i can be addressed off the GP register (this is true if it is in
518 the .sbss or .sdata section, or if it is known to be smaller than
519 the -G argument) this will generate the following instruction:
521 This instruction will use a GPREL reloc. If i can not be addressed
522 off the GP register, the following instruction sequence will be used:
525 In this case the first instruction will have a HI16 reloc, and the
526 second reloc will have a LO16 reloc. Both relocs will be against
529 The issue here is that we may not know whether i is GP addressable
530 until after we see the instruction that uses it. Therefore, we
531 want to be able to choose the final instruction sequence only at
532 the end of the assembly. This is similar to the way other
533 platforms choose the size of a PC relative instruction only at the
536 When generating position independent code we do not use GP
537 addressing in quite the same way, but the issue still arises as
538 external symbols and local symbols must be handled differently.
540 We handle these issues by actually generating both possible
541 instruction sequences. The longer one is put in a frag_var with
542 type rs_machine_dependent. We encode what to do with the frag in
543 the subtype field. We encode (1) the number of existing bytes to
544 replace, (2) the number of new bytes to use, (3) the offset from
545 the start of the existing bytes to the first reloc we must generate
546 (that is, the offset is applied from the start of the existing
547 bytes after they are replaced by the new bytes, if any), (4) the
548 offset from the start of the existing bytes to the second reloc,
549 (5) whether a third reloc is needed (the third reloc is always four
550 bytes after the second reloc), and (6) whether to warn if this
551 variant is used (this is sometimes needed if .set nomacro or .set
552 noat is in effect). All these numbers are reasonably small.
554 Generating two instruction sequences must be handled carefully to
555 ensure that delay slots are handled correctly. Fortunately, there
556 are a limited number of cases. When the second instruction
557 sequence is generated, append_insn is directed to maintain the
558 existing delay slot information, so it continues to apply to any
559 code after the second instruction sequence. This means that the
560 second instruction sequence must not impose any requirements not
561 required by the first instruction sequence.
563 These variant frags are then handled in functions called by the
564 machine independent code. md_estimate_size_before_relax returns
565 the final size of the frag. md_convert_frag sets up the final form
566 of the frag. tc_gen_reloc adjust the first reloc and adds a second
568 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
572 | (((reloc1) + 64) << 9) \
573 | (((reloc2) + 64) << 2) \
574 | ((reloc3) ? (1 << 1) : 0) \
576 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
577 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
578 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
579 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
580 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
581 #define RELAX_WARN(i) ((i) & 1)
583 /* For mips16 code, we use an entirely different form of relaxation.
584 mips16 supports two versions of most instructions which take
585 immediate values: a small one which takes some small value, and a
586 larger one which takes a 16 bit value. Since branches also follow
587 this pattern, relaxing these values is required.
589 We can assemble both mips16 and normal MIPS code in a single
590 object. Therefore, we need to support this type of relaxation at
591 the same time that we support the relaxation described above. We
592 use the high bit of the subtype field to distinguish these cases.
594 The information we store for this type of relaxation is the
595 argument code found in the opcode file for this relocation, whether
596 the user explicitly requested a small or extended form, and whether
597 the relocation is in a jump or jal delay slot. That tells us the
598 size of the value, and how it should be stored. We also store
599 whether the fragment is considered to be extended or not. We also
600 store whether this is known to be a branch to a different section,
601 whether we have tried to relax this frag yet, and whether we have
602 ever extended a PC relative fragment because of a shift count. */
603 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
606 | ((small) ? 0x100 : 0) \
607 | ((ext) ? 0x200 : 0) \
608 | ((dslot) ? 0x400 : 0) \
609 | ((jal_dslot) ? 0x800 : 0))
610 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
611 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
612 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
613 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
614 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
615 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
616 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
617 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
618 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
619 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
620 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
621 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
622 /* start-sanitize-branchbug4011 */
623 /* The 4011 core has a bug in it's branch processing that
624 an be avoided if branches never branches (where branches
625 are defined as those starting with 'b'). We do this here
626 by insuring that labels are not directly on branch instructions,
627 and if they are inserting a no-op between the label and the
629 static int mips_fix_4011_branch_bug
= 0;
630 /* end-sanitize-branchbug4011 */
632 /* Prototypes for static functions. */
635 #define internalError() \
636 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
638 #define internalError() as_fatal (_("MIPS internal Error"));
641 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
643 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
644 unsigned int reg
, enum mips_regclass
class));
645 static int reg_needs_delay
PARAMS ((int));
646 static void mips16_mark_labels
PARAMS ((void));
647 static void append_insn
PARAMS ((char *place
,
648 struct mips_cl_insn
* ip
,
650 bfd_reloc_code_real_type r
,
652 static void mips_no_prev_insn
PARAMS ((int));
653 static void mips_emit_delays
PARAMS ((boolean
));
655 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
656 const char *name
, const char *fmt
,
659 static void macro_build ();
661 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
662 const char *, const char *,
664 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
665 expressionS
* ep
, int regnum
));
666 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
667 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
669 static void load_register
PARAMS ((int *, int, expressionS
*, int));
670 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
671 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
672 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
673 #ifdef LOSING_COMPILER
674 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
676 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
677 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
678 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
679 boolean
, boolean
, unsigned long *,
680 boolean
*, unsigned short *));
681 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
682 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
683 static symbolS
*get_symbol
PARAMS ((void));
684 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
685 static void s_align
PARAMS ((int));
686 static void s_change_sec
PARAMS ((int));
687 static void s_cons
PARAMS ((int));
688 static void s_float_cons
PARAMS ((int));
689 static void s_mips_globl
PARAMS ((int));
690 static void s_option
PARAMS ((int));
691 static void s_mipsset
PARAMS ((int));
692 static void s_abicalls
PARAMS ((int));
693 static void s_cpload
PARAMS ((int));
694 static void s_cprestore
PARAMS ((int));
695 static void s_gpword
PARAMS ((int));
696 static void s_cpadd
PARAMS ((int));
697 static void s_insn
PARAMS ((int));
698 static void md_obj_begin
PARAMS ((void));
699 static void md_obj_end
PARAMS ((void));
700 static long get_number
PARAMS ((void));
701 static void s_ent
PARAMS ((int));
702 static void s_mipsend
PARAMS ((int));
703 static void s_file
PARAMS ((int));
704 static void s_mips_stab
PARAMS ((int));
705 static void s_mips_weakext
PARAMS ((int));
706 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
709 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
713 The following pseudo-ops from the Kane and Heinrich MIPS book
714 should be defined here, but are currently unsupported: .alias,
715 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
717 The following pseudo-ops from the Kane and Heinrich MIPS book are
718 specific to the type of debugging information being generated, and
719 should be defined by the object format: .aent, .begin, .bend,
720 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
723 The following pseudo-ops from the Kane and Heinrich MIPS book are
724 not MIPS CPU specific, but are also not specific to the object file
725 format. This file is probably the best place to define them, but
726 they are not currently supported: .asm0, .endr, .lab, .repeat,
729 static const pseudo_typeS mips_pseudo_table
[] =
731 /* MIPS specific pseudo-ops. */
732 {"option", s_option
, 0},
733 {"set", s_mipsset
, 0},
734 {"rdata", s_change_sec
, 'r'},
735 {"sdata", s_change_sec
, 's'},
736 {"livereg", s_ignore
, 0},
737 {"abicalls", s_abicalls
, 0},
738 {"cpload", s_cpload
, 0},
739 {"cprestore", s_cprestore
, 0},
740 {"gpword", s_gpword
, 0},
741 {"cpadd", s_cpadd
, 0},
744 /* Relatively generic pseudo-ops that happen to be used on MIPS
746 {"asciiz", stringer
, 1},
747 {"bss", s_change_sec
, 'b'},
750 {"dword", s_cons
, 3},
751 {"weakext", s_mips_weakext
, 0},
753 /* These pseudo-ops are defined in read.c, but must be overridden
754 here for one reason or another. */
755 {"align", s_align
, 0},
757 {"data", s_change_sec
, 'd'},
758 {"double", s_float_cons
, 'd'},
759 {"float", s_float_cons
, 'f'},
760 {"globl", s_mips_globl
, 0},
761 {"global", s_mips_globl
, 0},
762 {"hword", s_cons
, 1},
767 {"short", s_cons
, 1},
768 {"single", s_float_cons
, 'f'},
769 {"stabn", s_mips_stab
, 'n'},
770 {"text", s_change_sec
, 't'},
775 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
776 /* These pseudo-ops should be defined by the object file format.
777 However, a.out doesn't support them, so we have versions here. */
779 {"bgnb", s_ignore
, 0},
780 {"end", s_mipsend
, 0},
781 {"endb", s_ignore
, 0},
784 {"fmask", s_ignore
, 'F'},
785 {"frame", s_ignore
, 0},
786 {"loc", s_ignore
, 0},
787 {"mask", s_ignore
, 'R'},
788 {"verstamp", s_ignore
, 0},
792 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
797 pop_insert (mips_pseudo_table
);
798 if (! ECOFF_DEBUGGING
)
799 pop_insert (mips_nonecoff_pseudo_table
);
802 /* Symbols labelling the current insn. */
804 struct insn_label_list
806 struct insn_label_list
*next
;
810 static struct insn_label_list
*insn_labels
;
811 static struct insn_label_list
*free_insn_labels
;
813 static void mips_clear_insn_labels
PARAMS ((void));
816 mips_clear_insn_labels ()
818 register struct insn_label_list
**pl
;
820 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
826 static char *expr_end
;
828 /* Expressions which appear in instructions. These are set by
831 static expressionS imm_expr
;
832 static expressionS offset_expr
;
834 /* Relocs associated with imm_expr and offset_expr. */
836 static bfd_reloc_code_real_type imm_reloc
;
837 static bfd_reloc_code_real_type offset_reloc
;
839 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
841 static boolean imm_unmatched_hi
;
843 /* These are set by mips16_ip if an explicit extension is used. */
845 static boolean mips16_small
, mips16_ext
;
848 * This function is called once, at assembler startup time. It should
849 * set up all the tables, etc. that the MD part of the assembler will need.
855 register const char *retval
= NULL
;
856 register unsigned int i
= 0;
862 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
864 a
= xmalloc (sizeof TARGET_CPU
);
865 strcpy (a
, TARGET_CPU
);
866 a
[(sizeof TARGET_CPU
) - 3] = '\0';
872 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
873 just the generic 'mips', in which case set mips_cpu based
874 on the given ISA, if any. */
876 if (strcmp (cpu
, "mips") == 0)
878 if (mips_opts
.isa
< 0)
881 else if (mips_opts
.isa
== 2)
884 else if (mips_opts
.isa
== 3)
887 else if (mips_opts
.isa
== 4)
894 else if (strcmp (cpu
, "r3900") == 0
895 || strcmp (cpu
, "mipstx39") == 0
896 /* start-sanitize-tx19 */
897 || strcmp (cpu
, "r1900") == 0
898 || strcmp (cpu
, "mipstx19") == 0
899 /* end-sanitize-tx19 */
903 else if (strcmp (cpu
, "r6000") == 0
904 || strcmp (cpu
, "mips2") == 0)
907 else if (strcmp (cpu
, "mips64") == 0
908 || strcmp (cpu
, "r4000") == 0
909 || strcmp (cpu
, "mips3") == 0)
912 else if (strcmp (cpu
, "r4400") == 0)
915 else if (strcmp (cpu
, "mips64orion") == 0
916 || strcmp (cpu
, "r4600") == 0)
919 else if (strcmp (cpu
, "r4650") == 0)
922 else if (strcmp (cpu
, "mips64vr4300") == 0)
925 /* start-sanitize-vr4320 */
926 else if (strcmp (cpu
, "r4320") == 0
927 || strcmp (cpu
, "mips64vr4320") == 0)
930 /* end-sanitize-vr4320 */
931 else if (strcmp (cpu
, "mips64vr4100") == 0)
934 else if (strcmp (cpu
, "r4010") == 0)
937 /* start-sanitize-tx49 */
938 else if (strcmp (cpu
, "mips64tx49") == 0)
940 /* end-sanitize-tx49 */
942 else if (strcmp (cpu
, "r5000") == 0
943 || strcmp (cpu
, "mips64vr5000") == 0)
946 /* start-sanitize-cygnus */
947 else if (strcmp (cpu
, "r5400") == 0
948 || strcmp (cpu
, "mips64vr5400") == 0)
950 /* end-sanitize-cygnus */
952 /* start-sanitize-r5900 */
953 else if (strcmp (cpu
, "r5900") == 0
954 || strcmp (cpu
, "mips64r5900") == 0)
956 /* end-sanitize-r5900 */
958 else if (strcmp (cpu
, "r8000") == 0
959 || strcmp (cpu
, "mips4") == 0)
962 else if (strcmp (cpu
, "r10000") == 0)
965 else if (strcmp (cpu
, "mips16") == 0)
966 mips_cpu
= 0; /* FIXME */
972 if (mips_opts
.isa
== -1)
978 else if (mips_cpu
== 6000
982 else if (mips_cpu
== 4000
986 /* start-sanitize-vr4320 */
988 /* end-sanitize-vr4320 */
990 /* start-sanitize-tx49 */
992 /* end-sanitize-tx49 */
993 /* start-sanitize-r5900 */
995 /* end-sanitize-r5900 */
999 else if (mips_cpu
== 5000
1000 /* start-sanitize-cygnus */
1002 /* end-sanitize-cygnus */
1004 || mips_cpu
== 10000)
1011 if (mips_opts
.mips16
< 0)
1013 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1014 mips_opts
.mips16
= 1;
1016 mips_opts
.mips16
= 0;
1020 mips_4650
= (mips_cpu
== 4650);
1023 mips_4010
= (mips_cpu
== 4010);
1026 mips_4100
= (mips_cpu
== 4100);
1028 /* start-sanitize-vr4320 */
1030 mips_4320
= (mips_cpu
== 4320);
1032 /* end-sanitize-vr4320 */
1033 /* start-sanitize-cygnus */
1035 mips_5400
= (mips_cpu
== 5400);
1036 /* end-sanitize-cygnus */
1038 /* start-sanitize-r5900 */
1040 mips_5900
= (mips_cpu
== 5900);
1041 /* end-sanitize-r5900 */
1044 mips_3900
= (mips_cpu
== 3900);
1046 /* start-sanitize-tx49 */
1048 mips_4900
= (mips_cpu
== 4900);
1050 /* end-sanitize-tx49 */
1052 /* End of TARGET_CPU processing, get rid of malloced memory
1061 if (mips_opts
.isa
< 2 && mips_trap
)
1062 as_bad (_("trap exception not supported at ISA 1"));
1064 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1066 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1070 switch (mips_opts
.isa
)
1073 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1076 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1079 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1082 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1088 as_warn (_("Could not set architecture and machine"));
1090 file_mips_isa
= mips_opts
.isa
;
1092 op_hash
= hash_new ();
1094 for (i
= 0; i
< NUMOPCODES
;)
1096 const char *name
= mips_opcodes
[i
].name
;
1098 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1101 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1102 mips_opcodes
[i
].name
, retval
);
1103 /* Probably a memory allocation problem? Give up now. */
1104 as_fatal (_("Broken assembler. No assembly attempted."));
1108 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1110 if (!validate_mips_insn (&mips_opcodes
[i
]))
1115 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1118 mips16_op_hash
= hash_new ();
1121 while (i
< bfd_mips16_num_opcodes
)
1123 const char *name
= mips16_opcodes
[i
].name
;
1125 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1127 as_fatal (_("internal: can't hash `%s': %s"),
1128 mips16_opcodes
[i
].name
, retval
);
1131 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1132 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1133 != mips16_opcodes
[i
].match
))
1135 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1136 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1141 while (i
< bfd_mips16_num_opcodes
1142 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1146 as_fatal (_("Broken assembler. No assembly attempted."));
1148 /* We add all the general register names to the symbol table. This
1149 helps us detect invalid uses of them. */
1150 for (i
= 0; i
< 32; i
++)
1154 sprintf (buf
, "$%d", i
);
1155 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1156 &zero_address_frag
));
1158 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1159 &zero_address_frag
));
1160 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1161 &zero_address_frag
));
1162 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1163 &zero_address_frag
));
1164 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1165 &zero_address_frag
));
1166 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1167 &zero_address_frag
));
1168 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1169 &zero_address_frag
));
1170 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1171 &zero_address_frag
));
1173 mips_no_prev_insn (false);
1176 mips_cprmask
[0] = 0;
1177 mips_cprmask
[1] = 0;
1178 mips_cprmask
[2] = 0;
1179 mips_cprmask
[3] = 0;
1181 /* set the default alignment for the text section (2**2) */
1182 record_alignment (text_section
, 2);
1184 if (USE_GLOBAL_POINTER_OPT
)
1185 bfd_set_gp_size (stdoutput
, g_switch_value
);
1187 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1189 /* On a native system, sections must be aligned to 16 byte
1190 boundaries. When configured for an embedded ELF target, we
1192 if (strcmp (TARGET_OS
, "elf") != 0)
1194 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1195 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1196 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1199 /* Create a .reginfo section for register masks and a .mdebug
1200 section for debugging information. */
1208 subseg
= now_subseg
;
1210 /* The ABI says this section should be loaded so that the
1211 running program can access it. However, we don't load it
1212 if we are configured for an embedded target */
1213 flags
= SEC_READONLY
| SEC_DATA
;
1214 if (strcmp (TARGET_OS
, "elf") != 0)
1215 flags
|= SEC_ALLOC
| SEC_LOAD
;
1219 sec
= subseg_new (".reginfo", (subsegT
) 0);
1222 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1223 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1226 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1231 /* The 64-bit ABI uses a .MIPS.options section rather than
1232 .reginfo section. */
1233 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1234 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1235 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1238 /* Set up the option header. */
1240 Elf_Internal_Options opthdr
;
1243 opthdr
.kind
= ODK_REGINFO
;
1244 opthdr
.size
= (sizeof (Elf_External_Options
)
1245 + sizeof (Elf64_External_RegInfo
));
1248 f
= frag_more (sizeof (Elf_External_Options
));
1249 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1250 (Elf_External_Options
*) f
);
1252 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1257 if (ECOFF_DEBUGGING
)
1259 sec
= subseg_new (".mdebug", (subsegT
) 0);
1260 (void) bfd_set_section_flags (stdoutput
, sec
,
1261 SEC_HAS_CONTENTS
| SEC_READONLY
);
1262 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1265 subseg_set (seg
, subseg
);
1269 if (! ECOFF_DEBUGGING
)
1276 if (! ECOFF_DEBUGGING
)
1284 struct mips_cl_insn insn
;
1286 imm_expr
.X_op
= O_absent
;
1287 imm_reloc
= BFD_RELOC_UNUSED
;
1288 imm_unmatched_hi
= false;
1289 offset_expr
.X_op
= O_absent
;
1290 offset_reloc
= BFD_RELOC_UNUSED
;
1292 if (mips_opts
.mips16
)
1293 mips16_ip (str
, &insn
);
1296 mips_ip (str
, &insn
);
1297 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1298 str
, insn
.insn_opcode
));
1303 as_bad ("%s `%s'", insn_error
, str
);
1307 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1309 if (mips_opts
.mips16
)
1310 mips16_macro (&insn
);
1316 if (imm_expr
.X_op
!= O_absent
)
1317 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1319 else if (offset_expr
.X_op
!= O_absent
)
1320 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1322 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1326 /* See whether instruction IP reads register REG. CLASS is the type
1330 insn_uses_reg (ip
, reg
, class)
1331 struct mips_cl_insn
*ip
;
1333 enum mips_regclass
class;
1335 if (class == MIPS16_REG
)
1337 assert (mips_opts
.mips16
);
1338 reg
= mips16_to_32_reg_map
[reg
];
1339 class = MIPS_GR_REG
;
1342 /* Don't report on general register 0, since it never changes. */
1343 if (class == MIPS_GR_REG
&& reg
== 0)
1346 if (class == MIPS_FP_REG
)
1348 assert (! mips_opts
.mips16
);
1349 /* If we are called with either $f0 or $f1, we must check $f0.
1350 This is not optimal, because it will introduce an unnecessary
1351 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1352 need to distinguish reading both $f0 and $f1 or just one of
1353 them. Note that we don't have to check the other way,
1354 because there is no instruction that sets both $f0 and $f1
1355 and requires a delay. */
1356 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1357 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1358 == (reg
&~ (unsigned) 1)))
1360 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1361 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1362 == (reg
&~ (unsigned) 1)))
1365 else if (! mips_opts
.mips16
)
1367 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1368 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1370 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1371 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1376 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1377 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1378 & MIPS16OP_MASK_RX
)]
1381 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1382 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1383 & MIPS16OP_MASK_RY
)]
1386 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1387 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1388 & MIPS16OP_MASK_MOVE32Z
)]
1391 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1393 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1395 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1397 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1398 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1399 & MIPS16OP_MASK_REGR32
) == reg
)
1406 /* This function returns true if modifying a register requires a
1410 reg_needs_delay (reg
)
1413 unsigned long prev_pinfo
;
1415 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1416 if (! mips_opts
.noreorder
1417 && mips_opts
.isa
< 4
1418 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1419 || (! gpr_interlocks
1420 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1422 /* A load from a coprocessor or from memory. All load
1423 delays delay the use of general register rt for one
1424 instruction on the r3000. The r6000 and r4000 use
1426 /* Itbl support may require additional care here. */
1427 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1428 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1435 /* Mark instruction labels in mips16 mode. This permits the linker to
1436 handle them specially, such as generating jalx instructions when
1437 needed. We also make them odd for the duration of the assembly, in
1438 order to generate the right sort of code. We will make them even
1439 in the adjust_symtab routine, while leaving them marked. This is
1440 convenient for the debugger and the disassembler. The linker knows
1441 to make them odd again. */
1444 mips16_mark_labels ()
1446 if (mips_opts
.mips16
)
1448 struct insn_label_list
*l
;
1450 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1453 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1454 S_SET_OTHER (l
->label
, STO_MIPS16
);
1456 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1457 ++l
->label
->sy_value
.X_add_number
;
1462 /* Output an instruction. PLACE is where to put the instruction; if
1463 it is NULL, this uses frag_more to get room. IP is the instruction
1464 information. ADDRESS_EXPR is an operand of the instruction to be
1465 used with RELOC_TYPE. */
1468 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1470 struct mips_cl_insn
*ip
;
1471 expressionS
*address_expr
;
1472 bfd_reloc_code_real_type reloc_type
;
1473 boolean unmatched_hi
;
1475 register unsigned long prev_pinfo
, pinfo
;
1479 /* start-sanitize-branchbug4011 */
1480 int label_nop
= 0; /* True if a no-op needs to appear between
1481 the current insn and the current labels */
1482 /* end-sanitize-branchbug4011 */
1484 /* Mark instruction labels in mips16 mode. */
1485 if (mips_opts
.mips16
)
1486 mips16_mark_labels ();
1488 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1489 pinfo
= ip
->insn_mo
->pinfo
;
1491 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1495 /* If the previous insn required any delay slots, see if we need
1496 to insert a NOP or two. There are eight kinds of possible
1497 hazards, of which an instruction can have at most one type.
1498 (1) a load from memory delay
1499 (2) a load from a coprocessor delay
1500 (3) an unconditional branch delay
1501 (4) a conditional branch delay
1502 (5) a move to coprocessor register delay
1503 (6) a load coprocessor register from memory delay
1504 (7) a coprocessor condition code delay
1505 (8) a HI/LO special register delay
1507 There are a lot of optimizations we could do that we don't.
1508 In particular, we do not, in general, reorder instructions.
1509 If you use gcc with optimization, it will reorder
1510 instructions and generally do much more optimization then we
1511 do here; repeating all that work in the assembler would only
1512 benefit hand written assembly code, and does not seem worth
1515 /* This is how a NOP is emitted. */
1516 #define emit_nop() \
1518 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1519 : md_number_to_chars (frag_more (4), 0, 4))
1521 /* The previous insn might require a delay slot, depending upon
1522 the contents of the current insn. */
1523 if (! mips_opts
.mips16
1524 && mips_opts
.isa
< 4
1525 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1526 && ! cop_interlocks
)
1527 || (! gpr_interlocks
1528 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1530 /* A load from a coprocessor or from memory. All load
1531 delays delay the use of general register rt for one
1532 instruction on the r3000. The r6000 and r4000 use
1534 /* Itbl support may require additional care here. */
1535 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1536 if (mips_optimize
== 0
1537 || insn_uses_reg (ip
,
1538 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1543 else if (! mips_opts
.mips16
1544 && mips_opts
.isa
< 4
1545 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1546 && ! cop_interlocks
)
1547 || (mips_opts
.isa
< 2
1548 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1550 /* A generic coprocessor delay. The previous instruction
1551 modified a coprocessor general or control register. If
1552 it modified a control register, we need to avoid any
1553 coprocessor instruction (this is probably not always
1554 required, but it sometimes is). If it modified a general
1555 register, we avoid using that register.
1557 On the r6000 and r4000 loading a coprocessor register
1558 from memory is interlocked, and does not require a delay.
1560 This case is not handled very well. There is no special
1561 knowledge of CP0 handling, and the coprocessors other
1562 than the floating point unit are not distinguished at
1564 /* Itbl support may require additional care here. FIXME!
1565 Need to modify this to include knowledge about
1566 user specified delays! */
1567 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1569 if (mips_optimize
== 0
1570 || insn_uses_reg (ip
,
1571 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1576 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1578 if (mips_optimize
== 0
1579 || insn_uses_reg (ip
,
1580 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1587 /* We don't know exactly what the previous instruction
1588 does. If the current instruction uses a coprocessor
1589 register, we must insert a NOP. If previous
1590 instruction may set the condition codes, and the
1591 current instruction uses them, we must insert two
1593 /* Itbl support may require additional care here. */
1594 if (mips_optimize
== 0
1595 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1596 && (pinfo
& INSN_READ_COND_CODE
)))
1598 else if (pinfo
& INSN_COP
)
1602 else if (! mips_opts
.mips16
1603 && mips_opts
.isa
< 4
1604 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1605 && ! cop_interlocks
)
1607 /* The previous instruction sets the coprocessor condition
1608 codes, but does not require a general coprocessor delay
1609 (this means it is a floating point comparison
1610 instruction). If this instruction uses the condition
1611 codes, we need to insert a single NOP. */
1612 /* Itbl support may require additional care here. */
1613 if (mips_optimize
== 0
1614 || (pinfo
& INSN_READ_COND_CODE
))
1617 else if (prev_pinfo
& INSN_READ_LO
)
1619 /* The previous instruction reads the LO register; if the
1620 current instruction writes to the LO register, we must
1621 insert two NOPS. Some newer processors have interlocks. */
1622 if (! hilo_interlocks
1623 && (mips_optimize
== 0
1624 || (pinfo
& INSN_WRITE_LO
)))
1627 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1629 /* The previous instruction reads the HI register; if the
1630 current instruction writes to the HI register, we must
1631 insert a NOP. Some newer processors have interlocks. */
1632 if (! hilo_interlocks
1633 && (mips_optimize
== 0
1634 || (pinfo
& INSN_WRITE_HI
)))
1638 /* If the previous instruction was in a noreorder section, then
1639 we don't want to insert the nop after all. */
1640 /* Itbl support may require additional care here. */
1641 if (prev_insn_unreordered
)
1644 /* There are two cases which require two intervening
1645 instructions: 1) setting the condition codes using a move to
1646 coprocessor instruction which requires a general coprocessor
1647 delay and then reading the condition codes 2) reading the HI
1648 or LO register and then writing to it (except on processors
1649 which have interlocks). If we are not already emitting a NOP
1650 instruction, we must check for these cases compared to the
1651 instruction previous to the previous instruction. */
1652 if ((! mips_opts
.mips16
1653 && mips_opts
.isa
< 4
1654 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1655 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1656 && (pinfo
& INSN_READ_COND_CODE
)
1657 && ! cop_interlocks
)
1658 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1659 && (pinfo
& INSN_WRITE_LO
)
1660 && ! hilo_interlocks
)
1661 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1662 && (pinfo
& INSN_WRITE_HI
)
1663 && ! hilo_interlocks
))
1668 if (prev_prev_insn_unreordered
)
1671 if (prev_prev_nop
&& nops
== 0)
1674 /* If we are being given a nop instruction, don't bother with
1675 one of the nops we would otherwise output. This will only
1676 happen when a nop instruction is used with mips_optimize set
1679 && ! mips_opts
.noreorder
1680 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1683 /* start-sanitize-branchbug4011 */
1684 /* If we have a label on a branch insn, we need at least one no-op
1685 between the label and the branch. The pinfo flags in this test
1686 must cover all the kinds of branches. */
1687 if (mips_fix_4011_branch_bug
1688 && insn_labels
!= NULL
1689 && (ip
->insn_mo
->pinfo
1690 & (INSN_UNCOND_BRANCH_DELAY
1691 |INSN_COND_BRANCH_DELAY
1692 |INSN_COND_BRANCH_LIKELY
)))
1696 /* Make sure we've got at least one nop. */
1701 /* end-sanitize-branchbug4011 */
1702 /* Now emit the right number of NOP instructions. */
1703 if (nops
> 0 && ! mips_opts
.noreorder
)
1706 unsigned long old_frag_offset
;
1708 struct insn_label_list
*l
;
1710 old_frag
= frag_now
;
1711 old_frag_offset
= frag_now_fix ();
1713 /* start-sanitize-branchbug4011 */
1714 /* Emit the nops that should be before the label. */
1718 /* end-sanitize-branchbug4011 */
1719 for (i
= 0; i
< nops
; i
++)
1724 listing_prev_line ();
1725 /* We may be at the start of a variant frag. In case we
1726 are, make sure there is enough space for the frag
1727 after the frags created by listing_prev_line. The
1728 argument to frag_grow here must be at least as large
1729 as the argument to all other calls to frag_grow in
1730 this file. We don't have to worry about being in the
1731 middle of a variant frag, because the variants insert
1732 all needed nop instructions themselves. */
1736 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1738 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1739 l
->label
->sy_frag
= frag_now
;
1740 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1741 /* mips16 text labels are stored as odd. */
1742 if (mips_opts
.mips16
)
1743 ++l
->label
->sy_value
.X_add_number
;
1746 #ifndef NO_ECOFF_DEBUGGING
1747 if (ECOFF_DEBUGGING
)
1748 ecoff_fix_loc (old_frag
, old_frag_offset
);
1750 /* start-sanitize-branchbug4011 */
1753 /* Emit the nop after the label, and return the
1754 nop count to it's proper value. */
1758 /* end-sanitize-branchbug4011 */
1760 else if (prev_nop_frag
!= NULL
)
1762 /* We have a frag holding nops we may be able to remove. If
1763 we don't need any nops, we can decrease the size of
1764 prev_nop_frag by the size of one instruction. If we do
1765 need some nops, we count them in prev_nops_required. */
1766 if (prev_nop_frag_since
== 0)
1770 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1771 --prev_nop_frag_holds
;
1774 prev_nop_frag_required
+= nops
;
1778 if (prev_prev_nop
== 0)
1780 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1781 --prev_nop_frag_holds
;
1784 ++prev_nop_frag_required
;
1787 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1788 prev_nop_frag
= NULL
;
1790 ++prev_nop_frag_since
;
1792 /* Sanity check: by the time we reach the second instruction
1793 after prev_nop_frag, we should have used up all the nops
1794 one way or another. */
1795 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1799 if (reloc_type
> BFD_RELOC_UNUSED
)
1801 /* We need to set up a variant frag. */
1802 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1803 f
= frag_var (rs_machine_dependent
, 4, 0,
1804 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1805 mips16_small
, mips16_ext
,
1807 & INSN_UNCOND_BRANCH_DELAY
),
1808 (prev_insn_reloc_type
1809 == BFD_RELOC_MIPS16_JMP
)),
1810 make_expr_symbol (address_expr
), (offsetT
) 0,
1813 else if (place
!= NULL
)
1815 else if (mips_opts
.mips16
1817 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1819 /* Make sure there is enough room to swap this instruction with
1820 a following jump instruction. */
1826 if (mips_opts
.mips16
1827 && mips_opts
.noreorder
1828 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1829 as_warn (_("extended instruction in delay slot"));
1835 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1837 if (address_expr
->X_op
== O_constant
)
1842 ip
->insn_opcode
|= address_expr
->X_add_number
;
1845 case BFD_RELOC_LO16
:
1846 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1849 case BFD_RELOC_MIPS_JMP
:
1850 if ((address_expr
->X_add_number
& 3) != 0)
1851 as_bad (_("jump to misaligned address (0x%lx)"),
1852 (unsigned long) address_expr
->X_add_number
);
1853 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1856 case BFD_RELOC_MIPS16_JMP
:
1857 if ((address_expr
->X_add_number
& 3) != 0)
1858 as_bad (_("jump to misaligned address (0x%lx)"),
1859 (unsigned long) address_expr
->X_add_number
);
1861 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1862 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1863 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1866 /* start-sanitize-r5900 */
1867 case BFD_RELOC_MIPS15_S3
:
1868 ip
->insn_opcode
|= ((imm_expr
.X_add_number
& 0x7fff) >> 3) << 6;
1870 /* end-sanitize-r5900 */
1872 case BFD_RELOC_16_PCREL_S2
:
1882 /* Don't generate a reloc if we are writing into a variant
1886 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1888 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1892 struct mips_hi_fixup
*hi_fixup
;
1894 assert (reloc_type
== BFD_RELOC_HI16_S
);
1895 hi_fixup
= ((struct mips_hi_fixup
*)
1896 xmalloc (sizeof (struct mips_hi_fixup
)));
1897 hi_fixup
->fixp
= fixp
;
1898 hi_fixup
->seg
= now_seg
;
1899 hi_fixup
->next
= mips_hi_fixup_list
;
1900 mips_hi_fixup_list
= hi_fixup
;
1906 if (! mips_opts
.mips16
)
1907 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1908 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1910 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1911 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1917 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1920 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1923 /* Update the register mask information. */
1924 if (! mips_opts
.mips16
)
1926 if (pinfo
& INSN_WRITE_GPR_D
)
1927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1928 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1929 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1930 if (pinfo
& INSN_READ_GPR_S
)
1931 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1932 if (pinfo
& INSN_WRITE_GPR_31
)
1933 mips_gprmask
|= 1 << 31;
1934 if (pinfo
& INSN_WRITE_FPR_D
)
1935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1936 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1938 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1939 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1940 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1941 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1942 if (pinfo
& INSN_COP
)
1944 /* We don't keep enough information to sort these cases out.
1945 The itbl support does keep this information however, although
1946 we currently don't support itbl fprmats as part of the cop
1947 instruction. May want to add this support in the future. */
1949 /* Never set the bit for $0, which is always zero. */
1950 mips_gprmask
&=~ 1 << 0;
1954 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1955 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1956 & MIPS16OP_MASK_RX
);
1957 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1958 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1959 & MIPS16OP_MASK_RY
);
1960 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1961 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1962 & MIPS16OP_MASK_RZ
);
1963 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1964 mips_gprmask
|= 1 << TREG
;
1965 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1966 mips_gprmask
|= 1 << SP
;
1967 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1968 mips_gprmask
|= 1 << RA
;
1969 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1970 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1971 if (pinfo
& MIPS16_INSN_READ_Z
)
1972 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1973 & MIPS16OP_MASK_MOVE32Z
);
1974 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1975 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1976 & MIPS16OP_MASK_REGR32
);
1979 if (place
== NULL
&& ! mips_opts
.noreorder
)
1981 /* Filling the branch delay slot is more complex. We try to
1982 switch the branch with the previous instruction, which we can
1983 do if the previous instruction does not set up a condition
1984 that the branch tests and if the branch is not itself the
1985 target of any branch. */
1986 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1987 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1989 if (mips_optimize
< 2
1990 /* If we have seen .set volatile or .set nomove, don't
1992 || mips_opts
.nomove
!= 0
1993 /* If we had to emit any NOP instructions, then we
1994 already know we can not swap. */
1996 /* If we don't even know the previous insn, we can not
1998 || ! prev_insn_valid
1999 /* If the previous insn is already in a branch delay
2000 slot, then we can not swap. */
2001 || prev_insn_is_delay_slot
2002 /* start-sanitize-branchbug4011 */
2003 /* We can't swap the branch back to a previous label */
2004 || (mips_fix_4011_branch_bug
&& prev_insn_labels
)
2005 /* end-sanitize-branchbug4011 */
2006 /* If the previous previous insn was in a .set
2007 noreorder, we can't swap. Actually, the MIPS
2008 assembler will swap in this situation. However, gcc
2009 configured -with-gnu-as will generate code like
2015 in which we can not swap the bne and INSN. If gcc is
2016 not configured -with-gnu-as, it does not output the
2017 .set pseudo-ops. We don't have to check
2018 prev_insn_unreordered, because prev_insn_valid will
2019 be 0 in that case. We don't want to use
2020 prev_prev_insn_valid, because we do want to be able
2021 to swap at the start of a function. */
2022 || prev_prev_insn_unreordered
2023 /* If the branch is itself the target of a branch, we
2024 can not swap. We cheat on this; all we check for is
2025 whether there is a label on this instruction. If
2026 there are any branches to anything other than a
2027 label, users must use .set noreorder. */
2028 || insn_labels
!= NULL
2029 /* If the previous instruction is in a variant frag, we
2030 can not do the swap. This does not apply to the
2031 mips16, which uses variant frags for different
2033 || (! mips_opts
.mips16
2034 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2035 /* If the branch reads the condition codes, we don't
2036 even try to swap, because in the sequence
2041 we can not swap, and I don't feel like handling that
2043 || (! mips_opts
.mips16
2044 && mips_opts
.isa
< 4
2045 && (pinfo
& INSN_READ_COND_CODE
))
2046 /* We can not swap with an instruction that requires a
2047 delay slot, becase the target of the branch might
2048 interfere with that instruction. */
2049 || (! mips_opts
.mips16
2050 && mips_opts
.isa
< 4
2052 /* Itbl support may require additional care here. */
2053 & (INSN_LOAD_COPROC_DELAY
2054 | INSN_COPROC_MOVE_DELAY
2055 | INSN_WRITE_COND_CODE
)))
2056 || (! hilo_interlocks
2060 || (! mips_opts
.mips16
2062 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2063 || (! mips_opts
.mips16
2064 && mips_opts
.isa
< 2
2065 /* Itbl support may require additional care here. */
2066 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2067 /* We can not swap with a branch instruction. */
2069 & (INSN_UNCOND_BRANCH_DELAY
2070 | INSN_COND_BRANCH_DELAY
2071 | INSN_COND_BRANCH_LIKELY
))
2072 /* We do not swap with a trap instruction, since it
2073 complicates trap handlers to have the trap
2074 instruction be in a delay slot. */
2075 || (prev_pinfo
& INSN_TRAP
)
2076 /* If the branch reads a register that the previous
2077 instruction sets, we can not swap. */
2078 || (! mips_opts
.mips16
2079 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2080 && insn_uses_reg (ip
,
2081 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2084 || (! mips_opts
.mips16
2085 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2086 && insn_uses_reg (ip
,
2087 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2090 || (mips_opts
.mips16
2091 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2092 && insn_uses_reg (ip
,
2093 ((prev_insn
.insn_opcode
2095 & MIPS16OP_MASK_RX
),
2097 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2098 && insn_uses_reg (ip
,
2099 ((prev_insn
.insn_opcode
2101 & MIPS16OP_MASK_RY
),
2103 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2104 && insn_uses_reg (ip
,
2105 ((prev_insn
.insn_opcode
2107 & MIPS16OP_MASK_RZ
),
2109 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2110 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2111 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2112 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2113 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2114 && insn_uses_reg (ip
,
2115 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2118 /* If the branch writes a register that the previous
2119 instruction sets, we can not swap (we know that
2120 branches write only to RD or to $31). */
2121 || (! mips_opts
.mips16
2122 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2123 && (((pinfo
& INSN_WRITE_GPR_D
)
2124 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2125 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2126 || ((pinfo
& INSN_WRITE_GPR_31
)
2127 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2130 || (! mips_opts
.mips16
2131 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2132 && (((pinfo
& INSN_WRITE_GPR_D
)
2133 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2134 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2135 || ((pinfo
& INSN_WRITE_GPR_31
)
2136 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2139 || (mips_opts
.mips16
2140 && (pinfo
& MIPS16_INSN_WRITE_31
)
2141 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2142 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2143 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2145 /* If the branch writes a register that the previous
2146 instruction reads, we can not swap (we know that
2147 branches only write to RD or to $31). */
2148 || (! mips_opts
.mips16
2149 && (pinfo
& INSN_WRITE_GPR_D
)
2150 && insn_uses_reg (&prev_insn
,
2151 ((ip
->insn_opcode
>> OP_SH_RD
)
2154 || (! mips_opts
.mips16
2155 && (pinfo
& INSN_WRITE_GPR_31
)
2156 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2157 || (mips_opts
.mips16
2158 && (pinfo
& MIPS16_INSN_WRITE_31
)
2159 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2160 /* If we are generating embedded PIC code, the branch
2161 might be expanded into a sequence which uses $at, so
2162 we can't swap with an instruction which reads it. */
2163 || (mips_pic
== EMBEDDED_PIC
2164 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2165 /* If the previous previous instruction has a load
2166 delay, and sets a register that the branch reads, we
2168 || (! mips_opts
.mips16
2169 && mips_opts
.isa
< 4
2170 /* Itbl support may require additional care here. */
2171 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2172 || (! gpr_interlocks
2173 && (prev_prev_insn
.insn_mo
->pinfo
2174 & INSN_LOAD_MEMORY_DELAY
)))
2175 && insn_uses_reg (ip
,
2176 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2179 /* If one instruction sets a condition code and the
2180 other one uses a condition code, we can not swap. */
2181 || ((pinfo
& INSN_READ_COND_CODE
)
2182 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2183 || ((pinfo
& INSN_WRITE_COND_CODE
)
2184 && (prev_pinfo
& INSN_READ_COND_CODE
))
2185 /* If the previous instruction uses the PC, we can not
2187 || (mips_opts
.mips16
2188 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2189 /* If the previous instruction was extended, we can not
2191 || (mips_opts
.mips16
&& prev_insn_extended
)
2192 /* If the previous instruction had a fixup in mips16
2193 mode, we can not swap. This normally means that the
2194 previous instruction was a 4 byte branch anyhow. */
2195 || (mips_opts
.mips16
&& prev_insn_fixp
))
2197 /* We could do even better for unconditional branches to
2198 portions of this object file; we could pick up the
2199 instruction at the destination, put it in the delay
2200 slot, and bump the destination address. */
2202 /* Update the previous insn information. */
2203 prev_prev_insn
= *ip
;
2204 prev_insn
.insn_mo
= &dummy_opcode
;
2208 /* It looks like we can actually do the swap. */
2209 if (! mips_opts
.mips16
)
2214 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2215 memcpy (temp
, prev_f
, 4);
2216 memcpy (prev_f
, f
, 4);
2217 memcpy (f
, temp
, 4);
2220 prev_insn_fixp
->fx_frag
= frag_now
;
2221 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2225 fixp
->fx_frag
= prev_insn_frag
;
2226 fixp
->fx_where
= prev_insn_where
;
2234 assert (prev_insn_fixp
== NULL
);
2235 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2236 memcpy (temp
, prev_f
, 2);
2237 memcpy (prev_f
, f
, 2);
2238 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2240 assert (reloc_type
== BFD_RELOC_UNUSED
);
2241 memcpy (f
, temp
, 2);
2245 memcpy (f
, f
+ 2, 2);
2246 memcpy (f
+ 2, temp
, 2);
2250 fixp
->fx_frag
= prev_insn_frag
;
2251 fixp
->fx_where
= prev_insn_where
;
2255 /* Update the previous insn information; leave prev_insn
2257 prev_prev_insn
= *ip
;
2259 prev_insn_is_delay_slot
= 1;
2261 /* If that was an unconditional branch, forget the previous
2262 insn information. */
2263 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2265 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2266 prev_insn
.insn_mo
= &dummy_opcode
;
2269 prev_insn_fixp
= NULL
;
2270 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2271 prev_insn_extended
= 0;
2273 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2275 /* We don't yet optimize a branch likely. What we should do
2276 is look at the target, copy the instruction found there
2277 into the delay slot, and increment the branch to jump to
2278 the next instruction. */
2280 /* Update the previous insn information. */
2281 prev_prev_insn
= *ip
;
2282 prev_insn
.insn_mo
= &dummy_opcode
;
2283 prev_insn_fixp
= NULL
;
2284 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2285 prev_insn_extended
= 0;
2289 /* Update the previous insn information. */
2291 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2293 prev_prev_insn
= prev_insn
;
2296 /* Any time we see a branch, we always fill the delay slot
2297 immediately; since this insn is not a branch, we know it
2298 is not in a delay slot. */
2299 prev_insn_is_delay_slot
= 0;
2301 prev_insn_fixp
= fixp
;
2302 prev_insn_reloc_type
= reloc_type
;
2303 if (mips_opts
.mips16
)
2304 prev_insn_extended
= (ip
->use_extend
2305 || reloc_type
> BFD_RELOC_UNUSED
);
2308 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2309 prev_insn_unreordered
= 0;
2310 prev_insn_frag
= frag_now
;
2311 prev_insn_where
= f
- frag_now
->fr_literal
;
2312 prev_insn_valid
= 1;
2313 /* start-sanitize-branchbug4011 */
2314 prev_insn_labels
= !! insn_labels
;
2315 /* end-sanitize-branchbug4011 */
2317 else if (place
== NULL
)
2319 /* We need to record a bit of information even when we are not
2320 reordering, in order to determine the base address for mips16
2321 PC relative relocs. */
2322 prev_prev_insn
= prev_insn
;
2324 prev_insn_reloc_type
= reloc_type
;
2325 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2326 prev_insn_unreordered
= 1;
2327 /* start-sanitize-branchbug4011 */
2328 prev_insn_labels
= !! insn_labels
;
2329 /* end-sanitize-branchbug4011 */
2332 /* We just output an insn, so the next one doesn't have a label. */
2333 mips_clear_insn_labels ();
2335 /* We must ensure that a fixup associated with an unmatched %hi
2336 reloc does not become a variant frag. Otherwise, the
2337 rearrangement of %hi relocs in frob_file may confuse
2341 frag_wane (frag_now
);
2346 /* This function forgets that there was any previous instruction or
2347 label. If PRESERVE is non-zero, it remembers enough information to
2348 know whether nops are needed before a noreorder section. */
2351 mips_no_prev_insn (preserve
)
2356 prev_insn
.insn_mo
= &dummy_opcode
;
2357 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2358 prev_nop_frag
= NULL
;
2359 prev_nop_frag_holds
= 0;
2360 prev_nop_frag_required
= 0;
2361 prev_nop_frag_since
= 0;
2363 prev_insn_valid
= 0;
2364 prev_insn_is_delay_slot
= 0;
2365 prev_insn_unreordered
= 0;
2366 prev_insn_extended
= 0;
2367 /* start-sanitize-branchbug4011 */
2368 prev_insn_labels
= 0;
2369 /* end-sanitize-branchbug4011 */
2370 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2371 prev_prev_insn_unreordered
= 0;
2372 mips_clear_insn_labels ();
2375 /* This function must be called whenever we turn on noreorder or emit
2376 something other than instructions. It inserts any NOPS which might
2377 be needed by the previous instruction, and clears the information
2378 kept for the previous instructions. The INSNS parameter is true if
2379 instructions are to follow. */
2382 mips_emit_delays (insns
)
2385 if (! mips_opts
.noreorder
)
2390 if ((! mips_opts
.mips16
2391 && mips_opts
.isa
< 4
2392 && (! cop_interlocks
2393 && (prev_insn
.insn_mo
->pinfo
2394 & (INSN_LOAD_COPROC_DELAY
2395 | INSN_COPROC_MOVE_DELAY
2396 | INSN_WRITE_COND_CODE
))))
2397 || (! hilo_interlocks
2398 && (prev_insn
.insn_mo
->pinfo
2401 || (! mips_opts
.mips16
2403 && (prev_insn
.insn_mo
->pinfo
2404 & INSN_LOAD_MEMORY_DELAY
))
2405 || (! mips_opts
.mips16
2406 && mips_opts
.isa
< 2
2407 && (prev_insn
.insn_mo
->pinfo
2408 & INSN_COPROC_MEMORY_DELAY
)))
2410 /* Itbl support may require additional care here. */
2412 if ((! mips_opts
.mips16
2413 && mips_opts
.isa
< 4
2414 && (! cop_interlocks
2415 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2416 || (! hilo_interlocks
2417 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2418 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2421 if (prev_insn_unreordered
)
2424 else if ((! mips_opts
.mips16
2425 && mips_opts
.isa
< 4
2426 && (! cop_interlocks
2427 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2428 || (! hilo_interlocks
2429 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2430 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2432 /* Itbl support may require additional care here. */
2433 if (! prev_prev_insn_unreordered
)
2439 struct insn_label_list
*l
;
2443 /* Record the frag which holds the nop instructions, so
2444 that we can remove them if we don't need them. */
2445 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2446 prev_nop_frag
= frag_now
;
2447 prev_nop_frag_holds
= nops
;
2448 prev_nop_frag_required
= 0;
2449 prev_nop_frag_since
= 0;
2452 for (; nops
> 0; --nops
)
2457 /* Move on to a new frag, so that it is safe to simply
2458 decrease the size of prev_nop_frag. */
2459 frag_wane (frag_now
);
2463 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2465 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2466 l
->label
->sy_frag
= frag_now
;
2467 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2468 /* mips16 text labels are stored as odd. */
2469 if (mips_opts
.mips16
)
2470 ++l
->label
->sy_value
.X_add_number
;
2475 /* Mark instruction labels in mips16 mode. */
2476 if (mips_opts
.mips16
&& insns
)
2477 mips16_mark_labels ();
2479 mips_no_prev_insn (insns
);
2482 /* Build an instruction created by a macro expansion. This is passed
2483 a pointer to the count of instructions created so far, an
2484 expression, the name of the instruction to build, an operand format
2485 string, and corresponding arguments. */
2489 macro_build (char *place
,
2497 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2506 struct mips_cl_insn insn
;
2507 bfd_reloc_code_real_type r
;
2512 va_start (args
, fmt
);
2518 * If the macro is about to expand into a second instruction,
2519 * print a warning if needed. We need to pass ip as a parameter
2520 * to generate a better warning message here...
2522 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2523 as_warn (_("Macro instruction expanded into multiple instructions"));
2526 *counter
+= 1; /* bump instruction counter */
2528 if (mips_opts
.mips16
)
2530 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2535 r
= BFD_RELOC_UNUSED
;
2536 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2537 assert (insn
.insn_mo
);
2538 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2540 /* Search until we get a match for NAME. */
2543 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2545 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2547 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2549 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2554 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2555 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2556 && (insn_isa
<= mips_opts
.isa
2558 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2560 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2562 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2563 /* start-sanitize-vr4320 */
2565 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2566 /* end-sanitize-vr4320 */
2567 /* start-sanitize-tx49 */
2569 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2570 /* end-sanitize-tx49 */
2571 /* start-sanitize-r5900 */
2573 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2574 /* end-sanitize-r5900 */
2575 /* start-sanitize-cygnus */
2577 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2578 /* end-sanitize-cygnus */
2580 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2581 /* start-sanitize-r5900 */
2582 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2583 /* end-sanitize-r5900 */
2584 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2588 assert (insn
.insn_mo
->name
);
2589 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2592 insn
.insn_opcode
= insn
.insn_mo
->match
;
2608 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2614 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2619 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2624 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2631 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2635 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2639 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2643 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2650 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2656 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2657 assert (r
== BFD_RELOC_MIPS_GPREL
2658 || r
== BFD_RELOC_MIPS_LITERAL
2659 || r
== BFD_RELOC_LO16
2660 || r
== BFD_RELOC_MIPS_GOT16
2661 || r
== BFD_RELOC_MIPS_CALL16
2662 || r
== BFD_RELOC_MIPS_GOT_LO16
2663 || r
== BFD_RELOC_MIPS_CALL_LO16
2664 || (ep
->X_op
== O_subtract
2665 && now_seg
== text_section
2666 && r
== BFD_RELOC_PCREL_LO16
));
2670 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2672 && (ep
->X_op
== O_constant
2673 || (ep
->X_op
== O_symbol
2674 && (r
== BFD_RELOC_HI16_S
2675 || r
== BFD_RELOC_HI16
2676 || r
== BFD_RELOC_MIPS_GOT_HI16
2677 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2678 || (ep
->X_op
== O_subtract
2679 && now_seg
== text_section
2680 && r
== BFD_RELOC_PCREL_HI16_S
)));
2681 if (ep
->X_op
== O_constant
)
2683 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2685 r
= BFD_RELOC_UNUSED
;
2690 assert (ep
!= NULL
);
2692 * This allows macro() to pass an immediate expression for
2693 * creating short branches without creating a symbol.
2694 * Note that the expression still might come from the assembly
2695 * input, in which case the value is not checked for range nor
2696 * is a relocation entry generated (yuck).
2698 if (ep
->X_op
== O_constant
)
2700 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2704 r
= BFD_RELOC_16_PCREL_S2
;
2708 assert (ep
!= NULL
);
2709 r
= BFD_RELOC_MIPS_JMP
;
2713 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2722 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2724 append_insn (place
, &insn
, ep
, r
, false);
2728 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2736 struct mips_cl_insn insn
;
2737 bfd_reloc_code_real_type r
;
2739 r
= BFD_RELOC_UNUSED
;
2740 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2741 assert (insn
.insn_mo
);
2742 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2744 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2745 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2748 assert (insn
.insn_mo
->name
);
2749 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2752 insn
.insn_opcode
= insn
.insn_mo
->match
;
2753 insn
.use_extend
= false;
2772 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2777 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2781 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2785 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2795 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2802 regno
= va_arg (args
, int);
2803 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2804 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2825 assert (ep
!= NULL
);
2827 if (ep
->X_op
!= O_constant
)
2828 r
= BFD_RELOC_UNUSED
+ c
;
2831 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2832 false, false, &insn
.insn_opcode
,
2833 &insn
.use_extend
, &insn
.extend
);
2835 r
= BFD_RELOC_UNUSED
;
2841 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2848 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2850 append_insn (place
, &insn
, ep
, r
, false);
2854 * Generate a "lui" instruction.
2857 macro_build_lui (place
, counter
, ep
, regnum
)
2863 expressionS high_expr
;
2864 struct mips_cl_insn insn
;
2865 bfd_reloc_code_real_type r
;
2866 CONST
char *name
= "lui";
2867 CONST
char *fmt
= "t,u";
2869 assert (! mips_opts
.mips16
);
2875 high_expr
.X_op
= O_constant
;
2876 high_expr
.X_add_number
= ep
->X_add_number
;
2879 if (high_expr
.X_op
== O_constant
)
2881 /* we can compute the instruction now without a relocation entry */
2882 if (high_expr
.X_add_number
& 0x8000)
2883 high_expr
.X_add_number
+= 0x10000;
2884 high_expr
.X_add_number
=
2885 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2886 r
= BFD_RELOC_UNUSED
;
2890 assert (ep
->X_op
== O_symbol
);
2891 /* _gp_disp is a special case, used from s_cpload. */
2892 assert (mips_pic
== NO_PIC
2893 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2894 r
= BFD_RELOC_HI16_S
;
2898 * If the macro is about to expand into a second instruction,
2899 * print a warning if needed. We need to pass ip as a parameter
2900 * to generate a better warning message here...
2902 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2903 as_warn (_("Macro instruction expanded into multiple instructions"));
2906 *counter
+= 1; /* bump instruction counter */
2908 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2909 assert (insn
.insn_mo
);
2910 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2911 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2913 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2914 if (r
== BFD_RELOC_UNUSED
)
2916 insn
.insn_opcode
|= high_expr
.X_add_number
;
2917 append_insn (place
, &insn
, NULL
, r
, false);
2920 append_insn (place
, &insn
, &high_expr
, r
, false);
2924 * Generates code to set the $at register to true (one)
2925 * if reg is less than the immediate expression.
2928 set_at (counter
, reg
, unsignedp
)
2933 if (imm_expr
.X_op
== O_constant
2934 && imm_expr
.X_add_number
>= -0x8000
2935 && imm_expr
.X_add_number
< 0x8000)
2936 macro_build ((char *) NULL
, counter
, &imm_expr
,
2937 unsignedp
? "sltiu" : "slti",
2938 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2941 load_register (counter
, AT
, &imm_expr
, 0);
2942 macro_build ((char *) NULL
, counter
, NULL
,
2943 unsignedp
? "sltu" : "slt",
2944 "d,v,t", AT
, reg
, AT
);
2948 /* Warn if an expression is not a constant. */
2951 check_absolute_expr (ip
, ex
)
2952 struct mips_cl_insn
*ip
;
2955 if (ex
->X_op
== O_big
)
2956 as_bad (_("unsupported large constant"));
2957 else if (ex
->X_op
!= O_constant
)
2958 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2961 /* Count the leading zeroes by performing a binary chop. This is a
2962 bulky bit of source, but performance is a LOT better for the
2963 majority of values than a simple loop to count the bits:
2964 for (lcnt = 0; (lcnt < 32); lcnt++)
2965 if ((v) & (1 << (31 - lcnt)))
2967 However it is not code size friendly, and the gain will drop a bit
2968 on certain cached systems.
2970 #define COUNT_TOP_ZEROES(v) \
2971 (((v) & ~0xffff) == 0 \
2972 ? ((v) & ~0xff) == 0 \
2973 ? ((v) & ~0xf) == 0 \
2974 ? ((v) & ~0x3) == 0 \
2975 ? ((v) & ~0x1) == 0 \
2980 : ((v) & ~0x7) == 0 \
2983 : ((v) & ~0x3f) == 0 \
2984 ? ((v) & ~0x1f) == 0 \
2987 : ((v) & ~0x7f) == 0 \
2990 : ((v) & ~0xfff) == 0 \
2991 ? ((v) & ~0x3ff) == 0 \
2992 ? ((v) & ~0x1ff) == 0 \
2995 : ((v) & ~0x7ff) == 0 \
2998 : ((v) & ~0x3fff) == 0 \
2999 ? ((v) & ~0x1fff) == 0 \
3002 : ((v) & ~0x7fff) == 0 \
3005 : ((v) & ~0xffffff) == 0 \
3006 ? ((v) & ~0xfffff) == 0 \
3007 ? ((v) & ~0x3ffff) == 0 \
3008 ? ((v) & ~0x1ffff) == 0 \
3011 : ((v) & ~0x7ffff) == 0 \
3014 : ((v) & ~0x3fffff) == 0 \
3015 ? ((v) & ~0x1fffff) == 0 \
3018 : ((v) & ~0x7fffff) == 0 \
3021 : ((v) & ~0xfffffff) == 0 \
3022 ? ((v) & ~0x3ffffff) == 0 \
3023 ? ((v) & ~0x1ffffff) == 0 \
3026 : ((v) & ~0x7ffffff) == 0 \
3029 : ((v) & ~0x3fffffff) == 0 \
3030 ? ((v) & ~0x1fffffff) == 0 \
3033 : ((v) & ~0x7fffffff) == 0 \
3038 * This routine generates the least number of instructions neccessary to load
3039 * an absolute expression value into a register.
3042 load_register (counter
, reg
, ep
, dbl
)
3049 expressionS hi32
, lo32
;
3051 if (ep
->X_op
!= O_big
)
3053 assert (ep
->X_op
== O_constant
);
3054 if (ep
->X_add_number
< 0x8000
3055 && (ep
->X_add_number
>= 0
3056 || (ep
->X_add_number
>= -0x8000
3059 || sizeof (ep
->X_add_number
) > 4))))
3061 /* We can handle 16 bit signed values with an addiu to
3062 $zero. No need to ever use daddiu here, since $zero and
3063 the result are always correct in 32 bit mode. */
3064 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3065 (int) BFD_RELOC_LO16
);
3068 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3070 /* We can handle 16 bit unsigned values with an ori to
3072 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3073 (int) BFD_RELOC_LO16
);
3076 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3077 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3078 == ~ (offsetT
) 0x7fffffff))
3081 || sizeof (ep
->X_add_number
) > 4
3082 || (ep
->X_add_number
& 0x80000000) == 0))
3083 || ((mips_opts
.isa
< 3 || ! dbl
)
3084 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3085 || (mips_opts
.isa
< 3
3087 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3088 == ~ (offsetT
) 0xffffffff)))
3090 /* 32 bit values require an lui. */
3091 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3092 (int) BFD_RELOC_HI16
);
3093 if ((ep
->X_add_number
& 0xffff) != 0)
3094 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3095 (int) BFD_RELOC_LO16
);
3100 /* The value is larger than 32 bits. */
3102 if (mips_opts
.isa
< 3)
3104 as_bad (_("Number larger than 32 bits"));
3105 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3106 (int) BFD_RELOC_LO16
);
3110 if (ep
->X_op
!= O_big
)
3113 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3114 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3115 hi32
.X_add_number
&= 0xffffffff;
3117 lo32
.X_add_number
&= 0xffffffff;
3121 assert (ep
->X_add_number
> 2);
3122 if (ep
->X_add_number
== 3)
3123 generic_bignum
[3] = 0;
3124 else if (ep
->X_add_number
> 4)
3125 as_bad (_("Number larger than 64 bits"));
3126 lo32
.X_op
= O_constant
;
3127 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3128 hi32
.X_op
= O_constant
;
3129 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3132 if (hi32
.X_add_number
== 0)
3137 unsigned long hi
, lo
;
3139 if (hi32
.X_add_number
== 0xffffffff)
3141 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3143 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3144 reg
, 0, (int) BFD_RELOC_LO16
);
3147 if (lo32
.X_add_number
& 0x80000000)
3149 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3150 (int) BFD_RELOC_HI16
);
3151 if (lo32
.X_add_number
& 0xffff)
3152 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3153 reg
, reg
, (int) BFD_RELOC_LO16
);
3158 /* Check for 16bit shifted constant. We know that hi32 is
3159 non-zero, so start the mask on the first bit of the hi32
3164 unsigned long himask
, lomask
;
3168 himask
= 0xffff >> (32 - shift
);
3169 lomask
= (0xffff << shift
) & 0xffffffff;
3173 himask
= 0xffff << (shift
- 32);
3176 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3177 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3181 tmp
.X_op
= O_constant
;
3183 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3184 | (lo32
.X_add_number
>> shift
));
3186 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3187 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3188 (int) BFD_RELOC_LO16
);
3189 macro_build ((char *) NULL
, counter
, NULL
,
3190 (shift
>= 32) ? "dsll32" : "dsll",
3192 (shift
>= 32) ? shift
- 32 : shift
);
3196 } while (shift
<= (64 - 16));
3198 /* Find the bit number of the lowest one bit, and store the
3199 shifted value in hi/lo. */
3200 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3201 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3205 while ((lo
& 1) == 0)
3210 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3216 while ((hi
& 1) == 0)
3225 /* Optimize if the shifted value is a (power of 2) - 1. */
3226 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3227 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3229 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3234 /* This instruction will set the register to be all
3236 tmp
.X_op
= O_constant
;
3237 tmp
.X_add_number
= (offsetT
) -1;
3238 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3239 reg
, 0, (int) BFD_RELOC_LO16
);
3243 macro_build ((char *) NULL
, counter
, NULL
,
3244 (bit
>= 32) ? "dsll32" : "dsll",
3246 (bit
>= 32) ? bit
- 32 : bit
);
3248 macro_build ((char *) NULL
, counter
, NULL
,
3249 (shift
>= 32) ? "dsrl32" : "dsrl",
3251 (shift
>= 32) ? shift
- 32 : shift
);
3256 /* Sign extend hi32 before calling load_register, because we can
3257 generally get better code when we load a sign extended value. */
3258 if ((hi32
.X_add_number
& 0x80000000) != 0)
3259 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3260 load_register (counter
, reg
, &hi32
, 0);
3263 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3267 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3276 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3278 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3279 (int) BFD_RELOC_HI16
);
3280 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3287 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3292 mid16
.X_add_number
>>= 16;
3293 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3294 freg
, (int) BFD_RELOC_LO16
);
3295 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3299 if ((lo32
.X_add_number
& 0xffff) != 0)
3300 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3301 (int) BFD_RELOC_LO16
);
3304 /* Load an address into a register. */
3307 load_address (counter
, reg
, ep
)
3314 if (ep
->X_op
!= O_constant
3315 && ep
->X_op
!= O_symbol
)
3317 as_bad (_("expression too complex"));
3318 ep
->X_op
= O_constant
;
3321 if (ep
->X_op
== O_constant
)
3323 load_register (counter
, reg
, ep
, 0);
3327 if (mips_pic
== NO_PIC
)
3329 /* If this is a reference to a GP relative symbol, we want
3330 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3332 lui $reg,<sym> (BFD_RELOC_HI16_S)
3333 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3334 If we have an addend, we always use the latter form. */
3335 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3336 || nopic_need_relax (ep
->X_add_symbol
, 1))
3341 macro_build ((char *) NULL
, counter
, ep
,
3342 ((bfd_arch_bits_per_address (stdoutput
) == 32
3343 || mips_opts
.isa
< 3)
3344 ? "addiu" : "daddiu"),
3345 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3346 p
= frag_var (rs_machine_dependent
, 8, 0,
3347 RELAX_ENCODE (4, 8, 0, 4, 0,
3348 mips_opts
.warn_about_macros
),
3349 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3351 macro_build_lui (p
, counter
, ep
, reg
);
3354 macro_build (p
, counter
, ep
,
3355 ((bfd_arch_bits_per_address (stdoutput
) == 32
3356 || mips_opts
.isa
< 3)
3357 ? "addiu" : "daddiu"),
3358 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3360 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3364 /* If this is a reference to an external symbol, we want
3365 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3367 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3369 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3370 If there is a constant, it must be added in after. */
3371 ex
.X_add_number
= ep
->X_add_number
;
3372 ep
->X_add_number
= 0;
3374 macro_build ((char *) NULL
, counter
, ep
,
3375 ((bfd_arch_bits_per_address (stdoutput
) == 32
3376 || mips_opts
.isa
< 3)
3378 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3379 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3380 p
= frag_var (rs_machine_dependent
, 4, 0,
3381 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3382 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3383 macro_build (p
, counter
, ep
,
3384 ((bfd_arch_bits_per_address (stdoutput
) == 32
3385 || mips_opts
.isa
< 3)
3386 ? "addiu" : "daddiu"),
3387 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3388 if (ex
.X_add_number
!= 0)
3390 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3391 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3392 ex
.X_op
= O_constant
;
3393 macro_build ((char *) NULL
, counter
, &ex
,
3394 ((bfd_arch_bits_per_address (stdoutput
) == 32
3395 || mips_opts
.isa
< 3)
3396 ? "addiu" : "daddiu"),
3397 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3400 else if (mips_pic
== SVR4_PIC
)
3405 /* This is the large GOT case. If this is a reference to an
3406 external symbol, we want
3407 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3409 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3410 Otherwise, for a reference to a local symbol, we want
3411 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3413 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3414 If there is a constant, it must be added in after. */
3415 ex
.X_add_number
= ep
->X_add_number
;
3416 ep
->X_add_number
= 0;
3417 if (reg_needs_delay (GP
))
3422 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3423 (int) BFD_RELOC_MIPS_GOT_HI16
);
3424 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3425 ((bfd_arch_bits_per_address (stdoutput
) == 32
3426 || mips_opts
.isa
< 3)
3427 ? "addu" : "daddu"),
3428 "d,v,t", reg
, reg
, GP
);
3429 macro_build ((char *) NULL
, counter
, ep
,
3430 ((bfd_arch_bits_per_address (stdoutput
) == 32
3431 || mips_opts
.isa
< 3)
3433 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3434 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3435 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3436 mips_opts
.warn_about_macros
),
3437 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3440 /* We need a nop before loading from $gp. This special
3441 check is required because the lui which starts the main
3442 instruction stream does not refer to $gp, and so will not
3443 insert the nop which may be required. */
3444 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3447 macro_build (p
, counter
, ep
,
3448 ((bfd_arch_bits_per_address (stdoutput
) == 32
3449 || mips_opts
.isa
< 3)
3451 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3453 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3455 macro_build (p
, counter
, ep
,
3456 ((bfd_arch_bits_per_address (stdoutput
) == 32
3457 || mips_opts
.isa
< 3)
3458 ? "addiu" : "daddiu"),
3459 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3460 if (ex
.X_add_number
!= 0)
3462 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3463 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3464 ex
.X_op
= O_constant
;
3465 macro_build ((char *) NULL
, counter
, &ex
,
3466 ((bfd_arch_bits_per_address (stdoutput
) == 32
3467 || mips_opts
.isa
< 3)
3468 ? "addiu" : "daddiu"),
3469 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3472 else if (mips_pic
== EMBEDDED_PIC
)
3475 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3477 macro_build ((char *) NULL
, counter
, ep
,
3478 ((bfd_arch_bits_per_address (stdoutput
) == 32
3479 || mips_opts
.isa
< 3)
3480 ? "addiu" : "daddiu"),
3481 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3489 * This routine implements the seemingly endless macro or synthesized
3490 * instructions and addressing modes in the mips assembly language. Many
3491 * of these macros are simple and are similar to each other. These could
3492 * probably be handled by some kind of table or grammer aproach instead of
3493 * this verbose method. Others are not simple macros but are more like
3494 * optimizing code generation.
3495 * One interesting optimization is when several store macros appear
3496 * consecutivly that would load AT with the upper half of the same address.
3497 * The ensuing load upper instructions are ommited. This implies some kind
3498 * of global optimization. We currently only optimize within a single macro.
3499 * For many of the load and store macros if the address is specified as a
3500 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3501 * first load register 'at' with zero and use it as the base register. The
3502 * mips assembler simply uses register $zero. Just one tiny optimization
3507 struct mips_cl_insn
*ip
;
3509 register int treg
, sreg
, dreg
, breg
;
3525 bfd_reloc_code_real_type r
;
3527 int hold_mips_optimize
;
3529 assert (! mips_opts
.mips16
);
3531 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3532 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3533 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3534 mask
= ip
->insn_mo
->mask
;
3536 expr1
.X_op
= O_constant
;
3537 expr1
.X_op_symbol
= NULL
;
3538 expr1
.X_add_symbol
= NULL
;
3539 expr1
.X_add_number
= 1;
3551 mips_emit_delays (true);
3552 ++mips_opts
.noreorder
;
3553 mips_any_noreorder
= 1;
3555 expr1
.X_add_number
= 8;
3556 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3558 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3561 macro_build ((char *) NULL
, &icnt
, NULL
,
3562 dbl
? "dsub" : "sub",
3563 "d,v,t", dreg
, 0, sreg
);
3565 --mips_opts
.noreorder
;
3586 if (imm_expr
.X_op
== O_constant
3587 && imm_expr
.X_add_number
>= -0x8000
3588 && imm_expr
.X_add_number
< 0x8000)
3590 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3591 (int) BFD_RELOC_LO16
);
3594 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3595 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3614 if (imm_expr
.X_op
== O_constant
3615 && imm_expr
.X_add_number
>= 0
3616 && imm_expr
.X_add_number
< 0x10000)
3618 if (mask
!= M_NOR_I
)
3619 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3620 sreg
, (int) BFD_RELOC_LO16
);
3623 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3624 treg
, sreg
, (int) BFD_RELOC_LO16
);
3625 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3631 load_register (&icnt
, AT
, &imm_expr
, 0);
3632 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3649 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3651 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3655 load_register (&icnt
, AT
, &imm_expr
, 0);
3656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3664 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3665 likely
? "bgezl" : "bgez",
3671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3672 likely
? "blezl" : "blez",
3676 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3677 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3678 likely
? "beql" : "beq",
3685 /* check for > max integer */
3686 maxnum
= 0x7fffffff;
3687 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3694 if (imm_expr
.X_op
== O_constant
3695 && imm_expr
.X_add_number
>= maxnum
3696 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3699 /* result is always false */
3702 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3707 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3713 if (imm_expr
.X_op
!= O_constant
)
3714 as_bad (_("Unsupported large constant"));
3715 imm_expr
.X_add_number
++;
3719 if (mask
== M_BGEL_I
)
3721 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3723 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3724 likely
? "bgezl" : "bgez",
3728 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3730 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3731 likely
? "bgtzl" : "bgtz",
3735 maxnum
= 0x7fffffff;
3736 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3743 maxnum
= - maxnum
- 1;
3744 if (imm_expr
.X_op
== O_constant
3745 && imm_expr
.X_add_number
<= maxnum
3746 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3749 /* result is always true */
3750 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3754 set_at (&icnt
, sreg
, 0);
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 likely
? "beql" : "beq",
3767 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3768 likely
? "beql" : "beq",
3772 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3775 likely
? "beql" : "beq",
3783 || (mips_opts
.isa
< 3
3784 && imm_expr
.X_op
== O_constant
3785 && imm_expr
.X_add_number
== 0xffffffff))
3787 if (imm_expr
.X_op
!= O_constant
)
3788 as_bad (_("Unsupported large constant"));
3789 imm_expr
.X_add_number
++;
3793 if (mask
== M_BGEUL_I
)
3795 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3797 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3800 likely
? "bnel" : "bne",
3804 set_at (&icnt
, sreg
, 1);
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3806 likely
? "beql" : "beq",
3815 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3816 likely
? "bgtzl" : "bgtz",
3822 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3823 likely
? "bltzl" : "bltz",
3827 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3828 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3829 likely
? "bnel" : "bne",
3838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3839 likely
? "bnel" : "bne",
3845 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3848 likely
? "bnel" : "bne",
3857 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3858 likely
? "blezl" : "blez",
3864 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3865 likely
? "bgezl" : "bgez",
3869 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "beql" : "beq",
3878 maxnum
= 0x7fffffff;
3879 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3886 if (imm_expr
.X_op
== O_constant
3887 && imm_expr
.X_add_number
>= maxnum
3888 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3890 if (imm_expr
.X_op
!= O_constant
)
3891 as_bad (_("Unsupported large constant"));
3892 imm_expr
.X_add_number
++;
3896 if (mask
== M_BLTL_I
)
3898 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3900 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3901 likely
? "bltzl" : "bltz",
3905 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3907 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3908 likely
? "blezl" : "blez",
3912 set_at (&icnt
, sreg
, 0);
3913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3914 likely
? "bnel" : "bne",
3923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3924 likely
? "beql" : "beq",
3930 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3933 likely
? "beql" : "beq",
3941 || (mips_opts
.isa
< 3
3942 && imm_expr
.X_op
== O_constant
3943 && imm_expr
.X_add_number
== 0xffffffff))
3945 if (imm_expr
.X_op
!= O_constant
)
3946 as_bad (_("Unsupported large constant"));
3947 imm_expr
.X_add_number
++;
3951 if (mask
== M_BLTUL_I
)
3953 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3955 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3958 likely
? "beql" : "beq",
3962 set_at (&icnt
, sreg
, 1);
3963 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3964 likely
? "bnel" : "bne",
3973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3974 likely
? "bltzl" : "bltz",
3980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3981 likely
? "bgtzl" : "bgtz",
3985 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3987 likely
? "bnel" : "bne",
3998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3999 likely
? "bnel" : "bne",
4003 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4005 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4006 likely
? "bnel" : "bne",
4022 as_warn (_("Divide by zero."));
4024 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4026 /* start-sanitize-r5900 */
4028 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4030 /* end-sanitize-r5900 */
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4035 mips_emit_delays (true);
4036 ++mips_opts
.noreorder
;
4037 mips_any_noreorder
= 1;
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4041 macro_build ((char *) NULL
, &icnt
, NULL
,
4042 dbl
? "ddiv" : "div",
4043 "z,s,t", sreg
, treg
);
4047 expr1
.X_add_number
= 8;
4048 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4049 macro_build ((char *) NULL
, &icnt
, NULL
,
4050 dbl
? "ddiv" : "div",
4051 "z,s,t", sreg
, treg
);
4052 /* start-sanitize-r5900 */
4054 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4056 /* end-sanitize-r5900 */
4057 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4059 expr1
.X_add_number
= -1;
4060 macro_build ((char *) NULL
, &icnt
, &expr1
,
4061 dbl
? "daddiu" : "addiu",
4062 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4063 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4064 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4067 expr1
.X_add_number
= 1;
4068 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4069 (int) BFD_RELOC_LO16
);
4070 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4075 expr1
.X_add_number
= 0x80000000;
4076 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4077 (int) BFD_RELOC_HI16
);
4081 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4082 /* We want to close the noreorder block as soon as possible, so
4083 that later insns are available for delay slot filling. */
4084 --mips_opts
.noreorder
;
4088 expr1
.X_add_number
= 8;
4089 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4090 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4092 /* We want to close the noreorder block as soon as possible, so
4093 that later insns are available for delay slot filling. */
4094 --mips_opts
.noreorder
;
4096 /* start-sanitize-r5900 */
4098 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
4100 /* end-sanitize-r5900 */
4101 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4142 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4144 as_warn (_("Divide by zero."));
4146 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4148 /* start-sanitize-r5900 */
4150 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4152 /* end-sanitize-r5900 */
4153 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4156 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4158 if (strcmp (s2
, "mflo") == 0)
4159 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4162 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4165 if (imm_expr
.X_op
== O_constant
4166 && imm_expr
.X_add_number
== -1
4167 && s
[strlen (s
) - 1] != 'u')
4169 if (strcmp (s2
, "mflo") == 0)
4172 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4175 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4179 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4183 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4184 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4185 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4204 mips_emit_delays (true);
4205 ++mips_opts
.noreorder
;
4206 mips_any_noreorder
= 1;
4209 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4210 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4211 /* We want to close the noreorder block as soon as possible, so
4212 that later insns are available for delay slot filling. */
4213 --mips_opts
.noreorder
;
4217 expr1
.X_add_number
= 8;
4218 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4219 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4221 /* We want to close the noreorder block as soon as possible, so
4222 that later insns are available for delay slot filling. */
4223 --mips_opts
.noreorder
;
4224 /* start-sanitize-r5900 */
4226 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4228 /* end-sanitize-r5900 */
4229 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4231 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4237 /* Load the address of a symbol into a register. If breg is not
4238 zero, we then add a base register to it. */
4240 /* When generating embedded PIC code, we permit expressions of
4243 where bar is an address in the .text section. These are used
4244 when getting the addresses of functions. We don't permit
4245 X_add_number to be non-zero, because if the symbol is
4246 external the relaxing code needs to know that any addend is
4247 purely the offset to X_op_symbol. */
4248 if (mips_pic
== EMBEDDED_PIC
4249 && offset_expr
.X_op
== O_subtract
4250 && now_seg
== text_section
4251 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4252 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4253 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4254 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4255 ->sy_value
.X_add_symbol
)
4258 && offset_expr
.X_add_number
== 0)
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4261 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4263 ((bfd_arch_bits_per_address (stdoutput
) == 32
4264 || mips_opts
.isa
< 3)
4265 ? "addiu" : "daddiu"),
4266 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4270 if (offset_expr
.X_op
!= O_symbol
4271 && offset_expr
.X_op
!= O_constant
)
4273 as_bad (_("expression too complex"));
4274 offset_expr
.X_op
= O_constant
;
4288 if (offset_expr
.X_op
== O_constant
)
4289 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4290 else if (mips_pic
== NO_PIC
)
4292 /* If this is a reference to an GP relative symbol, we want
4293 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4295 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4296 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4297 If we have a constant, we need two instructions anyhow,
4298 so we may as well always use the latter form. */
4299 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4300 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4306 ((bfd_arch_bits_per_address (stdoutput
) == 32
4307 || mips_opts
.isa
< 3)
4308 ? "addiu" : "daddiu"),
4309 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4310 p
= frag_var (rs_machine_dependent
, 8, 0,
4311 RELAX_ENCODE (4, 8, 0, 4, 0,
4312 mips_opts
.warn_about_macros
),
4313 offset_expr
.X_add_symbol
, (offsetT
) 0,
4316 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4319 macro_build (p
, &icnt
, &offset_expr
,
4320 ((bfd_arch_bits_per_address (stdoutput
) == 32
4321 || mips_opts
.isa
< 3)
4322 ? "addiu" : "daddiu"),
4323 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4325 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4327 /* If this is a reference to an external symbol, and there
4328 is no constant, we want
4329 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4330 For a local symbol, we want
4331 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4333 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4335 If we have a small constant, and this is a reference to
4336 an external symbol, we want
4337 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4339 addiu $tempreg,$tempreg,<constant>
4340 For a local symbol, we want the same instruction
4341 sequence, but we output a BFD_RELOC_LO16 reloc on the
4344 If we have a large constant, and this is a reference to
4345 an external symbol, we want
4346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4347 lui $at,<hiconstant>
4348 addiu $at,$at,<loconstant>
4349 addu $tempreg,$tempreg,$at
4350 For a local symbol, we want the same instruction
4351 sequence, but we output a BFD_RELOC_LO16 reloc on the
4352 addiu instruction. */
4353 expr1
.X_add_number
= offset_expr
.X_add_number
;
4354 offset_expr
.X_add_number
= 0;
4356 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4358 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4359 if (expr1
.X_add_number
== 0)
4367 /* We're going to put in an addu instruction using
4368 tempreg, so we may as well insert the nop right
4370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4374 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4375 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4377 ? mips_opts
.warn_about_macros
4379 offset_expr
.X_add_symbol
, (offsetT
) 0,
4383 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4386 macro_build (p
, &icnt
, &expr1
,
4387 ((bfd_arch_bits_per_address (stdoutput
) == 32
4388 || mips_opts
.isa
< 3)
4389 ? "addiu" : "daddiu"),
4390 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4391 /* FIXME: If breg == 0, and the next instruction uses
4392 $tempreg, then if this variant case is used an extra
4393 nop will be generated. */
4395 else if (expr1
.X_add_number
>= -0x8000
4396 && expr1
.X_add_number
< 0x8000)
4398 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4400 macro_build ((char *) NULL
, &icnt
, &expr1
,
4401 ((bfd_arch_bits_per_address (stdoutput
) == 32
4402 || mips_opts
.isa
< 3)
4403 ? "addiu" : "daddiu"),
4404 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4405 (void) frag_var (rs_machine_dependent
, 0, 0,
4406 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4407 offset_expr
.X_add_symbol
, (offsetT
) 0,
4414 /* If we are going to add in a base register, and the
4415 target register and the base register are the same,
4416 then we are using AT as a temporary register. Since
4417 we want to load the constant into AT, we add our
4418 current AT (from the global offset table) and the
4419 register into the register now, and pretend we were
4420 not using a base register. */
4425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4427 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4428 ((bfd_arch_bits_per_address (stdoutput
) == 32
4429 || mips_opts
.isa
< 3)
4430 ? "addu" : "daddu"),
4431 "d,v,t", treg
, AT
, breg
);
4437 /* Set mips_optimize around the lui instruction to avoid
4438 inserting an unnecessary nop after the lw. */
4439 hold_mips_optimize
= mips_optimize
;
4441 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4442 mips_optimize
= hold_mips_optimize
;
4444 macro_build ((char *) NULL
, &icnt
, &expr1
,
4445 ((bfd_arch_bits_per_address (stdoutput
) == 32
4446 || mips_opts
.isa
< 3)
4447 ? "addiu" : "daddiu"),
4448 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4450 ((bfd_arch_bits_per_address (stdoutput
) == 32
4451 || mips_opts
.isa
< 3)
4452 ? "addu" : "daddu"),
4453 "d,v,t", tempreg
, tempreg
, AT
);
4454 (void) frag_var (rs_machine_dependent
, 0, 0,
4455 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4456 offset_expr
.X_add_symbol
, (offsetT
) 0,
4461 else if (mips_pic
== SVR4_PIC
)
4465 /* This is the large GOT case. If this is a reference to an
4466 external symbol, and there is no constant, we want
4467 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4468 addu $tempreg,$tempreg,$gp
4469 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4470 For a local symbol, we want
4471 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4473 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4475 If we have a small constant, and this is a reference to
4476 an external symbol, we want
4477 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4478 addu $tempreg,$tempreg,$gp
4479 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4481 addiu $tempreg,$tempreg,<constant>
4482 For a local symbol, we want
4483 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4485 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4487 If we have a large constant, and this is a reference to
4488 an external symbol, we want
4489 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4490 addu $tempreg,$tempreg,$gp
4491 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4492 lui $at,<hiconstant>
4493 addiu $at,$at,<loconstant>
4494 addu $tempreg,$tempreg,$at
4495 For a local symbol, we want
4496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4497 lui $at,<hiconstant>
4498 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4499 addu $tempreg,$tempreg,$at
4501 expr1
.X_add_number
= offset_expr
.X_add_number
;
4502 offset_expr
.X_add_number
= 0;
4504 if (reg_needs_delay (GP
))
4508 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4509 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4511 ((bfd_arch_bits_per_address (stdoutput
) == 32
4512 || mips_opts
.isa
< 3)
4513 ? "addu" : "daddu"),
4514 "d,v,t", tempreg
, tempreg
, GP
);
4515 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4517 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4519 if (expr1
.X_add_number
== 0)
4527 /* We're going to put in an addu instruction using
4528 tempreg, so we may as well insert the nop right
4530 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4535 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4536 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4539 ? mips_opts
.warn_about_macros
4541 offset_expr
.X_add_symbol
, (offsetT
) 0,
4544 else if (expr1
.X_add_number
>= -0x8000
4545 && expr1
.X_add_number
< 0x8000)
4547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4549 macro_build ((char *) NULL
, &icnt
, &expr1
,
4550 ((bfd_arch_bits_per_address (stdoutput
) == 32
4551 || mips_opts
.isa
< 3)
4552 ? "addiu" : "daddiu"),
4553 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4555 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4556 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4558 ? mips_opts
.warn_about_macros
4560 offset_expr
.X_add_symbol
, (offsetT
) 0,
4567 /* If we are going to add in a base register, and the
4568 target register and the base register are the same,
4569 then we are using AT as a temporary register. Since
4570 we want to load the constant into AT, we add our
4571 current AT (from the global offset table) and the
4572 register into the register now, and pretend we were
4573 not using a base register. */
4581 assert (tempreg
== AT
);
4582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4585 ((bfd_arch_bits_per_address (stdoutput
) == 32
4586 || mips_opts
.isa
< 3)
4587 ? "addu" : "daddu"),
4588 "d,v,t", treg
, AT
, breg
);
4593 /* Set mips_optimize around the lui instruction to avoid
4594 inserting an unnecessary nop after the lw. */
4595 hold_mips_optimize
= mips_optimize
;
4597 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4598 mips_optimize
= hold_mips_optimize
;
4600 macro_build ((char *) NULL
, &icnt
, &expr1
,
4601 ((bfd_arch_bits_per_address (stdoutput
) == 32
4602 || mips_opts
.isa
< 3)
4603 ? "addiu" : "daddiu"),
4604 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4606 ((bfd_arch_bits_per_address (stdoutput
) == 32
4607 || mips_opts
.isa
< 3)
4608 ? "addu" : "daddu"),
4609 "d,v,t", dreg
, dreg
, AT
);
4611 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4612 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4615 ? mips_opts
.warn_about_macros
4617 offset_expr
.X_add_symbol
, (offsetT
) 0,
4625 /* This is needed because this instruction uses $gp, but
4626 the first instruction on the main stream does not. */
4627 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4630 macro_build (p
, &icnt
, &offset_expr
,
4632 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4634 if (expr1
.X_add_number
>= -0x8000
4635 && expr1
.X_add_number
< 0x8000)
4637 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4639 macro_build (p
, &icnt
, &expr1
,
4640 ((bfd_arch_bits_per_address (stdoutput
) == 32
4641 || mips_opts
.isa
< 3)
4642 ? "addiu" : "daddiu"),
4643 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4644 /* FIXME: If add_number is 0, and there was no base
4645 register, the external symbol case ended with a load,
4646 so if the symbol turns out to not be external, and
4647 the next instruction uses tempreg, an unnecessary nop
4648 will be inserted. */
4654 /* We must add in the base register now, as in the
4655 external symbol case. */
4656 assert (tempreg
== AT
);
4657 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4659 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4660 ((bfd_arch_bits_per_address (stdoutput
) == 32
4661 || mips_opts
.isa
< 3)
4662 ? "addu" : "daddu"),
4663 "d,v,t", treg
, AT
, breg
);
4666 /* We set breg to 0 because we have arranged to add
4667 it in in both cases. */
4671 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4673 macro_build (p
, &icnt
, &expr1
,
4674 ((bfd_arch_bits_per_address (stdoutput
) == 32
4675 || mips_opts
.isa
< 3)
4676 ? "addiu" : "daddiu"),
4677 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4679 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4680 ((bfd_arch_bits_per_address (stdoutput
) == 32
4681 || mips_opts
.isa
< 3)
4682 ? "addu" : "daddu"),
4683 "d,v,t", tempreg
, tempreg
, AT
);
4687 else if (mips_pic
== EMBEDDED_PIC
)
4690 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4692 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4693 ((bfd_arch_bits_per_address (stdoutput
) == 32
4694 || mips_opts
.isa
< 3)
4695 ? "addiu" : "daddiu"),
4696 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4703 ((bfd_arch_bits_per_address (stdoutput
) == 32
4704 || mips_opts
.isa
< 3)
4705 ? "addu" : "daddu"),
4706 "d,v,t", treg
, tempreg
, breg
);
4714 /* The j instruction may not be used in PIC code, since it
4715 requires an absolute address. We convert it to a b
4717 if (mips_pic
== NO_PIC
)
4718 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4720 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4723 /* The jal instructions must be handled as macros because when
4724 generating PIC code they expand to multi-instruction
4725 sequences. Normally they are simple instructions. */
4730 if (mips_pic
== NO_PIC
4731 || mips_pic
== EMBEDDED_PIC
)
4732 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4734 else if (mips_pic
== SVR4_PIC
)
4736 if (sreg
!= PIC_CALL_REG
)
4737 as_warn (_("MIPS PIC call to register other than $25"));
4739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4741 if (mips_cprestore_offset
< 0)
4742 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4745 expr1
.X_add_number
= mips_cprestore_offset
;
4746 macro_build ((char *) NULL
, &icnt
, &expr1
,
4747 ((bfd_arch_bits_per_address (stdoutput
) == 32
4748 || mips_opts
.isa
< 3)
4750 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4759 if (mips_pic
== NO_PIC
)
4760 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4761 else if (mips_pic
== SVR4_PIC
)
4763 /* If this is a reference to an external symbol, and we are
4764 using a small GOT, we want
4765 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4769 lw $gp,cprestore($sp)
4770 The cprestore value is set using the .cprestore
4771 pseudo-op. If we are using a big GOT, we want
4772 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4774 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4778 lw $gp,cprestore($sp)
4779 If the symbol is not external, we want
4780 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4782 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4785 lw $gp,cprestore($sp) */
4789 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4790 ((bfd_arch_bits_per_address (stdoutput
) == 32
4791 || mips_opts
.isa
< 3)
4793 "t,o(b)", PIC_CALL_REG
,
4794 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4797 p
= frag_var (rs_machine_dependent
, 4, 0,
4798 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4799 offset_expr
.X_add_symbol
, (offsetT
) 0,
4806 if (reg_needs_delay (GP
))
4810 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4811 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4813 ((bfd_arch_bits_per_address (stdoutput
) == 32
4814 || mips_opts
.isa
< 3)
4815 ? "addu" : "daddu"),
4816 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4818 ((bfd_arch_bits_per_address (stdoutput
) == 32
4819 || mips_opts
.isa
< 3)
4821 "t,o(b)", PIC_CALL_REG
,
4822 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4825 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4826 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4828 offset_expr
.X_add_symbol
, (offsetT
) 0,
4832 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4835 macro_build (p
, &icnt
, &offset_expr
,
4836 ((bfd_arch_bits_per_address (stdoutput
) == 32
4837 || mips_opts
.isa
< 3)
4839 "t,o(b)", PIC_CALL_REG
,
4840 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4842 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4845 macro_build (p
, &icnt
, &offset_expr
,
4846 ((bfd_arch_bits_per_address (stdoutput
) == 32
4847 || mips_opts
.isa
< 3)
4848 ? "addiu" : "daddiu"),
4849 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4850 (int) BFD_RELOC_LO16
);
4851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4852 "jalr", "s", PIC_CALL_REG
);
4853 if (mips_cprestore_offset
< 0)
4854 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4857 if (mips_opts
.noreorder
)
4858 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4860 expr1
.X_add_number
= mips_cprestore_offset
;
4861 macro_build ((char *) NULL
, &icnt
, &expr1
,
4862 ((bfd_arch_bits_per_address (stdoutput
) == 32
4863 || mips_opts
.isa
< 3)
4865 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4869 else if (mips_pic
== EMBEDDED_PIC
)
4871 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4872 /* The linker may expand the call to a longer sequence which
4873 uses $at, so we must break rather than return. */
4898 /* Itbl support may require additional care here. */
4903 /* Itbl support may require additional care here. */
4908 /* Itbl support may require additional care here. */
4913 /* Itbl support may require additional care here. */
4927 as_bad (_("opcode not supported on this processor"));
4931 /* Itbl support may require additional care here. */
4936 /* Itbl support may require additional care here. */
4941 /* Itbl support may require additional care here. */
4961 if (breg
== treg
|| coproc
|| lr
)
4983 /* Itbl support may require additional care here. */
4988 /* Itbl support may require additional care here. */
4993 /* Itbl support may require additional care here. */
4998 /* Itbl support may require additional care here. */
5016 as_bad (_("opcode not supported on this processor"));
5021 /* Itbl support may require additional care here. */
5025 /* Itbl support may require additional care here. */
5030 /* Itbl support may require additional care here. */
5042 /* Itbl support may require additional care here. */
5043 if (mask
== M_LWC1_AB
5044 || mask
== M_SWC1_AB
5045 || mask
== M_LDC1_AB
5046 || mask
== M_SDC1_AB
5055 if (offset_expr
.X_op
!= O_constant
5056 && offset_expr
.X_op
!= O_symbol
)
5058 as_bad (_("expression too complex"));
5059 offset_expr
.X_op
= O_constant
;
5062 /* A constant expression in PIC code can be handled just as it
5063 is in non PIC code. */
5064 if (mips_pic
== NO_PIC
5065 || offset_expr
.X_op
== O_constant
)
5067 /* If this is a reference to a GP relative symbol, and there
5068 is no base register, we want
5069 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5070 Otherwise, if there is no base register, we want
5071 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5072 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5073 If we have a constant, we need two instructions anyhow,
5074 so we always use the latter form.
5076 If we have a base register, and this is a reference to a
5077 GP relative symbol, we want
5078 addu $tempreg,$breg,$gp
5079 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5081 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5082 addu $tempreg,$tempreg,$breg
5083 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5084 With a constant we always use the latter case. */
5087 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5088 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5094 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5095 p
= frag_var (rs_machine_dependent
, 8, 0,
5096 RELAX_ENCODE (4, 8, 0, 4, 0,
5097 (mips_opts
.warn_about_macros
5099 && mips_opts
.noat
))),
5100 offset_expr
.X_add_symbol
, (offsetT
) 0,
5104 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5107 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5108 (int) BFD_RELOC_LO16
, tempreg
);
5112 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5113 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5119 ((bfd_arch_bits_per_address (stdoutput
) == 32
5120 || mips_opts
.isa
< 3)
5121 ? "addu" : "daddu"),
5122 "d,v,t", tempreg
, breg
, GP
);
5123 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5124 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5125 p
= frag_var (rs_machine_dependent
, 12, 0,
5126 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5127 offset_expr
.X_add_symbol
, (offsetT
) 0,
5130 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5133 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5134 ((bfd_arch_bits_per_address (stdoutput
) == 32
5135 || mips_opts
.isa
< 3)
5136 ? "addu" : "daddu"),
5137 "d,v,t", tempreg
, tempreg
, breg
);
5140 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5141 (int) BFD_RELOC_LO16
, tempreg
);
5144 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5146 /* If this is a reference to an external symbol, we want
5147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5149 <op> $treg,0($tempreg)
5151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5153 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5154 <op> $treg,0($tempreg)
5155 If there is a base register, we add it to $tempreg before
5156 the <op>. If there is a constant, we stick it in the
5157 <op> instruction. We don't handle constants larger than
5158 16 bits, because we have no way to load the upper 16 bits
5159 (actually, we could handle them for the subset of cases
5160 in which we are not using $at). */
5161 assert (offset_expr
.X_op
== O_symbol
);
5162 expr1
.X_add_number
= offset_expr
.X_add_number
;
5163 offset_expr
.X_add_number
= 0;
5164 if (expr1
.X_add_number
< -0x8000
5165 || expr1
.X_add_number
>= 0x8000)
5166 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5169 ((bfd_arch_bits_per_address (stdoutput
) == 32
5170 || mips_opts
.isa
< 3)
5172 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5174 p
= frag_var (rs_machine_dependent
, 4, 0,
5175 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5176 offset_expr
.X_add_symbol
, (offsetT
) 0,
5178 macro_build (p
, &icnt
, &offset_expr
,
5179 ((bfd_arch_bits_per_address (stdoutput
) == 32
5180 || mips_opts
.isa
< 3)
5181 ? "addiu" : "daddiu"),
5182 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5185 ((bfd_arch_bits_per_address (stdoutput
) == 32
5186 || mips_opts
.isa
< 3)
5187 ? "addu" : "daddu"),
5188 "d,v,t", tempreg
, tempreg
, breg
);
5189 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5190 (int) BFD_RELOC_LO16
, tempreg
);
5192 else if (mips_pic
== SVR4_PIC
)
5196 /* If this is a reference to an external symbol, we want
5197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5198 addu $tempreg,$tempreg,$gp
5199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5200 <op> $treg,0($tempreg)
5202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5204 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5205 <op> $treg,0($tempreg)
5206 If there is a base register, we add it to $tempreg before
5207 the <op>. If there is a constant, we stick it in the
5208 <op> instruction. We don't handle constants larger than
5209 16 bits, because we have no way to load the upper 16 bits
5210 (actually, we could handle them for the subset of cases
5211 in which we are not using $at). */
5212 assert (offset_expr
.X_op
== O_symbol
);
5213 expr1
.X_add_number
= offset_expr
.X_add_number
;
5214 offset_expr
.X_add_number
= 0;
5215 if (expr1
.X_add_number
< -0x8000
5216 || expr1
.X_add_number
>= 0x8000)
5217 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5218 if (reg_needs_delay (GP
))
5223 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5224 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5226 ((bfd_arch_bits_per_address (stdoutput
) == 32
5227 || mips_opts
.isa
< 3)
5228 ? "addu" : "daddu"),
5229 "d,v,t", tempreg
, tempreg
, GP
);
5230 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5231 ((bfd_arch_bits_per_address (stdoutput
) == 32
5232 || mips_opts
.isa
< 3)
5234 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5236 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5237 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5238 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5241 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5244 macro_build (p
, &icnt
, &offset_expr
,
5245 ((bfd_arch_bits_per_address (stdoutput
) == 32
5246 || mips_opts
.isa
< 3)
5248 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5250 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5252 macro_build (p
, &icnt
, &offset_expr
,
5253 ((bfd_arch_bits_per_address (stdoutput
) == 32
5254 || mips_opts
.isa
< 3)
5255 ? "addiu" : "daddiu"),
5256 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5259 ((bfd_arch_bits_per_address (stdoutput
) == 32
5260 || mips_opts
.isa
< 3)
5261 ? "addu" : "daddu"),
5262 "d,v,t", tempreg
, tempreg
, breg
);
5263 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5264 (int) BFD_RELOC_LO16
, tempreg
);
5266 else if (mips_pic
== EMBEDDED_PIC
)
5268 /* If there is no base register, we want
5269 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5270 If there is a base register, we want
5271 addu $tempreg,$breg,$gp
5272 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5274 assert (offset_expr
.X_op
== O_symbol
);
5277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5278 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5284 ((bfd_arch_bits_per_address (stdoutput
) == 32
5285 || mips_opts
.isa
< 3)
5286 ? "addu" : "daddu"),
5287 "d,v,t", tempreg
, breg
, GP
);
5288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5289 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5302 load_register (&icnt
, treg
, &imm_expr
, 0);
5306 load_register (&icnt
, treg
, &imm_expr
, 1);
5310 if (imm_expr
.X_op
== O_constant
)
5312 load_register (&icnt
, AT
, &imm_expr
, 0);
5313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5314 "mtc1", "t,G", AT
, treg
);
5319 assert (offset_expr
.X_op
== O_symbol
5320 && strcmp (segment_name (S_GET_SEGMENT
5321 (offset_expr
.X_add_symbol
)),
5323 && offset_expr
.X_add_number
== 0);
5324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5325 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5330 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5331 the entire value, and in mips1 mode it is the high order 32
5332 bits of the value and the low order 32 bits are either zero
5333 or in offset_expr. */
5334 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5336 if (mips_opts
.isa
>= 3)
5337 load_register (&icnt
, treg
, &imm_expr
, 1);
5342 if (target_big_endian
)
5354 load_register (&icnt
, hreg
, &imm_expr
, 0);
5357 if (offset_expr
.X_op
== O_absent
)
5358 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5362 assert (offset_expr
.X_op
== O_constant
);
5363 load_register (&icnt
, lreg
, &offset_expr
, 0);
5370 /* We know that sym is in the .rdata section. First we get the
5371 upper 16 bits of the address. */
5372 if (mips_pic
== NO_PIC
)
5374 /* FIXME: This won't work for a 64 bit address. */
5375 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5377 else if (mips_pic
== SVR4_PIC
)
5379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5380 ((bfd_arch_bits_per_address (stdoutput
) == 32
5381 || mips_opts
.isa
< 3)
5383 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5385 else if (mips_pic
== EMBEDDED_PIC
)
5387 /* For embedded PIC we pick up the entire address off $gp in
5388 a single instruction. */
5389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5390 ((bfd_arch_bits_per_address (stdoutput
) == 32
5391 || mips_opts
.isa
< 3)
5392 ? "addiu" : "daddiu"),
5393 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5394 offset_expr
.X_op
= O_constant
;
5395 offset_expr
.X_add_number
= 0;
5400 /* Now we load the register(s). */
5401 if (mips_opts
.isa
>= 3)
5402 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5403 treg
, (int) BFD_RELOC_LO16
, AT
);
5406 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5407 treg
, (int) BFD_RELOC_LO16
, AT
);
5410 /* FIXME: How in the world do we deal with the possible
5412 offset_expr
.X_add_number
+= 4;
5413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5414 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5418 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5419 does not become a variant frag. */
5420 frag_wane (frag_now
);
5426 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5427 the entire value, and in mips1 mode it is the high order 32
5428 bits of the value and the low order 32 bits are either zero
5429 or in offset_expr. */
5430 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5432 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5433 if (mips_opts
.isa
>= 3)
5434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5435 "dmtc1", "t,S", AT
, treg
);
5438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5439 "mtc1", "t,G", AT
, treg
+ 1);
5440 if (offset_expr
.X_op
== O_absent
)
5441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5442 "mtc1", "t,G", 0, treg
);
5445 assert (offset_expr
.X_op
== O_constant
);
5446 load_register (&icnt
, AT
, &offset_expr
, 0);
5447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5448 "mtc1", "t,G", AT
, treg
);
5454 assert (offset_expr
.X_op
== O_symbol
5455 && offset_expr
.X_add_number
== 0);
5456 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5457 if (strcmp (s
, ".lit8") == 0)
5459 if (mips_opts
.isa
>= 2)
5461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5462 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5466 r
= BFD_RELOC_MIPS_LITERAL
;
5471 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5472 if (mips_pic
== SVR4_PIC
)
5473 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5474 ((bfd_arch_bits_per_address (stdoutput
) == 32
5475 || mips_opts
.isa
< 3)
5477 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5480 /* FIXME: This won't work for a 64 bit address. */
5481 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5484 if (mips_opts
.isa
>= 2)
5486 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5487 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5489 /* To avoid confusion in tc_gen_reloc, we must ensure
5490 that this does not become a variant frag. */
5491 frag_wane (frag_now
);
5504 as_bad (_("opcode not supported on this processor"));
5507 /* Even on a big endian machine $fn comes before $fn+1. We have
5508 to adjust when loading from memory. */
5511 assert (mips_opts
.isa
< 2);
5512 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5513 target_big_endian
? treg
+ 1 : treg
,
5515 /* FIXME: A possible overflow which I don't know how to deal
5517 offset_expr
.X_add_number
+= 4;
5518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5519 target_big_endian
? treg
: treg
+ 1,
5522 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5523 does not become a variant frag. */
5524 frag_wane (frag_now
);
5533 * The MIPS assembler seems to check for X_add_number not
5534 * being double aligned and generating:
5537 * addiu at,at,%lo(foo+1)
5540 * But, the resulting address is the same after relocation so why
5541 * generate the extra instruction?
5545 as_bad (_("opcode not supported on this processor"));
5548 /* Itbl support may require additional care here. */
5550 if (mips_opts
.isa
>= 2)
5563 as_bad (_("opcode not supported on this processor"));
5567 if (mips_opts
.isa
>= 2)
5575 /* Itbl support may require additional care here. */
5580 if (mips_opts
.isa
>= 3)
5591 if (mips_opts
.isa
>= 3)
5601 if (offset_expr
.X_op
!= O_symbol
5602 && offset_expr
.X_op
!= O_constant
)
5604 as_bad (_("expression too complex"));
5605 offset_expr
.X_op
= O_constant
;
5608 /* Even on a big endian machine $fn comes before $fn+1. We have
5609 to adjust when loading from memory. We set coproc if we must
5610 load $fn+1 first. */
5611 /* Itbl support may require additional care here. */
5612 if (! target_big_endian
)
5615 if (mips_pic
== NO_PIC
5616 || offset_expr
.X_op
== O_constant
)
5618 /* If this is a reference to a GP relative symbol, we want
5619 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5620 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5621 If we have a base register, we use this
5623 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5624 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5625 If this is not a GP relative symbol, we want
5626 lui $at,<sym> (BFD_RELOC_HI16_S)
5627 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5628 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5629 If there is a base register, we add it to $at after the
5630 lui instruction. If there is a constant, we always use
5632 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5633 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5653 ((bfd_arch_bits_per_address (stdoutput
) == 32
5654 || mips_opts
.isa
< 3)
5655 ? "addu" : "daddu"),
5656 "d,v,t", AT
, breg
, GP
);
5662 /* Itbl support may require additional care here. */
5663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5664 coproc
? treg
+ 1 : treg
,
5665 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5666 offset_expr
.X_add_number
+= 4;
5668 /* Set mips_optimize to 2 to avoid inserting an
5670 hold_mips_optimize
= mips_optimize
;
5672 /* Itbl support may require additional care here. */
5673 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5674 coproc
? treg
: treg
+ 1,
5675 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5676 mips_optimize
= hold_mips_optimize
;
5678 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5679 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5680 used_at
&& mips_opts
.noat
),
5681 offset_expr
.X_add_symbol
, (offsetT
) 0,
5684 /* We just generated two relocs. When tc_gen_reloc
5685 handles this case, it will skip the first reloc and
5686 handle the second. The second reloc already has an
5687 extra addend of 4, which we added above. We must
5688 subtract it out, and then subtract another 4 to make
5689 the first reloc come out right. The second reloc
5690 will come out right because we are going to add 4 to
5691 offset_expr when we build its instruction below.
5693 If we have a symbol, then we don't want to include
5694 the offset, because it will wind up being included
5695 when we generate the reloc. */
5697 if (offset_expr
.X_op
== O_constant
)
5698 offset_expr
.X_add_number
-= 8;
5701 offset_expr
.X_add_number
= -4;
5702 offset_expr
.X_op
= O_constant
;
5705 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5710 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5711 ((bfd_arch_bits_per_address (stdoutput
) == 32
5712 || mips_opts
.isa
< 3)
5713 ? "addu" : "daddu"),
5714 "d,v,t", AT
, breg
, AT
);
5718 /* Itbl support may require additional care here. */
5719 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5720 coproc
? treg
+ 1 : treg
,
5721 (int) BFD_RELOC_LO16
, AT
);
5724 /* FIXME: How do we handle overflow here? */
5725 offset_expr
.X_add_number
+= 4;
5726 /* Itbl support may require additional care here. */
5727 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5728 coproc
? treg
: treg
+ 1,
5729 (int) BFD_RELOC_LO16
, AT
);
5731 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5735 /* If this is a reference to an external symbol, we want
5736 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5741 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5743 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5744 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5745 If there is a base register we add it to $at before the
5746 lwc1 instructions. If there is a constant we include it
5747 in the lwc1 instructions. */
5749 expr1
.X_add_number
= offset_expr
.X_add_number
;
5750 offset_expr
.X_add_number
= 0;
5751 if (expr1
.X_add_number
< -0x8000
5752 || expr1
.X_add_number
>= 0x8000 - 4)
5753 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5758 frag_grow (24 + off
);
5759 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5760 ((bfd_arch_bits_per_address (stdoutput
) == 32
5761 || mips_opts
.isa
< 3)
5763 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5767 ((bfd_arch_bits_per_address (stdoutput
) == 32
5768 || mips_opts
.isa
< 3)
5769 ? "addu" : "daddu"),
5770 "d,v,t", AT
, breg
, AT
);
5771 /* Itbl support may require additional care here. */
5772 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5773 coproc
? treg
+ 1 : treg
,
5774 (int) BFD_RELOC_LO16
, AT
);
5775 expr1
.X_add_number
+= 4;
5777 /* Set mips_optimize to 2 to avoid inserting an undesired
5779 hold_mips_optimize
= mips_optimize
;
5781 /* Itbl support may require additional care here. */
5782 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5783 coproc
? treg
: treg
+ 1,
5784 (int) BFD_RELOC_LO16
, AT
);
5785 mips_optimize
= hold_mips_optimize
;
5787 (void) frag_var (rs_machine_dependent
, 0, 0,
5788 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5789 offset_expr
.X_add_symbol
, (offsetT
) 0,
5792 else if (mips_pic
== SVR4_PIC
)
5796 /* If this is a reference to an external symbol, we want
5797 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5799 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5804 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5806 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5807 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5808 If there is a base register we add it to $at before the
5809 lwc1 instructions. If there is a constant we include it
5810 in the lwc1 instructions. */
5812 expr1
.X_add_number
= offset_expr
.X_add_number
;
5813 offset_expr
.X_add_number
= 0;
5814 if (expr1
.X_add_number
< -0x8000
5815 || expr1
.X_add_number
>= 0x8000 - 4)
5816 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5817 if (reg_needs_delay (GP
))
5826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5827 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5829 ((bfd_arch_bits_per_address (stdoutput
) == 32
5830 || mips_opts
.isa
< 3)
5831 ? "addu" : "daddu"),
5832 "d,v,t", AT
, AT
, GP
);
5833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5834 ((bfd_arch_bits_per_address (stdoutput
) == 32
5835 || mips_opts
.isa
< 3)
5837 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5840 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5841 ((bfd_arch_bits_per_address (stdoutput
) == 32
5842 || mips_opts
.isa
< 3)
5843 ? "addu" : "daddu"),
5844 "d,v,t", AT
, breg
, AT
);
5845 /* Itbl support may require additional care here. */
5846 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5847 coproc
? treg
+ 1 : treg
,
5848 (int) BFD_RELOC_LO16
, AT
);
5849 expr1
.X_add_number
+= 4;
5851 /* Set mips_optimize to 2 to avoid inserting an undesired
5853 hold_mips_optimize
= mips_optimize
;
5855 /* Itbl support may require additional care here. */
5856 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5857 coproc
? treg
: treg
+ 1,
5858 (int) BFD_RELOC_LO16
, AT
);
5859 mips_optimize
= hold_mips_optimize
;
5860 expr1
.X_add_number
-= 4;
5862 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5863 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5864 8 + gpdel
+ off
, 1, 0),
5865 offset_expr
.X_add_symbol
, (offsetT
) 0,
5869 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5872 macro_build (p
, &icnt
, &offset_expr
,
5873 ((bfd_arch_bits_per_address (stdoutput
) == 32
5874 || mips_opts
.isa
< 3)
5876 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5878 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5882 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5883 ((bfd_arch_bits_per_address (stdoutput
) == 32
5884 || mips_opts
.isa
< 3)
5885 ? "addu" : "daddu"),
5886 "d,v,t", AT
, breg
, AT
);
5889 /* Itbl support may require additional care here. */
5890 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5891 coproc
? treg
+ 1 : treg
,
5892 (int) BFD_RELOC_LO16
, AT
);
5894 expr1
.X_add_number
+= 4;
5896 /* Set mips_optimize to 2 to avoid inserting an undesired
5898 hold_mips_optimize
= mips_optimize
;
5900 /* Itbl support may require additional care here. */
5901 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5902 coproc
? treg
: treg
+ 1,
5903 (int) BFD_RELOC_LO16
, AT
);
5904 mips_optimize
= hold_mips_optimize
;
5906 else if (mips_pic
== EMBEDDED_PIC
)
5908 /* If there is no base register, we use
5909 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5910 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5911 If we have a base register, we use
5913 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5914 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5924 ((bfd_arch_bits_per_address (stdoutput
) == 32
5925 || mips_opts
.isa
< 3)
5926 ? "addu" : "daddu"),
5927 "d,v,t", AT
, breg
, GP
);
5932 /* Itbl support may require additional care here. */
5933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5934 coproc
? treg
+ 1 : treg
,
5935 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5936 offset_expr
.X_add_number
+= 4;
5937 /* Itbl support may require additional care here. */
5938 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5939 coproc
? treg
: treg
+ 1,
5940 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5956 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5958 (int) BFD_RELOC_LO16
, breg
);
5959 offset_expr
.X_add_number
+= 4;
5960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5961 (int) BFD_RELOC_LO16
, breg
);
5964 /* New code added to support COPZ instructions.
5965 This code builds table entries out of the macros in mip_opcodes.
5966 R4000 uses interlocks to handle coproc delays.
5967 Other chips (like the R3000) require nops to be inserted for delays.
5969 FIXME: Currently, we require that the user handle delays.
5970 In order to fill delay slots for non-interlocked chips,
5971 we must have a way to specify delays based on the coprocessor.
5972 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5973 What are the side-effects of the cop instruction?
5974 What cache support might we have and what are its effects?
5975 Both coprocessor & memory require delays. how long???
5976 What registers are read/set/modified?
5978 If an itbl is provided to interpret cop instructions,
5979 this knowledge can be encoded in the itbl spec. */
5993 /* For now we just do C (same as Cz). The parameter will be
5994 stored in insn_opcode by mips_ip. */
5995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5999 #ifdef LOSING_COMPILER
6001 /* Try and see if this is a new itbl instruction.
6002 This code builds table entries out of the macros in mip_opcodes.
6003 FIXME: For now we just assemble the expression and pass it's
6004 value along as a 32-bit immediate.
6005 We may want to have the assembler assemble this value,
6006 so that we gain the assembler's knowledge of delay slots,
6008 Would it be more efficient to use mask (id) here? */
6009 if (itbl_have_entries
6010 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6012 s
= ip
->insn_mo
->name
;
6014 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6015 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6022 as_warn (_("Macro used $at after \".set noat\""));
6027 struct mips_cl_insn
*ip
;
6029 register int treg
, sreg
, dreg
, breg
;
6045 bfd_reloc_code_real_type r
;
6048 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6049 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6050 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6051 mask
= ip
->insn_mo
->mask
;
6053 expr1
.X_op
= O_constant
;
6054 expr1
.X_op_symbol
= NULL
;
6055 expr1
.X_add_symbol
= NULL
;
6056 expr1
.X_add_number
= 1;
6060 #endif /* LOSING_COMPILER */
6065 macro_build ((char *) NULL
, &icnt
, NULL
,
6066 dbl
? "dmultu" : "multu",
6068 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6074 /* The MIPS assembler some times generates shifts and adds. I'm
6075 not trying to be that fancy. GCC should do this for us
6077 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6078 macro_build ((char *) NULL
, &icnt
, NULL
,
6079 dbl
? "dmult" : "mult",
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6094 mips_emit_delays (true);
6095 ++mips_opts
.noreorder
;
6096 mips_any_noreorder
= 1;
6098 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6099 macro_build ((char *) NULL
, &icnt
, NULL
,
6100 dbl
? "dmult" : "mult",
6101 "s,t", sreg
, imm
? AT
: treg
);
6102 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6103 macro_build ((char *) NULL
, &icnt
, NULL
,
6104 dbl
? "dsra32" : "sra",
6105 "d,w,<", dreg
, dreg
, 31);
6106 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6108 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6111 expr1
.X_add_number
= 8;
6112 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6113 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6114 /* start-sanitize-r5900 */
6116 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6118 /* end-sanitize-r5900 */
6119 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6121 --mips_opts
.noreorder
;
6122 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6135 mips_emit_delays (true);
6136 ++mips_opts
.noreorder
;
6137 mips_any_noreorder
= 1;
6139 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6140 macro_build ((char *) NULL
, &icnt
, NULL
,
6141 dbl
? "dmultu" : "multu",
6142 "s,t", sreg
, imm
? AT
: treg
);
6143 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6144 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6146 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6149 expr1
.X_add_number
= 8;
6150 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6151 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6152 /* start-sanitize-r5900 */
6154 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6156 /* end-sanitize-r5900 */
6157 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6159 --mips_opts
.noreorder
;
6163 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6164 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6165 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6167 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6171 if (imm_expr
.X_op
!= O_constant
)
6172 as_bad (_("rotate count too large"));
6173 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6174 (int) (imm_expr
.X_add_number
& 0x1f));
6175 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6176 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6181 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6182 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6183 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6185 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6189 if (imm_expr
.X_op
!= O_constant
)
6190 as_bad (_("rotate count too large"));
6191 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6192 (int) (imm_expr
.X_add_number
& 0x1f));
6193 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6194 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6195 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6201 as_bad (_("opcode not supported on this processor"));
6204 assert (mips_opts
.isa
< 2);
6205 /* Even on a big endian machine $fn comes before $fn+1. We have
6206 to adjust when storing to memory. */
6207 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6208 target_big_endian
? treg
+ 1 : treg
,
6209 (int) BFD_RELOC_LO16
, breg
);
6210 offset_expr
.X_add_number
+= 4;
6211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6212 target_big_endian
? treg
: treg
+ 1,
6213 (int) BFD_RELOC_LO16
, breg
);
6218 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6219 treg
, (int) BFD_RELOC_LO16
);
6221 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6222 sreg
, (int) BFD_RELOC_LO16
);
6225 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6227 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6228 dreg
, (int) BFD_RELOC_LO16
);
6233 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6235 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6236 sreg
, (int) BFD_RELOC_LO16
);
6241 as_warn (_("Instruction %s: result is always false"),
6243 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6246 if (imm_expr
.X_op
== O_constant
6247 && imm_expr
.X_add_number
>= 0
6248 && imm_expr
.X_add_number
< 0x10000)
6250 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6251 sreg
, (int) BFD_RELOC_LO16
);
6254 else if (imm_expr
.X_op
== O_constant
6255 && imm_expr
.X_add_number
> -0x8000
6256 && imm_expr
.X_add_number
< 0)
6258 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6259 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6260 ((bfd_arch_bits_per_address (stdoutput
) == 32
6261 || mips_opts
.isa
< 3)
6262 ? "addiu" : "daddiu"),
6263 "t,r,j", dreg
, sreg
,
6264 (int) BFD_RELOC_LO16
);
6269 load_register (&icnt
, AT
, &imm_expr
, 0);
6270 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6274 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6275 (int) BFD_RELOC_LO16
);
6280 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6286 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6287 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6288 (int) BFD_RELOC_LO16
);
6291 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6293 if (imm_expr
.X_op
== O_constant
6294 && imm_expr
.X_add_number
>= -0x8000
6295 && imm_expr
.X_add_number
< 0x8000)
6297 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6298 mask
== M_SGE_I
? "slti" : "sltiu",
6299 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6304 load_register (&icnt
, AT
, &imm_expr
, 0);
6305 macro_build ((char *) NULL
, &icnt
, NULL
,
6306 mask
== M_SGE_I
? "slt" : "sltu",
6307 "d,v,t", dreg
, sreg
, AT
);
6310 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6311 (int) BFD_RELOC_LO16
);
6316 case M_SGT
: /* sreg > treg <==> treg < sreg */
6322 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6325 case M_SGT_I
: /* sreg > I <==> I < sreg */
6331 load_register (&icnt
, AT
, &imm_expr
, 0);
6332 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6335 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6341 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6342 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6343 (int) BFD_RELOC_LO16
);
6346 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6352 load_register (&icnt
, AT
, &imm_expr
, 0);
6353 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6354 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6355 (int) BFD_RELOC_LO16
);
6359 if (imm_expr
.X_op
== O_constant
6360 && imm_expr
.X_add_number
>= -0x8000
6361 && imm_expr
.X_add_number
< 0x8000)
6363 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6364 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6367 load_register (&icnt
, AT
, &imm_expr
, 0);
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6372 if (imm_expr
.X_op
== O_constant
6373 && imm_expr
.X_add_number
>= -0x8000
6374 && imm_expr
.X_add_number
< 0x8000)
6376 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6377 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6380 load_register (&icnt
, AT
, &imm_expr
, 0);
6381 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6387 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6390 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6394 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6396 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6402 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6404 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6410 as_warn (_("Instruction %s: result is always true"),
6412 macro_build ((char *) NULL
, &icnt
, &expr1
,
6413 ((bfd_arch_bits_per_address (stdoutput
) == 32
6414 || mips_opts
.isa
< 3)
6415 ? "addiu" : "daddiu"),
6416 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6419 if (imm_expr
.X_op
== O_constant
6420 && imm_expr
.X_add_number
>= 0
6421 && imm_expr
.X_add_number
< 0x10000)
6423 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6424 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6427 else if (imm_expr
.X_op
== O_constant
6428 && imm_expr
.X_add_number
> -0x8000
6429 && imm_expr
.X_add_number
< 0)
6431 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6432 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6433 ((bfd_arch_bits_per_address (stdoutput
) == 32
6434 || mips_opts
.isa
< 3)
6435 ? "addiu" : "daddiu"),
6436 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6441 load_register (&icnt
, AT
, &imm_expr
, 0);
6442 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6446 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6454 if (imm_expr
.X_op
== O_constant
6455 && imm_expr
.X_add_number
> -0x8000
6456 && imm_expr
.X_add_number
<= 0x8000)
6458 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6459 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6460 dbl
? "daddi" : "addi",
6461 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6464 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6465 macro_build ((char *) NULL
, &icnt
, NULL
,
6466 dbl
? "dsub" : "sub",
6467 "d,v,t", dreg
, sreg
, AT
);
6473 if (imm_expr
.X_op
== O_constant
6474 && imm_expr
.X_add_number
> -0x8000
6475 && imm_expr
.X_add_number
<= 0x8000)
6477 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6478 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6479 dbl
? "daddiu" : "addiu",
6480 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6483 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6484 macro_build ((char *) NULL
, &icnt
, NULL
,
6485 dbl
? "dsubu" : "subu",
6486 "d,v,t", dreg
, sreg
, AT
);
6507 load_register (&icnt
, AT
, &imm_expr
, 0);
6508 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6513 assert (mips_opts
.isa
< 2);
6514 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6515 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6518 * Is the double cfc1 instruction a bug in the mips assembler;
6519 * or is there a reason for it?
6521 mips_emit_delays (true);
6522 ++mips_opts
.noreorder
;
6523 mips_any_noreorder
= 1;
6524 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6525 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6526 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6527 expr1
.X_add_number
= 3;
6528 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6529 (int) BFD_RELOC_LO16
);
6530 expr1
.X_add_number
= 2;
6531 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6532 (int) BFD_RELOC_LO16
);
6533 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6534 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6535 macro_build ((char *) NULL
, &icnt
, NULL
,
6536 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6537 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6538 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6539 --mips_opts
.noreorder
;
6548 if (offset_expr
.X_add_number
>= 0x7fff)
6549 as_bad (_("operand overflow"));
6550 /* avoid load delay */
6551 if (! target_big_endian
)
6552 offset_expr
.X_add_number
+= 1;
6553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, breg
);
6555 if (! target_big_endian
)
6556 offset_expr
.X_add_number
-= 1;
6558 offset_expr
.X_add_number
+= 1;
6559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6560 (int) BFD_RELOC_LO16
, breg
);
6561 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6562 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6575 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6576 as_bad (_("operand overflow"));
6577 if (! target_big_endian
)
6578 offset_expr
.X_add_number
+= off
;
6579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6580 (int) BFD_RELOC_LO16
, breg
);
6581 if (! target_big_endian
)
6582 offset_expr
.X_add_number
-= off
;
6584 offset_expr
.X_add_number
+= off
;
6585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6586 (int) BFD_RELOC_LO16
, breg
);
6599 load_address (&icnt
, AT
, &offset_expr
);
6601 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6602 ((bfd_arch_bits_per_address (stdoutput
) == 32
6603 || mips_opts
.isa
< 3)
6604 ? "addu" : "daddu"),
6605 "d,v,t", AT
, AT
, breg
);
6606 if (! target_big_endian
)
6607 expr1
.X_add_number
= off
;
6609 expr1
.X_add_number
= 0;
6610 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6611 (int) BFD_RELOC_LO16
, AT
);
6612 if (! target_big_endian
)
6613 expr1
.X_add_number
= 0;
6615 expr1
.X_add_number
= off
;
6616 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6617 (int) BFD_RELOC_LO16
, AT
);
6622 load_address (&icnt
, AT
, &offset_expr
);
6624 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6625 ((bfd_arch_bits_per_address (stdoutput
) == 32
6626 || mips_opts
.isa
< 3)
6627 ? "addu" : "daddu"),
6628 "d,v,t", AT
, AT
, breg
);
6629 if (target_big_endian
)
6630 expr1
.X_add_number
= 0;
6631 macro_build ((char *) NULL
, &icnt
, &expr1
,
6632 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6633 (int) BFD_RELOC_LO16
, AT
);
6634 if (target_big_endian
)
6635 expr1
.X_add_number
= 1;
6637 expr1
.X_add_number
= 0;
6638 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6639 (int) BFD_RELOC_LO16
, AT
);
6640 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6642 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6647 if (offset_expr
.X_add_number
>= 0x7fff)
6648 as_bad (_("operand overflow"));
6649 if (target_big_endian
)
6650 offset_expr
.X_add_number
+= 1;
6651 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6652 (int) BFD_RELOC_LO16
, breg
);
6653 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6654 if (target_big_endian
)
6655 offset_expr
.X_add_number
-= 1;
6657 offset_expr
.X_add_number
+= 1;
6658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6659 (int) BFD_RELOC_LO16
, breg
);
6672 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6673 as_bad (_("operand overflow"));
6674 if (! target_big_endian
)
6675 offset_expr
.X_add_number
+= off
;
6676 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6677 (int) BFD_RELOC_LO16
, breg
);
6678 if (! target_big_endian
)
6679 offset_expr
.X_add_number
-= off
;
6681 offset_expr
.X_add_number
+= off
;
6682 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6683 (int) BFD_RELOC_LO16
, breg
);
6696 load_address (&icnt
, AT
, &offset_expr
);
6698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6699 ((bfd_arch_bits_per_address (stdoutput
) == 32
6700 || mips_opts
.isa
< 3)
6701 ? "addu" : "daddu"),
6702 "d,v,t", AT
, AT
, breg
);
6703 if (! target_big_endian
)
6704 expr1
.X_add_number
= off
;
6706 expr1
.X_add_number
= 0;
6707 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6708 (int) BFD_RELOC_LO16
, AT
);
6709 if (! target_big_endian
)
6710 expr1
.X_add_number
= 0;
6712 expr1
.X_add_number
= off
;
6713 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6714 (int) BFD_RELOC_LO16
, AT
);
6718 load_address (&icnt
, AT
, &offset_expr
);
6720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6721 ((bfd_arch_bits_per_address (stdoutput
) == 32
6722 || mips_opts
.isa
< 3)
6723 ? "addu" : "daddu"),
6724 "d,v,t", AT
, AT
, breg
);
6725 if (! target_big_endian
)
6726 expr1
.X_add_number
= 0;
6727 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6728 (int) BFD_RELOC_LO16
, AT
);
6729 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6731 if (! target_big_endian
)
6732 expr1
.X_add_number
= 1;
6734 expr1
.X_add_number
= 0;
6735 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6736 (int) BFD_RELOC_LO16
, AT
);
6737 if (! target_big_endian
)
6738 expr1
.X_add_number
= 0;
6740 expr1
.X_add_number
= 1;
6741 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6742 (int) BFD_RELOC_LO16
, AT
);
6743 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6745 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6750 /* FIXME: Check if this is one of the itbl macros, since they
6751 are added dynamically. */
6752 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6756 as_warn (_("Macro used $at after \".set noat\""));
6759 /* Implement macros in mips16 mode. */
6763 struct mips_cl_insn
*ip
;
6766 int xreg
, yreg
, zreg
, tmp
;
6770 const char *s
, *s2
, *s3
;
6772 mask
= ip
->insn_mo
->mask
;
6774 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6775 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6776 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6780 expr1
.X_op
= O_constant
;
6781 expr1
.X_op_symbol
= NULL
;
6782 expr1
.X_add_symbol
= NULL
;
6783 expr1
.X_add_number
= 1;
6802 mips_emit_delays (true);
6803 ++mips_opts
.noreorder
;
6804 mips_any_noreorder
= 1;
6805 macro_build ((char *) NULL
, &icnt
, NULL
,
6806 dbl
? "ddiv" : "div",
6807 "0,x,y", xreg
, yreg
);
6808 expr1
.X_add_number
= 2;
6809 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6810 /* start-sanitize-r5900 */
6812 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6814 /* end-sanitize-r5900 */
6815 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6817 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6818 since that causes an overflow. We should do that as well,
6819 but I don't see how to do the comparisons without a temporary
6821 --mips_opts
.noreorder
;
6822 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6841 mips_emit_delays (true);
6842 ++mips_opts
.noreorder
;
6843 mips_any_noreorder
= 1;
6844 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6845 expr1
.X_add_number
= 2;
6846 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6847 /* start-sanitize-r5900 */
6849 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6851 /* end-sanitize-r5900 */
6852 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6853 --mips_opts
.noreorder
;
6854 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6860 macro_build ((char *) NULL
, &icnt
, NULL
,
6861 dbl
? "dmultu" : "multu",
6863 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6871 if (imm_expr
.X_op
!= O_constant
)
6872 as_bad (_("Unsupported large constant"));
6873 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6874 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6875 dbl
? "daddiu" : "addiu",
6876 "y,x,4", yreg
, xreg
);
6880 if (imm_expr
.X_op
!= O_constant
)
6881 as_bad (_("Unsupported large constant"));
6882 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6883 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6888 if (imm_expr
.X_op
!= O_constant
)
6889 as_bad (_("Unsupported large constant"));
6890 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6891 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6914 goto do_reverse_branch
;
6918 goto do_reverse_branch
;
6930 goto do_reverse_branch
;
6941 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6970 goto do_addone_branch_i
;
6975 goto do_addone_branch_i
;
6990 goto do_addone_branch_i
;
6997 if (imm_expr
.X_op
!= O_constant
)
6998 as_bad (_("Unsupported large constant"));
6999 ++imm_expr
.X_add_number
;
7002 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7007 expr1
.X_add_number
= 0;
7008 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7010 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7011 "move", "y,X", xreg
, yreg
);
7012 expr1
.X_add_number
= 2;
7013 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7015 "neg", "x,w", xreg
, xreg
);
7019 /* For consistency checking, verify that all bits are specified either
7020 by the match/mask part of the instruction definition, or by the
7023 validate_mips_insn (opc
)
7024 const struct mips_opcode
*opc
;
7026 const char *p
= opc
->args
;
7028 unsigned long used_bits
= opc
->mask
;
7030 if ((used_bits
& opc
->match
) != opc
->match
)
7032 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7033 opc
->name
, opc
->args
);
7036 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7043 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7044 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7046 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
7047 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7048 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7049 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7051 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7054 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7055 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7056 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7057 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7058 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7059 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7060 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7061 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7062 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7063 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7064 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7066 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7067 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7068 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7069 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7071 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7072 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7073 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7074 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7075 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7076 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7077 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7078 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7079 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7082 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7083 /* start-sanitize-r5900 */
7084 case '0': USE_BITS (OP_MASK_VADDI
, OP_SH_VADDI
); break;
7085 case '1': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7086 case '2': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7087 case '3': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7088 case '4': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7089 case '5': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7090 case '6': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7092 USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
);
7093 USE_BITS (OP_MASK_VUFTF
, OP_SH_VUFTF
);
7096 USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
);
7097 USE_BITS (OP_MASK_VUFSF
, OP_SH_VUFSF
);
7105 case 'O': USE_BITS (OP_MASK_VUCALLMS
, OP_SH_VUCALLMS
);break;
7106 case '&': USE_BITS (OP_MASK_VUDEST
, OP_SH_VUDEST
); break;
7113 /* end-sanitize-r5900 */
7114 /* start-sanitize-cygnus */
7115 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7116 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7119 /* end-sanitize-cygnus */
7121 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7122 c
, opc
->name
, opc
->args
);
7126 if (used_bits
!= 0xffffffff)
7128 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7129 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7135 /* This routine assembles an instruction into its binary format. As a
7136 side effect, it sets one of the global variables imm_reloc or
7137 offset_reloc to the type of relocation to do if one of the operands
7138 is an address expression. */
7143 struct mips_cl_insn
*ip
;
7148 struct mips_opcode
*insn
;
7151 unsigned int lastregno
= 0;
7154 int full_opcode_match
= 1;
7158 /* If the instruction contains a '.', we first try to match an instruction
7159 including the '.'. Then we try again without the '.'. */
7161 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
7164 /* If we stopped on whitespace, then replace the whitespace with null for
7165 the call to hash_find. Save the character we replaced just in case we
7166 have to re-parse the instruction. */
7173 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7175 /* If we didn't find the instruction in the opcode table, try again, but
7176 this time with just the instruction up to, but not including the
7180 /* Restore the character we overwrite above (if any). */
7184 /* Scan up to the first '.' or whitespace. */
7185 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7188 /* If we did not find a '.', then we can quit now. */
7191 insn_error
= "unrecognized opcode";
7195 /* Lookup the instruction in the hash table. */
7197 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7199 insn_error
= "unrecognized opcode";
7203 full_opcode_match
= 0;
7212 assert (strcmp (insn
->name
, str
) == 0);
7214 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7216 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7218 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7220 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7225 if (insn_isa
<= mips_opts
.isa
)
7227 else if (insn
->pinfo
== INSN_MACRO
)
7229 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7230 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7231 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7232 /* start-sanitize-vr4320 */
7233 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7234 /* end-sanitize-vr4320 */
7235 /* start-sanitize-tx49 */
7236 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7237 /* end-sanitize-tx49 */
7238 /* start-sanitize-r5900 */
7239 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7240 /* end-sanitize-r5900 */
7241 /* start-sanitize-cygnus */
7242 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7243 /* end-sanitize-cygnus */
7244 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7249 if (insn
->pinfo
!= INSN_MACRO
)
7251 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7253 /* start-sanitize-r5900 */
7254 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7256 /* end-sanitize-r5900 */
7261 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7262 && strcmp (insn
->name
, insn
[1].name
) == 0)
7268 || insn_isa
<= mips_opts
.isa
)
7269 insn_error
= _("opcode not supported on this processor");
7272 static char buf
[100];
7274 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7281 ip
->insn_opcode
= insn
->match
;
7282 for (args
= insn
->args
;; ++args
)
7288 case '\0': /* end of args */
7301 ip
->insn_opcode
|= lastregno
<< 21;
7306 ip
->insn_opcode
|= lastregno
<< 16;
7310 ip
->insn_opcode
|= lastregno
<< 11;
7316 /* Handle optional base register.
7317 Either the base register is omitted or
7318 we must have a left paren. */
7319 /* This is dependent on the next operand specifier
7320 is a base register specification. */
7321 assert (args
[1] == 'b' || args
[1] == '5'
7322 || args
[1] == '-' || args
[1] == '4');
7326 case ')': /* these must match exactly */
7327 /* start-sanitize-cygnus */
7330 /* end-sanitize-cygnus */
7331 /* start-sanitize-r5900 */
7334 /* end-sanitize-r5900 */
7339 case '<': /* must be at least one digit */
7341 * According to the manual, if the shift amount is greater
7342 * than 31 or less than 0 the the shift amount should be
7343 * mod 32. In reality the mips assembler issues an error.
7344 * We issue a warning and mask out all but the low 5 bits.
7346 my_getExpression (&imm_expr
, s
);
7347 check_absolute_expr (ip
, &imm_expr
);
7348 if ((unsigned long) imm_expr
.X_add_number
> 31)
7350 as_warn (_("Improper shift amount (%ld)"),
7351 (long) imm_expr
.X_add_number
);
7352 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7354 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7355 imm_expr
.X_op
= O_absent
;
7359 case '>': /* shift amount minus 32 */
7360 my_getExpression (&imm_expr
, s
);
7361 check_absolute_expr (ip
, &imm_expr
);
7362 if ((unsigned long) imm_expr
.X_add_number
< 32
7363 || (unsigned long) imm_expr
.X_add_number
> 63)
7365 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7366 imm_expr
.X_op
= O_absent
;
7370 /* start-sanitize-r5900 */
7371 case '0': /* 5 bit signed immediate at 6 */
7372 my_getExpression (&imm_expr
, s
);
7373 check_absolute_expr (ip
, &imm_expr
);
7374 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7375 || ((imm_expr
.X_add_number
< -16
7376 || imm_expr
.X_add_number
>= 16)
7377 && imm_expr
.X_op
== O_constant
))
7379 if (imm_expr
.X_op
!= O_constant
7380 && imm_expr
.X_op
!= O_big
)
7381 insn_error
= "absolute expression required";
7383 as_bad (_("5 bit expression not in range -16..15"));
7385 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7386 imm_expr
.X_op
= O_absent
;
7390 case '9': /* vi27 for vcallmsr */
7391 if (strncmp (s
, "$vi27", 5) == 0)
7393 else if (strncmp (s
, "vi27", 4) == 0)
7396 as_bad (_("expected vi27"));
7399 case '#': /* escape character */
7400 /* '#' specifies that we've got an optional suffix to this
7401 operand that must match exactly (if it exists). */
7402 if (*s
!= '\0' && *s
!= ','
7403 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7405 if (*s
== *(args
+ 1))
7416 case 'K': /* DEST operand completer (optional), must
7417 match previous dest if specified. */
7418 case '&': /* DEST instruction completer */
7419 case ';': /* DEST instruction completer, must be xyz */
7426 /* Parse the completer. */
7428 while ((!full_opcode_match
|| *args
== 'K')
7429 && *s
!= '\0' && *s
!= ' ' && *s
!= ',')
7441 insn_error
= "Invalid dest specification";
7450 /* Each completer can only appear once. */
7451 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7453 insn_error
= "Invalid dest specification";
7457 /* If this is the opcode completer, then we must insert
7458 the appropriate value into the insn. */
7461 /* Not strictly in the specs, but requested by users. */
7462 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7465 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7466 | (y
<< 23) | (z
<< 22));
7467 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7469 else if (*args
== ';')
7471 /* This implicitly has the .xyz completer. */
7472 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7475 if (w
!= 0 || x
!= 1 || y
!= 1 || z
!= 1)
7477 insn_error
= "Invalid dest specification";
7481 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7487 /* This is the operand completer, make sure it matches
7488 the previous opcode completer. */
7489 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7490 if (temp
&& temp
!= last_h
)
7492 insn_error
= "DEST field in operand does not match DEST field in instruction";
7501 case 'J': /* vu0 I register */
7505 insn_error
= "operand `I' expected";
7508 case 'Q': /* vu0 Q register */
7512 insn_error
= "operand `Q' expected";
7515 case 'X': /* vu0 R register */
7519 insn_error
= "operand `R' expected";
7522 case 'U': /* vu0 ACC register */
7523 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7526 insn_error
= "operand `ACC' expected";
7530 my_getSmallExpression (&imm_expr
, s
);
7531 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7534 /* end-sanitize-r5900 */
7536 case 'k': /* cache code */
7537 case 'h': /* prefx code */
7538 my_getExpression (&imm_expr
, s
);
7539 check_absolute_expr (ip
, &imm_expr
);
7540 if ((unsigned long) imm_expr
.X_add_number
> 31)
7542 as_warn (_("Invalid value for `%s' (%lu)"),
7544 (unsigned long) imm_expr
.X_add_number
);
7545 imm_expr
.X_add_number
&= 0x1f;
7548 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7550 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7551 imm_expr
.X_op
= O_absent
;
7555 case 'c': /* break code */
7556 my_getExpression (&imm_expr
, s
);
7557 check_absolute_expr (ip
, &imm_expr
);
7558 if ((unsigned) imm_expr
.X_add_number
> 1023)
7560 as_warn (_("Illegal break code (%ld)"),
7561 (long) imm_expr
.X_add_number
);
7562 imm_expr
.X_add_number
&= 0x3ff;
7564 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7565 imm_expr
.X_op
= O_absent
;
7569 case 'q': /* lower break code */
7570 my_getExpression (&imm_expr
, s
);
7571 check_absolute_expr (ip
, &imm_expr
);
7572 if ((unsigned) imm_expr
.X_add_number
> 1023)
7574 as_warn (_("Illegal lower break code (%ld)"),
7575 (long) imm_expr
.X_add_number
);
7576 imm_expr
.X_add_number
&= 0x3ff;
7578 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7579 imm_expr
.X_op
= O_absent
;
7583 case 'B': /* syscall code */
7584 my_getExpression (&imm_expr
, s
);
7585 check_absolute_expr (ip
, &imm_expr
);
7586 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7587 as_warn (_("Illegal syscall code (%ld)"),
7588 (long) imm_expr
.X_add_number
);
7589 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7590 imm_expr
.X_op
= O_absent
;
7594 case 'C': /* Coprocessor code */
7595 my_getExpression (&imm_expr
, s
);
7596 check_absolute_expr (ip
, &imm_expr
);
7597 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7599 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7600 (long) imm_expr
.X_add_number
);
7601 imm_expr
.X_add_number
&= ((1<<25) - 1);
7603 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7604 imm_expr
.X_op
= O_absent
;
7608 case 'P': /* Performance register */
7609 my_getExpression (&imm_expr
, s
);
7610 check_absolute_expr (ip
, &imm_expr
);
7611 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7613 as_warn (_("Invalidate performance regster (%ld)"),
7614 (long) imm_expr
.X_add_number
);
7615 imm_expr
.X_add_number
&= 1;
7617 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7618 imm_expr
.X_op
= O_absent
;
7622 case 'b': /* base register */
7623 case 'd': /* destination register */
7624 case 's': /* source register */
7625 case 't': /* target register */
7626 case 'r': /* both target and source */
7627 case 'v': /* both dest and source */
7628 case 'w': /* both dest and target */
7629 case 'E': /* coprocessor target register */
7630 case 'G': /* coprocessor destination register */
7631 case 'x': /* ignore register name */
7632 case 'z': /* must be zero register */
7636 /* start-sanitize-r5900 */
7637 /* Allow "$viNN" as coprocessor register name */
7645 /* end-sanitize-r5900 */
7657 while (isdigit (*s
));
7659 as_bad (_("Invalid register number (%d)"), regno
);
7661 else if (*args
== 'E' || *args
== 'G')
7665 if (s
[1] == 'f' && s
[2] == 'p')
7670 else if (s
[1] == 's' && s
[2] == 'p')
7675 else if (s
[1] == 'g' && s
[2] == 'p')
7680 else if (s
[1] == 'a' && s
[2] == 't')
7685 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7690 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7695 else if (itbl_have_entries
)
7700 p
= s
+1; /* advance past '$' */
7701 n
= itbl_get_field (&p
); /* n is name */
7703 /* See if this is a register defined in an
7705 r
= itbl_get_reg_val (n
);
7708 /* Get_field advances to the start of
7709 the next field, so we need to back
7710 rack to the end of the last field. */
7714 s
= strchr (s
,'\0');
7727 as_warn (_("Used $at without \".set noat\""));
7733 if (c
== 'r' || c
== 'v' || c
== 'w')
7740 /* 'z' only matches $0. */
7741 if (c
== 'z' && regno
!= 0)
7744 /* Now that we have assembled one operand, we use the args string
7745 * to figure out where it goes in the instruction. */
7752 ip
->insn_opcode
|= regno
<< 21;
7756 ip
->insn_opcode
|= regno
<< 11;
7761 ip
->insn_opcode
|= regno
<< 16;
7764 /* This case exists because on the r3000 trunc
7765 expands into a macro which requires a gp
7766 register. On the r6000 or r4000 it is
7767 assembled into a single instruction which
7768 ignores the register. Thus the insn version
7769 is MIPS_ISA2 and uses 'x', and the macro
7770 version is MIPS_ISA1 and uses 't'. */
7773 /* This case is for the div instruction, which
7774 acts differently if the destination argument
7775 is $0. This only matches $0, and is checked
7776 outside the switch. */
7779 /* Itbl operand; not yet implemented. FIXME ?? */
7781 /* What about all other operands like 'i', which
7782 can be specified in the opcode table? */
7792 ip
->insn_opcode
|= lastregno
<< 21;
7795 ip
->insn_opcode
|= lastregno
<< 16;
7800 case 'D': /* floating point destination register */
7801 case 'S': /* floating point source register */
7802 case 'T': /* floating point target register */
7803 case 'R': /* floating point source register */
7806 /* start-sanitize-r5900 */
7807 case '1': /* vu0 fp reg position 1 */
7808 case '2': /* vu0 fp reg position 2 */
7809 case '3': /* vu0 fp reg position 3 */
7810 case '4': /* vu0 int reg position 1 */
7811 case '5': /* vu0 int reg position 2 */
7812 case '6': /* vu0 int reg position 3 */
7813 case '7': /* vu0 fp reg with ftf modifier */
7814 case '8': /* vu0 fp reg with fsf modifier */
7815 /* end-sanitize-r5900 */
7817 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7827 while (isdigit (*s
));
7830 as_bad (_("Invalid float register number (%d)"), regno
);
7832 if ((regno
& 1) != 0
7833 && mips_opts
.isa
< 3
7834 && ! (strcmp (str
, "mtc1") == 0
7835 || strcmp (str
, "mfc1") == 0
7836 || strcmp (str
, "lwc1") == 0
7837 || strcmp (str
, "swc1") == 0
7838 || strcmp (str
, "l.s") == 0
7839 || strcmp (str
, "s.s") == 0))
7840 as_warn (_("Float register should be even, was %d"),
7848 if (c
== 'V' || c
== 'W')
7858 ip
->insn_opcode
|= regno
<< 6;
7862 ip
->insn_opcode
|= regno
<< 11;
7866 ip
->insn_opcode
|= regno
<< 16;
7869 ip
->insn_opcode
|= regno
<< 21;
7876 /* start-sanitize-r5900 */
7877 /* Handle vf and vi regsiters for vu0. Handle optional
7881 && (s
[1] == 'f' || s
[1] == 'i')
7886 && (s
[2] == 'f' || s
[2] == 'i')
7899 while (isdigit (*s
));
7902 as_bad (_("Invalid vu0 register number (%d)"), regno
);
7906 if (c
== '7' || c
== '8')
7915 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7920 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7925 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7930 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7933 as_bad (_("Invalid FSF/FTF specification"));
7941 if (c
== 'V' || c
== 'W')
7953 ip
->insn_opcode
|= regno
<< 16;
7958 ip
->insn_opcode
|= regno
<< 11;
7962 ip
->insn_opcode
|= regno
<< 6;
7968 /* end-sanitize-r5900 */
7973 ip
->insn_opcode
|= lastregno
<< 11;
7976 ip
->insn_opcode
|= lastregno
<< 16;
7982 my_getExpression (&imm_expr
, s
);
7983 if (imm_expr
.X_op
!= O_big
7984 && imm_expr
.X_op
!= O_constant
)
7985 insn_error
= _("absolute expression required");
7990 my_getExpression (&offset_expr
, s
);
7991 imm_reloc
= BFD_RELOC_32
;
8003 unsigned char temp
[8];
8005 unsigned int length
;
8010 /* These only appear as the last operand in an
8011 instruction, and every instruction that accepts
8012 them in any variant accepts them in all variants.
8013 This means we don't have to worry about backing out
8014 any changes if the instruction does not match.
8016 The difference between them is the size of the
8017 floating point constant and where it goes. For 'F'
8018 and 'L' the constant is 64 bits; for 'f' and 'l' it
8019 is 32 bits. Where the constant is placed is based
8020 on how the MIPS assembler does things:
8023 f -- immediate value
8026 The .lit4 and .lit8 sections are only used if
8027 permitted by the -G argument.
8029 When generating embedded PIC code, we use the
8030 .lit8 section but not the .lit4 section (we can do
8031 .lit4 inline easily; we need to put .lit8
8032 somewhere in the data segment, and using .lit8
8033 permits the linker to eventually combine identical
8036 f64
= *args
== 'F' || *args
== 'L';
8038 save_in
= input_line_pointer
;
8039 input_line_pointer
= s
;
8040 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8042 s
= input_line_pointer
;
8043 input_line_pointer
= save_in
;
8044 if (err
!= NULL
&& *err
!= '\0')
8046 as_bad (_("Bad floating point constant: %s"), err
);
8047 memset (temp
, '\0', sizeof temp
);
8048 length
= f64
? 8 : 4;
8051 assert (length
== (f64
? 8 : 4));
8055 && (! USE_GLOBAL_POINTER_OPT
8056 || mips_pic
== EMBEDDED_PIC
8057 || g_switch_value
< 4
8058 || (temp
[0] == 0 && temp
[1] == 0)
8059 || (temp
[2] == 0 && temp
[3] == 0))))
8061 imm_expr
.X_op
= O_constant
;
8062 if (! target_big_endian
)
8063 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8065 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8068 && ((temp
[0] == 0 && temp
[1] == 0)
8069 || (temp
[2] == 0 && temp
[3] == 0))
8070 && ((temp
[4] == 0 && temp
[5] == 0)
8071 || (temp
[6] == 0 && temp
[7] == 0)))
8073 /* The value is simple enough to load with a
8074 couple of instructions. In mips1 mode, set
8075 imm_expr to the high order 32 bits and
8076 offset_expr to the low order 32 bits.
8077 Otherwise, set imm_expr to the entire 64 bit
8079 if (mips_opts
.isa
< 3)
8081 imm_expr
.X_op
= O_constant
;
8082 offset_expr
.X_op
= O_constant
;
8083 if (! target_big_endian
)
8085 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8086 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8090 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8091 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8093 if (offset_expr
.X_add_number
== 0)
8094 offset_expr
.X_op
= O_absent
;
8096 else if (sizeof (imm_expr
.X_add_number
) > 4)
8098 imm_expr
.X_op
= O_constant
;
8099 if (! target_big_endian
)
8100 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8102 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8106 imm_expr
.X_op
= O_big
;
8107 imm_expr
.X_add_number
= 4;
8108 if (! target_big_endian
)
8110 generic_bignum
[0] = bfd_getl16 (temp
);
8111 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8112 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8113 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8117 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8118 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8119 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8120 generic_bignum
[3] = bfd_getb16 (temp
);
8126 const char *newname
;
8129 /* Switch to the right section. */
8131 subseg
= now_subseg
;
8134 default: /* unused default case avoids warnings. */
8136 newname
= RDATA_SECTION_NAME
;
8137 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8141 newname
= RDATA_SECTION_NAME
;
8144 assert (!USE_GLOBAL_POINTER_OPT
8145 || g_switch_value
>= 4);
8149 new_seg
= subseg_new (newname
, (subsegT
) 0);
8150 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8151 bfd_set_section_flags (stdoutput
, new_seg
,
8156 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8157 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8158 && strcmp (TARGET_OS
, "elf") != 0)
8159 record_alignment (new_seg
, 4);
8161 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8163 as_bad (_("Can't use floating point insn in this section"));
8165 /* Set the argument to the current address in the
8167 offset_expr
.X_op
= O_symbol
;
8168 offset_expr
.X_add_symbol
=
8169 symbol_new ("L0\001", now_seg
,
8170 (valueT
) frag_now_fix (), frag_now
);
8171 offset_expr
.X_add_number
= 0;
8173 /* Put the floating point number into the section. */
8174 p
= frag_more ((int) length
);
8175 memcpy (p
, temp
, length
);
8177 /* Switch back to the original section. */
8178 subseg_set (seg
, subseg
);
8183 case 'i': /* 16 bit unsigned immediate */
8184 case 'j': /* 16 bit signed immediate */
8185 imm_reloc
= BFD_RELOC_LO16
;
8186 c
= my_getSmallExpression (&imm_expr
, s
);
8191 if (imm_expr
.X_op
== O_constant
)
8192 imm_expr
.X_add_number
=
8193 (imm_expr
.X_add_number
>> 16) & 0xffff;
8196 imm_reloc
= BFD_RELOC_HI16_S
;
8197 imm_unmatched_hi
= true;
8200 imm_reloc
= BFD_RELOC_HI16
;
8202 else if (imm_expr
.X_op
== O_constant
)
8203 imm_expr
.X_add_number
&= 0xffff;
8207 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8208 || ((imm_expr
.X_add_number
< 0
8209 || imm_expr
.X_add_number
>= 0x10000)
8210 && imm_expr
.X_op
== O_constant
))
8212 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8213 !strcmp (insn
->name
, insn
[1].name
))
8215 if (imm_expr
.X_op
!= O_constant
8216 && imm_expr
.X_op
!= O_big
)
8217 insn_error
= _("absolute expression required");
8219 as_bad (_("16 bit expression not in range 0..65535"));
8227 /* The upper bound should be 0x8000, but
8228 unfortunately the MIPS assembler accepts numbers
8229 from 0x8000 to 0xffff and sign extends them, and
8230 we want to be compatible. We only permit this
8231 extended range for an instruction which does not
8232 provide any further alternates, since those
8233 alternates may handle other cases. People should
8234 use the numbers they mean, rather than relying on
8235 a mysterious sign extension. */
8236 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8237 strcmp (insn
->name
, insn
[1].name
) == 0);
8242 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8243 || ((imm_expr
.X_add_number
< -0x8000
8244 || imm_expr
.X_add_number
>= max
)
8245 && imm_expr
.X_op
== O_constant
)
8247 && imm_expr
.X_add_number
< 0
8248 && mips_opts
.isa
>= 3
8249 && imm_expr
.X_unsigned
8250 && sizeof (imm_expr
.X_add_number
) <= 4))
8254 if (imm_expr
.X_op
!= O_constant
8255 && imm_expr
.X_op
!= O_big
)
8256 insn_error
= _("absolute expression required");
8258 as_bad (_("16 bit expression not in range -32768..32767"));
8264 case 'o': /* 16 bit offset */
8265 c
= my_getSmallExpression (&offset_expr
, s
);
8267 /* If this value won't fit into a 16 bit offset, then go
8268 find a macro that will generate the 32 bit offset
8269 code pattern. As a special hack, we accept the
8270 difference of two local symbols as a constant. This
8271 is required to suppose embedded PIC switches, which
8272 use an instruction which looks like
8273 lw $4,$L12-$LS12($4)
8274 The problem with handling this in a more general
8275 fashion is that the macro function doesn't expect to
8276 see anything which can be handled in a single
8277 constant instruction. */
8279 && (offset_expr
.X_op
!= O_constant
8280 || offset_expr
.X_add_number
>= 0x8000
8281 || offset_expr
.X_add_number
< -0x8000)
8282 && (mips_pic
!= EMBEDDED_PIC
8283 || offset_expr
.X_op
!= O_subtract
8284 || now_seg
!= text_section
8285 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8289 offset_reloc
= BFD_RELOC_LO16
;
8290 if (c
== 'h' || c
== 'H')
8292 assert (offset_expr
.X_op
== O_constant
);
8293 offset_expr
.X_add_number
=
8294 (offset_expr
.X_add_number
>> 16) & 0xffff;
8299 case 'p': /* pc relative offset */
8300 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8301 my_getExpression (&offset_expr
, s
);
8305 case 'u': /* upper 16 bits */
8306 c
= my_getSmallExpression (&imm_expr
, s
);
8307 imm_reloc
= BFD_RELOC_LO16
;
8312 if (imm_expr
.X_op
== O_constant
)
8313 imm_expr
.X_add_number
=
8314 (imm_expr
.X_add_number
>> 16) & 0xffff;
8317 imm_reloc
= BFD_RELOC_HI16_S
;
8318 imm_unmatched_hi
= true;
8321 imm_reloc
= BFD_RELOC_HI16
;
8323 else if (imm_expr
.X_op
== O_constant
)
8324 imm_expr
.X_add_number
&= 0xffff;
8326 if (imm_expr
.X_op
== O_constant
8327 && (imm_expr
.X_add_number
< 0
8328 || imm_expr
.X_add_number
>= 0x10000))
8329 as_bad (_("lui expression not in range 0..65535"));
8333 case 'a': /* 26 bit address */
8334 my_getExpression (&offset_expr
, s
);
8336 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8339 case 'N': /* 3 bit branch condition code */
8340 case 'M': /* 3 bit compare condition code */
8341 if (strncmp (s
, "$fcc", 4) != 0)
8351 while (isdigit (*s
));
8353 as_bad (_("invalid condition code register $fcc%d"), regno
);
8355 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8357 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8360 /* start-sanitize-cygnus */
8361 case 'e': /* must be at least one digit */
8362 my_getExpression (&imm_expr
, s
);
8363 check_absolute_expr (ip
, &imm_expr
);
8364 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8366 as_bad (_("bad byte vector index (%ld)"),
8367 (long) imm_expr
.X_add_number
);
8368 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8370 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8371 imm_expr
.X_op
= O_absent
;
8376 my_getExpression (&imm_expr
, s
);
8377 check_absolute_expr (ip
, &imm_expr
);
8378 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8380 as_bad (_("bad byte vector index (%ld)"),
8381 (long) imm_expr
.X_add_number
);
8382 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8384 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8385 imm_expr
.X_op
= O_absent
;
8389 /* end-sanitize-cygnus */
8391 as_bad (_("bad char = '%c'\n"), *args
);
8396 /* Args don't match. */
8397 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8398 !strcmp (insn
->name
, insn
[1].name
))
8404 insn_error
= _("illegal operands");
8409 /* This routine assembles an instruction into its binary format when
8410 assembling for the mips16. As a side effect, it sets one of the
8411 global variables imm_reloc or offset_reloc to the type of
8412 relocation to do if one of the operands is an address expression.
8413 It also sets mips16_small and mips16_ext if the user explicitly
8414 requested a small or extended instruction. */
8419 struct mips_cl_insn
*ip
;
8423 struct mips_opcode
*insn
;
8426 unsigned int lastregno
= 0;
8431 mips16_small
= false;
8434 for (s
= str
; islower (*s
); ++s
)
8446 if (s
[1] == 't' && s
[2] == ' ')
8449 mips16_small
= true;
8453 else if (s
[1] == 'e' && s
[2] == ' ')
8462 insn_error
= _("unknown opcode");
8466 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8467 mips16_small
= true;
8469 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8471 insn_error
= _("unrecognized opcode");
8478 assert (strcmp (insn
->name
, str
) == 0);
8481 ip
->insn_opcode
= insn
->match
;
8482 ip
->use_extend
= false;
8483 imm_expr
.X_op
= O_absent
;
8484 imm_reloc
= BFD_RELOC_UNUSED
;
8485 offset_expr
.X_op
= O_absent
;
8486 offset_reloc
= BFD_RELOC_UNUSED
;
8487 for (args
= insn
->args
; 1; ++args
)
8494 /* In this switch statement we call break if we did not find
8495 a match, continue if we did find a match, or return if we
8504 /* Stuff the immediate value in now, if we can. */
8505 if (imm_expr
.X_op
== O_constant
8506 && imm_reloc
> BFD_RELOC_UNUSED
8507 && insn
->pinfo
!= INSN_MACRO
)
8509 mips16_immed ((char *) NULL
, 0,
8510 imm_reloc
- BFD_RELOC_UNUSED
,
8511 imm_expr
.X_add_number
, true, mips16_small
,
8512 mips16_ext
, &ip
->insn_opcode
,
8513 &ip
->use_extend
, &ip
->extend
);
8514 imm_expr
.X_op
= O_absent
;
8515 imm_reloc
= BFD_RELOC_UNUSED
;
8529 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8532 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8548 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8550 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8577 while (isdigit (*s
));
8580 as_bad (_("invalid register number (%d)"), regno
);
8586 if (s
[1] == 'f' && s
[2] == 'p')
8591 else if (s
[1] == 's' && s
[2] == 'p')
8596 else if (s
[1] == 'g' && s
[2] == 'p')
8601 else if (s
[1] == 'a' && s
[2] == 't')
8606 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8611 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8624 if (c
== 'v' || c
== 'w')
8626 regno
= mips16_to_32_reg_map
[lastregno
];
8640 regno
= mips32_to_16_reg_map
[regno
];
8645 regno
= ILLEGAL_REG
;
8650 regno
= ILLEGAL_REG
;
8655 regno
= ILLEGAL_REG
;
8660 if (regno
== AT
&& ! mips_opts
.noat
)
8661 as_warn (_("used $at without \".set noat\""));
8668 if (regno
== ILLEGAL_REG
)
8675 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8679 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8682 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8685 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8691 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8694 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8695 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8705 if (strncmp (s
, "$pc", 3) == 0)
8729 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8731 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8732 and generate the appropriate reloc. If the text
8733 inside %gprel is not a symbol name with an
8734 optional offset, then we generate a normal reloc
8735 and will probably fail later. */
8736 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8737 if (imm_expr
.X_op
== O_symbol
)
8740 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8742 ip
->use_extend
= true;
8749 /* Just pick up a normal expression. */
8750 my_getExpression (&imm_expr
, s
);
8753 if (imm_expr
.X_op
== O_register
)
8755 /* What we thought was an expression turned out to
8758 if (s
[0] == '(' && args
[1] == '(')
8760 /* It looks like the expression was omitted
8761 before a register indirection, which means
8762 that the expression is implicitly zero. We
8763 still set up imm_expr, so that we handle
8764 explicit extensions correctly. */
8765 imm_expr
.X_op
= O_constant
;
8766 imm_expr
.X_add_number
= 0;
8767 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8774 /* We need to relax this instruction. */
8775 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8784 /* We use offset_reloc rather than imm_reloc for the PC
8785 relative operands. This lets macros with both
8786 immediate and address operands work correctly. */
8787 my_getExpression (&offset_expr
, s
);
8789 if (offset_expr
.X_op
== O_register
)
8792 /* We need to relax this instruction. */
8793 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8797 case '6': /* break code */
8798 my_getExpression (&imm_expr
, s
);
8799 check_absolute_expr (ip
, &imm_expr
);
8800 if ((unsigned long) imm_expr
.X_add_number
> 63)
8802 as_warn (_("Invalid value for `%s' (%lu)"),
8804 (unsigned long) imm_expr
.X_add_number
);
8805 imm_expr
.X_add_number
&= 0x3f;
8807 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8808 imm_expr
.X_op
= O_absent
;
8812 case 'a': /* 26 bit address */
8813 my_getExpression (&offset_expr
, s
);
8815 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8816 ip
->insn_opcode
<<= 16;
8819 case 'l': /* register list for entry macro */
8820 case 'L': /* register list for exit macro */
8830 int freg
, reg1
, reg2
;
8832 while (*s
== ' ' || *s
== ',')
8836 as_bad (_("can't parse register list"));
8848 while (isdigit (*s
))
8870 as_bad (_("invalid register list"));
8875 while (isdigit (*s
))
8882 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8887 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8892 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8893 mask
|= (reg2
- 3) << 3;
8894 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8895 mask
|= (reg2
- 15) << 1;
8896 else if (reg1
== 31 && reg2
== 31)
8900 as_bad (_("invalid register list"));
8904 /* The mask is filled in in the opcode table for the
8905 benefit of the disassembler. We remove it before
8906 applying the actual mask. */
8907 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8908 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8912 case 'e': /* extend code */
8913 my_getExpression (&imm_expr
, s
);
8914 check_absolute_expr (ip
, &imm_expr
);
8915 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8917 as_warn (_("Invalid value for `%s' (%lu)"),
8919 (unsigned long) imm_expr
.X_add_number
);
8920 imm_expr
.X_add_number
&= 0x7ff;
8922 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8923 imm_expr
.X_op
= O_absent
;
8933 /* Args don't match. */
8934 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8935 strcmp (insn
->name
, insn
[1].name
) == 0)
8942 insn_error
= _("illegal operands");
8948 /* This structure holds information we know about a mips16 immediate
8951 struct mips16_immed_operand
8953 /* The type code used in the argument string in the opcode table. */
8955 /* The number of bits in the short form of the opcode. */
8957 /* The number of bits in the extended form of the opcode. */
8959 /* The amount by which the short form is shifted when it is used;
8960 for example, the sw instruction has a shift count of 2. */
8962 /* The amount by which the short form is shifted when it is stored
8963 into the instruction code. */
8965 /* Non-zero if the short form is unsigned. */
8967 /* Non-zero if the extended form is unsigned. */
8969 /* Non-zero if the value is PC relative. */
8973 /* The mips16 immediate operand types. */
8975 static const struct mips16_immed_operand mips16_immed_operands
[] =
8977 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8978 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8979 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8980 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8981 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8982 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8983 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8984 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8985 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8986 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8987 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8988 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8989 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8990 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8991 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8992 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8993 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8994 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8995 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8996 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8997 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9000 #define MIPS16_NUM_IMMED \
9001 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9003 /* Handle a mips16 instruction with an immediate value. This or's the
9004 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9005 whether an extended value is needed; if one is needed, it sets
9006 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9007 If SMALL is true, an unextended opcode was explicitly requested.
9008 If EXT is true, an extended opcode was explicitly requested. If
9009 WARN is true, warn if EXT does not match reality. */
9012 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9021 unsigned long *insn
;
9022 boolean
*use_extend
;
9023 unsigned short *extend
;
9025 register const struct mips16_immed_operand
*op
;
9026 int mintiny
, maxtiny
;
9029 op
= mips16_immed_operands
;
9030 while (op
->type
!= type
)
9033 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9038 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9041 maxtiny
= 1 << op
->nbits
;
9046 maxtiny
= (1 << op
->nbits
) - 1;
9051 mintiny
= - (1 << (op
->nbits
- 1));
9052 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9055 /* Branch offsets have an implicit 0 in the lowest bit. */
9056 if (type
== 'p' || type
== 'q')
9059 if ((val
& ((1 << op
->shift
) - 1)) != 0
9060 || val
< (mintiny
<< op
->shift
)
9061 || val
> (maxtiny
<< op
->shift
))
9066 if (warn
&& ext
&& ! needext
)
9067 as_warn_where (file
, line
, _("extended operand requested but not required"));
9068 if (small
&& needext
)
9069 as_bad_where (file
, line
, _("invalid unextended operand value"));
9071 if (small
|| (! ext
&& ! needext
))
9075 *use_extend
= false;
9076 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9077 insnval
<<= op
->op_shift
;
9082 long minext
, maxext
;
9088 maxext
= (1 << op
->extbits
) - 1;
9092 minext
= - (1 << (op
->extbits
- 1));
9093 maxext
= (1 << (op
->extbits
- 1)) - 1;
9095 if (val
< minext
|| val
> maxext
)
9096 as_bad_where (file
, line
,
9097 _("operand value out of range for instruction"));
9100 if (op
->extbits
== 16)
9102 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9105 else if (op
->extbits
== 15)
9107 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9112 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9116 *extend
= (unsigned short) extval
;
9125 my_getSmallExpression (ep
, str
)
9136 ((str
[1] == 'h' && str
[2] == 'i')
9137 || (str
[1] == 'H' && str
[2] == 'I')
9138 || (str
[1] == 'l' && str
[2] == 'o'))
9150 * A small expression may be followed by a base register.
9151 * Scan to the end of this operand, and then back over a possible
9152 * base register. Then scan the small expression up to that
9153 * point. (Based on code in sparc.c...)
9155 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
9157 if (sp
- 4 >= str
&& sp
[-1] == RP
)
9159 if (isdigit (sp
[-2]))
9161 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
9163 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
9169 else if (sp
- 5 >= str
9172 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
9173 || (sp
[-3] == 's' && sp
[-2] == 'p')
9174 || (sp
[-3] == 'g' && sp
[-2] == 'p')
9175 || (sp
[-3] == 'a' && sp
[-2] == 't')))
9181 /* no expression means zero offset */
9184 /* %xx(reg) is an error */
9185 ep
->X_op
= O_absent
;
9190 ep
->X_op
= O_constant
;
9193 ep
->X_add_symbol
= NULL
;
9194 ep
->X_op_symbol
= NULL
;
9195 ep
->X_add_number
= 0;
9200 my_getExpression (ep
, str
);
9207 my_getExpression (ep
, str
);
9208 return c
; /* => %hi or %lo encountered */
9212 my_getExpression (ep
, str
)
9218 save_in
= input_line_pointer
;
9219 input_line_pointer
= str
;
9221 expr_end
= input_line_pointer
;
9222 input_line_pointer
= save_in
;
9224 /* If we are in mips16 mode, and this is an expression based on `.',
9225 then we bump the value of the symbol by 1 since that is how other
9226 text symbols are handled. We don't bother to handle complex
9227 expressions, just `.' plus or minus a constant. */
9228 if (mips_opts
.mips16
9229 && ep
->X_op
== O_symbol
9230 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9231 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9232 && ep
->X_add_symbol
->sy_frag
== frag_now
9233 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
9234 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
9235 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
9238 /* Turn a string in input_line_pointer into a floating point constant
9239 of type type, and store the appropriate bytes in *litP. The number
9240 of LITTLENUMS emitted is stored in *sizeP . An error message is
9241 returned, or NULL on OK. */
9244 md_atof (type
, litP
, sizeP
)
9250 LITTLENUM_TYPE words
[4];
9266 return _("bad call to md_atof");
9269 t
= atof_ieee (input_line_pointer
, type
, words
);
9271 input_line_pointer
= t
;
9275 if (! target_big_endian
)
9277 for (i
= prec
- 1; i
>= 0; i
--)
9279 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9285 for (i
= 0; i
< prec
; i
++)
9287 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9296 md_number_to_chars (buf
, val
, n
)
9301 if (target_big_endian
)
9302 number_to_chars_bigendian (buf
, val
, n
);
9304 number_to_chars_littleendian (buf
, val
, n
);
9307 CONST
char *md_shortopts
= "O::g::G:";
9309 struct option md_longopts
[] = {
9310 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9311 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9312 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9313 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9314 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9315 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9316 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9317 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9318 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9319 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9320 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9321 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9322 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9323 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9324 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9325 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9326 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9327 {"break", no_argument
, NULL
, OPTION_BREAK
},
9328 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9329 #define OPTION_EB (OPTION_MD_BASE + 11)
9330 {"EB", no_argument
, NULL
, OPTION_EB
},
9331 #define OPTION_EL (OPTION_MD_BASE + 12)
9332 {"EL", no_argument
, NULL
, OPTION_EL
},
9333 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9334 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9335 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9336 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9337 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9338 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9339 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9340 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9341 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9342 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9343 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9344 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9345 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9346 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9347 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9348 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9349 /* start-sanitize-r5900 */
9350 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9351 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9352 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9353 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9354 /* end-sanitize-r5900 */
9355 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9356 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9357 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9358 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9360 /* start-sanitize-tx19 */
9361 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9362 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9363 /* end-sanitize-tx19 */
9365 /* start-sanitize-cygnus */
9366 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9367 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9368 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9369 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9371 /* end-sanitize-cygnus */
9372 /* start-sanitize-tx49 */
9373 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9374 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9375 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9376 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9378 /* end-sanitize-tx49 */
9379 /* start-sanitize-vr4320 */
9380 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9381 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9382 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9383 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9385 /* end-sanitize-vr4320 */
9386 /* start-sanitize-branchbug4011 */
9387 #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34)
9388 {"fix-4011-branch-bug", no_argument
, NULL
, OPTION_FIX_4011_BRANCH_BUG
},
9389 #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35)
9390 {"no-fix-4011-branch-bug", no_argument
, NULL
, OPTION_NO_FIX_4011_BRANCH_BUG
},
9391 /* end-sanitize-branchbug4011 */
9392 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9393 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9394 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9395 #define OPTION_32 (OPTION_MD_BASE + 20)
9396 #define OPTION_64 (OPTION_MD_BASE + 21)
9398 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9399 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9400 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9401 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9402 {"32", no_argument
, NULL
, OPTION_32
},
9403 {"64", no_argument
, NULL
, OPTION_64
},
9406 {NULL
, no_argument
, NULL
, 0}
9408 size_t md_longopts_size
= sizeof(md_longopts
);
9411 md_parse_option (c
, arg
)
9426 target_big_endian
= 1;
9430 target_big_endian
= 0;
9434 if (arg
&& arg
[1] == '0')
9444 mips_debug
= atoi (arg
);
9445 /* When the MIPS assembler sees -g or -g2, it does not do
9446 optimizations which limit full symbolic debugging. We take
9447 that to be equivalent to -O0. */
9448 if (mips_debug
== 2)
9472 /* Identify the processor type */
9474 if (strcmp (p
, "default") == 0
9475 || strcmp (p
, "DEFAULT") == 0)
9481 /* We need to cope with the various "vr" prefixes for the 4300
9483 if (*p
== 'v' || *p
== 'V')
9489 if (*p
== 'r' || *p
== 'R')
9496 if (strcmp (p
, "10000") == 0
9497 || strcmp (p
, "10k") == 0
9498 || strcmp (p
, "10K") == 0)
9500 /* start-sanitize-tx19 */
9501 else if (strcmp (p
, "1900") == 0)
9503 /* end-sanitize-tx19 */
9507 if (strcmp (p
, "2000") == 0
9508 || strcmp (p
, "2k") == 0
9509 || strcmp (p
, "2K") == 0)
9514 if (strcmp (p
, "3000") == 0
9515 || strcmp (p
, "3k") == 0
9516 || strcmp (p
, "3K") == 0)
9518 else if (strcmp (p
, "3900") == 0)
9523 if (strcmp (p
, "4000") == 0
9524 || strcmp (p
, "4k") == 0
9525 || strcmp (p
, "4K") == 0)
9527 else if (strcmp (p
, "4100") == 0)
9529 else if (strcmp (p
, "4300") == 0)
9531 /* start-sanitize-vr4320 */
9532 else if (strcmp (p
, "4320") == 0)
9534 /* end-sanitize-vr4320 */
9535 else if (strcmp (p
, "4400") == 0)
9537 else if (strcmp (p
, "4600") == 0)
9539 else if (strcmp (p
, "4650") == 0)
9541 /* start-sanitize-tx49 */
9542 else if (strcmp (p
, "4900") == 0)
9544 /* end-sanitize-tx49 */
9545 else if (strcmp (p
, "4010") == 0)
9550 if (strcmp (p
, "5000") == 0
9551 || strcmp (p
, "5k") == 0
9552 || strcmp (p
, "5K") == 0)
9554 /* start-sanitize-cygnus */
9555 else if (strcmp (p
, "5400") == 0)
9557 /* end-sanitize-cygnus */
9558 /* start-sanitize-r5900 */
9559 else if (strcmp (p
, "5900") == 0)
9561 /* end-sanitize-r5900 */
9565 if (strcmp (p
, "6000") == 0
9566 || strcmp (p
, "6k") == 0
9567 || strcmp (p
, "6K") == 0)
9572 if (strcmp (p
, "8000") == 0
9573 || strcmp (p
, "8k") == 0
9574 || strcmp (p
, "8K") == 0)
9579 if (strcmp (p
, "orion") == 0)
9585 && (mips_cpu
!= 4300
9587 /* start-sanitize-vr4320 */
9589 /* end-sanitize-vr4320 */
9590 /* start-sanitize-cygnus */
9592 /* end-sanitize-cygnus */
9593 && mips_cpu
!= 5000))
9595 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9601 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9612 case OPTION_NO_M4650
:
9620 case OPTION_NO_M4010
:
9628 case OPTION_NO_M4100
:
9632 /* start-sanitize-r5900 */
9637 case OPTION_NO_M5900
:
9640 /* end-sanitize-r5900 */
9642 /* start-sanitize-vr4320 */
9647 case OPTION_NO_M4320
:
9651 /* end-sanitize-vr4320 */
9652 /* start-sanitize-cygnus */
9657 case OPTION_NO_M5400
:
9661 /* end-sanitize-cygnus */
9666 case OPTION_NO_M3900
:
9670 /* start-sanitize-tx49 */
9675 case OPTION_NO_M4900
:
9679 /* end-sanitize-tx49 */
9681 mips_opts
.mips16
= 1;
9682 mips_no_prev_insn (false);
9685 case OPTION_NO_MIPS16
:
9686 mips_opts
.mips16
= 0;
9687 mips_no_prev_insn (false);
9690 case OPTION_MEMBEDDED_PIC
:
9691 mips_pic
= EMBEDDED_PIC
;
9692 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9694 as_bad (_("-G may not be used with embedded PIC code"));
9697 g_switch_value
= 0x7fffffff;
9700 /* When generating ELF code, we permit -KPIC and -call_shared to
9701 select SVR4_PIC, and -non_shared to select no PIC. This is
9702 intended to be compatible with Irix 5. */
9703 case OPTION_CALL_SHARED
:
9704 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9706 as_bad (_("-call_shared is supported only for ELF format"));
9709 mips_pic
= SVR4_PIC
;
9710 if (g_switch_seen
&& g_switch_value
!= 0)
9712 as_bad (_("-G may not be used with SVR4 PIC code"));
9718 case OPTION_NON_SHARED
:
9719 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9721 as_bad (_("-non_shared is supported only for ELF format"));
9727 /* The -xgot option tells the assembler to use 32 offsets when
9728 accessing the got in SVR4_PIC mode. It is for Irix
9735 if (! USE_GLOBAL_POINTER_OPT
)
9737 as_bad (_("-G is not supported for this configuration"));
9740 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9742 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9746 g_switch_value
= atoi (arg
);
9750 /* The -32 and -64 options tell the assembler to output the 32
9751 bit or the 64 bit MIPS ELF format. */
9758 const char **list
, **l
;
9760 list
= bfd_target_list ();
9761 for (l
= list
; *l
!= NULL
; l
++)
9762 if (strcmp (*l
, "elf64-bigmips") == 0
9763 || strcmp (*l
, "elf64-littlemips") == 0)
9766 as_fatal (_("No compiled in support for 64 bit object file format"));
9772 /* start-sanitize-branchbug4011 */
9773 case OPTION_FIX_4011_BRANCH_BUG
:
9774 mips_fix_4011_branch_bug
= 1;
9777 case OPTION_NO_FIX_4011_BRANCH_BUG
:
9778 mips_fix_4011_branch_bug
= 0;
9781 /* end-sanitize-branchbug4011 */
9790 md_show_usage (stream
)
9793 fprintf(stream
, _("\
9795 -membedded-pic generate embedded position independent code\n\
9796 -EB generate big endian output\n\
9797 -EL generate little endian output\n\
9798 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9799 -G NUM allow referencing objects up to NUM bytes\n\
9800 implicitly with the gp register [default 8]\n"));
9801 fprintf(stream
, _("\
9802 -mips1 generate MIPS ISA I instructions\n\
9803 -mips2 generate MIPS ISA II instructions\n\
9804 -mips3 generate MIPS ISA III instructions\n\
9805 -mips4 generate MIPS ISA IV instructions\n\
9806 -mcpu=vr4300 generate code for vr4300\n\
9807 -mcpu=vr4100 generate code for vr4100\n\
9808 -m4650 permit R4650 instructions\n\
9809 -no-m4650 do not permit R4650 instructions\n\
9810 -m4010 permit R4010 instructions\n\
9811 -no-m4010 do not permit R4010 instructions\n\
9812 -m4100 permit VR4100 instructions\n\
9813 -no-m4100 do not permit VR4100 instructions\n"));
9814 fprintf(stream
, _("\
9815 -mips16 generate mips16 instructions\n\
9816 -no-mips16 do not generate mips16 instructions\n"));
9817 fprintf(stream
, _("\
9818 -O0 remove unneeded NOPs, do not swap branches\n\
9819 -O remove unneeded NOPs and swap branches\n\
9820 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9821 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9823 fprintf(stream
, _("\
9824 -KPIC, -call_shared generate SVR4 position independent code\n\
9825 -non_shared do not generate position independent code\n\
9826 -xgot assume a 32 bit GOT\n\
9827 -32 create 32 bit object file (default)\n\
9828 -64 create 64 bit object file\n"));
9833 mips_init_after_args ()
9835 /* initialize opcodes */
9836 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9837 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9841 md_pcrel_from (fixP
)
9844 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9845 && fixP
->fx_addsy
!= (symbolS
*) NULL
9846 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9848 /* This makes a branch to an undefined symbol be a branch to the
9849 current location. */
9853 /* return the address of the delay slot */
9854 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9857 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9858 reloc for a cons. We could use the definition there, except that
9859 we want to handle 64 bit relocs specially. */
9862 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9865 unsigned int nbytes
;
9869 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9871 if (nbytes
== 8 && ! mips_64
)
9873 if (target_big_endian
)
9879 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9880 as_bad (_("Unsupported reloc size %d"), nbytes
);
9882 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9885 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9888 /* This is called before the symbol table is processed. In order to
9889 work with gcc when using mips-tfile, we must keep all local labels.
9890 However, in other cases, we want to discard them. If we were
9891 called with -g, but we didn't see any debugging information, it may
9892 mean that gcc is smuggling debugging information through to
9893 mips-tfile, in which case we must generate all local labels. */
9896 mips_frob_file_before_adjust ()
9898 #ifndef NO_ECOFF_DEBUGGING
9901 && ! ecoff_debugging_seen
)
9902 flag_keep_locals
= 1;
9906 /* Sort any unmatched HI16_S relocs so that they immediately precede
9907 the corresponding LO reloc. This is called before md_apply_fix and
9908 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9909 explicit use of the %hi modifier. */
9914 struct mips_hi_fixup
*l
;
9916 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9918 segment_info_type
*seginfo
;
9921 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9923 /* Check quickly whether the next fixup happens to be a matching
9925 if (l
->fixp
->fx_next
!= NULL
9926 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9927 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9928 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9931 /* Look through the fixups for this segment for a matching %lo.
9932 When we find one, move the %hi just in front of it. We do
9933 this in two passes. In the first pass, we try to find a
9934 unique %lo. In the second pass, we permit multiple %hi
9935 relocs for a single %lo (this is a GNU extension). */
9936 seginfo
= seg_info (l
->seg
);
9937 for (pass
= 0; pass
< 2; pass
++)
9942 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9944 /* Check whether this is a %lo fixup which matches l->fixp. */
9945 if (f
->fx_r_type
== BFD_RELOC_LO16
9946 && f
->fx_addsy
== l
->fixp
->fx_addsy
9947 && f
->fx_offset
== l
->fixp
->fx_offset
9950 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9951 || prev
->fx_addsy
!= f
->fx_addsy
9952 || prev
->fx_offset
!= f
->fx_offset
))
9956 /* Move l->fixp before f. */
9957 for (pf
= &seginfo
->fix_root
;
9959 pf
= &(*pf
)->fx_next
)
9960 assert (*pf
!= NULL
);
9962 *pf
= l
->fixp
->fx_next
;
9964 l
->fixp
->fx_next
= f
;
9966 seginfo
->fix_root
= l
->fixp
;
9968 prev
->fx_next
= l
->fixp
;
9980 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9981 _("Unmatched %%hi reloc"));
9986 /* When generating embedded PIC code we need to use a special
9987 relocation to represent the difference of two symbols in the .text
9988 section (switch tables use a difference of this sort). See
9989 include/coff/mips.h for details. This macro checks whether this
9990 fixup requires the special reloc. */
9991 #define SWITCH_TABLE(fixp) \
9992 ((fixp)->fx_r_type == BFD_RELOC_32 \
9993 && (fixp)->fx_addsy != NULL \
9994 && (fixp)->fx_subsy != NULL \
9995 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9996 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9998 /* When generating embedded PIC code we must keep all PC relative
9999 relocations, in case the linker has to relax a call. We also need
10000 to keep relocations for switch table entries. */
10004 mips_force_relocation (fixp
)
10007 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10008 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10011 return (mips_pic
== EMBEDDED_PIC
10013 || SWITCH_TABLE (fixp
)
10014 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10015 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10018 /* Apply a fixup to the object file. */
10021 md_apply_fix (fixP
, valueP
)
10025 unsigned char *buf
;
10028 assert (fixP
->fx_size
== 4
10029 || fixP
->fx_r_type
== BFD_RELOC_16
10030 || fixP
->fx_r_type
== BFD_RELOC_64
10031 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10032 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10036 /* If we aren't adjusting this fixup to be against the section
10037 symbol, we need to adjust the value. */
10039 if (fixP
->fx_addsy
!= NULL
10040 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
10041 && (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10042 || S_IS_WEAK (fixP
->fx_addsy
)))
10044 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10045 if (value
!= 0 && ! fixP
->fx_pcrel
)
10047 /* In this case, the bfd_install_relocation routine will
10048 incorrectly add the symbol value back in. We just want
10049 the addend to appear in the object file. */
10050 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10055 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10057 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10060 switch (fixP
->fx_r_type
)
10062 case BFD_RELOC_MIPS_JMP
:
10063 case BFD_RELOC_HI16
:
10064 case BFD_RELOC_HI16_S
:
10065 case BFD_RELOC_MIPS_GPREL
:
10066 case BFD_RELOC_MIPS_LITERAL
:
10067 case BFD_RELOC_MIPS_CALL16
:
10068 case BFD_RELOC_MIPS_GOT16
:
10069 case BFD_RELOC_MIPS_GPREL32
:
10070 case BFD_RELOC_MIPS_GOT_HI16
:
10071 case BFD_RELOC_MIPS_GOT_LO16
:
10072 case BFD_RELOC_MIPS_CALL_HI16
:
10073 case BFD_RELOC_MIPS_CALL_LO16
:
10074 case BFD_RELOC_MIPS16_GPREL
:
10075 /* start-sanitize-r5900 */
10076 case BFD_RELOC_MIPS15_S3
:
10077 /* end-sanitize-r5900 */
10078 if (fixP
->fx_pcrel
)
10079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10080 _("Invalid PC relative reloc"));
10081 /* Nothing needed to do. The value comes from the reloc entry */
10084 case BFD_RELOC_MIPS16_JMP
:
10085 /* We currently always generate a reloc against a symbol, which
10086 means that we don't want an addend even if the symbol is
10088 fixP
->fx_addnumber
= 0;
10091 case BFD_RELOC_PCREL_HI16_S
:
10092 /* The addend for this is tricky if it is internal, so we just
10093 do everything here rather than in bfd_install_relocation. */
10094 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10096 /* For an external symbol adjust by the address to make it
10097 pcrel_offset. We use the address of the RELLO reloc
10098 which follows this one. */
10099 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10100 + fixP
->fx_next
->fx_where
);
10102 if (value
& 0x8000)
10105 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10106 if (target_big_endian
)
10108 md_number_to_chars (buf
, value
, 2);
10111 case BFD_RELOC_PCREL_LO16
:
10112 /* The addend for this is tricky if it is internal, so we just
10113 do everything here rather than in bfd_install_relocation. */
10114 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10115 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10116 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10117 if (target_big_endian
)
10119 md_number_to_chars (buf
, value
, 2);
10123 /* This is handled like BFD_RELOC_32, but we output a sign
10124 extended value if we are only 32 bits. */
10126 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10128 if (8 <= sizeof (valueT
))
10129 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10136 w1
= w2
= fixP
->fx_where
;
10137 if (target_big_endian
)
10141 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10142 if ((value
& 0x80000000) != 0)
10146 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10152 /* If we are deleting this reloc entry, we must fill in the
10153 value now. This can happen if we have a .word which is not
10154 resolved when it appears but is later defined. We also need
10155 to fill in the value if this is an embedded PIC switch table
10158 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10159 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10164 /* If we are deleting this reloc entry, we must fill in the
10166 assert (fixP
->fx_size
== 2);
10168 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10172 case BFD_RELOC_LO16
:
10173 /* When handling an embedded PIC switch statement, we can wind
10174 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10177 if (value
< -0x8000 || value
> 0x7fff)
10178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10179 _("relocation overflow"));
10180 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10181 if (target_big_endian
)
10183 md_number_to_chars (buf
, value
, 2);
10187 case BFD_RELOC_16_PCREL_S2
:
10189 * We need to save the bits in the instruction since fixup_segment()
10190 * might be deleting the relocation entry (i.e., a branch within
10191 * the current segment).
10193 if ((value
& 0x3) != 0)
10194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10195 _("Branch to odd address (%lx)"), value
);
10198 /* update old instruction data */
10199 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10200 if (target_big_endian
)
10201 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10203 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10205 if (value
>= -0x8000 && value
< 0x8000)
10206 insn
|= value
& 0xffff;
10209 /* The branch offset is too large. If this is an
10210 unconditional branch, and we are not generating PIC code,
10211 we can convert it to an absolute jump instruction. */
10212 if (mips_pic
== NO_PIC
10214 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10215 && (fixP
->fx_frag
->fr_address
10216 < text_section
->vma
+ text_section
->_raw_size
)
10217 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10218 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10219 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10221 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10222 insn
= 0x0c000000; /* jal */
10224 insn
= 0x08000000; /* j */
10225 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10227 fixP
->fx_addsy
= section_symbol (text_section
);
10228 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10232 /* FIXME. It would be possible in principle to handle
10233 conditional branches which overflow. They could be
10234 transformed into a branch around a jump. This would
10235 require setting up variant frags for each different
10236 branch type. The native MIPS assembler attempts to
10237 handle these cases, but it appears to do it
10239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10240 _("Branch out of range"));
10244 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10247 case BFD_RELOC_VTABLE_INHERIT
:
10250 && !S_IS_DEFINED (fixP
->fx_addsy
)
10251 && !S_IS_WEAK (fixP
->fx_addsy
))
10252 S_SET_WEAK (fixP
->fx_addsy
);
10255 case BFD_RELOC_VTABLE_ENTRY
:
10271 const struct mips_opcode
*p
;
10272 int treg
, sreg
, dreg
, shamt
;
10277 for (i
= 0; i
< NUMOPCODES
; ++i
)
10279 p
= &mips_opcodes
[i
];
10280 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10282 printf ("%08lx %s\t", oc
, p
->name
);
10283 treg
= (oc
>> 16) & 0x1f;
10284 sreg
= (oc
>> 21) & 0x1f;
10285 dreg
= (oc
>> 11) & 0x1f;
10286 shamt
= (oc
>> 6) & 0x1f;
10288 for (args
= p
->args
;; ++args
)
10299 printf ("%c", *args
);
10303 assert (treg
== sreg
);
10304 printf ("$%d,$%d", treg
, sreg
);
10309 printf ("$%d", dreg
);
10314 printf ("$%d", treg
);
10318 printf ("0x%x", treg
);
10323 printf ("$%d", sreg
);
10327 printf ("0x%08lx", oc
& 0x1ffffff);
10334 printf ("%d", imm
);
10339 printf ("$%d", shamt
);
10350 printf (_("%08lx UNDEFINED\n"), oc
);
10361 name
= input_line_pointer
;
10362 c
= get_symbol_end ();
10363 p
= (symbolS
*) symbol_find_or_make (name
);
10364 *input_line_pointer
= c
;
10368 /* Align the current frag to a given power of two. The MIPS assembler
10369 also automatically adjusts any preceding label. */
10372 mips_align (to
, fill
, label
)
10377 mips_emit_delays (false);
10378 frag_align (to
, fill
, 0);
10379 record_alignment (now_seg
, to
);
10382 assert (S_GET_SEGMENT (label
) == now_seg
);
10383 label
->sy_frag
= frag_now
;
10384 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10388 /* Align to a given power of two. .align 0 turns off the automatic
10389 alignment used by the data creating pseudo-ops. */
10396 register long temp_fill
;
10397 long max_alignment
= 15;
10401 o Note that the assembler pulls down any immediately preceeding label
10402 to the aligned address.
10403 o It's not documented but auto alignment is reinstated by
10404 a .align pseudo instruction.
10405 o Note also that after auto alignment is turned off the mips assembler
10406 issues an error on attempt to assemble an improperly aligned data item.
10411 temp
= get_absolute_expression ();
10412 if (temp
> max_alignment
)
10413 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10416 as_warn (_("Alignment negative: 0 assumed."));
10419 if (*input_line_pointer
== ',')
10421 input_line_pointer
++;
10422 temp_fill
= get_absolute_expression ();
10429 mips_align (temp
, (int) temp_fill
,
10430 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10437 demand_empty_rest_of_line ();
10441 mips_flush_pending_output ()
10443 mips_emit_delays (false);
10444 mips_clear_insn_labels ();
10453 /* When generating embedded PIC code, we only use the .text, .lit8,
10454 .sdata and .sbss sections. We change the .data and .rdata
10455 pseudo-ops to use .sdata. */
10456 if (mips_pic
== EMBEDDED_PIC
10457 && (sec
== 'd' || sec
== 'r'))
10461 /* The ELF backend needs to know that we are changing sections, so
10462 that .previous works correctly. We could do something like check
10463 for a obj_section_change_hook macro, but that might be confusing
10464 as it would not be appropriate to use it in the section changing
10465 functions in read.c, since obj-elf.c intercepts those. FIXME:
10466 This should be cleaner, somehow. */
10467 obj_elf_section_change_hook ();
10470 mips_emit_delays (false);
10480 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10481 demand_empty_rest_of_line ();
10485 if (USE_GLOBAL_POINTER_OPT
)
10487 seg
= subseg_new (RDATA_SECTION_NAME
,
10488 (subsegT
) get_absolute_expression ());
10489 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10491 bfd_set_section_flags (stdoutput
, seg
,
10497 if (strcmp (TARGET_OS
, "elf") != 0)
10498 bfd_set_section_alignment (stdoutput
, seg
, 4);
10500 demand_empty_rest_of_line ();
10504 as_bad (_("No read only data section in this object file format"));
10505 demand_empty_rest_of_line ();
10511 if (USE_GLOBAL_POINTER_OPT
)
10513 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10514 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10516 bfd_set_section_flags (stdoutput
, seg
,
10517 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10519 if (strcmp (TARGET_OS
, "elf") != 0)
10520 bfd_set_section_alignment (stdoutput
, seg
, 4);
10522 demand_empty_rest_of_line ();
10527 as_bad (_("Global pointers not supported; recompile -G 0"));
10528 demand_empty_rest_of_line ();
10537 mips_enable_auto_align ()
10548 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10549 mips_emit_delays (false);
10550 if (log_size
> 0 && auto_align
)
10551 mips_align (log_size
, 0, label
);
10552 mips_clear_insn_labels ();
10553 cons (1 << log_size
);
10557 s_float_cons (type
)
10562 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10564 mips_emit_delays (false);
10568 mips_align (3, 0, label
);
10570 mips_align (2, 0, label
);
10572 mips_clear_insn_labels ();
10577 /* Handle .globl. We need to override it because on Irix 5 you are
10580 where foo is an undefined symbol, to mean that foo should be
10581 considered to be the address of a function. */
10592 name
= input_line_pointer
;
10593 c
= get_symbol_end ();
10594 symbolP
= symbol_find_or_make (name
);
10595 *input_line_pointer
= c
;
10596 SKIP_WHITESPACE ();
10598 /* On Irix 5, every global symbol that is not explicitly labelled as
10599 being a function is apparently labelled as being an object. */
10602 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10607 secname
= input_line_pointer
;
10608 c
= get_symbol_end ();
10609 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10611 as_bad (_("%s: no such section"), secname
);
10612 *input_line_pointer
= c
;
10614 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10615 flag
= BSF_FUNCTION
;
10618 symbolP
->bsym
->flags
|= flag
;
10620 S_SET_EXTERNAL (symbolP
);
10621 demand_empty_rest_of_line ();
10631 opt
= input_line_pointer
;
10632 c
= get_symbol_end ();
10636 /* FIXME: What does this mean? */
10638 else if (strncmp (opt
, "pic", 3) == 0)
10642 i
= atoi (opt
+ 3);
10646 mips_pic
= SVR4_PIC
;
10648 as_bad (_(".option pic%d not supported"), i
);
10650 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10652 if (g_switch_seen
&& g_switch_value
!= 0)
10653 as_warn (_("-G may not be used with SVR4 PIC code"));
10654 g_switch_value
= 0;
10655 bfd_set_gp_size (stdoutput
, 0);
10659 as_warn (_("Unrecognized option \"%s\""), opt
);
10661 *input_line_pointer
= c
;
10662 demand_empty_rest_of_line ();
10665 /* This structure is used to hold a stack of .set values. */
10667 struct mips_option_stack
10669 struct mips_option_stack
*next
;
10670 struct mips_set_options options
;
10673 static struct mips_option_stack
*mips_opts_stack
;
10675 /* Handle the .set pseudo-op. */
10681 char *name
= input_line_pointer
, ch
;
10683 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10684 input_line_pointer
++;
10685 ch
= *input_line_pointer
;
10686 *input_line_pointer
= '\0';
10688 if (strcmp (name
, "reorder") == 0)
10690 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10692 /* If we still have pending nops, we can discard them. The
10693 usual nop handling will insert any that are still
10695 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10696 * (mips_opts
.mips16
? 2 : 4));
10697 prev_nop_frag
= NULL
;
10699 mips_opts
.noreorder
= 0;
10701 else if (strcmp (name
, "noreorder") == 0)
10703 mips_emit_delays (true);
10704 mips_opts
.noreorder
= 1;
10705 mips_any_noreorder
= 1;
10707 else if (strcmp (name
, "at") == 0)
10709 mips_opts
.noat
= 0;
10711 else if (strcmp (name
, "noat") == 0)
10713 mips_opts
.noat
= 1;
10715 else if (strcmp (name
, "macro") == 0)
10717 mips_opts
.warn_about_macros
= 0;
10719 else if (strcmp (name
, "nomacro") == 0)
10721 if (mips_opts
.noreorder
== 0)
10722 as_bad (_("`noreorder' must be set before `nomacro'"));
10723 mips_opts
.warn_about_macros
= 1;
10725 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10727 mips_opts
.nomove
= 0;
10729 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10731 mips_opts
.nomove
= 1;
10733 else if (strcmp (name
, "bopt") == 0)
10735 mips_opts
.nobopt
= 0;
10737 else if (strcmp (name
, "nobopt") == 0)
10739 mips_opts
.nobopt
= 1;
10741 else if (strcmp (name
, "mips16") == 0
10742 || strcmp (name
, "MIPS-16") == 0)
10743 mips_opts
.mips16
= 1;
10744 else if (strcmp (name
, "nomips16") == 0
10745 || strcmp (name
, "noMIPS-16") == 0)
10746 mips_opts
.mips16
= 0;
10747 else if (strncmp (name
, "mips", 4) == 0)
10751 /* Permit the user to change the ISA on the fly. Needless to
10752 say, misuse can cause serious problems. */
10753 isa
= atoi (name
+ 4);
10755 mips_opts
.isa
= file_mips_isa
;
10756 else if (isa
< 1 || isa
> 4)
10757 as_bad (_("unknown ISA level"));
10759 mips_opts
.isa
= isa
;
10761 else if (strcmp (name
, "autoextend") == 0)
10762 mips_opts
.noautoextend
= 0;
10763 else if (strcmp (name
, "noautoextend") == 0)
10764 mips_opts
.noautoextend
= 1;
10765 else if (strcmp (name
, "push") == 0)
10767 struct mips_option_stack
*s
;
10769 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10770 s
->next
= mips_opts_stack
;
10771 s
->options
= mips_opts
;
10772 mips_opts_stack
= s
;
10774 else if (strcmp (name
, "pop") == 0)
10776 struct mips_option_stack
*s
;
10778 s
= mips_opts_stack
;
10780 as_bad (_(".set pop with no .set push"));
10783 /* If we're changing the reorder mode we need to handle
10784 delay slots correctly. */
10785 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10786 mips_emit_delays (true);
10787 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10789 if (prev_nop_frag
!= NULL
)
10791 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10792 * (mips_opts
.mips16
? 2 : 4));
10793 prev_nop_frag
= NULL
;
10797 mips_opts
= s
->options
;
10798 mips_opts_stack
= s
->next
;
10804 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10806 *input_line_pointer
= ch
;
10807 demand_empty_rest_of_line ();
10810 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10811 .option pic2. It means to generate SVR4 PIC calls. */
10814 s_abicalls (ignore
)
10817 mips_pic
= SVR4_PIC
;
10818 if (USE_GLOBAL_POINTER_OPT
)
10820 if (g_switch_seen
&& g_switch_value
!= 0)
10821 as_warn (_("-G may not be used with SVR4 PIC code"));
10822 g_switch_value
= 0;
10824 bfd_set_gp_size (stdoutput
, 0);
10825 demand_empty_rest_of_line ();
10828 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10829 PIC code. It sets the $gp register for the function based on the
10830 function address, which is in the register named in the argument.
10831 This uses a relocation against _gp_disp, which is handled specially
10832 by the linker. The result is:
10833 lui $gp,%hi(_gp_disp)
10834 addiu $gp,$gp,%lo(_gp_disp)
10835 addu $gp,$gp,.cpload argument
10836 The .cpload argument is normally $25 == $t9. */
10845 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10846 if (mips_pic
!= SVR4_PIC
)
10852 /* .cpload should be a in .set noreorder section. */
10853 if (mips_opts
.noreorder
== 0)
10854 as_warn (_(".cpload not in noreorder section"));
10856 ex
.X_op
= O_symbol
;
10857 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10858 ex
.X_op_symbol
= NULL
;
10859 ex
.X_add_number
= 0;
10861 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10862 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10864 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10865 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10866 (int) BFD_RELOC_LO16
);
10868 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10869 GP
, GP
, tc_get_register (0));
10871 demand_empty_rest_of_line ();
10874 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10875 offset from $sp. The offset is remembered, and after making a PIC
10876 call $gp is restored from that location. */
10879 s_cprestore (ignore
)
10885 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10886 if (mips_pic
!= SVR4_PIC
)
10892 mips_cprestore_offset
= get_absolute_expression ();
10894 ex
.X_op
= O_constant
;
10895 ex
.X_add_symbol
= NULL
;
10896 ex
.X_op_symbol
= NULL
;
10897 ex
.X_add_number
= mips_cprestore_offset
;
10899 macro_build ((char *) NULL
, &icnt
, &ex
,
10900 ((bfd_arch_bits_per_address (stdoutput
) == 32
10901 || mips_opts
.isa
< 3)
10903 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10905 demand_empty_rest_of_line ();
10908 /* Handle the .gpword pseudo-op. This is used when generating PIC
10909 code. It generates a 32 bit GP relative reloc. */
10919 /* When not generating PIC code, this is treated as .word. */
10920 if (mips_pic
!= SVR4_PIC
)
10926 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10927 mips_emit_delays (true);
10929 mips_align (2, 0, label
);
10930 mips_clear_insn_labels ();
10934 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10936 as_bad (_("Unsupported use of .gpword"));
10937 ignore_rest_of_line ();
10941 md_number_to_chars (p
, (valueT
) 0, 4);
10942 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10943 BFD_RELOC_MIPS_GPREL32
);
10945 demand_empty_rest_of_line ();
10948 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10949 tables in SVR4 PIC code. */
10958 /* This is ignored when not generating SVR4 PIC code. */
10959 if (mips_pic
!= SVR4_PIC
)
10965 /* Add $gp to the register named as an argument. */
10966 reg
= tc_get_register (0);
10967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10968 ((bfd_arch_bits_per_address (stdoutput
) == 32
10969 || mips_opts
.isa
< 3)
10970 ? "addu" : "daddu"),
10971 "d,v,t", reg
, reg
, GP
);
10973 demand_empty_rest_of_line ();
10976 /* Handle the .insn pseudo-op. This marks instruction labels in
10977 mips16 mode. This permits the linker to handle them specially,
10978 such as generating jalx instructions when needed. We also make
10979 them odd for the duration of the assembly, in order to generate the
10980 right sort of code. We will make them even in the adjust_symtab
10981 routine, while leaving them marked. This is convenient for the
10982 debugger and the disassembler. The linker knows to make them odd
10989 if (mips_opts
.mips16
)
10990 mips16_mark_labels ();
10992 demand_empty_rest_of_line ();
10995 /* Handle a .stabn directive. We need these in order to mark a label
10996 as being a mips16 text label correctly. Sometimes the compiler
10997 will emit a label, followed by a .stabn, and then switch sections.
10998 If the label and .stabn are in mips16 mode, then the label is
10999 really a mips16 text label. */
11005 if (type
== 'n' && mips_opts
.mips16
)
11006 mips16_mark_labels ();
11011 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11015 s_mips_weakext (ignore
)
11023 name
= input_line_pointer
;
11024 c
= get_symbol_end ();
11025 symbolP
= symbol_find_or_make (name
);
11026 S_SET_WEAK (symbolP
);
11027 *input_line_pointer
= c
;
11029 SKIP_WHITESPACE ();
11031 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11033 if (S_IS_DEFINED (symbolP
))
11035 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11036 S_GET_NAME (symbolP
));
11037 ignore_rest_of_line ();
11041 if (*input_line_pointer
== ',')
11043 ++input_line_pointer
;
11044 SKIP_WHITESPACE ();
11048 if (exp
.X_op
!= O_symbol
)
11050 as_bad ("bad .weakext directive");
11051 ignore_rest_of_line();
11054 symbolP
->sy_value
= exp
;
11057 demand_empty_rest_of_line ();
11060 /* Parse a register string into a number. Called from the ECOFF code
11061 to parse .frame. The argument is non-zero if this is the frame
11062 register, so that we can record it in mips_frame_reg. */
11065 tc_get_register (frame
)
11070 SKIP_WHITESPACE ();
11071 if (*input_line_pointer
++ != '$')
11073 as_warn (_("expected `$'"));
11076 else if (isdigit ((unsigned char) *input_line_pointer
))
11078 reg
= get_absolute_expression ();
11079 if (reg
< 0 || reg
>= 32)
11081 as_warn (_("Bad register number"));
11087 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11089 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11091 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11093 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11097 as_warn (_("Unrecognized register name"));
11100 input_line_pointer
+= 2;
11103 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11108 md_section_align (seg
, addr
)
11112 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11115 /* We don't need to align ELF sections to the full alignment.
11116 However, Irix 5 may prefer that we align them at least to a 16
11117 byte boundary. We don't bother to align the sections if we are
11118 targeted for an embedded system. */
11119 if (strcmp (TARGET_OS
, "elf") == 0)
11125 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11128 /* Utility routine, called from above as well. If called while the
11129 input file is still being read, it's only an approximation. (For
11130 example, a symbol may later become defined which appeared to be
11131 undefined earlier.) */
11134 nopic_need_relax (sym
, before_relaxing
)
11136 int before_relaxing
;
11141 if (USE_GLOBAL_POINTER_OPT
)
11143 const char *symname
;
11146 /* Find out whether this symbol can be referenced off the GP
11147 register. It can be if it is smaller than the -G size or if
11148 it is in the .sdata or .sbss section. Certain symbols can
11149 not be referenced off the GP, although it appears as though
11151 symname
= S_GET_NAME (sym
);
11152 if (symname
!= (const char *) NULL
11153 && (strcmp (symname
, "eprol") == 0
11154 || strcmp (symname
, "etext") == 0
11155 || strcmp (symname
, "_gp") == 0
11156 || strcmp (symname
, "edata") == 0
11157 || strcmp (symname
, "_fbss") == 0
11158 || strcmp (symname
, "_fdata") == 0
11159 || strcmp (symname
, "_ftext") == 0
11160 || strcmp (symname
, "end") == 0
11161 || strcmp (symname
, "_gp_disp") == 0))
11163 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11165 #ifndef NO_ECOFF_DEBUGGING
11166 || (sym
->ecoff_extern_size
!= 0
11167 && sym
->ecoff_extern_size
<= g_switch_value
)
11169 /* We must defer this decision until after the whole
11170 file has been read, since there might be a .extern
11171 after the first use of this symbol. */
11172 || (before_relaxing
11173 #ifndef NO_ECOFF_DEBUGGING
11174 && sym
->ecoff_extern_size
== 0
11176 && S_GET_VALUE (sym
) == 0)
11177 || (S_GET_VALUE (sym
) != 0
11178 && S_GET_VALUE (sym
) <= g_switch_value
)))
11182 const char *segname
;
11184 segname
= segment_name (S_GET_SEGMENT (sym
));
11185 assert (strcmp (segname
, ".lit8") != 0
11186 && strcmp (segname
, ".lit4") != 0);
11187 change
= (strcmp (segname
, ".sdata") != 0
11188 && strcmp (segname
, ".sbss") != 0);
11193 /* We are not optimizing for the GP register. */
11197 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11198 extended opcode. SEC is the section the frag is in. */
11201 mips16_extended_frag (fragp
, sec
, stretch
)
11207 register const struct mips16_immed_operand
*op
;
11209 int mintiny
, maxtiny
;
11212 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11214 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11217 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11218 op
= mips16_immed_operands
;
11219 while (op
->type
!= type
)
11222 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11227 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11230 maxtiny
= 1 << op
->nbits
;
11235 maxtiny
= (1 << op
->nbits
) - 1;
11240 mintiny
= - (1 << (op
->nbits
- 1));
11241 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11244 /* We can't call S_GET_VALUE here, because we don't want to lock in
11245 a particular frag address. */
11246 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
11248 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
11249 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11250 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11252 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
11253 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
11256 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
11257 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
11258 + fragp
->fr_symbol
->sy_value
.X_add_number
11259 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11260 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
11269 /* We won't have the section when we are called from
11270 mips_relax_frag. However, we will always have been called
11271 from md_estimate_size_before_relax first. If this is a
11272 branch to a different section, we mark it as such. If SEC is
11273 NULL, and the frag is not marked, then it must be a branch to
11274 the same section. */
11277 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11284 fragp
->fr_subtype
=
11285 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11287 /* FIXME: We should support this, and let the linker
11288 catch branches and loads that are out of range. */
11289 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11290 _("unsupported PC relative reference to different section"));
11296 /* In this case, we know for sure that the symbol fragment is in
11297 the same section. If the fr_address of the symbol fragment
11298 is greater then the address of this fragment we want to add
11299 in STRETCH in order to get a better estimate of the address.
11300 This particularly matters because of the shift bits. */
11302 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
11306 /* Adjust stretch for any alignment frag. Note that if have
11307 been expanding the earlier code, the symbol may be
11308 defined in what appears to be an earlier frag. FIXME:
11309 This doesn't handle the fr_subtype field, which specifies
11310 a maximum number of bytes to skip when doing an
11313 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
11316 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11319 stretch
= - ((- stretch
)
11320 & ~ ((1 << (int) f
->fr_offset
) - 1));
11322 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11331 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11333 /* The base address rules are complicated. The base address of
11334 a branch is the following instruction. The base address of a
11335 PC relative load or add is the instruction itself, but if it
11336 is in a delay slot (in which case it can not be extended) use
11337 the address of the instruction whose delay slot it is in. */
11338 if (type
== 'p' || type
== 'q')
11342 /* If we are currently assuming that this frag should be
11343 extended, then, the current address is two bytes
11345 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11348 /* Ignore the low bit in the target, since it will be set
11349 for a text label. */
11350 if ((val
& 1) != 0)
11353 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11355 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11358 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11360 /* Branch offsets have an implicit 0 in the lowest bit. */
11361 if (type
== 'p' || type
== 'q')
11364 /* If any of the shifted bits are set, we must use an extended
11365 opcode. If the address depends on the size of this
11366 instruction, this can lead to a loop, so we arrange to always
11367 use an extended opcode. We only check this when we are in
11368 the main relaxation loop, when SEC is NULL. */
11369 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11371 fragp
->fr_subtype
=
11372 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11376 /* If we are about to mark a frag as extended because the value
11377 is precisely maxtiny + 1, then there is a chance of an
11378 infinite loop as in the following code:
11383 In this case when the la is extended, foo is 0x3fc bytes
11384 away, so the la can be shrunk, but then foo is 0x400 away, so
11385 the la must be extended. To avoid this loop, we mark the
11386 frag as extended if it was small, and is about to become
11387 extended with a value of maxtiny + 1. */
11388 if (val
== ((maxtiny
+ 1) << op
->shift
)
11389 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11392 fragp
->fr_subtype
=
11393 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11397 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11398 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11400 if ((val
& ((1 << op
->shift
) - 1)) != 0
11401 || val
< (mintiny
<< op
->shift
)
11402 || val
> (maxtiny
<< op
->shift
))
11408 /* Estimate the size of a frag before relaxing. Unless this is the
11409 mips16, we are not really relaxing here, and the final size is
11410 encoded in the subtype information. For the mips16, we have to
11411 decide whether we are using an extended opcode or not. */
11415 md_estimate_size_before_relax (fragp
, segtype
)
11421 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11423 if (mips16_extended_frag (fragp
, segtype
, 0))
11425 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11430 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11435 if (mips_pic
== NO_PIC
)
11437 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11439 else if (mips_pic
== SVR4_PIC
)
11444 sym
= fragp
->fr_symbol
;
11446 /* Handle the case of a symbol equated to another symbol. */
11447 while (sym
->sy_value
.X_op
== O_symbol
11448 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11452 /* It's possible to get a loop here in a badly written
11454 n
= sym
->sy_value
.X_add_symbol
;
11460 symsec
= S_GET_SEGMENT (sym
);
11462 /* This must duplicate the test in adjust_reloc_syms. */
11463 change
= (symsec
!= &bfd_und_section
11464 && symsec
!= &bfd_abs_section
11465 && ! bfd_is_com_section (symsec
));
11472 /* Record the offset to the first reloc in the fr_opcode field.
11473 This lets md_convert_frag and tc_gen_reloc know that the code
11474 must be expanded. */
11475 fragp
->fr_opcode
= (fragp
->fr_literal
11477 - RELAX_OLD (fragp
->fr_subtype
)
11478 + RELAX_RELOC1 (fragp
->fr_subtype
));
11479 /* FIXME: This really needs as_warn_where. */
11480 if (RELAX_WARN (fragp
->fr_subtype
))
11481 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11487 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11490 /* This is called to see whether a reloc against a defined symbol
11491 should be converted into a reloc against a section. Don't adjust
11492 MIPS16 jump relocations, so we don't have to worry about the format
11493 of the offset in the .o file. Don't adjust relocations against
11494 mips16 symbols, so that the linker can find them if it needs to set
11498 mips_fix_adjustable (fixp
)
11501 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11503 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11504 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11506 if (fixp
->fx_addsy
== NULL
)
11509 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11510 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11511 && fixp
->fx_subsy
== NULL
)
11517 /* Translate internal representation of relocation info to BFD target
11521 tc_gen_reloc (section
, fixp
)
11525 static arelent
*retval
[4];
11527 bfd_reloc_code_real_type code
;
11529 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11532 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11533 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11535 if (mips_pic
== EMBEDDED_PIC
11536 && SWITCH_TABLE (fixp
))
11538 /* For a switch table entry we use a special reloc. The addend
11539 is actually the difference between the reloc address and the
11541 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11542 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11543 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11544 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11546 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11548 /* We use a special addend for an internal RELLO reloc. */
11549 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11550 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11552 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11554 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11556 assert (fixp
->fx_next
!= NULL
11557 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11558 /* We use a special addend for an internal RELHI reloc. The
11559 reloc is relative to the RELLO; adjust the addend
11561 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11562 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11563 + fixp
->fx_next
->fx_where
11564 - S_GET_VALUE (fixp
->fx_subsy
));
11566 reloc
->addend
= (fixp
->fx_addnumber
11567 + fixp
->fx_next
->fx_frag
->fr_address
11568 + fixp
->fx_next
->fx_where
);
11570 else if (fixp
->fx_pcrel
== 0)
11571 reloc
->addend
= fixp
->fx_addnumber
;
11574 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11575 /* A gruesome hack which is a result of the gruesome gas reloc
11577 reloc
->addend
= reloc
->address
;
11579 reloc
->addend
= -reloc
->address
;
11582 /* If this is a variant frag, we may need to adjust the existing
11583 reloc and generate a new one. */
11584 if (fixp
->fx_frag
->fr_opcode
!= NULL
11585 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11586 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11587 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11588 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11589 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11590 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11591 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11595 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11597 /* If this is not the last reloc in this frag, then we have two
11598 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11599 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11600 the second one handle all of them. */
11601 if (fixp
->fx_next
!= NULL
11602 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11604 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11605 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11606 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11607 && (fixp
->fx_next
->fx_r_type
11608 == BFD_RELOC_MIPS_GOT_LO16
))
11609 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11610 && (fixp
->fx_next
->fx_r_type
11611 == BFD_RELOC_MIPS_CALL_LO16
)));
11616 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11617 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11618 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11620 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11621 reloc2
->address
= (reloc
->address
11622 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11623 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11624 reloc2
->addend
= fixp
->fx_addnumber
;
11625 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11626 assert (reloc2
->howto
!= NULL
);
11628 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11632 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11635 reloc3
->address
+= 4;
11638 if (mips_pic
== NO_PIC
)
11640 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11641 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11643 else if (mips_pic
== SVR4_PIC
)
11645 switch (fixp
->fx_r_type
)
11649 case BFD_RELOC_MIPS_GOT16
:
11651 case BFD_RELOC_MIPS_CALL16
:
11652 case BFD_RELOC_MIPS_GOT_LO16
:
11653 case BFD_RELOC_MIPS_CALL_LO16
:
11654 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11662 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11663 to be used in the relocation's section offset. */
11664 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11666 reloc
->address
= reloc
->addend
;
11670 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11671 fixup_segment converted a non-PC relative reloc into a PC
11672 relative reloc. In such a case, we need to convert the reloc
11674 code
= fixp
->fx_r_type
;
11675 if (fixp
->fx_pcrel
)
11680 code
= BFD_RELOC_8_PCREL
;
11683 code
= BFD_RELOC_16_PCREL
;
11686 code
= BFD_RELOC_32_PCREL
;
11689 code
= BFD_RELOC_64_PCREL
;
11691 case BFD_RELOC_8_PCREL
:
11692 case BFD_RELOC_16_PCREL
:
11693 case BFD_RELOC_32_PCREL
:
11694 case BFD_RELOC_64_PCREL
:
11695 case BFD_RELOC_16_PCREL_S2
:
11696 case BFD_RELOC_PCREL_HI16_S
:
11697 case BFD_RELOC_PCREL_LO16
:
11700 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11701 _("Cannot make %s relocation PC relative"),
11702 bfd_get_reloc_code_name (code
));
11706 /* To support a PC relative reloc when generating embedded PIC code
11707 for ECOFF, we use a Cygnus extension. We check for that here to
11708 make sure that we don't let such a reloc escape normally. */
11709 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11710 && code
== BFD_RELOC_16_PCREL_S2
11711 && mips_pic
!= EMBEDDED_PIC
)
11712 reloc
->howto
= NULL
;
11714 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11716 if (reloc
->howto
== NULL
)
11718 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11719 _("Can not represent %s relocation in this object file format"),
11720 bfd_get_reloc_code_name (code
));
11727 /* Relax a machine dependent frag. This returns the amount by which
11728 the current size of the frag should change. */
11731 mips_relax_frag (fragp
, stretch
)
11735 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11738 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11740 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11742 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11747 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11749 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11756 /* Convert a machine dependent frag. */
11759 md_convert_frag (abfd
, asec
, fragp
)
11767 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11770 register const struct mips16_immed_operand
*op
;
11771 boolean small
, ext
;
11774 unsigned long insn
;
11775 boolean use_extend
;
11776 unsigned short extend
;
11778 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11779 op
= mips16_immed_operands
;
11780 while (op
->type
!= type
)
11783 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11794 resolve_symbol_value (fragp
->fr_symbol
, 1);
11795 val
= S_GET_VALUE (fragp
->fr_symbol
);
11800 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11802 /* The rules for the base address of a PC relative reloc are
11803 complicated; see mips16_extended_frag. */
11804 if (type
== 'p' || type
== 'q')
11809 /* Ignore the low bit in the target, since it will be
11810 set for a text label. */
11811 if ((val
& 1) != 0)
11814 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11816 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11819 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11822 /* Make sure the section winds up with the alignment we have
11825 record_alignment (asec
, op
->shift
);
11829 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11830 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11831 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11832 _("extended instruction in delay slot"));
11834 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11836 if (target_big_endian
)
11837 insn
= bfd_getb16 (buf
);
11839 insn
= bfd_getl16 (buf
);
11841 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11842 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11843 small
, ext
, &insn
, &use_extend
, &extend
);
11847 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11848 fragp
->fr_fix
+= 2;
11852 md_number_to_chars (buf
, insn
, 2);
11853 fragp
->fr_fix
+= 2;
11858 if (fragp
->fr_opcode
== NULL
)
11861 old
= RELAX_OLD (fragp
->fr_subtype
);
11862 new = RELAX_NEW (fragp
->fr_subtype
);
11863 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11866 memcpy (fixptr
- old
, fixptr
, new);
11868 fragp
->fr_fix
+= new - old
;
11874 /* This function is called after the relocs have been generated.
11875 We've been storing mips16 text labels as odd. Here we convert them
11876 back to even for the convenience of the debugger. */
11879 mips_frob_file_after_relocs ()
11882 unsigned int count
, i
;
11884 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11887 syms
= bfd_get_outsymbols (stdoutput
);
11888 count
= bfd_get_symcount (stdoutput
);
11889 for (i
= 0; i
< count
; i
++, syms
++)
11891 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11892 && ((*syms
)->value
& 1) != 0)
11894 (*syms
)->value
&= ~1;
11895 /* If the symbol has an odd size, it was probably computed
11896 incorrectly, so adjust that as well. */
11897 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11898 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11905 /* This function is called whenever a label is defined. It is used
11906 when handling branch delays; if a branch has a label, we assume we
11907 can not move it. */
11910 mips_define_label (sym
)
11913 struct insn_label_list
*l
;
11915 if (free_insn_labels
== NULL
)
11916 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11919 l
= free_insn_labels
;
11920 free_insn_labels
= l
->next
;
11924 l
->next
= insn_labels
;
11928 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11930 /* Some special processing for a MIPS ELF file. */
11933 mips_elf_final_processing ()
11935 /* Write out the register information. */
11940 s
.ri_gprmask
= mips_gprmask
;
11941 s
.ri_cprmask
[0] = mips_cprmask
[0];
11942 s
.ri_cprmask
[1] = mips_cprmask
[1];
11943 s
.ri_cprmask
[2] = mips_cprmask
[2];
11944 s
.ri_cprmask
[3] = mips_cprmask
[3];
11945 /* The gp_value field is set by the MIPS ELF backend. */
11947 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11948 ((Elf32_External_RegInfo
*)
11949 mips_regmask_frag
));
11953 Elf64_Internal_RegInfo s
;
11955 s
.ri_gprmask
= mips_gprmask
;
11957 s
.ri_cprmask
[0] = mips_cprmask
[0];
11958 s
.ri_cprmask
[1] = mips_cprmask
[1];
11959 s
.ri_cprmask
[2] = mips_cprmask
[2];
11960 s
.ri_cprmask
[3] = mips_cprmask
[3];
11961 /* The gp_value field is set by the MIPS ELF backend. */
11963 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11964 ((Elf64_External_RegInfo
*)
11965 mips_regmask_frag
));
11968 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11969 sort of BFD interface for this. */
11970 if (mips_any_noreorder
)
11971 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11972 if (mips_pic
!= NO_PIC
)
11973 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11976 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11978 /* These functions should really be defined by the object file format,
11979 since they are related to debugging information. However, this
11980 code has to work for the a.out format, which does not define them,
11981 so we provide simple versions here. These don't actually generate
11982 any debugging information, but they do simple checking and someday
11983 somebody may make them useful. */
11987 struct loc
*loc_next
;
11988 unsigned long loc_fileno
;
11989 unsigned long loc_lineno
;
11990 unsigned long loc_offset
;
11991 unsigned short loc_delta
;
11992 unsigned short loc_count
;
11999 typedef struct proc
12001 struct proc
*proc_next
;
12002 struct symbol
*proc_isym
;
12003 struct symbol
*proc_end
;
12004 unsigned long proc_reg_mask
;
12005 unsigned long proc_reg_offset
;
12006 unsigned long proc_fpreg_mask
;
12007 unsigned long proc_fpreg_offset
;
12008 unsigned long proc_frameoffset
;
12009 unsigned long proc_framereg
;
12010 unsigned long proc_pcreg
;
12012 struct file
*proc_file
;
12017 typedef struct file
12019 struct file
*file_next
;
12020 unsigned long file_fileno
;
12021 struct symbol
*file_symbol
;
12022 struct symbol
*file_end
;
12023 struct proc
*file_proc
;
12028 static struct obstack proc_frags
;
12029 static procS
*proc_lastP
;
12030 static procS
*proc_rootP
;
12031 static int numprocs
;
12036 obstack_begin (&proc_frags
, 0x2000);
12042 /* check for premature end, nesting errors, etc */
12043 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
12044 as_warn (_("missing `.end' at end of assembly"));
12053 if (*input_line_pointer
== '-')
12055 ++input_line_pointer
;
12058 if (!isdigit (*input_line_pointer
))
12059 as_bad (_("Expected simple number."));
12060 if (input_line_pointer
[0] == '0')
12062 if (input_line_pointer
[1] == 'x')
12064 input_line_pointer
+= 2;
12065 while (isxdigit (*input_line_pointer
))
12068 val
|= hex_value (*input_line_pointer
++);
12070 return negative
? -val
: val
;
12074 ++input_line_pointer
;
12075 while (isdigit (*input_line_pointer
))
12078 val
|= *input_line_pointer
++ - '0';
12080 return negative
? -val
: val
;
12083 if (!isdigit (*input_line_pointer
))
12085 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12086 *input_line_pointer
, *input_line_pointer
);
12087 as_warn (_("Invalid number"));
12090 while (isdigit (*input_line_pointer
))
12093 val
+= *input_line_pointer
++ - '0';
12095 return negative
? -val
: val
;
12098 /* The .file directive; just like the usual .file directive, but there
12099 is an initial number which is the ECOFF file index. */
12107 line
= get_number ();
12112 /* The .end directive. */
12120 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12123 demand_empty_rest_of_line ();
12127 if (now_seg
!= text_section
)
12128 as_warn (_(".end not in text section"));
12131 as_warn (_(".end and no .ent seen yet."));
12137 assert (S_GET_NAME (p
));
12138 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
12139 as_warn (_(".end symbol does not match .ent symbol."));
12142 proc_lastP
->proc_end
= (symbolS
*) 1;
12145 /* The .aent and .ent directives. */
12155 symbolP
= get_symbol ();
12156 if (*input_line_pointer
== ',')
12157 input_line_pointer
++;
12158 SKIP_WHITESPACE ();
12159 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
12160 number
= get_number ();
12161 if (now_seg
!= text_section
)
12162 as_warn (_(".ent or .aent not in text section."));
12164 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
12165 as_warn (_("missing `.end'"));
12169 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
12170 procP
->proc_isym
= symbolP
;
12171 procP
->proc_reg_mask
= 0;
12172 procP
->proc_reg_offset
= 0;
12173 procP
->proc_fpreg_mask
= 0;
12174 procP
->proc_fpreg_offset
= 0;
12175 procP
->proc_frameoffset
= 0;
12176 procP
->proc_framereg
= 0;
12177 procP
->proc_pcreg
= 0;
12178 procP
->proc_end
= NULL
;
12179 procP
->proc_next
= NULL
;
12181 proc_lastP
->proc_next
= procP
;
12183 proc_rootP
= procP
;
12184 proc_lastP
= procP
;
12186 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
12190 demand_empty_rest_of_line ();
12193 /* The .frame directive. */
12206 frame_reg
= tc_get_register (1);
12207 if (*input_line_pointer
== ',')
12208 input_line_pointer
++;
12209 frame_off
= get_absolute_expression ();
12210 if (*input_line_pointer
== ',')
12211 input_line_pointer
++;
12212 pcreg
= tc_get_register (0);
12214 /* bob third eye */
12215 assert (proc_rootP
);
12216 proc_rootP
->proc_framereg
= frame_reg
;
12217 proc_rootP
->proc_frameoffset
= frame_off
;
12218 proc_rootP
->proc_pcreg
= pcreg
;
12219 /* bob macho .frame */
12221 /* We don't have to write out a frame stab for unoptimized code. */
12222 if (!(frame_reg
== FP
&& frame_off
== 0))
12225 as_warn (_("No .ent for .frame to use."));
12226 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
12227 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
12228 S_SET_TYPE (symP
, N_RMASK
);
12229 S_SET_OTHER (symP
, 0);
12230 S_SET_DESC (symP
, 0);
12231 symP
->sy_forward
= proc_lastP
->proc_isym
;
12232 /* bob perhaps I should have used pseudo set */
12234 demand_empty_rest_of_line ();
12238 /* The .fmask and .mask directives. */
12245 char str
[100], *strP
;
12251 mask
= get_number ();
12252 if (*input_line_pointer
== ',')
12253 input_line_pointer
++;
12254 off
= get_absolute_expression ();
12256 /* bob only for coff */
12257 assert (proc_rootP
);
12258 if (reg_type
== 'F')
12260 proc_rootP
->proc_fpreg_mask
= mask
;
12261 proc_rootP
->proc_fpreg_offset
= off
;
12265 proc_rootP
->proc_reg_mask
= mask
;
12266 proc_rootP
->proc_reg_offset
= off
;
12269 /* bob macho .mask + .fmask */
12271 /* We don't have to write out a mask stab if no saved regs. */
12275 as_warn (_("No .ent for .mask to use."));
12277 for (i
= 0; i
< 32; i
++)
12281 sprintf (strP
, "%c%d,", reg_type
, i
);
12282 strP
+= strlen (strP
);
12286 sprintf (strP
, ";%d,", off
);
12287 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
12288 S_SET_TYPE (symP
, N_RMASK
);
12289 S_SET_OTHER (symP
, 0);
12290 S_SET_DESC (symP
, 0);
12291 symP
->sy_forward
= proc_lastP
->proc_isym
;
12292 /* bob perhaps I should have used pseudo set */
12297 /* The .loc directive. */
12308 assert (now_seg
== text_section
);
12310 lineno
= get_number ();
12311 addroff
= frag_now_fix ();
12313 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12314 S_SET_TYPE (symbolP
, N_SLINE
);
12315 S_SET_OTHER (symbolP
, 0);
12316 S_SET_DESC (symbolP
, lineno
);
12317 symbolP
->sy_segment
= now_seg
;