1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared
= TRUE
;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros
;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
194 /* True if -mgp32 was passed. */
195 static int file_mips_gp32
= -1;
197 /* True if -mfp32 was passed. */
198 static int file_mips_fp32
= -1;
200 /* This is the struct we use to hold the current set of options. Note
201 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
202 -1 to indicate that they have not been initialized. */
204 static struct mips_set_options mips_opts
=
206 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
209 /* These variables are filled in with the masks of registers used.
210 The object format code reads them and puts them in the appropriate
212 unsigned long mips_gprmask
;
213 unsigned long mips_cprmask
[4];
215 /* MIPS ISA we are using for this output file. */
216 static int file_mips_isa
= ISA_UNKNOWN
;
218 /* True if -mips16 was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips16
;
222 /* True if -mips3d was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mips3d
;
226 /* True if -mdmx was passed or implied by arguments passed on the
227 command line (e.g., by -march). */
228 static int file_ase_mdmx
;
230 /* The argument of the -march= flag. The architecture we are assembling. */
231 static int file_mips_arch
= CPU_UNKNOWN
;
232 static const char *mips_arch_string
;
234 /* The argument of the -mtune= flag. The architecture for which we
236 static int mips_tune
= CPU_UNKNOWN
;
237 static const char *mips_tune_string
;
239 /* True when generating 32-bit code for a 64-bit processor. */
240 static int mips_32bitmode
= 0;
242 /* True if the given ABI requires 32-bit registers. */
243 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
245 /* Likewise 64-bit registers. */
246 #define ABI_NEEDS_64BIT_REGS(ABI) \
248 || (ABI) == N64_ABI \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
257 || (ISA) == ISA_MIPS64R2 \
260 /* Return true if ISA supports 64-bit right rotate (dror et al.)
262 #define ISA_HAS_DROR(ISA) ( \
263 (ISA) == ISA_MIPS64R2 \
266 /* Return true if ISA supports 32-bit right rotate (ror et al.)
268 #define ISA_HAS_ROR(ISA) ( \
269 (ISA) == ISA_MIPS32R2 \
270 || (ISA) == ISA_MIPS64R2 \
273 #define HAVE_32BIT_GPRS \
274 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276 #define HAVE_32BIT_FPRS \
277 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
279 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
280 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
282 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
284 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
286 /* True if relocations are stored in-place. */
287 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
289 /* We can only have 64bit addresses if the object file format supports it. */
290 #define HAVE_32BIT_ADDRESSES \
292 || (bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS)) \
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_VR5500 \
355 /* Whether the processor uses hardware interlocks to protect reads
356 from the GPRs after they are loaded from memory, and thus does not
357 require nops to be inserted. This applies to instructions marked
358 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 #define gpr_interlocks \
361 (mips_opts.isa != ISA_MIPS1 \
362 || mips_opts.arch == CPU_R3900)
364 /* Whether the processor uses hardware interlocks to avoid delays
365 required by coprocessor instructions, and thus does not require
366 nops to be inserted. This applies to instructions marked
367 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
368 between instructions marked INSN_WRITE_COND_CODE and ones marked
369 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
370 levels I, II, and III. */
371 /* Itbl support may require additional care here. */
372 #define cop_interlocks \
373 ((mips_opts.isa != ISA_MIPS1 \
374 && mips_opts.isa != ISA_MIPS2 \
375 && mips_opts.isa != ISA_MIPS3) \
376 || mips_opts.arch == CPU_R4300 \
379 /* Whether the processor uses hardware interlocks to protect reads
380 from coprocessor registers after they are loaded from memory, and
381 thus does not require nops to be inserted. This applies to
382 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
383 requires at MIPS ISA level I. */
384 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
386 /* Is this a mfhi or mflo instruction? */
387 #define MF_HILO_INSN(PINFO) \
388 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
390 /* MIPS PIC level. */
392 enum mips_pic_level mips_pic
;
394 /* 1 if we should generate 32 bit offsets from the $gp register in
395 SVR4_PIC mode. Currently has no meaning in other modes. */
396 static int mips_big_got
= 0;
398 /* 1 if trap instructions should used for overflow rather than break
400 static int mips_trap
= 0;
402 /* 1 if double width floating point constants should not be constructed
403 by assembling two single width halves into two single width floating
404 point registers which just happen to alias the double width destination
405 register. On some architectures this aliasing can be disabled by a bit
406 in the status register, and the setting of this bit cannot be determined
407 automatically at assemble time. */
408 static int mips_disable_float_construction
;
410 /* Non-zero if any .set noreorder directives were used. */
412 static int mips_any_noreorder
;
414 /* Non-zero if nops should be inserted when the register referenced in
415 an mfhi/mflo instruction is read in the next two instructions. */
416 static int mips_7000_hilo_fix
;
418 /* The size of the small data section. */
419 static unsigned int g_switch_value
= 8;
420 /* Whether the -G option was used. */
421 static int g_switch_seen
= 0;
426 /* If we can determine in advance that GP optimization won't be
427 possible, we can skip the relaxation stuff that tries to produce
428 GP-relative references. This makes delay slot optimization work
431 This function can only provide a guess, but it seems to work for
432 gcc output. It needs to guess right for gcc, otherwise gcc
433 will put what it thinks is a GP-relative instruction in a branch
436 I don't know if a fix is needed for the SVR4_PIC mode. I've only
437 fixed it for the non-PIC mode. KR 95/04/07 */
438 static int nopic_need_relax (symbolS
*, int);
440 /* handle of the OPCODE hash table */
441 static struct hash_control
*op_hash
= NULL
;
443 /* The opcode hash table we use for the mips16. */
444 static struct hash_control
*mips16_op_hash
= NULL
;
446 /* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful */
448 const char comment_chars
[] = "#";
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output */
453 /* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456 /* Also note that C style comments are always supported. */
457 const char line_comment_chars
[] = "#";
459 /* This array holds machine specific line separator characters. */
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point nums */
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant */
468 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
470 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
471 changed in read.c . Ideally it shouldn't have to know about it at all,
472 but nothing is ideal around here.
475 static char *insn_error
;
477 static int auto_align
= 1;
479 /* When outputting SVR4 PIC code, the assembler needs to know the
480 offset in the stack frame from which to restore the $gp register.
481 This is set by the .cprestore pseudo-op, and saved in this
483 static offsetT mips_cprestore_offset
= -1;
485 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
486 more optimizations, it can use a register value instead of a memory-saved
487 offset and even an other register than $gp as global pointer. */
488 static offsetT mips_cpreturn_offset
= -1;
489 static int mips_cpreturn_register
= -1;
490 static int mips_gp_register
= GP
;
491 static int mips_gprel_offset
= 0;
493 /* Whether mips_cprestore_offset has been set in the current function
494 (or whether it has already been warned about, if not). */
495 static int mips_cprestore_valid
= 0;
497 /* This is the register which holds the stack frame, as set by the
498 .frame pseudo-op. This is needed to implement .cprestore. */
499 static int mips_frame_reg
= SP
;
501 /* Whether mips_frame_reg has been set in the current function
502 (or whether it has already been warned about, if not). */
503 static int mips_frame_reg_valid
= 0;
505 /* To output NOP instructions correctly, we need to keep information
506 about the previous two instructions. */
508 /* Whether we are optimizing. The default value of 2 means to remove
509 unneeded NOPs and swap branch instructions when possible. A value
510 of 1 means to not swap branches. A value of 0 means to always
512 static int mips_optimize
= 2;
514 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
515 equivalent to seeing no -g option at all. */
516 static int mips_debug
= 0;
518 /* The previous instruction. */
519 static struct mips_cl_insn prev_insn
;
521 /* The instruction before prev_insn. */
522 static struct mips_cl_insn prev_prev_insn
;
524 /* If we don't want information for prev_insn or prev_prev_insn, we
525 point the insn_mo field at this dummy integer. */
526 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
528 /* Non-zero if prev_insn is valid. */
529 static int prev_insn_valid
;
531 /* The frag for the previous instruction. */
532 static struct frag
*prev_insn_frag
;
534 /* The offset into prev_insn_frag for the previous instruction. */
535 static long prev_insn_where
;
537 /* The reloc type for the previous instruction, if any. */
538 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
540 /* The reloc for the previous instruction, if any. */
541 static fixS
*prev_insn_fixp
[3];
543 /* Non-zero if the previous instruction was in a delay slot. */
544 static int prev_insn_is_delay_slot
;
546 /* Non-zero if the previous instruction was in a .set noreorder. */
547 static int prev_insn_unreordered
;
549 /* Non-zero if the previous instruction uses an extend opcode (if
551 static int prev_insn_extended
;
553 /* Non-zero if the previous previous instruction was in a .set
555 static int prev_prev_insn_unreordered
;
557 /* If this is set, it points to a frag holding nop instructions which
558 were inserted before the start of a noreorder section. If those
559 nops turn out to be unnecessary, the size of the frag can be
561 static fragS
*prev_nop_frag
;
563 /* The number of nop instructions we created in prev_nop_frag. */
564 static int prev_nop_frag_holds
;
566 /* The number of nop instructions that we know we need in
568 static int prev_nop_frag_required
;
570 /* The number of instructions we've seen since prev_nop_frag. */
571 static int prev_nop_frag_since
;
573 /* For ECOFF and ELF, relocations against symbols are done in two
574 parts, with a HI relocation and a LO relocation. Each relocation
575 has only 16 bits of space to store an addend. This means that in
576 order for the linker to handle carries correctly, it must be able
577 to locate both the HI and the LO relocation. This means that the
578 relocations must appear in order in the relocation table.
580 In order to implement this, we keep track of each unmatched HI
581 relocation. We then sort them so that they immediately precede the
582 corresponding LO relocation. */
587 struct mips_hi_fixup
*next
;
590 /* The section this fixup is in. */
594 /* The list of unmatched HI relocs. */
596 static struct mips_hi_fixup
*mips_hi_fixup_list
;
598 /* The frag containing the last explicit relocation operator.
599 Null if explicit relocations have not been used. */
601 static fragS
*prev_reloc_op_frag
;
603 /* Map normal MIPS register numbers to mips16 register numbers. */
605 #define X ILLEGAL_REG
606 static const int mips32_to_16_reg_map
[] =
608 X
, X
, 2, 3, 4, 5, 6, 7,
609 X
, X
, X
, X
, X
, X
, X
, X
,
610 0, 1, X
, X
, X
, X
, X
, X
,
611 X
, X
, X
, X
, X
, X
, X
, X
615 /* Map mips16 register numbers to normal MIPS register numbers. */
617 static const unsigned int mips16_to_32_reg_map
[] =
619 16, 17, 2, 3, 4, 5, 6, 7
622 static int mips_fix_vr4120
;
624 /* We don't relax branches by default, since this causes us to expand
625 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
626 fail to compute the offset before expanding the macro to the most
627 efficient expansion. */
629 static int mips_relax_branch
;
631 /* The expansion of many macros depends on the type of symbol that
632 they refer to. For example, when generating position-dependent code,
633 a macro that refers to a symbol may have two different expansions,
634 one which uses GP-relative addresses and one which uses absolute
635 addresses. When generating SVR4-style PIC, a macro may have
636 different expansions for local and global symbols.
638 We handle these situations by generating both sequences and putting
639 them in variant frags. In position-dependent code, the first sequence
640 will be the GP-relative one and the second sequence will be the
641 absolute one. In SVR4 PIC, the first sequence will be for global
642 symbols and the second will be for local symbols.
644 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
645 SECOND are the lengths of the two sequences in bytes. These fields
646 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
647 the subtype has the following flags:
650 Set if it has been decided that we should use the second
651 sequence instead of the first.
654 Set in the first variant frag if the macro's second implementation
655 is longer than its first. This refers to the macro as a whole,
656 not an individual relaxation.
659 Set in the first variant frag if the macro appeared in a .set nomacro
660 block and if one alternative requires a warning but the other does not.
663 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
666 The frag's "opcode" points to the first fixup for relaxable code.
668 Relaxable macros are generated using a sequence such as:
670 relax_start (SYMBOL);
671 ... generate first expansion ...
673 ... generate second expansion ...
676 The code and fixups for the unwanted alternative are discarded
677 by md_convert_frag. */
678 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
680 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
681 #define RELAX_SECOND(X) ((X) & 0xff)
682 #define RELAX_USE_SECOND 0x10000
683 #define RELAX_SECOND_LONGER 0x20000
684 #define RELAX_NOMACRO 0x40000
685 #define RELAX_DELAY_SLOT 0x80000
687 /* Branch without likely bit. If label is out of range, we turn:
689 beq reg1, reg2, label
699 with the following opcode replacements:
706 bltzal <-> bgezal (with jal label instead of j label)
708 Even though keeping the delay slot instruction in the delay slot of
709 the branch would be more efficient, it would be very tricky to do
710 correctly, because we'd have to introduce a variable frag *after*
711 the delay slot instruction, and expand that instead. Let's do it
712 the easy way for now, even if the branch-not-taken case now costs
713 one additional instruction. Out-of-range branches are not supposed
714 to be common, anyway.
716 Branch likely. If label is out of range, we turn:
718 beql reg1, reg2, label
719 delay slot (annulled if branch not taken)
728 delay slot (executed only if branch taken)
731 It would be possible to generate a shorter sequence by losing the
732 likely bit, generating something like:
737 delay slot (executed only if branch taken)
749 bltzall -> bgezal (with jal label instead of j label)
750 bgezall -> bltzal (ditto)
753 but it's not clear that it would actually improve performance. */
754 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
757 | ((toofar) ? 1 : 0) \
759 | ((likely) ? 4 : 0) \
760 | ((uncond) ? 8 : 0)))
761 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
762 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
763 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
764 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
765 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
767 /* For mips16 code, we use an entirely different form of relaxation.
768 mips16 supports two versions of most instructions which take
769 immediate values: a small one which takes some small value, and a
770 larger one which takes a 16 bit value. Since branches also follow
771 this pattern, relaxing these values is required.
773 We can assemble both mips16 and normal MIPS code in a single
774 object. Therefore, we need to support this type of relaxation at
775 the same time that we support the relaxation described above. We
776 use the high bit of the subtype field to distinguish these cases.
778 The information we store for this type of relaxation is the
779 argument code found in the opcode file for this relocation, whether
780 the user explicitly requested a small or extended form, and whether
781 the relocation is in a jump or jal delay slot. That tells us the
782 size of the value, and how it should be stored. We also store
783 whether the fragment is considered to be extended or not. We also
784 store whether this is known to be a branch to a different section,
785 whether we have tried to relax this frag yet, and whether we have
786 ever extended a PC relative fragment because of a shift count. */
787 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
790 | ((small) ? 0x100 : 0) \
791 | ((ext) ? 0x200 : 0) \
792 | ((dslot) ? 0x400 : 0) \
793 | ((jal_dslot) ? 0x800 : 0))
794 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
795 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
796 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
797 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
798 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
799 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
800 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
801 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
802 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
803 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
804 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
805 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
807 /* Is the given value a sign-extended 32-bit value? */
808 #define IS_SEXT_32BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fffffff) == 0 \
810 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
812 /* Is the given value a sign-extended 16-bit value? */
813 #define IS_SEXT_16BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fff) == 0 \
815 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
818 /* Global variables used when generating relaxable macros. See the
819 comment above RELAX_ENCODE for more details about how relaxation
822 /* 0 if we're not emitting a relaxable macro.
823 1 if we're emitting the first of the two relaxation alternatives.
824 2 if we're emitting the second alternative. */
827 /* The first relaxable fixup in the current frag. (In other words,
828 the first fixup that refers to relaxable code.) */
831 /* sizes[0] says how many bytes of the first alternative are stored in
832 the current frag. Likewise sizes[1] for the second alternative. */
833 unsigned int sizes
[2];
835 /* The symbol on which the choice of sequence depends. */
839 /* Global variables used to decide whether a macro needs a warning. */
841 /* True if the macro is in a branch delay slot. */
842 bfd_boolean delay_slot_p
;
844 /* For relaxable macros, sizes[0] is the length of the first alternative
845 in bytes and sizes[1] is the length of the second alternative.
846 For non-relaxable macros, both elements give the length of the
848 unsigned int sizes
[2];
850 /* The first variant frag for this macro. */
852 } mips_macro_warning
;
854 /* Prototypes for static functions. */
856 #define internalError() \
857 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
859 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
861 static void append_insn
862 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
863 static void mips_no_prev_insn (int);
864 static void mips16_macro_build
865 (expressionS
*, const char *, const char *, va_list);
866 static void load_register (int, expressionS
*, int);
867 static void macro_start (void);
868 static void macro_end (void);
869 static void macro (struct mips_cl_insn
* ip
);
870 static void mips16_macro (struct mips_cl_insn
* ip
);
871 #ifdef LOSING_COMPILER
872 static void macro2 (struct mips_cl_insn
* ip
);
874 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
875 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
876 static void mips16_immed
877 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
878 unsigned long *, bfd_boolean
*, unsigned short *);
879 static size_t my_getSmallExpression
880 (expressionS
*, bfd_reloc_code_real_type
*, char *);
881 static void my_getExpression (expressionS
*, char *);
882 static void s_align (int);
883 static void s_change_sec (int);
884 static void s_change_section (int);
885 static void s_cons (int);
886 static void s_float_cons (int);
887 static void s_mips_globl (int);
888 static void s_option (int);
889 static void s_mipsset (int);
890 static void s_abicalls (int);
891 static void s_cpload (int);
892 static void s_cpsetup (int);
893 static void s_cplocal (int);
894 static void s_cprestore (int);
895 static void s_cpreturn (int);
896 static void s_gpvalue (int);
897 static void s_gpword (int);
898 static void s_gpdword (int);
899 static void s_cpadd (int);
900 static void s_insn (int);
901 static void md_obj_begin (void);
902 static void md_obj_end (void);
903 static void s_mips_ent (int);
904 static void s_mips_end (int);
905 static void s_mips_frame (int);
906 static void s_mips_mask (int reg_type
);
907 static void s_mips_stab (int);
908 static void s_mips_weakext (int);
909 static void s_mips_file (int);
910 static void s_mips_loc (int);
911 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
912 static int relaxed_branch_length (fragS
*, asection
*, int);
913 static int validate_mips_insn (const struct mips_opcode
*);
915 /* Table and functions used to map between CPU/ISA names, and
916 ISA levels, and CPU numbers. */
920 const char *name
; /* CPU or ISA name. */
921 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
922 int isa
; /* ISA level. */
923 int cpu
; /* CPU number (default CPU if ISA). */
926 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
927 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
928 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table
[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option
, 0},
952 {"set", s_mipsset
, 0},
953 {"rdata", s_change_sec
, 'r'},
954 {"sdata", s_change_sec
, 's'},
955 {"livereg", s_ignore
, 0},
956 {"abicalls", s_abicalls
, 0},
957 {"cpload", s_cpload
, 0},
958 {"cpsetup", s_cpsetup
, 0},
959 {"cplocal", s_cplocal
, 0},
960 {"cprestore", s_cprestore
, 0},
961 {"cpreturn", s_cpreturn
, 0},
962 {"gpvalue", s_gpvalue
, 0},
963 {"gpword", s_gpword
, 0},
964 {"gpdword", s_gpdword
, 0},
965 {"cpadd", s_cpadd
, 0},
968 /* Relatively generic pseudo-ops that happen to be used on MIPS
970 {"asciiz", stringer
, 1},
971 {"bss", s_change_sec
, 'b'},
974 {"dword", s_cons
, 3},
975 {"weakext", s_mips_weakext
, 0},
977 /* These pseudo-ops are defined in read.c, but must be overridden
978 here for one reason or another. */
979 {"align", s_align
, 0},
981 {"data", s_change_sec
, 'd'},
982 {"double", s_float_cons
, 'd'},
983 {"float", s_float_cons
, 'f'},
984 {"globl", s_mips_globl
, 0},
985 {"global", s_mips_globl
, 0},
986 {"hword", s_cons
, 1},
991 {"section", s_change_section
, 0},
992 {"short", s_cons
, 1},
993 {"single", s_float_cons
, 'f'},
994 {"stabn", s_mips_stab
, 'n'},
995 {"text", s_change_sec
, 't'},
998 { "extern", ecoff_directive_extern
, 0},
1003 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1005 /* These pseudo-ops should be defined by the object file format.
1006 However, a.out doesn't support them, so we have versions here. */
1007 {"aent", s_mips_ent
, 1},
1008 {"bgnb", s_ignore
, 0},
1009 {"end", s_mips_end
, 0},
1010 {"endb", s_ignore
, 0},
1011 {"ent", s_mips_ent
, 0},
1012 {"file", s_mips_file
, 0},
1013 {"fmask", s_mips_mask
, 'F'},
1014 {"frame", s_mips_frame
, 0},
1015 {"loc", s_mips_loc
, 0},
1016 {"mask", s_mips_mask
, 'R'},
1017 {"verstamp", s_ignore
, 0},
1021 extern void pop_insert (const pseudo_typeS
*);
1024 mips_pop_insert (void)
1026 pop_insert (mips_pseudo_table
);
1027 if (! ECOFF_DEBUGGING
)
1028 pop_insert (mips_nonecoff_pseudo_table
);
1031 /* Symbols labelling the current insn. */
1033 struct insn_label_list
1035 struct insn_label_list
*next
;
1039 static struct insn_label_list
*insn_labels
;
1040 static struct insn_label_list
*free_insn_labels
;
1042 static void mips_clear_insn_labels (void);
1045 mips_clear_insn_labels (void)
1047 register struct insn_label_list
**pl
;
1049 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1055 static char *expr_end
;
1057 /* Expressions which appear in instructions. These are set by
1060 static expressionS imm_expr
;
1061 static expressionS imm2_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* These are set by mips16_ip if an explicit extension is used. */
1073 static bfd_boolean mips16_small
, mips16_ext
;
1076 /* The pdr segment for per procedure frame/regmask info. Not used for
1079 static segT pdr_seg
;
1082 /* The default target format to use. */
1085 mips_target_format (void)
1087 switch (OUTPUT_FLAVOR
)
1089 case bfd_target_ecoff_flavour
:
1090 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1091 case bfd_target_coff_flavour
:
1093 case bfd_target_elf_flavour
:
1095 /* This is traditional mips. */
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradbigmips"
1100 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradlittlemips"
1104 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1110 ? "elf32-nbigmips" : "elf32-bigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-littlemips"
1114 ? "elf32-nlittlemips" : "elf32-littlemips")));
1122 /* This function is called once, at assembler startup time. It should
1123 set up all the tables, etc. that the MD part of the assembler will need. */
1128 register const char *retval
= NULL
;
1132 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1133 as_warn (_("Could not set architecture and machine"));
1135 op_hash
= hash_new ();
1137 for (i
= 0; i
< NUMOPCODES
;)
1139 const char *name
= mips_opcodes
[i
].name
;
1141 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1144 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1145 mips_opcodes
[i
].name
, retval
);
1146 /* Probably a memory allocation problem? Give up now. */
1147 as_fatal (_("Broken assembler. No assembly attempted."));
1151 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1153 if (!validate_mips_insn (&mips_opcodes
[i
]))
1158 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1161 mips16_op_hash
= hash_new ();
1164 while (i
< bfd_mips16_num_opcodes
)
1166 const char *name
= mips16_opcodes
[i
].name
;
1168 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1170 as_fatal (_("internal: can't hash `%s': %s"),
1171 mips16_opcodes
[i
].name
, retval
);
1174 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1175 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1176 != mips16_opcodes
[i
].match
))
1178 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1179 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1184 while (i
< bfd_mips16_num_opcodes
1185 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1191 /* We add all the general register names to the symbol table. This
1192 helps us detect invalid uses of them. */
1193 for (i
= 0; i
< 32; i
++)
1197 sprintf (buf
, "$%d", i
);
1198 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1199 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1218 &zero_address_frag
));
1220 /* If we don't add these register names to the symbol table, they
1221 may end up being added as regular symbols by operand(), and then
1222 make it to the object file as undefined in case they're not
1223 regarded as local symbols. They're local in o32, since `$' is a
1224 local symbol prefix, but not in n32 or n64. */
1225 for (i
= 0; i
< 8; i
++)
1229 sprintf (buf
, "$fcc%i", i
);
1230 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1231 &zero_address_frag
));
1234 mips_no_prev_insn (FALSE
);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (HAVE_IN_PLACE_ADDENDS
1409 && (reloc
== BFD_RELOC_HI16_S
1410 || reloc
== BFD_RELOC_MIPS_GOT16
1411 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1414 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1417 static inline bfd_boolean
1418 fixup_has_matching_lo_p (fixS
*fixp
)
1420 return (fixp
->fx_next
!= NULL
1421 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1422 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1423 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1424 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1427 /* See whether instruction IP reads register REG. CLASS is the type
1431 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1432 enum mips_regclass
class)
1434 if (class == MIPS16_REG
)
1436 assert (mips_opts
.mips16
);
1437 reg
= mips16_to_32_reg_map
[reg
];
1438 class = MIPS_GR_REG
;
1441 /* Don't report on general register ZERO, since it never changes. */
1442 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1445 if (class == MIPS_FP_REG
)
1447 assert (! mips_opts
.mips16
);
1448 /* If we are called with either $f0 or $f1, we must check $f0.
1449 This is not optimal, because it will introduce an unnecessary
1450 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1451 need to distinguish reading both $f0 and $f1 or just one of
1452 them. Note that we don't have to check the other way,
1453 because there is no instruction that sets both $f0 and $f1
1454 and requires a delay. */
1455 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1456 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1457 == (reg
&~ (unsigned) 1)))
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1460 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1461 == (reg
&~ (unsigned) 1)))
1464 else if (! mips_opts
.mips16
)
1466 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1467 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1469 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1470 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1477 & MIPS16OP_MASK_RX
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1481 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1482 & MIPS16OP_MASK_RY
)]
1485 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1486 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1487 & MIPS16OP_MASK_MOVE32Z
)]
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1494 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1496 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1497 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1498 & MIPS16OP_MASK_REGR32
) == reg
)
1505 /* This function returns true if modifying a register requires a
1509 reg_needs_delay (unsigned int reg
)
1511 unsigned long prev_pinfo
;
1513 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1514 if (! mips_opts
.noreorder
1515 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1516 && ! gpr_interlocks
)
1517 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1518 && ! cop_interlocks
)))
1520 /* A load from a coprocessor or from memory. All load delays
1521 delay the use of general register rt for one instruction. */
1522 /* Itbl support may require additional care here. */
1523 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1524 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1531 /* Mark instruction labels in mips16 mode. This permits the linker to
1532 handle them specially, such as generating jalx instructions when
1533 needed. We also make them odd for the duration of the assembly, in
1534 order to generate the right sort of code. We will make them even
1535 in the adjust_symtab routine, while leaving them marked. This is
1536 convenient for the debugger and the disassembler. The linker knows
1537 to make them odd again. */
1540 mips16_mark_labels (void)
1542 if (mips_opts
.mips16
)
1544 struct insn_label_list
*l
;
1547 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1550 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1551 S_SET_OTHER (l
->label
, STO_MIPS16
);
1553 val
= S_GET_VALUE (l
->label
);
1555 S_SET_VALUE (l
->label
, val
+ 1);
1560 /* End the current frag. Make it a variant frag and record the
1564 relax_close_frag (void)
1566 mips_macro_warning
.first_frag
= frag_now
;
1567 frag_var (rs_machine_dependent
, 0, 0,
1568 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1569 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1571 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1572 mips_relax
.first_fixup
= 0;
1575 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1576 See the comment above RELAX_ENCODE for more details. */
1579 relax_start (symbolS
*symbol
)
1581 assert (mips_relax
.sequence
== 0);
1582 mips_relax
.sequence
= 1;
1583 mips_relax
.symbol
= symbol
;
1586 /* Start generating the second version of a relaxable sequence.
1587 See the comment above RELAX_ENCODE for more details. */
1592 assert (mips_relax
.sequence
== 1);
1593 mips_relax
.sequence
= 2;
1596 /* End the current relaxable sequence. */
1601 assert (mips_relax
.sequence
== 2);
1602 relax_close_frag ();
1603 mips_relax
.sequence
= 0;
1606 /* Output an instruction. IP is the instruction information.
1607 ADDRESS_EXPR is an operand of the instruction to be used with
1611 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1612 bfd_reloc_code_real_type
*reloc_type
)
1614 register unsigned long prev_pinfo
, pinfo
;
1618 relax_stateT prev_insn_frag_type
= 0;
1619 bfd_boolean relaxed_branch
= FALSE
;
1620 bfd_boolean force_new_frag
= FALSE
;
1622 /* Mark instruction labels in mips16 mode. */
1623 mips16_mark_labels ();
1625 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1626 pinfo
= ip
->insn_mo
->pinfo
;
1628 if (mips_relax
.sequence
!= 2
1629 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1633 /* If the previous insn required any delay slots, see if we need
1634 to insert a NOP or two. There are eight kinds of possible
1635 hazards, of which an instruction can have at most one type.
1636 (1) a load from memory delay
1637 (2) a load from a coprocessor delay
1638 (3) an unconditional branch delay
1639 (4) a conditional branch delay
1640 (5) a move to coprocessor register delay
1641 (6) a load coprocessor register from memory delay
1642 (7) a coprocessor condition code delay
1643 (8) a HI/LO special register delay
1645 There are a lot of optimizations we could do that we don't.
1646 In particular, we do not, in general, reorder instructions.
1647 If you use gcc with optimization, it will reorder
1648 instructions and generally do much more optimization then we
1649 do here; repeating all that work in the assembler would only
1650 benefit hand written assembly code, and does not seem worth
1653 /* This is how a NOP is emitted. */
1654 #define emit_nop() \
1656 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1657 : md_number_to_chars (frag_more (4), 0, 4))
1659 /* The previous insn might require a delay slot, depending upon
1660 the contents of the current insn. */
1661 if (! mips_opts
.mips16
1662 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1663 && ! gpr_interlocks
)
1664 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1665 && ! cop_interlocks
)))
1667 /* A load from a coprocessor or from memory. All load
1668 delays delay the use of general register rt for one
1670 /* Itbl support may require additional care here. */
1671 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1672 if (mips_optimize
== 0
1673 || insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1679 else if (! mips_opts
.mips16
1680 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1681 && ! cop_interlocks
)
1682 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1683 && ! cop_mem_interlocks
)))
1685 /* A generic coprocessor delay. The previous instruction
1686 modified a coprocessor general or control register. If
1687 it modified a control register, we need to avoid any
1688 coprocessor instruction (this is probably not always
1689 required, but it sometimes is). If it modified a general
1690 register, we avoid using that register.
1692 This case is not handled very well. There is no special
1693 knowledge of CP0 handling, and the coprocessors other
1694 than the floating point unit are not distinguished at
1696 /* Itbl support may require additional care here. FIXME!
1697 Need to modify this to include knowledge about
1698 user specified delays! */
1699 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1701 if (mips_optimize
== 0
1702 || insn_uses_reg (ip
,
1703 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1708 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1719 /* We don't know exactly what the previous instruction
1720 does. If the current instruction uses a coprocessor
1721 register, we must insert a NOP. If previous
1722 instruction may set the condition codes, and the
1723 current instruction uses them, we must insert two
1725 /* Itbl support may require additional care here. */
1726 if (mips_optimize
== 0
1727 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1728 && (pinfo
& INSN_READ_COND_CODE
)))
1730 else if (pinfo
& INSN_COP
)
1734 else if (! mips_opts
.mips16
1735 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1736 && ! cop_interlocks
)
1738 /* The previous instruction sets the coprocessor condition
1739 codes, but does not require a general coprocessor delay
1740 (this means it is a floating point comparison
1741 instruction). If this instruction uses the condition
1742 codes, we need to insert a single NOP. */
1743 /* Itbl support may require additional care here. */
1744 if (mips_optimize
== 0
1745 || (pinfo
& INSN_READ_COND_CODE
))
1749 /* If we're fixing up mfhi/mflo for the r7000 and the
1750 previous insn was an mfhi/mflo and the current insn
1751 reads the register that the mfhi/mflo wrote to, then
1754 else if (mips_7000_hilo_fix
1755 && MF_HILO_INSN (prev_pinfo
)
1756 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1763 /* If we're fixing up mfhi/mflo for the r7000 and the
1764 2nd previous insn was an mfhi/mflo and the current insn
1765 reads the register that the mfhi/mflo wrote to, then
1768 else if (mips_7000_hilo_fix
1769 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1770 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1778 else if (prev_pinfo
& INSN_READ_LO
)
1780 /* The previous instruction reads the LO register; if the
1781 current instruction writes to the LO register, we must
1782 insert two NOPS. Some newer processors have interlocks.
1783 Also the tx39's multiply instructions can be executed
1784 immediately after a read from HI/LO (without the delay),
1785 though the tx39's divide insns still do require the
1787 if (! (hilo_interlocks
1788 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1789 && (mips_optimize
== 0
1790 || (pinfo
& INSN_WRITE_LO
)))
1792 /* Most mips16 branch insns don't have a delay slot.
1793 If a read from LO is immediately followed by a branch
1794 to a write to LO we have a read followed by a write
1795 less than 2 insns away. We assume the target of
1796 a branch might be a write to LO, and insert a nop
1797 between a read and an immediately following branch. */
1798 else if (mips_opts
.mips16
1799 && (mips_optimize
== 0
1800 || (pinfo
& MIPS16_INSN_BRANCH
)))
1803 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1805 /* The previous instruction reads the HI register; if the
1806 current instruction writes to the HI register, we must
1807 insert a NOP. Some newer processors have interlocks.
1808 Also the note tx39's multiply above. */
1809 if (! (hilo_interlocks
1810 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1811 && (mips_optimize
== 0
1812 || (pinfo
& INSN_WRITE_HI
)))
1814 /* Most mips16 branch insns don't have a delay slot.
1815 If a read from HI is immediately followed by a branch
1816 to a write to HI we have a read followed by a write
1817 less than 2 insns away. We assume the target of
1818 a branch might be a write to HI, and insert a nop
1819 between a read and an immediately following branch. */
1820 else if (mips_opts
.mips16
1821 && (mips_optimize
== 0
1822 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 /* If the previous instruction was in a noreorder section, then
1827 we don't want to insert the nop after all. */
1828 /* Itbl support may require additional care here. */
1829 if (prev_insn_unreordered
)
1832 /* There are two cases which require two intervening
1833 instructions: 1) setting the condition codes using a move to
1834 coprocessor instruction which requires a general coprocessor
1835 delay and then reading the condition codes 2) reading the HI
1836 or LO register and then writing to it (except on processors
1837 which have interlocks). If we are not already emitting a NOP
1838 instruction, we must check for these cases compared to the
1839 instruction previous to the previous instruction. */
1840 if ((! mips_opts
.mips16
1841 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1842 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1843 && (pinfo
& INSN_READ_COND_CODE
)
1844 && ! cop_interlocks
)
1845 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1846 && (pinfo
& INSN_WRITE_LO
)
1847 && ! (hilo_interlocks
1848 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1849 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1850 && (pinfo
& INSN_WRITE_HI
)
1851 && ! (hilo_interlocks
1852 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1857 if (prev_prev_insn_unreordered
)
1860 if (prev_prev_nop
&& nops
== 0)
1863 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1865 /* We're out of bits in pinfo, so we must resort to string
1866 ops here. Shortcuts are selected based on opcodes being
1867 limited to the VR4120 instruction set. */
1869 const char *pn
= prev_insn
.insn_mo
->name
;
1870 const char *tn
= ip
->insn_mo
->name
;
1871 if (strncmp (pn
, "macc", 4) == 0
1872 || strncmp (pn
, "dmacc", 5) == 0)
1874 /* Errata 21 - [D]DIV[U] after [D]MACC */
1875 if (strstr (tn
, "div"))
1878 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1879 instruction is executed immediately after a MACC or
1880 DMACC instruction, the result of [either instruction]
1882 if (strncmp (tn
, "mult", 4) == 0
1883 || strncmp (tn
, "dmult", 5) == 0)
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1887 Applies on top of VR4181A MD(1) errata. */
1888 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1891 /* Errata 24 - MT{LO,HI} after [D]MACC */
1892 if (strcmp (tn
, "mtlo") == 0
1893 || strcmp (tn
, "mthi") == 0)
1896 else if (strncmp (pn
, "dmult", 5) == 0
1897 && (strncmp (tn
, "dmult", 5) == 0
1898 || strncmp (tn
, "dmacc", 5) == 0))
1900 /* Here is the rest of errata 23. */
1903 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1904 && (strncmp (tn
, "macc", 4) == 0
1905 || strncmp (tn
, "dmacc", 5) == 0))
1907 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1908 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1909 DDIV or DDIVU instruction, the result of the MACC or
1910 DMACC instruction is incorrect.". This partly overlaps
1911 the workaround for errata 23. */
1914 if (nops
< min_nops
)
1918 /* If we are being given a nop instruction, don't bother with
1919 one of the nops we would otherwise output. This will only
1920 happen when a nop instruction is used with mips_optimize set
1923 && ! mips_opts
.noreorder
1924 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1927 /* Now emit the right number of NOP instructions. */
1928 if (nops
> 0 && ! mips_opts
.noreorder
)
1931 unsigned long old_frag_offset
;
1933 struct insn_label_list
*l
;
1935 old_frag
= frag_now
;
1936 old_frag_offset
= frag_now_fix ();
1938 for (i
= 0; i
< nops
; i
++)
1943 listing_prev_line ();
1944 /* We may be at the start of a variant frag. In case we
1945 are, make sure there is enough space for the frag
1946 after the frags created by listing_prev_line. The
1947 argument to frag_grow here must be at least as large
1948 as the argument to all other calls to frag_grow in
1949 this file. We don't have to worry about being in the
1950 middle of a variant frag, because the variants insert
1951 all needed nop instructions themselves. */
1955 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1959 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1960 symbol_set_frag (l
->label
, frag_now
);
1961 val
= (valueT
) frag_now_fix ();
1962 /* mips16 text labels are stored as odd. */
1963 if (mips_opts
.mips16
)
1965 S_SET_VALUE (l
->label
, val
);
1968 #ifndef NO_ECOFF_DEBUGGING
1969 if (ECOFF_DEBUGGING
)
1970 ecoff_fix_loc (old_frag
, old_frag_offset
);
1973 else if (prev_nop_frag
!= NULL
)
1975 /* We have a frag holding nops we may be able to remove. If
1976 we don't need any nops, we can decrease the size of
1977 prev_nop_frag by the size of one instruction. If we do
1978 need some nops, we count them in prev_nops_required. */
1979 if (prev_nop_frag_since
== 0)
1983 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1984 --prev_nop_frag_holds
;
1987 prev_nop_frag_required
+= nops
;
1991 if (prev_prev_nop
== 0)
1993 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1994 --prev_nop_frag_holds
;
1997 ++prev_nop_frag_required
;
2000 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2001 prev_nop_frag
= NULL
;
2003 ++prev_nop_frag_since
;
2005 /* Sanity check: by the time we reach the second instruction
2006 after prev_nop_frag, we should have used up all the nops
2007 one way or another. */
2008 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2013 /* The value passed to dwarf2_emit_insn is the distance between
2014 the beginning of the current instruction and the address that
2015 should be recorded in the debug tables. For MIPS16 debug info
2016 we want to use ISA-encoded addresses, so we pass -1 for an
2017 address higher by one than the current. */
2018 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2021 /* Record the frag type before frag_var. */
2023 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2026 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2027 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2028 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2029 && mips_relax_branch
2030 /* Don't try branch relaxation within .set nomacro, or within
2031 .set noat if we use $at for PIC computations. If it turns
2032 out that the branch was out-of-range, we'll get an error. */
2033 && !mips_opts
.warn_about_macros
2034 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2035 && !mips_opts
.mips16
)
2037 relaxed_branch
= TRUE
;
2038 f
= frag_var (rs_machine_dependent
,
2039 relaxed_branch_length
2041 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2042 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2044 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2045 pinfo
& INSN_COND_BRANCH_LIKELY
,
2046 pinfo
& INSN_WRITE_GPR_31
,
2048 address_expr
->X_add_symbol
,
2049 address_expr
->X_add_number
,
2051 *reloc_type
= BFD_RELOC_UNUSED
;
2053 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2055 /* We need to set up a variant frag. */
2056 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2057 f
= frag_var (rs_machine_dependent
, 4, 0,
2058 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2059 mips16_small
, mips16_ext
,
2061 & INSN_UNCOND_BRANCH_DELAY
),
2062 (*prev_insn_reloc_type
2063 == BFD_RELOC_MIPS16_JMP
)),
2064 make_expr_symbol (address_expr
), 0, NULL
);
2066 else if (mips_opts
.mips16
2068 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2070 /* Make sure there is enough room to swap this instruction with
2071 a following jump instruction. */
2077 if (mips_opts
.mips16
2078 && mips_opts
.noreorder
2079 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2080 as_warn (_("extended instruction in delay slot"));
2082 if (mips_relax
.sequence
)
2084 /* If we've reached the end of this frag, turn it into a variant
2085 frag and record the information for the instructions we've
2087 if (frag_room () < 4)
2088 relax_close_frag ();
2089 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2092 if (mips_relax
.sequence
!= 2)
2093 mips_macro_warning
.sizes
[0] += 4;
2094 if (mips_relax
.sequence
!= 1)
2095 mips_macro_warning
.sizes
[1] += 4;
2100 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2101 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2103 if (address_expr
->X_op
== O_constant
)
2107 switch (*reloc_type
)
2110 ip
->insn_opcode
|= address_expr
->X_add_number
;
2113 case BFD_RELOC_MIPS_HIGHEST
:
2114 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2115 ip
->insn_opcode
|= tmp
& 0xffff;
2118 case BFD_RELOC_MIPS_HIGHER
:
2119 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2120 ip
->insn_opcode
|= tmp
& 0xffff;
2123 case BFD_RELOC_HI16_S
:
2124 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2125 ip
->insn_opcode
|= tmp
& 0xffff;
2128 case BFD_RELOC_HI16
:
2129 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2132 case BFD_RELOC_UNUSED
:
2133 case BFD_RELOC_LO16
:
2134 case BFD_RELOC_MIPS_GOT_DISP
:
2135 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2138 case BFD_RELOC_MIPS_JMP
:
2139 if ((address_expr
->X_add_number
& 3) != 0)
2140 as_bad (_("jump to misaligned address (0x%lx)"),
2141 (unsigned long) address_expr
->X_add_number
);
2142 if (address_expr
->X_add_number
& ~0xfffffff)
2143 as_bad (_("jump address range overflow (0x%lx)"),
2144 (unsigned long) address_expr
->X_add_number
);
2145 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2148 case BFD_RELOC_MIPS16_JMP
:
2149 if ((address_expr
->X_add_number
& 3) != 0)
2150 as_bad (_("jump to misaligned address (0x%lx)"),
2151 (unsigned long) address_expr
->X_add_number
);
2152 if (address_expr
->X_add_number
& ~0xfffffff)
2153 as_bad (_("jump address range overflow (0x%lx)"),
2154 (unsigned long) address_expr
->X_add_number
);
2156 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2157 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2158 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2161 case BFD_RELOC_16_PCREL_S2
:
2168 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2171 reloc_howto_type
*howto
;
2174 /* In a compound relocation, it is the final (outermost)
2175 operator that determines the relocated field. */
2176 for (i
= 1; i
< 3; i
++)
2177 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2180 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2181 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2182 bfd_get_reloc_size(howto
),
2184 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2187 /* These relocations can have an addend that won't fit in
2188 4 octets for 64bit assembly. */
2190 && ! howto
->partial_inplace
2191 && (reloc_type
[0] == BFD_RELOC_16
2192 || reloc_type
[0] == BFD_RELOC_32
2193 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2194 || reloc_type
[0] == BFD_RELOC_HI16_S
2195 || reloc_type
[0] == BFD_RELOC_LO16
2196 || reloc_type
[0] == BFD_RELOC_GPREL16
2197 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2198 || reloc_type
[0] == BFD_RELOC_GPREL32
2199 || reloc_type
[0] == BFD_RELOC_64
2200 || reloc_type
[0] == BFD_RELOC_CTOR
2201 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2202 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2203 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2204 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2205 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2206 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2207 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2208 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2209 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2210 fixp
[0]->fx_no_overflow
= 1;
2212 if (mips_relax
.sequence
)
2214 if (mips_relax
.first_fixup
== 0)
2215 mips_relax
.first_fixup
= fixp
[0];
2217 else if (reloc_needs_lo_p (*reloc_type
))
2219 struct mips_hi_fixup
*hi_fixup
;
2221 /* Reuse the last entry if it already has a matching %lo. */
2222 hi_fixup
= mips_hi_fixup_list
;
2224 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2226 hi_fixup
= ((struct mips_hi_fixup
*)
2227 xmalloc (sizeof (struct mips_hi_fixup
)));
2228 hi_fixup
->next
= mips_hi_fixup_list
;
2229 mips_hi_fixup_list
= hi_fixup
;
2231 hi_fixup
->fixp
= fixp
[0];
2232 hi_fixup
->seg
= now_seg
;
2235 /* Add fixups for the second and third relocations, if given.
2236 Note that the ABI allows the second relocation to be
2237 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2238 moment we only use RSS_UNDEF, but we could add support
2239 for the others if it ever becomes necessary. */
2240 for (i
= 1; i
< 3; i
++)
2241 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2243 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2244 fixp
[0]->fx_size
, NULL
, 0,
2245 FALSE
, reloc_type
[i
]);
2247 /* Use fx_tcbit to mark compound relocs. */
2248 fixp
[0]->fx_tcbit
= 1;
2249 fixp
[i
]->fx_tcbit
= 1;
2254 if (! mips_opts
.mips16
)
2255 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2256 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2258 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2259 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2265 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2268 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2271 /* Update the register mask information. */
2272 if (! mips_opts
.mips16
)
2274 if (pinfo
& INSN_WRITE_GPR_D
)
2275 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2276 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2277 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2278 if (pinfo
& INSN_READ_GPR_S
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2280 if (pinfo
& INSN_WRITE_GPR_31
)
2281 mips_gprmask
|= 1 << RA
;
2282 if (pinfo
& INSN_WRITE_FPR_D
)
2283 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2284 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2285 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2286 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2287 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2288 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2289 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2290 if (pinfo
& INSN_COP
)
2292 /* We don't keep enough information to sort these cases out.
2293 The itbl support does keep this information however, although
2294 we currently don't support itbl fprmats as part of the cop
2295 instruction. May want to add this support in the future. */
2297 /* Never set the bit for $0, which is always zero. */
2298 mips_gprmask
&= ~1 << 0;
2302 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2303 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2304 & MIPS16OP_MASK_RX
);
2305 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2306 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2307 & MIPS16OP_MASK_RY
);
2308 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2309 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2310 & MIPS16OP_MASK_RZ
);
2311 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2312 mips_gprmask
|= 1 << TREG
;
2313 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2314 mips_gprmask
|= 1 << SP
;
2315 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2316 mips_gprmask
|= 1 << RA
;
2317 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2318 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2319 if (pinfo
& MIPS16_INSN_READ_Z
)
2320 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2321 & MIPS16OP_MASK_MOVE32Z
);
2322 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2323 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2324 & MIPS16OP_MASK_REGR32
);
2327 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2329 /* Filling the branch delay slot is more complex. We try to
2330 switch the branch with the previous instruction, which we can
2331 do if the previous instruction does not set up a condition
2332 that the branch tests and if the branch is not itself the
2333 target of any branch. */
2334 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2335 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2337 if (mips_optimize
< 2
2338 /* If we have seen .set volatile or .set nomove, don't
2340 || mips_opts
.nomove
!= 0
2341 /* If we had to emit any NOP instructions, then we
2342 already know we can not swap. */
2344 /* If we don't even know the previous insn, we can not
2346 || ! prev_insn_valid
2347 /* If the previous insn is already in a branch delay
2348 slot, then we can not swap. */
2349 || prev_insn_is_delay_slot
2350 /* If the previous previous insn was in a .set
2351 noreorder, we can't swap. Actually, the MIPS
2352 assembler will swap in this situation. However, gcc
2353 configured -with-gnu-as will generate code like
2359 in which we can not swap the bne and INSN. If gcc is
2360 not configured -with-gnu-as, it does not output the
2361 .set pseudo-ops. We don't have to check
2362 prev_insn_unreordered, because prev_insn_valid will
2363 be 0 in that case. We don't want to use
2364 prev_prev_insn_valid, because we do want to be able
2365 to swap at the start of a function. */
2366 || prev_prev_insn_unreordered
2367 /* If the branch is itself the target of a branch, we
2368 can not swap. We cheat on this; all we check for is
2369 whether there is a label on this instruction. If
2370 there are any branches to anything other than a
2371 label, users must use .set noreorder. */
2372 || insn_labels
!= NULL
2373 /* If the previous instruction is in a variant frag
2374 other than this branch's one, we cannot do the swap.
2375 This does not apply to the mips16, which uses variant
2376 frags for different purposes. */
2377 || (! mips_opts
.mips16
2378 && prev_insn_frag_type
== rs_machine_dependent
)
2379 /* If the branch reads the condition codes, we don't
2380 even try to swap, because in the sequence
2385 we can not swap, and I don't feel like handling that
2387 || (! mips_opts
.mips16
2388 && (pinfo
& INSN_READ_COND_CODE
)
2389 && ! cop_interlocks
)
2390 /* We can not swap with an instruction that requires a
2391 delay slot, because the target of the branch might
2392 interfere with that instruction. */
2393 || (! mips_opts
.mips16
2395 /* Itbl support may require additional care here. */
2396 & (INSN_LOAD_COPROC_DELAY
2397 | INSN_COPROC_MOVE_DELAY
2398 | INSN_WRITE_COND_CODE
))
2399 && ! cop_interlocks
)
2400 || (! (hilo_interlocks
2401 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2405 || (! mips_opts
.mips16
2406 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2407 && ! gpr_interlocks
)
2408 || (! mips_opts
.mips16
2409 /* Itbl support may require additional care here. */
2410 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2411 && ! cop_mem_interlocks
)
2412 /* We can not swap with a branch instruction. */
2414 & (INSN_UNCOND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_DELAY
2416 | INSN_COND_BRANCH_LIKELY
))
2417 /* We do not swap with a trap instruction, since it
2418 complicates trap handlers to have the trap
2419 instruction be in a delay slot. */
2420 || (prev_pinfo
& INSN_TRAP
)
2421 /* If the branch reads a register that the previous
2422 instruction sets, we can not swap. */
2423 || (! mips_opts
.mips16
2424 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2425 && insn_uses_reg (ip
,
2426 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2429 || (! mips_opts
.mips16
2430 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2431 && insn_uses_reg (ip
,
2432 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2435 || (mips_opts
.mips16
2436 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2437 && insn_uses_reg (ip
,
2438 ((prev_insn
.insn_opcode
2440 & MIPS16OP_MASK_RX
),
2442 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2443 && insn_uses_reg (ip
,
2444 ((prev_insn
.insn_opcode
2446 & MIPS16OP_MASK_RY
),
2448 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2449 && insn_uses_reg (ip
,
2450 ((prev_insn
.insn_opcode
2452 & MIPS16OP_MASK_RZ
),
2454 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2455 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2456 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2457 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2459 && insn_uses_reg (ip
,
2460 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2463 /* If the branch writes a register that the previous
2464 instruction sets, we can not swap (we know that
2465 branches write only to RD or to $31). */
2466 || (! mips_opts
.mips16
2467 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2468 && (((pinfo
& INSN_WRITE_GPR_D
)
2469 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2470 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2471 || ((pinfo
& INSN_WRITE_GPR_31
)
2472 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2475 || (! mips_opts
.mips16
2476 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2477 && (((pinfo
& INSN_WRITE_GPR_D
)
2478 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2479 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2480 || ((pinfo
& INSN_WRITE_GPR_31
)
2481 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2484 || (mips_opts
.mips16
2485 && (pinfo
& MIPS16_INSN_WRITE_31
)
2486 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2487 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2488 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2490 /* If the branch writes a register that the previous
2491 instruction reads, we can not swap (we know that
2492 branches only write to RD or to $31). */
2493 || (! mips_opts
.mips16
2494 && (pinfo
& INSN_WRITE_GPR_D
)
2495 && insn_uses_reg (&prev_insn
,
2496 ((ip
->insn_opcode
>> OP_SH_RD
)
2499 || (! mips_opts
.mips16
2500 && (pinfo
& INSN_WRITE_GPR_31
)
2501 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2502 || (mips_opts
.mips16
2503 && (pinfo
& MIPS16_INSN_WRITE_31
)
2504 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts
.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2511 && ! cop_interlocks
)
2512 || ((prev_prev_insn
.insn_mo
->pinfo
2513 & INSN_LOAD_MEMORY_DELAY
)
2514 && ! gpr_interlocks
))
2515 && insn_uses_reg (ip
,
2516 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo
& INSN_READ_COND_CODE
)
2522 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2523 || ((pinfo
& INSN_WRITE_COND_CODE
)
2524 && (prev_pinfo
& INSN_READ_COND_CODE
))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts
.mips16
2528 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts
.mips16
&& prev_insn_extended
)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo
& INSN_SYNC
))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 if (mips_relax
.sequence
)
2546 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2547 /* Update the previous insn information. */
2548 prev_prev_insn
= *ip
;
2549 prev_insn
.insn_mo
= &dummy_opcode
;
2553 /* It looks like we can actually do the swap. */
2554 if (! mips_opts
.mips16
)
2559 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2560 if (!relaxed_branch
)
2562 /* If this is not a relaxed branch, then just
2563 swap the instructions. */
2564 memcpy (temp
, prev_f
, 4);
2565 memcpy (prev_f
, f
, 4);
2566 memcpy (f
, temp
, 4);
2570 /* If this is a relaxed branch, then we move the
2571 instruction to be placed in the delay slot to
2572 the current frag, shrinking the fixed part of
2573 the originating frag. If the branch occupies
2574 the tail of the latter, we move it backwards,
2575 into the space freed by the moved instruction. */
2577 memcpy (f
, prev_f
, 4);
2578 prev_insn_frag
->fr_fix
-= 4;
2579 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2580 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2583 if (prev_insn_fixp
[0])
2585 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2586 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2588 if (prev_insn_fixp
[1])
2590 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2591 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2593 if (prev_insn_fixp
[2])
2595 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2596 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2598 if (prev_insn_fixp
[0] && HAVE_NEWABI
2599 && prev_insn_frag
!= frag_now
2600 && (prev_insn_fixp
[0]->fx_r_type
2601 == BFD_RELOC_MIPS_GOT_DISP
2602 || (prev_insn_fixp
[0]->fx_r_type
2603 == BFD_RELOC_MIPS_CALL16
)))
2605 /* To avoid confusion in tc_gen_reloc, we must
2606 ensure that this does not become a variant
2608 force_new_frag
= TRUE
;
2611 if (!relaxed_branch
)
2615 fixp
[0]->fx_frag
= prev_insn_frag
;
2616 fixp
[0]->fx_where
= prev_insn_where
;
2620 fixp
[1]->fx_frag
= prev_insn_frag
;
2621 fixp
[1]->fx_where
= prev_insn_where
;
2625 fixp
[2]->fx_frag
= prev_insn_frag
;
2626 fixp
[2]->fx_where
= prev_insn_where
;
2629 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2632 fixp
[0]->fx_where
-= 4;
2634 fixp
[1]->fx_where
-= 4;
2636 fixp
[2]->fx_where
-= 4;
2644 assert (prev_insn_fixp
[0] == NULL
);
2645 assert (prev_insn_fixp
[1] == NULL
);
2646 assert (prev_insn_fixp
[2] == NULL
);
2647 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2648 memcpy (temp
, prev_f
, 2);
2649 memcpy (prev_f
, f
, 2);
2650 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2652 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2653 memcpy (f
, temp
, 2);
2657 memcpy (f
, f
+ 2, 2);
2658 memcpy (f
+ 2, temp
, 2);
2662 fixp
[0]->fx_frag
= prev_insn_frag
;
2663 fixp
[0]->fx_where
= prev_insn_where
;
2667 fixp
[1]->fx_frag
= prev_insn_frag
;
2668 fixp
[1]->fx_where
= prev_insn_where
;
2672 fixp
[2]->fx_frag
= prev_insn_frag
;
2673 fixp
[2]->fx_where
= prev_insn_where
;
2677 /* Update the previous insn information; leave prev_insn
2679 prev_prev_insn
= *ip
;
2681 prev_insn_is_delay_slot
= 1;
2683 /* If that was an unconditional branch, forget the previous
2684 insn information. */
2685 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2687 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2688 prev_insn
.insn_mo
= &dummy_opcode
;
2691 prev_insn_fixp
[0] = NULL
;
2692 prev_insn_fixp
[1] = NULL
;
2693 prev_insn_fixp
[2] = NULL
;
2694 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2695 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2696 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2697 prev_insn_extended
= 0;
2699 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2701 /* We don't yet optimize a branch likely. What we should do
2702 is look at the target, copy the instruction found there
2703 into the delay slot, and increment the branch to jump to
2704 the next instruction. */
2706 /* Update the previous insn information. */
2707 prev_prev_insn
= *ip
;
2708 prev_insn
.insn_mo
= &dummy_opcode
;
2709 prev_insn_fixp
[0] = NULL
;
2710 prev_insn_fixp
[1] = NULL
;
2711 prev_insn_fixp
[2] = NULL
;
2712 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2713 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2714 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2715 prev_insn_extended
= 0;
2716 prev_insn_is_delay_slot
= 1;
2720 /* Update the previous insn information. */
2722 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2724 prev_prev_insn
= prev_insn
;
2727 /* Any time we see a branch, we always fill the delay slot
2728 immediately; since this insn is not a branch, we know it
2729 is not in a delay slot. */
2730 prev_insn_is_delay_slot
= 0;
2732 prev_insn_fixp
[0] = fixp
[0];
2733 prev_insn_fixp
[1] = fixp
[1];
2734 prev_insn_fixp
[2] = fixp
[2];
2735 prev_insn_reloc_type
[0] = reloc_type
[0];
2736 prev_insn_reloc_type
[1] = reloc_type
[1];
2737 prev_insn_reloc_type
[2] = reloc_type
[2];
2738 if (mips_opts
.mips16
)
2739 prev_insn_extended
= (ip
->use_extend
2740 || *reloc_type
> BFD_RELOC_UNUSED
);
2743 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2744 prev_insn_unreordered
= 0;
2745 prev_insn_frag
= frag_now
;
2746 prev_insn_where
= f
- frag_now
->fr_literal
;
2747 prev_insn_valid
= 1;
2749 else if (mips_relax
.sequence
!= 2)
2751 /* We need to record a bit of information even when we are not
2752 reordering, in order to determine the base address for mips16
2753 PC relative relocs. */
2754 prev_prev_insn
= prev_insn
;
2756 prev_insn_reloc_type
[0] = reloc_type
[0];
2757 prev_insn_reloc_type
[1] = reloc_type
[1];
2758 prev_insn_reloc_type
[2] = reloc_type
[2];
2759 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2760 prev_insn_unreordered
= 1;
2763 /* We just output an insn, so the next one doesn't have a label. */
2764 mips_clear_insn_labels ();
2767 /* This function forgets that there was any previous instruction or
2768 label. If PRESERVE is non-zero, it remembers enough information to
2769 know whether nops are needed before a noreorder section. */
2772 mips_no_prev_insn (int preserve
)
2776 prev_insn
.insn_mo
= &dummy_opcode
;
2777 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2778 prev_nop_frag
= NULL
;
2779 prev_nop_frag_holds
= 0;
2780 prev_nop_frag_required
= 0;
2781 prev_nop_frag_since
= 0;
2783 prev_insn_valid
= 0;
2784 prev_insn_is_delay_slot
= 0;
2785 prev_insn_unreordered
= 0;
2786 prev_insn_extended
= 0;
2787 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2788 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2789 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2790 prev_prev_insn_unreordered
= 0;
2791 mips_clear_insn_labels ();
2794 /* This function must be called whenever we turn on noreorder or emit
2795 something other than instructions. It inserts any NOPS which might
2796 be needed by the previous instruction, and clears the information
2797 kept for the previous instructions. The INSNS parameter is true if
2798 instructions are to follow. */
2801 mips_emit_delays (bfd_boolean insns
)
2803 if (! mips_opts
.noreorder
)
2808 if ((! mips_opts
.mips16
2809 && ((prev_insn
.insn_mo
->pinfo
2810 & (INSN_LOAD_COPROC_DELAY
2811 | INSN_COPROC_MOVE_DELAY
2812 | INSN_WRITE_COND_CODE
))
2813 && ! cop_interlocks
))
2814 || (! hilo_interlocks
2815 && (prev_insn
.insn_mo
->pinfo
2818 || (! mips_opts
.mips16
2819 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2820 && ! gpr_interlocks
)
2821 || (! mips_opts
.mips16
2822 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2823 && ! cop_mem_interlocks
))
2825 /* Itbl support may require additional care here. */
2827 if ((! mips_opts
.mips16
2828 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2829 && ! cop_interlocks
))
2830 || (! hilo_interlocks
2831 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2832 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2835 if (prev_insn_unreordered
)
2838 else if ((! mips_opts
.mips16
2839 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2840 && ! cop_interlocks
))
2841 || (! hilo_interlocks
2842 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2843 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2845 /* Itbl support may require additional care here. */
2846 if (! prev_prev_insn_unreordered
)
2850 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2853 const char *pn
= prev_insn
.insn_mo
->name
;
2854 if (strncmp (pn
, "macc", 4) == 0
2855 || strncmp (pn
, "dmacc", 5) == 0
2856 || strncmp (pn
, "dmult", 5) == 0
2857 || strstr (pn
, "div"))
2859 if (nops
< min_nops
)
2865 struct insn_label_list
*l
;
2869 /* Record the frag which holds the nop instructions, so
2870 that we can remove them if we don't need them. */
2871 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2872 prev_nop_frag
= frag_now
;
2873 prev_nop_frag_holds
= nops
;
2874 prev_nop_frag_required
= 0;
2875 prev_nop_frag_since
= 0;
2878 for (; nops
> 0; --nops
)
2883 /* Move on to a new frag, so that it is safe to simply
2884 decrease the size of prev_nop_frag. */
2885 frag_wane (frag_now
);
2889 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2893 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2894 symbol_set_frag (l
->label
, frag_now
);
2895 val
= (valueT
) frag_now_fix ();
2896 /* mips16 text labels are stored as odd. */
2897 if (mips_opts
.mips16
)
2899 S_SET_VALUE (l
->label
, val
);
2904 /* Mark instruction labels in mips16 mode. */
2906 mips16_mark_labels ();
2908 mips_no_prev_insn (insns
);
2911 /* Set up global variables for the start of a new macro. */
2916 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2917 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2918 && (prev_insn
.insn_mo
->pinfo
2919 & (INSN_UNCOND_BRANCH_DELAY
2920 | INSN_COND_BRANCH_DELAY
2921 | INSN_COND_BRANCH_LIKELY
)) != 0);
2924 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2925 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2926 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2929 macro_warning (relax_substateT subtype
)
2931 if (subtype
& RELAX_DELAY_SLOT
)
2932 return _("Macro instruction expanded into multiple instructions"
2933 " in a branch delay slot");
2934 else if (subtype
& RELAX_NOMACRO
)
2935 return _("Macro instruction expanded into multiple instructions");
2940 /* Finish up a macro. Emit warnings as appropriate. */
2945 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2947 relax_substateT subtype
;
2949 /* Set up the relaxation warning flags. */
2951 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2952 subtype
|= RELAX_SECOND_LONGER
;
2953 if (mips_opts
.warn_about_macros
)
2954 subtype
|= RELAX_NOMACRO
;
2955 if (mips_macro_warning
.delay_slot_p
)
2956 subtype
|= RELAX_DELAY_SLOT
;
2958 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2960 /* Either the macro has a single implementation or both
2961 implementations are longer than 4 bytes. Emit the
2963 const char *msg
= macro_warning (subtype
);
2969 /* One implementation might need a warning but the other
2970 definitely doesn't. */
2971 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2976 /* Read a macro's relocation codes from *ARGS and store them in *R.
2977 The first argument in *ARGS will be either the code for a single
2978 relocation or -1 followed by the three codes that make up a
2979 composite relocation. */
2982 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2986 next
= va_arg (*args
, int);
2988 r
[0] = (bfd_reloc_code_real_type
) next
;
2990 for (i
= 0; i
< 3; i
++)
2991 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2994 /* Build an instruction created by a macro expansion. This is passed
2995 a pointer to the count of instructions created so far, an
2996 expression, the name of the instruction to build, an operand format
2997 string, and corresponding arguments. */
3000 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3002 struct mips_cl_insn insn
;
3003 bfd_reloc_code_real_type r
[3];
3006 va_start (args
, fmt
);
3008 if (mips_opts
.mips16
)
3010 mips16_macro_build (ep
, name
, fmt
, args
);
3015 r
[0] = BFD_RELOC_UNUSED
;
3016 r
[1] = BFD_RELOC_UNUSED
;
3017 r
[2] = BFD_RELOC_UNUSED
;
3018 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3019 assert (insn
.insn_mo
);
3020 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3022 /* Search until we get a match for NAME. */
3025 /* It is assumed here that macros will never generate
3026 MDMX or MIPS-3D instructions. */
3027 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3028 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3029 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3031 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3033 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3037 assert (insn
.insn_mo
->name
);
3038 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3041 insn
.insn_opcode
= insn
.insn_mo
->match
;
3059 insn
.insn_opcode
|= (va_arg (args
, int)
3060 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3065 /* Note that in the macro case, these arguments are already
3066 in MSB form. (When handling the instruction in the
3067 non-macro case, these arguments are sizes from which
3068 MSB values must be calculated.) */
3069 insn
.insn_opcode
|= (va_arg (args
, int)
3070 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3076 /* Note that in the macro case, these arguments are already
3077 in MSBD form. (When handling the instruction in the
3078 non-macro case, these arguments are sizes from which
3079 MSBD values must be calculated.) */
3080 insn
.insn_opcode
|= (va_arg (args
, int)
3081 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3092 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3101 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3107 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3112 int tmp
= va_arg (args
, int);
3114 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3115 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3121 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3128 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3140 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3144 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3151 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3157 macro_read_relocs (&args
, r
);
3158 assert (*r
== BFD_RELOC_GPREL16
3159 || *r
== BFD_RELOC_MIPS_LITERAL
3160 || *r
== BFD_RELOC_MIPS_HIGHER
3161 || *r
== BFD_RELOC_HI16_S
3162 || *r
== BFD_RELOC_LO16
3163 || *r
== BFD_RELOC_MIPS_GOT16
3164 || *r
== BFD_RELOC_MIPS_CALL16
3165 || *r
== BFD_RELOC_MIPS_GOT_DISP
3166 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3167 || *r
== BFD_RELOC_MIPS_GOT_OFST
3168 || *r
== BFD_RELOC_MIPS_GOT_LO16
3169 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3173 macro_read_relocs (&args
, r
);
3175 && (ep
->X_op
== O_constant
3176 || (ep
->X_op
== O_symbol
3177 && (*r
== BFD_RELOC_MIPS_HIGHEST
3178 || *r
== BFD_RELOC_HI16_S
3179 || *r
== BFD_RELOC_HI16
3180 || *r
== BFD_RELOC_GPREL16
3181 || *r
== BFD_RELOC_MIPS_GOT_HI16
3182 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3186 assert (ep
!= NULL
);
3188 * This allows macro() to pass an immediate expression for
3189 * creating short branches without creating a symbol.
3190 * Note that the expression still might come from the assembly
3191 * input, in which case the value is not checked for range nor
3192 * is a relocation entry generated (yuck).
3194 if (ep
->X_op
== O_constant
)
3196 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3200 *r
= BFD_RELOC_16_PCREL_S2
;
3204 assert (ep
!= NULL
);
3205 *r
= BFD_RELOC_MIPS_JMP
;
3209 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3218 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3220 append_insn (&insn
, ep
, r
);
3224 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3227 struct mips_cl_insn insn
;
3228 bfd_reloc_code_real_type r
[3]
3229 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3231 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3232 assert (insn
.insn_mo
);
3233 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3235 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3236 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3239 assert (insn
.insn_mo
->name
);
3240 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3243 insn
.insn_opcode
= insn
.insn_mo
->match
;
3244 insn
.use_extend
= FALSE
;
3263 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3268 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3272 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3276 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3286 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3293 regno
= va_arg (args
, int);
3294 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3295 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3316 assert (ep
!= NULL
);
3318 if (ep
->X_op
!= O_constant
)
3319 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3322 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3323 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3326 *r
= BFD_RELOC_UNUSED
;
3332 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3339 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3341 append_insn (&insn
, ep
, r
);
3345 * Generate a "jalr" instruction with a relocation hint to the called
3346 * function. This occurs in NewABI PIC code.
3349 macro_build_jalr (expressionS
*ep
)
3358 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3360 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3361 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3365 * Generate a "lui" instruction.
3368 macro_build_lui (expressionS
*ep
, int regnum
)
3370 expressionS high_expr
;
3371 struct mips_cl_insn insn
;
3372 bfd_reloc_code_real_type r
[3]
3373 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3374 const char *name
= "lui";
3375 const char *fmt
= "t,u";
3377 assert (! mips_opts
.mips16
);
3381 if (high_expr
.X_op
== O_constant
)
3383 /* we can compute the instruction now without a relocation entry */
3384 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3386 *r
= BFD_RELOC_UNUSED
;
3390 assert (ep
->X_op
== O_symbol
);
3391 /* _gp_disp is a special case, used from s_cpload. _gp is used
3392 if mips_no_shared. */
3393 assert (mips_pic
== NO_PIC
3395 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3396 || (! mips_in_shared
3397 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp") == 0));
3398 *r
= BFD_RELOC_HI16_S
;
3401 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3402 assert (insn
.insn_mo
);
3403 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3404 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3406 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3407 if (*r
== BFD_RELOC_UNUSED
)
3409 insn
.insn_opcode
|= high_expr
.X_add_number
;
3410 append_insn (&insn
, NULL
, r
);
3413 append_insn (&insn
, &high_expr
, r
);
3416 /* Generate a sequence of instructions to do a load or store from a constant
3417 offset off of a base register (breg) into/from a target register (treg),
3418 using AT if necessary. */
3420 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3421 int treg
, int breg
, int dbl
)
3423 assert (ep
->X_op
== O_constant
);
3425 /* Sign-extending 32-bit constants makes their handling easier. */
3426 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3427 == ~((bfd_vma
) 0x7fffffff)))
3429 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3430 as_bad (_("constant too large"));
3432 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3436 /* Right now, this routine can only handle signed 32-bit constants. */
3437 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3438 as_warn (_("operand overflow"));
3440 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3442 /* Signed 16-bit offset will fit in the op. Easy! */
3443 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3447 /* 32-bit offset, need multiple instructions and AT, like:
3448 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3449 addu $tempreg,$tempreg,$breg
3450 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3451 to handle the complete offset. */
3452 macro_build_lui (ep
, AT
);
3453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3454 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3457 as_bad (_("Macro used $at after \".set noat\""));
3462 * Generates code to set the $at register to true (one)
3463 * if reg is less than the immediate expression.
3466 set_at (int reg
, int unsignedp
)
3468 if (imm_expr
.X_op
== O_constant
3469 && imm_expr
.X_add_number
>= -0x8000
3470 && imm_expr
.X_add_number
< 0x8000)
3471 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3472 AT
, reg
, BFD_RELOC_LO16
);
3475 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3476 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3481 normalize_constant_expr (expressionS
*ex
)
3483 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3484 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3488 /* Warn if an expression is not a constant. */
3491 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3493 if (ex
->X_op
== O_big
)
3494 as_bad (_("unsupported large constant"));
3495 else if (ex
->X_op
!= O_constant
)
3496 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3498 normalize_constant_expr (ex
);
3501 /* Count the leading zeroes by performing a binary chop. This is a
3502 bulky bit of source, but performance is a LOT better for the
3503 majority of values than a simple loop to count the bits:
3504 for (lcnt = 0; (lcnt < 32); lcnt++)
3505 if ((v) & (1 << (31 - lcnt)))
3507 However it is not code size friendly, and the gain will drop a bit
3508 on certain cached systems.
3510 #define COUNT_TOP_ZEROES(v) \
3511 (((v) & ~0xffff) == 0 \
3512 ? ((v) & ~0xff) == 0 \
3513 ? ((v) & ~0xf) == 0 \
3514 ? ((v) & ~0x3) == 0 \
3515 ? ((v) & ~0x1) == 0 \
3520 : ((v) & ~0x7) == 0 \
3523 : ((v) & ~0x3f) == 0 \
3524 ? ((v) & ~0x1f) == 0 \
3527 : ((v) & ~0x7f) == 0 \
3530 : ((v) & ~0xfff) == 0 \
3531 ? ((v) & ~0x3ff) == 0 \
3532 ? ((v) & ~0x1ff) == 0 \
3535 : ((v) & ~0x7ff) == 0 \
3538 : ((v) & ~0x3fff) == 0 \
3539 ? ((v) & ~0x1fff) == 0 \
3542 : ((v) & ~0x7fff) == 0 \
3545 : ((v) & ~0xffffff) == 0 \
3546 ? ((v) & ~0xfffff) == 0 \
3547 ? ((v) & ~0x3ffff) == 0 \
3548 ? ((v) & ~0x1ffff) == 0 \
3551 : ((v) & ~0x7ffff) == 0 \
3554 : ((v) & ~0x3fffff) == 0 \
3555 ? ((v) & ~0x1fffff) == 0 \
3558 : ((v) & ~0x7fffff) == 0 \
3561 : ((v) & ~0xfffffff) == 0 \
3562 ? ((v) & ~0x3ffffff) == 0 \
3563 ? ((v) & ~0x1ffffff) == 0 \
3566 : ((v) & ~0x7ffffff) == 0 \
3569 : ((v) & ~0x3fffffff) == 0 \
3570 ? ((v) & ~0x1fffffff) == 0 \
3573 : ((v) & ~0x7fffffff) == 0 \
3578 * This routine generates the least number of instructions necessary to load
3579 * an absolute expression value into a register.
3582 load_register (int reg
, expressionS
*ep
, int dbl
)
3585 expressionS hi32
, lo32
;
3587 if (ep
->X_op
!= O_big
)
3589 assert (ep
->X_op
== O_constant
);
3591 /* Sign-extending 32-bit constants makes their handling easier. */
3592 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3593 == ~((bfd_vma
) 0x7fffffff)))
3595 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3596 as_bad (_("constant too large"));
3598 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3602 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3604 /* We can handle 16 bit signed values with an addiu to
3605 $zero. No need to ever use daddiu here, since $zero and
3606 the result are always correct in 32 bit mode. */
3607 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3610 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3612 /* We can handle 16 bit unsigned values with an ori to
3614 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3617 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3619 /* 32 bit values require an lui. */
3620 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3621 if ((ep
->X_add_number
& 0xffff) != 0)
3622 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3627 /* The value is larger than 32 bits. */
3629 if (HAVE_32BIT_GPRS
)
3631 as_bad (_("Number (0x%lx) larger than 32 bits"),
3632 (unsigned long) ep
->X_add_number
);
3633 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3637 if (ep
->X_op
!= O_big
)
3640 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3641 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3642 hi32
.X_add_number
&= 0xffffffff;
3644 lo32
.X_add_number
&= 0xffffffff;
3648 assert (ep
->X_add_number
> 2);
3649 if (ep
->X_add_number
== 3)
3650 generic_bignum
[3] = 0;
3651 else if (ep
->X_add_number
> 4)
3652 as_bad (_("Number larger than 64 bits"));
3653 lo32
.X_op
= O_constant
;
3654 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3655 hi32
.X_op
= O_constant
;
3656 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3659 if (hi32
.X_add_number
== 0)
3664 unsigned long hi
, lo
;
3666 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3668 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3670 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3673 if (lo32
.X_add_number
& 0x80000000)
3675 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3676 if (lo32
.X_add_number
& 0xffff)
3677 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3682 /* Check for 16bit shifted constant. We know that hi32 is
3683 non-zero, so start the mask on the first bit of the hi32
3688 unsigned long himask
, lomask
;
3692 himask
= 0xffff >> (32 - shift
);
3693 lomask
= (0xffff << shift
) & 0xffffffff;
3697 himask
= 0xffff << (shift
- 32);
3700 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3701 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3705 tmp
.X_op
= O_constant
;
3707 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3708 | (lo32
.X_add_number
>> shift
));
3710 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3711 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3712 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3713 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3718 while (shift
<= (64 - 16));
3720 /* Find the bit number of the lowest one bit, and store the
3721 shifted value in hi/lo. */
3722 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3723 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3727 while ((lo
& 1) == 0)
3732 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3738 while ((hi
& 1) == 0)
3747 /* Optimize if the shifted value is a (power of 2) - 1. */
3748 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3749 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3751 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3756 /* This instruction will set the register to be all
3758 tmp
.X_op
= O_constant
;
3759 tmp
.X_add_number
= (offsetT
) -1;
3760 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3764 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3765 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3767 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3768 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3773 /* Sign extend hi32 before calling load_register, because we can
3774 generally get better code when we load a sign extended value. */
3775 if ((hi32
.X_add_number
& 0x80000000) != 0)
3776 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3777 load_register (reg
, &hi32
, 0);
3780 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3784 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3792 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3794 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3795 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3801 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3805 mid16
.X_add_number
>>= 16;
3806 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3807 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3810 if ((lo32
.X_add_number
& 0xffff) != 0)
3811 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3815 load_delay_nop (void)
3817 if (!gpr_interlocks
)
3818 macro_build (NULL
, "nop", "");
3821 /* Load an address into a register. */
3824 load_address (int reg
, expressionS
*ep
, int *used_at
)
3826 if (ep
->X_op
!= O_constant
3827 && ep
->X_op
!= O_symbol
)
3829 as_bad (_("expression too complex"));
3830 ep
->X_op
= O_constant
;
3833 if (ep
->X_op
== O_constant
)
3835 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3839 if (mips_pic
== NO_PIC
)
3841 /* If this is a reference to a GP relative symbol, we want
3842 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3844 lui $reg,<sym> (BFD_RELOC_HI16_S)
3845 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3846 If we have an addend, we always use the latter form.
3848 With 64bit address space and a usable $at we want
3849 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3850 lui $at,<sym> (BFD_RELOC_HI16_S)
3851 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3852 daddiu $at,<sym> (BFD_RELOC_LO16)
3856 If $at is already in use, we use a path which is suboptimal
3857 on superscalar processors.
3858 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3859 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3861 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3863 daddiu $reg,<sym> (BFD_RELOC_LO16)
3865 if (HAVE_64BIT_ADDRESSES
)
3867 /* ??? We don't provide a GP-relative alternative for these macros.
3868 It used not to be possible with the original relaxation code,
3869 but it could be done now. */
3871 if (*used_at
== 0 && !mips_opts
.noat
)
3873 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3874 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3875 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3876 BFD_RELOC_MIPS_HIGHER
);
3877 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3878 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3879 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3884 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3885 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3886 BFD_RELOC_MIPS_HIGHER
);
3887 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3888 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3889 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3890 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3895 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3896 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3898 relax_start (ep
->X_add_symbol
);
3899 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3900 mips_gp_register
, BFD_RELOC_GPREL16
);
3903 macro_build_lui (ep
, reg
);
3904 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3905 reg
, reg
, BFD_RELOC_LO16
);
3906 if (mips_relax
.sequence
)
3910 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3914 /* If this is a reference to an external symbol, we want
3915 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3917 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3919 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3920 If there is a constant, it must be added in after.
3922 If we have NewABI, we want
3923 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3924 unless we're referencing a global symbol with a non-zero
3925 offset, in which case cst must be added separately. */
3928 if (ep
->X_add_number
)
3930 ex
.X_add_number
= ep
->X_add_number
;
3931 ep
->X_add_number
= 0;
3932 relax_start (ep
->X_add_symbol
);
3933 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3934 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3935 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3936 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3937 ex
.X_op
= O_constant
;
3938 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3939 reg
, reg
, BFD_RELOC_LO16
);
3940 ep
->X_add_number
= ex
.X_add_number
;
3943 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3944 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3945 if (mips_relax
.sequence
)
3950 ex
.X_add_number
= ep
->X_add_number
;
3951 ep
->X_add_number
= 0;
3952 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3953 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3955 relax_start (ep
->X_add_symbol
);
3957 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3961 if (ex
.X_add_number
!= 0)
3963 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3965 ex
.X_op
= O_constant
;
3966 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3967 reg
, reg
, BFD_RELOC_LO16
);
3971 else if (mips_pic
== SVR4_PIC
)
3975 /* This is the large GOT case. If this is a reference to an
3976 external symbol, we want
3977 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3979 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3981 Otherwise, for a reference to a local symbol in old ABI, we want
3982 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3984 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3985 If there is a constant, it must be added in after.
3987 In the NewABI, for local symbols, with or without offsets, we want:
3988 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3989 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3993 ex
.X_add_number
= ep
->X_add_number
;
3994 ep
->X_add_number
= 0;
3995 relax_start (ep
->X_add_symbol
);
3996 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3997 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3998 reg
, reg
, mips_gp_register
);
3999 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4000 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4001 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4002 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4003 else if (ex
.X_add_number
)
4005 ex
.X_op
= O_constant
;
4006 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4010 ep
->X_add_number
= ex
.X_add_number
;
4012 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4013 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4014 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4015 BFD_RELOC_MIPS_GOT_OFST
);
4020 ex
.X_add_number
= ep
->X_add_number
;
4021 ep
->X_add_number
= 0;
4022 relax_start (ep
->X_add_symbol
);
4023 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4024 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4025 reg
, reg
, mips_gp_register
);
4026 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4027 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4029 if (reg_needs_delay (mips_gp_register
))
4031 /* We need a nop before loading from $gp. This special
4032 check is required because the lui which starts the main
4033 instruction stream does not refer to $gp, and so will not
4034 insert the nop which may be required. */
4035 macro_build (NULL
, "nop", "");
4037 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4038 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4040 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4044 if (ex
.X_add_number
!= 0)
4046 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4047 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4048 ex
.X_op
= O_constant
;
4049 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4057 if (mips_opts
.noat
&& *used_at
== 1)
4058 as_bad (_("Macro used $at after \".set noat\""));
4061 /* Move the contents of register SOURCE into register DEST. */
4064 move_register (int dest
, int source
)
4066 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4070 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4071 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4072 The two alternatives are:
4074 Global symbol Local sybmol
4075 ------------- ------------
4076 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4078 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4080 load_got_offset emits the first instruction and add_got_offset
4081 emits the second for a 16-bit offset or add_got_offset_hilo emits
4082 a sequence to add a 32-bit offset using a scratch register. */
4085 load_got_offset (int dest
, expressionS
*local
)
4090 global
.X_add_number
= 0;
4092 relax_start (local
->X_add_symbol
);
4093 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4094 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4096 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4097 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4102 add_got_offset (int dest
, expressionS
*local
)
4106 global
.X_op
= O_constant
;
4107 global
.X_op_symbol
= NULL
;
4108 global
.X_add_symbol
= NULL
;
4109 global
.X_add_number
= local
->X_add_number
;
4111 relax_start (local
->X_add_symbol
);
4112 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4113 dest
, dest
, BFD_RELOC_LO16
);
4115 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4120 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4123 int hold_mips_optimize
;
4125 global
.X_op
= O_constant
;
4126 global
.X_op_symbol
= NULL
;
4127 global
.X_add_symbol
= NULL
;
4128 global
.X_add_number
= local
->X_add_number
;
4130 relax_start (local
->X_add_symbol
);
4131 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4133 /* Set mips_optimize around the lui instruction to avoid
4134 inserting an unnecessary nop after the lw. */
4135 hold_mips_optimize
= mips_optimize
;
4137 macro_build_lui (&global
, tmp
);
4138 mips_optimize
= hold_mips_optimize
;
4139 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4147 * This routine implements the seemingly endless macro or synthesized
4148 * instructions and addressing modes in the mips assembly language. Many
4149 * of these macros are simple and are similar to each other. These could
4150 * probably be handled by some kind of table or grammar approach instead of
4151 * this verbose method. Others are not simple macros but are more like
4152 * optimizing code generation.
4153 * One interesting optimization is when several store macros appear
4154 * consecutively that would load AT with the upper half of the same address.
4155 * The ensuing load upper instructions are ommited. This implies some kind
4156 * of global optimization. We currently only optimize within a single macro.
4157 * For many of the load and store macros if the address is specified as a
4158 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4159 * first load register 'at' with zero and use it as the base register. The
4160 * mips assembler simply uses register $zero. Just one tiny optimization
4164 macro (struct mips_cl_insn
*ip
)
4166 register int treg
, sreg
, dreg
, breg
;
4182 bfd_reloc_code_real_type r
;
4183 int hold_mips_optimize
;
4185 assert (! mips_opts
.mips16
);
4187 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4188 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4189 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4190 mask
= ip
->insn_mo
->mask
;
4192 expr1
.X_op
= O_constant
;
4193 expr1
.X_op_symbol
= NULL
;
4194 expr1
.X_add_symbol
= NULL
;
4195 expr1
.X_add_number
= 1;
4207 mips_emit_delays (TRUE
);
4208 ++mips_opts
.noreorder
;
4209 mips_any_noreorder
= 1;
4211 expr1
.X_add_number
= 8;
4212 macro_build (&expr1
, "bgez", "s,p", sreg
);
4214 macro_build (NULL
, "nop", "", 0);
4216 move_register (dreg
, sreg
);
4217 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4219 --mips_opts
.noreorder
;
4240 if (imm_expr
.X_op
== O_constant
4241 && imm_expr
.X_add_number
>= -0x8000
4242 && imm_expr
.X_add_number
< 0x8000)
4244 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4248 load_register (AT
, &imm_expr
, dbl
);
4249 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4268 if (imm_expr
.X_op
== O_constant
4269 && imm_expr
.X_add_number
>= 0
4270 && imm_expr
.X_add_number
< 0x10000)
4272 if (mask
!= M_NOR_I
)
4273 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4276 macro_build (&imm_expr
, "ori", "t,r,i",
4277 treg
, sreg
, BFD_RELOC_LO16
);
4278 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4284 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4285 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4302 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4304 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4308 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4309 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4317 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4322 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4326 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4327 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4333 /* check for > max integer */
4334 maxnum
= 0x7fffffff;
4335 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4342 if (imm_expr
.X_op
== O_constant
4343 && imm_expr
.X_add_number
>= maxnum
4344 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4347 /* result is always false */
4349 macro_build (NULL
, "nop", "", 0);
4351 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4354 if (imm_expr
.X_op
!= O_constant
)
4355 as_bad (_("Unsupported large constant"));
4356 ++imm_expr
.X_add_number
;
4360 if (mask
== M_BGEL_I
)
4362 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4364 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4367 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4369 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4372 maxnum
= 0x7fffffff;
4373 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4380 maxnum
= - maxnum
- 1;
4381 if (imm_expr
.X_op
== O_constant
4382 && imm_expr
.X_add_number
<= maxnum
4383 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4386 /* result is always true */
4387 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4388 macro_build (&offset_expr
, "b", "p");
4393 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4403 macro_build (&offset_expr
, likely
? "beql" : "beq",
4408 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4409 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4417 && imm_expr
.X_op
== O_constant
4418 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4420 if (imm_expr
.X_op
!= O_constant
)
4421 as_bad (_("Unsupported large constant"));
4422 ++imm_expr
.X_add_number
;
4426 if (mask
== M_BGEUL_I
)
4428 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4430 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4432 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4438 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4446 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4451 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4455 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4456 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4464 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4471 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4472 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4480 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4485 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4489 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4490 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4496 maxnum
= 0x7fffffff;
4497 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4504 if (imm_expr
.X_op
== O_constant
4505 && imm_expr
.X_add_number
>= maxnum
4506 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4508 if (imm_expr
.X_op
!= O_constant
)
4509 as_bad (_("Unsupported large constant"));
4510 ++imm_expr
.X_add_number
;
4514 if (mask
== M_BLTL_I
)
4516 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4518 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4521 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4523 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4528 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4536 macro_build (&offset_expr
, likely
? "beql" : "beq",
4543 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4544 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4552 && imm_expr
.X_op
== O_constant
4553 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4555 if (imm_expr
.X_op
!= O_constant
)
4556 as_bad (_("Unsupported large constant"));
4557 ++imm_expr
.X_add_number
;
4561 if (mask
== M_BLTUL_I
)
4563 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4565 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4567 macro_build (&offset_expr
, likely
? "beql" : "beq",
4573 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4581 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4586 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4590 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4591 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4601 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4606 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4607 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4615 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4617 as_bad (_("Unsupported large constant"));
4622 pos
= (unsigned long) imm_expr
.X_add_number
;
4623 size
= (unsigned long) imm2_expr
.X_add_number
;
4628 as_bad (_("Improper position (%lu)"), pos
);
4631 if (size
== 0 || size
> 64
4632 || (pos
+ size
- 1) > 63)
4634 as_bad (_("Improper extract size (%lu, position %lu)"),
4639 if (size
<= 32 && pos
< 32)
4644 else if (size
<= 32)
4654 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4663 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4665 as_bad (_("Unsupported large constant"));
4670 pos
= (unsigned long) imm_expr
.X_add_number
;
4671 size
= (unsigned long) imm2_expr
.X_add_number
;
4676 as_bad (_("Improper position (%lu)"), pos
);
4679 if (size
== 0 || size
> 64
4680 || (pos
+ size
- 1) > 63)
4682 as_bad (_("Improper insert size (%lu, position %lu)"),
4687 if (pos
< 32 && (pos
+ size
- 1) < 32)
4702 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4719 as_warn (_("Divide by zero."));
4721 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4723 macro_build (NULL
, "break", "c", 7);
4727 mips_emit_delays (TRUE
);
4728 ++mips_opts
.noreorder
;
4729 mips_any_noreorder
= 1;
4732 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4733 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4737 expr1
.X_add_number
= 8;
4738 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4739 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4740 macro_build (NULL
, "break", "c", 7);
4742 expr1
.X_add_number
= -1;
4744 load_register (AT
, &expr1
, dbl
);
4745 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4746 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4749 expr1
.X_add_number
= 1;
4750 load_register (AT
, &expr1
, dbl
);
4751 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4755 expr1
.X_add_number
= 0x80000000;
4756 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4760 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4761 /* We want to close the noreorder block as soon as possible, so
4762 that later insns are available for delay slot filling. */
4763 --mips_opts
.noreorder
;
4767 expr1
.X_add_number
= 8;
4768 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4769 macro_build (NULL
, "nop", "", 0);
4771 /* We want to close the noreorder block as soon as possible, so
4772 that later insns are available for delay slot filling. */
4773 --mips_opts
.noreorder
;
4775 macro_build (NULL
, "break", "c", 6);
4777 macro_build (NULL
, s
, "d", dreg
);
4816 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4818 as_warn (_("Divide by zero."));
4820 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4822 macro_build (NULL
, "break", "c", 7);
4825 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4827 if (strcmp (s2
, "mflo") == 0)
4828 move_register (dreg
, sreg
);
4830 move_register (dreg
, 0);
4833 if (imm_expr
.X_op
== O_constant
4834 && imm_expr
.X_add_number
== -1
4835 && s
[strlen (s
) - 1] != 'u')
4837 if (strcmp (s2
, "mflo") == 0)
4839 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4842 move_register (dreg
, 0);
4847 load_register (AT
, &imm_expr
, dbl
);
4848 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4849 macro_build (NULL
, s2
, "d", dreg
);
4868 mips_emit_delays (TRUE
);
4869 ++mips_opts
.noreorder
;
4870 mips_any_noreorder
= 1;
4873 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4874 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4875 /* We want to close the noreorder block as soon as possible, so
4876 that later insns are available for delay slot filling. */
4877 --mips_opts
.noreorder
;
4881 expr1
.X_add_number
= 8;
4882 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4883 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4885 /* We want to close the noreorder block as soon as possible, so
4886 that later insns are available for delay slot filling. */
4887 --mips_opts
.noreorder
;
4888 macro_build (NULL
, "break", "c", 7);
4890 macro_build (NULL
, s2
, "d", dreg
);
4902 /* Load the address of a symbol into a register. If breg is not
4903 zero, we then add a base register to it. */
4905 if (dbl
&& HAVE_32BIT_GPRS
)
4906 as_warn (_("dla used to load 32-bit register"));
4908 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4909 as_warn (_("la used to load 64-bit address"));
4911 if (offset_expr
.X_op
== O_constant
4912 && offset_expr
.X_add_number
>= -0x8000
4913 && offset_expr
.X_add_number
< 0x8000)
4915 macro_build (&offset_expr
,
4916 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4917 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4921 if (!mips_opts
.noat
&& (treg
== breg
))
4931 if (offset_expr
.X_op
!= O_symbol
4932 && offset_expr
.X_op
!= O_constant
)
4934 as_bad (_("expression too complex"));
4935 offset_expr
.X_op
= O_constant
;
4938 if (offset_expr
.X_op
== O_constant
)
4939 load_register (tempreg
, &offset_expr
,
4941 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4942 : HAVE_64BIT_ADDRESSES
));
4943 else if (mips_pic
== NO_PIC
)
4945 /* If this is a reference to a GP relative symbol, we want
4946 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4948 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4949 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4950 If we have a constant, we need two instructions anyhow,
4951 so we may as well always use the latter form.
4953 With 64bit address space and a usable $at we want
4954 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4955 lui $at,<sym> (BFD_RELOC_HI16_S)
4956 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4957 daddiu $at,<sym> (BFD_RELOC_LO16)
4959 daddu $tempreg,$tempreg,$at
4961 If $at is already in use, we use a path which is suboptimal
4962 on superscalar processors.
4963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4964 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4966 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4968 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4970 if (HAVE_64BIT_ADDRESSES
)
4972 /* ??? We don't provide a GP-relative alternative for
4973 these macros. It used not to be possible with the
4974 original relaxation code, but it could be done now. */
4976 if (used_at
== 0 && !mips_opts
.noat
)
4978 macro_build (&offset_expr
, "lui", "t,u",
4979 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4980 macro_build (&offset_expr
, "lui", "t,u",
4981 AT
, BFD_RELOC_HI16_S
);
4982 macro_build (&offset_expr
, "daddiu", "t,r,j",
4983 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4984 macro_build (&offset_expr
, "daddiu", "t,r,j",
4985 AT
, AT
, BFD_RELOC_LO16
);
4986 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4987 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4992 macro_build (&offset_expr
, "lui", "t,u",
4993 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4994 macro_build (&offset_expr
, "daddiu", "t,r,j",
4995 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4996 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4997 macro_build (&offset_expr
, "daddiu", "t,r,j",
4998 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4999 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5000 macro_build (&offset_expr
, "daddiu", "t,r,j",
5001 tempreg
, tempreg
, BFD_RELOC_LO16
);
5006 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5007 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5009 relax_start (offset_expr
.X_add_symbol
);
5010 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5011 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5014 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5015 as_bad (_("offset too large"));
5016 macro_build_lui (&offset_expr
, tempreg
);
5017 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5018 tempreg
, tempreg
, BFD_RELOC_LO16
);
5019 if (mips_relax
.sequence
)
5023 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5025 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5027 /* If this is a reference to an external symbol, and there
5028 is no constant, we want
5029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5030 or for lca or if tempreg is PIC_CALL_REG
5031 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5032 For a local symbol, we want
5033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5035 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5037 If we have a small constant, and this is a reference to
5038 an external symbol, we want
5039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5041 addiu $tempreg,$tempreg,<constant>
5042 For a local symbol, we want the same instruction
5043 sequence, but we output a BFD_RELOC_LO16 reloc on the
5046 If we have a large constant, and this is a reference to
5047 an external symbol, we want
5048 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5049 lui $at,<hiconstant>
5050 addiu $at,$at,<loconstant>
5051 addu $tempreg,$tempreg,$at
5052 For a local symbol, we want the same instruction
5053 sequence, but we output a BFD_RELOC_LO16 reloc on the
5057 if (offset_expr
.X_add_number
== 0)
5059 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5060 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5062 relax_start (offset_expr
.X_add_symbol
);
5063 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5064 lw_reloc_type
, mips_gp_register
);
5067 /* We're going to put in an addu instruction using
5068 tempreg, so we may as well insert the nop right
5073 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5074 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5076 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5077 tempreg
, tempreg
, BFD_RELOC_LO16
);
5079 /* FIXME: If breg == 0, and the next instruction uses
5080 $tempreg, then if this variant case is used an extra
5081 nop will be generated. */
5083 else if (offset_expr
.X_add_number
>= -0x8000
5084 && offset_expr
.X_add_number
< 0x8000)
5086 load_got_offset (tempreg
, &offset_expr
);
5088 add_got_offset (tempreg
, &offset_expr
);
5092 expr1
.X_add_number
= offset_expr
.X_add_number
;
5093 offset_expr
.X_add_number
=
5094 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5095 load_got_offset (tempreg
, &offset_expr
);
5096 offset_expr
.X_add_number
= expr1
.X_add_number
;
5097 /* If we are going to add in a base register, and the
5098 target register and the base register are the same,
5099 then we are using AT as a temporary register. Since
5100 we want to load the constant into AT, we add our
5101 current AT (from the global offset table) and the
5102 register into the register now, and pretend we were
5103 not using a base register. */
5107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5112 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5116 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5118 int add_breg_early
= 0;
5120 /* If this is a reference to an external, and there is no
5121 constant, or local symbol (*), with or without a
5123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5124 or for lca or if tempreg is PIC_CALL_REG
5125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5127 If we have a small constant, and this is a reference to
5128 an external symbol, we want
5129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5130 addiu $tempreg,$tempreg,<constant>
5132 If we have a large constant, and this is a reference to
5133 an external symbol, we want
5134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5135 lui $at,<hiconstant>
5136 addiu $at,$at,<loconstant>
5137 addu $tempreg,$tempreg,$at
5139 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5140 local symbols, even though it introduces an additional
5143 if (offset_expr
.X_add_number
)
5145 expr1
.X_add_number
= offset_expr
.X_add_number
;
5146 offset_expr
.X_add_number
= 0;
5148 relax_start (offset_expr
.X_add_symbol
);
5149 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5150 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5152 if (expr1
.X_add_number
>= -0x8000
5153 && expr1
.X_add_number
< 0x8000)
5155 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5156 tempreg
, tempreg
, BFD_RELOC_LO16
);
5158 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5162 /* If we are going to add in a base register, and the
5163 target register and the base register are the same,
5164 then we are using AT as a temporary register. Since
5165 we want to load the constant into AT, we add our
5166 current AT (from the global offset table) and the
5167 register into the register now, and pretend we were
5168 not using a base register. */
5173 assert (tempreg
== AT
);
5174 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5180 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5187 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5190 offset_expr
.X_add_number
= expr1
.X_add_number
;
5192 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5193 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5196 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5197 treg
, tempreg
, breg
);
5203 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5205 relax_start (offset_expr
.X_add_symbol
);
5206 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5207 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5209 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5210 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5216 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5219 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5222 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5223 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5224 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5226 /* This is the large GOT case. If this is a reference to an
5227 external symbol, and there is no constant, we want
5228 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5229 addu $tempreg,$tempreg,$gp
5230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5231 or for lca or if tempreg is PIC_CALL_REG
5232 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5233 addu $tempreg,$tempreg,$gp
5234 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5235 For a local symbol, we want
5236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5238 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5240 If we have a small constant, and this is a reference to
5241 an external symbol, we want
5242 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5243 addu $tempreg,$tempreg,$gp
5244 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5246 addiu $tempreg,$tempreg,<constant>
5247 For a local symbol, we want
5248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5250 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5252 If we have a large constant, and this is a reference to
5253 an external symbol, we want
5254 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5255 addu $tempreg,$tempreg,$gp
5256 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5257 lui $at,<hiconstant>
5258 addiu $at,$at,<loconstant>
5259 addu $tempreg,$tempreg,$at
5260 For a local symbol, we want
5261 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5262 lui $at,<hiconstant>
5263 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5264 addu $tempreg,$tempreg,$at
5267 expr1
.X_add_number
= offset_expr
.X_add_number
;
5268 offset_expr
.X_add_number
= 0;
5269 relax_start (offset_expr
.X_add_symbol
);
5270 gpdelay
= reg_needs_delay (mips_gp_register
);
5271 if (expr1
.X_add_number
== 0 && breg
== 0
5272 && (call
|| tempreg
== PIC_CALL_REG
))
5274 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5275 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5277 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5279 tempreg
, tempreg
, mips_gp_register
);
5280 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5281 tempreg
, lw_reloc_type
, tempreg
);
5282 if (expr1
.X_add_number
== 0)
5286 /* We're going to put in an addu instruction using
5287 tempreg, so we may as well insert the nop right
5292 else if (expr1
.X_add_number
>= -0x8000
5293 && expr1
.X_add_number
< 0x8000)
5296 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5297 tempreg
, tempreg
, BFD_RELOC_LO16
);
5303 /* If we are going to add in a base register, and the
5304 target register and the base register are the same,
5305 then we are using AT as a temporary register. Since
5306 we want to load the constant into AT, we add our
5307 current AT (from the global offset table) and the
5308 register into the register now, and pretend we were
5309 not using a base register. */
5314 assert (tempreg
== AT
);
5316 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5321 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5322 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5326 offset_expr
.X_add_number
=
5327 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5332 /* This is needed because this instruction uses $gp, but
5333 the first instruction on the main stream does not. */
5334 macro_build (NULL
, "nop", "");
5337 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5338 local_reloc_type
, mips_gp_register
);
5339 if (expr1
.X_add_number
>= -0x8000
5340 && expr1
.X_add_number
< 0x8000)
5343 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5344 tempreg
, tempreg
, BFD_RELOC_LO16
);
5345 /* FIXME: If add_number is 0, and there was no base
5346 register, the external symbol case ended with a load,
5347 so if the symbol turns out to not be external, and
5348 the next instruction uses tempreg, an unnecessary nop
5349 will be inserted. */
5355 /* We must add in the base register now, as in the
5356 external symbol case. */
5357 assert (tempreg
== AT
);
5359 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5362 /* We set breg to 0 because we have arranged to add
5363 it in in both cases. */
5367 macro_build_lui (&expr1
, AT
);
5368 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5369 AT
, AT
, BFD_RELOC_LO16
);
5370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5371 tempreg
, tempreg
, AT
);
5376 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5378 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5379 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5380 int add_breg_early
= 0;
5382 /* This is the large GOT case. If this is a reference to an
5383 external symbol, and there is no constant, we want
5384 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5385 add $tempreg,$tempreg,$gp
5386 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5387 or for lca or if tempreg is PIC_CALL_REG
5388 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5389 add $tempreg,$tempreg,$gp
5390 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5392 If we have a small constant, and this is a reference to
5393 an external symbol, we want
5394 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5395 add $tempreg,$tempreg,$gp
5396 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5397 addi $tempreg,$tempreg,<constant>
5399 If we have a large constant, and this is a reference to
5400 an external symbol, we want
5401 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5402 addu $tempreg,$tempreg,$gp
5403 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5404 lui $at,<hiconstant>
5405 addi $at,$at,<loconstant>
5406 add $tempreg,$tempreg,$at
5408 If we have NewABI, and we know it's a local symbol, we want
5409 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5410 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5411 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5413 relax_start (offset_expr
.X_add_symbol
);
5415 expr1
.X_add_number
= offset_expr
.X_add_number
;
5416 offset_expr
.X_add_number
= 0;
5418 if (expr1
.X_add_number
== 0 && breg
== 0
5419 && (call
|| tempreg
== PIC_CALL_REG
))
5421 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5422 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5424 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5425 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5426 tempreg
, tempreg
, mips_gp_register
);
5427 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5428 tempreg
, lw_reloc_type
, tempreg
);
5430 if (expr1
.X_add_number
== 0)
5432 else if (expr1
.X_add_number
>= -0x8000
5433 && expr1
.X_add_number
< 0x8000)
5435 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5436 tempreg
, tempreg
, BFD_RELOC_LO16
);
5438 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5442 /* If we are going to add in a base register, and the
5443 target register and the base register are the same,
5444 then we are using AT as a temporary register. Since
5445 we want to load the constant into AT, we add our
5446 current AT (from the global offset table) and the
5447 register into the register now, and pretend we were
5448 not using a base register. */
5453 assert (tempreg
== AT
);
5454 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5460 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5466 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5469 offset_expr
.X_add_number
= expr1
.X_add_number
;
5470 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5471 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5472 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5473 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5477 treg
, tempreg
, breg
);
5490 if (mips_pic
== NO_PIC
)
5491 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5493 s
= ADDRESS_ADD_INSN
;
5495 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5500 /* The j instruction may not be used in PIC code, since it
5501 requires an absolute address. We convert it to a b
5503 if (mips_pic
== NO_PIC
)
5504 macro_build (&offset_expr
, "j", "a");
5506 macro_build (&offset_expr
, "b", "p");
5509 /* The jal instructions must be handled as macros because when
5510 generating PIC code they expand to multi-instruction
5511 sequences. Normally they are simple instructions. */
5516 if (mips_pic
== NO_PIC
)
5517 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5518 else if (mips_pic
== SVR4_PIC
)
5520 if (sreg
!= PIC_CALL_REG
)
5521 as_warn (_("MIPS PIC call to register other than $25"));
5523 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5526 if (mips_cprestore_offset
< 0)
5527 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5530 if (! mips_frame_reg_valid
)
5532 as_warn (_("No .frame pseudo-op used in PIC code"));
5533 /* Quiet this warning. */
5534 mips_frame_reg_valid
= 1;
5536 if (! mips_cprestore_valid
)
5538 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5539 /* Quiet this warning. */
5540 mips_cprestore_valid
= 1;
5542 expr1
.X_add_number
= mips_cprestore_offset
;
5543 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5546 HAVE_64BIT_ADDRESSES
);
5556 if (mips_pic
== NO_PIC
)
5557 macro_build (&offset_expr
, "jal", "a");
5558 else if (mips_pic
== SVR4_PIC
)
5560 /* If this is a reference to an external symbol, and we are
5561 using a small GOT, we want
5562 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5566 lw $gp,cprestore($sp)
5567 The cprestore value is set using the .cprestore
5568 pseudo-op. If we are using a big GOT, we want
5569 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5571 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5575 lw $gp,cprestore($sp)
5576 If the symbol is not external, we want
5577 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5579 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5582 lw $gp,cprestore($sp)
5584 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5585 sequences above, minus nops, unless the symbol is local,
5586 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5592 relax_start (offset_expr
.X_add_symbol
);
5593 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5594 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5597 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5598 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5604 relax_start (offset_expr
.X_add_symbol
);
5605 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5606 BFD_RELOC_MIPS_CALL_HI16
);
5607 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5608 PIC_CALL_REG
, mips_gp_register
);
5609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5610 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5613 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5614 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5616 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5617 PIC_CALL_REG
, PIC_CALL_REG
,
5618 BFD_RELOC_MIPS_GOT_OFST
);
5622 macro_build_jalr (&offset_expr
);
5626 relax_start (offset_expr
.X_add_symbol
);
5629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5630 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5639 gpdelay
= reg_needs_delay (mips_gp_register
);
5640 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5641 BFD_RELOC_MIPS_CALL_HI16
);
5642 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5643 PIC_CALL_REG
, mips_gp_register
);
5644 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5645 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5650 macro_build (NULL
, "nop", "");
5652 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5653 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5656 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5657 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5659 macro_build_jalr (&offset_expr
);
5661 if (mips_cprestore_offset
< 0)
5662 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5665 if (! mips_frame_reg_valid
)
5667 as_warn (_("No .frame pseudo-op used in PIC code"));
5668 /* Quiet this warning. */
5669 mips_frame_reg_valid
= 1;
5671 if (! mips_cprestore_valid
)
5673 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5674 /* Quiet this warning. */
5675 mips_cprestore_valid
= 1;
5677 if (mips_opts
.noreorder
)
5678 macro_build (NULL
, "nop", "");
5679 expr1
.X_add_number
= mips_cprestore_offset
;
5680 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5683 HAVE_64BIT_ADDRESSES
);
5709 /* Itbl support may require additional care here. */
5714 /* Itbl support may require additional care here. */
5719 /* Itbl support may require additional care here. */
5724 /* Itbl support may require additional care here. */
5736 if (mips_opts
.arch
== CPU_R4650
)
5738 as_bad (_("opcode not supported on this processor"));
5742 /* Itbl support may require additional care here. */
5747 /* Itbl support may require additional care here. */
5752 /* Itbl support may require additional care here. */
5772 if (breg
== treg
|| coproc
|| lr
)
5793 /* Itbl support may require additional care here. */
5798 /* Itbl support may require additional care here. */
5803 /* Itbl support may require additional care here. */
5808 /* Itbl support may require additional care here. */
5824 if (mips_opts
.arch
== CPU_R4650
)
5826 as_bad (_("opcode not supported on this processor"));
5831 /* Itbl support may require additional care here. */
5835 /* Itbl support may require additional care here. */
5840 /* Itbl support may require additional care here. */
5852 /* Itbl support may require additional care here. */
5853 if (mask
== M_LWC1_AB
5854 || mask
== M_SWC1_AB
5855 || mask
== M_LDC1_AB
5856 || mask
== M_SDC1_AB
5865 /* Sign-extending 32-bit constants makes their handling easier.
5866 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5868 if ((! HAVE_64BIT_ADDRESSES
5869 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5870 && (offset_expr
.X_op
== O_constant
)
5871 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5872 == ~((bfd_vma
) 0x7fffffff)))
5874 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5875 as_bad (_("constant too large"));
5877 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5878 ^ 0x80000000) - 0x80000000);
5881 if (offset_expr
.X_op
!= O_constant
5882 && offset_expr
.X_op
!= O_symbol
)
5884 as_bad (_("expression too complex"));
5885 offset_expr
.X_op
= O_constant
;
5888 /* A constant expression in PIC code can be handled just as it
5889 is in non PIC code. */
5890 if (mips_pic
== NO_PIC
5891 || offset_expr
.X_op
== O_constant
)
5893 /* If this is a reference to a GP relative symbol, and there
5894 is no base register, we want
5895 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5896 Otherwise, if there is no base register, we want
5897 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5898 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5899 If we have a constant, we need two instructions anyhow,
5900 so we always use the latter form.
5902 If we have a base register, and this is a reference to a
5903 GP relative symbol, we want
5904 addu $tempreg,$breg,$gp
5905 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5907 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5908 addu $tempreg,$tempreg,$breg
5909 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5910 With a constant we always use the latter case.
5912 With 64bit address space and no base register and $at usable,
5914 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5915 lui $at,<sym> (BFD_RELOC_HI16_S)
5916 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5919 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5920 If we have a base register, we want
5921 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5922 lui $at,<sym> (BFD_RELOC_HI16_S)
5923 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5927 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5929 Without $at we can't generate the optimal path for superscalar
5930 processors here since this would require two temporary registers.
5931 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5934 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5936 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5937 If we have a base register, we want
5938 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5939 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5941 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5943 daddu $tempreg,$tempreg,$breg
5944 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5946 If we have 64-bit addresses, as an optimization, for
5947 addresses which are 32-bit constants (e.g. kseg0/kseg1
5948 addresses) we fall back to the 32-bit address generation
5949 mechanism since it is more efficient. Note that due to
5950 the signed offset used by memory operations, the 32-bit
5951 range is shifted down by 32768 here. This code should
5952 probably attempt to generate 64-bit constants more
5953 efficiently in general.
5955 As an extension for architectures with 64-bit registers,
5956 we don't truncate 64-bit addresses given as literal
5957 constants down to 32 bits, to support existing practice
5958 in the mips64 Linux (the kernel), that compiles source
5959 files with -mabi=64, assembling them as o32 or n32 (with
5960 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5961 the whole kernel is loaded into a memory region that is
5962 addressable with sign-extended 32-bit addresses, it is
5963 wasteful to compute the upper 32 bits of every
5964 non-literal address, that takes more space and time.
5965 Some day this should probably be implemented as an
5966 assembler option, such that the kernel doesn't have to
5967 use such ugly hacks, even though it will still have to
5968 end up converting the binary to ELF32 for a number of
5969 platforms whose boot loaders don't support ELF64
5971 if ((HAVE_64BIT_ADDRESSES
5972 && ! (offset_expr
.X_op
== O_constant
5973 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5975 && offset_expr
.X_op
== O_constant
5976 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5978 /* ??? We don't provide a GP-relative alternative for
5979 these macros. It used not to be possible with the
5980 original relaxation code, but it could be done now. */
5982 if (used_at
== 0 && !mips_opts
.noat
)
5984 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5985 BFD_RELOC_MIPS_HIGHEST
);
5986 macro_build (&offset_expr
, "lui", "t,u", AT
,
5988 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5989 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5991 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5992 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5993 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5994 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6000 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6001 BFD_RELOC_MIPS_HIGHEST
);
6002 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6003 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6004 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6005 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6006 tempreg
, BFD_RELOC_HI16_S
);
6007 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6009 macro_build (NULL
, "daddu", "d,v,t",
6010 tempreg
, tempreg
, breg
);
6011 macro_build (&offset_expr
, s
, fmt
, treg
,
6012 BFD_RELOC_LO16
, tempreg
);
6017 if (offset_expr
.X_op
== O_constant
6018 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6019 as_bad (_("load/store address overflow (max 32 bits)"));
6023 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6024 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6026 relax_start (offset_expr
.X_add_symbol
);
6027 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6031 macro_build_lui (&offset_expr
, tempreg
);
6032 macro_build (&offset_expr
, s
, fmt
, treg
,
6033 BFD_RELOC_LO16
, tempreg
);
6034 if (mips_relax
.sequence
)
6039 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6040 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6042 relax_start (offset_expr
.X_add_symbol
);
6043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6044 tempreg
, breg
, mips_gp_register
);
6045 macro_build (&offset_expr
, s
, fmt
, treg
,
6046 BFD_RELOC_GPREL16
, tempreg
);
6049 macro_build_lui (&offset_expr
, tempreg
);
6050 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6051 tempreg
, tempreg
, breg
);
6052 macro_build (&offset_expr
, s
, fmt
, treg
,
6053 BFD_RELOC_LO16
, tempreg
);
6054 if (mips_relax
.sequence
)
6058 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6060 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6062 /* If this is a reference to an external symbol, we want
6063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6065 <op> $treg,0($tempreg)
6067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6069 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6070 <op> $treg,0($tempreg)
6073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6074 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6076 If there is a base register, we add it to $tempreg before
6077 the <op>. If there is a constant, we stick it in the
6078 <op> instruction. We don't handle constants larger than
6079 16 bits, because we have no way to load the upper 16 bits
6080 (actually, we could handle them for the subset of cases
6081 in which we are not using $at). */
6082 assert (offset_expr
.X_op
== O_symbol
);
6085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6086 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6088 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6089 tempreg
, tempreg
, breg
);
6090 macro_build (&offset_expr
, s
, fmt
, treg
,
6091 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6094 expr1
.X_add_number
= offset_expr
.X_add_number
;
6095 offset_expr
.X_add_number
= 0;
6096 if (expr1
.X_add_number
< -0x8000
6097 || expr1
.X_add_number
>= 0x8000)
6098 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6099 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6100 lw_reloc_type
, mips_gp_register
);
6102 relax_start (offset_expr
.X_add_symbol
);
6104 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6105 tempreg
, BFD_RELOC_LO16
);
6108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6109 tempreg
, tempreg
, breg
);
6110 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6112 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6116 /* If this is a reference to an external symbol, we want
6117 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6118 addu $tempreg,$tempreg,$gp
6119 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6120 <op> $treg,0($tempreg)
6122 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6124 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6125 <op> $treg,0($tempreg)
6126 If there is a base register, we add it to $tempreg before
6127 the <op>. If there is a constant, we stick it in the
6128 <op> instruction. We don't handle constants larger than
6129 16 bits, because we have no way to load the upper 16 bits
6130 (actually, we could handle them for the subset of cases
6131 in which we are not using $at). */
6132 assert (offset_expr
.X_op
== O_symbol
);
6133 expr1
.X_add_number
= offset_expr
.X_add_number
;
6134 offset_expr
.X_add_number
= 0;
6135 if (expr1
.X_add_number
< -0x8000
6136 || expr1
.X_add_number
>= 0x8000)
6137 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6138 gpdelay
= reg_needs_delay (mips_gp_register
);
6139 relax_start (offset_expr
.X_add_symbol
);
6140 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6141 BFD_RELOC_MIPS_GOT_HI16
);
6142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6145 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6148 macro_build (NULL
, "nop", "");
6149 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6150 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6152 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6153 tempreg
, BFD_RELOC_LO16
);
6157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6158 tempreg
, tempreg
, breg
);
6159 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6161 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6163 /* If this is a reference to an external symbol, we want
6164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6165 add $tempreg,$tempreg,$gp
6166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6167 <op> $treg,<ofst>($tempreg)
6168 Otherwise, for local symbols, we want:
6169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6170 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6171 assert (offset_expr
.X_op
== O_symbol
);
6172 expr1
.X_add_number
= offset_expr
.X_add_number
;
6173 offset_expr
.X_add_number
= 0;
6174 if (expr1
.X_add_number
< -0x8000
6175 || expr1
.X_add_number
>= 0x8000)
6176 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6177 relax_start (offset_expr
.X_add_symbol
);
6178 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6179 BFD_RELOC_MIPS_GOT_HI16
);
6180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6182 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6183 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6185 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6186 tempreg
, tempreg
, breg
);
6187 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6190 offset_expr
.X_add_number
= expr1
.X_add_number
;
6191 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6192 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6194 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6195 tempreg
, tempreg
, breg
);
6196 macro_build (&offset_expr
, s
, fmt
, treg
,
6197 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6207 load_register (treg
, &imm_expr
, 0);
6211 load_register (treg
, &imm_expr
, 1);
6215 if (imm_expr
.X_op
== O_constant
)
6218 load_register (AT
, &imm_expr
, 0);
6219 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6224 assert (offset_expr
.X_op
== O_symbol
6225 && strcmp (segment_name (S_GET_SEGMENT
6226 (offset_expr
.X_add_symbol
)),
6228 && offset_expr
.X_add_number
== 0);
6229 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6230 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6235 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6236 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6237 order 32 bits of the value and the low order 32 bits are either
6238 zero or in OFFSET_EXPR. */
6239 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6241 if (HAVE_64BIT_GPRS
)
6242 load_register (treg
, &imm_expr
, 1);
6247 if (target_big_endian
)
6259 load_register (hreg
, &imm_expr
, 0);
6262 if (offset_expr
.X_op
== O_absent
)
6263 move_register (lreg
, 0);
6266 assert (offset_expr
.X_op
== O_constant
);
6267 load_register (lreg
, &offset_expr
, 0);
6274 /* We know that sym is in the .rdata section. First we get the
6275 upper 16 bits of the address. */
6276 if (mips_pic
== NO_PIC
)
6278 macro_build_lui (&offset_expr
, AT
);
6281 else if (mips_pic
== SVR4_PIC
)
6283 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6284 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6290 /* Now we load the register(s). */
6291 if (HAVE_64BIT_GPRS
)
6294 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6299 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6302 /* FIXME: How in the world do we deal with the possible
6304 offset_expr
.X_add_number
+= 4;
6305 macro_build (&offset_expr
, "lw", "t,o(b)",
6306 treg
+ 1, BFD_RELOC_LO16
, AT
);
6312 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6313 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6314 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6315 the value and the low order 32 bits are either zero or in
6317 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6320 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6321 if (HAVE_64BIT_FPRS
)
6323 assert (HAVE_64BIT_GPRS
);
6324 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6328 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6329 if (offset_expr
.X_op
== O_absent
)
6330 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6333 assert (offset_expr
.X_op
== O_constant
);
6334 load_register (AT
, &offset_expr
, 0);
6335 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6341 assert (offset_expr
.X_op
== O_symbol
6342 && offset_expr
.X_add_number
== 0);
6343 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6344 if (strcmp (s
, ".lit8") == 0)
6346 if (mips_opts
.isa
!= ISA_MIPS1
)
6348 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6349 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6352 breg
= mips_gp_register
;
6353 r
= BFD_RELOC_MIPS_LITERAL
;
6358 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6360 if (mips_pic
== SVR4_PIC
)
6361 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6362 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6365 /* FIXME: This won't work for a 64 bit address. */
6366 macro_build_lui (&offset_expr
, AT
);
6369 if (mips_opts
.isa
!= ISA_MIPS1
)
6371 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6372 treg
, BFD_RELOC_LO16
, AT
);
6381 if (mips_opts
.arch
== CPU_R4650
)
6383 as_bad (_("opcode not supported on this processor"));
6386 /* Even on a big endian machine $fn comes before $fn+1. We have
6387 to adjust when loading from memory. */
6390 assert (mips_opts
.isa
== ISA_MIPS1
);
6391 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6392 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6393 /* FIXME: A possible overflow which I don't know how to deal
6395 offset_expr
.X_add_number
+= 4;
6396 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6397 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6402 * The MIPS assembler seems to check for X_add_number not
6403 * being double aligned and generating:
6406 * addiu at,at,%lo(foo+1)
6409 * But, the resulting address is the same after relocation so why
6410 * generate the extra instruction?
6412 if (mips_opts
.arch
== CPU_R4650
)
6414 as_bad (_("opcode not supported on this processor"));
6417 /* Itbl support may require additional care here. */
6419 if (mips_opts
.isa
!= ISA_MIPS1
)
6430 if (mips_opts
.arch
== CPU_R4650
)
6432 as_bad (_("opcode not supported on this processor"));
6436 if (mips_opts
.isa
!= ISA_MIPS1
)
6444 /* Itbl support may require additional care here. */
6449 if (HAVE_64BIT_GPRS
)
6460 if (HAVE_64BIT_GPRS
)
6470 if (offset_expr
.X_op
!= O_symbol
6471 && offset_expr
.X_op
!= O_constant
)
6473 as_bad (_("expression too complex"));
6474 offset_expr
.X_op
= O_constant
;
6477 /* Even on a big endian machine $fn comes before $fn+1. We have
6478 to adjust when loading from memory. We set coproc if we must
6479 load $fn+1 first. */
6480 /* Itbl support may require additional care here. */
6481 if (! target_big_endian
)
6484 if (mips_pic
== NO_PIC
6485 || offset_expr
.X_op
== O_constant
)
6487 /* If this is a reference to a GP relative symbol, we want
6488 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6489 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6490 If we have a base register, we use this
6492 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6493 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6494 If this is not a GP relative symbol, we want
6495 lui $at,<sym> (BFD_RELOC_HI16_S)
6496 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6497 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6498 If there is a base register, we add it to $at after the
6499 lui instruction. If there is a constant, we always use
6501 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6502 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6506 relax_start (offset_expr
.X_add_symbol
);
6509 tempreg
= mips_gp_register
;
6513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6514 AT
, breg
, mips_gp_register
);
6519 /* Itbl support may require additional care here. */
6520 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6521 BFD_RELOC_GPREL16
, tempreg
);
6522 offset_expr
.X_add_number
+= 4;
6524 /* Set mips_optimize to 2 to avoid inserting an
6526 hold_mips_optimize
= mips_optimize
;
6528 /* Itbl support may require additional care here. */
6529 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6530 BFD_RELOC_GPREL16
, tempreg
);
6531 mips_optimize
= hold_mips_optimize
;
6535 /* We just generated two relocs. When tc_gen_reloc
6536 handles this case, it will skip the first reloc and
6537 handle the second. The second reloc already has an
6538 extra addend of 4, which we added above. We must
6539 subtract it out, and then subtract another 4 to make
6540 the first reloc come out right. The second reloc
6541 will come out right because we are going to add 4 to
6542 offset_expr when we build its instruction below.
6544 If we have a symbol, then we don't want to include
6545 the offset, because it will wind up being included
6546 when we generate the reloc. */
6548 if (offset_expr
.X_op
== O_constant
)
6549 offset_expr
.X_add_number
-= 8;
6552 offset_expr
.X_add_number
= -4;
6553 offset_expr
.X_op
= O_constant
;
6557 macro_build_lui (&offset_expr
, AT
);
6559 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6560 /* Itbl support may require additional care here. */
6561 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6562 BFD_RELOC_LO16
, AT
);
6563 /* FIXME: How do we handle overflow here? */
6564 offset_expr
.X_add_number
+= 4;
6565 /* Itbl support may require additional care here. */
6566 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6567 BFD_RELOC_LO16
, AT
);
6568 if (mips_relax
.sequence
)
6571 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6573 /* If this is a reference to an external symbol, we want
6574 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6579 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6581 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6582 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6583 If there is a base register we add it to $at before the
6584 lwc1 instructions. If there is a constant we include it
6585 in the lwc1 instructions. */
6587 expr1
.X_add_number
= offset_expr
.X_add_number
;
6588 if (expr1
.X_add_number
< -0x8000
6589 || expr1
.X_add_number
>= 0x8000 - 4)
6590 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6591 load_got_offset (AT
, &offset_expr
);
6594 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6596 /* Set mips_optimize to 2 to avoid inserting an undesired
6598 hold_mips_optimize
= mips_optimize
;
6601 /* Itbl support may require additional care here. */
6602 relax_start (offset_expr
.X_add_symbol
);
6603 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6604 BFD_RELOC_LO16
, AT
);
6605 expr1
.X_add_number
+= 4;
6606 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6607 BFD_RELOC_LO16
, AT
);
6609 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6610 BFD_RELOC_LO16
, AT
);
6611 offset_expr
.X_add_number
+= 4;
6612 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6613 BFD_RELOC_LO16
, AT
);
6616 mips_optimize
= hold_mips_optimize
;
6618 else if (mips_pic
== SVR4_PIC
)
6622 /* If this is a reference to an external symbol, we want
6623 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6625 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6630 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6632 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6633 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6634 If there is a base register we add it to $at before the
6635 lwc1 instructions. If there is a constant we include it
6636 in the lwc1 instructions. */
6638 expr1
.X_add_number
= offset_expr
.X_add_number
;
6639 offset_expr
.X_add_number
= 0;
6640 if (expr1
.X_add_number
< -0x8000
6641 || expr1
.X_add_number
>= 0x8000 - 4)
6642 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6643 gpdelay
= reg_needs_delay (mips_gp_register
);
6644 relax_start (offset_expr
.X_add_symbol
);
6645 macro_build (&offset_expr
, "lui", "t,u",
6646 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6648 AT
, AT
, mips_gp_register
);
6649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6650 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6654 /* Itbl support may require additional care here. */
6655 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6656 BFD_RELOC_LO16
, AT
);
6657 expr1
.X_add_number
+= 4;
6659 /* Set mips_optimize to 2 to avoid inserting an undesired
6661 hold_mips_optimize
= mips_optimize
;
6663 /* Itbl support may require additional care here. */
6664 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6665 BFD_RELOC_LO16
, AT
);
6666 mips_optimize
= hold_mips_optimize
;
6667 expr1
.X_add_number
-= 4;
6670 offset_expr
.X_add_number
= expr1
.X_add_number
;
6672 macro_build (NULL
, "nop", "");
6673 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6674 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6677 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6678 /* Itbl support may require additional care here. */
6679 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6680 BFD_RELOC_LO16
, AT
);
6681 offset_expr
.X_add_number
+= 4;
6683 /* Set mips_optimize to 2 to avoid inserting an undesired
6685 hold_mips_optimize
= mips_optimize
;
6687 /* Itbl support may require additional care here. */
6688 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6689 BFD_RELOC_LO16
, AT
);
6690 mips_optimize
= hold_mips_optimize
;
6704 assert (HAVE_32BIT_ADDRESSES
);
6705 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6706 offset_expr
.X_add_number
+= 4;
6707 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6710 /* New code added to support COPZ instructions.
6711 This code builds table entries out of the macros in mip_opcodes.
6712 R4000 uses interlocks to handle coproc delays.
6713 Other chips (like the R3000) require nops to be inserted for delays.
6715 FIXME: Currently, we require that the user handle delays.
6716 In order to fill delay slots for non-interlocked chips,
6717 we must have a way to specify delays based on the coprocessor.
6718 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6719 What are the side-effects of the cop instruction?
6720 What cache support might we have and what are its effects?
6721 Both coprocessor & memory require delays. how long???
6722 What registers are read/set/modified?
6724 If an itbl is provided to interpret cop instructions,
6725 this knowledge can be encoded in the itbl spec. */
6739 /* For now we just do C (same as Cz). The parameter will be
6740 stored in insn_opcode by mips_ip. */
6741 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6745 move_register (dreg
, sreg
);
6748 #ifdef LOSING_COMPILER
6750 /* Try and see if this is a new itbl instruction.
6751 This code builds table entries out of the macros in mip_opcodes.
6752 FIXME: For now we just assemble the expression and pass it's
6753 value along as a 32-bit immediate.
6754 We may want to have the assembler assemble this value,
6755 so that we gain the assembler's knowledge of delay slots,
6757 Would it be more efficient to use mask (id) here? */
6758 if (itbl_have_entries
6759 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6761 s
= ip
->insn_mo
->name
;
6763 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6764 macro_build (&immed_expr
, s
, "C");
6770 if (mips_opts
.noat
&& used_at
)
6771 as_bad (_("Macro used $at after \".set noat\""));
6775 macro2 (struct mips_cl_insn
*ip
)
6777 register int treg
, sreg
, dreg
, breg
;
6792 bfd_reloc_code_real_type r
;
6794 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6795 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6796 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6797 mask
= ip
->insn_mo
->mask
;
6799 expr1
.X_op
= O_constant
;
6800 expr1
.X_op_symbol
= NULL
;
6801 expr1
.X_add_symbol
= NULL
;
6802 expr1
.X_add_number
= 1;
6806 #endif /* LOSING_COMPILER */
6811 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6812 macro_build (NULL
, "mflo", "d", dreg
);
6818 /* The MIPS assembler some times generates shifts and adds. I'm
6819 not trying to be that fancy. GCC should do this for us
6822 load_register (AT
, &imm_expr
, dbl
);
6823 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6824 macro_build (NULL
, "mflo", "d", dreg
);
6837 mips_emit_delays (TRUE
);
6838 ++mips_opts
.noreorder
;
6839 mips_any_noreorder
= 1;
6842 load_register (AT
, &imm_expr
, dbl
);
6843 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6844 macro_build (NULL
, "mflo", "d", dreg
);
6845 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6846 macro_build (NULL
, "mfhi", "d", AT
);
6848 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6851 expr1
.X_add_number
= 8;
6852 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6853 macro_build (NULL
, "nop", "", 0);
6854 macro_build (NULL
, "break", "c", 6);
6856 --mips_opts
.noreorder
;
6857 macro_build (NULL
, "mflo", "d", dreg
);
6870 mips_emit_delays (TRUE
);
6871 ++mips_opts
.noreorder
;
6872 mips_any_noreorder
= 1;
6875 load_register (AT
, &imm_expr
, dbl
);
6876 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6877 sreg
, imm
? AT
: treg
);
6878 macro_build (NULL
, "mfhi", "d", AT
);
6879 macro_build (NULL
, "mflo", "d", dreg
);
6881 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6884 expr1
.X_add_number
= 8;
6885 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6886 macro_build (NULL
, "nop", "", 0);
6887 macro_build (NULL
, "break", "c", 6);
6889 --mips_opts
.noreorder
;
6893 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6904 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6905 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6909 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6910 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6911 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6912 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6916 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6927 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6928 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6932 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6933 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6934 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6935 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6943 if (imm_expr
.X_op
!= O_constant
)
6944 as_bad (_("Improper rotate count"));
6945 rot
= imm_expr
.X_add_number
& 0x3f;
6946 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6948 rot
= (64 - rot
) & 0x3f;
6950 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6952 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6957 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6960 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6961 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6964 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6965 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6966 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6974 if (imm_expr
.X_op
!= O_constant
)
6975 as_bad (_("Improper rotate count"));
6976 rot
= imm_expr
.X_add_number
& 0x1f;
6977 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6979 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6984 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6988 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6989 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6990 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6995 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6997 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7001 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7002 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7003 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7004 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7008 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7010 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7014 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7015 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7016 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7017 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7025 if (imm_expr
.X_op
!= O_constant
)
7026 as_bad (_("Improper rotate count"));
7027 rot
= imm_expr
.X_add_number
& 0x3f;
7028 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7031 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7033 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7038 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7041 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7042 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7045 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7046 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7047 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7055 if (imm_expr
.X_op
!= O_constant
)
7056 as_bad (_("Improper rotate count"));
7057 rot
= imm_expr
.X_add_number
& 0x1f;
7058 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7060 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7065 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7069 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7070 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7071 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7076 if (mips_opts
.arch
== CPU_R4650
)
7078 as_bad (_("opcode not supported on this processor"));
7081 assert (mips_opts
.isa
== ISA_MIPS1
);
7082 /* Even on a big endian machine $fn comes before $fn+1. We have
7083 to adjust when storing to memory. */
7084 macro_build (&offset_expr
, "swc1", "T,o(b)",
7085 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7086 offset_expr
.X_add_number
+= 4;
7087 macro_build (&offset_expr
, "swc1", "T,o(b)",
7088 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7093 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7095 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7098 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7099 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7104 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7106 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7111 as_warn (_("Instruction %s: result is always false"),
7113 move_register (dreg
, 0);
7116 if (imm_expr
.X_op
== O_constant
7117 && imm_expr
.X_add_number
>= 0
7118 && imm_expr
.X_add_number
< 0x10000)
7120 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7122 else if (imm_expr
.X_op
== O_constant
7123 && imm_expr
.X_add_number
> -0x8000
7124 && imm_expr
.X_add_number
< 0)
7126 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7127 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7128 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7132 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7133 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7136 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7139 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7145 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7146 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7149 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7151 if (imm_expr
.X_op
== O_constant
7152 && imm_expr
.X_add_number
>= -0x8000
7153 && imm_expr
.X_add_number
< 0x8000)
7155 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7156 dreg
, sreg
, BFD_RELOC_LO16
);
7160 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7161 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7165 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7168 case M_SGT
: /* sreg > treg <==> treg < sreg */
7174 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7177 case M_SGT_I
: /* sreg > I <==> I < sreg */
7184 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7185 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7188 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7194 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7195 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7198 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7205 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7206 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7207 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7211 if (imm_expr
.X_op
== O_constant
7212 && imm_expr
.X_add_number
>= -0x8000
7213 && imm_expr
.X_add_number
< 0x8000)
7215 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7219 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7220 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7224 if (imm_expr
.X_op
== O_constant
7225 && imm_expr
.X_add_number
>= -0x8000
7226 && imm_expr
.X_add_number
< 0x8000)
7228 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7233 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7234 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7239 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7241 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7244 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7245 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7250 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7252 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7257 as_warn (_("Instruction %s: result is always true"),
7259 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7260 dreg
, 0, BFD_RELOC_LO16
);
7263 if (imm_expr
.X_op
== O_constant
7264 && imm_expr
.X_add_number
>= 0
7265 && imm_expr
.X_add_number
< 0x10000)
7267 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7269 else if (imm_expr
.X_op
== O_constant
7270 && imm_expr
.X_add_number
> -0x8000
7271 && imm_expr
.X_add_number
< 0)
7273 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7274 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7275 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7279 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7280 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7283 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7289 if (imm_expr
.X_op
== O_constant
7290 && imm_expr
.X_add_number
> -0x8000
7291 && imm_expr
.X_add_number
<= 0x8000)
7293 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7294 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7295 dreg
, sreg
, BFD_RELOC_LO16
);
7299 load_register (AT
, &imm_expr
, dbl
);
7300 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7306 if (imm_expr
.X_op
== O_constant
7307 && imm_expr
.X_add_number
> -0x8000
7308 && imm_expr
.X_add_number
<= 0x8000)
7310 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7311 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7312 dreg
, sreg
, BFD_RELOC_LO16
);
7316 load_register (AT
, &imm_expr
, dbl
);
7317 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7339 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7340 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7345 assert (mips_opts
.isa
== ISA_MIPS1
);
7347 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7348 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7351 * Is the double cfc1 instruction a bug in the mips assembler;
7352 * or is there a reason for it?
7354 mips_emit_delays (TRUE
);
7355 ++mips_opts
.noreorder
;
7356 mips_any_noreorder
= 1;
7357 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7358 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7359 macro_build (NULL
, "nop", "");
7360 expr1
.X_add_number
= 3;
7361 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7362 expr1
.X_add_number
= 2;
7363 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7364 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7365 macro_build (NULL
, "nop", "");
7366 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7368 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7369 macro_build (NULL
, "nop", "");
7370 --mips_opts
.noreorder
;
7380 if (offset_expr
.X_add_number
>= 0x7fff)
7381 as_bad (_("operand overflow"));
7382 if (! target_big_endian
)
7383 ++offset_expr
.X_add_number
;
7384 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7385 if (! target_big_endian
)
7386 --offset_expr
.X_add_number
;
7388 ++offset_expr
.X_add_number
;
7389 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7390 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7391 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7404 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7405 as_bad (_("operand overflow"));
7413 if (! target_big_endian
)
7414 offset_expr
.X_add_number
+= off
;
7415 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7416 if (! target_big_endian
)
7417 offset_expr
.X_add_number
-= off
;
7419 offset_expr
.X_add_number
+= off
;
7420 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7422 /* If necessary, move the result in tempreg the final destination. */
7423 if (treg
== tempreg
)
7425 /* Protect second load's delay slot. */
7427 move_register (treg
, tempreg
);
7441 load_address (AT
, &offset_expr
, &used_at
);
7443 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7444 if (! target_big_endian
)
7445 expr1
.X_add_number
= off
;
7447 expr1
.X_add_number
= 0;
7448 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7449 if (! target_big_endian
)
7450 expr1
.X_add_number
= 0;
7452 expr1
.X_add_number
= off
;
7453 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7459 load_address (AT
, &offset_expr
, &used_at
);
7461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7462 if (target_big_endian
)
7463 expr1
.X_add_number
= 0;
7464 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7465 treg
, BFD_RELOC_LO16
, AT
);
7466 if (target_big_endian
)
7467 expr1
.X_add_number
= 1;
7469 expr1
.X_add_number
= 0;
7470 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7471 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7472 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7477 if (offset_expr
.X_add_number
>= 0x7fff)
7478 as_bad (_("operand overflow"));
7479 if (target_big_endian
)
7480 ++offset_expr
.X_add_number
;
7481 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7482 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7483 if (target_big_endian
)
7484 --offset_expr
.X_add_number
;
7486 ++offset_expr
.X_add_number
;
7487 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7500 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7501 as_bad (_("operand overflow"));
7502 if (! target_big_endian
)
7503 offset_expr
.X_add_number
+= off
;
7504 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7505 if (! target_big_endian
)
7506 offset_expr
.X_add_number
-= off
;
7508 offset_expr
.X_add_number
+= off
;
7509 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7523 load_address (AT
, &offset_expr
, &used_at
);
7525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7526 if (! target_big_endian
)
7527 expr1
.X_add_number
= off
;
7529 expr1
.X_add_number
= 0;
7530 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7531 if (! target_big_endian
)
7532 expr1
.X_add_number
= 0;
7534 expr1
.X_add_number
= off
;
7535 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7540 load_address (AT
, &offset_expr
, &used_at
);
7542 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7543 if (! target_big_endian
)
7544 expr1
.X_add_number
= 0;
7545 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7546 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7547 if (! target_big_endian
)
7548 expr1
.X_add_number
= 1;
7550 expr1
.X_add_number
= 0;
7551 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7552 if (! target_big_endian
)
7553 expr1
.X_add_number
= 0;
7555 expr1
.X_add_number
= 1;
7556 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7557 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7558 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7562 /* FIXME: Check if this is one of the itbl macros, since they
7563 are added dynamically. */
7564 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7567 if (mips_opts
.noat
&& used_at
)
7568 as_bad (_("Macro used $at after \".set noat\""));
7571 /* Implement macros in mips16 mode. */
7574 mips16_macro (struct mips_cl_insn
*ip
)
7577 int xreg
, yreg
, zreg
, tmp
;
7580 const char *s
, *s2
, *s3
;
7582 mask
= ip
->insn_mo
->mask
;
7584 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7585 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7586 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7588 expr1
.X_op
= O_constant
;
7589 expr1
.X_op_symbol
= NULL
;
7590 expr1
.X_add_symbol
= NULL
;
7591 expr1
.X_add_number
= 1;
7610 mips_emit_delays (TRUE
);
7611 ++mips_opts
.noreorder
;
7612 mips_any_noreorder
= 1;
7613 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7614 expr1
.X_add_number
= 2;
7615 macro_build (&expr1
, "bnez", "x,p", yreg
);
7616 macro_build (NULL
, "break", "6", 7);
7618 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7619 since that causes an overflow. We should do that as well,
7620 but I don't see how to do the comparisons without a temporary
7622 --mips_opts
.noreorder
;
7623 macro_build (NULL
, s
, "x", zreg
);
7642 mips_emit_delays (TRUE
);
7643 ++mips_opts
.noreorder
;
7644 mips_any_noreorder
= 1;
7645 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7646 expr1
.X_add_number
= 2;
7647 macro_build (&expr1
, "bnez", "x,p", yreg
);
7648 macro_build (NULL
, "break", "6", 7);
7649 --mips_opts
.noreorder
;
7650 macro_build (NULL
, s2
, "x", zreg
);
7656 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7657 macro_build (NULL
, "mflo", "x", zreg
);
7665 if (imm_expr
.X_op
!= O_constant
)
7666 as_bad (_("Unsupported large constant"));
7667 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7668 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7672 if (imm_expr
.X_op
!= O_constant
)
7673 as_bad (_("Unsupported large constant"));
7674 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7675 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7679 if (imm_expr
.X_op
!= O_constant
)
7680 as_bad (_("Unsupported large constant"));
7681 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7682 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7704 goto do_reverse_branch
;
7708 goto do_reverse_branch
;
7720 goto do_reverse_branch
;
7731 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7732 macro_build (&offset_expr
, s2
, "p");
7759 goto do_addone_branch_i
;
7764 goto do_addone_branch_i
;
7779 goto do_addone_branch_i
;
7786 if (imm_expr
.X_op
!= O_constant
)
7787 as_bad (_("Unsupported large constant"));
7788 ++imm_expr
.X_add_number
;
7791 macro_build (&imm_expr
, s
, s3
, xreg
);
7792 macro_build (&offset_expr
, s2
, "p");
7796 expr1
.X_add_number
= 0;
7797 macro_build (&expr1
, "slti", "x,8", yreg
);
7799 move_register (xreg
, yreg
);
7800 expr1
.X_add_number
= 2;
7801 macro_build (&expr1
, "bteqz", "p");
7802 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7806 /* For consistency checking, verify that all bits are specified either
7807 by the match/mask part of the instruction definition, or by the
7810 validate_mips_insn (const struct mips_opcode
*opc
)
7812 const char *p
= opc
->args
;
7814 unsigned long used_bits
= opc
->mask
;
7816 if ((used_bits
& opc
->match
) != opc
->match
)
7818 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7819 opc
->name
, opc
->args
);
7822 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7832 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7833 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7834 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7835 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7836 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7837 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7838 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7839 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7840 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7843 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7844 c
, opc
->name
, opc
->args
);
7848 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7849 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7851 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7852 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7853 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7854 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7856 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7857 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7859 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7860 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7862 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7863 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7864 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7865 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7866 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7867 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7868 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7869 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7870 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7871 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7872 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7873 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7874 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7875 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7876 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7877 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7878 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7880 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7881 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7882 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7883 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7885 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7886 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7887 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7888 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7889 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7890 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7891 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7892 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7893 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7896 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7897 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7898 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7899 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7900 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7904 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7905 c
, opc
->name
, opc
->args
);
7909 if (used_bits
!= 0xffffffff)
7911 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7912 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7918 /* This routine assembles an instruction into its binary format. As a
7919 side effect, it sets one of the global variables imm_reloc or
7920 offset_reloc to the type of relocation to do if one of the operands
7921 is an address expression. */
7924 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7929 struct mips_opcode
*insn
;
7932 unsigned int lastregno
= 0;
7933 unsigned int lastpos
= 0;
7934 unsigned int limlo
, limhi
;
7940 /* If the instruction contains a '.', we first try to match an instruction
7941 including the '.'. Then we try again without the '.'. */
7943 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7946 /* If we stopped on whitespace, then replace the whitespace with null for
7947 the call to hash_find. Save the character we replaced just in case we
7948 have to re-parse the instruction. */
7955 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7957 /* If we didn't find the instruction in the opcode table, try again, but
7958 this time with just the instruction up to, but not including the
7962 /* Restore the character we overwrite above (if any). */
7966 /* Scan up to the first '.' or whitespace. */
7968 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7972 /* If we did not find a '.', then we can quit now. */
7975 insn_error
= "unrecognized opcode";
7979 /* Lookup the instruction in the hash table. */
7981 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7983 insn_error
= "unrecognized opcode";
7993 assert (strcmp (insn
->name
, str
) == 0);
7995 if (OPCODE_IS_MEMBER (insn
,
7997 | (file_ase_mips16
? INSN_MIPS16
: 0)
7998 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7999 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8005 if (insn
->pinfo
!= INSN_MACRO
)
8007 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8013 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8014 && strcmp (insn
->name
, insn
[1].name
) == 0)
8023 static char buf
[100];
8025 _("opcode not supported on this processor: %s (%s)"),
8026 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8027 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8037 ip
->insn_opcode
= insn
->match
;
8039 for (args
= insn
->args
;; ++args
)
8043 s
+= strspn (s
, " \t");
8047 case '\0': /* end of args */
8060 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8064 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8068 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8072 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8078 /* Handle optional base register.
8079 Either the base register is omitted or
8080 we must have a left paren. */
8081 /* This is dependent on the next operand specifier
8082 is a base register specification. */
8083 assert (args
[1] == 'b' || args
[1] == '5'
8084 || args
[1] == '-' || args
[1] == '4');
8088 case ')': /* these must match exactly */
8095 case '+': /* Opcode extension character. */
8098 case 'A': /* ins/ext position, becomes LSB. */
8107 my_getExpression (&imm_expr
, s
);
8108 check_absolute_expr (ip
, &imm_expr
);
8109 if ((unsigned long) imm_expr
.X_add_number
< limlo
8110 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8112 as_bad (_("Improper position (%lu)"),
8113 (unsigned long) imm_expr
.X_add_number
);
8114 imm_expr
.X_add_number
= limlo
;
8116 lastpos
= imm_expr
.X_add_number
;
8117 ip
->insn_opcode
|= (imm_expr
.X_add_number
8118 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8119 imm_expr
.X_op
= O_absent
;
8123 case 'B': /* ins size, becomes MSB. */
8132 my_getExpression (&imm_expr
, s
);
8133 check_absolute_expr (ip
, &imm_expr
);
8134 /* Check for negative input so that small negative numbers
8135 will not succeed incorrectly. The checks against
8136 (pos+size) transitively check "size" itself,
8137 assuming that "pos" is reasonable. */
8138 if ((long) imm_expr
.X_add_number
< 0
8139 || ((unsigned long) imm_expr
.X_add_number
8141 || ((unsigned long) imm_expr
.X_add_number
8144 as_bad (_("Improper insert size (%lu, position %lu)"),
8145 (unsigned long) imm_expr
.X_add_number
,
8146 (unsigned long) lastpos
);
8147 imm_expr
.X_add_number
= limlo
- lastpos
;
8149 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8150 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8151 imm_expr
.X_op
= O_absent
;
8155 case 'C': /* ext size, becomes MSBD. */
8168 my_getExpression (&imm_expr
, s
);
8169 check_absolute_expr (ip
, &imm_expr
);
8170 /* Check for negative input so that small negative numbers
8171 will not succeed incorrectly. The checks against
8172 (pos+size) transitively check "size" itself,
8173 assuming that "pos" is reasonable. */
8174 if ((long) imm_expr
.X_add_number
< 0
8175 || ((unsigned long) imm_expr
.X_add_number
8177 || ((unsigned long) imm_expr
.X_add_number
8180 as_bad (_("Improper extract size (%lu, position %lu)"),
8181 (unsigned long) imm_expr
.X_add_number
,
8182 (unsigned long) lastpos
);
8183 imm_expr
.X_add_number
= limlo
- lastpos
;
8185 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8186 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8187 imm_expr
.X_op
= O_absent
;
8192 /* +D is for disassembly only; never match. */
8196 /* "+I" is like "I", except that imm2_expr is used. */
8197 my_getExpression (&imm2_expr
, s
);
8198 if (imm2_expr
.X_op
!= O_big
8199 && imm2_expr
.X_op
!= O_constant
)
8200 insn_error
= _("absolute expression required");
8201 normalize_constant_expr (&imm2_expr
);
8206 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8207 *args
, insn
->name
, insn
->args
);
8208 /* Further processing is fruitless. */
8213 case '<': /* must be at least one digit */
8215 * According to the manual, if the shift amount is greater
8216 * than 31 or less than 0, then the shift amount should be
8217 * mod 32. In reality the mips assembler issues an error.
8218 * We issue a warning and mask out all but the low 5 bits.
8220 my_getExpression (&imm_expr
, s
);
8221 check_absolute_expr (ip
, &imm_expr
);
8222 if ((unsigned long) imm_expr
.X_add_number
> 31)
8224 as_warn (_("Improper shift amount (%lu)"),
8225 (unsigned long) imm_expr
.X_add_number
);
8226 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8228 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8229 imm_expr
.X_op
= O_absent
;
8233 case '>': /* shift amount minus 32 */
8234 my_getExpression (&imm_expr
, s
);
8235 check_absolute_expr (ip
, &imm_expr
);
8236 if ((unsigned long) imm_expr
.X_add_number
< 32
8237 || (unsigned long) imm_expr
.X_add_number
> 63)
8239 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8240 imm_expr
.X_op
= O_absent
;
8244 case 'k': /* cache code */
8245 case 'h': /* prefx code */
8246 my_getExpression (&imm_expr
, s
);
8247 check_absolute_expr (ip
, &imm_expr
);
8248 if ((unsigned long) imm_expr
.X_add_number
> 31)
8250 as_warn (_("Invalid value for `%s' (%lu)"),
8252 (unsigned long) imm_expr
.X_add_number
);
8253 imm_expr
.X_add_number
&= 0x1f;
8256 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8258 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8259 imm_expr
.X_op
= O_absent
;
8263 case 'c': /* break code */
8264 my_getExpression (&imm_expr
, s
);
8265 check_absolute_expr (ip
, &imm_expr
);
8266 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8268 as_warn (_("Illegal break code (%lu)"),
8269 (unsigned long) imm_expr
.X_add_number
);
8270 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8272 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8273 imm_expr
.X_op
= O_absent
;
8277 case 'q': /* lower break code */
8278 my_getExpression (&imm_expr
, s
);
8279 check_absolute_expr (ip
, &imm_expr
);
8280 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8282 as_warn (_("Illegal lower break code (%lu)"),
8283 (unsigned long) imm_expr
.X_add_number
);
8284 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8286 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8287 imm_expr
.X_op
= O_absent
;
8291 case 'B': /* 20-bit syscall/break code. */
8292 my_getExpression (&imm_expr
, s
);
8293 check_absolute_expr (ip
, &imm_expr
);
8294 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8295 as_warn (_("Illegal 20-bit code (%lu)"),
8296 (unsigned long) imm_expr
.X_add_number
);
8297 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8298 imm_expr
.X_op
= O_absent
;
8302 case 'C': /* Coprocessor code */
8303 my_getExpression (&imm_expr
, s
);
8304 check_absolute_expr (ip
, &imm_expr
);
8305 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8307 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8308 (unsigned long) imm_expr
.X_add_number
);
8309 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8311 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8312 imm_expr
.X_op
= O_absent
;
8316 case 'J': /* 19-bit wait code. */
8317 my_getExpression (&imm_expr
, s
);
8318 check_absolute_expr (ip
, &imm_expr
);
8319 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8320 as_warn (_("Illegal 19-bit code (%lu)"),
8321 (unsigned long) imm_expr
.X_add_number
);
8322 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8323 imm_expr
.X_op
= O_absent
;
8327 case 'P': /* Performance register */
8328 my_getExpression (&imm_expr
, s
);
8329 check_absolute_expr (ip
, &imm_expr
);
8330 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8332 as_warn (_("Invalid performance register (%lu)"),
8333 (unsigned long) imm_expr
.X_add_number
);
8334 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8336 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8337 imm_expr
.X_op
= O_absent
;
8341 case 'b': /* base register */
8342 case 'd': /* destination register */
8343 case 's': /* source register */
8344 case 't': /* target register */
8345 case 'r': /* both target and source */
8346 case 'v': /* both dest and source */
8347 case 'w': /* both dest and target */
8348 case 'E': /* coprocessor target register */
8349 case 'G': /* coprocessor destination register */
8350 case 'K': /* 'rdhwr' destination register */
8351 case 'x': /* ignore register name */
8352 case 'z': /* must be zero register */
8353 case 'U': /* destination register (clo/clz). */
8368 while (ISDIGIT (*s
));
8370 as_bad (_("Invalid register number (%d)"), regno
);
8372 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8376 if (s
[1] == 'r' && s
[2] == 'a')
8381 else if (s
[1] == 'f' && s
[2] == 'p')
8386 else if (s
[1] == 's' && s
[2] == 'p')
8391 else if (s
[1] == 'g' && s
[2] == 'p')
8396 else if (s
[1] == 'a' && s
[2] == 't')
8401 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8406 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8411 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8416 else if (itbl_have_entries
)
8421 p
= s
+ 1; /* advance past '$' */
8422 n
= itbl_get_field (&p
); /* n is name */
8424 /* See if this is a register defined in an
8426 if (itbl_get_reg_val (n
, &r
))
8428 /* Get_field advances to the start of
8429 the next field, so we need to back
8430 rack to the end of the last field. */
8434 s
= strchr (s
, '\0');
8448 as_warn (_("Used $at without \".set noat\""));
8454 if (c
== 'r' || c
== 'v' || c
== 'w')
8461 /* 'z' only matches $0. */
8462 if (c
== 'z' && regno
!= 0)
8465 /* Now that we have assembled one operand, we use the args string
8466 * to figure out where it goes in the instruction. */
8473 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8478 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8481 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8482 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8487 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8490 /* This case exists because on the r3000 trunc
8491 expands into a macro which requires a gp
8492 register. On the r6000 or r4000 it is
8493 assembled into a single instruction which
8494 ignores the register. Thus the insn version
8495 is MIPS_ISA2 and uses 'x', and the macro
8496 version is MIPS_ISA1 and uses 't'. */
8499 /* This case is for the div instruction, which
8500 acts differently if the destination argument
8501 is $0. This only matches $0, and is checked
8502 outside the switch. */
8505 /* Itbl operand; not yet implemented. FIXME ?? */
8507 /* What about all other operands like 'i', which
8508 can be specified in the opcode table? */
8518 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8521 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8526 case 'O': /* MDMX alignment immediate constant. */
8527 my_getExpression (&imm_expr
, s
);
8528 check_absolute_expr (ip
, &imm_expr
);
8529 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8531 as_warn ("Improper align amount (%ld), using low bits",
8532 (long) imm_expr
.X_add_number
);
8533 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8535 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8536 imm_expr
.X_op
= O_absent
;
8540 case 'Q': /* MDMX vector, element sel, or const. */
8543 /* MDMX Immediate. */
8544 my_getExpression (&imm_expr
, s
);
8545 check_absolute_expr (ip
, &imm_expr
);
8546 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8548 as_warn (_("Invalid MDMX Immediate (%ld)"),
8549 (long) imm_expr
.X_add_number
);
8550 imm_expr
.X_add_number
&= OP_MASK_FT
;
8552 imm_expr
.X_add_number
&= OP_MASK_FT
;
8553 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8554 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8556 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8557 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8558 imm_expr
.X_op
= O_absent
;
8562 /* Not MDMX Immediate. Fall through. */
8563 case 'X': /* MDMX destination register. */
8564 case 'Y': /* MDMX source register. */
8565 case 'Z': /* MDMX target register. */
8567 case 'D': /* floating point destination register */
8568 case 'S': /* floating point source register */
8569 case 'T': /* floating point target register */
8570 case 'R': /* floating point source register */
8574 /* Accept $fN for FP and MDMX register numbers, and in
8575 addition accept $vN for MDMX register numbers. */
8576 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8577 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8588 while (ISDIGIT (*s
));
8591 as_bad (_("Invalid float register number (%d)"), regno
);
8593 if ((regno
& 1) != 0
8595 && ! (strcmp (str
, "mtc1") == 0
8596 || strcmp (str
, "mfc1") == 0
8597 || strcmp (str
, "lwc1") == 0
8598 || strcmp (str
, "swc1") == 0
8599 || strcmp (str
, "l.s") == 0
8600 || strcmp (str
, "s.s") == 0))
8601 as_warn (_("Float register should be even, was %d"),
8609 if (c
== 'V' || c
== 'W')
8620 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8625 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8628 /* This is like 'Z', but also needs to fix the MDMX
8629 vector/scalar select bits. Note that the
8630 scalar immediate case is handled above. */
8633 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8634 int max_el
= (is_qh
? 3 : 7);
8636 my_getExpression(&imm_expr
, s
);
8637 check_absolute_expr (ip
, &imm_expr
);
8639 if (imm_expr
.X_add_number
> max_el
)
8640 as_bad(_("Bad element selector %ld"),
8641 (long) imm_expr
.X_add_number
);
8642 imm_expr
.X_add_number
&= max_el
;
8643 ip
->insn_opcode
|= (imm_expr
.X_add_number
8646 imm_expr
.X_op
= O_absent
;
8648 as_warn(_("Expecting ']' found '%s'"), s
);
8654 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8655 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8658 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8665 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8668 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8678 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8681 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8687 my_getExpression (&imm_expr
, s
);
8688 if (imm_expr
.X_op
!= O_big
8689 && imm_expr
.X_op
!= O_constant
)
8690 insn_error
= _("absolute expression required");
8691 normalize_constant_expr (&imm_expr
);
8696 my_getExpression (&offset_expr
, s
);
8697 *imm_reloc
= BFD_RELOC_32
;
8710 unsigned char temp
[8];
8712 unsigned int length
;
8717 /* These only appear as the last operand in an
8718 instruction, and every instruction that accepts
8719 them in any variant accepts them in all variants.
8720 This means we don't have to worry about backing out
8721 any changes if the instruction does not match.
8723 The difference between them is the size of the
8724 floating point constant and where it goes. For 'F'
8725 and 'L' the constant is 64 bits; for 'f' and 'l' it
8726 is 32 bits. Where the constant is placed is based
8727 on how the MIPS assembler does things:
8730 f -- immediate value
8733 The .lit4 and .lit8 sections are only used if
8734 permitted by the -G argument.
8736 The code below needs to know whether the target register
8737 is 32 or 64 bits wide. It relies on the fact 'f' and
8738 'F' are used with GPR-based instructions and 'l' and
8739 'L' are used with FPR-based instructions. */
8741 f64
= *args
== 'F' || *args
== 'L';
8742 using_gprs
= *args
== 'F' || *args
== 'f';
8744 save_in
= input_line_pointer
;
8745 input_line_pointer
= s
;
8746 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8748 s
= input_line_pointer
;
8749 input_line_pointer
= save_in
;
8750 if (err
!= NULL
&& *err
!= '\0')
8752 as_bad (_("Bad floating point constant: %s"), err
);
8753 memset (temp
, '\0', sizeof temp
);
8754 length
= f64
? 8 : 4;
8757 assert (length
== (unsigned) (f64
? 8 : 4));
8761 && (g_switch_value
< 4
8762 || (temp
[0] == 0 && temp
[1] == 0)
8763 || (temp
[2] == 0 && temp
[3] == 0))))
8765 imm_expr
.X_op
= O_constant
;
8766 if (! target_big_endian
)
8767 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8769 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8772 && ! mips_disable_float_construction
8773 /* Constants can only be constructed in GPRs and
8774 copied to FPRs if the GPRs are at least as wide
8775 as the FPRs. Force the constant into memory if
8776 we are using 64-bit FPRs but the GPRs are only
8779 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8780 && ((temp
[0] == 0 && temp
[1] == 0)
8781 || (temp
[2] == 0 && temp
[3] == 0))
8782 && ((temp
[4] == 0 && temp
[5] == 0)
8783 || (temp
[6] == 0 && temp
[7] == 0)))
8785 /* The value is simple enough to load with a couple of
8786 instructions. If using 32-bit registers, set
8787 imm_expr to the high order 32 bits and offset_expr to
8788 the low order 32 bits. Otherwise, set imm_expr to
8789 the entire 64 bit constant. */
8790 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8792 imm_expr
.X_op
= O_constant
;
8793 offset_expr
.X_op
= O_constant
;
8794 if (! target_big_endian
)
8796 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8797 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8801 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8802 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8804 if (offset_expr
.X_add_number
== 0)
8805 offset_expr
.X_op
= O_absent
;
8807 else if (sizeof (imm_expr
.X_add_number
) > 4)
8809 imm_expr
.X_op
= O_constant
;
8810 if (! target_big_endian
)
8811 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8813 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8817 imm_expr
.X_op
= O_big
;
8818 imm_expr
.X_add_number
= 4;
8819 if (! target_big_endian
)
8821 generic_bignum
[0] = bfd_getl16 (temp
);
8822 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8823 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8824 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8828 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8829 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8830 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8831 generic_bignum
[3] = bfd_getb16 (temp
);
8837 const char *newname
;
8840 /* Switch to the right section. */
8842 subseg
= now_subseg
;
8845 default: /* unused default case avoids warnings. */
8847 newname
= RDATA_SECTION_NAME
;
8848 if (g_switch_value
>= 8)
8852 newname
= RDATA_SECTION_NAME
;
8855 assert (g_switch_value
>= 4);
8859 new_seg
= subseg_new (newname
, (subsegT
) 0);
8860 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8861 bfd_set_section_flags (stdoutput
, new_seg
,
8866 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8867 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8868 && strcmp (TARGET_OS
, "elf") != 0)
8869 record_alignment (new_seg
, 4);
8871 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8873 as_bad (_("Can't use floating point insn in this section"));
8875 /* Set the argument to the current address in the
8877 offset_expr
.X_op
= O_symbol
;
8878 offset_expr
.X_add_symbol
=
8879 symbol_new ("L0\001", now_seg
,
8880 (valueT
) frag_now_fix (), frag_now
);
8881 offset_expr
.X_add_number
= 0;
8883 /* Put the floating point number into the section. */
8884 p
= frag_more ((int) length
);
8885 memcpy (p
, temp
, length
);
8887 /* Switch back to the original section. */
8888 subseg_set (seg
, subseg
);
8893 case 'i': /* 16 bit unsigned immediate */
8894 case 'j': /* 16 bit signed immediate */
8895 *imm_reloc
= BFD_RELOC_LO16
;
8896 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8899 offsetT minval
, maxval
;
8901 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8902 && strcmp (insn
->name
, insn
[1].name
) == 0);
8904 /* If the expression was written as an unsigned number,
8905 only treat it as signed if there are no more
8909 && sizeof (imm_expr
.X_add_number
) <= 4
8910 && imm_expr
.X_op
== O_constant
8911 && imm_expr
.X_add_number
< 0
8912 && imm_expr
.X_unsigned
8916 /* For compatibility with older assemblers, we accept
8917 0x8000-0xffff as signed 16-bit numbers when only
8918 signed numbers are allowed. */
8920 minval
= 0, maxval
= 0xffff;
8922 minval
= -0x8000, maxval
= 0x7fff;
8924 minval
= -0x8000, maxval
= 0xffff;
8926 if (imm_expr
.X_op
!= O_constant
8927 || imm_expr
.X_add_number
< minval
8928 || imm_expr
.X_add_number
> maxval
)
8932 if (imm_expr
.X_op
== O_constant
8933 || imm_expr
.X_op
== O_big
)
8934 as_bad (_("expression out of range"));
8940 case 'o': /* 16 bit offset */
8941 /* Check whether there is only a single bracketed expression
8942 left. If so, it must be the base register and the
8943 constant must be zero. */
8944 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8946 offset_expr
.X_op
= O_constant
;
8947 offset_expr
.X_add_number
= 0;
8951 /* If this value won't fit into a 16 bit offset, then go
8952 find a macro that will generate the 32 bit offset
8954 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8955 && (offset_expr
.X_op
!= O_constant
8956 || offset_expr
.X_add_number
>= 0x8000
8957 || offset_expr
.X_add_number
< -0x8000))
8963 case 'p': /* pc relative offset */
8964 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8965 my_getExpression (&offset_expr
, s
);
8969 case 'u': /* upper 16 bits */
8970 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8971 && imm_expr
.X_op
== O_constant
8972 && (imm_expr
.X_add_number
< 0
8973 || imm_expr
.X_add_number
>= 0x10000))
8974 as_bad (_("lui expression not in range 0..65535"));
8978 case 'a': /* 26 bit address */
8979 my_getExpression (&offset_expr
, s
);
8981 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8984 case 'N': /* 3 bit branch condition code */
8985 case 'M': /* 3 bit compare condition code */
8986 if (strncmp (s
, "$fcc", 4) != 0)
8996 while (ISDIGIT (*s
));
8998 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8999 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9000 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9001 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9002 && (regno
& 1) != 0)
9003 as_warn(_("Condition code register should be even for %s, was %d"),
9005 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9006 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9007 && (regno
& 3) != 0)
9008 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9011 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9013 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9017 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9028 while (ISDIGIT (*s
));
9031 c
= 8; /* Invalid sel value. */
9034 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9035 ip
->insn_opcode
|= c
;
9039 /* Must be at least one digit. */
9040 my_getExpression (&imm_expr
, s
);
9041 check_absolute_expr (ip
, &imm_expr
);
9043 if ((unsigned long) imm_expr
.X_add_number
9044 > (unsigned long) OP_MASK_VECBYTE
)
9046 as_bad (_("bad byte vector index (%ld)"),
9047 (long) imm_expr
.X_add_number
);
9048 imm_expr
.X_add_number
= 0;
9051 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9052 imm_expr
.X_op
= O_absent
;
9057 my_getExpression (&imm_expr
, s
);
9058 check_absolute_expr (ip
, &imm_expr
);
9060 if ((unsigned long) imm_expr
.X_add_number
9061 > (unsigned long) OP_MASK_VECALIGN
)
9063 as_bad (_("bad byte vector index (%ld)"),
9064 (long) imm_expr
.X_add_number
);
9065 imm_expr
.X_add_number
= 0;
9068 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9069 imm_expr
.X_op
= O_absent
;
9074 as_bad (_("bad char = '%c'\n"), *args
);
9079 /* Args don't match. */
9080 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9081 !strcmp (insn
->name
, insn
[1].name
))
9085 insn_error
= _("illegal operands");
9090 insn_error
= _("illegal operands");
9095 /* This routine assembles an instruction into its binary format when
9096 assembling for the mips16. As a side effect, it sets one of the
9097 global variables imm_reloc or offset_reloc to the type of
9098 relocation to do if one of the operands is an address expression.
9099 It also sets mips16_small and mips16_ext if the user explicitly
9100 requested a small or extended instruction. */
9103 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9107 struct mips_opcode
*insn
;
9110 unsigned int lastregno
= 0;
9116 mips16_small
= FALSE
;
9119 for (s
= str
; ISLOWER (*s
); ++s
)
9131 if (s
[1] == 't' && s
[2] == ' ')
9134 mips16_small
= TRUE
;
9138 else if (s
[1] == 'e' && s
[2] == ' ')
9147 insn_error
= _("unknown opcode");
9151 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9152 mips16_small
= TRUE
;
9154 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9156 insn_error
= _("unrecognized opcode");
9163 assert (strcmp (insn
->name
, str
) == 0);
9166 ip
->insn_opcode
= insn
->match
;
9167 ip
->use_extend
= FALSE
;
9168 imm_expr
.X_op
= O_absent
;
9169 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9170 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9171 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9172 imm2_expr
.X_op
= O_absent
;
9173 offset_expr
.X_op
= O_absent
;
9174 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9175 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9176 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9177 for (args
= insn
->args
; 1; ++args
)
9184 /* In this switch statement we call break if we did not find
9185 a match, continue if we did find a match, or return if we
9194 /* Stuff the immediate value in now, if we can. */
9195 if (imm_expr
.X_op
== O_constant
9196 && *imm_reloc
> BFD_RELOC_UNUSED
9197 && insn
->pinfo
!= INSN_MACRO
)
9201 switch (*offset_reloc
)
9203 case BFD_RELOC_MIPS16_HI16_S
:
9204 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9207 case BFD_RELOC_MIPS16_HI16
:
9208 tmp
= imm_expr
.X_add_number
>> 16;
9211 case BFD_RELOC_MIPS16_LO16
:
9212 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9216 case BFD_RELOC_UNUSED
:
9217 tmp
= imm_expr
.X_add_number
;
9223 *offset_reloc
= BFD_RELOC_UNUSED
;
9225 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9226 tmp
, TRUE
, mips16_small
,
9227 mips16_ext
, &ip
->insn_opcode
,
9228 &ip
->use_extend
, &ip
->extend
);
9229 imm_expr
.X_op
= O_absent
;
9230 *imm_reloc
= BFD_RELOC_UNUSED
;
9244 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9247 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9263 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9265 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9292 while (ISDIGIT (*s
));
9295 as_bad (_("invalid register number (%d)"), regno
);
9301 if (s
[1] == 'r' && s
[2] == 'a')
9306 else if (s
[1] == 'f' && s
[2] == 'p')
9311 else if (s
[1] == 's' && s
[2] == 'p')
9316 else if (s
[1] == 'g' && s
[2] == 'p')
9321 else if (s
[1] == 'a' && s
[2] == 't')
9326 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9331 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9336 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9349 if (c
== 'v' || c
== 'w')
9351 regno
= mips16_to_32_reg_map
[lastregno
];
9365 regno
= mips32_to_16_reg_map
[regno
];
9370 regno
= ILLEGAL_REG
;
9375 regno
= ILLEGAL_REG
;
9380 regno
= ILLEGAL_REG
;
9385 if (regno
== AT
&& ! mips_opts
.noat
)
9386 as_warn (_("used $at without \".set noat\""));
9393 if (regno
== ILLEGAL_REG
)
9400 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9404 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9407 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9410 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9416 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9419 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9420 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9430 if (strncmp (s
, "$pc", 3) == 0)
9447 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9450 if (imm_expr
.X_op
!= O_constant
)
9453 ip
->use_extend
= TRUE
;
9458 /* We need to relax this instruction. */
9459 *offset_reloc
= *imm_reloc
;
9460 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9465 *imm_reloc
= BFD_RELOC_UNUSED
;
9473 my_getExpression (&imm_expr
, s
);
9474 if (imm_expr
.X_op
== O_register
)
9476 /* What we thought was an expression turned out to
9479 if (s
[0] == '(' && args
[1] == '(')
9481 /* It looks like the expression was omitted
9482 before a register indirection, which means
9483 that the expression is implicitly zero. We
9484 still set up imm_expr, so that we handle
9485 explicit extensions correctly. */
9486 imm_expr
.X_op
= O_constant
;
9487 imm_expr
.X_add_number
= 0;
9488 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9495 /* We need to relax this instruction. */
9496 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9505 /* We use offset_reloc rather than imm_reloc for the PC
9506 relative operands. This lets macros with both
9507 immediate and address operands work correctly. */
9508 my_getExpression (&offset_expr
, s
);
9510 if (offset_expr
.X_op
== O_register
)
9513 /* We need to relax this instruction. */
9514 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9518 case '6': /* break code */
9519 my_getExpression (&imm_expr
, s
);
9520 check_absolute_expr (ip
, &imm_expr
);
9521 if ((unsigned long) imm_expr
.X_add_number
> 63)
9523 as_warn (_("Invalid value for `%s' (%lu)"),
9525 (unsigned long) imm_expr
.X_add_number
);
9526 imm_expr
.X_add_number
&= 0x3f;
9528 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9529 imm_expr
.X_op
= O_absent
;
9533 case 'a': /* 26 bit address */
9534 my_getExpression (&offset_expr
, s
);
9536 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9537 ip
->insn_opcode
<<= 16;
9540 case 'l': /* register list for entry macro */
9541 case 'L': /* register list for exit macro */
9551 int freg
, reg1
, reg2
;
9553 while (*s
== ' ' || *s
== ',')
9557 as_bad (_("can't parse register list"));
9569 while (ISDIGIT (*s
))
9591 as_bad (_("invalid register list"));
9596 while (ISDIGIT (*s
))
9603 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9608 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9613 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9614 mask
|= (reg2
- 3) << 3;
9615 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9616 mask
|= (reg2
- 15) << 1;
9617 else if (reg1
== RA
&& reg2
== RA
)
9621 as_bad (_("invalid register list"));
9625 /* The mask is filled in in the opcode table for the
9626 benefit of the disassembler. We remove it before
9627 applying the actual mask. */
9628 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9629 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9633 case 'e': /* extend code */
9634 my_getExpression (&imm_expr
, s
);
9635 check_absolute_expr (ip
, &imm_expr
);
9636 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9638 as_warn (_("Invalid value for `%s' (%lu)"),
9640 (unsigned long) imm_expr
.X_add_number
);
9641 imm_expr
.X_add_number
&= 0x7ff;
9643 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9644 imm_expr
.X_op
= O_absent
;
9654 /* Args don't match. */
9655 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9656 strcmp (insn
->name
, insn
[1].name
) == 0)
9663 insn_error
= _("illegal operands");
9669 /* This structure holds information we know about a mips16 immediate
9672 struct mips16_immed_operand
9674 /* The type code used in the argument string in the opcode table. */
9676 /* The number of bits in the short form of the opcode. */
9678 /* The number of bits in the extended form of the opcode. */
9680 /* The amount by which the short form is shifted when it is used;
9681 for example, the sw instruction has a shift count of 2. */
9683 /* The amount by which the short form is shifted when it is stored
9684 into the instruction code. */
9686 /* Non-zero if the short form is unsigned. */
9688 /* Non-zero if the extended form is unsigned. */
9690 /* Non-zero if the value is PC relative. */
9694 /* The mips16 immediate operand types. */
9696 static const struct mips16_immed_operand mips16_immed_operands
[] =
9698 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9699 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9700 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9701 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9702 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9703 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9704 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9705 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9706 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9707 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9708 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9709 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9710 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9711 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9712 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9713 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9714 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9715 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9716 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9717 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9718 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9721 #define MIPS16_NUM_IMMED \
9722 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9724 /* Handle a mips16 instruction with an immediate value. This or's the
9725 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9726 whether an extended value is needed; if one is needed, it sets
9727 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9728 If SMALL is true, an unextended opcode was explicitly requested.
9729 If EXT is true, an extended opcode was explicitly requested. If
9730 WARN is true, warn if EXT does not match reality. */
9733 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9734 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9735 unsigned long *insn
, bfd_boolean
*use_extend
,
9736 unsigned short *extend
)
9738 register const struct mips16_immed_operand
*op
;
9739 int mintiny
, maxtiny
;
9740 bfd_boolean needext
;
9742 op
= mips16_immed_operands
;
9743 while (op
->type
!= type
)
9746 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9751 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9754 maxtiny
= 1 << op
->nbits
;
9759 maxtiny
= (1 << op
->nbits
) - 1;
9764 mintiny
= - (1 << (op
->nbits
- 1));
9765 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9768 /* Branch offsets have an implicit 0 in the lowest bit. */
9769 if (type
== 'p' || type
== 'q')
9772 if ((val
& ((1 << op
->shift
) - 1)) != 0
9773 || val
< (mintiny
<< op
->shift
)
9774 || val
> (maxtiny
<< op
->shift
))
9779 if (warn
&& ext
&& ! needext
)
9780 as_warn_where (file
, line
,
9781 _("extended operand requested but not required"));
9782 if (small
&& needext
)
9783 as_bad_where (file
, line
, _("invalid unextended operand value"));
9785 if (small
|| (! ext
&& ! needext
))
9789 *use_extend
= FALSE
;
9790 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9791 insnval
<<= op
->op_shift
;
9796 long minext
, maxext
;
9802 maxext
= (1 << op
->extbits
) - 1;
9806 minext
= - (1 << (op
->extbits
- 1));
9807 maxext
= (1 << (op
->extbits
- 1)) - 1;
9809 if (val
< minext
|| val
> maxext
)
9810 as_bad_where (file
, line
,
9811 _("operand value out of range for instruction"));
9814 if (op
->extbits
== 16)
9816 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9819 else if (op
->extbits
== 15)
9821 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9826 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9830 *extend
= (unsigned short) extval
;
9835 struct percent_op_match
9838 bfd_reloc_code_real_type reloc
;
9841 static const struct percent_op_match mips_percent_op
[] =
9843 {"%lo", BFD_RELOC_LO16
},
9845 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9846 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9847 {"%call16", BFD_RELOC_MIPS_CALL16
},
9848 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9849 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9850 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9851 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9852 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9853 {"%got", BFD_RELOC_MIPS_GOT16
},
9854 {"%gp_rel", BFD_RELOC_GPREL16
},
9855 {"%half", BFD_RELOC_16
},
9856 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9857 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9858 {"%neg", BFD_RELOC_MIPS_SUB
},
9860 {"%hi", BFD_RELOC_HI16_S
}
9863 static const struct percent_op_match mips16_percent_op
[] =
9865 {"%lo", BFD_RELOC_MIPS16_LO16
},
9866 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9867 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9871 /* Return true if *STR points to a relocation operator. When returning true,
9872 move *STR over the operator and store its relocation code in *RELOC.
9873 Leave both *STR and *RELOC alone when returning false. */
9876 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9878 const struct percent_op_match
*percent_op
;
9881 if (mips_opts
.mips16
)
9883 percent_op
= mips16_percent_op
;
9884 limit
= ARRAY_SIZE (mips16_percent_op
);
9888 percent_op
= mips_percent_op
;
9889 limit
= ARRAY_SIZE (mips_percent_op
);
9892 for (i
= 0; i
< limit
; i
++)
9893 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9895 *str
+= strlen (percent_op
[i
].str
);
9896 *reloc
= percent_op
[i
].reloc
;
9898 /* Check whether the output BFD supports this relocation.
9899 If not, issue an error and fall back on something safe. */
9900 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9902 as_bad ("relocation %s isn't supported by the current ABI",
9904 *reloc
= BFD_RELOC_UNUSED
;
9912 /* Parse string STR as a 16-bit relocatable operand. Store the
9913 expression in *EP and the relocations in the array starting
9914 at RELOC. Return the number of relocation operators used.
9916 On exit, EXPR_END points to the first character after the expression. */
9919 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9922 bfd_reloc_code_real_type reversed_reloc
[3];
9923 size_t reloc_index
, i
;
9924 int crux_depth
, str_depth
;
9927 /* Search for the start of the main expression, recoding relocations
9928 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9929 of the main expression and with CRUX_DEPTH containing the number
9930 of open brackets at that point. */
9937 crux_depth
= str_depth
;
9939 /* Skip over whitespace and brackets, keeping count of the number
9941 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9946 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9947 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9949 my_getExpression (ep
, crux
);
9952 /* Match every open bracket. */
9953 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9958 as_bad ("unclosed '('");
9962 if (reloc_index
!= 0)
9964 prev_reloc_op_frag
= frag_now
;
9965 for (i
= 0; i
< reloc_index
; i
++)
9966 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9973 my_getExpression (expressionS
*ep
, char *str
)
9978 save_in
= input_line_pointer
;
9979 input_line_pointer
= str
;
9981 expr_end
= input_line_pointer
;
9982 input_line_pointer
= save_in
;
9984 /* If we are in mips16 mode, and this is an expression based on `.',
9985 then we bump the value of the symbol by 1 since that is how other
9986 text symbols are handled. We don't bother to handle complex
9987 expressions, just `.' plus or minus a constant. */
9988 if (mips_opts
.mips16
9989 && ep
->X_op
== O_symbol
9990 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9991 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9992 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9993 && symbol_constant_p (ep
->X_add_symbol
)
9994 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9995 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9998 /* Turn a string in input_line_pointer into a floating point constant
9999 of type TYPE, and store the appropriate bytes in *LITP. The number
10000 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10001 returned, or NULL on OK. */
10004 md_atof (int type
, char *litP
, int *sizeP
)
10007 LITTLENUM_TYPE words
[4];
10023 return _("bad call to md_atof");
10026 t
= atof_ieee (input_line_pointer
, type
, words
);
10028 input_line_pointer
= t
;
10032 if (! target_big_endian
)
10034 for (i
= prec
- 1; i
>= 0; i
--)
10036 md_number_to_chars (litP
, words
[i
], 2);
10042 for (i
= 0; i
< prec
; i
++)
10044 md_number_to_chars (litP
, words
[i
], 2);
10053 md_number_to_chars (char *buf
, valueT val
, int n
)
10055 if (target_big_endian
)
10056 number_to_chars_bigendian (buf
, val
, n
);
10058 number_to_chars_littleendian (buf
, val
, n
);
10062 static int support_64bit_objects(void)
10064 const char **list
, **l
;
10067 list
= bfd_target_list ();
10068 for (l
= list
; *l
!= NULL
; l
++)
10070 /* This is traditional mips */
10071 if (strcmp (*l
, "elf64-tradbigmips") == 0
10072 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10074 if (strcmp (*l
, "elf64-bigmips") == 0
10075 || strcmp (*l
, "elf64-littlemips") == 0)
10078 yes
= (*l
!= NULL
);
10082 #endif /* OBJ_ELF */
10084 const char *md_shortopts
= "O::g::G:";
10086 struct option md_longopts
[] =
10088 /* Options which specify architecture. */
10089 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10090 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10091 {"march", required_argument
, NULL
, OPTION_MARCH
},
10092 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10093 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10094 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10095 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10096 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10097 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10098 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10099 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10100 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10101 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10102 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10103 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10104 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10105 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10106 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10107 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10108 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10109 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10110 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10111 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10112 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10114 /* Options which specify Application Specific Extensions (ASEs). */
10115 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10116 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10117 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10118 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10119 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10120 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10121 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10122 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10123 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10124 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10125 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10126 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10127 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10129 /* Old-style architecture options. Don't add more of these. */
10130 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10131 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10132 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10133 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10134 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10135 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10136 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10137 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10138 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10139 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10140 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10141 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10142 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10143 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10144 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10145 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10146 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10148 /* Options which enable bug fixes. */
10149 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10150 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10151 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10152 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10153 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10154 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10155 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10156 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10157 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10158 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10160 /* Miscellaneous options. */
10161 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10162 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10163 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10164 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10165 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10166 {"break", no_argument
, NULL
, OPTION_BREAK
},
10167 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10168 #define OPTION_EB (OPTION_MISC_BASE + 2)
10169 {"EB", no_argument
, NULL
, OPTION_EB
},
10170 #define OPTION_EL (OPTION_MISC_BASE + 3)
10171 {"EL", no_argument
, NULL
, OPTION_EL
},
10172 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10173 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10174 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10175 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10176 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10177 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10178 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10179 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10180 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10181 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10182 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10183 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10184 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10185 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10186 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10187 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10188 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10189 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10190 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10191 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10193 /* ELF-specific options. */
10195 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14)
10196 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10197 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10198 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10199 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10200 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10201 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10202 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10203 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10204 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10205 #define OPTION_32 (OPTION_ELF_BASE + 4)
10206 {"32", no_argument
, NULL
, OPTION_32
},
10207 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10208 {"n32", no_argument
, NULL
, OPTION_N32
},
10209 #define OPTION_64 (OPTION_ELF_BASE + 6)
10210 {"64", no_argument
, NULL
, OPTION_64
},
10211 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10212 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10213 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10214 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10215 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10216 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10217 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10218 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10219 #endif /* OBJ_ELF */
10221 {NULL
, no_argument
, NULL
, 0}
10223 size_t md_longopts_size
= sizeof (md_longopts
);
10225 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10226 NEW_VALUE. Warn if another value was already specified. Note:
10227 we have to defer parsing the -march and -mtune arguments in order
10228 to handle 'from-abi' correctly, since the ABI might be specified
10229 in a later argument. */
10232 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10234 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10235 as_warn (_("A different %s was already specified, is now %s"),
10236 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10239 *string_ptr
= new_value
;
10243 md_parse_option (int c
, char *arg
)
10247 case OPTION_CONSTRUCT_FLOATS
:
10248 mips_disable_float_construction
= 0;
10251 case OPTION_NO_CONSTRUCT_FLOATS
:
10252 mips_disable_float_construction
= 1;
10264 target_big_endian
= 1;
10268 target_big_endian
= 0;
10272 if (arg
&& arg
[1] == '0')
10282 mips_debug
= atoi (arg
);
10283 /* When the MIPS assembler sees -g or -g2, it does not do
10284 optimizations which limit full symbolic debugging. We take
10285 that to be equivalent to -O0. */
10286 if (mips_debug
== 2)
10291 file_mips_isa
= ISA_MIPS1
;
10295 file_mips_isa
= ISA_MIPS2
;
10299 file_mips_isa
= ISA_MIPS3
;
10303 file_mips_isa
= ISA_MIPS4
;
10307 file_mips_isa
= ISA_MIPS5
;
10310 case OPTION_MIPS32
:
10311 file_mips_isa
= ISA_MIPS32
;
10314 case OPTION_MIPS32R2
:
10315 file_mips_isa
= ISA_MIPS32R2
;
10318 case OPTION_MIPS64R2
:
10319 file_mips_isa
= ISA_MIPS64R2
;
10322 case OPTION_MIPS64
:
10323 file_mips_isa
= ISA_MIPS64
;
10327 mips_set_option_string (&mips_tune_string
, arg
);
10331 mips_set_option_string (&mips_arch_string
, arg
);
10335 mips_set_option_string (&mips_arch_string
, "4650");
10336 mips_set_option_string (&mips_tune_string
, "4650");
10339 case OPTION_NO_M4650
:
10343 mips_set_option_string (&mips_arch_string
, "4010");
10344 mips_set_option_string (&mips_tune_string
, "4010");
10347 case OPTION_NO_M4010
:
10351 mips_set_option_string (&mips_arch_string
, "4100");
10352 mips_set_option_string (&mips_tune_string
, "4100");
10355 case OPTION_NO_M4100
:
10359 mips_set_option_string (&mips_arch_string
, "3900");
10360 mips_set_option_string (&mips_tune_string
, "3900");
10363 case OPTION_NO_M3900
:
10367 mips_opts
.ase_mdmx
= 1;
10370 case OPTION_NO_MDMX
:
10371 mips_opts
.ase_mdmx
= 0;
10374 case OPTION_MIPS16
:
10375 mips_opts
.mips16
= 1;
10376 mips_no_prev_insn (FALSE
);
10379 case OPTION_NO_MIPS16
:
10380 mips_opts
.mips16
= 0;
10381 mips_no_prev_insn (FALSE
);
10384 case OPTION_MIPS3D
:
10385 mips_opts
.ase_mips3d
= 1;
10388 case OPTION_NO_MIPS3D
:
10389 mips_opts
.ase_mips3d
= 0;
10392 case OPTION_FIX_VR4120
:
10393 mips_fix_vr4120
= 1;
10396 case OPTION_NO_FIX_VR4120
:
10397 mips_fix_vr4120
= 0;
10400 case OPTION_RELAX_BRANCH
:
10401 mips_relax_branch
= 1;
10404 case OPTION_NO_RELAX_BRANCH
:
10405 mips_relax_branch
= 0;
10408 case OPTION_MSHARED
:
10409 mips_in_shared
= TRUE
;
10412 case OPTION_MNO_SHARED
:
10413 mips_in_shared
= FALSE
;
10417 /* When generating ELF code, we permit -KPIC and -call_shared to
10418 select SVR4_PIC, and -non_shared to select no PIC. This is
10419 intended to be compatible with Irix 5. */
10420 case OPTION_CALL_SHARED
:
10421 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10423 as_bad (_("-call_shared is supported only for ELF format"));
10426 mips_pic
= SVR4_PIC
;
10427 mips_abicalls
= TRUE
;
10428 if (g_switch_seen
&& g_switch_value
!= 0)
10430 as_bad (_("-G may not be used with SVR4 PIC code"));
10433 g_switch_value
= 0;
10436 case OPTION_NON_SHARED
:
10437 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10439 as_bad (_("-non_shared is supported only for ELF format"));
10443 mips_abicalls
= FALSE
;
10446 /* The -xgot option tells the assembler to use 32 offsets when
10447 accessing the got in SVR4_PIC mode. It is for Irix
10452 #endif /* OBJ_ELF */
10455 if (mips_pic
== SVR4_PIC
)
10457 as_bad (_("-G may not be used with SVR4 PIC code"));
10461 g_switch_value
= atoi (arg
);
10466 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10469 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10471 as_bad (_("-32 is supported for ELF format only"));
10474 mips_abi
= O32_ABI
;
10478 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10480 as_bad (_("-n32 is supported for ELF format only"));
10483 mips_abi
= N32_ABI
;
10487 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10489 as_bad (_("-64 is supported for ELF format only"));
10492 mips_abi
= N64_ABI
;
10493 if (! support_64bit_objects())
10494 as_fatal (_("No compiled in support for 64 bit object file format"));
10496 #endif /* OBJ_ELF */
10499 file_mips_gp32
= 1;
10503 file_mips_gp32
= 0;
10507 file_mips_fp32
= 1;
10511 file_mips_fp32
= 0;
10516 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10518 as_bad (_("-mabi is supported for ELF format only"));
10521 if (strcmp (arg
, "32") == 0)
10522 mips_abi
= O32_ABI
;
10523 else if (strcmp (arg
, "o64") == 0)
10524 mips_abi
= O64_ABI
;
10525 else if (strcmp (arg
, "n32") == 0)
10526 mips_abi
= N32_ABI
;
10527 else if (strcmp (arg
, "64") == 0)
10529 mips_abi
= N64_ABI
;
10530 if (! support_64bit_objects())
10531 as_fatal (_("No compiled in support for 64 bit object file "
10534 else if (strcmp (arg
, "eabi") == 0)
10535 mips_abi
= EABI_ABI
;
10538 as_fatal (_("invalid abi -mabi=%s"), arg
);
10542 #endif /* OBJ_ELF */
10544 case OPTION_M7000_HILO_FIX
:
10545 mips_7000_hilo_fix
= TRUE
;
10548 case OPTION_MNO_7000_HILO_FIX
:
10549 mips_7000_hilo_fix
= FALSE
;
10553 case OPTION_MDEBUG
:
10554 mips_flag_mdebug
= TRUE
;
10557 case OPTION_NO_MDEBUG
:
10558 mips_flag_mdebug
= FALSE
;
10562 mips_flag_pdr
= TRUE
;
10565 case OPTION_NO_PDR
:
10566 mips_flag_pdr
= FALSE
;
10568 #endif /* OBJ_ELF */
10577 /* Set up globals to generate code for the ISA or processor
10578 described by INFO. */
10581 mips_set_architecture (const struct mips_cpu_info
*info
)
10585 file_mips_arch
= info
->cpu
;
10586 mips_opts
.arch
= info
->cpu
;
10587 mips_opts
.isa
= info
->isa
;
10592 /* Likewise for tuning. */
10595 mips_set_tune (const struct mips_cpu_info
*info
)
10598 mips_tune
= info
->cpu
;
10603 mips_after_parse_args (void)
10605 const struct mips_cpu_info
*arch_info
= 0;
10606 const struct mips_cpu_info
*tune_info
= 0;
10608 /* GP relative stuff not working for PE */
10609 if (strncmp (TARGET_OS
, "pe", 2) == 0
10610 && g_switch_value
!= 0)
10613 as_bad (_("-G not supported in this configuration."));
10614 g_switch_value
= 0;
10617 if (mips_abi
== NO_ABI
)
10618 mips_abi
= MIPS_DEFAULT_ABI
;
10620 /* The following code determines the architecture and register size.
10621 Similar code was added to GCC 3.3 (see override_options() in
10622 config/mips/mips.c). The GAS and GCC code should be kept in sync
10623 as much as possible. */
10625 if (mips_arch_string
!= 0)
10626 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10628 if (file_mips_isa
!= ISA_UNKNOWN
)
10630 /* Handle -mipsN. At this point, file_mips_isa contains the
10631 ISA level specified by -mipsN, while arch_info->isa contains
10632 the -march selection (if any). */
10633 if (arch_info
!= 0)
10635 /* -march takes precedence over -mipsN, since it is more descriptive.
10636 There's no harm in specifying both as long as the ISA levels
10638 if (file_mips_isa
!= arch_info
->isa
)
10639 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10640 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10641 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10644 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10647 if (arch_info
== 0)
10648 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10650 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10651 as_bad ("-march=%s is not compatible with the selected ABI",
10654 mips_set_architecture (arch_info
);
10656 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10657 if (mips_tune_string
!= 0)
10658 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10660 if (tune_info
== 0)
10661 mips_set_tune (arch_info
);
10663 mips_set_tune (tune_info
);
10665 if (file_mips_gp32
>= 0)
10667 /* The user specified the size of the integer registers. Make sure
10668 it agrees with the ABI and ISA. */
10669 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10670 as_bad (_("-mgp64 used with a 32-bit processor"));
10671 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10672 as_bad (_("-mgp32 used with a 64-bit ABI"));
10673 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10674 as_bad (_("-mgp64 used with a 32-bit ABI"));
10678 /* Infer the integer register size from the ABI and processor.
10679 Restrict ourselves to 32-bit registers if that's all the
10680 processor has, or if the ABI cannot handle 64-bit registers. */
10681 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10682 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10685 /* ??? GAS treats single-float processors as though they had 64-bit
10686 float registers (although it complains when double-precision
10687 instructions are used). As things stand, saying they have 32-bit
10688 registers would lead to spurious "register must be even" messages.
10689 So here we assume float registers are always the same size as
10690 integer ones, unless the user says otherwise. */
10691 if (file_mips_fp32
< 0)
10692 file_mips_fp32
= file_mips_gp32
;
10694 /* End of GCC-shared inference code. */
10696 /* This flag is set when we have a 64-bit capable CPU but use only
10697 32-bit wide registers. Note that EABI does not use it. */
10698 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10699 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10700 || mips_abi
== O32_ABI
))
10701 mips_32bitmode
= 1;
10703 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10704 as_bad (_("trap exception not supported at ISA 1"));
10706 /* If the selected architecture includes support for ASEs, enable
10707 generation of code for them. */
10708 if (mips_opts
.mips16
== -1)
10709 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10710 if (mips_opts
.ase_mips3d
== -1)
10711 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10712 if (mips_opts
.ase_mdmx
== -1)
10713 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10715 file_mips_isa
= mips_opts
.isa
;
10716 file_ase_mips16
= mips_opts
.mips16
;
10717 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10718 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10719 mips_opts
.gp32
= file_mips_gp32
;
10720 mips_opts
.fp32
= file_mips_fp32
;
10722 if (mips_flag_mdebug
< 0)
10724 #ifdef OBJ_MAYBE_ECOFF
10725 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10726 mips_flag_mdebug
= 1;
10728 #endif /* OBJ_MAYBE_ECOFF */
10729 mips_flag_mdebug
= 0;
10734 mips_init_after_args (void)
10736 /* initialize opcodes */
10737 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10738 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10742 md_pcrel_from (fixS
*fixP
)
10744 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10745 switch (fixP
->fx_r_type
)
10747 case BFD_RELOC_16_PCREL_S2
:
10748 case BFD_RELOC_MIPS_JMP
:
10749 /* Return the address of the delay slot. */
10756 /* This is called before the symbol table is processed. In order to
10757 work with gcc when using mips-tfile, we must keep all local labels.
10758 However, in other cases, we want to discard them. If we were
10759 called with -g, but we didn't see any debugging information, it may
10760 mean that gcc is smuggling debugging information through to
10761 mips-tfile, in which case we must generate all local labels. */
10764 mips_frob_file_before_adjust (void)
10766 #ifndef NO_ECOFF_DEBUGGING
10767 if (ECOFF_DEBUGGING
10769 && ! ecoff_debugging_seen
)
10770 flag_keep_locals
= 1;
10774 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10775 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10776 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10777 relocation operators.
10779 For our purposes, a %lo() expression matches a %got() or %hi()
10782 (a) it refers to the same symbol; and
10783 (b) the offset applied in the %lo() expression is no lower than
10784 the offset applied in the %got() or %hi().
10786 (b) allows us to cope with code like:
10789 lh $4,%lo(foo+2)($4)
10791 ...which is legal on RELA targets, and has a well-defined behaviour
10792 if the user knows that adding 2 to "foo" will not induce a carry to
10795 When several %lo()s match a particular %got() or %hi(), we use the
10796 following rules to distinguish them:
10798 (1) %lo()s with smaller offsets are a better match than %lo()s with
10801 (2) %lo()s with no matching %got() or %hi() are better than those
10802 that already have a matching %got() or %hi().
10804 (3) later %lo()s are better than earlier %lo()s.
10806 These rules are applied in order.
10808 (1) means, among other things, that %lo()s with identical offsets are
10809 chosen if they exist.
10811 (2) means that we won't associate several high-part relocations with
10812 the same low-part relocation unless there's no alternative. Having
10813 several high parts for the same low part is a GNU extension; this rule
10814 allows careful users to avoid it.
10816 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10817 with the last high-part relocation being at the front of the list.
10818 It therefore makes sense to choose the last matching low-part
10819 relocation, all other things being equal. It's also easier
10820 to code that way. */
10823 mips_frob_file (void)
10825 struct mips_hi_fixup
*l
;
10827 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10829 segment_info_type
*seginfo
;
10830 bfd_boolean matched_lo_p
;
10831 fixS
**hi_pos
, **lo_pos
, **pos
;
10833 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10835 /* If a GOT16 relocation turns out to be against a global symbol,
10836 there isn't supposed to be a matching LO. */
10837 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10838 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10841 /* Check quickly whether the next fixup happens to be a matching %lo. */
10842 if (fixup_has_matching_lo_p (l
->fixp
))
10845 seginfo
= seg_info (l
->seg
);
10847 /* Set HI_POS to the position of this relocation in the chain.
10848 Set LO_POS to the position of the chosen low-part relocation.
10849 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10850 relocation that matches an immediately-preceding high-part
10854 matched_lo_p
= FALSE
;
10855 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10857 if (*pos
== l
->fixp
)
10860 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10861 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10862 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10864 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10866 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10869 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10870 && fixup_has_matching_lo_p (*pos
));
10873 /* If we found a match, remove the high-part relocation from its
10874 current position and insert it before the low-part relocation.
10875 Make the offsets match so that fixup_has_matching_lo_p()
10878 We don't warn about unmatched high-part relocations since some
10879 versions of gcc have been known to emit dead "lui ...%hi(...)"
10881 if (lo_pos
!= NULL
)
10883 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10884 if (l
->fixp
->fx_next
!= *lo_pos
)
10886 *hi_pos
= l
->fixp
->fx_next
;
10887 l
->fixp
->fx_next
= *lo_pos
;
10894 /* We may have combined relocations without symbols in the N32/N64 ABI.
10895 We have to prevent gas from dropping them. */
10898 mips_force_relocation (fixS
*fixp
)
10900 if (generic_force_reloc (fixp
))
10904 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10905 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10906 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10907 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10913 /* This hook is called before a fix is simplified. We don't really
10914 decide whether to skip a fix here. Rather, we turn global symbols
10915 used as branch targets into local symbols, such that they undergo
10916 simplification. We can only do this if the symbol is defined and
10917 it is in the same section as the branch. If this doesn't hold, we
10918 emit a better error message than just saying the relocation is not
10919 valid for the selected object format.
10921 FIXP is the fix-up we're going to try to simplify, SEG is the
10922 segment in which the fix up occurs. The return value should be
10923 non-zero to indicate the fix-up is valid for further
10924 simplifications. */
10927 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10929 /* There's a lot of discussion on whether it should be possible to
10930 use R_MIPS_PC16 to represent branch relocations. The outcome
10931 seems to be that it can, but gas/bfd are very broken in creating
10932 RELA relocations for this, so for now we only accept branches to
10933 symbols in the same section. Anything else is of dubious value,
10934 since there's no guarantee that at link time the symbol would be
10935 in range. Even for branches to local symbols this is arguably
10936 wrong, since it we assume the symbol is not going to be
10937 overridden, which should be possible per ELF library semantics,
10938 but then, there isn't a dynamic relocation that could be used to
10939 this effect, and the target would likely be out of range as well.
10941 Unfortunately, it seems that there is too much code out there
10942 that relies on branches to symbols that are global to be resolved
10943 as if they were local, like the IRIX tools do, so we do it as
10944 well, but with a warning so that people are reminded to fix their
10945 code. If we ever get back to using R_MIPS_PC16 for branch
10946 targets, this entire block should go away (and probably the
10947 whole function). */
10949 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10950 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10951 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10952 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10955 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10958 _("Cannot branch to undefined symbol."));
10959 /* Avoid any further errors about this fixup. */
10962 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10965 _("Cannot branch to symbol in another section."));
10968 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10970 symbolS
*sym
= fixP
->fx_addsy
;
10972 if (mips_pic
== SVR4_PIC
)
10973 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10974 _("Pretending global symbol used as branch target is local."));
10976 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10977 S_GET_SEGMENT (sym
),
10979 symbol_get_frag (sym
));
10980 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10981 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10982 assert (symbol_resolved_p (sym
));
10983 symbol_mark_resolved (fixP
->fx_addsy
);
10990 /* Apply a fixup to the object file. */
10993 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10997 reloc_howto_type
*howto
;
10999 /* We ignore generic BFD relocations we don't know about. */
11000 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11004 assert (fixP
->fx_size
== 4
11005 || fixP
->fx_r_type
== BFD_RELOC_16
11006 || fixP
->fx_r_type
== BFD_RELOC_64
11007 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11008 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11009 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11010 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11012 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11014 assert (! fixP
->fx_pcrel
);
11016 /* Don't treat parts of a composite relocation as done. There are two
11019 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11020 should nevertheless be emitted if the first part is.
11022 (2) In normal usage, composite relocations are never assembly-time
11023 constants. The easiest way of dealing with the pathological
11024 exceptions is to generate a relocation against STN_UNDEF and
11025 leave everything up to the linker. */
11026 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11029 switch (fixP
->fx_r_type
)
11031 case BFD_RELOC_MIPS_JMP
:
11032 case BFD_RELOC_MIPS_SHIFT5
:
11033 case BFD_RELOC_MIPS_SHIFT6
:
11034 case BFD_RELOC_MIPS_GOT_DISP
:
11035 case BFD_RELOC_MIPS_GOT_PAGE
:
11036 case BFD_RELOC_MIPS_GOT_OFST
:
11037 case BFD_RELOC_MIPS_SUB
:
11038 case BFD_RELOC_MIPS_INSERT_A
:
11039 case BFD_RELOC_MIPS_INSERT_B
:
11040 case BFD_RELOC_MIPS_DELETE
:
11041 case BFD_RELOC_MIPS_HIGHEST
:
11042 case BFD_RELOC_MIPS_HIGHER
:
11043 case BFD_RELOC_MIPS_SCN_DISP
:
11044 case BFD_RELOC_MIPS_REL16
:
11045 case BFD_RELOC_MIPS_RELGOT
:
11046 case BFD_RELOC_MIPS_JALR
:
11047 case BFD_RELOC_HI16
:
11048 case BFD_RELOC_HI16_S
:
11049 case BFD_RELOC_GPREL16
:
11050 case BFD_RELOC_MIPS_LITERAL
:
11051 case BFD_RELOC_MIPS_CALL16
:
11052 case BFD_RELOC_MIPS_GOT16
:
11053 case BFD_RELOC_GPREL32
:
11054 case BFD_RELOC_MIPS_GOT_HI16
:
11055 case BFD_RELOC_MIPS_GOT_LO16
:
11056 case BFD_RELOC_MIPS_CALL_HI16
:
11057 case BFD_RELOC_MIPS_CALL_LO16
:
11058 case BFD_RELOC_MIPS16_GPREL
:
11059 case BFD_RELOC_MIPS16_HI16
:
11060 case BFD_RELOC_MIPS16_HI16_S
:
11061 assert (! fixP
->fx_pcrel
);
11062 /* Nothing needed to do. The value comes from the reloc entry */
11065 case BFD_RELOC_MIPS16_JMP
:
11066 /* We currently always generate a reloc against a symbol, which
11067 means that we don't want an addend even if the symbol is
11073 /* This is handled like BFD_RELOC_32, but we output a sign
11074 extended value if we are only 32 bits. */
11077 if (8 <= sizeof (valueT
))
11078 md_number_to_chars (buf
, *valP
, 8);
11083 if ((*valP
& 0x80000000) != 0)
11087 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11089 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11095 case BFD_RELOC_RVA
:
11097 /* If we are deleting this reloc entry, we must fill in the
11098 value now. This can happen if we have a .word which is not
11099 resolved when it appears but is later defined. */
11101 md_number_to_chars (buf
, *valP
, 4);
11105 /* If we are deleting this reloc entry, we must fill in the
11108 md_number_to_chars (buf
, *valP
, 2);
11111 case BFD_RELOC_LO16
:
11112 case BFD_RELOC_MIPS16_LO16
:
11113 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11114 may be safe to remove, but if so it's not obvious. */
11115 /* When handling an embedded PIC switch statement, we can wind
11116 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11119 if (*valP
+ 0x8000 > 0xffff)
11120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11121 _("relocation overflow"));
11122 if (target_big_endian
)
11124 md_number_to_chars (buf
, *valP
, 2);
11128 case BFD_RELOC_16_PCREL_S2
:
11129 if ((*valP
& 0x3) != 0)
11130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11131 _("Branch to odd address (%lx)"), (long) *valP
);
11134 * We need to save the bits in the instruction since fixup_segment()
11135 * might be deleting the relocation entry (i.e., a branch within
11136 * the current segment).
11138 if (! fixP
->fx_done
)
11141 /* update old instruction data */
11142 if (target_big_endian
)
11143 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11145 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11147 if (*valP
+ 0x20000 <= 0x3ffff)
11149 insn
|= (*valP
>> 2) & 0xffff;
11150 md_number_to_chars (buf
, insn
, 4);
11152 else if (mips_pic
== NO_PIC
11154 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11155 && (fixP
->fx_frag
->fr_address
11156 < text_section
->vma
+ bfd_get_section_size (text_section
))
11157 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11158 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11159 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11161 /* The branch offset is too large. If this is an
11162 unconditional branch, and we are not generating PIC code,
11163 we can convert it to an absolute jump instruction. */
11164 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11165 insn
= 0x0c000000; /* jal */
11167 insn
= 0x08000000; /* j */
11168 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11170 fixP
->fx_addsy
= section_symbol (text_section
);
11171 *valP
+= md_pcrel_from (fixP
);
11172 md_number_to_chars (buf
, insn
, 4);
11176 /* If we got here, we have branch-relaxation disabled,
11177 and there's nothing we can do to fix this instruction
11178 without turning it into a longer sequence. */
11179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11180 _("Branch out of range"));
11184 case BFD_RELOC_VTABLE_INHERIT
:
11187 && !S_IS_DEFINED (fixP
->fx_addsy
)
11188 && !S_IS_WEAK (fixP
->fx_addsy
))
11189 S_SET_WEAK (fixP
->fx_addsy
);
11192 case BFD_RELOC_VTABLE_ENTRY
:
11200 /* Remember value for tc_gen_reloc. */
11201 fixP
->fx_addnumber
= *valP
;
11211 name
= input_line_pointer
;
11212 c
= get_symbol_end ();
11213 p
= (symbolS
*) symbol_find_or_make (name
);
11214 *input_line_pointer
= c
;
11218 /* Align the current frag to a given power of two. The MIPS assembler
11219 also automatically adjusts any preceding label. */
11222 mips_align (int to
, int fill
, symbolS
*label
)
11224 mips_emit_delays (FALSE
);
11225 frag_align (to
, fill
, 0);
11226 record_alignment (now_seg
, to
);
11229 assert (S_GET_SEGMENT (label
) == now_seg
);
11230 symbol_set_frag (label
, frag_now
);
11231 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11235 /* Align to a given power of two. .align 0 turns off the automatic
11236 alignment used by the data creating pseudo-ops. */
11239 s_align (int x ATTRIBUTE_UNUSED
)
11242 register long temp_fill
;
11243 long max_alignment
= 15;
11247 o Note that the assembler pulls down any immediately preceding label
11248 to the aligned address.
11249 o It's not documented but auto alignment is reinstated by
11250 a .align pseudo instruction.
11251 o Note also that after auto alignment is turned off the mips assembler
11252 issues an error on attempt to assemble an improperly aligned data item.
11257 temp
= get_absolute_expression ();
11258 if (temp
> max_alignment
)
11259 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11262 as_warn (_("Alignment negative: 0 assumed."));
11265 if (*input_line_pointer
== ',')
11267 ++input_line_pointer
;
11268 temp_fill
= get_absolute_expression ();
11275 mips_align (temp
, (int) temp_fill
,
11276 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11283 demand_empty_rest_of_line ();
11287 mips_flush_pending_output (void)
11289 mips_emit_delays (FALSE
);
11290 mips_clear_insn_labels ();
11294 s_change_sec (int sec
)
11299 /* The ELF backend needs to know that we are changing sections, so
11300 that .previous works correctly. We could do something like check
11301 for an obj_section_change_hook macro, but that might be confusing
11302 as it would not be appropriate to use it in the section changing
11303 functions in read.c, since obj-elf.c intercepts those. FIXME:
11304 This should be cleaner, somehow. */
11305 obj_elf_section_change_hook ();
11308 mips_emit_delays (FALSE
);
11318 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11319 demand_empty_rest_of_line ();
11323 seg
= subseg_new (RDATA_SECTION_NAME
,
11324 (subsegT
) get_absolute_expression ());
11325 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11327 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11328 | SEC_READONLY
| SEC_RELOC
11330 if (strcmp (TARGET_OS
, "elf") != 0)
11331 record_alignment (seg
, 4);
11333 demand_empty_rest_of_line ();
11337 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11338 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11340 bfd_set_section_flags (stdoutput
, seg
,
11341 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11342 if (strcmp (TARGET_OS
, "elf") != 0)
11343 record_alignment (seg
, 4);
11345 demand_empty_rest_of_line ();
11353 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11356 char *section_name
;
11361 int section_entry_size
;
11362 int section_alignment
;
11364 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11367 section_name
= input_line_pointer
;
11368 c
= get_symbol_end ();
11370 next_c
= *(input_line_pointer
+ 1);
11372 /* Do we have .section Name<,"flags">? */
11373 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11375 /* just after name is now '\0'. */
11376 *input_line_pointer
= c
;
11377 input_line_pointer
= section_name
;
11378 obj_elf_section (ignore
);
11381 input_line_pointer
++;
11383 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11385 section_type
= get_absolute_expression ();
11388 if (*input_line_pointer
++ == ',')
11389 section_flag
= get_absolute_expression ();
11392 if (*input_line_pointer
++ == ',')
11393 section_entry_size
= get_absolute_expression ();
11395 section_entry_size
= 0;
11396 if (*input_line_pointer
++ == ',')
11397 section_alignment
= get_absolute_expression ();
11399 section_alignment
= 0;
11401 section_name
= xstrdup (section_name
);
11403 /* When using the generic form of .section (as implemented by obj-elf.c),
11404 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11405 traditionally had to fall back on the more common @progbits instead.
11407 There's nothing really harmful in this, since bfd will correct
11408 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11409 means that, for backwards compatibiltiy, the special_section entries
11410 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11412 Even so, we shouldn't force users of the MIPS .section syntax to
11413 incorrectly label the sections as SHT_PROGBITS. The best compromise
11414 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11415 generic type-checking code. */
11416 if (section_type
== SHT_MIPS_DWARF
)
11417 section_type
= SHT_PROGBITS
;
11419 obj_elf_change_section (section_name
, section_type
, section_flag
,
11420 section_entry_size
, 0, 0, 0);
11422 if (now_seg
->name
!= section_name
)
11423 free (section_name
);
11424 #endif /* OBJ_ELF */
11428 mips_enable_auto_align (void)
11434 s_cons (int log_size
)
11438 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11439 mips_emit_delays (FALSE
);
11440 if (log_size
> 0 && auto_align
)
11441 mips_align (log_size
, 0, label
);
11442 mips_clear_insn_labels ();
11443 cons (1 << log_size
);
11447 s_float_cons (int type
)
11451 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11453 mips_emit_delays (FALSE
);
11458 mips_align (3, 0, label
);
11460 mips_align (2, 0, label
);
11463 mips_clear_insn_labels ();
11468 /* Handle .globl. We need to override it because on Irix 5 you are
11471 where foo is an undefined symbol, to mean that foo should be
11472 considered to be the address of a function. */
11475 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11482 name
= input_line_pointer
;
11483 c
= get_symbol_end ();
11484 symbolP
= symbol_find_or_make (name
);
11485 *input_line_pointer
= c
;
11486 SKIP_WHITESPACE ();
11488 /* On Irix 5, every global symbol that is not explicitly labelled as
11489 being a function is apparently labelled as being an object. */
11492 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11497 secname
= input_line_pointer
;
11498 c
= get_symbol_end ();
11499 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11501 as_bad (_("%s: no such section"), secname
);
11502 *input_line_pointer
= c
;
11504 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11505 flag
= BSF_FUNCTION
;
11508 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11510 S_SET_EXTERNAL (symbolP
);
11511 demand_empty_rest_of_line ();
11515 s_option (int x ATTRIBUTE_UNUSED
)
11520 opt
= input_line_pointer
;
11521 c
= get_symbol_end ();
11525 /* FIXME: What does this mean? */
11527 else if (strncmp (opt
, "pic", 3) == 0)
11531 i
= atoi (opt
+ 3);
11536 mips_pic
= SVR4_PIC
;
11537 mips_abicalls
= TRUE
;
11540 as_bad (_(".option pic%d not supported"), i
);
11542 if (mips_pic
== SVR4_PIC
)
11544 if (g_switch_seen
&& g_switch_value
!= 0)
11545 as_warn (_("-G may not be used with SVR4 PIC code"));
11546 g_switch_value
= 0;
11547 bfd_set_gp_size (stdoutput
, 0);
11551 as_warn (_("Unrecognized option \"%s\""), opt
);
11553 *input_line_pointer
= c
;
11554 demand_empty_rest_of_line ();
11557 /* This structure is used to hold a stack of .set values. */
11559 struct mips_option_stack
11561 struct mips_option_stack
*next
;
11562 struct mips_set_options options
;
11565 static struct mips_option_stack
*mips_opts_stack
;
11567 /* Handle the .set pseudo-op. */
11570 s_mipsset (int x ATTRIBUTE_UNUSED
)
11572 char *name
= input_line_pointer
, ch
;
11574 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11575 ++input_line_pointer
;
11576 ch
= *input_line_pointer
;
11577 *input_line_pointer
= '\0';
11579 if (strcmp (name
, "reorder") == 0)
11581 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11583 /* If we still have pending nops, we can discard them. The
11584 usual nop handling will insert any that are still
11586 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11587 * (mips_opts
.mips16
? 2 : 4));
11588 prev_nop_frag
= NULL
;
11590 mips_opts
.noreorder
= 0;
11592 else if (strcmp (name
, "noreorder") == 0)
11594 mips_emit_delays (TRUE
);
11595 mips_opts
.noreorder
= 1;
11596 mips_any_noreorder
= 1;
11598 else if (strcmp (name
, "at") == 0)
11600 mips_opts
.noat
= 0;
11602 else if (strcmp (name
, "noat") == 0)
11604 mips_opts
.noat
= 1;
11606 else if (strcmp (name
, "macro") == 0)
11608 mips_opts
.warn_about_macros
= 0;
11610 else if (strcmp (name
, "nomacro") == 0)
11612 if (mips_opts
.noreorder
== 0)
11613 as_bad (_("`noreorder' must be set before `nomacro'"));
11614 mips_opts
.warn_about_macros
= 1;
11616 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11618 mips_opts
.nomove
= 0;
11620 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11622 mips_opts
.nomove
= 1;
11624 else if (strcmp (name
, "bopt") == 0)
11626 mips_opts
.nobopt
= 0;
11628 else if (strcmp (name
, "nobopt") == 0)
11630 mips_opts
.nobopt
= 1;
11632 else if (strcmp (name
, "mips16") == 0
11633 || strcmp (name
, "MIPS-16") == 0)
11634 mips_opts
.mips16
= 1;
11635 else if (strcmp (name
, "nomips16") == 0
11636 || strcmp (name
, "noMIPS-16") == 0)
11637 mips_opts
.mips16
= 0;
11638 else if (strcmp (name
, "mips3d") == 0)
11639 mips_opts
.ase_mips3d
= 1;
11640 else if (strcmp (name
, "nomips3d") == 0)
11641 mips_opts
.ase_mips3d
= 0;
11642 else if (strcmp (name
, "mdmx") == 0)
11643 mips_opts
.ase_mdmx
= 1;
11644 else if (strcmp (name
, "nomdmx") == 0)
11645 mips_opts
.ase_mdmx
= 0;
11646 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11650 /* Permit the user to change the ISA and architecture on the fly.
11651 Needless to say, misuse can cause serious problems. */
11652 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11655 mips_opts
.isa
= file_mips_isa
;
11656 mips_opts
.arch
= file_mips_arch
;
11658 else if (strncmp (name
, "arch=", 5) == 0)
11660 const struct mips_cpu_info
*p
;
11662 p
= mips_parse_cpu("internal use", name
+ 5);
11664 as_bad (_("unknown architecture %s"), name
+ 5);
11667 mips_opts
.arch
= p
->cpu
;
11668 mips_opts
.isa
= p
->isa
;
11671 else if (strncmp (name
, "mips", 4) == 0)
11673 const struct mips_cpu_info
*p
;
11675 p
= mips_parse_cpu("internal use", name
);
11677 as_bad (_("unknown ISA level %s"), name
+ 4);
11680 mips_opts
.arch
= p
->cpu
;
11681 mips_opts
.isa
= p
->isa
;
11685 as_bad (_("unknown ISA or architecture %s"), name
);
11687 switch (mips_opts
.isa
)
11695 mips_opts
.gp32
= 1;
11696 mips_opts
.fp32
= 1;
11703 mips_opts
.gp32
= 0;
11704 mips_opts
.fp32
= 0;
11707 as_bad (_("unknown ISA level %s"), name
+ 4);
11712 mips_opts
.gp32
= file_mips_gp32
;
11713 mips_opts
.fp32
= file_mips_fp32
;
11716 else if (strcmp (name
, "autoextend") == 0)
11717 mips_opts
.noautoextend
= 0;
11718 else if (strcmp (name
, "noautoextend") == 0)
11719 mips_opts
.noautoextend
= 1;
11720 else if (strcmp (name
, "push") == 0)
11722 struct mips_option_stack
*s
;
11724 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11725 s
->next
= mips_opts_stack
;
11726 s
->options
= mips_opts
;
11727 mips_opts_stack
= s
;
11729 else if (strcmp (name
, "pop") == 0)
11731 struct mips_option_stack
*s
;
11733 s
= mips_opts_stack
;
11735 as_bad (_(".set pop with no .set push"));
11738 /* If we're changing the reorder mode we need to handle
11739 delay slots correctly. */
11740 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11741 mips_emit_delays (TRUE
);
11742 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11744 if (prev_nop_frag
!= NULL
)
11746 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11747 * (mips_opts
.mips16
? 2 : 4));
11748 prev_nop_frag
= NULL
;
11752 mips_opts
= s
->options
;
11753 mips_opts_stack
= s
->next
;
11759 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11761 *input_line_pointer
= ch
;
11762 demand_empty_rest_of_line ();
11765 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11766 .option pic2. It means to generate SVR4 PIC calls. */
11769 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11771 mips_pic
= SVR4_PIC
;
11772 mips_abicalls
= TRUE
;
11774 if (g_switch_seen
&& g_switch_value
!= 0)
11775 as_warn (_("-G may not be used with SVR4 PIC code"));
11776 g_switch_value
= 0;
11778 bfd_set_gp_size (stdoutput
, 0);
11779 demand_empty_rest_of_line ();
11782 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11783 PIC code. It sets the $gp register for the function based on the
11784 function address, which is in the register named in the argument.
11785 This uses a relocation against _gp_disp, which is handled specially
11786 by the linker. The result is:
11787 lui $gp,%hi(_gp_disp)
11788 addiu $gp,$gp,%lo(_gp_disp)
11789 addu $gp,$gp,.cpload argument
11790 The .cpload argument is normally $25 == $t9.
11792 The -mno-shared option changes this to:
11794 addiu $gp,$gp,%lo(_gp)
11795 and the argument is ignored. This saves an instruction, but the
11796 resulting code is not position independent; it uses an absolute
11797 address for _gp. Thus code assembled with -mno-shared can go into
11798 an ordinary executable, but not into a shared library. */
11801 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11807 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11808 .cpload is ignored. */
11809 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11815 /* .cpload should be in a .set noreorder section. */
11816 if (mips_opts
.noreorder
== 0)
11817 as_warn (_(".cpload not in noreorder section"));
11819 reg
= tc_get_register (0);
11821 /* If we need to produce a 64-bit address, we are better off using
11822 the default instruction sequence. */
11823 in_shared
= mips_in_shared
|| HAVE_64BIT_ADDRESSES
;
11825 ex
.X_op
= O_symbol
;
11826 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" : "_gp");
11827 ex
.X_op_symbol
= NULL
;
11828 ex
.X_add_number
= 0;
11830 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11831 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11834 macro_build_lui (&ex
, mips_gp_register
);
11835 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11836 mips_gp_register
, BFD_RELOC_LO16
);
11838 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11839 mips_gp_register
, reg
);
11842 demand_empty_rest_of_line ();
11845 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11846 .cpsetup $reg1, offset|$reg2, label
11848 If offset is given, this results in:
11849 sd $gp, offset($sp)
11850 lui $gp, %hi(%neg(%gp_rel(label)))
11851 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11852 daddu $gp, $gp, $reg1
11854 If $reg2 is given, this results in:
11855 daddu $reg2, $gp, $0
11856 lui $gp, %hi(%neg(%gp_rel(label)))
11857 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11858 daddu $gp, $gp, $reg1
11859 $reg1 is normally $25 == $t9.
11861 The -mno-shared option replaces the last three instructions with
11863 addiu $gp,$gp,%lo(_gp)
11867 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11869 expressionS ex_off
;
11870 expressionS ex_sym
;
11873 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11874 We also need NewABI support. */
11875 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11881 reg1
= tc_get_register (0);
11882 SKIP_WHITESPACE ();
11883 if (*input_line_pointer
!= ',')
11885 as_bad (_("missing argument separator ',' for .cpsetup"));
11889 ++input_line_pointer
;
11890 SKIP_WHITESPACE ();
11891 if (*input_line_pointer
== '$')
11893 mips_cpreturn_register
= tc_get_register (0);
11894 mips_cpreturn_offset
= -1;
11898 mips_cpreturn_offset
= get_absolute_expression ();
11899 mips_cpreturn_register
= -1;
11901 SKIP_WHITESPACE ();
11902 if (*input_line_pointer
!= ',')
11904 as_bad (_("missing argument separator ',' for .cpsetup"));
11908 ++input_line_pointer
;
11909 SKIP_WHITESPACE ();
11910 expression (&ex_sym
);
11913 if (mips_cpreturn_register
== -1)
11915 ex_off
.X_op
= O_constant
;
11916 ex_off
.X_add_symbol
= NULL
;
11917 ex_off
.X_op_symbol
= NULL
;
11918 ex_off
.X_add_number
= mips_cpreturn_offset
;
11920 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11921 BFD_RELOC_LO16
, SP
);
11924 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11925 mips_gp_register
, 0);
11927 if (mips_in_shared
|| HAVE_64BIT_ADDRESSES
)
11929 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11930 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11933 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11934 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11935 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11938 mips_gp_register
, reg1
);
11944 ex
.X_op
= O_symbol
;
11945 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11946 ex
.X_op_symbol
= NULL
;
11947 ex
.X_add_number
= 0;
11949 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11950 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11952 macro_build_lui (&ex
, mips_gp_register
);
11953 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11954 mips_gp_register
, BFD_RELOC_LO16
);
11959 demand_empty_rest_of_line ();
11963 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11965 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11966 .cplocal is ignored. */
11967 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11973 mips_gp_register
= tc_get_register (0);
11974 demand_empty_rest_of_line ();
11977 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11978 offset from $sp. The offset is remembered, and after making a PIC
11979 call $gp is restored from that location. */
11982 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11986 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11987 .cprestore is ignored. */
11988 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11994 mips_cprestore_offset
= get_absolute_expression ();
11995 mips_cprestore_valid
= 1;
11997 ex
.X_op
= O_constant
;
11998 ex
.X_add_symbol
= NULL
;
11999 ex
.X_op_symbol
= NULL
;
12000 ex
.X_add_number
= mips_cprestore_offset
;
12003 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12004 SP
, HAVE_64BIT_ADDRESSES
);
12007 demand_empty_rest_of_line ();
12010 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12011 was given in the preceding .cpsetup, it results in:
12012 ld $gp, offset($sp)
12014 If a register $reg2 was given there, it results in:
12015 daddu $gp, $reg2, $0
12018 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12022 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12023 We also need NewABI support. */
12024 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12031 if (mips_cpreturn_register
== -1)
12033 ex
.X_op
= O_constant
;
12034 ex
.X_add_symbol
= NULL
;
12035 ex
.X_op_symbol
= NULL
;
12036 ex
.X_add_number
= mips_cpreturn_offset
;
12038 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12041 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12042 mips_cpreturn_register
, 0);
12045 demand_empty_rest_of_line ();
12048 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12049 code. It sets the offset to use in gp_rel relocations. */
12052 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12054 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12055 We also need NewABI support. */
12056 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12062 mips_gprel_offset
= get_absolute_expression ();
12064 demand_empty_rest_of_line ();
12067 /* Handle the .gpword pseudo-op. This is used when generating PIC
12068 code. It generates a 32 bit GP relative reloc. */
12071 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12077 /* When not generating PIC code, this is treated as .word. */
12078 if (mips_pic
!= SVR4_PIC
)
12084 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12085 mips_emit_delays (TRUE
);
12087 mips_align (2, 0, label
);
12088 mips_clear_insn_labels ();
12092 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12094 as_bad (_("Unsupported use of .gpword"));
12095 ignore_rest_of_line ();
12099 md_number_to_chars (p
, 0, 4);
12100 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12101 BFD_RELOC_GPREL32
);
12103 demand_empty_rest_of_line ();
12107 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12113 /* When not generating PIC code, this is treated as .dword. */
12114 if (mips_pic
!= SVR4_PIC
)
12120 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12121 mips_emit_delays (TRUE
);
12123 mips_align (3, 0, label
);
12124 mips_clear_insn_labels ();
12128 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12130 as_bad (_("Unsupported use of .gpdword"));
12131 ignore_rest_of_line ();
12135 md_number_to_chars (p
, 0, 8);
12136 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12137 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12139 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12140 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12141 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12143 demand_empty_rest_of_line ();
12146 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12147 tables in SVR4 PIC code. */
12150 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12154 /* This is ignored when not generating SVR4 PIC code. */
12155 if (mips_pic
!= SVR4_PIC
)
12161 /* Add $gp to the register named as an argument. */
12163 reg
= tc_get_register (0);
12164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12167 demand_empty_rest_of_line ();
12170 /* Handle the .insn pseudo-op. This marks instruction labels in
12171 mips16 mode. This permits the linker to handle them specially,
12172 such as generating jalx instructions when needed. We also make
12173 them odd for the duration of the assembly, in order to generate the
12174 right sort of code. We will make them even in the adjust_symtab
12175 routine, while leaving them marked. This is convenient for the
12176 debugger and the disassembler. The linker knows to make them odd
12180 s_insn (int ignore ATTRIBUTE_UNUSED
)
12182 mips16_mark_labels ();
12184 demand_empty_rest_of_line ();
12187 /* Handle a .stabn directive. We need these in order to mark a label
12188 as being a mips16 text label correctly. Sometimes the compiler
12189 will emit a label, followed by a .stabn, and then switch sections.
12190 If the label and .stabn are in mips16 mode, then the label is
12191 really a mips16 text label. */
12194 s_mips_stab (int type
)
12197 mips16_mark_labels ();
12202 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12206 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12213 name
= input_line_pointer
;
12214 c
= get_symbol_end ();
12215 symbolP
= symbol_find_or_make (name
);
12216 S_SET_WEAK (symbolP
);
12217 *input_line_pointer
= c
;
12219 SKIP_WHITESPACE ();
12221 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12223 if (S_IS_DEFINED (symbolP
))
12225 as_bad ("ignoring attempt to redefine symbol %s",
12226 S_GET_NAME (symbolP
));
12227 ignore_rest_of_line ();
12231 if (*input_line_pointer
== ',')
12233 ++input_line_pointer
;
12234 SKIP_WHITESPACE ();
12238 if (exp
.X_op
!= O_symbol
)
12240 as_bad ("bad .weakext directive");
12241 ignore_rest_of_line ();
12244 symbol_set_value_expression (symbolP
, &exp
);
12247 demand_empty_rest_of_line ();
12250 /* Parse a register string into a number. Called from the ECOFF code
12251 to parse .frame. The argument is non-zero if this is the frame
12252 register, so that we can record it in mips_frame_reg. */
12255 tc_get_register (int frame
)
12259 SKIP_WHITESPACE ();
12260 if (*input_line_pointer
++ != '$')
12262 as_warn (_("expected `$'"));
12265 else if (ISDIGIT (*input_line_pointer
))
12267 reg
= get_absolute_expression ();
12268 if (reg
< 0 || reg
>= 32)
12270 as_warn (_("Bad register number"));
12276 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12279 input_line_pointer
+= 2;
12281 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12284 input_line_pointer
+= 2;
12286 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12289 input_line_pointer
+= 2;
12291 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12294 input_line_pointer
+= 2;
12296 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12299 input_line_pointer
+= 2;
12301 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12304 input_line_pointer
+= 3;
12306 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12309 input_line_pointer
+= 3;
12311 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12314 input_line_pointer
+= 4;
12318 as_warn (_("Unrecognized register name"));
12320 while (ISALNUM(*input_line_pointer
))
12321 input_line_pointer
++;
12326 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12327 mips_frame_reg_valid
= 1;
12328 mips_cprestore_valid
= 0;
12334 md_section_align (asection
*seg
, valueT addr
)
12336 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12339 /* We don't need to align ELF sections to the full alignment.
12340 However, Irix 5 may prefer that we align them at least to a 16
12341 byte boundary. We don't bother to align the sections if we are
12342 targeted for an embedded system. */
12343 if (strcmp (TARGET_OS
, "elf") == 0)
12349 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12352 /* Utility routine, called from above as well. If called while the
12353 input file is still being read, it's only an approximation. (For
12354 example, a symbol may later become defined which appeared to be
12355 undefined earlier.) */
12358 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12363 if (g_switch_value
> 0)
12365 const char *symname
;
12368 /* Find out whether this symbol can be referenced off the $gp
12369 register. It can be if it is smaller than the -G size or if
12370 it is in the .sdata or .sbss section. Certain symbols can
12371 not be referenced off the $gp, although it appears as though
12373 symname
= S_GET_NAME (sym
);
12374 if (symname
!= (const char *) NULL
12375 && (strcmp (symname
, "eprol") == 0
12376 || strcmp (symname
, "etext") == 0
12377 || strcmp (symname
, "_gp") == 0
12378 || strcmp (symname
, "edata") == 0
12379 || strcmp (symname
, "_fbss") == 0
12380 || strcmp (symname
, "_fdata") == 0
12381 || strcmp (symname
, "_ftext") == 0
12382 || strcmp (symname
, "end") == 0
12383 || strcmp (symname
, "_gp_disp") == 0))
12385 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12387 #ifndef NO_ECOFF_DEBUGGING
12388 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12389 && (symbol_get_obj (sym
)->ecoff_extern_size
12390 <= g_switch_value
))
12392 /* We must defer this decision until after the whole
12393 file has been read, since there might be a .extern
12394 after the first use of this symbol. */
12395 || (before_relaxing
12396 #ifndef NO_ECOFF_DEBUGGING
12397 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12399 && S_GET_VALUE (sym
) == 0)
12400 || (S_GET_VALUE (sym
) != 0
12401 && S_GET_VALUE (sym
) <= g_switch_value
)))
12405 const char *segname
;
12407 segname
= segment_name (S_GET_SEGMENT (sym
));
12408 assert (strcmp (segname
, ".lit8") != 0
12409 && strcmp (segname
, ".lit4") != 0);
12410 change
= (strcmp (segname
, ".sdata") != 0
12411 && strcmp (segname
, ".sbss") != 0
12412 && strncmp (segname
, ".sdata.", 7) != 0
12413 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12418 /* We are not optimizing for the $gp register. */
12423 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12426 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12429 bfd_boolean linkonce
;
12431 /* Handle the case of a symbol equated to another symbol. */
12432 while (symbol_equated_reloc_p (sym
))
12436 /* It's possible to get a loop here in a badly written
12438 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12444 symsec
= S_GET_SEGMENT (sym
);
12446 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12448 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12450 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12454 /* The GNU toolchain uses an extension for ELF: a section
12455 beginning with the magic string .gnu.linkonce is a linkonce
12457 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12458 sizeof ".gnu.linkonce" - 1) == 0)
12462 /* This must duplicate the test in adjust_reloc_syms. */
12463 return (symsec
!= &bfd_und_section
12464 && symsec
!= &bfd_abs_section
12465 && ! bfd_is_com_section (symsec
)
12468 /* A global or weak symbol is treated as external. */
12469 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12470 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12476 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12477 extended opcode. SEC is the section the frag is in. */
12480 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12483 register const struct mips16_immed_operand
*op
;
12485 int mintiny
, maxtiny
;
12489 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12491 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12494 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12495 op
= mips16_immed_operands
;
12496 while (op
->type
!= type
)
12499 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12504 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12507 maxtiny
= 1 << op
->nbits
;
12512 maxtiny
= (1 << op
->nbits
) - 1;
12517 mintiny
= - (1 << (op
->nbits
- 1));
12518 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12521 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12522 val
= S_GET_VALUE (fragp
->fr_symbol
);
12523 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12529 /* We won't have the section when we are called from
12530 mips_relax_frag. However, we will always have been called
12531 from md_estimate_size_before_relax first. If this is a
12532 branch to a different section, we mark it as such. If SEC is
12533 NULL, and the frag is not marked, then it must be a branch to
12534 the same section. */
12537 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12542 /* Must have been called from md_estimate_size_before_relax. */
12545 fragp
->fr_subtype
=
12546 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12548 /* FIXME: We should support this, and let the linker
12549 catch branches and loads that are out of range. */
12550 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12551 _("unsupported PC relative reference to different section"));
12555 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12556 /* Assume non-extended on the first relaxation pass.
12557 The address we have calculated will be bogus if this is
12558 a forward branch to another frag, as the forward frag
12559 will have fr_address == 0. */
12563 /* In this case, we know for sure that the symbol fragment is in
12564 the same section. If the relax_marker of the symbol fragment
12565 differs from the relax_marker of this fragment, we have not
12566 yet adjusted the symbol fragment fr_address. We want to add
12567 in STRETCH in order to get a better estimate of the address.
12568 This particularly matters because of the shift bits. */
12570 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12574 /* Adjust stretch for any alignment frag. Note that if have
12575 been expanding the earlier code, the symbol may be
12576 defined in what appears to be an earlier frag. FIXME:
12577 This doesn't handle the fr_subtype field, which specifies
12578 a maximum number of bytes to skip when doing an
12580 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12582 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12585 stretch
= - ((- stretch
)
12586 & ~ ((1 << (int) f
->fr_offset
) - 1));
12588 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12597 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12599 /* The base address rules are complicated. The base address of
12600 a branch is the following instruction. The base address of a
12601 PC relative load or add is the instruction itself, but if it
12602 is in a delay slot (in which case it can not be extended) use
12603 the address of the instruction whose delay slot it is in. */
12604 if (type
== 'p' || type
== 'q')
12608 /* If we are currently assuming that this frag should be
12609 extended, then, the current address is two bytes
12611 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12614 /* Ignore the low bit in the target, since it will be set
12615 for a text label. */
12616 if ((val
& 1) != 0)
12619 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12621 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12624 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12626 /* Branch offsets have an implicit 0 in the lowest bit. */
12627 if (type
== 'p' || type
== 'q')
12630 /* If any of the shifted bits are set, we must use an extended
12631 opcode. If the address depends on the size of this
12632 instruction, this can lead to a loop, so we arrange to always
12633 use an extended opcode. We only check this when we are in
12634 the main relaxation loop, when SEC is NULL. */
12635 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12637 fragp
->fr_subtype
=
12638 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12642 /* If we are about to mark a frag as extended because the value
12643 is precisely maxtiny + 1, then there is a chance of an
12644 infinite loop as in the following code:
12649 In this case when the la is extended, foo is 0x3fc bytes
12650 away, so the la can be shrunk, but then foo is 0x400 away, so
12651 the la must be extended. To avoid this loop, we mark the
12652 frag as extended if it was small, and is about to become
12653 extended with a value of maxtiny + 1. */
12654 if (val
== ((maxtiny
+ 1) << op
->shift
)
12655 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12658 fragp
->fr_subtype
=
12659 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12663 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12664 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12666 if ((val
& ((1 << op
->shift
) - 1)) != 0
12667 || val
< (mintiny
<< op
->shift
)
12668 || val
> (maxtiny
<< op
->shift
))
12674 /* Compute the length of a branch sequence, and adjust the
12675 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12676 worst-case length is computed, with UPDATE being used to indicate
12677 whether an unconditional (-1), branch-likely (+1) or regular (0)
12678 branch is to be computed. */
12680 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12682 bfd_boolean toofar
;
12686 && S_IS_DEFINED (fragp
->fr_symbol
)
12687 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12692 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12694 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12698 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12701 /* If the symbol is not defined or it's in a different segment,
12702 assume the user knows what's going on and emit a short
12708 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12710 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12711 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12712 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12718 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12721 if (mips_pic
!= NO_PIC
)
12723 /* Additional space for PIC loading of target address. */
12725 if (mips_opts
.isa
== ISA_MIPS1
)
12726 /* Additional space for $at-stabilizing nop. */
12730 /* If branch is conditional. */
12731 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12738 /* Estimate the size of a frag before relaxing. Unless this is the
12739 mips16, we are not really relaxing here, and the final size is
12740 encoded in the subtype information. For the mips16, we have to
12741 decide whether we are using an extended opcode or not. */
12744 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12748 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12751 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12753 return fragp
->fr_var
;
12756 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12757 /* We don't want to modify the EXTENDED bit here; it might get us
12758 into infinite loops. We change it only in mips_relax_frag(). */
12759 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12761 if (mips_pic
== NO_PIC
)
12762 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12763 else if (mips_pic
== SVR4_PIC
)
12764 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12770 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12771 return -RELAX_FIRST (fragp
->fr_subtype
);
12774 return -RELAX_SECOND (fragp
->fr_subtype
);
12777 /* This is called to see whether a reloc against a defined symbol
12778 should be converted into a reloc against a section. */
12781 mips_fix_adjustable (fixS
*fixp
)
12783 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12784 about the format of the offset in the .o file. */
12785 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12788 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12789 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12792 if (fixp
->fx_addsy
== NULL
)
12795 /* If symbol SYM is in a mergeable section, relocations of the form
12796 SYM + 0 can usually be made section-relative. The mergeable data
12797 is then identified by the section offset rather than by the symbol.
12799 However, if we're generating REL LO16 relocations, the offset is split
12800 between the LO16 and parterning high part relocation. The linker will
12801 need to recalculate the complete offset in order to correctly identify
12804 The linker has traditionally not looked for the parterning high part
12805 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12806 placed anywhere. Rather than break backwards compatibility by changing
12807 this, it seems better not to force the issue, and instead keep the
12808 original symbol. This will work with either linker behavior. */
12809 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12810 && HAVE_IN_PLACE_ADDENDS
12811 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12815 /* Don't adjust relocations against mips16 symbols, so that the linker
12816 can find them if it needs to set up a stub. */
12817 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12818 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12819 && fixp
->fx_subsy
== NULL
)
12826 /* Translate internal representation of relocation info to BFD target
12830 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12832 static arelent
*retval
[4];
12834 bfd_reloc_code_real_type code
;
12836 memset (retval
, 0, sizeof(retval
));
12837 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12838 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12839 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12840 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12842 assert (! fixp
->fx_pcrel
);
12843 reloc
->addend
= fixp
->fx_addnumber
;
12845 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12846 entry to be used in the relocation's section offset. */
12847 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12849 reloc
->address
= reloc
->addend
;
12853 code
= fixp
->fx_r_type
;
12855 /* To support a PC relative reloc, we used a Cygnus extension.
12856 We check for that here to make sure that we don't let such a
12857 reloc escape normally. (FIXME: This was formerly used by
12858 embedded-PIC support, but is now used by branch handling in
12859 general. That probably should be fixed.) */
12860 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12861 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12862 && code
== BFD_RELOC_16_PCREL_S2
)
12863 reloc
->howto
= NULL
;
12865 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12867 if (reloc
->howto
== NULL
)
12869 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12870 _("Can not represent %s relocation in this object file format"),
12871 bfd_get_reloc_code_name (code
));
12878 /* Relax a machine dependent frag. This returns the amount by which
12879 the current size of the frag should change. */
12882 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12884 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12886 offsetT old_var
= fragp
->fr_var
;
12888 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12890 return fragp
->fr_var
- old_var
;
12893 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12896 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12898 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12900 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12905 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12907 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12914 /* Convert a machine dependent frag. */
12917 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12919 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12922 unsigned long insn
;
12926 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12928 if (target_big_endian
)
12929 insn
= bfd_getb32 (buf
);
12931 insn
= bfd_getl32 (buf
);
12933 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12935 /* We generate a fixup instead of applying it right now
12936 because, if there are linker relaxations, we're going to
12937 need the relocations. */
12938 exp
.X_op
= O_symbol
;
12939 exp
.X_add_symbol
= fragp
->fr_symbol
;
12940 exp
.X_add_number
= fragp
->fr_offset
;
12942 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12944 BFD_RELOC_16_PCREL_S2
);
12945 fixp
->fx_file
= fragp
->fr_file
;
12946 fixp
->fx_line
= fragp
->fr_line
;
12948 md_number_to_chars (buf
, insn
, 4);
12955 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12956 _("relaxed out-of-range branch into a jump"));
12958 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12961 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12963 /* Reverse the branch. */
12964 switch ((insn
>> 28) & 0xf)
12967 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12968 have the condition reversed by tweaking a single
12969 bit, and their opcodes all have 0x4???????. */
12970 assert ((insn
& 0xf1000000) == 0x41000000);
12971 insn
^= 0x00010000;
12975 /* bltz 0x04000000 bgez 0x04010000
12976 bltzal 0x04100000 bgezal 0x04110000 */
12977 assert ((insn
& 0xfc0e0000) == 0x04000000);
12978 insn
^= 0x00010000;
12982 /* beq 0x10000000 bne 0x14000000
12983 blez 0x18000000 bgtz 0x1c000000 */
12984 insn
^= 0x04000000;
12992 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12994 /* Clear the and-link bit. */
12995 assert ((insn
& 0xfc1c0000) == 0x04100000);
12997 /* bltzal 0x04100000 bgezal 0x04110000
12998 bltzall 0x04120000 bgezall 0x04130000 */
12999 insn
&= ~0x00100000;
13002 /* Branch over the branch (if the branch was likely) or the
13003 full jump (not likely case). Compute the offset from the
13004 current instruction to branch to. */
13005 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13009 /* How many bytes in instructions we've already emitted? */
13010 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13011 /* How many bytes in instructions from here to the end? */
13012 i
= fragp
->fr_var
- i
;
13014 /* Convert to instruction count. */
13016 /* Branch counts from the next instruction. */
13019 /* Branch over the jump. */
13020 md_number_to_chars (buf
, insn
, 4);
13024 md_number_to_chars (buf
, 0, 4);
13027 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13029 /* beql $0, $0, 2f */
13031 /* Compute the PC offset from the current instruction to
13032 the end of the variable frag. */
13033 /* How many bytes in instructions we've already emitted? */
13034 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13035 /* How many bytes in instructions from here to the end? */
13036 i
= fragp
->fr_var
- i
;
13037 /* Convert to instruction count. */
13039 /* Don't decrement i, because we want to branch over the
13043 md_number_to_chars (buf
, insn
, 4);
13046 md_number_to_chars (buf
, 0, 4);
13051 if (mips_pic
== NO_PIC
)
13054 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13055 ? 0x0c000000 : 0x08000000);
13056 exp
.X_op
= O_symbol
;
13057 exp
.X_add_symbol
= fragp
->fr_symbol
;
13058 exp
.X_add_number
= fragp
->fr_offset
;
13060 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13061 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13062 fixp
->fx_file
= fragp
->fr_file
;
13063 fixp
->fx_line
= fragp
->fr_line
;
13065 md_number_to_chars (buf
, insn
, 4);
13070 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13071 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13072 exp
.X_op
= O_symbol
;
13073 exp
.X_add_symbol
= fragp
->fr_symbol
;
13074 exp
.X_add_number
= fragp
->fr_offset
;
13076 if (fragp
->fr_offset
)
13078 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13079 exp
.X_add_number
= 0;
13082 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13083 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13084 fixp
->fx_file
= fragp
->fr_file
;
13085 fixp
->fx_line
= fragp
->fr_line
;
13087 md_number_to_chars (buf
, insn
, 4);
13090 if (mips_opts
.isa
== ISA_MIPS1
)
13093 md_number_to_chars (buf
, 0, 4);
13097 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13098 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13100 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13101 4, &exp
, 0, BFD_RELOC_LO16
);
13102 fixp
->fx_file
= fragp
->fr_file
;
13103 fixp
->fx_line
= fragp
->fr_line
;
13105 md_number_to_chars (buf
, insn
, 4);
13109 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13114 md_number_to_chars (buf
, insn
, 4);
13119 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13120 + fragp
->fr_fix
+ fragp
->fr_var
);
13122 fragp
->fr_fix
+= fragp
->fr_var
;
13127 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13130 register const struct mips16_immed_operand
*op
;
13131 bfd_boolean small
, ext
;
13134 unsigned long insn
;
13135 bfd_boolean use_extend
;
13136 unsigned short extend
;
13138 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13139 op
= mips16_immed_operands
;
13140 while (op
->type
!= type
)
13143 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13154 resolve_symbol_value (fragp
->fr_symbol
);
13155 val
= S_GET_VALUE (fragp
->fr_symbol
);
13160 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13162 /* The rules for the base address of a PC relative reloc are
13163 complicated; see mips16_extended_frag. */
13164 if (type
== 'p' || type
== 'q')
13169 /* Ignore the low bit in the target, since it will be
13170 set for a text label. */
13171 if ((val
& 1) != 0)
13174 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13176 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13179 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13182 /* Make sure the section winds up with the alignment we have
13185 record_alignment (asec
, op
->shift
);
13189 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13190 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13191 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13192 _("extended instruction in delay slot"));
13194 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13196 if (target_big_endian
)
13197 insn
= bfd_getb16 (buf
);
13199 insn
= bfd_getl16 (buf
);
13201 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13202 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13203 small
, ext
, &insn
, &use_extend
, &extend
);
13207 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13208 fragp
->fr_fix
+= 2;
13212 md_number_to_chars (buf
, insn
, 2);
13213 fragp
->fr_fix
+= 2;
13221 first
= RELAX_FIRST (fragp
->fr_subtype
);
13222 second
= RELAX_SECOND (fragp
->fr_subtype
);
13223 fixp
= (fixS
*) fragp
->fr_opcode
;
13225 /* Possibly emit a warning if we've chosen the longer option. */
13226 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13227 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13229 const char *msg
= macro_warning (fragp
->fr_subtype
);
13231 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13234 /* Go through all the fixups for the first sequence. Disable them
13235 (by marking them as done) if we're going to use the second
13236 sequence instead. */
13238 && fixp
->fx_frag
== fragp
13239 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13241 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13243 fixp
= fixp
->fx_next
;
13246 /* Go through the fixups for the second sequence. Disable them if
13247 we're going to use the first sequence, otherwise adjust their
13248 addresses to account for the relaxation. */
13249 while (fixp
&& fixp
->fx_frag
== fragp
)
13251 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13252 fixp
->fx_where
-= first
;
13255 fixp
= fixp
->fx_next
;
13258 /* Now modify the frag contents. */
13259 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13263 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13264 memmove (start
, start
+ first
, second
);
13265 fragp
->fr_fix
-= first
;
13268 fragp
->fr_fix
-= second
;
13274 /* This function is called after the relocs have been generated.
13275 We've been storing mips16 text labels as odd. Here we convert them
13276 back to even for the convenience of the debugger. */
13279 mips_frob_file_after_relocs (void)
13282 unsigned int count
, i
;
13284 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13287 syms
= bfd_get_outsymbols (stdoutput
);
13288 count
= bfd_get_symcount (stdoutput
);
13289 for (i
= 0; i
< count
; i
++, syms
++)
13291 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13292 && ((*syms
)->value
& 1) != 0)
13294 (*syms
)->value
&= ~1;
13295 /* If the symbol has an odd size, it was probably computed
13296 incorrectly, so adjust that as well. */
13297 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13298 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13305 /* This function is called whenever a label is defined. It is used
13306 when handling branch delays; if a branch has a label, we assume we
13307 can not move it. */
13310 mips_define_label (symbolS
*sym
)
13312 struct insn_label_list
*l
;
13314 if (free_insn_labels
== NULL
)
13315 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13318 l
= free_insn_labels
;
13319 free_insn_labels
= l
->next
;
13323 l
->next
= insn_labels
;
13327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13329 /* Some special processing for a MIPS ELF file. */
13332 mips_elf_final_processing (void)
13334 /* Write out the register information. */
13335 if (mips_abi
!= N64_ABI
)
13339 s
.ri_gprmask
= mips_gprmask
;
13340 s
.ri_cprmask
[0] = mips_cprmask
[0];
13341 s
.ri_cprmask
[1] = mips_cprmask
[1];
13342 s
.ri_cprmask
[2] = mips_cprmask
[2];
13343 s
.ri_cprmask
[3] = mips_cprmask
[3];
13344 /* The gp_value field is set by the MIPS ELF backend. */
13346 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13347 ((Elf32_External_RegInfo
*)
13348 mips_regmask_frag
));
13352 Elf64_Internal_RegInfo s
;
13354 s
.ri_gprmask
= mips_gprmask
;
13356 s
.ri_cprmask
[0] = mips_cprmask
[0];
13357 s
.ri_cprmask
[1] = mips_cprmask
[1];
13358 s
.ri_cprmask
[2] = mips_cprmask
[2];
13359 s
.ri_cprmask
[3] = mips_cprmask
[3];
13360 /* The gp_value field is set by the MIPS ELF backend. */
13362 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13363 ((Elf64_External_RegInfo
*)
13364 mips_regmask_frag
));
13367 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13368 sort of BFD interface for this. */
13369 if (mips_any_noreorder
)
13370 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13371 if (mips_pic
!= NO_PIC
)
13373 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13374 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13377 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13379 /* Set MIPS ELF flags for ASEs. */
13380 if (file_ase_mips16
)
13381 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13382 #if 0 /* XXX FIXME */
13383 if (file_ase_mips3d
)
13384 elf_elfheader (stdoutput
)->e_flags
|= ???;
13387 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13389 /* Set the MIPS ELF ABI flags. */
13390 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13391 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13392 else if (mips_abi
== O64_ABI
)
13393 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13394 else if (mips_abi
== EABI_ABI
)
13396 if (!file_mips_gp32
)
13397 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13399 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13401 else if (mips_abi
== N32_ABI
)
13402 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13404 /* Nothing to do for N64_ABI. */
13406 if (mips_32bitmode
)
13407 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13410 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13412 typedef struct proc
{
13414 symbolS
*func_end_sym
;
13415 unsigned long reg_mask
;
13416 unsigned long reg_offset
;
13417 unsigned long fpreg_mask
;
13418 unsigned long fpreg_offset
;
13419 unsigned long frame_offset
;
13420 unsigned long frame_reg
;
13421 unsigned long pc_reg
;
13424 static procS cur_proc
;
13425 static procS
*cur_proc_ptr
;
13426 static int numprocs
;
13428 /* Fill in an rs_align_code fragment. */
13431 mips_handle_align (fragS
*fragp
)
13433 if (fragp
->fr_type
!= rs_align_code
)
13436 if (mips_opts
.mips16
)
13438 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13439 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13444 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13445 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13453 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13457 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13461 md_obj_begin (void)
13468 /* check for premature end, nesting errors, etc */
13470 as_warn (_("missing .end at end of assembly"));
13479 if (*input_line_pointer
== '-')
13481 ++input_line_pointer
;
13484 if (!ISDIGIT (*input_line_pointer
))
13485 as_bad (_("expected simple number"));
13486 if (input_line_pointer
[0] == '0')
13488 if (input_line_pointer
[1] == 'x')
13490 input_line_pointer
+= 2;
13491 while (ISXDIGIT (*input_line_pointer
))
13494 val
|= hex_value (*input_line_pointer
++);
13496 return negative
? -val
: val
;
13500 ++input_line_pointer
;
13501 while (ISDIGIT (*input_line_pointer
))
13504 val
|= *input_line_pointer
++ - '0';
13506 return negative
? -val
: val
;
13509 if (!ISDIGIT (*input_line_pointer
))
13511 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13512 *input_line_pointer
, *input_line_pointer
);
13513 as_warn (_("invalid number"));
13516 while (ISDIGIT (*input_line_pointer
))
13519 val
+= *input_line_pointer
++ - '0';
13521 return negative
? -val
: val
;
13524 /* The .file directive; just like the usual .file directive, but there
13525 is an initial number which is the ECOFF file index. In the non-ECOFF
13526 case .file implies DWARF-2. */
13529 s_mips_file (int x ATTRIBUTE_UNUSED
)
13531 static int first_file_directive
= 0;
13533 if (ECOFF_DEBUGGING
)
13542 filename
= dwarf2_directive_file (0);
13544 /* Versions of GCC up to 3.1 start files with a ".file"
13545 directive even for stabs output. Make sure that this
13546 ".file" is handled. Note that you need a version of GCC
13547 after 3.1 in order to support DWARF-2 on MIPS. */
13548 if (filename
!= NULL
&& ! first_file_directive
)
13550 (void) new_logical_line (filename
, -1);
13551 s_app_file_string (filename
, 0);
13553 first_file_directive
= 1;
13557 /* The .loc directive, implying DWARF-2. */
13560 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13562 if (!ECOFF_DEBUGGING
)
13563 dwarf2_directive_loc (0);
13566 /* The .end directive. */
13569 s_mips_end (int x ATTRIBUTE_UNUSED
)
13573 /* Following functions need their own .frame and .cprestore directives. */
13574 mips_frame_reg_valid
= 0;
13575 mips_cprestore_valid
= 0;
13577 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13580 demand_empty_rest_of_line ();
13585 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13586 as_warn (_(".end not in text section"));
13590 as_warn (_(".end directive without a preceding .ent directive."));
13591 demand_empty_rest_of_line ();
13597 assert (S_GET_NAME (p
));
13598 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13599 as_warn (_(".end symbol does not match .ent symbol."));
13601 if (debug_type
== DEBUG_STABS
)
13602 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13606 as_warn (_(".end directive missing or unknown symbol"));
13608 /* Create an expression to calculate the size of the function. */
13609 if (p
&& cur_proc_ptr
)
13611 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13612 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13615 exp
->X_op
= O_subtract
;
13616 exp
->X_add_symbol
= symbol_temp_new_now ();
13617 exp
->X_op_symbol
= p
;
13618 exp
->X_add_number
= 0;
13620 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13624 /* Generate a .pdr section. */
13625 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13628 segT saved_seg
= now_seg
;
13629 subsegT saved_subseg
= now_subseg
;
13634 dot
= frag_now_fix ();
13636 #ifdef md_flush_pending_output
13637 md_flush_pending_output ();
13641 subseg_set (pdr_seg
, 0);
13643 /* Write the symbol. */
13644 exp
.X_op
= O_symbol
;
13645 exp
.X_add_symbol
= p
;
13646 exp
.X_add_number
= 0;
13647 emit_expr (&exp
, 4);
13649 fragp
= frag_more (7 * 4);
13651 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13652 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13653 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13654 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13655 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13656 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13657 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13659 subseg_set (saved_seg
, saved_subseg
);
13661 #endif /* OBJ_ELF */
13663 cur_proc_ptr
= NULL
;
13666 /* The .aent and .ent directives. */
13669 s_mips_ent (int aent
)
13673 symbolP
= get_symbol ();
13674 if (*input_line_pointer
== ',')
13675 ++input_line_pointer
;
13676 SKIP_WHITESPACE ();
13677 if (ISDIGIT (*input_line_pointer
)
13678 || *input_line_pointer
== '-')
13681 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13682 as_warn (_(".ent or .aent not in text section."));
13684 if (!aent
&& cur_proc_ptr
)
13685 as_warn (_("missing .end"));
13689 /* This function needs its own .frame and .cprestore directives. */
13690 mips_frame_reg_valid
= 0;
13691 mips_cprestore_valid
= 0;
13693 cur_proc_ptr
= &cur_proc
;
13694 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13696 cur_proc_ptr
->func_sym
= symbolP
;
13698 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13702 if (debug_type
== DEBUG_STABS
)
13703 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13704 S_GET_NAME (symbolP
));
13707 demand_empty_rest_of_line ();
13710 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13711 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13712 s_mips_frame is used so that we can set the PDR information correctly.
13713 We can't use the ecoff routines because they make reference to the ecoff
13714 symbol table (in the mdebug section). */
13717 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13720 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13724 if (cur_proc_ptr
== (procS
*) NULL
)
13726 as_warn (_(".frame outside of .ent"));
13727 demand_empty_rest_of_line ();
13731 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13733 SKIP_WHITESPACE ();
13734 if (*input_line_pointer
++ != ','
13735 || get_absolute_expression_and_terminator (&val
) != ',')
13737 as_warn (_("Bad .frame directive"));
13738 --input_line_pointer
;
13739 demand_empty_rest_of_line ();
13743 cur_proc_ptr
->frame_offset
= val
;
13744 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13746 demand_empty_rest_of_line ();
13749 #endif /* OBJ_ELF */
13753 /* The .fmask and .mask directives. If the mdebug section is present
13754 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13755 embedded targets, s_mips_mask is used so that we can set the PDR
13756 information correctly. We can't use the ecoff routines because they
13757 make reference to the ecoff symbol table (in the mdebug section). */
13760 s_mips_mask (int reg_type
)
13763 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13767 if (cur_proc_ptr
== (procS
*) NULL
)
13769 as_warn (_(".mask/.fmask outside of .ent"));
13770 demand_empty_rest_of_line ();
13774 if (get_absolute_expression_and_terminator (&mask
) != ',')
13776 as_warn (_("Bad .mask/.fmask directive"));
13777 --input_line_pointer
;
13778 demand_empty_rest_of_line ();
13782 off
= get_absolute_expression ();
13784 if (reg_type
== 'F')
13786 cur_proc_ptr
->fpreg_mask
= mask
;
13787 cur_proc_ptr
->fpreg_offset
= off
;
13791 cur_proc_ptr
->reg_mask
= mask
;
13792 cur_proc_ptr
->reg_offset
= off
;
13795 demand_empty_rest_of_line ();
13798 #endif /* OBJ_ELF */
13799 s_ignore (reg_type
);
13802 /* A table describing all the processors gas knows about. Names are
13803 matched in the order listed.
13805 To ease comparison, please keep this table in the same order as
13806 gcc's mips_cpu_info_table[]. */
13807 static const struct mips_cpu_info mips_cpu_info_table
[] =
13809 /* Entries for generic ISAs */
13810 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13811 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13812 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13813 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13814 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13815 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13816 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13817 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13818 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13821 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13822 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13823 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13826 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13829 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13830 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13831 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13832 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13833 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13834 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13835 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13836 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13837 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13838 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13839 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13840 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13843 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13844 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13845 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13846 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13847 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13848 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13849 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13850 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13851 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13852 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13853 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13854 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13855 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13858 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13859 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13860 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13863 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13864 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13866 /* Broadcom SB-1 CPU core */
13867 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13874 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13875 with a final "000" replaced by "k". Ignore case.
13877 Note: this function is shared between GCC and GAS. */
13880 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13882 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13883 given
++, canonical
++;
13885 return ((*given
== 0 && *canonical
== 0)
13886 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13890 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13891 CPU name. We've traditionally allowed a lot of variation here.
13893 Note: this function is shared between GCC and GAS. */
13896 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13898 /* First see if the name matches exactly, or with a final "000"
13899 turned into "k". */
13900 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13903 /* If not, try comparing based on numerical designation alone.
13904 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13905 if (TOLOWER (*given
) == 'r')
13907 if (!ISDIGIT (*given
))
13910 /* Skip over some well-known prefixes in the canonical name,
13911 hoping to find a number there too. */
13912 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13914 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13916 else if (TOLOWER (canonical
[0]) == 'r')
13919 return mips_strict_matching_cpu_name_p (canonical
, given
);
13923 /* Parse an option that takes the name of a processor as its argument.
13924 OPTION is the name of the option and CPU_STRING is the argument.
13925 Return the corresponding processor enumeration if the CPU_STRING is
13926 recognized, otherwise report an error and return null.
13928 A similar function exists in GCC. */
13930 static const struct mips_cpu_info
*
13931 mips_parse_cpu (const char *option
, const char *cpu_string
)
13933 const struct mips_cpu_info
*p
;
13935 /* 'from-abi' selects the most compatible architecture for the given
13936 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13937 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13938 version. Look first at the -mgp options, if given, otherwise base
13939 the choice on MIPS_DEFAULT_64BIT.
13941 Treat NO_ABI like the EABIs. One reason to do this is that the
13942 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13943 architecture. This code picks MIPS I for 'mips' and MIPS III for
13944 'mips64', just as we did in the days before 'from-abi'. */
13945 if (strcasecmp (cpu_string
, "from-abi") == 0)
13947 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13948 return mips_cpu_info_from_isa (ISA_MIPS1
);
13950 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13951 return mips_cpu_info_from_isa (ISA_MIPS3
);
13953 if (file_mips_gp32
>= 0)
13954 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13956 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13961 /* 'default' has traditionally been a no-op. Probably not very useful. */
13962 if (strcasecmp (cpu_string
, "default") == 0)
13965 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13966 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13969 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13973 /* Return the canonical processor information for ISA (a member of the
13974 ISA_MIPS* enumeration). */
13976 static const struct mips_cpu_info
*
13977 mips_cpu_info_from_isa (int isa
)
13981 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13982 if (mips_cpu_info_table
[i
].is_isa
13983 && isa
== mips_cpu_info_table
[i
].isa
)
13984 return (&mips_cpu_info_table
[i
]);
13989 static const struct mips_cpu_info
*
13990 mips_cpu_info_from_arch (int arch
)
13994 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13995 if (arch
== mips_cpu_info_table
[i
].cpu
)
13996 return (&mips_cpu_info_table
[i
]);
14002 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14006 fprintf (stream
, "%24s", "");
14011 fprintf (stream
, ", ");
14015 if (*col_p
+ strlen (string
) > 72)
14017 fprintf (stream
, "\n%24s", "");
14021 fprintf (stream
, "%s", string
);
14022 *col_p
+= strlen (string
);
14028 md_show_usage (FILE *stream
)
14033 fprintf (stream
, _("\
14035 -EB generate big endian output\n\
14036 -EL generate little endian output\n\
14037 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14038 -G NUM allow referencing objects up to NUM bytes\n\
14039 implicitly with the gp register [default 8]\n"));
14040 fprintf (stream
, _("\
14041 -mips1 generate MIPS ISA I instructions\n\
14042 -mips2 generate MIPS ISA II instructions\n\
14043 -mips3 generate MIPS ISA III instructions\n\
14044 -mips4 generate MIPS ISA IV instructions\n\
14045 -mips5 generate MIPS ISA V instructions\n\
14046 -mips32 generate MIPS32 ISA instructions\n\
14047 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14048 -mips64 generate MIPS64 ISA instructions\n\
14049 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14050 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14054 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14055 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14056 show (stream
, "from-abi", &column
, &first
);
14057 fputc ('\n', stream
);
14059 fprintf (stream
, _("\
14060 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14061 -no-mCPU don't generate code specific to CPU.\n\
14062 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14066 show (stream
, "3900", &column
, &first
);
14067 show (stream
, "4010", &column
, &first
);
14068 show (stream
, "4100", &column
, &first
);
14069 show (stream
, "4650", &column
, &first
);
14070 fputc ('\n', stream
);
14072 fprintf (stream
, _("\
14073 -mips16 generate mips16 instructions\n\
14074 -no-mips16 do not generate mips16 instructions\n"));
14075 fprintf (stream
, _("\
14076 -mfix-vr4120 work around certain VR4120 errata\n\
14077 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14078 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14079 -O0 remove unneeded NOPs, do not swap branches\n\
14080 -O remove unneeded NOPs and swap branches\n\
14081 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14082 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14083 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14085 fprintf (stream
, _("\
14086 -KPIC, -call_shared generate SVR4 position independent code\n\
14087 -non_shared do not generate position independent code\n\
14088 -xgot assume a 32 bit GOT\n\
14089 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14090 -mabi=ABI create ABI conformant object file for:\n"));
14094 show (stream
, "32", &column
, &first
);
14095 show (stream
, "o64", &column
, &first
);
14096 show (stream
, "n32", &column
, &first
);
14097 show (stream
, "64", &column
, &first
);
14098 show (stream
, "eabi", &column
, &first
);
14100 fputc ('\n', stream
);
14102 fprintf (stream
, _("\
14103 -32 create o32 ABI object file (default)\n\
14104 -n32 create n32 ABI object file\n\
14105 -64 create 64 ABI object file\n"));
14110 mips_dwarf2_format (void)
14112 if (mips_abi
== N64_ABI
)
14115 return dwarf2_format_64bit_irix
;
14117 return dwarf2_format_64bit
;
14121 return dwarf2_format_32bit
;
14125 mips_dwarf2_addr_size (void)
14127 if (mips_abi
== N64_ABI
)