1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
41 #endif /* NO_VARARGS */
42 #endif /* NO_STDARG */
44 #include "opcode/mips.h"
49 static char *mips_regmask_frag
;
53 #define PIC_CALL_REG 25
59 /* Decide whether to do GP reference optimizations based on the object
69 /* The default target format to use. */
71 #ifdef TARGET_BYTES_BIG_ENDIAN
72 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
74 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
78 #ifdef TARGET_BYTES_BIG_ENDIAN
79 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
81 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
83 #endif /* OBJ_ECOFF */
85 #ifdef TARGET_BYTES_BIG_ENDIAN
86 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
88 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
92 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
94 /* The name of the readonly data section. */
96 #define RDATA_SECTION_NAME ".data"
99 #define RDATA_SECTION_NAME ".rdata"
102 #define RDATA_SECTION_NAME ".rodata"
105 /* These variables are filled in with the masks of registers used.
106 The object format code reads them and puts them in the appropriate
108 unsigned long mips_gprmask
;
109 unsigned long mips_cprmask
[4];
111 /* MIPS ISA (Instruction Set Architecture) level (may be changed
112 temporarily using .set mipsN). */
113 static int mips_isa
= -1;
115 /* MIPS ISA we are using for this output file. */
116 static int file_mips_isa
;
118 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
119 static int mips_cpu
= -1;
121 /* MIPS PIC level. */
125 /* Do not generate PIC code. */
128 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
129 not sure what it is supposed to do. */
132 /* Generate PIC code as in the SVR4 MIPS ABI. */
135 /* Generate PIC code without using a global offset table: the data
136 segment has a maximum size of 64K, all data references are off
137 the $gp register, and all text references are PC relative. This
138 is used on some embedded systems. */
142 static enum mips_pic_level mips_pic
;
144 /* 1 if trap instructions should used for overflow rather than break
146 static int mips_trap
;
148 static int mips_warn_about_macros
;
149 static int mips_noreorder
;
150 static int mips_any_noreorder
;
151 static int mips_nomove
;
152 static int mips_noat
;
153 static int mips_nobopt
;
156 /* The size of the small data section. */
157 static int g_switch_value
= 8;
158 /* Whether the -G option was used. */
159 static int g_switch_seen
= 0;
165 /* handle of the OPCODE hash table */
166 static struct hash_control
*op_hash
= NULL
;
168 /* This array holds the chars that always start a comment. If the
169 pre-processor is disabled, these aren't very useful */
170 const char comment_chars
[] = "#";
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that C style comments are always supported. */
179 const char line_comment_chars
[] = "#";
181 /* This array holds machine specific line separator characters. */
182 const char line_separator_chars
[] = "";
184 /* Chars that can be used to separate mant from exp in floating point nums */
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant */
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c . Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here.
197 static char *insn_error
;
199 static int byte_order
= BYTE_ORDER
;
201 static int auto_align
= 1;
203 /* Symbol labelling the current insn. */
204 static symbolS
*insn_label
;
206 /* When outputting SVR4 PIC code, the assembler needs to know the
207 offset in the stack frame from which to restore the $gp register.
208 This is set by the .cprestore pseudo-op, and saved in this
210 static offsetT mips_cprestore_offset
= -1;
212 /* This is the register which holds the stack frame, as set by the
213 .frame pseudo-op. This is needed to implement .cprestore. */
214 static int mips_frame_reg
= SP
;
216 /* To output NOP instructions correctly, we need to keep information
217 about the previous two instructions. */
219 /* Whether we are optimizing. The default value of 2 means to remove
220 unneeded NOPs and swap branch instructions when possible. A value
221 of 1 means to not swap branches. A value of 0 means to always
223 static int mips_optimize
= 2;
225 /* The previous instruction. */
226 static struct mips_cl_insn prev_insn
;
228 /* The instruction before prev_insn. */
229 static struct mips_cl_insn prev_prev_insn
;
231 /* If we don't want information for prev_insn or prev_prev_insn, we
232 point the insn_mo field at this dummy integer. */
233 static const struct mips_opcode dummy_opcode
= { 0 };
235 /* Non-zero if prev_insn is valid. */
236 static int prev_insn_valid
;
238 /* The frag for the previous instruction. */
239 static struct frag
*prev_insn_frag
;
241 /* The offset into prev_insn_frag for the previous instruction. */
242 static long prev_insn_where
;
244 /* The reloc for the previous instruction, if any. */
245 static fixS
*prev_insn_fixp
;
247 /* Non-zero if the previous instruction was in a delay slot. */
248 static int prev_insn_is_delay_slot
;
250 /* Non-zero if the previous instruction was in a .set noreorder. */
251 static int prev_insn_unreordered
;
253 /* Non-zero if the previous previous instruction was in a .set
255 static int prev_prev_insn_unreordered
;
257 /* Since the MIPS does not have multiple forms of PC relative
258 instructions, we do not have to do relaxing as is done on other
259 platforms. However, we do have to handle GP relative addressing
260 correctly, which turns out to be a similar problem.
262 Every macro that refers to a symbol can occur in (at least) two
263 forms, one with GP relative addressing and one without. For
264 example, loading a global variable into a register generally uses
265 a macro instruction like this:
267 If i can be addressed off the GP register (this is true if it is in
268 the .sbss or .sdata section, or if it is known to be smaller than
269 the -G argument) this will generate the following instruction:
271 This instruction will use a GPREL reloc. If i can not be addressed
272 off the GP register, the following instruction sequence will be used:
275 In this case the first instruction will have a HI16 reloc, and the
276 second reloc will have a LO16 reloc. Both relocs will be against
279 The issue here is that we may not know whether i is GP addressable
280 until after we see the instruction that uses it. Therefore, we
281 want to be able to choose the final instruction sequence only at
282 the end of the assembly. This is similar to the way other
283 platforms choose the size of a PC relative instruction only at the
286 When generating position independent code we do not use GP
287 addressing in quite the same way, but the issue still arises as
288 external symbols and local symbols must be handled differently.
290 We handle these issues by actually generating both possible
291 instruction sequences. The longer one is put in a frag_var with
292 type rs_machine_dependent. We encode what to do with the frag in
293 the subtype field. We encode (1) the number of existing bytes to
294 replace, (2) the number of new bytes to use, (3) the offset from
295 the start of the existing bytes to the first reloc we must generate
296 (that is, the offset is applied from the start of the existing
297 bytes after they are replaced by the new bytes, if any), (4) the
298 offset from the start of the existing bytes to the second reloc,
299 (5) whether a third reloc is needed (the third reloc is always four
300 bytes after the second reloc), and (6) whether to warn if this
301 variant is used (this is sometimes needed if .set nomacro or .set
302 noat is in effect). All these numbers are reasonably small.
304 Generating two instruction sequences must be handled carefully to
305 ensure that delay slots are handled correctly. Fortunately, there
306 are a limited number of cases. When the second instruction
307 sequence is generated, append_insn is directed to maintain the
308 existing delay slot information, so it continues to apply to any
309 code after the second instruction sequence. This means that the
310 second instruction sequence must not impose any requirements not
311 required by the first instruction sequence.
313 These variant frags are then handled in functions called by the
314 machine independent code. md_estimate_size_before_relax returns
315 the final size of the frag. md_convert_frag sets up the final form
316 of the frag. tc_gen_reloc adjust the first reloc and adds a second
318 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
322 | (((reloc1) + 64) << 9) \
323 | (((reloc2) + 64) << 2) \
324 | ((reloc3) ? (1 << 1) : 0) \
326 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
327 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
328 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
329 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
330 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
331 #define RELAX_WARN(i) ((i) & 1)
333 /* Prototypes for static functions. */
336 #define internalError() \
337 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
339 #define internalError() as_fatal ("MIPS internal Error");
342 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
343 unsigned int reg
, int fpr
));
344 static void append_insn
PARAMS ((char *place
,
345 struct mips_cl_insn
* ip
,
347 bfd_reloc_code_real_type r
));
348 static void mips_no_prev_insn
PARAMS ((void));
349 static void mips_emit_delays
PARAMS ((void));
350 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
351 const char *name
, const char *fmt
,
353 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
354 expressionS
* ep
, int regnum
));
355 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
356 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
358 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
359 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
360 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
361 #ifdef LOSING_COMPILER
362 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
364 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
365 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
366 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
367 static symbolS
*get_symbol
PARAMS ((void));
368 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
369 static void s_align
PARAMS ((int));
370 static void s_stringer
PARAMS ((int));
371 static void s_change_sec
PARAMS ((int));
372 static void s_cons
PARAMS ((int));
373 static void s_err
PARAMS ((int));
374 static void s_extern
PARAMS ((int));
375 static void s_float_cons
PARAMS ((int));
376 static void s_mips_globl
PARAMS ((int));
377 static void s_option
PARAMS ((int));
378 static void s_mipsset
PARAMS ((int));
379 static void s_mips_space
PARAMS ((int));
380 static void s_abicalls
PARAMS ((int));
381 static void s_cpload
PARAMS ((int));
382 static void s_cprestore
PARAMS ((int));
383 static void s_gpword
PARAMS ((int));
384 static void s_cpadd
PARAMS ((int));
385 #ifndef ECOFF_DEBUGGING
386 static void md_obj_begin
PARAMS ((void));
387 static void md_obj_end
PARAMS ((void));
388 static long get_number
PARAMS ((void));
389 static void s_ent
PARAMS ((int));
390 static void s_mipsend
PARAMS ((int));
391 static void s_file
PARAMS ((int));
393 static void s_frame
PARAMS ((int));
394 static void s_loc
PARAMS ((int));
395 static void s_mask
PARAMS ((char));
399 static void s_elf_section
PARAMS ((int));
404 The following pseudo-ops from the Kane and Heinrich MIPS book
405 should be defined here, but are currently unsupported: .alias,
406 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
408 The following pseudo-ops from the Kane and Heinrich MIPS book are
409 specific to the type of debugging information being generated, and
410 should be defined by the object format: .aent, .begin, .bend,
411 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
414 The following pseudo-ops from the Kane and Heinrich MIPS book are
415 not MIPS CPU specific, but are also not specific to the object file
416 format. This file is probably the best place to define them, but
417 they are not currently supported: .asm0, .endr, .lab, .repeat,
418 .struct, .weakext. */
420 const pseudo_typeS md_pseudo_table
[] =
422 /* MIPS specific pseudo-ops. */
423 {"option", s_option
, 0},
424 {"set", s_mipsset
, 0},
425 {"rdata", s_change_sec
, 'r'},
426 {"sdata", s_change_sec
, 's'},
427 {"livereg", s_ignore
, 0},
428 { "abicalls", s_abicalls
, 0},
429 { "cpload", s_cpload
, 0},
430 { "cprestore", s_cprestore
, 0},
431 { "gpword", s_gpword
, 0},
432 { "cpadd", s_cpadd
, 0},
434 /* Relatively generic pseudo-ops that happen to be used on MIPS
436 {"asciiz", s_stringer
, 1},
437 {"bss", s_change_sec
, 'b'},
440 {"dword", s_cons
, 3},
442 /* These pseudo-ops are defined in read.c, but must be overridden
443 here for one reason or another. */
444 {"align", s_align
, 0},
445 {"ascii", s_stringer
, 0},
446 {"asciz", s_stringer
, 1},
448 {"data", s_change_sec
, 'd'},
449 {"double", s_float_cons
, 'd'},
450 {"extern", s_extern
, 0},
451 {"float", s_float_cons
, 'f'},
452 {"globl", s_mips_globl
, 0},
453 {"global", s_mips_globl
, 0},
454 {"hword", s_cons
, 1},
459 {"short", s_cons
, 1},
460 {"single", s_float_cons
, 'f'},
461 {"space", s_mips_space
, 0},
462 {"text", s_change_sec
, 't'},
465 #ifndef ECOFF_DEBUGGING
466 /* These pseudo-ops should be defined by the object file format.
467 However, a.out doesn't support them, so we have versions here. */
469 {"bgnb", s_ignore
, 0},
470 {"end", s_mipsend
, 0},
471 {"endb", s_ignore
, 0},
474 {"fmask", s_ignore
, 'F'},
475 {"frame", s_ignore
, 0},
476 {"loc", s_ignore
, 0},
477 {"mask", s_ignore
, 'R'},
478 {"verstamp", s_ignore
, 0},
482 /* We need to tweak the ELF ".section" pseudo-op a bit. */
483 {"section", s_elf_section
, 0},
490 const relax_typeS md_relax_table
[] =
495 static char *expr_end
;
497 static expressionS imm_expr
;
498 static expressionS offset_expr
;
499 static bfd_reloc_code_real_type imm_reloc
;
500 static bfd_reloc_code_real_type offset_reloc
;
502 /* FIXME: This should be handled in a different way. */
503 extern int target_big_endian
;
506 * This function is called once, at assembler startup time. It should
507 * set up all the tables, etc. that the MD part of the assembler will need.
513 register const char *retval
= NULL
;
514 register unsigned int i
= 0;
522 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
524 a
= xmalloc (sizeof TARGET_CPU
);
525 strcpy (a
, TARGET_CPU
);
526 a
[(sizeof TARGET_CPU
) - 3] = '\0';
530 if (strcmp (cpu
, "mips") == 0)
536 else if (strcmp (cpu
, "r6000") == 0
537 || strcmp (cpu
, "mips2") == 0)
543 else if (strcmp (cpu
, "mips64") == 0
544 || strcmp (cpu
, "r4000") == 0
545 || strcmp (cpu
, "mips3") == 0)
551 else if (strcmp (cpu
, "r4400") == 0)
557 else if (strcmp (cpu
, "mips64orion") == 0
558 || strcmp (cpu
, "r4600") == 0)
575 if (mips_isa
< 2 && mips_trap
)
576 as_bad ("trap exception not supported at ISA 1");
581 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
584 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
587 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
591 as_warn ("Could not set architecture and machine");
593 file_mips_isa
= mips_isa
;
595 op_hash
= hash_new ();
597 for (i
= 0; i
< NUMOPCODES
;)
599 const char *name
= mips_opcodes
[i
].name
;
601 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
604 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
605 mips_opcodes
[i
].name
, retval
);
606 as_fatal ("Broken assembler. No assembly attempted.");
610 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
611 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
612 != mips_opcodes
[i
].match
))
614 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
615 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
616 as_fatal ("Broken assembler. No assembly attempted.");
620 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
623 mips_no_prev_insn ();
631 /* set the default alignment for the text section (2**2) */
632 record_alignment (text_section
, 2);
634 /* FIXME: This should be handled in a different way. */
635 target_big_endian
= byte_order
== BIG_ENDIAN
;
638 bfd_set_gp_size (stdoutput
, g_switch_value
);
642 /* Sections must be aligned to 16 byte boundaries. */
643 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
644 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
645 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
647 /* Create a .reginfo section for register masks and a .mdebug
648 section for debugging information. */
656 sec
= subseg_new (".reginfo", (subsegT
) 0);
658 /* The ABI says this section should be loaded so that the running
659 program can access it. */
660 (void) bfd_set_section_flags (stdoutput
, sec
,
661 (SEC_ALLOC
| SEC_LOAD
662 | SEC_READONLY
| SEC_DATA
));
663 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
665 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
667 #ifdef ECOFF_DEBUGGING
668 sec
= subseg_new (".mdebug", (subsegT
) 0);
669 (void) bfd_set_section_flags (stdoutput
, sec
,
670 SEC_HAS_CONTENTS
| SEC_READONLY
);
671 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
674 subseg_set (seg
, subseg
);
678 #ifndef ECOFF_DEBUGGING
686 #ifndef ECOFF_DEBUGGING
695 struct mips_cl_insn insn
;
697 imm_expr
.X_op
= O_absent
;
698 offset_expr
.X_op
= O_absent
;
700 mips_ip (str
, &insn
);
703 as_bad ("%s `%s'", insn_error
, str
);
706 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
712 if (imm_expr
.X_op
!= O_absent
)
713 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
714 else if (offset_expr
.X_op
!= O_absent
)
715 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
717 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
721 /* See whether instruction IP reads register REG. If FPR is non-zero,
722 REG is a floating point register. */
725 insn_uses_reg (ip
, reg
, fpr
)
726 struct mips_cl_insn
*ip
;
730 /* Don't report on general register 0, since it never changes. */
731 if (! fpr
&& reg
== 0)
736 /* If we are called with either $f0 or $f1, we must check $f0.
737 This is not optimal, because it will introduce an unnecessary
738 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
739 need to distinguish reading both $f0 and $f1 or just one of
740 them. Note that we don't have to check the other way,
741 because there is no instruction that sets both $f0 and $f1
742 and requires a delay. */
743 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
744 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
745 == (reg
&~ (unsigned) 1)))
747 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
748 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
749 == (reg
&~ (unsigned) 1)))
754 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
755 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
757 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
758 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
765 /* Output an instruction. PLACE is where to put the instruction; if
766 it is NULL, this uses frag_more to get room. IP is the instruction
767 information. ADDRESS_EXPR is an operand of the instruction to be
768 used with RELOC_TYPE. */
771 append_insn (place
, ip
, address_expr
, reloc_type
)
773 struct mips_cl_insn
*ip
;
774 expressionS
*address_expr
;
775 bfd_reloc_code_real_type reloc_type
;
777 register unsigned long prev_pinfo
, pinfo
;
782 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
783 pinfo
= ip
->insn_mo
->pinfo
;
785 if (place
== NULL
&& ! mips_noreorder
)
787 /* If the previous insn required any delay slots, see if we need
788 to insert a NOP or two. There are eight kinds of possible
789 hazards, of which an instruction can have at most one type.
790 (1) a load from memory delay
791 (2) a load from a coprocessor delay
792 (3) an unconditional branch delay
793 (4) a conditional branch delay
794 (5) a move to coprocessor register delay
795 (6) a load coprocessor register from memory delay
796 (7) a coprocessor condition code delay
797 (8) a HI/LO special register delay
799 There are a lot of optimizations we could do that we don't.
800 In particular, we do not, in general, reorder instructions.
801 If you use gcc with optimization, it will reorder
802 instructions and generally do much more optimization then we
803 do here; repeating all that work in the assembler would only
804 benefit hand written assembly code, and does not seem worth
807 /* This is how a NOP is emitted. */
808 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
810 /* The previous insn might require a delay slot, depending upon
811 the contents of the current insn. */
812 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
814 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
816 /* A load from a coprocessor or from memory. All load
817 delays delay the use of general register rt for one
818 instruction on the r3000. The r6000 and r4000 use
820 know (prev_pinfo
& INSN_WRITE_GPR_T
);
821 if (mips_optimize
== 0
822 || insn_uses_reg (ip
,
823 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
828 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
830 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
832 /* A generic coprocessor delay. The previous instruction
833 modified a coprocessor general or control register. If
834 it modified a control register, we need to avoid any
835 coprocessor instruction (this is probably not always
836 required, but it sometimes is). If it modified a general
837 register, we avoid using that register.
839 On the r6000 and r4000 loading a coprocessor register
840 from memory is interlocked, and does not require a delay.
842 This case is not handled very well. There is no special
843 knowledge of CP0 handling, and the coprocessors other
844 than the floating point unit are not distinguished at
846 if (prev_pinfo
& INSN_WRITE_FPR_T
)
848 if (mips_optimize
== 0
849 || insn_uses_reg (ip
,
850 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
855 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
857 if (mips_optimize
== 0
858 || insn_uses_reg (ip
,
859 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
866 /* We don't know exactly what the previous instruction
867 does. If the current instruction uses a coprocessor
868 register, we must insert a NOP. If previous
869 instruction may set the condition codes, and the
870 current instruction uses them, we must insert two
872 if (mips_optimize
== 0
873 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
874 && (pinfo
& INSN_READ_COND_CODE
)))
876 else if (pinfo
& INSN_COP
)
880 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
882 /* The previous instruction sets the coprocessor condition
883 codes, but does not require a general coprocessor delay
884 (this means it is a floating point comparison
885 instruction). If this instruction uses the condition
886 codes, we need to insert a single NOP. */
887 if (mips_optimize
== 0
888 || (pinfo
& INSN_READ_COND_CODE
))
891 else if (prev_pinfo
& INSN_READ_LO
)
893 /* The previous instruction reads the LO register; if the
894 current instruction writes to the LO register, we must
896 if (mips_optimize
== 0
897 || (pinfo
& INSN_WRITE_LO
))
900 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
902 /* The previous instruction reads the HI register; if the
903 current instruction writes to the HI register, we must
905 if (mips_optimize
== 0
906 || (pinfo
& INSN_WRITE_HI
))
910 /* There are two cases which require two intervening
911 instructions: 1) setting the condition codes using a move to
912 coprocessor instruction which requires a general coprocessor
913 delay and then reading the condition codes 2) reading the HI
914 or LO register and then writing to it. If we are not already
915 emitting a NOP instruction, we must check for these cases
916 compared to the instruction previous to the previous
919 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
920 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
921 && (pinfo
& INSN_READ_COND_CODE
))
922 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
923 && (pinfo
& INSN_WRITE_LO
))
924 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
925 && (pinfo
& INSN_WRITE_HI
))))
928 /* If we are being given a nop instruction, don't bother with
929 one of the nops we would otherwise output. This will only
930 happen when a nop instruction is used with mips_optimize set
932 if (nops
> 0 && ip
->insn_opcode
== 0)
935 /* Now emit the right number of NOP instructions. */
940 for (i
= 0; i
< nops
; i
++)
943 listing_prev_line ();
944 if (insn_label
!= NULL
)
946 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
947 insn_label
->sy_frag
= frag_now
;
948 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
958 if (address_expr
!= NULL
)
960 if (address_expr
->X_op
== O_constant
)
965 ip
->insn_opcode
|= address_expr
->X_add_number
;
969 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
972 case BFD_RELOC_MIPS_JMP
:
973 case BFD_RELOC_16_PCREL_S2
:
982 assert (reloc_type
!= BFD_RELOC_UNUSED
);
984 /* Don't generate a reloc if we are writing into a variant
987 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
989 reloc_type
== BFD_RELOC_16_PCREL_S2
,
994 md_number_to_chars (f
, ip
->insn_opcode
, 4);
996 /* Update the register mask information. */
997 if (pinfo
& INSN_WRITE_GPR_D
)
998 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
999 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1000 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1001 if (pinfo
& INSN_READ_GPR_S
)
1002 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1003 if (pinfo
& INSN_WRITE_GPR_31
)
1004 mips_gprmask
|= 1 << 31;
1005 if (pinfo
& INSN_WRITE_FPR_D
)
1006 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1007 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1008 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1009 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1010 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1011 if (pinfo
& INSN_COP
)
1013 /* We don't keep enough information to sort these cases out. */
1015 /* Never set the bit for $0, which is always zero. */
1016 mips_gprmask
&=~ 1 << 0;
1018 if (place
== NULL
&& ! mips_noreorder
)
1020 /* Filling the branch delay slot is more complex. We try to
1021 switch the branch with the previous instruction, which we can
1022 do if the previous instruction does not set up a condition
1023 that the branch tests and if the branch is not itself the
1024 target of any branch. */
1025 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1026 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1028 if (mips_optimize
< 2
1029 /* If we have seen .set volatile or .set nomove, don't
1032 /* If we had to emit any NOP instructions, then we
1033 already know we can not swap. */
1035 /* If we don't even know the previous insn, we can not
1037 || ! prev_insn_valid
1038 /* If the previous insn is already in a branch delay
1039 slot, then we can not swap. */
1040 || prev_insn_is_delay_slot
1041 /* If the previous previous insn was in a .set
1042 noreorder, we can't swap. Actually, the MIPS
1043 assembler will swap in this situation. However, gcc
1044 configured -with-gnu-as will generate code like
1050 in which we can not swap the bne and INSN. If gcc is
1051 not configured -with-gnu-as, it does not output the
1052 .set pseudo-ops. We don't have to check
1053 prev_insn_unreordered, because prev_insn_valid will
1054 be 0 in that case. We don't want to use
1055 prev_prev_insn_valid, because we do want to be able
1056 to swap at the start of a function. */
1057 || prev_prev_insn_unreordered
1058 /* If the branch is itself the target of a branch, we
1059 can not swap. We cheat on this; all we check for is
1060 whether there is a label on this instruction. If
1061 there are any branches to anything other than a
1062 label, users must use .set noreorder. */
1063 || insn_label
!= NULL
1064 /* If the previous instruction is in a variant frag, we
1065 can not do the swap. */
1066 || prev_insn_frag
->fr_type
== rs_machine_dependent
1067 /* If the branch reads the condition codes, we don't
1068 even try to swap, because in the sequence
1073 we can not swap, and I don't feel like handling that
1075 || (pinfo
& INSN_READ_COND_CODE
)
1076 /* We can not swap with an instruction that requires a
1077 delay slot, becase the target of the branch might
1078 interfere with that instruction. */
1080 & (INSN_LOAD_COPROC_DELAY
1081 | INSN_COPROC_MOVE_DELAY
1082 | INSN_WRITE_COND_CODE
1087 & (INSN_LOAD_MEMORY_DELAY
1088 | INSN_COPROC_MEMORY_DELAY
)))
1089 /* We can not swap with a branch instruction. */
1091 & (INSN_UNCOND_BRANCH_DELAY
1092 | INSN_COND_BRANCH_DELAY
1093 | INSN_COND_BRANCH_LIKELY
))
1094 /* We do not swap with a trap instruction, since it
1095 complicates trap handlers to have the trap
1096 instruction be in a delay slot. */
1097 || (prev_pinfo
& INSN_TRAP
)
1098 /* If the branch reads a register that the previous
1099 instruction sets, we can not swap. */
1100 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1101 && insn_uses_reg (ip
,
1102 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1105 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1106 && insn_uses_reg (ip
,
1107 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1110 /* If the branch writes a register that the previous
1111 instruction sets, we can not swap (we know that
1112 branches write only to RD or to $31). */
1113 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1114 && (((pinfo
& INSN_WRITE_GPR_D
)
1115 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1116 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1117 || ((pinfo
& INSN_WRITE_GPR_31
)
1118 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1121 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1122 && (((pinfo
& INSN_WRITE_GPR_D
)
1123 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1124 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1125 || ((pinfo
& INSN_WRITE_GPR_31
)
1126 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1129 /* If the branch writes a register that the previous
1130 instruction reads, we can not swap (we know that
1131 branches only write to RD or to $31). */
1132 || ((pinfo
& INSN_WRITE_GPR_D
)
1133 && insn_uses_reg (&prev_insn
,
1134 ((ip
->insn_opcode
>> OP_SH_RD
)
1137 || ((pinfo
& INSN_WRITE_GPR_31
)
1138 && insn_uses_reg (&prev_insn
, 31, 0))
1139 /* If we are generating embedded PIC code, the branch
1140 might be expanded into a sequence which uses $at, so
1141 we can't swap with an instruction which reads it. */
1142 || (mips_pic
== EMBEDDED_PIC
1143 && insn_uses_reg (&prev_insn
, AT
, 0))
1144 /* If the previous previous instruction has a load
1145 delay, and sets a register that the branch reads, we
1147 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1149 && (prev_prev_insn
.insn_mo
->pinfo
1150 & INSN_LOAD_MEMORY_DELAY
)))
1151 && insn_uses_reg (ip
,
1152 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1156 /* We could do even better for unconditional branches to
1157 portions of this object file; we could pick up the
1158 instruction at the destination, put it in the delay
1159 slot, and bump the destination address. */
1161 /* Update the previous insn information. */
1162 prev_prev_insn
= *ip
;
1163 prev_insn
.insn_mo
= &dummy_opcode
;
1170 /* It looks like we can actually do the swap. */
1171 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1172 memcpy (temp
, prev_f
, 4);
1173 memcpy (prev_f
, f
, 4);
1174 memcpy (f
, temp
, 4);
1177 prev_insn_fixp
->fx_frag
= frag_now
;
1178 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1182 fixp
->fx_frag
= prev_insn_frag
;
1183 fixp
->fx_where
= prev_insn_where
;
1185 /* Update the previous insn information; leave prev_insn
1187 prev_prev_insn
= *ip
;
1189 prev_insn_is_delay_slot
= 1;
1191 /* If that was an unconditional branch, forget the previous
1192 insn information. */
1193 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1195 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1196 prev_insn
.insn_mo
= &dummy_opcode
;
1199 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1201 /* We don't yet optimize a branch likely. What we should do
1202 is look at the target, copy the instruction found there
1203 into the delay slot, and increment the branch to jump to
1204 the next instruction. */
1206 /* Update the previous insn information. */
1207 prev_prev_insn
= *ip
;
1208 prev_insn
.insn_mo
= &dummy_opcode
;
1212 /* Update the previous insn information. */
1214 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1216 prev_prev_insn
= prev_insn
;
1219 /* Any time we see a branch, we always fill the delay slot
1220 immediately; since this insn is not a branch, we know it
1221 is not in a delay slot. */
1222 prev_insn_is_delay_slot
= 0;
1225 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1226 prev_insn_unreordered
= 0;
1227 prev_insn_frag
= frag_now
;
1228 prev_insn_where
= f
- frag_now
->fr_literal
;
1229 prev_insn_fixp
= fixp
;
1230 prev_insn_valid
= 1;
1233 /* We just output an insn, so the next one doesn't have a label. */
1237 /* This function forgets that there was any previous instruction or
1241 mips_no_prev_insn ()
1243 prev_insn
.insn_mo
= &dummy_opcode
;
1244 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1245 prev_insn_valid
= 0;
1246 prev_insn_is_delay_slot
= 0;
1247 prev_insn_unreordered
= 0;
1248 prev_prev_insn_unreordered
= 0;
1252 /* This function must be called whenever we turn on noreorder or emit
1253 something other than instructions. It inserts any NOPS which might
1254 be needed by the previous instruction, and clears the information
1255 kept for the previous instructions. */
1260 if (! mips_noreorder
)
1265 if ((prev_insn
.insn_mo
->pinfo
1266 & (INSN_LOAD_COPROC_DELAY
1267 | INSN_COPROC_MOVE_DELAY
1268 | INSN_WRITE_COND_CODE
1272 && (prev_insn
.insn_mo
->pinfo
1273 & (INSN_LOAD_MEMORY_DELAY
1274 | INSN_COPROC_MEMORY_DELAY
))))
1277 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1278 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1279 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1282 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1283 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1284 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1289 if (insn_label
!= NULL
)
1291 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1292 insn_label
->sy_frag
= frag_now
;
1293 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1298 mips_no_prev_insn ();
1301 /* Build an instruction created by a macro expansion. This is passed
1302 a pointer to the count of instructions created so far, an
1303 expression, the name of the instruction to build, an operand format
1304 string, and corresponding arguments. */
1308 macro_build (char *place
,
1314 #else /* ! defined (NO_STDARG) */
1316 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1323 #endif /* ! defined (NO_STDARG) */
1325 struct mips_cl_insn insn
;
1326 bfd_reloc_code_real_type r
;
1330 va_start (args
, fmt
);
1336 * If the macro is about to expand into a second instruction,
1337 * print a warning if needed. We need to pass ip as a parameter
1338 * to generate a better warning message here...
1340 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1341 as_warn ("Macro instruction expanded into multiple instructions");
1344 *counter
+= 1; /* bump instruction counter */
1346 r
= BFD_RELOC_UNUSED
;
1347 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1348 assert (insn
.insn_mo
);
1349 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1351 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1352 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1355 assert (insn
.insn_mo
->name
);
1356 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1358 insn
.insn_opcode
= insn
.insn_mo
->match
;
1374 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1380 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1385 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1390 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1397 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1401 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1405 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1412 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1418 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1419 assert (r
== BFD_RELOC_MIPS_GPREL
1420 || r
== BFD_RELOC_MIPS_LITERAL
1421 || r
== BFD_RELOC_LO16
1422 || r
== BFD_RELOC_MIPS_GOT16
1423 || r
== BFD_RELOC_MIPS_CALL16
1424 || (ep
->X_op
== O_subtract
1425 && now_seg
== text_section
1426 && r
== BFD_RELOC_PCREL_LO16
));
1430 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1432 && (ep
->X_op
== O_constant
1433 || (ep
->X_op
== O_symbol
1434 && (r
== BFD_RELOC_HI16_S
1435 || r
== BFD_RELOC_HI16
))
1436 || (ep
->X_op
== O_subtract
1437 && now_seg
== text_section
1438 && r
== BFD_RELOC_PCREL_HI16_S
)));
1439 if (ep
->X_op
== O_constant
)
1441 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1443 r
= BFD_RELOC_UNUSED
;
1448 assert (ep
!= NULL
);
1450 * This allows macro() to pass an immediate expression for
1451 * creating short branches without creating a symbol.
1452 * Note that the expression still might come from the assembly
1453 * input, in which case the value is not checked for range nor
1454 * is a relocation entry generated (yuck).
1456 if (ep
->X_op
== O_constant
)
1458 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1462 r
= BFD_RELOC_16_PCREL_S2
;
1466 assert (ep
!= NULL
);
1467 r
= BFD_RELOC_MIPS_JMP
;
1476 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1478 append_insn (place
, &insn
, ep
, r
);
1482 * Generate a "lui" instruction.
1485 macro_build_lui (place
, counter
, ep
, regnum
)
1491 expressionS high_expr
;
1492 struct mips_cl_insn insn
;
1493 bfd_reloc_code_real_type r
;
1494 CONST
char *name
= "lui";
1495 CONST
char *fmt
= "t,u";
1501 high_expr
.X_op
= O_constant
;
1502 high_expr
.X_add_number
= 0;
1505 if (high_expr
.X_op
== O_constant
)
1507 /* we can compute the instruction now without a relocation entry */
1508 if (high_expr
.X_add_number
& 0x8000)
1509 high_expr
.X_add_number
+= 0x10000;
1510 high_expr
.X_add_number
=
1511 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1512 r
= BFD_RELOC_UNUSED
;
1516 assert (ep
->X_op
== O_symbol
);
1517 /* _gp_disp is a special case, used from s_cpload. */
1518 assert (mips_pic
== NO_PIC
1519 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1520 r
= BFD_RELOC_HI16_S
;
1524 * If the macro is about to expand into a second instruction,
1525 * print a warning if needed. We need to pass ip as a parameter
1526 * to generate a better warning message here...
1528 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1529 as_warn ("Macro instruction expanded into multiple instructions");
1532 *counter
+= 1; /* bump instruction counter */
1534 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1535 assert (insn
.insn_mo
);
1536 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1537 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1539 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1540 if (r
== BFD_RELOC_UNUSED
)
1542 insn
.insn_opcode
|= high_expr
.X_add_number
;
1543 append_insn (place
, &insn
, NULL
, r
);
1546 append_insn (place
, &insn
, &high_expr
, r
);
1550 * Generates code to set the $at register to true (one)
1551 * if reg is less than the immediate expression.
1554 set_at (counter
, reg
, unsignedp
)
1559 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1560 macro_build ((char *) NULL
, counter
, &imm_expr
,
1561 unsignedp
? "sltiu" : "slti",
1562 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1565 load_register (counter
, AT
, &imm_expr
);
1566 macro_build ((char *) NULL
, counter
, NULL
,
1567 unsignedp
? "sltu" : "slt",
1568 "d,v,t", AT
, reg
, AT
);
1572 /* Warn if an expression is not a constant. */
1575 check_absolute_expr (ip
, ex
)
1576 struct mips_cl_insn
*ip
;
1579 if (ex
->X_op
!= O_constant
)
1580 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1584 * This routine generates the least number of instructions neccessary to load
1585 * an absolute expression value into a register.
1588 load_register (counter
, reg
, ep
)
1594 expressionS hi32
, lo32
;
1596 if (ep
->X_op
!= O_big
)
1598 assert (ep
->X_op
== O_constant
);
1599 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1601 /* We can handle 16 bit signed values with an addiu to
1602 $zero. No need to ever use daddiu here, since $zero and
1603 the result are always correct in 32 bit mode. */
1604 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1605 (int) BFD_RELOC_LO16
);
1608 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1610 /* We can handle 16 bit unsigned values with an ori to
1612 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1613 (int) BFD_RELOC_LO16
);
1616 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1617 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1618 == ~ (offsetT
) 0x7fffffff))
1620 /* 32 bit values require an lui. */
1621 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1622 (int) BFD_RELOC_HI16
);
1623 if ((ep
->X_add_number
& 0xffff) != 0)
1624 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1625 (int) BFD_RELOC_LO16
);
1630 /* The value is larger than 32 bits. */
1634 as_bad ("Number larger than 32 bits");
1635 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1636 (int) BFD_RELOC_LO16
);
1640 if (ep
->X_op
!= O_big
)
1644 hi32
.X_add_number
>>= shift
;
1645 hi32
.X_add_number
&= 0xffffffff;
1646 if ((hi32
.X_add_number
& 0x80000000) != 0)
1647 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1649 lo32
.X_add_number
&= 0xffffffff;
1653 assert (ep
->X_add_number
> 2);
1654 if (ep
->X_add_number
== 3)
1655 generic_bignum
[3] = 0;
1656 else if (ep
->X_add_number
> 4)
1657 as_bad ("Number larger than 64 bits");
1658 lo32
.X_op
= O_constant
;
1659 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1660 hi32
.X_op
= O_constant
;
1661 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1664 load_register (counter
, reg
, &hi32
);
1665 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1666 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1672 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1675 mid16
.X_add_number
>>= 16;
1676 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1677 reg
, (int) BFD_RELOC_LO16
);
1678 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1681 if ((lo32
.X_add_number
& 0xffff) != 0)
1682 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1683 (int) BFD_RELOC_LO16
);
1686 /* Load an address into a register. */
1689 load_address (counter
, reg
, ep
)
1696 if (ep
->X_op
!= O_constant
1697 && ep
->X_op
!= O_symbol
)
1699 as_bad ("expression too complex");
1700 ep
->X_op
= O_constant
;
1703 if (ep
->X_op
== O_constant
)
1705 load_register (counter
, reg
, ep
);
1709 if (mips_pic
== NO_PIC
)
1711 /* If this is a reference to a GP relative symbol, we want
1712 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1714 lui $reg,<sym> (BFD_RELOC_HI16_S)
1715 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1716 If we have an addend, we always use the latter form. */
1717 if (ep
->X_add_number
!= 0)
1722 macro_build ((char *) NULL
, counter
, ep
,
1723 mips_isa
< 3 ? "addiu" : "daddiu",
1724 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1725 p
= frag_var (rs_machine_dependent
, 8, 0,
1726 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1727 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1729 macro_build_lui (p
, counter
, ep
, reg
);
1732 macro_build (p
, counter
, ep
,
1733 mips_isa
< 3 ? "addiu" : "daddiu",
1734 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1736 else if (mips_pic
== SVR4_PIC
)
1740 /* If this is a reference to an external symbol, we want
1741 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1743 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1745 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1746 If there is a constant, it must be added in after. */
1747 ex
.X_add_number
= ep
->X_add_number
;
1748 ep
->X_add_number
= 0;
1750 macro_build ((char *) NULL
, counter
, ep
,
1751 mips_isa
< 3 ? "lw" : "ld",
1752 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1753 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1754 p
= frag_var (rs_machine_dependent
, 4, 0,
1755 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1756 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1757 macro_build (p
, counter
, ep
,
1758 mips_isa
< 3 ? "addiu" : "daddiu",
1759 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1760 if (ex
.X_add_number
!= 0)
1762 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1763 as_bad ("PIC code offset overflow (max 16 signed bits)");
1764 ex
.X_op
= O_constant
;
1765 macro_build (p
, counter
, &ex
,
1766 mips_isa
< 3 ? "addiu" : "daddiu",
1767 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1770 else if (mips_pic
== EMBEDDED_PIC
)
1773 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1775 macro_build ((char *) NULL
, counter
, ep
,
1776 mips_isa
< 3 ? "addiu" : "daddiu",
1777 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1785 * This routine implements the seemingly endless macro or synthesized
1786 * instructions and addressing modes in the mips assembly language. Many
1787 * of these macros are simple and are similar to each other. These could
1788 * probably be handled by some kind of table or grammer aproach instead of
1789 * this verbose method. Others are not simple macros but are more like
1790 * optimizing code generation.
1791 * One interesting optimization is when several store macros appear
1792 * consecutivly that would load AT with the upper half of the same address.
1793 * The ensuing load upper instructions are ommited. This implies some kind
1794 * of global optimization. We currently only optimize within a single macro.
1795 * For many of the load and store macros if the address is specified as a
1796 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1797 * first load register 'at' with zero and use it as the base register. The
1798 * mips assembler simply uses register $zero. Just one tiny optimization
1803 struct mips_cl_insn
*ip
;
1805 register int treg
, sreg
, dreg
, breg
;
1818 bfd_reloc_code_real_type r
;
1820 int hold_mips_optimize
;
1822 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1823 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1824 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1825 mask
= ip
->insn_mo
->mask
;
1827 expr1
.X_op
= O_constant
;
1828 expr1
.X_op_symbol
= NULL
;
1829 expr1
.X_add_symbol
= NULL
;
1830 expr1
.X_add_number
= 1;
1842 mips_emit_delays ();
1844 mips_any_noreorder
= 1;
1846 expr1
.X_add_number
= 8;
1847 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1849 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1851 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1852 macro_build ((char *) NULL
, &icnt
, NULL
,
1853 dbl
? "dsub" : "sub",
1854 "d,v,t", dreg
, 0, sreg
);
1877 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1879 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1880 (int) BFD_RELOC_LO16
);
1883 load_register (&icnt
, AT
, &imm_expr
);
1884 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1903 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1905 if (mask
!= M_NOR_I
)
1906 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1907 sreg
, (int) BFD_RELOC_LO16
);
1910 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1911 treg
, sreg
, (int) BFD_RELOC_LO16
);
1912 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1918 load_register (&icnt
, AT
, &imm_expr
);
1919 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1936 if (imm_expr
.X_add_number
== 0)
1938 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1942 load_register (&icnt
, AT
, &imm_expr
);
1943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1951 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1952 likely
? "bgezl" : "bgez",
1958 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1959 likely
? "blezl" : "blez",
1963 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1965 likely
? "beql" : "beq",
1972 /* check for > max integer */
1973 maxnum
= 0x7fffffff;
1981 if (imm_expr
.X_add_number
>= maxnum
1982 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
1985 /* result is always false */
1988 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1989 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1993 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1999 imm_expr
.X_add_number
++;
2003 if (mask
== M_BGEL_I
)
2005 if (imm_expr
.X_add_number
== 0)
2007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2008 likely
? "bgezl" : "bgez",
2012 if (imm_expr
.X_add_number
== 1)
2014 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2015 likely
? "bgtzl" : "bgtz",
2019 maxnum
= 0x7fffffff;
2027 maxnum
= - maxnum
- 1;
2028 if (imm_expr
.X_add_number
<= maxnum
2029 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2032 /* result is always true */
2033 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2034 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2037 set_at (&icnt
, sreg
, 0);
2038 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2039 likely
? "beql" : "beq",
2050 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2051 likely
? "beql" : "beq",
2055 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2057 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2058 likely
? "beql" : "beq",
2065 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2067 imm_expr
.X_add_number
++;
2071 if (mask
== M_BGEUL_I
)
2073 if (imm_expr
.X_add_number
== 0)
2075 if (imm_expr
.X_add_number
== 1)
2077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2078 likely
? "bnel" : "bne",
2082 set_at (&icnt
, sreg
, 1);
2083 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2084 likely
? "beql" : "beq",
2093 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2094 likely
? "bgtzl" : "bgtz",
2100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2101 likely
? "bltzl" : "bltz",
2105 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2107 likely
? "bnel" : "bne",
2116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2117 likely
? "bnel" : "bne",
2123 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2125 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2126 likely
? "bnel" : "bne",
2135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2136 likely
? "blezl" : "blez",
2142 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2143 likely
? "bgezl" : "bgez",
2147 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2149 likely
? "beql" : "beq",
2156 maxnum
= 0x7fffffff;
2164 if (imm_expr
.X_add_number
>= maxnum
2165 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2167 imm_expr
.X_add_number
++;
2171 if (mask
== M_BLTL_I
)
2173 if (imm_expr
.X_add_number
== 0)
2175 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2176 likely
? "bltzl" : "bltz",
2180 if (imm_expr
.X_add_number
== 1)
2182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2183 likely
? "blezl" : "blez",
2187 set_at (&icnt
, sreg
, 0);
2188 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2189 likely
? "bnel" : "bne",
2198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2199 likely
? "beql" : "beq",
2205 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2207 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2208 likely
? "beql" : "beq",
2215 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2217 imm_expr
.X_add_number
++;
2221 if (mask
== M_BLTUL_I
)
2223 if (imm_expr
.X_add_number
== 0)
2225 if (imm_expr
.X_add_number
== 1)
2227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2228 likely
? "beql" : "beq",
2232 set_at (&icnt
, sreg
, 1);
2233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2234 likely
? "bnel" : "bne",
2243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2244 likely
? "bltzl" : "bltz",
2250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2251 likely
? "bgtzl" : "bgtz",
2255 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2257 likely
? "bnel" : "bne",
2268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2269 likely
? "bnel" : "bne",
2273 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2275 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2276 likely
? "bnel" : "bne",
2292 as_warn ("Divide by zero.");
2294 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2296 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2300 mips_emit_delays ();
2302 mips_any_noreorder
= 1;
2303 macro_build ((char *) NULL
, &icnt
, NULL
,
2304 dbl
? "ddiv" : "div",
2305 "z,s,t", sreg
, treg
);
2307 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2310 expr1
.X_add_number
= 8;
2311 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2312 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2313 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2315 expr1
.X_add_number
= -1;
2316 macro_build ((char *) NULL
, &icnt
, &expr1
,
2317 dbl
? "daddiu" : "addiu",
2318 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2319 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2320 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2323 expr1
.X_add_number
= 1;
2324 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2325 (int) BFD_RELOC_LO16
);
2326 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2331 expr1
.X_add_number
= 0x80000000;
2332 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2333 (int) BFD_RELOC_HI16
);
2336 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2339 expr1
.X_add_number
= 8;
2340 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2341 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2342 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2345 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2384 if (imm_expr
.X_add_number
== 0)
2386 as_warn ("Divide by zero.");
2388 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2390 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2393 if (imm_expr
.X_add_number
== 1)
2395 if (strcmp (s2
, "mflo") == 0)
2396 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2399 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2402 if (imm_expr
.X_add_number
== -1
2403 && s
[strlen (s
) - 1] != 'u')
2405 if (strcmp (s2
, "mflo") == 0)
2408 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2411 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2415 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2419 load_register (&icnt
, AT
, &imm_expr
);
2420 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2421 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2440 mips_emit_delays ();
2442 mips_any_noreorder
= 1;
2443 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2445 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2448 expr1
.X_add_number
= 8;
2449 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2450 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2451 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2454 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2458 /* Load the address of a symbol into a register. If breg is not
2459 zero, we then add a base register to it. */
2461 /* When generating embedded PIC code, we permit expressions of
2464 where bar is an address in the .text section. These are used
2465 when getting the addresses of functions. We don't permit
2466 X_add_number to be non-zero, because if the symbol is
2467 external the relaxing code needs to know that any addend is
2468 purely the offset to X_op_symbol. */
2469 if (mips_pic
== EMBEDDED_PIC
2470 && offset_expr
.X_op
== O_subtract
2471 && now_seg
== text_section
2472 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2473 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2474 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2475 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2476 ->sy_value
.X_add_symbol
)
2479 && offset_expr
.X_add_number
== 0)
2481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2482 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2483 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2484 mips_isa
< 3 ? "addiu" : "daddiu",
2485 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2489 if (offset_expr
.X_op
!= O_symbol
2490 && offset_expr
.X_op
!= O_constant
)
2492 as_bad ("expression too complex");
2493 offset_expr
.X_op
= O_constant
;
2507 if (offset_expr
.X_op
== O_constant
)
2508 load_register (&icnt
, tempreg
, &offset_expr
);
2509 else if (mips_pic
== NO_PIC
)
2511 /* If this is a reference to an GP relative symbol, we want
2512 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2514 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2515 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2516 If we have a constant, we need two instructions anyhow,
2517 so we may as well always use the latter form. */
2518 if (offset_expr
.X_add_number
!= 0)
2523 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2524 mips_isa
< 3 ? "addiu" : "daddiu",
2525 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2526 p
= frag_var (rs_machine_dependent
, 8, 0,
2527 RELAX_ENCODE (4, 8, 0, 4, 0,
2528 mips_warn_about_macros
),
2529 offset_expr
.X_add_symbol
, (long) 0,
2532 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2535 macro_build (p
, &icnt
, &offset_expr
,
2536 mips_isa
< 3 ? "addiu" : "daddiu",
2537 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2539 else if (mips_pic
== SVR4_PIC
)
2541 /* If this is a reference to an external symbol, and there
2542 is no constant, we want
2543 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2544 For a local symbol, we want
2545 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2547 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2549 If we have a small constant, and this is a reference to
2550 an external symbol, we want
2551 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2553 addiu $tempreg,$tempreg,<constant>
2554 For a local symbol, we want the same instruction
2555 sequence, but we output a BFD_RELOC_LO16 reloc on the
2558 If we have a large constant, and this is a reference to
2559 an external symbol, we want
2560 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2561 lui $at,<hiconstant>
2562 addiu $at,$at,<loconstant>
2563 addu $tempreg,$tempreg,$at
2564 For a local symbol, we want the same instruction
2565 sequence, but we output a BFD_RELOC_LO16 reloc on the
2566 addiu instruction. */
2567 expr1
.X_add_number
= offset_expr
.X_add_number
;
2568 offset_expr
.X_add_number
= 0;
2570 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2571 mips_isa
< 3 ? "lw" : "ld",
2572 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2573 if (expr1
.X_add_number
== 0)
2581 /* We're going to put in an addu instruction using
2582 tempreg, so we may as well insert the nop right
2584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2588 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2589 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2591 ? mips_warn_about_macros
2593 offset_expr
.X_add_symbol
, (long) 0,
2597 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2600 macro_build (p
, &icnt
, &expr1
,
2601 mips_isa
< 3 ? "addiu" : "daddiu",
2602 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2603 /* FIXME: If breg == 0, and the next instruction uses
2604 $tempreg, then if this variant case is used an extra
2605 nop will be generated. */
2607 else if (expr1
.X_add_number
>= -0x8000
2608 && expr1
.X_add_number
< 0x8000)
2610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2612 macro_build ((char *) NULL
, &icnt
, &expr1
,
2613 mips_isa
< 3 ? "addiu" : "daddiu",
2614 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2615 (void) frag_var (rs_machine_dependent
, 0, 0,
2616 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2617 offset_expr
.X_add_symbol
, (long) 0,
2624 /* If we are going to add in a base register, and the
2625 target register and the base register are the same,
2626 then we are using AT as a temporary register. Since
2627 we want to load the constant into AT, we add our
2628 current AT (from the global offset table) and the
2629 register into the register now, and pretend we were
2630 not using a base register. */
2635 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2638 mips_isa
< 3 ? "addu" : "daddu",
2639 "d,v,t", treg
, AT
, breg
);
2645 /* Set mips_optimize around the lui instruction to avoid
2646 inserting an unnecessary nop after the lw. */
2647 hold_mips_optimize
= mips_optimize
;
2649 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2650 mips_optimize
= hold_mips_optimize
;
2652 macro_build ((char *) NULL
, &icnt
, &expr1
,
2653 mips_isa
< 3 ? "addiu" : "daddiu",
2654 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2655 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2656 mips_isa
< 3 ? "addu" : "daddu",
2657 "d,v,t", tempreg
, tempreg
, AT
);
2658 (void) frag_var (rs_machine_dependent
, 0, 0,
2659 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2660 offset_expr
.X_add_symbol
, (long) 0,
2665 else if (mips_pic
== EMBEDDED_PIC
)
2668 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2670 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2671 mips_isa
< 3 ? "addiu" : "daddiu",
2672 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2679 mips_isa
< 3 ? "addu" : "daddu",
2680 "d,v,t", treg
, tempreg
, breg
);
2688 /* The j instruction may not be used in PIC code, since it
2689 requires an absolute address. We convert it to a b
2691 if (mips_pic
== NO_PIC
)
2692 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2694 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2697 /* The jal instructions must be handled as macros because when
2698 generating PIC code they expand to multi-instruction
2699 sequences. Normally they are simple instructions. */
2704 if (mips_pic
== NO_PIC
2705 || mips_pic
== EMBEDDED_PIC
)
2706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2708 else if (mips_pic
== SVR4_PIC
)
2710 if (sreg
!= PIC_CALL_REG
)
2711 as_warn ("MIPS PIC call to register other than $25");
2713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2715 if (mips_cprestore_offset
< 0)
2716 as_warn ("No .cprestore pseudo-op used in PIC code");
2719 expr1
.X_add_number
= mips_cprestore_offset
;
2720 macro_build ((char *) NULL
, &icnt
, &expr1
,
2721 mips_isa
< 3 ? "lw" : "ld",
2722 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2731 if (mips_pic
== NO_PIC
)
2732 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2733 else if (mips_pic
== SVR4_PIC
)
2735 /* If this is a reference to an external symbol, we want
2736 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2740 lw $gp,cprestore($sp)
2741 The cprestore value is set using the .cprestore
2742 pseudo-op. If the symbol is not external, we want
2743 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2745 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2748 lw $gp,cprestore($sp)
2751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2752 mips_isa
< 3 ? "lw" : "ld",
2753 "t,o(b)", PIC_CALL_REG
,
2754 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2756 p
= frag_var (rs_machine_dependent
, 4, 0,
2757 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2758 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2759 macro_build (p
, &icnt
, &offset_expr
,
2760 mips_isa
< 3 ? "addiu" : "daddiu",
2761 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2762 (int) BFD_RELOC_LO16
);
2763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2764 "jalr", "s", PIC_CALL_REG
);
2765 if (mips_cprestore_offset
< 0)
2766 as_warn ("No .cprestore pseudo-op used in PIC code");
2770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2772 expr1
.X_add_number
= mips_cprestore_offset
;
2773 macro_build ((char *) NULL
, &icnt
, &expr1
,
2774 mips_isa
< 3 ? "lw" : "ld",
2775 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2779 else if (mips_pic
== EMBEDDED_PIC
)
2781 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2782 /* The linker may expand the call to a longer sequence which
2783 uses $at, so we must break rather than return. */
2855 if (breg
== treg
|| coproc
)
2924 if (mask
== M_LWC1_AB
2925 || mask
== M_SWC1_AB
2926 || mask
== M_LDC1_AB
2927 || mask
== M_SDC1_AB
2936 if (offset_expr
.X_op
!= O_constant
2937 && offset_expr
.X_op
!= O_symbol
)
2939 as_bad ("expression too complex");
2940 offset_expr
.X_op
= O_constant
;
2943 /* A constant expression in PIC code can be handled just as it
2944 is in non PIC code. */
2945 if (mips_pic
== NO_PIC
2946 || offset_expr
.X_op
== O_constant
)
2948 /* If this is a reference to a GP relative symbol, and there
2949 is no base register, we want
2950 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2951 Otherwise, if there is no base register, we want
2952 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2953 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2954 If we have a constant, we need two instructions anyhow,
2955 so we always use the latter form.
2957 If we have a base register, and this is a reference to a
2958 GP relative symbol, we want
2959 addu $tempreg,$breg,$gp
2960 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2962 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2963 addu $tempreg,$tempreg,$breg
2964 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2965 With a constant we always use the latter case. */
2968 if (offset_expr
.X_add_number
!= 0)
2973 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2974 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2975 p
= frag_var (rs_machine_dependent
, 8, 0,
2976 RELAX_ENCODE (4, 8, 0, 4, 0,
2977 (mips_warn_about_macros
2978 || (used_at
&& mips_noat
))),
2979 offset_expr
.X_add_symbol
, (long) 0,
2983 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2986 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2987 (int) BFD_RELOC_LO16
, tempreg
);
2991 if (offset_expr
.X_add_number
!= 0)
2996 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2997 mips_isa
< 3 ? "addu" : "daddu",
2998 "d,v,t", tempreg
, breg
, GP
);
2999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3000 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3001 p
= frag_var (rs_machine_dependent
, 12, 0,
3002 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3003 offset_expr
.X_add_symbol
, (long) 0,
3006 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3009 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3010 mips_isa
< 3 ? "addu" : "daddu",
3011 "d,v,t", tempreg
, tempreg
, breg
);
3014 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3015 (int) BFD_RELOC_LO16
, tempreg
);
3018 else if (mips_pic
== SVR4_PIC
)
3020 /* If this is a reference to an external symbol, we want
3021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3023 <op> $treg,0($tempreg)
3025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3027 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3028 <op> $treg,0($tempreg)
3029 If there is a base register, we add it to $tempreg before
3030 the <op>. If there is a constant, we stick it in the
3031 <op> instruction. We don't handle constants larger than
3032 16 bits, because we have no way to load the upper 16 bits
3033 (actually, we could handle them for the subset of cases
3034 in which we are not using $at). */
3035 assert (offset_expr
.X_op
== O_symbol
);
3036 expr1
.X_add_number
= offset_expr
.X_add_number
;
3037 offset_expr
.X_add_number
= 0;
3038 if (expr1
.X_add_number
< -0x8000
3039 || expr1
.X_add_number
>= 0x8000)
3040 as_bad ("PIC code offset overflow (max 16 signed bits)");
3042 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3043 mips_isa
< 3 ? "lw" : "ld",
3044 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3046 p
= frag_var (rs_machine_dependent
, 4, 0,
3047 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3048 offset_expr
.X_add_symbol
, (long) 0,
3050 macro_build (p
, &icnt
, &offset_expr
,
3051 mips_isa
< 3 ? "addiu" : "daddiu",
3052 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3054 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3055 mips_isa
< 3 ? "addu" : "daddu",
3056 "d,v,t", tempreg
, tempreg
, breg
);
3057 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3058 (int) BFD_RELOC_LO16
, tempreg
);
3060 else if (mips_pic
== EMBEDDED_PIC
)
3062 /* If there is no base register, we want
3063 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3064 If there is a base register, we want
3065 addu $tempreg,$breg,$gp
3066 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3068 assert (offset_expr
.X_op
== O_symbol
);
3071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3072 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3078 mips_isa
< 3 ? "addu" : "daddu",
3079 "d,v,t", tempreg
, breg
, GP
);
3080 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3081 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3094 load_register (&icnt
, treg
, &imm_expr
);
3098 if (imm_expr
.X_op
== O_constant
)
3100 load_register (&icnt
, AT
, &imm_expr
);
3101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3102 "mtc1", "t,G", AT
, treg
);
3107 assert (offset_expr
.X_op
== O_symbol
3108 && strcmp (segment_name (S_GET_SEGMENT
3109 (offset_expr
.X_add_symbol
)),
3111 && offset_expr
.X_add_number
== 0);
3112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3113 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3118 /* We know that sym is in the .rdata section. First we get the
3119 upper 16 bits of the address. */
3120 if (mips_pic
== NO_PIC
)
3122 /* FIXME: This won't work for a 64 bit address. */
3123 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3125 else if (mips_pic
== SVR4_PIC
)
3127 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3128 mips_isa
< 3 ? "lw" : "ld",
3129 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3131 else if (mips_pic
== EMBEDDED_PIC
)
3133 /* For embedded PIC we pick up the entire address off $gp in
3134 a single instruction. */
3135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3136 mips_isa
< 3 ? "addiu" : "daddiu",
3137 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3138 offset_expr
.X_op
= O_constant
;
3139 offset_expr
.X_add_number
= 0;
3144 /* Now we load the register(s). */
3146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3147 treg
, (int) BFD_RELOC_LO16
, AT
);
3150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3151 treg
, (int) BFD_RELOC_LO16
, AT
);
3154 /* FIXME: How in the world do we deal with the possible
3156 offset_expr
.X_add_number
+= 4;
3157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3158 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3162 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3163 does not become a variant frag. */
3164 frag_wane (frag_now
);
3170 assert (offset_expr
.X_op
== O_symbol
3171 && offset_expr
.X_add_number
== 0);
3172 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3173 if (strcmp (s
, ".lit8") == 0)
3177 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3178 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3182 r
= BFD_RELOC_MIPS_LITERAL
;
3187 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3188 if (mips_pic
== SVR4_PIC
)
3189 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3190 mips_isa
< 3 ? "lw" : "ld",
3191 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3194 /* FIXME: This won't work for a 64 bit address. */
3195 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3201 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3203 /* To avoid confusion in tc_gen_reloc, we must ensure
3204 that this does not become a variant frag. */
3205 frag_wane (frag_now
);
3216 /* Even on a big endian machine $fn comes before $fn+1. We have
3217 to adjust when loading from memory. */
3220 assert (mips_isa
< 2);
3221 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3222 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3224 /* FIXME: A possible overflow which I don't know how to deal
3226 offset_expr
.X_add_number
+= 4;
3227 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3228 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3231 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3232 does not become a variant frag. */
3233 frag_wane (frag_now
);
3242 * The MIPS assembler seems to check for X_add_number not
3243 * being double aligned and generating:
3246 * addiu at,at,%lo(foo+1)
3249 * But, the resulting address is the same after relocation so why
3250 * generate the extra instruction?
3297 if (offset_expr
.X_op
!= O_symbol
3298 && offset_expr
.X_op
!= O_constant
)
3300 as_bad ("expression too complex");
3301 offset_expr
.X_op
= O_constant
;
3304 /* Even on a big endian machine $fn comes before $fn+1. We have
3305 to adjust when loading from memory. We set coproc if we must
3306 load $fn+1 first. */
3307 if (byte_order
== LITTLE_ENDIAN
)
3310 if (mips_pic
== NO_PIC
3311 || offset_expr
.X_op
== O_constant
)
3313 /* If this is a reference to a GP relative symbol, we want
3314 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3315 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3316 If we have a base register, we use this
3318 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3319 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3320 If this is not a GP relative symbol, we want
3321 lui $at,<sym> (BFD_RELOC_HI16_S)
3322 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3323 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3324 If there is a base register, we add it to $at after the
3325 lui instruction. If there is a constant, we always use
3327 if (offset_expr
.X_add_number
!= 0)
3346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3347 mips_isa
< 3 ? "addu" : "daddu",
3348 "d,v,t", AT
, breg
, GP
);
3354 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3355 coproc
? treg
+ 1 : treg
,
3356 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3357 offset_expr
.X_add_number
+= 4;
3359 /* Set mips_optimize to 2 to avoid inserting an
3361 hold_mips_optimize
= mips_optimize
;
3363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3364 coproc
? treg
: treg
+ 1,
3365 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3366 mips_optimize
= hold_mips_optimize
;
3368 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3369 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3370 used_at
&& mips_noat
),
3371 offset_expr
.X_add_symbol
, (long) 0,
3374 /* We just generated two relocs. When tc_gen_reloc
3375 handles this case, it will skip the first reloc and
3376 handle the second. The second reloc already has an
3377 extra addend of 4, which we added above. We must
3378 subtract it out, and then subtract another 4 to make
3379 the first reloc come out right. The second reloc
3380 will come out right because we are going to add 4 to
3381 offset_expr when we build its instruction below. */
3382 offset_expr
.X_add_number
-= 8;
3383 offset_expr
.X_op
= O_constant
;
3385 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3390 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3391 mips_isa
< 3 ? "addu" : "daddu",
3392 "d,v,t", AT
, breg
, AT
);
3396 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3397 coproc
? treg
+ 1 : treg
,
3398 (int) BFD_RELOC_LO16
, AT
);
3401 /* FIXME: How do we handle overflow here? */
3402 offset_expr
.X_add_number
+= 4;
3403 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3404 coproc
? treg
: treg
+ 1,
3405 (int) BFD_RELOC_LO16
, AT
);
3407 else if (mips_pic
== SVR4_PIC
)
3411 /* If this is a reference to an external symbol, we want
3412 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3417 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3419 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3420 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3421 If there is a base register we add it to $at before the
3422 lwc1 instructions. If there is a constant we include it
3423 in the lwc1 instructions. */
3425 expr1
.X_add_number
= offset_expr
.X_add_number
;
3426 offset_expr
.X_add_number
= 0;
3427 if (expr1
.X_add_number
< -0x8000
3428 || expr1
.X_add_number
>= 0x8000 - 4)
3429 as_bad ("PIC code offset overflow (max 16 signed bits)");
3434 frag_grow (24 + off
);
3435 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3436 mips_isa
< 3 ? "lw" : "ld",
3437 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3440 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3441 mips_isa
< 3 ? "addu" : "daddu",
3442 "d,v,t", AT
, breg
, AT
);
3443 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3444 coproc
? treg
+ 1 : treg
,
3445 (int) BFD_RELOC_LO16
, AT
);
3446 expr1
.X_add_number
+= 4;
3448 /* Set mips_optimize to 2 to avoid inserting an undesired
3450 hold_mips_optimize
= mips_optimize
;
3452 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3453 coproc
? treg
: treg
+ 1,
3454 (int) BFD_RELOC_LO16
, AT
);
3455 mips_optimize
= hold_mips_optimize
;
3457 (void) frag_var (rs_machine_dependent
, 0, 0,
3458 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3459 offset_expr
.X_add_symbol
, (long) 0,
3462 else if (mips_pic
== EMBEDDED_PIC
)
3464 /* If there is no base register, we use
3465 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3466 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3467 If we have a base register, we use
3469 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3470 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3480 mips_isa
< 3 ? "addu" : "daddu",
3481 "d,v,t", AT
, breg
, GP
);
3486 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3487 coproc
? treg
+ 1 : treg
,
3488 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3489 offset_expr
.X_add_number
+= 4;
3490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3491 coproc
? treg
: treg
+ 1,
3492 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3508 assert (mips_isa
< 3);
3509 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3510 (int) BFD_RELOC_LO16
, breg
);
3511 offset_expr
.X_add_number
+= 4;
3512 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3513 (int) BFD_RELOC_LO16
, breg
);
3515 #ifdef LOSING_COMPILER
3521 as_warn ("Macro used $at after \".set noat\"");
3526 struct mips_cl_insn
*ip
;
3528 register int treg
, sreg
, dreg
, breg
;
3541 bfd_reloc_code_real_type r
;
3544 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3545 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3546 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3547 mask
= ip
->insn_mo
->mask
;
3549 expr1
.X_op
= O_constant
;
3550 expr1
.X_op_symbol
= NULL
;
3551 expr1
.X_add_symbol
= NULL
;
3552 expr1
.X_add_number
= 1;
3556 #endif /* LOSING_COMPILER */
3561 macro_build ((char *) NULL
, &icnt
, NULL
,
3562 dbl
? "dmultu" : "multu",
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3570 /* The MIPS assembler some times generates shifts and adds. I'm
3571 not trying to be that fancy. GCC should do this for us
3573 load_register (&icnt
, AT
, &imm_expr
);
3574 macro_build ((char *) NULL
, &icnt
, NULL
,
3575 dbl
? "dmult" : "mult",
3577 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3583 mips_emit_delays ();
3585 mips_any_noreorder
= 1;
3586 macro_build ((char *) NULL
, &icnt
, NULL
,
3587 dbl
? "dmult" : "mult",
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3590 macro_build ((char *) NULL
, &icnt
, NULL
,
3591 dbl
? "dsra32" : "sra",
3592 "d,w,<", dreg
, dreg
, 31);
3593 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3595 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3598 expr1
.X_add_number
= 8;
3599 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3600 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3604 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3610 mips_emit_delays ();
3612 mips_any_noreorder
= 1;
3613 macro_build ((char *) NULL
, &icnt
, NULL
,
3614 dbl
? "dmultu" : "multu",
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3622 expr1
.X_add_number
= 8;
3623 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3624 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3625 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3631 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3632 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3633 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3640 imm_expr
.X_add_number
& 0x1f);
3641 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3642 (0 - imm_expr
.X_add_number
) & 0x1f);
3643 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3647 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3648 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3649 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3655 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3656 imm_expr
.X_add_number
& 0x1f);
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3658 (0 - imm_expr
.X_add_number
) & 0x1f);
3659 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3663 assert (mips_isa
< 2);
3664 /* Even on a big endian machine $fn comes before $fn+1. We have
3665 to adjust when storing to memory. */
3666 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3667 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3668 (int) BFD_RELOC_LO16
, breg
);
3669 offset_expr
.X_add_number
+= 4;
3670 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3671 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3672 (int) BFD_RELOC_LO16
, breg
);
3677 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3678 treg
, (int) BFD_RELOC_LO16
);
3680 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3681 sreg
, (int) BFD_RELOC_LO16
);
3684 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3686 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3687 dreg
, (int) BFD_RELOC_LO16
);
3692 if (imm_expr
.X_add_number
== 0)
3694 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3695 sreg
, (int) BFD_RELOC_LO16
);
3700 as_warn ("Instruction %s: result is always false",
3702 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3705 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3707 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3708 sreg
, (int) BFD_RELOC_LO16
);
3711 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3713 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3714 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3715 mips_isa
< 3 ? "addiu" : "daddiu",
3716 "t,r,j", dreg
, sreg
,
3717 (int) BFD_RELOC_LO16
);
3722 load_register (&icnt
, AT
, &imm_expr
);
3723 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3727 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3728 (int) BFD_RELOC_LO16
);
3733 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3739 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3740 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3741 (int) BFD_RELOC_LO16
);
3744 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3746 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3748 macro_build ((char *) NULL
, &icnt
, &expr1
,
3749 mask
== M_SGE_I
? "slti" : "sltiu",
3750 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3755 load_register (&icnt
, AT
, &imm_expr
);
3756 macro_build ((char *) NULL
, &icnt
, NULL
,
3757 mask
== M_SGE_I
? "slt" : "sltu",
3758 "d,v,t", dreg
, sreg
, AT
);
3761 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3762 (int) BFD_RELOC_LO16
);
3767 case M_SGT
: /* sreg > treg <==> treg < sreg */
3773 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3776 case M_SGT_I
: /* sreg > I <==> I < sreg */
3782 load_register (&icnt
, AT
, &imm_expr
);
3783 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3786 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3792 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3793 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3794 (int) BFD_RELOC_LO16
);
3797 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3803 load_register (&icnt
, AT
, &imm_expr
);
3804 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3805 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3806 (int) BFD_RELOC_LO16
);
3810 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3812 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3813 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3816 load_register (&icnt
, AT
, &imm_expr
);
3817 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3821 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3823 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3824 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3827 load_register (&icnt
, AT
, &imm_expr
);
3828 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3834 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3841 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3843 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3849 if (imm_expr
.X_add_number
== 0)
3851 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3857 as_warn ("Instruction %s: result is always true",
3859 macro_build ((char *) NULL
, &icnt
, &expr1
,
3860 mips_isa
< 3 ? "addiu" : "daddiu",
3861 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3864 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3866 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3867 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3870 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3872 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3873 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3874 mips_isa
< 3 ? "addiu" : "daddiu",
3875 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3880 load_register (&icnt
, AT
, &imm_expr
);
3881 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3885 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3893 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3895 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3896 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3897 dbl
? "daddi" : "addi",
3898 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3901 load_register (&icnt
, AT
, &imm_expr
);
3902 macro_build ((char *) NULL
, &icnt
, NULL
,
3903 dbl
? "dsub" : "sub",
3904 "d,v,t", dreg
, sreg
, AT
);
3910 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3912 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3913 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3914 dbl
? "daddiu" : "addiu",
3915 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3918 load_register (&icnt
, AT
, &imm_expr
);
3919 macro_build ((char *) NULL
, &icnt
, NULL
,
3920 dbl
? "dsubu" : "subu",
3921 "d,v,t", dreg
, sreg
, AT
);
3942 load_register (&icnt
, AT
, &imm_expr
);
3943 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3948 assert (mips_isa
< 2);
3949 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3950 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3953 * Is the double cfc1 instruction a bug in the mips assembler;
3954 * or is there a reason for it?
3956 mips_emit_delays ();
3958 mips_any_noreorder
= 1;
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3962 expr1
.X_add_number
= 3;
3963 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3964 (int) BFD_RELOC_LO16
);
3965 expr1
.X_add_number
= 2;
3966 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3967 (int) BFD_RELOC_LO16
);
3968 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3969 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3970 macro_build ((char *) NULL
, &icnt
, NULL
,
3971 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3972 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3973 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3983 if (offset_expr
.X_add_number
>= 0x7fff)
3984 as_bad ("operand overflow");
3985 /* avoid load delay */
3986 if (byte_order
== LITTLE_ENDIAN
)
3987 offset_expr
.X_add_number
+= 1;
3988 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3989 (int) BFD_RELOC_LO16
, breg
);
3990 if (byte_order
== LITTLE_ENDIAN
)
3991 offset_expr
.X_add_number
-= 1;
3993 offset_expr
.X_add_number
+= 1;
3994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3995 (int) BFD_RELOC_LO16
, breg
);
3996 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3997 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4001 if (offset_expr
.X_add_number
>= 0x7ffd)
4002 as_bad ("operand overflow");
4003 if (byte_order
== LITTLE_ENDIAN
)
4004 offset_expr
.X_add_number
+= 3;
4005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
4006 (int) BFD_RELOC_LO16
, breg
);
4007 if (byte_order
== LITTLE_ENDIAN
)
4008 offset_expr
.X_add_number
-= 3;
4010 offset_expr
.X_add_number
+= 3;
4011 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
4012 (int) BFD_RELOC_LO16
, breg
);
4018 load_address (&icnt
, AT
, &offset_expr
);
4019 if (mask
== M_ULW_A
)
4021 if (byte_order
== LITTLE_ENDIAN
)
4022 expr1
.X_add_number
= 3;
4024 expr1
.X_add_number
= 0;
4025 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
4026 (int) BFD_RELOC_LO16
, AT
);
4027 if (byte_order
== LITTLE_ENDIAN
)
4028 expr1
.X_add_number
= 0;
4030 expr1
.X_add_number
= 3;
4031 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
4032 (int) BFD_RELOC_LO16
, AT
);
4036 if (byte_order
== BIG_ENDIAN
)
4037 expr1
.X_add_number
= 0;
4038 macro_build ((char *) NULL
, &icnt
, &expr1
,
4039 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4040 (int) BFD_RELOC_LO16
, AT
);
4041 if (byte_order
== BIG_ENDIAN
)
4042 expr1
.X_add_number
= 1;
4044 expr1
.X_add_number
= 0;
4045 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4046 (int) BFD_RELOC_LO16
, AT
);
4047 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4055 if (offset_expr
.X_add_number
>= 0x7fff)
4056 as_bad ("operand overflow");
4057 if (byte_order
== BIG_ENDIAN
)
4058 offset_expr
.X_add_number
+= 1;
4059 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4060 (int) BFD_RELOC_LO16
, breg
);
4061 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4062 if (byte_order
== BIG_ENDIAN
)
4063 offset_expr
.X_add_number
-= 1;
4065 offset_expr
.X_add_number
+= 1;
4066 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4067 (int) BFD_RELOC_LO16
, breg
);
4071 if (offset_expr
.X_add_number
>= 0x7ffd)
4072 as_bad ("operand overflow");
4073 if (byte_order
== LITTLE_ENDIAN
)
4074 offset_expr
.X_add_number
+= 3;
4075 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4076 (int) BFD_RELOC_LO16
, breg
);
4077 if (byte_order
== LITTLE_ENDIAN
)
4078 offset_expr
.X_add_number
-= 3;
4080 offset_expr
.X_add_number
+= 3;
4081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4082 (int) BFD_RELOC_LO16
, breg
);
4087 load_address (&icnt
, AT
, &offset_expr
);
4088 if (mask
== M_USW_A
)
4090 if (byte_order
== LITTLE_ENDIAN
)
4091 expr1
.X_add_number
= 3;
4093 expr1
.X_add_number
= 0;
4094 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4095 (int) BFD_RELOC_LO16
, AT
);
4096 if (byte_order
== LITTLE_ENDIAN
)
4097 expr1
.X_add_number
= 0;
4099 expr1
.X_add_number
= 3;
4100 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4101 (int) BFD_RELOC_LO16
, AT
);
4105 if (byte_order
== LITTLE_ENDIAN
)
4106 expr1
.X_add_number
= 0;
4107 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4108 (int) BFD_RELOC_LO16
, AT
);
4109 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4111 if (byte_order
== LITTLE_ENDIAN
)
4112 expr1
.X_add_number
= 1;
4114 expr1
.X_add_number
= 0;
4115 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4116 (int) BFD_RELOC_LO16
, AT
);
4117 if (byte_order
== LITTLE_ENDIAN
)
4118 expr1
.X_add_number
= 0;
4120 expr1
.X_add_number
= 1;
4121 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4122 (int) BFD_RELOC_LO16
, AT
);
4123 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4125 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4131 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4135 as_warn ("Macro used $at after \".set noat\"");
4140 This routine assembles an instruction into its binary format. As a side
4141 effect it sets one of the global variables imm_reloc or offset_reloc to the
4142 type of relocation to do if one of the operands is an address expression.
4147 struct mips_cl_insn
*ip
;
4152 struct mips_opcode
*insn
;
4155 unsigned int lastregno
= 0;
4160 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4172 as_fatal ("Unknown opcode: `%s'", str
);
4174 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4176 as_warn ("`%s' not in hash table.", str
);
4177 insn_error
= "ERROR: Unrecognized opcode";
4185 assert (strcmp (insn
->name
, str
) == 0);
4187 if (insn
->pinfo
== INSN_MACRO
)
4188 insn_isa
= insn
->match
;
4189 else if (insn
->pinfo
& INSN_ISA2
)
4191 else if (insn
->pinfo
& INSN_ISA3
)
4196 if (insn_isa
> mips_isa
)
4198 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4199 && strcmp (insn
->name
, insn
[1].name
) == 0)
4204 as_warn ("Instruction not supported on this processor");
4208 ip
->insn_opcode
= insn
->match
;
4209 for (args
= insn
->args
;; ++args
)
4215 case '\0': /* end of args */
4228 ip
->insn_opcode
|= lastregno
<< 21;
4233 ip
->insn_opcode
|= lastregno
<< 16;
4237 ip
->insn_opcode
|= lastregno
<< 11;
4243 /* handle optional base register.
4244 Either the base register is omitted or
4245 we must have a left paren. */
4246 /* this is dependent on the next operand specifier
4247 is a 'b' for base register */
4248 assert (args
[1] == 'b');
4252 case ')': /* these must match exactly */
4257 case '<': /* must be at least one digit */
4259 * According to the manual, if the shift amount is greater
4260 * than 31 or less than 0 the the shift amount should be
4261 * mod 32. In reality the mips assembler issues an error.
4262 * We issue a warning and mask out all but the low 5 bits.
4264 my_getExpression (&imm_expr
, s
);
4265 check_absolute_expr (ip
, &imm_expr
);
4266 if ((unsigned long) imm_expr
.X_add_number
> 31)
4268 as_warn ("Improper shift amount (%ld)",
4269 (long) imm_expr
.X_add_number
);
4270 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4272 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4273 imm_expr
.X_op
= O_absent
;
4277 case '>': /* shift amount minus 32 */
4278 my_getExpression (&imm_expr
, s
);
4279 check_absolute_expr (ip
, &imm_expr
);
4280 if ((unsigned long) imm_expr
.X_add_number
< 32
4281 || (unsigned long) imm_expr
.X_add_number
> 63)
4283 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4284 imm_expr
.X_op
= O_absent
;
4288 case 'k': /* cache code */
4289 my_getExpression (&imm_expr
, s
);
4290 check_absolute_expr (ip
, &imm_expr
);
4291 if ((unsigned long) imm_expr
.X_add_number
> 31)
4293 as_warn ("Invalid cahce opcode (%lu)",
4294 (unsigned long) imm_expr
.X_add_number
);
4295 imm_expr
.X_add_number
&= 0x1f;
4297 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4298 imm_expr
.X_op
= O_absent
;
4302 case 'c': /* break code */
4303 my_getExpression (&imm_expr
, s
);
4304 check_absolute_expr (ip
, &imm_expr
);
4305 if ((unsigned) imm_expr
.X_add_number
> 1023)
4306 as_warn ("Illegal break code (%ld)",
4307 (long) imm_expr
.X_add_number
);
4308 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4309 imm_expr
.X_op
= O_absent
;
4313 case 'B': /* syscall code */
4314 my_getExpression (&imm_expr
, s
);
4315 check_absolute_expr (ip
, &imm_expr
);
4316 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4317 as_warn ("Illegal syscall code (%ld)",
4318 (long) imm_expr
.X_add_number
);
4319 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4320 imm_expr
.X_op
= O_absent
;
4324 case 'C': /* Coprocessor code */
4325 my_getExpression (&imm_expr
, s
);
4326 check_absolute_expr (ip
, &imm_expr
);
4327 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4329 as_warn ("Coproccesor code > 25 bits (%ld)",
4330 (long) imm_expr
.X_add_number
);
4331 imm_expr
.X_add_number
&= ((1<<25) - 1);
4333 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4334 imm_expr
.X_op
= O_absent
;
4338 case 'b': /* base register */
4339 case 'd': /* destination register */
4340 case 's': /* source register */
4341 case 't': /* target register */
4342 case 'r': /* both target and source */
4343 case 'v': /* both dest and source */
4344 case 'w': /* both dest and target */
4345 case 'E': /* coprocessor target register */
4346 case 'G': /* coprocessor destination register */
4347 case 'x': /* ignore register name */
4348 case 'z': /* must be zero register */
4362 while (isdigit (*s
));
4364 as_bad ("Invalid register number (%d)", regno
);
4366 else if (*args
== 'E' || *args
== 'G')
4370 if (s
[1] == 'f' && s
[2] == 'p')
4375 else if (s
[1] == 's' && s
[2] == 'p')
4380 else if (s
[1] == 'g' && s
[2] == 'p')
4385 else if (s
[1] == 'a' && s
[2] == 't')
4393 if (regno
== AT
&& ! mips_noat
)
4394 as_warn ("Used $at without \".set noat\"");
4400 if (c
== 'r' || c
== 'v' || c
== 'w')
4407 /* 'z' only matches $0. */
4408 if (c
== 'z' && regno
!= 0)
4416 ip
->insn_opcode
|= regno
<< 21;
4420 ip
->insn_opcode
|= regno
<< 11;
4425 ip
->insn_opcode
|= regno
<< 16;
4428 /* This case exists because on the r3000 trunc
4429 expands into a macro which requires a gp
4430 register. On the r6000 or r4000 it is
4431 assembled into a single instruction which
4432 ignores the register. Thus the insn version
4433 is MIPS_ISA2 and uses 'x', and the macro
4434 version is MIPS_ISA1 and uses 't'. */
4437 /* This case is for the div instruction, which
4438 acts differently if the destination argument
4439 is $0. This only matches $0, and is checked
4440 outside the switch. */
4451 ip
->insn_opcode
|= lastregno
<< 21;
4454 ip
->insn_opcode
|= lastregno
<< 16;
4459 case 'D': /* floating point destination register */
4460 case 'S': /* floating point source register */
4461 case 'T': /* floating point target register */
4465 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4475 while (isdigit (*s
));
4478 as_bad ("Invalid float register number (%d)", regno
);
4480 if ((regno
& 1) != 0
4482 && ! (strcmp (str
, "mtc1") == 0 ||
4483 strcmp (str
, "mfc1") == 0 ||
4484 strcmp (str
, "lwc1") == 0 ||
4485 strcmp (str
, "swc1") == 0))
4486 as_warn ("Float register should be even, was %d",
4494 if (c
== 'V' || c
== 'W')
4504 ip
->insn_opcode
|= regno
<< 6;
4508 ip
->insn_opcode
|= regno
<< 11;
4512 ip
->insn_opcode
|= regno
<< 16;
4520 ip
->insn_opcode
|= lastregno
<< 11;
4523 ip
->insn_opcode
|= lastregno
<< 16;
4529 my_getExpression (&imm_expr
, s
);
4530 if (imm_expr
.X_op
!= O_big
)
4531 check_absolute_expr (ip
, &imm_expr
);
4536 my_getExpression (&offset_expr
, s
);
4537 imm_reloc
= BFD_RELOC_32
;
4549 unsigned char temp
[8];
4551 unsigned int length
;
4556 /* These only appear as the last operand in an
4557 instruction, and every instruction that accepts
4558 them in any variant accepts them in all variants.
4559 This means we don't have to worry about backing out
4560 any changes if the instruction does not match.
4562 The difference between them is the size of the
4563 floating point constant and where it goes. For 'F'
4564 and 'L' the constant is 64 bits; for 'f' and 'l' it
4565 is 32 bits. Where the constant is placed is based
4566 on how the MIPS assembler does things:
4569 f -- immediate value
4572 The .lit4 and .lit8 sections are only used if
4573 permitted by the -G argument.
4575 When generating embedded PIC code, we use the
4576 .lit8 section but not the .lit4 section (we can do
4577 .lit4 inline easily; we need to put .lit8
4578 somewhere in the data segment, and using .lit8
4579 permits the linker to eventually combine identical
4582 f64
= *args
== 'F' || *args
== 'L';
4584 save_in
= input_line_pointer
;
4585 input_line_pointer
= s
;
4586 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4588 s
= input_line_pointer
;
4589 input_line_pointer
= save_in
;
4590 if (err
!= NULL
&& *err
!= '\0')
4592 as_bad ("Bad floating point constant: %s", err
);
4593 memset (temp
, '\0', sizeof temp
);
4594 length
= f64
? 8 : 4;
4597 assert (length
== (f64
? 8 : 4));
4601 && (mips_pic
== EMBEDDED_PIC
4603 || g_switch_value
< 4
4607 imm_expr
.X_op
= O_constant
;
4608 if (byte_order
== LITTLE_ENDIAN
)
4609 imm_expr
.X_add_number
=
4610 (((((((int) temp
[3] << 8)
4615 imm_expr
.X_add_number
=
4616 (((((((int) temp
[0] << 8)
4623 const char *newname
;
4626 /* Switch to the right section. */
4628 subseg
= now_subseg
;
4631 default: /* unused default case avoids warnings. */
4635 if (g_switch_value
< 8)
4636 newname
= RDATA_SECTION_NAME
;
4640 newname
= RDATA_SECTION_NAME
;
4644 assert (g_switch_value
>= 4);
4649 new_seg
= subseg_new (newname
, (subsegT
) 0);
4650 frag_align (*args
== 'l' ? 2 : 3, 0);
4652 record_alignment (new_seg
, 4);
4654 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4657 as_bad ("Can't use floating point insn in this section");
4659 /* Set the argument to the current address in the
4661 offset_expr
.X_op
= O_symbol
;
4662 offset_expr
.X_add_symbol
=
4663 symbol_new ("L0\001", now_seg
,
4664 (valueT
) frag_now_fix (), frag_now
);
4665 offset_expr
.X_add_number
= 0;
4667 /* Put the floating point number into the section. */
4668 p
= frag_more ((int) length
);
4669 memcpy (p
, temp
, length
);
4671 /* Switch back to the original section. */
4672 subseg_set (seg
, subseg
);
4677 case 'i': /* 16 bit unsigned immediate */
4678 case 'j': /* 16 bit signed immediate */
4679 imm_reloc
= BFD_RELOC_LO16
;
4680 c
= my_getSmallExpression (&imm_expr
, s
);
4685 if (imm_expr
.X_op
== O_constant
)
4686 imm_expr
.X_add_number
=
4687 (imm_expr
.X_add_number
>> 16) & 0xffff;
4689 imm_reloc
= BFD_RELOC_HI16_S
;
4691 imm_reloc
= BFD_RELOC_HI16
;
4694 else if (imm_expr
.X_op
!= O_big
)
4695 check_absolute_expr (ip
, &imm_expr
);
4698 if (imm_expr
.X_op
== O_big
4699 || imm_expr
.X_add_number
< 0
4700 || imm_expr
.X_add_number
>= 0x10000)
4702 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4703 !strcmp (insn
->name
, insn
[1].name
))
4705 as_bad ("16 bit expression not in range 0..65535");
4713 /* The upper bound should be 0x8000, but
4714 unfortunately the MIPS assembler accepts numbers
4715 from 0x8000 to 0xffff and sign extends them, and
4716 we want to be compatible. We only permit this
4717 extended range for an instruction which does not
4718 provide any further alternates, since those
4719 alternates may handle other cases. People should
4720 use the numbers they mean, rather than relying on
4721 a mysterious sign extension. */
4722 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4723 strcmp (insn
->name
, insn
[1].name
) == 0);
4728 if (imm_expr
.X_op
== O_big
4729 || imm_expr
.X_add_number
< -0x8000
4730 || imm_expr
.X_add_number
>= max
)
4734 as_bad ("16 bit expression not in range -32768..32767");
4740 case 'o': /* 16 bit offset */
4741 c
= my_getSmallExpression (&offset_expr
, s
);
4743 /* If this value won't fit into a 16 bit offset, then go
4744 find a macro that will generate the 32 bit offset
4745 code pattern. As a special hack, we accept the
4746 difference of two local symbols as a constant. This
4747 is required to suppose embedded PIC switches, which
4748 use an instruction which looks like
4749 lw $4,$L12-$LS12($4)
4750 The problem with handling this in a more general
4751 fashion is that the macro function doesn't expect to
4752 see anything which can be handled in a single
4753 constant instruction. */
4755 && (offset_expr
.X_op
!= O_constant
4756 || offset_expr
.X_add_number
>= 0x8000
4757 || offset_expr
.X_add_number
< -0x8000)
4758 && (mips_pic
!= EMBEDDED_PIC
4759 || offset_expr
.X_op
!= O_subtract
4760 || now_seg
!= text_section
4761 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4765 offset_reloc
= BFD_RELOC_LO16
;
4766 if (c
== 'h' || c
== 'H')
4768 assert (offset_expr
.X_op
== O_constant
);
4769 offset_expr
.X_add_number
=
4770 (offset_expr
.X_add_number
>> 16) & 0xffff;
4775 case 'p': /* pc relative offset */
4776 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4777 my_getExpression (&offset_expr
, s
);
4781 case 'u': /* upper 16 bits */
4782 c
= my_getSmallExpression (&imm_expr
, s
);
4783 if (imm_expr
.X_op
== O_constant
4784 && (imm_expr
.X_add_number
< 0
4785 || imm_expr
.X_add_number
>= 0x10000))
4786 as_bad ("lui expression not in range 0..65535");
4787 imm_reloc
= BFD_RELOC_LO16
;
4792 if (imm_expr
.X_op
== O_constant
)
4793 imm_expr
.X_add_number
=
4794 (imm_expr
.X_add_number
>> 16) & 0xffff;
4796 imm_reloc
= BFD_RELOC_HI16_S
;
4798 imm_reloc
= BFD_RELOC_HI16
;
4804 case 'a': /* 26 bit address */
4805 my_getExpression (&offset_expr
, s
);
4807 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4811 fprintf (stderr
, "bad char = '%c'\n", *args
);
4816 /* Args don't match. */
4817 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4818 !strcmp (insn
->name
, insn
[1].name
))
4824 insn_error
= "ERROR: Illegal operands";
4833 my_getSmallExpression (ep
, str
)
4844 ((str
[1] == 'h' && str
[2] == 'i')
4845 || (str
[1] == 'H' && str
[2] == 'I')
4846 || (str
[1] == 'l' && str
[2] == 'o'))
4858 * A small expression may be followed by a base register.
4859 * Scan to the end of this operand, and then back over a possible
4860 * base register. Then scan the small expression up to that
4861 * point. (Based on code in sparc.c...)
4863 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4865 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4867 if (isdigit (sp
[-2]))
4869 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4871 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4877 else if (sp
- 5 >= str
4880 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4881 || (sp
[-3] == 's' && sp
[-2] == 'p')
4882 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4883 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4889 /* no expression means zero offset */
4892 /* %xx(reg) is an error */
4893 ep
->X_op
= O_absent
;
4898 ep
->X_op
= O_constant
;
4901 ep
->X_add_symbol
= NULL
;
4902 ep
->X_op_symbol
= NULL
;
4903 ep
->X_add_number
= 0;
4908 my_getExpression (ep
, str
);
4915 my_getExpression (ep
, str
);
4916 return c
; /* => %hi or %lo encountered */
4920 my_getExpression (ep
, str
)
4926 save_in
= input_line_pointer
;
4927 input_line_pointer
= str
;
4929 expr_end
= input_line_pointer
;
4930 input_line_pointer
= save_in
;
4933 /* Turn a string in input_line_pointer into a floating point constant
4934 of type type, and store the appropriate bytes in *litP. The number
4935 of LITTLENUMS emitted is stored in *sizeP . An error message is
4936 returned, or NULL on OK. */
4939 md_atof (type
, litP
, sizeP
)
4945 LITTLENUM_TYPE words
[4];
4961 return "bad call to md_atof";
4964 t
= atof_ieee (input_line_pointer
, type
, words
);
4966 input_line_pointer
= t
;
4970 if (byte_order
== LITTLE_ENDIAN
)
4972 for (i
= prec
- 1; i
>= 0; i
--)
4974 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4980 for (i
= 0; i
< prec
; i
++)
4982 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4991 md_number_to_chars (buf
, val
, n
)
4999 number_to_chars_littleendian (buf
, val
, n
);
5003 number_to_chars_bigendian (buf
, val
, n
);
5012 CONST
char *md_shortopts
= "O::g::G:";
5014 CONST
char *md_shortopts
= "O::g::";
5016 struct option md_longopts
[] = {
5017 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5018 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5019 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5020 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5021 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5022 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5023 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5024 #define OPTION_MCPU (OPTION_MD_BASE + 4)
5025 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5026 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
5027 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5028 #define OPTION_TRAP (OPTION_MD_BASE + 8)
5029 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5030 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5031 #define OPTION_BREAK (OPTION_MD_BASE + 9)
5032 {"break", no_argument
, NULL
, OPTION_BREAK
},
5033 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5034 #define OPTION_EB (OPTION_MD_BASE + 10)
5035 {"EB", no_argument
, NULL
, OPTION_EB
},
5036 #define OPTION_EL (OPTION_MD_BASE + 11)
5037 {"EL", no_argument
, NULL
, OPTION_EL
},
5040 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
5041 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5042 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5043 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
5044 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5047 {NULL
, no_argument
, NULL
, 0}
5049 size_t md_longopts_size
= sizeof(md_longopts
);
5052 md_parse_option (c
, arg
)
5067 byte_order
= BIG_ENDIAN
;
5069 mips_target_format
= "a.out-mips-big";
5072 mips_target_format
= "ecoff-bigmips";
5075 mips_target_format
= "elf32-bigmips";
5080 byte_order
= LITTLE_ENDIAN
;
5082 mips_target_format
= "a.out-mips-little";
5085 mips_target_format
= "ecoff-littlemips";
5088 mips_target_format
= "elf32-littlemips";
5093 if (arg
&& arg
[1] == '0')
5100 if (arg
== NULL
|| arg
[1] == '2')
5126 /* Identify the processor type */
5128 if (strcmp (p
, "default") == 0
5129 || strcmp (p
, "DEFAULT") == 0)
5133 if (*p
== 'r' || *p
== 'R')
5140 if (strcmp (p
, "2000") == 0
5141 || strcmp (p
, "2k") == 0
5142 || strcmp (p
, "2K") == 0)
5147 if (strcmp (p
, "3000") == 0
5148 || strcmp (p
, "3k") == 0
5149 || strcmp (p
, "3K") == 0)
5154 if (strcmp (p
, "4000") == 0
5155 || strcmp (p
, "4k") == 0
5156 || strcmp (p
, "4K") == 0)
5158 else if (strcmp (p
, "4400") == 0)
5160 else if (strcmp (p
, "4600") == 0)
5165 if (strcmp (p
, "6000") == 0
5166 || strcmp (p
, "6k") == 0
5167 || strcmp (p
, "6K") == 0)
5172 if (strcmp (p
, "orion") == 0)
5179 as_bad ("invalid architecture -mcpu=%s", arg
);
5186 case OPTION_MEMBEDDED_PIC
:
5187 mips_pic
= EMBEDDED_PIC
;
5191 as_bad ("-G may not be used with embedded PIC code");
5194 g_switch_value
= 0x7fffffff;
5199 /* When generating ELF code, we permit -KPIC and -call_shared to
5200 select SVR4_PIC, and -non_shared to select no PIC. This is
5201 intended to be compatible with Irix 5. */
5202 case OPTION_CALL_SHARED
:
5203 mips_pic
= SVR4_PIC
;
5204 if (g_switch_seen
&& g_switch_value
!= 0)
5206 as_bad ("-G may not be used with SVR4 PIC code");
5212 case OPTION_NON_SHARED
:
5215 #endif /* OBJ_ELF */
5219 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5221 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5225 g_switch_value
= atoi (arg
);
5238 md_show_usage (stream
)
5243 -membedded-pic generate embedded position independent code\n\
5244 -EB generate big endian output\n\
5245 -EL generate little endian output\n\
5246 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5247 -G NUM allow referencing objects up to NUM bytes\n\
5248 implicitly with the gp register [default 8]\n");
5250 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5251 -mips2, -mcpu=r6000 generate code for r6000\n\
5252 -mips3, -mcpu=r4000 generate code for r4000\n\
5253 -O0 remove unneeded NOPs, do not swap branches\n\
5254 -O remove unneeded NOPs and swap branches\n\
5255 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5256 --break, --no-trap break exception on div by 0 and mult overflow\n");
5259 -KPIC, -call_shared generate SVR4 position independent code\n\
5260 -non_shared do not generate position independent code\n");
5265 md_pcrel_from (fixP
)
5269 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5270 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5272 /* This makes a branch to an undefined symbol be a branch to the
5273 current location. */
5278 /* return the address of the delay slot */
5279 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5282 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5283 reloc for a cons. We could use the definition there, except that
5284 we want to handle 64 bit relocs specially. */
5287 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5290 unsigned int nbytes
;
5293 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5295 FIXME: There is no way to select anything but 32 bit mode right
5299 if (byte_order
== BIG_ENDIAN
)
5304 if (nbytes
!= 2 && nbytes
!= 4)
5305 as_bad ("Unsupported reloc size %d", nbytes
);
5307 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5308 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5311 /* When generating embedded PIC code we need to use a special
5312 relocation to represent the difference of two symbols in the .text
5313 section (switch tables use a difference of this sort). See
5314 include/coff/mips.h for details. This macro checks whether this
5315 fixup requires the special reloc. */
5316 #define SWITCH_TABLE(fixp) \
5317 ((fixp)->fx_r_type == BFD_RELOC_32 \
5318 && (fixp)->fx_addsy != NULL \
5319 && (fixp)->fx_subsy != NULL \
5320 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5321 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5323 /* When generating embedded PIC code we must keep all PC relative
5324 relocations, in case the linker has to relax a call. We also need
5325 to keep relocations for switch table entries. */
5329 mips_force_relocation (fixp
)
5332 return (mips_pic
== EMBEDDED_PIC
5334 || SWITCH_TABLE (fixp
)
5335 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5336 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5339 /* Apply a fixup to the object file. */
5342 md_apply_fix (fixP
, valueP
)
5349 assert (fixP
->fx_size
== 4);
5352 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5354 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5357 switch (fixP
->fx_r_type
)
5359 case BFD_RELOC_MIPS_JMP
:
5360 case BFD_RELOC_HI16
:
5361 case BFD_RELOC_HI16_S
:
5362 case BFD_RELOC_MIPS_GPREL
:
5363 case BFD_RELOC_MIPS_LITERAL
:
5364 case BFD_RELOC_MIPS_CALL16
:
5365 case BFD_RELOC_MIPS_GOT16
:
5366 case BFD_RELOC_MIPS_GPREL32
:
5368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5369 "Invalid PC relative reloc");
5370 /* Nothing needed to do. The value comes from the reloc entry */
5373 case BFD_RELOC_PCREL_HI16_S
:
5374 /* The addend for this is tricky if it is internal, so we just
5375 do everything here rather than in bfd_perform_relocation. */
5376 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5378 /* For an external symbol adjust by the address to make it
5379 pcrel_offset. We use the address of the RELLO reloc
5380 which follows this one. */
5381 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5382 + fixP
->fx_next
->fx_where
);
5387 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5388 if (byte_order
== BIG_ENDIAN
)
5390 md_number_to_chars (buf
, value
, 2);
5393 case BFD_RELOC_PCREL_LO16
:
5394 /* The addend for this is tricky if it is internal, so we just
5395 do everything here rather than in bfd_perform_relocation. */
5396 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5397 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5398 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5399 if (byte_order
== BIG_ENDIAN
)
5401 md_number_to_chars (buf
, value
, 2);
5405 /* If we are deleting this reloc entry, we must fill in the
5406 value now. This can happen if we have a .word which is not
5407 resolved when it appears but is later defined. We also need
5408 to fill in the value if this is an embedded PIC switch table
5411 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5412 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5416 case BFD_RELOC_LO16
:
5417 /* When handling an embedded PIC switch statement, we can wind
5418 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5421 if (value
< -0x8000 || value
> 0x7fff)
5422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5423 "relocation overflow");
5424 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5425 if (byte_order
== BIG_ENDIAN
)
5427 md_number_to_chars (buf
, value
, 2);
5431 case BFD_RELOC_16_PCREL_S2
:
5433 * We need to save the bits in the instruction since fixup_segment()
5434 * might be deleting the relocation entry (i.e., a branch within
5435 * the current segment).
5438 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5439 "Branch to odd address (%lx)", value
);
5442 /* update old instruction data */
5443 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5447 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5451 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5459 if (value
>= -0x8000 && value
< 0x8000)
5460 insn
|= value
& 0xffff;
5463 /* The branch offset is too large. If this is an
5464 unconditional branch, and we are not generating PIC code,
5465 we can convert it to an absolute jump instruction. */
5466 if (mips_pic
== NO_PIC
5468 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5469 && (fixP
->fx_frag
->fr_address
5470 < text_section
->vma
+ text_section
->_raw_size
)
5471 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5472 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5473 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5475 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5476 insn
= 0x0c000000; /* jal */
5478 insn
= 0x08000000; /* j */
5479 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5481 fixP
->fx_addsy
= section_symbol (text_section
);
5482 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5486 /* FIXME. It would be possible in principle to handle
5487 conditional branches which overflow. They could be
5488 transformed into a branch around a jump. This would
5489 require setting up variant frags for each different
5490 branch type. The native MIPS assembler attempts to
5491 handle these cases, but it appears to do it
5493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5494 "Relocation overflow");
5498 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5513 const struct mips_opcode
*p
;
5514 int treg
, sreg
, dreg
, shamt
;
5519 for (i
= 0; i
< NUMOPCODES
; ++i
)
5521 p
= &mips_opcodes
[i
];
5522 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5524 printf ("%08lx %s\t", oc
, p
->name
);
5525 treg
= (oc
>> 16) & 0x1f;
5526 sreg
= (oc
>> 21) & 0x1f;
5527 dreg
= (oc
>> 11) & 0x1f;
5528 shamt
= (oc
>> 6) & 0x1f;
5530 for (args
= p
->args
;; ++args
)
5541 printf ("%c", *args
);
5545 assert (treg
== sreg
);
5546 printf ("$%d,$%d", treg
, sreg
);
5551 printf ("$%d", dreg
);
5556 printf ("$%d", treg
);
5560 printf ("0x%x", treg
);
5565 printf ("$%d", sreg
);
5569 printf ("0x%08lx", oc
& 0x1ffffff);
5581 printf ("$%d", shamt
);
5592 printf ("%08lx UNDEFINED\n", oc
);
5603 name
= input_line_pointer
;
5604 c
= get_symbol_end ();
5605 p
= (symbolS
*) symbol_find_or_make (name
);
5606 *input_line_pointer
= c
;
5610 /* Align the current frag to a given power of two. The MIPS assembler
5611 also automatically adjusts any preceding label. */
5614 mips_align (to
, fill
, label
)
5619 mips_emit_delays ();
5620 frag_align (to
, fill
);
5621 record_alignment (now_seg
, to
);
5624 assert (S_GET_SEGMENT (label
) == now_seg
);
5625 label
->sy_frag
= frag_now
;
5626 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5630 /* Align to a given power of two. .align 0 turns off the automatic
5631 alignment used by the data creating pseudo-ops. */
5638 register long temp_fill
;
5639 long max_alignment
= 15;
5643 o Note that the assembler pulls down any immediately preceeding label
5644 to the aligned address.
5645 o It's not documented but auto alignment is reinstated by
5646 a .align pseudo instruction.
5647 o Note also that after auto alignment is turned off the mips assembler
5648 issues an error on attempt to assemble an improperly aligned data item.
5653 temp
= get_absolute_expression ();
5654 if (temp
> max_alignment
)
5655 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5658 as_warn ("Alignment negative: 0 assumed.");
5661 if (*input_line_pointer
== ',')
5663 input_line_pointer
++;
5664 temp_fill
= get_absolute_expression ();
5671 mips_align (temp
, (int) temp_fill
, insn_label
);
5678 demand_empty_rest_of_line ();
5681 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5682 that there was a previous instruction. */
5685 s_stringer (append_zero
)
5688 mips_emit_delays ();
5690 stringer (append_zero
);
5701 /* When generating embedded PIC code, we only use the .text, .lit8,
5702 .sdata and .sbss sections. We change the .data and .rdata
5703 pseudo-ops to use .sdata. */
5704 if (mips_pic
== EMBEDDED_PIC
5705 && (sec
== 'd' || sec
== 'r'))
5708 mips_emit_delays ();
5718 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5719 demand_empty_rest_of_line ();
5724 seg
= subseg_new (RDATA_SECTION_NAME
,
5725 (subsegT
) get_absolute_expression ());
5727 bfd_set_section_flags (stdoutput
, seg
,
5733 bfd_set_section_alignment (stdoutput
, seg
, 4);
5735 demand_empty_rest_of_line ();
5736 #else /* ! defined (GPOPT) */
5737 as_bad ("No read only data section in this object file format");
5738 demand_empty_rest_of_line ();
5740 #endif /* ! defined (GPOPT) */
5745 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5747 bfd_set_section_flags (stdoutput
, seg
,
5748 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5749 bfd_set_section_alignment (stdoutput
, seg
, 4);
5751 demand_empty_rest_of_line ();
5753 #else /* ! defined (GPOPT) */
5754 as_bad ("Global pointers not supported; recompile -G 0");
5755 demand_empty_rest_of_line ();
5757 #endif /* ! defined (GPOPT) */
5765 /* Handle the ELF .section pseudo-op. This is a wrapper around
5772 mips_emit_delays ();
5773 obj_elf_section (x
);
5777 #endif /* OBJ_ELF */
5786 mips_emit_delays ();
5787 if (log_size
> 0 && auto_align
)
5788 mips_align (log_size
, 0, label
);
5790 cons (1 << log_size
);
5797 as_fatal ("Encountered `.err', aborting assembly");
5807 symbolP
= get_symbol ();
5808 if (*input_line_pointer
== ',')
5809 input_line_pointer
++;
5810 size
= get_absolute_expression ();
5811 S_SET_EXTERNAL (symbolP
);
5813 #ifdef ECOFF_DEBUGGING
5814 symbolP
->ecoff_extern_size
= size
;
5826 mips_emit_delays ();
5830 mips_align (3, 0, label
);
5832 mips_align (2, 0, label
);
5839 /* Handle .globl. We need to override it because on Irix 5 you are
5842 where foo is an undefined symbol, to mean that foo should be
5843 considered to be the address of a function. */
5853 name
= input_line_pointer
;
5854 c
= get_symbol_end ();
5855 symbolP
= symbol_find_or_make (name
);
5856 *input_line_pointer
= c
;
5858 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5863 secname
= input_line_pointer
;
5864 c
= get_symbol_end ();
5865 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5867 as_bad ("%s: no such section", secname
);
5868 *input_line_pointer
= c
;
5870 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5871 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5874 S_SET_EXTERNAL (symbolP
);
5875 demand_empty_rest_of_line ();
5885 opt
= input_line_pointer
;
5886 c
= get_symbol_end ();
5890 /* FIXME: What does this mean? */
5892 else if (strncmp (opt
, "pic", 3) == 0)
5900 mips_pic
= SVR4_PIC
;
5902 as_bad (".option pic%d not supported", i
);
5905 if (mips_pic
== SVR4_PIC
)
5907 if (g_switch_seen
&& g_switch_value
!= 0)
5908 as_warn ("-G may not be used with SVR4 PIC code");
5910 bfd_set_gp_size (stdoutput
, 0);
5915 as_warn ("Unrecognized option \"%s\"", opt
);
5917 *input_line_pointer
= c
;
5918 demand_empty_rest_of_line ();
5925 char *name
= input_line_pointer
, ch
;
5927 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5928 input_line_pointer
++;
5929 ch
= *input_line_pointer
;
5930 *input_line_pointer
= '\0';
5932 if (strcmp (name
, "reorder") == 0)
5936 prev_insn_unreordered
= 1;
5937 prev_prev_insn_unreordered
= 1;
5941 else if (strcmp (name
, "noreorder") == 0)
5943 mips_emit_delays ();
5945 mips_any_noreorder
= 1;
5947 else if (strcmp (name
, "at") == 0)
5951 else if (strcmp (name
, "noat") == 0)
5955 else if (strcmp (name
, "macro") == 0)
5957 mips_warn_about_macros
= 0;
5959 else if (strcmp (name
, "nomacro") == 0)
5961 if (mips_noreorder
== 0)
5962 as_bad ("`noreorder' must be set before `nomacro'");
5963 mips_warn_about_macros
= 1;
5965 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5969 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5973 else if (strcmp (name
, "bopt") == 0)
5977 else if (strcmp (name
, "nobopt") == 0)
5981 else if (strncmp (name
, "mips", 4) == 0)
5985 /* Permit the user to change the ISA on the fly. Needless to
5986 say, misuse can cause serious problems. */
5987 isa
= atoi (name
+ 4);
5989 mips_isa
= file_mips_isa
;
5990 else if (isa
< 1 || isa
> 3)
5991 as_bad ("unknown ISA level");
5997 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5999 *input_line_pointer
= ch
;
6000 demand_empty_rest_of_line ();
6003 /* The same as the usual .space directive, except that we have to
6004 forget about any previous instruction. */
6007 s_mips_space (param
)
6010 mips_emit_delays ();
6015 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6016 .option pic2. It means to generate SVR4 PIC calls. */
6022 mips_pic
= SVR4_PIC
;
6024 if (g_switch_seen
&& g_switch_value
!= 0)
6025 as_warn ("-G may not be used with SVR4 PIC code");
6028 bfd_set_gp_size (stdoutput
, 0);
6029 demand_empty_rest_of_line ();
6032 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6033 PIC code. It sets the $gp register for the function based on the
6034 function address, which is in the register named in the argument.
6035 This uses a relocation against _gp_disp, which is handled specially
6036 by the linker. The result is:
6037 lui $gp,%hi(_gp_disp)
6038 addiu $gp,$gp,%lo(_gp_disp)
6039 addu $gp,$gp,.cpload argument
6040 The .cpload argument is normally $25 == $t9. */
6049 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6050 if (mips_pic
!= SVR4_PIC
)
6056 /* .cpload should be a in .set noreorder section. */
6057 if (mips_noreorder
== 0)
6058 as_warn (".cpload not in noreorder section");
6061 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6062 ex
.X_op_symbol
= NULL
;
6063 ex
.X_add_number
= 0;
6065 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6066 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6067 (int) BFD_RELOC_LO16
);
6069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6070 GP
, GP
, tc_get_register (0));
6072 demand_empty_rest_of_line ();
6075 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6076 offset from $sp. The offset is remembered, and after making a PIC
6077 call $gp is restored from that location. */
6080 s_cprestore (ignore
)
6086 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6087 if (mips_pic
!= SVR4_PIC
)
6093 mips_cprestore_offset
= get_absolute_expression ();
6095 ex
.X_op
= O_constant
;
6096 ex
.X_add_symbol
= NULL
;
6097 ex
.X_op_symbol
= NULL
;
6098 ex
.X_add_number
= mips_cprestore_offset
;
6100 macro_build ((char *) NULL
, &icnt
, &ex
,
6101 mips_isa
< 3 ? "sw" : "sd",
6102 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6104 demand_empty_rest_of_line ();
6107 /* Handle the .gpword pseudo-op. This is used when generating PIC
6108 code. It generates a 32 bit GP relative reloc. */
6118 /* When not generating PIC code, this is treated as .word. */
6119 if (mips_pic
!= SVR4_PIC
)
6126 mips_emit_delays ();
6128 mips_align (2, 0, label
);
6133 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6135 as_bad ("Unsupported use of .gpword");
6136 ignore_rest_of_line ();
6140 md_number_to_chars (p
, (valueT
) 0, 4);
6141 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6142 BFD_RELOC_MIPS_GPREL32
);
6144 demand_empty_rest_of_line ();
6147 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6148 tables in SVR4 PIC code. */
6157 /* This is ignored when not generating SVR4 PIC code. */
6158 if (mips_pic
!= SVR4_PIC
)
6164 /* Add $gp to the register named as an argument. */
6165 reg
= tc_get_register (0);
6166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6167 mips_isa
< 3 ? "addu" : "daddu",
6168 "d,v,t", reg
, reg
, GP
);
6170 demand_empty_rest_of_line ();
6173 /* Parse a register string into a number. Called from the ECOFF code
6174 to parse .frame. The argument is non-zero if this is the frame
6175 register, so that we can record it in mips_frame_reg. */
6178 tc_get_register (frame
)
6184 if (*input_line_pointer
++ != '$')
6186 as_warn ("expected `$'");
6189 else if (isdigit ((unsigned char) *input_line_pointer
))
6191 reg
= get_absolute_expression ();
6192 if (reg
< 0 || reg
>= 32)
6194 as_warn ("Bad register number");
6200 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6202 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6204 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6206 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6210 as_warn ("Unrecognized register name");
6213 input_line_pointer
+= 2;
6216 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6221 md_section_align (seg
, addr
)
6225 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6227 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6230 /* Estimate the size of a frag before relaxing. We are not really
6231 relaxing here, and the final size is encoded in the subtype
6236 md_estimate_size_before_relax (fragp
, segtype
)
6242 if (mips_pic
== NO_PIC
)
6245 const char *symname
;
6247 /* Find out whether this symbol can be referenced off the GP
6248 register. It can be if it is smaller than the -G size or if
6249 it is in the .sdata or .sbss section. Certain symbols can
6250 not be referenced off the GP, although it appears as though
6252 symname
= S_GET_NAME (fragp
->fr_symbol
);
6253 if (symname
!= (const char *) NULL
6254 && (strcmp (symname
, "eprol") == 0
6255 || strcmp (symname
, "etext") == 0
6256 || strcmp (symname
, "_gp") == 0
6257 || strcmp (symname
, "edata") == 0
6258 || strcmp (symname
, "_fbss") == 0
6259 || strcmp (symname
, "_fdata") == 0
6260 || strcmp (symname
, "_ftext") == 0
6261 || strcmp (symname
, "end") == 0
6262 || strcmp (symname
, "_gp_disp") == 0))
6264 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6265 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6266 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6267 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6268 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6272 const char *segname
;
6274 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6275 assert (strcmp (segname
, ".lit8") != 0
6276 && strcmp (segname
, ".lit4") != 0);
6277 change
= (strcmp (segname
, ".sdata") != 0
6278 && strcmp (segname
, ".sbss") != 0);
6280 #else /* ! defined (GPOPT) */
6281 /* We are not optimizing for the GP register. */
6283 #endif /* ! defined (GPOPT) */
6285 else if (mips_pic
== SVR4_PIC
)
6287 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6289 /* This must duplicate the test in adjust_reloc_syms. */
6290 change
= (symsec
!= &bfd_und_section
6291 && symsec
!= &bfd_abs_section
6292 && ! bfd_is_com_section (symsec
));
6299 /* Record the offset to the first reloc in the fr_opcode field.
6300 This lets md_convert_frag and tc_gen_reloc know that the code
6301 must be expanded. */
6302 fragp
->fr_opcode
= (fragp
->fr_literal
6304 - RELAX_OLD (fragp
->fr_subtype
)
6305 + RELAX_RELOC1 (fragp
->fr_subtype
));
6306 /* FIXME: This really needs as_warn_where. */
6307 if (RELAX_WARN (fragp
->fr_subtype
))
6308 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6314 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6317 /* Translate internal representation of relocation info to BFD target
6321 tc_gen_reloc (section
, fixp
)
6325 static arelent
*retval
[4];
6328 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6331 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6332 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6334 if (mips_pic
== EMBEDDED_PIC
6335 && SWITCH_TABLE (fixp
))
6337 /* For a switch table entry we use a special reloc. The addend
6338 is actually the difference between the reloc address and the
6340 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6342 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6344 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6346 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6348 /* We use a special addend for an internal RELLO reloc. */
6349 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6350 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6352 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6354 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6356 assert (fixp
->fx_next
!= NULL
6357 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6358 /* We use a special addend for an internal RELHI reloc. The
6359 reloc is relative to the RELLO; adjust the addend
6361 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6362 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6363 + fixp
->fx_next
->fx_where
6364 - S_GET_VALUE (fixp
->fx_subsy
));
6366 reloc
->addend
= (fixp
->fx_addnumber
6367 + fixp
->fx_next
->fx_frag
->fr_address
6368 + fixp
->fx_next
->fx_where
);
6370 else if (fixp
->fx_pcrel
== 0)
6371 reloc
->addend
= fixp
->fx_addnumber
;
6375 /* A gruesome hack which is a result of the gruesome gas reloc
6377 reloc
->addend
= reloc
->address
;
6379 reloc
->addend
= -reloc
->address
;
6383 /* If this is a variant frag, we may need to adjust the existing
6384 reloc and generate a new one. */
6385 if (fixp
->fx_frag
->fr_opcode
!= NULL
6386 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6387 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6388 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6392 /* If this is not the last reloc in this frag, then we have two
6393 GPREL relocs, both of which are being replaced. Let the
6394 second one handle all of them. */
6395 if (fixp
->fx_next
!= NULL
6396 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6398 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6399 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6404 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6405 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6406 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6408 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6409 reloc2
->address
= (reloc
->address
6410 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6411 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6412 reloc2
->addend
= fixp
->fx_addnumber
;
6413 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6414 assert (reloc2
->howto
!= NULL
);
6416 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6420 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6423 reloc3
->address
+= 4;
6426 if (mips_pic
== NO_PIC
)
6428 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6429 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6431 else if (mips_pic
== SVR4_PIC
)
6433 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6435 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6436 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6443 /* To support a PC relative reloc when generating embedded PIC code
6444 for ECOFF, we use a Cygnus extension. We check for that here to
6445 make sure that we don't let such a reloc escape normally. */
6447 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6448 && mips_pic
!= EMBEDDED_PIC
)
6449 reloc
->howto
= NULL
;
6452 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6454 if (reloc
->howto
== NULL
)
6456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6457 "Can not represent relocation in this object file format");
6464 /* Convert a machine dependent frag. */
6467 md_convert_frag (abfd
, asec
, fragp
)
6475 if (fragp
->fr_opcode
== NULL
)
6478 old
= RELAX_OLD (fragp
->fr_subtype
);
6479 new = RELAX_NEW (fragp
->fr_subtype
);
6480 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6483 memcpy (fixptr
- old
, fixptr
, new);
6485 fragp
->fr_fix
+= new - old
;
6488 /* This function is called whenever a label is defined. It is used
6489 when handling branch delays; if a branch has a label, we assume we
6493 mips_define_label (sym
)
6501 /* Some special processing for a MIPS ELF file. */
6504 mips_elf_final_processing ()
6508 /* Write out the .reginfo section. */
6509 s
.ri_gprmask
= mips_gprmask
;
6510 s
.ri_cprmask
[0] = mips_cprmask
[0];
6511 s
.ri_cprmask
[1] = mips_cprmask
[1];
6512 s
.ri_cprmask
[2] = mips_cprmask
[2];
6513 s
.ri_cprmask
[3] = mips_cprmask
[3];
6514 /* The gp_value field is set by the MIPS ELF backend. */
6516 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6517 ((Elf32_External_RegInfo
*)
6518 mips_regmask_frag
));
6520 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6521 sort of BFD interface for this. */
6522 if (mips_any_noreorder
)
6523 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6524 if (mips_pic
!= NO_PIC
)
6525 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6528 #endif /* OBJ_ELF */
6530 #ifndef ECOFF_DEBUGGING
6532 /* These functions should really be defined by the object file format,
6533 since they are related to debugging information. However, this
6534 code has to work for the a.out format, which does not define them,
6535 so we provide simple versions here. These don't actually generate
6536 any debugging information, but they do simple checking and someday
6537 somebody may make them useful. */
6541 struct loc
*loc_next
;
6542 unsigned long loc_fileno
;
6543 unsigned long loc_lineno
;
6544 unsigned long loc_offset
;
6545 unsigned short loc_delta
;
6546 unsigned short loc_count
;
6555 struct proc
*proc_next
;
6556 struct symbol
*proc_isym
;
6557 struct symbol
*proc_end
;
6558 unsigned long proc_reg_mask
;
6559 unsigned long proc_reg_offset
;
6560 unsigned long proc_fpreg_mask
;
6561 unsigned long proc_fpreg_offset
;
6562 unsigned long proc_frameoffset
;
6563 unsigned long proc_framereg
;
6564 unsigned long proc_pcreg
;
6566 struct file
*proc_file
;
6573 struct file
*file_next
;
6574 unsigned long file_fileno
;
6575 struct symbol
*file_symbol
;
6576 struct symbol
*file_end
;
6577 struct proc
*file_proc
;
6582 static struct obstack proc_frags
;
6583 static procS
*proc_lastP
;
6584 static procS
*proc_rootP
;
6585 static int numprocs
;
6590 obstack_begin (&proc_frags
, 0x2000);
6596 /* check for premature end, nesting errors, etc */
6597 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6598 as_warn ("missing `.end' at end of assembly");
6601 extern char hex_value
[];
6609 if (*input_line_pointer
== '-')
6611 ++input_line_pointer
;
6614 if (!isdigit (*input_line_pointer
))
6615 as_bad ("Expected simple number.");
6616 if (input_line_pointer
[0] == '0')
6618 if (input_line_pointer
[1] == 'x')
6620 input_line_pointer
+= 2;
6621 while (isxdigit (*input_line_pointer
))
6624 val
|= hex_value
[(int) *input_line_pointer
++];
6626 return negative
? -val
: val
;
6630 ++input_line_pointer
;
6631 while (isdigit (*input_line_pointer
))
6634 val
|= *input_line_pointer
++ - '0';
6636 return negative
? -val
: val
;
6639 if (!isdigit (*input_line_pointer
))
6641 printf (" *input_line_pointer == '%c' 0x%02x\n",
6642 *input_line_pointer
, *input_line_pointer
);
6643 as_warn ("Invalid number");
6646 while (isdigit (*input_line_pointer
))
6649 val
+= *input_line_pointer
++ - '0';
6651 return negative
? -val
: val
;
6654 /* The .file directive; just like the usual .file directive, but there
6655 is an initial number which is the ECOFF file index. */
6663 line
= get_number ();
6668 /* The .end directive. */
6676 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6679 demand_empty_rest_of_line ();
6683 if (now_seg
!= text_section
)
6684 as_warn (".end not in text section");
6687 as_warn (".end and no .ent seen yet.");
6693 assert (S_GET_NAME (p
));
6694 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6695 as_warn (".end symbol does not match .ent symbol.");
6698 proc_lastP
->proc_end
= (symbolS
*) 1;
6701 /* The .aent and .ent directives. */
6711 symbolP
= get_symbol ();
6712 if (*input_line_pointer
== ',')
6713 input_line_pointer
++;
6715 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6716 number
= get_number ();
6717 if (now_seg
!= text_section
)
6718 as_warn (".ent or .aent not in text section.");
6720 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6721 as_warn ("missing `.end'");
6725 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6726 procP
->proc_isym
= symbolP
;
6727 procP
->proc_reg_mask
= 0;
6728 procP
->proc_reg_offset
= 0;
6729 procP
->proc_fpreg_mask
= 0;
6730 procP
->proc_fpreg_offset
= 0;
6731 procP
->proc_frameoffset
= 0;
6732 procP
->proc_framereg
= 0;
6733 procP
->proc_pcreg
= 0;
6734 procP
->proc_end
= NULL
;
6735 procP
->proc_next
= NULL
;
6737 proc_lastP
->proc_next
= procP
;
6743 demand_empty_rest_of_line ();
6746 /* The .frame directive. */
6759 frame_reg
= tc_get_register (1);
6760 if (*input_line_pointer
== ',')
6761 input_line_pointer
++;
6762 frame_off
= get_absolute_expression ();
6763 if (*input_line_pointer
== ',')
6764 input_line_pointer
++;
6765 pcreg
= tc_get_register (0);
6768 assert (proc_rootP
);
6769 proc_rootP
->proc_framereg
= frame_reg
;
6770 proc_rootP
->proc_frameoffset
= frame_off
;
6771 proc_rootP
->proc_pcreg
= pcreg
;
6772 /* bob macho .frame */
6774 /* We don't have to write out a frame stab for unoptimized code. */
6775 if (!(frame_reg
== FP
&& frame_off
== 0))
6778 as_warn ("No .ent for .frame to use.");
6779 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6780 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6781 S_SET_TYPE (symP
, N_RMASK
);
6782 S_SET_OTHER (symP
, 0);
6783 S_SET_DESC (symP
, 0);
6784 symP
->sy_forward
= proc_lastP
->proc_isym
;
6785 /* bob perhaps I should have used pseudo set */
6787 demand_empty_rest_of_line ();
6791 /* The .fmask and .mask directives. */
6798 char str
[100], *strP
;
6804 mask
= get_number ();
6805 if (*input_line_pointer
== ',')
6806 input_line_pointer
++;
6807 off
= get_absolute_expression ();
6809 /* bob only for coff */
6810 assert (proc_rootP
);
6811 if (reg_type
== 'F')
6813 proc_rootP
->proc_fpreg_mask
= mask
;
6814 proc_rootP
->proc_fpreg_offset
= off
;
6818 proc_rootP
->proc_reg_mask
= mask
;
6819 proc_rootP
->proc_reg_offset
= off
;
6822 /* bob macho .mask + .fmask */
6824 /* We don't have to write out a mask stab if no saved regs. */
6828 as_warn ("No .ent for .mask to use.");
6830 for (i
= 0; i
< 32; i
++)
6834 sprintf (strP
, "%c%d,", reg_type
, i
);
6835 strP
+= strlen (strP
);
6839 sprintf (strP
, ";%d,", off
);
6840 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6841 S_SET_TYPE (symP
, N_RMASK
);
6842 S_SET_OTHER (symP
, 0);
6843 S_SET_DESC (symP
, 0);
6844 symP
->sy_forward
= proc_lastP
->proc_isym
;
6845 /* bob perhaps I should have used pseudo set */
6850 /* The .loc directive. */
6861 assert (now_seg
== text_section
);
6863 lineno
= get_number ();
6864 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6866 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6867 S_SET_TYPE (symbolP
, N_SLINE
);
6868 S_SET_OTHER (symbolP
, 0);
6869 S_SET_DESC (symbolP
, lineno
);
6870 symbolP
->sy_segment
= now_seg
;
6874 #endif /* ! defined (ECOFF_DEBUGGING) */