1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_coff_flavour
:
123 case bfd_target_elf_flavour
:
124 return (target_big_endian
125 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
126 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
133 /* The name of the readonly data section. */
134 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
136 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
138 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
140 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
144 /* This is the set of options which may be modified by the .set
145 pseudo-op. We use a struct so that .set push and .set pop are more
148 struct mips_set_options
150 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
151 if it has not been initialized. Changed by `.set mipsN', and the
152 -mipsN command line option, and the default CPU. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa and mips16 fields to -1 to indicate that
184 they have not been initialized. */
186 static struct mips_set_options mips_opts
= { -1, -1 };
188 /* These variables are filled in with the masks of registers used.
189 The object format code reads them and puts them in the appropriate
191 unsigned long mips_gprmask
;
192 unsigned long mips_cprmask
[4];
194 /* MIPS ISA we are using for this output file. */
195 static int file_mips_isa
;
197 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
198 static int mips_cpu
= -1;
200 /* The argument of the -mabi= flag. */
201 static char* mips_abi_string
= 0;
203 /* Wether we should mark the file EABI64 or EABI32. */
204 static int mips_eabi64
= 0;
206 /* If they asked for mips1 or mips2 and a cpu that is
207 mips3 or greater, then mark the object file 32BITMODE. */
208 static int mips_32bitmode
= 0;
210 /* True if -mgp32 was passed. */
211 static int mips_gp32
= 0;
213 /* Some ISA's have delay slots for instructions which read or write
214 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
215 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
216 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
217 delay slot in this ISA. The uses of this macro assume that any
218 ISA that has delay slots for one of these, has them for all. They
219 also assume that ISAs which don't have delays for these insns, don't
220 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
221 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 /* Return true if ISA supports 64 bit gp register instructions. */
228 #define ISA_HAS_64BIT_REGS(ISA) ( \
233 /* Whether the processor uses hardware interlocks to protect
234 reads from the HI and LO registers, and thus does not
235 require nops to be inserted.
237 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
238 -mcpu=FOO schedules for FOO, but still produces code that meets the
239 requirements of MIPS ISA I. For example, it won't generate any
240 FOO-specific instructions, and it will still assume that any
241 scheduling hazards described in MIPS ISA I are there, even if FOO
242 has interlocks. -mFOO gives GCC permission to generate code that
243 will only run on a FOO; it will generate FOO-specific instructions,
244 and assume interlocks provided by a FOO.
246 However, GAS currently doesn't make this distinction; before Jan 28
247 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
248 assumptions. The GCC driver passes these flags through to GAS, so
249 if GAS actually does anything that doesn't meet MIPS ISA I with
250 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
252 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
253 which seems senseless --- why generate code which will only run on
254 a FOO, but schedule for something else?
256 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
258 -- Jim Blandy <jimb@cygnus.com> */
260 #define hilo_interlocks (mips_cpu == 4010 \
263 /* Whether the processor uses hardware interlocks to protect reads
264 from the GPRs, and thus does not require nops to be inserted. */
265 #define gpr_interlocks \
266 (mips_opts.isa != 1 \
269 /* As with other "interlocks" this is used by hardware that has FP
270 (co-processor) interlocks. */
271 /* Itbl support may require additional care here. */
272 #define cop_interlocks (mips_cpu == 4300 \
275 /* Is this a mfhi or mflo instruction? */
276 #define MF_HILO_INSN(PINFO) \
277 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
279 /* MIPS PIC level. */
283 /* Do not generate PIC code. */
286 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
287 not sure what it is supposed to do. */
290 /* Generate PIC code as in the SVR4 MIPS ABI. */
293 /* Generate PIC code without using a global offset table: the data
294 segment has a maximum size of 64K, all data references are off
295 the $gp register, and all text references are PC relative. This
296 is used on some embedded systems. */
300 static enum mips_pic_level mips_pic
;
302 /* 1 if we should generate 32 bit offsets from the GP register in
303 SVR4_PIC mode. Currently has no meaning in other modes. */
304 static int mips_big_got
;
306 /* 1 if trap instructions should used for overflow rather than break
308 static int mips_trap
;
310 /* Non-zero if any .set noreorder directives were used. */
312 static int mips_any_noreorder
;
314 /* Non-zero if nops should be inserted when the register referenced in
315 an mfhi/mflo instruction is read in the next two instructions. */
316 static int mips_7000_hilo_fix
;
318 /* The size of the small data section. */
319 static int g_switch_value
= 8;
320 /* Whether the -G option was used. */
321 static int g_switch_seen
= 0;
326 /* If we can determine in advance that GP optimization won't be
327 possible, we can skip the relaxation stuff that tries to produce
328 GP-relative references. This makes delay slot optimization work
331 This function can only provide a guess, but it seems to work for
332 gcc output. It needs to guess right for gcc, otherwise gcc
333 will put what it thinks is a GP-relative instruction in a branch
336 I don't know if a fix is needed for the SVR4_PIC mode. I've only
337 fixed it for the non-PIC mode. KR 95/04/07 */
338 static int nopic_need_relax
PARAMS ((symbolS
*, int));
340 /* handle of the OPCODE hash table */
341 static struct hash_control
*op_hash
= NULL
;
343 /* The opcode hash table we use for the mips16. */
344 static struct hash_control
*mips16_op_hash
= NULL
;
346 /* This array holds the chars that always start a comment. If the
347 pre-processor is disabled, these aren't very useful */
348 const char comment_chars
[] = "#";
350 /* This array holds the chars that only start a comment at the beginning of
351 a line. If the line seems to have the form '# 123 filename'
352 .line and .file directives will appear in the pre-processed output */
353 /* Note that input_file.c hand checks for '#' at the beginning of the
354 first line of the input file. This is because the compiler outputs
355 #NO_APP at the beginning of its output. */
356 /* Also note that C style comments are always supported. */
357 const char line_comment_chars
[] = "#";
359 /* This array holds machine specific line separator characters. */
360 const char line_separator_chars
[] = "";
362 /* Chars that can be used to separate mant from exp in floating point nums */
363 const char EXP_CHARS
[] = "eE";
365 /* Chars that mean this number is a floating point constant */
368 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
370 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
371 changed in read.c . Ideally it shouldn't have to know about it at all,
372 but nothing is ideal around here.
375 static char *insn_error
;
377 static int auto_align
= 1;
379 /* When outputting SVR4 PIC code, the assembler needs to know the
380 offset in the stack frame from which to restore the $gp register.
381 This is set by the .cprestore pseudo-op, and saved in this
383 static offsetT mips_cprestore_offset
= -1;
385 /* This is the register which holds the stack frame, as set by the
386 .frame pseudo-op. This is needed to implement .cprestore. */
387 static int mips_frame_reg
= SP
;
389 /* To output NOP instructions correctly, we need to keep information
390 about the previous two instructions. */
392 /* Whether we are optimizing. The default value of 2 means to remove
393 unneeded NOPs and swap branch instructions when possible. A value
394 of 1 means to not swap branches. A value of 0 means to always
396 static int mips_optimize
= 2;
398 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
399 equivalent to seeing no -g option at all. */
400 static int mips_debug
= 0;
402 /* The previous instruction. */
403 static struct mips_cl_insn prev_insn
;
405 /* The instruction before prev_insn. */
406 static struct mips_cl_insn prev_prev_insn
;
408 /* If we don't want information for prev_insn or prev_prev_insn, we
409 point the insn_mo field at this dummy integer. */
410 static const struct mips_opcode dummy_opcode
= { 0 };
412 /* Non-zero if prev_insn is valid. */
413 static int prev_insn_valid
;
415 /* The frag for the previous instruction. */
416 static struct frag
*prev_insn_frag
;
418 /* The offset into prev_insn_frag for the previous instruction. */
419 static long prev_insn_where
;
421 /* The reloc type for the previous instruction, if any. */
422 static bfd_reloc_code_real_type prev_insn_reloc_type
;
424 /* The reloc for the previous instruction, if any. */
425 static fixS
*prev_insn_fixp
;
427 /* Non-zero if the previous instruction was in a delay slot. */
428 static int prev_insn_is_delay_slot
;
430 /* Non-zero if the previous instruction was in a .set noreorder. */
431 static int prev_insn_unreordered
;
433 /* Non-zero if the previous instruction uses an extend opcode (if
435 static int prev_insn_extended
;
437 /* Non-zero if the previous previous instruction was in a .set
439 static int prev_prev_insn_unreordered
;
441 /* If this is set, it points to a frag holding nop instructions which
442 were inserted before the start of a noreorder section. If those
443 nops turn out to be unnecessary, the size of the frag can be
445 static fragS
*prev_nop_frag
;
447 /* The number of nop instructions we created in prev_nop_frag. */
448 static int prev_nop_frag_holds
;
450 /* The number of nop instructions that we know we need in
452 static int prev_nop_frag_required
;
454 /* The number of instructions we've seen since prev_nop_frag. */
455 static int prev_nop_frag_since
;
457 /* For ECOFF and ELF, relocations against symbols are done in two
458 parts, with a HI relocation and a LO relocation. Each relocation
459 has only 16 bits of space to store an addend. This means that in
460 order for the linker to handle carries correctly, it must be able
461 to locate both the HI and the LO relocation. This means that the
462 relocations must appear in order in the relocation table.
464 In order to implement this, we keep track of each unmatched HI
465 relocation. We then sort them so that they immediately precede the
466 corresponding LO relocation. */
471 struct mips_hi_fixup
*next
;
474 /* The section this fixup is in. */
478 /* The list of unmatched HI relocs. */
480 static struct mips_hi_fixup
*mips_hi_fixup_list
;
482 /* Map normal MIPS register numbers to mips16 register numbers. */
484 #define X ILLEGAL_REG
485 static const int mips32_to_16_reg_map
[] =
487 X
, X
, 2, 3, 4, 5, 6, 7,
488 X
, X
, X
, X
, X
, X
, X
, X
,
489 0, 1, X
, X
, X
, X
, X
, X
,
490 X
, X
, X
, X
, X
, X
, X
, X
494 /* Map mips16 register numbers to normal MIPS register numbers. */
496 static const int mips16_to_32_reg_map
[] =
498 16, 17, 2, 3, 4, 5, 6, 7
501 /* Since the MIPS does not have multiple forms of PC relative
502 instructions, we do not have to do relaxing as is done on other
503 platforms. However, we do have to handle GP relative addressing
504 correctly, which turns out to be a similar problem.
506 Every macro that refers to a symbol can occur in (at least) two
507 forms, one with GP relative addressing and one without. For
508 example, loading a global variable into a register generally uses
509 a macro instruction like this:
511 If i can be addressed off the GP register (this is true if it is in
512 the .sbss or .sdata section, or if it is known to be smaller than
513 the -G argument) this will generate the following instruction:
515 This instruction will use a GPREL reloc. If i can not be addressed
516 off the GP register, the following instruction sequence will be used:
519 In this case the first instruction will have a HI16 reloc, and the
520 second reloc will have a LO16 reloc. Both relocs will be against
523 The issue here is that we may not know whether i is GP addressable
524 until after we see the instruction that uses it. Therefore, we
525 want to be able to choose the final instruction sequence only at
526 the end of the assembly. This is similar to the way other
527 platforms choose the size of a PC relative instruction only at the
530 When generating position independent code we do not use GP
531 addressing in quite the same way, but the issue still arises as
532 external symbols and local symbols must be handled differently.
534 We handle these issues by actually generating both possible
535 instruction sequences. The longer one is put in a frag_var with
536 type rs_machine_dependent. We encode what to do with the frag in
537 the subtype field. We encode (1) the number of existing bytes to
538 replace, (2) the number of new bytes to use, (3) the offset from
539 the start of the existing bytes to the first reloc we must generate
540 (that is, the offset is applied from the start of the existing
541 bytes after they are replaced by the new bytes, if any), (4) the
542 offset from the start of the existing bytes to the second reloc,
543 (5) whether a third reloc is needed (the third reloc is always four
544 bytes after the second reloc), and (6) whether to warn if this
545 variant is used (this is sometimes needed if .set nomacro or .set
546 noat is in effect). All these numbers are reasonably small.
548 Generating two instruction sequences must be handled carefully to
549 ensure that delay slots are handled correctly. Fortunately, there
550 are a limited number of cases. When the second instruction
551 sequence is generated, append_insn is directed to maintain the
552 existing delay slot information, so it continues to apply to any
553 code after the second instruction sequence. This means that the
554 second instruction sequence must not impose any requirements not
555 required by the first instruction sequence.
557 These variant frags are then handled in functions called by the
558 machine independent code. md_estimate_size_before_relax returns
559 the final size of the frag. md_convert_frag sets up the final form
560 of the frag. tc_gen_reloc adjust the first reloc and adds a second
562 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
566 | (((reloc1) + 64) << 9) \
567 | (((reloc2) + 64) << 2) \
568 | ((reloc3) ? (1 << 1) : 0) \
570 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
571 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
572 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
573 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
574 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
575 #define RELAX_WARN(i) ((i) & 1)
577 /* For mips16 code, we use an entirely different form of relaxation.
578 mips16 supports two versions of most instructions which take
579 immediate values: a small one which takes some small value, and a
580 larger one which takes a 16 bit value. Since branches also follow
581 this pattern, relaxing these values is required.
583 We can assemble both mips16 and normal MIPS code in a single
584 object. Therefore, we need to support this type of relaxation at
585 the same time that we support the relaxation described above. We
586 use the high bit of the subtype field to distinguish these cases.
588 The information we store for this type of relaxation is the
589 argument code found in the opcode file for this relocation, whether
590 the user explicitly requested a small or extended form, and whether
591 the relocation is in a jump or jal delay slot. That tells us the
592 size of the value, and how it should be stored. We also store
593 whether the fragment is considered to be extended or not. We also
594 store whether this is known to be a branch to a different section,
595 whether we have tried to relax this frag yet, and whether we have
596 ever extended a PC relative fragment because of a shift count. */
597 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
600 | ((small) ? 0x100 : 0) \
601 | ((ext) ? 0x200 : 0) \
602 | ((dslot) ? 0x400 : 0) \
603 | ((jal_dslot) ? 0x800 : 0))
604 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
605 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
606 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
607 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
608 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
609 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
610 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
611 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
612 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
613 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
614 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
615 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
617 /* Prototypes for static functions. */
620 #define internalError() \
621 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
623 #define internalError() as_fatal (_("MIPS internal Error"));
626 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
628 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
629 unsigned int reg
, enum mips_regclass
class));
630 static int reg_needs_delay
PARAMS ((int));
631 static void mips16_mark_labels
PARAMS ((void));
632 static void append_insn
PARAMS ((char *place
,
633 struct mips_cl_insn
* ip
,
635 bfd_reloc_code_real_type r
,
637 static void mips_no_prev_insn
PARAMS ((int));
638 static void mips_emit_delays
PARAMS ((boolean
));
640 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
641 const char *name
, const char *fmt
,
644 static void macro_build ();
646 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
647 const char *, const char *,
649 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
650 expressionS
* ep
, int regnum
));
651 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
652 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
654 static void load_register
PARAMS ((int *, int, expressionS
*, int));
655 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
656 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
657 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
658 #ifdef LOSING_COMPILER
659 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
661 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
662 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
663 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
664 boolean
, boolean
, unsigned long *,
665 boolean
*, unsigned short *));
666 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
667 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
668 static symbolS
*get_symbol
PARAMS ((void));
669 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
670 static void s_align
PARAMS ((int));
671 static void s_change_sec
PARAMS ((int));
672 static void s_cons
PARAMS ((int));
673 static void s_float_cons
PARAMS ((int));
674 static void s_mips_globl
PARAMS ((int));
675 static void s_option
PARAMS ((int));
676 static void s_mipsset
PARAMS ((int));
677 static void s_abicalls
PARAMS ((int));
678 static void s_cpload
PARAMS ((int));
679 static void s_cprestore
PARAMS ((int));
680 static void s_gpword
PARAMS ((int));
681 static void s_cpadd
PARAMS ((int));
682 static void s_insn
PARAMS ((int));
683 static void md_obj_begin
PARAMS ((void));
684 static void md_obj_end
PARAMS ((void));
685 static long get_number
PARAMS ((void));
686 static void s_mips_ent
PARAMS ((int));
687 static void s_mips_end
PARAMS ((int));
688 static void s_mips_frame
PARAMS ((int));
689 static void s_mips_mask
PARAMS ((int));
690 static void s_mips_stab
PARAMS ((int));
691 static void s_mips_weakext
PARAMS ((int));
692 static void s_file
PARAMS ((int));
693 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
696 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
700 The following pseudo-ops from the Kane and Heinrich MIPS book
701 should be defined here, but are currently unsupported: .alias,
702 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
704 The following pseudo-ops from the Kane and Heinrich MIPS book are
705 specific to the type of debugging information being generated, and
706 should be defined by the object format: .aent, .begin, .bend,
707 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
710 The following pseudo-ops from the Kane and Heinrich MIPS book are
711 not MIPS CPU specific, but are also not specific to the object file
712 format. This file is probably the best place to define them, but
713 they are not currently supported: .asm0, .endr, .lab, .repeat,
716 static const pseudo_typeS mips_pseudo_table
[] =
718 /* MIPS specific pseudo-ops. */
719 {"option", s_option
, 0},
720 {"set", s_mipsset
, 0},
721 {"rdata", s_change_sec
, 'r'},
722 {"sdata", s_change_sec
, 's'},
723 {"livereg", s_ignore
, 0},
724 {"abicalls", s_abicalls
, 0},
725 {"cpload", s_cpload
, 0},
726 {"cprestore", s_cprestore
, 0},
727 {"gpword", s_gpword
, 0},
728 {"cpadd", s_cpadd
, 0},
731 /* Relatively generic pseudo-ops that happen to be used on MIPS
733 {"asciiz", stringer
, 1},
734 {"bss", s_change_sec
, 'b'},
737 {"dword", s_cons
, 3},
738 {"weakext", s_mips_weakext
, 0},
740 /* These pseudo-ops are defined in read.c, but must be overridden
741 here for one reason or another. */
742 {"align", s_align
, 0},
744 {"data", s_change_sec
, 'd'},
745 {"double", s_float_cons
, 'd'},
746 {"float", s_float_cons
, 'f'},
747 {"globl", s_mips_globl
, 0},
748 {"global", s_mips_globl
, 0},
749 {"hword", s_cons
, 1},
754 {"short", s_cons
, 1},
755 {"single", s_float_cons
, 'f'},
756 {"stabn", s_mips_stab
, 'n'},
757 {"text", s_change_sec
, 't'},
762 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
763 /* These pseudo-ops should be defined by the object file format.
764 However, a.out doesn't support them, so we have versions here. */
765 {"aent", s_mips_ent
, 1},
766 {"bgnb", s_ignore
, 0},
767 {"end", s_mips_end
, 0},
768 {"endb", s_ignore
, 0},
769 {"ent", s_mips_ent
, 0},
771 {"fmask", s_mips_mask
, 'F'},
772 {"frame", s_mips_frame
, 0},
773 {"loc", s_ignore
, 0},
774 {"mask", s_mips_mask
, 'R'},
775 {"verstamp", s_ignore
, 0},
779 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
784 pop_insert (mips_pseudo_table
);
785 if (! ECOFF_DEBUGGING
)
786 pop_insert (mips_nonecoff_pseudo_table
);
789 /* Symbols labelling the current insn. */
791 struct insn_label_list
793 struct insn_label_list
*next
;
797 static struct insn_label_list
*insn_labels
;
798 static struct insn_label_list
*free_insn_labels
;
800 static void mips_clear_insn_labels
PARAMS ((void));
803 mips_clear_insn_labels ()
805 register struct insn_label_list
**pl
;
807 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
813 static char *expr_end
;
815 /* Expressions which appear in instructions. These are set by
818 static expressionS imm_expr
;
819 static expressionS offset_expr
;
821 /* Relocs associated with imm_expr and offset_expr. */
823 static bfd_reloc_code_real_type imm_reloc
;
824 static bfd_reloc_code_real_type offset_reloc
;
826 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
828 static boolean imm_unmatched_hi
;
830 /* These are set by mips16_ip if an explicit extension is used. */
832 static boolean mips16_small
, mips16_ext
;
834 #ifdef MIPS_STABS_ELF
835 /* The pdr segment for per procedure frame/regmask info */
841 * This function is called once, at assembler startup time. It should
842 * set up all the tables, etc. that the MD part of the assembler will need.
848 register const char *retval
= NULL
;
849 register unsigned int i
= 0;
853 int mips_isa_from_cpu
;
855 /* GP relative stuff not working for PE */
856 if (strncmp (TARGET_OS
, "pe", 2) == 0
857 && g_switch_value
!= 0)
860 as_bad (_("-G not supported in this configuration."));
865 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
867 a
= xmalloc (sizeof TARGET_CPU
);
868 strcpy (a
, TARGET_CPU
);
869 a
[(sizeof TARGET_CPU
) - 3] = '\0';
875 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
876 just the generic 'mips', in which case set mips_cpu based
877 on the given ISA, if any. */
879 if (strcmp (cpu
, "mips") == 0)
881 if (mips_opts
.isa
< 0)
884 else if (mips_opts
.isa
== 2)
887 else if (mips_opts
.isa
== 3)
890 else if (mips_opts
.isa
== 4)
897 else if (strcmp (cpu
, "r3900") == 0
898 || strcmp (cpu
, "mipstx39") == 0
902 else if (strcmp (cpu
, "r6000") == 0
903 || strcmp (cpu
, "mips2") == 0)
906 else if (strcmp (cpu
, "mips64") == 0
907 || strcmp (cpu
, "r4000") == 0
908 || strcmp (cpu
, "mips3") == 0)
911 else if (strcmp (cpu
, "r4400") == 0)
914 else if (strcmp (cpu
, "mips64orion") == 0
915 || strcmp (cpu
, "r4600") == 0)
918 else if (strcmp (cpu
, "r4650") == 0)
921 else if (strcmp (cpu
, "mips64vr4300") == 0)
924 else if (strcmp (cpu
, "mips64vr4111") == 0)
927 else if (strcmp (cpu
, "mips64vr4100") == 0)
930 else if (strcmp (cpu
, "r4010") == 0)
934 else if (strcmp (cpu
, "r5000") == 0
935 || strcmp (cpu
, "mips64vr5000") == 0)
940 else if (strcmp (cpu
, "r8000") == 0
941 || strcmp (cpu
, "mips4") == 0)
944 else if (strcmp (cpu
, "r10000") == 0)
947 else if (strcmp (cpu
, "mips16") == 0)
948 mips_cpu
= 0; /* FIXME */
956 mips_isa_from_cpu
= 1;
958 else if (mips_cpu
== 6000
960 mips_isa_from_cpu
= 2;
962 else if (mips_cpu
== 4000
969 mips_isa_from_cpu
= 3;
971 else if (mips_cpu
== 5000
973 || mips_cpu
== 10000)
974 mips_isa_from_cpu
= 4;
977 mips_isa_from_cpu
= -1;
979 if (mips_opts
.isa
== -1)
981 if (mips_isa_from_cpu
!= -1)
982 mips_opts
.isa
= mips_isa_from_cpu
;
987 if (mips_opts
.mips16
< 0)
989 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
990 mips_opts
.mips16
= 1;
992 mips_opts
.mips16
= 0;
995 /* End of TARGET_CPU processing, get rid of malloced memory
1004 if (mips_opts
.isa
== 1 && mips_trap
)
1005 as_bad (_("trap exception not supported at ISA 1"));
1007 /* Set the EABI kind based on the ISA before the user gets
1008 to change the ISA with directives. This isn't really
1009 the best, but then neither is basing the abi on the isa. */
1010 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1012 && 0 == strcmp (mips_abi_string
,"eabi"))
1015 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1017 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1019 /* If they asked for mips1 or mips2 and a cpu that is
1020 mips3 or greater, then mark the object file 32BITMODE. */
1021 if (mips_isa_from_cpu
!= -1
1022 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1023 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1028 switch (mips_opts
.isa
)
1031 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1034 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1037 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1040 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1046 as_warn (_("Could not set architecture and machine"));
1048 file_mips_isa
= mips_opts
.isa
;
1050 op_hash
= hash_new ();
1052 for (i
= 0; i
< NUMOPCODES
;)
1054 const char *name
= mips_opcodes
[i
].name
;
1056 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1059 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1060 mips_opcodes
[i
].name
, retval
);
1061 /* Probably a memory allocation problem? Give up now. */
1062 as_fatal (_("Broken assembler. No assembly attempted."));
1066 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1068 if (!validate_mips_insn (&mips_opcodes
[i
]))
1073 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1076 mips16_op_hash
= hash_new ();
1079 while (i
< bfd_mips16_num_opcodes
)
1081 const char *name
= mips16_opcodes
[i
].name
;
1083 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1085 as_fatal (_("internal: can't hash `%s': %s"),
1086 mips16_opcodes
[i
].name
, retval
);
1089 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1090 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1091 != mips16_opcodes
[i
].match
))
1093 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1094 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1099 while (i
< bfd_mips16_num_opcodes
1100 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1104 as_fatal (_("Broken assembler. No assembly attempted."));
1106 /* We add all the general register names to the symbol table. This
1107 helps us detect invalid uses of them. */
1108 for (i
= 0; i
< 32; i
++)
1112 sprintf (buf
, "$%d", i
);
1113 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1114 &zero_address_frag
));
1116 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1117 &zero_address_frag
));
1118 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1119 &zero_address_frag
));
1120 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1121 &zero_address_frag
));
1122 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1123 &zero_address_frag
));
1124 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1125 &zero_address_frag
));
1126 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1127 &zero_address_frag
));
1128 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1129 &zero_address_frag
));
1131 mips_no_prev_insn (false);
1134 mips_cprmask
[0] = 0;
1135 mips_cprmask
[1] = 0;
1136 mips_cprmask
[2] = 0;
1137 mips_cprmask
[3] = 0;
1139 /* set the default alignment for the text section (2**2) */
1140 record_alignment (text_section
, 2);
1142 if (USE_GLOBAL_POINTER_OPT
)
1143 bfd_set_gp_size (stdoutput
, g_switch_value
);
1145 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1147 /* On a native system, sections must be aligned to 16 byte
1148 boundaries. When configured for an embedded ELF target, we
1150 if (strcmp (TARGET_OS
, "elf") != 0)
1152 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1153 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1154 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1157 /* Create a .reginfo section for register masks and a .mdebug
1158 section for debugging information. */
1166 subseg
= now_subseg
;
1168 /* The ABI says this section should be loaded so that the
1169 running program can access it. However, we don't load it
1170 if we are configured for an embedded target */
1171 flags
= SEC_READONLY
| SEC_DATA
;
1172 if (strcmp (TARGET_OS
, "elf") != 0)
1173 flags
|= SEC_ALLOC
| SEC_LOAD
;
1177 sec
= subseg_new (".reginfo", (subsegT
) 0);
1180 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1181 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1184 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1189 /* The 64-bit ABI uses a .MIPS.options section rather than
1190 .reginfo section. */
1191 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1192 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1193 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1196 /* Set up the option header. */
1198 Elf_Internal_Options opthdr
;
1201 opthdr
.kind
= ODK_REGINFO
;
1202 opthdr
.size
= (sizeof (Elf_External_Options
)
1203 + sizeof (Elf64_External_RegInfo
));
1206 f
= frag_more (sizeof (Elf_External_Options
));
1207 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1208 (Elf_External_Options
*) f
);
1210 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1215 if (ECOFF_DEBUGGING
)
1217 sec
= subseg_new (".mdebug", (subsegT
) 0);
1218 (void) bfd_set_section_flags (stdoutput
, sec
,
1219 SEC_HAS_CONTENTS
| SEC_READONLY
);
1220 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1223 #ifdef MIPS_STABS_ELF
1224 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1225 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1226 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1227 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1230 subseg_set (seg
, subseg
);
1234 if (! ECOFF_DEBUGGING
)
1241 if (! ECOFF_DEBUGGING
)
1249 struct mips_cl_insn insn
;
1251 imm_expr
.X_op
= O_absent
;
1252 imm_reloc
= BFD_RELOC_UNUSED
;
1253 imm_unmatched_hi
= false;
1254 offset_expr
.X_op
= O_absent
;
1255 offset_reloc
= BFD_RELOC_UNUSED
;
1257 if (mips_opts
.mips16
)
1258 mips16_ip (str
, &insn
);
1261 mips_ip (str
, &insn
);
1262 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1263 str
, insn
.insn_opcode
));
1268 as_bad ("%s `%s'", insn_error
, str
);
1272 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1274 if (mips_opts
.mips16
)
1275 mips16_macro (&insn
);
1281 if (imm_expr
.X_op
!= O_absent
)
1282 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1284 else if (offset_expr
.X_op
!= O_absent
)
1285 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1287 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1291 /* See whether instruction IP reads register REG. CLASS is the type
1295 insn_uses_reg (ip
, reg
, class)
1296 struct mips_cl_insn
*ip
;
1298 enum mips_regclass
class;
1300 if (class == MIPS16_REG
)
1302 assert (mips_opts
.mips16
);
1303 reg
= mips16_to_32_reg_map
[reg
];
1304 class = MIPS_GR_REG
;
1307 /* Don't report on general register 0, since it never changes. */
1308 if (class == MIPS_GR_REG
&& reg
== 0)
1311 if (class == MIPS_FP_REG
)
1313 assert (! mips_opts
.mips16
);
1314 /* If we are called with either $f0 or $f1, we must check $f0.
1315 This is not optimal, because it will introduce an unnecessary
1316 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1317 need to distinguish reading both $f0 and $f1 or just one of
1318 them. Note that we don't have to check the other way,
1319 because there is no instruction that sets both $f0 and $f1
1320 and requires a delay. */
1321 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1322 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1323 == (reg
&~ (unsigned) 1)))
1325 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1326 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1327 == (reg
&~ (unsigned) 1)))
1330 else if (! mips_opts
.mips16
)
1332 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1333 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1335 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1336 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1341 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1342 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1343 & MIPS16OP_MASK_RX
)]
1346 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1347 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1348 & MIPS16OP_MASK_RY
)]
1351 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1352 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1353 & MIPS16OP_MASK_MOVE32Z
)]
1356 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1358 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1362 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1363 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1364 & MIPS16OP_MASK_REGR32
) == reg
)
1371 /* This function returns true if modifying a register requires a
1375 reg_needs_delay (reg
)
1378 unsigned long prev_pinfo
;
1380 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1381 if (! mips_opts
.noreorder
1382 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1383 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1384 || (! gpr_interlocks
1385 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1387 /* A load from a coprocessor or from memory. All load
1388 delays delay the use of general register rt for one
1389 instruction on the r3000. The r6000 and r4000 use
1391 /* Itbl support may require additional care here. */
1392 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1393 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1400 /* Mark instruction labels in mips16 mode. This permits the linker to
1401 handle them specially, such as generating jalx instructions when
1402 needed. We also make them odd for the duration of the assembly, in
1403 order to generate the right sort of code. We will make them even
1404 in the adjust_symtab routine, while leaving them marked. This is
1405 convenient for the debugger and the disassembler. The linker knows
1406 to make them odd again. */
1409 mips16_mark_labels ()
1411 if (mips_opts
.mips16
)
1413 struct insn_label_list
*l
;
1415 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1418 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1419 S_SET_OTHER (l
->label
, STO_MIPS16
);
1421 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1422 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1427 /* Output an instruction. PLACE is where to put the instruction; if
1428 it is NULL, this uses frag_more to get room. IP is the instruction
1429 information. ADDRESS_EXPR is an operand of the instruction to be
1430 used with RELOC_TYPE. */
1433 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1435 struct mips_cl_insn
*ip
;
1436 expressionS
*address_expr
;
1437 bfd_reloc_code_real_type reloc_type
;
1438 boolean unmatched_hi
;
1440 register unsigned long prev_pinfo
, pinfo
;
1445 /* Mark instruction labels in mips16 mode. */
1446 if (mips_opts
.mips16
)
1447 mips16_mark_labels ();
1449 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1450 pinfo
= ip
->insn_mo
->pinfo
;
1452 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1456 /* If the previous insn required any delay slots, see if we need
1457 to insert a NOP or two. There are eight kinds of possible
1458 hazards, of which an instruction can have at most one type.
1459 (1) a load from memory delay
1460 (2) a load from a coprocessor delay
1461 (3) an unconditional branch delay
1462 (4) a conditional branch delay
1463 (5) a move to coprocessor register delay
1464 (6) a load coprocessor register from memory delay
1465 (7) a coprocessor condition code delay
1466 (8) a HI/LO special register delay
1468 There are a lot of optimizations we could do that we don't.
1469 In particular, we do not, in general, reorder instructions.
1470 If you use gcc with optimization, it will reorder
1471 instructions and generally do much more optimization then we
1472 do here; repeating all that work in the assembler would only
1473 benefit hand written assembly code, and does not seem worth
1476 /* This is how a NOP is emitted. */
1477 #define emit_nop() \
1479 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1480 : md_number_to_chars (frag_more (4), 0, 4))
1482 /* The previous insn might require a delay slot, depending upon
1483 the contents of the current insn. */
1484 if (! mips_opts
.mips16
1485 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1486 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1487 && ! cop_interlocks
)
1488 || (! gpr_interlocks
1489 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1491 /* A load from a coprocessor or from memory. All load
1492 delays delay the use of general register rt for one
1493 instruction on the r3000. The r6000 and r4000 use
1495 /* Itbl support may require additional care here. */
1496 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1497 if (mips_optimize
== 0
1498 || insn_uses_reg (ip
,
1499 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1504 else if (! mips_opts
.mips16
1505 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1506 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1507 && ! cop_interlocks
)
1508 || (mips_opts
.isa
== 1
1509 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1511 /* A generic coprocessor delay. The previous instruction
1512 modified a coprocessor general or control register. If
1513 it modified a control register, we need to avoid any
1514 coprocessor instruction (this is probably not always
1515 required, but it sometimes is). If it modified a general
1516 register, we avoid using that register.
1518 On the r6000 and r4000 loading a coprocessor register
1519 from memory is interlocked, and does not require a delay.
1521 This case is not handled very well. There is no special
1522 knowledge of CP0 handling, and the coprocessors other
1523 than the floating point unit are not distinguished at
1525 /* Itbl support may require additional care here. FIXME!
1526 Need to modify this to include knowledge about
1527 user specified delays! */
1528 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1530 if (mips_optimize
== 0
1531 || insn_uses_reg (ip
,
1532 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1537 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1539 if (mips_optimize
== 0
1540 || insn_uses_reg (ip
,
1541 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1548 /* We don't know exactly what the previous instruction
1549 does. If the current instruction uses a coprocessor
1550 register, we must insert a NOP. If previous
1551 instruction may set the condition codes, and the
1552 current instruction uses them, we must insert two
1554 /* Itbl support may require additional care here. */
1555 if (mips_optimize
== 0
1556 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1557 && (pinfo
& INSN_READ_COND_CODE
)))
1559 else if (pinfo
& INSN_COP
)
1563 else if (! mips_opts
.mips16
1564 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1565 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1566 && ! cop_interlocks
)
1568 /* The previous instruction sets the coprocessor condition
1569 codes, but does not require a general coprocessor delay
1570 (this means it is a floating point comparison
1571 instruction). If this instruction uses the condition
1572 codes, we need to insert a single NOP. */
1573 /* Itbl support may require additional care here. */
1574 if (mips_optimize
== 0
1575 || (pinfo
& INSN_READ_COND_CODE
))
1579 /* If we're fixing up mfhi/mflo for the r7000 and the
1580 previous insn was an mfhi/mflo and the current insn
1581 reads the register that the mfhi/mflo wrote to, then
1584 else if (mips_7000_hilo_fix
1585 && MF_HILO_INSN (prev_pinfo
)
1586 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1594 /* If we're fixing up mfhi/mflo for the r7000 and the
1595 2nd previous insn was an mfhi/mflo and the current insn
1596 reads the register that the mfhi/mflo wrote to, then
1599 else if (mips_7000_hilo_fix
1600 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1601 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1609 else if (prev_pinfo
& INSN_READ_LO
)
1611 /* The previous instruction reads the LO register; if the
1612 current instruction writes to the LO register, we must
1613 insert two NOPS. Some newer processors have interlocks.
1614 Also the tx39's multiply instructions can be exectuted
1615 immediatly after a read from HI/LO (without the delay),
1616 though the tx39's divide insns still do require the
1618 if (! (hilo_interlocks
1619 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1620 && (mips_optimize
== 0
1621 || (pinfo
& INSN_WRITE_LO
)))
1623 /* Most mips16 branch insns don't have a delay slot.
1624 If a read from LO is immediately followed by a branch
1625 to a write to LO we have a read followed by a write
1626 less than 2 insns away. We assume the target of
1627 a branch might be a write to LO, and insert a nop
1628 between a read and an immediately following branch. */
1629 else if (mips_opts
.mips16
1630 && (mips_optimize
== 0
1631 || (pinfo
& MIPS16_INSN_BRANCH
)))
1634 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1636 /* The previous instruction reads the HI register; if the
1637 current instruction writes to the HI register, we must
1638 insert a NOP. Some newer processors have interlocks.
1639 Also the note tx39's multiply above. */
1640 if (! (hilo_interlocks
1641 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1642 && (mips_optimize
== 0
1643 || (pinfo
& INSN_WRITE_HI
)))
1645 /* Most mips16 branch insns don't have a delay slot.
1646 If a read from HI is immediately followed by a branch
1647 to a write to HI we have a read followed by a write
1648 less than 2 insns away. We assume the target of
1649 a branch might be a write to HI, and insert a nop
1650 between a read and an immediately following branch. */
1651 else if (mips_opts
.mips16
1652 && (mips_optimize
== 0
1653 || (pinfo
& MIPS16_INSN_BRANCH
)))
1657 /* If the previous instruction was in a noreorder section, then
1658 we don't want to insert the nop after all. */
1659 /* Itbl support may require additional care here. */
1660 if (prev_insn_unreordered
)
1663 /* There are two cases which require two intervening
1664 instructions: 1) setting the condition codes using a move to
1665 coprocessor instruction which requires a general coprocessor
1666 delay and then reading the condition codes 2) reading the HI
1667 or LO register and then writing to it (except on processors
1668 which have interlocks). If we are not already emitting a NOP
1669 instruction, we must check for these cases compared to the
1670 instruction previous to the previous instruction. */
1671 if ((! mips_opts
.mips16
1672 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1673 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1674 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1675 && (pinfo
& INSN_READ_COND_CODE
)
1676 && ! cop_interlocks
)
1677 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1678 && (pinfo
& INSN_WRITE_LO
)
1679 && ! (hilo_interlocks
1680 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1681 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1682 && (pinfo
& INSN_WRITE_HI
)
1683 && ! (hilo_interlocks
1684 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1689 if (prev_prev_insn_unreordered
)
1692 if (prev_prev_nop
&& nops
== 0)
1695 /* If we are being given a nop instruction, don't bother with
1696 one of the nops we would otherwise output. This will only
1697 happen when a nop instruction is used with mips_optimize set
1700 && ! mips_opts
.noreorder
1701 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1704 /* Now emit the right number of NOP instructions. */
1705 if (nops
> 0 && ! mips_opts
.noreorder
)
1708 unsigned long old_frag_offset
;
1710 struct insn_label_list
*l
;
1712 old_frag
= frag_now
;
1713 old_frag_offset
= frag_now_fix ();
1715 for (i
= 0; i
< nops
; i
++)
1720 listing_prev_line ();
1721 /* We may be at the start of a variant frag. In case we
1722 are, make sure there is enough space for the frag
1723 after the frags created by listing_prev_line. The
1724 argument to frag_grow here must be at least as large
1725 as the argument to all other calls to frag_grow in
1726 this file. We don't have to worry about being in the
1727 middle of a variant frag, because the variants insert
1728 all needed nop instructions themselves. */
1732 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1734 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1735 symbol_set_frag (l
->label
, frag_now
);
1736 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1737 /* mips16 text labels are stored as odd. */
1738 if (mips_opts
.mips16
)
1739 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1742 #ifndef NO_ECOFF_DEBUGGING
1743 if (ECOFF_DEBUGGING
)
1744 ecoff_fix_loc (old_frag
, old_frag_offset
);
1747 else if (prev_nop_frag
!= NULL
)
1749 /* We have a frag holding nops we may be able to remove. If
1750 we don't need any nops, we can decrease the size of
1751 prev_nop_frag by the size of one instruction. If we do
1752 need some nops, we count them in prev_nops_required. */
1753 if (prev_nop_frag_since
== 0)
1757 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1758 --prev_nop_frag_holds
;
1761 prev_nop_frag_required
+= nops
;
1765 if (prev_prev_nop
== 0)
1767 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1768 --prev_nop_frag_holds
;
1771 ++prev_nop_frag_required
;
1774 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1775 prev_nop_frag
= NULL
;
1777 ++prev_nop_frag_since
;
1779 /* Sanity check: by the time we reach the second instruction
1780 after prev_nop_frag, we should have used up all the nops
1781 one way or another. */
1782 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1786 if (reloc_type
> BFD_RELOC_UNUSED
)
1788 /* We need to set up a variant frag. */
1789 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1790 f
= frag_var (rs_machine_dependent
, 4, 0,
1791 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1792 mips16_small
, mips16_ext
,
1794 & INSN_UNCOND_BRANCH_DELAY
),
1795 (prev_insn_reloc_type
1796 == BFD_RELOC_MIPS16_JMP
)),
1797 make_expr_symbol (address_expr
), (offsetT
) 0,
1800 else if (place
!= NULL
)
1802 else if (mips_opts
.mips16
1804 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1806 /* Make sure there is enough room to swap this instruction with
1807 a following jump instruction. */
1813 if (mips_opts
.mips16
1814 && mips_opts
.noreorder
1815 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1816 as_warn (_("extended instruction in delay slot"));
1822 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1824 if (address_expr
->X_op
== O_constant
)
1829 ip
->insn_opcode
|= address_expr
->X_add_number
;
1832 case BFD_RELOC_LO16
:
1833 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1836 case BFD_RELOC_MIPS_JMP
:
1837 if ((address_expr
->X_add_number
& 3) != 0)
1838 as_bad (_("jump to misaligned address (0x%lx)"),
1839 (unsigned long) address_expr
->X_add_number
);
1840 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1843 case BFD_RELOC_MIPS16_JMP
:
1844 if ((address_expr
->X_add_number
& 3) != 0)
1845 as_bad (_("jump to misaligned address (0x%lx)"),
1846 (unsigned long) address_expr
->X_add_number
);
1848 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1849 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1850 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1854 case BFD_RELOC_16_PCREL_S2
:
1864 /* Don't generate a reloc if we are writing into a variant
1868 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1870 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1874 struct mips_hi_fixup
*hi_fixup
;
1876 assert (reloc_type
== BFD_RELOC_HI16_S
);
1877 hi_fixup
= ((struct mips_hi_fixup
*)
1878 xmalloc (sizeof (struct mips_hi_fixup
)));
1879 hi_fixup
->fixp
= fixp
;
1880 hi_fixup
->seg
= now_seg
;
1881 hi_fixup
->next
= mips_hi_fixup_list
;
1882 mips_hi_fixup_list
= hi_fixup
;
1888 if (! mips_opts
.mips16
)
1889 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1890 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1892 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1893 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1899 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1902 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1905 /* Update the register mask information. */
1906 if (! mips_opts
.mips16
)
1908 if (pinfo
& INSN_WRITE_GPR_D
)
1909 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1910 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1911 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1912 if (pinfo
& INSN_READ_GPR_S
)
1913 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1914 if (pinfo
& INSN_WRITE_GPR_31
)
1915 mips_gprmask
|= 1 << 31;
1916 if (pinfo
& INSN_WRITE_FPR_D
)
1917 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1918 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1919 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1920 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1921 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1922 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1923 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1924 if (pinfo
& INSN_COP
)
1926 /* We don't keep enough information to sort these cases out.
1927 The itbl support does keep this information however, although
1928 we currently don't support itbl fprmats as part of the cop
1929 instruction. May want to add this support in the future. */
1931 /* Never set the bit for $0, which is always zero. */
1932 mips_gprmask
&=~ 1 << 0;
1936 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1937 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1938 & MIPS16OP_MASK_RX
);
1939 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1940 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1941 & MIPS16OP_MASK_RY
);
1942 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1943 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1944 & MIPS16OP_MASK_RZ
);
1945 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1946 mips_gprmask
|= 1 << TREG
;
1947 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1948 mips_gprmask
|= 1 << SP
;
1949 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1950 mips_gprmask
|= 1 << RA
;
1951 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1952 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1953 if (pinfo
& MIPS16_INSN_READ_Z
)
1954 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1955 & MIPS16OP_MASK_MOVE32Z
);
1956 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1957 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1958 & MIPS16OP_MASK_REGR32
);
1961 if (place
== NULL
&& ! mips_opts
.noreorder
)
1963 /* Filling the branch delay slot is more complex. We try to
1964 switch the branch with the previous instruction, which we can
1965 do if the previous instruction does not set up a condition
1966 that the branch tests and if the branch is not itself the
1967 target of any branch. */
1968 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1969 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1971 if (mips_optimize
< 2
1972 /* If we have seen .set volatile or .set nomove, don't
1974 || mips_opts
.nomove
!= 0
1975 /* If we had to emit any NOP instructions, then we
1976 already know we can not swap. */
1978 /* If we don't even know the previous insn, we can not
1980 || ! prev_insn_valid
1981 /* If the previous insn is already in a branch delay
1982 slot, then we can not swap. */
1983 || prev_insn_is_delay_slot
1984 /* If the previous previous insn was in a .set
1985 noreorder, we can't swap. Actually, the MIPS
1986 assembler will swap in this situation. However, gcc
1987 configured -with-gnu-as will generate code like
1993 in which we can not swap the bne and INSN. If gcc is
1994 not configured -with-gnu-as, it does not output the
1995 .set pseudo-ops. We don't have to check
1996 prev_insn_unreordered, because prev_insn_valid will
1997 be 0 in that case. We don't want to use
1998 prev_prev_insn_valid, because we do want to be able
1999 to swap at the start of a function. */
2000 || prev_prev_insn_unreordered
2001 /* If the branch is itself the target of a branch, we
2002 can not swap. We cheat on this; all we check for is
2003 whether there is a label on this instruction. If
2004 there are any branches to anything other than a
2005 label, users must use .set noreorder. */
2006 || insn_labels
!= NULL
2007 /* If the previous instruction is in a variant frag, we
2008 can not do the swap. This does not apply to the
2009 mips16, which uses variant frags for different
2011 || (! mips_opts
.mips16
2012 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2013 /* If the branch reads the condition codes, we don't
2014 even try to swap, because in the sequence
2019 we can not swap, and I don't feel like handling that
2021 || (! mips_opts
.mips16
2022 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2023 && (pinfo
& INSN_READ_COND_CODE
))
2024 /* We can not swap with an instruction that requires a
2025 delay slot, becase the target of the branch might
2026 interfere with that instruction. */
2027 || (! mips_opts
.mips16
2028 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2030 /* Itbl support may require additional care here. */
2031 & (INSN_LOAD_COPROC_DELAY
2032 | INSN_COPROC_MOVE_DELAY
2033 | INSN_WRITE_COND_CODE
)))
2034 || (! (hilo_interlocks
2035 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2039 || (! mips_opts
.mips16
2041 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2042 || (! mips_opts
.mips16
2043 && mips_opts
.isa
== 1
2044 /* Itbl support may require additional care here. */
2045 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2046 /* We can not swap with a branch instruction. */
2048 & (INSN_UNCOND_BRANCH_DELAY
2049 | INSN_COND_BRANCH_DELAY
2050 | INSN_COND_BRANCH_LIKELY
))
2051 /* We do not swap with a trap instruction, since it
2052 complicates trap handlers to have the trap
2053 instruction be in a delay slot. */
2054 || (prev_pinfo
& INSN_TRAP
)
2055 /* If the branch reads a register that the previous
2056 instruction sets, we can not swap. */
2057 || (! mips_opts
.mips16
2058 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2059 && insn_uses_reg (ip
,
2060 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2063 || (! mips_opts
.mips16
2064 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2065 && insn_uses_reg (ip
,
2066 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2069 || (mips_opts
.mips16
2070 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2071 && insn_uses_reg (ip
,
2072 ((prev_insn
.insn_opcode
2074 & MIPS16OP_MASK_RX
),
2076 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2077 && insn_uses_reg (ip
,
2078 ((prev_insn
.insn_opcode
2080 & MIPS16OP_MASK_RY
),
2082 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2083 && insn_uses_reg (ip
,
2084 ((prev_insn
.insn_opcode
2086 & MIPS16OP_MASK_RZ
),
2088 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2089 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2090 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2091 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2092 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2093 && insn_uses_reg (ip
,
2094 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2097 /* If the branch writes a register that the previous
2098 instruction sets, we can not swap (we know that
2099 branches write only to RD or to $31). */
2100 || (! mips_opts
.mips16
2101 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2102 && (((pinfo
& INSN_WRITE_GPR_D
)
2103 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2104 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2105 || ((pinfo
& INSN_WRITE_GPR_31
)
2106 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2109 || (! mips_opts
.mips16
2110 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2111 && (((pinfo
& INSN_WRITE_GPR_D
)
2112 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2113 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2114 || ((pinfo
& INSN_WRITE_GPR_31
)
2115 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2118 || (mips_opts
.mips16
2119 && (pinfo
& MIPS16_INSN_WRITE_31
)
2120 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2121 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2122 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2124 /* If the branch writes a register that the previous
2125 instruction reads, we can not swap (we know that
2126 branches only write to RD or to $31). */
2127 || (! mips_opts
.mips16
2128 && (pinfo
& INSN_WRITE_GPR_D
)
2129 && insn_uses_reg (&prev_insn
,
2130 ((ip
->insn_opcode
>> OP_SH_RD
)
2133 || (! mips_opts
.mips16
2134 && (pinfo
& INSN_WRITE_GPR_31
)
2135 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2136 || (mips_opts
.mips16
2137 && (pinfo
& MIPS16_INSN_WRITE_31
)
2138 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2139 /* If we are generating embedded PIC code, the branch
2140 might be expanded into a sequence which uses $at, so
2141 we can't swap with an instruction which reads it. */
2142 || (mips_pic
== EMBEDDED_PIC
2143 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2144 /* If the previous previous instruction has a load
2145 delay, and sets a register that the branch reads, we
2147 || (! mips_opts
.mips16
2148 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2149 /* Itbl support may require additional care here. */
2150 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2151 || (! gpr_interlocks
2152 && (prev_prev_insn
.insn_mo
->pinfo
2153 & INSN_LOAD_MEMORY_DELAY
)))
2154 && insn_uses_reg (ip
,
2155 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2158 /* If one instruction sets a condition code and the
2159 other one uses a condition code, we can not swap. */
2160 || ((pinfo
& INSN_READ_COND_CODE
)
2161 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2162 || ((pinfo
& INSN_WRITE_COND_CODE
)
2163 && (prev_pinfo
& INSN_READ_COND_CODE
))
2164 /* If the previous instruction uses the PC, we can not
2166 || (mips_opts
.mips16
2167 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2168 /* If the previous instruction was extended, we can not
2170 || (mips_opts
.mips16
&& prev_insn_extended
)
2171 /* If the previous instruction had a fixup in mips16
2172 mode, we can not swap. This normally means that the
2173 previous instruction was a 4 byte branch anyhow. */
2174 || (mips_opts
.mips16
&& prev_insn_fixp
)
2175 /* If the previous instruction is a sync, sync.l, or
2176 sync.p, we can not swap. */
2177 || (prev_pinfo
& INSN_SYNC
))
2179 /* We could do even better for unconditional branches to
2180 portions of this object file; we could pick up the
2181 instruction at the destination, put it in the delay
2182 slot, and bump the destination address. */
2184 /* Update the previous insn information. */
2185 prev_prev_insn
= *ip
;
2186 prev_insn
.insn_mo
= &dummy_opcode
;
2190 /* It looks like we can actually do the swap. */
2191 if (! mips_opts
.mips16
)
2196 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2197 memcpy (temp
, prev_f
, 4);
2198 memcpy (prev_f
, f
, 4);
2199 memcpy (f
, temp
, 4);
2202 prev_insn_fixp
->fx_frag
= frag_now
;
2203 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2207 fixp
->fx_frag
= prev_insn_frag
;
2208 fixp
->fx_where
= prev_insn_where
;
2216 assert (prev_insn_fixp
== NULL
);
2217 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2218 memcpy (temp
, prev_f
, 2);
2219 memcpy (prev_f
, f
, 2);
2220 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2222 assert (reloc_type
== BFD_RELOC_UNUSED
);
2223 memcpy (f
, temp
, 2);
2227 memcpy (f
, f
+ 2, 2);
2228 memcpy (f
+ 2, temp
, 2);
2232 fixp
->fx_frag
= prev_insn_frag
;
2233 fixp
->fx_where
= prev_insn_where
;
2237 /* Update the previous insn information; leave prev_insn
2239 prev_prev_insn
= *ip
;
2241 prev_insn_is_delay_slot
= 1;
2243 /* If that was an unconditional branch, forget the previous
2244 insn information. */
2245 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2247 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2248 prev_insn
.insn_mo
= &dummy_opcode
;
2251 prev_insn_fixp
= NULL
;
2252 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2253 prev_insn_extended
= 0;
2255 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2257 /* We don't yet optimize a branch likely. What we should do
2258 is look at the target, copy the instruction found there
2259 into the delay slot, and increment the branch to jump to
2260 the next instruction. */
2262 /* Update the previous insn information. */
2263 prev_prev_insn
= *ip
;
2264 prev_insn
.insn_mo
= &dummy_opcode
;
2265 prev_insn_fixp
= NULL
;
2266 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2267 prev_insn_extended
= 0;
2271 /* Update the previous insn information. */
2273 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2275 prev_prev_insn
= prev_insn
;
2278 /* Any time we see a branch, we always fill the delay slot
2279 immediately; since this insn is not a branch, we know it
2280 is not in a delay slot. */
2281 prev_insn_is_delay_slot
= 0;
2283 prev_insn_fixp
= fixp
;
2284 prev_insn_reloc_type
= reloc_type
;
2285 if (mips_opts
.mips16
)
2286 prev_insn_extended
= (ip
->use_extend
2287 || reloc_type
> BFD_RELOC_UNUSED
);
2290 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2291 prev_insn_unreordered
= 0;
2292 prev_insn_frag
= frag_now
;
2293 prev_insn_where
= f
- frag_now
->fr_literal
;
2294 prev_insn_valid
= 1;
2296 else if (place
== NULL
)
2298 /* We need to record a bit of information even when we are not
2299 reordering, in order to determine the base address for mips16
2300 PC relative relocs. */
2301 prev_prev_insn
= prev_insn
;
2303 prev_insn_reloc_type
= reloc_type
;
2304 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2305 prev_insn_unreordered
= 1;
2308 /* We just output an insn, so the next one doesn't have a label. */
2309 mips_clear_insn_labels ();
2311 /* We must ensure that a fixup associated with an unmatched %hi
2312 reloc does not become a variant frag. Otherwise, the
2313 rearrangement of %hi relocs in frob_file may confuse
2317 frag_wane (frag_now
);
2322 /* This function forgets that there was any previous instruction or
2323 label. If PRESERVE is non-zero, it remembers enough information to
2324 know whether nops are needed before a noreorder section. */
2327 mips_no_prev_insn (preserve
)
2332 prev_insn
.insn_mo
= &dummy_opcode
;
2333 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2334 prev_nop_frag
= NULL
;
2335 prev_nop_frag_holds
= 0;
2336 prev_nop_frag_required
= 0;
2337 prev_nop_frag_since
= 0;
2339 prev_insn_valid
= 0;
2340 prev_insn_is_delay_slot
= 0;
2341 prev_insn_unreordered
= 0;
2342 prev_insn_extended
= 0;
2343 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2344 prev_prev_insn_unreordered
= 0;
2345 mips_clear_insn_labels ();
2348 /* This function must be called whenever we turn on noreorder or emit
2349 something other than instructions. It inserts any NOPS which might
2350 be needed by the previous instruction, and clears the information
2351 kept for the previous instructions. The INSNS parameter is true if
2352 instructions are to follow. */
2355 mips_emit_delays (insns
)
2358 if (! mips_opts
.noreorder
)
2363 if ((! mips_opts
.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2365 && (! cop_interlocks
2366 && (prev_insn
.insn_mo
->pinfo
2367 & (INSN_LOAD_COPROC_DELAY
2368 | INSN_COPROC_MOVE_DELAY
2369 | INSN_WRITE_COND_CODE
))))
2370 || (! hilo_interlocks
2371 && (prev_insn
.insn_mo
->pinfo
2374 || (! mips_opts
.mips16
2376 && (prev_insn
.insn_mo
->pinfo
2377 & INSN_LOAD_MEMORY_DELAY
))
2378 || (! mips_opts
.mips16
2379 && mips_opts
.isa
== 1
2380 && (prev_insn
.insn_mo
->pinfo
2381 & INSN_COPROC_MEMORY_DELAY
)))
2383 /* Itbl support may require additional care here. */
2385 if ((! mips_opts
.mips16
2386 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2387 && (! cop_interlocks
2388 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2389 || (! hilo_interlocks
2390 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2391 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2394 if (prev_insn_unreordered
)
2397 else if ((! mips_opts
.mips16
2398 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2399 && (! cop_interlocks
2400 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2401 || (! hilo_interlocks
2402 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2403 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2405 /* Itbl support may require additional care here. */
2406 if (! prev_prev_insn_unreordered
)
2412 struct insn_label_list
*l
;
2416 /* Record the frag which holds the nop instructions, so
2417 that we can remove them if we don't need them. */
2418 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2419 prev_nop_frag
= frag_now
;
2420 prev_nop_frag_holds
= nops
;
2421 prev_nop_frag_required
= 0;
2422 prev_nop_frag_since
= 0;
2425 for (; nops
> 0; --nops
)
2430 /* Move on to a new frag, so that it is safe to simply
2431 decrease the size of prev_nop_frag. */
2432 frag_wane (frag_now
);
2436 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2438 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2439 symbol_set_frag (l
->label
, frag_now
);
2440 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2441 /* mips16 text labels are stored as odd. */
2442 if (mips_opts
.mips16
)
2443 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2448 /* Mark instruction labels in mips16 mode. */
2449 if (mips_opts
.mips16
&& insns
)
2450 mips16_mark_labels ();
2452 mips_no_prev_insn (insns
);
2455 /* Build an instruction created by a macro expansion. This is passed
2456 a pointer to the count of instructions created so far, an
2457 expression, the name of the instruction to build, an operand format
2458 string, and corresponding arguments. */
2462 macro_build (char *place
,
2470 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2479 struct mips_cl_insn insn
;
2480 bfd_reloc_code_real_type r
;
2484 va_start (args
, fmt
);
2490 * If the macro is about to expand into a second instruction,
2491 * print a warning if needed. We need to pass ip as a parameter
2492 * to generate a better warning message here...
2494 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2495 as_warn (_("Macro instruction expanded into multiple instructions"));
2498 *counter
+= 1; /* bump instruction counter */
2500 if (mips_opts
.mips16
)
2502 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2507 r
= BFD_RELOC_UNUSED
;
2508 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2509 assert (insn
.insn_mo
);
2510 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2512 /* Search until we get a match for NAME. */
2515 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2516 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2517 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2519 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2523 assert (insn
.insn_mo
->name
);
2524 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2527 insn
.insn_opcode
= insn
.insn_mo
->match
;
2543 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2554 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2559 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2566 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2570 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2574 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2578 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2585 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2591 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2592 assert (r
== BFD_RELOC_MIPS_GPREL
2593 || r
== BFD_RELOC_MIPS_LITERAL
2594 || r
== BFD_RELOC_LO16
2595 || r
== BFD_RELOC_MIPS_GOT16
2596 || r
== BFD_RELOC_MIPS_CALL16
2597 || r
== BFD_RELOC_MIPS_GOT_LO16
2598 || r
== BFD_RELOC_MIPS_CALL_LO16
2599 || (ep
->X_op
== O_subtract
2600 && now_seg
== text_section
2601 && r
== BFD_RELOC_PCREL_LO16
));
2605 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2607 && (ep
->X_op
== O_constant
2608 || (ep
->X_op
== O_symbol
2609 && (r
== BFD_RELOC_HI16_S
2610 || r
== BFD_RELOC_HI16
2611 || r
== BFD_RELOC_MIPS_GOT_HI16
2612 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2613 || (ep
->X_op
== O_subtract
2614 && now_seg
== text_section
2615 && r
== BFD_RELOC_PCREL_HI16_S
)));
2616 if (ep
->X_op
== O_constant
)
2618 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2620 r
= BFD_RELOC_UNUSED
;
2625 assert (ep
!= NULL
);
2627 * This allows macro() to pass an immediate expression for
2628 * creating short branches without creating a symbol.
2629 * Note that the expression still might come from the assembly
2630 * input, in which case the value is not checked for range nor
2631 * is a relocation entry generated (yuck).
2633 if (ep
->X_op
== O_constant
)
2635 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2639 r
= BFD_RELOC_16_PCREL_S2
;
2643 assert (ep
!= NULL
);
2644 r
= BFD_RELOC_MIPS_JMP
;
2648 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2657 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2659 append_insn (place
, &insn
, ep
, r
, false);
2663 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2671 struct mips_cl_insn insn
;
2672 bfd_reloc_code_real_type r
;
2674 r
= BFD_RELOC_UNUSED
;
2675 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2676 assert (insn
.insn_mo
);
2677 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2679 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2680 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2683 assert (insn
.insn_mo
->name
);
2684 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2687 insn
.insn_opcode
= insn
.insn_mo
->match
;
2688 insn
.use_extend
= false;
2707 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2712 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2716 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2720 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2730 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2737 regno
= va_arg (args
, int);
2738 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2739 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2760 assert (ep
!= NULL
);
2762 if (ep
->X_op
!= O_constant
)
2763 r
= BFD_RELOC_UNUSED
+ c
;
2766 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2767 false, false, &insn
.insn_opcode
,
2768 &insn
.use_extend
, &insn
.extend
);
2770 r
= BFD_RELOC_UNUSED
;
2776 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2783 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2785 append_insn (place
, &insn
, ep
, r
, false);
2789 * Generate a "lui" instruction.
2792 macro_build_lui (place
, counter
, ep
, regnum
)
2798 expressionS high_expr
;
2799 struct mips_cl_insn insn
;
2800 bfd_reloc_code_real_type r
;
2801 CONST
char *name
= "lui";
2802 CONST
char *fmt
= "t,u";
2804 assert (! mips_opts
.mips16
);
2810 high_expr
.X_op
= O_constant
;
2811 high_expr
.X_add_number
= ep
->X_add_number
;
2814 if (high_expr
.X_op
== O_constant
)
2816 /* we can compute the instruction now without a relocation entry */
2817 if (high_expr
.X_add_number
& 0x8000)
2818 high_expr
.X_add_number
+= 0x10000;
2819 high_expr
.X_add_number
=
2820 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2821 r
= BFD_RELOC_UNUSED
;
2825 assert (ep
->X_op
== O_symbol
);
2826 /* _gp_disp is a special case, used from s_cpload. */
2827 assert (mips_pic
== NO_PIC
2828 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2829 r
= BFD_RELOC_HI16_S
;
2833 * If the macro is about to expand into a second instruction,
2834 * print a warning if needed. We need to pass ip as a parameter
2835 * to generate a better warning message here...
2837 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2838 as_warn (_("Macro instruction expanded into multiple instructions"));
2841 *counter
+= 1; /* bump instruction counter */
2843 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2844 assert (insn
.insn_mo
);
2845 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2846 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2848 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2849 if (r
== BFD_RELOC_UNUSED
)
2851 insn
.insn_opcode
|= high_expr
.X_add_number
;
2852 append_insn (place
, &insn
, NULL
, r
, false);
2855 append_insn (place
, &insn
, &high_expr
, r
, false);
2859 * Generates code to set the $at register to true (one)
2860 * if reg is less than the immediate expression.
2863 set_at (counter
, reg
, unsignedp
)
2868 if (imm_expr
.X_op
== O_constant
2869 && imm_expr
.X_add_number
>= -0x8000
2870 && imm_expr
.X_add_number
< 0x8000)
2871 macro_build ((char *) NULL
, counter
, &imm_expr
,
2872 unsignedp
? "sltiu" : "slti",
2873 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2876 load_register (counter
, AT
, &imm_expr
, 0);
2877 macro_build ((char *) NULL
, counter
, NULL
,
2878 unsignedp
? "sltu" : "slt",
2879 "d,v,t", AT
, reg
, AT
);
2883 /* Warn if an expression is not a constant. */
2886 check_absolute_expr (ip
, ex
)
2887 struct mips_cl_insn
*ip
;
2890 if (ex
->X_op
== O_big
)
2891 as_bad (_("unsupported large constant"));
2892 else if (ex
->X_op
!= O_constant
)
2893 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2896 /* Count the leading zeroes by performing a binary chop. This is a
2897 bulky bit of source, but performance is a LOT better for the
2898 majority of values than a simple loop to count the bits:
2899 for (lcnt = 0; (lcnt < 32); lcnt++)
2900 if ((v) & (1 << (31 - lcnt)))
2902 However it is not code size friendly, and the gain will drop a bit
2903 on certain cached systems.
2905 #define COUNT_TOP_ZEROES(v) \
2906 (((v) & ~0xffff) == 0 \
2907 ? ((v) & ~0xff) == 0 \
2908 ? ((v) & ~0xf) == 0 \
2909 ? ((v) & ~0x3) == 0 \
2910 ? ((v) & ~0x1) == 0 \
2915 : ((v) & ~0x7) == 0 \
2918 : ((v) & ~0x3f) == 0 \
2919 ? ((v) & ~0x1f) == 0 \
2922 : ((v) & ~0x7f) == 0 \
2925 : ((v) & ~0xfff) == 0 \
2926 ? ((v) & ~0x3ff) == 0 \
2927 ? ((v) & ~0x1ff) == 0 \
2930 : ((v) & ~0x7ff) == 0 \
2933 : ((v) & ~0x3fff) == 0 \
2934 ? ((v) & ~0x1fff) == 0 \
2937 : ((v) & ~0x7fff) == 0 \
2940 : ((v) & ~0xffffff) == 0 \
2941 ? ((v) & ~0xfffff) == 0 \
2942 ? ((v) & ~0x3ffff) == 0 \
2943 ? ((v) & ~0x1ffff) == 0 \
2946 : ((v) & ~0x7ffff) == 0 \
2949 : ((v) & ~0x3fffff) == 0 \
2950 ? ((v) & ~0x1fffff) == 0 \
2953 : ((v) & ~0x7fffff) == 0 \
2956 : ((v) & ~0xfffffff) == 0 \
2957 ? ((v) & ~0x3ffffff) == 0 \
2958 ? ((v) & ~0x1ffffff) == 0 \
2961 : ((v) & ~0x7ffffff) == 0 \
2964 : ((v) & ~0x3fffffff) == 0 \
2965 ? ((v) & ~0x1fffffff) == 0 \
2968 : ((v) & ~0x7fffffff) == 0 \
2973 * This routine generates the least number of instructions neccessary to load
2974 * an absolute expression value into a register.
2977 load_register (counter
, reg
, ep
, dbl
)
2984 expressionS hi32
, lo32
;
2986 if (ep
->X_op
!= O_big
)
2988 assert (ep
->X_op
== O_constant
);
2989 if (ep
->X_add_number
< 0x8000
2990 && (ep
->X_add_number
>= 0
2991 || (ep
->X_add_number
>= -0x8000
2994 || sizeof (ep
->X_add_number
) > 4))))
2996 /* We can handle 16 bit signed values with an addiu to
2997 $zero. No need to ever use daddiu here, since $zero and
2998 the result are always correct in 32 bit mode. */
2999 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3000 (int) BFD_RELOC_LO16
);
3003 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3005 /* We can handle 16 bit unsigned values with an ori to
3007 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3008 (int) BFD_RELOC_LO16
);
3011 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3012 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3013 == ~ (offsetT
) 0x7fffffff))
3016 || sizeof (ep
->X_add_number
) > 4
3017 || (ep
->X_add_number
& 0x80000000) == 0))
3018 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3019 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3020 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3022 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3023 == ~ (offsetT
) 0xffffffff)))
3025 /* 32 bit values require an lui. */
3026 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3027 (int) BFD_RELOC_HI16
);
3028 if ((ep
->X_add_number
& 0xffff) != 0)
3029 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3030 (int) BFD_RELOC_LO16
);
3035 /* The value is larger than 32 bits. */
3037 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3039 as_bad (_("Number larger than 32 bits"));
3040 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3041 (int) BFD_RELOC_LO16
);
3045 if (ep
->X_op
!= O_big
)
3048 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3049 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3050 hi32
.X_add_number
&= 0xffffffff;
3052 lo32
.X_add_number
&= 0xffffffff;
3056 assert (ep
->X_add_number
> 2);
3057 if (ep
->X_add_number
== 3)
3058 generic_bignum
[3] = 0;
3059 else if (ep
->X_add_number
> 4)
3060 as_bad (_("Number larger than 64 bits"));
3061 lo32
.X_op
= O_constant
;
3062 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3063 hi32
.X_op
= O_constant
;
3064 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3067 if (hi32
.X_add_number
== 0)
3072 unsigned long hi
, lo
;
3074 if (hi32
.X_add_number
== 0xffffffff)
3076 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3078 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3079 reg
, 0, (int) BFD_RELOC_LO16
);
3082 if (lo32
.X_add_number
& 0x80000000)
3084 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3085 (int) BFD_RELOC_HI16
);
3086 if (lo32
.X_add_number
& 0xffff)
3087 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3088 reg
, reg
, (int) BFD_RELOC_LO16
);
3093 /* Check for 16bit shifted constant. We know that hi32 is
3094 non-zero, so start the mask on the first bit of the hi32
3099 unsigned long himask
, lomask
;
3103 himask
= 0xffff >> (32 - shift
);
3104 lomask
= (0xffff << shift
) & 0xffffffff;
3108 himask
= 0xffff << (shift
- 32);
3111 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3112 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3116 tmp
.X_op
= O_constant
;
3118 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3119 | (lo32
.X_add_number
>> shift
));
3121 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3122 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3123 (int) BFD_RELOC_LO16
);
3124 macro_build ((char *) NULL
, counter
, NULL
,
3125 (shift
>= 32) ? "dsll32" : "dsll",
3127 (shift
>= 32) ? shift
- 32 : shift
);
3131 } while (shift
<= (64 - 16));
3133 /* Find the bit number of the lowest one bit, and store the
3134 shifted value in hi/lo. */
3135 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3136 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3140 while ((lo
& 1) == 0)
3145 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3151 while ((hi
& 1) == 0)
3160 /* Optimize if the shifted value is a (power of 2) - 1. */
3161 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3162 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3164 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3169 /* This instruction will set the register to be all
3171 tmp
.X_op
= O_constant
;
3172 tmp
.X_add_number
= (offsetT
) -1;
3173 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3174 reg
, 0, (int) BFD_RELOC_LO16
);
3178 macro_build ((char *) NULL
, counter
, NULL
,
3179 (bit
>= 32) ? "dsll32" : "dsll",
3181 (bit
>= 32) ? bit
- 32 : bit
);
3183 macro_build ((char *) NULL
, counter
, NULL
,
3184 (shift
>= 32) ? "dsrl32" : "dsrl",
3186 (shift
>= 32) ? shift
- 32 : shift
);
3191 /* Sign extend hi32 before calling load_register, because we can
3192 generally get better code when we load a sign extended value. */
3193 if ((hi32
.X_add_number
& 0x80000000) != 0)
3194 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3195 load_register (counter
, reg
, &hi32
, 0);
3198 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3202 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3211 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3213 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3214 (int) BFD_RELOC_HI16
);
3215 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3222 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3227 mid16
.X_add_number
>>= 16;
3228 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3229 freg
, (int) BFD_RELOC_LO16
);
3230 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3234 if ((lo32
.X_add_number
& 0xffff) != 0)
3235 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3236 (int) BFD_RELOC_LO16
);
3239 /* Load an address into a register. */
3242 load_address (counter
, reg
, ep
)
3249 if (ep
->X_op
!= O_constant
3250 && ep
->X_op
!= O_symbol
)
3252 as_bad (_("expression too complex"));
3253 ep
->X_op
= O_constant
;
3256 if (ep
->X_op
== O_constant
)
3258 load_register (counter
, reg
, ep
, 0);
3262 if (mips_pic
== NO_PIC
)
3264 /* If this is a reference to a GP relative symbol, we want
3265 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3267 lui $reg,<sym> (BFD_RELOC_HI16_S)
3268 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3269 If we have an addend, we always use the latter form. */
3270 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3271 || nopic_need_relax (ep
->X_add_symbol
, 1))
3276 macro_build ((char *) NULL
, counter
, ep
,
3277 ((bfd_arch_bits_per_address (stdoutput
) == 32
3278 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3279 ? "addiu" : "daddiu"),
3280 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3281 p
= frag_var (rs_machine_dependent
, 8, 0,
3282 RELAX_ENCODE (4, 8, 0, 4, 0,
3283 mips_opts
.warn_about_macros
),
3284 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3286 macro_build_lui (p
, counter
, ep
, reg
);
3289 macro_build (p
, counter
, ep
,
3290 ((bfd_arch_bits_per_address (stdoutput
) == 32
3291 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3292 ? "addiu" : "daddiu"),
3293 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3295 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3299 /* If this is a reference to an external symbol, we want
3300 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3302 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3304 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3305 If there is a constant, it must be added in after. */
3306 ex
.X_add_number
= ep
->X_add_number
;
3307 ep
->X_add_number
= 0;
3309 macro_build ((char *) NULL
, counter
, ep
,
3310 ((bfd_arch_bits_per_address (stdoutput
) == 32
3311 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3313 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3314 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3315 p
= frag_var (rs_machine_dependent
, 4, 0,
3316 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3317 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3318 macro_build (p
, counter
, ep
,
3319 ((bfd_arch_bits_per_address (stdoutput
) == 32
3320 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3321 ? "addiu" : "daddiu"),
3322 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3323 if (ex
.X_add_number
!= 0)
3325 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3326 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3327 ex
.X_op
= O_constant
;
3328 macro_build ((char *) NULL
, counter
, &ex
,
3329 ((bfd_arch_bits_per_address (stdoutput
) == 32
3330 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3331 ? "addiu" : "daddiu"),
3332 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3335 else if (mips_pic
== SVR4_PIC
)
3340 /* This is the large GOT case. If this is a reference to an
3341 external symbol, we want
3342 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3344 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3345 Otherwise, for a reference to a local symbol, we want
3346 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3348 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3349 If there is a constant, it must be added in after. */
3350 ex
.X_add_number
= ep
->X_add_number
;
3351 ep
->X_add_number
= 0;
3352 if (reg_needs_delay (GP
))
3357 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3358 (int) BFD_RELOC_MIPS_GOT_HI16
);
3359 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3360 ((bfd_arch_bits_per_address (stdoutput
) == 32
3361 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3362 ? "addu" : "daddu"),
3363 "d,v,t", reg
, reg
, GP
);
3364 macro_build ((char *) NULL
, counter
, ep
,
3365 ((bfd_arch_bits_per_address (stdoutput
) == 32
3366 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3368 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3369 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3370 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3371 mips_opts
.warn_about_macros
),
3372 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3375 /* We need a nop before loading from $gp. This special
3376 check is required because the lui which starts the main
3377 instruction stream does not refer to $gp, and so will not
3378 insert the nop which may be required. */
3379 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3382 macro_build (p
, counter
, ep
,
3383 ((bfd_arch_bits_per_address (stdoutput
) == 32
3384 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3386 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3388 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3390 macro_build (p
, counter
, ep
,
3391 ((bfd_arch_bits_per_address (stdoutput
) == 32
3392 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3393 ? "addiu" : "daddiu"),
3394 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3395 if (ex
.X_add_number
!= 0)
3397 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3398 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3399 ex
.X_op
= O_constant
;
3400 macro_build ((char *) NULL
, counter
, &ex
,
3401 ((bfd_arch_bits_per_address (stdoutput
) == 32
3402 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3403 ? "addiu" : "daddiu"),
3404 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3407 else if (mips_pic
== EMBEDDED_PIC
)
3410 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3412 macro_build ((char *) NULL
, counter
, ep
,
3413 ((bfd_arch_bits_per_address (stdoutput
) == 32
3414 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3415 ? "addiu" : "daddiu"),
3416 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3424 * This routine implements the seemingly endless macro or synthesized
3425 * instructions and addressing modes in the mips assembly language. Many
3426 * of these macros are simple and are similar to each other. These could
3427 * probably be handled by some kind of table or grammer aproach instead of
3428 * this verbose method. Others are not simple macros but are more like
3429 * optimizing code generation.
3430 * One interesting optimization is when several store macros appear
3431 * consecutivly that would load AT with the upper half of the same address.
3432 * The ensuing load upper instructions are ommited. This implies some kind
3433 * of global optimization. We currently only optimize within a single macro.
3434 * For many of the load and store macros if the address is specified as a
3435 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3436 * first load register 'at' with zero and use it as the base register. The
3437 * mips assembler simply uses register $zero. Just one tiny optimization
3442 struct mips_cl_insn
*ip
;
3444 register int treg
, sreg
, dreg
, breg
;
3460 bfd_reloc_code_real_type r
;
3462 int hold_mips_optimize
;
3464 assert (! mips_opts
.mips16
);
3466 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3467 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3468 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3469 mask
= ip
->insn_mo
->mask
;
3471 expr1
.X_op
= O_constant
;
3472 expr1
.X_op_symbol
= NULL
;
3473 expr1
.X_add_symbol
= NULL
;
3474 expr1
.X_add_number
= 1;
3486 mips_emit_delays (true);
3487 ++mips_opts
.noreorder
;
3488 mips_any_noreorder
= 1;
3490 expr1
.X_add_number
= 8;
3491 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3493 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3496 macro_build ((char *) NULL
, &icnt
, NULL
,
3497 dbl
? "dsub" : "sub",
3498 "d,v,t", dreg
, 0, sreg
);
3500 --mips_opts
.noreorder
;
3521 if (imm_expr
.X_op
== O_constant
3522 && imm_expr
.X_add_number
>= -0x8000
3523 && imm_expr
.X_add_number
< 0x8000)
3525 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3526 (int) BFD_RELOC_LO16
);
3529 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3530 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3549 if (imm_expr
.X_op
== O_constant
3550 && imm_expr
.X_add_number
>= 0
3551 && imm_expr
.X_add_number
< 0x10000)
3553 if (mask
!= M_NOR_I
)
3554 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3555 sreg
, (int) BFD_RELOC_LO16
);
3558 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3559 treg
, sreg
, (int) BFD_RELOC_LO16
);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3566 load_register (&icnt
, AT
, &imm_expr
, 0);
3567 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3584 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3586 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3590 load_register (&icnt
, AT
, &imm_expr
, 0);
3591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3600 likely
? "bgezl" : "bgez",
3606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3607 likely
? "blezl" : "blez",
3611 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3612 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3613 likely
? "beql" : "beq",
3620 /* check for > max integer */
3621 maxnum
= 0x7fffffff;
3622 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3629 if (imm_expr
.X_op
== O_constant
3630 && imm_expr
.X_add_number
>= maxnum
3631 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3634 /* result is always false */
3637 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3638 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3642 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3643 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3648 if (imm_expr
.X_op
!= O_constant
)
3649 as_bad (_("Unsupported large constant"));
3650 imm_expr
.X_add_number
++;
3654 if (mask
== M_BGEL_I
)
3656 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3659 likely
? "bgezl" : "bgez",
3663 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3666 likely
? "bgtzl" : "bgtz",
3670 maxnum
= 0x7fffffff;
3671 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3678 maxnum
= - maxnum
- 1;
3679 if (imm_expr
.X_op
== O_constant
3680 && imm_expr
.X_add_number
<= maxnum
3681 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3684 /* result is always true */
3685 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3686 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3689 set_at (&icnt
, sreg
, 0);
3690 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3691 likely
? "beql" : "beq",
3702 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3703 likely
? "beql" : "beq",
3707 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3710 likely
? "beql" : "beq",
3718 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3719 && imm_expr
.X_op
== O_constant
3720 && imm_expr
.X_add_number
== 0xffffffff))
3722 if (imm_expr
.X_op
!= O_constant
)
3723 as_bad (_("Unsupported large constant"));
3724 imm_expr
.X_add_number
++;
3728 if (mask
== M_BGEUL_I
)
3730 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3732 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3734 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3735 likely
? "bnel" : "bne",
3739 set_at (&icnt
, sreg
, 1);
3740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3741 likely
? "beql" : "beq",
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "bgtzl" : "bgtz",
3757 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3758 likely
? "bltzl" : "bltz",
3762 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3763 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3764 likely
? "bnel" : "bne",
3773 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3774 likely
? "bnel" : "bne",
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3782 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3783 likely
? "bnel" : "bne",
3792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3793 likely
? "blezl" : "blez",
3799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3800 likely
? "bgezl" : "bgez",
3804 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3806 likely
? "beql" : "beq",
3813 maxnum
= 0x7fffffff;
3814 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3821 if (imm_expr
.X_op
== O_constant
3822 && imm_expr
.X_add_number
>= maxnum
3823 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3825 if (imm_expr
.X_op
!= O_constant
)
3826 as_bad (_("Unsupported large constant"));
3827 imm_expr
.X_add_number
++;
3831 if (mask
== M_BLTL_I
)
3833 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3835 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3836 likely
? "bltzl" : "bltz",
3840 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 likely
? "blezl" : "blez",
3847 set_at (&icnt
, sreg
, 0);
3848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3849 likely
? "bnel" : "bne",
3858 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3859 likely
? "beql" : "beq",
3865 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3868 likely
? "beql" : "beq",
3876 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3877 && imm_expr
.X_op
== O_constant
3878 && imm_expr
.X_add_number
== 0xffffffff))
3880 if (imm_expr
.X_op
!= O_constant
)
3881 as_bad (_("Unsupported large constant"));
3882 imm_expr
.X_add_number
++;
3886 if (mask
== M_BLTUL_I
)
3888 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3890 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3892 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3893 likely
? "beql" : "beq",
3897 set_at (&icnt
, sreg
, 1);
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3899 likely
? "bnel" : "bne",
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3909 likely
? "bltzl" : "bltz",
3915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3916 likely
? "bgtzl" : "bgtz",
3920 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3921 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3922 likely
? "bnel" : "bne",
3933 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3934 likely
? "bnel" : "bne",
3938 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3940 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3941 likely
? "bnel" : "bne",
3957 as_warn (_("Divide by zero."));
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3965 mips_emit_delays (true);
3966 ++mips_opts
.noreorder
;
3967 mips_any_noreorder
= 1;
3970 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3971 macro_build ((char *) NULL
, &icnt
, NULL
,
3972 dbl
? "ddiv" : "div",
3973 "z,s,t", sreg
, treg
);
3977 expr1
.X_add_number
= 8;
3978 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3979 macro_build ((char *) NULL
, &icnt
, NULL
,
3980 dbl
? "ddiv" : "div",
3981 "z,s,t", sreg
, treg
);
3982 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3984 expr1
.X_add_number
= -1;
3985 macro_build ((char *) NULL
, &icnt
, &expr1
,
3986 dbl
? "daddiu" : "addiu",
3987 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3988 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3989 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3992 expr1
.X_add_number
= 1;
3993 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3994 (int) BFD_RELOC_LO16
);
3995 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4000 expr1
.X_add_number
= 0x80000000;
4001 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4002 (int) BFD_RELOC_HI16
);
4006 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4007 /* We want to close the noreorder block as soon as possible, so
4008 that later insns are available for delay slot filling. */
4009 --mips_opts
.noreorder
;
4013 expr1
.X_add_number
= 8;
4014 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4015 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4017 /* We want to close the noreorder block as soon as possible, so
4018 that later insns are available for delay slot filling. */
4019 --mips_opts
.noreorder
;
4021 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4023 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4062 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4064 as_warn (_("Divide by zero."));
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4068 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4071 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4073 if (strcmp (s2
, "mflo") == 0)
4074 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4077 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4080 if (imm_expr
.X_op
== O_constant
4081 && imm_expr
.X_add_number
== -1
4082 && s
[strlen (s
) - 1] != 'u')
4084 if (strcmp (s2
, "mflo") == 0)
4087 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4090 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4094 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4098 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4099 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4100 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4119 mips_emit_delays (true);
4120 ++mips_opts
.noreorder
;
4121 mips_any_noreorder
= 1;
4124 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4125 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4126 /* We want to close the noreorder block as soon as possible, so
4127 that later insns are available for delay slot filling. */
4128 --mips_opts
.noreorder
;
4132 expr1
.X_add_number
= 8;
4133 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4134 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4136 /* We want to close the noreorder block as soon as possible, so
4137 that later insns are available for delay slot filling. */
4138 --mips_opts
.noreorder
;
4139 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4141 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4147 /* Load the address of a symbol into a register. If breg is not
4148 zero, we then add a base register to it. */
4150 /* When generating embedded PIC code, we permit expressions of
4153 where bar is an address in the .text section. These are used
4154 when getting the addresses of functions. We don't permit
4155 X_add_number to be non-zero, because if the symbol is
4156 external the relaxing code needs to know that any addend is
4157 purely the offset to X_op_symbol. */
4158 if (mips_pic
== EMBEDDED_PIC
4159 && offset_expr
.X_op
== O_subtract
4160 && now_seg
== text_section
4161 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4162 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4163 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4165 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4169 && offset_expr
.X_add_number
== 0)
4171 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4172 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4174 ((bfd_arch_bits_per_address (stdoutput
) == 32
4175 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4176 ? "addiu" : "daddiu"),
4177 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4181 if (offset_expr
.X_op
!= O_symbol
4182 && offset_expr
.X_op
!= O_constant
)
4184 as_bad (_("expression too complex"));
4185 offset_expr
.X_op
= O_constant
;
4199 if (offset_expr
.X_op
== O_constant
)
4200 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4201 else if (mips_pic
== NO_PIC
)
4203 /* If this is a reference to an GP relative symbol, we want
4204 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4206 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4207 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4208 If we have a constant, we need two instructions anyhow,
4209 so we may as well always use the latter form. */
4210 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4211 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4216 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4217 ((bfd_arch_bits_per_address (stdoutput
) == 32
4218 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4219 ? "addiu" : "daddiu"),
4220 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4221 p
= frag_var (rs_machine_dependent
, 8, 0,
4222 RELAX_ENCODE (4, 8, 0, 4, 0,
4223 mips_opts
.warn_about_macros
),
4224 offset_expr
.X_add_symbol
, (offsetT
) 0,
4227 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4230 macro_build (p
, &icnt
, &offset_expr
,
4231 ((bfd_arch_bits_per_address (stdoutput
) == 32
4232 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4233 ? "addiu" : "daddiu"),
4234 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4236 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4238 /* If this is a reference to an external symbol, and there
4239 is no constant, we want
4240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4241 For a local symbol, we want
4242 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4244 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4246 If we have a small constant, and this is a reference to
4247 an external symbol, we want
4248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4250 addiu $tempreg,$tempreg,<constant>
4251 For a local symbol, we want the same instruction
4252 sequence, but we output a BFD_RELOC_LO16 reloc on the
4255 If we have a large constant, and this is a reference to
4256 an external symbol, we want
4257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4258 lui $at,<hiconstant>
4259 addiu $at,$at,<loconstant>
4260 addu $tempreg,$tempreg,$at
4261 For a local symbol, we want the same instruction
4262 sequence, but we output a BFD_RELOC_LO16 reloc on the
4263 addiu instruction. */
4264 expr1
.X_add_number
= offset_expr
.X_add_number
;
4265 offset_expr
.X_add_number
= 0;
4267 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4269 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4270 if (expr1
.X_add_number
== 0)
4278 /* We're going to put in an addu instruction using
4279 tempreg, so we may as well insert the nop right
4281 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4285 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4286 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4288 ? mips_opts
.warn_about_macros
4290 offset_expr
.X_add_symbol
, (offsetT
) 0,
4294 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4297 macro_build (p
, &icnt
, &expr1
,
4298 ((bfd_arch_bits_per_address (stdoutput
) == 32
4299 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4300 ? "addiu" : "daddiu"),
4301 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4302 /* FIXME: If breg == 0, and the next instruction uses
4303 $tempreg, then if this variant case is used an extra
4304 nop will be generated. */
4306 else if (expr1
.X_add_number
>= -0x8000
4307 && expr1
.X_add_number
< 0x8000)
4309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4311 macro_build ((char *) NULL
, &icnt
, &expr1
,
4312 ((bfd_arch_bits_per_address (stdoutput
) == 32
4313 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4314 ? "addiu" : "daddiu"),
4315 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4316 (void) frag_var (rs_machine_dependent
, 0, 0,
4317 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4318 offset_expr
.X_add_symbol
, (offsetT
) 0,
4325 /* If we are going to add in a base register, and the
4326 target register and the base register are the same,
4327 then we are using AT as a temporary register. Since
4328 we want to load the constant into AT, we add our
4329 current AT (from the global offset table) and the
4330 register into the register now, and pretend we were
4331 not using a base register. */
4336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4338 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4339 ((bfd_arch_bits_per_address (stdoutput
) == 32
4340 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4341 ? "addu" : "daddu"),
4342 "d,v,t", treg
, AT
, breg
);
4348 /* Set mips_optimize around the lui instruction to avoid
4349 inserting an unnecessary nop after the lw. */
4350 hold_mips_optimize
= mips_optimize
;
4352 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4353 mips_optimize
= hold_mips_optimize
;
4355 macro_build ((char *) NULL
, &icnt
, &expr1
,
4356 ((bfd_arch_bits_per_address (stdoutput
) == 32
4357 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4358 ? "addiu" : "daddiu"),
4359 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4360 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4361 ((bfd_arch_bits_per_address (stdoutput
) == 32
4362 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4363 ? "addu" : "daddu"),
4364 "d,v,t", tempreg
, tempreg
, AT
);
4365 (void) frag_var (rs_machine_dependent
, 0, 0,
4366 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4367 offset_expr
.X_add_symbol
, (offsetT
) 0,
4372 else if (mips_pic
== SVR4_PIC
)
4376 /* This is the large GOT case. If this is a reference to an
4377 external symbol, and there is no constant, we want
4378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4379 addu $tempreg,$tempreg,$gp
4380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4381 For a local symbol, we want
4382 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4384 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4386 If we have a small constant, and this is a reference to
4387 an external symbol, we want
4388 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4389 addu $tempreg,$tempreg,$gp
4390 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4392 addiu $tempreg,$tempreg,<constant>
4393 For a local symbol, we want
4394 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4396 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4398 If we have a large constant, and this is a reference to
4399 an external symbol, we want
4400 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4401 addu $tempreg,$tempreg,$gp
4402 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4403 lui $at,<hiconstant>
4404 addiu $at,$at,<loconstant>
4405 addu $tempreg,$tempreg,$at
4406 For a local symbol, we want
4407 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4408 lui $at,<hiconstant>
4409 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4410 addu $tempreg,$tempreg,$at
4412 expr1
.X_add_number
= offset_expr
.X_add_number
;
4413 offset_expr
.X_add_number
= 0;
4415 if (reg_needs_delay (GP
))
4419 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4420 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4422 ((bfd_arch_bits_per_address (stdoutput
) == 32
4423 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4424 ? "addu" : "daddu"),
4425 "d,v,t", tempreg
, tempreg
, GP
);
4426 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4428 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4430 if (expr1
.X_add_number
== 0)
4438 /* We're going to put in an addu instruction using
4439 tempreg, so we may as well insert the nop right
4441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4446 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4447 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4450 ? mips_opts
.warn_about_macros
4452 offset_expr
.X_add_symbol
, (offsetT
) 0,
4455 else if (expr1
.X_add_number
>= -0x8000
4456 && expr1
.X_add_number
< 0x8000)
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4460 macro_build ((char *) NULL
, &icnt
, &expr1
,
4461 ((bfd_arch_bits_per_address (stdoutput
) == 32
4462 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4463 ? "addiu" : "daddiu"),
4464 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4466 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4467 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4469 ? mips_opts
.warn_about_macros
4471 offset_expr
.X_add_symbol
, (offsetT
) 0,
4478 /* If we are going to add in a base register, and the
4479 target register and the base register are the same,
4480 then we are using AT as a temporary register. Since
4481 we want to load the constant into AT, we add our
4482 current AT (from the global offset table) and the
4483 register into the register now, and pretend we were
4484 not using a base register. */
4492 assert (tempreg
== AT
);
4493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4496 ((bfd_arch_bits_per_address (stdoutput
) == 32
4497 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4498 ? "addu" : "daddu"),
4499 "d,v,t", treg
, AT
, breg
);
4504 /* Set mips_optimize around the lui instruction to avoid
4505 inserting an unnecessary nop after the lw. */
4506 hold_mips_optimize
= mips_optimize
;
4508 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4509 mips_optimize
= hold_mips_optimize
;
4511 macro_build ((char *) NULL
, &icnt
, &expr1
,
4512 ((bfd_arch_bits_per_address (stdoutput
) == 32
4513 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4514 ? "addiu" : "daddiu"),
4515 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4517 ((bfd_arch_bits_per_address (stdoutput
) == 32
4518 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4519 ? "addu" : "daddu"),
4520 "d,v,t", dreg
, dreg
, AT
);
4522 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4523 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4526 ? mips_opts
.warn_about_macros
4528 offset_expr
.X_add_symbol
, (offsetT
) 0,
4536 /* This is needed because this instruction uses $gp, but
4537 the first instruction on the main stream does not. */
4538 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4541 macro_build (p
, &icnt
, &offset_expr
,
4543 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4545 if (expr1
.X_add_number
>= -0x8000
4546 && expr1
.X_add_number
< 0x8000)
4548 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4550 macro_build (p
, &icnt
, &expr1
,
4551 ((bfd_arch_bits_per_address (stdoutput
) == 32
4552 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4553 ? "addiu" : "daddiu"),
4554 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4555 /* FIXME: If add_number is 0, and there was no base
4556 register, the external symbol case ended with a load,
4557 so if the symbol turns out to not be external, and
4558 the next instruction uses tempreg, an unnecessary nop
4559 will be inserted. */
4565 /* We must add in the base register now, as in the
4566 external symbol case. */
4567 assert (tempreg
== AT
);
4568 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4570 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4571 ((bfd_arch_bits_per_address (stdoutput
) == 32
4572 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4573 ? "addu" : "daddu"),
4574 "d,v,t", treg
, AT
, breg
);
4577 /* We set breg to 0 because we have arranged to add
4578 it in in both cases. */
4582 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4584 macro_build (p
, &icnt
, &expr1
,
4585 ((bfd_arch_bits_per_address (stdoutput
) == 32
4586 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4587 ? "addiu" : "daddiu"),
4588 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4590 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4591 ((bfd_arch_bits_per_address (stdoutput
) == 32
4592 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4593 ? "addu" : "daddu"),
4594 "d,v,t", tempreg
, tempreg
, AT
);
4598 else if (mips_pic
== EMBEDDED_PIC
)
4601 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4603 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4604 ((bfd_arch_bits_per_address (stdoutput
) == 32
4605 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4606 ? "addiu" : "daddiu"),
4607 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4613 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4614 ((bfd_arch_bits_per_address (stdoutput
) == 32
4615 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4616 ? "addu" : "daddu"),
4617 "d,v,t", treg
, tempreg
, breg
);
4625 /* The j instruction may not be used in PIC code, since it
4626 requires an absolute address. We convert it to a b
4628 if (mips_pic
== NO_PIC
)
4629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4634 /* The jal instructions must be handled as macros because when
4635 generating PIC code they expand to multi-instruction
4636 sequences. Normally they are simple instructions. */
4641 if (mips_pic
== NO_PIC
4642 || mips_pic
== EMBEDDED_PIC
)
4643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4645 else if (mips_pic
== SVR4_PIC
)
4647 if (sreg
!= PIC_CALL_REG
)
4648 as_warn (_("MIPS PIC call to register other than $25"));
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4652 if (mips_cprestore_offset
< 0)
4653 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4656 expr1
.X_add_number
= mips_cprestore_offset
;
4657 macro_build ((char *) NULL
, &icnt
, &expr1
,
4658 ((bfd_arch_bits_per_address (stdoutput
) == 32
4659 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4661 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4670 if (mips_pic
== NO_PIC
)
4671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4672 else if (mips_pic
== SVR4_PIC
)
4674 /* If this is a reference to an external symbol, and we are
4675 using a small GOT, we want
4676 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4680 lw $gp,cprestore($sp)
4681 The cprestore value is set using the .cprestore
4682 pseudo-op. If we are using a big GOT, we want
4683 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4685 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4689 lw $gp,cprestore($sp)
4690 If the symbol is not external, we want
4691 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4693 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4696 lw $gp,cprestore($sp) */
4700 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4701 ((bfd_arch_bits_per_address (stdoutput
) == 32
4702 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4704 "t,o(b)", PIC_CALL_REG
,
4705 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4708 p
= frag_var (rs_machine_dependent
, 4, 0,
4709 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4710 offset_expr
.X_add_symbol
, (offsetT
) 0,
4717 if (reg_needs_delay (GP
))
4721 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4722 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4723 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4724 ((bfd_arch_bits_per_address (stdoutput
) == 32
4725 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4726 ? "addu" : "daddu"),
4727 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4728 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4729 ((bfd_arch_bits_per_address (stdoutput
) == 32
4730 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4732 "t,o(b)", PIC_CALL_REG
,
4733 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4736 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4737 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4739 offset_expr
.X_add_symbol
, (offsetT
) 0,
4743 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4746 macro_build (p
, &icnt
, &offset_expr
,
4747 ((bfd_arch_bits_per_address (stdoutput
) == 32
4748 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4750 "t,o(b)", PIC_CALL_REG
,
4751 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4753 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4756 macro_build (p
, &icnt
, &offset_expr
,
4757 ((bfd_arch_bits_per_address (stdoutput
) == 32
4758 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4759 ? "addiu" : "daddiu"),
4760 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4761 (int) BFD_RELOC_LO16
);
4762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4763 "jalr", "s", PIC_CALL_REG
);
4764 if (mips_cprestore_offset
< 0)
4765 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4768 if (mips_opts
.noreorder
)
4769 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4771 expr1
.X_add_number
= mips_cprestore_offset
;
4772 macro_build ((char *) NULL
, &icnt
, &expr1
,
4773 ((bfd_arch_bits_per_address (stdoutput
) == 32
4774 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4776 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4780 else if (mips_pic
== EMBEDDED_PIC
)
4782 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4783 /* The linker may expand the call to a longer sequence which
4784 uses $at, so we must break rather than return. */
4809 /* Itbl support may require additional care here. */
4814 /* Itbl support may require additional care here. */
4819 /* Itbl support may require additional care here. */
4824 /* Itbl support may require additional care here. */
4836 if (mips_cpu
== 4650)
4838 as_bad (_("opcode not supported on this processor"));
4842 /* Itbl support may require additional care here. */
4847 /* Itbl support may require additional care here. */
4852 /* Itbl support may require additional care here. */
4872 if (breg
== treg
|| coproc
|| lr
)
4894 /* Itbl support may require additional care here. */
4899 /* Itbl support may require additional care here. */
4904 /* Itbl support may require additional care here. */
4909 /* Itbl support may require additional care here. */
4925 if (mips_cpu
== 4650)
4927 as_bad (_("opcode not supported on this processor"));
4932 /* Itbl support may require additional care here. */
4936 /* Itbl support may require additional care here. */
4941 /* Itbl support may require additional care here. */
4953 /* Itbl support may require additional care here. */
4954 if (mask
== M_LWC1_AB
4955 || mask
== M_SWC1_AB
4956 || mask
== M_LDC1_AB
4957 || mask
== M_SDC1_AB
4966 if (offset_expr
.X_op
!= O_constant
4967 && offset_expr
.X_op
!= O_symbol
)
4969 as_bad (_("expression too complex"));
4970 offset_expr
.X_op
= O_constant
;
4973 /* A constant expression in PIC code can be handled just as it
4974 is in non PIC code. */
4975 if (mips_pic
== NO_PIC
4976 || offset_expr
.X_op
== O_constant
)
4978 /* If this is a reference to a GP relative symbol, and there
4979 is no base register, we want
4980 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4981 Otherwise, if there is no base register, we want
4982 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4983 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4984 If we have a constant, we need two instructions anyhow,
4985 so we always use the latter form.
4987 If we have a base register, and this is a reference to a
4988 GP relative symbol, we want
4989 addu $tempreg,$breg,$gp
4990 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4992 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4993 addu $tempreg,$tempreg,$breg
4994 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4995 With a constant we always use the latter case. */
4998 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4999 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5004 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5005 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5006 p
= frag_var (rs_machine_dependent
, 8, 0,
5007 RELAX_ENCODE (4, 8, 0, 4, 0,
5008 (mips_opts
.warn_about_macros
5010 && mips_opts
.noat
))),
5011 offset_expr
.X_add_symbol
, (offsetT
) 0,
5015 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5018 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5019 (int) BFD_RELOC_LO16
, tempreg
);
5023 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5024 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5030 ((bfd_arch_bits_per_address (stdoutput
) == 32
5031 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5032 ? "addu" : "daddu"),
5033 "d,v,t", tempreg
, breg
, GP
);
5034 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5035 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5036 p
= frag_var (rs_machine_dependent
, 12, 0,
5037 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5038 offset_expr
.X_add_symbol
, (offsetT
) 0,
5041 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5044 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5045 ((bfd_arch_bits_per_address (stdoutput
) == 32
5046 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5047 ? "addu" : "daddu"),
5048 "d,v,t", tempreg
, tempreg
, breg
);
5051 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5052 (int) BFD_RELOC_LO16
, tempreg
);
5055 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5057 /* If this is a reference to an external symbol, we want
5058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5060 <op> $treg,0($tempreg)
5062 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5064 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5065 <op> $treg,0($tempreg)
5066 If there is a base register, we add it to $tempreg before
5067 the <op>. If there is a constant, we stick it in the
5068 <op> instruction. We don't handle constants larger than
5069 16 bits, because we have no way to load the upper 16 bits
5070 (actually, we could handle them for the subset of cases
5071 in which we are not using $at). */
5072 assert (offset_expr
.X_op
== O_symbol
);
5073 expr1
.X_add_number
= offset_expr
.X_add_number
;
5074 offset_expr
.X_add_number
= 0;
5075 if (expr1
.X_add_number
< -0x8000
5076 || expr1
.X_add_number
>= 0x8000)
5077 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5079 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5080 ((bfd_arch_bits_per_address (stdoutput
) == 32
5081 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5083 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5085 p
= frag_var (rs_machine_dependent
, 4, 0,
5086 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5087 offset_expr
.X_add_symbol
, (offsetT
) 0,
5089 macro_build (p
, &icnt
, &offset_expr
,
5090 ((bfd_arch_bits_per_address (stdoutput
) == 32
5091 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5092 ? "addiu" : "daddiu"),
5093 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5096 ((bfd_arch_bits_per_address (stdoutput
) == 32
5097 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5098 ? "addu" : "daddu"),
5099 "d,v,t", tempreg
, tempreg
, breg
);
5100 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5101 (int) BFD_RELOC_LO16
, tempreg
);
5103 else if (mips_pic
== SVR4_PIC
)
5107 /* If this is a reference to an external symbol, we want
5108 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5109 addu $tempreg,$tempreg,$gp
5110 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5111 <op> $treg,0($tempreg)
5113 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5115 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5116 <op> $treg,0($tempreg)
5117 If there is a base register, we add it to $tempreg before
5118 the <op>. If there is a constant, we stick it in the
5119 <op> instruction. We don't handle constants larger than
5120 16 bits, because we have no way to load the upper 16 bits
5121 (actually, we could handle them for the subset of cases
5122 in which we are not using $at). */
5123 assert (offset_expr
.X_op
== O_symbol
);
5124 expr1
.X_add_number
= offset_expr
.X_add_number
;
5125 offset_expr
.X_add_number
= 0;
5126 if (expr1
.X_add_number
< -0x8000
5127 || expr1
.X_add_number
>= 0x8000)
5128 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5129 if (reg_needs_delay (GP
))
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5135 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5136 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5137 ((bfd_arch_bits_per_address (stdoutput
) == 32
5138 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5139 ? "addu" : "daddu"),
5140 "d,v,t", tempreg
, tempreg
, GP
);
5141 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5142 ((bfd_arch_bits_per_address (stdoutput
) == 32
5143 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5145 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5147 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5148 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5149 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5152 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5155 macro_build (p
, &icnt
, &offset_expr
,
5156 ((bfd_arch_bits_per_address (stdoutput
) == 32
5157 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5159 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5161 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5163 macro_build (p
, &icnt
, &offset_expr
,
5164 ((bfd_arch_bits_per_address (stdoutput
) == 32
5165 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5166 ? "addiu" : "daddiu"),
5167 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5170 ((bfd_arch_bits_per_address (stdoutput
) == 32
5171 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5172 ? "addu" : "daddu"),
5173 "d,v,t", tempreg
, tempreg
, breg
);
5174 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5175 (int) BFD_RELOC_LO16
, tempreg
);
5177 else if (mips_pic
== EMBEDDED_PIC
)
5179 /* If there is no base register, we want
5180 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5181 If there is a base register, we want
5182 addu $tempreg,$breg,$gp
5183 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5185 assert (offset_expr
.X_op
== O_symbol
);
5188 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5189 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5194 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5195 ((bfd_arch_bits_per_address (stdoutput
) == 32
5196 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5197 ? "addu" : "daddu"),
5198 "d,v,t", tempreg
, breg
, GP
);
5199 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5200 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5213 load_register (&icnt
, treg
, &imm_expr
, 0);
5217 load_register (&icnt
, treg
, &imm_expr
, 1);
5221 if (imm_expr
.X_op
== O_constant
)
5223 load_register (&icnt
, AT
, &imm_expr
, 0);
5224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5225 "mtc1", "t,G", AT
, treg
);
5230 assert (offset_expr
.X_op
== O_symbol
5231 && strcmp (segment_name (S_GET_SEGMENT
5232 (offset_expr
.X_add_symbol
)),
5234 && offset_expr
.X_add_number
== 0);
5235 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5236 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5241 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5242 the entire value, and in mips1 mode it is the high order 32
5243 bits of the value and the low order 32 bits are either zero
5244 or in offset_expr. */
5245 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5247 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5248 load_register (&icnt
, treg
, &imm_expr
, 1);
5253 if (target_big_endian
)
5265 load_register (&icnt
, hreg
, &imm_expr
, 0);
5268 if (offset_expr
.X_op
== O_absent
)
5269 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5273 assert (offset_expr
.X_op
== O_constant
);
5274 load_register (&icnt
, lreg
, &offset_expr
, 0);
5281 /* We know that sym is in the .rdata section. First we get the
5282 upper 16 bits of the address. */
5283 if (mips_pic
== NO_PIC
)
5285 /* FIXME: This won't work for a 64 bit address. */
5286 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5288 else if (mips_pic
== SVR4_PIC
)
5290 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5291 ((bfd_arch_bits_per_address (stdoutput
) == 32
5292 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5294 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5296 else if (mips_pic
== EMBEDDED_PIC
)
5298 /* For embedded PIC we pick up the entire address off $gp in
5299 a single instruction. */
5300 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5301 ((bfd_arch_bits_per_address (stdoutput
) == 32
5302 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5303 ? "addiu" : "daddiu"),
5304 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5305 offset_expr
.X_op
= O_constant
;
5306 offset_expr
.X_add_number
= 0;
5311 /* Now we load the register(s). */
5312 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5313 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5314 treg
, (int) BFD_RELOC_LO16
, AT
);
5317 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5318 treg
, (int) BFD_RELOC_LO16
, AT
);
5321 /* FIXME: How in the world do we deal with the possible
5323 offset_expr
.X_add_number
+= 4;
5324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5325 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5329 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5330 does not become a variant frag. */
5331 frag_wane (frag_now
);
5337 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5338 the entire value, and in mips1 mode it is the high order 32
5339 bits of the value and the low order 32 bits are either zero
5340 or in offset_expr. */
5341 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5343 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5344 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5346 "dmtc1", "t,S", AT
, treg
);
5349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5350 "mtc1", "t,G", AT
, treg
+ 1);
5351 if (offset_expr
.X_op
== O_absent
)
5352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5353 "mtc1", "t,G", 0, treg
);
5356 assert (offset_expr
.X_op
== O_constant
);
5357 load_register (&icnt
, AT
, &offset_expr
, 0);
5358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5359 "mtc1", "t,G", AT
, treg
);
5365 assert (offset_expr
.X_op
== O_symbol
5366 && offset_expr
.X_add_number
== 0);
5367 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5368 if (strcmp (s
, ".lit8") == 0)
5370 if (mips_opts
.isa
!= 1)
5372 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5373 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5377 r
= BFD_RELOC_MIPS_LITERAL
;
5382 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5383 if (mips_pic
== SVR4_PIC
)
5384 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5385 ((bfd_arch_bits_per_address (stdoutput
) == 32
5386 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5388 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5391 /* FIXME: This won't work for a 64 bit address. */
5392 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5395 if (mips_opts
.isa
!= 1)
5397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5398 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5400 /* To avoid confusion in tc_gen_reloc, we must ensure
5401 that this does not become a variant frag. */
5402 frag_wane (frag_now
);
5413 if (mips_cpu
== 4650)
5415 as_bad (_("opcode not supported on this processor"));
5418 /* Even on a big endian machine $fn comes before $fn+1. We have
5419 to adjust when loading from memory. */
5422 assert (mips_opts
.isa
== 1);
5423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5424 target_big_endian
? treg
+ 1 : treg
,
5426 /* FIXME: A possible overflow which I don't know how to deal
5428 offset_expr
.X_add_number
+= 4;
5429 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5430 target_big_endian
? treg
: treg
+ 1,
5433 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5434 does not become a variant frag. */
5435 frag_wane (frag_now
);
5444 * The MIPS assembler seems to check for X_add_number not
5445 * being double aligned and generating:
5448 * addiu at,at,%lo(foo+1)
5451 * But, the resulting address is the same after relocation so why
5452 * generate the extra instruction?
5454 if (mips_cpu
== 4650)
5456 as_bad (_("opcode not supported on this processor"));
5459 /* Itbl support may require additional care here. */
5461 if (mips_opts
.isa
!= 1)
5472 if (mips_cpu
== 4650)
5474 as_bad (_("opcode not supported on this processor"));
5478 if (mips_opts
.isa
!= 1)
5486 /* Itbl support may require additional care here. */
5491 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5502 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5512 if (offset_expr
.X_op
!= O_symbol
5513 && offset_expr
.X_op
!= O_constant
)
5515 as_bad (_("expression too complex"));
5516 offset_expr
.X_op
= O_constant
;
5519 /* Even on a big endian machine $fn comes before $fn+1. We have
5520 to adjust when loading from memory. We set coproc if we must
5521 load $fn+1 first. */
5522 /* Itbl support may require additional care here. */
5523 if (! target_big_endian
)
5526 if (mips_pic
== NO_PIC
5527 || offset_expr
.X_op
== O_constant
)
5529 /* If this is a reference to a GP relative symbol, we want
5530 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5531 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5532 If we have a base register, we use this
5534 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5535 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5536 If this is not a GP relative symbol, we want
5537 lui $at,<sym> (BFD_RELOC_HI16_S)
5538 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5539 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5540 If there is a base register, we add it to $at after the
5541 lui instruction. If there is a constant, we always use
5543 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5544 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5564 ((bfd_arch_bits_per_address (stdoutput
) == 32
5565 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5566 ? "addu" : "daddu"),
5567 "d,v,t", AT
, breg
, GP
);
5573 /* Itbl support may require additional care here. */
5574 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5575 coproc
? treg
+ 1 : treg
,
5576 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5577 offset_expr
.X_add_number
+= 4;
5579 /* Set mips_optimize to 2 to avoid inserting an
5581 hold_mips_optimize
= mips_optimize
;
5583 /* Itbl support may require additional care here. */
5584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5585 coproc
? treg
: treg
+ 1,
5586 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5587 mips_optimize
= hold_mips_optimize
;
5589 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5590 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5591 used_at
&& mips_opts
.noat
),
5592 offset_expr
.X_add_symbol
, (offsetT
) 0,
5595 /* We just generated two relocs. When tc_gen_reloc
5596 handles this case, it will skip the first reloc and
5597 handle the second. The second reloc already has an
5598 extra addend of 4, which we added above. We must
5599 subtract it out, and then subtract another 4 to make
5600 the first reloc come out right. The second reloc
5601 will come out right because we are going to add 4 to
5602 offset_expr when we build its instruction below.
5604 If we have a symbol, then we don't want to include
5605 the offset, because it will wind up being included
5606 when we generate the reloc. */
5608 if (offset_expr
.X_op
== O_constant
)
5609 offset_expr
.X_add_number
-= 8;
5612 offset_expr
.X_add_number
= -4;
5613 offset_expr
.X_op
= O_constant
;
5616 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5621 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5622 ((bfd_arch_bits_per_address (stdoutput
) == 32
5623 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5624 ? "addu" : "daddu"),
5625 "d,v,t", AT
, breg
, AT
);
5629 /* Itbl support may require additional care here. */
5630 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5631 coproc
? treg
+ 1 : treg
,
5632 (int) BFD_RELOC_LO16
, AT
);
5635 /* FIXME: How do we handle overflow here? */
5636 offset_expr
.X_add_number
+= 4;
5637 /* Itbl support may require additional care here. */
5638 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5639 coproc
? treg
: treg
+ 1,
5640 (int) BFD_RELOC_LO16
, AT
);
5642 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5646 /* If this is a reference to an external symbol, we want
5647 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5652 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5654 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5655 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5656 If there is a base register we add it to $at before the
5657 lwc1 instructions. If there is a constant we include it
5658 in the lwc1 instructions. */
5660 expr1
.X_add_number
= offset_expr
.X_add_number
;
5661 offset_expr
.X_add_number
= 0;
5662 if (expr1
.X_add_number
< -0x8000
5663 || expr1
.X_add_number
>= 0x8000 - 4)
5664 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5669 frag_grow (24 + off
);
5670 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5671 ((bfd_arch_bits_per_address (stdoutput
) == 32
5672 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5674 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5677 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5678 ((bfd_arch_bits_per_address (stdoutput
) == 32
5679 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5680 ? "addu" : "daddu"),
5681 "d,v,t", AT
, breg
, AT
);
5682 /* Itbl support may require additional care here. */
5683 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5684 coproc
? treg
+ 1 : treg
,
5685 (int) BFD_RELOC_LO16
, AT
);
5686 expr1
.X_add_number
+= 4;
5688 /* Set mips_optimize to 2 to avoid inserting an undesired
5690 hold_mips_optimize
= mips_optimize
;
5692 /* Itbl support may require additional care here. */
5693 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5694 coproc
? treg
: treg
+ 1,
5695 (int) BFD_RELOC_LO16
, AT
);
5696 mips_optimize
= hold_mips_optimize
;
5698 (void) frag_var (rs_machine_dependent
, 0, 0,
5699 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5700 offset_expr
.X_add_symbol
, (offsetT
) 0,
5703 else if (mips_pic
== SVR4_PIC
)
5707 /* If this is a reference to an external symbol, we want
5708 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5710 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5715 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5717 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5718 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5719 If there is a base register we add it to $at before the
5720 lwc1 instructions. If there is a constant we include it
5721 in the lwc1 instructions. */
5723 expr1
.X_add_number
= offset_expr
.X_add_number
;
5724 offset_expr
.X_add_number
= 0;
5725 if (expr1
.X_add_number
< -0x8000
5726 || expr1
.X_add_number
>= 0x8000 - 4)
5727 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5728 if (reg_needs_delay (GP
))
5737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5738 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5740 ((bfd_arch_bits_per_address (stdoutput
) == 32
5741 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5742 ? "addu" : "daddu"),
5743 "d,v,t", AT
, AT
, GP
);
5744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5745 ((bfd_arch_bits_per_address (stdoutput
) == 32
5746 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5748 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5752 ((bfd_arch_bits_per_address (stdoutput
) == 32
5753 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5754 ? "addu" : "daddu"),
5755 "d,v,t", AT
, breg
, AT
);
5756 /* Itbl support may require additional care here. */
5757 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5758 coproc
? treg
+ 1 : treg
,
5759 (int) BFD_RELOC_LO16
, AT
);
5760 expr1
.X_add_number
+= 4;
5762 /* Set mips_optimize to 2 to avoid inserting an undesired
5764 hold_mips_optimize
= mips_optimize
;
5766 /* Itbl support may require additional care here. */
5767 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5768 coproc
? treg
: treg
+ 1,
5769 (int) BFD_RELOC_LO16
, AT
);
5770 mips_optimize
= hold_mips_optimize
;
5771 expr1
.X_add_number
-= 4;
5773 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5774 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5775 8 + gpdel
+ off
, 1, 0),
5776 offset_expr
.X_add_symbol
, (offsetT
) 0,
5780 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5783 macro_build (p
, &icnt
, &offset_expr
,
5784 ((bfd_arch_bits_per_address (stdoutput
) == 32
5785 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5787 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5789 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5793 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5794 ((bfd_arch_bits_per_address (stdoutput
) == 32
5795 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5796 ? "addu" : "daddu"),
5797 "d,v,t", AT
, breg
, AT
);
5800 /* Itbl support may require additional care here. */
5801 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5802 coproc
? treg
+ 1 : treg
,
5803 (int) BFD_RELOC_LO16
, AT
);
5805 expr1
.X_add_number
+= 4;
5807 /* Set mips_optimize to 2 to avoid inserting an undesired
5809 hold_mips_optimize
= mips_optimize
;
5811 /* Itbl support may require additional care here. */
5812 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5813 coproc
? treg
: treg
+ 1,
5814 (int) BFD_RELOC_LO16
, AT
);
5815 mips_optimize
= hold_mips_optimize
;
5817 else if (mips_pic
== EMBEDDED_PIC
)
5819 /* If there is no base register, we use
5820 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5821 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5822 If we have a base register, we use
5824 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5825 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5834 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5835 ((bfd_arch_bits_per_address (stdoutput
) == 32
5836 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5837 ? "addu" : "daddu"),
5838 "d,v,t", AT
, breg
, GP
);
5843 /* Itbl support may require additional care here. */
5844 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5845 coproc
? treg
+ 1 : treg
,
5846 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5847 offset_expr
.X_add_number
+= 4;
5848 /* Itbl support may require additional care here. */
5849 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5850 coproc
? treg
: treg
+ 1,
5851 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5867 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5868 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5869 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5870 (int) BFD_RELOC_LO16
, breg
);
5871 offset_expr
.X_add_number
+= 4;
5872 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5873 (int) BFD_RELOC_LO16
, breg
);
5876 /* New code added to support COPZ instructions.
5877 This code builds table entries out of the macros in mip_opcodes.
5878 R4000 uses interlocks to handle coproc delays.
5879 Other chips (like the R3000) require nops to be inserted for delays.
5881 FIXME: Currently, we require that the user handle delays.
5882 In order to fill delay slots for non-interlocked chips,
5883 we must have a way to specify delays based on the coprocessor.
5884 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5885 What are the side-effects of the cop instruction?
5886 What cache support might we have and what are its effects?
5887 Both coprocessor & memory require delays. how long???
5888 What registers are read/set/modified?
5890 If an itbl is provided to interpret cop instructions,
5891 this knowledge can be encoded in the itbl spec. */
5905 /* For now we just do C (same as Cz). The parameter will be
5906 stored in insn_opcode by mips_ip. */
5907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5911 #ifdef LOSING_COMPILER
5913 /* Try and see if this is a new itbl instruction.
5914 This code builds table entries out of the macros in mip_opcodes.
5915 FIXME: For now we just assemble the expression and pass it's
5916 value along as a 32-bit immediate.
5917 We may want to have the assembler assemble this value,
5918 so that we gain the assembler's knowledge of delay slots,
5920 Would it be more efficient to use mask (id) here? */
5921 if (itbl_have_entries
5922 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5924 s
= ip
->insn_mo
->name
;
5926 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5927 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5934 as_warn (_("Macro used $at after \".set noat\""));
5939 struct mips_cl_insn
*ip
;
5941 register int treg
, sreg
, dreg
, breg
;
5957 bfd_reloc_code_real_type r
;
5960 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5961 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5962 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5963 mask
= ip
->insn_mo
->mask
;
5965 expr1
.X_op
= O_constant
;
5966 expr1
.X_op_symbol
= NULL
;
5967 expr1
.X_add_symbol
= NULL
;
5968 expr1
.X_add_number
= 1;
5972 #endif /* LOSING_COMPILER */
5977 macro_build ((char *) NULL
, &icnt
, NULL
,
5978 dbl
? "dmultu" : "multu",
5980 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5986 /* The MIPS assembler some times generates shifts and adds. I'm
5987 not trying to be that fancy. GCC should do this for us
5989 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5990 macro_build ((char *) NULL
, &icnt
, NULL
,
5991 dbl
? "dmult" : "mult",
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6006 mips_emit_delays (true);
6007 ++mips_opts
.noreorder
;
6008 mips_any_noreorder
= 1;
6010 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6011 macro_build ((char *) NULL
, &icnt
, NULL
,
6012 dbl
? "dmult" : "mult",
6013 "s,t", sreg
, imm
? AT
: treg
);
6014 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6015 macro_build ((char *) NULL
, &icnt
, NULL
,
6016 dbl
? "dsra32" : "sra",
6017 "d,w,<", dreg
, dreg
, 31);
6018 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6023 expr1
.X_add_number
= 8;
6024 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6028 --mips_opts
.noreorder
;
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6042 mips_emit_delays (true);
6043 ++mips_opts
.noreorder
;
6044 mips_any_noreorder
= 1;
6046 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6047 macro_build ((char *) NULL
, &icnt
, NULL
,
6048 dbl
? "dmultu" : "multu",
6049 "s,t", sreg
, imm
? AT
: treg
);
6050 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6051 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6053 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6056 expr1
.X_add_number
= 8;
6057 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6058 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6061 --mips_opts
.noreorder
;
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6069 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6073 if (imm_expr
.X_op
!= O_constant
)
6074 as_bad (_("rotate count too large"));
6075 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6076 (int) (imm_expr
.X_add_number
& 0x1f));
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6078 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6083 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6084 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6085 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6087 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6091 if (imm_expr
.X_op
!= O_constant
)
6092 as_bad (_("rotate count too large"));
6093 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6094 (int) (imm_expr
.X_add_number
& 0x1f));
6095 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6096 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6097 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6101 if (mips_cpu
== 4650)
6103 as_bad (_("opcode not supported on this processor"));
6106 assert (mips_opts
.isa
== 1);
6107 /* Even on a big endian machine $fn comes before $fn+1. We have
6108 to adjust when storing to memory. */
6109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6110 target_big_endian
? treg
+ 1 : treg
,
6111 (int) BFD_RELOC_LO16
, breg
);
6112 offset_expr
.X_add_number
+= 4;
6113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6114 target_big_endian
? treg
: treg
+ 1,
6115 (int) BFD_RELOC_LO16
, breg
);
6120 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6121 treg
, (int) BFD_RELOC_LO16
);
6123 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6124 sreg
, (int) BFD_RELOC_LO16
);
6127 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6129 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6130 dreg
, (int) BFD_RELOC_LO16
);
6135 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6137 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6138 sreg
, (int) BFD_RELOC_LO16
);
6143 as_warn (_("Instruction %s: result is always false"),
6145 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6148 if (imm_expr
.X_op
== O_constant
6149 && imm_expr
.X_add_number
>= 0
6150 && imm_expr
.X_add_number
< 0x10000)
6152 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6153 sreg
, (int) BFD_RELOC_LO16
);
6156 else if (imm_expr
.X_op
== O_constant
6157 && imm_expr
.X_add_number
> -0x8000
6158 && imm_expr
.X_add_number
< 0)
6160 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6161 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6162 ((bfd_arch_bits_per_address (stdoutput
) == 32
6163 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6164 ? "addiu" : "daddiu"),
6165 "t,r,j", dreg
, sreg
,
6166 (int) BFD_RELOC_LO16
);
6171 load_register (&icnt
, AT
, &imm_expr
, 0);
6172 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6176 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6177 (int) BFD_RELOC_LO16
);
6182 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6188 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6189 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6190 (int) BFD_RELOC_LO16
);
6193 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6195 if (imm_expr
.X_op
== O_constant
6196 && imm_expr
.X_add_number
>= -0x8000
6197 && imm_expr
.X_add_number
< 0x8000)
6199 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6200 mask
== M_SGE_I
? "slti" : "sltiu",
6201 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6206 load_register (&icnt
, AT
, &imm_expr
, 0);
6207 macro_build ((char *) NULL
, &icnt
, NULL
,
6208 mask
== M_SGE_I
? "slt" : "sltu",
6209 "d,v,t", dreg
, sreg
, AT
);
6212 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6213 (int) BFD_RELOC_LO16
);
6218 case M_SGT
: /* sreg > treg <==> treg < sreg */
6224 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6227 case M_SGT_I
: /* sreg > I <==> I < sreg */
6233 load_register (&icnt
, AT
, &imm_expr
, 0);
6234 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6237 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6243 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6244 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6245 (int) BFD_RELOC_LO16
);
6248 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6254 load_register (&icnt
, AT
, &imm_expr
, 0);
6255 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6256 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6257 (int) BFD_RELOC_LO16
);
6261 if (imm_expr
.X_op
== O_constant
6262 && imm_expr
.X_add_number
>= -0x8000
6263 && imm_expr
.X_add_number
< 0x8000)
6265 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6266 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6269 load_register (&icnt
, AT
, &imm_expr
, 0);
6270 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6274 if (imm_expr
.X_op
== O_constant
6275 && imm_expr
.X_add_number
>= -0x8000
6276 && imm_expr
.X_add_number
< 0x8000)
6278 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6279 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6282 load_register (&icnt
, AT
, &imm_expr
, 0);
6283 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6289 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6292 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6296 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6298 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6304 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6306 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6312 as_warn (_("Instruction %s: result is always true"),
6314 macro_build ((char *) NULL
, &icnt
, &expr1
,
6315 ((bfd_arch_bits_per_address (stdoutput
) == 32
6316 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6317 ? "addiu" : "daddiu"),
6318 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6321 if (imm_expr
.X_op
== O_constant
6322 && imm_expr
.X_add_number
>= 0
6323 && imm_expr
.X_add_number
< 0x10000)
6325 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6326 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6329 else if (imm_expr
.X_op
== O_constant
6330 && imm_expr
.X_add_number
> -0x8000
6331 && imm_expr
.X_add_number
< 0)
6333 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6334 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6335 ((bfd_arch_bits_per_address (stdoutput
) == 32
6336 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6337 ? "addiu" : "daddiu"),
6338 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6343 load_register (&icnt
, AT
, &imm_expr
, 0);
6344 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6348 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6356 if (imm_expr
.X_op
== O_constant
6357 && imm_expr
.X_add_number
> -0x8000
6358 && imm_expr
.X_add_number
<= 0x8000)
6360 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6361 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6362 dbl
? "daddi" : "addi",
6363 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6366 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6367 macro_build ((char *) NULL
, &icnt
, NULL
,
6368 dbl
? "dsub" : "sub",
6369 "d,v,t", dreg
, sreg
, AT
);
6375 if (imm_expr
.X_op
== O_constant
6376 && imm_expr
.X_add_number
> -0x8000
6377 && imm_expr
.X_add_number
<= 0x8000)
6379 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6380 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6381 dbl
? "daddiu" : "addiu",
6382 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6385 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6386 macro_build ((char *) NULL
, &icnt
, NULL
,
6387 dbl
? "dsubu" : "subu",
6388 "d,v,t", dreg
, sreg
, AT
);
6409 load_register (&icnt
, AT
, &imm_expr
, 0);
6410 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6415 assert (mips_opts
.isa
== 1);
6416 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6417 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6420 * Is the double cfc1 instruction a bug in the mips assembler;
6421 * or is there a reason for it?
6423 mips_emit_delays (true);
6424 ++mips_opts
.noreorder
;
6425 mips_any_noreorder
= 1;
6426 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6427 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6428 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6429 expr1
.X_add_number
= 3;
6430 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6431 (int) BFD_RELOC_LO16
);
6432 expr1
.X_add_number
= 2;
6433 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6434 (int) BFD_RELOC_LO16
);
6435 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6436 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6437 macro_build ((char *) NULL
, &icnt
, NULL
,
6438 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6439 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6440 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6441 --mips_opts
.noreorder
;
6450 if (offset_expr
.X_add_number
>= 0x7fff)
6451 as_bad (_("operand overflow"));
6452 /* avoid load delay */
6453 if (! target_big_endian
)
6454 offset_expr
.X_add_number
+= 1;
6455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6456 (int) BFD_RELOC_LO16
, breg
);
6457 if (! target_big_endian
)
6458 offset_expr
.X_add_number
-= 1;
6460 offset_expr
.X_add_number
+= 1;
6461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6462 (int) BFD_RELOC_LO16
, breg
);
6463 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6464 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6477 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6478 as_bad (_("operand overflow"));
6479 if (! target_big_endian
)
6480 offset_expr
.X_add_number
+= off
;
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, breg
);
6483 if (! target_big_endian
)
6484 offset_expr
.X_add_number
-= off
;
6486 offset_expr
.X_add_number
+= off
;
6487 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6488 (int) BFD_RELOC_LO16
, breg
);
6501 load_address (&icnt
, AT
, &offset_expr
);
6503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6504 ((bfd_arch_bits_per_address (stdoutput
) == 32
6505 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6506 ? "addu" : "daddu"),
6507 "d,v,t", AT
, AT
, breg
);
6508 if (! target_big_endian
)
6509 expr1
.X_add_number
= off
;
6511 expr1
.X_add_number
= 0;
6512 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6513 (int) BFD_RELOC_LO16
, AT
);
6514 if (! target_big_endian
)
6515 expr1
.X_add_number
= 0;
6517 expr1
.X_add_number
= off
;
6518 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6519 (int) BFD_RELOC_LO16
, AT
);
6524 load_address (&icnt
, AT
, &offset_expr
);
6526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6527 ((bfd_arch_bits_per_address (stdoutput
) == 32
6528 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6529 ? "addu" : "daddu"),
6530 "d,v,t", AT
, AT
, breg
);
6531 if (target_big_endian
)
6532 expr1
.X_add_number
= 0;
6533 macro_build ((char *) NULL
, &icnt
, &expr1
,
6534 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6535 (int) BFD_RELOC_LO16
, AT
);
6536 if (target_big_endian
)
6537 expr1
.X_add_number
= 1;
6539 expr1
.X_add_number
= 0;
6540 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6541 (int) BFD_RELOC_LO16
, AT
);
6542 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6544 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6549 if (offset_expr
.X_add_number
>= 0x7fff)
6550 as_bad (_("operand overflow"));
6551 if (target_big_endian
)
6552 offset_expr
.X_add_number
+= 1;
6553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, breg
);
6555 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6556 if (target_big_endian
)
6557 offset_expr
.X_add_number
-= 1;
6559 offset_expr
.X_add_number
+= 1;
6560 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6561 (int) BFD_RELOC_LO16
, breg
);
6574 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6575 as_bad (_("operand overflow"));
6576 if (! target_big_endian
)
6577 offset_expr
.X_add_number
+= off
;
6578 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6579 (int) BFD_RELOC_LO16
, breg
);
6580 if (! target_big_endian
)
6581 offset_expr
.X_add_number
-= off
;
6583 offset_expr
.X_add_number
+= off
;
6584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6585 (int) BFD_RELOC_LO16
, breg
);
6598 load_address (&icnt
, AT
, &offset_expr
);
6600 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6601 ((bfd_arch_bits_per_address (stdoutput
) == 32
6602 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6603 ? "addu" : "daddu"),
6604 "d,v,t", AT
, AT
, breg
);
6605 if (! target_big_endian
)
6606 expr1
.X_add_number
= off
;
6608 expr1
.X_add_number
= 0;
6609 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6610 (int) BFD_RELOC_LO16
, AT
);
6611 if (! target_big_endian
)
6612 expr1
.X_add_number
= 0;
6614 expr1
.X_add_number
= off
;
6615 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6616 (int) BFD_RELOC_LO16
, AT
);
6620 load_address (&icnt
, AT
, &offset_expr
);
6622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6623 ((bfd_arch_bits_per_address (stdoutput
) == 32
6624 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6625 ? "addu" : "daddu"),
6626 "d,v,t", AT
, AT
, breg
);
6627 if (! target_big_endian
)
6628 expr1
.X_add_number
= 0;
6629 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6630 (int) BFD_RELOC_LO16
, AT
);
6631 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6633 if (! target_big_endian
)
6634 expr1
.X_add_number
= 1;
6636 expr1
.X_add_number
= 0;
6637 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6638 (int) BFD_RELOC_LO16
, AT
);
6639 if (! target_big_endian
)
6640 expr1
.X_add_number
= 0;
6642 expr1
.X_add_number
= 1;
6643 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6644 (int) BFD_RELOC_LO16
, AT
);
6645 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6647 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6652 /* FIXME: Check if this is one of the itbl macros, since they
6653 are added dynamically. */
6654 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6658 as_warn (_("Macro used $at after \".set noat\""));
6661 /* Implement macros in mips16 mode. */
6665 struct mips_cl_insn
*ip
;
6668 int xreg
, yreg
, zreg
, tmp
;
6672 const char *s
, *s2
, *s3
;
6674 mask
= ip
->insn_mo
->mask
;
6676 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6677 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6678 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6682 expr1
.X_op
= O_constant
;
6683 expr1
.X_op_symbol
= NULL
;
6684 expr1
.X_add_symbol
= NULL
;
6685 expr1
.X_add_number
= 1;
6704 mips_emit_delays (true);
6705 ++mips_opts
.noreorder
;
6706 mips_any_noreorder
= 1;
6707 macro_build ((char *) NULL
, &icnt
, NULL
,
6708 dbl
? "ddiv" : "div",
6709 "0,x,y", xreg
, yreg
);
6710 expr1
.X_add_number
= 2;
6711 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6712 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6714 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6715 since that causes an overflow. We should do that as well,
6716 but I don't see how to do the comparisons without a temporary
6718 --mips_opts
.noreorder
;
6719 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6738 mips_emit_delays (true);
6739 ++mips_opts
.noreorder
;
6740 mips_any_noreorder
= 1;
6741 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6742 expr1
.X_add_number
= 2;
6743 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6744 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6745 --mips_opts
.noreorder
;
6746 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6752 macro_build ((char *) NULL
, &icnt
, NULL
,
6753 dbl
? "dmultu" : "multu",
6755 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6763 if (imm_expr
.X_op
!= O_constant
)
6764 as_bad (_("Unsupported large constant"));
6765 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6766 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6767 dbl
? "daddiu" : "addiu",
6768 "y,x,4", yreg
, xreg
);
6772 if (imm_expr
.X_op
!= O_constant
)
6773 as_bad (_("Unsupported large constant"));
6774 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6775 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6780 if (imm_expr
.X_op
!= O_constant
)
6781 as_bad (_("Unsupported large constant"));
6782 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6783 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6806 goto do_reverse_branch
;
6810 goto do_reverse_branch
;
6822 goto do_reverse_branch
;
6833 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6862 goto do_addone_branch_i
;
6867 goto do_addone_branch_i
;
6882 goto do_addone_branch_i
;
6889 if (imm_expr
.X_op
!= O_constant
)
6890 as_bad (_("Unsupported large constant"));
6891 ++imm_expr
.X_add_number
;
6894 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6895 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6899 expr1
.X_add_number
= 0;
6900 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6903 "move", "y,X", xreg
, yreg
);
6904 expr1
.X_add_number
= 2;
6905 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6907 "neg", "x,w", xreg
, xreg
);
6911 /* For consistency checking, verify that all bits are specified either
6912 by the match/mask part of the instruction definition, or by the
6915 validate_mips_insn (opc
)
6916 const struct mips_opcode
*opc
;
6918 const char *p
= opc
->args
;
6920 unsigned long used_bits
= opc
->mask
;
6922 if ((used_bits
& opc
->match
) != opc
->match
)
6924 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6925 opc
->name
, opc
->args
);
6928 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6935 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6936 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6938 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6939 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6940 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6941 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6943 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6946 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6947 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6948 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6949 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6950 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6951 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6952 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6953 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6954 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6955 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6956 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6958 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6959 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6960 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6961 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6963 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6964 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6965 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6966 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6967 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6968 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6969 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6970 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6971 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6974 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6976 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6977 c
, opc
->name
, opc
->args
);
6981 if (used_bits
!= 0xffffffff)
6983 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6984 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6990 /* This routine assembles an instruction into its binary format. As a
6991 side effect, it sets one of the global variables imm_reloc or
6992 offset_reloc to the type of relocation to do if one of the operands
6993 is an address expression. */
6998 struct mips_cl_insn
*ip
;
7003 struct mips_opcode
*insn
;
7006 unsigned int lastregno
= 0;
7009 int full_opcode_match
= 1;
7013 /* If the instruction contains a '.', we first try to match an instruction
7014 including the '.'. Then we try again without the '.'. */
7016 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7019 /* If we stopped on whitespace, then replace the whitespace with null for
7020 the call to hash_find. Save the character we replaced just in case we
7021 have to re-parse the instruction. */
7022 if (isspace ((unsigned char) *s
))
7028 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7030 /* If we didn't find the instruction in the opcode table, try again, but
7031 this time with just the instruction up to, but not including the
7035 /* Restore the character we overwrite above (if any). */
7039 /* Scan up to the first '.' or whitespace. */
7040 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7043 /* If we did not find a '.', then we can quit now. */
7046 insn_error
= "unrecognized opcode";
7050 /* Lookup the instruction in the hash table. */
7052 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7054 insn_error
= "unrecognized opcode";
7058 full_opcode_match
= 0;
7066 assert (strcmp (insn
->name
, str
) == 0);
7068 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7073 if (insn
->pinfo
!= INSN_MACRO
)
7075 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7081 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7082 && strcmp (insn
->name
, insn
[1].name
) == 0)
7089 static char buf
[100];
7091 _("opcode not supported on this processor: %d (MIPS%d)"),
7092 mips_cpu
, mips_opts
.isa
);
7100 ip
->insn_opcode
= insn
->match
;
7101 for (args
= insn
->args
;; ++args
)
7107 case '\0': /* end of args */
7120 ip
->insn_opcode
|= lastregno
<< 21;
7125 ip
->insn_opcode
|= lastregno
<< 16;
7129 ip
->insn_opcode
|= lastregno
<< 11;
7135 /* Handle optional base register.
7136 Either the base register is omitted or
7137 we must have a left paren. */
7138 /* This is dependent on the next operand specifier
7139 is a base register specification. */
7140 assert (args
[1] == 'b' || args
[1] == '5'
7141 || args
[1] == '-' || args
[1] == '4');
7145 case ')': /* these must match exactly */
7150 case '<': /* must be at least one digit */
7152 * According to the manual, if the shift amount is greater
7153 * than 31 or less than 0 the the shift amount should be
7154 * mod 32. In reality the mips assembler issues an error.
7155 * We issue a warning and mask out all but the low 5 bits.
7157 my_getExpression (&imm_expr
, s
);
7158 check_absolute_expr (ip
, &imm_expr
);
7159 if ((unsigned long) imm_expr
.X_add_number
> 31)
7161 as_warn (_("Improper shift amount (%ld)"),
7162 (long) imm_expr
.X_add_number
);
7163 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7165 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7166 imm_expr
.X_op
= O_absent
;
7170 case '>': /* shift amount minus 32 */
7171 my_getExpression (&imm_expr
, s
);
7172 check_absolute_expr (ip
, &imm_expr
);
7173 if ((unsigned long) imm_expr
.X_add_number
< 32
7174 || (unsigned long) imm_expr
.X_add_number
> 63)
7176 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7177 imm_expr
.X_op
= O_absent
;
7182 case 'k': /* cache code */
7183 case 'h': /* prefx code */
7184 my_getExpression (&imm_expr
, s
);
7185 check_absolute_expr (ip
, &imm_expr
);
7186 if ((unsigned long) imm_expr
.X_add_number
> 31)
7188 as_warn (_("Invalid value for `%s' (%lu)"),
7190 (unsigned long) imm_expr
.X_add_number
);
7191 imm_expr
.X_add_number
&= 0x1f;
7194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7196 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7197 imm_expr
.X_op
= O_absent
;
7201 case 'c': /* break code */
7202 my_getExpression (&imm_expr
, s
);
7203 check_absolute_expr (ip
, &imm_expr
);
7204 if ((unsigned) imm_expr
.X_add_number
> 1023)
7206 as_warn (_("Illegal break code (%ld)"),
7207 (long) imm_expr
.X_add_number
);
7208 imm_expr
.X_add_number
&= 0x3ff;
7210 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7211 imm_expr
.X_op
= O_absent
;
7215 case 'q': /* lower break code */
7216 my_getExpression (&imm_expr
, s
);
7217 check_absolute_expr (ip
, &imm_expr
);
7218 if ((unsigned) imm_expr
.X_add_number
> 1023)
7220 as_warn (_("Illegal lower break code (%ld)"),
7221 (long) imm_expr
.X_add_number
);
7222 imm_expr
.X_add_number
&= 0x3ff;
7224 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7225 imm_expr
.X_op
= O_absent
;
7229 case 'B': /* syscall code */
7230 my_getExpression (&imm_expr
, s
);
7231 check_absolute_expr (ip
, &imm_expr
);
7232 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7233 as_warn (_("Illegal syscall code (%ld)"),
7234 (long) imm_expr
.X_add_number
);
7235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7236 imm_expr
.X_op
= O_absent
;
7240 case 'C': /* Coprocessor code */
7241 my_getExpression (&imm_expr
, s
);
7242 check_absolute_expr (ip
, &imm_expr
);
7243 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7245 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7246 (long) imm_expr
.X_add_number
);
7247 imm_expr
.X_add_number
&= ((1<<25) - 1);
7249 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7250 imm_expr
.X_op
= O_absent
;
7254 case 'P': /* Performance register */
7255 my_getExpression (&imm_expr
, s
);
7256 check_absolute_expr (ip
, &imm_expr
);
7257 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7259 as_warn (_("Invalidate performance regster (%ld)"),
7260 (long) imm_expr
.X_add_number
);
7261 imm_expr
.X_add_number
&= 1;
7263 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7264 imm_expr
.X_op
= O_absent
;
7268 case 'b': /* base register */
7269 case 'd': /* destination register */
7270 case 's': /* source register */
7271 case 't': /* target register */
7272 case 'r': /* both target and source */
7273 case 'v': /* both dest and source */
7274 case 'w': /* both dest and target */
7275 case 'E': /* coprocessor target register */
7276 case 'G': /* coprocessor destination register */
7277 case 'x': /* ignore register name */
7278 case 'z': /* must be zero register */
7283 if (isdigit ((unsigned char) s
[1]))
7293 while (isdigit ((unsigned char) *s
));
7295 as_bad (_("Invalid register number (%d)"), regno
);
7297 else if (*args
== 'E' || *args
== 'G')
7301 if (s
[1] == 'f' && s
[2] == 'p')
7306 else if (s
[1] == 's' && s
[2] == 'p')
7311 else if (s
[1] == 'g' && s
[2] == 'p')
7316 else if (s
[1] == 'a' && s
[2] == 't')
7321 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7326 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7331 else if (itbl_have_entries
)
7336 p
= s
+ 1; /* advance past '$' */
7337 n
= itbl_get_field (&p
); /* n is name */
7339 /* See if this is a register defined in an
7341 if (itbl_get_reg_val (n
, &r
))
7343 /* Get_field advances to the start of
7344 the next field, so we need to back
7345 rack to the end of the last field. */
7349 s
= strchr (s
, '\0');
7362 as_warn (_("Used $at without \".set noat\""));
7368 if (c
== 'r' || c
== 'v' || c
== 'w')
7375 /* 'z' only matches $0. */
7376 if (c
== 'z' && regno
!= 0)
7379 /* Now that we have assembled one operand, we use the args string
7380 * to figure out where it goes in the instruction. */
7387 ip
->insn_opcode
|= regno
<< 21;
7391 ip
->insn_opcode
|= regno
<< 11;
7396 ip
->insn_opcode
|= regno
<< 16;
7399 /* This case exists because on the r3000 trunc
7400 expands into a macro which requires a gp
7401 register. On the r6000 or r4000 it is
7402 assembled into a single instruction which
7403 ignores the register. Thus the insn version
7404 is MIPS_ISA2 and uses 'x', and the macro
7405 version is MIPS_ISA1 and uses 't'. */
7408 /* This case is for the div instruction, which
7409 acts differently if the destination argument
7410 is $0. This only matches $0, and is checked
7411 outside the switch. */
7414 /* Itbl operand; not yet implemented. FIXME ?? */
7416 /* What about all other operands like 'i', which
7417 can be specified in the opcode table? */
7427 ip
->insn_opcode
|= lastregno
<< 21;
7430 ip
->insn_opcode
|= lastregno
<< 16;
7435 case 'D': /* floating point destination register */
7436 case 'S': /* floating point source register */
7437 case 'T': /* floating point target register */
7438 case 'R': /* floating point source register */
7442 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7452 while (isdigit ((unsigned char) *s
));
7455 as_bad (_("Invalid float register number (%d)"), regno
);
7457 if ((regno
& 1) != 0
7458 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7459 && ! (strcmp (str
, "mtc1") == 0
7460 || strcmp (str
, "mfc1") == 0
7461 || strcmp (str
, "lwc1") == 0
7462 || strcmp (str
, "swc1") == 0
7463 || strcmp (str
, "l.s") == 0
7464 || strcmp (str
, "s.s") == 0))
7465 as_warn (_("Float register should be even, was %d"),
7473 if (c
== 'V' || c
== 'W')
7483 ip
->insn_opcode
|= regno
<< 6;
7487 ip
->insn_opcode
|= regno
<< 11;
7491 ip
->insn_opcode
|= regno
<< 16;
7494 ip
->insn_opcode
|= regno
<< 21;
7505 ip
->insn_opcode
|= lastregno
<< 11;
7508 ip
->insn_opcode
|= lastregno
<< 16;
7514 my_getExpression (&imm_expr
, s
);
7515 if (imm_expr
.X_op
!= O_big
7516 && imm_expr
.X_op
!= O_constant
)
7517 insn_error
= _("absolute expression required");
7522 my_getExpression (&offset_expr
, s
);
7523 imm_reloc
= BFD_RELOC_32
;
7535 unsigned char temp
[8];
7537 unsigned int length
;
7542 /* These only appear as the last operand in an
7543 instruction, and every instruction that accepts
7544 them in any variant accepts them in all variants.
7545 This means we don't have to worry about backing out
7546 any changes if the instruction does not match.
7548 The difference between them is the size of the
7549 floating point constant and where it goes. For 'F'
7550 and 'L' the constant is 64 bits; for 'f' and 'l' it
7551 is 32 bits. Where the constant is placed is based
7552 on how the MIPS assembler does things:
7555 f -- immediate value
7558 The .lit4 and .lit8 sections are only used if
7559 permitted by the -G argument.
7561 When generating embedded PIC code, we use the
7562 .lit8 section but not the .lit4 section (we can do
7563 .lit4 inline easily; we need to put .lit8
7564 somewhere in the data segment, and using .lit8
7565 permits the linker to eventually combine identical
7568 f64
= *args
== 'F' || *args
== 'L';
7570 save_in
= input_line_pointer
;
7571 input_line_pointer
= s
;
7572 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7574 s
= input_line_pointer
;
7575 input_line_pointer
= save_in
;
7576 if (err
!= NULL
&& *err
!= '\0')
7578 as_bad (_("Bad floating point constant: %s"), err
);
7579 memset (temp
, '\0', sizeof temp
);
7580 length
= f64
? 8 : 4;
7583 assert (length
== (f64
? 8 : 4));
7587 && (! USE_GLOBAL_POINTER_OPT
7588 || mips_pic
== EMBEDDED_PIC
7589 || g_switch_value
< 4
7590 || (temp
[0] == 0 && temp
[1] == 0)
7591 || (temp
[2] == 0 && temp
[3] == 0))))
7593 imm_expr
.X_op
= O_constant
;
7594 if (! target_big_endian
)
7595 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7597 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7600 && ((temp
[0] == 0 && temp
[1] == 0)
7601 || (temp
[2] == 0 && temp
[3] == 0))
7602 && ((temp
[4] == 0 && temp
[5] == 0)
7603 || (temp
[6] == 0 && temp
[7] == 0)))
7605 /* The value is simple enough to load with a
7606 couple of instructions. In mips1 mode, set
7607 imm_expr to the high order 32 bits and
7608 offset_expr to the low order 32 bits.
7609 Otherwise, set imm_expr to the entire 64 bit
7611 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7613 imm_expr
.X_op
= O_constant
;
7614 offset_expr
.X_op
= O_constant
;
7615 if (! target_big_endian
)
7617 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7618 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7622 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7623 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7625 if (offset_expr
.X_add_number
== 0)
7626 offset_expr
.X_op
= O_absent
;
7628 else if (sizeof (imm_expr
.X_add_number
) > 4)
7630 imm_expr
.X_op
= O_constant
;
7631 if (! target_big_endian
)
7632 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7634 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7638 imm_expr
.X_op
= O_big
;
7639 imm_expr
.X_add_number
= 4;
7640 if (! target_big_endian
)
7642 generic_bignum
[0] = bfd_getl16 (temp
);
7643 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7644 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7645 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7649 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7650 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7651 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7652 generic_bignum
[3] = bfd_getb16 (temp
);
7658 const char *newname
;
7661 /* Switch to the right section. */
7663 subseg
= now_subseg
;
7666 default: /* unused default case avoids warnings. */
7668 newname
= RDATA_SECTION_NAME
;
7669 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7673 newname
= RDATA_SECTION_NAME
;
7676 assert (!USE_GLOBAL_POINTER_OPT
7677 || g_switch_value
>= 4);
7681 new_seg
= subseg_new (newname
, (subsegT
) 0);
7682 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7683 bfd_set_section_flags (stdoutput
, new_seg
,
7688 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7689 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7690 && strcmp (TARGET_OS
, "elf") != 0)
7691 record_alignment (new_seg
, 4);
7693 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7695 as_bad (_("Can't use floating point insn in this section"));
7697 /* Set the argument to the current address in the
7699 offset_expr
.X_op
= O_symbol
;
7700 offset_expr
.X_add_symbol
=
7701 symbol_new ("L0\001", now_seg
,
7702 (valueT
) frag_now_fix (), frag_now
);
7703 offset_expr
.X_add_number
= 0;
7705 /* Put the floating point number into the section. */
7706 p
= frag_more ((int) length
);
7707 memcpy (p
, temp
, length
);
7709 /* Switch back to the original section. */
7710 subseg_set (seg
, subseg
);
7715 case 'i': /* 16 bit unsigned immediate */
7716 case 'j': /* 16 bit signed immediate */
7717 imm_reloc
= BFD_RELOC_LO16
;
7718 c
= my_getSmallExpression (&imm_expr
, s
);
7723 if (imm_expr
.X_op
== O_constant
)
7724 imm_expr
.X_add_number
=
7725 (imm_expr
.X_add_number
>> 16) & 0xffff;
7728 imm_reloc
= BFD_RELOC_HI16_S
;
7729 imm_unmatched_hi
= true;
7732 imm_reloc
= BFD_RELOC_HI16
;
7734 else if (imm_expr
.X_op
== O_constant
)
7735 imm_expr
.X_add_number
&= 0xffff;
7739 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7740 || ((imm_expr
.X_add_number
< 0
7741 || imm_expr
.X_add_number
>= 0x10000)
7742 && imm_expr
.X_op
== O_constant
))
7744 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7745 !strcmp (insn
->name
, insn
[1].name
))
7747 if (imm_expr
.X_op
!= O_constant
7748 && imm_expr
.X_op
!= O_big
)
7749 insn_error
= _("absolute expression required");
7751 as_bad (_("16 bit expression not in range 0..65535"));
7759 /* The upper bound should be 0x8000, but
7760 unfortunately the MIPS assembler accepts numbers
7761 from 0x8000 to 0xffff and sign extends them, and
7762 we want to be compatible. We only permit this
7763 extended range for an instruction which does not
7764 provide any further alternates, since those
7765 alternates may handle other cases. People should
7766 use the numbers they mean, rather than relying on
7767 a mysterious sign extension. */
7768 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7769 strcmp (insn
->name
, insn
[1].name
) == 0);
7774 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7775 || ((imm_expr
.X_add_number
< -0x8000
7776 || imm_expr
.X_add_number
>= max
)
7777 && imm_expr
.X_op
== O_constant
)
7779 && imm_expr
.X_add_number
< 0
7780 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7781 && imm_expr
.X_unsigned
7782 && sizeof (imm_expr
.X_add_number
) <= 4))
7786 if (imm_expr
.X_op
!= O_constant
7787 && imm_expr
.X_op
!= O_big
)
7788 insn_error
= _("absolute expression required");
7790 as_bad (_("16 bit expression not in range -32768..32767"));
7796 case 'o': /* 16 bit offset */
7797 c
= my_getSmallExpression (&offset_expr
, s
);
7799 /* If this value won't fit into a 16 bit offset, then go
7800 find a macro that will generate the 32 bit offset
7801 code pattern. As a special hack, we accept the
7802 difference of two local symbols as a constant. This
7803 is required to suppose embedded PIC switches, which
7804 use an instruction which looks like
7805 lw $4,$L12-$LS12($4)
7806 The problem with handling this in a more general
7807 fashion is that the macro function doesn't expect to
7808 see anything which can be handled in a single
7809 constant instruction. */
7811 && (offset_expr
.X_op
!= O_constant
7812 || offset_expr
.X_add_number
>= 0x8000
7813 || offset_expr
.X_add_number
< -0x8000)
7814 && (mips_pic
!= EMBEDDED_PIC
7815 || offset_expr
.X_op
!= O_subtract
7816 || now_seg
!= text_section
7817 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7821 if (c
== 'h' || c
== 'H')
7823 if (offset_expr
.X_op
!= O_constant
)
7825 offset_expr
.X_add_number
=
7826 (offset_expr
.X_add_number
>> 16) & 0xffff;
7828 offset_reloc
= BFD_RELOC_LO16
;
7832 case 'p': /* pc relative offset */
7833 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7834 my_getExpression (&offset_expr
, s
);
7838 case 'u': /* upper 16 bits */
7839 c
= my_getSmallExpression (&imm_expr
, s
);
7840 imm_reloc
= BFD_RELOC_LO16
;
7845 if (imm_expr
.X_op
== O_constant
)
7846 imm_expr
.X_add_number
=
7847 (imm_expr
.X_add_number
>> 16) & 0xffff;
7850 imm_reloc
= BFD_RELOC_HI16_S
;
7851 imm_unmatched_hi
= true;
7854 imm_reloc
= BFD_RELOC_HI16
;
7856 else if (imm_expr
.X_op
== O_constant
)
7857 imm_expr
.X_add_number
&= 0xffff;
7859 if (imm_expr
.X_op
== O_constant
7860 && (imm_expr
.X_add_number
< 0
7861 || imm_expr
.X_add_number
>= 0x10000))
7862 as_bad (_("lui expression not in range 0..65535"));
7866 case 'a': /* 26 bit address */
7867 my_getExpression (&offset_expr
, s
);
7869 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7872 case 'N': /* 3 bit branch condition code */
7873 case 'M': /* 3 bit compare condition code */
7874 if (strncmp (s
, "$fcc", 4) != 0)
7884 while (isdigit ((unsigned char) *s
));
7886 as_bad (_("invalid condition code register $fcc%d"), regno
);
7888 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7890 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7894 as_bad (_("bad char = '%c'\n"), *args
);
7899 /* Args don't match. */
7900 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7901 !strcmp (insn
->name
, insn
[1].name
))
7907 insn_error
= _("illegal operands");
7912 /* This routine assembles an instruction into its binary format when
7913 assembling for the mips16. As a side effect, it sets one of the
7914 global variables imm_reloc or offset_reloc to the type of
7915 relocation to do if one of the operands is an address expression.
7916 It also sets mips16_small and mips16_ext if the user explicitly
7917 requested a small or extended instruction. */
7922 struct mips_cl_insn
*ip
;
7926 struct mips_opcode
*insn
;
7929 unsigned int lastregno
= 0;
7934 mips16_small
= false;
7937 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7949 if (s
[1] == 't' && s
[2] == ' ')
7952 mips16_small
= true;
7956 else if (s
[1] == 'e' && s
[2] == ' ')
7965 insn_error
= _("unknown opcode");
7969 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7970 mips16_small
= true;
7972 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7974 insn_error
= _("unrecognized opcode");
7981 assert (strcmp (insn
->name
, str
) == 0);
7984 ip
->insn_opcode
= insn
->match
;
7985 ip
->use_extend
= false;
7986 imm_expr
.X_op
= O_absent
;
7987 imm_reloc
= BFD_RELOC_UNUSED
;
7988 offset_expr
.X_op
= O_absent
;
7989 offset_reloc
= BFD_RELOC_UNUSED
;
7990 for (args
= insn
->args
; 1; ++args
)
7997 /* In this switch statement we call break if we did not find
7998 a match, continue if we did find a match, or return if we
8007 /* Stuff the immediate value in now, if we can. */
8008 if (imm_expr
.X_op
== O_constant
8009 && imm_reloc
> BFD_RELOC_UNUSED
8010 && insn
->pinfo
!= INSN_MACRO
)
8012 mips16_immed ((char *) NULL
, 0,
8013 imm_reloc
- BFD_RELOC_UNUSED
,
8014 imm_expr
.X_add_number
, true, mips16_small
,
8015 mips16_ext
, &ip
->insn_opcode
,
8016 &ip
->use_extend
, &ip
->extend
);
8017 imm_expr
.X_op
= O_absent
;
8018 imm_reloc
= BFD_RELOC_UNUSED
;
8032 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8035 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8051 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8053 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8070 if (isdigit ((unsigned char) s
[1]))
8080 while (isdigit ((unsigned char) *s
));
8083 as_bad (_("invalid register number (%d)"), regno
);
8089 if (s
[1] == 'f' && s
[2] == 'p')
8094 else if (s
[1] == 's' && s
[2] == 'p')
8099 else if (s
[1] == 'g' && s
[2] == 'p')
8104 else if (s
[1] == 'a' && s
[2] == 't')
8109 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8114 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8127 if (c
== 'v' || c
== 'w')
8129 regno
= mips16_to_32_reg_map
[lastregno
];
8143 regno
= mips32_to_16_reg_map
[regno
];
8148 regno
= ILLEGAL_REG
;
8153 regno
= ILLEGAL_REG
;
8158 regno
= ILLEGAL_REG
;
8163 if (regno
== AT
&& ! mips_opts
.noat
)
8164 as_warn (_("used $at without \".set noat\""));
8171 if (regno
== ILLEGAL_REG
)
8178 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8182 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8185 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8188 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8194 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8197 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8198 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8208 if (strncmp (s
, "$pc", 3) == 0)
8232 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8234 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8235 and generate the appropriate reloc. If the text
8236 inside %gprel is not a symbol name with an
8237 optional offset, then we generate a normal reloc
8238 and will probably fail later. */
8239 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8240 if (imm_expr
.X_op
== O_symbol
)
8243 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8245 ip
->use_extend
= true;
8252 /* Just pick up a normal expression. */
8253 my_getExpression (&imm_expr
, s
);
8256 if (imm_expr
.X_op
== O_register
)
8258 /* What we thought was an expression turned out to
8261 if (s
[0] == '(' && args
[1] == '(')
8263 /* It looks like the expression was omitted
8264 before a register indirection, which means
8265 that the expression is implicitly zero. We
8266 still set up imm_expr, so that we handle
8267 explicit extensions correctly. */
8268 imm_expr
.X_op
= O_constant
;
8269 imm_expr
.X_add_number
= 0;
8270 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8277 /* We need to relax this instruction. */
8278 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8287 /* We use offset_reloc rather than imm_reloc for the PC
8288 relative operands. This lets macros with both
8289 immediate and address operands work correctly. */
8290 my_getExpression (&offset_expr
, s
);
8292 if (offset_expr
.X_op
== O_register
)
8295 /* We need to relax this instruction. */
8296 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8300 case '6': /* break code */
8301 my_getExpression (&imm_expr
, s
);
8302 check_absolute_expr (ip
, &imm_expr
);
8303 if ((unsigned long) imm_expr
.X_add_number
> 63)
8305 as_warn (_("Invalid value for `%s' (%lu)"),
8307 (unsigned long) imm_expr
.X_add_number
);
8308 imm_expr
.X_add_number
&= 0x3f;
8310 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8311 imm_expr
.X_op
= O_absent
;
8315 case 'a': /* 26 bit address */
8316 my_getExpression (&offset_expr
, s
);
8318 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8319 ip
->insn_opcode
<<= 16;
8322 case 'l': /* register list for entry macro */
8323 case 'L': /* register list for exit macro */
8333 int freg
, reg1
, reg2
;
8335 while (*s
== ' ' || *s
== ',')
8339 as_bad (_("can't parse register list"));
8351 while (isdigit ((unsigned char) *s
))
8373 as_bad (_("invalid register list"));
8378 while (isdigit ((unsigned char) *s
))
8385 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8390 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8395 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8396 mask
|= (reg2
- 3) << 3;
8397 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8398 mask
|= (reg2
- 15) << 1;
8399 else if (reg1
== 31 && reg2
== 31)
8403 as_bad (_("invalid register list"));
8407 /* The mask is filled in in the opcode table for the
8408 benefit of the disassembler. We remove it before
8409 applying the actual mask. */
8410 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8411 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8415 case 'e': /* extend code */
8416 my_getExpression (&imm_expr
, s
);
8417 check_absolute_expr (ip
, &imm_expr
);
8418 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8420 as_warn (_("Invalid value for `%s' (%lu)"),
8422 (unsigned long) imm_expr
.X_add_number
);
8423 imm_expr
.X_add_number
&= 0x7ff;
8425 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8426 imm_expr
.X_op
= O_absent
;
8436 /* Args don't match. */
8437 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8438 strcmp (insn
->name
, insn
[1].name
) == 0)
8445 insn_error
= _("illegal operands");
8451 /* This structure holds information we know about a mips16 immediate
8454 struct mips16_immed_operand
8456 /* The type code used in the argument string in the opcode table. */
8458 /* The number of bits in the short form of the opcode. */
8460 /* The number of bits in the extended form of the opcode. */
8462 /* The amount by which the short form is shifted when it is used;
8463 for example, the sw instruction has a shift count of 2. */
8465 /* The amount by which the short form is shifted when it is stored
8466 into the instruction code. */
8468 /* Non-zero if the short form is unsigned. */
8470 /* Non-zero if the extended form is unsigned. */
8472 /* Non-zero if the value is PC relative. */
8476 /* The mips16 immediate operand types. */
8478 static const struct mips16_immed_operand mips16_immed_operands
[] =
8480 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8481 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8482 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8483 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8484 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8485 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8486 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8487 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8488 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8489 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8490 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8491 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8492 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8493 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8494 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8495 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8496 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8497 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8498 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8499 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8500 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8503 #define MIPS16_NUM_IMMED \
8504 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8506 /* Handle a mips16 instruction with an immediate value. This or's the
8507 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8508 whether an extended value is needed; if one is needed, it sets
8509 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8510 If SMALL is true, an unextended opcode was explicitly requested.
8511 If EXT is true, an extended opcode was explicitly requested. If
8512 WARN is true, warn if EXT does not match reality. */
8515 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8524 unsigned long *insn
;
8525 boolean
*use_extend
;
8526 unsigned short *extend
;
8528 register const struct mips16_immed_operand
*op
;
8529 int mintiny
, maxtiny
;
8532 op
= mips16_immed_operands
;
8533 while (op
->type
!= type
)
8536 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8541 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8544 maxtiny
= 1 << op
->nbits
;
8549 maxtiny
= (1 << op
->nbits
) - 1;
8554 mintiny
= - (1 << (op
->nbits
- 1));
8555 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8558 /* Branch offsets have an implicit 0 in the lowest bit. */
8559 if (type
== 'p' || type
== 'q')
8562 if ((val
& ((1 << op
->shift
) - 1)) != 0
8563 || val
< (mintiny
<< op
->shift
)
8564 || val
> (maxtiny
<< op
->shift
))
8569 if (warn
&& ext
&& ! needext
)
8570 as_warn_where (file
, line
, _("extended operand requested but not required"));
8571 if (small
&& needext
)
8572 as_bad_where (file
, line
, _("invalid unextended operand value"));
8574 if (small
|| (! ext
&& ! needext
))
8578 *use_extend
= false;
8579 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8580 insnval
<<= op
->op_shift
;
8585 long minext
, maxext
;
8591 maxext
= (1 << op
->extbits
) - 1;
8595 minext
= - (1 << (op
->extbits
- 1));
8596 maxext
= (1 << (op
->extbits
- 1)) - 1;
8598 if (val
< minext
|| val
> maxext
)
8599 as_bad_where (file
, line
,
8600 _("operand value out of range for instruction"));
8603 if (op
->extbits
== 16)
8605 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8608 else if (op
->extbits
== 15)
8610 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8615 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8619 *extend
= (unsigned short) extval
;
8628 my_getSmallExpression (ep
, str
)
8639 ((str
[1] == 'h' && str
[2] == 'i')
8640 || (str
[1] == 'H' && str
[2] == 'I')
8641 || (str
[1] == 'l' && str
[2] == 'o'))
8653 * A small expression may be followed by a base register.
8654 * Scan to the end of this operand, and then back over a possible
8655 * base register. Then scan the small expression up to that
8656 * point. (Based on code in sparc.c...)
8658 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8660 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8662 if (isdigit ((unsigned char) sp
[-2]))
8664 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8666 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8672 else if (sp
- 5 >= str
8675 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8676 || (sp
[-3] == 's' && sp
[-2] == 'p')
8677 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8678 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8684 /* no expression means zero offset */
8687 /* %xx(reg) is an error */
8688 ep
->X_op
= O_absent
;
8693 ep
->X_op
= O_constant
;
8696 ep
->X_add_symbol
= NULL
;
8697 ep
->X_op_symbol
= NULL
;
8698 ep
->X_add_number
= 0;
8703 my_getExpression (ep
, str
);
8710 my_getExpression (ep
, str
);
8711 return c
; /* => %hi or %lo encountered */
8715 my_getExpression (ep
, str
)
8721 save_in
= input_line_pointer
;
8722 input_line_pointer
= str
;
8724 expr_end
= input_line_pointer
;
8725 input_line_pointer
= save_in
;
8727 /* If we are in mips16 mode, and this is an expression based on `.',
8728 then we bump the value of the symbol by 1 since that is how other
8729 text symbols are handled. We don't bother to handle complex
8730 expressions, just `.' plus or minus a constant. */
8731 if (mips_opts
.mips16
8732 && ep
->X_op
== O_symbol
8733 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8734 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8735 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8736 && symbol_constant_p (ep
->X_add_symbol
)
8737 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8738 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8741 /* Turn a string in input_line_pointer into a floating point constant
8742 of type type, and store the appropriate bytes in *litP. The number
8743 of LITTLENUMS emitted is stored in *sizeP . An error message is
8744 returned, or NULL on OK. */
8747 md_atof (type
, litP
, sizeP
)
8753 LITTLENUM_TYPE words
[4];
8769 return _("bad call to md_atof");
8772 t
= atof_ieee (input_line_pointer
, type
, words
);
8774 input_line_pointer
= t
;
8778 if (! target_big_endian
)
8780 for (i
= prec
- 1; i
>= 0; i
--)
8782 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8788 for (i
= 0; i
< prec
; i
++)
8790 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8799 md_number_to_chars (buf
, val
, n
)
8804 if (target_big_endian
)
8805 number_to_chars_bigendian (buf
, val
, n
);
8807 number_to_chars_littleendian (buf
, val
, n
);
8810 CONST
char *md_shortopts
= "O::g::G:";
8812 struct option md_longopts
[] = {
8813 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8814 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8815 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8816 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8817 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8818 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8819 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8820 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8821 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8822 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8823 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8824 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8825 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8826 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8827 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8828 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8829 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8830 {"break", no_argument
, NULL
, OPTION_BREAK
},
8831 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8832 #define OPTION_EB (OPTION_MD_BASE + 11)
8833 {"EB", no_argument
, NULL
, OPTION_EB
},
8834 #define OPTION_EL (OPTION_MD_BASE + 12)
8835 {"EL", no_argument
, NULL
, OPTION_EL
},
8836 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8837 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8838 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8839 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8840 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8841 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8842 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8843 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8844 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8845 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8846 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8847 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8848 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8849 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8850 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8851 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8852 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8853 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8854 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8855 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8858 #define OPTION_MABI (OPTION_MD_BASE + 38)
8859 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8861 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8862 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8863 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8864 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8866 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8867 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8868 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8869 #define OPTION_32 (OPTION_MD_BASE + 20)
8870 #define OPTION_64 (OPTION_MD_BASE + 21)
8872 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8873 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8874 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8875 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8876 {"32", no_argument
, NULL
, OPTION_32
},
8877 {"64", no_argument
, NULL
, OPTION_64
},
8880 #define OPTION_GP32 (OPTION_MD_BASE + 41)
8881 #define OPTION_GP64 (OPTION_MD_BASE + 42)
8882 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8883 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8885 {NULL
, no_argument
, NULL
, 0}
8887 size_t md_longopts_size
= sizeof(md_longopts
);
8890 md_parse_option (c
, arg
)
8905 target_big_endian
= 1;
8909 target_big_endian
= 0;
8913 if (arg
&& arg
[1] == '0')
8923 mips_debug
= atoi (arg
);
8924 /* When the MIPS assembler sees -g or -g2, it does not do
8925 optimizations which limit full symbolic debugging. We take
8926 that to be equivalent to -O0. */
8927 if (mips_debug
== 2)
8951 /* Identify the processor type */
8953 if (strcmp (p
, "default") == 0
8954 || strcmp (p
, "DEFAULT") == 0)
8960 /* We need to cope with the various "vr" prefixes for the 4300
8962 if (*p
== 'v' || *p
== 'V')
8968 if (*p
== 'r' || *p
== 'R')
8975 if (strcmp (p
, "10000") == 0
8976 || strcmp (p
, "10k") == 0
8977 || strcmp (p
, "10K") == 0)
8982 if (strcmp (p
, "2000") == 0
8983 || strcmp (p
, "2k") == 0
8984 || strcmp (p
, "2K") == 0)
8989 if (strcmp (p
, "3000") == 0
8990 || strcmp (p
, "3k") == 0
8991 || strcmp (p
, "3K") == 0)
8993 else if (strcmp (p
, "3900") == 0)
8998 if (strcmp (p
, "4000") == 0
8999 || strcmp (p
, "4k") == 0
9000 || strcmp (p
, "4K") == 0)
9002 else if (strcmp (p
, "4100") == 0)
9004 else if (strcmp (p
, "4111") == 0)
9006 else if (strcmp (p
, "4300") == 0)
9008 else if (strcmp (p
, "4400") == 0)
9010 else if (strcmp (p
, "4600") == 0)
9012 else if (strcmp (p
, "4650") == 0)
9014 else if (strcmp (p
, "4010") == 0)
9019 if (strcmp (p
, "5000") == 0
9020 || strcmp (p
, "5k") == 0
9021 || strcmp (p
, "5K") == 0)
9026 if (strcmp (p
, "6000") == 0
9027 || strcmp (p
, "6k") == 0
9028 || strcmp (p
, "6K") == 0)
9033 if (strcmp (p
, "8000") == 0
9034 || strcmp (p
, "8k") == 0
9035 || strcmp (p
, "8K") == 0)
9040 if (strcmp (p
, "orion") == 0)
9046 && (mips_cpu
!= 4300
9049 && mips_cpu
!= 5000))
9051 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9057 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9068 case OPTION_NO_M4650
:
9075 case OPTION_NO_M4010
:
9082 case OPTION_NO_M4100
:
9090 case OPTION_NO_M3900
:
9094 mips_opts
.mips16
= 1;
9095 mips_no_prev_insn (false);
9098 case OPTION_NO_MIPS16
:
9099 mips_opts
.mips16
= 0;
9100 mips_no_prev_insn (false);
9103 case OPTION_MEMBEDDED_PIC
:
9104 mips_pic
= EMBEDDED_PIC
;
9105 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9107 as_bad (_("-G may not be used with embedded PIC code"));
9110 g_switch_value
= 0x7fffffff;
9113 /* When generating ELF code, we permit -KPIC and -call_shared to
9114 select SVR4_PIC, and -non_shared to select no PIC. This is
9115 intended to be compatible with Irix 5. */
9116 case OPTION_CALL_SHARED
:
9117 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9119 as_bad (_("-call_shared is supported only for ELF format"));
9122 mips_pic
= SVR4_PIC
;
9123 if (g_switch_seen
&& g_switch_value
!= 0)
9125 as_bad (_("-G may not be used with SVR4 PIC code"));
9131 case OPTION_NON_SHARED
:
9132 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9134 as_bad (_("-non_shared is supported only for ELF format"));
9140 /* The -xgot option tells the assembler to use 32 offsets when
9141 accessing the got in SVR4_PIC mode. It is for Irix
9148 if (! USE_GLOBAL_POINTER_OPT
)
9150 as_bad (_("-G is not supported for this configuration"));
9153 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9155 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9159 g_switch_value
= atoi (arg
);
9163 /* The -32 and -64 options tell the assembler to output the 32
9164 bit or the 64 bit MIPS ELF format. */
9171 const char **list
, **l
;
9173 list
= bfd_target_list ();
9174 for (l
= list
; *l
!= NULL
; l
++)
9175 if (strcmp (*l
, "elf64-bigmips") == 0
9176 || strcmp (*l
, "elf64-littlemips") == 0)
9179 as_fatal (_("No compiled in support for 64 bit object file format"));
9189 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9190 flag in object files because to do so would make it
9191 impossible to link with libraries compiled without "-gp32".
9192 This is unnecessarily restrictive.
9194 We could solve this problem by adding "-gp32" multilibs to
9195 gcc, but to set this flag before gcc is built with such
9196 multilibs will break too many systems. */
9198 /* mips_32bitmode = 1; */
9204 /* mips_32bitmode = 0; */
9208 if (strcmp (arg
,"32") == 0
9209 || strcmp (arg
,"n32") == 0
9210 || strcmp (arg
,"64") == 0
9211 || strcmp (arg
,"o64") == 0
9212 || strcmp (arg
,"eabi") == 0)
9213 mips_abi_string
= arg
;
9216 case OPTION_M7000_HILO_FIX
:
9217 mips_7000_hilo_fix
= true;
9220 case OPTION_NO_M7000_HILO_FIX
:
9221 mips_7000_hilo_fix
= false;
9233 show (stream
, string
, col_p
, first_p
)
9241 fprintf (stream
, "%24s", "");
9246 fprintf (stream
, ", ");
9250 if (*col_p
+ strlen (string
) > 72)
9252 fprintf (stream
, "\n%24s", "");
9256 fprintf (stream
, "%s", string
);
9257 *col_p
+= strlen (string
);
9264 md_show_usage (stream
)
9269 fprintf(stream
, _("\
9271 -membedded-pic generate embedded position independent code\n\
9272 -EB generate big endian output\n\
9273 -EL generate little endian output\n\
9274 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9275 -G NUM allow referencing objects up to NUM bytes\n\
9276 implicitly with the gp register [default 8]\n"));
9277 fprintf(stream
, _("\
9278 -mips1 generate MIPS ISA I instructions\n\
9279 -mips2 generate MIPS ISA II instructions\n\
9280 -mips3 generate MIPS ISA III instructions\n\
9281 -mips4 generate MIPS ISA IV instructions\n\
9282 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9286 show (stream
, "2000", &column
, &first
);
9287 show (stream
, "3000", &column
, &first
);
9288 show (stream
, "3900", &column
, &first
);
9289 show (stream
, "4000", &column
, &first
);
9290 show (stream
, "4010", &column
, &first
);
9291 show (stream
, "4100", &column
, &first
);
9292 show (stream
, "4111", &column
, &first
);
9293 show (stream
, "4300", &column
, &first
);
9294 show (stream
, "4400", &column
, &first
);
9295 show (stream
, "4600", &column
, &first
);
9296 show (stream
, "4650", &column
, &first
);
9297 show (stream
, "5000", &column
, &first
);
9298 show (stream
, "6000", &column
, &first
);
9299 show (stream
, "8000", &column
, &first
);
9300 show (stream
, "10000", &column
, &first
);
9301 fputc ('\n', stream
);
9303 fprintf (stream
, _("\
9304 -mCPU equivalent to -mcpu=CPU.\n\
9305 -no-mCPU don't generate code specific to CPU.\n\
9306 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9310 show (stream
, "3900", &column
, &first
);
9311 show (stream
, "4010", &column
, &first
);
9312 show (stream
, "4100", &column
, &first
);
9313 show (stream
, "4650", &column
, &first
);
9314 fputc ('\n', stream
);
9316 fprintf(stream
, _("\
9317 -mips16 generate mips16 instructions\n\
9318 -no-mips16 do not generate mips16 instructions\n"));
9319 fprintf(stream
, _("\
9320 -O0 remove unneeded NOPs, do not swap branches\n\
9321 -O remove unneeded NOPs and swap branches\n\
9322 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9323 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9325 fprintf(stream
, _("\
9326 -KPIC, -call_shared generate SVR4 position independent code\n\
9327 -non_shared do not generate position independent code\n\
9328 -xgot assume a 32 bit GOT\n\
9329 -32 create 32 bit object file (default)\n\
9330 -64 create 64 bit object file\n"));
9335 mips_init_after_args ()
9337 /* initialize opcodes */
9338 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9339 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9343 md_pcrel_from (fixP
)
9346 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9347 && fixP
->fx_addsy
!= (symbolS
*) NULL
9348 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9350 /* This makes a branch to an undefined symbol be a branch to the
9351 current location. */
9355 /* return the address of the delay slot */
9356 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9359 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9360 reloc for a cons. We could use the definition there, except that
9361 we want to handle 64 bit relocs specially. */
9364 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9367 unsigned int nbytes
;
9371 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9373 if (nbytes
== 8 && ! mips_64
)
9375 if (target_big_endian
)
9381 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9382 as_bad (_("Unsupported reloc size %d"), nbytes
);
9384 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9387 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9390 /* This is called before the symbol table is processed. In order to
9391 work with gcc when using mips-tfile, we must keep all local labels.
9392 However, in other cases, we want to discard them. If we were
9393 called with -g, but we didn't see any debugging information, it may
9394 mean that gcc is smuggling debugging information through to
9395 mips-tfile, in which case we must generate all local labels. */
9398 mips_frob_file_before_adjust ()
9400 #ifndef NO_ECOFF_DEBUGGING
9403 && ! ecoff_debugging_seen
)
9404 flag_keep_locals
= 1;
9408 /* Sort any unmatched HI16_S relocs so that they immediately precede
9409 the corresponding LO reloc. This is called before md_apply_fix and
9410 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9411 explicit use of the %hi modifier. */
9416 struct mips_hi_fixup
*l
;
9418 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9420 segment_info_type
*seginfo
;
9423 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9425 /* Check quickly whether the next fixup happens to be a matching
9427 if (l
->fixp
->fx_next
!= NULL
9428 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9429 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9430 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9433 /* Look through the fixups for this segment for a matching %lo.
9434 When we find one, move the %hi just in front of it. We do
9435 this in two passes. In the first pass, we try to find a
9436 unique %lo. In the second pass, we permit multiple %hi
9437 relocs for a single %lo (this is a GNU extension). */
9438 seginfo
= seg_info (l
->seg
);
9439 for (pass
= 0; pass
< 2; pass
++)
9444 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9446 /* Check whether this is a %lo fixup which matches l->fixp. */
9447 if (f
->fx_r_type
== BFD_RELOC_LO16
9448 && f
->fx_addsy
== l
->fixp
->fx_addsy
9449 && f
->fx_offset
== l
->fixp
->fx_offset
9452 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9453 || prev
->fx_addsy
!= f
->fx_addsy
9454 || prev
->fx_offset
!= f
->fx_offset
))
9458 /* Move l->fixp before f. */
9459 for (pf
= &seginfo
->fix_root
;
9461 pf
= &(*pf
)->fx_next
)
9462 assert (*pf
!= NULL
);
9464 *pf
= l
->fixp
->fx_next
;
9466 l
->fixp
->fx_next
= f
;
9468 seginfo
->fix_root
= l
->fixp
;
9470 prev
->fx_next
= l
->fixp
;
9481 #if 0 /* GCC code motion plus incomplete dead code elimination
9482 can leave a %hi without a %lo. */
9484 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9485 _("Unmatched %%hi reloc"));
9491 /* When generating embedded PIC code we need to use a special
9492 relocation to represent the difference of two symbols in the .text
9493 section (switch tables use a difference of this sort). See
9494 include/coff/mips.h for details. This macro checks whether this
9495 fixup requires the special reloc. */
9496 #define SWITCH_TABLE(fixp) \
9497 ((fixp)->fx_r_type == BFD_RELOC_32 \
9498 && (fixp)->fx_addsy != NULL \
9499 && (fixp)->fx_subsy != NULL \
9500 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9501 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9503 /* When generating embedded PIC code we must keep all PC relative
9504 relocations, in case the linker has to relax a call. We also need
9505 to keep relocations for switch table entries. */
9509 mips_force_relocation (fixp
)
9512 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9513 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9516 return (mips_pic
== EMBEDDED_PIC
9518 || SWITCH_TABLE (fixp
)
9519 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9520 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9523 /* Apply a fixup to the object file. */
9526 md_apply_fix (fixP
, valueP
)
9533 assert (fixP
->fx_size
== 4
9534 || fixP
->fx_r_type
== BFD_RELOC_16
9535 || fixP
->fx_r_type
== BFD_RELOC_64
9536 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9537 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9541 /* If we aren't adjusting this fixup to be against the section
9542 symbol, we need to adjust the value. */
9544 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9545 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9546 || S_IS_WEAK (fixP
->fx_addsy
)
9547 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9548 && (((bfd_get_section_flags (stdoutput
,
9549 S_GET_SEGMENT (fixP
->fx_addsy
))
9550 & SEC_LINK_ONCE
) != 0)
9551 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9553 sizeof (".gnu.linkonce") - 1))))
9556 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9557 if (value
!= 0 && ! fixP
->fx_pcrel
)
9559 /* In this case, the bfd_install_relocation routine will
9560 incorrectly add the symbol value back in. We just want
9561 the addend to appear in the object file. */
9562 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9568 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9570 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9573 switch (fixP
->fx_r_type
)
9575 case BFD_RELOC_MIPS_JMP
:
9576 case BFD_RELOC_HI16
:
9577 case BFD_RELOC_HI16_S
:
9578 case BFD_RELOC_MIPS_GPREL
:
9579 case BFD_RELOC_MIPS_LITERAL
:
9580 case BFD_RELOC_MIPS_CALL16
:
9581 case BFD_RELOC_MIPS_GOT16
:
9582 case BFD_RELOC_MIPS_GPREL32
:
9583 case BFD_RELOC_MIPS_GOT_HI16
:
9584 case BFD_RELOC_MIPS_GOT_LO16
:
9585 case BFD_RELOC_MIPS_CALL_HI16
:
9586 case BFD_RELOC_MIPS_CALL_LO16
:
9587 case BFD_RELOC_MIPS16_GPREL
:
9589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9590 _("Invalid PC relative reloc"));
9591 /* Nothing needed to do. The value comes from the reloc entry */
9594 case BFD_RELOC_MIPS16_JMP
:
9595 /* We currently always generate a reloc against a symbol, which
9596 means that we don't want an addend even if the symbol is
9598 fixP
->fx_addnumber
= 0;
9601 case BFD_RELOC_PCREL_HI16_S
:
9602 /* The addend for this is tricky if it is internal, so we just
9603 do everything here rather than in bfd_install_relocation. */
9604 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9606 /* For an external symbol adjust by the address to make it
9607 pcrel_offset. We use the address of the RELLO reloc
9608 which follows this one. */
9609 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9610 + fixP
->fx_next
->fx_where
);
9615 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9616 if (target_big_endian
)
9618 md_number_to_chars (buf
, value
, 2);
9621 case BFD_RELOC_PCREL_LO16
:
9622 /* The addend for this is tricky if it is internal, so we just
9623 do everything here rather than in bfd_install_relocation. */
9624 if ((symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9625 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9626 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9627 if (target_big_endian
)
9629 md_number_to_chars (buf
, value
, 2);
9633 /* This is handled like BFD_RELOC_32, but we output a sign
9634 extended value if we are only 32 bits. */
9636 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9638 if (8 <= sizeof (valueT
))
9639 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9646 w1
= w2
= fixP
->fx_where
;
9647 if (target_big_endian
)
9651 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9652 if ((value
& 0x80000000) != 0)
9656 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9663 /* If we are deleting this reloc entry, we must fill in the
9664 value now. This can happen if we have a .word which is not
9665 resolved when it appears but is later defined. We also need
9666 to fill in the value if this is an embedded PIC switch table
9669 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9670 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9675 /* If we are deleting this reloc entry, we must fill in the
9677 assert (fixP
->fx_size
== 2);
9679 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9683 case BFD_RELOC_LO16
:
9684 /* When handling an embedded PIC switch statement, we can wind
9685 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9688 if (value
< -0x8000 || value
> 0x7fff)
9689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9690 _("relocation overflow"));
9691 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9692 if (target_big_endian
)
9694 md_number_to_chars (buf
, value
, 2);
9698 case BFD_RELOC_16_PCREL_S2
:
9700 * We need to save the bits in the instruction since fixup_segment()
9701 * might be deleting the relocation entry (i.e., a branch within
9702 * the current segment).
9704 if ((value
& 0x3) != 0)
9705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9706 _("Branch to odd address (%lx)"), value
);
9709 /* update old instruction data */
9710 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9711 if (target_big_endian
)
9712 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9714 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9716 if (value
>= -0x8000 && value
< 0x8000)
9717 insn
|= value
& 0xffff;
9720 /* The branch offset is too large. If this is an
9721 unconditional branch, and we are not generating PIC code,
9722 we can convert it to an absolute jump instruction. */
9723 if (mips_pic
== NO_PIC
9725 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9726 && (fixP
->fx_frag
->fr_address
9727 < text_section
->vma
+ text_section
->_raw_size
)
9728 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9729 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9730 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9732 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9733 insn
= 0x0c000000; /* jal */
9735 insn
= 0x08000000; /* j */
9736 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9738 fixP
->fx_addsy
= section_symbol (text_section
);
9739 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9743 /* FIXME. It would be possible in principle to handle
9744 conditional branches which overflow. They could be
9745 transformed into a branch around a jump. This would
9746 require setting up variant frags for each different
9747 branch type. The native MIPS assembler attempts to
9748 handle these cases, but it appears to do it
9750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9751 _("Branch out of range"));
9755 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9758 case BFD_RELOC_VTABLE_INHERIT
:
9761 && !S_IS_DEFINED (fixP
->fx_addsy
)
9762 && !S_IS_WEAK (fixP
->fx_addsy
))
9763 S_SET_WEAK (fixP
->fx_addsy
);
9766 case BFD_RELOC_VTABLE_ENTRY
:
9782 const struct mips_opcode
*p
;
9783 int treg
, sreg
, dreg
, shamt
;
9788 for (i
= 0; i
< NUMOPCODES
; ++i
)
9790 p
= &mips_opcodes
[i
];
9791 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9793 printf ("%08lx %s\t", oc
, p
->name
);
9794 treg
= (oc
>> 16) & 0x1f;
9795 sreg
= (oc
>> 21) & 0x1f;
9796 dreg
= (oc
>> 11) & 0x1f;
9797 shamt
= (oc
>> 6) & 0x1f;
9799 for (args
= p
->args
;; ++args
)
9810 printf ("%c", *args
);
9814 assert (treg
== sreg
);
9815 printf ("$%d,$%d", treg
, sreg
);
9820 printf ("$%d", dreg
);
9825 printf ("$%d", treg
);
9829 printf ("0x%x", treg
);
9834 printf ("$%d", sreg
);
9838 printf ("0x%08lx", oc
& 0x1ffffff);
9850 printf ("$%d", shamt
);
9861 printf (_("%08lx UNDEFINED\n"), oc
);
9872 name
= input_line_pointer
;
9873 c
= get_symbol_end ();
9874 p
= (symbolS
*) symbol_find_or_make (name
);
9875 *input_line_pointer
= c
;
9879 /* Align the current frag to a given power of two. The MIPS assembler
9880 also automatically adjusts any preceding label. */
9883 mips_align (to
, fill
, label
)
9888 mips_emit_delays (false);
9889 frag_align (to
, fill
, 0);
9890 record_alignment (now_seg
, to
);
9893 assert (S_GET_SEGMENT (label
) == now_seg
);
9894 symbol_set_frag (label
, frag_now
);
9895 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9899 /* Align to a given power of two. .align 0 turns off the automatic
9900 alignment used by the data creating pseudo-ops. */
9907 register long temp_fill
;
9908 long max_alignment
= 15;
9912 o Note that the assembler pulls down any immediately preceeding label
9913 to the aligned address.
9914 o It's not documented but auto alignment is reinstated by
9915 a .align pseudo instruction.
9916 o Note also that after auto alignment is turned off the mips assembler
9917 issues an error on attempt to assemble an improperly aligned data item.
9922 temp
= get_absolute_expression ();
9923 if (temp
> max_alignment
)
9924 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9927 as_warn (_("Alignment negative: 0 assumed."));
9930 if (*input_line_pointer
== ',')
9932 input_line_pointer
++;
9933 temp_fill
= get_absolute_expression ();
9940 mips_align (temp
, (int) temp_fill
,
9941 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9948 demand_empty_rest_of_line ();
9952 mips_flush_pending_output ()
9954 mips_emit_delays (false);
9955 mips_clear_insn_labels ();
9964 /* When generating embedded PIC code, we only use the .text, .lit8,
9965 .sdata and .sbss sections. We change the .data and .rdata
9966 pseudo-ops to use .sdata. */
9967 if (mips_pic
== EMBEDDED_PIC
9968 && (sec
== 'd' || sec
== 'r'))
9972 /* The ELF backend needs to know that we are changing sections, so
9973 that .previous works correctly. We could do something like check
9974 for a obj_section_change_hook macro, but that might be confusing
9975 as it would not be appropriate to use it in the section changing
9976 functions in read.c, since obj-elf.c intercepts those. FIXME:
9977 This should be cleaner, somehow. */
9978 obj_elf_section_change_hook ();
9981 mips_emit_delays (false);
9991 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9992 demand_empty_rest_of_line ();
9996 if (USE_GLOBAL_POINTER_OPT
)
9998 seg
= subseg_new (RDATA_SECTION_NAME
,
9999 (subsegT
) get_absolute_expression ());
10000 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10002 bfd_set_section_flags (stdoutput
, seg
,
10008 if (strcmp (TARGET_OS
, "elf") != 0)
10009 bfd_set_section_alignment (stdoutput
, seg
, 4);
10011 demand_empty_rest_of_line ();
10015 as_bad (_("No read only data section in this object file format"));
10016 demand_empty_rest_of_line ();
10022 if (USE_GLOBAL_POINTER_OPT
)
10024 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10025 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10027 bfd_set_section_flags (stdoutput
, seg
,
10028 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10030 if (strcmp (TARGET_OS
, "elf") != 0)
10031 bfd_set_section_alignment (stdoutput
, seg
, 4);
10033 demand_empty_rest_of_line ();
10038 as_bad (_("Global pointers not supported; recompile -G 0"));
10039 demand_empty_rest_of_line ();
10048 mips_enable_auto_align ()
10059 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10060 mips_emit_delays (false);
10061 if (log_size
> 0 && auto_align
)
10062 mips_align (log_size
, 0, label
);
10063 mips_clear_insn_labels ();
10064 cons (1 << log_size
);
10068 s_float_cons (type
)
10073 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10075 mips_emit_delays (false);
10080 mips_align (3, 0, label
);
10082 mips_align (2, 0, label
);
10085 mips_clear_insn_labels ();
10090 /* Handle .globl. We need to override it because on Irix 5 you are
10093 where foo is an undefined symbol, to mean that foo should be
10094 considered to be the address of a function. */
10105 name
= input_line_pointer
;
10106 c
= get_symbol_end ();
10107 symbolP
= symbol_find_or_make (name
);
10108 *input_line_pointer
= c
;
10109 SKIP_WHITESPACE ();
10111 /* On Irix 5, every global symbol that is not explicitly labelled as
10112 being a function is apparently labelled as being an object. */
10115 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10120 secname
= input_line_pointer
;
10121 c
= get_symbol_end ();
10122 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10124 as_bad (_("%s: no such section"), secname
);
10125 *input_line_pointer
= c
;
10127 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10128 flag
= BSF_FUNCTION
;
10131 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10133 S_SET_EXTERNAL (symbolP
);
10134 demand_empty_rest_of_line ();
10144 opt
= input_line_pointer
;
10145 c
= get_symbol_end ();
10149 /* FIXME: What does this mean? */
10151 else if (strncmp (opt
, "pic", 3) == 0)
10155 i
= atoi (opt
+ 3);
10159 mips_pic
= SVR4_PIC
;
10161 as_bad (_(".option pic%d not supported"), i
);
10163 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10165 if (g_switch_seen
&& g_switch_value
!= 0)
10166 as_warn (_("-G may not be used with SVR4 PIC code"));
10167 g_switch_value
= 0;
10168 bfd_set_gp_size (stdoutput
, 0);
10172 as_warn (_("Unrecognized option \"%s\""), opt
);
10174 *input_line_pointer
= c
;
10175 demand_empty_rest_of_line ();
10178 /* This structure is used to hold a stack of .set values. */
10180 struct mips_option_stack
10182 struct mips_option_stack
*next
;
10183 struct mips_set_options options
;
10186 static struct mips_option_stack
*mips_opts_stack
;
10188 /* Handle the .set pseudo-op. */
10194 char *name
= input_line_pointer
, ch
;
10196 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10197 input_line_pointer
++;
10198 ch
= *input_line_pointer
;
10199 *input_line_pointer
= '\0';
10201 if (strcmp (name
, "reorder") == 0)
10203 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10205 /* If we still have pending nops, we can discard them. The
10206 usual nop handling will insert any that are still
10208 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10209 * (mips_opts
.mips16
? 2 : 4));
10210 prev_nop_frag
= NULL
;
10212 mips_opts
.noreorder
= 0;
10214 else if (strcmp (name
, "noreorder") == 0)
10216 mips_emit_delays (true);
10217 mips_opts
.noreorder
= 1;
10218 mips_any_noreorder
= 1;
10220 else if (strcmp (name
, "at") == 0)
10222 mips_opts
.noat
= 0;
10224 else if (strcmp (name
, "noat") == 0)
10226 mips_opts
.noat
= 1;
10228 else if (strcmp (name
, "macro") == 0)
10230 mips_opts
.warn_about_macros
= 0;
10232 else if (strcmp (name
, "nomacro") == 0)
10234 if (mips_opts
.noreorder
== 0)
10235 as_bad (_("`noreorder' must be set before `nomacro'"));
10236 mips_opts
.warn_about_macros
= 1;
10238 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10240 mips_opts
.nomove
= 0;
10242 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10244 mips_opts
.nomove
= 1;
10246 else if (strcmp (name
, "bopt") == 0)
10248 mips_opts
.nobopt
= 0;
10250 else if (strcmp (name
, "nobopt") == 0)
10252 mips_opts
.nobopt
= 1;
10254 else if (strcmp (name
, "mips16") == 0
10255 || strcmp (name
, "MIPS-16") == 0)
10256 mips_opts
.mips16
= 1;
10257 else if (strcmp (name
, "nomips16") == 0
10258 || strcmp (name
, "noMIPS-16") == 0)
10259 mips_opts
.mips16
= 0;
10260 else if (strncmp (name
, "mips", 4) == 0)
10264 /* Permit the user to change the ISA on the fly. Needless to
10265 say, misuse can cause serious problems. */
10266 isa
= atoi (name
+ 4);
10268 mips_opts
.isa
= file_mips_isa
;
10269 else if (isa
< 1 || isa
> 4)
10270 as_bad (_("unknown ISA level"));
10272 mips_opts
.isa
= isa
;
10274 else if (strcmp (name
, "autoextend") == 0)
10275 mips_opts
.noautoextend
= 0;
10276 else if (strcmp (name
, "noautoextend") == 0)
10277 mips_opts
.noautoextend
= 1;
10278 else if (strcmp (name
, "push") == 0)
10280 struct mips_option_stack
*s
;
10282 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10283 s
->next
= mips_opts_stack
;
10284 s
->options
= mips_opts
;
10285 mips_opts_stack
= s
;
10287 else if (strcmp (name
, "pop") == 0)
10289 struct mips_option_stack
*s
;
10291 s
= mips_opts_stack
;
10293 as_bad (_(".set pop with no .set push"));
10296 /* If we're changing the reorder mode we need to handle
10297 delay slots correctly. */
10298 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10299 mips_emit_delays (true);
10300 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10302 if (prev_nop_frag
!= NULL
)
10304 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10305 * (mips_opts
.mips16
? 2 : 4));
10306 prev_nop_frag
= NULL
;
10310 mips_opts
= s
->options
;
10311 mips_opts_stack
= s
->next
;
10317 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10319 *input_line_pointer
= ch
;
10320 demand_empty_rest_of_line ();
10323 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10324 .option pic2. It means to generate SVR4 PIC calls. */
10327 s_abicalls (ignore
)
10330 mips_pic
= SVR4_PIC
;
10331 if (USE_GLOBAL_POINTER_OPT
)
10333 if (g_switch_seen
&& g_switch_value
!= 0)
10334 as_warn (_("-G may not be used with SVR4 PIC code"));
10335 g_switch_value
= 0;
10337 bfd_set_gp_size (stdoutput
, 0);
10338 demand_empty_rest_of_line ();
10341 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10342 PIC code. It sets the $gp register for the function based on the
10343 function address, which is in the register named in the argument.
10344 This uses a relocation against _gp_disp, which is handled specially
10345 by the linker. The result is:
10346 lui $gp,%hi(_gp_disp)
10347 addiu $gp,$gp,%lo(_gp_disp)
10348 addu $gp,$gp,.cpload argument
10349 The .cpload argument is normally $25 == $t9. */
10358 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10359 if (mips_pic
!= SVR4_PIC
)
10365 /* .cpload should be a in .set noreorder section. */
10366 if (mips_opts
.noreorder
== 0)
10367 as_warn (_(".cpload not in noreorder section"));
10369 ex
.X_op
= O_symbol
;
10370 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10371 ex
.X_op_symbol
= NULL
;
10372 ex
.X_add_number
= 0;
10374 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10375 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10377 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10378 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10379 (int) BFD_RELOC_LO16
);
10381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10382 GP
, GP
, tc_get_register (0));
10384 demand_empty_rest_of_line ();
10387 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10388 offset from $sp. The offset is remembered, and after making a PIC
10389 call $gp is restored from that location. */
10392 s_cprestore (ignore
)
10398 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10399 if (mips_pic
!= SVR4_PIC
)
10405 mips_cprestore_offset
= get_absolute_expression ();
10407 ex
.X_op
= O_constant
;
10408 ex
.X_add_symbol
= NULL
;
10409 ex
.X_op_symbol
= NULL
;
10410 ex
.X_add_number
= mips_cprestore_offset
;
10412 macro_build ((char *) NULL
, &icnt
, &ex
,
10413 ((bfd_arch_bits_per_address (stdoutput
) == 32
10414 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10416 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10418 demand_empty_rest_of_line ();
10421 /* Handle the .gpword pseudo-op. This is used when generating PIC
10422 code. It generates a 32 bit GP relative reloc. */
10432 /* When not generating PIC code, this is treated as .word. */
10433 if (mips_pic
!= SVR4_PIC
)
10439 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10440 mips_emit_delays (true);
10442 mips_align (2, 0, label
);
10443 mips_clear_insn_labels ();
10447 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10449 as_bad (_("Unsupported use of .gpword"));
10450 ignore_rest_of_line ();
10454 md_number_to_chars (p
, (valueT
) 0, 4);
10455 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10456 BFD_RELOC_MIPS_GPREL32
);
10458 demand_empty_rest_of_line ();
10461 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10462 tables in SVR4 PIC code. */
10471 /* This is ignored when not generating SVR4 PIC code. */
10472 if (mips_pic
!= SVR4_PIC
)
10478 /* Add $gp to the register named as an argument. */
10479 reg
= tc_get_register (0);
10480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10481 ((bfd_arch_bits_per_address (stdoutput
) == 32
10482 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10483 ? "addu" : "daddu"),
10484 "d,v,t", reg
, reg
, GP
);
10486 demand_empty_rest_of_line ();
10489 /* Handle the .insn pseudo-op. This marks instruction labels in
10490 mips16 mode. This permits the linker to handle them specially,
10491 such as generating jalx instructions when needed. We also make
10492 them odd for the duration of the assembly, in order to generate the
10493 right sort of code. We will make them even in the adjust_symtab
10494 routine, while leaving them marked. This is convenient for the
10495 debugger and the disassembler. The linker knows to make them odd
10502 if (mips_opts
.mips16
)
10503 mips16_mark_labels ();
10505 demand_empty_rest_of_line ();
10508 /* Handle a .stabn directive. We need these in order to mark a label
10509 as being a mips16 text label correctly. Sometimes the compiler
10510 will emit a label, followed by a .stabn, and then switch sections.
10511 If the label and .stabn are in mips16 mode, then the label is
10512 really a mips16 text label. */
10518 if (type
== 'n' && mips_opts
.mips16
)
10519 mips16_mark_labels ();
10524 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10528 s_mips_weakext (ignore
)
10536 name
= input_line_pointer
;
10537 c
= get_symbol_end ();
10538 symbolP
= symbol_find_or_make (name
);
10539 S_SET_WEAK (symbolP
);
10540 *input_line_pointer
= c
;
10542 SKIP_WHITESPACE ();
10544 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10546 if (S_IS_DEFINED (symbolP
))
10548 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10549 S_GET_NAME (symbolP
));
10550 ignore_rest_of_line ();
10554 if (*input_line_pointer
== ',')
10556 ++input_line_pointer
;
10557 SKIP_WHITESPACE ();
10561 if (exp
.X_op
!= O_symbol
)
10563 as_bad ("bad .weakext directive");
10564 ignore_rest_of_line();
10567 symbol_set_value_expression (symbolP
, &exp
);
10570 demand_empty_rest_of_line ();
10573 /* Parse a register string into a number. Called from the ECOFF code
10574 to parse .frame. The argument is non-zero if this is the frame
10575 register, so that we can record it in mips_frame_reg. */
10578 tc_get_register (frame
)
10583 SKIP_WHITESPACE ();
10584 if (*input_line_pointer
++ != '$')
10586 as_warn (_("expected `$'"));
10589 else if (isdigit ((unsigned char) *input_line_pointer
))
10591 reg
= get_absolute_expression ();
10592 if (reg
< 0 || reg
>= 32)
10594 as_warn (_("Bad register number"));
10600 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10602 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10604 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10606 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10610 as_warn (_("Unrecognized register name"));
10613 input_line_pointer
+= 2;
10616 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10621 md_section_align (seg
, addr
)
10625 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10628 /* We don't need to align ELF sections to the full alignment.
10629 However, Irix 5 may prefer that we align them at least to a 16
10630 byte boundary. We don't bother to align the sections if we are
10631 targeted for an embedded system. */
10632 if (strcmp (TARGET_OS
, "elf") == 0)
10638 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10641 /* Utility routine, called from above as well. If called while the
10642 input file is still being read, it's only an approximation. (For
10643 example, a symbol may later become defined which appeared to be
10644 undefined earlier.) */
10647 nopic_need_relax (sym
, before_relaxing
)
10649 int before_relaxing
;
10654 if (USE_GLOBAL_POINTER_OPT
)
10656 const char *symname
;
10659 /* Find out whether this symbol can be referenced off the GP
10660 register. It can be if it is smaller than the -G size or if
10661 it is in the .sdata or .sbss section. Certain symbols can
10662 not be referenced off the GP, although it appears as though
10664 symname
= S_GET_NAME (sym
);
10665 if (symname
!= (const char *) NULL
10666 && (strcmp (symname
, "eprol") == 0
10667 || strcmp (symname
, "etext") == 0
10668 || strcmp (symname
, "_gp") == 0
10669 || strcmp (symname
, "edata") == 0
10670 || strcmp (symname
, "_fbss") == 0
10671 || strcmp (symname
, "_fdata") == 0
10672 || strcmp (symname
, "_ftext") == 0
10673 || strcmp (symname
, "end") == 0
10674 || strcmp (symname
, "_gp_disp") == 0))
10676 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10678 #ifndef NO_ECOFF_DEBUGGING
10679 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10680 && (symbol_get_obj (sym
)->ecoff_extern_size
10681 <= g_switch_value
))
10683 /* We must defer this decision until after the whole
10684 file has been read, since there might be a .extern
10685 after the first use of this symbol. */
10686 || (before_relaxing
10687 #ifndef NO_ECOFF_DEBUGGING
10688 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10690 && S_GET_VALUE (sym
) == 0)
10691 || (S_GET_VALUE (sym
) != 0
10692 && S_GET_VALUE (sym
) <= g_switch_value
)))
10696 const char *segname
;
10698 segname
= segment_name (S_GET_SEGMENT (sym
));
10699 assert (strcmp (segname
, ".lit8") != 0
10700 && strcmp (segname
, ".lit4") != 0);
10701 change
= (strcmp (segname
, ".sdata") != 0
10702 && strcmp (segname
, ".sbss") != 0
10703 && strncmp (segname
, ".sdata.", 7) != 0
10704 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10709 /* We are not optimizing for the GP register. */
10713 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10714 extended opcode. SEC is the section the frag is in. */
10717 mips16_extended_frag (fragp
, sec
, stretch
)
10723 register const struct mips16_immed_operand
*op
;
10725 int mintiny
, maxtiny
;
10728 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10730 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10733 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10734 op
= mips16_immed_operands
;
10735 while (op
->type
!= type
)
10738 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10743 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10746 maxtiny
= 1 << op
->nbits
;
10751 maxtiny
= (1 << op
->nbits
) - 1;
10756 mintiny
= - (1 << (op
->nbits
- 1));
10757 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10760 /* We can't always call S_GET_VALUE here, because we don't want to
10761 lock in a particular frag address. */
10762 if (symbol_constant_p (fragp
->fr_symbol
))
10764 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10765 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10766 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10768 else if (symbol_equated_p (fragp
->fr_symbol
)
10769 && (symbol_constant_p
10770 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10774 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10775 val
= (S_GET_VALUE (eqsym
)
10776 + symbol_get_frag (eqsym
)->fr_address
10777 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10778 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10779 symsec
= S_GET_SEGMENT (eqsym
);
10788 /* We won't have the section when we are called from
10789 mips_relax_frag. However, we will always have been called
10790 from md_estimate_size_before_relax first. If this is a
10791 branch to a different section, we mark it as such. If SEC is
10792 NULL, and the frag is not marked, then it must be a branch to
10793 the same section. */
10796 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10803 fragp
->fr_subtype
=
10804 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10806 /* FIXME: We should support this, and let the linker
10807 catch branches and loads that are out of range. */
10808 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10809 _("unsupported PC relative reference to different section"));
10815 /* In this case, we know for sure that the symbol fragment is in
10816 the same section. If the fr_address of the symbol fragment
10817 is greater then the address of this fragment we want to add
10818 in STRETCH in order to get a better estimate of the address.
10819 This particularly matters because of the shift bits. */
10821 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10822 >= fragp
->fr_address
))
10826 /* Adjust stretch for any alignment frag. Note that if have
10827 been expanding the earlier code, the symbol may be
10828 defined in what appears to be an earlier frag. FIXME:
10829 This doesn't handle the fr_subtype field, which specifies
10830 a maximum number of bytes to skip when doing an
10833 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10836 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10839 stretch
= - ((- stretch
)
10840 & ~ ((1 << (int) f
->fr_offset
) - 1));
10842 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10851 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10853 /* The base address rules are complicated. The base address of
10854 a branch is the following instruction. The base address of a
10855 PC relative load or add is the instruction itself, but if it
10856 is in a delay slot (in which case it can not be extended) use
10857 the address of the instruction whose delay slot it is in. */
10858 if (type
== 'p' || type
== 'q')
10862 /* If we are currently assuming that this frag should be
10863 extended, then, the current address is two bytes
10865 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10868 /* Ignore the low bit in the target, since it will be set
10869 for a text label. */
10870 if ((val
& 1) != 0)
10873 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10875 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10878 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10880 /* Branch offsets have an implicit 0 in the lowest bit. */
10881 if (type
== 'p' || type
== 'q')
10884 /* If any of the shifted bits are set, we must use an extended
10885 opcode. If the address depends on the size of this
10886 instruction, this can lead to a loop, so we arrange to always
10887 use an extended opcode. We only check this when we are in
10888 the main relaxation loop, when SEC is NULL. */
10889 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10891 fragp
->fr_subtype
=
10892 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10896 /* If we are about to mark a frag as extended because the value
10897 is precisely maxtiny + 1, then there is a chance of an
10898 infinite loop as in the following code:
10903 In this case when the la is extended, foo is 0x3fc bytes
10904 away, so the la can be shrunk, but then foo is 0x400 away, so
10905 the la must be extended. To avoid this loop, we mark the
10906 frag as extended if it was small, and is about to become
10907 extended with a value of maxtiny + 1. */
10908 if (val
== ((maxtiny
+ 1) << op
->shift
)
10909 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10912 fragp
->fr_subtype
=
10913 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10917 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10918 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10920 if ((val
& ((1 << op
->shift
) - 1)) != 0
10921 || val
< (mintiny
<< op
->shift
)
10922 || val
> (maxtiny
<< op
->shift
))
10928 /* Estimate the size of a frag before relaxing. Unless this is the
10929 mips16, we are not really relaxing here, and the final size is
10930 encoded in the subtype information. For the mips16, we have to
10931 decide whether we are using an extended opcode or not. */
10935 md_estimate_size_before_relax (fragp
, segtype
)
10941 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10943 if (mips16_extended_frag (fragp
, segtype
, 0))
10945 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10950 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10955 if (mips_pic
== NO_PIC
)
10957 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10959 else if (mips_pic
== SVR4_PIC
)
10964 sym
= fragp
->fr_symbol
;
10966 /* Handle the case of a symbol equated to another symbol. */
10967 while (symbol_equated_p (sym
)
10968 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10972 /* It's possible to get a loop here in a badly written
10974 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10980 symsec
= S_GET_SEGMENT (sym
);
10982 /* This must duplicate the test in adjust_reloc_syms. */
10983 change
= (symsec
!= &bfd_und_section
10984 && symsec
!= &bfd_abs_section
10985 && ! bfd_is_com_section (symsec
));
10992 /* Record the offset to the first reloc in the fr_opcode field.
10993 This lets md_convert_frag and tc_gen_reloc know that the code
10994 must be expanded. */
10995 fragp
->fr_opcode
= (fragp
->fr_literal
10997 - RELAX_OLD (fragp
->fr_subtype
)
10998 + RELAX_RELOC1 (fragp
->fr_subtype
));
10999 /* FIXME: This really needs as_warn_where. */
11000 if (RELAX_WARN (fragp
->fr_subtype
))
11001 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11007 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11010 /* This is called to see whether a reloc against a defined symbol
11011 should be converted into a reloc against a section. Don't adjust
11012 MIPS16 jump relocations, so we don't have to worry about the format
11013 of the offset in the .o file. Don't adjust relocations against
11014 mips16 symbols, so that the linker can find them if it needs to set
11018 mips_fix_adjustable (fixp
)
11021 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11023 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11024 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11026 if (fixp
->fx_addsy
== NULL
)
11029 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11030 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11031 && fixp
->fx_subsy
== NULL
)
11037 /* Translate internal representation of relocation info to BFD target
11041 tc_gen_reloc (section
, fixp
)
11045 static arelent
*retval
[4];
11047 bfd_reloc_code_real_type code
;
11049 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11052 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11053 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11054 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11056 if (mips_pic
== EMBEDDED_PIC
11057 && SWITCH_TABLE (fixp
))
11059 /* For a switch table entry we use a special reloc. The addend
11060 is actually the difference between the reloc address and the
11062 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11063 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11064 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11065 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11067 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11069 /* We use a special addend for an internal RELLO reloc. */
11070 if (symbol_section_p (fixp
->fx_addsy
))
11071 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11073 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11075 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11077 assert (fixp
->fx_next
!= NULL
11078 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11079 /* We use a special addend for an internal RELHI reloc. The
11080 reloc is relative to the RELLO; adjust the addend
11082 if (symbol_section_p (fixp
->fx_addsy
))
11083 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11084 + fixp
->fx_next
->fx_where
11085 - S_GET_VALUE (fixp
->fx_subsy
));
11087 reloc
->addend
= (fixp
->fx_addnumber
11088 + fixp
->fx_next
->fx_frag
->fr_address
11089 + fixp
->fx_next
->fx_where
);
11091 else if (fixp
->fx_pcrel
== 0)
11092 reloc
->addend
= fixp
->fx_addnumber
;
11095 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11096 /* A gruesome hack which is a result of the gruesome gas reloc
11098 reloc
->addend
= reloc
->address
;
11100 reloc
->addend
= -reloc
->address
;
11103 /* If this is a variant frag, we may need to adjust the existing
11104 reloc and generate a new one. */
11105 if (fixp
->fx_frag
->fr_opcode
!= NULL
11106 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11107 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11108 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11109 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11110 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11111 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11112 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11116 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11118 /* If this is not the last reloc in this frag, then we have two
11119 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11120 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11121 the second one handle all of them. */
11122 if (fixp
->fx_next
!= NULL
11123 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11125 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11126 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11127 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11128 && (fixp
->fx_next
->fx_r_type
11129 == BFD_RELOC_MIPS_GOT_LO16
))
11130 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11131 && (fixp
->fx_next
->fx_r_type
11132 == BFD_RELOC_MIPS_CALL_LO16
)));
11137 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11138 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11139 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11141 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11142 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11143 reloc2
->address
= (reloc
->address
11144 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11145 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11146 reloc2
->addend
= fixp
->fx_addnumber
;
11147 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11148 assert (reloc2
->howto
!= NULL
);
11150 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11154 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11157 reloc3
->address
+= 4;
11160 if (mips_pic
== NO_PIC
)
11162 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11163 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11165 else if (mips_pic
== SVR4_PIC
)
11167 switch (fixp
->fx_r_type
)
11171 case BFD_RELOC_MIPS_GOT16
:
11173 case BFD_RELOC_MIPS_CALL16
:
11174 case BFD_RELOC_MIPS_GOT_LO16
:
11175 case BFD_RELOC_MIPS_CALL_LO16
:
11176 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11184 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11185 to be used in the relocation's section offset. */
11186 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11188 reloc
->address
= reloc
->addend
;
11192 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11193 fixup_segment converted a non-PC relative reloc into a PC
11194 relative reloc. In such a case, we need to convert the reloc
11196 code
= fixp
->fx_r_type
;
11197 if (fixp
->fx_pcrel
)
11202 code
= BFD_RELOC_8_PCREL
;
11205 code
= BFD_RELOC_16_PCREL
;
11208 code
= BFD_RELOC_32_PCREL
;
11211 code
= BFD_RELOC_64_PCREL
;
11213 case BFD_RELOC_8_PCREL
:
11214 case BFD_RELOC_16_PCREL
:
11215 case BFD_RELOC_32_PCREL
:
11216 case BFD_RELOC_64_PCREL
:
11217 case BFD_RELOC_16_PCREL_S2
:
11218 case BFD_RELOC_PCREL_HI16_S
:
11219 case BFD_RELOC_PCREL_LO16
:
11222 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11223 _("Cannot make %s relocation PC relative"),
11224 bfd_get_reloc_code_name (code
));
11228 /* To support a PC relative reloc when generating embedded PIC code
11229 for ECOFF, we use a Cygnus extension. We check for that here to
11230 make sure that we don't let such a reloc escape normally. */
11231 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11232 && code
== BFD_RELOC_16_PCREL_S2
11233 && mips_pic
!= EMBEDDED_PIC
)
11234 reloc
->howto
= NULL
;
11236 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11238 if (reloc
->howto
== NULL
)
11240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11241 _("Can not represent %s relocation in this object file format"),
11242 bfd_get_reloc_code_name (code
));
11249 /* Relax a machine dependent frag. This returns the amount by which
11250 the current size of the frag should change. */
11253 mips_relax_frag (fragp
, stretch
)
11257 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11260 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11262 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11264 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11269 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11271 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11278 /* Convert a machine dependent frag. */
11281 md_convert_frag (abfd
, asec
, fragp
)
11289 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11292 register const struct mips16_immed_operand
*op
;
11293 boolean small
, ext
;
11296 unsigned long insn
;
11297 boolean use_extend
;
11298 unsigned short extend
;
11300 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11301 op
= mips16_immed_operands
;
11302 while (op
->type
!= type
)
11305 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11316 resolve_symbol_value (fragp
->fr_symbol
, 1);
11317 val
= S_GET_VALUE (fragp
->fr_symbol
);
11322 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11324 /* The rules for the base address of a PC relative reloc are
11325 complicated; see mips16_extended_frag. */
11326 if (type
== 'p' || type
== 'q')
11331 /* Ignore the low bit in the target, since it will be
11332 set for a text label. */
11333 if ((val
& 1) != 0)
11336 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11338 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11341 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11344 /* Make sure the section winds up with the alignment we have
11347 record_alignment (asec
, op
->shift
);
11351 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11352 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11353 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11354 _("extended instruction in delay slot"));
11356 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11358 if (target_big_endian
)
11359 insn
= bfd_getb16 (buf
);
11361 insn
= bfd_getl16 (buf
);
11363 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11364 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11365 small
, ext
, &insn
, &use_extend
, &extend
);
11369 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11370 fragp
->fr_fix
+= 2;
11374 md_number_to_chars (buf
, insn
, 2);
11375 fragp
->fr_fix
+= 2;
11380 if (fragp
->fr_opcode
== NULL
)
11383 old
= RELAX_OLD (fragp
->fr_subtype
);
11384 new = RELAX_NEW (fragp
->fr_subtype
);
11385 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11388 memcpy (fixptr
- old
, fixptr
, new);
11390 fragp
->fr_fix
+= new - old
;
11396 /* This function is called after the relocs have been generated.
11397 We've been storing mips16 text labels as odd. Here we convert them
11398 back to even for the convenience of the debugger. */
11401 mips_frob_file_after_relocs ()
11404 unsigned int count
, i
;
11406 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11409 syms
= bfd_get_outsymbols (stdoutput
);
11410 count
= bfd_get_symcount (stdoutput
);
11411 for (i
= 0; i
< count
; i
++, syms
++)
11413 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11414 && ((*syms
)->value
& 1) != 0)
11416 (*syms
)->value
&= ~1;
11417 /* If the symbol has an odd size, it was probably computed
11418 incorrectly, so adjust that as well. */
11419 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11420 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11427 /* This function is called whenever a label is defined. It is used
11428 when handling branch delays; if a branch has a label, we assume we
11429 can not move it. */
11432 mips_define_label (sym
)
11435 struct insn_label_list
*l
;
11437 if (free_insn_labels
== NULL
)
11438 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11441 l
= free_insn_labels
;
11442 free_insn_labels
= l
->next
;
11446 l
->next
= insn_labels
;
11450 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11452 /* Some special processing for a MIPS ELF file. */
11455 mips_elf_final_processing ()
11457 /* Write out the register information. */
11462 s
.ri_gprmask
= mips_gprmask
;
11463 s
.ri_cprmask
[0] = mips_cprmask
[0];
11464 s
.ri_cprmask
[1] = mips_cprmask
[1];
11465 s
.ri_cprmask
[2] = mips_cprmask
[2];
11466 s
.ri_cprmask
[3] = mips_cprmask
[3];
11467 /* The gp_value field is set by the MIPS ELF backend. */
11469 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11470 ((Elf32_External_RegInfo
*)
11471 mips_regmask_frag
));
11475 Elf64_Internal_RegInfo s
;
11477 s
.ri_gprmask
= mips_gprmask
;
11479 s
.ri_cprmask
[0] = mips_cprmask
[0];
11480 s
.ri_cprmask
[1] = mips_cprmask
[1];
11481 s
.ri_cprmask
[2] = mips_cprmask
[2];
11482 s
.ri_cprmask
[3] = mips_cprmask
[3];
11483 /* The gp_value field is set by the MIPS ELF backend. */
11485 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11486 ((Elf64_External_RegInfo
*)
11487 mips_regmask_frag
));
11490 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11491 sort of BFD interface for this. */
11492 if (mips_any_noreorder
)
11493 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11494 if (mips_pic
!= NO_PIC
)
11495 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11497 /* Set the MIPS ELF ABI flags. */
11498 if (mips_abi_string
== 0)
11500 else if (strcmp (mips_abi_string
,"32") == 0)
11501 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11502 else if (strcmp (mips_abi_string
,"o64") == 0)
11503 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11504 else if (strcmp (mips_abi_string
,"eabi") == 0)
11507 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11509 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11512 if (mips_32bitmode
)
11513 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11516 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11518 typedef struct proc
11521 unsigned long reg_mask
;
11522 unsigned long reg_offset
;
11523 unsigned long fpreg_mask
;
11524 unsigned long fpreg_offset
;
11525 unsigned long frame_offset
;
11526 unsigned long frame_reg
;
11527 unsigned long pc_reg
;
11531 static procS cur_proc
;
11532 static procS
*cur_proc_ptr
;
11533 static int numprocs
;
11535 /* When we align code in the .text section of mips16, use the correct two
11536 byte nop pattern of 0x6500 (move $0,$0) */
11539 mips_do_align (n
, fill
, len
, max
)
11546 && subseg_text_p (now_seg
)
11548 && mips_opts
.mips16
)
11550 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11551 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11553 frag_align (1, 0, 0);
11555 if (target_big_endian
)
11556 frag_align_pattern (n
, be_nop
, 2, max
);
11558 frag_align_pattern (n
, le_nop
, 2, max
);
11573 /* check for premature end, nesting errors, etc */
11575 as_warn (_("missing `.end' at end of assembly"));
11584 if (*input_line_pointer
== '-')
11586 ++input_line_pointer
;
11589 if (!isdigit ((unsigned char) *input_line_pointer
))
11590 as_bad (_("Expected simple number."));
11591 if (input_line_pointer
[0] == '0')
11593 if (input_line_pointer
[1] == 'x')
11595 input_line_pointer
+= 2;
11596 while (isxdigit ((unsigned char) *input_line_pointer
))
11599 val
|= hex_value (*input_line_pointer
++);
11601 return negative
? -val
: val
;
11605 ++input_line_pointer
;
11606 while (isdigit ((unsigned char) *input_line_pointer
))
11609 val
|= *input_line_pointer
++ - '0';
11611 return negative
? -val
: val
;
11614 if (!isdigit ((unsigned char) *input_line_pointer
))
11616 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11617 *input_line_pointer
, *input_line_pointer
);
11618 as_warn (_("Invalid number"));
11621 while (isdigit ((unsigned char) *input_line_pointer
))
11624 val
+= *input_line_pointer
++ - '0';
11626 return negative
? -val
: val
;
11629 /* The .file directive; just like the usual .file directive, but there
11630 is an initial number which is the ECOFF file index. */
11638 line
= get_number ();
11643 /* The .end directive. */
11652 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11655 demand_empty_rest_of_line ();
11660 #ifdef BFD_ASSEMBLER
11661 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11666 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11673 as_warn (_(".end not in text section"));
11677 as_warn (_(".end directive without a preceding .ent directive."));
11678 demand_empty_rest_of_line ();
11684 assert (S_GET_NAME (p
));
11685 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11686 as_warn (_(".end symbol does not match .ent symbol."));
11689 as_warn (_(".end directive missing or unknown symbol"));
11691 #ifdef MIPS_STABS_ELF
11693 segT saved_seg
= now_seg
;
11694 subsegT saved_subseg
= now_subseg
;
11695 fragS
*saved_frag
= frag_now
;
11701 dot
= frag_now_fix ();
11703 #ifdef md_flush_pending_output
11704 md_flush_pending_output ();
11708 subseg_set (pdr_seg
, 0);
11710 /* Write the symbol */
11711 exp
.X_op
= O_symbol
;
11712 exp
.X_add_symbol
= p
;
11713 exp
.X_add_number
= 0;
11714 emit_expr (&exp
, 4);
11716 fragp
= frag_more (7*4);
11718 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11719 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11720 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11721 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11722 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11723 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11724 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11726 subseg_set (saved_seg
, saved_subseg
);
11730 cur_proc_ptr
= NULL
;
11733 /* The .aent and .ent directives. */
11743 symbolP
= get_symbol ();
11744 if (*input_line_pointer
== ',')
11745 input_line_pointer
++;
11746 SKIP_WHITESPACE ();
11747 if (isdigit ((unsigned char) *input_line_pointer
)
11748 || *input_line_pointer
== '-')
11749 number
= get_number ();
11751 #ifdef BFD_ASSEMBLER
11752 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11757 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11764 as_warn (_(".ent or .aent not in text section."));
11766 if (!aent
&& cur_proc_ptr
)
11767 as_warn (_("missing `.end'"));
11771 cur_proc_ptr
= &cur_proc
;
11772 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11774 cur_proc_ptr
->isym
= symbolP
;
11776 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11781 demand_empty_rest_of_line ();
11784 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11785 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11786 s_mips_frame is used so that we can set the PDR information correctly.
11787 We can't use the ecoff routines because they make reference to the ecoff
11788 symbol table (in the mdebug section). */
11791 s_mips_frame (ignore
)
11794 #ifdef MIPS_STABS_ELF
11798 if (cur_proc_ptr
== (procS
*) NULL
)
11800 as_warn (_(".frame outside of .ent"));
11801 demand_empty_rest_of_line ();
11805 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11807 SKIP_WHITESPACE ();
11808 if (*input_line_pointer
++ != ','
11809 || get_absolute_expression_and_terminator (&val
) != ',')
11811 as_warn (_("Bad .frame directive"));
11812 --input_line_pointer
;
11813 demand_empty_rest_of_line ();
11817 cur_proc_ptr
->frame_offset
= val
;
11818 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11820 demand_empty_rest_of_line ();
11823 #endif /* MIPS_STABS_ELF */
11826 /* The .fmask and .mask directives. If the mdebug section is present
11827 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11828 embedded targets, s_mips_mask is used so that we can set the PDR
11829 information correctly. We can't use the ecoff routines because they
11830 make reference to the ecoff symbol table (in the mdebug section). */
11833 s_mips_mask (reg_type
)
11836 #ifdef MIPS_STABS_ELF
11839 if (cur_proc_ptr
== (procS
*) NULL
)
11841 as_warn (_(".mask/.fmask outside of .ent"));
11842 demand_empty_rest_of_line ();
11846 if (get_absolute_expression_and_terminator (&mask
) != ',')
11848 as_warn (_("Bad .mask/.fmask directive"));
11849 --input_line_pointer
;
11850 demand_empty_rest_of_line ();
11854 off
= get_absolute_expression ();
11856 if (reg_type
== 'F')
11858 cur_proc_ptr
->fpreg_mask
= mask
;
11859 cur_proc_ptr
->fpreg_offset
= off
;
11863 cur_proc_ptr
->reg_mask
= mask
;
11864 cur_proc_ptr
->reg_offset
= off
;
11867 demand_empty_rest_of_line ();
11869 s_ignore (reg_type
);
11870 #endif /* MIPS_STABS_ELF */
11873 /* The .loc directive. */
11884 assert (now_seg
== text_section
);
11886 lineno
= get_number ();
11887 addroff
= frag_now_fix ();
11889 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11890 S_SET_TYPE (symbolP
, N_SLINE
);
11891 S_SET_OTHER (symbolP
, 0);
11892 S_SET_DESC (symbolP
, lineno
);
11893 symbolP
->sy_segment
= now_seg
;