1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 /* Return true if ISA supports 64-bit right rotate (dror et al.)
265 #define ISA_HAS_DROR(ISA) ( \
269 /* Return true if ISA supports 32-bit right rotate (ror et al.)
271 #define ISA_HAS_ROR(ISA) ( \
272 (ISA) == ISA_MIPS32R2 \
275 #define HAVE_32BIT_GPRS \
276 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
278 #define HAVE_32BIT_FPRS \
279 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
282 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
284 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
286 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
288 /* We can only have 64bit addresses if the object file format
290 #define HAVE_32BIT_ADDRESSES \
292 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS) \
294 && mips_pic != EMBEDDED_PIC))
296 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
298 /* Return true if the given CPU supports the MIPS16 ASE. */
299 #define CPU_HAS_MIPS16(cpu) \
300 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
301 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
303 /* Return true if the given CPU supports the MIPS3D ASE. */
304 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
307 /* Return true if the given CPU supports the MDMX ASE. */
308 #define CPU_HAS_MDMX(cpu) (FALSE \
311 /* True if CPU has a dror instruction. */
312 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
314 /* True if CPU has a ror instruction. */
315 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
317 /* Whether the processor uses hardware interlocks to protect
318 reads from the HI and LO registers, and thus does not
319 require nops to be inserted. */
321 #define hilo_interlocks (mips_arch == CPU_R4010 \
322 || mips_arch == CPU_VR5500 \
323 || mips_arch == CPU_SB1 \
326 /* Whether the processor uses hardware interlocks to protect reads
327 from the GPRs, and thus does not require nops to be inserted. */
328 #define gpr_interlocks \
329 (mips_opts.isa != ISA_MIPS1 \
330 || mips_arch == CPU_VR5400 \
331 || mips_arch == CPU_VR5500 \
332 || mips_arch == CPU_R3900)
334 /* As with other "interlocks" this is used by hardware that has FP
335 (co-processor) interlocks. */
336 /* Itbl support may require additional care here. */
337 #define cop_interlocks (mips_arch == CPU_R4300 \
338 || mips_arch == CPU_VR5400 \
339 || mips_arch == CPU_VR5500 \
340 || mips_arch == CPU_SB1 \
343 /* Is this a mfhi or mflo instruction? */
344 #define MF_HILO_INSN(PINFO) \
345 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
347 /* MIPS PIC level. */
349 enum mips_pic_level mips_pic
;
351 /* Warn about all NOPS that the assembler generates. */
352 static int warn_nops
= 0;
354 /* 1 if we should generate 32 bit offsets from the $gp register in
355 SVR4_PIC mode. Currently has no meaning in other modes. */
356 static int mips_big_got
= 0;
358 /* 1 if trap instructions should used for overflow rather than break
360 static int mips_trap
= 0;
362 /* 1 if double width floating point constants should not be constructed
363 by assembling two single width halves into two single width floating
364 point registers which just happen to alias the double width destination
365 register. On some architectures this aliasing can be disabled by a bit
366 in the status register, and the setting of this bit cannot be determined
367 automatically at assemble time. */
368 static int mips_disable_float_construction
;
370 /* Non-zero if any .set noreorder directives were used. */
372 static int mips_any_noreorder
;
374 /* Non-zero if nops should be inserted when the register referenced in
375 an mfhi/mflo instruction is read in the next two instructions. */
376 static int mips_7000_hilo_fix
;
378 /* The size of the small data section. */
379 static unsigned int g_switch_value
= 8;
380 /* Whether the -G option was used. */
381 static int g_switch_seen
= 0;
386 /* If we can determine in advance that GP optimization won't be
387 possible, we can skip the relaxation stuff that tries to produce
388 GP-relative references. This makes delay slot optimization work
391 This function can only provide a guess, but it seems to work for
392 gcc output. It needs to guess right for gcc, otherwise gcc
393 will put what it thinks is a GP-relative instruction in a branch
396 I don't know if a fix is needed for the SVR4_PIC mode. I've only
397 fixed it for the non-PIC mode. KR 95/04/07 */
398 static int nopic_need_relax
PARAMS ((symbolS
*, int));
400 /* handle of the OPCODE hash table */
401 static struct hash_control
*op_hash
= NULL
;
403 /* The opcode hash table we use for the mips16. */
404 static struct hash_control
*mips16_op_hash
= NULL
;
406 /* This array holds the chars that always start a comment. If the
407 pre-processor is disabled, these aren't very useful */
408 const char comment_chars
[] = "#";
410 /* This array holds the chars that only start a comment at the beginning of
411 a line. If the line seems to have the form '# 123 filename'
412 .line and .file directives will appear in the pre-processed output */
413 /* Note that input_file.c hand checks for '#' at the beginning of the
414 first line of the input file. This is because the compiler outputs
415 #NO_APP at the beginning of its output. */
416 /* Also note that C style comments are always supported. */
417 const char line_comment_chars
[] = "#";
419 /* This array holds machine specific line separator characters. */
420 const char line_separator_chars
[] = ";";
422 /* Chars that can be used to separate mant from exp in floating point nums */
423 const char EXP_CHARS
[] = "eE";
425 /* Chars that mean this number is a floating point constant */
428 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
430 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
431 changed in read.c . Ideally it shouldn't have to know about it at all,
432 but nothing is ideal around here.
435 static char *insn_error
;
437 static int auto_align
= 1;
439 /* When outputting SVR4 PIC code, the assembler needs to know the
440 offset in the stack frame from which to restore the $gp register.
441 This is set by the .cprestore pseudo-op, and saved in this
443 static offsetT mips_cprestore_offset
= -1;
445 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
446 more optimizations, it can use a register value instead of a memory-saved
447 offset and even an other register than $gp as global pointer. */
448 static offsetT mips_cpreturn_offset
= -1;
449 static int mips_cpreturn_register
= -1;
450 static int mips_gp_register
= GP
;
451 static int mips_gprel_offset
= 0;
453 /* Whether mips_cprestore_offset has been set in the current function
454 (or whether it has already been warned about, if not). */
455 static int mips_cprestore_valid
= 0;
457 /* This is the register which holds the stack frame, as set by the
458 .frame pseudo-op. This is needed to implement .cprestore. */
459 static int mips_frame_reg
= SP
;
461 /* Whether mips_frame_reg has been set in the current function
462 (or whether it has already been warned about, if not). */
463 static int mips_frame_reg_valid
= 0;
465 /* To output NOP instructions correctly, we need to keep information
466 about the previous two instructions. */
468 /* Whether we are optimizing. The default value of 2 means to remove
469 unneeded NOPs and swap branch instructions when possible. A value
470 of 1 means to not swap branches. A value of 0 means to always
472 static int mips_optimize
= 2;
474 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
475 equivalent to seeing no -g option at all. */
476 static int mips_debug
= 0;
478 /* The previous instruction. */
479 static struct mips_cl_insn prev_insn
;
481 /* The instruction before prev_insn. */
482 static struct mips_cl_insn prev_prev_insn
;
484 /* If we don't want information for prev_insn or prev_prev_insn, we
485 point the insn_mo field at this dummy integer. */
486 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
488 /* Non-zero if prev_insn is valid. */
489 static int prev_insn_valid
;
491 /* The frag for the previous instruction. */
492 static struct frag
*prev_insn_frag
;
494 /* The offset into prev_insn_frag for the previous instruction. */
495 static long prev_insn_where
;
497 /* The reloc type for the previous instruction, if any. */
498 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
500 /* The reloc for the previous instruction, if any. */
501 static fixS
*prev_insn_fixp
[3];
503 /* Non-zero if the previous instruction was in a delay slot. */
504 static int prev_insn_is_delay_slot
;
506 /* Non-zero if the previous instruction was in a .set noreorder. */
507 static int prev_insn_unreordered
;
509 /* Non-zero if the previous instruction uses an extend opcode (if
511 static int prev_insn_extended
;
513 /* Non-zero if the previous previous instruction was in a .set
515 static int prev_prev_insn_unreordered
;
517 /* If this is set, it points to a frag holding nop instructions which
518 were inserted before the start of a noreorder section. If those
519 nops turn out to be unnecessary, the size of the frag can be
521 static fragS
*prev_nop_frag
;
523 /* The number of nop instructions we created in prev_nop_frag. */
524 static int prev_nop_frag_holds
;
526 /* The number of nop instructions that we know we need in
528 static int prev_nop_frag_required
;
530 /* The number of instructions we've seen since prev_nop_frag. */
531 static int prev_nop_frag_since
;
533 /* For ECOFF and ELF, relocations against symbols are done in two
534 parts, with a HI relocation and a LO relocation. Each relocation
535 has only 16 bits of space to store an addend. This means that in
536 order for the linker to handle carries correctly, it must be able
537 to locate both the HI and the LO relocation. This means that the
538 relocations must appear in order in the relocation table.
540 In order to implement this, we keep track of each unmatched HI
541 relocation. We then sort them so that they immediately precede the
542 corresponding LO relocation. */
547 struct mips_hi_fixup
*next
;
550 /* The section this fixup is in. */
554 /* The list of unmatched HI relocs. */
556 static struct mips_hi_fixup
*mips_hi_fixup_list
;
558 /* Map normal MIPS register numbers to mips16 register numbers. */
560 #define X ILLEGAL_REG
561 static const int mips32_to_16_reg_map
[] =
563 X
, X
, 2, 3, 4, 5, 6, 7,
564 X
, X
, X
, X
, X
, X
, X
, X
,
565 0, 1, X
, X
, X
, X
, X
, X
,
566 X
, X
, X
, X
, X
, X
, X
, X
570 /* Map mips16 register numbers to normal MIPS register numbers. */
572 static const unsigned int mips16_to_32_reg_map
[] =
574 16, 17, 2, 3, 4, 5, 6, 7
577 static int mips_fix_4122_bugs
;
579 /* We don't relax branches by default, since this causes us to expand
580 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
581 fail to compute the offset before expanding the macro to the most
582 efficient expansion. */
584 static int mips_relax_branch
;
586 /* Since the MIPS does not have multiple forms of PC relative
587 instructions, we do not have to do relaxing as is done on other
588 platforms. However, we do have to handle GP relative addressing
589 correctly, which turns out to be a similar problem.
591 Every macro that refers to a symbol can occur in (at least) two
592 forms, one with GP relative addressing and one without. For
593 example, loading a global variable into a register generally uses
594 a macro instruction like this:
596 If i can be addressed off the GP register (this is true if it is in
597 the .sbss or .sdata section, or if it is known to be smaller than
598 the -G argument) this will generate the following instruction:
600 This instruction will use a GPREL reloc. If i can not be addressed
601 off the GP register, the following instruction sequence will be used:
604 In this case the first instruction will have a HI16 reloc, and the
605 second reloc will have a LO16 reloc. Both relocs will be against
608 The issue here is that we may not know whether i is GP addressable
609 until after we see the instruction that uses it. Therefore, we
610 want to be able to choose the final instruction sequence only at
611 the end of the assembly. This is similar to the way other
612 platforms choose the size of a PC relative instruction only at the
615 When generating position independent code we do not use GP
616 addressing in quite the same way, but the issue still arises as
617 external symbols and local symbols must be handled differently.
619 We handle these issues by actually generating both possible
620 instruction sequences. The longer one is put in a frag_var with
621 type rs_machine_dependent. We encode what to do with the frag in
622 the subtype field. We encode (1) the number of existing bytes to
623 replace, (2) the number of new bytes to use, (3) the offset from
624 the start of the existing bytes to the first reloc we must generate
625 (that is, the offset is applied from the start of the existing
626 bytes after they are replaced by the new bytes, if any), (4) the
627 offset from the start of the existing bytes to the second reloc,
628 (5) whether a third reloc is needed (the third reloc is always four
629 bytes after the second reloc), and (6) whether to warn if this
630 variant is used (this is sometimes needed if .set nomacro or .set
631 noat is in effect). All these numbers are reasonably small.
633 Generating two instruction sequences must be handled carefully to
634 ensure that delay slots are handled correctly. Fortunately, there
635 are a limited number of cases. When the second instruction
636 sequence is generated, append_insn is directed to maintain the
637 existing delay slot information, so it continues to apply to any
638 code after the second instruction sequence. This means that the
639 second instruction sequence must not impose any requirements not
640 required by the first instruction sequence.
642 These variant frags are then handled in functions called by the
643 machine independent code. md_estimate_size_before_relax returns
644 the final size of the frag. md_convert_frag sets up the final form
645 of the frag. tc_gen_reloc adjust the first reloc and adds a second
647 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
651 | (((reloc1) + 64) << 9) \
652 | (((reloc2) + 64) << 2) \
653 | ((reloc3) ? (1 << 1) : 0) \
655 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
656 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
657 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
658 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
659 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
660 #define RELAX_WARN(i) ((i) & 1)
662 /* Branch without likely bit. If label is out of range, we turn:
664 beq reg1, reg2, label
674 with the following opcode replacements:
681 bltzal <-> bgezal (with jal label instead of j label)
683 Even though keeping the delay slot instruction in the delay slot of
684 the branch would be more efficient, it would be very tricky to do
685 correctly, because we'd have to introduce a variable frag *after*
686 the delay slot instruction, and expand that instead. Let's do it
687 the easy way for now, even if the branch-not-taken case now costs
688 one additional instruction. Out-of-range branches are not supposed
689 to be common, anyway.
691 Branch likely. If label is out of range, we turn:
693 beql reg1, reg2, label
694 delay slot (annulled if branch not taken)
703 delay slot (executed only if branch taken)
706 It would be possible to generate a shorter sequence by losing the
707 likely bit, generating something like:
712 delay slot (executed only if branch taken)
724 bltzall -> bgezal (with jal label instead of j label)
725 bgezall -> bltzal (ditto)
728 but it's not clear that it would actually improve performance. */
729 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
732 | ((toofar) ? 1 : 0) \
734 | ((likely) ? 4 : 0) \
735 | ((uncond) ? 8 : 0)))
736 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
737 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
738 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
739 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
740 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
742 /* For mips16 code, we use an entirely different form of relaxation.
743 mips16 supports two versions of most instructions which take
744 immediate values: a small one which takes some small value, and a
745 larger one which takes a 16 bit value. Since branches also follow
746 this pattern, relaxing these values is required.
748 We can assemble both mips16 and normal MIPS code in a single
749 object. Therefore, we need to support this type of relaxation at
750 the same time that we support the relaxation described above. We
751 use the high bit of the subtype field to distinguish these cases.
753 The information we store for this type of relaxation is the
754 argument code found in the opcode file for this relocation, whether
755 the user explicitly requested a small or extended form, and whether
756 the relocation is in a jump or jal delay slot. That tells us the
757 size of the value, and how it should be stored. We also store
758 whether the fragment is considered to be extended or not. We also
759 store whether this is known to be a branch to a different section,
760 whether we have tried to relax this frag yet, and whether we have
761 ever extended a PC relative fragment because of a shift count. */
762 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
765 | ((small) ? 0x100 : 0) \
766 | ((ext) ? 0x200 : 0) \
767 | ((dslot) ? 0x400 : 0) \
768 | ((jal_dslot) ? 0x800 : 0))
769 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
770 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
771 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
772 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
773 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
774 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
775 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
776 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
777 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
778 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
779 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
780 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
782 /* Is the given value a sign-extended 32-bit value? */
783 #define IS_SEXT_32BIT_NUM(x) \
784 (((x) &~ (offsetT) 0x7fffffff) == 0 \
785 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
787 /* Is the given value a sign-extended 16-bit value? */
788 #define IS_SEXT_16BIT_NUM(x) \
789 (((x) &~ (offsetT) 0x7fff) == 0 \
790 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
793 /* Prototypes for static functions. */
796 #define internalError() \
797 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
799 #define internalError() as_fatal (_("MIPS internal Error"));
802 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
804 static int insn_uses_reg
805 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
806 enum mips_regclass
class));
807 static int reg_needs_delay
808 PARAMS ((unsigned int));
809 static void mips16_mark_labels
811 static void append_insn
812 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
813 bfd_reloc_code_real_type
*r
));
814 static void mips_no_prev_insn
816 static void mips_emit_delays
817 PARAMS ((bfd_boolean
));
819 static void macro_build
820 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
821 const char *fmt
, ...));
823 static void macro_build ();
825 static void mips16_macro_build
826 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
827 static void macro_build_jalr
828 PARAMS ((int, expressionS
*));
829 static void macro_build_lui
830 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
831 static void macro_build_ldst_constoffset
832 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
833 int valreg
, int breg
));
835 PARAMS ((int *counter
, int reg
, int unsignedp
));
836 static void check_absolute_expr
837 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
838 static void load_register
839 PARAMS ((int *, int, expressionS
*, int));
840 static void load_address
841 PARAMS ((int *, int, expressionS
*, int *));
842 static void move_register
843 PARAMS ((int *, int, int));
845 PARAMS ((struct mips_cl_insn
* ip
));
846 static void mips16_macro
847 PARAMS ((struct mips_cl_insn
* ip
));
848 #ifdef LOSING_COMPILER
850 PARAMS ((struct mips_cl_insn
* ip
));
853 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
854 static void mips16_ip
855 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
856 static void mips16_immed
857 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
858 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
859 static bfd_boolean parse_relocation
860 PARAMS ((char **, bfd_reloc_code_real_type
*));
861 static size_t my_getSmallExpression
862 PARAMS ((expressionS
*, bfd_reloc_code_real_type
*, char *));
863 static void my_getExpression
864 PARAMS ((expressionS
*, char *));
866 static int support_64bit_objects
869 static void mips_set_option_string
870 PARAMS ((const char **, const char *));
871 static symbolS
*get_symbol
873 static void mips_align
874 PARAMS ((int to
, int fill
, symbolS
*label
));
877 static void s_change_sec
879 static void s_change_section
883 static void s_float_cons
885 static void s_mips_globl
889 static void s_mipsset
891 static void s_abicalls
895 static void s_cpsetup
897 static void s_cplocal
899 static void s_cprestore
901 static void s_cpreturn
903 static void s_gpvalue
907 static void s_gpdword
913 static void md_obj_begin
915 static void md_obj_end
917 static long get_number
919 static void s_mips_ent
921 static void s_mips_end
923 static void s_mips_frame
925 static void s_mips_mask
927 static void s_mips_stab
929 static void s_mips_weakext
931 static void s_mips_file
933 static void s_mips_loc
935 static int mips16_extended_frag
936 PARAMS ((fragS
*, asection
*, long));
937 static int relaxed_branch_length (fragS
*, asection
*, int);
938 static int validate_mips_insn
939 PARAMS ((const struct mips_opcode
*));
941 PARAMS ((FILE *, const char *, int *, int *));
943 static int mips_need_elf_addend_fixup
947 /* Table and functions used to map between CPU/ISA names, and
948 ISA levels, and CPU numbers. */
952 const char *name
; /* CPU or ISA name. */
953 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
954 int isa
; /* ISA level. */
955 int cpu
; /* CPU number (default CPU if ISA). */
958 static void mips_set_architecture
959 PARAMS ((const struct mips_cpu_info
*));
960 static void mips_set_tune
961 PARAMS ((const struct mips_cpu_info
*));
962 static bfd_boolean mips_strict_matching_cpu_name_p
963 PARAMS ((const char *, const char *));
964 static bfd_boolean mips_matching_cpu_name_p
965 PARAMS ((const char *, const char *));
966 static const struct mips_cpu_info
*mips_parse_cpu
967 PARAMS ((const char *, const char *));
968 static const struct mips_cpu_info
*mips_cpu_info_from_isa
973 The following pseudo-ops from the Kane and Heinrich MIPS book
974 should be defined here, but are currently unsupported: .alias,
975 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
977 The following pseudo-ops from the Kane and Heinrich MIPS book are
978 specific to the type of debugging information being generated, and
979 should be defined by the object format: .aent, .begin, .bend,
980 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
983 The following pseudo-ops from the Kane and Heinrich MIPS book are
984 not MIPS CPU specific, but are also not specific to the object file
985 format. This file is probably the best place to define them, but
986 they are not currently supported: .asm0, .endr, .lab, .repeat,
989 static const pseudo_typeS mips_pseudo_table
[] =
991 /* MIPS specific pseudo-ops. */
992 {"option", s_option
, 0},
993 {"set", s_mipsset
, 0},
994 {"rdata", s_change_sec
, 'r'},
995 {"sdata", s_change_sec
, 's'},
996 {"livereg", s_ignore
, 0},
997 {"abicalls", s_abicalls
, 0},
998 {"cpload", s_cpload
, 0},
999 {"cpsetup", s_cpsetup
, 0},
1000 {"cplocal", s_cplocal
, 0},
1001 {"cprestore", s_cprestore
, 0},
1002 {"cpreturn", s_cpreturn
, 0},
1003 {"gpvalue", s_gpvalue
, 0},
1004 {"gpword", s_gpword
, 0},
1005 {"gpdword", s_gpdword
, 0},
1006 {"cpadd", s_cpadd
, 0},
1007 {"insn", s_insn
, 0},
1009 /* Relatively generic pseudo-ops that happen to be used on MIPS
1011 {"asciiz", stringer
, 1},
1012 {"bss", s_change_sec
, 'b'},
1014 {"half", s_cons
, 1},
1015 {"dword", s_cons
, 3},
1016 {"weakext", s_mips_weakext
, 0},
1018 /* These pseudo-ops are defined in read.c, but must be overridden
1019 here for one reason or another. */
1020 {"align", s_align
, 0},
1021 {"byte", s_cons
, 0},
1022 {"data", s_change_sec
, 'd'},
1023 {"double", s_float_cons
, 'd'},
1024 {"float", s_float_cons
, 'f'},
1025 {"globl", s_mips_globl
, 0},
1026 {"global", s_mips_globl
, 0},
1027 {"hword", s_cons
, 1},
1029 {"long", s_cons
, 2},
1030 {"octa", s_cons
, 4},
1031 {"quad", s_cons
, 3},
1032 {"section", s_change_section
, 0},
1033 {"short", s_cons
, 1},
1034 {"single", s_float_cons
, 'f'},
1035 {"stabn", s_mips_stab
, 'n'},
1036 {"text", s_change_sec
, 't'},
1037 {"word", s_cons
, 2},
1039 { "extern", ecoff_directive_extern
, 0},
1044 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1046 /* These pseudo-ops should be defined by the object file format.
1047 However, a.out doesn't support them, so we have versions here. */
1048 {"aent", s_mips_ent
, 1},
1049 {"bgnb", s_ignore
, 0},
1050 {"end", s_mips_end
, 0},
1051 {"endb", s_ignore
, 0},
1052 {"ent", s_mips_ent
, 0},
1053 {"file", s_mips_file
, 0},
1054 {"fmask", s_mips_mask
, 'F'},
1055 {"frame", s_mips_frame
, 0},
1056 {"loc", s_mips_loc
, 0},
1057 {"mask", s_mips_mask
, 'R'},
1058 {"verstamp", s_ignore
, 0},
1062 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1067 pop_insert (mips_pseudo_table
);
1068 if (! ECOFF_DEBUGGING
)
1069 pop_insert (mips_nonecoff_pseudo_table
);
1072 /* Symbols labelling the current insn. */
1074 struct insn_label_list
1076 struct insn_label_list
*next
;
1080 static struct insn_label_list
*insn_labels
;
1081 static struct insn_label_list
*free_insn_labels
;
1083 static void mips_clear_insn_labels
PARAMS ((void));
1086 mips_clear_insn_labels ()
1088 register struct insn_label_list
**pl
;
1090 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1096 static char *expr_end
;
1098 /* Expressions which appear in instructions. These are set by
1101 static expressionS imm_expr
;
1102 static expressionS offset_expr
;
1104 /* Relocs associated with imm_expr and offset_expr. */
1106 static bfd_reloc_code_real_type imm_reloc
[3]
1107 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1108 static bfd_reloc_code_real_type offset_reloc
[3]
1109 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1111 /* These are set by mips16_ip if an explicit extension is used. */
1113 static bfd_boolean mips16_small
, mips16_ext
;
1116 /* The pdr segment for per procedure frame/regmask info. Not used for
1119 static segT pdr_seg
;
1122 /* The default target format to use. */
1125 mips_target_format ()
1127 switch (OUTPUT_FLAVOR
)
1129 case bfd_target_aout_flavour
:
1130 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1131 case bfd_target_ecoff_flavour
:
1132 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1133 case bfd_target_coff_flavour
:
1135 case bfd_target_elf_flavour
:
1137 /* This is traditional mips. */
1138 return (target_big_endian
1139 ? (HAVE_64BIT_OBJECTS
1140 ? "elf64-tradbigmips"
1142 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1143 : (HAVE_64BIT_OBJECTS
1144 ? "elf64-tradlittlemips"
1146 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1148 return (target_big_endian
1149 ? (HAVE_64BIT_OBJECTS
1152 ? "elf32-nbigmips" : "elf32-bigmips"))
1153 : (HAVE_64BIT_OBJECTS
1154 ? "elf64-littlemips"
1156 ? "elf32-nlittlemips" : "elf32-littlemips")));
1164 /* This function is called once, at assembler startup time. It should
1165 set up all the tables, etc. that the MD part of the assembler will need. */
1170 register const char *retval
= NULL
;
1174 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1175 as_warn (_("Could not set architecture and machine"));
1177 op_hash
= hash_new ();
1179 for (i
= 0; i
< NUMOPCODES
;)
1181 const char *name
= mips_opcodes
[i
].name
;
1183 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1186 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1187 mips_opcodes
[i
].name
, retval
);
1188 /* Probably a memory allocation problem? Give up now. */
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1193 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1195 if (!validate_mips_insn (&mips_opcodes
[i
]))
1200 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1203 mips16_op_hash
= hash_new ();
1206 while (i
< bfd_mips16_num_opcodes
)
1208 const char *name
= mips16_opcodes
[i
].name
;
1210 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1212 as_fatal (_("internal: can't hash `%s': %s"),
1213 mips16_opcodes
[i
].name
, retval
);
1216 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1217 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1218 != mips16_opcodes
[i
].match
))
1220 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1221 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1226 while (i
< bfd_mips16_num_opcodes
1227 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1231 as_fatal (_("Broken assembler. No assembly attempted."));
1233 /* We add all the general register names to the symbol table. This
1234 helps us detect invalid uses of them. */
1235 for (i
= 0; i
< 32; i
++)
1239 sprintf (buf
, "$%d", i
);
1240 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1241 &zero_address_frag
));
1243 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1244 &zero_address_frag
));
1245 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1246 &zero_address_frag
));
1247 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1248 &zero_address_frag
));
1249 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1250 &zero_address_frag
));
1251 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1252 &zero_address_frag
));
1253 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1254 &zero_address_frag
));
1255 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1256 &zero_address_frag
));
1257 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1258 &zero_address_frag
));
1259 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1260 &zero_address_frag
));
1262 /* If we don't add these register names to the symbol table, they
1263 may end up being added as regular symbols by operand(), and then
1264 make it to the object file as undefined in case they're not
1265 regarded as local symbols. They're local in o32, since `$' is a
1266 local symbol prefix, but not in n32 or n64. */
1267 for (i
= 0; i
< 8; i
++)
1271 sprintf (buf
, "$fcc%i", i
);
1272 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1273 &zero_address_frag
));
1276 mips_no_prev_insn (FALSE
);
1279 mips_cprmask
[0] = 0;
1280 mips_cprmask
[1] = 0;
1281 mips_cprmask
[2] = 0;
1282 mips_cprmask
[3] = 0;
1284 /* set the default alignment for the text section (2**2) */
1285 record_alignment (text_section
, 2);
1287 if (USE_GLOBAL_POINTER_OPT
)
1288 bfd_set_gp_size (stdoutput
, g_switch_value
);
1290 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1292 /* On a native system, sections must be aligned to 16 byte
1293 boundaries. When configured for an embedded ELF target, we
1295 if (strcmp (TARGET_OS
, "elf") != 0)
1297 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1298 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1299 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1302 /* Create a .reginfo section for register masks and a .mdebug
1303 section for debugging information. */
1311 subseg
= now_subseg
;
1313 /* The ABI says this section should be loaded so that the
1314 running program can access it. However, we don't load it
1315 if we are configured for an embedded target */
1316 flags
= SEC_READONLY
| SEC_DATA
;
1317 if (strcmp (TARGET_OS
, "elf") != 0)
1318 flags
|= SEC_ALLOC
| SEC_LOAD
;
1320 if (mips_abi
!= N64_ABI
)
1322 sec
= subseg_new (".reginfo", (subsegT
) 0);
1324 bfd_set_section_flags (stdoutput
, sec
, flags
);
1325 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1328 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1333 /* The 64-bit ABI uses a .MIPS.options section rather than
1334 .reginfo section. */
1335 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1336 bfd_set_section_flags (stdoutput
, sec
, flags
);
1337 bfd_set_section_alignment (stdoutput
, sec
, 3);
1340 /* Set up the option header. */
1342 Elf_Internal_Options opthdr
;
1345 opthdr
.kind
= ODK_REGINFO
;
1346 opthdr
.size
= (sizeof (Elf_External_Options
)
1347 + sizeof (Elf64_External_RegInfo
));
1350 f
= frag_more (sizeof (Elf_External_Options
));
1351 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1352 (Elf_External_Options
*) f
);
1354 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1359 if (ECOFF_DEBUGGING
)
1361 sec
= subseg_new (".mdebug", (subsegT
) 0);
1362 (void) bfd_set_section_flags (stdoutput
, sec
,
1363 SEC_HAS_CONTENTS
| SEC_READONLY
);
1364 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1367 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1369 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1370 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1371 SEC_READONLY
| SEC_RELOC
1373 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1377 subseg_set (seg
, subseg
);
1381 if (! ECOFF_DEBUGGING
)
1388 if (! ECOFF_DEBUGGING
)
1396 struct mips_cl_insn insn
;
1397 bfd_reloc_code_real_type unused_reloc
[3]
1398 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1400 imm_expr
.X_op
= O_absent
;
1401 offset_expr
.X_op
= O_absent
;
1402 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1403 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1404 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1405 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1406 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1407 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1409 if (mips_opts
.mips16
)
1410 mips16_ip (str
, &insn
);
1413 mips_ip (str
, &insn
);
1414 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1415 str
, insn
.insn_opcode
));
1420 as_bad ("%s `%s'", insn_error
, str
);
1424 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1426 if (mips_opts
.mips16
)
1427 mips16_macro (&insn
);
1433 if (imm_expr
.X_op
!= O_absent
)
1434 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1435 else if (offset_expr
.X_op
!= O_absent
)
1436 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1438 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1442 /* See whether instruction IP reads register REG. CLASS is the type
1446 insn_uses_reg (ip
, reg
, class)
1447 struct mips_cl_insn
*ip
;
1449 enum mips_regclass
class;
1451 if (class == MIPS16_REG
)
1453 assert (mips_opts
.mips16
);
1454 reg
= mips16_to_32_reg_map
[reg
];
1455 class = MIPS_GR_REG
;
1458 /* Don't report on general register ZERO, since it never changes. */
1459 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1462 if (class == MIPS_FP_REG
)
1464 assert (! mips_opts
.mips16
);
1465 /* If we are called with either $f0 or $f1, we must check $f0.
1466 This is not optimal, because it will introduce an unnecessary
1467 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1468 need to distinguish reading both $f0 and $f1 or just one of
1469 them. Note that we don't have to check the other way,
1470 because there is no instruction that sets both $f0 and $f1
1471 and requires a delay. */
1472 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1473 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1474 == (reg
&~ (unsigned) 1)))
1476 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1477 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1478 == (reg
&~ (unsigned) 1)))
1481 else if (! mips_opts
.mips16
)
1483 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1484 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1486 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1487 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1493 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1494 & MIPS16OP_MASK_RX
)]
1497 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1498 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1499 & MIPS16OP_MASK_RY
)]
1502 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1503 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1504 & MIPS16OP_MASK_MOVE32Z
)]
1507 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1509 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1511 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1513 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1514 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1515 & MIPS16OP_MASK_REGR32
) == reg
)
1522 /* This function returns true if modifying a register requires a
1526 reg_needs_delay (reg
)
1529 unsigned long prev_pinfo
;
1531 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1532 if (! mips_opts
.noreorder
1533 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1534 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1535 || (! gpr_interlocks
1536 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1538 /* A load from a coprocessor or from memory. All load
1539 delays delay the use of general register rt for one
1540 instruction on the r3000. The r6000 and r4000 use
1542 /* Itbl support may require additional care here. */
1543 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1544 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1551 /* Mark instruction labels in mips16 mode. This permits the linker to
1552 handle them specially, such as generating jalx instructions when
1553 needed. We also make them odd for the duration of the assembly, in
1554 order to generate the right sort of code. We will make them even
1555 in the adjust_symtab routine, while leaving them marked. This is
1556 convenient for the debugger and the disassembler. The linker knows
1557 to make them odd again. */
1560 mips16_mark_labels ()
1562 if (mips_opts
.mips16
)
1564 struct insn_label_list
*l
;
1567 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1570 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1571 S_SET_OTHER (l
->label
, STO_MIPS16
);
1573 val
= S_GET_VALUE (l
->label
);
1575 S_SET_VALUE (l
->label
, val
+ 1);
1580 /* Output an instruction. PLACE is where to put the instruction; if
1581 it is NULL, this uses frag_more to get room. IP is the instruction
1582 information. ADDRESS_EXPR is an operand of the instruction to be
1583 used with RELOC_TYPE. */
1586 append_insn (place
, ip
, address_expr
, reloc_type
)
1588 struct mips_cl_insn
*ip
;
1589 expressionS
*address_expr
;
1590 bfd_reloc_code_real_type
*reloc_type
;
1592 register unsigned long prev_pinfo
, pinfo
;
1596 bfd_boolean unmatched_reloc_p
;
1598 /* Mark instruction labels in mips16 mode. */
1599 mips16_mark_labels ();
1601 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1602 pinfo
= ip
->insn_mo
->pinfo
;
1603 unmatched_reloc_p
= FALSE
;
1605 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1609 /* If the previous insn required any delay slots, see if we need
1610 to insert a NOP or two. There are eight kinds of possible
1611 hazards, of which an instruction can have at most one type.
1612 (1) a load from memory delay
1613 (2) a load from a coprocessor delay
1614 (3) an unconditional branch delay
1615 (4) a conditional branch delay
1616 (5) a move to coprocessor register delay
1617 (6) a load coprocessor register from memory delay
1618 (7) a coprocessor condition code delay
1619 (8) a HI/LO special register delay
1621 There are a lot of optimizations we could do that we don't.
1622 In particular, we do not, in general, reorder instructions.
1623 If you use gcc with optimization, it will reorder
1624 instructions and generally do much more optimization then we
1625 do here; repeating all that work in the assembler would only
1626 benefit hand written assembly code, and does not seem worth
1629 /* This is how a NOP is emitted. */
1630 #define emit_nop() \
1632 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1633 : md_number_to_chars (frag_more (4), 0, 4))
1635 /* The previous insn might require a delay slot, depending upon
1636 the contents of the current insn. */
1637 if (! mips_opts
.mips16
1638 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1639 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1640 && ! cop_interlocks
)
1641 || (! gpr_interlocks
1642 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1644 /* A load from a coprocessor or from memory. All load
1645 delays delay the use of general register rt for one
1646 instruction on the r3000. The r6000 and r4000 use
1648 /* Itbl support may require additional care here. */
1649 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1650 if (mips_optimize
== 0
1651 || insn_uses_reg (ip
,
1652 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1657 else if (! mips_opts
.mips16
1658 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1659 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1660 && ! cop_interlocks
)
1661 || (mips_opts
.isa
== ISA_MIPS1
1662 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1664 /* A generic coprocessor delay. The previous instruction
1665 modified a coprocessor general or control register. If
1666 it modified a control register, we need to avoid any
1667 coprocessor instruction (this is probably not always
1668 required, but it sometimes is). If it modified a general
1669 register, we avoid using that register.
1671 On the r6000 and r4000 loading a coprocessor register
1672 from memory is interlocked, and does not require a delay.
1674 This case is not handled very well. There is no special
1675 knowledge of CP0 handling, and the coprocessors other
1676 than the floating point unit are not distinguished at
1678 /* Itbl support may require additional care here. FIXME!
1679 Need to modify this to include knowledge about
1680 user specified delays! */
1681 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1683 if (mips_optimize
== 0
1684 || insn_uses_reg (ip
,
1685 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1690 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1692 if (mips_optimize
== 0
1693 || insn_uses_reg (ip
,
1694 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1701 /* We don't know exactly what the previous instruction
1702 does. If the current instruction uses a coprocessor
1703 register, we must insert a NOP. If previous
1704 instruction may set the condition codes, and the
1705 current instruction uses them, we must insert two
1707 /* Itbl support may require additional care here. */
1708 if (mips_optimize
== 0
1709 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1710 && (pinfo
& INSN_READ_COND_CODE
)))
1712 else if (pinfo
& INSN_COP
)
1716 else if (! mips_opts
.mips16
1717 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1718 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1719 && ! cop_interlocks
)
1721 /* The previous instruction sets the coprocessor condition
1722 codes, but does not require a general coprocessor delay
1723 (this means it is a floating point comparison
1724 instruction). If this instruction uses the condition
1725 codes, we need to insert a single NOP. */
1726 /* Itbl support may require additional care here. */
1727 if (mips_optimize
== 0
1728 || (pinfo
& INSN_READ_COND_CODE
))
1732 /* If we're fixing up mfhi/mflo for the r7000 and the
1733 previous insn was an mfhi/mflo and the current insn
1734 reads the register that the mfhi/mflo wrote to, then
1737 else if (mips_7000_hilo_fix
1738 && MF_HILO_INSN (prev_pinfo
)
1739 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1746 /* If we're fixing up mfhi/mflo for the r7000 and the
1747 2nd previous insn was an mfhi/mflo and the current insn
1748 reads the register that the mfhi/mflo wrote to, then
1751 else if (mips_7000_hilo_fix
1752 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1753 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1761 else if (prev_pinfo
& INSN_READ_LO
)
1763 /* The previous instruction reads the LO register; if the
1764 current instruction writes to the LO register, we must
1765 insert two NOPS. Some newer processors have interlocks.
1766 Also the tx39's multiply instructions can be exectuted
1767 immediatly after a read from HI/LO (without the delay),
1768 though the tx39's divide insns still do require the
1770 if (! (hilo_interlocks
1771 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1772 && (mips_optimize
== 0
1773 || (pinfo
& INSN_WRITE_LO
)))
1775 /* Most mips16 branch insns don't have a delay slot.
1776 If a read from LO is immediately followed by a branch
1777 to a write to LO we have a read followed by a write
1778 less than 2 insns away. We assume the target of
1779 a branch might be a write to LO, and insert a nop
1780 between a read and an immediately following branch. */
1781 else if (mips_opts
.mips16
1782 && (mips_optimize
== 0
1783 || (pinfo
& MIPS16_INSN_BRANCH
)))
1786 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1788 /* The previous instruction reads the HI register; if the
1789 current instruction writes to the HI register, we must
1790 insert a NOP. Some newer processors have interlocks.
1791 Also the note tx39's multiply above. */
1792 if (! (hilo_interlocks
1793 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1794 && (mips_optimize
== 0
1795 || (pinfo
& INSN_WRITE_HI
)))
1797 /* Most mips16 branch insns don't have a delay slot.
1798 If a read from HI is immediately followed by a branch
1799 to a write to HI we have a read followed by a write
1800 less than 2 insns away. We assume the target of
1801 a branch might be a write to HI, and insert a nop
1802 between a read and an immediately following branch. */
1803 else if (mips_opts
.mips16
1804 && (mips_optimize
== 0
1805 || (pinfo
& MIPS16_INSN_BRANCH
)))
1809 /* If the previous instruction was in a noreorder section, then
1810 we don't want to insert the nop after all. */
1811 /* Itbl support may require additional care here. */
1812 if (prev_insn_unreordered
)
1815 /* There are two cases which require two intervening
1816 instructions: 1) setting the condition codes using a move to
1817 coprocessor instruction which requires a general coprocessor
1818 delay and then reading the condition codes 2) reading the HI
1819 or LO register and then writing to it (except on processors
1820 which have interlocks). If we are not already emitting a NOP
1821 instruction, we must check for these cases compared to the
1822 instruction previous to the previous instruction. */
1823 if ((! mips_opts
.mips16
1824 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1825 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1826 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1827 && (pinfo
& INSN_READ_COND_CODE
)
1828 && ! cop_interlocks
)
1829 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1830 && (pinfo
& INSN_WRITE_LO
)
1831 && ! (hilo_interlocks
1832 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1833 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1834 && (pinfo
& INSN_WRITE_HI
)
1835 && ! (hilo_interlocks
1836 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1841 if (prev_prev_insn_unreordered
)
1844 if (prev_prev_nop
&& nops
== 0)
1847 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1849 /* We're out of bits in pinfo, so we must resort to string
1850 ops here. Shortcuts are selected based on opcodes being
1851 limited to the VR4122 instruction set. */
1853 const char *pn
= prev_insn
.insn_mo
->name
;
1854 const char *tn
= ip
->insn_mo
->name
;
1855 if (strncmp(pn
, "macc", 4) == 0
1856 || strncmp(pn
, "dmacc", 5) == 0)
1858 /* Errata 21 - [D]DIV[U] after [D]MACC */
1859 if (strstr (tn
, "div"))
1864 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1865 if (pn
[0] == 'd' /* dmacc */
1866 && (strncmp(tn
, "dmult", 5) == 0
1867 || strncmp(tn
, "dmacc", 5) == 0))
1872 /* Errata 24 - MT{LO,HI} after [D]MACC */
1873 if (strcmp (tn
, "mtlo") == 0
1874 || strcmp (tn
, "mthi") == 0)
1880 else if (strncmp(pn
, "dmult", 5) == 0
1881 && (strncmp(tn
, "dmult", 5) == 0
1882 || strncmp(tn
, "dmacc", 5) == 0))
1884 /* Here is the rest of errata 23. */
1887 if (nops
< min_nops
)
1891 /* If we are being given a nop instruction, don't bother with
1892 one of the nops we would otherwise output. This will only
1893 happen when a nop instruction is used with mips_optimize set
1896 && ! mips_opts
.noreorder
1897 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1900 /* Now emit the right number of NOP instructions. */
1901 if (nops
> 0 && ! mips_opts
.noreorder
)
1904 unsigned long old_frag_offset
;
1906 struct insn_label_list
*l
;
1908 old_frag
= frag_now
;
1909 old_frag_offset
= frag_now_fix ();
1911 for (i
= 0; i
< nops
; i
++)
1916 listing_prev_line ();
1917 /* We may be at the start of a variant frag. In case we
1918 are, make sure there is enough space for the frag
1919 after the frags created by listing_prev_line. The
1920 argument to frag_grow here must be at least as large
1921 as the argument to all other calls to frag_grow in
1922 this file. We don't have to worry about being in the
1923 middle of a variant frag, because the variants insert
1924 all needed nop instructions themselves. */
1928 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1932 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1933 symbol_set_frag (l
->label
, frag_now
);
1934 val
= (valueT
) frag_now_fix ();
1935 /* mips16 text labels are stored as odd. */
1936 if (mips_opts
.mips16
)
1938 S_SET_VALUE (l
->label
, val
);
1941 #ifndef NO_ECOFF_DEBUGGING
1942 if (ECOFF_DEBUGGING
)
1943 ecoff_fix_loc (old_frag
, old_frag_offset
);
1946 else if (prev_nop_frag
!= NULL
)
1948 /* We have a frag holding nops we may be able to remove. If
1949 we don't need any nops, we can decrease the size of
1950 prev_nop_frag by the size of one instruction. If we do
1951 need some nops, we count them in prev_nops_required. */
1952 if (prev_nop_frag_since
== 0)
1956 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1957 --prev_nop_frag_holds
;
1960 prev_nop_frag_required
+= nops
;
1964 if (prev_prev_nop
== 0)
1966 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1967 --prev_nop_frag_holds
;
1970 ++prev_nop_frag_required
;
1973 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1974 prev_nop_frag
= NULL
;
1976 ++prev_nop_frag_since
;
1978 /* Sanity check: by the time we reach the second instruction
1979 after prev_nop_frag, we should have used up all the nops
1980 one way or another. */
1981 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1987 && *reloc_type
== BFD_RELOC_16_PCREL_S2
1988 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
1989 || pinfo
& INSN_COND_BRANCH_LIKELY
)
1990 && mips_relax_branch
1991 /* Don't try branch relaxation within .set nomacro, or within
1992 .set noat if we use $at for PIC computations. If it turns
1993 out that the branch was out-of-range, we'll get an error. */
1994 && !mips_opts
.warn_about_macros
1995 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
1996 && !mips_opts
.mips16
)
1998 f
= frag_var (rs_machine_dependent
,
1999 relaxed_branch_length
2001 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2002 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2004 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2005 pinfo
& INSN_COND_BRANCH_LIKELY
,
2006 pinfo
& INSN_WRITE_GPR_31
,
2008 address_expr
->X_add_symbol
,
2009 address_expr
->X_add_number
,
2011 *reloc_type
= BFD_RELOC_UNUSED
;
2013 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2015 /* We need to set up a variant frag. */
2016 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2017 f
= frag_var (rs_machine_dependent
, 4, 0,
2018 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2019 mips16_small
, mips16_ext
,
2021 & INSN_UNCOND_BRANCH_DELAY
),
2022 (*prev_insn_reloc_type
2023 == BFD_RELOC_MIPS16_JMP
)),
2024 make_expr_symbol (address_expr
), 0, NULL
);
2026 else if (place
!= NULL
)
2028 else if (mips_opts
.mips16
2030 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2032 /* Make sure there is enough room to swap this instruction with
2033 a following jump instruction. */
2039 if (mips_opts
.mips16
2040 && mips_opts
.noreorder
2041 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2042 as_warn (_("extended instruction in delay slot"));
2047 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2048 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2050 if (address_expr
->X_op
== O_constant
)
2054 switch (*reloc_type
)
2057 ip
->insn_opcode
|= address_expr
->X_add_number
;
2060 case BFD_RELOC_MIPS_HIGHEST
:
2061 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2063 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2066 case BFD_RELOC_MIPS_HIGHER
:
2067 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2068 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2071 case BFD_RELOC_HI16_S
:
2072 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2076 case BFD_RELOC_HI16
:
2077 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2080 case BFD_RELOC_LO16
:
2081 case BFD_RELOC_MIPS_GOT_DISP
:
2082 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2085 case BFD_RELOC_MIPS_JMP
:
2086 if ((address_expr
->X_add_number
& 3) != 0)
2087 as_bad (_("jump to misaligned address (0x%lx)"),
2088 (unsigned long) address_expr
->X_add_number
);
2089 if (address_expr
->X_add_number
& ~0xfffffff)
2090 as_bad (_("jump address range overflow (0x%lx)"),
2091 (unsigned long) address_expr
->X_add_number
);
2092 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2095 case BFD_RELOC_MIPS16_JMP
:
2096 if ((address_expr
->X_add_number
& 3) != 0)
2097 as_bad (_("jump to misaligned address (0x%lx)"),
2098 (unsigned long) address_expr
->X_add_number
);
2099 if (address_expr
->X_add_number
& ~0xfffffff)
2100 as_bad (_("jump address range overflow (0x%lx)"),
2101 (unsigned long) address_expr
->X_add_number
);
2103 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2104 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2105 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2108 case BFD_RELOC_16_PCREL_S2
:
2118 /* Don't generate a reloc if we are writing into a variant frag. */
2121 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2123 *reloc_type
== BFD_RELOC_16_PCREL_S2
,
2126 /* These relocations can have an addend that won't fit in
2127 4 octets for 64bit assembly. */
2128 if (HAVE_64BIT_GPRS
&&
2129 (*reloc_type
== BFD_RELOC_16
2130 || *reloc_type
== BFD_RELOC_32
2131 || *reloc_type
== BFD_RELOC_MIPS_JMP
2132 || *reloc_type
== BFD_RELOC_HI16_S
2133 || *reloc_type
== BFD_RELOC_LO16
2134 || *reloc_type
== BFD_RELOC_GPREL16
2135 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2136 || *reloc_type
== BFD_RELOC_GPREL32
2137 || *reloc_type
== BFD_RELOC_64
2138 || *reloc_type
== BFD_RELOC_CTOR
2139 || *reloc_type
== BFD_RELOC_MIPS_SUB
2140 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2141 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2142 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2143 || *reloc_type
== BFD_RELOC_MIPS_REL16
2144 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2145 fixp
[0]->fx_no_overflow
= 1;
2147 if (reloc_type
[0] == BFD_RELOC_HI16_S
)
2149 struct mips_hi_fixup
*hi_fixup
;
2151 hi_fixup
= ((struct mips_hi_fixup
*)
2152 xmalloc (sizeof (struct mips_hi_fixup
)));
2153 hi_fixup
->fixp
= fixp
[0];
2154 hi_fixup
->seg
= now_seg
;
2155 hi_fixup
->next
= mips_hi_fixup_list
;
2156 mips_hi_fixup_list
= hi_fixup
;
2157 unmatched_reloc_p
= TRUE
;
2160 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2162 /* FIXME: This symbol can be one of
2163 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2164 address_expr
->X_op
= O_absent
;
2165 address_expr
->X_add_symbol
= 0;
2166 address_expr
->X_add_number
= 0;
2168 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2169 4, address_expr
, FALSE
,
2172 /* These relocations can have an addend that won't fit in
2173 4 octets for 64bit assembly. */
2174 if (HAVE_64BIT_GPRS
&&
2175 (*reloc_type
== BFD_RELOC_16
2176 || *reloc_type
== BFD_RELOC_32
2177 || *reloc_type
== BFD_RELOC_MIPS_JMP
2178 || *reloc_type
== BFD_RELOC_HI16_S
2179 || *reloc_type
== BFD_RELOC_LO16
2180 || *reloc_type
== BFD_RELOC_GPREL16
2181 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2182 || *reloc_type
== BFD_RELOC_GPREL32
2183 || *reloc_type
== BFD_RELOC_64
2184 || *reloc_type
== BFD_RELOC_CTOR
2185 || *reloc_type
== BFD_RELOC_MIPS_SUB
2186 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2187 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2188 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2189 || *reloc_type
== BFD_RELOC_MIPS_REL16
2190 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2191 fixp
[1]->fx_no_overflow
= 1;
2193 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2195 address_expr
->X_op
= O_absent
;
2196 address_expr
->X_add_symbol
= 0;
2197 address_expr
->X_add_number
= 0;
2199 fixp
[2] = fix_new_exp (frag_now
,
2200 f
- frag_now
->fr_literal
, 4,
2201 address_expr
, FALSE
,
2204 /* These relocations can have an addend that won't fit in
2205 4 octets for 64bit assembly. */
2206 if (HAVE_64BIT_GPRS
&&
2207 (*reloc_type
== BFD_RELOC_16
2208 || *reloc_type
== BFD_RELOC_32
2209 || *reloc_type
== BFD_RELOC_MIPS_JMP
2210 || *reloc_type
== BFD_RELOC_HI16_S
2211 || *reloc_type
== BFD_RELOC_LO16
2212 || *reloc_type
== BFD_RELOC_GPREL16
2213 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2214 || *reloc_type
== BFD_RELOC_GPREL32
2215 || *reloc_type
== BFD_RELOC_64
2216 || *reloc_type
== BFD_RELOC_CTOR
2217 || *reloc_type
== BFD_RELOC_MIPS_SUB
2218 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2219 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2220 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2221 || *reloc_type
== BFD_RELOC_MIPS_REL16
2222 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2223 fixp
[2]->fx_no_overflow
= 1;
2230 if (! mips_opts
.mips16
)
2232 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2234 dwarf2_emit_insn (4);
2237 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2239 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2240 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2242 dwarf2_emit_insn (4);
2249 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2252 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2254 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2258 /* Update the register mask information. */
2259 if (! mips_opts
.mips16
)
2261 if (pinfo
& INSN_WRITE_GPR_D
)
2262 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2263 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2264 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2265 if (pinfo
& INSN_READ_GPR_S
)
2266 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2267 if (pinfo
& INSN_WRITE_GPR_31
)
2268 mips_gprmask
|= 1 << RA
;
2269 if (pinfo
& INSN_WRITE_FPR_D
)
2270 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2271 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2272 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2273 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2274 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2275 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2276 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2277 if (pinfo
& INSN_COP
)
2279 /* We don't keep enough information to sort these cases out.
2280 The itbl support does keep this information however, although
2281 we currently don't support itbl fprmats as part of the cop
2282 instruction. May want to add this support in the future. */
2284 /* Never set the bit for $0, which is always zero. */
2285 mips_gprmask
&= ~1 << 0;
2289 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2290 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2291 & MIPS16OP_MASK_RX
);
2292 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2293 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2294 & MIPS16OP_MASK_RY
);
2295 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2296 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2297 & MIPS16OP_MASK_RZ
);
2298 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2299 mips_gprmask
|= 1 << TREG
;
2300 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2301 mips_gprmask
|= 1 << SP
;
2302 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2303 mips_gprmask
|= 1 << RA
;
2304 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2305 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2306 if (pinfo
& MIPS16_INSN_READ_Z
)
2307 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2308 & MIPS16OP_MASK_MOVE32Z
);
2309 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2310 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2311 & MIPS16OP_MASK_REGR32
);
2314 if (place
== NULL
&& ! mips_opts
.noreorder
)
2316 /* Filling the branch delay slot is more complex. We try to
2317 switch the branch with the previous instruction, which we can
2318 do if the previous instruction does not set up a condition
2319 that the branch tests and if the branch is not itself the
2320 target of any branch. */
2321 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2322 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2324 if (mips_optimize
< 2
2325 /* If we have seen .set volatile or .set nomove, don't
2327 || mips_opts
.nomove
!= 0
2328 /* If we had to emit any NOP instructions, then we
2329 already know we can not swap. */
2331 /* If we don't even know the previous insn, we can not
2333 || ! prev_insn_valid
2334 /* If the previous insn is already in a branch delay
2335 slot, then we can not swap. */
2336 || prev_insn_is_delay_slot
2337 /* If the previous previous insn was in a .set
2338 noreorder, we can't swap. Actually, the MIPS
2339 assembler will swap in this situation. However, gcc
2340 configured -with-gnu-as will generate code like
2346 in which we can not swap the bne and INSN. If gcc is
2347 not configured -with-gnu-as, it does not output the
2348 .set pseudo-ops. We don't have to check
2349 prev_insn_unreordered, because prev_insn_valid will
2350 be 0 in that case. We don't want to use
2351 prev_prev_insn_valid, because we do want to be able
2352 to swap at the start of a function. */
2353 || prev_prev_insn_unreordered
2354 /* If the branch is itself the target of a branch, we
2355 can not swap. We cheat on this; all we check for is
2356 whether there is a label on this instruction. If
2357 there are any branches to anything other than a
2358 label, users must use .set noreorder. */
2359 || insn_labels
!= NULL
2360 /* If the previous instruction is in a variant frag, we
2361 can not do the swap. This does not apply to the
2362 mips16, which uses variant frags for different
2364 || (! mips_opts
.mips16
2365 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2366 /* If the branch reads the condition codes, we don't
2367 even try to swap, because in the sequence
2372 we can not swap, and I don't feel like handling that
2374 || (! mips_opts
.mips16
2375 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2376 && (pinfo
& INSN_READ_COND_CODE
))
2377 /* We can not swap with an instruction that requires a
2378 delay slot, becase the target of the branch might
2379 interfere with that instruction. */
2380 || (! mips_opts
.mips16
2381 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2383 /* Itbl support may require additional care here. */
2384 & (INSN_LOAD_COPROC_DELAY
2385 | INSN_COPROC_MOVE_DELAY
2386 | INSN_WRITE_COND_CODE
)))
2387 || (! (hilo_interlocks
2388 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2392 || (! mips_opts
.mips16
2394 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2395 || (! mips_opts
.mips16
2396 && mips_opts
.isa
== ISA_MIPS1
2397 /* Itbl support may require additional care here. */
2398 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2399 /* We can not swap with a branch instruction. */
2401 & (INSN_UNCOND_BRANCH_DELAY
2402 | INSN_COND_BRANCH_DELAY
2403 | INSN_COND_BRANCH_LIKELY
))
2404 /* We do not swap with a trap instruction, since it
2405 complicates trap handlers to have the trap
2406 instruction be in a delay slot. */
2407 || (prev_pinfo
& INSN_TRAP
)
2408 /* If the branch reads a register that the previous
2409 instruction sets, we can not swap. */
2410 || (! mips_opts
.mips16
2411 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2412 && insn_uses_reg (ip
,
2413 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2416 || (! mips_opts
.mips16
2417 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2418 && insn_uses_reg (ip
,
2419 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2422 || (mips_opts
.mips16
2423 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2424 && insn_uses_reg (ip
,
2425 ((prev_insn
.insn_opcode
2427 & MIPS16OP_MASK_RX
),
2429 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2430 && insn_uses_reg (ip
,
2431 ((prev_insn
.insn_opcode
2433 & MIPS16OP_MASK_RY
),
2435 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2436 && insn_uses_reg (ip
,
2437 ((prev_insn
.insn_opcode
2439 & MIPS16OP_MASK_RZ
),
2441 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2442 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2443 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2444 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2445 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2446 && insn_uses_reg (ip
,
2447 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2450 /* If the branch writes a register that the previous
2451 instruction sets, we can not swap (we know that
2452 branches write only to RD or to $31). */
2453 || (! mips_opts
.mips16
2454 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2455 && (((pinfo
& INSN_WRITE_GPR_D
)
2456 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2457 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2458 || ((pinfo
& INSN_WRITE_GPR_31
)
2459 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2462 || (! mips_opts
.mips16
2463 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2464 && (((pinfo
& INSN_WRITE_GPR_D
)
2465 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2466 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2467 || ((pinfo
& INSN_WRITE_GPR_31
)
2468 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2471 || (mips_opts
.mips16
2472 && (pinfo
& MIPS16_INSN_WRITE_31
)
2473 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2474 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2475 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2477 /* If the branch writes a register that the previous
2478 instruction reads, we can not swap (we know that
2479 branches only write to RD or to $31). */
2480 || (! mips_opts
.mips16
2481 && (pinfo
& INSN_WRITE_GPR_D
)
2482 && insn_uses_reg (&prev_insn
,
2483 ((ip
->insn_opcode
>> OP_SH_RD
)
2486 || (! mips_opts
.mips16
2487 && (pinfo
& INSN_WRITE_GPR_31
)
2488 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2489 || (mips_opts
.mips16
2490 && (pinfo
& MIPS16_INSN_WRITE_31
)
2491 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2492 /* If we are generating embedded PIC code, the branch
2493 might be expanded into a sequence which uses $at, so
2494 we can't swap with an instruction which reads it. */
2495 || (mips_pic
== EMBEDDED_PIC
2496 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2497 /* If the previous previous instruction has a load
2498 delay, and sets a register that the branch reads, we
2500 || (! mips_opts
.mips16
2501 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2502 /* Itbl support may require additional care here. */
2503 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2504 || (! gpr_interlocks
2505 && (prev_prev_insn
.insn_mo
->pinfo
2506 & INSN_LOAD_MEMORY_DELAY
)))
2507 && insn_uses_reg (ip
,
2508 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2511 /* If one instruction sets a condition code and the
2512 other one uses a condition code, we can not swap. */
2513 || ((pinfo
& INSN_READ_COND_CODE
)
2514 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2515 || ((pinfo
& INSN_WRITE_COND_CODE
)
2516 && (prev_pinfo
& INSN_READ_COND_CODE
))
2517 /* If the previous instruction uses the PC, we can not
2519 || (mips_opts
.mips16
2520 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2521 /* If the previous instruction was extended, we can not
2523 || (mips_opts
.mips16
&& prev_insn_extended
)
2524 /* If the previous instruction had a fixup in mips16
2525 mode, we can not swap. This normally means that the
2526 previous instruction was a 4 byte branch anyhow. */
2527 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2528 /* If the previous instruction is a sync, sync.l, or
2529 sync.p, we can not swap. */
2530 || (prev_pinfo
& INSN_SYNC
))
2532 /* We could do even better for unconditional branches to
2533 portions of this object file; we could pick up the
2534 instruction at the destination, put it in the delay
2535 slot, and bump the destination address. */
2537 /* Update the previous insn information. */
2538 prev_prev_insn
= *ip
;
2539 prev_insn
.insn_mo
= &dummy_opcode
;
2543 /* It looks like we can actually do the swap. */
2544 if (! mips_opts
.mips16
)
2549 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2550 memcpy (temp
, prev_f
, 4);
2551 memcpy (prev_f
, f
, 4);
2552 memcpy (f
, temp
, 4);
2553 if (prev_insn_fixp
[0])
2555 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2556 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2558 if (prev_insn_fixp
[1])
2560 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2561 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2563 if (prev_insn_fixp
[2])
2565 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2566 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2570 fixp
[0]->fx_frag
= prev_insn_frag
;
2571 fixp
[0]->fx_where
= prev_insn_where
;
2575 fixp
[1]->fx_frag
= prev_insn_frag
;
2576 fixp
[1]->fx_where
= prev_insn_where
;
2580 fixp
[2]->fx_frag
= prev_insn_frag
;
2581 fixp
[2]->fx_where
= prev_insn_where
;
2589 assert (prev_insn_fixp
[0] == NULL
);
2590 assert (prev_insn_fixp
[1] == NULL
);
2591 assert (prev_insn_fixp
[2] == NULL
);
2592 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2593 memcpy (temp
, prev_f
, 2);
2594 memcpy (prev_f
, f
, 2);
2595 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2597 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2598 memcpy (f
, temp
, 2);
2602 memcpy (f
, f
+ 2, 2);
2603 memcpy (f
+ 2, temp
, 2);
2607 fixp
[0]->fx_frag
= prev_insn_frag
;
2608 fixp
[0]->fx_where
= prev_insn_where
;
2612 fixp
[1]->fx_frag
= prev_insn_frag
;
2613 fixp
[1]->fx_where
= prev_insn_where
;
2617 fixp
[2]->fx_frag
= prev_insn_frag
;
2618 fixp
[2]->fx_where
= prev_insn_where
;
2622 /* Update the previous insn information; leave prev_insn
2624 prev_prev_insn
= *ip
;
2626 prev_insn_is_delay_slot
= 1;
2628 /* If that was an unconditional branch, forget the previous
2629 insn information. */
2630 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2632 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2633 prev_insn
.insn_mo
= &dummy_opcode
;
2636 prev_insn_fixp
[0] = NULL
;
2637 prev_insn_fixp
[1] = NULL
;
2638 prev_insn_fixp
[2] = NULL
;
2639 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2640 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2641 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2642 prev_insn_extended
= 0;
2644 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2646 /* We don't yet optimize a branch likely. What we should do
2647 is look at the target, copy the instruction found there
2648 into the delay slot, and increment the branch to jump to
2649 the next instruction. */
2651 /* Update the previous insn information. */
2652 prev_prev_insn
= *ip
;
2653 prev_insn
.insn_mo
= &dummy_opcode
;
2654 prev_insn_fixp
[0] = NULL
;
2655 prev_insn_fixp
[1] = NULL
;
2656 prev_insn_fixp
[2] = NULL
;
2657 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2658 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2659 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2660 prev_insn_extended
= 0;
2664 /* Update the previous insn information. */
2666 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2668 prev_prev_insn
= prev_insn
;
2671 /* Any time we see a branch, we always fill the delay slot
2672 immediately; since this insn is not a branch, we know it
2673 is not in a delay slot. */
2674 prev_insn_is_delay_slot
= 0;
2676 prev_insn_fixp
[0] = fixp
[0];
2677 prev_insn_fixp
[1] = fixp
[1];
2678 prev_insn_fixp
[2] = fixp
[2];
2679 prev_insn_reloc_type
[0] = reloc_type
[0];
2680 prev_insn_reloc_type
[1] = reloc_type
[1];
2681 prev_insn_reloc_type
[2] = reloc_type
[2];
2682 if (mips_opts
.mips16
)
2683 prev_insn_extended
= (ip
->use_extend
2684 || *reloc_type
> BFD_RELOC_UNUSED
);
2687 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2688 prev_insn_unreordered
= 0;
2689 prev_insn_frag
= frag_now
;
2690 prev_insn_where
= f
- frag_now
->fr_literal
;
2691 prev_insn_valid
= 1;
2693 else if (place
== NULL
)
2695 /* We need to record a bit of information even when we are not
2696 reordering, in order to determine the base address for mips16
2697 PC relative relocs. */
2698 prev_prev_insn
= prev_insn
;
2700 prev_insn_reloc_type
[0] = reloc_type
[0];
2701 prev_insn_reloc_type
[1] = reloc_type
[1];
2702 prev_insn_reloc_type
[2] = reloc_type
[2];
2703 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2704 prev_insn_unreordered
= 1;
2707 /* We just output an insn, so the next one doesn't have a label. */
2708 mips_clear_insn_labels ();
2710 /* We must ensure that a fixup associated with an unmatched %hi
2711 reloc does not become a variant frag. Otherwise, the
2712 rearrangement of %hi relocs in frob_file may confuse
2714 if (unmatched_reloc_p
)
2716 frag_wane (frag_now
);
2721 /* This function forgets that there was any previous instruction or
2722 label. If PRESERVE is non-zero, it remembers enough information to
2723 know whether nops are needed before a noreorder section. */
2726 mips_no_prev_insn (preserve
)
2731 prev_insn
.insn_mo
= &dummy_opcode
;
2732 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2733 prev_nop_frag
= NULL
;
2734 prev_nop_frag_holds
= 0;
2735 prev_nop_frag_required
= 0;
2736 prev_nop_frag_since
= 0;
2738 prev_insn_valid
= 0;
2739 prev_insn_is_delay_slot
= 0;
2740 prev_insn_unreordered
= 0;
2741 prev_insn_extended
= 0;
2742 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2743 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2744 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2745 prev_prev_insn_unreordered
= 0;
2746 mips_clear_insn_labels ();
2749 /* This function must be called whenever we turn on noreorder or emit
2750 something other than instructions. It inserts any NOPS which might
2751 be needed by the previous instruction, and clears the information
2752 kept for the previous instructions. The INSNS parameter is true if
2753 instructions are to follow. */
2756 mips_emit_delays (insns
)
2759 if (! mips_opts
.noreorder
)
2764 if ((! mips_opts
.mips16
2765 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2766 && (! cop_interlocks
2767 && (prev_insn
.insn_mo
->pinfo
2768 & (INSN_LOAD_COPROC_DELAY
2769 | INSN_COPROC_MOVE_DELAY
2770 | INSN_WRITE_COND_CODE
))))
2771 || (! hilo_interlocks
2772 && (prev_insn
.insn_mo
->pinfo
2775 || (! mips_opts
.mips16
2777 && (prev_insn
.insn_mo
->pinfo
2778 & INSN_LOAD_MEMORY_DELAY
))
2779 || (! mips_opts
.mips16
2780 && mips_opts
.isa
== ISA_MIPS1
2781 && (prev_insn
.insn_mo
->pinfo
2782 & INSN_COPROC_MEMORY_DELAY
)))
2784 /* Itbl support may require additional care here. */
2786 if ((! mips_opts
.mips16
2787 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2788 && (! cop_interlocks
2789 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2790 || (! hilo_interlocks
2791 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2792 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2795 if (prev_insn_unreordered
)
2798 else if ((! mips_opts
.mips16
2799 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2800 && (! cop_interlocks
2801 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2802 || (! hilo_interlocks
2803 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2804 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2806 /* Itbl support may require additional care here. */
2807 if (! prev_prev_insn_unreordered
)
2811 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2814 const char *pn
= prev_insn
.insn_mo
->name
;
2815 if (strncmp(pn
, "macc", 4) == 0
2816 || strncmp(pn
, "dmacc", 5) == 0
2817 || strncmp(pn
, "dmult", 5) == 0)
2821 if (nops
< min_nops
)
2827 struct insn_label_list
*l
;
2831 /* Record the frag which holds the nop instructions, so
2832 that we can remove them if we don't need them. */
2833 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2834 prev_nop_frag
= frag_now
;
2835 prev_nop_frag_holds
= nops
;
2836 prev_nop_frag_required
= 0;
2837 prev_nop_frag_since
= 0;
2840 for (; nops
> 0; --nops
)
2845 /* Move on to a new frag, so that it is safe to simply
2846 decrease the size of prev_nop_frag. */
2847 frag_wane (frag_now
);
2851 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2855 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2856 symbol_set_frag (l
->label
, frag_now
);
2857 val
= (valueT
) frag_now_fix ();
2858 /* mips16 text labels are stored as odd. */
2859 if (mips_opts
.mips16
)
2861 S_SET_VALUE (l
->label
, val
);
2866 /* Mark instruction labels in mips16 mode. */
2868 mips16_mark_labels ();
2870 mips_no_prev_insn (insns
);
2873 /* Build an instruction created by a macro expansion. This is passed
2874 a pointer to the count of instructions created so far, an
2875 expression, the name of the instruction to build, an operand format
2876 string, and corresponding arguments. */
2880 macro_build (char *place
,
2888 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2897 struct mips_cl_insn insn
;
2898 bfd_reloc_code_real_type r
[3];
2902 va_start (args
, fmt
);
2908 * If the macro is about to expand into a second instruction,
2909 * print a warning if needed. We need to pass ip as a parameter
2910 * to generate a better warning message here...
2912 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2913 as_warn (_("Macro instruction expanded into multiple instructions"));
2916 * If the macro is about to expand into a second instruction,
2917 * and it is in a delay slot, print a warning.
2921 && mips_opts
.noreorder
2922 && (prev_prev_insn
.insn_mo
->pinfo
2923 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2924 | INSN_COND_BRANCH_LIKELY
)) != 0)
2925 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2928 ++*counter
; /* bump instruction counter */
2930 if (mips_opts
.mips16
)
2932 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2937 r
[0] = BFD_RELOC_UNUSED
;
2938 r
[1] = BFD_RELOC_UNUSED
;
2939 r
[2] = BFD_RELOC_UNUSED
;
2940 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2941 assert (insn
.insn_mo
);
2942 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2944 /* Search until we get a match for NAME. */
2947 /* It is assumed here that macros will never generate
2948 MDMX or MIPS-3D instructions. */
2949 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2950 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2951 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2953 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2955 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2959 assert (insn
.insn_mo
->name
);
2960 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2963 insn
.insn_opcode
= insn
.insn_mo
->match
;
2979 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2983 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2988 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2994 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2999 int tmp
= va_arg (args
, int);
3001 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3002 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3008 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3015 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3019 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3023 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3027 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3031 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3038 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3044 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3045 assert (*r
== BFD_RELOC_GPREL16
3046 || *r
== BFD_RELOC_MIPS_LITERAL
3047 || *r
== BFD_RELOC_MIPS_HIGHER
3048 || *r
== BFD_RELOC_HI16_S
3049 || *r
== BFD_RELOC_LO16
3050 || *r
== BFD_RELOC_MIPS_GOT16
3051 || *r
== BFD_RELOC_MIPS_CALL16
3052 || *r
== BFD_RELOC_MIPS_GOT_DISP
3053 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3054 || *r
== BFD_RELOC_MIPS_GOT_OFST
3055 || *r
== BFD_RELOC_MIPS_GOT_LO16
3056 || *r
== BFD_RELOC_MIPS_CALL_LO16
3057 || (ep
->X_op
== O_subtract
3058 && *r
== BFD_RELOC_PCREL_LO16
));
3062 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3064 && (ep
->X_op
== O_constant
3065 || (ep
->X_op
== O_symbol
3066 && (*r
== BFD_RELOC_MIPS_HIGHEST
3067 || *r
== BFD_RELOC_HI16_S
3068 || *r
== BFD_RELOC_HI16
3069 || *r
== BFD_RELOC_GPREL16
3070 || *r
== BFD_RELOC_MIPS_GOT_HI16
3071 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3072 || (ep
->X_op
== O_subtract
3073 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3077 assert (ep
!= NULL
);
3079 * This allows macro() to pass an immediate expression for
3080 * creating short branches without creating a symbol.
3081 * Note that the expression still might come from the assembly
3082 * input, in which case the value is not checked for range nor
3083 * is a relocation entry generated (yuck).
3085 if (ep
->X_op
== O_constant
)
3087 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3091 *r
= BFD_RELOC_16_PCREL_S2
;
3095 assert (ep
!= NULL
);
3096 *r
= BFD_RELOC_MIPS_JMP
;
3100 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3109 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3111 append_insn (place
, &insn
, ep
, r
);
3115 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3117 int *counter ATTRIBUTE_UNUSED
;
3123 struct mips_cl_insn insn
;
3124 bfd_reloc_code_real_type r
[3]
3125 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3127 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3128 assert (insn
.insn_mo
);
3129 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3131 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3132 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3135 assert (insn
.insn_mo
->name
);
3136 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3139 insn
.insn_opcode
= insn
.insn_mo
->match
;
3140 insn
.use_extend
= FALSE
;
3159 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3164 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3168 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3172 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3182 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3189 regno
= va_arg (args
, int);
3190 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3191 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3212 assert (ep
!= NULL
);
3214 if (ep
->X_op
!= O_constant
)
3215 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3218 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3219 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3222 *r
= BFD_RELOC_UNUSED
;
3228 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3235 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3237 append_insn (place
, &insn
, ep
, r
);
3241 * Generate a "jalr" instruction with a relocation hint to the called
3242 * function. This occurs in NewABI PIC code.
3245 macro_build_jalr (icnt
, ep
)
3256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3259 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3260 0, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3264 * Generate a "lui" instruction.
3267 macro_build_lui (place
, counter
, ep
, regnum
)
3273 expressionS high_expr
;
3274 struct mips_cl_insn insn
;
3275 bfd_reloc_code_real_type r
[3]
3276 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3277 const char *name
= "lui";
3278 const char *fmt
= "t,u";
3280 assert (! mips_opts
.mips16
);
3286 high_expr
.X_op
= O_constant
;
3287 high_expr
.X_add_number
= ep
->X_add_number
;
3290 if (high_expr
.X_op
== O_constant
)
3292 /* we can compute the instruction now without a relocation entry */
3293 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3295 *r
= BFD_RELOC_UNUSED
;
3299 assert (ep
->X_op
== O_symbol
);
3300 /* _gp_disp is a special case, used from s_cpload. */
3301 assert (mips_pic
== NO_PIC
3303 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3304 *r
= BFD_RELOC_HI16_S
;
3308 * If the macro is about to expand into a second instruction,
3309 * print a warning if needed. We need to pass ip as a parameter
3310 * to generate a better warning message here...
3312 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3313 as_warn (_("Macro instruction expanded into multiple instructions"));
3316 ++*counter
; /* bump instruction counter */
3318 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3319 assert (insn
.insn_mo
);
3320 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3321 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3323 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3324 if (*r
== BFD_RELOC_UNUSED
)
3326 insn
.insn_opcode
|= high_expr
.X_add_number
;
3327 append_insn (place
, &insn
, NULL
, r
);
3330 append_insn (place
, &insn
, &high_expr
, r
);
3333 /* Generate a sequence of instructions to do a load or store from a constant
3334 offset off of a base register (breg) into/from a target register (treg),
3335 using AT if necessary. */
3337 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3344 assert (ep
->X_op
== O_constant
);
3346 /* Right now, this routine can only handle signed 32-bit contants. */
3347 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3348 as_warn (_("operand overflow"));
3350 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3352 /* Signed 16-bit offset will fit in the op. Easy! */
3353 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3354 (int) BFD_RELOC_LO16
, breg
);
3358 /* 32-bit offset, need multiple instructions and AT, like:
3359 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3360 addu $tempreg,$tempreg,$breg
3361 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3362 to handle the complete offset. */
3363 macro_build_lui (place
, counter
, ep
, AT
);
3366 macro_build (place
, counter
, (expressionS
*) NULL
,
3367 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3368 "d,v,t", AT
, AT
, breg
);
3371 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3372 (int) BFD_RELOC_LO16
, AT
);
3375 as_warn (_("Macro used $at after \".set noat\""));
3380 * Generates code to set the $at register to true (one)
3381 * if reg is less than the immediate expression.
3384 set_at (counter
, reg
, unsignedp
)
3389 if (imm_expr
.X_op
== O_constant
3390 && imm_expr
.X_add_number
>= -0x8000
3391 && imm_expr
.X_add_number
< 0x8000)
3392 macro_build ((char *) NULL
, counter
, &imm_expr
,
3393 unsignedp
? "sltiu" : "slti",
3394 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3397 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3398 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3399 unsignedp
? "sltu" : "slt",
3400 "d,v,t", AT
, reg
, AT
);
3404 /* Warn if an expression is not a constant. */
3407 check_absolute_expr (ip
, ex
)
3408 struct mips_cl_insn
*ip
;
3411 if (ex
->X_op
== O_big
)
3412 as_bad (_("unsupported large constant"));
3413 else if (ex
->X_op
!= O_constant
)
3414 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3417 /* Count the leading zeroes by performing a binary chop. This is a
3418 bulky bit of source, but performance is a LOT better for the
3419 majority of values than a simple loop to count the bits:
3420 for (lcnt = 0; (lcnt < 32); lcnt++)
3421 if ((v) & (1 << (31 - lcnt)))
3423 However it is not code size friendly, and the gain will drop a bit
3424 on certain cached systems.
3426 #define COUNT_TOP_ZEROES(v) \
3427 (((v) & ~0xffff) == 0 \
3428 ? ((v) & ~0xff) == 0 \
3429 ? ((v) & ~0xf) == 0 \
3430 ? ((v) & ~0x3) == 0 \
3431 ? ((v) & ~0x1) == 0 \
3436 : ((v) & ~0x7) == 0 \
3439 : ((v) & ~0x3f) == 0 \
3440 ? ((v) & ~0x1f) == 0 \
3443 : ((v) & ~0x7f) == 0 \
3446 : ((v) & ~0xfff) == 0 \
3447 ? ((v) & ~0x3ff) == 0 \
3448 ? ((v) & ~0x1ff) == 0 \
3451 : ((v) & ~0x7ff) == 0 \
3454 : ((v) & ~0x3fff) == 0 \
3455 ? ((v) & ~0x1fff) == 0 \
3458 : ((v) & ~0x7fff) == 0 \
3461 : ((v) & ~0xffffff) == 0 \
3462 ? ((v) & ~0xfffff) == 0 \
3463 ? ((v) & ~0x3ffff) == 0 \
3464 ? ((v) & ~0x1ffff) == 0 \
3467 : ((v) & ~0x7ffff) == 0 \
3470 : ((v) & ~0x3fffff) == 0 \
3471 ? ((v) & ~0x1fffff) == 0 \
3474 : ((v) & ~0x7fffff) == 0 \
3477 : ((v) & ~0xfffffff) == 0 \
3478 ? ((v) & ~0x3ffffff) == 0 \
3479 ? ((v) & ~0x1ffffff) == 0 \
3482 : ((v) & ~0x7ffffff) == 0 \
3485 : ((v) & ~0x3fffffff) == 0 \
3486 ? ((v) & ~0x1fffffff) == 0 \
3489 : ((v) & ~0x7fffffff) == 0 \
3494 * This routine generates the least number of instructions neccessary to load
3495 * an absolute expression value into a register.
3498 load_register (counter
, reg
, ep
, dbl
)
3505 expressionS hi32
, lo32
;
3507 if (ep
->X_op
!= O_big
)
3509 assert (ep
->X_op
== O_constant
);
3510 if (ep
->X_add_number
< 0x8000
3511 && (ep
->X_add_number
>= 0
3512 || (ep
->X_add_number
>= -0x8000
3515 || sizeof (ep
->X_add_number
) > 4))))
3517 /* We can handle 16 bit signed values with an addiu to
3518 $zero. No need to ever use daddiu here, since $zero and
3519 the result are always correct in 32 bit mode. */
3520 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3521 (int) BFD_RELOC_LO16
);
3524 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3526 /* We can handle 16 bit unsigned values with an ori to
3528 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3529 (int) BFD_RELOC_LO16
);
3532 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3535 || sizeof (ep
->X_add_number
) > 4
3536 || (ep
->X_add_number
& 0x80000000) == 0))
3537 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3538 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3541 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3542 == ~ (offsetT
) 0xffffffff)))
3544 /* 32 bit values require an lui. */
3545 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3546 (int) BFD_RELOC_HI16
);
3547 if ((ep
->X_add_number
& 0xffff) != 0)
3548 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3549 (int) BFD_RELOC_LO16
);
3554 /* The value is larger than 32 bits. */
3556 if (HAVE_32BIT_GPRS
)
3558 as_bad (_("Number (0x%lx) larger than 32 bits"),
3559 (unsigned long) ep
->X_add_number
);
3560 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3561 (int) BFD_RELOC_LO16
);
3565 if (ep
->X_op
!= O_big
)
3568 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3569 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3570 hi32
.X_add_number
&= 0xffffffff;
3572 lo32
.X_add_number
&= 0xffffffff;
3576 assert (ep
->X_add_number
> 2);
3577 if (ep
->X_add_number
== 3)
3578 generic_bignum
[3] = 0;
3579 else if (ep
->X_add_number
> 4)
3580 as_bad (_("Number larger than 64 bits"));
3581 lo32
.X_op
= O_constant
;
3582 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3583 hi32
.X_op
= O_constant
;
3584 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3587 if (hi32
.X_add_number
== 0)
3592 unsigned long hi
, lo
;
3594 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3596 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3598 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3599 reg
, 0, (int) BFD_RELOC_LO16
);
3602 if (lo32
.X_add_number
& 0x80000000)
3604 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3605 (int) BFD_RELOC_HI16
);
3606 if (lo32
.X_add_number
& 0xffff)
3607 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3608 reg
, reg
, (int) BFD_RELOC_LO16
);
3613 /* Check for 16bit shifted constant. We know that hi32 is
3614 non-zero, so start the mask on the first bit of the hi32
3619 unsigned long himask
, lomask
;
3623 himask
= 0xffff >> (32 - shift
);
3624 lomask
= (0xffff << shift
) & 0xffffffff;
3628 himask
= 0xffff << (shift
- 32);
3631 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3632 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3636 tmp
.X_op
= O_constant
;
3638 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3639 | (lo32
.X_add_number
>> shift
));
3641 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3642 macro_build ((char *) NULL
, counter
, &tmp
,
3643 "ori", "t,r,i", reg
, 0,
3644 (int) BFD_RELOC_LO16
);
3645 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3646 (shift
>= 32) ? "dsll32" : "dsll",
3648 (shift
>= 32) ? shift
- 32 : shift
);
3653 while (shift
<= (64 - 16));
3655 /* Find the bit number of the lowest one bit, and store the
3656 shifted value in hi/lo. */
3657 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3658 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3662 while ((lo
& 1) == 0)
3667 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3673 while ((hi
& 1) == 0)
3682 /* Optimize if the shifted value is a (power of 2) - 1. */
3683 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3684 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3686 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3691 /* This instruction will set the register to be all
3693 tmp
.X_op
= O_constant
;
3694 tmp
.X_add_number
= (offsetT
) -1;
3695 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3696 reg
, 0, (int) BFD_RELOC_LO16
);
3700 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3701 (bit
>= 32) ? "dsll32" : "dsll",
3703 (bit
>= 32) ? bit
- 32 : bit
);
3705 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3706 (shift
>= 32) ? "dsrl32" : "dsrl",
3708 (shift
>= 32) ? shift
- 32 : shift
);
3713 /* Sign extend hi32 before calling load_register, because we can
3714 generally get better code when we load a sign extended value. */
3715 if ((hi32
.X_add_number
& 0x80000000) != 0)
3716 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3717 load_register (counter
, reg
, &hi32
, 0);
3720 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3724 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3725 "dsll32", "d,w,<", reg
, freg
, 0);
3733 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3735 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3736 (int) BFD_RELOC_HI16
);
3737 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3738 "dsrl32", "d,w,<", reg
, reg
, 0);
3744 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3745 "d,w,<", reg
, freg
, 16);
3749 mid16
.X_add_number
>>= 16;
3750 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3751 freg
, (int) BFD_RELOC_LO16
);
3752 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3753 "d,w,<", reg
, reg
, 16);
3756 if ((lo32
.X_add_number
& 0xffff) != 0)
3757 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3758 (int) BFD_RELOC_LO16
);
3761 /* Load an address into a register. */
3764 load_address (counter
, reg
, ep
, used_at
)
3772 if (ep
->X_op
!= O_constant
3773 && ep
->X_op
!= O_symbol
)
3775 as_bad (_("expression too complex"));
3776 ep
->X_op
= O_constant
;
3779 if (ep
->X_op
== O_constant
)
3781 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3785 if (mips_pic
== NO_PIC
)
3787 /* If this is a reference to a GP relative symbol, we want
3788 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3790 lui $reg,<sym> (BFD_RELOC_HI16_S)
3791 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3792 If we have an addend, we always use the latter form.
3794 With 64bit address space and a usable $at we want
3795 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3796 lui $at,<sym> (BFD_RELOC_HI16_S)
3797 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3798 daddiu $at,<sym> (BFD_RELOC_LO16)
3802 If $at is already in use, we use a path which is suboptimal
3803 on superscalar processors.
3804 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3805 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3807 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3809 daddiu $reg,<sym> (BFD_RELOC_LO16)
3811 if (HAVE_64BIT_ADDRESSES
)
3813 /* We don't do GP optimization for now because RELAX_ENCODE can't
3814 hold the data for such large chunks. */
3816 if (*used_at
== 0 && ! mips_opts
.noat
)
3818 macro_build (p
, counter
, ep
, "lui", "t,u",
3819 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3820 macro_build (p
, counter
, ep
, "lui", "t,u",
3821 AT
, (int) BFD_RELOC_HI16_S
);
3822 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3823 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3824 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3825 AT
, AT
, (int) BFD_RELOC_LO16
);
3826 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3827 "d,w,<", reg
, reg
, 0);
3828 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3829 "d,v,t", reg
, reg
, AT
);
3834 macro_build (p
, counter
, ep
, "lui", "t,u",
3835 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3836 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3837 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3838 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3839 "d,w,<", reg
, reg
, 16);
3840 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3841 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3842 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3843 "d,w,<", reg
, reg
, 16);
3844 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3845 reg
, reg
, (int) BFD_RELOC_LO16
);
3850 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3851 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3854 macro_build ((char *) NULL
, counter
, ep
,
3855 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3856 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3857 p
= frag_var (rs_machine_dependent
, 8, 0,
3858 RELAX_ENCODE (4, 8, 0, 4, 0,
3859 mips_opts
.warn_about_macros
),
3860 ep
->X_add_symbol
, 0, NULL
);
3862 macro_build_lui (p
, counter
, ep
, reg
);
3865 macro_build (p
, counter
, ep
,
3866 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3867 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3870 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3874 /* If this is a reference to an external symbol, we want
3875 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3877 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3879 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3880 If we have NewABI, we want
3881 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3882 If there is a constant, it must be added in after. */
3883 ex
.X_add_number
= ep
->X_add_number
;
3884 ep
->X_add_number
= 0;
3888 macro_build ((char *) NULL
, counter
, ep
,
3889 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3890 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3894 macro_build ((char *) NULL
, counter
, ep
,
3895 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3896 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3897 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3898 p
= frag_var (rs_machine_dependent
, 4, 0,
3899 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3900 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3901 macro_build (p
, counter
, ep
,
3902 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3903 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3906 if (ex
.X_add_number
!= 0)
3908 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3909 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3910 ex
.X_op
= O_constant
;
3911 macro_build ((char *) NULL
, counter
, &ex
,
3912 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3913 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3916 else if (mips_pic
== SVR4_PIC
)
3921 /* This is the large GOT case. If this is a reference to an
3922 external symbol, we want
3923 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3925 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3926 Otherwise, for a reference to a local symbol, we want
3927 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3929 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3930 If we have NewABI, we want
3931 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3932 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3933 If there is a constant, it must be added in after. */
3934 ex
.X_add_number
= ep
->X_add_number
;
3935 ep
->X_add_number
= 0;
3938 macro_build ((char *) NULL
, counter
, ep
,
3939 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3940 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3941 macro_build (p
, counter
, ep
,
3942 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3943 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3947 if (reg_needs_delay (mips_gp_register
))
3952 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3953 (int) BFD_RELOC_MIPS_GOT_HI16
);
3954 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3955 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3956 reg
, mips_gp_register
);
3957 macro_build ((char *) NULL
, counter
, ep
,
3958 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3959 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3960 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3961 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3962 mips_opts
.warn_about_macros
),
3963 ep
->X_add_symbol
, 0, NULL
);
3966 /* We need a nop before loading from $gp. This special
3967 check is required because the lui which starts the main
3968 instruction stream does not refer to $gp, and so will not
3969 insert the nop which may be required. */
3970 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3973 macro_build (p
, counter
, ep
,
3974 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3975 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3977 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3979 macro_build (p
, counter
, ep
,
3980 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3981 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3984 if (ex
.X_add_number
!= 0)
3986 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3987 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3988 ex
.X_op
= O_constant
;
3989 macro_build ((char *) NULL
, counter
, &ex
,
3990 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3991 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3994 else if (mips_pic
== EMBEDDED_PIC
)
3997 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3999 macro_build ((char *) NULL
, counter
, ep
,
4000 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4001 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4007 /* Move the contents of register SOURCE into register DEST. */
4010 move_register (counter
, dest
, source
)
4015 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4016 HAVE_32BIT_GPRS
? "addu" : "daddu",
4017 "d,v,t", dest
, source
, 0);
4022 * This routine implements the seemingly endless macro or synthesized
4023 * instructions and addressing modes in the mips assembly language. Many
4024 * of these macros are simple and are similar to each other. These could
4025 * probably be handled by some kind of table or grammer aproach instead of
4026 * this verbose method. Others are not simple macros but are more like
4027 * optimizing code generation.
4028 * One interesting optimization is when several store macros appear
4029 * consecutivly that would load AT with the upper half of the same address.
4030 * The ensuing load upper instructions are ommited. This implies some kind
4031 * of global optimization. We currently only optimize within a single macro.
4032 * For many of the load and store macros if the address is specified as a
4033 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4034 * first load register 'at' with zero and use it as the base register. The
4035 * mips assembler simply uses register $zero. Just one tiny optimization
4040 struct mips_cl_insn
*ip
;
4042 register int treg
, sreg
, dreg
, breg
;
4058 bfd_reloc_code_real_type r
;
4059 int hold_mips_optimize
;
4061 assert (! mips_opts
.mips16
);
4063 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4064 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4065 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4066 mask
= ip
->insn_mo
->mask
;
4068 expr1
.X_op
= O_constant
;
4069 expr1
.X_op_symbol
= NULL
;
4070 expr1
.X_add_symbol
= NULL
;
4071 expr1
.X_add_number
= 1;
4083 mips_emit_delays (TRUE
);
4084 ++mips_opts
.noreorder
;
4085 mips_any_noreorder
= 1;
4087 expr1
.X_add_number
= 8;
4088 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4093 move_register (&icnt
, dreg
, sreg
);
4094 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4095 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4097 --mips_opts
.noreorder
;
4118 if (imm_expr
.X_op
== O_constant
4119 && imm_expr
.X_add_number
>= -0x8000
4120 && imm_expr
.X_add_number
< 0x8000)
4122 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4123 (int) BFD_RELOC_LO16
);
4126 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4127 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4147 if (imm_expr
.X_op
== O_constant
4148 && imm_expr
.X_add_number
>= 0
4149 && imm_expr
.X_add_number
< 0x10000)
4151 if (mask
!= M_NOR_I
)
4152 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4153 sreg
, (int) BFD_RELOC_LO16
);
4156 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4157 treg
, sreg
, (int) BFD_RELOC_LO16
);
4158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4159 "d,v,t", treg
, treg
, 0);
4164 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4165 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4183 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4185 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4189 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4199 likely
? "bgezl" : "bgez", "s,p", sreg
);
4204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4205 likely
? "blezl" : "blez", "s,p", treg
);
4208 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4210 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4211 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4217 /* check for > max integer */
4218 maxnum
= 0x7fffffff;
4219 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4226 if (imm_expr
.X_op
== O_constant
4227 && imm_expr
.X_add_number
>= maxnum
4228 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4231 /* result is always false */
4235 as_warn (_("Branch %s is always false (nop)"),
4237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4243 as_warn (_("Branch likely %s is always false"),
4245 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4250 if (imm_expr
.X_op
!= O_constant
)
4251 as_bad (_("Unsupported large constant"));
4252 ++imm_expr
.X_add_number
;
4256 if (mask
== M_BGEL_I
)
4258 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4261 likely
? "bgezl" : "bgez", "s,p", sreg
);
4264 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4266 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4267 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4270 maxnum
= 0x7fffffff;
4271 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4278 maxnum
= - maxnum
- 1;
4279 if (imm_expr
.X_op
== O_constant
4280 && imm_expr
.X_add_number
<= maxnum
4281 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4284 /* result is always true */
4285 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4289 set_at (&icnt
, sreg
, 0);
4290 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4291 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4302 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4306 "d,v,t", AT
, sreg
, treg
);
4307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4308 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4316 && imm_expr
.X_op
== O_constant
4317 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4319 if (imm_expr
.X_op
!= O_constant
)
4320 as_bad (_("Unsupported large constant"));
4321 ++imm_expr
.X_add_number
;
4325 if (mask
== M_BGEUL_I
)
4327 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4329 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4332 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4335 set_at (&icnt
, sreg
, 1);
4336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4337 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4346 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4351 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4352 likely
? "bltzl" : "bltz", "s,p", treg
);
4355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4357 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4358 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4367 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4373 "d,v,t", AT
, treg
, sreg
);
4374 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4375 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4383 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4384 likely
? "blezl" : "blez", "s,p", sreg
);
4389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4390 likely
? "bgezl" : "bgez", "s,p", treg
);
4393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4396 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4402 maxnum
= 0x7fffffff;
4403 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4410 if (imm_expr
.X_op
== O_constant
4411 && imm_expr
.X_add_number
>= maxnum
4412 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4414 if (imm_expr
.X_op
!= O_constant
)
4415 as_bad (_("Unsupported large constant"));
4416 ++imm_expr
.X_add_number
;
4420 if (mask
== M_BLTL_I
)
4422 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4425 likely
? "bltzl" : "bltz", "s,p", sreg
);
4428 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4431 likely
? "blezl" : "blez", "s,p", sreg
);
4434 set_at (&icnt
, sreg
, 0);
4435 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4436 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4445 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4451 "d,v,t", AT
, treg
, sreg
);
4452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4453 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4461 && imm_expr
.X_op
== O_constant
4462 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4464 if (imm_expr
.X_op
!= O_constant
)
4465 as_bad (_("Unsupported large constant"));
4466 ++imm_expr
.X_add_number
;
4470 if (mask
== M_BLTUL_I
)
4472 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4474 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 likely
? "beql" : "beq",
4481 set_at (&icnt
, sreg
, 1);
4482 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4483 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4492 likely
? "bltzl" : "bltz", "s,p", sreg
);
4497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4498 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4504 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4514 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4515 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4522 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4537 as_warn (_("Divide by zero."));
4539 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4547 mips_emit_delays (TRUE
);
4548 ++mips_opts
.noreorder
;
4549 mips_any_noreorder
= 1;
4552 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4553 "s,t,q", treg
, 0, 7);
4554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4555 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4559 expr1
.X_add_number
= 8;
4560 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4562 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4566 expr1
.X_add_number
= -1;
4567 macro_build ((char *) NULL
, &icnt
, &expr1
,
4568 dbl
? "daddiu" : "addiu",
4569 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4570 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4571 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4574 expr1
.X_add_number
= 1;
4575 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4576 (int) BFD_RELOC_LO16
);
4577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4578 "d,w,<", AT
, AT
, 31);
4582 expr1
.X_add_number
= 0x80000000;
4583 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4584 (int) BFD_RELOC_HI16
);
4588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4589 "s,t,q", sreg
, AT
, 6);
4590 /* We want to close the noreorder block as soon as possible, so
4591 that later insns are available for delay slot filling. */
4592 --mips_opts
.noreorder
;
4596 expr1
.X_add_number
= 8;
4597 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4601 /* We want to close the noreorder block as soon as possible, so
4602 that later insns are available for delay slot filling. */
4603 --mips_opts
.noreorder
;
4605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4647 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4649 as_warn (_("Divide by zero."));
4651 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4658 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4660 if (strcmp (s2
, "mflo") == 0)
4661 move_register (&icnt
, dreg
, sreg
);
4663 move_register (&icnt
, dreg
, 0);
4666 if (imm_expr
.X_op
== O_constant
4667 && imm_expr
.X_add_number
== -1
4668 && s
[strlen (s
) - 1] != 'u')
4670 if (strcmp (s2
, "mflo") == 0)
4672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4673 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4676 move_register (&icnt
, dreg
, 0);
4680 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4702 mips_emit_delays (TRUE
);
4703 ++mips_opts
.noreorder
;
4704 mips_any_noreorder
= 1;
4707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4708 "s,t,q", treg
, 0, 7);
4709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4711 /* We want to close the noreorder block as soon as possible, so
4712 that later insns are available for delay slot filling. */
4713 --mips_opts
.noreorder
;
4717 expr1
.X_add_number
= 8;
4718 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4719 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4722 /* We want to close the noreorder block as soon as possible, so
4723 that later insns are available for delay slot filling. */
4724 --mips_opts
.noreorder
;
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4734 /* Load the address of a symbol into a register. If breg is not
4735 zero, we then add a base register to it. */
4737 if (dbl
&& HAVE_32BIT_GPRS
)
4738 as_warn (_("dla used to load 32-bit register"));
4740 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4741 as_warn (_("la used to load 64-bit address"));
4743 if (offset_expr
.X_op
== O_constant
4744 && offset_expr
.X_add_number
>= -0x8000
4745 && offset_expr
.X_add_number
< 0x8000)
4747 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4748 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4749 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4764 /* When generating embedded PIC code, we permit expressions of
4767 la $treg,foo-bar($breg)
4768 where bar is an address in the current section. These are used
4769 when getting the addresses of functions. We don't permit
4770 X_add_number to be non-zero, because if the symbol is
4771 external the relaxing code needs to know that any addend is
4772 purely the offset to X_op_symbol. */
4773 if (mips_pic
== EMBEDDED_PIC
4774 && offset_expr
.X_op
== O_subtract
4775 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4776 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4777 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4779 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4782 && (offset_expr
.X_add_number
== 0
4783 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4790 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4794 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4795 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4796 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4797 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4798 "d,v,t", tempreg
, tempreg
, breg
);
4800 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4801 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4802 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4808 if (offset_expr
.X_op
!= O_symbol
4809 && offset_expr
.X_op
!= O_constant
)
4811 as_bad (_("expression too complex"));
4812 offset_expr
.X_op
= O_constant
;
4815 if (offset_expr
.X_op
== O_constant
)
4816 load_register (&icnt
, tempreg
, &offset_expr
,
4817 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4818 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4819 : HAVE_64BIT_ADDRESSES
));
4820 else if (mips_pic
== NO_PIC
)
4822 /* If this is a reference to a GP relative symbol, we want
4823 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4825 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4826 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4827 If we have a constant, we need two instructions anyhow,
4828 so we may as well always use the latter form.
4830 With 64bit address space and a usable $at we want
4831 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4832 lui $at,<sym> (BFD_RELOC_HI16_S)
4833 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4834 daddiu $at,<sym> (BFD_RELOC_LO16)
4836 daddu $tempreg,$tempreg,$at
4838 If $at is already in use, we use a path which is suboptimal
4839 on superscalar processors.
4840 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4841 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4843 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4845 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4848 if (HAVE_64BIT_ADDRESSES
)
4850 /* We don't do GP optimization for now because RELAX_ENCODE can't
4851 hold the data for such large chunks. */
4853 if (used_at
== 0 && ! mips_opts
.noat
)
4855 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4856 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4857 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4858 AT
, (int) BFD_RELOC_HI16_S
);
4859 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4860 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4861 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4862 AT
, AT
, (int) BFD_RELOC_LO16
);
4863 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4864 "d,w,<", tempreg
, tempreg
, 0);
4865 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4866 "d,v,t", tempreg
, tempreg
, AT
);
4871 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4872 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4873 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4874 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4875 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4876 tempreg
, tempreg
, 16);
4877 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4878 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4879 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4880 tempreg
, tempreg
, 16);
4881 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4882 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4887 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4888 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4891 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4892 "t,r,j", tempreg
, mips_gp_register
,
4893 (int) BFD_RELOC_GPREL16
);
4894 p
= frag_var (rs_machine_dependent
, 8, 0,
4895 RELAX_ENCODE (4, 8, 0, 4, 0,
4896 mips_opts
.warn_about_macros
),
4897 offset_expr
.X_add_symbol
, 0, NULL
);
4899 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4902 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4903 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4906 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4908 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4910 /* If this is a reference to an external symbol, and there
4911 is no constant, we want
4912 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4913 or if tempreg is PIC_CALL_REG
4914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4915 For a local symbol, we want
4916 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4918 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4920 If we have a small constant, and this is a reference to
4921 an external symbol, we want
4922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4924 addiu $tempreg,$tempreg,<constant>
4925 For a local symbol, we want the same instruction
4926 sequence, but we output a BFD_RELOC_LO16 reloc on the
4929 If we have a large constant, and this is a reference to
4930 an external symbol, we want
4931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4932 lui $at,<hiconstant>
4933 addiu $at,$at,<loconstant>
4934 addu $tempreg,$tempreg,$at
4935 For a local symbol, we want the same instruction
4936 sequence, but we output a BFD_RELOC_LO16 reloc on the
4939 For NewABI, we want for local or external data addresses
4940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4941 For a local function symbol, we want
4942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4944 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4947 expr1
.X_add_number
= offset_expr
.X_add_number
;
4948 offset_expr
.X_add_number
= 0;
4950 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4951 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4952 else if (HAVE_NEWABI
)
4953 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4954 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4955 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4956 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4957 if (expr1
.X_add_number
== 0)
4966 /* We're going to put in an addu instruction using
4967 tempreg, so we may as well insert the nop right
4969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4973 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4974 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4976 ? mips_opts
.warn_about_macros
4978 offset_expr
.X_add_symbol
, 0, NULL
);
4981 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4984 macro_build (p
, &icnt
, &expr1
,
4985 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4986 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4987 /* FIXME: If breg == 0, and the next instruction uses
4988 $tempreg, then if this variant case is used an extra
4989 nop will be generated. */
4991 else if (expr1
.X_add_number
>= -0x8000
4992 && expr1
.X_add_number
< 0x8000)
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4996 macro_build ((char *) NULL
, &icnt
, &expr1
,
4997 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4998 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4999 frag_var (rs_machine_dependent
, 0, 0,
5000 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5001 offset_expr
.X_add_symbol
, 0, NULL
);
5007 /* If we are going to add in a base register, and the
5008 target register and the base register are the same,
5009 then we are using AT as a temporary register. Since
5010 we want to load the constant into AT, we add our
5011 current AT (from the global offset table) and the
5012 register into the register now, and pretend we were
5013 not using a base register. */
5018 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5021 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5022 "d,v,t", treg
, AT
, breg
);
5028 /* Set mips_optimize around the lui instruction to avoid
5029 inserting an unnecessary nop after the lw. */
5030 hold_mips_optimize
= mips_optimize
;
5032 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5033 mips_optimize
= hold_mips_optimize
;
5035 macro_build ((char *) NULL
, &icnt
, &expr1
,
5036 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5037 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5039 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5040 "d,v,t", tempreg
, tempreg
, AT
);
5041 frag_var (rs_machine_dependent
, 0, 0,
5042 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5043 offset_expr
.X_add_symbol
, 0, NULL
);
5047 else if (mips_pic
== SVR4_PIC
)
5051 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5052 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5053 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5055 /* This is the large GOT case. If this is a reference to an
5056 external symbol, and there is no constant, we want
5057 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5058 addu $tempreg,$tempreg,$gp
5059 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5060 or if tempreg is PIC_CALL_REG
5061 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5062 addu $tempreg,$tempreg,$gp
5063 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5064 For a local symbol, we want
5065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5067 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5069 If we have a small constant, and this is a reference to
5070 an external symbol, we want
5071 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5072 addu $tempreg,$tempreg,$gp
5073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5075 addiu $tempreg,$tempreg,<constant>
5076 For a local symbol, we want
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5079 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5081 If we have a large constant, and this is a reference to
5082 an external symbol, we want
5083 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5084 addu $tempreg,$tempreg,$gp
5085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5086 lui $at,<hiconstant>
5087 addiu $at,$at,<loconstant>
5088 addu $tempreg,$tempreg,$at
5089 For a local symbol, we want
5090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5091 lui $at,<hiconstant>
5092 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5093 addu $tempreg,$tempreg,$at
5095 For NewABI, we want for local data addresses
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5099 expr1
.X_add_number
= offset_expr
.X_add_number
;
5100 offset_expr
.X_add_number
= 0;
5102 if (reg_needs_delay (mips_gp_register
))
5106 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5108 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5109 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5112 tempreg
, lui_reloc_type
);
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5114 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5115 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5117 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5118 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5119 if (expr1
.X_add_number
== 0)
5127 /* We're going to put in an addu instruction using
5128 tempreg, so we may as well insert the nop right
5130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5135 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5136 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5139 ? mips_opts
.warn_about_macros
5141 offset_expr
.X_add_symbol
, 0, NULL
);
5143 else if (expr1
.X_add_number
>= -0x8000
5144 && expr1
.X_add_number
< 0x8000)
5146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5148 macro_build ((char *) NULL
, &icnt
, &expr1
,
5149 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5150 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5152 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5153 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5155 ? mips_opts
.warn_about_macros
5157 offset_expr
.X_add_symbol
, 0, NULL
);
5163 /* If we are going to add in a base register, and the
5164 target register and the base register are the same,
5165 then we are using AT as a temporary register. Since
5166 we want to load the constant into AT, we add our
5167 current AT (from the global offset table) and the
5168 register into the register now, and pretend we were
5169 not using a base register. */
5177 assert (tempreg
== AT
);
5178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5181 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5182 "d,v,t", treg
, AT
, breg
);
5187 /* Set mips_optimize around the lui instruction to avoid
5188 inserting an unnecessary nop after the lw. */
5189 hold_mips_optimize
= mips_optimize
;
5191 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5192 mips_optimize
= hold_mips_optimize
;
5194 macro_build ((char *) NULL
, &icnt
, &expr1
,
5195 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5196 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5198 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5199 "d,v,t", dreg
, dreg
, AT
);
5201 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5202 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5205 ? mips_opts
.warn_about_macros
5207 offset_expr
.X_add_symbol
, 0, NULL
);
5214 /* This is needed because this instruction uses $gp, but
5215 the first instruction on the main stream does not. */
5216 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5221 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5222 macro_build (p
, &icnt
, &offset_expr
,
5223 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5228 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5230 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5233 if (expr1
.X_add_number
>= -0x8000
5234 && expr1
.X_add_number
< 0x8000)
5236 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5238 macro_build (p
, &icnt
, &expr1
,
5239 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5240 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5241 /* FIXME: If add_number is 0, and there was no base
5242 register, the external symbol case ended with a load,
5243 so if the symbol turns out to not be external, and
5244 the next instruction uses tempreg, an unnecessary nop
5245 will be inserted. */
5251 /* We must add in the base register now, as in the
5252 external symbol case. */
5253 assert (tempreg
== AT
);
5254 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5256 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5257 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5258 "d,v,t", treg
, AT
, breg
);
5261 /* We set breg to 0 because we have arranged to add
5262 it in in both cases. */
5266 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5268 macro_build (p
, &icnt
, &expr1
,
5269 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5270 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5272 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5273 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5274 "d,v,t", tempreg
, tempreg
, AT
);
5278 else if (mips_pic
== EMBEDDED_PIC
)
5281 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5283 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5284 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5285 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5294 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5295 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5297 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5300 "d,v,t", treg
, tempreg
, breg
);
5309 /* The j instruction may not be used in PIC code, since it
5310 requires an absolute address. We convert it to a b
5312 if (mips_pic
== NO_PIC
)
5313 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5315 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5318 /* The jal instructions must be handled as macros because when
5319 generating PIC code they expand to multi-instruction
5320 sequences. Normally they are simple instructions. */
5325 if (mips_pic
== NO_PIC
5326 || mips_pic
== EMBEDDED_PIC
)
5327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5329 else if (mips_pic
== SVR4_PIC
)
5331 if (sreg
!= PIC_CALL_REG
)
5332 as_warn (_("MIPS PIC call to register other than $25"));
5334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5338 if (mips_cprestore_offset
< 0)
5339 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5342 if (! mips_frame_reg_valid
)
5344 as_warn (_("No .frame pseudo-op used in PIC code"));
5345 /* Quiet this warning. */
5346 mips_frame_reg_valid
= 1;
5348 if (! mips_cprestore_valid
)
5350 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5351 /* Quiet this warning. */
5352 mips_cprestore_valid
= 1;
5354 expr1
.X_add_number
= mips_cprestore_offset
;
5355 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5356 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5357 mips_gp_register
, mips_frame_reg
);
5367 if (mips_pic
== NO_PIC
)
5368 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5369 else if (mips_pic
== SVR4_PIC
)
5373 /* If this is a reference to an external symbol, and we are
5374 using a small GOT, we want
5375 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5379 lw $gp,cprestore($sp)
5380 The cprestore value is set using the .cprestore
5381 pseudo-op. If we are using a big GOT, we want
5382 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5384 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5388 lw $gp,cprestore($sp)
5389 If the symbol is not external, we want
5390 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5392 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5395 lw $gp,cprestore($sp)
5397 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5398 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5403 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5404 "t,o(b)", PIC_CALL_REG
,
5405 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5406 macro_build_jalr (icnt
, &offset_expr
);
5413 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5414 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5415 "t,o(b)", PIC_CALL_REG
,
5416 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5419 p
= frag_var (rs_machine_dependent
, 4, 0,
5420 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5421 offset_expr
.X_add_symbol
, 0, NULL
);
5427 if (reg_needs_delay (mips_gp_register
))
5431 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5432 "t,u", PIC_CALL_REG
,
5433 (int) BFD_RELOC_MIPS_CALL_HI16
);
5434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5435 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5436 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5438 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5439 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5440 "t,o(b)", PIC_CALL_REG
,
5441 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5444 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5445 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5447 offset_expr
.X_add_symbol
, 0, NULL
);
5450 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5453 macro_build (p
, &icnt
, &offset_expr
,
5454 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5455 "t,o(b)", PIC_CALL_REG
,
5456 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5458 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5461 macro_build (p
, &icnt
, &offset_expr
,
5462 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5463 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5464 (int) BFD_RELOC_LO16
);
5465 macro_build_jalr (icnt
, &offset_expr
);
5467 if (mips_cprestore_offset
< 0)
5468 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5471 if (! mips_frame_reg_valid
)
5473 as_warn (_("No .frame pseudo-op used in PIC code"));
5474 /* Quiet this warning. */
5475 mips_frame_reg_valid
= 1;
5477 if (! mips_cprestore_valid
)
5479 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5480 /* Quiet this warning. */
5481 mips_cprestore_valid
= 1;
5483 if (mips_opts
.noreorder
)
5484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5486 expr1
.X_add_number
= mips_cprestore_offset
;
5487 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5488 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5489 mips_gp_register
, mips_frame_reg
);
5493 else if (mips_pic
== EMBEDDED_PIC
)
5495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5496 /* The linker may expand the call to a longer sequence which
5497 uses $at, so we must break rather than return. */
5522 /* Itbl support may require additional care here. */
5527 /* Itbl support may require additional care here. */
5532 /* Itbl support may require additional care here. */
5537 /* Itbl support may require additional care here. */
5549 if (mips_arch
== CPU_R4650
)
5551 as_bad (_("opcode not supported on this processor"));
5555 /* Itbl support may require additional care here. */
5560 /* Itbl support may require additional care here. */
5565 /* Itbl support may require additional care here. */
5585 if (breg
== treg
|| coproc
|| lr
)
5607 /* Itbl support may require additional care here. */
5612 /* Itbl support may require additional care here. */
5617 /* Itbl support may require additional care here. */
5622 /* Itbl support may require additional care here. */
5638 if (mips_arch
== CPU_R4650
)
5640 as_bad (_("opcode not supported on this processor"));
5645 /* Itbl support may require additional care here. */
5649 /* Itbl support may require additional care here. */
5654 /* Itbl support may require additional care here. */
5666 /* Itbl support may require additional care here. */
5667 if (mask
== M_LWC1_AB
5668 || mask
== M_SWC1_AB
5669 || mask
== M_LDC1_AB
5670 || mask
== M_SDC1_AB
5679 /* For embedded PIC, we allow loads where the offset is calculated
5680 by subtracting a symbol in the current segment from an unknown
5681 symbol, relative to a base register, e.g.:
5682 <op> $treg, <sym>-<localsym>($breg)
5683 This is used by the compiler for switch statements. */
5684 if (mips_pic
== EMBEDDED_PIC
5685 && offset_expr
.X_op
== O_subtract
5686 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5687 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5688 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5690 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5694 && (offset_expr
.X_add_number
== 0
5695 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5697 /* For this case, we output the instructions:
5698 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5699 addiu $tempreg,$tempreg,$breg
5700 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5701 If the relocation would fit entirely in 16 bits, it would be
5703 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5704 instead, but that seems quite difficult. */
5705 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5706 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5708 ((bfd_arch_bits_per_address (stdoutput
) == 32
5709 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5710 ? "addu" : "daddu"),
5711 "d,v,t", tempreg
, tempreg
, breg
);
5712 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5713 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5719 if (offset_expr
.X_op
!= O_constant
5720 && offset_expr
.X_op
!= O_symbol
)
5722 as_bad (_("expression too complex"));
5723 offset_expr
.X_op
= O_constant
;
5726 /* A constant expression in PIC code can be handled just as it
5727 is in non PIC code. */
5728 if (mips_pic
== NO_PIC
5729 || offset_expr
.X_op
== O_constant
)
5733 /* If this is a reference to a GP relative symbol, and there
5734 is no base register, we want
5735 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5736 Otherwise, if there is no base register, we want
5737 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5738 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5739 If we have a constant, we need two instructions anyhow,
5740 so we always use the latter form.
5742 If we have a base register, and this is a reference to a
5743 GP relative symbol, we want
5744 addu $tempreg,$breg,$gp
5745 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5747 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5748 addu $tempreg,$tempreg,$breg
5749 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5750 With a constant we always use the latter case.
5752 With 64bit address space and no base register and $at usable,
5754 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5755 lui $at,<sym> (BFD_RELOC_HI16_S)
5756 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5759 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5760 If we have a base register, we want
5761 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5762 lui $at,<sym> (BFD_RELOC_HI16_S)
5763 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5767 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5769 Without $at we can't generate the optimal path for superscalar
5770 processors here since this would require two temporary registers.
5771 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5772 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5774 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5776 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5777 If we have a base register, we want
5778 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5779 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5781 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5783 daddu $tempreg,$tempreg,$breg
5784 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5786 If we have 64-bit addresses, as an optimization, for
5787 addresses which are 32-bit constants (e.g. kseg0/kseg1
5788 addresses) we fall back to the 32-bit address generation
5789 mechanism since it is more efficient. Note that due to
5790 the signed offset used by memory operations, the 32-bit
5791 range is shifted down by 32768 here. This code should
5792 probably attempt to generate 64-bit constants more
5793 efficiently in general.
5795 if (HAVE_64BIT_ADDRESSES
5796 && !(offset_expr
.X_op
== O_constant
5797 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5801 /* We don't do GP optimization for now because RELAX_ENCODE can't
5802 hold the data for such large chunks. */
5804 if (used_at
== 0 && ! mips_opts
.noat
)
5806 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5807 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5808 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5809 AT
, (int) BFD_RELOC_HI16_S
);
5810 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5811 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5813 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5814 "d,v,t", AT
, AT
, breg
);
5815 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5816 "d,w,<", tempreg
, tempreg
, 0);
5817 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5818 "d,v,t", tempreg
, tempreg
, AT
);
5819 macro_build (p
, &icnt
, &offset_expr
, s
,
5820 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5825 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5826 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5827 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5828 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5829 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5830 "d,w,<", tempreg
, tempreg
, 16);
5831 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5832 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5833 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5834 "d,w,<", tempreg
, tempreg
, 16);
5836 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5837 "d,v,t", tempreg
, tempreg
, breg
);
5838 macro_build (p
, &icnt
, &offset_expr
, s
,
5839 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5847 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5848 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5854 treg
, (int) BFD_RELOC_GPREL16
,
5856 p
= frag_var (rs_machine_dependent
, 8, 0,
5857 RELAX_ENCODE (4, 8, 0, 4, 0,
5858 (mips_opts
.warn_about_macros
5860 && mips_opts
.noat
))),
5861 offset_expr
.X_add_symbol
, 0, NULL
);
5864 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5867 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5868 (int) BFD_RELOC_LO16
, tempreg
);
5872 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5873 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5879 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5880 "d,v,t", tempreg
, breg
, mips_gp_register
);
5881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5882 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5883 p
= frag_var (rs_machine_dependent
, 12, 0,
5884 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5885 offset_expr
.X_add_symbol
, 0, NULL
);
5887 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5890 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5891 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5892 "d,v,t", tempreg
, tempreg
, breg
);
5895 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5896 (int) BFD_RELOC_LO16
, tempreg
);
5899 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5902 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5904 /* If this is a reference to an external symbol, we want
5905 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5907 <op> $treg,0($tempreg)
5909 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5911 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5912 <op> $treg,0($tempreg)
5913 If we have NewABI, we want
5914 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5915 If there is a base register, we add it to $tempreg before
5916 the <op>. If there is a constant, we stick it in the
5917 <op> instruction. We don't handle constants larger than
5918 16 bits, because we have no way to load the upper 16 bits
5919 (actually, we could handle them for the subset of cases
5920 in which we are not using $at). */
5921 assert (offset_expr
.X_op
== O_symbol
);
5922 expr1
.X_add_number
= offset_expr
.X_add_number
;
5923 offset_expr
.X_add_number
= 0;
5925 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5926 if (expr1
.X_add_number
< -0x8000
5927 || expr1
.X_add_number
>= 0x8000)
5928 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5931 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5932 (int) lw_reloc_type
, mips_gp_register
);
5933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5934 p
= frag_var (rs_machine_dependent
, 4, 0,
5935 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5936 offset_expr
.X_add_symbol
, 0, NULL
);
5937 macro_build (p
, &icnt
, &offset_expr
,
5938 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5939 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5941 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5942 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5943 "d,v,t", tempreg
, tempreg
, breg
);
5944 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5945 (int) BFD_RELOC_LO16
, tempreg
);
5947 else if (mips_pic
== SVR4_PIC
)
5952 /* If this is a reference to an external symbol, we want
5953 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5954 addu $tempreg,$tempreg,$gp
5955 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5956 <op> $treg,0($tempreg)
5958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5961 <op> $treg,0($tempreg)
5962 If there is a base register, we add it to $tempreg before
5963 the <op>. If there is a constant, we stick it in the
5964 <op> instruction. We don't handle constants larger than
5965 16 bits, because we have no way to load the upper 16 bits
5966 (actually, we could handle them for the subset of cases
5967 in which we are not using $at).
5970 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5971 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5972 <op> $treg,0($tempreg)
5974 assert (offset_expr
.X_op
== O_symbol
);
5975 expr1
.X_add_number
= offset_expr
.X_add_number
;
5976 offset_expr
.X_add_number
= 0;
5977 if (expr1
.X_add_number
< -0x8000
5978 || expr1
.X_add_number
>= 0x8000)
5979 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5982 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5983 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5984 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5987 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5988 "t,r,j", tempreg
, tempreg
,
5989 BFD_RELOC_MIPS_GOT_OFST
);
5991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5992 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5993 "d,v,t", tempreg
, tempreg
, breg
);
5994 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5995 (int) BFD_RELOC_LO16
, tempreg
);
6002 if (reg_needs_delay (mips_gp_register
))
6007 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6008 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6010 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6011 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6013 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6014 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6016 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6017 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6018 offset_expr
.X_add_symbol
, 0, NULL
);
6021 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6024 macro_build (p
, &icnt
, &offset_expr
,
6025 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6026 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6029 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6031 macro_build (p
, &icnt
, &offset_expr
,
6032 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6033 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6036 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6037 "d,v,t", tempreg
, tempreg
, breg
);
6038 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6039 (int) BFD_RELOC_LO16
, tempreg
);
6041 else if (mips_pic
== EMBEDDED_PIC
)
6043 /* If there is no base register, we want
6044 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6045 If there is a base register, we want
6046 addu $tempreg,$breg,$gp
6047 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6049 assert (offset_expr
.X_op
== O_symbol
);
6052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6053 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6058 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6059 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6060 "d,v,t", tempreg
, breg
, mips_gp_register
);
6061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6062 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6075 load_register (&icnt
, treg
, &imm_expr
, 0);
6079 load_register (&icnt
, treg
, &imm_expr
, 1);
6083 if (imm_expr
.X_op
== O_constant
)
6085 load_register (&icnt
, AT
, &imm_expr
, 0);
6086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6087 "mtc1", "t,G", AT
, treg
);
6092 assert (offset_expr
.X_op
== O_symbol
6093 && strcmp (segment_name (S_GET_SEGMENT
6094 (offset_expr
.X_add_symbol
)),
6096 && offset_expr
.X_add_number
== 0);
6097 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6098 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6103 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6104 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6105 order 32 bits of the value and the low order 32 bits are either
6106 zero or in OFFSET_EXPR. */
6107 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6109 if (HAVE_64BIT_GPRS
)
6110 load_register (&icnt
, treg
, &imm_expr
, 1);
6115 if (target_big_endian
)
6127 load_register (&icnt
, hreg
, &imm_expr
, 0);
6130 if (offset_expr
.X_op
== O_absent
)
6131 move_register (&icnt
, lreg
, 0);
6134 assert (offset_expr
.X_op
== O_constant
);
6135 load_register (&icnt
, lreg
, &offset_expr
, 0);
6142 /* We know that sym is in the .rdata section. First we get the
6143 upper 16 bits of the address. */
6144 if (mips_pic
== NO_PIC
)
6146 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6148 else if (mips_pic
== SVR4_PIC
)
6150 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6151 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6152 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6155 else if (mips_pic
== EMBEDDED_PIC
)
6157 /* For embedded PIC we pick up the entire address off $gp in
6158 a single instruction. */
6159 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6160 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6161 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6162 offset_expr
.X_op
= O_constant
;
6163 offset_expr
.X_add_number
= 0;
6168 /* Now we load the register(s). */
6169 if (HAVE_64BIT_GPRS
)
6170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6171 treg
, (int) BFD_RELOC_LO16
, AT
);
6174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6175 treg
, (int) BFD_RELOC_LO16
, AT
);
6178 /* FIXME: How in the world do we deal with the possible
6180 offset_expr
.X_add_number
+= 4;
6181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6182 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6186 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6187 does not become a variant frag. */
6188 frag_wane (frag_now
);
6194 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6195 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6196 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6197 the value and the low order 32 bits are either zero or in
6199 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6201 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6202 if (HAVE_64BIT_FPRS
)
6204 assert (HAVE_64BIT_GPRS
);
6205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6206 "dmtc1", "t,S", AT
, treg
);
6210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6211 "mtc1", "t,G", AT
, treg
+ 1);
6212 if (offset_expr
.X_op
== O_absent
)
6213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6214 "mtc1", "t,G", 0, treg
);
6217 assert (offset_expr
.X_op
== O_constant
);
6218 load_register (&icnt
, AT
, &offset_expr
, 0);
6219 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6220 "mtc1", "t,G", AT
, treg
);
6226 assert (offset_expr
.X_op
== O_symbol
6227 && offset_expr
.X_add_number
== 0);
6228 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6229 if (strcmp (s
, ".lit8") == 0)
6231 if (mips_opts
.isa
!= ISA_MIPS1
)
6233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6234 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6238 breg
= mips_gp_register
;
6239 r
= BFD_RELOC_MIPS_LITERAL
;
6244 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6245 if (mips_pic
== SVR4_PIC
)
6246 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6247 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6248 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6252 /* FIXME: This won't work for a 64 bit address. */
6253 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6256 if (mips_opts
.isa
!= ISA_MIPS1
)
6258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6259 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6261 /* To avoid confusion in tc_gen_reloc, we must ensure
6262 that this does not become a variant frag. */
6263 frag_wane (frag_now
);
6274 if (mips_arch
== CPU_R4650
)
6276 as_bad (_("opcode not supported on this processor"));
6279 /* Even on a big endian machine $fn comes before $fn+1. We have
6280 to adjust when loading from memory. */
6283 assert (mips_opts
.isa
== ISA_MIPS1
);
6284 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6285 target_big_endian
? treg
+ 1 : treg
,
6287 /* FIXME: A possible overflow which I don't know how to deal
6289 offset_expr
.X_add_number
+= 4;
6290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6291 target_big_endian
? treg
: treg
+ 1,
6294 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6295 does not become a variant frag. */
6296 frag_wane (frag_now
);
6305 * The MIPS assembler seems to check for X_add_number not
6306 * being double aligned and generating:
6309 * addiu at,at,%lo(foo+1)
6312 * But, the resulting address is the same after relocation so why
6313 * generate the extra instruction?
6315 if (mips_arch
== CPU_R4650
)
6317 as_bad (_("opcode not supported on this processor"));
6320 /* Itbl support may require additional care here. */
6322 if (mips_opts
.isa
!= ISA_MIPS1
)
6333 if (mips_arch
== CPU_R4650
)
6335 as_bad (_("opcode not supported on this processor"));
6339 if (mips_opts
.isa
!= ISA_MIPS1
)
6347 /* Itbl support may require additional care here. */
6352 if (HAVE_64BIT_GPRS
)
6363 if (HAVE_64BIT_GPRS
)
6373 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6374 loads for the case of doing a pair of loads to simulate an 'ld'.
6375 This is not currently done by the compiler, and assembly coders
6376 writing embedded-pic code can cope. */
6378 if (offset_expr
.X_op
!= O_symbol
6379 && offset_expr
.X_op
!= O_constant
)
6381 as_bad (_("expression too complex"));
6382 offset_expr
.X_op
= O_constant
;
6385 /* Even on a big endian machine $fn comes before $fn+1. We have
6386 to adjust when loading from memory. We set coproc if we must
6387 load $fn+1 first. */
6388 /* Itbl support may require additional care here. */
6389 if (! target_big_endian
)
6392 if (mips_pic
== NO_PIC
6393 || offset_expr
.X_op
== O_constant
)
6397 /* If this is a reference to a GP relative symbol, we want
6398 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6399 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6400 If we have a base register, we use this
6402 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6403 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6404 If this is not a GP relative symbol, we want
6405 lui $at,<sym> (BFD_RELOC_HI16_S)
6406 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6407 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6408 If there is a base register, we add it to $at after the
6409 lui instruction. If there is a constant, we always use
6411 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6412 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6424 tempreg
= mips_gp_register
;
6431 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6432 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6433 "d,v,t", AT
, breg
, mips_gp_register
);
6439 /* Itbl support may require additional care here. */
6440 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6441 coproc
? treg
+ 1 : treg
,
6442 (int) BFD_RELOC_GPREL16
, tempreg
);
6443 offset_expr
.X_add_number
+= 4;
6445 /* Set mips_optimize to 2 to avoid inserting an
6447 hold_mips_optimize
= mips_optimize
;
6449 /* Itbl support may require additional care here. */
6450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6451 coproc
? treg
: treg
+ 1,
6452 (int) BFD_RELOC_GPREL16
, tempreg
);
6453 mips_optimize
= hold_mips_optimize
;
6455 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6456 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6457 used_at
&& mips_opts
.noat
),
6458 offset_expr
.X_add_symbol
, 0, NULL
);
6460 /* We just generated two relocs. When tc_gen_reloc
6461 handles this case, it will skip the first reloc and
6462 handle the second. The second reloc already has an
6463 extra addend of 4, which we added above. We must
6464 subtract it out, and then subtract another 4 to make
6465 the first reloc come out right. The second reloc
6466 will come out right because we are going to add 4 to
6467 offset_expr when we build its instruction below.
6469 If we have a symbol, then we don't want to include
6470 the offset, because it will wind up being included
6471 when we generate the reloc. */
6473 if (offset_expr
.X_op
== O_constant
)
6474 offset_expr
.X_add_number
-= 8;
6477 offset_expr
.X_add_number
= -4;
6478 offset_expr
.X_op
= O_constant
;
6481 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6486 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6487 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6488 "d,v,t", AT
, breg
, AT
);
6492 /* Itbl support may require additional care here. */
6493 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6494 coproc
? treg
+ 1 : treg
,
6495 (int) BFD_RELOC_LO16
, AT
);
6498 /* FIXME: How do we handle overflow here? */
6499 offset_expr
.X_add_number
+= 4;
6500 /* Itbl support may require additional care here. */
6501 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6502 coproc
? treg
: treg
+ 1,
6503 (int) BFD_RELOC_LO16
, AT
);
6505 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6509 /* If this is a reference to an external symbol, we want
6510 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6515 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6517 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6518 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6519 If there is a base register we add it to $at before the
6520 lwc1 instructions. If there is a constant we include it
6521 in the lwc1 instructions. */
6523 expr1
.X_add_number
= offset_expr
.X_add_number
;
6524 offset_expr
.X_add_number
= 0;
6525 if (expr1
.X_add_number
< -0x8000
6526 || expr1
.X_add_number
>= 0x8000 - 4)
6527 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6532 frag_grow (24 + off
);
6533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6534 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6535 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6539 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6540 "d,v,t", AT
, breg
, AT
);
6541 /* Itbl support may require additional care here. */
6542 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6543 coproc
? treg
+ 1 : treg
,
6544 (int) BFD_RELOC_LO16
, AT
);
6545 expr1
.X_add_number
+= 4;
6547 /* Set mips_optimize to 2 to avoid inserting an undesired
6549 hold_mips_optimize
= mips_optimize
;
6551 /* Itbl support may require additional care here. */
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6553 coproc
? treg
: treg
+ 1,
6554 (int) BFD_RELOC_LO16
, AT
);
6555 mips_optimize
= hold_mips_optimize
;
6557 (void) frag_var (rs_machine_dependent
, 0, 0,
6558 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6559 offset_expr
.X_add_symbol
, 0, NULL
);
6561 else if (mips_pic
== SVR4_PIC
)
6566 /* If this is a reference to an external symbol, we want
6567 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6569 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6574 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6576 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6577 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6578 If there is a base register we add it to $at before the
6579 lwc1 instructions. If there is a constant we include it
6580 in the lwc1 instructions. */
6582 expr1
.X_add_number
= offset_expr
.X_add_number
;
6583 offset_expr
.X_add_number
= 0;
6584 if (expr1
.X_add_number
< -0x8000
6585 || expr1
.X_add_number
>= 0x8000 - 4)
6586 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6587 if (reg_needs_delay (mips_gp_register
))
6596 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6597 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6599 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6600 "d,v,t", AT
, AT
, mips_gp_register
);
6601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6602 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6603 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6607 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6608 "d,v,t", AT
, breg
, AT
);
6609 /* Itbl support may require additional care here. */
6610 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6611 coproc
? treg
+ 1 : treg
,
6612 (int) BFD_RELOC_LO16
, AT
);
6613 expr1
.X_add_number
+= 4;
6615 /* Set mips_optimize to 2 to avoid inserting an undesired
6617 hold_mips_optimize
= mips_optimize
;
6619 /* Itbl support may require additional care here. */
6620 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6621 coproc
? treg
: treg
+ 1,
6622 (int) BFD_RELOC_LO16
, AT
);
6623 mips_optimize
= hold_mips_optimize
;
6624 expr1
.X_add_number
-= 4;
6626 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6627 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6628 8 + gpdel
+ off
, 1, 0),
6629 offset_expr
.X_add_symbol
, 0, NULL
);
6632 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6635 macro_build (p
, &icnt
, &offset_expr
,
6636 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6637 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6640 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6644 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6645 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6646 "d,v,t", AT
, breg
, AT
);
6649 /* Itbl support may require additional care here. */
6650 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6651 coproc
? treg
+ 1 : treg
,
6652 (int) BFD_RELOC_LO16
, AT
);
6654 expr1
.X_add_number
+= 4;
6656 /* Set mips_optimize to 2 to avoid inserting an undesired
6658 hold_mips_optimize
= mips_optimize
;
6660 /* Itbl support may require additional care here. */
6661 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6662 coproc
? treg
: treg
+ 1,
6663 (int) BFD_RELOC_LO16
, AT
);
6664 mips_optimize
= hold_mips_optimize
;
6666 else if (mips_pic
== EMBEDDED_PIC
)
6668 /* If there is no base register, we use
6669 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6670 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6671 If we have a base register, we use
6673 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6674 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6678 tempreg
= mips_gp_register
;
6683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6684 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6685 "d,v,t", AT
, breg
, mips_gp_register
);
6690 /* Itbl support may require additional care here. */
6691 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6692 coproc
? treg
+ 1 : treg
,
6693 (int) BFD_RELOC_GPREL16
, tempreg
);
6694 offset_expr
.X_add_number
+= 4;
6695 /* Itbl support may require additional care here. */
6696 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6697 coproc
? treg
: treg
+ 1,
6698 (int) BFD_RELOC_GPREL16
, tempreg
);
6714 assert (HAVE_32BIT_ADDRESSES
);
6715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6716 (int) BFD_RELOC_LO16
, breg
);
6717 offset_expr
.X_add_number
+= 4;
6718 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6719 (int) BFD_RELOC_LO16
, breg
);
6722 /* New code added to support COPZ instructions.
6723 This code builds table entries out of the macros in mip_opcodes.
6724 R4000 uses interlocks to handle coproc delays.
6725 Other chips (like the R3000) require nops to be inserted for delays.
6727 FIXME: Currently, we require that the user handle delays.
6728 In order to fill delay slots for non-interlocked chips,
6729 we must have a way to specify delays based on the coprocessor.
6730 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6731 What are the side-effects of the cop instruction?
6732 What cache support might we have and what are its effects?
6733 Both coprocessor & memory require delays. how long???
6734 What registers are read/set/modified?
6736 If an itbl is provided to interpret cop instructions,
6737 this knowledge can be encoded in the itbl spec. */
6751 /* For now we just do C (same as Cz). The parameter will be
6752 stored in insn_opcode by mips_ip. */
6753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6758 move_register (&icnt
, dreg
, sreg
);
6761 #ifdef LOSING_COMPILER
6763 /* Try and see if this is a new itbl instruction.
6764 This code builds table entries out of the macros in mip_opcodes.
6765 FIXME: For now we just assemble the expression and pass it's
6766 value along as a 32-bit immediate.
6767 We may want to have the assembler assemble this value,
6768 so that we gain the assembler's knowledge of delay slots,
6770 Would it be more efficient to use mask (id) here? */
6771 if (itbl_have_entries
6772 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6774 s
= ip
->insn_mo
->name
;
6776 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6777 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6784 as_warn (_("Macro used $at after \".set noat\""));
6789 struct mips_cl_insn
*ip
;
6791 register int treg
, sreg
, dreg
, breg
;
6807 bfd_reloc_code_real_type r
;
6810 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6811 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6812 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6813 mask
= ip
->insn_mo
->mask
;
6815 expr1
.X_op
= O_constant
;
6816 expr1
.X_op_symbol
= NULL
;
6817 expr1
.X_add_symbol
= NULL
;
6818 expr1
.X_add_number
= 1;
6822 #endif /* LOSING_COMPILER */
6827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6828 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6836 /* The MIPS assembler some times generates shifts and adds. I'm
6837 not trying to be that fancy. GCC should do this for us
6839 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6840 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6841 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6842 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6856 mips_emit_delays (TRUE
);
6857 ++mips_opts
.noreorder
;
6858 mips_any_noreorder
= 1;
6860 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6862 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6865 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6866 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6870 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6871 "s,t,q", dreg
, AT
, 6);
6874 expr1
.X_add_number
= 8;
6875 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6879 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6882 --mips_opts
.noreorder
;
6883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6896 mips_emit_delays (TRUE
);
6897 ++mips_opts
.noreorder
;
6898 mips_any_noreorder
= 1;
6900 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6902 dbl
? "dmultu" : "multu",
6903 "s,t", sreg
, imm
? AT
: treg
);
6904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6913 expr1
.X_add_number
= 8;
6914 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6917 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6920 --mips_opts
.noreorder
;
6924 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
6936 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
6937 "d,w", tempreg
, treg
);
6938 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
6939 "d,t,s", dreg
, sreg
, tempreg
);
6944 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6945 "d,v,t", AT
, 0, treg
);
6946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6947 "d,t,s", AT
, sreg
, AT
);
6948 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6949 "d,t,s", dreg
, sreg
, treg
);
6950 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6951 "d,v,t", dreg
, dreg
, AT
);
6955 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
6967 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
6968 "d,w", tempreg
, treg
);
6969 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
6970 "d,t,s", dreg
, sreg
, tempreg
);
6975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6976 "d,v,t", AT
, 0, treg
);
6977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6978 "d,t,s", AT
, sreg
, AT
);
6979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6980 "d,t,s", dreg
, sreg
, treg
);
6981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6982 "d,v,t", dreg
, dreg
, AT
);
6990 if (imm_expr
.X_op
!= O_constant
)
6991 as_bad (_("Improper rotate count"));
6992 rot
= imm_expr
.X_add_number
& 0x3f;
6993 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
6995 rot
= (64 - rot
) & 0x3f;
6997 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
6998 "d,w,<", dreg
, sreg
, rot
- 32);
7000 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7001 "d,w,<", dreg
, sreg
, rot
);
7006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7007 "d,w,<", dreg
, sreg
, 0);
7010 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7011 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7013 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7014 "d,w,<", AT
, sreg
, rot
);
7015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7016 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7017 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7018 "d,v,t", dreg
, dreg
, AT
);
7026 if (imm_expr
.X_op
!= O_constant
)
7027 as_bad (_("Improper rotate count"));
7028 rot
= imm_expr
.X_add_number
& 0x1f;
7029 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7031 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7032 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7038 "d,w,<", dreg
, sreg
, 0);
7041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7042 "d,w,<", AT
, sreg
, rot
);
7043 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7044 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7046 "d,v,t", dreg
, dreg
, AT
);
7051 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7053 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7054 "d,t,s", dreg
, sreg
, treg
);
7057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7058 "d,v,t", AT
, 0, treg
);
7059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7060 "d,t,s", AT
, sreg
, AT
);
7061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7062 "d,t,s", dreg
, sreg
, treg
);
7063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7064 "d,v,t", dreg
, dreg
, AT
);
7068 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7070 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7071 "d,t,s", dreg
, sreg
, treg
);
7074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7075 "d,v,t", AT
, 0, treg
);
7076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7077 "d,t,s", AT
, sreg
, AT
);
7078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7079 "d,t,s", dreg
, sreg
, treg
);
7080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7081 "d,v,t", dreg
, dreg
, AT
);
7089 if (imm_expr
.X_op
!= O_constant
)
7090 as_bad (_("Improper rotate count"));
7091 rot
= imm_expr
.X_add_number
& 0x3f;
7092 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7095 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7096 "d,w,<", dreg
, sreg
, rot
- 32);
7098 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7099 "d,w,<", dreg
, sreg
, rot
);
7104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7105 "d,w,<", dreg
, sreg
, 0);
7108 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7109 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7112 "d,w,<", AT
, sreg
, rot
);
7113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7114 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7115 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7116 "d,v,t", dreg
, dreg
, AT
);
7124 if (imm_expr
.X_op
!= O_constant
)
7125 as_bad (_("Improper rotate count"));
7126 rot
= imm_expr
.X_add_number
& 0x1f;
7127 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7129 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7130 "d,w,<", dreg
, sreg
, rot
);
7135 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7136 "d,w,<", dreg
, sreg
, 0);
7139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7140 "d,w,<", AT
, sreg
, rot
);
7141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7142 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7143 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7144 "d,v,t", dreg
, dreg
, AT
);
7149 if (mips_arch
== CPU_R4650
)
7151 as_bad (_("opcode not supported on this processor"));
7154 assert (mips_opts
.isa
== ISA_MIPS1
);
7155 /* Even on a big endian machine $fn comes before $fn+1. We have
7156 to adjust when storing to memory. */
7157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7158 target_big_endian
? treg
+ 1 : treg
,
7159 (int) BFD_RELOC_LO16
, breg
);
7160 offset_expr
.X_add_number
+= 4;
7161 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7162 target_big_endian
? treg
: treg
+ 1,
7163 (int) BFD_RELOC_LO16
, breg
);
7168 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7169 treg
, (int) BFD_RELOC_LO16
);
7171 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7172 sreg
, (int) BFD_RELOC_LO16
);
7175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7176 "d,v,t", dreg
, sreg
, treg
);
7177 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7178 dreg
, (int) BFD_RELOC_LO16
);
7183 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7185 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7186 sreg
, (int) BFD_RELOC_LO16
);
7191 as_warn (_("Instruction %s: result is always false"),
7193 move_register (&icnt
, dreg
, 0);
7196 if (imm_expr
.X_op
== O_constant
7197 && imm_expr
.X_add_number
>= 0
7198 && imm_expr
.X_add_number
< 0x10000)
7200 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7201 sreg
, (int) BFD_RELOC_LO16
);
7204 else if (imm_expr
.X_op
== O_constant
7205 && imm_expr
.X_add_number
> -0x8000
7206 && imm_expr
.X_add_number
< 0)
7208 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7209 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7210 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7211 "t,r,j", dreg
, sreg
,
7212 (int) BFD_RELOC_LO16
);
7217 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7218 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7219 "d,v,t", dreg
, sreg
, AT
);
7222 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7223 (int) BFD_RELOC_LO16
);
7228 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7234 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7236 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7237 (int) BFD_RELOC_LO16
);
7240 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7242 if (imm_expr
.X_op
== O_constant
7243 && imm_expr
.X_add_number
>= -0x8000
7244 && imm_expr
.X_add_number
< 0x8000)
7246 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7247 mask
== M_SGE_I
? "slti" : "sltiu",
7248 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7253 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7254 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7255 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7259 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7260 (int) BFD_RELOC_LO16
);
7265 case M_SGT
: /* sreg > treg <==> treg < sreg */
7271 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7275 case M_SGT_I
: /* sreg > I <==> I < sreg */
7281 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7286 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7294 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7295 (int) BFD_RELOC_LO16
);
7298 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7304 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7307 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7308 (int) BFD_RELOC_LO16
);
7312 if (imm_expr
.X_op
== O_constant
7313 && imm_expr
.X_add_number
>= -0x8000
7314 && imm_expr
.X_add_number
< 0x8000)
7316 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7317 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7320 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7326 if (imm_expr
.X_op
== O_constant
7327 && imm_expr
.X_add_number
>= -0x8000
7328 && imm_expr
.X_add_number
< 0x8000)
7330 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7331 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7334 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7336 "d,v,t", dreg
, sreg
, AT
);
7341 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7342 "d,v,t", dreg
, 0, treg
);
7344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7345 "d,v,t", dreg
, 0, sreg
);
7348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7349 "d,v,t", dreg
, sreg
, treg
);
7350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7351 "d,v,t", dreg
, 0, dreg
);
7356 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7359 "d,v,t", dreg
, 0, sreg
);
7364 as_warn (_("Instruction %s: result is always true"),
7366 macro_build ((char *) NULL
, &icnt
, &expr1
,
7367 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7368 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7371 if (imm_expr
.X_op
== O_constant
7372 && imm_expr
.X_add_number
>= 0
7373 && imm_expr
.X_add_number
< 0x10000)
7375 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7376 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7379 else if (imm_expr
.X_op
== O_constant
7380 && imm_expr
.X_add_number
> -0x8000
7381 && imm_expr
.X_add_number
< 0)
7383 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7384 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7385 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7386 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7391 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7393 "d,v,t", dreg
, sreg
, AT
);
7396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7397 "d,v,t", dreg
, 0, dreg
);
7405 if (imm_expr
.X_op
== O_constant
7406 && imm_expr
.X_add_number
> -0x8000
7407 && imm_expr
.X_add_number
<= 0x8000)
7409 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7410 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7411 dbl
? "daddi" : "addi",
7412 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7415 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7416 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7417 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7423 if (imm_expr
.X_op
== O_constant
7424 && imm_expr
.X_add_number
> -0x8000
7425 && imm_expr
.X_add_number
<= 0x8000)
7427 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7428 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7429 dbl
? "daddiu" : "addiu",
7430 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7433 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7434 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7435 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7456 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7463 assert (mips_opts
.isa
== ISA_MIPS1
);
7464 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7465 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7468 * Is the double cfc1 instruction a bug in the mips assembler;
7469 * or is there a reason for it?
7471 mips_emit_delays (TRUE
);
7472 ++mips_opts
.noreorder
;
7473 mips_any_noreorder
= 1;
7474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7479 expr1
.X_add_number
= 3;
7480 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7481 (int) BFD_RELOC_LO16
);
7482 expr1
.X_add_number
= 2;
7483 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7484 (int) BFD_RELOC_LO16
);
7485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7489 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7493 --mips_opts
.noreorder
;
7502 if (offset_expr
.X_add_number
>= 0x7fff)
7503 as_bad (_("operand overflow"));
7504 /* avoid load delay */
7505 if (! target_big_endian
)
7506 ++offset_expr
.X_add_number
;
7507 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7508 (int) BFD_RELOC_LO16
, breg
);
7509 if (! target_big_endian
)
7510 --offset_expr
.X_add_number
;
7512 ++offset_expr
.X_add_number
;
7513 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7514 (int) BFD_RELOC_LO16
, breg
);
7515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7531 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7532 as_bad (_("operand overflow"));
7533 if (! target_big_endian
)
7534 offset_expr
.X_add_number
+= off
;
7535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7536 (int) BFD_RELOC_LO16
, breg
);
7537 if (! target_big_endian
)
7538 offset_expr
.X_add_number
-= off
;
7540 offset_expr
.X_add_number
+= off
;
7541 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7542 (int) BFD_RELOC_LO16
, breg
);
7556 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7559 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7560 "d,v,t", AT
, AT
, breg
);
7561 if (! target_big_endian
)
7562 expr1
.X_add_number
= off
;
7564 expr1
.X_add_number
= 0;
7565 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7566 (int) BFD_RELOC_LO16
, AT
);
7567 if (! target_big_endian
)
7568 expr1
.X_add_number
= 0;
7570 expr1
.X_add_number
= off
;
7571 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7572 (int) BFD_RELOC_LO16
, AT
);
7578 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7581 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7582 "d,v,t", AT
, AT
, breg
);
7583 if (target_big_endian
)
7584 expr1
.X_add_number
= 0;
7585 macro_build ((char *) NULL
, &icnt
, &expr1
,
7586 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7587 (int) BFD_RELOC_LO16
, AT
);
7588 if (target_big_endian
)
7589 expr1
.X_add_number
= 1;
7591 expr1
.X_add_number
= 0;
7592 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7593 (int) BFD_RELOC_LO16
, AT
);
7594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7601 if (offset_expr
.X_add_number
>= 0x7fff)
7602 as_bad (_("operand overflow"));
7603 if (target_big_endian
)
7604 ++offset_expr
.X_add_number
;
7605 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7606 (int) BFD_RELOC_LO16
, breg
);
7607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7609 if (target_big_endian
)
7610 --offset_expr
.X_add_number
;
7612 ++offset_expr
.X_add_number
;
7613 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7614 (int) BFD_RELOC_LO16
, breg
);
7627 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7628 as_bad (_("operand overflow"));
7629 if (! target_big_endian
)
7630 offset_expr
.X_add_number
+= off
;
7631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7632 (int) BFD_RELOC_LO16
, breg
);
7633 if (! target_big_endian
)
7634 offset_expr
.X_add_number
-= off
;
7636 offset_expr
.X_add_number
+= off
;
7637 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7638 (int) BFD_RELOC_LO16
, breg
);
7652 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7655 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7656 "d,v,t", AT
, AT
, breg
);
7657 if (! target_big_endian
)
7658 expr1
.X_add_number
= off
;
7660 expr1
.X_add_number
= 0;
7661 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7662 (int) BFD_RELOC_LO16
, AT
);
7663 if (! target_big_endian
)
7664 expr1
.X_add_number
= 0;
7666 expr1
.X_add_number
= off
;
7667 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7668 (int) BFD_RELOC_LO16
, AT
);
7673 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7676 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7677 "d,v,t", AT
, AT
, breg
);
7678 if (! target_big_endian
)
7679 expr1
.X_add_number
= 0;
7680 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7681 (int) BFD_RELOC_LO16
, AT
);
7682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7684 if (! target_big_endian
)
7685 expr1
.X_add_number
= 1;
7687 expr1
.X_add_number
= 0;
7688 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7689 (int) BFD_RELOC_LO16
, AT
);
7690 if (! target_big_endian
)
7691 expr1
.X_add_number
= 0;
7693 expr1
.X_add_number
= 1;
7694 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7695 (int) BFD_RELOC_LO16
, AT
);
7696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7703 /* FIXME: Check if this is one of the itbl macros, since they
7704 are added dynamically. */
7705 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7709 as_warn (_("Macro used $at after \".set noat\""));
7712 /* Implement macros in mips16 mode. */
7716 struct mips_cl_insn
*ip
;
7719 int xreg
, yreg
, zreg
, tmp
;
7723 const char *s
, *s2
, *s3
;
7725 mask
= ip
->insn_mo
->mask
;
7727 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7728 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7729 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7733 expr1
.X_op
= O_constant
;
7734 expr1
.X_op_symbol
= NULL
;
7735 expr1
.X_add_symbol
= NULL
;
7736 expr1
.X_add_number
= 1;
7755 mips_emit_delays (TRUE
);
7756 ++mips_opts
.noreorder
;
7757 mips_any_noreorder
= 1;
7758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7759 dbl
? "ddiv" : "div",
7760 "0,x,y", xreg
, yreg
);
7761 expr1
.X_add_number
= 2;
7762 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7766 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7767 since that causes an overflow. We should do that as well,
7768 but I don't see how to do the comparisons without a temporary
7770 --mips_opts
.noreorder
;
7771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7790 mips_emit_delays (TRUE
);
7791 ++mips_opts
.noreorder
;
7792 mips_any_noreorder
= 1;
7793 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7795 expr1
.X_add_number
= 2;
7796 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7799 --mips_opts
.noreorder
;
7800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7807 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7817 if (imm_expr
.X_op
!= O_constant
)
7818 as_bad (_("Unsupported large constant"));
7819 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7820 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7821 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7825 if (imm_expr
.X_op
!= O_constant
)
7826 as_bad (_("Unsupported large constant"));
7827 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7828 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7833 if (imm_expr
.X_op
!= O_constant
)
7834 as_bad (_("Unsupported large constant"));
7835 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7836 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7859 goto do_reverse_branch
;
7863 goto do_reverse_branch
;
7875 goto do_reverse_branch
;
7886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7888 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7915 goto do_addone_branch_i
;
7920 goto do_addone_branch_i
;
7935 goto do_addone_branch_i
;
7942 if (imm_expr
.X_op
!= O_constant
)
7943 as_bad (_("Unsupported large constant"));
7944 ++imm_expr
.X_add_number
;
7947 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7952 expr1
.X_add_number
= 0;
7953 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7955 move_register (&icnt
, xreg
, yreg
);
7956 expr1
.X_add_number
= 2;
7957 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7958 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7959 "neg", "x,w", xreg
, xreg
);
7963 /* For consistency checking, verify that all bits are specified either
7964 by the match/mask part of the instruction definition, or by the
7967 validate_mips_insn (opc
)
7968 const struct mips_opcode
*opc
;
7970 const char *p
= opc
->args
;
7972 unsigned long used_bits
= opc
->mask
;
7974 if ((used_bits
& opc
->match
) != opc
->match
)
7976 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7977 opc
->name
, opc
->args
);
7980 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7990 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7991 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7992 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7993 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7994 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7996 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7997 c
, opc
->name
, opc
->args
);
8001 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8002 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8004 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8005 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8006 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8007 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8009 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8010 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8012 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8013 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8015 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8016 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8017 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8018 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8019 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8020 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8021 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8022 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8023 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8024 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8025 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8026 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8027 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8028 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8029 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8030 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8031 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8033 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8034 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8035 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8036 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8038 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8039 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8040 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8041 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8042 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8043 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8044 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8045 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8046 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8049 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8050 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8051 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8052 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8053 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8057 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8058 c
, opc
->name
, opc
->args
);
8062 if (used_bits
!= 0xffffffff)
8064 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8065 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8071 /* This routine assembles an instruction into its binary format. As a
8072 side effect, it sets one of the global variables imm_reloc or
8073 offset_reloc to the type of relocation to do if one of the operands
8074 is an address expression. */
8079 struct mips_cl_insn
*ip
;
8084 struct mips_opcode
*insn
;
8087 unsigned int lastregno
= 0;
8088 unsigned int lastpos
= 0;
8089 unsigned int limlo
, limhi
;
8095 /* If the instruction contains a '.', we first try to match an instruction
8096 including the '.'. Then we try again without the '.'. */
8098 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8101 /* If we stopped on whitespace, then replace the whitespace with null for
8102 the call to hash_find. Save the character we replaced just in case we
8103 have to re-parse the instruction. */
8110 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8112 /* If we didn't find the instruction in the opcode table, try again, but
8113 this time with just the instruction up to, but not including the
8117 /* Restore the character we overwrite above (if any). */
8121 /* Scan up to the first '.' or whitespace. */
8123 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8127 /* If we did not find a '.', then we can quit now. */
8130 insn_error
= "unrecognized opcode";
8134 /* Lookup the instruction in the hash table. */
8136 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8138 insn_error
= "unrecognized opcode";
8148 assert (strcmp (insn
->name
, str
) == 0);
8150 if (OPCODE_IS_MEMBER (insn
,
8152 | (file_ase_mips16
? INSN_MIPS16
: 0)
8153 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8154 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8160 if (insn
->pinfo
!= INSN_MACRO
)
8162 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8168 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8169 && strcmp (insn
->name
, insn
[1].name
) == 0)
8178 static char buf
[100];
8179 if (mips_arch_info
->is_isa
)
8181 _("opcode not supported at this ISA level (%s)"),
8182 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8185 _("opcode not supported on this processor: %s (%s)"),
8186 mips_arch_info
->name
,
8187 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8197 ip
->insn_opcode
= insn
->match
;
8199 for (args
= insn
->args
;; ++args
)
8203 s
+= strspn (s
, " \t");
8207 case '\0': /* end of args */
8220 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8224 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8228 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8232 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8238 /* Handle optional base register.
8239 Either the base register is omitted or
8240 we must have a left paren. */
8241 /* This is dependent on the next operand specifier
8242 is a base register specification. */
8243 assert (args
[1] == 'b' || args
[1] == '5'
8244 || args
[1] == '-' || args
[1] == '4');
8248 case ')': /* these must match exactly */
8255 case '+': /* Opcode extension character. */
8258 case 'A': /* ins/ext position, becomes LSB. */
8261 my_getExpression (&imm_expr
, s
);
8262 check_absolute_expr (ip
, &imm_expr
);
8263 if ((unsigned long) imm_expr
.X_add_number
< limlo
8264 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8266 as_bad (_("Improper position (%lu)"),
8267 (unsigned long) imm_expr
.X_add_number
);
8268 imm_expr
.X_add_number
= limlo
;
8270 lastpos
= imm_expr
.X_add_number
;
8271 ip
->insn_opcode
|= (imm_expr
.X_add_number
8272 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8273 imm_expr
.X_op
= O_absent
;
8277 case 'B': /* ins size, becomes MSB. */
8280 my_getExpression (&imm_expr
, s
);
8281 check_absolute_expr (ip
, &imm_expr
);
8282 /* Check for negative input so that small negative numbers
8283 will not succeed incorrectly. The checks against
8284 (pos+size) transitively check "size" itself,
8285 assuming that "pos" is reasonable. */
8286 if ((long) imm_expr
.X_add_number
< 0
8287 || ((unsigned long) imm_expr
.X_add_number
8289 || ((unsigned long) imm_expr
.X_add_number
8292 as_bad (_("Improper insert size (%lu, position %lu)"),
8293 (unsigned long) imm_expr
.X_add_number
,
8294 (unsigned long) lastpos
);
8295 imm_expr
.X_add_number
= limlo
- lastpos
;
8297 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8298 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8299 imm_expr
.X_op
= O_absent
;
8303 case 'C': /* ext size, becomes MSBD. */
8306 my_getExpression (&imm_expr
, s
);
8307 check_absolute_expr (ip
, &imm_expr
);
8308 /* Check for negative input so that small negative numbers
8309 will not succeed incorrectly. The checks against
8310 (pos+size) transitively check "size" itself,
8311 assuming that "pos" is reasonable. */
8312 if ((long) imm_expr
.X_add_number
< 0
8313 || ((unsigned long) imm_expr
.X_add_number
8315 || ((unsigned long) imm_expr
.X_add_number
8318 as_bad (_("Improper extract size (%lu, position %lu)"),
8319 (unsigned long) imm_expr
.X_add_number
,
8320 (unsigned long) lastpos
);
8321 imm_expr
.X_add_number
= limlo
- lastpos
;
8323 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8324 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8325 imm_expr
.X_op
= O_absent
;
8330 /* +D is for disassembly only; never match. */
8334 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8335 *args
, insn
->name
, insn
->args
);
8336 /* Further processing is fruitless. */
8341 case '<': /* must be at least one digit */
8343 * According to the manual, if the shift amount is greater
8344 * than 31 or less than 0, then the shift amount should be
8345 * mod 32. In reality the mips assembler issues an error.
8346 * We issue a warning and mask out all but the low 5 bits.
8348 my_getExpression (&imm_expr
, s
);
8349 check_absolute_expr (ip
, &imm_expr
);
8350 if ((unsigned long) imm_expr
.X_add_number
> 31)
8352 as_warn (_("Improper shift amount (%lu)"),
8353 (unsigned long) imm_expr
.X_add_number
);
8354 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8356 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8357 imm_expr
.X_op
= O_absent
;
8361 case '>': /* shift amount minus 32 */
8362 my_getExpression (&imm_expr
, s
);
8363 check_absolute_expr (ip
, &imm_expr
);
8364 if ((unsigned long) imm_expr
.X_add_number
< 32
8365 || (unsigned long) imm_expr
.X_add_number
> 63)
8367 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8368 imm_expr
.X_op
= O_absent
;
8372 case 'k': /* cache code */
8373 case 'h': /* prefx code */
8374 my_getExpression (&imm_expr
, s
);
8375 check_absolute_expr (ip
, &imm_expr
);
8376 if ((unsigned long) imm_expr
.X_add_number
> 31)
8378 as_warn (_("Invalid value for `%s' (%lu)"),
8380 (unsigned long) imm_expr
.X_add_number
);
8381 imm_expr
.X_add_number
&= 0x1f;
8384 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8386 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8387 imm_expr
.X_op
= O_absent
;
8391 case 'c': /* break code */
8392 my_getExpression (&imm_expr
, s
);
8393 check_absolute_expr (ip
, &imm_expr
);
8394 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8396 as_warn (_("Illegal break code (%lu)"),
8397 (unsigned long) imm_expr
.X_add_number
);
8398 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8400 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8401 imm_expr
.X_op
= O_absent
;
8405 case 'q': /* lower break code */
8406 my_getExpression (&imm_expr
, s
);
8407 check_absolute_expr (ip
, &imm_expr
);
8408 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8410 as_warn (_("Illegal lower break code (%lu)"),
8411 (unsigned long) imm_expr
.X_add_number
);
8412 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8414 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8415 imm_expr
.X_op
= O_absent
;
8419 case 'B': /* 20-bit syscall/break code. */
8420 my_getExpression (&imm_expr
, s
);
8421 check_absolute_expr (ip
, &imm_expr
);
8422 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8423 as_warn (_("Illegal 20-bit code (%lu)"),
8424 (unsigned long) imm_expr
.X_add_number
);
8425 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8426 imm_expr
.X_op
= O_absent
;
8430 case 'C': /* Coprocessor code */
8431 my_getExpression (&imm_expr
, s
);
8432 check_absolute_expr (ip
, &imm_expr
);
8433 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8435 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8436 (unsigned long) imm_expr
.X_add_number
);
8437 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8439 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8440 imm_expr
.X_op
= O_absent
;
8444 case 'J': /* 19-bit wait code. */
8445 my_getExpression (&imm_expr
, s
);
8446 check_absolute_expr (ip
, &imm_expr
);
8447 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8448 as_warn (_("Illegal 19-bit code (%lu)"),
8449 (unsigned long) imm_expr
.X_add_number
);
8450 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8451 imm_expr
.X_op
= O_absent
;
8455 case 'P': /* Performance register */
8456 my_getExpression (&imm_expr
, s
);
8457 check_absolute_expr (ip
, &imm_expr
);
8458 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8460 as_warn (_("Invalid performance register (%lu)"),
8461 (unsigned long) imm_expr
.X_add_number
);
8462 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8464 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8465 imm_expr
.X_op
= O_absent
;
8469 case 'b': /* base register */
8470 case 'd': /* destination register */
8471 case 's': /* source register */
8472 case 't': /* target register */
8473 case 'r': /* both target and source */
8474 case 'v': /* both dest and source */
8475 case 'w': /* both dest and target */
8476 case 'E': /* coprocessor target register */
8477 case 'G': /* coprocessor destination register */
8478 case 'K': /* 'rdhwr' destination register */
8479 case 'x': /* ignore register name */
8480 case 'z': /* must be zero register */
8481 case 'U': /* destination register (clo/clz). */
8496 while (ISDIGIT (*s
));
8498 as_bad (_("Invalid register number (%d)"), regno
);
8500 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8504 if (s
[1] == 'r' && s
[2] == 'a')
8509 else if (s
[1] == 'f' && s
[2] == 'p')
8514 else if (s
[1] == 's' && s
[2] == 'p')
8519 else if (s
[1] == 'g' && s
[2] == 'p')
8524 else if (s
[1] == 'a' && s
[2] == 't')
8529 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8534 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8539 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8544 else if (itbl_have_entries
)
8549 p
= s
+ 1; /* advance past '$' */
8550 n
= itbl_get_field (&p
); /* n is name */
8552 /* See if this is a register defined in an
8554 if (itbl_get_reg_val (n
, &r
))
8556 /* Get_field advances to the start of
8557 the next field, so we need to back
8558 rack to the end of the last field. */
8562 s
= strchr (s
, '\0');
8576 as_warn (_("Used $at without \".set noat\""));
8582 if (c
== 'r' || c
== 'v' || c
== 'w')
8589 /* 'z' only matches $0. */
8590 if (c
== 'z' && regno
!= 0)
8593 /* Now that we have assembled one operand, we use the args string
8594 * to figure out where it goes in the instruction. */
8601 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8606 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8609 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8610 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8615 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8618 /* This case exists because on the r3000 trunc
8619 expands into a macro which requires a gp
8620 register. On the r6000 or r4000 it is
8621 assembled into a single instruction which
8622 ignores the register. Thus the insn version
8623 is MIPS_ISA2 and uses 'x', and the macro
8624 version is MIPS_ISA1 and uses 't'. */
8627 /* This case is for the div instruction, which
8628 acts differently if the destination argument
8629 is $0. This only matches $0, and is checked
8630 outside the switch. */
8633 /* Itbl operand; not yet implemented. FIXME ?? */
8635 /* What about all other operands like 'i', which
8636 can be specified in the opcode table? */
8646 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8649 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8654 case 'O': /* MDMX alignment immediate constant. */
8655 my_getExpression (&imm_expr
, s
);
8656 check_absolute_expr (ip
, &imm_expr
);
8657 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8659 as_warn ("Improper align amount (%ld), using low bits",
8660 (long) imm_expr
.X_add_number
);
8661 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8663 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8664 imm_expr
.X_op
= O_absent
;
8668 case 'Q': /* MDMX vector, element sel, or const. */
8671 /* MDMX Immediate. */
8672 my_getExpression (&imm_expr
, s
);
8673 check_absolute_expr (ip
, &imm_expr
);
8674 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8676 as_warn (_("Invalid MDMX Immediate (%ld)"),
8677 (long) imm_expr
.X_add_number
);
8678 imm_expr
.X_add_number
&= OP_MASK_FT
;
8680 imm_expr
.X_add_number
&= OP_MASK_FT
;
8681 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8682 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8684 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8685 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8686 imm_expr
.X_op
= O_absent
;
8690 /* Not MDMX Immediate. Fall through. */
8691 case 'X': /* MDMX destination register. */
8692 case 'Y': /* MDMX source register. */
8693 case 'Z': /* MDMX target register. */
8695 case 'D': /* floating point destination register */
8696 case 'S': /* floating point source register */
8697 case 'T': /* floating point target register */
8698 case 'R': /* floating point source register */
8702 /* Accept $fN for FP and MDMX register numbers, and in
8703 addition accept $vN for MDMX register numbers. */
8704 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8705 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8716 while (ISDIGIT (*s
));
8719 as_bad (_("Invalid float register number (%d)"), regno
);
8721 if ((regno
& 1) != 0
8723 && ! (strcmp (str
, "mtc1") == 0
8724 || strcmp (str
, "mfc1") == 0
8725 || strcmp (str
, "lwc1") == 0
8726 || strcmp (str
, "swc1") == 0
8727 || strcmp (str
, "l.s") == 0
8728 || strcmp (str
, "s.s") == 0))
8729 as_warn (_("Float register should be even, was %d"),
8737 if (c
== 'V' || c
== 'W')
8748 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8753 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8756 /* This is like 'Z', but also needs to fix the MDMX
8757 vector/scalar select bits. Note that the
8758 scalar immediate case is handled above. */
8761 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8762 int max_el
= (is_qh
? 3 : 7);
8764 my_getExpression(&imm_expr
, s
);
8765 check_absolute_expr (ip
, &imm_expr
);
8767 if (imm_expr
.X_add_number
> max_el
)
8768 as_bad(_("Bad element selector %ld"),
8769 (long) imm_expr
.X_add_number
);
8770 imm_expr
.X_add_number
&= max_el
;
8771 ip
->insn_opcode
|= (imm_expr
.X_add_number
8775 as_warn(_("Expecting ']' found '%s'"), s
);
8781 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8782 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8785 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8792 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8795 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8805 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8808 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8814 my_getExpression (&imm_expr
, s
);
8815 if (imm_expr
.X_op
!= O_big
8816 && imm_expr
.X_op
!= O_constant
)
8817 insn_error
= _("absolute expression required");
8822 my_getExpression (&offset_expr
, s
);
8823 *imm_reloc
= BFD_RELOC_32
;
8836 unsigned char temp
[8];
8838 unsigned int length
;
8843 /* These only appear as the last operand in an
8844 instruction, and every instruction that accepts
8845 them in any variant accepts them in all variants.
8846 This means we don't have to worry about backing out
8847 any changes if the instruction does not match.
8849 The difference between them is the size of the
8850 floating point constant and where it goes. For 'F'
8851 and 'L' the constant is 64 bits; for 'f' and 'l' it
8852 is 32 bits. Where the constant is placed is based
8853 on how the MIPS assembler does things:
8856 f -- immediate value
8859 The .lit4 and .lit8 sections are only used if
8860 permitted by the -G argument.
8862 When generating embedded PIC code, we use the
8863 .lit8 section but not the .lit4 section (we can do
8864 .lit4 inline easily; we need to put .lit8
8865 somewhere in the data segment, and using .lit8
8866 permits the linker to eventually combine identical
8869 The code below needs to know whether the target register
8870 is 32 or 64 bits wide. It relies on the fact 'f' and
8871 'F' are used with GPR-based instructions and 'l' and
8872 'L' are used with FPR-based instructions. */
8874 f64
= *args
== 'F' || *args
== 'L';
8875 using_gprs
= *args
== 'F' || *args
== 'f';
8877 save_in
= input_line_pointer
;
8878 input_line_pointer
= s
;
8879 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8881 s
= input_line_pointer
;
8882 input_line_pointer
= save_in
;
8883 if (err
!= NULL
&& *err
!= '\0')
8885 as_bad (_("Bad floating point constant: %s"), err
);
8886 memset (temp
, '\0', sizeof temp
);
8887 length
= f64
? 8 : 4;
8890 assert (length
== (unsigned) (f64
? 8 : 4));
8894 && (! USE_GLOBAL_POINTER_OPT
8895 || mips_pic
== EMBEDDED_PIC
8896 || g_switch_value
< 4
8897 || (temp
[0] == 0 && temp
[1] == 0)
8898 || (temp
[2] == 0 && temp
[3] == 0))))
8900 imm_expr
.X_op
= O_constant
;
8901 if (! target_big_endian
)
8902 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8904 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8907 && ! mips_disable_float_construction
8908 /* Constants can only be constructed in GPRs and
8909 copied to FPRs if the GPRs are at least as wide
8910 as the FPRs. Force the constant into memory if
8911 we are using 64-bit FPRs but the GPRs are only
8914 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8915 && ((temp
[0] == 0 && temp
[1] == 0)
8916 || (temp
[2] == 0 && temp
[3] == 0))
8917 && ((temp
[4] == 0 && temp
[5] == 0)
8918 || (temp
[6] == 0 && temp
[7] == 0)))
8920 /* The value is simple enough to load with a couple of
8921 instructions. If using 32-bit registers, set
8922 imm_expr to the high order 32 bits and offset_expr to
8923 the low order 32 bits. Otherwise, set imm_expr to
8924 the entire 64 bit constant. */
8925 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8927 imm_expr
.X_op
= O_constant
;
8928 offset_expr
.X_op
= O_constant
;
8929 if (! target_big_endian
)
8931 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8932 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8936 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8937 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8939 if (offset_expr
.X_add_number
== 0)
8940 offset_expr
.X_op
= O_absent
;
8942 else if (sizeof (imm_expr
.X_add_number
) > 4)
8944 imm_expr
.X_op
= O_constant
;
8945 if (! target_big_endian
)
8946 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8948 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8952 imm_expr
.X_op
= O_big
;
8953 imm_expr
.X_add_number
= 4;
8954 if (! target_big_endian
)
8956 generic_bignum
[0] = bfd_getl16 (temp
);
8957 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8958 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8959 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8963 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8964 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8965 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8966 generic_bignum
[3] = bfd_getb16 (temp
);
8972 const char *newname
;
8975 /* Switch to the right section. */
8977 subseg
= now_subseg
;
8980 default: /* unused default case avoids warnings. */
8982 newname
= RDATA_SECTION_NAME
;
8983 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8984 || mips_pic
== EMBEDDED_PIC
)
8988 if (mips_pic
== EMBEDDED_PIC
)
8991 newname
= RDATA_SECTION_NAME
;
8994 assert (!USE_GLOBAL_POINTER_OPT
8995 || g_switch_value
>= 4);
8999 new_seg
= subseg_new (newname
, (subsegT
) 0);
9000 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9001 bfd_set_section_flags (stdoutput
, new_seg
,
9006 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9007 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9008 && strcmp (TARGET_OS
, "elf") != 0)
9009 record_alignment (new_seg
, 4);
9011 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9013 as_bad (_("Can't use floating point insn in this section"));
9015 /* Set the argument to the current address in the
9017 offset_expr
.X_op
= O_symbol
;
9018 offset_expr
.X_add_symbol
=
9019 symbol_new ("L0\001", now_seg
,
9020 (valueT
) frag_now_fix (), frag_now
);
9021 offset_expr
.X_add_number
= 0;
9023 /* Put the floating point number into the section. */
9024 p
= frag_more ((int) length
);
9025 memcpy (p
, temp
, length
);
9027 /* Switch back to the original section. */
9028 subseg_set (seg
, subseg
);
9033 case 'i': /* 16 bit unsigned immediate */
9034 case 'j': /* 16 bit signed immediate */
9035 *imm_reloc
= BFD_RELOC_LO16
;
9036 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9039 offsetT minval
, maxval
;
9041 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9042 && strcmp (insn
->name
, insn
[1].name
) == 0);
9044 /* If the expression was written as an unsigned number,
9045 only treat it as signed if there are no more
9049 && sizeof (imm_expr
.X_add_number
) <= 4
9050 && imm_expr
.X_op
== O_constant
9051 && imm_expr
.X_add_number
< 0
9052 && imm_expr
.X_unsigned
9056 /* For compatibility with older assemblers, we accept
9057 0x8000-0xffff as signed 16-bit numbers when only
9058 signed numbers are allowed. */
9060 minval
= 0, maxval
= 0xffff;
9062 minval
= -0x8000, maxval
= 0x7fff;
9064 minval
= -0x8000, maxval
= 0xffff;
9066 if (imm_expr
.X_op
!= O_constant
9067 || imm_expr
.X_add_number
< minval
9068 || imm_expr
.X_add_number
> maxval
)
9072 if (imm_expr
.X_op
== O_constant
9073 || imm_expr
.X_op
== O_big
)
9074 as_bad (_("expression out of range"));
9080 case 'o': /* 16 bit offset */
9081 /* Check whether there is only a single bracketed expression
9082 left. If so, it must be the base register and the
9083 constant must be zero. */
9084 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9086 offset_expr
.X_op
= O_constant
;
9087 offset_expr
.X_add_number
= 0;
9091 /* If this value won't fit into a 16 bit offset, then go
9092 find a macro that will generate the 32 bit offset
9094 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9095 && (offset_expr
.X_op
!= O_constant
9096 || offset_expr
.X_add_number
>= 0x8000
9097 || offset_expr
.X_add_number
< -0x8000))
9103 case 'p': /* pc relative offset */
9104 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9105 my_getExpression (&offset_expr
, s
);
9109 case 'u': /* upper 16 bits */
9110 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9111 && imm_expr
.X_op
== O_constant
9112 && (imm_expr
.X_add_number
< 0
9113 || imm_expr
.X_add_number
>= 0x10000))
9114 as_bad (_("lui expression not in range 0..65535"));
9118 case 'a': /* 26 bit address */
9119 my_getExpression (&offset_expr
, s
);
9121 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9124 case 'N': /* 3 bit branch condition code */
9125 case 'M': /* 3 bit compare condition code */
9126 if (strncmp (s
, "$fcc", 4) != 0)
9136 while (ISDIGIT (*s
));
9138 as_bad (_("invalid condition code register $fcc%d"), regno
);
9140 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9142 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9146 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9157 while (ISDIGIT (*s
));
9160 c
= 8; /* Invalid sel value. */
9163 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9164 ip
->insn_opcode
|= c
;
9168 /* Must be at least one digit. */
9169 my_getExpression (&imm_expr
, s
);
9170 check_absolute_expr (ip
, &imm_expr
);
9172 if ((unsigned long) imm_expr
.X_add_number
9173 > (unsigned long) OP_MASK_VECBYTE
)
9175 as_bad (_("bad byte vector index (%ld)"),
9176 (long) imm_expr
.X_add_number
);
9177 imm_expr
.X_add_number
= 0;
9180 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9181 imm_expr
.X_op
= O_absent
;
9186 my_getExpression (&imm_expr
, s
);
9187 check_absolute_expr (ip
, &imm_expr
);
9189 if ((unsigned long) imm_expr
.X_add_number
9190 > (unsigned long) OP_MASK_VECALIGN
)
9192 as_bad (_("bad byte vector index (%ld)"),
9193 (long) imm_expr
.X_add_number
);
9194 imm_expr
.X_add_number
= 0;
9197 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9198 imm_expr
.X_op
= O_absent
;
9203 as_bad (_("bad char = '%c'\n"), *args
);
9208 /* Args don't match. */
9209 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9210 !strcmp (insn
->name
, insn
[1].name
))
9214 insn_error
= _("illegal operands");
9219 insn_error
= _("illegal operands");
9224 /* This routine assembles an instruction into its binary format when
9225 assembling for the mips16. As a side effect, it sets one of the
9226 global variables imm_reloc or offset_reloc to the type of
9227 relocation to do if one of the operands is an address expression.
9228 It also sets mips16_small and mips16_ext if the user explicitly
9229 requested a small or extended instruction. */
9234 struct mips_cl_insn
*ip
;
9238 struct mips_opcode
*insn
;
9241 unsigned int lastregno
= 0;
9246 mips16_small
= FALSE
;
9249 for (s
= str
; ISLOWER (*s
); ++s
)
9261 if (s
[1] == 't' && s
[2] == ' ')
9264 mips16_small
= TRUE
;
9268 else if (s
[1] == 'e' && s
[2] == ' ')
9277 insn_error
= _("unknown opcode");
9281 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9282 mips16_small
= TRUE
;
9284 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9286 insn_error
= _("unrecognized opcode");
9293 assert (strcmp (insn
->name
, str
) == 0);
9296 ip
->insn_opcode
= insn
->match
;
9297 ip
->use_extend
= FALSE
;
9298 imm_expr
.X_op
= O_absent
;
9299 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9300 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9301 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9302 offset_expr
.X_op
= O_absent
;
9303 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9304 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9305 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9306 for (args
= insn
->args
; 1; ++args
)
9313 /* In this switch statement we call break if we did not find
9314 a match, continue if we did find a match, or return if we
9323 /* Stuff the immediate value in now, if we can. */
9324 if (imm_expr
.X_op
== O_constant
9325 && *imm_reloc
> BFD_RELOC_UNUSED
9326 && insn
->pinfo
!= INSN_MACRO
)
9328 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9329 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9330 mips16_ext
, &ip
->insn_opcode
,
9331 &ip
->use_extend
, &ip
->extend
);
9332 imm_expr
.X_op
= O_absent
;
9333 *imm_reloc
= BFD_RELOC_UNUSED
;
9347 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9350 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9366 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9368 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9395 while (ISDIGIT (*s
));
9398 as_bad (_("invalid register number (%d)"), regno
);
9404 if (s
[1] == 'r' && s
[2] == 'a')
9409 else if (s
[1] == 'f' && s
[2] == 'p')
9414 else if (s
[1] == 's' && s
[2] == 'p')
9419 else if (s
[1] == 'g' && s
[2] == 'p')
9424 else if (s
[1] == 'a' && s
[2] == 't')
9429 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9434 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9439 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9452 if (c
== 'v' || c
== 'w')
9454 regno
= mips16_to_32_reg_map
[lastregno
];
9468 regno
= mips32_to_16_reg_map
[regno
];
9473 regno
= ILLEGAL_REG
;
9478 regno
= ILLEGAL_REG
;
9483 regno
= ILLEGAL_REG
;
9488 if (regno
== AT
&& ! mips_opts
.noat
)
9489 as_warn (_("used $at without \".set noat\""));
9496 if (regno
== ILLEGAL_REG
)
9503 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9507 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9510 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9513 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9519 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9522 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9523 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9533 if (strncmp (s
, "$pc", 3) == 0)
9557 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9559 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9560 and generate the appropriate reloc. If the text
9561 inside %gprel is not a symbol name with an
9562 optional offset, then we generate a normal reloc
9563 and will probably fail later. */
9564 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9565 if (imm_expr
.X_op
== O_symbol
)
9568 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9570 ip
->use_extend
= TRUE
;
9577 /* Just pick up a normal expression. */
9578 my_getExpression (&imm_expr
, s
);
9581 if (imm_expr
.X_op
== O_register
)
9583 /* What we thought was an expression turned out to
9586 if (s
[0] == '(' && args
[1] == '(')
9588 /* It looks like the expression was omitted
9589 before a register indirection, which means
9590 that the expression is implicitly zero. We
9591 still set up imm_expr, so that we handle
9592 explicit extensions correctly. */
9593 imm_expr
.X_op
= O_constant
;
9594 imm_expr
.X_add_number
= 0;
9595 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9602 /* We need to relax this instruction. */
9603 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9612 /* We use offset_reloc rather than imm_reloc for the PC
9613 relative operands. This lets macros with both
9614 immediate and address operands work correctly. */
9615 my_getExpression (&offset_expr
, s
);
9617 if (offset_expr
.X_op
== O_register
)
9620 /* We need to relax this instruction. */
9621 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9625 case '6': /* break code */
9626 my_getExpression (&imm_expr
, s
);
9627 check_absolute_expr (ip
, &imm_expr
);
9628 if ((unsigned long) imm_expr
.X_add_number
> 63)
9630 as_warn (_("Invalid value for `%s' (%lu)"),
9632 (unsigned long) imm_expr
.X_add_number
);
9633 imm_expr
.X_add_number
&= 0x3f;
9635 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9636 imm_expr
.X_op
= O_absent
;
9640 case 'a': /* 26 bit address */
9641 my_getExpression (&offset_expr
, s
);
9643 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9644 ip
->insn_opcode
<<= 16;
9647 case 'l': /* register list for entry macro */
9648 case 'L': /* register list for exit macro */
9658 int freg
, reg1
, reg2
;
9660 while (*s
== ' ' || *s
== ',')
9664 as_bad (_("can't parse register list"));
9676 while (ISDIGIT (*s
))
9698 as_bad (_("invalid register list"));
9703 while (ISDIGIT (*s
))
9710 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9715 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9720 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9721 mask
|= (reg2
- 3) << 3;
9722 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9723 mask
|= (reg2
- 15) << 1;
9724 else if (reg1
== RA
&& reg2
== RA
)
9728 as_bad (_("invalid register list"));
9732 /* The mask is filled in in the opcode table for the
9733 benefit of the disassembler. We remove it before
9734 applying the actual mask. */
9735 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9736 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9740 case 'e': /* extend code */
9741 my_getExpression (&imm_expr
, s
);
9742 check_absolute_expr (ip
, &imm_expr
);
9743 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9745 as_warn (_("Invalid value for `%s' (%lu)"),
9747 (unsigned long) imm_expr
.X_add_number
);
9748 imm_expr
.X_add_number
&= 0x7ff;
9750 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9751 imm_expr
.X_op
= O_absent
;
9761 /* Args don't match. */
9762 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9763 strcmp (insn
->name
, insn
[1].name
) == 0)
9770 insn_error
= _("illegal operands");
9776 /* This structure holds information we know about a mips16 immediate
9779 struct mips16_immed_operand
9781 /* The type code used in the argument string in the opcode table. */
9783 /* The number of bits in the short form of the opcode. */
9785 /* The number of bits in the extended form of the opcode. */
9787 /* The amount by which the short form is shifted when it is used;
9788 for example, the sw instruction has a shift count of 2. */
9790 /* The amount by which the short form is shifted when it is stored
9791 into the instruction code. */
9793 /* Non-zero if the short form is unsigned. */
9795 /* Non-zero if the extended form is unsigned. */
9797 /* Non-zero if the value is PC relative. */
9801 /* The mips16 immediate operand types. */
9803 static const struct mips16_immed_operand mips16_immed_operands
[] =
9805 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9806 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9807 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9808 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9809 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9810 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9811 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9812 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9813 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9814 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9815 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9816 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9817 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9818 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9819 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9820 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9821 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9822 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9823 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9824 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9825 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9828 #define MIPS16_NUM_IMMED \
9829 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9831 /* Handle a mips16 instruction with an immediate value. This or's the
9832 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9833 whether an extended value is needed; if one is needed, it sets
9834 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9835 If SMALL is true, an unextended opcode was explicitly requested.
9836 If EXT is true, an extended opcode was explicitly requested. If
9837 WARN is true, warn if EXT does not match reality. */
9840 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9849 unsigned long *insn
;
9850 bfd_boolean
*use_extend
;
9851 unsigned short *extend
;
9853 register const struct mips16_immed_operand
*op
;
9854 int mintiny
, maxtiny
;
9855 bfd_boolean needext
;
9857 op
= mips16_immed_operands
;
9858 while (op
->type
!= type
)
9861 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9866 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9869 maxtiny
= 1 << op
->nbits
;
9874 maxtiny
= (1 << op
->nbits
) - 1;
9879 mintiny
= - (1 << (op
->nbits
- 1));
9880 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9883 /* Branch offsets have an implicit 0 in the lowest bit. */
9884 if (type
== 'p' || type
== 'q')
9887 if ((val
& ((1 << op
->shift
) - 1)) != 0
9888 || val
< (mintiny
<< op
->shift
)
9889 || val
> (maxtiny
<< op
->shift
))
9894 if (warn
&& ext
&& ! needext
)
9895 as_warn_where (file
, line
,
9896 _("extended operand requested but not required"));
9897 if (small
&& needext
)
9898 as_bad_where (file
, line
, _("invalid unextended operand value"));
9900 if (small
|| (! ext
&& ! needext
))
9904 *use_extend
= FALSE
;
9905 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9906 insnval
<<= op
->op_shift
;
9911 long minext
, maxext
;
9917 maxext
= (1 << op
->extbits
) - 1;
9921 minext
= - (1 << (op
->extbits
- 1));
9922 maxext
= (1 << (op
->extbits
- 1)) - 1;
9924 if (val
< minext
|| val
> maxext
)
9925 as_bad_where (file
, line
,
9926 _("operand value out of range for instruction"));
9929 if (op
->extbits
== 16)
9931 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9934 else if (op
->extbits
== 15)
9936 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9941 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9945 *extend
= (unsigned short) extval
;
9950 static const struct percent_op_match
9953 bfd_reloc_code_real_type reloc
;
9956 {"%lo", BFD_RELOC_LO16
},
9958 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9959 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9960 {"%call16", BFD_RELOC_MIPS_CALL16
},
9961 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9962 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9963 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9964 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9965 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9966 {"%got", BFD_RELOC_MIPS_GOT16
},
9967 {"%gp_rel", BFD_RELOC_GPREL16
},
9968 {"%half", BFD_RELOC_16
},
9969 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9970 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9971 {"%neg", BFD_RELOC_MIPS_SUB
},
9973 {"%hi", BFD_RELOC_HI16_S
}
9977 /* Return true if *STR points to a relocation operator. When returning true,
9978 move *STR over the operator and store its relocation code in *RELOC.
9979 Leave both *STR and *RELOC alone when returning false. */
9982 parse_relocation (str
, reloc
)
9984 bfd_reloc_code_real_type
*reloc
;
9988 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9989 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9991 *str
+= strlen (percent_op
[i
].str
);
9992 *reloc
= percent_op
[i
].reloc
;
9994 /* Check whether the output BFD supports this relocation.
9995 If not, issue an error and fall back on something safe. */
9996 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9998 as_bad ("relocation %s isn't supported by the current ABI",
10000 *reloc
= BFD_RELOC_LO16
;
10008 /* Parse string STR as a 16-bit relocatable operand. Store the
10009 expression in *EP and the relocations in the array starting
10010 at RELOC. Return the number of relocation operators used.
10012 On exit, EXPR_END points to the first character after the expression.
10013 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10016 my_getSmallExpression (ep
, reloc
, str
)
10018 bfd_reloc_code_real_type
*reloc
;
10021 bfd_reloc_code_real_type reversed_reloc
[3];
10022 size_t reloc_index
, i
;
10023 int crux_depth
, str_depth
;
10026 /* Search for the start of the main expression, recoding relocations
10027 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10028 of the main expression and with CRUX_DEPTH containing the number
10029 of open brackets at that point. */
10036 crux_depth
= str_depth
;
10038 /* Skip over whitespace and brackets, keeping count of the number
10040 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10045 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10046 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10048 my_getExpression (ep
, crux
);
10051 /* Match every open bracket. */
10052 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10056 if (crux_depth
> 0)
10057 as_bad ("unclosed '('");
10061 reloc
[0] = BFD_RELOC_LO16
;
10062 for (i
= 0; i
< reloc_index
; i
++)
10063 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10065 return reloc_index
;
10069 my_getExpression (ep
, str
)
10076 save_in
= input_line_pointer
;
10077 input_line_pointer
= str
;
10079 expr_end
= input_line_pointer
;
10080 input_line_pointer
= save_in
;
10082 /* If we are in mips16 mode, and this is an expression based on `.',
10083 then we bump the value of the symbol by 1 since that is how other
10084 text symbols are handled. We don't bother to handle complex
10085 expressions, just `.' plus or minus a constant. */
10086 if (mips_opts
.mips16
10087 && ep
->X_op
== O_symbol
10088 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10089 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10090 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10091 && symbol_constant_p (ep
->X_add_symbol
)
10092 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10093 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10096 /* Turn a string in input_line_pointer into a floating point constant
10097 of type TYPE, and store the appropriate bytes in *LITP. The number
10098 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10099 returned, or NULL on OK. */
10102 md_atof (type
, litP
, sizeP
)
10108 LITTLENUM_TYPE words
[4];
10124 return _("bad call to md_atof");
10127 t
= atof_ieee (input_line_pointer
, type
, words
);
10129 input_line_pointer
= t
;
10133 if (! target_big_endian
)
10135 for (i
= prec
- 1; i
>= 0; i
--)
10137 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10143 for (i
= 0; i
< prec
; i
++)
10145 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10154 md_number_to_chars (buf
, val
, n
)
10159 if (target_big_endian
)
10160 number_to_chars_bigendian (buf
, val
, n
);
10162 number_to_chars_littleendian (buf
, val
, n
);
10166 static int support_64bit_objects(void)
10168 const char **list
, **l
;
10171 list
= bfd_target_list ();
10172 for (l
= list
; *l
!= NULL
; l
++)
10174 /* This is traditional mips */
10175 if (strcmp (*l
, "elf64-tradbigmips") == 0
10176 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10178 if (strcmp (*l
, "elf64-bigmips") == 0
10179 || strcmp (*l
, "elf64-littlemips") == 0)
10182 yes
= (*l
!= NULL
);
10186 #endif /* OBJ_ELF */
10188 const char *md_shortopts
= "nO::g::G:";
10190 struct option md_longopts
[] =
10192 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10193 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10194 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10195 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10196 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10197 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10198 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10199 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10200 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10201 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10202 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10203 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10204 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10205 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10206 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10207 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10208 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10209 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10210 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10211 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10212 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10213 {"break", no_argument
, NULL
, OPTION_BREAK
},
10214 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10215 #define OPTION_EB (OPTION_MD_BASE + 11)
10216 {"EB", no_argument
, NULL
, OPTION_EB
},
10217 #define OPTION_EL (OPTION_MD_BASE + 12)
10218 {"EL", no_argument
, NULL
, OPTION_EL
},
10219 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10220 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10221 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10222 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10223 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10224 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10225 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10226 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10227 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10228 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10229 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10230 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10231 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10232 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10233 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10234 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10235 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10236 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10237 {"march", required_argument
, NULL
, OPTION_MARCH
},
10238 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10239 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10240 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10241 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10242 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10243 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10244 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10245 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10246 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10247 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10248 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10249 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10250 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10251 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10252 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10253 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10254 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10255 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10256 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10257 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10258 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10259 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10260 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10261 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10262 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10263 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10264 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10265 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10266 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10267 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10268 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10269 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10270 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10271 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10272 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10273 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10274 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10275 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10276 #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41)
10277 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10279 #define OPTION_ELF_BASE (OPTION_MD_BASE + 42)
10280 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10281 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10282 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10283 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10284 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10285 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10286 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10287 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10288 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10289 #define OPTION_32 (OPTION_ELF_BASE + 4)
10290 {"32", no_argument
, NULL
, OPTION_32
},
10291 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10292 {"n32", no_argument
, NULL
, OPTION_N32
},
10293 #define OPTION_64 (OPTION_ELF_BASE + 6)
10294 {"64", no_argument
, NULL
, OPTION_64
},
10295 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10296 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10297 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10298 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10299 #endif /* OBJ_ELF */
10300 {NULL
, no_argument
, NULL
, 0}
10302 size_t md_longopts_size
= sizeof (md_longopts
);
10304 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10305 NEW_VALUE. Warn if another value was already specified. Note:
10306 we have to defer parsing the -march and -mtune arguments in order
10307 to handle 'from-abi' correctly, since the ABI might be specified
10308 in a later argument. */
10311 mips_set_option_string (string_ptr
, new_value
)
10312 const char **string_ptr
, *new_value
;
10314 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10315 as_warn (_("A different %s was already specified, is now %s"),
10316 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10319 *string_ptr
= new_value
;
10323 md_parse_option (c
, arg
)
10329 case OPTION_CONSTRUCT_FLOATS
:
10330 mips_disable_float_construction
= 0;
10333 case OPTION_NO_CONSTRUCT_FLOATS
:
10334 mips_disable_float_construction
= 1;
10346 target_big_endian
= 1;
10350 target_big_endian
= 0;
10358 if (arg
&& arg
[1] == '0')
10368 mips_debug
= atoi (arg
);
10369 /* When the MIPS assembler sees -g or -g2, it does not do
10370 optimizations which limit full symbolic debugging. We take
10371 that to be equivalent to -O0. */
10372 if (mips_debug
== 2)
10377 file_mips_isa
= ISA_MIPS1
;
10381 file_mips_isa
= ISA_MIPS2
;
10385 file_mips_isa
= ISA_MIPS3
;
10389 file_mips_isa
= ISA_MIPS4
;
10393 file_mips_isa
= ISA_MIPS5
;
10396 case OPTION_MIPS32
:
10397 file_mips_isa
= ISA_MIPS32
;
10400 case OPTION_MIPS32R2
:
10401 file_mips_isa
= ISA_MIPS32R2
;
10404 case OPTION_MIPS64
:
10405 file_mips_isa
= ISA_MIPS64
;
10409 mips_set_option_string (&mips_tune_string
, arg
);
10413 mips_set_option_string (&mips_arch_string
, arg
);
10417 mips_set_option_string (&mips_arch_string
, "4650");
10418 mips_set_option_string (&mips_tune_string
, "4650");
10421 case OPTION_NO_M4650
:
10425 mips_set_option_string (&mips_arch_string
, "4010");
10426 mips_set_option_string (&mips_tune_string
, "4010");
10429 case OPTION_NO_M4010
:
10433 mips_set_option_string (&mips_arch_string
, "4100");
10434 mips_set_option_string (&mips_tune_string
, "4100");
10437 case OPTION_NO_M4100
:
10441 mips_set_option_string (&mips_arch_string
, "3900");
10442 mips_set_option_string (&mips_tune_string
, "3900");
10445 case OPTION_NO_M3900
:
10449 mips_opts
.ase_mdmx
= 1;
10452 case OPTION_NO_MDMX
:
10453 mips_opts
.ase_mdmx
= 0;
10456 case OPTION_MIPS16
:
10457 mips_opts
.mips16
= 1;
10458 mips_no_prev_insn (FALSE
);
10461 case OPTION_NO_MIPS16
:
10462 mips_opts
.mips16
= 0;
10463 mips_no_prev_insn (FALSE
);
10466 case OPTION_MIPS3D
:
10467 mips_opts
.ase_mips3d
= 1;
10470 case OPTION_NO_MIPS3D
:
10471 mips_opts
.ase_mips3d
= 0;
10474 case OPTION_MEMBEDDED_PIC
:
10475 mips_pic
= EMBEDDED_PIC
;
10476 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10478 as_bad (_("-G may not be used with embedded PIC code"));
10481 g_switch_value
= 0x7fffffff;
10484 case OPTION_FIX_VR4122
:
10485 mips_fix_4122_bugs
= 1;
10488 case OPTION_NO_FIX_VR4122
:
10489 mips_fix_4122_bugs
= 0;
10492 case OPTION_RELAX_BRANCH
:
10493 mips_relax_branch
= 1;
10496 case OPTION_NO_RELAX_BRANCH
:
10497 mips_relax_branch
= 0;
10501 /* When generating ELF code, we permit -KPIC and -call_shared to
10502 select SVR4_PIC, and -non_shared to select no PIC. This is
10503 intended to be compatible with Irix 5. */
10504 case OPTION_CALL_SHARED
:
10505 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10507 as_bad (_("-call_shared is supported only for ELF format"));
10510 mips_pic
= SVR4_PIC
;
10511 if (g_switch_seen
&& g_switch_value
!= 0)
10513 as_bad (_("-G may not be used with SVR4 PIC code"));
10516 g_switch_value
= 0;
10519 case OPTION_NON_SHARED
:
10520 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10522 as_bad (_("-non_shared is supported only for ELF format"));
10528 /* The -xgot option tells the assembler to use 32 offsets when
10529 accessing the got in SVR4_PIC mode. It is for Irix
10534 #endif /* OBJ_ELF */
10537 if (! USE_GLOBAL_POINTER_OPT
)
10539 as_bad (_("-G is not supported for this configuration"));
10542 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10544 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10548 g_switch_value
= atoi (arg
);
10553 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10556 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10558 as_bad (_("-32 is supported for ELF format only"));
10561 mips_abi
= O32_ABI
;
10565 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10567 as_bad (_("-n32 is supported for ELF format only"));
10570 mips_abi
= N32_ABI
;
10574 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10576 as_bad (_("-64 is supported for ELF format only"));
10579 mips_abi
= N64_ABI
;
10580 if (! support_64bit_objects())
10581 as_fatal (_("No compiled in support for 64 bit object file format"));
10583 #endif /* OBJ_ELF */
10586 file_mips_gp32
= 1;
10590 file_mips_gp32
= 0;
10594 file_mips_fp32
= 1;
10598 file_mips_fp32
= 0;
10603 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10605 as_bad (_("-mabi is supported for ELF format only"));
10608 if (strcmp (arg
, "32") == 0)
10609 mips_abi
= O32_ABI
;
10610 else if (strcmp (arg
, "o64") == 0)
10611 mips_abi
= O64_ABI
;
10612 else if (strcmp (arg
, "n32") == 0)
10613 mips_abi
= N32_ABI
;
10614 else if (strcmp (arg
, "64") == 0)
10616 mips_abi
= N64_ABI
;
10617 if (! support_64bit_objects())
10618 as_fatal (_("No compiled in support for 64 bit object file "
10621 else if (strcmp (arg
, "eabi") == 0)
10622 mips_abi
= EABI_ABI
;
10625 as_fatal (_("invalid abi -mabi=%s"), arg
);
10629 #endif /* OBJ_ELF */
10631 case OPTION_M7000_HILO_FIX
:
10632 mips_7000_hilo_fix
= TRUE
;
10635 case OPTION_MNO_7000_HILO_FIX
:
10636 mips_7000_hilo_fix
= FALSE
;
10640 case OPTION_MDEBUG
:
10641 mips_flag_mdebug
= TRUE
;
10644 case OPTION_NO_MDEBUG
:
10645 mips_flag_mdebug
= FALSE
;
10647 #endif /* OBJ_ELF */
10656 /* Set up globals to generate code for the ISA or processor
10657 described by INFO. */
10660 mips_set_architecture (info
)
10661 const struct mips_cpu_info
*info
;
10665 mips_arch_info
= info
;
10666 mips_arch
= info
->cpu
;
10667 mips_opts
.isa
= info
->isa
;
10672 /* Likewise for tuning. */
10675 mips_set_tune (info
)
10676 const struct mips_cpu_info
*info
;
10680 mips_tune_info
= info
;
10681 mips_tune
= info
->cpu
;
10687 mips_after_parse_args ()
10689 /* GP relative stuff not working for PE */
10690 if (strncmp (TARGET_OS
, "pe", 2) == 0
10691 && g_switch_value
!= 0)
10694 as_bad (_("-G not supported in this configuration."));
10695 g_switch_value
= 0;
10698 /* The following code determines the architecture and register size.
10699 Similar code was added to GCC 3.3 (see override_options() in
10700 config/mips/mips.c). The GAS and GCC code should be kept in sync
10701 as much as possible. */
10703 if (mips_arch_string
!= 0)
10704 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10706 if (mips_tune_string
!= 0)
10707 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10709 if (file_mips_isa
!= ISA_UNKNOWN
)
10711 /* Handle -mipsN. At this point, file_mips_isa contains the
10712 ISA level specified by -mipsN, while mips_opts.isa contains
10713 the -march selection (if any). */
10714 if (mips_arch_info
!= 0)
10716 /* -march takes precedence over -mipsN, since it is more descriptive.
10717 There's no harm in specifying both as long as the ISA levels
10719 if (file_mips_isa
!= mips_opts
.isa
)
10720 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10721 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10722 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10725 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10728 if (mips_arch_info
== 0)
10729 mips_set_architecture (mips_parse_cpu ("default CPU",
10730 MIPS_CPU_STRING_DEFAULT
));
10732 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10733 as_bad ("-march=%s is not compatible with the selected ABI",
10734 mips_arch_info
->name
);
10736 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10737 if (mips_tune_info
== 0)
10738 mips_set_tune (mips_arch_info
);
10740 if (file_mips_gp32
>= 0)
10742 /* The user specified the size of the integer registers. Make sure
10743 it agrees with the ABI and ISA. */
10744 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10745 as_bad (_("-mgp64 used with a 32-bit processor"));
10746 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10747 as_bad (_("-mgp32 used with a 64-bit ABI"));
10748 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10749 as_bad (_("-mgp64 used with a 32-bit ABI"));
10753 /* Infer the integer register size from the ABI and processor.
10754 Restrict ourselves to 32-bit registers if that's all the
10755 processor has, or if the ABI cannot handle 64-bit registers. */
10756 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10757 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10760 /* ??? GAS treats single-float processors as though they had 64-bit
10761 float registers (although it complains when double-precision
10762 instructions are used). As things stand, saying they have 32-bit
10763 registers would lead to spurious "register must be even" messages.
10764 So here we assume float registers are always the same size as
10765 integer ones, unless the user says otherwise. */
10766 if (file_mips_fp32
< 0)
10767 file_mips_fp32
= file_mips_gp32
;
10769 /* End of GCC-shared inference code. */
10771 /* ??? When do we want this flag to be set? Who uses it? */
10772 if (file_mips_gp32
== 1
10773 && mips_abi
== NO_ABI
10774 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10775 mips_32bitmode
= 1;
10777 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10778 as_bad (_("trap exception not supported at ISA 1"));
10780 /* If the selected architecture includes support for ASEs, enable
10781 generation of code for them. */
10782 if (mips_opts
.mips16
== -1)
10783 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10784 if (mips_opts
.ase_mips3d
== -1)
10785 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10786 if (mips_opts
.ase_mdmx
== -1)
10787 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10789 file_mips_isa
= mips_opts
.isa
;
10790 file_ase_mips16
= mips_opts
.mips16
;
10791 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10792 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10793 mips_opts
.gp32
= file_mips_gp32
;
10794 mips_opts
.fp32
= file_mips_fp32
;
10796 if (mips_flag_mdebug
< 0)
10798 #ifdef OBJ_MAYBE_ECOFF
10799 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10800 mips_flag_mdebug
= 1;
10802 #endif /* OBJ_MAYBE_ECOFF */
10803 mips_flag_mdebug
= 0;
10808 mips_init_after_args ()
10810 /* initialize opcodes */
10811 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10812 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10816 md_pcrel_from (fixP
)
10819 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10820 && fixP
->fx_addsy
!= (symbolS
*) NULL
10821 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10824 /* Return the address of the delay slot. */
10825 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10828 /* This is called before the symbol table is processed. In order to
10829 work with gcc when using mips-tfile, we must keep all local labels.
10830 However, in other cases, we want to discard them. If we were
10831 called with -g, but we didn't see any debugging information, it may
10832 mean that gcc is smuggling debugging information through to
10833 mips-tfile, in which case we must generate all local labels. */
10836 mips_frob_file_before_adjust ()
10838 #ifndef NO_ECOFF_DEBUGGING
10839 if (ECOFF_DEBUGGING
10841 && ! ecoff_debugging_seen
)
10842 flag_keep_locals
= 1;
10846 /* Sort any unmatched HI16_S relocs so that they immediately precede
10847 the corresponding LO reloc. This is called before md_apply_fix3 and
10848 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10849 explicit use of the %hi modifier. */
10854 struct mips_hi_fixup
*l
;
10856 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10858 segment_info_type
*seginfo
;
10861 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10863 /* Check quickly whether the next fixup happens to be a matching
10865 if (l
->fixp
->fx_next
!= NULL
10866 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10867 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10868 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10871 /* Look through the fixups for this segment for a matching %lo.
10872 When we find one, move the %hi just in front of it. We do
10873 this in two passes. In the first pass, we try to find a
10874 unique %lo. In the second pass, we permit multiple %hi
10875 relocs for a single %lo (this is a GNU extension). */
10876 seginfo
= seg_info (l
->seg
);
10877 for (pass
= 0; pass
< 2; pass
++)
10882 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10884 /* Check whether this is a %lo fixup which matches l->fixp. */
10885 if (f
->fx_r_type
== BFD_RELOC_LO16
10886 && f
->fx_addsy
== l
->fixp
->fx_addsy
10887 && f
->fx_offset
== l
->fixp
->fx_offset
10890 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10891 || prev
->fx_addsy
!= f
->fx_addsy
10892 || prev
->fx_offset
!= f
->fx_offset
))
10896 /* Move l->fixp before f. */
10897 for (pf
= &seginfo
->fix_root
;
10899 pf
= &(*pf
)->fx_next
)
10900 assert (*pf
!= NULL
);
10902 *pf
= l
->fixp
->fx_next
;
10904 l
->fixp
->fx_next
= f
;
10906 seginfo
->fix_root
= l
->fixp
;
10908 prev
->fx_next
= l
->fixp
;
10919 #if 0 /* GCC code motion plus incomplete dead code elimination
10920 can leave a %hi without a %lo. */
10922 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10923 _("Unmatched %%hi reloc"));
10929 /* When generating embedded PIC code we need to use a special
10930 relocation to represent the difference of two symbols in the .text
10931 section (switch tables use a difference of this sort). See
10932 include/coff/mips.h for details. This macro checks whether this
10933 fixup requires the special reloc. */
10934 #define SWITCH_TABLE(fixp) \
10935 ((fixp)->fx_r_type == BFD_RELOC_32 \
10936 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10937 && (fixp)->fx_addsy != NULL \
10938 && (fixp)->fx_subsy != NULL \
10939 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10940 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10942 /* When generating embedded PIC code we must keep all PC relative
10943 relocations, in case the linker has to relax a call. We also need
10944 to keep relocations for switch table entries.
10946 We may have combined relocations without symbols in the N32/N64 ABI.
10947 We have to prevent gas from dropping them. */
10950 mips_force_relocation (fixp
)
10953 if (generic_force_reloc (fixp
))
10957 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10958 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10959 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10960 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10963 return (mips_pic
== EMBEDDED_PIC
10965 || SWITCH_TABLE (fixp
)
10966 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10967 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10972 mips_need_elf_addend_fixup (fixP
)
10975 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10977 if (mips_pic
== EMBEDDED_PIC
10978 && S_IS_WEAK (fixP
->fx_addsy
))
10980 if (mips_pic
!= EMBEDDED_PIC
10981 && (S_IS_WEAK (fixP
->fx_addsy
)
10982 || S_IS_EXTERNAL (fixP
->fx_addsy
))
10983 && !S_IS_COMMON (fixP
->fx_addsy
))
10985 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10986 && (((bfd_get_section_flags (stdoutput
,
10987 S_GET_SEGMENT (fixP
->fx_addsy
))
10988 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
10989 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10991 sizeof (".gnu.linkonce") - 1)))
10997 /* Apply a fixup to the object file. */
11000 md_apply_fix3 (fixP
, valP
, seg
)
11003 segT seg ATTRIBUTE_UNUSED
;
11008 static int previous_fx_r_type
= 0;
11010 /* FIXME: Maybe just return for all reloc types not listed below?
11011 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11012 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11015 assert (fixP
->fx_size
== 4
11016 || fixP
->fx_r_type
== BFD_RELOC_16
11017 || fixP
->fx_r_type
== BFD_RELOC_32
11018 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11019 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11020 || fixP
->fx_r_type
== BFD_RELOC_LO16
11021 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11022 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11023 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11024 || fixP
->fx_r_type
== BFD_RELOC_64
11025 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11026 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11027 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11028 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11029 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11030 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11031 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11032 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11033 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11034 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11038 /* If we aren't adjusting this fixup to be against the section
11039 symbol, we need to adjust the value. */
11041 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11043 if (mips_need_elf_addend_fixup (fixP
))
11045 reloc_howto_type
*howto
;
11046 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11050 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11051 if (value
!= 0 && howto
&& howto
->partial_inplace
11052 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
11054 /* In this case, the bfd_install_relocation routine will
11055 incorrectly add the symbol value back in. We just want
11056 the addend to appear in the object file.
11058 howto->pcrel_offset is added for R_MIPS_PC16, which is
11059 generated for code like
11070 /* Make sure the addend is still non-zero. If it became zero
11071 after the last operation, set it to a spurious value and
11072 subtract the same value from the object file's contents. */
11077 /* The in-place addends for LO16 relocations are signed;
11078 leave the matching HI16 in-place addends as zero. */
11079 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11081 bfd_vma contents
, mask
, field
;
11083 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11086 target_big_endian
);
11088 /* MASK has bits set where the relocation should go.
11089 FIELD is -value, shifted into the appropriate place
11090 for this relocation. */
11091 mask
= 1 << (howto
->bitsize
- 1);
11092 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11093 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11095 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11096 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11098 target_big_endian
);
11104 /* This code was generated using trial and error and so is
11105 fragile and not trustworthy. If you change it, you should
11106 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11107 they still pass. */
11108 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11110 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11112 /* BFD's REL handling, for MIPS, is _very_ weird.
11113 This gives the right results, but it can't possibly
11114 be the way things are supposed to work. */
11115 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11116 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11117 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11122 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11124 /* We are not done if this is a composite relocation to set up gp. */
11125 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11126 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11127 || (fixP
->fx_r_type
== BFD_RELOC_64
11128 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11129 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11130 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11131 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11132 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11134 previous_fx_r_type
= fixP
->fx_r_type
;
11136 switch (fixP
->fx_r_type
)
11138 case BFD_RELOC_MIPS_JMP
:
11139 case BFD_RELOC_MIPS_SHIFT5
:
11140 case BFD_RELOC_MIPS_SHIFT6
:
11141 case BFD_RELOC_MIPS_GOT_DISP
:
11142 case BFD_RELOC_MIPS_GOT_PAGE
:
11143 case BFD_RELOC_MIPS_GOT_OFST
:
11144 case BFD_RELOC_MIPS_SUB
:
11145 case BFD_RELOC_MIPS_INSERT_A
:
11146 case BFD_RELOC_MIPS_INSERT_B
:
11147 case BFD_RELOC_MIPS_DELETE
:
11148 case BFD_RELOC_MIPS_HIGHEST
:
11149 case BFD_RELOC_MIPS_HIGHER
:
11150 case BFD_RELOC_MIPS_SCN_DISP
:
11151 case BFD_RELOC_MIPS_REL16
:
11152 case BFD_RELOC_MIPS_RELGOT
:
11153 case BFD_RELOC_MIPS_JALR
:
11154 case BFD_RELOC_HI16
:
11155 case BFD_RELOC_HI16_S
:
11156 case BFD_RELOC_GPREL16
:
11157 case BFD_RELOC_MIPS_LITERAL
:
11158 case BFD_RELOC_MIPS_CALL16
:
11159 case BFD_RELOC_MIPS_GOT16
:
11160 case BFD_RELOC_GPREL32
:
11161 case BFD_RELOC_MIPS_GOT_HI16
:
11162 case BFD_RELOC_MIPS_GOT_LO16
:
11163 case BFD_RELOC_MIPS_CALL_HI16
:
11164 case BFD_RELOC_MIPS_CALL_LO16
:
11165 case BFD_RELOC_MIPS16_GPREL
:
11166 if (fixP
->fx_pcrel
)
11167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11168 _("Invalid PC relative reloc"));
11169 /* Nothing needed to do. The value comes from the reloc entry */
11172 case BFD_RELOC_MIPS16_JMP
:
11173 /* We currently always generate a reloc against a symbol, which
11174 means that we don't want an addend even if the symbol is
11176 fixP
->fx_addnumber
= 0;
11179 case BFD_RELOC_PCREL_HI16_S
:
11180 /* The addend for this is tricky if it is internal, so we just
11181 do everything here rather than in bfd_install_relocation. */
11182 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11187 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11189 /* For an external symbol adjust by the address to make it
11190 pcrel_offset. We use the address of the RELLO reloc
11191 which follows this one. */
11192 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11193 + fixP
->fx_next
->fx_where
);
11195 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11196 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11197 if (target_big_endian
)
11199 md_number_to_chars ((char *) buf
, value
, 2);
11202 case BFD_RELOC_PCREL_LO16
:
11203 /* The addend for this is tricky if it is internal, so we just
11204 do everything here rather than in bfd_install_relocation. */
11205 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11210 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11211 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11212 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11213 if (target_big_endian
)
11215 md_number_to_chars ((char *) buf
, value
, 2);
11219 /* This is handled like BFD_RELOC_32, but we output a sign
11220 extended value if we are only 32 bits. */
11222 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11224 if (8 <= sizeof (valueT
))
11225 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11232 w1
= w2
= fixP
->fx_where
;
11233 if (target_big_endian
)
11237 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11238 if ((value
& 0x80000000) != 0)
11242 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11247 case BFD_RELOC_RVA
:
11249 /* If we are deleting this reloc entry, we must fill in the
11250 value now. This can happen if we have a .word which is not
11251 resolved when it appears but is later defined. We also need
11252 to fill in the value if this is an embedded PIC switch table
11255 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11256 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11261 /* If we are deleting this reloc entry, we must fill in the
11263 assert (fixP
->fx_size
== 2);
11265 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11269 case BFD_RELOC_LO16
:
11270 /* When handling an embedded PIC switch statement, we can wind
11271 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11274 if (value
+ 0x8000 > 0xffff)
11275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11276 _("relocation overflow"));
11277 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11278 if (target_big_endian
)
11280 md_number_to_chars ((char *) buf
, value
, 2);
11284 case BFD_RELOC_16_PCREL_S2
:
11285 if ((value
& 0x3) != 0)
11286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11287 _("Branch to odd address (%lx)"), (long) value
);
11290 * We need to save the bits in the instruction since fixup_segment()
11291 * might be deleting the relocation entry (i.e., a branch within
11292 * the current segment).
11294 if (!fixP
->fx_done
&& (value
!= 0 || HAVE_NEWABI
))
11296 /* If 'value' is zero, the remaining reloc code won't actually
11297 do the store, so it must be done here. This is probably
11298 a bug somewhere. */
11300 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11301 || fixP
->fx_addsy
== NULL
/* ??? */
11302 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11303 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11305 value
= (offsetT
) value
>> 2;
11307 /* update old instruction data */
11308 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11309 if (target_big_endian
)
11310 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11312 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11314 if (value
+ 0x8000 <= 0xffff)
11315 insn
|= value
& 0xffff;
11318 /* The branch offset is too large. If this is an
11319 unconditional branch, and we are not generating PIC code,
11320 we can convert it to an absolute jump instruction. */
11321 if (mips_pic
== NO_PIC
11323 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11324 && (fixP
->fx_frag
->fr_address
11325 < text_section
->vma
+ text_section
->_raw_size
)
11326 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11327 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11328 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11330 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11331 insn
= 0x0c000000; /* jal */
11333 insn
= 0x08000000; /* j */
11334 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11336 fixP
->fx_addsy
= section_symbol (text_section
);
11337 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11341 /* If we got here, we have branch-relaxation disabled,
11342 and there's nothing we can do to fix this instruction
11343 without turning it into a longer sequence. */
11344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11345 _("Branch out of range"));
11349 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11352 case BFD_RELOC_VTABLE_INHERIT
:
11355 && !S_IS_DEFINED (fixP
->fx_addsy
)
11356 && !S_IS_WEAK (fixP
->fx_addsy
))
11357 S_SET_WEAK (fixP
->fx_addsy
);
11360 case BFD_RELOC_VTABLE_ENTRY
:
11374 const struct mips_opcode
*p
;
11375 int treg
, sreg
, dreg
, shamt
;
11380 for (i
= 0; i
< NUMOPCODES
; ++i
)
11382 p
= &mips_opcodes
[i
];
11383 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11385 printf ("%08lx %s\t", oc
, p
->name
);
11386 treg
= (oc
>> 16) & 0x1f;
11387 sreg
= (oc
>> 21) & 0x1f;
11388 dreg
= (oc
>> 11) & 0x1f;
11389 shamt
= (oc
>> 6) & 0x1f;
11391 for (args
= p
->args
;; ++args
)
11402 printf ("%c", *args
);
11406 assert (treg
== sreg
);
11407 printf ("$%d,$%d", treg
, sreg
);
11412 printf ("$%d", dreg
);
11417 printf ("$%d", treg
);
11421 printf ("0x%x", treg
);
11426 printf ("$%d", sreg
);
11430 printf ("0x%08lx", oc
& 0x1ffffff);
11437 printf ("%d", imm
);
11442 printf ("$%d", shamt
);
11453 printf (_("%08lx UNDEFINED\n"), oc
);
11464 name
= input_line_pointer
;
11465 c
= get_symbol_end ();
11466 p
= (symbolS
*) symbol_find_or_make (name
);
11467 *input_line_pointer
= c
;
11471 /* Align the current frag to a given power of two. The MIPS assembler
11472 also automatically adjusts any preceding label. */
11475 mips_align (to
, fill
, label
)
11480 mips_emit_delays (FALSE
);
11481 frag_align (to
, fill
, 0);
11482 record_alignment (now_seg
, to
);
11485 assert (S_GET_SEGMENT (label
) == now_seg
);
11486 symbol_set_frag (label
, frag_now
);
11487 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11491 /* Align to a given power of two. .align 0 turns off the automatic
11492 alignment used by the data creating pseudo-ops. */
11496 int x ATTRIBUTE_UNUSED
;
11499 register long temp_fill
;
11500 long max_alignment
= 15;
11504 o Note that the assembler pulls down any immediately preceeding label
11505 to the aligned address.
11506 o It's not documented but auto alignment is reinstated by
11507 a .align pseudo instruction.
11508 o Note also that after auto alignment is turned off the mips assembler
11509 issues an error on attempt to assemble an improperly aligned data item.
11514 temp
= get_absolute_expression ();
11515 if (temp
> max_alignment
)
11516 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11519 as_warn (_("Alignment negative: 0 assumed."));
11522 if (*input_line_pointer
== ',')
11524 ++input_line_pointer
;
11525 temp_fill
= get_absolute_expression ();
11532 mips_align (temp
, (int) temp_fill
,
11533 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11540 demand_empty_rest_of_line ();
11544 mips_flush_pending_output ()
11546 mips_emit_delays (FALSE
);
11547 mips_clear_insn_labels ();
11556 /* When generating embedded PIC code, we only use the .text, .lit8,
11557 .sdata and .sbss sections. We change the .data and .rdata
11558 pseudo-ops to use .sdata. */
11559 if (mips_pic
== EMBEDDED_PIC
11560 && (sec
== 'd' || sec
== 'r'))
11564 /* The ELF backend needs to know that we are changing sections, so
11565 that .previous works correctly. We could do something like check
11566 for an obj_section_change_hook macro, but that might be confusing
11567 as it would not be appropriate to use it in the section changing
11568 functions in read.c, since obj-elf.c intercepts those. FIXME:
11569 This should be cleaner, somehow. */
11570 obj_elf_section_change_hook ();
11573 mips_emit_delays (FALSE
);
11583 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11584 demand_empty_rest_of_line ();
11588 if (USE_GLOBAL_POINTER_OPT
)
11590 seg
= subseg_new (RDATA_SECTION_NAME
,
11591 (subsegT
) get_absolute_expression ());
11592 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11594 bfd_set_section_flags (stdoutput
, seg
,
11600 if (strcmp (TARGET_OS
, "elf") != 0)
11601 record_alignment (seg
, 4);
11603 demand_empty_rest_of_line ();
11607 as_bad (_("No read only data section in this object file format"));
11608 demand_empty_rest_of_line ();
11614 if (USE_GLOBAL_POINTER_OPT
)
11616 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11617 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11619 bfd_set_section_flags (stdoutput
, seg
,
11620 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11622 if (strcmp (TARGET_OS
, "elf") != 0)
11623 record_alignment (seg
, 4);
11625 demand_empty_rest_of_line ();
11630 as_bad (_("Global pointers not supported; recompile -G 0"));
11631 demand_empty_rest_of_line ();
11640 s_change_section (ignore
)
11641 int ignore ATTRIBUTE_UNUSED
;
11644 char *section_name
;
11649 int section_entry_size
;
11650 int section_alignment
;
11652 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11655 section_name
= input_line_pointer
;
11656 c
= get_symbol_end ();
11658 next_c
= *(input_line_pointer
+ 1);
11660 /* Do we have .section Name<,"flags">? */
11661 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11663 /* just after name is now '\0'. */
11664 *input_line_pointer
= c
;
11665 input_line_pointer
= section_name
;
11666 obj_elf_section (ignore
);
11669 input_line_pointer
++;
11671 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11673 section_type
= get_absolute_expression ();
11676 if (*input_line_pointer
++ == ',')
11677 section_flag
= get_absolute_expression ();
11680 if (*input_line_pointer
++ == ',')
11681 section_entry_size
= get_absolute_expression ();
11683 section_entry_size
= 0;
11684 if (*input_line_pointer
++ == ',')
11685 section_alignment
= get_absolute_expression ();
11687 section_alignment
= 0;
11689 section_name
= xstrdup (section_name
);
11691 obj_elf_change_section (section_name
, section_type
, section_flag
,
11692 section_entry_size
, 0, 0, 0);
11694 if (now_seg
->name
!= section_name
)
11695 free (section_name
);
11696 #endif /* OBJ_ELF */
11700 mips_enable_auto_align ()
11711 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11712 mips_emit_delays (FALSE
);
11713 if (log_size
> 0 && auto_align
)
11714 mips_align (log_size
, 0, label
);
11715 mips_clear_insn_labels ();
11716 cons (1 << log_size
);
11720 s_float_cons (type
)
11725 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11727 mips_emit_delays (FALSE
);
11732 mips_align (3, 0, label
);
11734 mips_align (2, 0, label
);
11737 mips_clear_insn_labels ();
11742 /* Handle .globl. We need to override it because on Irix 5 you are
11745 where foo is an undefined symbol, to mean that foo should be
11746 considered to be the address of a function. */
11750 int x ATTRIBUTE_UNUSED
;
11757 name
= input_line_pointer
;
11758 c
= get_symbol_end ();
11759 symbolP
= symbol_find_or_make (name
);
11760 *input_line_pointer
= c
;
11761 SKIP_WHITESPACE ();
11763 /* On Irix 5, every global symbol that is not explicitly labelled as
11764 being a function is apparently labelled as being an object. */
11767 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11772 secname
= input_line_pointer
;
11773 c
= get_symbol_end ();
11774 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11776 as_bad (_("%s: no such section"), secname
);
11777 *input_line_pointer
= c
;
11779 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11780 flag
= BSF_FUNCTION
;
11783 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11785 S_SET_EXTERNAL (symbolP
);
11786 demand_empty_rest_of_line ();
11791 int x ATTRIBUTE_UNUSED
;
11796 opt
= input_line_pointer
;
11797 c
= get_symbol_end ();
11801 /* FIXME: What does this mean? */
11803 else if (strncmp (opt
, "pic", 3) == 0)
11807 i
= atoi (opt
+ 3);
11811 mips_pic
= SVR4_PIC
;
11813 as_bad (_(".option pic%d not supported"), i
);
11815 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11817 if (g_switch_seen
&& g_switch_value
!= 0)
11818 as_warn (_("-G may not be used with SVR4 PIC code"));
11819 g_switch_value
= 0;
11820 bfd_set_gp_size (stdoutput
, 0);
11824 as_warn (_("Unrecognized option \"%s\""), opt
);
11826 *input_line_pointer
= c
;
11827 demand_empty_rest_of_line ();
11830 /* This structure is used to hold a stack of .set values. */
11832 struct mips_option_stack
11834 struct mips_option_stack
*next
;
11835 struct mips_set_options options
;
11838 static struct mips_option_stack
*mips_opts_stack
;
11840 /* Handle the .set pseudo-op. */
11844 int x ATTRIBUTE_UNUSED
;
11846 char *name
= input_line_pointer
, ch
;
11848 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11849 ++input_line_pointer
;
11850 ch
= *input_line_pointer
;
11851 *input_line_pointer
= '\0';
11853 if (strcmp (name
, "reorder") == 0)
11855 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11857 /* If we still have pending nops, we can discard them. The
11858 usual nop handling will insert any that are still
11860 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11861 * (mips_opts
.mips16
? 2 : 4));
11862 prev_nop_frag
= NULL
;
11864 mips_opts
.noreorder
= 0;
11866 else if (strcmp (name
, "noreorder") == 0)
11868 mips_emit_delays (TRUE
);
11869 mips_opts
.noreorder
= 1;
11870 mips_any_noreorder
= 1;
11872 else if (strcmp (name
, "at") == 0)
11874 mips_opts
.noat
= 0;
11876 else if (strcmp (name
, "noat") == 0)
11878 mips_opts
.noat
= 1;
11880 else if (strcmp (name
, "macro") == 0)
11882 mips_opts
.warn_about_macros
= 0;
11884 else if (strcmp (name
, "nomacro") == 0)
11886 if (mips_opts
.noreorder
== 0)
11887 as_bad (_("`noreorder' must be set before `nomacro'"));
11888 mips_opts
.warn_about_macros
= 1;
11890 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11892 mips_opts
.nomove
= 0;
11894 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11896 mips_opts
.nomove
= 1;
11898 else if (strcmp (name
, "bopt") == 0)
11900 mips_opts
.nobopt
= 0;
11902 else if (strcmp (name
, "nobopt") == 0)
11904 mips_opts
.nobopt
= 1;
11906 else if (strcmp (name
, "mips16") == 0
11907 || strcmp (name
, "MIPS-16") == 0)
11908 mips_opts
.mips16
= 1;
11909 else if (strcmp (name
, "nomips16") == 0
11910 || strcmp (name
, "noMIPS-16") == 0)
11911 mips_opts
.mips16
= 0;
11912 else if (strcmp (name
, "mips3d") == 0)
11913 mips_opts
.ase_mips3d
= 1;
11914 else if (strcmp (name
, "nomips3d") == 0)
11915 mips_opts
.ase_mips3d
= 0;
11916 else if (strcmp (name
, "mdmx") == 0)
11917 mips_opts
.ase_mdmx
= 1;
11918 else if (strcmp (name
, "nomdmx") == 0)
11919 mips_opts
.ase_mdmx
= 0;
11920 else if (strncmp (name
, "mips", 4) == 0)
11924 /* Permit the user to change the ISA on the fly. Needless to
11925 say, misuse can cause serious problems. */
11926 if (strcmp (name
, "mips0") == 0)
11929 mips_opts
.isa
= file_mips_isa
;
11931 else if (strcmp (name
, "mips1") == 0)
11932 mips_opts
.isa
= ISA_MIPS1
;
11933 else if (strcmp (name
, "mips2") == 0)
11934 mips_opts
.isa
= ISA_MIPS2
;
11935 else if (strcmp (name
, "mips3") == 0)
11936 mips_opts
.isa
= ISA_MIPS3
;
11937 else if (strcmp (name
, "mips4") == 0)
11938 mips_opts
.isa
= ISA_MIPS4
;
11939 else if (strcmp (name
, "mips5") == 0)
11940 mips_opts
.isa
= ISA_MIPS5
;
11941 else if (strcmp (name
, "mips32") == 0)
11942 mips_opts
.isa
= ISA_MIPS32
;
11943 else if (strcmp (name
, "mips32r2") == 0)
11944 mips_opts
.isa
= ISA_MIPS32R2
;
11945 else if (strcmp (name
, "mips64") == 0)
11946 mips_opts
.isa
= ISA_MIPS64
;
11948 as_bad (_("unknown ISA level %s"), name
+ 4);
11950 switch (mips_opts
.isa
)
11958 mips_opts
.gp32
= 1;
11959 mips_opts
.fp32
= 1;
11965 mips_opts
.gp32
= 0;
11966 mips_opts
.fp32
= 0;
11969 as_bad (_("unknown ISA level %s"), name
+ 4);
11974 mips_opts
.gp32
= file_mips_gp32
;
11975 mips_opts
.fp32
= file_mips_fp32
;
11978 else if (strcmp (name
, "autoextend") == 0)
11979 mips_opts
.noautoextend
= 0;
11980 else if (strcmp (name
, "noautoextend") == 0)
11981 mips_opts
.noautoextend
= 1;
11982 else if (strcmp (name
, "push") == 0)
11984 struct mips_option_stack
*s
;
11986 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11987 s
->next
= mips_opts_stack
;
11988 s
->options
= mips_opts
;
11989 mips_opts_stack
= s
;
11991 else if (strcmp (name
, "pop") == 0)
11993 struct mips_option_stack
*s
;
11995 s
= mips_opts_stack
;
11997 as_bad (_(".set pop with no .set push"));
12000 /* If we're changing the reorder mode we need to handle
12001 delay slots correctly. */
12002 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12003 mips_emit_delays (TRUE
);
12004 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12006 if (prev_nop_frag
!= NULL
)
12008 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12009 * (mips_opts
.mips16
? 2 : 4));
12010 prev_nop_frag
= NULL
;
12014 mips_opts
= s
->options
;
12015 mips_opts_stack
= s
->next
;
12021 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12023 *input_line_pointer
= ch
;
12024 demand_empty_rest_of_line ();
12027 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12028 .option pic2. It means to generate SVR4 PIC calls. */
12031 s_abicalls (ignore
)
12032 int ignore ATTRIBUTE_UNUSED
;
12034 mips_pic
= SVR4_PIC
;
12035 if (USE_GLOBAL_POINTER_OPT
)
12037 if (g_switch_seen
&& g_switch_value
!= 0)
12038 as_warn (_("-G may not be used with SVR4 PIC code"));
12039 g_switch_value
= 0;
12041 bfd_set_gp_size (stdoutput
, 0);
12042 demand_empty_rest_of_line ();
12045 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12046 PIC code. It sets the $gp register for the function based on the
12047 function address, which is in the register named in the argument.
12048 This uses a relocation against _gp_disp, which is handled specially
12049 by the linker. The result is:
12050 lui $gp,%hi(_gp_disp)
12051 addiu $gp,$gp,%lo(_gp_disp)
12052 addu $gp,$gp,.cpload argument
12053 The .cpload argument is normally $25 == $t9. */
12057 int ignore ATTRIBUTE_UNUSED
;
12062 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12063 .cpload is ignored. */
12064 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12070 /* .cpload should be in a .set noreorder section. */
12071 if (mips_opts
.noreorder
== 0)
12072 as_warn (_(".cpload not in noreorder section"));
12074 ex
.X_op
= O_symbol
;
12075 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12076 ex
.X_op_symbol
= NULL
;
12077 ex
.X_add_number
= 0;
12079 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12080 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12082 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12083 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12084 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12087 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12089 demand_empty_rest_of_line ();
12092 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12093 .cpsetup $reg1, offset|$reg2, label
12095 If offset is given, this results in:
12096 sd $gp, offset($sp)
12097 lui $gp, %hi(%neg(%gp_rel(label)))
12098 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12099 daddu $gp, $gp, $reg1
12101 If $reg2 is given, this results in:
12102 daddu $reg2, $gp, $0
12103 lui $gp, %hi(%neg(%gp_rel(label)))
12104 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12105 daddu $gp, $gp, $reg1
12106 $reg1 is normally $25 == $t9. */
12109 int ignore ATTRIBUTE_UNUSED
;
12111 expressionS ex_off
;
12112 expressionS ex_sym
;
12117 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12118 We also need NewABI support. */
12119 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12125 reg1
= tc_get_register (0);
12126 SKIP_WHITESPACE ();
12127 if (*input_line_pointer
!= ',')
12129 as_bad (_("missing argument separator ',' for .cpsetup"));
12133 ++input_line_pointer
;
12134 SKIP_WHITESPACE ();
12135 if (*input_line_pointer
== '$')
12137 mips_cpreturn_register
= tc_get_register (0);
12138 mips_cpreturn_offset
= -1;
12142 mips_cpreturn_offset
= get_absolute_expression ();
12143 mips_cpreturn_register
= -1;
12145 SKIP_WHITESPACE ();
12146 if (*input_line_pointer
!= ',')
12148 as_bad (_("missing argument separator ',' for .cpsetup"));
12152 ++input_line_pointer
;
12153 SKIP_WHITESPACE ();
12154 expression (&ex_sym
);
12156 if (mips_cpreturn_register
== -1)
12158 ex_off
.X_op
= O_constant
;
12159 ex_off
.X_add_symbol
= NULL
;
12160 ex_off
.X_op_symbol
= NULL
;
12161 ex_off
.X_add_number
= mips_cpreturn_offset
;
12163 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12164 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12168 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12170 /* Ensure there's room for the next two instructions, so that `f'
12171 doesn't end up with an address in the wrong frag. */
12174 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12175 (int) BFD_RELOC_GPREL16
);
12176 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12177 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12178 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12179 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12182 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12183 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12184 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12185 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12186 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12187 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12190 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12191 mips_gp_register
, mips_gp_register
, reg1
);
12193 demand_empty_rest_of_line ();
12198 int ignore ATTRIBUTE_UNUSED
;
12200 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12201 .cplocal is ignored. */
12202 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12208 mips_gp_register
= tc_get_register (0);
12209 demand_empty_rest_of_line ();
12212 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12213 offset from $sp. The offset is remembered, and after making a PIC
12214 call $gp is restored from that location. */
12217 s_cprestore (ignore
)
12218 int ignore ATTRIBUTE_UNUSED
;
12223 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12224 .cprestore is ignored. */
12225 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12231 mips_cprestore_offset
= get_absolute_expression ();
12232 mips_cprestore_valid
= 1;
12234 ex
.X_op
= O_constant
;
12235 ex
.X_add_symbol
= NULL
;
12236 ex
.X_op_symbol
= NULL
;
12237 ex
.X_add_number
= mips_cprestore_offset
;
12239 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12240 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12241 mips_gp_register
, SP
);
12243 demand_empty_rest_of_line ();
12246 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12247 was given in the preceeding .gpsetup, it results in:
12248 ld $gp, offset($sp)
12250 If a register $reg2 was given there, it results in:
12251 daddiu $gp, $gp, $reg2
12254 s_cpreturn (ignore
)
12255 int ignore ATTRIBUTE_UNUSED
;
12260 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12261 We also need NewABI support. */
12262 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12268 if (mips_cpreturn_register
== -1)
12270 ex
.X_op
= O_constant
;
12271 ex
.X_add_symbol
= NULL
;
12272 ex
.X_op_symbol
= NULL
;
12273 ex
.X_add_number
= mips_cpreturn_offset
;
12275 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12276 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12280 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12282 demand_empty_rest_of_line ();
12285 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12286 code. It sets the offset to use in gp_rel relocations. */
12290 int ignore ATTRIBUTE_UNUSED
;
12292 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12293 We also need NewABI support. */
12294 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12300 mips_gprel_offset
= get_absolute_expression ();
12302 demand_empty_rest_of_line ();
12305 /* Handle the .gpword pseudo-op. This is used when generating PIC
12306 code. It generates a 32 bit GP relative reloc. */
12310 int ignore ATTRIBUTE_UNUSED
;
12316 /* When not generating PIC code, this is treated as .word. */
12317 if (mips_pic
!= SVR4_PIC
)
12323 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12324 mips_emit_delays (TRUE
);
12326 mips_align (2, 0, label
);
12327 mips_clear_insn_labels ();
12331 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12333 as_bad (_("Unsupported use of .gpword"));
12334 ignore_rest_of_line ();
12338 md_number_to_chars (p
, (valueT
) 0, 4);
12339 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12340 BFD_RELOC_GPREL32
);
12342 demand_empty_rest_of_line ();
12347 int ignore ATTRIBUTE_UNUSED
;
12353 /* When not generating PIC code, this is treated as .dword. */
12354 if (mips_pic
!= SVR4_PIC
)
12360 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12361 mips_emit_delays (TRUE
);
12363 mips_align (3, 0, label
);
12364 mips_clear_insn_labels ();
12368 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12370 as_bad (_("Unsupported use of .gpdword"));
12371 ignore_rest_of_line ();
12375 md_number_to_chars (p
, (valueT
) 0, 8);
12376 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12377 BFD_RELOC_GPREL32
);
12379 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12380 ex
.X_op
= O_absent
;
12381 ex
.X_add_symbol
= 0;
12382 ex
.X_add_number
= 0;
12383 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12386 demand_empty_rest_of_line ();
12389 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12390 tables in SVR4 PIC code. */
12394 int ignore ATTRIBUTE_UNUSED
;
12399 /* This is ignored when not generating SVR4 PIC code. */
12400 if (mips_pic
!= SVR4_PIC
)
12406 /* Add $gp to the register named as an argument. */
12407 reg
= tc_get_register (0);
12408 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12409 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12410 "d,v,t", reg
, reg
, mips_gp_register
);
12412 demand_empty_rest_of_line ();
12415 /* Handle the .insn pseudo-op. This marks instruction labels in
12416 mips16 mode. This permits the linker to handle them specially,
12417 such as generating jalx instructions when needed. We also make
12418 them odd for the duration of the assembly, in order to generate the
12419 right sort of code. We will make them even in the adjust_symtab
12420 routine, while leaving them marked. This is convenient for the
12421 debugger and the disassembler. The linker knows to make them odd
12426 int ignore ATTRIBUTE_UNUSED
;
12428 mips16_mark_labels ();
12430 demand_empty_rest_of_line ();
12433 /* Handle a .stabn directive. We need these in order to mark a label
12434 as being a mips16 text label correctly. Sometimes the compiler
12435 will emit a label, followed by a .stabn, and then switch sections.
12436 If the label and .stabn are in mips16 mode, then the label is
12437 really a mips16 text label. */
12444 mips16_mark_labels ();
12449 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12453 s_mips_weakext (ignore
)
12454 int ignore ATTRIBUTE_UNUSED
;
12461 name
= input_line_pointer
;
12462 c
= get_symbol_end ();
12463 symbolP
= symbol_find_or_make (name
);
12464 S_SET_WEAK (symbolP
);
12465 *input_line_pointer
= c
;
12467 SKIP_WHITESPACE ();
12469 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12471 if (S_IS_DEFINED (symbolP
))
12473 as_bad ("ignoring attempt to redefine symbol %s",
12474 S_GET_NAME (symbolP
));
12475 ignore_rest_of_line ();
12479 if (*input_line_pointer
== ',')
12481 ++input_line_pointer
;
12482 SKIP_WHITESPACE ();
12486 if (exp
.X_op
!= O_symbol
)
12488 as_bad ("bad .weakext directive");
12489 ignore_rest_of_line ();
12492 symbol_set_value_expression (symbolP
, &exp
);
12495 demand_empty_rest_of_line ();
12498 /* Parse a register string into a number. Called from the ECOFF code
12499 to parse .frame. The argument is non-zero if this is the frame
12500 register, so that we can record it in mips_frame_reg. */
12503 tc_get_register (frame
)
12508 SKIP_WHITESPACE ();
12509 if (*input_line_pointer
++ != '$')
12511 as_warn (_("expected `$'"));
12514 else if (ISDIGIT (*input_line_pointer
))
12516 reg
= get_absolute_expression ();
12517 if (reg
< 0 || reg
>= 32)
12519 as_warn (_("Bad register number"));
12525 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12528 input_line_pointer
+= 2;
12530 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12533 input_line_pointer
+= 2;
12535 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12538 input_line_pointer
+= 2;
12540 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12543 input_line_pointer
+= 2;
12545 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12548 input_line_pointer
+= 2;
12550 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12553 input_line_pointer
+= 3;
12555 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12558 input_line_pointer
+= 3;
12560 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12563 input_line_pointer
+= 4;
12567 as_warn (_("Unrecognized register name"));
12569 while (ISALNUM(*input_line_pointer
))
12570 input_line_pointer
++;
12575 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12576 mips_frame_reg_valid
= 1;
12577 mips_cprestore_valid
= 0;
12583 md_section_align (seg
, addr
)
12587 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12590 /* We don't need to align ELF sections to the full alignment.
12591 However, Irix 5 may prefer that we align them at least to a 16
12592 byte boundary. We don't bother to align the sections if we are
12593 targeted for an embedded system. */
12594 if (strcmp (TARGET_OS
, "elf") == 0)
12600 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12603 /* Utility routine, called from above as well. If called while the
12604 input file is still being read, it's only an approximation. (For
12605 example, a symbol may later become defined which appeared to be
12606 undefined earlier.) */
12609 nopic_need_relax (sym
, before_relaxing
)
12611 int before_relaxing
;
12616 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12618 const char *symname
;
12621 /* Find out whether this symbol can be referenced off the $gp
12622 register. It can be if it is smaller than the -G size or if
12623 it is in the .sdata or .sbss section. Certain symbols can
12624 not be referenced off the $gp, although it appears as though
12626 symname
= S_GET_NAME (sym
);
12627 if (symname
!= (const char *) NULL
12628 && (strcmp (symname
, "eprol") == 0
12629 || strcmp (symname
, "etext") == 0
12630 || strcmp (symname
, "_gp") == 0
12631 || strcmp (symname
, "edata") == 0
12632 || strcmp (symname
, "_fbss") == 0
12633 || strcmp (symname
, "_fdata") == 0
12634 || strcmp (symname
, "_ftext") == 0
12635 || strcmp (symname
, "end") == 0
12636 || strcmp (symname
, "_gp_disp") == 0))
12638 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12640 #ifndef NO_ECOFF_DEBUGGING
12641 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12642 && (symbol_get_obj (sym
)->ecoff_extern_size
12643 <= g_switch_value
))
12645 /* We must defer this decision until after the whole
12646 file has been read, since there might be a .extern
12647 after the first use of this symbol. */
12648 || (before_relaxing
12649 #ifndef NO_ECOFF_DEBUGGING
12650 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12652 && S_GET_VALUE (sym
) == 0)
12653 || (S_GET_VALUE (sym
) != 0
12654 && S_GET_VALUE (sym
) <= g_switch_value
)))
12658 const char *segname
;
12660 segname
= segment_name (S_GET_SEGMENT (sym
));
12661 assert (strcmp (segname
, ".lit8") != 0
12662 && strcmp (segname
, ".lit4") != 0);
12663 change
= (strcmp (segname
, ".sdata") != 0
12664 && strcmp (segname
, ".sbss") != 0
12665 && strncmp (segname
, ".sdata.", 7) != 0
12666 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12671 /* We are not optimizing for the $gp register. */
12675 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12676 extended opcode. SEC is the section the frag is in. */
12679 mips16_extended_frag (fragp
, sec
, stretch
)
12685 register const struct mips16_immed_operand
*op
;
12687 int mintiny
, maxtiny
;
12691 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12693 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12696 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12697 op
= mips16_immed_operands
;
12698 while (op
->type
!= type
)
12701 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12706 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12709 maxtiny
= 1 << op
->nbits
;
12714 maxtiny
= (1 << op
->nbits
) - 1;
12719 mintiny
= - (1 << (op
->nbits
- 1));
12720 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12723 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12724 val
= S_GET_VALUE (fragp
->fr_symbol
);
12725 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12731 /* We won't have the section when we are called from
12732 mips_relax_frag. However, we will always have been called
12733 from md_estimate_size_before_relax first. If this is a
12734 branch to a different section, we mark it as such. If SEC is
12735 NULL, and the frag is not marked, then it must be a branch to
12736 the same section. */
12739 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12744 /* Must have been called from md_estimate_size_before_relax. */
12747 fragp
->fr_subtype
=
12748 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12750 /* FIXME: We should support this, and let the linker
12751 catch branches and loads that are out of range. */
12752 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12753 _("unsupported PC relative reference to different section"));
12757 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12758 /* Assume non-extended on the first relaxation pass.
12759 The address we have calculated will be bogus if this is
12760 a forward branch to another frag, as the forward frag
12761 will have fr_address == 0. */
12765 /* In this case, we know for sure that the symbol fragment is in
12766 the same section. If the relax_marker of the symbol fragment
12767 differs from the relax_marker of this fragment, we have not
12768 yet adjusted the symbol fragment fr_address. We want to add
12769 in STRETCH in order to get a better estimate of the address.
12770 This particularly matters because of the shift bits. */
12772 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12776 /* Adjust stretch for any alignment frag. Note that if have
12777 been expanding the earlier code, the symbol may be
12778 defined in what appears to be an earlier frag. FIXME:
12779 This doesn't handle the fr_subtype field, which specifies
12780 a maximum number of bytes to skip when doing an
12782 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12784 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12787 stretch
= - ((- stretch
)
12788 & ~ ((1 << (int) f
->fr_offset
) - 1));
12790 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12799 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12801 /* The base address rules are complicated. The base address of
12802 a branch is the following instruction. The base address of a
12803 PC relative load or add is the instruction itself, but if it
12804 is in a delay slot (in which case it can not be extended) use
12805 the address of the instruction whose delay slot it is in. */
12806 if (type
== 'p' || type
== 'q')
12810 /* If we are currently assuming that this frag should be
12811 extended, then, the current address is two bytes
12813 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12816 /* Ignore the low bit in the target, since it will be set
12817 for a text label. */
12818 if ((val
& 1) != 0)
12821 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12823 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12826 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12828 /* Branch offsets have an implicit 0 in the lowest bit. */
12829 if (type
== 'p' || type
== 'q')
12832 /* If any of the shifted bits are set, we must use an extended
12833 opcode. If the address depends on the size of this
12834 instruction, this can lead to a loop, so we arrange to always
12835 use an extended opcode. We only check this when we are in
12836 the main relaxation loop, when SEC is NULL. */
12837 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12839 fragp
->fr_subtype
=
12840 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12844 /* If we are about to mark a frag as extended because the value
12845 is precisely maxtiny + 1, then there is a chance of an
12846 infinite loop as in the following code:
12851 In this case when the la is extended, foo is 0x3fc bytes
12852 away, so the la can be shrunk, but then foo is 0x400 away, so
12853 the la must be extended. To avoid this loop, we mark the
12854 frag as extended if it was small, and is about to become
12855 extended with a value of maxtiny + 1. */
12856 if (val
== ((maxtiny
+ 1) << op
->shift
)
12857 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12860 fragp
->fr_subtype
=
12861 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12865 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12866 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12868 if ((val
& ((1 << op
->shift
) - 1)) != 0
12869 || val
< (mintiny
<< op
->shift
)
12870 || val
> (maxtiny
<< op
->shift
))
12876 /* Compute the length of a branch sequence, and adjust the
12877 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12878 worst-case length is computed, with UPDATE being used to indicate
12879 whether an unconditional (-1), branch-likely (+1) or regular (0)
12880 branch is to be computed. */
12882 relaxed_branch_length (fragp
, sec
, update
)
12887 bfd_boolean toofar
;
12891 && S_IS_DEFINED (fragp
->fr_symbol
)
12892 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12897 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12899 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12903 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12906 /* If the symbol is not defined or it's in a different segment,
12907 assume the user knows what's going on and emit a short
12913 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12915 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12916 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12917 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12923 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12926 if (mips_pic
!= NO_PIC
)
12928 /* Additional space for PIC loading of target address. */
12930 if (mips_opts
.isa
== ISA_MIPS1
)
12931 /* Additional space for $at-stabilizing nop. */
12935 /* If branch is conditional. */
12936 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12943 /* Estimate the size of a frag before relaxing. Unless this is the
12944 mips16, we are not really relaxing here, and the final size is
12945 encoded in the subtype information. For the mips16, we have to
12946 decide whether we are using an extended opcode or not. */
12949 md_estimate_size_before_relax (fragp
, segtype
)
12954 bfd_boolean linkonce
= FALSE
;
12956 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12959 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12961 return fragp
->fr_var
;
12964 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12965 /* We don't want to modify the EXTENDED bit here; it might get us
12966 into infinite loops. We change it only in mips_relax_frag(). */
12967 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12969 if (mips_pic
== NO_PIC
)
12971 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12973 else if (mips_pic
== SVR4_PIC
)
12978 sym
= fragp
->fr_symbol
;
12980 /* Handle the case of a symbol equated to another symbol. */
12981 while (symbol_equated_reloc_p (sym
))
12985 /* It's possible to get a loop here in a badly written
12987 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12993 symsec
= S_GET_SEGMENT (sym
);
12995 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12996 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12998 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13002 /* The GNU toolchain uses an extension for ELF: a section
13003 beginning with the magic string .gnu.linkonce is a linkonce
13005 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13006 sizeof ".gnu.linkonce" - 1) == 0)
13010 /* This must duplicate the test in adjust_reloc_syms. */
13011 change
= (symsec
!= &bfd_und_section
13012 && symsec
!= &bfd_abs_section
13013 && ! bfd_is_com_section (symsec
)
13016 /* A global or weak symbol is treated as external. */
13017 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13018 || (! S_IS_WEAK (sym
)
13019 && (! S_IS_EXTERNAL (sym
)
13020 || mips_pic
== EMBEDDED_PIC
)))
13029 /* Record the offset to the first reloc in the fr_opcode field.
13030 This lets md_convert_frag and tc_gen_reloc know that the code
13031 must be expanded. */
13032 fragp
->fr_opcode
= (fragp
->fr_literal
13034 - RELAX_OLD (fragp
->fr_subtype
)
13035 + RELAX_RELOC1 (fragp
->fr_subtype
));
13036 /* FIXME: This really needs as_warn_where. */
13037 if (RELAX_WARN (fragp
->fr_subtype
))
13038 as_warn (_("AT used after \".set noat\" or macro used after "
13039 "\".set nomacro\""));
13041 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13047 /* This is called to see whether a reloc against a defined symbol
13048 should be converted into a reloc against a section. Don't adjust
13049 MIPS16 jump relocations, so we don't have to worry about the format
13050 of the offset in the .o file. Don't adjust relocations against
13051 mips16 symbols, so that the linker can find them if it needs to set
13055 mips_fix_adjustable (fixp
)
13058 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13061 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13062 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13065 if (fixp
->fx_addsy
== NULL
)
13069 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13070 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13071 && fixp
->fx_subsy
== NULL
)
13078 /* Translate internal representation of relocation info to BFD target
13082 tc_gen_reloc (section
, fixp
)
13083 asection
*section ATTRIBUTE_UNUSED
;
13086 static arelent
*retval
[4];
13088 bfd_reloc_code_real_type code
;
13090 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13093 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13094 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13095 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13097 if (mips_pic
== EMBEDDED_PIC
13098 && SWITCH_TABLE (fixp
))
13100 /* For a switch table entry we use a special reloc. The addend
13101 is actually the difference between the reloc address and the
13103 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13104 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13105 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13106 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13108 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13110 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13111 reloc
->addend
= fixp
->fx_addnumber
;
13114 /* We use a special addend for an internal RELLO reloc. */
13115 if (symbol_section_p (fixp
->fx_addsy
))
13116 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13118 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13121 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13123 assert (fixp
->fx_next
!= NULL
13124 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13126 /* The reloc is relative to the RELLO; adjust the addend
13128 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13129 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13132 /* We use a special addend for an internal RELHI reloc. */
13133 if (symbol_section_p (fixp
->fx_addsy
))
13134 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13135 + fixp
->fx_next
->fx_where
13136 - S_GET_VALUE (fixp
->fx_subsy
));
13138 reloc
->addend
= (fixp
->fx_addnumber
13139 + fixp
->fx_next
->fx_frag
->fr_address
13140 + fixp
->fx_next
->fx_where
);
13143 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13144 reloc
->addend
= fixp
->fx_addnumber
;
13147 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13148 /* A gruesome hack which is a result of the gruesome gas reloc
13150 reloc
->addend
= reloc
->address
;
13152 reloc
->addend
= -reloc
->address
;
13155 /* If this is a variant frag, we may need to adjust the existing
13156 reloc and generate a new one. */
13157 if (fixp
->fx_frag
->fr_opcode
!= NULL
13158 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13160 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13161 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13162 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13163 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13164 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13165 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13170 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13172 /* If this is not the last reloc in this frag, then we have two
13173 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13174 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13175 the second one handle all of them. */
13176 if (fixp
->fx_next
!= NULL
13177 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13179 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13180 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13181 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13182 && (fixp
->fx_next
->fx_r_type
13183 == BFD_RELOC_MIPS_GOT_LO16
))
13184 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13185 && (fixp
->fx_next
->fx_r_type
13186 == BFD_RELOC_MIPS_CALL_LO16
)));
13191 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13192 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13193 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13195 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13196 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13197 reloc2
->address
= (reloc
->address
13198 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13199 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13200 reloc2
->addend
= fixp
->fx_addnumber
;
13201 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13202 assert (reloc2
->howto
!= NULL
);
13204 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13208 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13211 reloc3
->address
+= 4;
13214 if (mips_pic
== NO_PIC
)
13216 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13217 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13219 else if (mips_pic
== SVR4_PIC
)
13221 switch (fixp
->fx_r_type
)
13225 case BFD_RELOC_MIPS_GOT16
:
13227 case BFD_RELOC_MIPS_GOT_LO16
:
13228 case BFD_RELOC_MIPS_CALL_LO16
:
13229 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13231 case BFD_RELOC_MIPS_CALL16
:
13234 /* BFD_RELOC_MIPS_GOT16;*/
13235 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13236 reloc2
->howto
= bfd_reloc_type_lookup
13237 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13240 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13247 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13248 if (HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
)
13250 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13255 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13256 entry to be used in the relocation's section offset. */
13257 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13259 reloc
->address
= reloc
->addend
;
13263 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13264 fixup_segment converted a non-PC relative reloc into a PC
13265 relative reloc. In such a case, we need to convert the reloc
13267 code
= fixp
->fx_r_type
;
13268 if (fixp
->fx_pcrel
)
13273 code
= BFD_RELOC_8_PCREL
;
13276 code
= BFD_RELOC_16_PCREL
;
13279 code
= BFD_RELOC_32_PCREL
;
13282 code
= BFD_RELOC_64_PCREL
;
13284 case BFD_RELOC_8_PCREL
:
13285 case BFD_RELOC_16_PCREL
:
13286 case BFD_RELOC_32_PCREL
:
13287 case BFD_RELOC_64_PCREL
:
13288 case BFD_RELOC_16_PCREL_S2
:
13289 case BFD_RELOC_PCREL_HI16_S
:
13290 case BFD_RELOC_PCREL_LO16
:
13293 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13294 _("Cannot make %s relocation PC relative"),
13295 bfd_get_reloc_code_name (code
));
13300 /* md_apply_fix3 has a double-subtraction hack to get
13301 bfd_install_relocation to behave nicely. GPREL relocations are
13302 handled correctly without this hack, so undo it here. We can't
13303 stop md_apply_fix3 from subtracting twice in the first place since
13304 the fake addend is required for variant frags above. */
13305 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13306 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13307 && reloc
->addend
!= 0
13308 && mips_need_elf_addend_fixup (fixp
))
13309 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13312 /* To support a PC relative reloc when generating embedded PIC code
13313 for ECOFF, we use a Cygnus extension. We check for that here to
13314 make sure that we don't let such a reloc escape normally. */
13315 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13316 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13317 && code
== BFD_RELOC_16_PCREL_S2
13318 && mips_pic
!= EMBEDDED_PIC
)
13319 reloc
->howto
= NULL
;
13321 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13323 if (reloc
->howto
== NULL
)
13325 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13326 _("Can not represent %s relocation in this object file format"),
13327 bfd_get_reloc_code_name (code
));
13334 /* Relax a machine dependent frag. This returns the amount by which
13335 the current size of the frag should change. */
13338 mips_relax_frag (sec
, fragp
, stretch
)
13343 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13345 offsetT old_var
= fragp
->fr_var
;
13347 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13349 return fragp
->fr_var
- old_var
;
13352 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13355 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13357 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13359 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13364 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13366 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13373 /* Convert a machine dependent frag. */
13376 md_convert_frag (abfd
, asec
, fragp
)
13377 bfd
*abfd ATTRIBUTE_UNUSED
;
13384 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13387 unsigned long insn
;
13391 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13393 if (target_big_endian
)
13394 insn
= bfd_getb32 (buf
);
13396 insn
= bfd_getl32 (buf
);
13398 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13400 /* We generate a fixup instead of applying it right now
13401 because, if there are linker relaxations, we're going to
13402 need the relocations. */
13403 exp
.X_op
= O_symbol
;
13404 exp
.X_add_symbol
= fragp
->fr_symbol
;
13405 exp
.X_add_number
= fragp
->fr_offset
;
13407 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13409 BFD_RELOC_16_PCREL_S2
);
13410 fixp
->fx_file
= fragp
->fr_file
;
13411 fixp
->fx_line
= fragp
->fr_line
;
13413 md_number_to_chars ((char *)buf
, insn
, 4);
13420 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13421 _("relaxed out-of-range branch into a jump"));
13423 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13426 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13428 /* Reverse the branch. */
13429 switch ((insn
>> 28) & 0xf)
13432 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13433 have the condition reversed by tweaking a single
13434 bit, and their opcodes all have 0x4???????. */
13435 assert ((insn
& 0xf1000000) == 0x41000000);
13436 insn
^= 0x00010000;
13440 /* bltz 0x04000000 bgez 0x04010000
13441 bltzal 0x04100000 bgezal 0x04110000 */
13442 assert ((insn
& 0xfc0e0000) == 0x04000000);
13443 insn
^= 0x00010000;
13447 /* beq 0x10000000 bne 0x14000000
13448 blez 0x18000000 bgtz 0x1c000000 */
13449 insn
^= 0x04000000;
13457 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13459 /* Clear the and-link bit. */
13460 assert ((insn
& 0xfc1c0000) == 0x04100000);
13462 /* bltzal 0x04100000 bgezal 0x04110000
13463 bltzall 0x04120000 bgezall 0x04130000 */
13464 insn
&= ~0x00100000;
13467 /* Branch over the branch (if the branch was likely) or the
13468 full jump (not likely case). Compute the offset from the
13469 current instruction to branch to. */
13470 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13474 /* How many bytes in instructions we've already emitted? */
13475 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13476 /* How many bytes in instructions from here to the end? */
13477 i
= fragp
->fr_var
- i
;
13479 /* Convert to instruction count. */
13481 /* Branch counts from the next instruction. */
13484 /* Branch over the jump. */
13485 md_number_to_chars ((char *)buf
, insn
, 4);
13489 md_number_to_chars ((char*)buf
, 0, 4);
13492 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13494 /* beql $0, $0, 2f */
13496 /* Compute the PC offset from the current instruction to
13497 the end of the variable frag. */
13498 /* How many bytes in instructions we've already emitted? */
13499 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13500 /* How many bytes in instructions from here to the end? */
13501 i
= fragp
->fr_var
- i
;
13502 /* Convert to instruction count. */
13504 /* Don't decrement i, because we want to branch over the
13508 md_number_to_chars ((char *)buf
, insn
, 4);
13511 md_number_to_chars ((char *)buf
, 0, 4);
13516 if (mips_pic
== NO_PIC
)
13519 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13520 ? 0x0c000000 : 0x08000000);
13521 exp
.X_op
= O_symbol
;
13522 exp
.X_add_symbol
= fragp
->fr_symbol
;
13523 exp
.X_add_number
= fragp
->fr_offset
;
13525 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13526 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13527 fixp
->fx_file
= fragp
->fr_file
;
13528 fixp
->fx_line
= fragp
->fr_line
;
13530 md_number_to_chars ((char*)buf
, insn
, 4);
13535 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13536 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13537 exp
.X_op
= O_symbol
;
13538 exp
.X_add_symbol
= fragp
->fr_symbol
;
13539 exp
.X_add_number
= fragp
->fr_offset
;
13541 if (fragp
->fr_offset
)
13543 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13544 exp
.X_add_number
= 0;
13547 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13548 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13549 fixp
->fx_file
= fragp
->fr_file
;
13550 fixp
->fx_line
= fragp
->fr_line
;
13552 md_number_to_chars ((char*)buf
, insn
, 4);
13555 if (mips_opts
.isa
== ISA_MIPS1
)
13558 md_number_to_chars ((char*)buf
, 0, 4);
13562 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13563 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13565 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13566 4, &exp
, 0, BFD_RELOC_LO16
);
13567 fixp
->fx_file
= fragp
->fr_file
;
13568 fixp
->fx_line
= fragp
->fr_line
;
13570 md_number_to_chars ((char*)buf
, insn
, 4);
13574 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13579 md_number_to_chars ((char*)buf
, insn
, 4);
13584 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13585 + fragp
->fr_fix
+ fragp
->fr_var
);
13587 fragp
->fr_fix
+= fragp
->fr_var
;
13592 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13595 register const struct mips16_immed_operand
*op
;
13596 bfd_boolean small
, ext
;
13599 unsigned long insn
;
13600 bfd_boolean use_extend
;
13601 unsigned short extend
;
13603 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13604 op
= mips16_immed_operands
;
13605 while (op
->type
!= type
)
13608 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13619 resolve_symbol_value (fragp
->fr_symbol
);
13620 val
= S_GET_VALUE (fragp
->fr_symbol
);
13625 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13627 /* The rules for the base address of a PC relative reloc are
13628 complicated; see mips16_extended_frag. */
13629 if (type
== 'p' || type
== 'q')
13634 /* Ignore the low bit in the target, since it will be
13635 set for a text label. */
13636 if ((val
& 1) != 0)
13639 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13641 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13644 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13647 /* Make sure the section winds up with the alignment we have
13650 record_alignment (asec
, op
->shift
);
13654 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13655 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13656 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13657 _("extended instruction in delay slot"));
13659 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13661 if (target_big_endian
)
13662 insn
= bfd_getb16 (buf
);
13664 insn
= bfd_getl16 (buf
);
13666 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13667 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13668 small
, ext
, &insn
, &use_extend
, &extend
);
13672 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13673 fragp
->fr_fix
+= 2;
13677 md_number_to_chars ((char *) buf
, insn
, 2);
13678 fragp
->fr_fix
+= 2;
13683 if (fragp
->fr_opcode
== NULL
)
13686 old
= RELAX_OLD (fragp
->fr_subtype
);
13687 new = RELAX_NEW (fragp
->fr_subtype
);
13688 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13691 memcpy (fixptr
- old
, fixptr
, new);
13693 fragp
->fr_fix
+= new - old
;
13699 /* This function is called after the relocs have been generated.
13700 We've been storing mips16 text labels as odd. Here we convert them
13701 back to even for the convenience of the debugger. */
13704 mips_frob_file_after_relocs ()
13707 unsigned int count
, i
;
13709 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13712 syms
= bfd_get_outsymbols (stdoutput
);
13713 count
= bfd_get_symcount (stdoutput
);
13714 for (i
= 0; i
< count
; i
++, syms
++)
13716 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13717 && ((*syms
)->value
& 1) != 0)
13719 (*syms
)->value
&= ~1;
13720 /* If the symbol has an odd size, it was probably computed
13721 incorrectly, so adjust that as well. */
13722 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13723 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13730 /* This function is called whenever a label is defined. It is used
13731 when handling branch delays; if a branch has a label, we assume we
13732 can not move it. */
13735 mips_define_label (sym
)
13738 struct insn_label_list
*l
;
13740 if (free_insn_labels
== NULL
)
13741 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13744 l
= free_insn_labels
;
13745 free_insn_labels
= l
->next
;
13749 l
->next
= insn_labels
;
13753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13755 /* Some special processing for a MIPS ELF file. */
13758 mips_elf_final_processing ()
13760 /* Write out the register information. */
13761 if (mips_abi
!= N64_ABI
)
13765 s
.ri_gprmask
= mips_gprmask
;
13766 s
.ri_cprmask
[0] = mips_cprmask
[0];
13767 s
.ri_cprmask
[1] = mips_cprmask
[1];
13768 s
.ri_cprmask
[2] = mips_cprmask
[2];
13769 s
.ri_cprmask
[3] = mips_cprmask
[3];
13770 /* The gp_value field is set by the MIPS ELF backend. */
13772 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13773 ((Elf32_External_RegInfo
*)
13774 mips_regmask_frag
));
13778 Elf64_Internal_RegInfo s
;
13780 s
.ri_gprmask
= mips_gprmask
;
13782 s
.ri_cprmask
[0] = mips_cprmask
[0];
13783 s
.ri_cprmask
[1] = mips_cprmask
[1];
13784 s
.ri_cprmask
[2] = mips_cprmask
[2];
13785 s
.ri_cprmask
[3] = mips_cprmask
[3];
13786 /* The gp_value field is set by the MIPS ELF backend. */
13788 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13789 ((Elf64_External_RegInfo
*)
13790 mips_regmask_frag
));
13793 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13794 sort of BFD interface for this. */
13795 if (mips_any_noreorder
)
13796 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13797 if (mips_pic
!= NO_PIC
)
13798 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13800 /* Set MIPS ELF flags for ASEs. */
13801 if (file_ase_mips16
)
13802 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13803 #if 0 /* XXX FIXME */
13804 if (file_ase_mips3d
)
13805 elf_elfheader (stdoutput
)->e_flags
|= ???;
13808 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13810 /* Set the MIPS ELF ABI flags. */
13811 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13812 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13813 else if (mips_abi
== O64_ABI
)
13814 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13815 else if (mips_abi
== EABI_ABI
)
13817 if (!file_mips_gp32
)
13818 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13820 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13822 else if (mips_abi
== N32_ABI
)
13823 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13825 /* Nothing to do for N64_ABI. */
13827 if (mips_32bitmode
)
13828 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13831 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13833 typedef struct proc
{
13835 unsigned long reg_mask
;
13836 unsigned long reg_offset
;
13837 unsigned long fpreg_mask
;
13838 unsigned long fpreg_offset
;
13839 unsigned long frame_offset
;
13840 unsigned long frame_reg
;
13841 unsigned long pc_reg
;
13844 static procS cur_proc
;
13845 static procS
*cur_proc_ptr
;
13846 static int numprocs
;
13848 /* Fill in an rs_align_code fragment. */
13851 mips_handle_align (fragp
)
13854 if (fragp
->fr_type
!= rs_align_code
)
13857 if (mips_opts
.mips16
)
13859 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13860 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13865 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13866 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13874 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13878 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13889 /* check for premature end, nesting errors, etc */
13891 as_warn (_("missing .end at end of assembly"));
13900 if (*input_line_pointer
== '-')
13902 ++input_line_pointer
;
13905 if (!ISDIGIT (*input_line_pointer
))
13906 as_bad (_("expected simple number"));
13907 if (input_line_pointer
[0] == '0')
13909 if (input_line_pointer
[1] == 'x')
13911 input_line_pointer
+= 2;
13912 while (ISXDIGIT (*input_line_pointer
))
13915 val
|= hex_value (*input_line_pointer
++);
13917 return negative
? -val
: val
;
13921 ++input_line_pointer
;
13922 while (ISDIGIT (*input_line_pointer
))
13925 val
|= *input_line_pointer
++ - '0';
13927 return negative
? -val
: val
;
13930 if (!ISDIGIT (*input_line_pointer
))
13932 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13933 *input_line_pointer
, *input_line_pointer
);
13934 as_warn (_("invalid number"));
13937 while (ISDIGIT (*input_line_pointer
))
13940 val
+= *input_line_pointer
++ - '0';
13942 return negative
? -val
: val
;
13945 /* The .file directive; just like the usual .file directive, but there
13946 is an initial number which is the ECOFF file index. In the non-ECOFF
13947 case .file implies DWARF-2. */
13951 int x ATTRIBUTE_UNUSED
;
13953 static int first_file_directive
= 0;
13955 if (ECOFF_DEBUGGING
)
13964 filename
= dwarf2_directive_file (0);
13966 /* Versions of GCC up to 3.1 start files with a ".file"
13967 directive even for stabs output. Make sure that this
13968 ".file" is handled. Note that you need a version of GCC
13969 after 3.1 in order to support DWARF-2 on MIPS. */
13970 if (filename
!= NULL
&& ! first_file_directive
)
13972 (void) new_logical_line (filename
, -1);
13973 s_app_file_string (filename
);
13975 first_file_directive
= 1;
13979 /* The .loc directive, implying DWARF-2. */
13983 int x ATTRIBUTE_UNUSED
;
13985 if (!ECOFF_DEBUGGING
)
13986 dwarf2_directive_loc (0);
13989 /* The .end directive. */
13993 int x ATTRIBUTE_UNUSED
;
13998 /* Following functions need their own .frame and .cprestore directives. */
13999 mips_frame_reg_valid
= 0;
14000 mips_cprestore_valid
= 0;
14002 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14005 demand_empty_rest_of_line ();
14010 #ifdef BFD_ASSEMBLER
14011 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14016 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14023 as_warn (_(".end not in text section"));
14027 as_warn (_(".end directive without a preceding .ent directive."));
14028 demand_empty_rest_of_line ();
14034 assert (S_GET_NAME (p
));
14035 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14036 as_warn (_(".end symbol does not match .ent symbol."));
14038 if (debug_type
== DEBUG_STABS
)
14039 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14043 as_warn (_(".end directive missing or unknown symbol"));
14046 /* Generate a .pdr section. */
14047 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14049 segT saved_seg
= now_seg
;
14050 subsegT saved_subseg
= now_subseg
;
14055 dot
= frag_now_fix ();
14057 #ifdef md_flush_pending_output
14058 md_flush_pending_output ();
14062 subseg_set (pdr_seg
, 0);
14064 /* Write the symbol. */
14065 exp
.X_op
= O_symbol
;
14066 exp
.X_add_symbol
= p
;
14067 exp
.X_add_number
= 0;
14068 emit_expr (&exp
, 4);
14070 fragp
= frag_more (7 * 4);
14072 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14073 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14074 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14075 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14076 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14077 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14078 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14080 subseg_set (saved_seg
, saved_subseg
);
14082 #endif /* OBJ_ELF */
14084 cur_proc_ptr
= NULL
;
14087 /* The .aent and .ent directives. */
14096 symbolP
= get_symbol ();
14097 if (*input_line_pointer
== ',')
14098 ++input_line_pointer
;
14099 SKIP_WHITESPACE ();
14100 if (ISDIGIT (*input_line_pointer
)
14101 || *input_line_pointer
== '-')
14104 #ifdef BFD_ASSEMBLER
14105 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14110 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14117 as_warn (_(".ent or .aent not in text section."));
14119 if (!aent
&& cur_proc_ptr
)
14120 as_warn (_("missing .end"));
14124 /* This function needs its own .frame and .cprestore directives. */
14125 mips_frame_reg_valid
= 0;
14126 mips_cprestore_valid
= 0;
14128 cur_proc_ptr
= &cur_proc
;
14129 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14131 cur_proc_ptr
->isym
= symbolP
;
14133 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14137 if (debug_type
== DEBUG_STABS
)
14138 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14139 S_GET_NAME (symbolP
));
14142 demand_empty_rest_of_line ();
14145 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14146 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14147 s_mips_frame is used so that we can set the PDR information correctly.
14148 We can't use the ecoff routines because they make reference to the ecoff
14149 symbol table (in the mdebug section). */
14152 s_mips_frame (ignore
)
14153 int ignore ATTRIBUTE_UNUSED
;
14156 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14160 if (cur_proc_ptr
== (procS
*) NULL
)
14162 as_warn (_(".frame outside of .ent"));
14163 demand_empty_rest_of_line ();
14167 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14169 SKIP_WHITESPACE ();
14170 if (*input_line_pointer
++ != ','
14171 || get_absolute_expression_and_terminator (&val
) != ',')
14173 as_warn (_("Bad .frame directive"));
14174 --input_line_pointer
;
14175 demand_empty_rest_of_line ();
14179 cur_proc_ptr
->frame_offset
= val
;
14180 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14182 demand_empty_rest_of_line ();
14185 #endif /* OBJ_ELF */
14189 /* The .fmask and .mask directives. If the mdebug section is present
14190 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14191 embedded targets, s_mips_mask is used so that we can set the PDR
14192 information correctly. We can't use the ecoff routines because they
14193 make reference to the ecoff symbol table (in the mdebug section). */
14196 s_mips_mask (reg_type
)
14200 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14204 if (cur_proc_ptr
== (procS
*) NULL
)
14206 as_warn (_(".mask/.fmask outside of .ent"));
14207 demand_empty_rest_of_line ();
14211 if (get_absolute_expression_and_terminator (&mask
) != ',')
14213 as_warn (_("Bad .mask/.fmask directive"));
14214 --input_line_pointer
;
14215 demand_empty_rest_of_line ();
14219 off
= get_absolute_expression ();
14221 if (reg_type
== 'F')
14223 cur_proc_ptr
->fpreg_mask
= mask
;
14224 cur_proc_ptr
->fpreg_offset
= off
;
14228 cur_proc_ptr
->reg_mask
= mask
;
14229 cur_proc_ptr
->reg_offset
= off
;
14232 demand_empty_rest_of_line ();
14235 #endif /* OBJ_ELF */
14236 s_ignore (reg_type
);
14239 /* The .loc directive. */
14250 assert (now_seg
== text_section
);
14252 lineno
= get_number ();
14253 addroff
= frag_now_fix ();
14255 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14256 S_SET_TYPE (symbolP
, N_SLINE
);
14257 S_SET_OTHER (symbolP
, 0);
14258 S_SET_DESC (symbolP
, lineno
);
14259 symbolP
->sy_segment
= now_seg
;
14263 /* A table describing all the processors gas knows about. Names are
14264 matched in the order listed.
14266 To ease comparison, please keep this table in the same order as
14267 gcc's mips_cpu_info_table[]. */
14268 static const struct mips_cpu_info mips_cpu_info_table
[] =
14270 /* Entries for generic ISAs */
14271 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14272 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14273 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14274 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14275 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14276 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14277 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14278 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14281 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14282 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14283 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14286 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14289 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14290 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14291 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14292 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14293 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14294 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14295 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14296 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14297 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14298 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14299 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14300 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14303 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14304 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14305 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14306 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14307 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14308 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14309 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14310 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14311 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14312 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14313 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14314 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14317 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14318 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14319 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14322 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14323 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14325 /* Broadcom SB-1 CPU core */
14326 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14333 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14334 with a final "000" replaced by "k". Ignore case.
14336 Note: this function is shared between GCC and GAS. */
14339 mips_strict_matching_cpu_name_p (canonical
, given
)
14340 const char *canonical
, *given
;
14342 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14343 given
++, canonical
++;
14345 return ((*given
== 0 && *canonical
== 0)
14346 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14350 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14351 CPU name. We've traditionally allowed a lot of variation here.
14353 Note: this function is shared between GCC and GAS. */
14356 mips_matching_cpu_name_p (canonical
, given
)
14357 const char *canonical
, *given
;
14359 /* First see if the name matches exactly, or with a final "000"
14360 turned into "k". */
14361 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14364 /* If not, try comparing based on numerical designation alone.
14365 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14366 if (TOLOWER (*given
) == 'r')
14368 if (!ISDIGIT (*given
))
14371 /* Skip over some well-known prefixes in the canonical name,
14372 hoping to find a number there too. */
14373 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14375 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14377 else if (TOLOWER (canonical
[0]) == 'r')
14380 return mips_strict_matching_cpu_name_p (canonical
, given
);
14384 /* Parse an option that takes the name of a processor as its argument.
14385 OPTION is the name of the option and CPU_STRING is the argument.
14386 Return the corresponding processor enumeration if the CPU_STRING is
14387 recognized, otherwise report an error and return null.
14389 A similar function exists in GCC. */
14391 static const struct mips_cpu_info
*
14392 mips_parse_cpu (option
, cpu_string
)
14393 const char *option
, *cpu_string
;
14395 const struct mips_cpu_info
*p
;
14397 /* 'from-abi' selects the most compatible architecture for the given
14398 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14399 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14400 version. Look first at the -mgp options, if given, otherwise base
14401 the choice on MIPS_DEFAULT_64BIT.
14403 Treat NO_ABI like the EABIs. One reason to do this is that the
14404 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14405 architecture. This code picks MIPS I for 'mips' and MIPS III for
14406 'mips64', just as we did in the days before 'from-abi'. */
14407 if (strcasecmp (cpu_string
, "from-abi") == 0)
14409 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14410 return mips_cpu_info_from_isa (ISA_MIPS1
);
14412 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14413 return mips_cpu_info_from_isa (ISA_MIPS3
);
14415 if (file_mips_gp32
>= 0)
14416 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14418 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14423 /* 'default' has traditionally been a no-op. Probably not very useful. */
14424 if (strcasecmp (cpu_string
, "default") == 0)
14427 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14428 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14431 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14435 /* Return the canonical processor information for ISA (a member of the
14436 ISA_MIPS* enumeration). */
14438 static const struct mips_cpu_info
*
14439 mips_cpu_info_from_isa (isa
)
14444 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14445 if (mips_cpu_info_table
[i
].is_isa
14446 && isa
== mips_cpu_info_table
[i
].isa
)
14447 return (&mips_cpu_info_table
[i
]);
14453 show (stream
, string
, col_p
, first_p
)
14455 const char *string
;
14461 fprintf (stream
, "%24s", "");
14466 fprintf (stream
, ", ");
14470 if (*col_p
+ strlen (string
) > 72)
14472 fprintf (stream
, "\n%24s", "");
14476 fprintf (stream
, "%s", string
);
14477 *col_p
+= strlen (string
);
14483 md_show_usage (stream
)
14489 fprintf (stream
, _("\
14491 -membedded-pic generate embedded position independent code\n\
14492 -EB generate big endian output\n\
14493 -EL generate little endian output\n\
14494 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14495 -G NUM allow referencing objects up to NUM bytes\n\
14496 implicitly with the gp register [default 8]\n"));
14497 fprintf (stream
, _("\
14498 -mips1 generate MIPS ISA I instructions\n\
14499 -mips2 generate MIPS ISA II instructions\n\
14500 -mips3 generate MIPS ISA III instructions\n\
14501 -mips4 generate MIPS ISA IV instructions\n\
14502 -mips5 generate MIPS ISA V instructions\n\
14503 -mips32 generate MIPS32 ISA instructions\n\
14504 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14505 -mips64 generate MIPS64 ISA instructions\n\
14506 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14510 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14511 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14512 show (stream
, "from-abi", &column
, &first
);
14513 fputc ('\n', stream
);
14515 fprintf (stream
, _("\
14516 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14517 -no-mCPU don't generate code specific to CPU.\n\
14518 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14522 show (stream
, "3900", &column
, &first
);
14523 show (stream
, "4010", &column
, &first
);
14524 show (stream
, "4100", &column
, &first
);
14525 show (stream
, "4650", &column
, &first
);
14526 fputc ('\n', stream
);
14528 fprintf (stream
, _("\
14529 -mips16 generate mips16 instructions\n\
14530 -no-mips16 do not generate mips16 instructions\n"));
14531 fprintf (stream
, _("\
14532 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14533 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14534 -O0 remove unneeded NOPs, do not swap branches\n\
14535 -O remove unneeded NOPs and swap branches\n\
14536 -n warn about NOPs generated from macros\n\
14537 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14538 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14539 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14541 fprintf (stream
, _("\
14542 -KPIC, -call_shared generate SVR4 position independent code\n\
14543 -non_shared do not generate position independent code\n\
14544 -xgot assume a 32 bit GOT\n\
14545 -mabi=ABI create ABI conformant object file for:\n"));
14549 show (stream
, "32", &column
, &first
);
14550 show (stream
, "o64", &column
, &first
);
14551 show (stream
, "n32", &column
, &first
);
14552 show (stream
, "64", &column
, &first
);
14553 show (stream
, "eabi", &column
, &first
);
14555 fputc ('\n', stream
);
14557 fprintf (stream
, _("\
14558 -32 create o32 ABI object file (default)\n\
14559 -n32 create n32 ABI object file\n\
14560 -64 create 64 ABI object file\n"));
14565 mips_dwarf2_format ()
14567 if (mips_abi
== N64_ABI
)
14570 return dwarf2_format_64bit_irix
;
14572 return dwarf2_format_64bit
;
14576 return dwarf2_format_32bit
;